1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 // If the input is a buildvector just emit a smaller one.
89 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
90 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
91 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
93 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
100 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
101 /// sets things up to match to an AVX VINSERTF128 instruction or a
102 /// simple superregister reference. Idx is an index in the 128 bits
103 /// we want. It need not be aligned to a 128-bit bounday. That makes
104 /// lowering INSERT_VECTOR_ELT operations easier.
105 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
106 unsigned IdxVal, SelectionDAG &DAG,
108 // Inserting UNDEF is Result
109 if (Vec.getOpcode() == ISD::UNDEF)
112 EVT VT = Vec.getValueType();
113 assert(VT.is128BitVector() && "Unexpected vector size!");
115 EVT ElVT = VT.getVectorElementType();
116 EVT ResultVT = Result.getValueType();
118 // Insert the relevant 128 bits.
119 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
121 // This is the index of the first element of the 128-bit chunk
123 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
126 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
127 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
131 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
132 /// instructions. This is used because creating CONCAT_VECTOR nodes of
133 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
134 /// large BUILD_VECTORS.
135 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
136 unsigned NumElems, SelectionDAG &DAG,
138 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
139 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
142 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
143 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
144 bool is64Bit = Subtarget->is64Bit();
146 if (Subtarget->isTargetEnvMacho()) {
148 return new X86_64MachoTargetObjectFile();
149 return new TargetLoweringObjectFileMachO();
152 if (Subtarget->isTargetLinux())
153 return new X86LinuxTargetObjectFile();
154 if (Subtarget->isTargetELF())
155 return new TargetLoweringObjectFileELF();
156 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
157 return new TargetLoweringObjectFileCOFF();
158 llvm_unreachable("unknown subtarget type");
161 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
162 : TargetLowering(TM, createTLOF(TM)) {
163 Subtarget = &TM.getSubtarget<X86Subtarget>();
164 X86ScalarSSEf64 = Subtarget->hasSSE2();
165 X86ScalarSSEf32 = Subtarget->hasSSE1();
166 RegInfo = TM.getRegisterInfo();
167 TD = getDataLayout();
169 resetOperationActions();
172 void X86TargetLowering::resetOperationActions() {
173 const TargetMachine &TM = getTargetMachine();
174 static bool FirstTimeThrough = true;
176 // If none of the target options have changed, then we don't need to reset the
177 // operation actions.
178 if (!FirstTimeThrough && TO == TM.Options) return;
180 if (!FirstTimeThrough) {
181 // Reinitialize the actions.
183 FirstTimeThrough = false;
188 // Set up the TargetLowering object.
189 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
191 // X86 is weird, it always uses i8 for shift amounts and setcc results.
192 setBooleanContents(ZeroOrOneBooleanContent);
193 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
194 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
196 // For 64-bit since we have so many registers use the ILP scheduler, for
197 // 32-bit code use the register pressure specific scheduling.
198 // For Atom, always use ILP scheduling.
199 if (Subtarget->isAtom())
200 setSchedulingPreference(Sched::ILP);
201 else if (Subtarget->is64Bit())
202 setSchedulingPreference(Sched::ILP);
204 setSchedulingPreference(Sched::RegPressure);
205 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
207 // Bypass expensive divides on Atom when compiling with O2
208 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
209 addBypassSlowDiv(32, 8);
210 if (Subtarget->is64Bit())
211 addBypassSlowDiv(64, 16);
214 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
215 // Setup Windows compiler runtime calls.
216 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
217 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
218 setLibcallName(RTLIB::SREM_I64, "_allrem");
219 setLibcallName(RTLIB::UREM_I64, "_aullrem");
220 setLibcallName(RTLIB::MUL_I64, "_allmul");
221 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
222 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
223 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
224 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
225 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
227 // The _ftol2 runtime function has an unusual calling conv, which
228 // is modeled by a special pseudo-instruction.
229 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
230 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
231 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
232 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
235 if (Subtarget->isTargetDarwin()) {
236 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
237 setUseUnderscoreSetJmp(false);
238 setUseUnderscoreLongJmp(false);
239 } else if (Subtarget->isTargetMingw()) {
240 // MS runtime is weird: it exports _setjmp, but longjmp!
241 setUseUnderscoreSetJmp(true);
242 setUseUnderscoreLongJmp(false);
244 setUseUnderscoreSetJmp(true);
245 setUseUnderscoreLongJmp(true);
248 // Set up the register classes.
249 addRegisterClass(MVT::i8, &X86::GR8RegClass);
250 addRegisterClass(MVT::i16, &X86::GR16RegClass);
251 addRegisterClass(MVT::i32, &X86::GR32RegClass);
252 if (Subtarget->is64Bit())
253 addRegisterClass(MVT::i64, &X86::GR64RegClass);
255 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
257 // We don't accept any truncstore of integer registers.
258 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
259 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
260 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
261 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
262 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
263 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
265 // SETOEQ and SETUNE require checking two conditions.
266 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
267 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
268 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
269 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
270 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
271 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
273 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
275 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
276 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
277 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
279 if (Subtarget->is64Bit()) {
280 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
281 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
282 } else if (!TM.Options.UseSoftFloat) {
283 // We have an algorithm for SSE2->double, and we turn this into a
284 // 64-bit FILD followed by conditional FADD for other targets.
285 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
286 // We have an algorithm for SSE2, and we turn this into a 64-bit
287 // FILD for other targets.
288 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
291 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
293 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
294 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
296 if (!TM.Options.UseSoftFloat) {
297 // SSE has no i16 to fp conversion, only i32
298 if (X86ScalarSSEf32) {
299 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
300 // f32 and f64 cases are Legal, f80 case is not
301 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
303 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
304 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
307 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
308 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
311 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
312 // are Legal, f80 is custom lowered.
313 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
314 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
316 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
318 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
319 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
321 if (X86ScalarSSEf32) {
322 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
323 // f32 and f64 cases are Legal, f80 case is not
324 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
326 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
327 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
330 // Handle FP_TO_UINT by promoting the destination to a larger signed
332 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
333 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
334 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
338 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
339 } else if (!TM.Options.UseSoftFloat) {
340 // Since AVX is a superset of SSE3, only check for SSE here.
341 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
342 // Expand FP_TO_UINT into a select.
343 // FIXME: We would like to use a Custom expander here eventually to do
344 // the optimal thing for SSE vs. the default expansion in the legalizer.
345 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
347 // With SSE3 we can use fisttpll to convert to a signed i64; without
348 // SSE, we're stuck with a fistpll.
349 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
352 if (isTargetFTOL()) {
353 // Use the _ftol2 runtime function, which has a pseudo-instruction
354 // to handle its weird calling convention.
355 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
358 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
359 if (!X86ScalarSSEf64) {
360 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
361 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
364 // Without SSE, i64->f64 goes through memory.
365 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
369 // Scalar integer divide and remainder are lowered to use operations that
370 // produce two results, to match the available instructions. This exposes
371 // the two-result form to trivial CSE, which is able to combine x/y and x%y
372 // into a single instruction.
374 // Scalar integer multiply-high is also lowered to use two-result
375 // operations, to match the available instructions. However, plain multiply
376 // (low) operations are left as Legal, as there are single-result
377 // instructions for this in x86. Using the two-result multiply instructions
378 // when both high and low results are needed must be arranged by dagcombine.
379 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
381 setOperationAction(ISD::MULHS, VT, Expand);
382 setOperationAction(ISD::MULHU, VT, Expand);
383 setOperationAction(ISD::SDIV, VT, Expand);
384 setOperationAction(ISD::UDIV, VT, Expand);
385 setOperationAction(ISD::SREM, VT, Expand);
386 setOperationAction(ISD::UREM, VT, Expand);
388 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
389 setOperationAction(ISD::ADDC, VT, Custom);
390 setOperationAction(ISD::ADDE, VT, Custom);
391 setOperationAction(ISD::SUBC, VT, Custom);
392 setOperationAction(ISD::SUBE, VT, Custom);
395 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
396 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
397 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
398 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
399 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
400 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
401 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
402 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
403 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
404 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
405 if (Subtarget->is64Bit())
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
410 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
411 setOperationAction(ISD::FREM , MVT::f32 , Expand);
412 setOperationAction(ISD::FREM , MVT::f64 , Expand);
413 setOperationAction(ISD::FREM , MVT::f80 , Expand);
414 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
416 // Promote the i8 variants and force them on up to i32 which has a shorter
418 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
419 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
420 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
421 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
422 if (Subtarget->hasBMI()) {
423 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
424 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
425 if (Subtarget->is64Bit())
426 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
428 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
429 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
430 if (Subtarget->is64Bit())
431 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
434 if (Subtarget->hasLZCNT()) {
435 // When promoting the i8 variants, force them to i32 for a shorter
437 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
438 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
439 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
440 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
441 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
442 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
446 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
447 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
448 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
449 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
450 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
451 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
452 if (Subtarget->is64Bit()) {
453 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
454 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
458 if (Subtarget->hasPOPCNT()) {
459 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
461 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
462 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
463 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
468 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
469 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
471 // These should be promoted to a larger select which is supported.
472 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
473 // X86 wants to expand cmov itself.
474 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
475 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
476 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
477 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
478 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
479 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
480 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
481 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
482 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
483 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
484 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
485 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
486 if (Subtarget->is64Bit()) {
487 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
488 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
490 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
491 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
492 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
493 // support continuation, user-level threading, and etc.. As a result, no
494 // other SjLj exception interfaces are implemented and please don't build
495 // your own exception handling based on them.
496 // LLVM/Clang supports zero-cost DWARF exception handling.
497 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
498 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
501 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
502 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
503 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
504 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
505 if (Subtarget->is64Bit())
506 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
507 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
508 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
509 if (Subtarget->is64Bit()) {
510 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
511 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
512 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
513 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
514 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
516 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
517 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
518 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
519 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
520 if (Subtarget->is64Bit()) {
521 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
522 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
523 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
526 if (Subtarget->hasSSE1())
527 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
529 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
531 // Expand certain atomics
532 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
534 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
535 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
536 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
539 if (!Subtarget->is64Bit()) {
540 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
541 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
542 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
543 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
544 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
545 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
546 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
547 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
548 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
549 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
550 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
551 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
554 if (Subtarget->hasCmpxchg16b()) {
555 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
558 // FIXME - use subtarget debug flags
559 if (!Subtarget->isTargetDarwin() &&
560 !Subtarget->isTargetELF() &&
561 !Subtarget->isTargetCygMing()) {
562 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
565 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
566 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
567 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
568 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
569 if (Subtarget->is64Bit()) {
570 setExceptionPointerRegister(X86::RAX);
571 setExceptionSelectorRegister(X86::RDX);
573 setExceptionPointerRegister(X86::EAX);
574 setExceptionSelectorRegister(X86::EDX);
576 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
577 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
579 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
580 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
582 setOperationAction(ISD::TRAP, MVT::Other, Legal);
583 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
585 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
586 setOperationAction(ISD::VASTART , MVT::Other, Custom);
587 setOperationAction(ISD::VAEND , MVT::Other, Expand);
588 if (Subtarget->is64Bit()) {
589 setOperationAction(ISD::VAARG , MVT::Other, Custom);
590 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
592 setOperationAction(ISD::VAARG , MVT::Other, Expand);
593 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
596 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
597 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
599 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
600 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
601 MVT::i64 : MVT::i32, Custom);
602 else if (TM.Options.EnableSegmentedStacks)
603 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
604 MVT::i64 : MVT::i32, Custom);
606 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
607 MVT::i64 : MVT::i32, Expand);
609 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
610 // f32 and f64 use SSE.
611 // Set up the FP register classes.
612 addRegisterClass(MVT::f32, &X86::FR32RegClass);
613 addRegisterClass(MVT::f64, &X86::FR64RegClass);
615 // Use ANDPD to simulate FABS.
616 setOperationAction(ISD::FABS , MVT::f64, Custom);
617 setOperationAction(ISD::FABS , MVT::f32, Custom);
619 // Use XORP to simulate FNEG.
620 setOperationAction(ISD::FNEG , MVT::f64, Custom);
621 setOperationAction(ISD::FNEG , MVT::f32, Custom);
623 // Use ANDPD and ORPD to simulate FCOPYSIGN.
624 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
627 // Lower this to FGETSIGNx86 plus an AND.
628 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
629 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
631 // We don't support sin/cos/fmod
632 setOperationAction(ISD::FSIN , MVT::f64, Expand);
633 setOperationAction(ISD::FCOS , MVT::f64, Expand);
634 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
635 setOperationAction(ISD::FSIN , MVT::f32, Expand);
636 setOperationAction(ISD::FCOS , MVT::f32, Expand);
637 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
639 // Expand FP immediates into loads from the stack, except for the special
641 addLegalFPImmediate(APFloat(+0.0)); // xorpd
642 addLegalFPImmediate(APFloat(+0.0f)); // xorps
643 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
644 // Use SSE for f32, x87 for f64.
645 // Set up the FP register classes.
646 addRegisterClass(MVT::f32, &X86::FR32RegClass);
647 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
649 // Use ANDPS to simulate FABS.
650 setOperationAction(ISD::FABS , MVT::f32, Custom);
652 // Use XORP to simulate FNEG.
653 setOperationAction(ISD::FNEG , MVT::f32, Custom);
655 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
657 // Use ANDPS and ORPS to simulate FCOPYSIGN.
658 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
659 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
661 // We don't support sin/cos/fmod
662 setOperationAction(ISD::FSIN , MVT::f32, Expand);
663 setOperationAction(ISD::FCOS , MVT::f32, Expand);
664 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
666 // Special cases we handle for FP constants.
667 addLegalFPImmediate(APFloat(+0.0f)); // xorps
668 addLegalFPImmediate(APFloat(+0.0)); // FLD0
669 addLegalFPImmediate(APFloat(+1.0)); // FLD1
670 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
671 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
673 if (!TM.Options.UnsafeFPMath) {
674 setOperationAction(ISD::FSIN , MVT::f64, Expand);
675 setOperationAction(ISD::FCOS , MVT::f64, Expand);
676 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 } else if (!TM.Options.UseSoftFloat) {
679 // f32 and f64 in x87.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
682 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
684 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
685 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
686 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
687 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
689 if (!TM.Options.UnsafeFPMath) {
690 setOperationAction(ISD::FSIN , MVT::f64, Expand);
691 setOperationAction(ISD::FSIN , MVT::f32, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FCOS , MVT::f32, Expand);
694 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
695 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
697 addLegalFPImmediate(APFloat(+0.0)); // FLD0
698 addLegalFPImmediate(APFloat(+1.0)); // FLD1
699 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
700 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
701 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
702 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
703 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
704 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
707 // We don't support FMA.
708 setOperationAction(ISD::FMA, MVT::f64, Expand);
709 setOperationAction(ISD::FMA, MVT::f32, Expand);
711 // Long double always uses X87.
712 if (!TM.Options.UseSoftFloat) {
713 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
714 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
715 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
717 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
718 addLegalFPImmediate(TmpFlt); // FLD0
720 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
723 APFloat TmpFlt2(+1.0);
724 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
726 addLegalFPImmediate(TmpFlt2); // FLD1
727 TmpFlt2.changeSign();
728 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
731 if (!TM.Options.UnsafeFPMath) {
732 setOperationAction(ISD::FSIN , MVT::f80, Expand);
733 setOperationAction(ISD::FCOS , MVT::f80, Expand);
734 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
737 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
738 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
739 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
740 setOperationAction(ISD::FRINT, MVT::f80, Expand);
741 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
742 setOperationAction(ISD::FMA, MVT::f80, Expand);
745 // Always use a library call for pow.
746 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
747 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
748 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
750 setOperationAction(ISD::FLOG, MVT::f80, Expand);
751 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
752 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
753 setOperationAction(ISD::FEXP, MVT::f80, Expand);
754 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
756 // First set operation action for all vector types to either promote
757 // (for widening) or expand (for scalarization). Then we will selectively
758 // turn on ones that can be effectively codegen'd.
759 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
760 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
761 MVT VT = (MVT::SimpleValueType)i;
762 setOperationAction(ISD::ADD , VT, Expand);
763 setOperationAction(ISD::SUB , VT, Expand);
764 setOperationAction(ISD::FADD, VT, Expand);
765 setOperationAction(ISD::FNEG, VT, Expand);
766 setOperationAction(ISD::FSUB, VT, Expand);
767 setOperationAction(ISD::MUL , VT, Expand);
768 setOperationAction(ISD::FMUL, VT, Expand);
769 setOperationAction(ISD::SDIV, VT, Expand);
770 setOperationAction(ISD::UDIV, VT, Expand);
771 setOperationAction(ISD::FDIV, VT, Expand);
772 setOperationAction(ISD::SREM, VT, Expand);
773 setOperationAction(ISD::UREM, VT, Expand);
774 setOperationAction(ISD::LOAD, VT, Expand);
775 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
777 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
778 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
779 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
780 setOperationAction(ISD::FABS, VT, Expand);
781 setOperationAction(ISD::FSIN, VT, Expand);
782 setOperationAction(ISD::FSINCOS, VT, Expand);
783 setOperationAction(ISD::FCOS, VT, Expand);
784 setOperationAction(ISD::FSINCOS, VT, Expand);
785 setOperationAction(ISD::FREM, VT, Expand);
786 setOperationAction(ISD::FMA, VT, Expand);
787 setOperationAction(ISD::FPOWI, VT, Expand);
788 setOperationAction(ISD::FSQRT, VT, Expand);
789 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
790 setOperationAction(ISD::FFLOOR, VT, Expand);
791 setOperationAction(ISD::FCEIL, VT, Expand);
792 setOperationAction(ISD::FTRUNC, VT, Expand);
793 setOperationAction(ISD::FRINT, VT, Expand);
794 setOperationAction(ISD::FNEARBYINT, VT, Expand);
795 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
796 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
797 setOperationAction(ISD::SDIVREM, VT, Expand);
798 setOperationAction(ISD::UDIVREM, VT, Expand);
799 setOperationAction(ISD::FPOW, VT, Expand);
800 setOperationAction(ISD::CTPOP, VT, Expand);
801 setOperationAction(ISD::CTTZ, VT, Expand);
802 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
803 setOperationAction(ISD::CTLZ, VT, Expand);
804 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
805 setOperationAction(ISD::SHL, VT, Expand);
806 setOperationAction(ISD::SRA, VT, Expand);
807 setOperationAction(ISD::SRL, VT, Expand);
808 setOperationAction(ISD::ROTL, VT, Expand);
809 setOperationAction(ISD::ROTR, VT, Expand);
810 setOperationAction(ISD::BSWAP, VT, Expand);
811 setOperationAction(ISD::SETCC, VT, Expand);
812 setOperationAction(ISD::FLOG, VT, Expand);
813 setOperationAction(ISD::FLOG2, VT, Expand);
814 setOperationAction(ISD::FLOG10, VT, Expand);
815 setOperationAction(ISD::FEXP, VT, Expand);
816 setOperationAction(ISD::FEXP2, VT, Expand);
817 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
818 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
819 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
820 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
821 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
822 setOperationAction(ISD::TRUNCATE, VT, Expand);
823 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
824 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
825 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
826 setOperationAction(ISD::VSELECT, VT, Expand);
827 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
828 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
829 setTruncStoreAction(VT,
830 (MVT::SimpleValueType)InnerVT, Expand);
831 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
832 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
833 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
836 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
837 // with -msoft-float, disable use of MMX as well.
838 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
839 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
840 // No operations on x86mmx supported, everything uses intrinsics.
843 // MMX-sized vectors (other than x86mmx) are expected to be expanded
844 // into smaller operations.
845 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
846 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
847 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
848 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
849 setOperationAction(ISD::AND, MVT::v8i8, Expand);
850 setOperationAction(ISD::AND, MVT::v4i16, Expand);
851 setOperationAction(ISD::AND, MVT::v2i32, Expand);
852 setOperationAction(ISD::AND, MVT::v1i64, Expand);
853 setOperationAction(ISD::OR, MVT::v8i8, Expand);
854 setOperationAction(ISD::OR, MVT::v4i16, Expand);
855 setOperationAction(ISD::OR, MVT::v2i32, Expand);
856 setOperationAction(ISD::OR, MVT::v1i64, Expand);
857 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
858 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
859 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
860 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
862 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
863 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
865 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
866 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
867 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
868 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
869 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
870 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
871 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
872 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
873 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
875 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
876 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
878 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
879 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
880 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
881 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
882 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
883 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
884 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
885 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
888 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
889 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
892 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
893 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
895 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
896 // registers cannot be used even for integer operations.
897 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
898 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
899 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
900 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
902 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
903 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
904 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
905 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
906 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
907 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
908 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
909 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
910 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
911 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
912 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
913 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
914 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
915 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
916 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
918 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
919 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
921 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
922 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
923 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
924 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
928 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
930 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
932 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
933 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
934 MVT VT = (MVT::SimpleValueType)i;
935 // Do not attempt to custom lower non-power-of-2 vectors
936 if (!isPowerOf2_32(VT.getVectorNumElements()))
938 // Do not attempt to custom lower non-128-bit vectors
939 if (!VT.is128BitVector())
941 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
942 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
946 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
947 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
948 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
949 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
950 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
951 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
953 if (Subtarget->is64Bit()) {
954 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
958 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
959 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
960 MVT VT = (MVT::SimpleValueType)i;
962 // Do not attempt to promote non-128-bit vectors
963 if (!VT.is128BitVector())
966 setOperationAction(ISD::AND, VT, Promote);
967 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
968 setOperationAction(ISD::OR, VT, Promote);
969 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
970 setOperationAction(ISD::XOR, VT, Promote);
971 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
972 setOperationAction(ISD::LOAD, VT, Promote);
973 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
974 setOperationAction(ISD::SELECT, VT, Promote);
975 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
978 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
980 // Custom lower v2i64 and v2f64 selects.
981 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
982 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
983 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
984 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
986 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
987 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
989 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
990 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
991 // As there is no 64-bit GPR available, we need build a special custom
992 // sequence to convert from v2i32 to v2f32.
993 if (!Subtarget->is64Bit())
994 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
996 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
997 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
999 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1002 if (Subtarget->hasSSE41()) {
1003 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1004 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1005 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1006 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1007 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1008 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1009 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1010 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1011 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1012 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1014 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1015 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1016 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1017 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1018 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1019 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1020 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1021 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1022 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1023 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1025 // FIXME: Do we need to handle scalar-to-vector here?
1026 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1028 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1029 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1030 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1031 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1032 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1034 // i8 and i16 vectors are custom , because the source register and source
1035 // source memory operand types are not the same width. f32 vectors are
1036 // custom since the immediate controlling the insert encodes additional
1038 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1040 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1043 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1044 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1045 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1046 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1048 // FIXME: these should be Legal but thats only for the case where
1049 // the index is constant. For now custom expand to deal with that.
1050 if (Subtarget->is64Bit()) {
1051 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1052 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1056 if (Subtarget->hasSSE2()) {
1057 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1058 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1060 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1061 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1063 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1064 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1066 // In the customized shift lowering, the legal cases in AVX2 will be
1068 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1069 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1071 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1072 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1074 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1076 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1077 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1080 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1081 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1082 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1083 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1084 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1085 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1086 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1088 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1089 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1090 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1092 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1093 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1094 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1095 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1096 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1100 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1102 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1103 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1105 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1106 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1107 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1108 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1109 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1110 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1111 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1112 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1113 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1114 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1115 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1116 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1118 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1119 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1121 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1123 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1124 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1125 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1126 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1130 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1132 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1134 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1135 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1137 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1138 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1140 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1141 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1143 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1145 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1146 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1147 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1148 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1150 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1151 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1152 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1154 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1155 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1156 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1159 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1160 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1161 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1164 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1166 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1167 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1168 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1169 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1170 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1171 setOperationAction(ISD::FMA, MVT::f32, Legal);
1172 setOperationAction(ISD::FMA, MVT::f64, Legal);
1175 if (Subtarget->hasInt256()) {
1176 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1177 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1178 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1179 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1181 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1182 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1183 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1186 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1187 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1188 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1189 // Don't lower v32i8 because there is no 128-bit byte mul
1191 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1193 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1195 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1196 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1197 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1198 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1200 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1201 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1202 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1203 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1205 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1206 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1207 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1208 // Don't lower v32i8 because there is no 128-bit byte mul
1211 // In the customized shift lowering, the legal cases in AVX2 will be
1213 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1214 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1216 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1217 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1219 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1221 // Custom lower several nodes for 256-bit types.
1222 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1223 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1224 MVT VT = (MVT::SimpleValueType)i;
1226 // Extract subvector is special because the value type
1227 // (result) is 128-bit but the source is 256-bit wide.
1228 if (VT.is128BitVector())
1229 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1231 // Do not attempt to custom lower other non-256-bit vectors
1232 if (!VT.is256BitVector())
1235 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1236 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1237 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1238 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1239 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1240 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1241 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1244 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1245 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1246 MVT VT = (MVT::SimpleValueType)i;
1248 // Do not attempt to promote non-256-bit vectors
1249 if (!VT.is256BitVector())
1252 setOperationAction(ISD::AND, VT, Promote);
1253 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1254 setOperationAction(ISD::OR, VT, Promote);
1255 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1256 setOperationAction(ISD::XOR, VT, Promote);
1257 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1258 setOperationAction(ISD::LOAD, VT, Promote);
1259 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1260 setOperationAction(ISD::SELECT, VT, Promote);
1261 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1265 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1266 // of this type with custom code.
1267 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1268 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1269 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1273 // We want to custom lower some of our intrinsics.
1274 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1275 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1277 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1278 // handle type legalization for these operations here.
1280 // FIXME: We really should do custom legalization for addition and
1281 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1282 // than generic legalization for 64-bit multiplication-with-overflow, though.
1283 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1284 // Add/Sub/Mul with overflow operations are custom lowered.
1286 setOperationAction(ISD::SADDO, VT, Custom);
1287 setOperationAction(ISD::UADDO, VT, Custom);
1288 setOperationAction(ISD::SSUBO, VT, Custom);
1289 setOperationAction(ISD::USUBO, VT, Custom);
1290 setOperationAction(ISD::SMULO, VT, Custom);
1291 setOperationAction(ISD::UMULO, VT, Custom);
1294 // There are no 8-bit 3-address imul/mul instructions
1295 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1296 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1298 if (!Subtarget->is64Bit()) {
1299 // These libcalls are not available in 32-bit.
1300 setLibcallName(RTLIB::SHL_I128, 0);
1301 setLibcallName(RTLIB::SRL_I128, 0);
1302 setLibcallName(RTLIB::SRA_I128, 0);
1305 // Combine sin / cos into one node or libcall if possible.
1306 if (Subtarget->hasSinCos()) {
1307 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1308 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1309 if (Subtarget->isTargetDarwin()) {
1310 // For MacOSX, we don't want to the normal expansion of a libcall to
1311 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1313 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1314 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1318 // We have target-specific dag combine patterns for the following nodes:
1319 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1320 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1321 setTargetDAGCombine(ISD::VSELECT);
1322 setTargetDAGCombine(ISD::SELECT);
1323 setTargetDAGCombine(ISD::SHL);
1324 setTargetDAGCombine(ISD::SRA);
1325 setTargetDAGCombine(ISD::SRL);
1326 setTargetDAGCombine(ISD::OR);
1327 setTargetDAGCombine(ISD::AND);
1328 setTargetDAGCombine(ISD::ADD);
1329 setTargetDAGCombine(ISD::FADD);
1330 setTargetDAGCombine(ISD::FSUB);
1331 setTargetDAGCombine(ISD::FMA);
1332 setTargetDAGCombine(ISD::SUB);
1333 setTargetDAGCombine(ISD::LOAD);
1334 setTargetDAGCombine(ISD::STORE);
1335 setTargetDAGCombine(ISD::ZERO_EXTEND);
1336 setTargetDAGCombine(ISD::ANY_EXTEND);
1337 setTargetDAGCombine(ISD::SIGN_EXTEND);
1338 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1339 setTargetDAGCombine(ISD::TRUNCATE);
1340 setTargetDAGCombine(ISD::SINT_TO_FP);
1341 setTargetDAGCombine(ISD::SETCC);
1342 if (Subtarget->is64Bit())
1343 setTargetDAGCombine(ISD::MUL);
1344 setTargetDAGCombine(ISD::XOR);
1346 computeRegisterProperties();
1348 // On Darwin, -Os means optimize for size without hurting performance,
1349 // do not reduce the limit.
1350 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1351 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1352 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1353 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1354 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1355 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1356 setPrefLoopAlignment(4); // 2^4 bytes.
1358 // Predictable cmov don't hurt on atom because it's in-order.
1359 PredictableSelectIsExpensive = !Subtarget->isAtom();
1361 setPrefFunctionAlignment(4); // 2^4 bytes.
1364 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1365 if (!VT.isVector()) return MVT::i8;
1366 return VT.changeVectorElementTypeToInteger();
1369 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1370 /// the desired ByVal argument alignment.
1371 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1374 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1375 if (VTy->getBitWidth() == 128)
1377 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1378 unsigned EltAlign = 0;
1379 getMaxByValAlign(ATy->getElementType(), EltAlign);
1380 if (EltAlign > MaxAlign)
1381 MaxAlign = EltAlign;
1382 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1383 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1384 unsigned EltAlign = 0;
1385 getMaxByValAlign(STy->getElementType(i), EltAlign);
1386 if (EltAlign > MaxAlign)
1387 MaxAlign = EltAlign;
1394 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1395 /// function arguments in the caller parameter area. For X86, aggregates
1396 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1397 /// are at 4-byte boundaries.
1398 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1399 if (Subtarget->is64Bit()) {
1400 // Max of 8 and alignment of type.
1401 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1408 if (Subtarget->hasSSE1())
1409 getMaxByValAlign(Ty, Align);
1413 /// getOptimalMemOpType - Returns the target specific optimal type for load
1414 /// and store operations as a result of memset, memcpy, and memmove
1415 /// lowering. If DstAlign is zero that means it's safe to destination
1416 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1417 /// means there isn't a need to check it against alignment requirement,
1418 /// probably because the source does not need to be loaded. If 'IsMemset' is
1419 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1420 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1421 /// source is constant so it does not need to be loaded.
1422 /// It returns EVT::Other if the type should be determined using generic
1423 /// target-independent logic.
1425 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1426 unsigned DstAlign, unsigned SrcAlign,
1427 bool IsMemset, bool ZeroMemset,
1429 MachineFunction &MF) const {
1430 const Function *F = MF.getFunction();
1431 if ((!IsMemset || ZeroMemset) &&
1432 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1433 Attribute::NoImplicitFloat)) {
1435 (Subtarget->isUnalignedMemAccessFast() ||
1436 ((DstAlign == 0 || DstAlign >= 16) &&
1437 (SrcAlign == 0 || SrcAlign >= 16)))) {
1439 if (Subtarget->hasInt256())
1441 if (Subtarget->hasFp256())
1444 if (Subtarget->hasSSE2())
1446 if (Subtarget->hasSSE1())
1448 } else if (!MemcpyStrSrc && Size >= 8 &&
1449 !Subtarget->is64Bit() &&
1450 Subtarget->hasSSE2()) {
1451 // Do not use f64 to lower memcpy if source is string constant. It's
1452 // better to use i32 to avoid the loads.
1456 if (Subtarget->is64Bit() && Size >= 8)
1461 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1463 return X86ScalarSSEf32;
1464 else if (VT == MVT::f64)
1465 return X86ScalarSSEf64;
1470 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1472 *Fast = Subtarget->isUnalignedMemAccessFast();
1476 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1477 /// current function. The returned value is a member of the
1478 /// MachineJumpTableInfo::JTEntryKind enum.
1479 unsigned X86TargetLowering::getJumpTableEncoding() const {
1480 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1482 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1483 Subtarget->isPICStyleGOT())
1484 return MachineJumpTableInfo::EK_Custom32;
1486 // Otherwise, use the normal jump table encoding heuristics.
1487 return TargetLowering::getJumpTableEncoding();
1491 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1492 const MachineBasicBlock *MBB,
1493 unsigned uid,MCContext &Ctx) const{
1494 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1495 Subtarget->isPICStyleGOT());
1496 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1498 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1499 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1502 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1504 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1505 SelectionDAG &DAG) const {
1506 if (!Subtarget->is64Bit())
1507 // This doesn't have DebugLoc associated with it, but is not really the
1508 // same as a Register.
1509 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1513 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1514 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1516 const MCExpr *X86TargetLowering::
1517 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1518 MCContext &Ctx) const {
1519 // X86-64 uses RIP relative addressing based on the jump table label.
1520 if (Subtarget->isPICStyleRIPRel())
1521 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1523 // Otherwise, the reference is relative to the PIC base.
1524 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1527 // FIXME: Why this routine is here? Move to RegInfo!
1528 std::pair<const TargetRegisterClass*, uint8_t>
1529 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1530 const TargetRegisterClass *RRC = 0;
1532 switch (VT.SimpleTy) {
1534 return TargetLowering::findRepresentativeClass(VT);
1535 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1536 RRC = Subtarget->is64Bit() ?
1537 (const TargetRegisterClass*)&X86::GR64RegClass :
1538 (const TargetRegisterClass*)&X86::GR32RegClass;
1541 RRC = &X86::VR64RegClass;
1543 case MVT::f32: case MVT::f64:
1544 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1545 case MVT::v4f32: case MVT::v2f64:
1546 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1548 RRC = &X86::VR128RegClass;
1551 return std::make_pair(RRC, Cost);
1554 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1555 unsigned &Offset) const {
1556 if (!Subtarget->isTargetLinux())
1559 if (Subtarget->is64Bit()) {
1560 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1562 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1574 //===----------------------------------------------------------------------===//
1575 // Return Value Calling Convention Implementation
1576 //===----------------------------------------------------------------------===//
1578 #include "X86GenCallingConv.inc"
1581 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1582 MachineFunction &MF, bool isVarArg,
1583 const SmallVectorImpl<ISD::OutputArg> &Outs,
1584 LLVMContext &Context) const {
1585 SmallVector<CCValAssign, 16> RVLocs;
1586 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1588 return CCInfo.CheckReturn(Outs, RetCC_X86);
1592 X86TargetLowering::LowerReturn(SDValue Chain,
1593 CallingConv::ID CallConv, bool isVarArg,
1594 const SmallVectorImpl<ISD::OutputArg> &Outs,
1595 const SmallVectorImpl<SDValue> &OutVals,
1596 DebugLoc dl, SelectionDAG &DAG) const {
1597 MachineFunction &MF = DAG.getMachineFunction();
1598 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1600 SmallVector<CCValAssign, 16> RVLocs;
1601 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1602 RVLocs, *DAG.getContext());
1603 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1606 SmallVector<SDValue, 6> RetOps;
1607 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1608 // Operand #1 = Bytes To Pop
1609 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1612 // Copy the result values into the output registers.
1613 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1614 CCValAssign &VA = RVLocs[i];
1615 assert(VA.isRegLoc() && "Can only return in registers!");
1616 SDValue ValToCopy = OutVals[i];
1617 EVT ValVT = ValToCopy.getValueType();
1619 // Promote values to the appropriate types
1620 if (VA.getLocInfo() == CCValAssign::SExt)
1621 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1622 else if (VA.getLocInfo() == CCValAssign::ZExt)
1623 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1624 else if (VA.getLocInfo() == CCValAssign::AExt)
1625 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1626 else if (VA.getLocInfo() == CCValAssign::BCvt)
1627 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1629 // If this is x86-64, and we disabled SSE, we can't return FP values,
1630 // or SSE or MMX vectors.
1631 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1632 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1633 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1634 report_fatal_error("SSE register return with SSE disabled");
1636 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1637 // llvm-gcc has never done it right and no one has noticed, so this
1638 // should be OK for now.
1639 if (ValVT == MVT::f64 &&
1640 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1641 report_fatal_error("SSE2 register return with SSE2 disabled");
1643 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1644 // the RET instruction and handled by the FP Stackifier.
1645 if (VA.getLocReg() == X86::ST0 ||
1646 VA.getLocReg() == X86::ST1) {
1647 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1648 // change the value to the FP stack register class.
1649 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1650 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1651 RetOps.push_back(ValToCopy);
1652 // Don't emit a copytoreg.
1656 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1657 // which is returned in RAX / RDX.
1658 if (Subtarget->is64Bit()) {
1659 if (ValVT == MVT::x86mmx) {
1660 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1661 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1662 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1664 // If we don't have SSE2 available, convert to v4f32 so the generated
1665 // register is legal.
1666 if (!Subtarget->hasSSE2())
1667 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1672 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1673 Flag = Chain.getValue(1);
1674 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1677 // The x86-64 ABIs require that for returning structs by value we copy
1678 // the sret argument into %rax/%eax (depending on ABI) for the return.
1679 // Win32 requires us to put the sret argument to %eax as well.
1680 // We saved the argument into a virtual register in the entry block,
1681 // so now we copy the value out and into %rax/%eax.
1682 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1683 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1684 MachineFunction &MF = DAG.getMachineFunction();
1685 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1686 unsigned Reg = FuncInfo->getSRetReturnReg();
1688 "SRetReturnReg should have been set in LowerFormalArguments().");
1689 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1692 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1693 X86::RAX : X86::EAX;
1694 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1695 Flag = Chain.getValue(1);
1697 // RAX/EAX now acts like a return value.
1698 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1701 RetOps[0] = Chain; // Update chain.
1703 // Add the flag if we have it.
1705 RetOps.push_back(Flag);
1707 return DAG.getNode(X86ISD::RET_FLAG, dl,
1708 MVT::Other, &RetOps[0], RetOps.size());
1711 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1712 if (N->getNumValues() != 1)
1714 if (!N->hasNUsesOfValue(1, 0))
1717 SDValue TCChain = Chain;
1718 SDNode *Copy = *N->use_begin();
1719 if (Copy->getOpcode() == ISD::CopyToReg) {
1720 // If the copy has a glue operand, we conservatively assume it isn't safe to
1721 // perform a tail call.
1722 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1724 TCChain = Copy->getOperand(0);
1725 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1728 bool HasRet = false;
1729 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1731 if (UI->getOpcode() != X86ISD::RET_FLAG)
1744 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1745 ISD::NodeType ExtendKind) const {
1747 // TODO: Is this also valid on 32-bit?
1748 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1749 ReturnMVT = MVT::i8;
1751 ReturnMVT = MVT::i32;
1753 MVT MinVT = getRegisterType(ReturnMVT);
1754 return VT.bitsLT(MinVT) ? MinVT : VT;
1757 /// LowerCallResult - Lower the result values of a call into the
1758 /// appropriate copies out of appropriate physical registers.
1761 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1762 CallingConv::ID CallConv, bool isVarArg,
1763 const SmallVectorImpl<ISD::InputArg> &Ins,
1764 DebugLoc dl, SelectionDAG &DAG,
1765 SmallVectorImpl<SDValue> &InVals) const {
1767 // Assign locations to each value returned by this call.
1768 SmallVector<CCValAssign, 16> RVLocs;
1769 bool Is64Bit = Subtarget->is64Bit();
1770 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1771 getTargetMachine(), RVLocs, *DAG.getContext());
1772 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1774 // Copy all of the result registers out of their specified physreg.
1775 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1776 CCValAssign &VA = RVLocs[i];
1777 EVT CopyVT = VA.getValVT();
1779 // If this is x86-64, and we disabled SSE, we can't return FP values
1780 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1781 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1782 report_fatal_error("SSE register return with SSE disabled");
1787 // If this is a call to a function that returns an fp value on the floating
1788 // point stack, we must guarantee the value is popped from the stack, so
1789 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1790 // if the return value is not used. We use the FpPOP_RETVAL instruction
1792 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1793 // If we prefer to use the value in xmm registers, copy it out as f80 and
1794 // use a truncate to move it from fp stack reg to xmm reg.
1795 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1796 SDValue Ops[] = { Chain, InFlag };
1797 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1798 MVT::Other, MVT::Glue, Ops), 1);
1799 Val = Chain.getValue(0);
1801 // Round the f80 to the right size, which also moves it to the appropriate
1803 if (CopyVT != VA.getValVT())
1804 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1805 // This truncation won't change the value.
1806 DAG.getIntPtrConstant(1));
1808 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1809 CopyVT, InFlag).getValue(1);
1810 Val = Chain.getValue(0);
1812 InFlag = Chain.getValue(2);
1813 InVals.push_back(Val);
1819 //===----------------------------------------------------------------------===//
1820 // C & StdCall & Fast Calling Convention implementation
1821 //===----------------------------------------------------------------------===//
1822 // StdCall calling convention seems to be standard for many Windows' API
1823 // routines and around. It differs from C calling convention just a little:
1824 // callee should clean up the stack, not caller. Symbols should be also
1825 // decorated in some fancy way :) It doesn't support any vector arguments.
1826 // For info on fast calling convention see Fast Calling Convention (tail call)
1827 // implementation LowerX86_32FastCCCallTo.
1829 /// CallIsStructReturn - Determines whether a call uses struct return
1831 enum StructReturnType {
1836 static StructReturnType
1837 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1839 return NotStructReturn;
1841 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1842 if (!Flags.isSRet())
1843 return NotStructReturn;
1844 if (Flags.isInReg())
1845 return RegStructReturn;
1846 return StackStructReturn;
1849 /// ArgsAreStructReturn - Determines whether a function uses struct
1850 /// return semantics.
1851 static StructReturnType
1852 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1854 return NotStructReturn;
1856 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1857 if (!Flags.isSRet())
1858 return NotStructReturn;
1859 if (Flags.isInReg())
1860 return RegStructReturn;
1861 return StackStructReturn;
1864 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1865 /// by "Src" to address "Dst" with size and alignment information specified by
1866 /// the specific parameter attribute. The copy will be passed as a byval
1867 /// function parameter.
1869 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1870 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1872 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1874 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1875 /*isVolatile*/false, /*AlwaysInline=*/true,
1876 MachinePointerInfo(), MachinePointerInfo());
1879 /// IsTailCallConvention - Return true if the calling convention is one that
1880 /// supports tail call optimization.
1881 static bool IsTailCallConvention(CallingConv::ID CC) {
1882 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1883 CC == CallingConv::HiPE);
1886 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1887 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1891 CallingConv::ID CalleeCC = CS.getCallingConv();
1892 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1898 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1899 /// a tailcall target by changing its ABI.
1900 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1901 bool GuaranteedTailCallOpt) {
1902 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1906 X86TargetLowering::LowerMemArgument(SDValue Chain,
1907 CallingConv::ID CallConv,
1908 const SmallVectorImpl<ISD::InputArg> &Ins,
1909 DebugLoc dl, SelectionDAG &DAG,
1910 const CCValAssign &VA,
1911 MachineFrameInfo *MFI,
1913 // Create the nodes corresponding to a load from this parameter slot.
1914 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1915 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1916 getTargetMachine().Options.GuaranteedTailCallOpt);
1917 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1920 // If value is passed by pointer we have address passed instead of the value
1922 if (VA.getLocInfo() == CCValAssign::Indirect)
1923 ValVT = VA.getLocVT();
1925 ValVT = VA.getValVT();
1927 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1928 // changed with more analysis.
1929 // In case of tail call optimization mark all arguments mutable. Since they
1930 // could be overwritten by lowering of arguments in case of a tail call.
1931 if (Flags.isByVal()) {
1932 unsigned Bytes = Flags.getByValSize();
1933 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1934 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1935 return DAG.getFrameIndex(FI, getPointerTy());
1937 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1938 VA.getLocMemOffset(), isImmutable);
1939 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1940 return DAG.getLoad(ValVT, dl, Chain, FIN,
1941 MachinePointerInfo::getFixedStack(FI),
1942 false, false, false, 0);
1947 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1948 CallingConv::ID CallConv,
1950 const SmallVectorImpl<ISD::InputArg> &Ins,
1953 SmallVectorImpl<SDValue> &InVals)
1955 MachineFunction &MF = DAG.getMachineFunction();
1956 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1958 const Function* Fn = MF.getFunction();
1959 if (Fn->hasExternalLinkage() &&
1960 Subtarget->isTargetCygMing() &&
1961 Fn->getName() == "main")
1962 FuncInfo->setForceFramePointer(true);
1964 MachineFrameInfo *MFI = MF.getFrameInfo();
1965 bool Is64Bit = Subtarget->is64Bit();
1966 bool IsWindows = Subtarget->isTargetWindows();
1967 bool IsWin64 = Subtarget->isTargetWin64();
1969 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1970 "Var args not supported with calling convention fastcc, ghc or hipe");
1972 // Assign locations to all of the incoming arguments.
1973 SmallVector<CCValAssign, 16> ArgLocs;
1974 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1975 ArgLocs, *DAG.getContext());
1977 // Allocate shadow area for Win64
1979 CCInfo.AllocateStack(32, 8);
1982 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1984 unsigned LastVal = ~0U;
1986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1987 CCValAssign &VA = ArgLocs[i];
1988 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1990 assert(VA.getValNo() != LastVal &&
1991 "Don't support value assigned to multiple locs yet");
1993 LastVal = VA.getValNo();
1995 if (VA.isRegLoc()) {
1996 EVT RegVT = VA.getLocVT();
1997 const TargetRegisterClass *RC;
1998 if (RegVT == MVT::i32)
1999 RC = &X86::GR32RegClass;
2000 else if (Is64Bit && RegVT == MVT::i64)
2001 RC = &X86::GR64RegClass;
2002 else if (RegVT == MVT::f32)
2003 RC = &X86::FR32RegClass;
2004 else if (RegVT == MVT::f64)
2005 RC = &X86::FR64RegClass;
2006 else if (RegVT.is256BitVector())
2007 RC = &X86::VR256RegClass;
2008 else if (RegVT.is128BitVector())
2009 RC = &X86::VR128RegClass;
2010 else if (RegVT == MVT::x86mmx)
2011 RC = &X86::VR64RegClass;
2013 llvm_unreachable("Unknown argument type!");
2015 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2016 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2018 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2019 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2021 if (VA.getLocInfo() == CCValAssign::SExt)
2022 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2023 DAG.getValueType(VA.getValVT()));
2024 else if (VA.getLocInfo() == CCValAssign::ZExt)
2025 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2026 DAG.getValueType(VA.getValVT()));
2027 else if (VA.getLocInfo() == CCValAssign::BCvt)
2028 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2030 if (VA.isExtInLoc()) {
2031 // Handle MMX values passed in XMM regs.
2032 if (RegVT.isVector())
2033 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2035 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2038 assert(VA.isMemLoc());
2039 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2042 // If value is passed via pointer - do a load.
2043 if (VA.getLocInfo() == CCValAssign::Indirect)
2044 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2045 MachinePointerInfo(), false, false, false, 0);
2047 InVals.push_back(ArgValue);
2050 // The x86-64 ABIs require that for returning structs by value we copy
2051 // the sret argument into %rax/%eax (depending on ABI) for the return.
2052 // Win32 requires us to put the sret argument to %eax as well.
2053 // Save the argument into a virtual register so that we can access it
2054 // from the return points.
2055 if (MF.getFunction()->hasStructRetAttr() &&
2056 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2057 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2058 unsigned Reg = FuncInfo->getSRetReturnReg();
2060 MVT PtrTy = getPointerTy();
2061 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2062 FuncInfo->setSRetReturnReg(Reg);
2064 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2065 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2068 unsigned StackSize = CCInfo.getNextStackOffset();
2069 // Align stack specially for tail calls.
2070 if (FuncIsMadeTailCallSafe(CallConv,
2071 MF.getTarget().Options.GuaranteedTailCallOpt))
2072 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2074 // If the function takes variable number of arguments, make a frame index for
2075 // the start of the first vararg value... for expansion of llvm.va_start.
2077 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2078 CallConv != CallingConv::X86_ThisCall)) {
2079 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2082 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2084 // FIXME: We should really autogenerate these arrays
2085 static const uint16_t GPR64ArgRegsWin64[] = {
2086 X86::RCX, X86::RDX, X86::R8, X86::R9
2088 static const uint16_t GPR64ArgRegs64Bit[] = {
2089 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2091 static const uint16_t XMMArgRegs64Bit[] = {
2092 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2093 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2095 const uint16_t *GPR64ArgRegs;
2096 unsigned NumXMMRegs = 0;
2099 // The XMM registers which might contain var arg parameters are shadowed
2100 // in their paired GPR. So we only need to save the GPR to their home
2102 TotalNumIntRegs = 4;
2103 GPR64ArgRegs = GPR64ArgRegsWin64;
2105 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2106 GPR64ArgRegs = GPR64ArgRegs64Bit;
2108 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2111 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2114 bool NoImplicitFloatOps = Fn->getAttributes().
2115 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2116 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2117 "SSE register cannot be used when SSE is disabled!");
2118 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2119 NoImplicitFloatOps) &&
2120 "SSE register cannot be used when SSE is disabled!");
2121 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2122 !Subtarget->hasSSE1())
2123 // Kernel mode asks for SSE to be disabled, so don't push them
2125 TotalNumXMMRegs = 0;
2128 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2129 // Get to the caller-allocated home save location. Add 8 to account
2130 // for the return address.
2131 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2132 FuncInfo->setRegSaveFrameIndex(
2133 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2134 // Fixup to set vararg frame on shadow area (4 x i64).
2136 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2138 // For X86-64, if there are vararg parameters that are passed via
2139 // registers, then we must store them to their spots on the stack so
2140 // they may be loaded by deferencing the result of va_next.
2141 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2142 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2143 FuncInfo->setRegSaveFrameIndex(
2144 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2148 // Store the integer parameter registers.
2149 SmallVector<SDValue, 8> MemOps;
2150 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2152 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2153 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2154 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2155 DAG.getIntPtrConstant(Offset));
2156 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2157 &X86::GR64RegClass);
2158 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2160 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2161 MachinePointerInfo::getFixedStack(
2162 FuncInfo->getRegSaveFrameIndex(), Offset),
2164 MemOps.push_back(Store);
2168 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2169 // Now store the XMM (fp + vector) parameter registers.
2170 SmallVector<SDValue, 11> SaveXMMOps;
2171 SaveXMMOps.push_back(Chain);
2173 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2174 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2175 SaveXMMOps.push_back(ALVal);
2177 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2178 FuncInfo->getRegSaveFrameIndex()));
2179 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2180 FuncInfo->getVarArgsFPOffset()));
2182 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2183 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2184 &X86::VR128RegClass);
2185 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2186 SaveXMMOps.push_back(Val);
2188 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2190 &SaveXMMOps[0], SaveXMMOps.size()));
2193 if (!MemOps.empty())
2194 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2195 &MemOps[0], MemOps.size());
2199 // Some CCs need callee pop.
2200 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2201 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2202 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2204 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2205 // If this is an sret function, the return should pop the hidden pointer.
2206 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2207 argsAreStructReturn(Ins) == StackStructReturn)
2208 FuncInfo->setBytesToPopOnReturn(4);
2212 // RegSaveFrameIndex is X86-64 only.
2213 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2214 if (CallConv == CallingConv::X86_FastCall ||
2215 CallConv == CallingConv::X86_ThisCall)
2216 // fastcc functions can't have varargs.
2217 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2220 FuncInfo->setArgumentStackSize(StackSize);
2226 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2227 SDValue StackPtr, SDValue Arg,
2228 DebugLoc dl, SelectionDAG &DAG,
2229 const CCValAssign &VA,
2230 ISD::ArgFlagsTy Flags) const {
2231 unsigned LocMemOffset = VA.getLocMemOffset();
2232 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2233 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2234 if (Flags.isByVal())
2235 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2237 return DAG.getStore(Chain, dl, Arg, PtrOff,
2238 MachinePointerInfo::getStack(LocMemOffset),
2242 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2243 /// optimization is performed and it is required.
2245 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2246 SDValue &OutRetAddr, SDValue Chain,
2247 bool IsTailCall, bool Is64Bit,
2248 int FPDiff, DebugLoc dl) const {
2249 // Adjust the Return address stack slot.
2250 EVT VT = getPointerTy();
2251 OutRetAddr = getReturnAddressFrameIndex(DAG);
2253 // Load the "old" Return address.
2254 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2255 false, false, false, 0);
2256 return SDValue(OutRetAddr.getNode(), 1);
2259 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2260 /// optimization is performed and it is required (FPDiff!=0).
2262 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2263 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2264 unsigned SlotSize, int FPDiff, DebugLoc dl) {
2265 // Store the return address to the appropriate stack slot.
2266 if (!FPDiff) return Chain;
2267 // Calculate the new stack slot for the return address.
2268 int NewReturnAddrFI =
2269 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2270 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2271 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2272 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2278 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2279 SmallVectorImpl<SDValue> &InVals) const {
2280 SelectionDAG &DAG = CLI.DAG;
2281 DebugLoc &dl = CLI.DL;
2282 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2283 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2284 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2285 SDValue Chain = CLI.Chain;
2286 SDValue Callee = CLI.Callee;
2287 CallingConv::ID CallConv = CLI.CallConv;
2288 bool &isTailCall = CLI.IsTailCall;
2289 bool isVarArg = CLI.IsVarArg;
2291 MachineFunction &MF = DAG.getMachineFunction();
2292 bool Is64Bit = Subtarget->is64Bit();
2293 bool IsWin64 = Subtarget->isTargetWin64();
2294 bool IsWindows = Subtarget->isTargetWindows();
2295 StructReturnType SR = callIsStructReturn(Outs);
2296 bool IsSibcall = false;
2298 if (MF.getTarget().Options.DisableTailCalls)
2302 // Check if it's really possible to do a tail call.
2303 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2304 isVarArg, SR != NotStructReturn,
2305 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2306 Outs, OutVals, Ins, DAG);
2308 // Sibcalls are automatically detected tailcalls which do not require
2310 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2317 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2318 "Var args not supported with calling convention fastcc, ghc or hipe");
2320 // Analyze operands of the call, assigning locations to each operand.
2321 SmallVector<CCValAssign, 16> ArgLocs;
2322 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2323 ArgLocs, *DAG.getContext());
2325 // Allocate shadow area for Win64
2327 CCInfo.AllocateStack(32, 8);
2330 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2332 // Get a count of how many bytes are to be pushed on the stack.
2333 unsigned NumBytes = CCInfo.getNextStackOffset();
2335 // This is a sibcall. The memory operands are available in caller's
2336 // own caller's stack.
2338 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2339 IsTailCallConvention(CallConv))
2340 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2343 if (isTailCall && !IsSibcall) {
2344 // Lower arguments at fp - stackoffset + fpdiff.
2345 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2346 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2348 FPDiff = NumBytesCallerPushed - NumBytes;
2350 // Set the delta of movement of the returnaddr stackslot.
2351 // But only set if delta is greater than previous delta.
2352 if (FPDiff < X86Info->getTCReturnAddrDelta())
2353 X86Info->setTCReturnAddrDelta(FPDiff);
2357 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2359 SDValue RetAddrFrIdx;
2360 // Load return address for tail calls.
2361 if (isTailCall && FPDiff)
2362 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2363 Is64Bit, FPDiff, dl);
2365 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2366 SmallVector<SDValue, 8> MemOpChains;
2369 // Walk the register/memloc assignments, inserting copies/loads. In the case
2370 // of tail call optimization arguments are handle later.
2371 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2372 CCValAssign &VA = ArgLocs[i];
2373 EVT RegVT = VA.getLocVT();
2374 SDValue Arg = OutVals[i];
2375 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2376 bool isByVal = Flags.isByVal();
2378 // Promote the value if needed.
2379 switch (VA.getLocInfo()) {
2380 default: llvm_unreachable("Unknown loc info!");
2381 case CCValAssign::Full: break;
2382 case CCValAssign::SExt:
2383 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2385 case CCValAssign::ZExt:
2386 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2388 case CCValAssign::AExt:
2389 if (RegVT.is128BitVector()) {
2390 // Special case: passing MMX values in XMM registers.
2391 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2392 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2393 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2395 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2397 case CCValAssign::BCvt:
2398 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2400 case CCValAssign::Indirect: {
2401 // Store the argument.
2402 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2403 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2404 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2405 MachinePointerInfo::getFixedStack(FI),
2412 if (VA.isRegLoc()) {
2413 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2414 if (isVarArg && IsWin64) {
2415 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2416 // shadow reg if callee is a varargs function.
2417 unsigned ShadowReg = 0;
2418 switch (VA.getLocReg()) {
2419 case X86::XMM0: ShadowReg = X86::RCX; break;
2420 case X86::XMM1: ShadowReg = X86::RDX; break;
2421 case X86::XMM2: ShadowReg = X86::R8; break;
2422 case X86::XMM3: ShadowReg = X86::R9; break;
2425 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2427 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2428 assert(VA.isMemLoc());
2429 if (StackPtr.getNode() == 0)
2430 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2432 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2433 dl, DAG, VA, Flags));
2437 if (!MemOpChains.empty())
2438 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2439 &MemOpChains[0], MemOpChains.size());
2441 if (Subtarget->isPICStyleGOT()) {
2442 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2445 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2446 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2448 // If we are tail calling and generating PIC/GOT style code load the
2449 // address of the callee into ECX. The value in ecx is used as target of
2450 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2451 // for tail calls on PIC/GOT architectures. Normally we would just put the
2452 // address of GOT into ebx and then call target@PLT. But for tail calls
2453 // ebx would be restored (since ebx is callee saved) before jumping to the
2456 // Note: The actual moving to ECX is done further down.
2457 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2458 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2459 !G->getGlobal()->hasProtectedVisibility())
2460 Callee = LowerGlobalAddress(Callee, DAG);
2461 else if (isa<ExternalSymbolSDNode>(Callee))
2462 Callee = LowerExternalSymbol(Callee, DAG);
2466 if (Is64Bit && isVarArg && !IsWin64) {
2467 // From AMD64 ABI document:
2468 // For calls that may call functions that use varargs or stdargs
2469 // (prototype-less calls or calls to functions containing ellipsis (...) in
2470 // the declaration) %al is used as hidden argument to specify the number
2471 // of SSE registers used. The contents of %al do not need to match exactly
2472 // the number of registers, but must be an ubound on the number of SSE
2473 // registers used and is in the range 0 - 8 inclusive.
2475 // Count the number of XMM registers allocated.
2476 static const uint16_t XMMArgRegs[] = {
2477 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2478 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2480 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2481 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2482 && "SSE registers cannot be used when SSE is disabled");
2484 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2485 DAG.getConstant(NumXMMRegs, MVT::i8)));
2488 // For tail calls lower the arguments to the 'real' stack slot.
2490 // Force all the incoming stack arguments to be loaded from the stack
2491 // before any new outgoing arguments are stored to the stack, because the
2492 // outgoing stack slots may alias the incoming argument stack slots, and
2493 // the alias isn't otherwise explicit. This is slightly more conservative
2494 // than necessary, because it means that each store effectively depends
2495 // on every argument instead of just those arguments it would clobber.
2496 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2498 SmallVector<SDValue, 8> MemOpChains2;
2501 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2503 CCValAssign &VA = ArgLocs[i];
2506 assert(VA.isMemLoc());
2507 SDValue Arg = OutVals[i];
2508 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2509 // Create frame index.
2510 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2511 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2512 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2513 FIN = DAG.getFrameIndex(FI, getPointerTy());
2515 if (Flags.isByVal()) {
2516 // Copy relative to framepointer.
2517 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2518 if (StackPtr.getNode() == 0)
2519 StackPtr = DAG.getCopyFromReg(Chain, dl,
2520 RegInfo->getStackRegister(),
2522 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2524 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2528 // Store relative to framepointer.
2529 MemOpChains2.push_back(
2530 DAG.getStore(ArgChain, dl, Arg, FIN,
2531 MachinePointerInfo::getFixedStack(FI),
2537 if (!MemOpChains2.empty())
2538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2539 &MemOpChains2[0], MemOpChains2.size());
2541 // Store the return address to the appropriate stack slot.
2542 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2543 getPointerTy(), RegInfo->getSlotSize(),
2547 // Build a sequence of copy-to-reg nodes chained together with token chain
2548 // and flag operands which copy the outgoing args into registers.
2550 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2551 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2552 RegsToPass[i].second, InFlag);
2553 InFlag = Chain.getValue(1);
2556 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2557 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2558 // In the 64-bit large code model, we have to make all calls
2559 // through a register, since the call instruction's 32-bit
2560 // pc-relative offset may not be large enough to hold the whole
2562 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2563 // If the callee is a GlobalAddress node (quite common, every direct call
2564 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2567 // We should use extra load for direct calls to dllimported functions in
2569 const GlobalValue *GV = G->getGlobal();
2570 if (!GV->hasDLLImportLinkage()) {
2571 unsigned char OpFlags = 0;
2572 bool ExtraLoad = false;
2573 unsigned WrapperKind = ISD::DELETED_NODE;
2575 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2576 // external symbols most go through the PLT in PIC mode. If the symbol
2577 // has hidden or protected visibility, or if it is static or local, then
2578 // we don't need to use the PLT - we can directly call it.
2579 if (Subtarget->isTargetELF() &&
2580 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2581 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2582 OpFlags = X86II::MO_PLT;
2583 } else if (Subtarget->isPICStyleStubAny() &&
2584 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2585 (!Subtarget->getTargetTriple().isMacOSX() ||
2586 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2587 // PC-relative references to external symbols should go through $stub,
2588 // unless we're building with the leopard linker or later, which
2589 // automatically synthesizes these stubs.
2590 OpFlags = X86II::MO_DARWIN_STUB;
2591 } else if (Subtarget->isPICStyleRIPRel() &&
2592 isa<Function>(GV) &&
2593 cast<Function>(GV)->getAttributes().
2594 hasAttribute(AttributeSet::FunctionIndex,
2595 Attribute::NonLazyBind)) {
2596 // If the function is marked as non-lazy, generate an indirect call
2597 // which loads from the GOT directly. This avoids runtime overhead
2598 // at the cost of eager binding (and one extra byte of encoding).
2599 OpFlags = X86II::MO_GOTPCREL;
2600 WrapperKind = X86ISD::WrapperRIP;
2604 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2605 G->getOffset(), OpFlags);
2607 // Add a wrapper if needed.
2608 if (WrapperKind != ISD::DELETED_NODE)
2609 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2610 // Add extra indirection if needed.
2612 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2613 MachinePointerInfo::getGOT(),
2614 false, false, false, 0);
2616 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2617 unsigned char OpFlags = 0;
2619 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2620 // external symbols should go through the PLT.
2621 if (Subtarget->isTargetELF() &&
2622 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2623 OpFlags = X86II::MO_PLT;
2624 } else if (Subtarget->isPICStyleStubAny() &&
2625 (!Subtarget->getTargetTriple().isMacOSX() ||
2626 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2627 // PC-relative references to external symbols should go through $stub,
2628 // unless we're building with the leopard linker or later, which
2629 // automatically synthesizes these stubs.
2630 OpFlags = X86II::MO_DARWIN_STUB;
2633 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2637 // Returns a chain & a flag for retval copy to use.
2638 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2639 SmallVector<SDValue, 8> Ops;
2641 if (!IsSibcall && isTailCall) {
2642 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2643 DAG.getIntPtrConstant(0, true), InFlag);
2644 InFlag = Chain.getValue(1);
2647 Ops.push_back(Chain);
2648 Ops.push_back(Callee);
2651 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2653 // Add argument registers to the end of the list so that they are known live
2655 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2656 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2657 RegsToPass[i].second.getValueType()));
2659 // Add a register mask operand representing the call-preserved registers.
2660 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2661 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2662 assert(Mask && "Missing call preserved mask for calling convention");
2663 Ops.push_back(DAG.getRegisterMask(Mask));
2665 if (InFlag.getNode())
2666 Ops.push_back(InFlag);
2670 //// If this is the first return lowered for this function, add the regs
2671 //// to the liveout set for the function.
2672 // This isn't right, although it's probably harmless on x86; liveouts
2673 // should be computed from returns not tail calls. Consider a void
2674 // function making a tail call to a function returning int.
2675 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2678 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2679 InFlag = Chain.getValue(1);
2681 // Create the CALLSEQ_END node.
2682 unsigned NumBytesForCalleeToPush;
2683 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2684 getTargetMachine().Options.GuaranteedTailCallOpt))
2685 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2686 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2687 SR == StackStructReturn)
2688 // If this is a call to a struct-return function, the callee
2689 // pops the hidden struct pointer, so we have to push it back.
2690 // This is common for Darwin/X86, Linux & Mingw32 targets.
2691 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2692 NumBytesForCalleeToPush = 4;
2694 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2696 // Returns a flag for retval copy to use.
2698 Chain = DAG.getCALLSEQ_END(Chain,
2699 DAG.getIntPtrConstant(NumBytes, true),
2700 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2703 InFlag = Chain.getValue(1);
2706 // Handle result values, copying them out of physregs into vregs that we
2708 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2709 Ins, dl, DAG, InVals);
2712 //===----------------------------------------------------------------------===//
2713 // Fast Calling Convention (tail call) implementation
2714 //===----------------------------------------------------------------------===//
2716 // Like std call, callee cleans arguments, convention except that ECX is
2717 // reserved for storing the tail called function address. Only 2 registers are
2718 // free for argument passing (inreg). Tail call optimization is performed
2720 // * tailcallopt is enabled
2721 // * caller/callee are fastcc
2722 // On X86_64 architecture with GOT-style position independent code only local
2723 // (within module) calls are supported at the moment.
2724 // To keep the stack aligned according to platform abi the function
2725 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2726 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2727 // If a tail called function callee has more arguments than the caller the
2728 // caller needs to make sure that there is room to move the RETADDR to. This is
2729 // achieved by reserving an area the size of the argument delta right after the
2730 // original REtADDR, but before the saved framepointer or the spilled registers
2731 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2743 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2744 /// for a 16 byte align requirement.
2746 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2747 SelectionDAG& DAG) const {
2748 MachineFunction &MF = DAG.getMachineFunction();
2749 const TargetMachine &TM = MF.getTarget();
2750 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2751 unsigned StackAlignment = TFI.getStackAlignment();
2752 uint64_t AlignMask = StackAlignment - 1;
2753 int64_t Offset = StackSize;
2754 unsigned SlotSize = RegInfo->getSlotSize();
2755 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2756 // Number smaller than 12 so just add the difference.
2757 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2759 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2760 Offset = ((~AlignMask) & Offset) + StackAlignment +
2761 (StackAlignment-SlotSize);
2766 /// MatchingStackOffset - Return true if the given stack call argument is
2767 /// already available in the same position (relatively) of the caller's
2768 /// incoming argument stack.
2770 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2771 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2772 const X86InstrInfo *TII) {
2773 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2775 if (Arg.getOpcode() == ISD::CopyFromReg) {
2776 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2777 if (!TargetRegisterInfo::isVirtualRegister(VR))
2779 MachineInstr *Def = MRI->getVRegDef(VR);
2782 if (!Flags.isByVal()) {
2783 if (!TII->isLoadFromStackSlot(Def, FI))
2786 unsigned Opcode = Def->getOpcode();
2787 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2788 Def->getOperand(1).isFI()) {
2789 FI = Def->getOperand(1).getIndex();
2790 Bytes = Flags.getByValSize();
2794 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2795 if (Flags.isByVal())
2796 // ByVal argument is passed in as a pointer but it's now being
2797 // dereferenced. e.g.
2798 // define @foo(%struct.X* %A) {
2799 // tail call @bar(%struct.X* byval %A)
2802 SDValue Ptr = Ld->getBasePtr();
2803 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2806 FI = FINode->getIndex();
2807 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2808 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2809 FI = FINode->getIndex();
2810 Bytes = Flags.getByValSize();
2814 assert(FI != INT_MAX);
2815 if (!MFI->isFixedObjectIndex(FI))
2817 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2820 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2821 /// for tail call optimization. Targets which want to do tail call
2822 /// optimization should implement this function.
2824 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2825 CallingConv::ID CalleeCC,
2827 bool isCalleeStructRet,
2828 bool isCallerStructRet,
2830 const SmallVectorImpl<ISD::OutputArg> &Outs,
2831 const SmallVectorImpl<SDValue> &OutVals,
2832 const SmallVectorImpl<ISD::InputArg> &Ins,
2833 SelectionDAG &DAG) const {
2834 if (!IsTailCallConvention(CalleeCC) &&
2835 CalleeCC != CallingConv::C)
2838 // If -tailcallopt is specified, make fastcc functions tail-callable.
2839 const MachineFunction &MF = DAG.getMachineFunction();
2840 const Function *CallerF = DAG.getMachineFunction().getFunction();
2842 // If the function return type is x86_fp80 and the callee return type is not,
2843 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2844 // perform a tailcall optimization here.
2845 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
2848 CallingConv::ID CallerCC = CallerF->getCallingConv();
2849 bool CCMatch = CallerCC == CalleeCC;
2851 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2852 if (IsTailCallConvention(CalleeCC) && CCMatch)
2857 // Look for obvious safe cases to perform tail call optimization that do not
2858 // require ABI changes. This is what gcc calls sibcall.
2860 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2861 // emit a special epilogue.
2862 if (RegInfo->needsStackRealignment(MF))
2865 // Also avoid sibcall optimization if either caller or callee uses struct
2866 // return semantics.
2867 if (isCalleeStructRet || isCallerStructRet)
2870 // An stdcall caller is expected to clean up its arguments; the callee
2871 // isn't going to do that.
2872 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
2875 // Do not sibcall optimize vararg calls unless all arguments are passed via
2877 if (isVarArg && !Outs.empty()) {
2879 // Optimizing for varargs on Win64 is unlikely to be safe without
2880 // additional testing.
2881 if (Subtarget->isTargetWin64())
2884 SmallVector<CCValAssign, 16> ArgLocs;
2885 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2886 getTargetMachine(), ArgLocs, *DAG.getContext());
2888 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2889 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2890 if (!ArgLocs[i].isRegLoc())
2894 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2895 // stack. Therefore, if it's not used by the call it is not safe to optimize
2896 // this into a sibcall.
2897 bool Unused = false;
2898 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2905 SmallVector<CCValAssign, 16> RVLocs;
2906 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2907 getTargetMachine(), RVLocs, *DAG.getContext());
2908 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2909 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2910 CCValAssign &VA = RVLocs[i];
2911 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2916 // If the calling conventions do not match, then we'd better make sure the
2917 // results are returned in the same way as what the caller expects.
2919 SmallVector<CCValAssign, 16> RVLocs1;
2920 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2921 getTargetMachine(), RVLocs1, *DAG.getContext());
2922 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2924 SmallVector<CCValAssign, 16> RVLocs2;
2925 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2926 getTargetMachine(), RVLocs2, *DAG.getContext());
2927 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2929 if (RVLocs1.size() != RVLocs2.size())
2931 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2932 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2934 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2936 if (RVLocs1[i].isRegLoc()) {
2937 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2940 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2946 // If the callee takes no arguments then go on to check the results of the
2948 if (!Outs.empty()) {
2949 // Check if stack adjustment is needed. For now, do not do this if any
2950 // argument is passed on the stack.
2951 SmallVector<CCValAssign, 16> ArgLocs;
2952 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2953 getTargetMachine(), ArgLocs, *DAG.getContext());
2955 // Allocate shadow area for Win64
2956 if (Subtarget->isTargetWin64()) {
2957 CCInfo.AllocateStack(32, 8);
2960 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2961 if (CCInfo.getNextStackOffset()) {
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2966 // Check if the arguments are already laid out in the right way as
2967 // the caller's fixed stack objects.
2968 MachineFrameInfo *MFI = MF.getFrameInfo();
2969 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2970 const X86InstrInfo *TII =
2971 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
2972 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2973 CCValAssign &VA = ArgLocs[i];
2974 SDValue Arg = OutVals[i];
2975 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2976 if (VA.getLocInfo() == CCValAssign::Indirect)
2978 if (!VA.isRegLoc()) {
2979 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2986 // If the tailcall address may be in a register, then make sure it's
2987 // possible to register allocate for it. In 32-bit, the call address can
2988 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2989 // callee-saved registers are restored. These happen to be the same
2990 // registers used to pass 'inreg' arguments so watch out for those.
2991 if (!Subtarget->is64Bit() &&
2992 ((!isa<GlobalAddressSDNode>(Callee) &&
2993 !isa<ExternalSymbolSDNode>(Callee)) ||
2994 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
2995 unsigned NumInRegs = 0;
2996 // In PIC we need an extra register to formulate the address computation
2998 unsigned MaxInRegs =
2999 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3001 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3002 CCValAssign &VA = ArgLocs[i];
3005 unsigned Reg = VA.getLocReg();
3008 case X86::EAX: case X86::EDX: case X86::ECX:
3009 if (++NumInRegs == MaxInRegs)
3021 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3022 const TargetLibraryInfo *libInfo) const {
3023 return X86::createFastISel(funcInfo, libInfo);
3026 //===----------------------------------------------------------------------===//
3027 // Other Lowering Hooks
3028 //===----------------------------------------------------------------------===//
3030 static bool MayFoldLoad(SDValue Op) {
3031 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3034 static bool MayFoldIntoStore(SDValue Op) {
3035 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3038 static bool isTargetShuffle(unsigned Opcode) {
3040 default: return false;
3041 case X86ISD::PSHUFD:
3042 case X86ISD::PSHUFHW:
3043 case X86ISD::PSHUFLW:
3045 case X86ISD::PALIGNR:
3046 case X86ISD::MOVLHPS:
3047 case X86ISD::MOVLHPD:
3048 case X86ISD::MOVHLPS:
3049 case X86ISD::MOVLPS:
3050 case X86ISD::MOVLPD:
3051 case X86ISD::MOVSHDUP:
3052 case X86ISD::MOVSLDUP:
3053 case X86ISD::MOVDDUP:
3056 case X86ISD::UNPCKL:
3057 case X86ISD::UNPCKH:
3058 case X86ISD::VPERMILP:
3059 case X86ISD::VPERM2X128:
3060 case X86ISD::VPERMI:
3065 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3066 SDValue V1, SelectionDAG &DAG) {
3068 default: llvm_unreachable("Unknown x86 shuffle node");
3069 case X86ISD::MOVSHDUP:
3070 case X86ISD::MOVSLDUP:
3071 case X86ISD::MOVDDUP:
3072 return DAG.getNode(Opc, dl, VT, V1);
3076 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3077 SDValue V1, unsigned TargetMask,
3078 SelectionDAG &DAG) {
3080 default: llvm_unreachable("Unknown x86 shuffle node");
3081 case X86ISD::PSHUFD:
3082 case X86ISD::PSHUFHW:
3083 case X86ISD::PSHUFLW:
3084 case X86ISD::VPERMILP:
3085 case X86ISD::VPERMI:
3086 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3090 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3091 SDValue V1, SDValue V2, unsigned TargetMask,
3092 SelectionDAG &DAG) {
3094 default: llvm_unreachable("Unknown x86 shuffle node");
3095 case X86ISD::PALIGNR:
3097 case X86ISD::VPERM2X128:
3098 return DAG.getNode(Opc, dl, VT, V1, V2,
3099 DAG.getConstant(TargetMask, MVT::i8));
3103 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3104 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3106 default: llvm_unreachable("Unknown x86 shuffle node");
3107 case X86ISD::MOVLHPS:
3108 case X86ISD::MOVLHPD:
3109 case X86ISD::MOVHLPS:
3110 case X86ISD::MOVLPS:
3111 case X86ISD::MOVLPD:
3114 case X86ISD::UNPCKL:
3115 case X86ISD::UNPCKH:
3116 return DAG.getNode(Opc, dl, VT, V1, V2);
3120 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3121 MachineFunction &MF = DAG.getMachineFunction();
3122 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3123 int ReturnAddrIndex = FuncInfo->getRAIndex();
3125 if (ReturnAddrIndex == 0) {
3126 // Set up a frame object for the return address.
3127 unsigned SlotSize = RegInfo->getSlotSize();
3128 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3130 FuncInfo->setRAIndex(ReturnAddrIndex);
3133 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3136 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3137 bool hasSymbolicDisplacement) {
3138 // Offset should fit into 32 bit immediate field.
3139 if (!isInt<32>(Offset))
3142 // If we don't have a symbolic displacement - we don't have any extra
3144 if (!hasSymbolicDisplacement)
3147 // FIXME: Some tweaks might be needed for medium code model.
3148 if (M != CodeModel::Small && M != CodeModel::Kernel)
3151 // For small code model we assume that latest object is 16MB before end of 31
3152 // bits boundary. We may also accept pretty large negative constants knowing
3153 // that all objects are in the positive half of address space.
3154 if (M == CodeModel::Small && Offset < 16*1024*1024)
3157 // For kernel code model we know that all object resist in the negative half
3158 // of 32bits address space. We may not accept negative offsets, since they may
3159 // be just off and we may accept pretty large positive ones.
3160 if (M == CodeModel::Kernel && Offset > 0)
3166 /// isCalleePop - Determines whether the callee is required to pop its
3167 /// own arguments. Callee pop is necessary to support tail calls.
3168 bool X86::isCalleePop(CallingConv::ID CallingConv,
3169 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3173 switch (CallingConv) {
3176 case CallingConv::X86_StdCall:
3178 case CallingConv::X86_FastCall:
3180 case CallingConv::X86_ThisCall:
3182 case CallingConv::Fast:
3184 case CallingConv::GHC:
3186 case CallingConv::HiPE:
3191 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3192 /// specific condition code, returning the condition code and the LHS/RHS of the
3193 /// comparison to make.
3194 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3195 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3197 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3198 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3199 // X > -1 -> X == 0, jump !sign.
3200 RHS = DAG.getConstant(0, RHS.getValueType());
3201 return X86::COND_NS;
3203 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3204 // X < 0 -> X == 0, jump on sign.
3207 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3209 RHS = DAG.getConstant(0, RHS.getValueType());
3210 return X86::COND_LE;
3214 switch (SetCCOpcode) {
3215 default: llvm_unreachable("Invalid integer condition!");
3216 case ISD::SETEQ: return X86::COND_E;
3217 case ISD::SETGT: return X86::COND_G;
3218 case ISD::SETGE: return X86::COND_GE;
3219 case ISD::SETLT: return X86::COND_L;
3220 case ISD::SETLE: return X86::COND_LE;
3221 case ISD::SETNE: return X86::COND_NE;
3222 case ISD::SETULT: return X86::COND_B;
3223 case ISD::SETUGT: return X86::COND_A;
3224 case ISD::SETULE: return X86::COND_BE;
3225 case ISD::SETUGE: return X86::COND_AE;
3229 // First determine if it is required or is profitable to flip the operands.
3231 // If LHS is a foldable load, but RHS is not, flip the condition.
3232 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3233 !ISD::isNON_EXTLoad(RHS.getNode())) {
3234 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3235 std::swap(LHS, RHS);
3238 switch (SetCCOpcode) {
3244 std::swap(LHS, RHS);
3248 // On a floating point condition, the flags are set as follows:
3250 // 0 | 0 | 0 | X > Y
3251 // 0 | 0 | 1 | X < Y
3252 // 1 | 0 | 0 | X == Y
3253 // 1 | 1 | 1 | unordered
3254 switch (SetCCOpcode) {
3255 default: llvm_unreachable("Condcode should be pre-legalized away");
3257 case ISD::SETEQ: return X86::COND_E;
3258 case ISD::SETOLT: // flipped
3260 case ISD::SETGT: return X86::COND_A;
3261 case ISD::SETOLE: // flipped
3263 case ISD::SETGE: return X86::COND_AE;
3264 case ISD::SETUGT: // flipped
3266 case ISD::SETLT: return X86::COND_B;
3267 case ISD::SETUGE: // flipped
3269 case ISD::SETLE: return X86::COND_BE;
3271 case ISD::SETNE: return X86::COND_NE;
3272 case ISD::SETUO: return X86::COND_P;
3273 case ISD::SETO: return X86::COND_NP;
3275 case ISD::SETUNE: return X86::COND_INVALID;
3279 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3280 /// code. Current x86 isa includes the following FP cmov instructions:
3281 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3282 static bool hasFPCMov(unsigned X86CC) {
3298 /// isFPImmLegal - Returns true if the target can instruction select the
3299 /// specified FP immediate natively. If false, the legalizer will
3300 /// materialize the FP immediate as a load from a constant pool.
3301 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3302 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3303 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3309 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3310 /// the specified range (L, H].
3311 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3312 return (Val < 0) || (Val >= Low && Val < Hi);
3315 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3316 /// specified value.
3317 static bool isUndefOrEqual(int Val, int CmpVal) {
3318 return (Val < 0 || Val == CmpVal);
3321 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3322 /// from position Pos and ending in Pos+Size, falls within the specified
3323 /// sequential range (L, L+Pos]. or is undef.
3324 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3325 unsigned Pos, unsigned Size, int Low) {
3326 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3327 if (!isUndefOrEqual(Mask[i], Low))
3332 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3333 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3334 /// the second operand.
3335 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3336 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3337 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3338 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3339 return (Mask[0] < 2 && Mask[1] < 2);
3343 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3344 /// is suitable for input to PSHUFHW.
3345 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3346 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3349 // Lower quadword copied in order or undef.
3350 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3353 // Upper quadword shuffled.
3354 for (unsigned i = 4; i != 8; ++i)
3355 if (!isUndefOrInRange(Mask[i], 4, 8))
3358 if (VT == MVT::v16i16) {
3359 // Lower quadword copied in order or undef.
3360 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3363 // Upper quadword shuffled.
3364 for (unsigned i = 12; i != 16; ++i)
3365 if (!isUndefOrInRange(Mask[i], 12, 16))
3372 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3373 /// is suitable for input to PSHUFLW.
3374 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3375 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3378 // Upper quadword copied in order.
3379 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3382 // Lower quadword shuffled.
3383 for (unsigned i = 0; i != 4; ++i)
3384 if (!isUndefOrInRange(Mask[i], 0, 4))
3387 if (VT == MVT::v16i16) {
3388 // Upper quadword copied in order.
3389 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3392 // Lower quadword shuffled.
3393 for (unsigned i = 8; i != 12; ++i)
3394 if (!isUndefOrInRange(Mask[i], 8, 12))
3401 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3402 /// is suitable for input to PALIGNR.
3403 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3404 const X86Subtarget *Subtarget) {
3405 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3406 (VT.is256BitVector() && !Subtarget->hasInt256()))
3409 unsigned NumElts = VT.getVectorNumElements();
3410 unsigned NumLanes = VT.getSizeInBits()/128;
3411 unsigned NumLaneElts = NumElts/NumLanes;
3413 // Do not handle 64-bit element shuffles with palignr.
3414 if (NumLaneElts == 2)
3417 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3419 for (i = 0; i != NumLaneElts; ++i) {
3424 // Lane is all undef, go to next lane
3425 if (i == NumLaneElts)
3428 int Start = Mask[i+l];
3430 // Make sure its in this lane in one of the sources
3431 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3432 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3435 // If not lane 0, then we must match lane 0
3436 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3439 // Correct second source to be contiguous with first source
3440 if (Start >= (int)NumElts)
3441 Start -= NumElts - NumLaneElts;
3443 // Make sure we're shifting in the right direction.
3444 if (Start <= (int)(i+l))
3449 // Check the rest of the elements to see if they are consecutive.
3450 for (++i; i != NumLaneElts; ++i) {
3451 int Idx = Mask[i+l];
3453 // Make sure its in this lane
3454 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3455 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3458 // If not lane 0, then we must match lane 0
3459 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3462 if (Idx >= (int)NumElts)
3463 Idx -= NumElts - NumLaneElts;
3465 if (!isUndefOrEqual(Idx, Start+i))
3474 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3475 /// the two vector operands have swapped position.
3476 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3477 unsigned NumElems) {
3478 for (unsigned i = 0; i != NumElems; ++i) {
3482 else if (idx < (int)NumElems)
3483 Mask[i] = idx + NumElems;
3485 Mask[i] = idx - NumElems;
3489 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3490 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3491 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3492 /// reverse of what x86 shuffles want.
3493 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3494 bool Commuted = false) {
3495 if (!HasFp256 && VT.is256BitVector())
3498 unsigned NumElems = VT.getVectorNumElements();
3499 unsigned NumLanes = VT.getSizeInBits()/128;
3500 unsigned NumLaneElems = NumElems/NumLanes;
3502 if (NumLaneElems != 2 && NumLaneElems != 4)
3505 // VSHUFPSY divides the resulting vector into 4 chunks.
3506 // The sources are also splitted into 4 chunks, and each destination
3507 // chunk must come from a different source chunk.
3509 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3510 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3512 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3513 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3515 // VSHUFPDY divides the resulting vector into 4 chunks.
3516 // The sources are also splitted into 4 chunks, and each destination
3517 // chunk must come from a different source chunk.
3519 // SRC1 => X3 X2 X1 X0
3520 // SRC2 => Y3 Y2 Y1 Y0
3522 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3524 unsigned HalfLaneElems = NumLaneElems/2;
3525 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3526 for (unsigned i = 0; i != NumLaneElems; ++i) {
3527 int Idx = Mask[i+l];
3528 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3529 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3531 // For VSHUFPSY, the mask of the second half must be the same as the
3532 // first but with the appropriate offsets. This works in the same way as
3533 // VPERMILPS works with masks.
3534 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3536 if (!isUndefOrEqual(Idx, Mask[i]+l))
3544 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3545 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3546 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3547 if (!VT.is128BitVector())
3550 unsigned NumElems = VT.getVectorNumElements();
3555 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3556 return isUndefOrEqual(Mask[0], 6) &&
3557 isUndefOrEqual(Mask[1], 7) &&
3558 isUndefOrEqual(Mask[2], 2) &&
3559 isUndefOrEqual(Mask[3], 3);
3562 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3563 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3565 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3566 if (!VT.is128BitVector())
3569 unsigned NumElems = VT.getVectorNumElements();
3574 return isUndefOrEqual(Mask[0], 2) &&
3575 isUndefOrEqual(Mask[1], 3) &&
3576 isUndefOrEqual(Mask[2], 2) &&
3577 isUndefOrEqual(Mask[3], 3);
3580 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3581 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3582 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3583 if (!VT.is128BitVector())
3586 unsigned NumElems = VT.getVectorNumElements();
3588 if (NumElems != 2 && NumElems != 4)
3591 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3592 if (!isUndefOrEqual(Mask[i], i + NumElems))
3595 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3596 if (!isUndefOrEqual(Mask[i], i))
3602 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3603 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3604 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3605 if (!VT.is128BitVector())
3608 unsigned NumElems = VT.getVectorNumElements();
3610 if (NumElems != 2 && NumElems != 4)
3613 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3614 if (!isUndefOrEqual(Mask[i], i))
3617 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3618 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3625 // Some special combinations that can be optimized.
3628 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3629 SelectionDAG &DAG) {
3630 MVT VT = SVOp->getValueType(0).getSimpleVT();
3631 DebugLoc dl = SVOp->getDebugLoc();
3633 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3636 ArrayRef<int> Mask = SVOp->getMask();
3638 // These are the special masks that may be optimized.
3639 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3640 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3641 bool MatchEvenMask = true;
3642 bool MatchOddMask = true;
3643 for (int i=0; i<8; ++i) {
3644 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3645 MatchEvenMask = false;
3646 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3647 MatchOddMask = false;
3650 if (!MatchEvenMask && !MatchOddMask)
3653 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3655 SDValue Op0 = SVOp->getOperand(0);
3656 SDValue Op1 = SVOp->getOperand(1);
3658 if (MatchEvenMask) {
3659 // Shift the second operand right to 32 bits.
3660 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3661 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3663 // Shift the first operand left to 32 bits.
3664 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3665 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3667 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3668 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3671 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3672 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3673 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3674 bool HasInt256, bool V2IsSplat = false) {
3675 unsigned NumElts = VT.getVectorNumElements();
3677 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3678 "Unsupported vector type for unpckh");
3680 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3681 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3684 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3685 // independently on 128-bit lanes.
3686 unsigned NumLanes = VT.getSizeInBits()/128;
3687 unsigned NumLaneElts = NumElts/NumLanes;
3689 for (unsigned l = 0; l != NumLanes; ++l) {
3690 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3691 i != (l+1)*NumLaneElts;
3694 int BitI1 = Mask[i+1];
3695 if (!isUndefOrEqual(BitI, j))
3698 if (!isUndefOrEqual(BitI1, NumElts))
3701 if (!isUndefOrEqual(BitI1, j + NumElts))
3710 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3711 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3712 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3713 bool HasInt256, bool V2IsSplat = false) {
3714 unsigned NumElts = VT.getVectorNumElements();
3716 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3717 "Unsupported vector type for unpckh");
3719 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3720 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3723 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3724 // independently on 128-bit lanes.
3725 unsigned NumLanes = VT.getSizeInBits()/128;
3726 unsigned NumLaneElts = NumElts/NumLanes;
3728 for (unsigned l = 0; l != NumLanes; ++l) {
3729 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3730 i != (l+1)*NumLaneElts; i += 2, ++j) {
3732 int BitI1 = Mask[i+1];
3733 if (!isUndefOrEqual(BitI, j))
3736 if (isUndefOrEqual(BitI1, NumElts))
3739 if (!isUndefOrEqual(BitI1, j+NumElts))
3747 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3748 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3750 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3751 unsigned NumElts = VT.getVectorNumElements();
3752 bool Is256BitVec = VT.is256BitVector();
3754 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3755 "Unsupported vector type for unpckh");
3757 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3758 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3761 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3762 // FIXME: Need a better way to get rid of this, there's no latency difference
3763 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3764 // the former later. We should also remove the "_undef" special mask.
3765 if (NumElts == 4 && Is256BitVec)
3768 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3769 // independently on 128-bit lanes.
3770 unsigned NumLanes = VT.getSizeInBits()/128;
3771 unsigned NumLaneElts = NumElts/NumLanes;
3773 for (unsigned l = 0; l != NumLanes; ++l) {
3774 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3775 i != (l+1)*NumLaneElts;
3778 int BitI1 = Mask[i+1];
3780 if (!isUndefOrEqual(BitI, j))
3782 if (!isUndefOrEqual(BitI1, j))
3790 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3791 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3793 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3794 unsigned NumElts = VT.getVectorNumElements();
3796 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3797 "Unsupported vector type for unpckh");
3799 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3800 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3803 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3804 // independently on 128-bit lanes.
3805 unsigned NumLanes = VT.getSizeInBits()/128;
3806 unsigned NumLaneElts = NumElts/NumLanes;
3808 for (unsigned l = 0; l != NumLanes; ++l) {
3809 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3810 i != (l+1)*NumLaneElts; i += 2, ++j) {
3812 int BitI1 = Mask[i+1];
3813 if (!isUndefOrEqual(BitI, j))
3815 if (!isUndefOrEqual(BitI1, j))
3822 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3823 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3824 /// MOVSD, and MOVD, i.e. setting the lowest element.
3825 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3826 if (VT.getVectorElementType().getSizeInBits() < 32)
3828 if (!VT.is128BitVector())
3831 unsigned NumElts = VT.getVectorNumElements();
3833 if (!isUndefOrEqual(Mask[0], NumElts))
3836 for (unsigned i = 1; i != NumElts; ++i)
3837 if (!isUndefOrEqual(Mask[i], i))
3843 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3844 /// as permutations between 128-bit chunks or halves. As an example: this
3846 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3847 /// The first half comes from the second half of V1 and the second half from the
3848 /// the second half of V2.
3849 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3850 if (!HasFp256 || !VT.is256BitVector())
3853 // The shuffle result is divided into half A and half B. In total the two
3854 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3855 // B must come from C, D, E or F.
3856 unsigned HalfSize = VT.getVectorNumElements()/2;
3857 bool MatchA = false, MatchB = false;
3859 // Check if A comes from one of C, D, E, F.
3860 for (unsigned Half = 0; Half != 4; ++Half) {
3861 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3867 // Check if B comes from one of C, D, E, F.
3868 for (unsigned Half = 0; Half != 4; ++Half) {
3869 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3875 return MatchA && MatchB;
3878 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3879 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3880 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3881 MVT VT = SVOp->getValueType(0).getSimpleVT();
3883 unsigned HalfSize = VT.getVectorNumElements()/2;
3885 unsigned FstHalf = 0, SndHalf = 0;
3886 for (unsigned i = 0; i < HalfSize; ++i) {
3887 if (SVOp->getMaskElt(i) > 0) {
3888 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3892 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3893 if (SVOp->getMaskElt(i) > 0) {
3894 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3899 return (FstHalf | (SndHalf << 4));
3902 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3903 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3904 /// Note that VPERMIL mask matching is different depending whether theunderlying
3905 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3906 /// to the same elements of the low, but to the higher half of the source.
3907 /// In VPERMILPD the two lanes could be shuffled independently of each other
3908 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3909 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3913 unsigned NumElts = VT.getVectorNumElements();
3914 // Only match 256-bit with 32/64-bit types
3915 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
3918 unsigned NumLanes = VT.getSizeInBits()/128;
3919 unsigned LaneSize = NumElts/NumLanes;
3920 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3921 for (unsigned i = 0; i != LaneSize; ++i) {
3922 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3924 if (NumElts != 8 || l == 0)
3926 // VPERMILPS handling
3929 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3937 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3938 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3939 /// element of vector 2 and the other elements to come from vector 1 in order.
3940 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3941 bool V2IsSplat = false, bool V2IsUndef = false) {
3942 if (!VT.is128BitVector())
3945 unsigned NumOps = VT.getVectorNumElements();
3946 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3949 if (!isUndefOrEqual(Mask[0], 0))
3952 for (unsigned i = 1; i != NumOps; ++i)
3953 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3954 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3955 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3961 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3962 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3963 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3964 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3965 const X86Subtarget *Subtarget) {
3966 if (!Subtarget->hasSSE3())
3969 unsigned NumElems = VT.getVectorNumElements();
3971 if ((VT.is128BitVector() && NumElems != 4) ||
3972 (VT.is256BitVector() && NumElems != 8))
3975 // "i+1" is the value the indexed mask element must have
3976 for (unsigned i = 0; i != NumElems; i += 2)
3977 if (!isUndefOrEqual(Mask[i], i+1) ||
3978 !isUndefOrEqual(Mask[i+1], i+1))
3984 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3985 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3986 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3987 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3988 const X86Subtarget *Subtarget) {
3989 if (!Subtarget->hasSSE3())
3992 unsigned NumElems = VT.getVectorNumElements();
3994 if ((VT.is128BitVector() && NumElems != 4) ||
3995 (VT.is256BitVector() && NumElems != 8))
3998 // "i" is the value the indexed mask element must have
3999 for (unsigned i = 0; i != NumElems; i += 2)
4000 if (!isUndefOrEqual(Mask[i], i) ||
4001 !isUndefOrEqual(Mask[i+1], i))
4007 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4008 /// specifies a shuffle of elements that is suitable for input to 256-bit
4009 /// version of MOVDDUP.
4010 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
4011 if (!HasFp256 || !VT.is256BitVector())
4014 unsigned NumElts = VT.getVectorNumElements();
4018 for (unsigned i = 0; i != NumElts/2; ++i)
4019 if (!isUndefOrEqual(Mask[i], 0))
4021 for (unsigned i = NumElts/2; i != NumElts; ++i)
4022 if (!isUndefOrEqual(Mask[i], NumElts/2))
4027 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4028 /// specifies a shuffle of elements that is suitable for input to 128-bit
4029 /// version of MOVDDUP.
4030 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
4031 if (!VT.is128BitVector())
4034 unsigned e = VT.getVectorNumElements() / 2;
4035 for (unsigned i = 0; i != e; ++i)
4036 if (!isUndefOrEqual(Mask[i], i))
4038 for (unsigned i = 0; i != e; ++i)
4039 if (!isUndefOrEqual(Mask[e+i], i))
4044 /// isVEXTRACTF128Index - Return true if the specified
4045 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4046 /// suitable for input to VEXTRACTF128.
4047 bool X86::isVEXTRACTF128Index(SDNode *N) {
4048 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4051 // The index should be aligned on a 128-bit boundary.
4053 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4055 MVT VT = N->getValueType(0).getSimpleVT();
4056 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4057 bool Result = (Index * ElSize) % 128 == 0;
4062 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4063 /// operand specifies a subvector insert that is suitable for input to
4065 bool X86::isVINSERTF128Index(SDNode *N) {
4066 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4069 // The index should be aligned on a 128-bit boundary.
4071 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4073 MVT VT = N->getValueType(0).getSimpleVT();
4074 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4075 bool Result = (Index * ElSize) % 128 == 0;
4080 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4081 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4082 /// Handles 128-bit and 256-bit.
4083 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4084 MVT VT = N->getValueType(0).getSimpleVT();
4086 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4087 "Unsupported vector type for PSHUF/SHUFP");
4089 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4090 // independently on 128-bit lanes.
4091 unsigned NumElts = VT.getVectorNumElements();
4092 unsigned NumLanes = VT.getSizeInBits()/128;
4093 unsigned NumLaneElts = NumElts/NumLanes;
4095 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4096 "Only supports 2 or 4 elements per lane");
4098 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4100 for (unsigned i = 0; i != NumElts; ++i) {
4101 int Elt = N->getMaskElt(i);
4102 if (Elt < 0) continue;
4103 Elt &= NumLaneElts - 1;
4104 unsigned ShAmt = (i << Shift) % 8;
4105 Mask |= Elt << ShAmt;
4111 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4112 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4113 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4114 MVT VT = N->getValueType(0).getSimpleVT();
4116 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4117 "Unsupported vector type for PSHUFHW");
4119 unsigned NumElts = VT.getVectorNumElements();
4122 for (unsigned l = 0; l != NumElts; l += 8) {
4123 // 8 nodes per lane, but we only care about the last 4.
4124 for (unsigned i = 0; i < 4; ++i) {
4125 int Elt = N->getMaskElt(l+i+4);
4126 if (Elt < 0) continue;
4127 Elt &= 0x3; // only 2-bits.
4128 Mask |= Elt << (i * 2);
4135 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4136 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4137 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4138 MVT VT = N->getValueType(0).getSimpleVT();
4140 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4141 "Unsupported vector type for PSHUFHW");
4143 unsigned NumElts = VT.getVectorNumElements();
4146 for (unsigned l = 0; l != NumElts; l += 8) {
4147 // 8 nodes per lane, but we only care about the first 4.
4148 for (unsigned i = 0; i < 4; ++i) {
4149 int Elt = N->getMaskElt(l+i);
4150 if (Elt < 0) continue;
4151 Elt &= 0x3; // only 2-bits
4152 Mask |= Elt << (i * 2);
4159 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4160 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4161 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4162 MVT VT = SVOp->getValueType(0).getSimpleVT();
4163 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4165 unsigned NumElts = VT.getVectorNumElements();
4166 unsigned NumLanes = VT.getSizeInBits()/128;
4167 unsigned NumLaneElts = NumElts/NumLanes;
4171 for (i = 0; i != NumElts; ++i) {
4172 Val = SVOp->getMaskElt(i);
4176 if (Val >= (int)NumElts)
4177 Val -= NumElts - NumLaneElts;
4179 assert(Val - i > 0 && "PALIGNR imm should be positive");
4180 return (Val - i) * EltSize;
4183 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4184 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4186 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4187 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4188 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4191 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4193 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT();
4194 MVT ElVT = VecVT.getVectorElementType();
4196 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4197 return Index / NumElemsPerChunk;
4200 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4201 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4203 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4204 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4205 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4208 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4210 MVT VecVT = N->getValueType(0).getSimpleVT();
4211 MVT ElVT = VecVT.getVectorElementType();
4213 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4214 return Index / NumElemsPerChunk;
4217 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4218 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4219 /// Handles 256-bit.
4220 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4221 MVT VT = N->getValueType(0).getSimpleVT();
4223 unsigned NumElts = VT.getVectorNumElements();
4225 assert((VT.is256BitVector() && NumElts == 4) &&
4226 "Unsupported vector type for VPERMQ/VPERMPD");
4229 for (unsigned i = 0; i != NumElts; ++i) {
4230 int Elt = N->getMaskElt(i);
4233 Mask |= Elt << (i*2);
4238 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4240 bool X86::isZeroNode(SDValue Elt) {
4241 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4242 return CN->isNullValue();
4243 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4244 return CFP->getValueAPF().isPosZero();
4248 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4249 /// their permute mask.
4250 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4251 SelectionDAG &DAG) {
4252 MVT VT = SVOp->getValueType(0).getSimpleVT();
4253 unsigned NumElems = VT.getVectorNumElements();
4254 SmallVector<int, 8> MaskVec;
4256 for (unsigned i = 0; i != NumElems; ++i) {
4257 int Idx = SVOp->getMaskElt(i);
4259 if (Idx < (int)NumElems)
4264 MaskVec.push_back(Idx);
4266 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4267 SVOp->getOperand(0), &MaskVec[0]);
4270 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4271 /// match movhlps. The lower half elements should come from upper half of
4272 /// V1 (and in order), and the upper half elements should come from the upper
4273 /// half of V2 (and in order).
4274 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4275 if (!VT.is128BitVector())
4277 if (VT.getVectorNumElements() != 4)
4279 for (unsigned i = 0, e = 2; i != e; ++i)
4280 if (!isUndefOrEqual(Mask[i], i+2))
4282 for (unsigned i = 2; i != 4; ++i)
4283 if (!isUndefOrEqual(Mask[i], i+4))
4288 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4289 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4291 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4292 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4294 N = N->getOperand(0).getNode();
4295 if (!ISD::isNON_EXTLoad(N))
4298 *LD = cast<LoadSDNode>(N);
4302 // Test whether the given value is a vector value which will be legalized
4304 static bool WillBeConstantPoolLoad(SDNode *N) {
4305 if (N->getOpcode() != ISD::BUILD_VECTOR)
4308 // Check for any non-constant elements.
4309 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4310 switch (N->getOperand(i).getNode()->getOpcode()) {
4312 case ISD::ConstantFP:
4319 // Vectors of all-zeros and all-ones are materialized with special
4320 // instructions rather than being loaded.
4321 return !ISD::isBuildVectorAllZeros(N) &&
4322 !ISD::isBuildVectorAllOnes(N);
4325 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4326 /// match movlp{s|d}. The lower half elements should come from lower half of
4327 /// V1 (and in order), and the upper half elements should come from the upper
4328 /// half of V2 (and in order). And since V1 will become the source of the
4329 /// MOVLP, it must be either a vector load or a scalar load to vector.
4330 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4331 ArrayRef<int> Mask, EVT VT) {
4332 if (!VT.is128BitVector())
4335 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4337 // Is V2 is a vector load, don't do this transformation. We will try to use
4338 // load folding shufps op.
4339 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4342 unsigned NumElems = VT.getVectorNumElements();
4344 if (NumElems != 2 && NumElems != 4)
4346 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4347 if (!isUndefOrEqual(Mask[i], i))
4349 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4350 if (!isUndefOrEqual(Mask[i], i+NumElems))
4355 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4357 static bool isSplatVector(SDNode *N) {
4358 if (N->getOpcode() != ISD::BUILD_VECTOR)
4361 SDValue SplatValue = N->getOperand(0);
4362 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4363 if (N->getOperand(i) != SplatValue)
4368 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4369 /// to an zero vector.
4370 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4371 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4372 SDValue V1 = N->getOperand(0);
4373 SDValue V2 = N->getOperand(1);
4374 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4375 for (unsigned i = 0; i != NumElems; ++i) {
4376 int Idx = N->getMaskElt(i);
4377 if (Idx >= (int)NumElems) {
4378 unsigned Opc = V2.getOpcode();
4379 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4381 if (Opc != ISD::BUILD_VECTOR ||
4382 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4384 } else if (Idx >= 0) {
4385 unsigned Opc = V1.getOpcode();
4386 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4388 if (Opc != ISD::BUILD_VECTOR ||
4389 !X86::isZeroNode(V1.getOperand(Idx)))
4396 /// getZeroVector - Returns a vector of specified type with all zero elements.
4398 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4399 SelectionDAG &DAG, DebugLoc dl) {
4400 assert(VT.isVector() && "Expected a vector type");
4402 // Always build SSE zero vectors as <4 x i32> bitcasted
4403 // to their dest type. This ensures they get CSE'd.
4405 if (VT.is128BitVector()) { // SSE
4406 if (Subtarget->hasSSE2()) { // SSE2
4407 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4408 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4410 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4411 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4413 } else if (VT.is256BitVector()) { // AVX
4414 if (Subtarget->hasInt256()) { // AVX2
4415 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4416 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4417 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4418 array_lengthof(Ops));
4420 // 256-bit logic and arithmetic instructions in AVX are all
4421 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4422 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4423 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4424 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4425 array_lengthof(Ops));
4428 llvm_unreachable("Unexpected vector type");
4430 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4433 /// getOnesVector - Returns a vector of specified type with all bits set.
4434 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4435 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4436 /// Then bitcast to their original type, ensuring they get CSE'd.
4437 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4439 assert(VT.isVector() && "Expected a vector type");
4441 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4443 if (VT.is256BitVector()) {
4444 if (HasInt256) { // AVX2
4445 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4446 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4447 array_lengthof(Ops));
4449 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4450 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4452 } else if (VT.is128BitVector()) {
4453 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4455 llvm_unreachable("Unexpected vector type");
4457 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4460 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4461 /// that point to V2 points to its first element.
4462 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4463 for (unsigned i = 0; i != NumElems; ++i) {
4464 if (Mask[i] > (int)NumElems) {
4470 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4471 /// operation of specified width.
4472 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4474 unsigned NumElems = VT.getVectorNumElements();
4475 SmallVector<int, 8> Mask;
4476 Mask.push_back(NumElems);
4477 for (unsigned i = 1; i != NumElems; ++i)
4479 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4482 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4483 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4485 unsigned NumElems = VT.getVectorNumElements();
4486 SmallVector<int, 8> Mask;
4487 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4489 Mask.push_back(i + NumElems);
4491 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4494 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4495 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4497 unsigned NumElems = VT.getVectorNumElements();
4498 SmallVector<int, 8> Mask;
4499 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4500 Mask.push_back(i + Half);
4501 Mask.push_back(i + NumElems + Half);
4503 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4506 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4507 // a generic shuffle instruction because the target has no such instructions.
4508 // Generate shuffles which repeat i16 and i8 several times until they can be
4509 // represented by v4f32 and then be manipulated by target suported shuffles.
4510 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4511 EVT VT = V.getValueType();
4512 int NumElems = VT.getVectorNumElements();
4513 DebugLoc dl = V.getDebugLoc();
4515 while (NumElems > 4) {
4516 if (EltNo < NumElems/2) {
4517 V = getUnpackl(DAG, dl, VT, V, V);
4519 V = getUnpackh(DAG, dl, VT, V, V);
4520 EltNo -= NumElems/2;
4527 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4528 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4529 EVT VT = V.getValueType();
4530 DebugLoc dl = V.getDebugLoc();
4532 if (VT.is128BitVector()) {
4533 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4534 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4535 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4537 } else if (VT.is256BitVector()) {
4538 // To use VPERMILPS to splat scalars, the second half of indicies must
4539 // refer to the higher part, which is a duplication of the lower one,
4540 // because VPERMILPS can only handle in-lane permutations.
4541 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4542 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4544 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4545 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4548 llvm_unreachable("Vector size not supported");
4550 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4553 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4554 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4555 EVT SrcVT = SV->getValueType(0);
4556 SDValue V1 = SV->getOperand(0);
4557 DebugLoc dl = SV->getDebugLoc();
4559 int EltNo = SV->getSplatIndex();
4560 int NumElems = SrcVT.getVectorNumElements();
4561 bool Is256BitVec = SrcVT.is256BitVector();
4563 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4564 "Unknown how to promote splat for type");
4566 // Extract the 128-bit part containing the splat element and update
4567 // the splat element index when it refers to the higher register.
4569 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4570 if (EltNo >= NumElems/2)
4571 EltNo -= NumElems/2;
4574 // All i16 and i8 vector types can't be used directly by a generic shuffle
4575 // instruction because the target has no such instruction. Generate shuffles
4576 // which repeat i16 and i8 several times until they fit in i32, and then can
4577 // be manipulated by target suported shuffles.
4578 EVT EltVT = SrcVT.getVectorElementType();
4579 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4580 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4582 // Recreate the 256-bit vector and place the same 128-bit vector
4583 // into the low and high part. This is necessary because we want
4584 // to use VPERM* to shuffle the vectors
4586 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4589 return getLegalSplat(DAG, V1, EltNo);
4592 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4593 /// vector of zero or undef vector. This produces a shuffle where the low
4594 /// element of V2 is swizzled into the zero/undef vector, landing at element
4595 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4596 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4598 const X86Subtarget *Subtarget,
4599 SelectionDAG &DAG) {
4600 EVT VT = V2.getValueType();
4602 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4603 unsigned NumElems = VT.getVectorNumElements();
4604 SmallVector<int, 16> MaskVec;
4605 for (unsigned i = 0; i != NumElems; ++i)
4606 // If this is the insertion idx, put the low elt of V2 here.
4607 MaskVec.push_back(i == Idx ? NumElems : i);
4608 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4611 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4612 /// target specific opcode. Returns true if the Mask could be calculated.
4613 /// Sets IsUnary to true if only uses one source.
4614 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4615 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4616 unsigned NumElems = VT.getVectorNumElements();
4620 switch(N->getOpcode()) {
4622 ImmN = N->getOperand(N->getNumOperands()-1);
4623 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4625 case X86ISD::UNPCKH:
4626 DecodeUNPCKHMask(VT, Mask);
4628 case X86ISD::UNPCKL:
4629 DecodeUNPCKLMask(VT, Mask);
4631 case X86ISD::MOVHLPS:
4632 DecodeMOVHLPSMask(NumElems, Mask);
4634 case X86ISD::MOVLHPS:
4635 DecodeMOVLHPSMask(NumElems, Mask);
4637 case X86ISD::PALIGNR:
4638 ImmN = N->getOperand(N->getNumOperands()-1);
4639 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4641 case X86ISD::PSHUFD:
4642 case X86ISD::VPERMILP:
4643 ImmN = N->getOperand(N->getNumOperands()-1);
4644 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4647 case X86ISD::PSHUFHW:
4648 ImmN = N->getOperand(N->getNumOperands()-1);
4649 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4652 case X86ISD::PSHUFLW:
4653 ImmN = N->getOperand(N->getNumOperands()-1);
4654 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4657 case X86ISD::VPERMI:
4658 ImmN = N->getOperand(N->getNumOperands()-1);
4659 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4663 case X86ISD::MOVSD: {
4664 // The index 0 always comes from the first element of the second source,
4665 // this is why MOVSS and MOVSD are used in the first place. The other
4666 // elements come from the other positions of the first source vector
4667 Mask.push_back(NumElems);
4668 for (unsigned i = 1; i != NumElems; ++i) {
4673 case X86ISD::VPERM2X128:
4674 ImmN = N->getOperand(N->getNumOperands()-1);
4675 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4676 if (Mask.empty()) return false;
4678 case X86ISD::MOVDDUP:
4679 case X86ISD::MOVLHPD:
4680 case X86ISD::MOVLPD:
4681 case X86ISD::MOVLPS:
4682 case X86ISD::MOVSHDUP:
4683 case X86ISD::MOVSLDUP:
4684 // Not yet implemented
4686 default: llvm_unreachable("unknown target shuffle node");
4692 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4693 /// element of the result of the vector shuffle.
4694 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4697 return SDValue(); // Limit search depth.
4699 SDValue V = SDValue(N, 0);
4700 EVT VT = V.getValueType();
4701 unsigned Opcode = V.getOpcode();
4703 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4704 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4705 int Elt = SV->getMaskElt(Index);
4708 return DAG.getUNDEF(VT.getVectorElementType());
4710 unsigned NumElems = VT.getVectorNumElements();
4711 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4712 : SV->getOperand(1);
4713 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4716 // Recurse into target specific vector shuffles to find scalars.
4717 if (isTargetShuffle(Opcode)) {
4718 MVT ShufVT = V.getValueType().getSimpleVT();
4719 unsigned NumElems = ShufVT.getVectorNumElements();
4720 SmallVector<int, 16> ShuffleMask;
4723 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4726 int Elt = ShuffleMask[Index];
4728 return DAG.getUNDEF(ShufVT.getVectorElementType());
4730 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4732 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4736 // Actual nodes that may contain scalar elements
4737 if (Opcode == ISD::BITCAST) {
4738 V = V.getOperand(0);
4739 EVT SrcVT = V.getValueType();
4740 unsigned NumElems = VT.getVectorNumElements();
4742 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4746 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4747 return (Index == 0) ? V.getOperand(0)
4748 : DAG.getUNDEF(VT.getVectorElementType());
4750 if (V.getOpcode() == ISD::BUILD_VECTOR)
4751 return V.getOperand(Index);
4756 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4757 /// shuffle operation which come from a consecutively from a zero. The
4758 /// search can start in two different directions, from left or right.
4760 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4761 bool ZerosFromLeft, SelectionDAG &DAG) {
4763 for (i = 0; i != NumElems; ++i) {
4764 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4765 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4766 if (!(Elt.getNode() &&
4767 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4774 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4775 /// correspond consecutively to elements from one of the vector operands,
4776 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4778 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4779 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4780 unsigned NumElems, unsigned &OpNum) {
4781 bool SeenV1 = false;
4782 bool SeenV2 = false;
4784 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4785 int Idx = SVOp->getMaskElt(i);
4786 // Ignore undef indicies
4790 if (Idx < (int)NumElems)
4795 // Only accept consecutive elements from the same vector
4796 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4800 OpNum = SeenV1 ? 0 : 1;
4804 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4805 /// logical left shift of a vector.
4806 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4807 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4808 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4809 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4810 false /* check zeros from right */, DAG);
4816 // Considering the elements in the mask that are not consecutive zeros,
4817 // check if they consecutively come from only one of the source vectors.
4819 // V1 = {X, A, B, C} 0
4821 // vector_shuffle V1, V2 <1, 2, 3, X>
4823 if (!isShuffleMaskConsecutive(SVOp,
4824 0, // Mask Start Index
4825 NumElems-NumZeros, // Mask End Index(exclusive)
4826 NumZeros, // Where to start looking in the src vector
4827 NumElems, // Number of elements in vector
4828 OpSrc)) // Which source operand ?
4833 ShVal = SVOp->getOperand(OpSrc);
4837 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4838 /// logical left shift of a vector.
4839 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4840 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4841 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4842 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4843 true /* check zeros from left */, DAG);
4849 // Considering the elements in the mask that are not consecutive zeros,
4850 // check if they consecutively come from only one of the source vectors.
4852 // 0 { A, B, X, X } = V2
4854 // vector_shuffle V1, V2 <X, X, 4, 5>
4856 if (!isShuffleMaskConsecutive(SVOp,
4857 NumZeros, // Mask Start Index
4858 NumElems, // Mask End Index(exclusive)
4859 0, // Where to start looking in the src vector
4860 NumElems, // Number of elements in vector
4861 OpSrc)) // Which source operand ?
4866 ShVal = SVOp->getOperand(OpSrc);
4870 /// isVectorShift - Returns true if the shuffle can be implemented as a
4871 /// logical left or right shift of a vector.
4872 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4873 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4874 // Although the logic below support any bitwidth size, there are no
4875 // shift instructions which handle more than 128-bit vectors.
4876 if (!SVOp->getValueType(0).is128BitVector())
4879 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4880 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4886 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4888 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4889 unsigned NumNonZero, unsigned NumZero,
4891 const X86Subtarget* Subtarget,
4892 const TargetLowering &TLI) {
4896 DebugLoc dl = Op.getDebugLoc();
4899 for (unsigned i = 0; i < 16; ++i) {
4900 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4901 if (ThisIsNonZero && First) {
4903 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4905 V = DAG.getUNDEF(MVT::v8i16);
4910 SDValue ThisElt(0, 0), LastElt(0, 0);
4911 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4912 if (LastIsNonZero) {
4913 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4914 MVT::i16, Op.getOperand(i-1));
4916 if (ThisIsNonZero) {
4917 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4918 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4919 ThisElt, DAG.getConstant(8, MVT::i8));
4921 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4925 if (ThisElt.getNode())
4926 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4927 DAG.getIntPtrConstant(i/2));
4931 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4934 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4936 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4937 unsigned NumNonZero, unsigned NumZero,
4939 const X86Subtarget* Subtarget,
4940 const TargetLowering &TLI) {
4944 DebugLoc dl = Op.getDebugLoc();
4947 for (unsigned i = 0; i < 8; ++i) {
4948 bool isNonZero = (NonZeros & (1 << i)) != 0;
4952 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4954 V = DAG.getUNDEF(MVT::v8i16);
4957 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4958 MVT::v8i16, V, Op.getOperand(i),
4959 DAG.getIntPtrConstant(i));
4966 /// getVShift - Return a vector logical shift node.
4968 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4969 unsigned NumBits, SelectionDAG &DAG,
4970 const TargetLowering &TLI, DebugLoc dl) {
4971 assert(VT.is128BitVector() && "Unknown type for VShift");
4972 EVT ShVT = MVT::v2i64;
4973 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4974 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4975 return DAG.getNode(ISD::BITCAST, dl, VT,
4976 DAG.getNode(Opc, dl, ShVT, SrcOp,
4977 DAG.getConstant(NumBits,
4978 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
4982 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4983 SelectionDAG &DAG) const {
4985 // Check if the scalar load can be widened into a vector load. And if
4986 // the address is "base + cst" see if the cst can be "absorbed" into
4987 // the shuffle mask.
4988 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4989 SDValue Ptr = LD->getBasePtr();
4990 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4992 EVT PVT = LD->getValueType(0);
4993 if (PVT != MVT::i32 && PVT != MVT::f32)
4998 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4999 FI = FINode->getIndex();
5001 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5002 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5003 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5004 Offset = Ptr.getConstantOperandVal(1);
5005 Ptr = Ptr.getOperand(0);
5010 // FIXME: 256-bit vector instructions don't require a strict alignment,
5011 // improve this code to support it better.
5012 unsigned RequiredAlign = VT.getSizeInBits()/8;
5013 SDValue Chain = LD->getChain();
5014 // Make sure the stack object alignment is at least 16 or 32.
5015 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5016 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5017 if (MFI->isFixedObjectIndex(FI)) {
5018 // Can't change the alignment. FIXME: It's possible to compute
5019 // the exact stack offset and reference FI + adjust offset instead.
5020 // If someone *really* cares about this. That's the way to implement it.
5023 MFI->setObjectAlignment(FI, RequiredAlign);
5027 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5028 // Ptr + (Offset & ~15).
5031 if ((Offset % RequiredAlign) & 3)
5033 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5035 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
5036 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5038 int EltNo = (Offset - StartOffset) >> 2;
5039 unsigned NumElems = VT.getVectorNumElements();
5041 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5042 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5043 LD->getPointerInfo().getWithOffset(StartOffset),
5044 false, false, false, 0);
5046 SmallVector<int, 8> Mask;
5047 for (unsigned i = 0; i != NumElems; ++i)
5048 Mask.push_back(EltNo);
5050 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5056 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5057 /// vector of type 'VT', see if the elements can be replaced by a single large
5058 /// load which has the same value as a build_vector whose operands are 'elts'.
5060 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5062 /// FIXME: we'd also like to handle the case where the last elements are zero
5063 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5064 /// There's even a handy isZeroNode for that purpose.
5065 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5066 DebugLoc &DL, SelectionDAG &DAG) {
5067 EVT EltVT = VT.getVectorElementType();
5068 unsigned NumElems = Elts.size();
5070 LoadSDNode *LDBase = NULL;
5071 unsigned LastLoadedElt = -1U;
5073 // For each element in the initializer, see if we've found a load or an undef.
5074 // If we don't find an initial load element, or later load elements are
5075 // non-consecutive, bail out.
5076 for (unsigned i = 0; i < NumElems; ++i) {
5077 SDValue Elt = Elts[i];
5079 if (!Elt.getNode() ||
5080 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5083 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5085 LDBase = cast<LoadSDNode>(Elt.getNode());
5089 if (Elt.getOpcode() == ISD::UNDEF)
5092 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5093 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5098 // If we have found an entire vector of loads and undefs, then return a large
5099 // load of the entire vector width starting at the base pointer. If we found
5100 // consecutive loads for the low half, generate a vzext_load node.
5101 if (LastLoadedElt == NumElems - 1) {
5102 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5103 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5104 LDBase->getPointerInfo(),
5105 LDBase->isVolatile(), LDBase->isNonTemporal(),
5106 LDBase->isInvariant(), 0);
5107 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5108 LDBase->getPointerInfo(),
5109 LDBase->isVolatile(), LDBase->isNonTemporal(),
5110 LDBase->isInvariant(), LDBase->getAlignment());
5112 if (NumElems == 4 && LastLoadedElt == 1 &&
5113 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5114 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5115 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5117 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5118 array_lengthof(Ops), MVT::i64,
5119 LDBase->getPointerInfo(),
5120 LDBase->getAlignment(),
5121 false/*isVolatile*/, true/*ReadMem*/,
5124 // Make sure the newly-created LOAD is in the same position as LDBase in
5125 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5126 // update uses of LDBase's output chain to use the TokenFactor.
5127 if (LDBase->hasAnyUseOfValue(1)) {
5128 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5129 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5130 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5131 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5132 SDValue(ResNode.getNode(), 1));
5135 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5140 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5141 /// to generate a splat value for the following cases:
5142 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5143 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5144 /// a scalar load, or a constant.
5145 /// The VBROADCAST node is returned when a pattern is found,
5146 /// or SDValue() otherwise.
5148 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5149 if (!Subtarget->hasFp256())
5152 MVT VT = Op.getValueType().getSimpleVT();
5153 DebugLoc dl = Op.getDebugLoc();
5155 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5156 "Unsupported vector type for broadcast.");
5161 switch (Op.getOpcode()) {
5163 // Unknown pattern found.
5166 case ISD::BUILD_VECTOR: {
5167 // The BUILD_VECTOR node must be a splat.
5168 if (!isSplatVector(Op.getNode()))
5171 Ld = Op.getOperand(0);
5172 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5173 Ld.getOpcode() == ISD::ConstantFP);
5175 // The suspected load node has several users. Make sure that all
5176 // of its users are from the BUILD_VECTOR node.
5177 // Constants may have multiple users.
5178 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5183 case ISD::VECTOR_SHUFFLE: {
5184 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5186 // Shuffles must have a splat mask where the first element is
5188 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5191 SDValue Sc = Op.getOperand(0);
5192 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5193 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5195 if (!Subtarget->hasInt256())
5198 // Use the register form of the broadcast instruction available on AVX2.
5199 if (VT.is256BitVector())
5200 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5201 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5204 Ld = Sc.getOperand(0);
5205 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5206 Ld.getOpcode() == ISD::ConstantFP);
5208 // The scalar_to_vector node and the suspected
5209 // load node must have exactly one user.
5210 // Constants may have multiple users.
5211 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5217 bool Is256 = VT.is256BitVector();
5219 // Handle the broadcasting a single constant scalar from the constant pool
5220 // into a vector. On Sandybridge it is still better to load a constant vector
5221 // from the constant pool and not to broadcast it from a scalar.
5222 if (ConstSplatVal && Subtarget->hasInt256()) {
5223 EVT CVT = Ld.getValueType();
5224 assert(!CVT.isVector() && "Must not broadcast a vector type");
5225 unsigned ScalarSize = CVT.getSizeInBits();
5227 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5228 const Constant *C = 0;
5229 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5230 C = CI->getConstantIntValue();
5231 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5232 C = CF->getConstantFPValue();
5234 assert(C && "Invalid constant type");
5236 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5237 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5238 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5239 MachinePointerInfo::getConstantPool(),
5240 false, false, false, Alignment);
5242 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5246 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5247 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5249 // Handle AVX2 in-register broadcasts.
5250 if (!IsLoad && Subtarget->hasInt256() &&
5251 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5252 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5254 // The scalar source must be a normal load.
5258 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5259 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5261 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5262 // double since there is no vbroadcastsd xmm
5263 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5264 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5265 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5268 // Unsupported broadcast.
5273 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5274 EVT VT = Op.getValueType();
5276 // Skip if insert_vec_elt is not supported.
5277 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5280 DebugLoc DL = Op.getDebugLoc();
5281 unsigned NumElems = Op.getNumOperands();
5285 SmallVector<unsigned, 4> InsertIndices;
5286 SmallVector<int, 8> Mask(NumElems, -1);
5288 for (unsigned i = 0; i != NumElems; ++i) {
5289 unsigned Opc = Op.getOperand(i).getOpcode();
5291 if (Opc == ISD::UNDEF)
5294 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5295 // Quit if more than 1 elements need inserting.
5296 if (InsertIndices.size() > 1)
5299 InsertIndices.push_back(i);
5303 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5304 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5306 // Quit if extracted from vector of different type.
5307 if (ExtractedFromVec.getValueType() != VT)
5310 // Quit if non-constant index.
5311 if (!isa<ConstantSDNode>(ExtIdx))
5314 if (VecIn1.getNode() == 0)
5315 VecIn1 = ExtractedFromVec;
5316 else if (VecIn1 != ExtractedFromVec) {
5317 if (VecIn2.getNode() == 0)
5318 VecIn2 = ExtractedFromVec;
5319 else if (VecIn2 != ExtractedFromVec)
5320 // Quit if more than 2 vectors to shuffle
5324 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5326 if (ExtractedFromVec == VecIn1)
5328 else if (ExtractedFromVec == VecIn2)
5329 Mask[i] = Idx + NumElems;
5332 if (VecIn1.getNode() == 0)
5335 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5336 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5337 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5338 unsigned Idx = InsertIndices[i];
5339 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5340 DAG.getIntPtrConstant(Idx));
5347 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5348 DebugLoc dl = Op.getDebugLoc();
5350 MVT VT = Op.getValueType().getSimpleVT();
5351 MVT ExtVT = VT.getVectorElementType();
5352 unsigned NumElems = Op.getNumOperands();
5354 // Vectors containing all zeros can be matched by pxor and xorps later
5355 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5356 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5357 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5358 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5361 return getZeroVector(VT, Subtarget, DAG, dl);
5364 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5365 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5366 // vpcmpeqd on 256-bit vectors.
5367 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5368 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5371 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5374 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5375 if (Broadcast.getNode())
5378 unsigned EVTBits = ExtVT.getSizeInBits();
5380 unsigned NumZero = 0;
5381 unsigned NumNonZero = 0;
5382 unsigned NonZeros = 0;
5383 bool IsAllConstants = true;
5384 SmallSet<SDValue, 8> Values;
5385 for (unsigned i = 0; i < NumElems; ++i) {
5386 SDValue Elt = Op.getOperand(i);
5387 if (Elt.getOpcode() == ISD::UNDEF)
5390 if (Elt.getOpcode() != ISD::Constant &&
5391 Elt.getOpcode() != ISD::ConstantFP)
5392 IsAllConstants = false;
5393 if (X86::isZeroNode(Elt))
5396 NonZeros |= (1 << i);
5401 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5402 if (NumNonZero == 0)
5403 return DAG.getUNDEF(VT);
5405 // Special case for single non-zero, non-undef, element.
5406 if (NumNonZero == 1) {
5407 unsigned Idx = CountTrailingZeros_32(NonZeros);
5408 SDValue Item = Op.getOperand(Idx);
5410 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5411 // the value are obviously zero, truncate the value to i32 and do the
5412 // insertion that way. Only do this if the value is non-constant or if the
5413 // value is a constant being inserted into element 0. It is cheaper to do
5414 // a constant pool load than it is to do a movd + shuffle.
5415 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5416 (!IsAllConstants || Idx == 0)) {
5417 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5419 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5420 EVT VecVT = MVT::v4i32;
5421 unsigned VecElts = 4;
5423 // Truncate the value (which may itself be a constant) to i32, and
5424 // convert it to a vector with movd (S2V+shuffle to zero extend).
5425 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5426 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5427 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5429 // Now we have our 32-bit value zero extended in the low element of
5430 // a vector. If Idx != 0, swizzle it into place.
5432 SmallVector<int, 4> Mask;
5433 Mask.push_back(Idx);
5434 for (unsigned i = 1; i != VecElts; ++i)
5436 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5439 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5443 // If we have a constant or non-constant insertion into the low element of
5444 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5445 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5446 // depending on what the source datatype is.
5449 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5451 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5452 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5453 if (VT.is256BitVector()) {
5454 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5455 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5456 Item, DAG.getIntPtrConstant(0));
5458 assert(VT.is128BitVector() && "Expected an SSE value type!");
5459 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5460 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5461 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5464 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5465 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5466 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5467 if (VT.is256BitVector()) {
5468 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5469 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5471 assert(VT.is128BitVector() && "Expected an SSE value type!");
5472 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5474 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5478 // Is it a vector logical left shift?
5479 if (NumElems == 2 && Idx == 1 &&
5480 X86::isZeroNode(Op.getOperand(0)) &&
5481 !X86::isZeroNode(Op.getOperand(1))) {
5482 unsigned NumBits = VT.getSizeInBits();
5483 return getVShift(true, VT,
5484 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5485 VT, Op.getOperand(1)),
5486 NumBits/2, DAG, *this, dl);
5489 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5492 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5493 // is a non-constant being inserted into an element other than the low one,
5494 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5495 // movd/movss) to move this into the low element, then shuffle it into
5497 if (EVTBits == 32) {
5498 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5500 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5501 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5502 SmallVector<int, 8> MaskVec;
5503 for (unsigned i = 0; i != NumElems; ++i)
5504 MaskVec.push_back(i == Idx ? 0 : 1);
5505 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5509 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5510 if (Values.size() == 1) {
5511 if (EVTBits == 32) {
5512 // Instead of a shuffle like this:
5513 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5514 // Check if it's possible to issue this instead.
5515 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5516 unsigned Idx = CountTrailingZeros_32(NonZeros);
5517 SDValue Item = Op.getOperand(Idx);
5518 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5519 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5524 // A vector full of immediates; various special cases are already
5525 // handled, so this is best done with a single constant-pool load.
5529 // For AVX-length vectors, build the individual 128-bit pieces and use
5530 // shuffles to put them in place.
5531 if (VT.is256BitVector()) {
5532 SmallVector<SDValue, 32> V;
5533 for (unsigned i = 0; i != NumElems; ++i)
5534 V.push_back(Op.getOperand(i));
5536 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5538 // Build both the lower and upper subvector.
5539 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5540 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5543 // Recreate the wider vector with the lower and upper part.
5544 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5547 // Let legalizer expand 2-wide build_vectors.
5548 if (EVTBits == 64) {
5549 if (NumNonZero == 1) {
5550 // One half is zero or undef.
5551 unsigned Idx = CountTrailingZeros_32(NonZeros);
5552 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5553 Op.getOperand(Idx));
5554 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5559 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5560 if (EVTBits == 8 && NumElems == 16) {
5561 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5563 if (V.getNode()) return V;
5566 if (EVTBits == 16 && NumElems == 8) {
5567 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5569 if (V.getNode()) return V;
5572 // If element VT is == 32 bits, turn it into a number of shuffles.
5573 SmallVector<SDValue, 8> V(NumElems);
5574 if (NumElems == 4 && NumZero > 0) {
5575 for (unsigned i = 0; i < 4; ++i) {
5576 bool isZero = !(NonZeros & (1 << i));
5578 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5580 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5583 for (unsigned i = 0; i < 2; ++i) {
5584 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5587 V[i] = V[i*2]; // Must be a zero vector.
5590 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5593 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5596 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5601 bool Reverse1 = (NonZeros & 0x3) == 2;
5602 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5606 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5607 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5609 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5612 if (Values.size() > 1 && VT.is128BitVector()) {
5613 // Check for a build vector of consecutive loads.
5614 for (unsigned i = 0; i < NumElems; ++i)
5615 V[i] = Op.getOperand(i);
5617 // Check for elements which are consecutive loads.
5618 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5622 // Check for a build vector from mostly shuffle plus few inserting.
5623 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5627 // For SSE 4.1, use insertps to put the high elements into the low element.
5628 if (getSubtarget()->hasSSE41()) {
5630 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5631 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5633 Result = DAG.getUNDEF(VT);
5635 for (unsigned i = 1; i < NumElems; ++i) {
5636 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5637 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5638 Op.getOperand(i), DAG.getIntPtrConstant(i));
5643 // Otherwise, expand into a number of unpckl*, start by extending each of
5644 // our (non-undef) elements to the full vector width with the element in the
5645 // bottom slot of the vector (which generates no code for SSE).
5646 for (unsigned i = 0; i < NumElems; ++i) {
5647 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5648 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5650 V[i] = DAG.getUNDEF(VT);
5653 // Next, we iteratively mix elements, e.g. for v4f32:
5654 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5655 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5656 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5657 unsigned EltStride = NumElems >> 1;
5658 while (EltStride != 0) {
5659 for (unsigned i = 0; i < EltStride; ++i) {
5660 // If V[i+EltStride] is undef and this is the first round of mixing,
5661 // then it is safe to just drop this shuffle: V[i] is already in the
5662 // right place, the one element (since it's the first round) being
5663 // inserted as undef can be dropped. This isn't safe for successive
5664 // rounds because they will permute elements within both vectors.
5665 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5666 EltStride == NumElems/2)
5669 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5678 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5679 // to create 256-bit vectors from two other 128-bit ones.
5680 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5681 DebugLoc dl = Op.getDebugLoc();
5682 MVT ResVT = Op.getValueType().getSimpleVT();
5684 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5686 SDValue V1 = Op.getOperand(0);
5687 SDValue V2 = Op.getOperand(1);
5688 unsigned NumElems = ResVT.getVectorNumElements();
5690 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5693 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5694 assert(Op.getNumOperands() == 2);
5696 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5697 // from two other 128-bit ones.
5698 return LowerAVXCONCAT_VECTORS(Op, DAG);
5701 // Try to lower a shuffle node into a simple blend instruction.
5703 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5704 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5705 SDValue V1 = SVOp->getOperand(0);
5706 SDValue V2 = SVOp->getOperand(1);
5707 DebugLoc dl = SVOp->getDebugLoc();
5708 MVT VT = SVOp->getValueType(0).getSimpleVT();
5709 MVT EltVT = VT.getVectorElementType();
5710 unsigned NumElems = VT.getVectorNumElements();
5712 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5714 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5717 // Check the mask for BLEND and build the value.
5718 unsigned MaskValue = 0;
5719 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5720 unsigned NumLanes = (NumElems-1)/8 + 1;
5721 unsigned NumElemsInLane = NumElems / NumLanes;
5723 // Blend for v16i16 should be symetric for the both lanes.
5724 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5726 int SndLaneEltIdx = (NumLanes == 2) ?
5727 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5728 int EltIdx = SVOp->getMaskElt(i);
5730 if ((EltIdx < 0 || EltIdx == (int)i) &&
5731 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5734 if (((unsigned)EltIdx == (i + NumElems)) &&
5735 (SndLaneEltIdx < 0 ||
5736 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
5737 MaskValue |= (1<<i);
5742 // Convert i32 vectors to floating point if it is not AVX2.
5743 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
5745 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
5746 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
5748 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5749 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5752 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
5753 DAG.getConstant(MaskValue, MVT::i32));
5754 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5757 // v8i16 shuffles - Prefer shuffles in the following order:
5758 // 1. [all] pshuflw, pshufhw, optional move
5759 // 2. [ssse3] 1 x pshufb
5760 // 3. [ssse3] 2 x pshufb + 1 x por
5761 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5763 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
5764 SelectionDAG &DAG) {
5765 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5766 SDValue V1 = SVOp->getOperand(0);
5767 SDValue V2 = SVOp->getOperand(1);
5768 DebugLoc dl = SVOp->getDebugLoc();
5769 SmallVector<int, 8> MaskVals;
5771 // Determine if more than 1 of the words in each of the low and high quadwords
5772 // of the result come from the same quadword of one of the two inputs. Undef
5773 // mask values count as coming from any quadword, for better codegen.
5774 unsigned LoQuad[] = { 0, 0, 0, 0 };
5775 unsigned HiQuad[] = { 0, 0, 0, 0 };
5776 std::bitset<4> InputQuads;
5777 for (unsigned i = 0; i < 8; ++i) {
5778 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5779 int EltIdx = SVOp->getMaskElt(i);
5780 MaskVals.push_back(EltIdx);
5789 InputQuads.set(EltIdx / 4);
5792 int BestLoQuad = -1;
5793 unsigned MaxQuad = 1;
5794 for (unsigned i = 0; i < 4; ++i) {
5795 if (LoQuad[i] > MaxQuad) {
5797 MaxQuad = LoQuad[i];
5801 int BestHiQuad = -1;
5803 for (unsigned i = 0; i < 4; ++i) {
5804 if (HiQuad[i] > MaxQuad) {
5806 MaxQuad = HiQuad[i];
5810 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5811 // of the two input vectors, shuffle them into one input vector so only a
5812 // single pshufb instruction is necessary. If There are more than 2 input
5813 // quads, disable the next transformation since it does not help SSSE3.
5814 bool V1Used = InputQuads[0] || InputQuads[1];
5815 bool V2Used = InputQuads[2] || InputQuads[3];
5816 if (Subtarget->hasSSSE3()) {
5817 if (InputQuads.count() == 2 && V1Used && V2Used) {
5818 BestLoQuad = InputQuads[0] ? 0 : 1;
5819 BestHiQuad = InputQuads[2] ? 2 : 3;
5821 if (InputQuads.count() > 2) {
5827 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5828 // the shuffle mask. If a quad is scored as -1, that means that it contains
5829 // words from all 4 input quadwords.
5831 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5833 BestLoQuad < 0 ? 0 : BestLoQuad,
5834 BestHiQuad < 0 ? 1 : BestHiQuad
5836 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5837 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5838 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5839 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5841 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5842 // source words for the shuffle, to aid later transformations.
5843 bool AllWordsInNewV = true;
5844 bool InOrder[2] = { true, true };
5845 for (unsigned i = 0; i != 8; ++i) {
5846 int idx = MaskVals[i];
5848 InOrder[i/4] = false;
5849 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5851 AllWordsInNewV = false;
5855 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5856 if (AllWordsInNewV) {
5857 for (int i = 0; i != 8; ++i) {
5858 int idx = MaskVals[i];
5861 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5862 if ((idx != i) && idx < 4)
5864 if ((idx != i) && idx > 3)
5873 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5874 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5875 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5876 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5877 unsigned TargetMask = 0;
5878 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5879 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5880 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5881 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5882 getShufflePSHUFLWImmediate(SVOp);
5883 V1 = NewV.getOperand(0);
5884 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5888 // Promote splats to a larger type which usually leads to more efficient code.
5889 // FIXME: Is this true if pshufb is available?
5890 if (SVOp->isSplat())
5891 return PromoteSplat(SVOp, DAG);
5893 // If we have SSSE3, and all words of the result are from 1 input vector,
5894 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5895 // is present, fall back to case 4.
5896 if (Subtarget->hasSSSE3()) {
5897 SmallVector<SDValue,16> pshufbMask;
5899 // If we have elements from both input vectors, set the high bit of the
5900 // shuffle mask element to zero out elements that come from V2 in the V1
5901 // mask, and elements that come from V1 in the V2 mask, so that the two
5902 // results can be OR'd together.
5903 bool TwoInputs = V1Used && V2Used;
5904 for (unsigned i = 0; i != 8; ++i) {
5905 int EltIdx = MaskVals[i] * 2;
5906 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5907 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5908 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5909 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5911 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5912 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5913 DAG.getNode(ISD::BUILD_VECTOR, dl,
5914 MVT::v16i8, &pshufbMask[0], 16));
5916 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5918 // Calculate the shuffle mask for the second input, shuffle it, and
5919 // OR it with the first shuffled input.
5921 for (unsigned i = 0; i != 8; ++i) {
5922 int EltIdx = MaskVals[i] * 2;
5923 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5924 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5925 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5926 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5928 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5929 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5930 DAG.getNode(ISD::BUILD_VECTOR, dl,
5931 MVT::v16i8, &pshufbMask[0], 16));
5932 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5933 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5936 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5937 // and update MaskVals with new element order.
5938 std::bitset<8> InOrder;
5939 if (BestLoQuad >= 0) {
5940 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5941 for (int i = 0; i != 4; ++i) {
5942 int idx = MaskVals[i];
5945 } else if ((idx / 4) == BestLoQuad) {
5950 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5953 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5954 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5955 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5957 getShufflePSHUFLWImmediate(SVOp), DAG);
5961 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5962 // and update MaskVals with the new element order.
5963 if (BestHiQuad >= 0) {
5964 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5965 for (unsigned i = 4; i != 8; ++i) {
5966 int idx = MaskVals[i];
5969 } else if ((idx / 4) == BestHiQuad) {
5970 MaskV[i] = (idx & 3) + 4;
5974 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5977 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5978 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5979 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5981 getShufflePSHUFHWImmediate(SVOp), DAG);
5985 // In case BestHi & BestLo were both -1, which means each quadword has a word
5986 // from each of the four input quadwords, calculate the InOrder bitvector now
5987 // before falling through to the insert/extract cleanup.
5988 if (BestLoQuad == -1 && BestHiQuad == -1) {
5990 for (int i = 0; i != 8; ++i)
5991 if (MaskVals[i] < 0 || MaskVals[i] == i)
5995 // The other elements are put in the right place using pextrw and pinsrw.
5996 for (unsigned i = 0; i != 8; ++i) {
5999 int EltIdx = MaskVals[i];
6002 SDValue ExtOp = (EltIdx < 8) ?
6003 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6004 DAG.getIntPtrConstant(EltIdx)) :
6005 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6006 DAG.getIntPtrConstant(EltIdx - 8));
6007 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6008 DAG.getIntPtrConstant(i));
6013 // v16i8 shuffles - Prefer shuffles in the following order:
6014 // 1. [ssse3] 1 x pshufb
6015 // 2. [ssse3] 2 x pshufb + 1 x por
6016 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6018 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6020 const X86TargetLowering &TLI) {
6021 SDValue V1 = SVOp->getOperand(0);
6022 SDValue V2 = SVOp->getOperand(1);
6023 DebugLoc dl = SVOp->getDebugLoc();
6024 ArrayRef<int> MaskVals = SVOp->getMask();
6026 // Promote splats to a larger type which usually leads to more efficient code.
6027 // FIXME: Is this true if pshufb is available?
6028 if (SVOp->isSplat())
6029 return PromoteSplat(SVOp, DAG);
6031 // If we have SSSE3, case 1 is generated when all result bytes come from
6032 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6033 // present, fall back to case 3.
6035 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6036 if (TLI.getSubtarget()->hasSSSE3()) {
6037 SmallVector<SDValue,16> pshufbMask;
6039 // If all result elements are from one input vector, then only translate
6040 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6042 // Otherwise, we have elements from both input vectors, and must zero out
6043 // elements that come from V2 in the first mask, and V1 in the second mask
6044 // so that we can OR them together.
6045 for (unsigned i = 0; i != 16; ++i) {
6046 int EltIdx = MaskVals[i];
6047 if (EltIdx < 0 || EltIdx >= 16)
6049 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6051 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6052 DAG.getNode(ISD::BUILD_VECTOR, dl,
6053 MVT::v16i8, &pshufbMask[0], 16));
6055 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6056 // the 2nd operand if it's undefined or zero.
6057 if (V2.getOpcode() == ISD::UNDEF ||
6058 ISD::isBuildVectorAllZeros(V2.getNode()))
6061 // Calculate the shuffle mask for the second input, shuffle it, and
6062 // OR it with the first shuffled input.
6064 for (unsigned i = 0; i != 16; ++i) {
6065 int EltIdx = MaskVals[i];
6066 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6067 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6069 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6070 DAG.getNode(ISD::BUILD_VECTOR, dl,
6071 MVT::v16i8, &pshufbMask[0], 16));
6072 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6075 // No SSSE3 - Calculate in place words and then fix all out of place words
6076 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6077 // the 16 different words that comprise the two doublequadword input vectors.
6078 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6079 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6081 for (int i = 0; i != 8; ++i) {
6082 int Elt0 = MaskVals[i*2];
6083 int Elt1 = MaskVals[i*2+1];
6085 // This word of the result is all undef, skip it.
6086 if (Elt0 < 0 && Elt1 < 0)
6089 // This word of the result is already in the correct place, skip it.
6090 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6093 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6094 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6097 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6098 // using a single extract together, load it and store it.
6099 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6100 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6101 DAG.getIntPtrConstant(Elt1 / 2));
6102 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6103 DAG.getIntPtrConstant(i));
6107 // If Elt1 is defined, extract it from the appropriate source. If the
6108 // source byte is not also odd, shift the extracted word left 8 bits
6109 // otherwise clear the bottom 8 bits if we need to do an or.
6111 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6112 DAG.getIntPtrConstant(Elt1 / 2));
6113 if ((Elt1 & 1) == 0)
6114 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6116 TLI.getShiftAmountTy(InsElt.getValueType())));
6118 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6119 DAG.getConstant(0xFF00, MVT::i16));
6121 // If Elt0 is defined, extract it from the appropriate source. If the
6122 // source byte is not also even, shift the extracted word right 8 bits. If
6123 // Elt1 was also defined, OR the extracted values together before
6124 // inserting them in the result.
6126 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6127 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6128 if ((Elt0 & 1) != 0)
6129 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6131 TLI.getShiftAmountTy(InsElt0.getValueType())));
6133 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6134 DAG.getConstant(0x00FF, MVT::i16));
6135 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6138 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6139 DAG.getIntPtrConstant(i));
6141 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6144 // v32i8 shuffles - Translate to VPSHUFB if possible.
6146 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6147 const X86Subtarget *Subtarget,
6148 SelectionDAG &DAG) {
6149 MVT VT = SVOp->getValueType(0).getSimpleVT();
6150 SDValue V1 = SVOp->getOperand(0);
6151 SDValue V2 = SVOp->getOperand(1);
6152 DebugLoc dl = SVOp->getDebugLoc();
6153 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6155 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6156 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6157 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6159 // VPSHUFB may be generated if
6160 // (1) one of input vector is undefined or zeroinitializer.
6161 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6162 // And (2) the mask indexes don't cross the 128-bit lane.
6163 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6164 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6167 if (V1IsAllZero && !V2IsAllZero) {
6168 CommuteVectorShuffleMask(MaskVals, 32);
6171 SmallVector<SDValue, 32> pshufbMask;
6172 for (unsigned i = 0; i != 32; i++) {
6173 int EltIdx = MaskVals[i];
6174 if (EltIdx < 0 || EltIdx >= 32)
6177 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6178 // Cross lane is not allowed.
6182 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6184 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6185 DAG.getNode(ISD::BUILD_VECTOR, dl,
6186 MVT::v32i8, &pshufbMask[0], 32));
6189 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6190 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6191 /// done when every pair / quad of shuffle mask elements point to elements in
6192 /// the right sequence. e.g.
6193 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6195 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6196 SelectionDAG &DAG) {
6197 MVT VT = SVOp->getValueType(0).getSimpleVT();
6198 DebugLoc dl = SVOp->getDebugLoc();
6199 unsigned NumElems = VT.getVectorNumElements();
6202 switch (VT.SimpleTy) {
6203 default: llvm_unreachable("Unexpected!");
6204 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6205 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6206 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6207 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6208 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6209 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6212 SmallVector<int, 8> MaskVec;
6213 for (unsigned i = 0; i != NumElems; i += Scale) {
6215 for (unsigned j = 0; j != Scale; ++j) {
6216 int EltIdx = SVOp->getMaskElt(i+j);
6220 StartIdx = (EltIdx / Scale);
6221 if (EltIdx != (int)(StartIdx*Scale + j))
6224 MaskVec.push_back(StartIdx);
6227 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6228 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6229 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6232 /// getVZextMovL - Return a zero-extending vector move low node.
6234 static SDValue getVZextMovL(MVT VT, EVT OpVT,
6235 SDValue SrcOp, SelectionDAG &DAG,
6236 const X86Subtarget *Subtarget, DebugLoc dl) {
6237 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6238 LoadSDNode *LD = NULL;
6239 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6240 LD = dyn_cast<LoadSDNode>(SrcOp);
6242 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6244 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6245 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6246 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6247 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6248 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6250 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6251 return DAG.getNode(ISD::BITCAST, dl, VT,
6252 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6253 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6261 return DAG.getNode(ISD::BITCAST, dl, VT,
6262 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6263 DAG.getNode(ISD::BITCAST, dl,
6267 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6268 /// which could not be matched by any known target speficic shuffle
6270 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6272 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6273 if (NewOp.getNode())
6276 MVT VT = SVOp->getValueType(0).getSimpleVT();
6278 unsigned NumElems = VT.getVectorNumElements();
6279 unsigned NumLaneElems = NumElems / 2;
6281 DebugLoc dl = SVOp->getDebugLoc();
6282 MVT EltVT = VT.getVectorElementType();
6283 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6286 SmallVector<int, 16> Mask;
6287 for (unsigned l = 0; l < 2; ++l) {
6288 // Build a shuffle mask for the output, discovering on the fly which
6289 // input vectors to use as shuffle operands (recorded in InputUsed).
6290 // If building a suitable shuffle vector proves too hard, then bail
6291 // out with UseBuildVector set.
6292 bool UseBuildVector = false;
6293 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6294 unsigned LaneStart = l * NumLaneElems;
6295 for (unsigned i = 0; i != NumLaneElems; ++i) {
6296 // The mask element. This indexes into the input.
6297 int Idx = SVOp->getMaskElt(i+LaneStart);
6299 // the mask element does not index into any input vector.
6304 // The input vector this mask element indexes into.
6305 int Input = Idx / NumLaneElems;
6307 // Turn the index into an offset from the start of the input vector.
6308 Idx -= Input * NumLaneElems;
6310 // Find or create a shuffle vector operand to hold this input.
6312 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6313 if (InputUsed[OpNo] == Input)
6314 // This input vector is already an operand.
6316 if (InputUsed[OpNo] < 0) {
6317 // Create a new operand for this input vector.
6318 InputUsed[OpNo] = Input;
6323 if (OpNo >= array_lengthof(InputUsed)) {
6324 // More than two input vectors used! Give up on trying to create a
6325 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6326 UseBuildVector = true;
6330 // Add the mask index for the new shuffle vector.
6331 Mask.push_back(Idx + OpNo * NumLaneElems);
6334 if (UseBuildVector) {
6335 SmallVector<SDValue, 16> SVOps;
6336 for (unsigned i = 0; i != NumLaneElems; ++i) {
6337 // The mask element. This indexes into the input.
6338 int Idx = SVOp->getMaskElt(i+LaneStart);
6340 SVOps.push_back(DAG.getUNDEF(EltVT));
6344 // The input vector this mask element indexes into.
6345 int Input = Idx / NumElems;
6347 // Turn the index into an offset from the start of the input vector.
6348 Idx -= Input * NumElems;
6350 // Extract the vector element by hand.
6351 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6352 SVOp->getOperand(Input),
6353 DAG.getIntPtrConstant(Idx)));
6356 // Construct the output using a BUILD_VECTOR.
6357 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6359 } else if (InputUsed[0] < 0) {
6360 // No input vectors were used! The result is undefined.
6361 Output[l] = DAG.getUNDEF(NVT);
6363 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6364 (InputUsed[0] % 2) * NumLaneElems,
6366 // If only one input was used, use an undefined vector for the other.
6367 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6368 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6369 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6370 // At least one input vector was used. Create a new shuffle vector.
6371 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6377 // Concatenate the result back
6378 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6381 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6382 /// 4 elements, and match them with several different shuffle types.
6384 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6385 SDValue V1 = SVOp->getOperand(0);
6386 SDValue V2 = SVOp->getOperand(1);
6387 DebugLoc dl = SVOp->getDebugLoc();
6388 MVT VT = SVOp->getValueType(0).getSimpleVT();
6390 assert(VT.is128BitVector() && "Unsupported vector size");
6392 std::pair<int, int> Locs[4];
6393 int Mask1[] = { -1, -1, -1, -1 };
6394 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6398 for (unsigned i = 0; i != 4; ++i) {
6399 int Idx = PermMask[i];
6401 Locs[i] = std::make_pair(-1, -1);
6403 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6405 Locs[i] = std::make_pair(0, NumLo);
6409 Locs[i] = std::make_pair(1, NumHi);
6411 Mask1[2+NumHi] = Idx;
6417 if (NumLo <= 2 && NumHi <= 2) {
6418 // If no more than two elements come from either vector. This can be
6419 // implemented with two shuffles. First shuffle gather the elements.
6420 // The second shuffle, which takes the first shuffle as both of its
6421 // vector operands, put the elements into the right order.
6422 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6424 int Mask2[] = { -1, -1, -1, -1 };
6426 for (unsigned i = 0; i != 4; ++i)
6427 if (Locs[i].first != -1) {
6428 unsigned Idx = (i < 2) ? 0 : 4;
6429 Idx += Locs[i].first * 2 + Locs[i].second;
6433 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6436 if (NumLo == 3 || NumHi == 3) {
6437 // Otherwise, we must have three elements from one vector, call it X, and
6438 // one element from the other, call it Y. First, use a shufps to build an
6439 // intermediate vector with the one element from Y and the element from X
6440 // that will be in the same half in the final destination (the indexes don't
6441 // matter). Then, use a shufps to build the final vector, taking the half
6442 // containing the element from Y from the intermediate, and the other half
6445 // Normalize it so the 3 elements come from V1.
6446 CommuteVectorShuffleMask(PermMask, 4);
6450 // Find the element from V2.
6452 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6453 int Val = PermMask[HiIndex];
6460 Mask1[0] = PermMask[HiIndex];
6462 Mask1[2] = PermMask[HiIndex^1];
6464 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6467 Mask1[0] = PermMask[0];
6468 Mask1[1] = PermMask[1];
6469 Mask1[2] = HiIndex & 1 ? 6 : 4;
6470 Mask1[3] = HiIndex & 1 ? 4 : 6;
6471 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6474 Mask1[0] = HiIndex & 1 ? 2 : 0;
6475 Mask1[1] = HiIndex & 1 ? 0 : 2;
6476 Mask1[2] = PermMask[2];
6477 Mask1[3] = PermMask[3];
6482 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6485 // Break it into (shuffle shuffle_hi, shuffle_lo).
6486 int LoMask[] = { -1, -1, -1, -1 };
6487 int HiMask[] = { -1, -1, -1, -1 };
6489 int *MaskPtr = LoMask;
6490 unsigned MaskIdx = 0;
6493 for (unsigned i = 0; i != 4; ++i) {
6500 int Idx = PermMask[i];
6502 Locs[i] = std::make_pair(-1, -1);
6503 } else if (Idx < 4) {
6504 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6505 MaskPtr[LoIdx] = Idx;
6508 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6509 MaskPtr[HiIdx] = Idx;
6514 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6515 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6516 int MaskOps[] = { -1, -1, -1, -1 };
6517 for (unsigned i = 0; i != 4; ++i)
6518 if (Locs[i].first != -1)
6519 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6520 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6523 static bool MayFoldVectorLoad(SDValue V) {
6524 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6525 V = V.getOperand(0);
6527 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6528 V = V.getOperand(0);
6529 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6530 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6531 // BUILD_VECTOR (load), undef
6532 V = V.getOperand(0);
6534 return MayFoldLoad(V);
6538 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6539 EVT VT = Op.getValueType();
6541 // Canonizalize to v2f64.
6542 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6543 return DAG.getNode(ISD::BITCAST, dl, VT,
6544 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6549 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6551 SDValue V1 = Op.getOperand(0);
6552 SDValue V2 = Op.getOperand(1);
6553 EVT VT = Op.getValueType();
6555 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6557 if (HasSSE2 && VT == MVT::v2f64)
6558 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6560 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6561 return DAG.getNode(ISD::BITCAST, dl, VT,
6562 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6563 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6564 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6568 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6569 SDValue V1 = Op.getOperand(0);
6570 SDValue V2 = Op.getOperand(1);
6571 EVT VT = Op.getValueType();
6573 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6574 "unsupported shuffle type");
6576 if (V2.getOpcode() == ISD::UNDEF)
6580 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6584 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6585 SDValue V1 = Op.getOperand(0);
6586 SDValue V2 = Op.getOperand(1);
6587 EVT VT = Op.getValueType();
6588 unsigned NumElems = VT.getVectorNumElements();
6590 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6591 // operand of these instructions is only memory, so check if there's a
6592 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6594 bool CanFoldLoad = false;
6596 // Trivial case, when V2 comes from a load.
6597 if (MayFoldVectorLoad(V2))
6600 // When V1 is a load, it can be folded later into a store in isel, example:
6601 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6603 // (MOVLPSmr addr:$src1, VR128:$src2)
6604 // So, recognize this potential and also use MOVLPS or MOVLPD
6605 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6608 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6610 if (HasSSE2 && NumElems == 2)
6611 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6614 // If we don't care about the second element, proceed to use movss.
6615 if (SVOp->getMaskElt(1) != -1)
6616 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6619 // movl and movlp will both match v2i64, but v2i64 is never matched by
6620 // movl earlier because we make it strict to avoid messing with the movlp load
6621 // folding logic (see the code above getMOVLP call). Match it here then,
6622 // this is horrible, but will stay like this until we move all shuffle
6623 // matching to x86 specific nodes. Note that for the 1st condition all
6624 // types are matched with movsd.
6626 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6627 // as to remove this logic from here, as much as possible
6628 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6629 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6630 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6633 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6635 // Invert the operand order and use SHUFPS to match it.
6636 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6637 getShuffleSHUFImmediate(SVOp), DAG);
6640 // Reduce a vector shuffle to zext.
6642 X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6643 // PMOVZX is only available from SSE41.
6644 if (!Subtarget->hasSSE41())
6647 EVT VT = Op.getValueType();
6649 // Only AVX2 support 256-bit vector integer extending.
6650 if (!Subtarget->hasInt256() && VT.is256BitVector())
6653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6654 DebugLoc DL = Op.getDebugLoc();
6655 SDValue V1 = Op.getOperand(0);
6656 SDValue V2 = Op.getOperand(1);
6657 unsigned NumElems = VT.getVectorNumElements();
6659 // Extending is an unary operation and the element type of the source vector
6660 // won't be equal to or larger than i64.
6661 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6662 VT.getVectorElementType() == MVT::i64)
6665 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6666 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6667 while ((1U << Shift) < NumElems) {
6668 if (SVOp->getMaskElt(1U << Shift) == 1)
6671 // The maximal ratio is 8, i.e. from i8 to i64.
6676 // Check the shuffle mask.
6677 unsigned Mask = (1U << Shift) - 1;
6678 for (unsigned i = 0; i != NumElems; ++i) {
6679 int EltIdx = SVOp->getMaskElt(i);
6680 if ((i & Mask) != 0 && EltIdx != -1)
6682 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6686 LLVMContext *Context = DAG.getContext();
6687 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6688 EVT NeVT = EVT::getIntegerVT(*Context, NBits);
6689 EVT NVT = EVT::getVectorVT(*Context, NeVT, NumElems >> Shift);
6691 if (!isTypeLegal(NVT))
6694 // Simplify the operand as it's prepared to be fed into shuffle.
6695 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6696 if (V1.getOpcode() == ISD::BITCAST &&
6697 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6698 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6700 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6701 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6702 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6703 ConstantSDNode *CIdx =
6704 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6705 // If it's foldable, i.e. normal load with single use, we will let code
6706 // selection to fold it. Otherwise, we will short the conversion sequence.
6707 if (CIdx && CIdx->getZExtValue() == 0 &&
6708 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
6709 if (V.getValueSizeInBits() > V1.getValueSizeInBits()) {
6710 // The "ext_vec_elt" node is wider than the result node.
6711 // In this case we should extract subvector from V.
6712 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
6713 unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits();
6714 EVT FullVT = V.getValueType();
6715 EVT SubVecVT = EVT::getVectorVT(*Context,
6716 FullVT.getVectorElementType(),
6717 FullVT.getVectorNumElements()/Ratio);
6718 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
6719 DAG.getIntPtrConstant(0));
6721 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6725 return DAG.getNode(ISD::BITCAST, DL, VT,
6726 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6730 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6731 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6732 MVT VT = Op.getValueType().getSimpleVT();
6733 DebugLoc dl = Op.getDebugLoc();
6734 SDValue V1 = Op.getOperand(0);
6735 SDValue V2 = Op.getOperand(1);
6737 if (isZeroShuffle(SVOp))
6738 return getZeroVector(VT, Subtarget, DAG, dl);
6740 // Handle splat operations
6741 if (SVOp->isSplat()) {
6742 // Use vbroadcast whenever the splat comes from a foldable load
6743 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6744 if (Broadcast.getNode())
6748 // Check integer expanding shuffles.
6749 SDValue NewOp = LowerVectorIntExtend(Op, DAG);
6750 if (NewOp.getNode())
6753 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6755 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6756 VT == MVT::v16i16 || VT == MVT::v32i8) {
6757 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6758 if (NewOp.getNode())
6759 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6760 } else if ((VT == MVT::v4i32 ||
6761 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6762 // FIXME: Figure out a cleaner way to do this.
6763 // Try to make use of movq to zero out the top part.
6764 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6765 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6766 if (NewOp.getNode()) {
6767 MVT NewVT = NewOp.getValueType().getSimpleVT();
6768 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6769 NewVT, true, false))
6770 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6771 DAG, Subtarget, dl);
6773 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6774 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6775 if (NewOp.getNode()) {
6776 MVT NewVT = NewOp.getValueType().getSimpleVT();
6777 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6778 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6779 DAG, Subtarget, dl);
6787 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6788 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6789 SDValue V1 = Op.getOperand(0);
6790 SDValue V2 = Op.getOperand(1);
6791 MVT VT = Op.getValueType().getSimpleVT();
6792 DebugLoc dl = Op.getDebugLoc();
6793 unsigned NumElems = VT.getVectorNumElements();
6794 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6795 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6796 bool V1IsSplat = false;
6797 bool V2IsSplat = false;
6798 bool HasSSE2 = Subtarget->hasSSE2();
6799 bool HasFp256 = Subtarget->hasFp256();
6800 bool HasInt256 = Subtarget->hasInt256();
6801 MachineFunction &MF = DAG.getMachineFunction();
6802 bool OptForSize = MF.getFunction()->getAttributes().
6803 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6805 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6807 if (V1IsUndef && V2IsUndef)
6808 return DAG.getUNDEF(VT);
6810 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6812 // Vector shuffle lowering takes 3 steps:
6814 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6815 // narrowing and commutation of operands should be handled.
6816 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6818 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6819 // so the shuffle can be broken into other shuffles and the legalizer can
6820 // try the lowering again.
6822 // The general idea is that no vector_shuffle operation should be left to
6823 // be matched during isel, all of them must be converted to a target specific
6826 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6827 // narrowing and commutation of operands should be handled. The actual code
6828 // doesn't include all of those, work in progress...
6829 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6830 if (NewOp.getNode())
6833 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6835 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6836 // unpckh_undef). Only use pshufd if speed is more important than size.
6837 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6838 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6839 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6840 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6842 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6843 V2IsUndef && MayFoldVectorLoad(V1))
6844 return getMOVDDup(Op, dl, V1, DAG);
6846 if (isMOVHLPS_v_undef_Mask(M, VT))
6847 return getMOVHighToLow(Op, dl, DAG);
6849 // Use to match splats
6850 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
6851 (VT == MVT::v2f64 || VT == MVT::v2i64))
6852 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6854 if (isPSHUFDMask(M, VT)) {
6855 // The actual implementation will match the mask in the if above and then
6856 // during isel it can match several different instructions, not only pshufd
6857 // as its name says, sad but true, emulate the behavior for now...
6858 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6859 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6861 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6863 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6864 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6866 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6867 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
6870 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6874 // Check if this can be converted into a logical shift.
6875 bool isLeft = false;
6878 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6879 if (isShift && ShVal.hasOneUse()) {
6880 // If the shifted value has multiple uses, it may be cheaper to use
6881 // v_set0 + movlhps or movhlps, etc.
6882 MVT EltVT = VT.getVectorElementType();
6883 ShAmt *= EltVT.getSizeInBits();
6884 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6887 if (isMOVLMask(M, VT)) {
6888 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6889 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6890 if (!isMOVLPMask(M, VT)) {
6891 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6892 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6894 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6895 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6899 // FIXME: fold these into legal mask.
6900 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
6901 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6903 if (isMOVHLPSMask(M, VT))
6904 return getMOVHighToLow(Op, dl, DAG);
6906 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6907 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6909 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6910 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6912 if (isMOVLPMask(M, VT))
6913 return getMOVLP(Op, dl, DAG, HasSSE2);
6915 if (ShouldXformToMOVHLPS(M, VT) ||
6916 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6917 return CommuteVectorShuffle(SVOp, DAG);
6920 // No better options. Use a vshldq / vsrldq.
6921 MVT EltVT = VT.getVectorElementType();
6922 ShAmt *= EltVT.getSizeInBits();
6923 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6926 bool Commuted = false;
6927 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6928 // 1,1,1,1 -> v8i16 though.
6929 V1IsSplat = isSplatVector(V1.getNode());
6930 V2IsSplat = isSplatVector(V2.getNode());
6932 // Canonicalize the splat or undef, if present, to be on the RHS.
6933 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6934 CommuteVectorShuffleMask(M, NumElems);
6936 std::swap(V1IsSplat, V2IsSplat);
6940 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6941 // Shuffling low element of v1 into undef, just return v1.
6944 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6945 // the instruction selector will not match, so get a canonical MOVL with
6946 // swapped operands to undo the commute.
6947 return getMOVL(DAG, dl, VT, V2, V1);
6950 if (isUNPCKLMask(M, VT, HasInt256))
6951 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6953 if (isUNPCKHMask(M, VT, HasInt256))
6954 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6957 // Normalize mask so all entries that point to V2 points to its first
6958 // element then try to match unpck{h|l} again. If match, return a
6959 // new vector_shuffle with the corrected mask.p
6960 SmallVector<int, 8> NewMask(M.begin(), M.end());
6961 NormalizeMask(NewMask, NumElems);
6962 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
6963 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6964 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
6965 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6969 // Commute is back and try unpck* again.
6970 // FIXME: this seems wrong.
6971 CommuteVectorShuffleMask(M, NumElems);
6973 std::swap(V1IsSplat, V2IsSplat);
6976 if (isUNPCKLMask(M, VT, HasInt256))
6977 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6979 if (isUNPCKHMask(M, VT, HasInt256))
6980 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6983 // Normalize the node to match x86 shuffle ops if needed
6984 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
6985 return CommuteVectorShuffle(SVOp, DAG);
6987 // The checks below are all present in isShuffleMaskLegal, but they are
6988 // inlined here right now to enable us to directly emit target specific
6989 // nodes, and remove one by one until they don't return Op anymore.
6991 if (isPALIGNRMask(M, VT, Subtarget))
6992 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
6993 getShufflePALIGNRImmediate(SVOp),
6996 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6997 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6998 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6999 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7002 if (isPSHUFHWMask(M, VT, HasInt256))
7003 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7004 getShufflePSHUFHWImmediate(SVOp),
7007 if (isPSHUFLWMask(M, VT, HasInt256))
7008 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7009 getShufflePSHUFLWImmediate(SVOp),
7012 if (isSHUFPMask(M, VT, HasFp256))
7013 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7014 getShuffleSHUFImmediate(SVOp), DAG);
7016 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7017 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7018 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7019 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7021 //===--------------------------------------------------------------------===//
7022 // Generate target specific nodes for 128 or 256-bit shuffles only
7023 // supported in the AVX instruction set.
7026 // Handle VMOVDDUPY permutations
7027 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7028 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7030 // Handle VPERMILPS/D* permutations
7031 if (isVPERMILPMask(M, VT, HasFp256)) {
7032 if (HasInt256 && VT == MVT::v8i32)
7033 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7034 getShuffleSHUFImmediate(SVOp), DAG);
7035 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7036 getShuffleSHUFImmediate(SVOp), DAG);
7039 // Handle VPERM2F128/VPERM2I128 permutations
7040 if (isVPERM2X128Mask(M, VT, HasFp256))
7041 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7042 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7044 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7045 if (BlendOp.getNode())
7048 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
7049 SmallVector<SDValue, 8> permclMask;
7050 for (unsigned i = 0; i != 8; ++i) {
7051 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
7053 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
7055 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7056 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7057 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7060 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
7061 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
7062 getShuffleCLImmediate(SVOp), DAG);
7064 //===--------------------------------------------------------------------===//
7065 // Since no target specific shuffle was selected for this generic one,
7066 // lower it into other known shuffles. FIXME: this isn't true yet, but
7067 // this is the plan.
7070 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7071 if (VT == MVT::v8i16) {
7072 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7073 if (NewOp.getNode())
7077 if (VT == MVT::v16i8) {
7078 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7079 if (NewOp.getNode())
7083 if (VT == MVT::v32i8) {
7084 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7085 if (NewOp.getNode())
7089 // Handle all 128-bit wide vectors with 4 elements, and match them with
7090 // several different shuffle types.
7091 if (NumElems == 4 && VT.is128BitVector())
7092 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7094 // Handle general 256-bit shuffles
7095 if (VT.is256BitVector())
7096 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7101 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7102 MVT VT = Op.getValueType().getSimpleVT();
7103 DebugLoc dl = Op.getDebugLoc();
7105 if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector())
7108 if (VT.getSizeInBits() == 8) {
7109 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7110 Op.getOperand(0), Op.getOperand(1));
7111 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7112 DAG.getValueType(VT));
7113 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7116 if (VT.getSizeInBits() == 16) {
7117 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7118 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7120 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7121 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7122 DAG.getNode(ISD::BITCAST, dl,
7126 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7127 Op.getOperand(0), Op.getOperand(1));
7128 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7129 DAG.getValueType(VT));
7130 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7133 if (VT == MVT::f32) {
7134 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7135 // the result back to FR32 register. It's only worth matching if the
7136 // result has a single use which is a store or a bitcast to i32. And in
7137 // the case of a store, it's not worth it if the index is a constant 0,
7138 // because a MOVSSmr can be used instead, which is smaller and faster.
7139 if (!Op.hasOneUse())
7141 SDNode *User = *Op.getNode()->use_begin();
7142 if ((User->getOpcode() != ISD::STORE ||
7143 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7144 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7145 (User->getOpcode() != ISD::BITCAST ||
7146 User->getValueType(0) != MVT::i32))
7148 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7149 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7152 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7155 if (VT == MVT::i32 || VT == MVT::i64) {
7156 // ExtractPS/pextrq works with constant index.
7157 if (isa<ConstantSDNode>(Op.getOperand(1)))
7164 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7165 SelectionDAG &DAG) const {
7166 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7169 SDValue Vec = Op.getOperand(0);
7170 MVT VecVT = Vec.getValueType().getSimpleVT();
7172 // If this is a 256-bit vector result, first extract the 128-bit vector and
7173 // then extract the element from the 128-bit vector.
7174 if (VecVT.is256BitVector()) {
7175 DebugLoc dl = Op.getNode()->getDebugLoc();
7176 unsigned NumElems = VecVT.getVectorNumElements();
7177 SDValue Idx = Op.getOperand(1);
7178 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7180 // Get the 128-bit vector.
7181 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7183 if (IdxVal >= NumElems/2)
7184 IdxVal -= NumElems/2;
7185 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7186 DAG.getConstant(IdxVal, MVT::i32));
7189 assert(VecVT.is128BitVector() && "Unexpected vector length");
7191 if (Subtarget->hasSSE41()) {
7192 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7197 MVT VT = Op.getValueType().getSimpleVT();
7198 DebugLoc dl = Op.getDebugLoc();
7199 // TODO: handle v16i8.
7200 if (VT.getSizeInBits() == 16) {
7201 SDValue Vec = Op.getOperand(0);
7202 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7204 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7205 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7206 DAG.getNode(ISD::BITCAST, dl,
7209 // Transform it so it match pextrw which produces a 32-bit result.
7210 MVT EltVT = MVT::i32;
7211 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7212 Op.getOperand(0), Op.getOperand(1));
7213 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7214 DAG.getValueType(VT));
7215 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7218 if (VT.getSizeInBits() == 32) {
7219 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7223 // SHUFPS the element to the lowest double word, then movss.
7224 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7225 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7226 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7227 DAG.getUNDEF(VVT), Mask);
7228 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7229 DAG.getIntPtrConstant(0));
7232 if (VT.getSizeInBits() == 64) {
7233 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7234 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7235 // to match extract_elt for f64.
7236 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7240 // UNPCKHPD the element to the lowest double word, then movsd.
7241 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7242 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7243 int Mask[2] = { 1, -1 };
7244 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7245 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7246 DAG.getUNDEF(VVT), Mask);
7247 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7248 DAG.getIntPtrConstant(0));
7254 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7255 MVT VT = Op.getValueType().getSimpleVT();
7256 MVT EltVT = VT.getVectorElementType();
7257 DebugLoc dl = Op.getDebugLoc();
7259 SDValue N0 = Op.getOperand(0);
7260 SDValue N1 = Op.getOperand(1);
7261 SDValue N2 = Op.getOperand(2);
7263 if (!VT.is128BitVector())
7266 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7267 isa<ConstantSDNode>(N2)) {
7269 if (VT == MVT::v8i16)
7270 Opc = X86ISD::PINSRW;
7271 else if (VT == MVT::v16i8)
7272 Opc = X86ISD::PINSRB;
7274 Opc = X86ISD::PINSRB;
7276 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7278 if (N1.getValueType() != MVT::i32)
7279 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7280 if (N2.getValueType() != MVT::i32)
7281 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7282 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7285 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7286 // Bits [7:6] of the constant are the source select. This will always be
7287 // zero here. The DAG Combiner may combine an extract_elt index into these
7288 // bits. For example (insert (extract, 3), 2) could be matched by putting
7289 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7290 // Bits [5:4] of the constant are the destination select. This is the
7291 // value of the incoming immediate.
7292 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7293 // combine either bitwise AND or insert of float 0.0 to set these bits.
7294 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7295 // Create this as a scalar to vector..
7296 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7297 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7300 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7301 // PINSR* works with constant index.
7308 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7309 MVT VT = Op.getValueType().getSimpleVT();
7310 MVT EltVT = VT.getVectorElementType();
7312 DebugLoc dl = Op.getDebugLoc();
7313 SDValue N0 = Op.getOperand(0);
7314 SDValue N1 = Op.getOperand(1);
7315 SDValue N2 = Op.getOperand(2);
7317 // If this is a 256-bit vector result, first extract the 128-bit vector,
7318 // insert the element into the extracted half and then place it back.
7319 if (VT.is256BitVector()) {
7320 if (!isa<ConstantSDNode>(N2))
7323 // Get the desired 128-bit vector half.
7324 unsigned NumElems = VT.getVectorNumElements();
7325 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7326 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7328 // Insert the element into the desired half.
7329 bool Upper = IdxVal >= NumElems/2;
7330 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7331 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7333 // Insert the changed part back to the 256-bit vector
7334 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7337 if (Subtarget->hasSSE41())
7338 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7340 if (EltVT == MVT::i8)
7343 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7344 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7345 // as its second argument.
7346 if (N1.getValueType() != MVT::i32)
7347 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7348 if (N2.getValueType() != MVT::i32)
7349 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7350 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7355 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7356 LLVMContext *Context = DAG.getContext();
7357 DebugLoc dl = Op.getDebugLoc();
7358 MVT OpVT = Op.getValueType().getSimpleVT();
7360 // If this is a 256-bit vector result, first insert into a 128-bit
7361 // vector and then insert into the 256-bit vector.
7362 if (!OpVT.is128BitVector()) {
7363 // Insert into a 128-bit vector.
7364 EVT VT128 = EVT::getVectorVT(*Context,
7365 OpVT.getVectorElementType(),
7366 OpVT.getVectorNumElements() / 2);
7368 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7370 // Insert the 128-bit vector.
7371 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7374 if (OpVT == MVT::v1i64 &&
7375 Op.getOperand(0).getValueType() == MVT::i64)
7376 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7378 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7379 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7380 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7381 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7384 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7385 // a simple subregister reference or explicit instructions to grab
7386 // upper bits of a vector.
7387 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7388 SelectionDAG &DAG) {
7389 if (Subtarget->hasFp256()) {
7390 DebugLoc dl = Op.getNode()->getDebugLoc();
7391 SDValue Vec = Op.getNode()->getOperand(0);
7392 SDValue Idx = Op.getNode()->getOperand(1);
7394 if (Op.getNode()->getValueType(0).is128BitVector() &&
7395 Vec.getNode()->getValueType(0).is256BitVector() &&
7396 isa<ConstantSDNode>(Idx)) {
7397 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7398 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7404 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7405 // simple superregister reference or explicit instructions to insert
7406 // the upper bits of a vector.
7407 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7408 SelectionDAG &DAG) {
7409 if (Subtarget->hasFp256()) {
7410 DebugLoc dl = Op.getNode()->getDebugLoc();
7411 SDValue Vec = Op.getNode()->getOperand(0);
7412 SDValue SubVec = Op.getNode()->getOperand(1);
7413 SDValue Idx = Op.getNode()->getOperand(2);
7415 if (Op.getNode()->getValueType(0).is256BitVector() &&
7416 SubVec.getNode()->getValueType(0).is128BitVector() &&
7417 isa<ConstantSDNode>(Idx)) {
7418 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7419 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7425 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7426 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7427 // one of the above mentioned nodes. It has to be wrapped because otherwise
7428 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7429 // be used to form addressing mode. These wrapped nodes will be selected
7432 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7433 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7435 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7437 unsigned char OpFlag = 0;
7438 unsigned WrapperKind = X86ISD::Wrapper;
7439 CodeModel::Model M = getTargetMachine().getCodeModel();
7441 if (Subtarget->isPICStyleRIPRel() &&
7442 (M == CodeModel::Small || M == CodeModel::Kernel))
7443 WrapperKind = X86ISD::WrapperRIP;
7444 else if (Subtarget->isPICStyleGOT())
7445 OpFlag = X86II::MO_GOTOFF;
7446 else if (Subtarget->isPICStyleStubPIC())
7447 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7449 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7451 CP->getOffset(), OpFlag);
7452 DebugLoc DL = CP->getDebugLoc();
7453 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7454 // With PIC, the address is actually $g + Offset.
7456 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7457 DAG.getNode(X86ISD::GlobalBaseReg,
7458 DebugLoc(), getPointerTy()),
7465 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7466 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7468 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7470 unsigned char OpFlag = 0;
7471 unsigned WrapperKind = X86ISD::Wrapper;
7472 CodeModel::Model M = getTargetMachine().getCodeModel();
7474 if (Subtarget->isPICStyleRIPRel() &&
7475 (M == CodeModel::Small || M == CodeModel::Kernel))
7476 WrapperKind = X86ISD::WrapperRIP;
7477 else if (Subtarget->isPICStyleGOT())
7478 OpFlag = X86II::MO_GOTOFF;
7479 else if (Subtarget->isPICStyleStubPIC())
7480 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7482 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7484 DebugLoc DL = JT->getDebugLoc();
7485 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7487 // With PIC, the address is actually $g + Offset.
7489 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7490 DAG.getNode(X86ISD::GlobalBaseReg,
7491 DebugLoc(), getPointerTy()),
7498 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7499 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7501 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7503 unsigned char OpFlag = 0;
7504 unsigned WrapperKind = X86ISD::Wrapper;
7505 CodeModel::Model M = getTargetMachine().getCodeModel();
7507 if (Subtarget->isPICStyleRIPRel() &&
7508 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7509 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7510 OpFlag = X86II::MO_GOTPCREL;
7511 WrapperKind = X86ISD::WrapperRIP;
7512 } else if (Subtarget->isPICStyleGOT()) {
7513 OpFlag = X86II::MO_GOT;
7514 } else if (Subtarget->isPICStyleStubPIC()) {
7515 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7516 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7517 OpFlag = X86II::MO_DARWIN_NONLAZY;
7520 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7522 DebugLoc DL = Op.getDebugLoc();
7523 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7525 // With PIC, the address is actually $g + Offset.
7526 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7527 !Subtarget->is64Bit()) {
7528 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7529 DAG.getNode(X86ISD::GlobalBaseReg,
7530 DebugLoc(), getPointerTy()),
7534 // For symbols that require a load from a stub to get the address, emit the
7536 if (isGlobalStubReference(OpFlag))
7537 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7538 MachinePointerInfo::getGOT(), false, false, false, 0);
7544 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7545 // Create the TargetBlockAddressAddress node.
7546 unsigned char OpFlags =
7547 Subtarget->ClassifyBlockAddressReference();
7548 CodeModel::Model M = getTargetMachine().getCodeModel();
7549 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7550 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7551 DebugLoc dl = Op.getDebugLoc();
7552 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7555 if (Subtarget->isPICStyleRIPRel() &&
7556 (M == CodeModel::Small || M == CodeModel::Kernel))
7557 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7559 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7561 // With PIC, the address is actually $g + Offset.
7562 if (isGlobalRelativeToPICBase(OpFlags)) {
7563 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7564 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7572 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7573 int64_t Offset, SelectionDAG &DAG) const {
7574 // Create the TargetGlobalAddress node, folding in the constant
7575 // offset if it is legal.
7576 unsigned char OpFlags =
7577 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7578 CodeModel::Model M = getTargetMachine().getCodeModel();
7580 if (OpFlags == X86II::MO_NO_FLAG &&
7581 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7582 // A direct static reference to a global.
7583 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7586 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7589 if (Subtarget->isPICStyleRIPRel() &&
7590 (M == CodeModel::Small || M == CodeModel::Kernel))
7591 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7593 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7595 // With PIC, the address is actually $g + Offset.
7596 if (isGlobalRelativeToPICBase(OpFlags)) {
7597 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7598 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7602 // For globals that require a load from a stub to get the address, emit the
7604 if (isGlobalStubReference(OpFlags))
7605 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7606 MachinePointerInfo::getGOT(), false, false, false, 0);
7608 // If there was a non-zero offset that we didn't fold, create an explicit
7611 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7612 DAG.getConstant(Offset, getPointerTy()));
7618 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7619 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7620 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7621 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7625 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7626 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7627 unsigned char OperandFlags, bool LocalDynamic = false) {
7628 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7629 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7630 DebugLoc dl = GA->getDebugLoc();
7631 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7632 GA->getValueType(0),
7636 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7640 SDValue Ops[] = { Chain, TGA, *InFlag };
7641 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
7643 SDValue Ops[] = { Chain, TGA };
7644 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
7647 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7648 MFI->setAdjustsStack(true);
7650 SDValue Flag = Chain.getValue(1);
7651 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7654 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7656 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7659 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7660 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7661 DAG.getNode(X86ISD::GlobalBaseReg,
7662 DebugLoc(), PtrVT), InFlag);
7663 InFlag = Chain.getValue(1);
7665 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7668 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7670 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7672 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7673 X86::RAX, X86II::MO_TLSGD);
7676 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7680 DebugLoc dl = GA->getDebugLoc();
7682 // Get the start address of the TLS block for this module.
7683 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7684 .getInfo<X86MachineFunctionInfo>();
7685 MFI->incNumLocalDynamicTLSAccesses();
7689 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7690 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7693 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7694 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7695 InFlag = Chain.getValue(1);
7696 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7697 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7700 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7704 unsigned char OperandFlags = X86II::MO_DTPOFF;
7705 unsigned WrapperKind = X86ISD::Wrapper;
7706 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7707 GA->getValueType(0),
7708 GA->getOffset(), OperandFlags);
7709 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7711 // Add x@dtpoff with the base.
7712 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7715 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7716 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7717 const EVT PtrVT, TLSModel::Model model,
7718 bool is64Bit, bool isPIC) {
7719 DebugLoc dl = GA->getDebugLoc();
7721 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7722 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7723 is64Bit ? 257 : 256));
7725 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7726 DAG.getIntPtrConstant(0),
7727 MachinePointerInfo(Ptr),
7728 false, false, false, 0);
7730 unsigned char OperandFlags = 0;
7731 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7733 unsigned WrapperKind = X86ISD::Wrapper;
7734 if (model == TLSModel::LocalExec) {
7735 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7736 } else if (model == TLSModel::InitialExec) {
7738 OperandFlags = X86II::MO_GOTTPOFF;
7739 WrapperKind = X86ISD::WrapperRIP;
7741 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7744 llvm_unreachable("Unexpected model");
7747 // emit "addl x@ntpoff,%eax" (local exec)
7748 // or "addl x@indntpoff,%eax" (initial exec)
7749 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7750 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7751 GA->getValueType(0),
7752 GA->getOffset(), OperandFlags);
7753 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7755 if (model == TLSModel::InitialExec) {
7756 if (isPIC && !is64Bit) {
7757 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7758 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7762 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7763 MachinePointerInfo::getGOT(), false, false, false,
7767 // The address of the thread local variable is the add of the thread
7768 // pointer with the offset of the variable.
7769 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7773 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7775 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7776 const GlobalValue *GV = GA->getGlobal();
7778 if (Subtarget->isTargetELF()) {
7779 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7782 case TLSModel::GeneralDynamic:
7783 if (Subtarget->is64Bit())
7784 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7785 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7786 case TLSModel::LocalDynamic:
7787 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7788 Subtarget->is64Bit());
7789 case TLSModel::InitialExec:
7790 case TLSModel::LocalExec:
7791 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7792 Subtarget->is64Bit(),
7793 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7795 llvm_unreachable("Unknown TLS model.");
7798 if (Subtarget->isTargetDarwin()) {
7799 // Darwin only has one model of TLS. Lower to that.
7800 unsigned char OpFlag = 0;
7801 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7802 X86ISD::WrapperRIP : X86ISD::Wrapper;
7804 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7806 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7807 !Subtarget->is64Bit();
7809 OpFlag = X86II::MO_TLVP_PIC_BASE;
7811 OpFlag = X86II::MO_TLVP;
7812 DebugLoc DL = Op.getDebugLoc();
7813 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7814 GA->getValueType(0),
7815 GA->getOffset(), OpFlag);
7816 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7818 // With PIC32, the address is actually $g + Offset.
7820 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7821 DAG.getNode(X86ISD::GlobalBaseReg,
7822 DebugLoc(), getPointerTy()),
7825 // Lowering the machine isd will make sure everything is in the right
7827 SDValue Chain = DAG.getEntryNode();
7828 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7829 SDValue Args[] = { Chain, Offset };
7830 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7832 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7833 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7834 MFI->setAdjustsStack(true);
7836 // And our return value (tls address) is in the standard call return value
7838 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7839 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7843 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
7844 // Just use the implicit TLS architecture
7845 // Need to generate someting similar to:
7846 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7848 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7849 // mov rcx, qword [rdx+rcx*8]
7850 // mov eax, .tls$:tlsvar
7851 // [rax+rcx] contains the address
7852 // Windows 64bit: gs:0x58
7853 // Windows 32bit: fs:__tls_array
7855 // If GV is an alias then use the aliasee for determining
7856 // thread-localness.
7857 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7858 GV = GA->resolveAliasedGlobal(false);
7859 DebugLoc dl = GA->getDebugLoc();
7860 SDValue Chain = DAG.getEntryNode();
7862 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7863 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
7864 // use its literal value of 0x2C.
7865 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7866 ? Type::getInt8PtrTy(*DAG.getContext(),
7868 : Type::getInt32PtrTy(*DAG.getContext(),
7871 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
7872 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
7873 DAG.getExternalSymbol("_tls_array", getPointerTy()));
7875 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
7876 MachinePointerInfo(Ptr),
7877 false, false, false, 0);
7879 // Load the _tls_index variable
7880 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7881 if (Subtarget->is64Bit())
7882 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7883 IDX, MachinePointerInfo(), MVT::i32,
7886 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7887 false, false, false, 0);
7889 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7891 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7893 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7894 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7895 false, false, false, 0);
7897 // Get the offset of start of .tls section
7898 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7899 GA->getValueType(0),
7900 GA->getOffset(), X86II::MO_SECREL);
7901 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7903 // The address of the thread local variable is the add of the thread
7904 // pointer with the offset of the variable.
7905 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7908 llvm_unreachable("TLS not implemented for this target.");
7911 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7912 /// and take a 2 x i32 value to shift plus a shift amount.
7913 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7914 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7915 EVT VT = Op.getValueType();
7916 unsigned VTBits = VT.getSizeInBits();
7917 DebugLoc dl = Op.getDebugLoc();
7918 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7919 SDValue ShOpLo = Op.getOperand(0);
7920 SDValue ShOpHi = Op.getOperand(1);
7921 SDValue ShAmt = Op.getOperand(2);
7922 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7923 DAG.getConstant(VTBits - 1, MVT::i8))
7924 : DAG.getConstant(0, VT);
7927 if (Op.getOpcode() == ISD::SHL_PARTS) {
7928 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7929 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7931 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7932 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7935 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7936 DAG.getConstant(VTBits, MVT::i8));
7937 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7938 AndNode, DAG.getConstant(0, MVT::i8));
7941 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7942 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7943 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7945 if (Op.getOpcode() == ISD::SHL_PARTS) {
7946 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7947 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7949 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7950 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7953 SDValue Ops[2] = { Lo, Hi };
7954 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
7957 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7958 SelectionDAG &DAG) const {
7959 EVT SrcVT = Op.getOperand(0).getValueType();
7961 if (SrcVT.isVector())
7964 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7965 "Unknown SINT_TO_FP to lower!");
7967 // These are really Legal; return the operand so the caller accepts it as
7969 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7971 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7972 Subtarget->is64Bit()) {
7976 DebugLoc dl = Op.getDebugLoc();
7977 unsigned Size = SrcVT.getSizeInBits()/8;
7978 MachineFunction &MF = DAG.getMachineFunction();
7979 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7980 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7981 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7983 MachinePointerInfo::getFixedStack(SSFI),
7985 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7988 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7990 SelectionDAG &DAG) const {
7992 DebugLoc DL = Op.getDebugLoc();
7994 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7996 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7998 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8000 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8002 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8003 MachineMemOperand *MMO;
8005 int SSFI = FI->getIndex();
8007 DAG.getMachineFunction()
8008 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8009 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8011 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8012 StackSlot = StackSlot.getOperand(1);
8014 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8015 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8017 Tys, Ops, array_lengthof(Ops),
8021 Chain = Result.getValue(1);
8022 SDValue InFlag = Result.getValue(2);
8024 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8025 // shouldn't be necessary except that RFP cannot be live across
8026 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8027 MachineFunction &MF = DAG.getMachineFunction();
8028 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8029 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8030 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8031 Tys = DAG.getVTList(MVT::Other);
8033 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8035 MachineMemOperand *MMO =
8036 DAG.getMachineFunction()
8037 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8038 MachineMemOperand::MOStore, SSFISize, SSFISize);
8040 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8041 Ops, array_lengthof(Ops),
8042 Op.getValueType(), MMO);
8043 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8044 MachinePointerInfo::getFixedStack(SSFI),
8045 false, false, false, 0);
8051 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8052 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8053 SelectionDAG &DAG) const {
8054 // This algorithm is not obvious. Here it is what we're trying to output:
8057 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8058 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8062 pshufd $0x4e, %xmm0, %xmm1
8067 DebugLoc dl = Op.getDebugLoc();
8068 LLVMContext *Context = DAG.getContext();
8070 // Build some magic constants.
8071 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8072 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8073 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8075 SmallVector<Constant*,2> CV1;
8077 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8078 APInt(64, 0x4330000000000000ULL))));
8080 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8081 APInt(64, 0x4530000000000000ULL))));
8082 Constant *C1 = ConstantVector::get(CV1);
8083 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8085 // Load the 64-bit value into an XMM register.
8086 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8088 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8089 MachinePointerInfo::getConstantPool(),
8090 false, false, false, 16);
8091 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8092 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8095 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8096 MachinePointerInfo::getConstantPool(),
8097 false, false, false, 16);
8098 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8099 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8102 if (Subtarget->hasSSE3()) {
8103 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8104 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8106 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8107 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8109 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8110 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8114 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8115 DAG.getIntPtrConstant(0));
8118 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8119 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8120 SelectionDAG &DAG) const {
8121 DebugLoc dl = Op.getDebugLoc();
8122 // FP constant to bias correct the final result.
8123 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8126 // Load the 32-bit value into an XMM register.
8127 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8130 // Zero out the upper parts of the register.
8131 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8133 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8134 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8135 DAG.getIntPtrConstant(0));
8137 // Or the load with the bias.
8138 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8139 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8140 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8142 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8143 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8144 MVT::v2f64, Bias)));
8145 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8146 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8147 DAG.getIntPtrConstant(0));
8149 // Subtract the bias.
8150 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8152 // Handle final rounding.
8153 EVT DestVT = Op.getValueType();
8155 if (DestVT.bitsLT(MVT::f64))
8156 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8157 DAG.getIntPtrConstant(0));
8158 if (DestVT.bitsGT(MVT::f64))
8159 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8161 // Handle final rounding.
8165 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8166 SelectionDAG &DAG) const {
8167 SDValue N0 = Op.getOperand(0);
8168 EVT SVT = N0.getValueType();
8169 DebugLoc dl = Op.getDebugLoc();
8171 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8172 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8173 "Custom UINT_TO_FP is not supported!");
8175 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8176 SVT.getVectorNumElements());
8177 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8178 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8181 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8182 SelectionDAG &DAG) const {
8183 SDValue N0 = Op.getOperand(0);
8184 DebugLoc dl = Op.getDebugLoc();
8186 if (Op.getValueType().isVector())
8187 return lowerUINT_TO_FP_vec(Op, DAG);
8189 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8190 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8191 // the optimization here.
8192 if (DAG.SignBitIsZero(N0))
8193 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8195 EVT SrcVT = N0.getValueType();
8196 EVT DstVT = Op.getValueType();
8197 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8198 return LowerUINT_TO_FP_i64(Op, DAG);
8199 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8200 return LowerUINT_TO_FP_i32(Op, DAG);
8201 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8204 // Make a 64-bit buffer, and use it to build an FILD.
8205 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8206 if (SrcVT == MVT::i32) {
8207 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8208 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8209 getPointerTy(), StackSlot, WordOff);
8210 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8211 StackSlot, MachinePointerInfo(),
8213 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8214 OffsetSlot, MachinePointerInfo(),
8216 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8220 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8221 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8222 StackSlot, MachinePointerInfo(),
8224 // For i64 source, we need to add the appropriate power of 2 if the input
8225 // was negative. This is the same as the optimization in
8226 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8227 // we must be careful to do the computation in x87 extended precision, not
8228 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8229 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8230 MachineMemOperand *MMO =
8231 DAG.getMachineFunction()
8232 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8233 MachineMemOperand::MOLoad, 8, 8);
8235 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8236 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8237 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8238 array_lengthof(Ops), MVT::i64, MMO);
8240 APInt FF(32, 0x5F800000ULL);
8242 // Check whether the sign bit is set.
8243 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
8244 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8247 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8248 SDValue FudgePtr = DAG.getConstantPool(
8249 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8252 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8253 SDValue Zero = DAG.getIntPtrConstant(0);
8254 SDValue Four = DAG.getIntPtrConstant(4);
8255 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8257 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8259 // Load the value out, extending it from f32 to f80.
8260 // FIXME: Avoid the extend by constructing the right constant pool?
8261 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8262 FudgePtr, MachinePointerInfo::getConstantPool(),
8263 MVT::f32, false, false, 4);
8264 // Extend everything to 80 bits to force it to be done on x87.
8265 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8266 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8269 std::pair<SDValue,SDValue>
8270 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8271 bool IsSigned, bool IsReplace) const {
8272 DebugLoc DL = Op.getDebugLoc();
8274 EVT DstTy = Op.getValueType();
8276 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8277 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8281 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8282 DstTy.getSimpleVT() >= MVT::i16 &&
8283 "Unknown FP_TO_INT to lower!");
8285 // These are really Legal.
8286 if (DstTy == MVT::i32 &&
8287 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8288 return std::make_pair(SDValue(), SDValue());
8289 if (Subtarget->is64Bit() &&
8290 DstTy == MVT::i64 &&
8291 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8292 return std::make_pair(SDValue(), SDValue());
8294 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8295 // stack slot, or into the FTOL runtime function.
8296 MachineFunction &MF = DAG.getMachineFunction();
8297 unsigned MemSize = DstTy.getSizeInBits()/8;
8298 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8299 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8302 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8303 Opc = X86ISD::WIN_FTOL;
8305 switch (DstTy.getSimpleVT().SimpleTy) {
8306 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8307 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8308 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8309 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8312 SDValue Chain = DAG.getEntryNode();
8313 SDValue Value = Op.getOperand(0);
8314 EVT TheVT = Op.getOperand(0).getValueType();
8315 // FIXME This causes a redundant load/store if the SSE-class value is already
8316 // in memory, such as if it is on the callstack.
8317 if (isScalarFPTypeInSSEReg(TheVT)) {
8318 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8319 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8320 MachinePointerInfo::getFixedStack(SSFI),
8322 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8324 Chain, StackSlot, DAG.getValueType(TheVT)
8327 MachineMemOperand *MMO =
8328 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8329 MachineMemOperand::MOLoad, MemSize, MemSize);
8330 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8331 array_lengthof(Ops), DstTy, MMO);
8332 Chain = Value.getValue(1);
8333 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8334 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8337 MachineMemOperand *MMO =
8338 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8339 MachineMemOperand::MOStore, MemSize, MemSize);
8341 if (Opc != X86ISD::WIN_FTOL) {
8342 // Build the FP_TO_INT*_IN_MEM
8343 SDValue Ops[] = { Chain, Value, StackSlot };
8344 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8345 Ops, array_lengthof(Ops), DstTy,
8347 return std::make_pair(FIST, StackSlot);
8349 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8350 DAG.getVTList(MVT::Other, MVT::Glue),
8352 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8353 MVT::i32, ftol.getValue(1));
8354 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8355 MVT::i32, eax.getValue(2));
8356 SDValue Ops[] = { eax, edx };
8357 SDValue pair = IsReplace
8358 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8359 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8360 return std::make_pair(pair, SDValue());
8364 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8365 const X86Subtarget *Subtarget) {
8366 MVT VT = Op->getValueType(0).getSimpleVT();
8367 SDValue In = Op->getOperand(0);
8368 MVT InVT = In.getValueType().getSimpleVT();
8369 DebugLoc dl = Op->getDebugLoc();
8371 // Optimize vectors in AVX mode:
8374 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8375 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8376 // Concat upper and lower parts.
8379 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8380 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8381 // Concat upper and lower parts.
8384 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8385 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8388 if (Subtarget->hasInt256())
8389 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8391 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8392 SDValue Undef = DAG.getUNDEF(InVT);
8393 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8394 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8395 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8397 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8398 VT.getVectorNumElements()/2);
8400 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8401 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8403 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8406 SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
8407 SelectionDAG &DAG) const {
8408 if (Subtarget->hasFp256()) {
8409 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8416 SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
8417 SelectionDAG &DAG) const {
8418 DebugLoc DL = Op.getDebugLoc();
8419 MVT VT = Op.getValueType().getSimpleVT();
8420 SDValue In = Op.getOperand(0);
8421 MVT SVT = In.getValueType().getSimpleVT();
8423 if (Subtarget->hasFp256()) {
8424 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8429 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8430 VT.getVectorNumElements() != SVT.getVectorNumElements())
8433 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8435 // AVX2 has better support of integer extending.
8436 if (Subtarget->hasInt256())
8437 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8439 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8440 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8441 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8442 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8443 DAG.getUNDEF(MVT::v8i16),
8446 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8449 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8450 DebugLoc DL = Op.getDebugLoc();
8451 MVT VT = Op.getValueType().getSimpleVT();
8452 SDValue In = Op.getOperand(0);
8453 MVT SVT = In.getValueType().getSimpleVT();
8455 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8456 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8457 if (Subtarget->hasInt256()) {
8458 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8459 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8460 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8462 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8463 DAG.getIntPtrConstant(0));
8466 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8467 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8468 DAG.getIntPtrConstant(0));
8469 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8470 DAG.getIntPtrConstant(2));
8472 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8473 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8476 static const int ShufMask1[] = {0, 2, 0, 0};
8477 SDValue Undef = DAG.getUNDEF(VT);
8478 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8479 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8481 // The MOVLHPS mask:
8482 static const int ShufMask2[] = {0, 1, 4, 5};
8483 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8486 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8487 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8488 if (Subtarget->hasInt256()) {
8489 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8491 SmallVector<SDValue,32> pshufbMask;
8492 for (unsigned i = 0; i < 2; ++i) {
8493 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8494 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8495 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8496 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8497 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8498 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8499 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8500 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8501 for (unsigned j = 0; j < 8; ++j)
8502 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8504 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8505 &pshufbMask[0], 32);
8506 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8507 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8509 static const int ShufMask[] = {0, 2, -1, -1};
8510 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8512 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8513 DAG.getIntPtrConstant(0));
8514 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8517 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8518 DAG.getIntPtrConstant(0));
8520 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8521 DAG.getIntPtrConstant(4));
8523 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8524 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8527 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8528 -1, -1, -1, -1, -1, -1, -1, -1};
8530 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8531 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8532 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8534 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8535 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8537 // The MOVLHPS Mask:
8538 static const int ShufMask2[] = {0, 1, 4, 5};
8539 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8540 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8543 // Handle truncation of V256 to V128 using shuffles.
8544 if (!VT.is128BitVector() || !SVT.is256BitVector())
8547 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8549 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8551 unsigned NumElems = VT.getVectorNumElements();
8552 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8555 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8556 // Prepare truncation shuffle mask
8557 for (unsigned i = 0; i != NumElems; ++i)
8559 SDValue V = DAG.getVectorShuffle(NVT, DL,
8560 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8561 DAG.getUNDEF(NVT), &MaskVec[0]);
8562 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8563 DAG.getIntPtrConstant(0));
8566 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8567 SelectionDAG &DAG) const {
8568 MVT VT = Op.getValueType().getSimpleVT();
8569 if (VT.isVector()) {
8570 if (VT == MVT::v8i16)
8571 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), VT,
8572 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8573 MVT::v8i32, Op.getOperand(0)));
8577 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8578 /*IsSigned=*/ true, /*IsReplace=*/ false);
8579 SDValue FIST = Vals.first, StackSlot = Vals.second;
8580 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8581 if (FIST.getNode() == 0) return Op;
8583 if (StackSlot.getNode())
8585 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8586 FIST, StackSlot, MachinePointerInfo(),
8587 false, false, false, 0);
8589 // The node is the result.
8593 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8594 SelectionDAG &DAG) const {
8595 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8596 /*IsSigned=*/ false, /*IsReplace=*/ false);
8597 SDValue FIST = Vals.first, StackSlot = Vals.second;
8598 assert(FIST.getNode() && "Unexpected failure");
8600 if (StackSlot.getNode())
8602 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8603 FIST, StackSlot, MachinePointerInfo(),
8604 false, false, false, 0);
8606 // The node is the result.
8610 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
8611 DebugLoc DL = Op.getDebugLoc();
8612 MVT VT = Op.getValueType().getSimpleVT();
8613 SDValue In = Op.getOperand(0);
8614 MVT SVT = In.getValueType().getSimpleVT();
8616 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8618 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8619 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8620 In, DAG.getUNDEF(SVT)));
8623 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8624 LLVMContext *Context = DAG.getContext();
8625 DebugLoc dl = Op.getDebugLoc();
8626 MVT VT = Op.getValueType().getSimpleVT();
8628 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8629 if (VT.isVector()) {
8630 EltVT = VT.getVectorElementType();
8631 NumElts = VT.getVectorNumElements();
8634 if (EltVT == MVT::f64)
8635 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8636 APInt(64, ~(1ULL << 63))));
8638 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8639 APInt(32, ~(1U << 31))));
8640 C = ConstantVector::getSplat(NumElts, C);
8641 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8642 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8643 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8644 MachinePointerInfo::getConstantPool(),
8645 false, false, false, Alignment);
8646 if (VT.isVector()) {
8647 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8648 return DAG.getNode(ISD::BITCAST, dl, VT,
8649 DAG.getNode(ISD::AND, dl, ANDVT,
8650 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8652 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8654 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8657 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8658 LLVMContext *Context = DAG.getContext();
8659 DebugLoc dl = Op.getDebugLoc();
8660 MVT VT = Op.getValueType().getSimpleVT();
8662 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8663 if (VT.isVector()) {
8664 EltVT = VT.getVectorElementType();
8665 NumElts = VT.getVectorNumElements();
8668 if (EltVT == MVT::f64)
8669 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8670 APInt(64, 1ULL << 63)));
8672 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8673 APInt(32, 1U << 31)));
8674 C = ConstantVector::getSplat(NumElts, C);
8675 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8676 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8677 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8678 MachinePointerInfo::getConstantPool(),
8679 false, false, false, Alignment);
8680 if (VT.isVector()) {
8681 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8682 return DAG.getNode(ISD::BITCAST, dl, VT,
8683 DAG.getNode(ISD::XOR, dl, XORVT,
8684 DAG.getNode(ISD::BITCAST, dl, XORVT,
8686 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8689 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8692 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8693 LLVMContext *Context = DAG.getContext();
8694 SDValue Op0 = Op.getOperand(0);
8695 SDValue Op1 = Op.getOperand(1);
8696 DebugLoc dl = Op.getDebugLoc();
8697 MVT VT = Op.getValueType().getSimpleVT();
8698 MVT SrcVT = Op1.getValueType().getSimpleVT();
8700 // If second operand is smaller, extend it first.
8701 if (SrcVT.bitsLT(VT)) {
8702 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8705 // And if it is bigger, shrink it first.
8706 if (SrcVT.bitsGT(VT)) {
8707 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8711 // At this point the operands and the result should have the same
8712 // type, and that won't be f80 since that is not custom lowered.
8714 // First get the sign bit of second operand.
8715 SmallVector<Constant*,4> CV;
8716 if (SrcVT == MVT::f64) {
8717 const fltSemantics &Sem = APFloat::IEEEdouble;
8718 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
8719 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
8721 const fltSemantics &Sem = APFloat::IEEEsingle;
8722 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
8723 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8724 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8725 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8727 Constant *C = ConstantVector::get(CV);
8728 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8729 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8730 MachinePointerInfo::getConstantPool(),
8731 false, false, false, 16);
8732 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8734 // Shift sign bit right or left if the two operands have different types.
8735 if (SrcVT.bitsGT(VT)) {
8736 // Op0 is MVT::f32, Op1 is MVT::f64.
8737 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8738 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8739 DAG.getConstant(32, MVT::i32));
8740 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8741 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8742 DAG.getIntPtrConstant(0));
8745 // Clear first operand sign bit.
8747 if (VT == MVT::f64) {
8748 const fltSemantics &Sem = APFloat::IEEEdouble;
8749 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
8750 APInt(64, ~(1ULL << 63)))));
8751 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
8753 const fltSemantics &Sem = APFloat::IEEEsingle;
8754 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
8755 APInt(32, ~(1U << 31)))));
8756 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8757 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8758 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8760 C = ConstantVector::get(CV);
8761 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8762 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8763 MachinePointerInfo::getConstantPool(),
8764 false, false, false, 16);
8765 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8767 // Or the value with the sign bit.
8768 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8771 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
8772 SDValue N0 = Op.getOperand(0);
8773 DebugLoc dl = Op.getDebugLoc();
8774 MVT VT = Op.getValueType().getSimpleVT();
8776 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8777 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8778 DAG.getConstant(1, VT));
8779 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8782 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
8784 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op,
8785 SelectionDAG &DAG) const {
8786 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8788 if (!Subtarget->hasSSE41())
8791 if (!Op->hasOneUse())
8794 SDNode *N = Op.getNode();
8795 DebugLoc DL = N->getDebugLoc();
8797 SmallVector<SDValue, 8> Opnds;
8798 DenseMap<SDValue, unsigned> VecInMap;
8799 EVT VT = MVT::Other;
8801 // Recognize a special case where a vector is casted into wide integer to
8803 Opnds.push_back(N->getOperand(0));
8804 Opnds.push_back(N->getOperand(1));
8806 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
8807 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot;
8808 // BFS traverse all OR'd operands.
8809 if (I->getOpcode() == ISD::OR) {
8810 Opnds.push_back(I->getOperand(0));
8811 Opnds.push_back(I->getOperand(1));
8812 // Re-evaluate the number of nodes to be traversed.
8813 e += 2; // 2 more nodes (LHS and RHS) are pushed.
8817 // Quit if a non-EXTRACT_VECTOR_ELT
8818 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8821 // Quit if without a constant index.
8822 SDValue Idx = I->getOperand(1);
8823 if (!isa<ConstantSDNode>(Idx))
8826 SDValue ExtractedFromVec = I->getOperand(0);
8827 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
8828 if (M == VecInMap.end()) {
8829 VT = ExtractedFromVec.getValueType();
8830 // Quit if not 128/256-bit vector.
8831 if (!VT.is128BitVector() && !VT.is256BitVector())
8833 // Quit if not the same type.
8834 if (VecInMap.begin() != VecInMap.end() &&
8835 VT != VecInMap.begin()->first.getValueType())
8837 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
8839 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
8842 assert((VT.is128BitVector() || VT.is256BitVector()) &&
8843 "Not extracted from 128-/256-bit vector.");
8845 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
8846 SmallVector<SDValue, 8> VecIns;
8848 for (DenseMap<SDValue, unsigned>::const_iterator
8849 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
8850 // Quit if not all elements are used.
8851 if (I->second != FullMask)
8853 VecIns.push_back(I->first);
8856 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8858 // Cast all vectors into TestVT for PTEST.
8859 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
8860 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8862 // If more than one full vectors are evaluated, OR them first before PTEST.
8863 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
8864 // Each iteration will OR 2 nodes and append the result until there is only
8865 // 1 node left, i.e. the final OR'd value of all vectors.
8866 SDValue LHS = VecIns[Slot];
8867 SDValue RHS = VecIns[Slot + 1];
8868 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8871 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
8872 VecIns.back(), VecIns.back());
8875 /// Emit nodes that will be selected as "test Op0,Op0", or something
8877 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8878 SelectionDAG &DAG) const {
8879 DebugLoc dl = Op.getDebugLoc();
8881 // CF and OF aren't always set the way we want. Determine which
8882 // of these we need.
8883 bool NeedCF = false;
8884 bool NeedOF = false;
8887 case X86::COND_A: case X86::COND_AE:
8888 case X86::COND_B: case X86::COND_BE:
8891 case X86::COND_G: case X86::COND_GE:
8892 case X86::COND_L: case X86::COND_LE:
8893 case X86::COND_O: case X86::COND_NO:
8898 // See if we can use the EFLAGS value from the operand instead of
8899 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8900 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8901 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8902 // Emit a CMP with 0, which is the TEST pattern.
8903 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8904 DAG.getConstant(0, Op.getValueType()));
8906 unsigned Opcode = 0;
8907 unsigned NumOperands = 0;
8909 // Truncate operations may prevent the merge of the SETCC instruction
8910 // and the arithmetic intruction before it. Attempt to truncate the operands
8911 // of the arithmetic instruction and use a reduced bit-width instruction.
8912 bool NeedTruncation = false;
8913 SDValue ArithOp = Op;
8914 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8915 SDValue Arith = Op->getOperand(0);
8916 // Both the trunc and the arithmetic op need to have one user each.
8917 if (Arith->hasOneUse())
8918 switch (Arith.getOpcode()) {
8925 NeedTruncation = true;
8931 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8932 // which may be the result of a CAST. We use the variable 'Op', which is the
8933 // non-casted variable when we check for possible users.
8934 switch (ArithOp.getOpcode()) {
8936 // Due to an isel shortcoming, be conservative if this add is likely to be
8937 // selected as part of a load-modify-store instruction. When the root node
8938 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8939 // uses of other nodes in the match, such as the ADD in this case. This
8940 // leads to the ADD being left around and reselected, with the result being
8941 // two adds in the output. Alas, even if none our users are stores, that
8942 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8943 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8944 // climbing the DAG back to the root, and it doesn't seem to be worth the
8946 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8947 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8948 if (UI->getOpcode() != ISD::CopyToReg &&
8949 UI->getOpcode() != ISD::SETCC &&
8950 UI->getOpcode() != ISD::STORE)
8953 if (ConstantSDNode *C =
8954 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8955 // An add of one will be selected as an INC.
8956 if (C->getAPIntValue() == 1) {
8957 Opcode = X86ISD::INC;
8962 // An add of negative one (subtract of one) will be selected as a DEC.
8963 if (C->getAPIntValue().isAllOnesValue()) {
8964 Opcode = X86ISD::DEC;
8970 // Otherwise use a regular EFLAGS-setting add.
8971 Opcode = X86ISD::ADD;
8975 // If the primary and result isn't used, don't bother using X86ISD::AND,
8976 // because a TEST instruction will be better.
8977 bool NonFlagUse = false;
8978 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8979 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8981 unsigned UOpNo = UI.getOperandNo();
8982 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8983 // Look pass truncate.
8984 UOpNo = User->use_begin().getOperandNo();
8985 User = *User->use_begin();
8988 if (User->getOpcode() != ISD::BRCOND &&
8989 User->getOpcode() != ISD::SETCC &&
8990 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9003 // Due to the ISEL shortcoming noted above, be conservative if this op is
9004 // likely to be selected as part of a load-modify-store instruction.
9005 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9006 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9007 if (UI->getOpcode() == ISD::STORE)
9010 // Otherwise use a regular EFLAGS-setting instruction.
9011 switch (ArithOp.getOpcode()) {
9012 default: llvm_unreachable("unexpected operator!");
9013 case ISD::SUB: Opcode = X86ISD::SUB; break;
9014 case ISD::XOR: Opcode = X86ISD::XOR; break;
9015 case ISD::AND: Opcode = X86ISD::AND; break;
9017 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9018 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
9019 if (EFLAGS.getNode())
9022 Opcode = X86ISD::OR;
9036 return SDValue(Op.getNode(), 1);
9042 // If we found that truncation is beneficial, perform the truncation and
9044 if (NeedTruncation) {
9045 EVT VT = Op.getValueType();
9046 SDValue WideVal = Op->getOperand(0);
9047 EVT WideVT = WideVal.getValueType();
9048 unsigned ConvertedOp = 0;
9049 // Use a target machine opcode to prevent further DAGCombine
9050 // optimizations that may separate the arithmetic operations
9051 // from the setcc node.
9052 switch (WideVal.getOpcode()) {
9054 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9055 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9056 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9057 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9058 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9063 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9064 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9065 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9066 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9072 // Emit a CMP with 0, which is the TEST pattern.
9073 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9074 DAG.getConstant(0, Op.getValueType()));
9076 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9077 SmallVector<SDValue, 4> Ops;
9078 for (unsigned i = 0; i != NumOperands; ++i)
9079 Ops.push_back(Op.getOperand(i));
9081 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9082 DAG.ReplaceAllUsesWith(Op, New);
9083 return SDValue(New.getNode(), 1);
9086 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9088 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9089 SelectionDAG &DAG) const {
9090 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9091 if (C->getAPIntValue() == 0)
9092 return EmitTest(Op0, X86CC, DAG);
9094 DebugLoc dl = Op0.getDebugLoc();
9095 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9096 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9097 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9098 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9099 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9101 return SDValue(Sub.getNode(), 1);
9103 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9106 /// Convert a comparison if required by the subtarget.
9107 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9108 SelectionDAG &DAG) const {
9109 // If the subtarget does not support the FUCOMI instruction, floating-point
9110 // comparisons have to be converted.
9111 if (Subtarget->hasCMov() ||
9112 Cmp.getOpcode() != X86ISD::CMP ||
9113 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9114 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9117 // The instruction selector will select an FUCOM instruction instead of
9118 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9119 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9120 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9121 DebugLoc dl = Cmp.getDebugLoc();
9122 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9123 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9124 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9125 DAG.getConstant(8, MVT::i8));
9126 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9127 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9130 static bool isAllOnes(SDValue V) {
9131 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9132 return C && C->isAllOnesValue();
9135 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9136 /// if it's possible.
9137 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9138 DebugLoc dl, SelectionDAG &DAG) const {
9139 SDValue Op0 = And.getOperand(0);
9140 SDValue Op1 = And.getOperand(1);
9141 if (Op0.getOpcode() == ISD::TRUNCATE)
9142 Op0 = Op0.getOperand(0);
9143 if (Op1.getOpcode() == ISD::TRUNCATE)
9144 Op1 = Op1.getOperand(0);
9147 if (Op1.getOpcode() == ISD::SHL)
9148 std::swap(Op0, Op1);
9149 if (Op0.getOpcode() == ISD::SHL) {
9150 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9151 if (And00C->getZExtValue() == 1) {
9152 // If we looked past a truncate, check that it's only truncating away
9154 unsigned BitWidth = Op0.getValueSizeInBits();
9155 unsigned AndBitWidth = And.getValueSizeInBits();
9156 if (BitWidth > AndBitWidth) {
9158 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9159 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9163 RHS = Op0.getOperand(1);
9165 } else if (Op1.getOpcode() == ISD::Constant) {
9166 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9167 uint64_t AndRHSVal = AndRHS->getZExtValue();
9168 SDValue AndLHS = Op0;
9170 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9171 LHS = AndLHS.getOperand(0);
9172 RHS = AndLHS.getOperand(1);
9175 // Use BT if the immediate can't be encoded in a TEST instruction.
9176 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9178 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9182 if (LHS.getNode()) {
9183 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip
9184 // the condition code later.
9185 bool Invert = false;
9186 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
9188 LHS = LHS.getOperand(0);
9191 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9192 // instruction. Since the shift amount is in-range-or-undefined, we know
9193 // that doing a bittest on the i32 value is ok. We extend to i32 because
9194 // the encoding for the i16 version is larger than the i32 version.
9195 // Also promote i16 to i32 for performance / code size reason.
9196 if (LHS.getValueType() == MVT::i8 ||
9197 LHS.getValueType() == MVT::i16)
9198 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9200 // If the operand types disagree, extend the shift amount to match. Since
9201 // BT ignores high bits (like shifts) we can use anyextend.
9202 if (LHS.getValueType() != RHS.getValueType())
9203 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9205 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9206 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9207 // Flip the condition if the LHS was a not instruction
9209 Cond = X86::GetOppositeBranchCondition(Cond);
9210 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9211 DAG.getConstant(Cond, MVT::i8), BT);
9217 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9218 // ones, and then concatenate the result back.
9219 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9220 MVT VT = Op.getValueType().getSimpleVT();
9222 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9223 "Unsupported value type for operation");
9225 unsigned NumElems = VT.getVectorNumElements();
9226 DebugLoc dl = Op.getDebugLoc();
9227 SDValue CC = Op.getOperand(2);
9229 // Extract the LHS vectors
9230 SDValue LHS = Op.getOperand(0);
9231 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9232 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9234 // Extract the RHS vectors
9235 SDValue RHS = Op.getOperand(1);
9236 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9237 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9239 // Issue the operation on the smaller types and concatenate the result back
9240 MVT EltVT = VT.getVectorElementType();
9241 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9242 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9243 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9244 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9247 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9248 SelectionDAG &DAG) {
9250 SDValue Op0 = Op.getOperand(0);
9251 SDValue Op1 = Op.getOperand(1);
9252 SDValue CC = Op.getOperand(2);
9253 MVT VT = Op.getValueType().getSimpleVT();
9254 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9255 bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint();
9256 DebugLoc dl = Op.getDebugLoc();
9260 MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
9261 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9267 // SSE Condition code mapping:
9276 switch (SetCCOpcode) {
9277 default: llvm_unreachable("Unexpected SETCC condition");
9279 case ISD::SETEQ: SSECC = 0; break;
9281 case ISD::SETGT: Swap = true; // Fallthrough
9283 case ISD::SETOLT: SSECC = 1; break;
9285 case ISD::SETGE: Swap = true; // Fallthrough
9287 case ISD::SETOLE: SSECC = 2; break;
9288 case ISD::SETUO: SSECC = 3; break;
9290 case ISD::SETNE: SSECC = 4; break;
9291 case ISD::SETULE: Swap = true; // Fallthrough
9292 case ISD::SETUGE: SSECC = 5; break;
9293 case ISD::SETULT: Swap = true; // Fallthrough
9294 case ISD::SETUGT: SSECC = 6; break;
9295 case ISD::SETO: SSECC = 7; break;
9297 case ISD::SETONE: SSECC = 8; break;
9300 std::swap(Op0, Op1);
9302 // In the two special cases we can't handle, emit two comparisons.
9305 unsigned CombineOpc;
9306 if (SetCCOpcode == ISD::SETUEQ) {
9307 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9309 assert(SetCCOpcode == ISD::SETONE);
9310 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9313 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9314 DAG.getConstant(CC0, MVT::i8));
9315 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9316 DAG.getConstant(CC1, MVT::i8));
9317 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9319 // Handle all other FP comparisons here.
9320 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9321 DAG.getConstant(SSECC, MVT::i8));
9324 // Break 256-bit integer vector compare into smaller ones.
9325 if (VT.is256BitVector() && !Subtarget->hasInt256())
9326 return Lower256IntVSETCC(Op, DAG);
9328 // We are handling one of the integer comparisons here. Since SSE only has
9329 // GT and EQ comparisons for integer, swapping operands and multiple
9330 // operations may be required for some comparisons.
9332 bool Swap = false, Invert = false, FlipSigns = false;
9334 switch (SetCCOpcode) {
9335 default: llvm_unreachable("Unexpected SETCC condition");
9336 case ISD::SETNE: Invert = true;
9337 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9338 case ISD::SETLT: Swap = true;
9339 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9340 case ISD::SETGE: Swap = true;
9341 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9342 case ISD::SETULT: Swap = true;
9343 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9344 case ISD::SETUGE: Swap = true;
9345 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9348 std::swap(Op0, Op1);
9350 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9351 // bits of the inputs before performing those operations.
9353 EVT EltVT = VT.getVectorElementType();
9354 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
9356 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
9357 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9359 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9360 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9363 // Check that the operation in question is available (most are plain SSE2,
9364 // but PCMPGTQ and PCMPEQQ have different requirements).
9365 if (VT == MVT::v2i64) {
9366 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9367 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9369 // First cast everything to the right type,
9370 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9371 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9373 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9374 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9375 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9377 // Create masks for only the low parts/high parts of the 64 bit integers.
9378 const int MaskHi[] = { 1, 1, 3, 3 };
9379 const int MaskLo[] = { 0, 0, 2, 2 };
9380 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9381 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9382 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9384 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9385 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9388 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9390 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9393 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9394 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9395 // pcmpeqd + pshufd + pand.
9396 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9398 // First cast everything to the right type,
9399 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9400 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9403 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9405 // Make sure the lower and upper halves are both all-ones.
9406 const int Mask[] = { 1, 0, 3, 2 };
9407 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9408 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9411 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9413 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9417 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9419 // If the logical-not of the result is required, perform that now.
9421 Result = DAG.getNOT(dl, Result, VT);
9426 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9428 MVT VT = Op.getValueType().getSimpleVT();
9430 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9432 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9433 SDValue Op0 = Op.getOperand(0);
9434 SDValue Op1 = Op.getOperand(1);
9435 DebugLoc dl = Op.getDebugLoc();
9436 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9438 // Optimize to BT if possible.
9439 // Lower (X & (1 << N)) == 0 to BT(X, N).
9440 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9441 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9442 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9443 Op1.getOpcode() == ISD::Constant &&
9444 cast<ConstantSDNode>(Op1)->isNullValue() &&
9445 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9446 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9447 if (NewSetCC.getNode())
9451 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9453 if (Op1.getOpcode() == ISD::Constant &&
9454 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9455 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9456 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9458 // If the input is a setcc, then reuse the input setcc or use a new one with
9459 // the inverted condition.
9460 if (Op0.getOpcode() == X86ISD::SETCC) {
9461 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9462 bool Invert = (CC == ISD::SETNE) ^
9463 cast<ConstantSDNode>(Op1)->isNullValue();
9464 if (!Invert) return Op0;
9466 CCode = X86::GetOppositeBranchCondition(CCode);
9467 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9468 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9472 bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint();
9473 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9474 if (X86CC == X86::COND_INVALID)
9477 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9478 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9479 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9480 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9483 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9484 static bool isX86LogicalCmp(SDValue Op) {
9485 unsigned Opc = Op.getNode()->getOpcode();
9486 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9487 Opc == X86ISD::SAHF)
9489 if (Op.getResNo() == 1 &&
9490 (Opc == X86ISD::ADD ||
9491 Opc == X86ISD::SUB ||
9492 Opc == X86ISD::ADC ||
9493 Opc == X86ISD::SBB ||
9494 Opc == X86ISD::SMUL ||
9495 Opc == X86ISD::UMUL ||
9496 Opc == X86ISD::INC ||
9497 Opc == X86ISD::DEC ||
9498 Opc == X86ISD::OR ||
9499 Opc == X86ISD::XOR ||
9500 Opc == X86ISD::AND))
9503 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9509 static bool isZero(SDValue V) {
9510 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9511 return C && C->isNullValue();
9514 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9515 if (V.getOpcode() != ISD::TRUNCATE)
9518 SDValue VOp0 = V.getOperand(0);
9519 unsigned InBits = VOp0.getValueSizeInBits();
9520 unsigned Bits = V.getValueSizeInBits();
9521 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9524 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9525 bool addTest = true;
9526 SDValue Cond = Op.getOperand(0);
9527 SDValue Op1 = Op.getOperand(1);
9528 SDValue Op2 = Op.getOperand(2);
9529 DebugLoc DL = Op.getDebugLoc();
9532 if (Cond.getOpcode() == ISD::SETCC) {
9533 SDValue NewCond = LowerSETCC(Cond, DAG);
9534 if (NewCond.getNode())
9538 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9539 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9540 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9541 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9542 if (Cond.getOpcode() == X86ISD::SETCC &&
9543 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9544 isZero(Cond.getOperand(1).getOperand(1))) {
9545 SDValue Cmp = Cond.getOperand(1);
9547 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9549 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9550 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9551 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9553 SDValue CmpOp0 = Cmp.getOperand(0);
9554 // Apply further optimizations for special cases
9555 // (select (x != 0), -1, 0) -> neg & sbb
9556 // (select (x == 0), 0, -1) -> neg & sbb
9557 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9558 if (YC->isNullValue() &&
9559 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9560 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9561 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9562 DAG.getConstant(0, CmpOp0.getValueType()),
9564 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9565 DAG.getConstant(X86::COND_B, MVT::i8),
9566 SDValue(Neg.getNode(), 1));
9570 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9571 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9572 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9574 SDValue Res = // Res = 0 or -1.
9575 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9576 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9578 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9579 Res = DAG.getNOT(DL, Res, Res.getValueType());
9581 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9582 if (N2C == 0 || !N2C->isNullValue())
9583 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9588 // Look past (and (setcc_carry (cmp ...)), 1).
9589 if (Cond.getOpcode() == ISD::AND &&
9590 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9591 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9592 if (C && C->getAPIntValue() == 1)
9593 Cond = Cond.getOperand(0);
9596 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9597 // setting operand in place of the X86ISD::SETCC.
9598 unsigned CondOpcode = Cond.getOpcode();
9599 if (CondOpcode == X86ISD::SETCC ||
9600 CondOpcode == X86ISD::SETCC_CARRY) {
9601 CC = Cond.getOperand(0);
9603 SDValue Cmp = Cond.getOperand(1);
9604 unsigned Opc = Cmp.getOpcode();
9605 MVT VT = Op.getValueType().getSimpleVT();
9607 bool IllegalFPCMov = false;
9608 if (VT.isFloatingPoint() && !VT.isVector() &&
9609 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9610 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9612 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9613 Opc == X86ISD::BT) { // FIXME
9617 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9618 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9619 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9620 Cond.getOperand(0).getValueType() != MVT::i8)) {
9621 SDValue LHS = Cond.getOperand(0);
9622 SDValue RHS = Cond.getOperand(1);
9626 switch (CondOpcode) {
9627 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9628 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9629 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9630 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9631 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9632 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9633 default: llvm_unreachable("unexpected overflowing operator");
9635 if (CondOpcode == ISD::UMULO)
9636 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9639 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9641 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9643 if (CondOpcode == ISD::UMULO)
9644 Cond = X86Op.getValue(2);
9646 Cond = X86Op.getValue(1);
9648 CC = DAG.getConstant(X86Cond, MVT::i8);
9653 // Look pass the truncate if the high bits are known zero.
9654 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9655 Cond = Cond.getOperand(0);
9657 // We know the result of AND is compared against zero. Try to match
9659 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9660 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9661 if (NewSetCC.getNode()) {
9662 CC = NewSetCC.getOperand(0);
9663 Cond = NewSetCC.getOperand(1);
9670 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9671 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9674 // a < b ? -1 : 0 -> RES = ~setcc_carry
9675 // a < b ? 0 : -1 -> RES = setcc_carry
9676 // a >= b ? -1 : 0 -> RES = setcc_carry
9677 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9678 if (Cond.getOpcode() == X86ISD::SUB) {
9679 Cond = ConvertCmpIfNecessary(Cond, DAG);
9680 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9682 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9683 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9684 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9685 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9686 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9687 return DAG.getNOT(DL, Res, Res.getValueType());
9692 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9693 // widen the cmov and push the truncate through. This avoids introducing a new
9694 // branch during isel and doesn't add any extensions.
9695 if (Op.getValueType() == MVT::i8 &&
9696 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9697 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
9698 if (T1.getValueType() == T2.getValueType() &&
9699 // Blacklist CopyFromReg to avoid partial register stalls.
9700 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9701 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
9702 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
9703 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9707 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9708 // condition is true.
9709 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9710 SDValue Ops[] = { Op2, Op1, CC, Cond };
9711 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9714 SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
9715 SelectionDAG &DAG) const {
9716 MVT VT = Op->getValueType(0).getSimpleVT();
9717 SDValue In = Op->getOperand(0);
9718 MVT InVT = In.getValueType().getSimpleVT();
9719 DebugLoc dl = Op->getDebugLoc();
9721 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
9722 (VT != MVT::v8i32 || InVT != MVT::v8i16))
9725 if (Subtarget->hasInt256())
9726 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
9728 // Optimize vectors in AVX mode
9729 // Sign extend v8i16 to v8i32 and
9732 // Divide input vector into two parts
9733 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
9734 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
9735 // concat the vectors to original VT
9737 unsigned NumElems = InVT.getVectorNumElements();
9738 SDValue Undef = DAG.getUNDEF(InVT);
9740 SmallVector<int,8> ShufMask1(NumElems, -1);
9741 for (unsigned i = 0; i != NumElems/2; ++i)
9744 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
9746 SmallVector<int,8> ShufMask2(NumElems, -1);
9747 for (unsigned i = 0; i != NumElems/2; ++i)
9748 ShufMask2[i] = i + NumElems/2;
9750 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
9752 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
9753 VT.getVectorNumElements()/2);
9755 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
9756 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
9758 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9761 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9762 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9763 // from the AND / OR.
9764 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9765 Opc = Op.getOpcode();
9766 if (Opc != ISD::OR && Opc != ISD::AND)
9768 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9769 Op.getOperand(0).hasOneUse() &&
9770 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9771 Op.getOperand(1).hasOneUse());
9774 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9775 // 1 and that the SETCC node has a single use.
9776 static bool isXor1OfSetCC(SDValue Op) {
9777 if (Op.getOpcode() != ISD::XOR)
9779 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9780 if (N1C && N1C->getAPIntValue() == 1) {
9781 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9782 Op.getOperand(0).hasOneUse();
9787 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9788 bool addTest = true;
9789 SDValue Chain = Op.getOperand(0);
9790 SDValue Cond = Op.getOperand(1);
9791 SDValue Dest = Op.getOperand(2);
9792 DebugLoc dl = Op.getDebugLoc();
9794 bool Inverted = false;
9796 if (Cond.getOpcode() == ISD::SETCC) {
9797 // Check for setcc([su]{add,sub,mul}o == 0).
9798 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9799 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9800 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9801 Cond.getOperand(0).getResNo() == 1 &&
9802 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9803 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9804 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9805 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9806 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9807 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9809 Cond = Cond.getOperand(0);
9811 SDValue NewCond = LowerSETCC(Cond, DAG);
9812 if (NewCond.getNode())
9817 // FIXME: LowerXALUO doesn't handle these!!
9818 else if (Cond.getOpcode() == X86ISD::ADD ||
9819 Cond.getOpcode() == X86ISD::SUB ||
9820 Cond.getOpcode() == X86ISD::SMUL ||
9821 Cond.getOpcode() == X86ISD::UMUL)
9822 Cond = LowerXALUO(Cond, DAG);
9825 // Look pass (and (setcc_carry (cmp ...)), 1).
9826 if (Cond.getOpcode() == ISD::AND &&
9827 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9828 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9829 if (C && C->getAPIntValue() == 1)
9830 Cond = Cond.getOperand(0);
9833 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9834 // setting operand in place of the X86ISD::SETCC.
9835 unsigned CondOpcode = Cond.getOpcode();
9836 if (CondOpcode == X86ISD::SETCC ||
9837 CondOpcode == X86ISD::SETCC_CARRY) {
9838 CC = Cond.getOperand(0);
9840 SDValue Cmp = Cond.getOperand(1);
9841 unsigned Opc = Cmp.getOpcode();
9842 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9843 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9847 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9851 // These can only come from an arithmetic instruction with overflow,
9852 // e.g. SADDO, UADDO.
9853 Cond = Cond.getNode()->getOperand(1);
9859 CondOpcode = Cond.getOpcode();
9860 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9861 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9862 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9863 Cond.getOperand(0).getValueType() != MVT::i8)) {
9864 SDValue LHS = Cond.getOperand(0);
9865 SDValue RHS = Cond.getOperand(1);
9869 switch (CondOpcode) {
9870 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9871 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9872 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9873 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9874 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9875 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9876 default: llvm_unreachable("unexpected overflowing operator");
9879 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9880 if (CondOpcode == ISD::UMULO)
9881 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9884 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9886 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9888 if (CondOpcode == ISD::UMULO)
9889 Cond = X86Op.getValue(2);
9891 Cond = X86Op.getValue(1);
9893 CC = DAG.getConstant(X86Cond, MVT::i8);
9897 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9898 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9899 if (CondOpc == ISD::OR) {
9900 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9901 // two branches instead of an explicit OR instruction with a
9903 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9904 isX86LogicalCmp(Cmp)) {
9905 CC = Cond.getOperand(0).getOperand(0);
9906 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9907 Chain, Dest, CC, Cmp);
9908 CC = Cond.getOperand(1).getOperand(0);
9912 } else { // ISD::AND
9913 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9914 // two branches instead of an explicit AND instruction with a
9915 // separate test. However, we only do this if this block doesn't
9916 // have a fall-through edge, because this requires an explicit
9917 // jmp when the condition is false.
9918 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9919 isX86LogicalCmp(Cmp) &&
9920 Op.getNode()->hasOneUse()) {
9921 X86::CondCode CCode =
9922 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9923 CCode = X86::GetOppositeBranchCondition(CCode);
9924 CC = DAG.getConstant(CCode, MVT::i8);
9925 SDNode *User = *Op.getNode()->use_begin();
9926 // Look for an unconditional branch following this conditional branch.
9927 // We need this because we need to reverse the successors in order
9928 // to implement FCMP_OEQ.
9929 if (User->getOpcode() == ISD::BR) {
9930 SDValue FalseBB = User->getOperand(1);
9932 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9933 assert(NewBR == User);
9937 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9938 Chain, Dest, CC, Cmp);
9939 X86::CondCode CCode =
9940 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9941 CCode = X86::GetOppositeBranchCondition(CCode);
9942 CC = DAG.getConstant(CCode, MVT::i8);
9948 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9949 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9950 // It should be transformed during dag combiner except when the condition
9951 // is set by a arithmetics with overflow node.
9952 X86::CondCode CCode =
9953 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9954 CCode = X86::GetOppositeBranchCondition(CCode);
9955 CC = DAG.getConstant(CCode, MVT::i8);
9956 Cond = Cond.getOperand(0).getOperand(1);
9958 } else if (Cond.getOpcode() == ISD::SETCC &&
9959 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9960 // For FCMP_OEQ, we can emit
9961 // two branches instead of an explicit AND instruction with a
9962 // separate test. However, we only do this if this block doesn't
9963 // have a fall-through edge, because this requires an explicit
9964 // jmp when the condition is false.
9965 if (Op.getNode()->hasOneUse()) {
9966 SDNode *User = *Op.getNode()->use_begin();
9967 // Look for an unconditional branch following this conditional branch.
9968 // We need this because we need to reverse the successors in order
9969 // to implement FCMP_OEQ.
9970 if (User->getOpcode() == ISD::BR) {
9971 SDValue FalseBB = User->getOperand(1);
9973 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9974 assert(NewBR == User);
9978 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9979 Cond.getOperand(0), Cond.getOperand(1));
9980 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9981 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9982 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9983 Chain, Dest, CC, Cmp);
9984 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9989 } else if (Cond.getOpcode() == ISD::SETCC &&
9990 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9991 // For FCMP_UNE, we can emit
9992 // two branches instead of an explicit AND instruction with a
9993 // separate test. However, we only do this if this block doesn't
9994 // have a fall-through edge, because this requires an explicit
9995 // jmp when the condition is false.
9996 if (Op.getNode()->hasOneUse()) {
9997 SDNode *User = *Op.getNode()->use_begin();
9998 // Look for an unconditional branch following this conditional branch.
9999 // We need this because we need to reverse the successors in order
10000 // to implement FCMP_UNE.
10001 if (User->getOpcode() == ISD::BR) {
10002 SDValue FalseBB = User->getOperand(1);
10004 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10005 assert(NewBR == User);
10008 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10009 Cond.getOperand(0), Cond.getOperand(1));
10010 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10011 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10012 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10013 Chain, Dest, CC, Cmp);
10014 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10024 // Look pass the truncate if the high bits are known zero.
10025 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10026 Cond = Cond.getOperand(0);
10028 // We know the result of AND is compared against zero. Try to match
10030 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10031 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10032 if (NewSetCC.getNode()) {
10033 CC = NewSetCC.getOperand(0);
10034 Cond = NewSetCC.getOperand(1);
10041 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10042 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10044 Cond = ConvertCmpIfNecessary(Cond, DAG);
10045 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10046 Chain, Dest, CC, Cond);
10049 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10050 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10051 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10052 // that the guard pages used by the OS virtual memory manager are allocated in
10053 // correct sequence.
10055 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10056 SelectionDAG &DAG) const {
10057 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10058 getTargetMachine().Options.EnableSegmentedStacks) &&
10059 "This should be used only on Windows targets or when segmented stacks "
10061 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10062 DebugLoc dl = Op.getDebugLoc();
10065 SDValue Chain = Op.getOperand(0);
10066 SDValue Size = Op.getOperand(1);
10067 // FIXME: Ensure alignment here
10069 bool Is64Bit = Subtarget->is64Bit();
10070 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10072 if (getTargetMachine().Options.EnableSegmentedStacks) {
10073 MachineFunction &MF = DAG.getMachineFunction();
10074 MachineRegisterInfo &MRI = MF.getRegInfo();
10077 // The 64 bit implementation of segmented stacks needs to clobber both r10
10078 // r11. This makes it impossible to use it along with nested parameters.
10079 const Function *F = MF.getFunction();
10081 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10083 if (I->hasNestAttr())
10084 report_fatal_error("Cannot use segmented stacks with functions that "
10085 "have nested arguments.");
10088 const TargetRegisterClass *AddrRegClass =
10089 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10090 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10091 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10092 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10093 DAG.getRegister(Vreg, SPTy));
10094 SDValue Ops1[2] = { Value, Chain };
10095 return DAG.getMergeValues(Ops1, 2, dl);
10098 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10100 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10101 Flag = Chain.getValue(1);
10102 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10104 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10105 Flag = Chain.getValue(1);
10107 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10110 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10111 return DAG.getMergeValues(Ops1, 2, dl);
10115 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10116 MachineFunction &MF = DAG.getMachineFunction();
10117 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10119 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10120 DebugLoc DL = Op.getDebugLoc();
10122 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10123 // vastart just stores the address of the VarArgsFrameIndex slot into the
10124 // memory location argument.
10125 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10127 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10128 MachinePointerInfo(SV), false, false, 0);
10132 // gp_offset (0 - 6 * 8)
10133 // fp_offset (48 - 48 + 8 * 16)
10134 // overflow_arg_area (point to parameters coming in memory).
10136 SmallVector<SDValue, 8> MemOps;
10137 SDValue FIN = Op.getOperand(1);
10139 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10140 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10142 FIN, MachinePointerInfo(SV), false, false, 0);
10143 MemOps.push_back(Store);
10146 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10147 FIN, DAG.getIntPtrConstant(4));
10148 Store = DAG.getStore(Op.getOperand(0), DL,
10149 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10151 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10152 MemOps.push_back(Store);
10154 // Store ptr to overflow_arg_area
10155 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10156 FIN, DAG.getIntPtrConstant(4));
10157 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10159 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10160 MachinePointerInfo(SV, 8),
10162 MemOps.push_back(Store);
10164 // Store ptr to reg_save_area.
10165 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10166 FIN, DAG.getIntPtrConstant(8));
10167 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10169 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10170 MachinePointerInfo(SV, 16), false, false, 0);
10171 MemOps.push_back(Store);
10172 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10173 &MemOps[0], MemOps.size());
10176 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10177 assert(Subtarget->is64Bit() &&
10178 "LowerVAARG only handles 64-bit va_arg!");
10179 assert((Subtarget->isTargetLinux() ||
10180 Subtarget->isTargetDarwin()) &&
10181 "Unhandled target in LowerVAARG");
10182 assert(Op.getNode()->getNumOperands() == 4);
10183 SDValue Chain = Op.getOperand(0);
10184 SDValue SrcPtr = Op.getOperand(1);
10185 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10186 unsigned Align = Op.getConstantOperandVal(3);
10187 DebugLoc dl = Op.getDebugLoc();
10189 EVT ArgVT = Op.getNode()->getValueType(0);
10190 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10191 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10194 // Decide which area this value should be read from.
10195 // TODO: Implement the AMD64 ABI in its entirety. This simple
10196 // selection mechanism works only for the basic types.
10197 if (ArgVT == MVT::f80) {
10198 llvm_unreachable("va_arg for f80 not yet implemented");
10199 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10200 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10201 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10202 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10204 llvm_unreachable("Unhandled argument type in LowerVAARG");
10207 if (ArgMode == 2) {
10208 // Sanity Check: Make sure using fp_offset makes sense.
10209 assert(!getTargetMachine().Options.UseSoftFloat &&
10210 !(DAG.getMachineFunction()
10211 .getFunction()->getAttributes()
10212 .hasAttribute(AttributeSet::FunctionIndex,
10213 Attribute::NoImplicitFloat)) &&
10214 Subtarget->hasSSE1());
10217 // Insert VAARG_64 node into the DAG
10218 // VAARG_64 returns two values: Variable Argument Address, Chain
10219 SmallVector<SDValue, 11> InstOps;
10220 InstOps.push_back(Chain);
10221 InstOps.push_back(SrcPtr);
10222 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10223 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10224 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10225 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10226 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10227 VTs, &InstOps[0], InstOps.size(),
10229 MachinePointerInfo(SV),
10231 /*Volatile=*/false,
10233 /*WriteMem=*/true);
10234 Chain = VAARG.getValue(1);
10236 // Load the next argument and return it
10237 return DAG.getLoad(ArgVT, dl,
10240 MachinePointerInfo(),
10241 false, false, false, 0);
10244 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10245 SelectionDAG &DAG) {
10246 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10247 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10248 SDValue Chain = Op.getOperand(0);
10249 SDValue DstPtr = Op.getOperand(1);
10250 SDValue SrcPtr = Op.getOperand(2);
10251 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10252 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10253 DebugLoc DL = Op.getDebugLoc();
10255 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10256 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10258 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10261 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10262 // may or may not be a constant. Takes immediate version of shift as input.
10263 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
10264 SDValue SrcOp, SDValue ShAmt,
10265 SelectionDAG &DAG) {
10266 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10268 if (isa<ConstantSDNode>(ShAmt)) {
10269 // Constant may be a TargetConstant. Use a regular constant.
10270 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10272 default: llvm_unreachable("Unknown target vector shift node");
10273 case X86ISD::VSHLI:
10274 case X86ISD::VSRLI:
10275 case X86ISD::VSRAI:
10276 return DAG.getNode(Opc, dl, VT, SrcOp,
10277 DAG.getConstant(ShiftAmt, MVT::i32));
10281 // Change opcode to non-immediate version
10283 default: llvm_unreachable("Unknown target vector shift node");
10284 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10285 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10286 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10289 // Need to build a vector containing shift amount
10290 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10293 ShOps[1] = DAG.getConstant(0, MVT::i32);
10294 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10295 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10297 // The return type has to be a 128-bit type with the same element
10298 // type as the input type.
10299 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10300 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10302 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10303 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10306 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10307 DebugLoc dl = Op.getDebugLoc();
10308 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10310 default: return SDValue(); // Don't custom lower most intrinsics.
10311 // Comparison intrinsics.
10312 case Intrinsic::x86_sse_comieq_ss:
10313 case Intrinsic::x86_sse_comilt_ss:
10314 case Intrinsic::x86_sse_comile_ss:
10315 case Intrinsic::x86_sse_comigt_ss:
10316 case Intrinsic::x86_sse_comige_ss:
10317 case Intrinsic::x86_sse_comineq_ss:
10318 case Intrinsic::x86_sse_ucomieq_ss:
10319 case Intrinsic::x86_sse_ucomilt_ss:
10320 case Intrinsic::x86_sse_ucomile_ss:
10321 case Intrinsic::x86_sse_ucomigt_ss:
10322 case Intrinsic::x86_sse_ucomige_ss:
10323 case Intrinsic::x86_sse_ucomineq_ss:
10324 case Intrinsic::x86_sse2_comieq_sd:
10325 case Intrinsic::x86_sse2_comilt_sd:
10326 case Intrinsic::x86_sse2_comile_sd:
10327 case Intrinsic::x86_sse2_comigt_sd:
10328 case Intrinsic::x86_sse2_comige_sd:
10329 case Intrinsic::x86_sse2_comineq_sd:
10330 case Intrinsic::x86_sse2_ucomieq_sd:
10331 case Intrinsic::x86_sse2_ucomilt_sd:
10332 case Intrinsic::x86_sse2_ucomile_sd:
10333 case Intrinsic::x86_sse2_ucomigt_sd:
10334 case Intrinsic::x86_sse2_ucomige_sd:
10335 case Intrinsic::x86_sse2_ucomineq_sd: {
10339 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10340 case Intrinsic::x86_sse_comieq_ss:
10341 case Intrinsic::x86_sse2_comieq_sd:
10342 Opc = X86ISD::COMI;
10345 case Intrinsic::x86_sse_comilt_ss:
10346 case Intrinsic::x86_sse2_comilt_sd:
10347 Opc = X86ISD::COMI;
10350 case Intrinsic::x86_sse_comile_ss:
10351 case Intrinsic::x86_sse2_comile_sd:
10352 Opc = X86ISD::COMI;
10355 case Intrinsic::x86_sse_comigt_ss:
10356 case Intrinsic::x86_sse2_comigt_sd:
10357 Opc = X86ISD::COMI;
10360 case Intrinsic::x86_sse_comige_ss:
10361 case Intrinsic::x86_sse2_comige_sd:
10362 Opc = X86ISD::COMI;
10365 case Intrinsic::x86_sse_comineq_ss:
10366 case Intrinsic::x86_sse2_comineq_sd:
10367 Opc = X86ISD::COMI;
10370 case Intrinsic::x86_sse_ucomieq_ss:
10371 case Intrinsic::x86_sse2_ucomieq_sd:
10372 Opc = X86ISD::UCOMI;
10375 case Intrinsic::x86_sse_ucomilt_ss:
10376 case Intrinsic::x86_sse2_ucomilt_sd:
10377 Opc = X86ISD::UCOMI;
10380 case Intrinsic::x86_sse_ucomile_ss:
10381 case Intrinsic::x86_sse2_ucomile_sd:
10382 Opc = X86ISD::UCOMI;
10385 case Intrinsic::x86_sse_ucomigt_ss:
10386 case Intrinsic::x86_sse2_ucomigt_sd:
10387 Opc = X86ISD::UCOMI;
10390 case Intrinsic::x86_sse_ucomige_ss:
10391 case Intrinsic::x86_sse2_ucomige_sd:
10392 Opc = X86ISD::UCOMI;
10395 case Intrinsic::x86_sse_ucomineq_ss:
10396 case Intrinsic::x86_sse2_ucomineq_sd:
10397 Opc = X86ISD::UCOMI;
10402 SDValue LHS = Op.getOperand(1);
10403 SDValue RHS = Op.getOperand(2);
10404 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10405 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10406 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10407 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10408 DAG.getConstant(X86CC, MVT::i8), Cond);
10409 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10412 // Arithmetic intrinsics.
10413 case Intrinsic::x86_sse2_pmulu_dq:
10414 case Intrinsic::x86_avx2_pmulu_dq:
10415 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10416 Op.getOperand(1), Op.getOperand(2));
10418 // SSE2/AVX2 sub with unsigned saturation intrinsics
10419 case Intrinsic::x86_sse2_psubus_b:
10420 case Intrinsic::x86_sse2_psubus_w:
10421 case Intrinsic::x86_avx2_psubus_b:
10422 case Intrinsic::x86_avx2_psubus_w:
10423 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10424 Op.getOperand(1), Op.getOperand(2));
10426 // SSE3/AVX horizontal add/sub intrinsics
10427 case Intrinsic::x86_sse3_hadd_ps:
10428 case Intrinsic::x86_sse3_hadd_pd:
10429 case Intrinsic::x86_avx_hadd_ps_256:
10430 case Intrinsic::x86_avx_hadd_pd_256:
10431 case Intrinsic::x86_sse3_hsub_ps:
10432 case Intrinsic::x86_sse3_hsub_pd:
10433 case Intrinsic::x86_avx_hsub_ps_256:
10434 case Intrinsic::x86_avx_hsub_pd_256:
10435 case Intrinsic::x86_ssse3_phadd_w_128:
10436 case Intrinsic::x86_ssse3_phadd_d_128:
10437 case Intrinsic::x86_avx2_phadd_w:
10438 case Intrinsic::x86_avx2_phadd_d:
10439 case Intrinsic::x86_ssse3_phsub_w_128:
10440 case Intrinsic::x86_ssse3_phsub_d_128:
10441 case Intrinsic::x86_avx2_phsub_w:
10442 case Intrinsic::x86_avx2_phsub_d: {
10445 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10446 case Intrinsic::x86_sse3_hadd_ps:
10447 case Intrinsic::x86_sse3_hadd_pd:
10448 case Intrinsic::x86_avx_hadd_ps_256:
10449 case Intrinsic::x86_avx_hadd_pd_256:
10450 Opcode = X86ISD::FHADD;
10452 case Intrinsic::x86_sse3_hsub_ps:
10453 case Intrinsic::x86_sse3_hsub_pd:
10454 case Intrinsic::x86_avx_hsub_ps_256:
10455 case Intrinsic::x86_avx_hsub_pd_256:
10456 Opcode = X86ISD::FHSUB;
10458 case Intrinsic::x86_ssse3_phadd_w_128:
10459 case Intrinsic::x86_ssse3_phadd_d_128:
10460 case Intrinsic::x86_avx2_phadd_w:
10461 case Intrinsic::x86_avx2_phadd_d:
10462 Opcode = X86ISD::HADD;
10464 case Intrinsic::x86_ssse3_phsub_w_128:
10465 case Intrinsic::x86_ssse3_phsub_d_128:
10466 case Intrinsic::x86_avx2_phsub_w:
10467 case Intrinsic::x86_avx2_phsub_d:
10468 Opcode = X86ISD::HSUB;
10471 return DAG.getNode(Opcode, dl, Op.getValueType(),
10472 Op.getOperand(1), Op.getOperand(2));
10475 // SSE2/SSE41/AVX2 integer max/min intrinsics.
10476 case Intrinsic::x86_sse2_pmaxu_b:
10477 case Intrinsic::x86_sse41_pmaxuw:
10478 case Intrinsic::x86_sse41_pmaxud:
10479 case Intrinsic::x86_avx2_pmaxu_b:
10480 case Intrinsic::x86_avx2_pmaxu_w:
10481 case Intrinsic::x86_avx2_pmaxu_d:
10482 case Intrinsic::x86_sse2_pminu_b:
10483 case Intrinsic::x86_sse41_pminuw:
10484 case Intrinsic::x86_sse41_pminud:
10485 case Intrinsic::x86_avx2_pminu_b:
10486 case Intrinsic::x86_avx2_pminu_w:
10487 case Intrinsic::x86_avx2_pminu_d:
10488 case Intrinsic::x86_sse41_pmaxsb:
10489 case Intrinsic::x86_sse2_pmaxs_w:
10490 case Intrinsic::x86_sse41_pmaxsd:
10491 case Intrinsic::x86_avx2_pmaxs_b:
10492 case Intrinsic::x86_avx2_pmaxs_w:
10493 case Intrinsic::x86_avx2_pmaxs_d:
10494 case Intrinsic::x86_sse41_pminsb:
10495 case Intrinsic::x86_sse2_pmins_w:
10496 case Intrinsic::x86_sse41_pminsd:
10497 case Intrinsic::x86_avx2_pmins_b:
10498 case Intrinsic::x86_avx2_pmins_w:
10499 case Intrinsic::x86_avx2_pmins_d: {
10502 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10503 case Intrinsic::x86_sse2_pmaxu_b:
10504 case Intrinsic::x86_sse41_pmaxuw:
10505 case Intrinsic::x86_sse41_pmaxud:
10506 case Intrinsic::x86_avx2_pmaxu_b:
10507 case Intrinsic::x86_avx2_pmaxu_w:
10508 case Intrinsic::x86_avx2_pmaxu_d:
10509 Opcode = X86ISD::UMAX;
10511 case Intrinsic::x86_sse2_pminu_b:
10512 case Intrinsic::x86_sse41_pminuw:
10513 case Intrinsic::x86_sse41_pminud:
10514 case Intrinsic::x86_avx2_pminu_b:
10515 case Intrinsic::x86_avx2_pminu_w:
10516 case Intrinsic::x86_avx2_pminu_d:
10517 Opcode = X86ISD::UMIN;
10519 case Intrinsic::x86_sse41_pmaxsb:
10520 case Intrinsic::x86_sse2_pmaxs_w:
10521 case Intrinsic::x86_sse41_pmaxsd:
10522 case Intrinsic::x86_avx2_pmaxs_b:
10523 case Intrinsic::x86_avx2_pmaxs_w:
10524 case Intrinsic::x86_avx2_pmaxs_d:
10525 Opcode = X86ISD::SMAX;
10527 case Intrinsic::x86_sse41_pminsb:
10528 case Intrinsic::x86_sse2_pmins_w:
10529 case Intrinsic::x86_sse41_pminsd:
10530 case Intrinsic::x86_avx2_pmins_b:
10531 case Intrinsic::x86_avx2_pmins_w:
10532 case Intrinsic::x86_avx2_pmins_d:
10533 Opcode = X86ISD::SMIN;
10536 return DAG.getNode(Opcode, dl, Op.getValueType(),
10537 Op.getOperand(1), Op.getOperand(2));
10540 // SSE/SSE2/AVX floating point max/min intrinsics.
10541 case Intrinsic::x86_sse_max_ps:
10542 case Intrinsic::x86_sse2_max_pd:
10543 case Intrinsic::x86_avx_max_ps_256:
10544 case Intrinsic::x86_avx_max_pd_256:
10545 case Intrinsic::x86_sse_min_ps:
10546 case Intrinsic::x86_sse2_min_pd:
10547 case Intrinsic::x86_avx_min_ps_256:
10548 case Intrinsic::x86_avx_min_pd_256: {
10551 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10552 case Intrinsic::x86_sse_max_ps:
10553 case Intrinsic::x86_sse2_max_pd:
10554 case Intrinsic::x86_avx_max_ps_256:
10555 case Intrinsic::x86_avx_max_pd_256:
10556 Opcode = X86ISD::FMAX;
10558 case Intrinsic::x86_sse_min_ps:
10559 case Intrinsic::x86_sse2_min_pd:
10560 case Intrinsic::x86_avx_min_ps_256:
10561 case Intrinsic::x86_avx_min_pd_256:
10562 Opcode = X86ISD::FMIN;
10565 return DAG.getNode(Opcode, dl, Op.getValueType(),
10566 Op.getOperand(1), Op.getOperand(2));
10569 // AVX2 variable shift intrinsics
10570 case Intrinsic::x86_avx2_psllv_d:
10571 case Intrinsic::x86_avx2_psllv_q:
10572 case Intrinsic::x86_avx2_psllv_d_256:
10573 case Intrinsic::x86_avx2_psllv_q_256:
10574 case Intrinsic::x86_avx2_psrlv_d:
10575 case Intrinsic::x86_avx2_psrlv_q:
10576 case Intrinsic::x86_avx2_psrlv_d_256:
10577 case Intrinsic::x86_avx2_psrlv_q_256:
10578 case Intrinsic::x86_avx2_psrav_d:
10579 case Intrinsic::x86_avx2_psrav_d_256: {
10582 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10583 case Intrinsic::x86_avx2_psllv_d:
10584 case Intrinsic::x86_avx2_psllv_q:
10585 case Intrinsic::x86_avx2_psllv_d_256:
10586 case Intrinsic::x86_avx2_psllv_q_256:
10589 case Intrinsic::x86_avx2_psrlv_d:
10590 case Intrinsic::x86_avx2_psrlv_q:
10591 case Intrinsic::x86_avx2_psrlv_d_256:
10592 case Intrinsic::x86_avx2_psrlv_q_256:
10595 case Intrinsic::x86_avx2_psrav_d:
10596 case Intrinsic::x86_avx2_psrav_d_256:
10600 return DAG.getNode(Opcode, dl, Op.getValueType(),
10601 Op.getOperand(1), Op.getOperand(2));
10604 case Intrinsic::x86_ssse3_pshuf_b_128:
10605 case Intrinsic::x86_avx2_pshuf_b:
10606 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10607 Op.getOperand(1), Op.getOperand(2));
10609 case Intrinsic::x86_ssse3_psign_b_128:
10610 case Intrinsic::x86_ssse3_psign_w_128:
10611 case Intrinsic::x86_ssse3_psign_d_128:
10612 case Intrinsic::x86_avx2_psign_b:
10613 case Intrinsic::x86_avx2_psign_w:
10614 case Intrinsic::x86_avx2_psign_d:
10615 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10616 Op.getOperand(1), Op.getOperand(2));
10618 case Intrinsic::x86_sse41_insertps:
10619 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10620 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10622 case Intrinsic::x86_avx_vperm2f128_ps_256:
10623 case Intrinsic::x86_avx_vperm2f128_pd_256:
10624 case Intrinsic::x86_avx_vperm2f128_si_256:
10625 case Intrinsic::x86_avx2_vperm2i128:
10626 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10627 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10629 case Intrinsic::x86_avx2_permd:
10630 case Intrinsic::x86_avx2_permps:
10631 // Operands intentionally swapped. Mask is last operand to intrinsic,
10632 // but second operand for node/intruction.
10633 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10634 Op.getOperand(2), Op.getOperand(1));
10636 case Intrinsic::x86_sse_sqrt_ps:
10637 case Intrinsic::x86_sse2_sqrt_pd:
10638 case Intrinsic::x86_avx_sqrt_ps_256:
10639 case Intrinsic::x86_avx_sqrt_pd_256:
10640 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
10642 // ptest and testp intrinsics. The intrinsic these come from are designed to
10643 // return an integer value, not just an instruction so lower it to the ptest
10644 // or testp pattern and a setcc for the result.
10645 case Intrinsic::x86_sse41_ptestz:
10646 case Intrinsic::x86_sse41_ptestc:
10647 case Intrinsic::x86_sse41_ptestnzc:
10648 case Intrinsic::x86_avx_ptestz_256:
10649 case Intrinsic::x86_avx_ptestc_256:
10650 case Intrinsic::x86_avx_ptestnzc_256:
10651 case Intrinsic::x86_avx_vtestz_ps:
10652 case Intrinsic::x86_avx_vtestc_ps:
10653 case Intrinsic::x86_avx_vtestnzc_ps:
10654 case Intrinsic::x86_avx_vtestz_pd:
10655 case Intrinsic::x86_avx_vtestc_pd:
10656 case Intrinsic::x86_avx_vtestnzc_pd:
10657 case Intrinsic::x86_avx_vtestz_ps_256:
10658 case Intrinsic::x86_avx_vtestc_ps_256:
10659 case Intrinsic::x86_avx_vtestnzc_ps_256:
10660 case Intrinsic::x86_avx_vtestz_pd_256:
10661 case Intrinsic::x86_avx_vtestc_pd_256:
10662 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10663 bool IsTestPacked = false;
10666 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10667 case Intrinsic::x86_avx_vtestz_ps:
10668 case Intrinsic::x86_avx_vtestz_pd:
10669 case Intrinsic::x86_avx_vtestz_ps_256:
10670 case Intrinsic::x86_avx_vtestz_pd_256:
10671 IsTestPacked = true; // Fallthrough
10672 case Intrinsic::x86_sse41_ptestz:
10673 case Intrinsic::x86_avx_ptestz_256:
10675 X86CC = X86::COND_E;
10677 case Intrinsic::x86_avx_vtestc_ps:
10678 case Intrinsic::x86_avx_vtestc_pd:
10679 case Intrinsic::x86_avx_vtestc_ps_256:
10680 case Intrinsic::x86_avx_vtestc_pd_256:
10681 IsTestPacked = true; // Fallthrough
10682 case Intrinsic::x86_sse41_ptestc:
10683 case Intrinsic::x86_avx_ptestc_256:
10685 X86CC = X86::COND_B;
10687 case Intrinsic::x86_avx_vtestnzc_ps:
10688 case Intrinsic::x86_avx_vtestnzc_pd:
10689 case Intrinsic::x86_avx_vtestnzc_ps_256:
10690 case Intrinsic::x86_avx_vtestnzc_pd_256:
10691 IsTestPacked = true; // Fallthrough
10692 case Intrinsic::x86_sse41_ptestnzc:
10693 case Intrinsic::x86_avx_ptestnzc_256:
10695 X86CC = X86::COND_A;
10699 SDValue LHS = Op.getOperand(1);
10700 SDValue RHS = Op.getOperand(2);
10701 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
10702 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
10703 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
10704 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10705 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10708 // SSE/AVX shift intrinsics
10709 case Intrinsic::x86_sse2_psll_w:
10710 case Intrinsic::x86_sse2_psll_d:
10711 case Intrinsic::x86_sse2_psll_q:
10712 case Intrinsic::x86_avx2_psll_w:
10713 case Intrinsic::x86_avx2_psll_d:
10714 case Intrinsic::x86_avx2_psll_q:
10715 case Intrinsic::x86_sse2_psrl_w:
10716 case Intrinsic::x86_sse2_psrl_d:
10717 case Intrinsic::x86_sse2_psrl_q:
10718 case Intrinsic::x86_avx2_psrl_w:
10719 case Intrinsic::x86_avx2_psrl_d:
10720 case Intrinsic::x86_avx2_psrl_q:
10721 case Intrinsic::x86_sse2_psra_w:
10722 case Intrinsic::x86_sse2_psra_d:
10723 case Intrinsic::x86_avx2_psra_w:
10724 case Intrinsic::x86_avx2_psra_d: {
10727 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10728 case Intrinsic::x86_sse2_psll_w:
10729 case Intrinsic::x86_sse2_psll_d:
10730 case Intrinsic::x86_sse2_psll_q:
10731 case Intrinsic::x86_avx2_psll_w:
10732 case Intrinsic::x86_avx2_psll_d:
10733 case Intrinsic::x86_avx2_psll_q:
10734 Opcode = X86ISD::VSHL;
10736 case Intrinsic::x86_sse2_psrl_w:
10737 case Intrinsic::x86_sse2_psrl_d:
10738 case Intrinsic::x86_sse2_psrl_q:
10739 case Intrinsic::x86_avx2_psrl_w:
10740 case Intrinsic::x86_avx2_psrl_d:
10741 case Intrinsic::x86_avx2_psrl_q:
10742 Opcode = X86ISD::VSRL;
10744 case Intrinsic::x86_sse2_psra_w:
10745 case Intrinsic::x86_sse2_psra_d:
10746 case Intrinsic::x86_avx2_psra_w:
10747 case Intrinsic::x86_avx2_psra_d:
10748 Opcode = X86ISD::VSRA;
10751 return DAG.getNode(Opcode, dl, Op.getValueType(),
10752 Op.getOperand(1), Op.getOperand(2));
10755 // SSE/AVX immediate shift intrinsics
10756 case Intrinsic::x86_sse2_pslli_w:
10757 case Intrinsic::x86_sse2_pslli_d:
10758 case Intrinsic::x86_sse2_pslli_q:
10759 case Intrinsic::x86_avx2_pslli_w:
10760 case Intrinsic::x86_avx2_pslli_d:
10761 case Intrinsic::x86_avx2_pslli_q:
10762 case Intrinsic::x86_sse2_psrli_w:
10763 case Intrinsic::x86_sse2_psrli_d:
10764 case Intrinsic::x86_sse2_psrli_q:
10765 case Intrinsic::x86_avx2_psrli_w:
10766 case Intrinsic::x86_avx2_psrli_d:
10767 case Intrinsic::x86_avx2_psrli_q:
10768 case Intrinsic::x86_sse2_psrai_w:
10769 case Intrinsic::x86_sse2_psrai_d:
10770 case Intrinsic::x86_avx2_psrai_w:
10771 case Intrinsic::x86_avx2_psrai_d: {
10774 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10775 case Intrinsic::x86_sse2_pslli_w:
10776 case Intrinsic::x86_sse2_pslli_d:
10777 case Intrinsic::x86_sse2_pslli_q:
10778 case Intrinsic::x86_avx2_pslli_w:
10779 case Intrinsic::x86_avx2_pslli_d:
10780 case Intrinsic::x86_avx2_pslli_q:
10781 Opcode = X86ISD::VSHLI;
10783 case Intrinsic::x86_sse2_psrli_w:
10784 case Intrinsic::x86_sse2_psrli_d:
10785 case Intrinsic::x86_sse2_psrli_q:
10786 case Intrinsic::x86_avx2_psrli_w:
10787 case Intrinsic::x86_avx2_psrli_d:
10788 case Intrinsic::x86_avx2_psrli_q:
10789 Opcode = X86ISD::VSRLI;
10791 case Intrinsic::x86_sse2_psrai_w:
10792 case Intrinsic::x86_sse2_psrai_d:
10793 case Intrinsic::x86_avx2_psrai_w:
10794 case Intrinsic::x86_avx2_psrai_d:
10795 Opcode = X86ISD::VSRAI;
10798 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
10799 Op.getOperand(1), Op.getOperand(2), DAG);
10802 case Intrinsic::x86_sse42_pcmpistria128:
10803 case Intrinsic::x86_sse42_pcmpestria128:
10804 case Intrinsic::x86_sse42_pcmpistric128:
10805 case Intrinsic::x86_sse42_pcmpestric128:
10806 case Intrinsic::x86_sse42_pcmpistrio128:
10807 case Intrinsic::x86_sse42_pcmpestrio128:
10808 case Intrinsic::x86_sse42_pcmpistris128:
10809 case Intrinsic::x86_sse42_pcmpestris128:
10810 case Intrinsic::x86_sse42_pcmpistriz128:
10811 case Intrinsic::x86_sse42_pcmpestriz128: {
10815 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10816 case Intrinsic::x86_sse42_pcmpistria128:
10817 Opcode = X86ISD::PCMPISTRI;
10818 X86CC = X86::COND_A;
10820 case Intrinsic::x86_sse42_pcmpestria128:
10821 Opcode = X86ISD::PCMPESTRI;
10822 X86CC = X86::COND_A;
10824 case Intrinsic::x86_sse42_pcmpistric128:
10825 Opcode = X86ISD::PCMPISTRI;
10826 X86CC = X86::COND_B;
10828 case Intrinsic::x86_sse42_pcmpestric128:
10829 Opcode = X86ISD::PCMPESTRI;
10830 X86CC = X86::COND_B;
10832 case Intrinsic::x86_sse42_pcmpistrio128:
10833 Opcode = X86ISD::PCMPISTRI;
10834 X86CC = X86::COND_O;
10836 case Intrinsic::x86_sse42_pcmpestrio128:
10837 Opcode = X86ISD::PCMPESTRI;
10838 X86CC = X86::COND_O;
10840 case Intrinsic::x86_sse42_pcmpistris128:
10841 Opcode = X86ISD::PCMPISTRI;
10842 X86CC = X86::COND_S;
10844 case Intrinsic::x86_sse42_pcmpestris128:
10845 Opcode = X86ISD::PCMPESTRI;
10846 X86CC = X86::COND_S;
10848 case Intrinsic::x86_sse42_pcmpistriz128:
10849 Opcode = X86ISD::PCMPISTRI;
10850 X86CC = X86::COND_E;
10852 case Intrinsic::x86_sse42_pcmpestriz128:
10853 Opcode = X86ISD::PCMPESTRI;
10854 X86CC = X86::COND_E;
10857 SmallVector<SDValue, 5> NewOps;
10858 NewOps.append(Op->op_begin()+1, Op->op_end());
10859 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10860 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10861 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10862 DAG.getConstant(X86CC, MVT::i8),
10863 SDValue(PCMP.getNode(), 1));
10864 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10867 case Intrinsic::x86_sse42_pcmpistri128:
10868 case Intrinsic::x86_sse42_pcmpestri128: {
10870 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10871 Opcode = X86ISD::PCMPISTRI;
10873 Opcode = X86ISD::PCMPESTRI;
10875 SmallVector<SDValue, 5> NewOps;
10876 NewOps.append(Op->op_begin()+1, Op->op_end());
10877 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10878 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10880 case Intrinsic::x86_fma_vfmadd_ps:
10881 case Intrinsic::x86_fma_vfmadd_pd:
10882 case Intrinsic::x86_fma_vfmsub_ps:
10883 case Intrinsic::x86_fma_vfmsub_pd:
10884 case Intrinsic::x86_fma_vfnmadd_ps:
10885 case Intrinsic::x86_fma_vfnmadd_pd:
10886 case Intrinsic::x86_fma_vfnmsub_ps:
10887 case Intrinsic::x86_fma_vfnmsub_pd:
10888 case Intrinsic::x86_fma_vfmaddsub_ps:
10889 case Intrinsic::x86_fma_vfmaddsub_pd:
10890 case Intrinsic::x86_fma_vfmsubadd_ps:
10891 case Intrinsic::x86_fma_vfmsubadd_pd:
10892 case Intrinsic::x86_fma_vfmadd_ps_256:
10893 case Intrinsic::x86_fma_vfmadd_pd_256:
10894 case Intrinsic::x86_fma_vfmsub_ps_256:
10895 case Intrinsic::x86_fma_vfmsub_pd_256:
10896 case Intrinsic::x86_fma_vfnmadd_ps_256:
10897 case Intrinsic::x86_fma_vfnmadd_pd_256:
10898 case Intrinsic::x86_fma_vfnmsub_ps_256:
10899 case Intrinsic::x86_fma_vfnmsub_pd_256:
10900 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10901 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10902 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10903 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10906 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10907 case Intrinsic::x86_fma_vfmadd_ps:
10908 case Intrinsic::x86_fma_vfmadd_pd:
10909 case Intrinsic::x86_fma_vfmadd_ps_256:
10910 case Intrinsic::x86_fma_vfmadd_pd_256:
10911 Opc = X86ISD::FMADD;
10913 case Intrinsic::x86_fma_vfmsub_ps:
10914 case Intrinsic::x86_fma_vfmsub_pd:
10915 case Intrinsic::x86_fma_vfmsub_ps_256:
10916 case Intrinsic::x86_fma_vfmsub_pd_256:
10917 Opc = X86ISD::FMSUB;
10919 case Intrinsic::x86_fma_vfnmadd_ps:
10920 case Intrinsic::x86_fma_vfnmadd_pd:
10921 case Intrinsic::x86_fma_vfnmadd_ps_256:
10922 case Intrinsic::x86_fma_vfnmadd_pd_256:
10923 Opc = X86ISD::FNMADD;
10925 case Intrinsic::x86_fma_vfnmsub_ps:
10926 case Intrinsic::x86_fma_vfnmsub_pd:
10927 case Intrinsic::x86_fma_vfnmsub_ps_256:
10928 case Intrinsic::x86_fma_vfnmsub_pd_256:
10929 Opc = X86ISD::FNMSUB;
10931 case Intrinsic::x86_fma_vfmaddsub_ps:
10932 case Intrinsic::x86_fma_vfmaddsub_pd:
10933 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10934 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10935 Opc = X86ISD::FMADDSUB;
10937 case Intrinsic::x86_fma_vfmsubadd_ps:
10938 case Intrinsic::x86_fma_vfmsubadd_pd:
10939 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10940 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10941 Opc = X86ISD::FMSUBADD;
10945 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10946 Op.getOperand(2), Op.getOperand(3));
10951 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
10952 DebugLoc dl = Op.getDebugLoc();
10953 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10955 default: return SDValue(); // Don't custom lower most intrinsics.
10957 // RDRAND/RDSEED intrinsics.
10958 case Intrinsic::x86_rdrand_16:
10959 case Intrinsic::x86_rdrand_32:
10960 case Intrinsic::x86_rdrand_64:
10961 case Intrinsic::x86_rdseed_16:
10962 case Intrinsic::x86_rdseed_32:
10963 case Intrinsic::x86_rdseed_64: {
10964 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
10965 IntNo == Intrinsic::x86_rdseed_32 ||
10966 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
10968 // Emit the node with the right value type.
10969 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10970 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
10972 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
10973 // Otherwise return the value from Rand, which is always 0, casted to i32.
10974 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10975 DAG.getConstant(1, Op->getValueType(1)),
10976 DAG.getConstant(X86::COND_B, MVT::i32),
10977 SDValue(Result.getNode(), 1) };
10978 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10979 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10980 Ops, array_lengthof(Ops));
10982 // Return { result, isValid, chain }.
10983 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10984 SDValue(Result.getNode(), 2));
10987 // XTEST intrinsics.
10988 case Intrinsic::x86_xtest: {
10989 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
10990 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
10991 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10992 DAG.getConstant(X86::COND_NE, MVT::i8),
10994 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
10995 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
10996 Ret, SDValue(InTrans.getNode(), 1));
11001 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11002 SelectionDAG &DAG) const {
11003 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11004 MFI->setReturnAddressIsTaken(true);
11006 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11007 DebugLoc dl = Op.getDebugLoc();
11008 EVT PtrVT = getPointerTy();
11011 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11013 DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11014 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11015 DAG.getNode(ISD::ADD, dl, PtrVT,
11016 FrameAddr, Offset),
11017 MachinePointerInfo(), false, false, false, 0);
11020 // Just load the return address.
11021 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11022 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11023 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11026 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11027 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11028 MFI->setFrameAddressIsTaken(true);
11030 EVT VT = Op.getValueType();
11031 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
11032 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11033 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
11034 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11036 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11037 MachinePointerInfo(),
11038 false, false, false, 0);
11042 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11043 SelectionDAG &DAG) const {
11044 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11047 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11048 SDValue Chain = Op.getOperand(0);
11049 SDValue Offset = Op.getOperand(1);
11050 SDValue Handler = Op.getOperand(2);
11051 DebugLoc dl = Op.getDebugLoc();
11053 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
11054 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
11056 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
11058 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
11059 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11060 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
11061 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
11063 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
11065 return DAG.getNode(X86ISD::EH_RETURN, dl,
11067 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
11070 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
11071 SelectionDAG &DAG) const {
11072 DebugLoc DL = Op.getDebugLoc();
11073 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
11074 DAG.getVTList(MVT::i32, MVT::Other),
11075 Op.getOperand(0), Op.getOperand(1));
11078 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
11079 SelectionDAG &DAG) const {
11080 DebugLoc DL = Op.getDebugLoc();
11081 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
11082 Op.getOperand(0), Op.getOperand(1));
11085 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
11086 return Op.getOperand(0);
11089 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
11090 SelectionDAG &DAG) const {
11091 SDValue Root = Op.getOperand(0);
11092 SDValue Trmp = Op.getOperand(1); // trampoline
11093 SDValue FPtr = Op.getOperand(2); // nested function
11094 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
11095 DebugLoc dl = Op.getDebugLoc();
11097 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11098 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
11100 if (Subtarget->is64Bit()) {
11101 SDValue OutChains[6];
11103 // Large code-model.
11104 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11105 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11107 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
11108 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
11110 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
11112 // Load the pointer to the nested function into R11.
11113 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11114 SDValue Addr = Trmp;
11115 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11116 Addr, MachinePointerInfo(TrmpAddr),
11119 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11120 DAG.getConstant(2, MVT::i64));
11121 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11122 MachinePointerInfo(TrmpAddr, 2),
11125 // Load the 'nest' parameter value into R10.
11126 // R10 is specified in X86CallingConv.td
11127 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11128 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11129 DAG.getConstant(10, MVT::i64));
11130 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11131 Addr, MachinePointerInfo(TrmpAddr, 10),
11134 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11135 DAG.getConstant(12, MVT::i64));
11136 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11137 MachinePointerInfo(TrmpAddr, 12),
11140 // Jump to the nested function.
11141 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11143 DAG.getConstant(20, MVT::i64));
11144 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11145 Addr, MachinePointerInfo(TrmpAddr, 20),
11148 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11149 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11150 DAG.getConstant(22, MVT::i64));
11151 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11152 MachinePointerInfo(TrmpAddr, 22),
11155 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11157 const Function *Func =
11158 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11159 CallingConv::ID CC = Func->getCallingConv();
11164 llvm_unreachable("Unsupported calling convention");
11165 case CallingConv::C:
11166 case CallingConv::X86_StdCall: {
11167 // Pass 'nest' parameter in ECX.
11168 // Must be kept in sync with X86CallingConv.td
11169 NestReg = X86::ECX;
11171 // Check that ECX wasn't needed by an 'inreg' parameter.
11172 FunctionType *FTy = Func->getFunctionType();
11173 const AttributeSet &Attrs = Func->getAttributes();
11175 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11176 unsigned InRegCount = 0;
11179 for (FunctionType::param_iterator I = FTy->param_begin(),
11180 E = FTy->param_end(); I != E; ++I, ++Idx)
11181 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11182 // FIXME: should only count parameters that are lowered to integers.
11183 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11185 if (InRegCount > 2) {
11186 report_fatal_error("Nest register in use - reduce number of inreg"
11192 case CallingConv::X86_FastCall:
11193 case CallingConv::X86_ThisCall:
11194 case CallingConv::Fast:
11195 // Pass 'nest' parameter in EAX.
11196 // Must be kept in sync with X86CallingConv.td
11197 NestReg = X86::EAX;
11201 SDValue OutChains[4];
11202 SDValue Addr, Disp;
11204 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11205 DAG.getConstant(10, MVT::i32));
11206 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11208 // This is storing the opcode for MOV32ri.
11209 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11210 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11211 OutChains[0] = DAG.getStore(Root, dl,
11212 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11213 Trmp, MachinePointerInfo(TrmpAddr),
11216 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11217 DAG.getConstant(1, MVT::i32));
11218 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11219 MachinePointerInfo(TrmpAddr, 1),
11222 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11223 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11224 DAG.getConstant(5, MVT::i32));
11225 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11226 MachinePointerInfo(TrmpAddr, 5),
11229 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11230 DAG.getConstant(6, MVT::i32));
11231 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11232 MachinePointerInfo(TrmpAddr, 6),
11235 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11239 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11240 SelectionDAG &DAG) const {
11242 The rounding mode is in bits 11:10 of FPSR, and has the following
11244 00 Round to nearest
11249 FLT_ROUNDS, on the other hand, expects the following:
11256 To perform the conversion, we do:
11257 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11260 MachineFunction &MF = DAG.getMachineFunction();
11261 const TargetMachine &TM = MF.getTarget();
11262 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11263 unsigned StackAlignment = TFI.getStackAlignment();
11264 EVT VT = Op.getValueType();
11265 DebugLoc DL = Op.getDebugLoc();
11267 // Save FP Control Word to stack slot
11268 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11269 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11271 MachineMemOperand *MMO =
11272 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11273 MachineMemOperand::MOStore, 2, 2);
11275 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11276 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11277 DAG.getVTList(MVT::Other),
11278 Ops, array_lengthof(Ops), MVT::i16,
11281 // Load FP Control Word from stack slot
11282 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11283 MachinePointerInfo(), false, false, false, 0);
11285 // Transform as necessary
11287 DAG.getNode(ISD::SRL, DL, MVT::i16,
11288 DAG.getNode(ISD::AND, DL, MVT::i16,
11289 CWD, DAG.getConstant(0x800, MVT::i16)),
11290 DAG.getConstant(11, MVT::i8));
11292 DAG.getNode(ISD::SRL, DL, MVT::i16,
11293 DAG.getNode(ISD::AND, DL, MVT::i16,
11294 CWD, DAG.getConstant(0x400, MVT::i16)),
11295 DAG.getConstant(9, MVT::i8));
11298 DAG.getNode(ISD::AND, DL, MVT::i16,
11299 DAG.getNode(ISD::ADD, DL, MVT::i16,
11300 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11301 DAG.getConstant(1, MVT::i16)),
11302 DAG.getConstant(3, MVT::i16));
11304 return DAG.getNode((VT.getSizeInBits() < 16 ?
11305 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11308 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11309 EVT VT = Op.getValueType();
11311 unsigned NumBits = VT.getSizeInBits();
11312 DebugLoc dl = Op.getDebugLoc();
11314 Op = Op.getOperand(0);
11315 if (VT == MVT::i8) {
11316 // Zero extend to i32 since there is not an i8 bsr.
11318 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11321 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11322 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11323 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11325 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11328 DAG.getConstant(NumBits+NumBits-1, OpVT),
11329 DAG.getConstant(X86::COND_E, MVT::i8),
11332 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11334 // Finally xor with NumBits-1.
11335 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11338 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11342 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11343 EVT VT = Op.getValueType();
11345 unsigned NumBits = VT.getSizeInBits();
11346 DebugLoc dl = Op.getDebugLoc();
11348 Op = Op.getOperand(0);
11349 if (VT == MVT::i8) {
11350 // Zero extend to i32 since there is not an i8 bsr.
11352 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11355 // Issue a bsr (scan bits in reverse).
11356 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11357 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11359 // And xor with NumBits-1.
11360 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11363 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11367 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11368 EVT VT = Op.getValueType();
11369 unsigned NumBits = VT.getSizeInBits();
11370 DebugLoc dl = Op.getDebugLoc();
11371 Op = Op.getOperand(0);
11373 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11374 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11375 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11377 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11380 DAG.getConstant(NumBits, VT),
11381 DAG.getConstant(X86::COND_E, MVT::i8),
11384 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11387 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11388 // ones, and then concatenate the result back.
11389 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11390 EVT VT = Op.getValueType();
11392 assert(VT.is256BitVector() && VT.isInteger() &&
11393 "Unsupported value type for operation");
11395 unsigned NumElems = VT.getVectorNumElements();
11396 DebugLoc dl = Op.getDebugLoc();
11398 // Extract the LHS vectors
11399 SDValue LHS = Op.getOperand(0);
11400 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11401 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11403 // Extract the RHS vectors
11404 SDValue RHS = Op.getOperand(1);
11405 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11406 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11408 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11409 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11411 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11412 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11413 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11416 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
11417 assert(Op.getValueType().is256BitVector() &&
11418 Op.getValueType().isInteger() &&
11419 "Only handle AVX 256-bit vector integer operation");
11420 return Lower256IntArith(Op, DAG);
11423 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
11424 assert(Op.getValueType().is256BitVector() &&
11425 Op.getValueType().isInteger() &&
11426 "Only handle AVX 256-bit vector integer operation");
11427 return Lower256IntArith(Op, DAG);
11430 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
11431 SelectionDAG &DAG) {
11432 DebugLoc dl = Op.getDebugLoc();
11433 EVT VT = Op.getValueType();
11435 // Decompose 256-bit ops into smaller 128-bit ops.
11436 if (VT.is256BitVector() && !Subtarget->hasInt256())
11437 return Lower256IntArith(Op, DAG);
11439 SDValue A = Op.getOperand(0);
11440 SDValue B = Op.getOperand(1);
11442 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
11443 if (VT == MVT::v4i32) {
11444 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
11445 "Should not custom lower when pmuldq is available!");
11447 // Extract the odd parts.
11448 const int UnpackMask[] = { 1, -1, 3, -1 };
11449 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
11450 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
11452 // Multiply the even parts.
11453 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
11454 // Now multiply odd parts.
11455 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
11457 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
11458 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
11460 // Merge the two vectors back together with a shuffle. This expands into 2
11462 const int ShufMask[] = { 0, 4, 2, 6 };
11463 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
11466 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11467 "Only know how to lower V2I64/V4I64 multiply");
11469 // Ahi = psrlqi(a, 32);
11470 // Bhi = psrlqi(b, 32);
11472 // AloBlo = pmuludq(a, b);
11473 // AloBhi = pmuludq(a, Bhi);
11474 // AhiBlo = pmuludq(Ahi, b);
11476 // AloBhi = psllqi(AloBhi, 32);
11477 // AhiBlo = psllqi(AhiBlo, 32);
11478 // return AloBlo + AloBhi + AhiBlo;
11480 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11482 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11483 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11485 // Bit cast to 32-bit vectors for MULUDQ
11486 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11487 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11488 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11489 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11490 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11492 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11493 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11494 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11496 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11497 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11499 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11500 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11503 SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
11504 EVT VT = Op.getValueType();
11505 EVT EltTy = VT.getVectorElementType();
11506 unsigned NumElts = VT.getVectorNumElements();
11507 SDValue N0 = Op.getOperand(0);
11508 DebugLoc dl = Op.getDebugLoc();
11510 // Lower sdiv X, pow2-const.
11511 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
11515 APInt SplatValue, SplatUndef;
11516 unsigned MinSplatBits;
11518 if (!C->isConstantSplat(SplatValue, SplatUndef, MinSplatBits, HasAnyUndefs))
11521 if ((SplatValue != 0) &&
11522 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
11523 unsigned lg2 = SplatValue.countTrailingZeros();
11524 // Splat the sign bit.
11525 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
11526 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
11527 // Add (N0 < 0) ? abs2 - 1 : 0;
11528 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
11529 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
11530 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
11531 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
11532 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
11534 // If we're dividing by a positive value, we're done. Otherwise, we must
11535 // negate the result.
11536 if (SplatValue.isNonNegative())
11539 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
11540 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
11541 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
11546 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
11547 const X86Subtarget *Subtarget) {
11548 EVT VT = Op.getValueType();
11549 DebugLoc dl = Op.getDebugLoc();
11550 SDValue R = Op.getOperand(0);
11551 SDValue Amt = Op.getOperand(1);
11553 // Optimize shl/srl/sra with constant shift amount.
11554 if (isSplatVector(Amt.getNode())) {
11555 SDValue SclrAmt = Amt->getOperand(0);
11556 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11557 uint64_t ShiftAmt = C->getZExtValue();
11559 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11560 (Subtarget->hasInt256() &&
11561 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11562 if (Op.getOpcode() == ISD::SHL)
11563 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11564 DAG.getConstant(ShiftAmt, MVT::i32));
11565 if (Op.getOpcode() == ISD::SRL)
11566 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11567 DAG.getConstant(ShiftAmt, MVT::i32));
11568 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11569 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11570 DAG.getConstant(ShiftAmt, MVT::i32));
11573 if (VT == MVT::v16i8) {
11574 if (Op.getOpcode() == ISD::SHL) {
11575 // Make a large shift.
11576 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11577 DAG.getConstant(ShiftAmt, MVT::i32));
11578 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11579 // Zero out the rightmost bits.
11580 SmallVector<SDValue, 16> V(16,
11581 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11583 return DAG.getNode(ISD::AND, dl, VT, SHL,
11584 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11586 if (Op.getOpcode() == ISD::SRL) {
11587 // Make a large shift.
11588 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11589 DAG.getConstant(ShiftAmt, MVT::i32));
11590 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11591 // Zero out the leftmost bits.
11592 SmallVector<SDValue, 16> V(16,
11593 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11595 return DAG.getNode(ISD::AND, dl, VT, SRL,
11596 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11598 if (Op.getOpcode() == ISD::SRA) {
11599 if (ShiftAmt == 7) {
11600 // R s>> 7 === R s< 0
11601 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11602 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11605 // R s>> a === ((R u>> a) ^ m) - m
11606 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11607 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11609 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11610 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11611 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11614 llvm_unreachable("Unknown shift opcode.");
11617 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11618 if (Op.getOpcode() == ISD::SHL) {
11619 // Make a large shift.
11620 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11621 DAG.getConstant(ShiftAmt, MVT::i32));
11622 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11623 // Zero out the rightmost bits.
11624 SmallVector<SDValue, 32> V(32,
11625 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11627 return DAG.getNode(ISD::AND, dl, VT, SHL,
11628 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11630 if (Op.getOpcode() == ISD::SRL) {
11631 // Make a large shift.
11632 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11633 DAG.getConstant(ShiftAmt, MVT::i32));
11634 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11635 // Zero out the leftmost bits.
11636 SmallVector<SDValue, 32> V(32,
11637 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11639 return DAG.getNode(ISD::AND, dl, VT, SRL,
11640 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11642 if (Op.getOpcode() == ISD::SRA) {
11643 if (ShiftAmt == 7) {
11644 // R s>> 7 === R s< 0
11645 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11646 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11649 // R s>> a === ((R u>> a) ^ m) - m
11650 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11651 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11653 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11654 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11655 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11658 llvm_unreachable("Unknown shift opcode.");
11663 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
11664 if (!Subtarget->is64Bit() &&
11665 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
11666 Amt.getOpcode() == ISD::BITCAST &&
11667 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
11668 Amt = Amt.getOperand(0);
11669 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
11670 VT.getVectorNumElements();
11671 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
11672 uint64_t ShiftAmt = 0;
11673 for (unsigned i = 0; i != Ratio; ++i) {
11674 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
11678 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
11680 // Check remaining shift amounts.
11681 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
11682 uint64_t ShAmt = 0;
11683 for (unsigned j = 0; j != Ratio; ++j) {
11684 ConstantSDNode *C =
11685 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
11689 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
11691 if (ShAmt != ShiftAmt)
11694 switch (Op.getOpcode()) {
11696 llvm_unreachable("Unknown shift opcode!");
11698 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11699 DAG.getConstant(ShiftAmt, MVT::i32));
11701 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11702 DAG.getConstant(ShiftAmt, MVT::i32));
11704 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11705 DAG.getConstant(ShiftAmt, MVT::i32));
11712 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
11713 const X86Subtarget* Subtarget) {
11714 EVT VT = Op.getValueType();
11715 DebugLoc dl = Op.getDebugLoc();
11716 SDValue R = Op.getOperand(0);
11717 SDValue Amt = Op.getOperand(1);
11719 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
11720 VT == MVT::v4i32 || VT == MVT::v8i16 ||
11721 (Subtarget->hasInt256() &&
11722 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
11723 VT == MVT::v8i32 || VT == MVT::v16i16))) {
11725 EVT EltVT = VT.getVectorElementType();
11727 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11728 unsigned NumElts = VT.getVectorNumElements();
11730 for (i = 0; i != NumElts; ++i) {
11731 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
11735 for (j = i; j != NumElts; ++j) {
11736 SDValue Arg = Amt.getOperand(j);
11737 if (Arg.getOpcode() == ISD::UNDEF) continue;
11738 if (Arg != Amt.getOperand(i))
11741 if (i != NumElts && j == NumElts)
11742 BaseShAmt = Amt.getOperand(i);
11744 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
11745 Amt = Amt.getOperand(0);
11746 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
11747 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
11748 SDValue InVec = Amt.getOperand(0);
11749 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
11750 unsigned NumElts = InVec.getValueType().getVectorNumElements();
11752 for (; i != NumElts; ++i) {
11753 SDValue Arg = InVec.getOperand(i);
11754 if (Arg.getOpcode() == ISD::UNDEF) continue;
11758 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
11759 if (ConstantSDNode *C =
11760 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
11761 unsigned SplatIdx =
11762 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
11763 if (C->getZExtValue() == SplatIdx)
11764 BaseShAmt = InVec.getOperand(1);
11767 if (BaseShAmt.getNode() == 0)
11768 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
11769 DAG.getIntPtrConstant(0));
11773 if (BaseShAmt.getNode()) {
11774 if (EltVT.bitsGT(MVT::i32))
11775 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
11776 else if (EltVT.bitsLT(MVT::i32))
11777 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
11779 switch (Op.getOpcode()) {
11781 llvm_unreachable("Unknown shift opcode!");
11783 switch (VT.getSimpleVT().SimpleTy) {
11784 default: return SDValue();
11791 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
11794 switch (VT.getSimpleVT().SimpleTy) {
11795 default: return SDValue();
11800 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
11803 switch (VT.getSimpleVT().SimpleTy) {
11804 default: return SDValue();
11811 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
11817 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
11818 if (!Subtarget->is64Bit() &&
11819 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
11820 Amt.getOpcode() == ISD::BITCAST &&
11821 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
11822 Amt = Amt.getOperand(0);
11823 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
11824 VT.getVectorNumElements();
11825 std::vector<SDValue> Vals(Ratio);
11826 for (unsigned i = 0; i != Ratio; ++i)
11827 Vals[i] = Amt.getOperand(i);
11828 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
11829 for (unsigned j = 0; j != Ratio; ++j)
11830 if (Vals[j] != Amt.getOperand(i + j))
11833 switch (Op.getOpcode()) {
11835 llvm_unreachable("Unknown shift opcode!");
11837 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
11839 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
11841 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
11848 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
11850 EVT VT = Op.getValueType();
11851 DebugLoc dl = Op.getDebugLoc();
11852 SDValue R = Op.getOperand(0);
11853 SDValue Amt = Op.getOperand(1);
11856 if (!Subtarget->hasSSE2())
11859 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
11863 V = LowerScalarVariableShift(Op, DAG, Subtarget);
11867 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
11868 if (Subtarget->hasInt256()) {
11869 if (Op.getOpcode() == ISD::SRL &&
11870 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
11871 VT == MVT::v4i64 || VT == MVT::v8i32))
11873 if (Op.getOpcode() == ISD::SHL &&
11874 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
11875 VT == MVT::v4i64 || VT == MVT::v8i32))
11877 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
11881 // Lower SHL with variable shift amount.
11882 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11883 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
11885 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
11886 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11887 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11888 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11890 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11891 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
11894 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
11895 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11897 // Turn 'a' into a mask suitable for VSELECT
11898 SDValue VSelM = DAG.getConstant(0x80, VT);
11899 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11900 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11902 SDValue CM1 = DAG.getConstant(0x0f, VT);
11903 SDValue CM2 = DAG.getConstant(0x3f, VT);
11905 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
11906 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11907 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11908 DAG.getConstant(4, MVT::i32), DAG);
11909 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11910 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11913 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11914 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11915 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11917 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
11918 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11919 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11920 DAG.getConstant(2, MVT::i32), DAG);
11921 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11922 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11925 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11926 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11927 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11929 // return VSELECT(r, r+r, a);
11930 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11931 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11935 // Decompose 256-bit shifts into smaller 128-bit shifts.
11936 if (VT.is256BitVector()) {
11937 unsigned NumElems = VT.getVectorNumElements();
11938 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11939 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11941 // Extract the two vectors
11942 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
11943 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
11945 // Recreate the shift amount vectors
11946 SDValue Amt1, Amt2;
11947 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11948 // Constant shift amount
11949 SmallVector<SDValue, 4> Amt1Csts;
11950 SmallVector<SDValue, 4> Amt2Csts;
11951 for (unsigned i = 0; i != NumElems/2; ++i)
11952 Amt1Csts.push_back(Amt->getOperand(i));
11953 for (unsigned i = NumElems/2; i != NumElems; ++i)
11954 Amt2Csts.push_back(Amt->getOperand(i));
11956 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11957 &Amt1Csts[0], NumElems/2);
11958 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11959 &Amt2Csts[0], NumElems/2);
11961 // Variable shift amount
11962 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11963 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
11966 // Issue new vector shifts for the smaller types
11967 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11968 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11970 // Concatenate the result back
11971 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11977 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
11978 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
11979 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
11980 // looks for this combo and may remove the "setcc" instruction if the "setcc"
11981 // has only one use.
11982 SDNode *N = Op.getNode();
11983 SDValue LHS = N->getOperand(0);
11984 SDValue RHS = N->getOperand(1);
11985 unsigned BaseOp = 0;
11987 DebugLoc DL = Op.getDebugLoc();
11988 switch (Op.getOpcode()) {
11989 default: llvm_unreachable("Unknown ovf instruction!");
11991 // A subtract of one will be selected as a INC. Note that INC doesn't
11992 // set CF, so we can't do this for UADDO.
11993 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11995 BaseOp = X86ISD::INC;
11996 Cond = X86::COND_O;
11999 BaseOp = X86ISD::ADD;
12000 Cond = X86::COND_O;
12003 BaseOp = X86ISD::ADD;
12004 Cond = X86::COND_B;
12007 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12008 // set CF, so we can't do this for USUBO.
12009 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12011 BaseOp = X86ISD::DEC;
12012 Cond = X86::COND_O;
12015 BaseOp = X86ISD::SUB;
12016 Cond = X86::COND_O;
12019 BaseOp = X86ISD::SUB;
12020 Cond = X86::COND_B;
12023 BaseOp = X86ISD::SMUL;
12024 Cond = X86::COND_O;
12026 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12027 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12029 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12032 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12033 DAG.getConstant(X86::COND_O, MVT::i32),
12034 SDValue(Sum.getNode(), 2));
12036 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12040 // Also sets EFLAGS.
12041 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12042 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
12045 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12046 DAG.getConstant(Cond, MVT::i32),
12047 SDValue(Sum.getNode(), 1));
12049 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12052 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
12053 SelectionDAG &DAG) const {
12054 DebugLoc dl = Op.getDebugLoc();
12055 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
12056 EVT VT = Op.getValueType();
12058 if (!Subtarget->hasSSE2() || !VT.isVector())
12061 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
12062 ExtraVT.getScalarType().getSizeInBits();
12063 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
12065 switch (VT.getSimpleVT().SimpleTy) {
12066 default: return SDValue();
12069 if (!Subtarget->hasFp256())
12071 if (!Subtarget->hasInt256()) {
12072 // needs to be split
12073 unsigned NumElems = VT.getVectorNumElements();
12075 // Extract the LHS vectors
12076 SDValue LHS = Op.getOperand(0);
12077 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12078 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12080 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12081 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12083 EVT ExtraEltVT = ExtraVT.getVectorElementType();
12084 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
12085 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
12087 SDValue Extra = DAG.getValueType(ExtraVT);
12089 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
12090 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
12092 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
12097 // (sext (vzext x)) -> (vsext x)
12098 SDValue Op0 = Op.getOperand(0);
12099 SDValue Op00 = Op0.getOperand(0);
12101 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
12102 if (Op0.getOpcode() == ISD::BITCAST &&
12103 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
12104 Tmp1 = LowerVectorIntExtend(Op00, DAG);
12105 if (Tmp1.getNode()) {
12106 SDValue Tmp1Op0 = Tmp1.getOperand(0);
12107 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
12108 "This optimization is invalid without a VZEXT.");
12109 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
12112 // If the above didn't work, then just use Shift-Left + Shift-Right.
12113 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
12114 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
12119 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
12120 SelectionDAG &DAG) {
12121 DebugLoc dl = Op.getDebugLoc();
12122 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
12123 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
12124 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
12125 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
12127 // The only fence that needs an instruction is a sequentially-consistent
12128 // cross-thread fence.
12129 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
12130 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
12131 // no-sse2). There isn't any reason to disable it if the target processor
12133 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
12134 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
12136 SDValue Chain = Op.getOperand(0);
12137 SDValue Zero = DAG.getConstant(0, MVT::i32);
12139 DAG.getRegister(X86::ESP, MVT::i32), // Base
12140 DAG.getTargetConstant(1, MVT::i8), // Scale
12141 DAG.getRegister(0, MVT::i32), // Index
12142 DAG.getTargetConstant(0, MVT::i32), // Disp
12143 DAG.getRegister(0, MVT::i32), // Segment.
12147 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
12148 return SDValue(Res, 0);
12151 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
12152 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
12155 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
12156 SelectionDAG &DAG) {
12157 EVT T = Op.getValueType();
12158 DebugLoc DL = Op.getDebugLoc();
12161 switch(T.getSimpleVT().SimpleTy) {
12162 default: llvm_unreachable("Invalid value type!");
12163 case MVT::i8: Reg = X86::AL; size = 1; break;
12164 case MVT::i16: Reg = X86::AX; size = 2; break;
12165 case MVT::i32: Reg = X86::EAX; size = 4; break;
12167 assert(Subtarget->is64Bit() && "Node not type legal!");
12168 Reg = X86::RAX; size = 8;
12171 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
12172 Op.getOperand(2), SDValue());
12173 SDValue Ops[] = { cpIn.getValue(0),
12176 DAG.getTargetConstant(size, MVT::i8),
12177 cpIn.getValue(1) };
12178 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12179 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
12180 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
12181 Ops, array_lengthof(Ops), T, MMO);
12183 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
12187 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
12188 SelectionDAG &DAG) {
12189 assert(Subtarget->is64Bit() && "Result not type legalized?");
12190 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12191 SDValue TheChain = Op.getOperand(0);
12192 DebugLoc dl = Op.getDebugLoc();
12193 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12194 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
12195 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
12197 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
12198 DAG.getConstant(32, MVT::i8));
12200 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
12203 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
12206 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
12207 EVT SrcVT = Op.getOperand(0).getValueType();
12208 EVT DstVT = Op.getValueType();
12209 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
12210 Subtarget->hasMMX() && "Unexpected custom BITCAST");
12211 assert((DstVT == MVT::i64 ||
12212 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
12213 "Unexpected custom BITCAST");
12214 // i64 <=> MMX conversions are Legal.
12215 if (SrcVT==MVT::i64 && DstVT.isVector())
12217 if (DstVT==MVT::i64 && SrcVT.isVector())
12219 // MMX <=> MMX conversions are Legal.
12220 if (SrcVT.isVector() && DstVT.isVector())
12222 // All other conversions need to be expanded.
12226 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
12227 SDNode *Node = Op.getNode();
12228 DebugLoc dl = Node->getDebugLoc();
12229 EVT T = Node->getValueType(0);
12230 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
12231 DAG.getConstant(0, T), Node->getOperand(2));
12232 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
12233 cast<AtomicSDNode>(Node)->getMemoryVT(),
12234 Node->getOperand(0),
12235 Node->getOperand(1), negOp,
12236 cast<AtomicSDNode>(Node)->getSrcValue(),
12237 cast<AtomicSDNode>(Node)->getAlignment(),
12238 cast<AtomicSDNode>(Node)->getOrdering(),
12239 cast<AtomicSDNode>(Node)->getSynchScope());
12242 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
12243 SDNode *Node = Op.getNode();
12244 DebugLoc dl = Node->getDebugLoc();
12245 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12247 // Convert seq_cst store -> xchg
12248 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
12249 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12250 // (The only way to get a 16-byte store is cmpxchg16b)
12251 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
12252 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
12253 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12254 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
12255 cast<AtomicSDNode>(Node)->getMemoryVT(),
12256 Node->getOperand(0),
12257 Node->getOperand(1), Node->getOperand(2),
12258 cast<AtomicSDNode>(Node)->getMemOperand(),
12259 cast<AtomicSDNode>(Node)->getOrdering(),
12260 cast<AtomicSDNode>(Node)->getSynchScope());
12261 return Swap.getValue(1);
12263 // Other atomic stores have a simple pattern.
12267 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
12268 EVT VT = Op.getNode()->getValueType(0);
12270 // Let legalize expand this if it isn't a legal type yet.
12271 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
12274 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12277 bool ExtraOp = false;
12278 switch (Op.getOpcode()) {
12279 default: llvm_unreachable("Invalid code");
12280 case ISD::ADDC: Opc = X86ISD::ADD; break;
12281 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12282 case ISD::SUBC: Opc = X86ISD::SUB; break;
12283 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12287 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
12289 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
12290 Op.getOperand(1), Op.getOperand(2));
12293 SDValue X86TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
12294 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
12296 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
12297 // which returns the values as { float, float } (in XMM0) or
12298 // { double, double } (which is returned in XMM0, XMM1).
12299 DebugLoc dl = Op.getDebugLoc();
12300 SDValue Arg = Op.getOperand(0);
12301 EVT ArgVT = Arg.getValueType();
12302 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
12305 ArgListEntry Entry;
12309 Entry.isSExt = false;
12310 Entry.isZExt = false;
12311 Args.push_back(Entry);
12313 bool isF64 = ArgVT == MVT::f64;
12314 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
12315 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12316 // the results are returned via SRet in memory.
12317 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
12318 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
12320 Type *RetTy = isF64
12321 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
12322 : (Type*)VectorType::get(ArgTy, 4);
12324 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
12325 false, false, false, false, 0,
12326 CallingConv::C, /*isTaillCall=*/false,
12327 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
12328 Callee, Args, DAG, dl);
12329 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
12332 // Returned in xmm0 and xmm1.
12333 return CallResult.first;
12335 // Returned in bits 0:31 and 32:64 xmm0.
12336 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12337 CallResult.first, DAG.getIntPtrConstant(0));
12338 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12339 CallResult.first, DAG.getIntPtrConstant(1));
12340 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
12341 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
12344 /// LowerOperation - Provide custom lowering hooks for some operations.
12346 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12347 switch (Op.getOpcode()) {
12348 default: llvm_unreachable("Should not custom lower this!");
12349 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12350 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12351 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12352 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12353 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12354 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12355 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12356 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12357 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12358 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12359 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12360 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12361 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12362 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12363 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12364 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12365 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12366 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12367 case ISD::SHL_PARTS:
12368 case ISD::SRA_PARTS:
12369 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12370 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12371 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12372 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
12373 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
12374 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
12375 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
12376 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12377 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12378 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
12379 case ISD::FABS: return LowerFABS(Op, DAG);
12380 case ISD::FNEG: return LowerFNEG(Op, DAG);
12381 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12382 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12383 case ISD::SETCC: return LowerSETCC(Op, DAG);
12384 case ISD::SELECT: return LowerSELECT(Op, DAG);
12385 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12386 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12387 case ISD::VASTART: return LowerVASTART(Op, DAG);
12388 case ISD::VAARG: return LowerVAARG(Op, DAG);
12389 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12390 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12391 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12392 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12393 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12394 case ISD::FRAME_TO_ARGS_OFFSET:
12395 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12396 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12397 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12398 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12399 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12400 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12401 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12402 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12403 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12404 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12405 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12406 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12409 case ISD::SHL: return LowerShift(Op, DAG);
12415 case ISD::UMULO: return LowerXALUO(Op, DAG);
12416 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12417 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
12421 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
12422 case ISD::ADD: return LowerADD(Op, DAG);
12423 case ISD::SUB: return LowerSUB(Op, DAG);
12424 case ISD::SDIV: return LowerSDIV(Op, DAG);
12425 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
12429 static void ReplaceATOMIC_LOAD(SDNode *Node,
12430 SmallVectorImpl<SDValue> &Results,
12431 SelectionDAG &DAG) {
12432 DebugLoc dl = Node->getDebugLoc();
12433 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12435 // Convert wide load -> cmpxchg8b/cmpxchg16b
12436 // FIXME: On 32-bit, load -> fild or movq would be more efficient
12437 // (The only way to get a 16-byte load is cmpxchg16b)
12438 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
12439 SDValue Zero = DAG.getConstant(0, VT);
12440 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
12441 Node->getOperand(0),
12442 Node->getOperand(1), Zero, Zero,
12443 cast<AtomicSDNode>(Node)->getMemOperand(),
12444 cast<AtomicSDNode>(Node)->getOrdering(),
12445 cast<AtomicSDNode>(Node)->getSynchScope());
12446 Results.push_back(Swap.getValue(0));
12447 Results.push_back(Swap.getValue(1));
12451 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
12452 SelectionDAG &DAG, unsigned NewOp) {
12453 DebugLoc dl = Node->getDebugLoc();
12454 assert (Node->getValueType(0) == MVT::i64 &&
12455 "Only know how to expand i64 atomics");
12457 SDValue Chain = Node->getOperand(0);
12458 SDValue In1 = Node->getOperand(1);
12459 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12460 Node->getOperand(2), DAG.getIntPtrConstant(0));
12461 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12462 Node->getOperand(2), DAG.getIntPtrConstant(1));
12463 SDValue Ops[] = { Chain, In1, In2L, In2H };
12464 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
12466 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
12467 cast<MemSDNode>(Node)->getMemOperand());
12468 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
12469 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12470 Results.push_back(Result.getValue(2));
12473 /// ReplaceNodeResults - Replace a node with an illegal result type
12474 /// with a new node built out of custom code.
12475 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
12476 SmallVectorImpl<SDValue>&Results,
12477 SelectionDAG &DAG) const {
12478 DebugLoc dl = N->getDebugLoc();
12479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12480 switch (N->getOpcode()) {
12482 llvm_unreachable("Do not know how to custom type legalize this operation!");
12483 case ISD::SIGN_EXTEND_INREG:
12488 // We don't want to expand or promote these.
12490 case ISD::FP_TO_SINT:
12491 case ISD::FP_TO_UINT: {
12492 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12494 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
12497 std::pair<SDValue,SDValue> Vals =
12498 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
12499 SDValue FIST = Vals.first, StackSlot = Vals.second;
12500 if (FIST.getNode() != 0) {
12501 EVT VT = N->getValueType(0);
12502 // Return a load from the stack slot.
12503 if (StackSlot.getNode() != 0)
12504 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
12505 MachinePointerInfo(),
12506 false, false, false, 0));
12508 Results.push_back(FIST);
12512 case ISD::UINT_TO_FP: {
12513 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
12514 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
12515 N->getValueType(0) != MVT::v2f32)
12517 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12519 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12521 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12522 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12523 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12524 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12525 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12526 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12529 case ISD::FP_ROUND: {
12530 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
12532 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
12533 Results.push_back(V);
12536 case ISD::READCYCLECOUNTER: {
12537 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12538 SDValue TheChain = N->getOperand(0);
12539 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12540 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12542 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12544 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12545 SDValue Ops[] = { eax, edx };
12546 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
12547 array_lengthof(Ops)));
12548 Results.push_back(edx.getValue(1));
12551 case ISD::ATOMIC_CMP_SWAP: {
12552 EVT T = N->getValueType(0);
12553 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
12554 bool Regs64bit = T == MVT::i128;
12555 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
12556 SDValue cpInL, cpInH;
12557 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12558 DAG.getConstant(0, HalfT));
12559 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12560 DAG.getConstant(1, HalfT));
12561 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
12562 Regs64bit ? X86::RAX : X86::EAX,
12564 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
12565 Regs64bit ? X86::RDX : X86::EDX,
12566 cpInH, cpInL.getValue(1));
12567 SDValue swapInL, swapInH;
12568 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12569 DAG.getConstant(0, HalfT));
12570 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12571 DAG.getConstant(1, HalfT));
12572 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
12573 Regs64bit ? X86::RBX : X86::EBX,
12574 swapInL, cpInH.getValue(1));
12575 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
12576 Regs64bit ? X86::RCX : X86::ECX,
12577 swapInH, swapInL.getValue(1));
12578 SDValue Ops[] = { swapInH.getValue(0),
12580 swapInH.getValue(1) };
12581 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12582 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
12583 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
12584 X86ISD::LCMPXCHG8_DAG;
12585 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
12586 Ops, array_lengthof(Ops), T, MMO);
12587 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
12588 Regs64bit ? X86::RAX : X86::EAX,
12589 HalfT, Result.getValue(1));
12590 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
12591 Regs64bit ? X86::RDX : X86::EDX,
12592 HalfT, cpOutL.getValue(2));
12593 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
12594 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
12595 Results.push_back(cpOutH.getValue(1));
12598 case ISD::ATOMIC_LOAD_ADD:
12599 case ISD::ATOMIC_LOAD_AND:
12600 case ISD::ATOMIC_LOAD_NAND:
12601 case ISD::ATOMIC_LOAD_OR:
12602 case ISD::ATOMIC_LOAD_SUB:
12603 case ISD::ATOMIC_LOAD_XOR:
12604 case ISD::ATOMIC_LOAD_MAX:
12605 case ISD::ATOMIC_LOAD_MIN:
12606 case ISD::ATOMIC_LOAD_UMAX:
12607 case ISD::ATOMIC_LOAD_UMIN:
12608 case ISD::ATOMIC_SWAP: {
12610 switch (N->getOpcode()) {
12611 default: llvm_unreachable("Unexpected opcode");
12612 case ISD::ATOMIC_LOAD_ADD:
12613 Opc = X86ISD::ATOMADD64_DAG;
12615 case ISD::ATOMIC_LOAD_AND:
12616 Opc = X86ISD::ATOMAND64_DAG;
12618 case ISD::ATOMIC_LOAD_NAND:
12619 Opc = X86ISD::ATOMNAND64_DAG;
12621 case ISD::ATOMIC_LOAD_OR:
12622 Opc = X86ISD::ATOMOR64_DAG;
12624 case ISD::ATOMIC_LOAD_SUB:
12625 Opc = X86ISD::ATOMSUB64_DAG;
12627 case ISD::ATOMIC_LOAD_XOR:
12628 Opc = X86ISD::ATOMXOR64_DAG;
12630 case ISD::ATOMIC_LOAD_MAX:
12631 Opc = X86ISD::ATOMMAX64_DAG;
12633 case ISD::ATOMIC_LOAD_MIN:
12634 Opc = X86ISD::ATOMMIN64_DAG;
12636 case ISD::ATOMIC_LOAD_UMAX:
12637 Opc = X86ISD::ATOMUMAX64_DAG;
12639 case ISD::ATOMIC_LOAD_UMIN:
12640 Opc = X86ISD::ATOMUMIN64_DAG;
12642 case ISD::ATOMIC_SWAP:
12643 Opc = X86ISD::ATOMSWAP64_DAG;
12646 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
12649 case ISD::ATOMIC_LOAD:
12650 ReplaceATOMIC_LOAD(N, Results, DAG);
12654 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
12656 default: return NULL;
12657 case X86ISD::BSF: return "X86ISD::BSF";
12658 case X86ISD::BSR: return "X86ISD::BSR";
12659 case X86ISD::SHLD: return "X86ISD::SHLD";
12660 case X86ISD::SHRD: return "X86ISD::SHRD";
12661 case X86ISD::FAND: return "X86ISD::FAND";
12662 case X86ISD::FOR: return "X86ISD::FOR";
12663 case X86ISD::FXOR: return "X86ISD::FXOR";
12664 case X86ISD::FSRL: return "X86ISD::FSRL";
12665 case X86ISD::FILD: return "X86ISD::FILD";
12666 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
12667 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
12668 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
12669 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
12670 case X86ISD::FLD: return "X86ISD::FLD";
12671 case X86ISD::FST: return "X86ISD::FST";
12672 case X86ISD::CALL: return "X86ISD::CALL";
12673 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
12674 case X86ISD::BT: return "X86ISD::BT";
12675 case X86ISD::CMP: return "X86ISD::CMP";
12676 case X86ISD::COMI: return "X86ISD::COMI";
12677 case X86ISD::UCOMI: return "X86ISD::UCOMI";
12678 case X86ISD::SETCC: return "X86ISD::SETCC";
12679 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
12680 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
12681 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
12682 case X86ISD::CMOV: return "X86ISD::CMOV";
12683 case X86ISD::BRCOND: return "X86ISD::BRCOND";
12684 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
12685 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
12686 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
12687 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
12688 case X86ISD::Wrapper: return "X86ISD::Wrapper";
12689 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
12690 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
12691 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
12692 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
12693 case X86ISD::PINSRB: return "X86ISD::PINSRB";
12694 case X86ISD::PINSRW: return "X86ISD::PINSRW";
12695 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
12696 case X86ISD::ANDNP: return "X86ISD::ANDNP";
12697 case X86ISD::PSIGN: return "X86ISD::PSIGN";
12698 case X86ISD::BLENDV: return "X86ISD::BLENDV";
12699 case X86ISD::BLENDI: return "X86ISD::BLENDI";
12700 case X86ISD::SUBUS: return "X86ISD::SUBUS";
12701 case X86ISD::HADD: return "X86ISD::HADD";
12702 case X86ISD::HSUB: return "X86ISD::HSUB";
12703 case X86ISD::FHADD: return "X86ISD::FHADD";
12704 case X86ISD::FHSUB: return "X86ISD::FHSUB";
12705 case X86ISD::UMAX: return "X86ISD::UMAX";
12706 case X86ISD::UMIN: return "X86ISD::UMIN";
12707 case X86ISD::SMAX: return "X86ISD::SMAX";
12708 case X86ISD::SMIN: return "X86ISD::SMIN";
12709 case X86ISD::FMAX: return "X86ISD::FMAX";
12710 case X86ISD::FMIN: return "X86ISD::FMIN";
12711 case X86ISD::FMAXC: return "X86ISD::FMAXC";
12712 case X86ISD::FMINC: return "X86ISD::FMINC";
12713 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
12714 case X86ISD::FRCP: return "X86ISD::FRCP";
12715 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
12716 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
12717 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
12718 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
12719 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
12720 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
12721 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
12722 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
12723 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
12724 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
12725 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
12726 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
12727 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
12728 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
12729 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
12730 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
12731 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
12732 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
12733 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
12734 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
12735 case X86ISD::VZEXT: return "X86ISD::VZEXT";
12736 case X86ISD::VSEXT: return "X86ISD::VSEXT";
12737 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
12738 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
12739 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
12740 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
12741 case X86ISD::VSHL: return "X86ISD::VSHL";
12742 case X86ISD::VSRL: return "X86ISD::VSRL";
12743 case X86ISD::VSRA: return "X86ISD::VSRA";
12744 case X86ISD::VSHLI: return "X86ISD::VSHLI";
12745 case X86ISD::VSRLI: return "X86ISD::VSRLI";
12746 case X86ISD::VSRAI: return "X86ISD::VSRAI";
12747 case X86ISD::CMPP: return "X86ISD::CMPP";
12748 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
12749 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
12750 case X86ISD::ADD: return "X86ISD::ADD";
12751 case X86ISD::SUB: return "X86ISD::SUB";
12752 case X86ISD::ADC: return "X86ISD::ADC";
12753 case X86ISD::SBB: return "X86ISD::SBB";
12754 case X86ISD::SMUL: return "X86ISD::SMUL";
12755 case X86ISD::UMUL: return "X86ISD::UMUL";
12756 case X86ISD::INC: return "X86ISD::INC";
12757 case X86ISD::DEC: return "X86ISD::DEC";
12758 case X86ISD::OR: return "X86ISD::OR";
12759 case X86ISD::XOR: return "X86ISD::XOR";
12760 case X86ISD::AND: return "X86ISD::AND";
12761 case X86ISD::BLSI: return "X86ISD::BLSI";
12762 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
12763 case X86ISD::BLSR: return "X86ISD::BLSR";
12764 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
12765 case X86ISD::PTEST: return "X86ISD::PTEST";
12766 case X86ISD::TESTP: return "X86ISD::TESTP";
12767 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
12768 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
12769 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
12770 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
12771 case X86ISD::SHUFP: return "X86ISD::SHUFP";
12772 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
12773 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
12774 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
12775 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
12776 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
12777 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
12778 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
12779 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
12780 case X86ISD::MOVSD: return "X86ISD::MOVSD";
12781 case X86ISD::MOVSS: return "X86ISD::MOVSS";
12782 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
12783 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
12784 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
12785 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
12786 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
12787 case X86ISD::VPERMV: return "X86ISD::VPERMV";
12788 case X86ISD::VPERMI: return "X86ISD::VPERMI";
12789 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
12790 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
12791 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
12792 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
12793 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
12794 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
12795 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
12796 case X86ISD::SAHF: return "X86ISD::SAHF";
12797 case X86ISD::RDRAND: return "X86ISD::RDRAND";
12798 case X86ISD::RDSEED: return "X86ISD::RDSEED";
12799 case X86ISD::FMADD: return "X86ISD::FMADD";
12800 case X86ISD::FMSUB: return "X86ISD::FMSUB";
12801 case X86ISD::FNMADD: return "X86ISD::FNMADD";
12802 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
12803 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
12804 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
12805 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
12806 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12807 case X86ISD::XTEST: return "X86ISD::XTEST";
12811 // isLegalAddressingMode - Return true if the addressing mode represented
12812 // by AM is legal for this target, for a load/store of the specified type.
12813 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
12815 // X86 supports extremely general addressing modes.
12816 CodeModel::Model M = getTargetMachine().getCodeModel();
12817 Reloc::Model R = getTargetMachine().getRelocationModel();
12819 // X86 allows a sign-extended 32-bit immediate field as a displacement.
12820 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
12825 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
12827 // If a reference to this global requires an extra load, we can't fold it.
12828 if (isGlobalStubReference(GVFlags))
12831 // If BaseGV requires a register for the PIC base, we cannot also have a
12832 // BaseReg specified.
12833 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
12836 // If lower 4G is not available, then we must use rip-relative addressing.
12837 if ((M != CodeModel::Small || R != Reloc::Static) &&
12838 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
12842 switch (AM.Scale) {
12848 // These scales always work.
12853 // These scales are formed with basereg+scalereg. Only accept if there is
12858 default: // Other stuff never works.
12865 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12866 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12868 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12869 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12870 return NumBits1 > NumBits2;
12873 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12874 return isInt<32>(Imm);
12877 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
12878 // Can also use sub to handle negated immediates.
12879 return isInt<32>(Imm);
12882 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12883 if (!VT1.isInteger() || !VT2.isInteger())
12885 unsigned NumBits1 = VT1.getSizeInBits();
12886 unsigned NumBits2 = VT2.getSizeInBits();
12887 return NumBits1 > NumBits2;
12890 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
12891 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12892 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
12895 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
12896 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12897 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
12900 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12901 EVT VT1 = Val.getValueType();
12902 if (isZExtFree(VT1, VT2))
12905 if (Val.getOpcode() != ISD::LOAD)
12908 if (!VT1.isSimple() || !VT1.isInteger() ||
12909 !VT2.isSimple() || !VT2.isInteger())
12912 switch (VT1.getSimpleVT().SimpleTy) {
12917 // X86 has 8, 16, and 32-bit zero-extending loads.
12924 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
12925 // i16 instructions are longer (0x66 prefix) and potentially slower.
12926 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
12929 /// isShuffleMaskLegal - Targets can use this to indicate that they only
12930 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
12931 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12932 /// are assumed to be legal.
12934 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
12936 // Very little shuffling can be done for 64-bit vectors right now.
12937 if (VT.getSizeInBits() == 64)
12940 // FIXME: pshufb, blends, shifts.
12941 return (VT.getVectorNumElements() == 2 ||
12942 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
12943 isMOVLMask(M, VT) ||
12944 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
12945 isPSHUFDMask(M, VT) ||
12946 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
12947 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
12948 isPALIGNRMask(M, VT, Subtarget) ||
12949 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
12950 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
12951 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
12952 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
12956 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
12958 unsigned NumElts = VT.getVectorNumElements();
12959 // FIXME: This collection of masks seems suspect.
12962 if (NumElts == 4 && VT.is128BitVector()) {
12963 return (isMOVLMask(Mask, VT) ||
12964 isCommutedMOVLMask(Mask, VT, true) ||
12965 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
12966 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
12971 //===----------------------------------------------------------------------===//
12972 // X86 Scheduler Hooks
12973 //===----------------------------------------------------------------------===//
12975 /// Utility function to emit xbegin specifying the start of an RTM region.
12976 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
12977 const TargetInstrInfo *TII) {
12978 DebugLoc DL = MI->getDebugLoc();
12980 const BasicBlock *BB = MBB->getBasicBlock();
12981 MachineFunction::iterator I = MBB;
12984 // For the v = xbegin(), we generate
12995 MachineBasicBlock *thisMBB = MBB;
12996 MachineFunction *MF = MBB->getParent();
12997 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12998 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12999 MF->insert(I, mainMBB);
13000 MF->insert(I, sinkMBB);
13002 // Transfer the remainder of BB and its successor edges to sinkMBB.
13003 sinkMBB->splice(sinkMBB->begin(), MBB,
13004 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13005 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13009 // # fallthrough to mainMBB
13010 // # abortion to sinkMBB
13011 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
13012 thisMBB->addSuccessor(mainMBB);
13013 thisMBB->addSuccessor(sinkMBB);
13017 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
13018 mainMBB->addSuccessor(sinkMBB);
13021 // EAX is live into the sinkMBB
13022 sinkMBB->addLiveIn(X86::EAX);
13023 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13024 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13027 MI->eraseFromParent();
13031 // Get CMPXCHG opcode for the specified data type.
13032 static unsigned getCmpXChgOpcode(EVT VT) {
13033 switch (VT.getSimpleVT().SimpleTy) {
13034 case MVT::i8: return X86::LCMPXCHG8;
13035 case MVT::i16: return X86::LCMPXCHG16;
13036 case MVT::i32: return X86::LCMPXCHG32;
13037 case MVT::i64: return X86::LCMPXCHG64;
13041 llvm_unreachable("Invalid operand size!");
13044 // Get LOAD opcode for the specified data type.
13045 static unsigned getLoadOpcode(EVT VT) {
13046 switch (VT.getSimpleVT().SimpleTy) {
13047 case MVT::i8: return X86::MOV8rm;
13048 case MVT::i16: return X86::MOV16rm;
13049 case MVT::i32: return X86::MOV32rm;
13050 case MVT::i64: return X86::MOV64rm;
13054 llvm_unreachable("Invalid operand size!");
13057 // Get opcode of the non-atomic one from the specified atomic instruction.
13058 static unsigned getNonAtomicOpcode(unsigned Opc) {
13060 case X86::ATOMAND8: return X86::AND8rr;
13061 case X86::ATOMAND16: return X86::AND16rr;
13062 case X86::ATOMAND32: return X86::AND32rr;
13063 case X86::ATOMAND64: return X86::AND64rr;
13064 case X86::ATOMOR8: return X86::OR8rr;
13065 case X86::ATOMOR16: return X86::OR16rr;
13066 case X86::ATOMOR32: return X86::OR32rr;
13067 case X86::ATOMOR64: return X86::OR64rr;
13068 case X86::ATOMXOR8: return X86::XOR8rr;
13069 case X86::ATOMXOR16: return X86::XOR16rr;
13070 case X86::ATOMXOR32: return X86::XOR32rr;
13071 case X86::ATOMXOR64: return X86::XOR64rr;
13073 llvm_unreachable("Unhandled atomic-load-op opcode!");
13076 // Get opcode of the non-atomic one from the specified atomic instruction with
13078 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
13079 unsigned &ExtraOpc) {
13081 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
13082 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
13083 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
13084 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
13085 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
13086 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
13087 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
13088 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
13089 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
13090 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
13091 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
13092 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
13093 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
13094 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
13095 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
13096 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
13097 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
13098 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
13099 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
13100 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
13102 llvm_unreachable("Unhandled atomic-load-op opcode!");
13105 // Get opcode of the non-atomic one from the specified atomic instruction for
13106 // 64-bit data type on 32-bit target.
13107 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
13109 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
13110 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
13111 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
13112 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
13113 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
13114 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
13115 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
13116 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
13117 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
13118 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
13120 llvm_unreachable("Unhandled atomic-load-op opcode!");
13123 // Get opcode of the non-atomic one from the specified atomic instruction for
13124 // 64-bit data type on 32-bit target with extra opcode.
13125 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
13127 unsigned &ExtraOpc) {
13129 case X86::ATOMNAND6432:
13130 ExtraOpc = X86::NOT32r;
13131 HiOpc = X86::AND32rr;
13132 return X86::AND32rr;
13134 llvm_unreachable("Unhandled atomic-load-op opcode!");
13137 // Get pseudo CMOV opcode from the specified data type.
13138 static unsigned getPseudoCMOVOpc(EVT VT) {
13139 switch (VT.getSimpleVT().SimpleTy) {
13140 case MVT::i8: return X86::CMOV_GR8;
13141 case MVT::i16: return X86::CMOV_GR16;
13142 case MVT::i32: return X86::CMOV_GR32;
13146 llvm_unreachable("Unknown CMOV opcode!");
13149 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
13150 // They will be translated into a spin-loop or compare-exchange loop from
13153 // dst = atomic-fetch-op MI.addr, MI.val
13159 // t1 = LOAD MI.addr
13161 // t4 = phi(t1, t3 / loop)
13162 // t2 = OP MI.val, t4
13164 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
13170 MachineBasicBlock *
13171 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
13172 MachineBasicBlock *MBB) const {
13173 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13174 DebugLoc DL = MI->getDebugLoc();
13176 MachineFunction *MF = MBB->getParent();
13177 MachineRegisterInfo &MRI = MF->getRegInfo();
13179 const BasicBlock *BB = MBB->getBasicBlock();
13180 MachineFunction::iterator I = MBB;
13183 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
13184 "Unexpected number of operands");
13186 assert(MI->hasOneMemOperand() &&
13187 "Expected atomic-load-op to have one memoperand");
13189 // Memory Reference
13190 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13191 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13193 unsigned DstReg, SrcReg;
13194 unsigned MemOpndSlot;
13196 unsigned CurOp = 0;
13198 DstReg = MI->getOperand(CurOp++).getReg();
13199 MemOpndSlot = CurOp;
13200 CurOp += X86::AddrNumOperands;
13201 SrcReg = MI->getOperand(CurOp++).getReg();
13203 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
13204 MVT::SimpleValueType VT = *RC->vt_begin();
13205 unsigned t1 = MRI.createVirtualRegister(RC);
13206 unsigned t2 = MRI.createVirtualRegister(RC);
13207 unsigned t3 = MRI.createVirtualRegister(RC);
13208 unsigned t4 = MRI.createVirtualRegister(RC);
13209 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
13211 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
13212 unsigned LOADOpc = getLoadOpcode(VT);
13214 // For the atomic load-arith operator, we generate
13217 // t1 = LOAD [MI.addr]
13219 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
13220 // t1 = OP MI.val, EAX
13222 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
13228 MachineBasicBlock *thisMBB = MBB;
13229 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13230 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13231 MF->insert(I, mainMBB);
13232 MF->insert(I, sinkMBB);
13234 MachineInstrBuilder MIB;
13236 // Transfer the remainder of BB and its successor edges to sinkMBB.
13237 sinkMBB->splice(sinkMBB->begin(), MBB,
13238 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13239 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13242 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
13243 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13244 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13246 NewMO.setIsKill(false);
13247 MIB.addOperand(NewMO);
13249 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13250 unsigned flags = (*MMOI)->getFlags();
13251 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13252 MachineMemOperand *MMO =
13253 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13254 (*MMOI)->getSize(),
13255 (*MMOI)->getBaseAlignment(),
13256 (*MMOI)->getTBAAInfo(),
13257 (*MMOI)->getRanges());
13258 MIB.addMemOperand(MMO);
13261 thisMBB->addSuccessor(mainMBB);
13264 MachineBasicBlock *origMainMBB = mainMBB;
13267 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
13268 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13270 unsigned Opc = MI->getOpcode();
13273 llvm_unreachable("Unhandled atomic-load-op opcode!");
13274 case X86::ATOMAND8:
13275 case X86::ATOMAND16:
13276 case X86::ATOMAND32:
13277 case X86::ATOMAND64:
13279 case X86::ATOMOR16:
13280 case X86::ATOMOR32:
13281 case X86::ATOMOR64:
13282 case X86::ATOMXOR8:
13283 case X86::ATOMXOR16:
13284 case X86::ATOMXOR32:
13285 case X86::ATOMXOR64: {
13286 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
13287 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
13291 case X86::ATOMNAND8:
13292 case X86::ATOMNAND16:
13293 case X86::ATOMNAND32:
13294 case X86::ATOMNAND64: {
13295 unsigned Tmp = MRI.createVirtualRegister(RC);
13297 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
13298 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
13300 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
13303 case X86::ATOMMAX8:
13304 case X86::ATOMMAX16:
13305 case X86::ATOMMAX32:
13306 case X86::ATOMMAX64:
13307 case X86::ATOMMIN8:
13308 case X86::ATOMMIN16:
13309 case X86::ATOMMIN32:
13310 case X86::ATOMMIN64:
13311 case X86::ATOMUMAX8:
13312 case X86::ATOMUMAX16:
13313 case X86::ATOMUMAX32:
13314 case X86::ATOMUMAX64:
13315 case X86::ATOMUMIN8:
13316 case X86::ATOMUMIN16:
13317 case X86::ATOMUMIN32:
13318 case X86::ATOMUMIN64: {
13320 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
13322 BuildMI(mainMBB, DL, TII->get(CMPOpc))
13326 if (Subtarget->hasCMov()) {
13327 if (VT != MVT::i8) {
13329 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
13333 // Promote i8 to i32 to use CMOV32
13334 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13335 const TargetRegisterClass *RC32 =
13336 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
13337 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
13338 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
13339 unsigned Tmp = MRI.createVirtualRegister(RC32);
13341 unsigned Undef = MRI.createVirtualRegister(RC32);
13342 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
13344 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
13347 .addImm(X86::sub_8bit);
13348 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
13351 .addImm(X86::sub_8bit);
13353 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
13357 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
13358 .addReg(Tmp, 0, X86::sub_8bit);
13361 // Use pseudo select and lower them.
13362 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
13363 "Invalid atomic-load-op transformation!");
13364 unsigned SelOpc = getPseudoCMOVOpc(VT);
13365 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
13366 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
13367 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
13368 .addReg(SrcReg).addReg(t4)
13370 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13371 // Replace the original PHI node as mainMBB is changed after CMOV
13373 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
13374 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13375 Phi->eraseFromParent();
13381 // Copy PhyReg back from virtual register.
13382 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
13385 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13386 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13387 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13389 NewMO.setIsKill(false);
13390 MIB.addOperand(NewMO);
13393 MIB.setMemRefs(MMOBegin, MMOEnd);
13395 // Copy PhyReg back to virtual register.
13396 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
13399 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13401 mainMBB->addSuccessor(origMainMBB);
13402 mainMBB->addSuccessor(sinkMBB);
13405 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13406 TII->get(TargetOpcode::COPY), DstReg)
13409 MI->eraseFromParent();
13413 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
13414 // instructions. They will be translated into a spin-loop or compare-exchange
13418 // dst = atomic-fetch-op MI.addr, MI.val
13424 // t1L = LOAD [MI.addr + 0]
13425 // t1H = LOAD [MI.addr + 4]
13427 // t4L = phi(t1L, t3L / loop)
13428 // t4H = phi(t1H, t3H / loop)
13429 // t2L = OP MI.val.lo, t4L
13430 // t2H = OP MI.val.hi, t4H
13435 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13443 MachineBasicBlock *
13444 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
13445 MachineBasicBlock *MBB) const {
13446 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13447 DebugLoc DL = MI->getDebugLoc();
13449 MachineFunction *MF = MBB->getParent();
13450 MachineRegisterInfo &MRI = MF->getRegInfo();
13452 const BasicBlock *BB = MBB->getBasicBlock();
13453 MachineFunction::iterator I = MBB;
13456 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
13457 "Unexpected number of operands");
13459 assert(MI->hasOneMemOperand() &&
13460 "Expected atomic-load-op32 to have one memoperand");
13462 // Memory Reference
13463 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13464 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13466 unsigned DstLoReg, DstHiReg;
13467 unsigned SrcLoReg, SrcHiReg;
13468 unsigned MemOpndSlot;
13470 unsigned CurOp = 0;
13472 DstLoReg = MI->getOperand(CurOp++).getReg();
13473 DstHiReg = MI->getOperand(CurOp++).getReg();
13474 MemOpndSlot = CurOp;
13475 CurOp += X86::AddrNumOperands;
13476 SrcLoReg = MI->getOperand(CurOp++).getReg();
13477 SrcHiReg = MI->getOperand(CurOp++).getReg();
13479 const TargetRegisterClass *RC = &X86::GR32RegClass;
13480 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
13482 unsigned t1L = MRI.createVirtualRegister(RC);
13483 unsigned t1H = MRI.createVirtualRegister(RC);
13484 unsigned t2L = MRI.createVirtualRegister(RC);
13485 unsigned t2H = MRI.createVirtualRegister(RC);
13486 unsigned t3L = MRI.createVirtualRegister(RC);
13487 unsigned t3H = MRI.createVirtualRegister(RC);
13488 unsigned t4L = MRI.createVirtualRegister(RC);
13489 unsigned t4H = MRI.createVirtualRegister(RC);
13491 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
13492 unsigned LOADOpc = X86::MOV32rm;
13494 // For the atomic load-arith operator, we generate
13497 // t1L = LOAD [MI.addr + 0]
13498 // t1H = LOAD [MI.addr + 4]
13500 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
13501 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
13502 // t2L = OP MI.val.lo, t4L
13503 // t2H = OP MI.val.hi, t4H
13506 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13514 MachineBasicBlock *thisMBB = MBB;
13515 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13516 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13517 MF->insert(I, mainMBB);
13518 MF->insert(I, sinkMBB);
13520 MachineInstrBuilder MIB;
13522 // Transfer the remainder of BB and its successor edges to sinkMBB.
13523 sinkMBB->splice(sinkMBB->begin(), MBB,
13524 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13525 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13529 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
13530 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13531 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13533 NewMO.setIsKill(false);
13534 MIB.addOperand(NewMO);
13536 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13537 unsigned flags = (*MMOI)->getFlags();
13538 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13539 MachineMemOperand *MMO =
13540 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13541 (*MMOI)->getSize(),
13542 (*MMOI)->getBaseAlignment(),
13543 (*MMOI)->getTBAAInfo(),
13544 (*MMOI)->getRanges());
13545 MIB.addMemOperand(MMO);
13547 MachineInstr *LowMI = MIB;
13550 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
13551 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13552 if (i == X86::AddrDisp) {
13553 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
13555 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13557 NewMO.setIsKill(false);
13558 MIB.addOperand(NewMO);
13561 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
13563 thisMBB->addSuccessor(mainMBB);
13566 MachineBasicBlock *origMainMBB = mainMBB;
13569 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
13570 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
13571 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
13572 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
13574 unsigned Opc = MI->getOpcode();
13577 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
13578 case X86::ATOMAND6432:
13579 case X86::ATOMOR6432:
13580 case X86::ATOMXOR6432:
13581 case X86::ATOMADD6432:
13582 case X86::ATOMSUB6432: {
13584 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13585 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
13587 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
13591 case X86::ATOMNAND6432: {
13592 unsigned HiOpc, NOTOpc;
13593 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
13594 unsigned TmpL = MRI.createVirtualRegister(RC);
13595 unsigned TmpH = MRI.createVirtualRegister(RC);
13596 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
13598 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
13600 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
13601 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
13604 case X86::ATOMMAX6432:
13605 case X86::ATOMMIN6432:
13606 case X86::ATOMUMAX6432:
13607 case X86::ATOMUMIN6432: {
13609 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13610 unsigned cL = MRI.createVirtualRegister(RC8);
13611 unsigned cH = MRI.createVirtualRegister(RC8);
13612 unsigned cL32 = MRI.createVirtualRegister(RC);
13613 unsigned cH32 = MRI.createVirtualRegister(RC);
13614 unsigned cc = MRI.createVirtualRegister(RC);
13615 // cl := cmp src_lo, lo
13616 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13617 .addReg(SrcLoReg).addReg(t4L);
13618 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
13619 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
13620 // ch := cmp src_hi, hi
13621 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13622 .addReg(SrcHiReg).addReg(t4H);
13623 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
13624 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
13625 // cc := if (src_hi == hi) ? cl : ch;
13626 if (Subtarget->hasCMov()) {
13627 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
13628 .addReg(cH32).addReg(cL32);
13630 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
13631 .addReg(cH32).addReg(cL32)
13632 .addImm(X86::COND_E);
13633 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13635 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
13636 if (Subtarget->hasCMov()) {
13637 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
13638 .addReg(SrcLoReg).addReg(t4L);
13639 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
13640 .addReg(SrcHiReg).addReg(t4H);
13642 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
13643 .addReg(SrcLoReg).addReg(t4L)
13644 .addImm(X86::COND_NE);
13645 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13646 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
13647 // 2nd CMOV lowering.
13648 mainMBB->addLiveIn(X86::EFLAGS);
13649 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
13650 .addReg(SrcHiReg).addReg(t4H)
13651 .addImm(X86::COND_NE);
13652 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13653 // Replace the original PHI node as mainMBB is changed after CMOV
13655 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
13656 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
13657 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
13658 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
13659 PhiL->eraseFromParent();
13660 PhiH->eraseFromParent();
13664 case X86::ATOMSWAP6432: {
13666 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13667 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
13668 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
13673 // Copy EDX:EAX back from HiReg:LoReg
13674 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
13675 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
13676 // Copy ECX:EBX from t1H:t1L
13677 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
13678 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
13680 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13681 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13682 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13684 NewMO.setIsKill(false);
13685 MIB.addOperand(NewMO);
13687 MIB.setMemRefs(MMOBegin, MMOEnd);
13689 // Copy EDX:EAX back to t3H:t3L
13690 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
13691 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
13693 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13695 mainMBB->addSuccessor(origMainMBB);
13696 mainMBB->addSuccessor(sinkMBB);
13699 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13700 TII->get(TargetOpcode::COPY), DstLoReg)
13702 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13703 TII->get(TargetOpcode::COPY), DstHiReg)
13706 MI->eraseFromParent();
13710 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
13711 // or XMM0_V32I8 in AVX all of this code can be replaced with that
13712 // in the .td file.
13713 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
13714 const TargetInstrInfo *TII) {
13716 switch (MI->getOpcode()) {
13717 default: llvm_unreachable("illegal opcode!");
13718 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
13719 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
13720 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
13721 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
13722 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
13723 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
13724 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
13725 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
13728 DebugLoc dl = MI->getDebugLoc();
13729 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13731 unsigned NumArgs = MI->getNumOperands();
13732 for (unsigned i = 1; i < NumArgs; ++i) {
13733 MachineOperand &Op = MI->getOperand(i);
13734 if (!(Op.isReg() && Op.isImplicit()))
13735 MIB.addOperand(Op);
13737 if (MI->hasOneMemOperand())
13738 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13740 BuildMI(*BB, MI, dl,
13741 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13742 .addReg(X86::XMM0);
13744 MI->eraseFromParent();
13748 // FIXME: Custom handling because TableGen doesn't support multiple implicit
13749 // defs in an instruction pattern
13750 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
13751 const TargetInstrInfo *TII) {
13753 switch (MI->getOpcode()) {
13754 default: llvm_unreachable("illegal opcode!");
13755 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
13756 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
13757 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
13758 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
13759 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
13760 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
13761 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
13762 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
13765 DebugLoc dl = MI->getDebugLoc();
13766 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13768 unsigned NumArgs = MI->getNumOperands(); // remove the results
13769 for (unsigned i = 1; i < NumArgs; ++i) {
13770 MachineOperand &Op = MI->getOperand(i);
13771 if (!(Op.isReg() && Op.isImplicit()))
13772 MIB.addOperand(Op);
13774 if (MI->hasOneMemOperand())
13775 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13777 BuildMI(*BB, MI, dl,
13778 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13781 MI->eraseFromParent();
13785 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
13786 const TargetInstrInfo *TII,
13787 const X86Subtarget* Subtarget) {
13788 DebugLoc dl = MI->getDebugLoc();
13790 // Address into RAX/EAX, other two args into ECX, EDX.
13791 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
13792 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13793 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
13794 for (int i = 0; i < X86::AddrNumOperands; ++i)
13795 MIB.addOperand(MI->getOperand(i));
13797 unsigned ValOps = X86::AddrNumOperands;
13798 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
13799 .addReg(MI->getOperand(ValOps).getReg());
13800 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
13801 .addReg(MI->getOperand(ValOps+1).getReg());
13803 // The instruction doesn't actually take any operands though.
13804 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
13806 MI->eraseFromParent(); // The pseudo is gone now.
13810 MachineBasicBlock *
13811 X86TargetLowering::EmitVAARG64WithCustomInserter(
13813 MachineBasicBlock *MBB) const {
13814 // Emit va_arg instruction on X86-64.
13816 // Operands to this pseudo-instruction:
13817 // 0 ) Output : destination address (reg)
13818 // 1-5) Input : va_list address (addr, i64mem)
13819 // 6 ) ArgSize : Size (in bytes) of vararg type
13820 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
13821 // 8 ) Align : Alignment of type
13822 // 9 ) EFLAGS (implicit-def)
13824 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
13825 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
13827 unsigned DestReg = MI->getOperand(0).getReg();
13828 MachineOperand &Base = MI->getOperand(1);
13829 MachineOperand &Scale = MI->getOperand(2);
13830 MachineOperand &Index = MI->getOperand(3);
13831 MachineOperand &Disp = MI->getOperand(4);
13832 MachineOperand &Segment = MI->getOperand(5);
13833 unsigned ArgSize = MI->getOperand(6).getImm();
13834 unsigned ArgMode = MI->getOperand(7).getImm();
13835 unsigned Align = MI->getOperand(8).getImm();
13837 // Memory Reference
13838 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
13839 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13840 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13842 // Machine Information
13843 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13844 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
13845 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
13846 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
13847 DebugLoc DL = MI->getDebugLoc();
13849 // struct va_list {
13852 // i64 overflow_area (address)
13853 // i64 reg_save_area (address)
13855 // sizeof(va_list) = 24
13856 // alignment(va_list) = 8
13858 unsigned TotalNumIntRegs = 6;
13859 unsigned TotalNumXMMRegs = 8;
13860 bool UseGPOffset = (ArgMode == 1);
13861 bool UseFPOffset = (ArgMode == 2);
13862 unsigned MaxOffset = TotalNumIntRegs * 8 +
13863 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
13865 /* Align ArgSize to a multiple of 8 */
13866 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
13867 bool NeedsAlign = (Align > 8);
13869 MachineBasicBlock *thisMBB = MBB;
13870 MachineBasicBlock *overflowMBB;
13871 MachineBasicBlock *offsetMBB;
13872 MachineBasicBlock *endMBB;
13874 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
13875 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
13876 unsigned OffsetReg = 0;
13878 if (!UseGPOffset && !UseFPOffset) {
13879 // If we only pull from the overflow region, we don't create a branch.
13880 // We don't need to alter control flow.
13881 OffsetDestReg = 0; // unused
13882 OverflowDestReg = DestReg;
13885 overflowMBB = thisMBB;
13888 // First emit code to check if gp_offset (or fp_offset) is below the bound.
13889 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
13890 // If not, pull from overflow_area. (branch to overflowMBB)
13895 // offsetMBB overflowMBB
13900 // Registers for the PHI in endMBB
13901 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
13902 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
13904 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13905 MachineFunction *MF = MBB->getParent();
13906 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13907 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13908 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13910 MachineFunction::iterator MBBIter = MBB;
13913 // Insert the new basic blocks
13914 MF->insert(MBBIter, offsetMBB);
13915 MF->insert(MBBIter, overflowMBB);
13916 MF->insert(MBBIter, endMBB);
13918 // Transfer the remainder of MBB and its successor edges to endMBB.
13919 endMBB->splice(endMBB->begin(), thisMBB,
13920 llvm::next(MachineBasicBlock::iterator(MI)),
13922 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
13924 // Make offsetMBB and overflowMBB successors of thisMBB
13925 thisMBB->addSuccessor(offsetMBB);
13926 thisMBB->addSuccessor(overflowMBB);
13928 // endMBB is a successor of both offsetMBB and overflowMBB
13929 offsetMBB->addSuccessor(endMBB);
13930 overflowMBB->addSuccessor(endMBB);
13932 // Load the offset value into a register
13933 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13934 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13938 .addDisp(Disp, UseFPOffset ? 4 : 0)
13939 .addOperand(Segment)
13940 .setMemRefs(MMOBegin, MMOEnd);
13942 // Check if there is enough room left to pull this argument.
13943 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13945 .addImm(MaxOffset + 8 - ArgSizeA8);
13947 // Branch to "overflowMBB" if offset >= max
13948 // Fall through to "offsetMBB" otherwise
13949 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13950 .addMBB(overflowMBB);
13953 // In offsetMBB, emit code to use the reg_save_area.
13955 assert(OffsetReg != 0);
13957 // Read the reg_save_area address.
13958 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
13959 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13964 .addOperand(Segment)
13965 .setMemRefs(MMOBegin, MMOEnd);
13967 // Zero-extend the offset
13968 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
13969 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13972 .addImm(X86::sub_32bit);
13974 // Add the offset to the reg_save_area to get the final address.
13975 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13976 .addReg(OffsetReg64)
13977 .addReg(RegSaveReg);
13979 // Compute the offset for the next argument
13980 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13981 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13983 .addImm(UseFPOffset ? 16 : 8);
13985 // Store it back into the va_list.
13986 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13990 .addDisp(Disp, UseFPOffset ? 4 : 0)
13991 .addOperand(Segment)
13992 .addReg(NextOffsetReg)
13993 .setMemRefs(MMOBegin, MMOEnd);
13996 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
14001 // Emit code to use overflow area
14004 // Load the overflow_area address into a register.
14005 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
14006 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
14011 .addOperand(Segment)
14012 .setMemRefs(MMOBegin, MMOEnd);
14014 // If we need to align it, do so. Otherwise, just copy the address
14015 // to OverflowDestReg.
14017 // Align the overflow address
14018 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
14019 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
14021 // aligned_addr = (addr + (align-1)) & ~(align-1)
14022 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
14023 .addReg(OverflowAddrReg)
14026 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
14028 .addImm(~(uint64_t)(Align-1));
14030 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
14031 .addReg(OverflowAddrReg);
14034 // Compute the next overflow address after this argument.
14035 // (the overflow address should be kept 8-byte aligned)
14036 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
14037 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
14038 .addReg(OverflowDestReg)
14039 .addImm(ArgSizeA8);
14041 // Store the new overflow address.
14042 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
14047 .addOperand(Segment)
14048 .addReg(NextAddrReg)
14049 .setMemRefs(MMOBegin, MMOEnd);
14051 // If we branched, emit the PHI to the front of endMBB.
14053 BuildMI(*endMBB, endMBB->begin(), DL,
14054 TII->get(X86::PHI), DestReg)
14055 .addReg(OffsetDestReg).addMBB(offsetMBB)
14056 .addReg(OverflowDestReg).addMBB(overflowMBB);
14059 // Erase the pseudo instruction
14060 MI->eraseFromParent();
14065 MachineBasicBlock *
14066 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
14068 MachineBasicBlock *MBB) const {
14069 // Emit code to save XMM registers to the stack. The ABI says that the
14070 // number of registers to save is given in %al, so it's theoretically
14071 // possible to do an indirect jump trick to avoid saving all of them,
14072 // however this code takes a simpler approach and just executes all
14073 // of the stores if %al is non-zero. It's less code, and it's probably
14074 // easier on the hardware branch predictor, and stores aren't all that
14075 // expensive anyway.
14077 // Create the new basic blocks. One block contains all the XMM stores,
14078 // and one block is the final destination regardless of whether any
14079 // stores were performed.
14080 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14081 MachineFunction *F = MBB->getParent();
14082 MachineFunction::iterator MBBIter = MBB;
14084 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
14085 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
14086 F->insert(MBBIter, XMMSaveMBB);
14087 F->insert(MBBIter, EndMBB);
14089 // Transfer the remainder of MBB and its successor edges to EndMBB.
14090 EndMBB->splice(EndMBB->begin(), MBB,
14091 llvm::next(MachineBasicBlock::iterator(MI)),
14093 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
14095 // The original block will now fall through to the XMM save block.
14096 MBB->addSuccessor(XMMSaveMBB);
14097 // The XMMSaveMBB will fall through to the end block.
14098 XMMSaveMBB->addSuccessor(EndMBB);
14100 // Now add the instructions.
14101 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14102 DebugLoc DL = MI->getDebugLoc();
14104 unsigned CountReg = MI->getOperand(0).getReg();
14105 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
14106 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
14108 if (!Subtarget->isTargetWin64()) {
14109 // If %al is 0, branch around the XMM save block.
14110 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
14111 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
14112 MBB->addSuccessor(EndMBB);
14115 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
14116 // In the XMM save block, save all the XMM argument registers.
14117 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
14118 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
14119 MachineMemOperand *MMO =
14120 F->getMachineMemOperand(
14121 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
14122 MachineMemOperand::MOStore,
14123 /*Size=*/16, /*Align=*/16);
14124 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
14125 .addFrameIndex(RegSaveFrameIndex)
14126 .addImm(/*Scale=*/1)
14127 .addReg(/*IndexReg=*/0)
14128 .addImm(/*Disp=*/Offset)
14129 .addReg(/*Segment=*/0)
14130 .addReg(MI->getOperand(i).getReg())
14131 .addMemOperand(MMO);
14134 MI->eraseFromParent(); // The pseudo instruction is gone now.
14139 // The EFLAGS operand of SelectItr might be missing a kill marker
14140 // because there were multiple uses of EFLAGS, and ISel didn't know
14141 // which to mark. Figure out whether SelectItr should have had a
14142 // kill marker, and set it if it should. Returns the correct kill
14144 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
14145 MachineBasicBlock* BB,
14146 const TargetRegisterInfo* TRI) {
14147 // Scan forward through BB for a use/def of EFLAGS.
14148 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
14149 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
14150 const MachineInstr& mi = *miI;
14151 if (mi.readsRegister(X86::EFLAGS))
14153 if (mi.definesRegister(X86::EFLAGS))
14154 break; // Should have kill-flag - update below.
14157 // If we hit the end of the block, check whether EFLAGS is live into a
14159 if (miI == BB->end()) {
14160 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
14161 sEnd = BB->succ_end();
14162 sItr != sEnd; ++sItr) {
14163 MachineBasicBlock* succ = *sItr;
14164 if (succ->isLiveIn(X86::EFLAGS))
14169 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
14170 // out. SelectMI should have a kill flag on EFLAGS.
14171 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
14175 MachineBasicBlock *
14176 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
14177 MachineBasicBlock *BB) const {
14178 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14179 DebugLoc DL = MI->getDebugLoc();
14181 // To "insert" a SELECT_CC instruction, we actually have to insert the
14182 // diamond control-flow pattern. The incoming instruction knows the
14183 // destination vreg to set, the condition code register to branch on, the
14184 // true/false values to select between, and a branch opcode to use.
14185 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14186 MachineFunction::iterator It = BB;
14192 // cmpTY ccX, r1, r2
14194 // fallthrough --> copy0MBB
14195 MachineBasicBlock *thisMBB = BB;
14196 MachineFunction *F = BB->getParent();
14197 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
14198 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
14199 F->insert(It, copy0MBB);
14200 F->insert(It, sinkMBB);
14202 // If the EFLAGS register isn't dead in the terminator, then claim that it's
14203 // live into the sink and copy blocks.
14204 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14205 if (!MI->killsRegister(X86::EFLAGS) &&
14206 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
14207 copy0MBB->addLiveIn(X86::EFLAGS);
14208 sinkMBB->addLiveIn(X86::EFLAGS);
14211 // Transfer the remainder of BB and its successor edges to sinkMBB.
14212 sinkMBB->splice(sinkMBB->begin(), BB,
14213 llvm::next(MachineBasicBlock::iterator(MI)),
14215 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
14217 // Add the true and fallthrough blocks as its successors.
14218 BB->addSuccessor(copy0MBB);
14219 BB->addSuccessor(sinkMBB);
14221 // Create the conditional branch instruction.
14223 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
14224 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
14227 // %FalseValue = ...
14228 // # fallthrough to sinkMBB
14229 copy0MBB->addSuccessor(sinkMBB);
14232 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
14234 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14235 TII->get(X86::PHI), MI->getOperand(0).getReg())
14236 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
14237 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
14239 MI->eraseFromParent(); // The pseudo instruction is gone now.
14243 MachineBasicBlock *
14244 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
14245 bool Is64Bit) const {
14246 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14247 DebugLoc DL = MI->getDebugLoc();
14248 MachineFunction *MF = BB->getParent();
14249 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14251 assert(getTargetMachine().Options.EnableSegmentedStacks);
14253 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
14254 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
14257 // ... [Till the alloca]
14258 // If stacklet is not large enough, jump to mallocMBB
14261 // Allocate by subtracting from RSP
14262 // Jump to continueMBB
14265 // Allocate by call to runtime
14269 // [rest of original BB]
14272 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14273 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14274 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14276 MachineRegisterInfo &MRI = MF->getRegInfo();
14277 const TargetRegisterClass *AddrRegClass =
14278 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
14280 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14281 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14282 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
14283 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
14284 sizeVReg = MI->getOperand(1).getReg(),
14285 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
14287 MachineFunction::iterator MBBIter = BB;
14290 MF->insert(MBBIter, bumpMBB);
14291 MF->insert(MBBIter, mallocMBB);
14292 MF->insert(MBBIter, continueMBB);
14294 continueMBB->splice(continueMBB->begin(), BB, llvm::next
14295 (MachineBasicBlock::iterator(MI)), BB->end());
14296 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
14298 // Add code to the main basic block to check if the stack limit has been hit,
14299 // and if so, jump to mallocMBB otherwise to bumpMBB.
14300 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
14301 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
14302 .addReg(tmpSPVReg).addReg(sizeVReg);
14303 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
14304 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
14305 .addReg(SPLimitVReg);
14306 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
14308 // bumpMBB simply decreases the stack pointer, since we know the current
14309 // stacklet has enough space.
14310 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
14311 .addReg(SPLimitVReg);
14312 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
14313 .addReg(SPLimitVReg);
14314 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14316 // Calls into a routine in libgcc to allocate more space from the heap.
14317 const uint32_t *RegMask =
14318 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14320 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
14322 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
14323 .addExternalSymbol("__morestack_allocate_stack_space")
14324 .addRegMask(RegMask)
14325 .addReg(X86::RDI, RegState::Implicit)
14326 .addReg(X86::RAX, RegState::ImplicitDefine);
14328 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
14330 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
14331 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
14332 .addExternalSymbol("__morestack_allocate_stack_space")
14333 .addRegMask(RegMask)
14334 .addReg(X86::EAX, RegState::ImplicitDefine);
14338 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
14341 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
14342 .addReg(Is64Bit ? X86::RAX : X86::EAX);
14343 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14345 // Set up the CFG correctly.
14346 BB->addSuccessor(bumpMBB);
14347 BB->addSuccessor(mallocMBB);
14348 mallocMBB->addSuccessor(continueMBB);
14349 bumpMBB->addSuccessor(continueMBB);
14351 // Take care of the PHI nodes.
14352 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
14353 MI->getOperand(0).getReg())
14354 .addReg(mallocPtrVReg).addMBB(mallocMBB)
14355 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
14357 // Delete the original pseudo instruction.
14358 MI->eraseFromParent();
14361 return continueMBB;
14364 MachineBasicBlock *
14365 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
14366 MachineBasicBlock *BB) const {
14367 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14368 DebugLoc DL = MI->getDebugLoc();
14370 assert(!Subtarget->isTargetEnvMacho());
14372 // The lowering is pretty easy: we're just emitting the call to _alloca. The
14373 // non-trivial part is impdef of ESP.
14375 if (Subtarget->isTargetWin64()) {
14376 if (Subtarget->isTargetCygMing()) {
14377 // ___chkstk(Mingw64):
14378 // Clobbers R10, R11, RAX and EFLAGS.
14380 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14381 .addExternalSymbol("___chkstk")
14382 .addReg(X86::RAX, RegState::Implicit)
14383 .addReg(X86::RSP, RegState::Implicit)
14384 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
14385 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
14386 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14388 // __chkstk(MSVCRT): does not update stack pointer.
14389 // Clobbers R10, R11 and EFLAGS.
14390 // FIXME: RAX(allocated size) might be reused and not killed.
14391 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14392 .addExternalSymbol("__chkstk")
14393 .addReg(X86::RAX, RegState::Implicit)
14394 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14395 // RAX has the offset to subtracted from RSP.
14396 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
14401 const char *StackProbeSymbol =
14402 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
14404 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
14405 .addExternalSymbol(StackProbeSymbol)
14406 .addReg(X86::EAX, RegState::Implicit)
14407 .addReg(X86::ESP, RegState::Implicit)
14408 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
14409 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
14410 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14413 MI->eraseFromParent(); // The pseudo instruction is gone now.
14417 MachineBasicBlock *
14418 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
14419 MachineBasicBlock *BB) const {
14420 // This is pretty easy. We're taking the value that we received from
14421 // our load from the relocation, sticking it in either RDI (x86-64)
14422 // or EAX and doing an indirect call. The return value will then
14423 // be in the normal return register.
14424 const X86InstrInfo *TII
14425 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
14426 DebugLoc DL = MI->getDebugLoc();
14427 MachineFunction *F = BB->getParent();
14429 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
14430 assert(MI->getOperand(3).isGlobal() && "This should be a global");
14432 // Get a register mask for the lowered call.
14433 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
14434 // proper register mask.
14435 const uint32_t *RegMask =
14436 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14437 if (Subtarget->is64Bit()) {
14438 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14439 TII->get(X86::MOV64rm), X86::RDI)
14441 .addImm(0).addReg(0)
14442 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14443 MI->getOperand(3).getTargetFlags())
14445 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
14446 addDirectMem(MIB, X86::RDI);
14447 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
14448 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
14449 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14450 TII->get(X86::MOV32rm), X86::EAX)
14452 .addImm(0).addReg(0)
14453 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14454 MI->getOperand(3).getTargetFlags())
14456 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14457 addDirectMem(MIB, X86::EAX);
14458 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14460 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14461 TII->get(X86::MOV32rm), X86::EAX)
14462 .addReg(TII->getGlobalBaseReg(F))
14463 .addImm(0).addReg(0)
14464 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14465 MI->getOperand(3).getTargetFlags())
14467 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14468 addDirectMem(MIB, X86::EAX);
14469 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14472 MI->eraseFromParent(); // The pseudo instruction is gone now.
14476 MachineBasicBlock *
14477 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
14478 MachineBasicBlock *MBB) const {
14479 DebugLoc DL = MI->getDebugLoc();
14480 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14482 MachineFunction *MF = MBB->getParent();
14483 MachineRegisterInfo &MRI = MF->getRegInfo();
14485 const BasicBlock *BB = MBB->getBasicBlock();
14486 MachineFunction::iterator I = MBB;
14489 // Memory Reference
14490 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14491 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14494 unsigned MemOpndSlot = 0;
14496 unsigned CurOp = 0;
14498 DstReg = MI->getOperand(CurOp++).getReg();
14499 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14500 assert(RC->hasType(MVT::i32) && "Invalid destination!");
14501 unsigned mainDstReg = MRI.createVirtualRegister(RC);
14502 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
14504 MemOpndSlot = CurOp;
14506 MVT PVT = getPointerTy();
14507 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14508 "Invalid Pointer Size!");
14510 // For v = setjmp(buf), we generate
14513 // buf[LabelOffset] = restoreMBB
14514 // SjLjSetup restoreMBB
14520 // v = phi(main, restore)
14525 MachineBasicBlock *thisMBB = MBB;
14526 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14527 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14528 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
14529 MF->insert(I, mainMBB);
14530 MF->insert(I, sinkMBB);
14531 MF->push_back(restoreMBB);
14533 MachineInstrBuilder MIB;
14535 // Transfer the remainder of BB and its successor edges to sinkMBB.
14536 sinkMBB->splice(sinkMBB->begin(), MBB,
14537 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14538 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14541 unsigned PtrStoreOpc = 0;
14542 unsigned LabelReg = 0;
14543 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14544 Reloc::Model RM = getTargetMachine().getRelocationModel();
14545 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
14546 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
14548 // Prepare IP either in reg or imm.
14549 if (!UseImmLabel) {
14550 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
14551 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
14552 LabelReg = MRI.createVirtualRegister(PtrRC);
14553 if (Subtarget->is64Bit()) {
14554 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
14558 .addMBB(restoreMBB)
14561 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
14562 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
14563 .addReg(XII->getGlobalBaseReg(MF))
14566 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
14570 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
14572 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
14573 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14574 if (i == X86::AddrDisp)
14575 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
14577 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
14580 MIB.addReg(LabelReg);
14582 MIB.addMBB(restoreMBB);
14583 MIB.setMemRefs(MMOBegin, MMOEnd);
14585 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
14586 .addMBB(restoreMBB);
14587 MIB.addRegMask(RegInfo->getNoPreservedMask());
14588 thisMBB->addSuccessor(mainMBB);
14589 thisMBB->addSuccessor(restoreMBB);
14593 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
14594 mainMBB->addSuccessor(sinkMBB);
14597 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14598 TII->get(X86::PHI), DstReg)
14599 .addReg(mainDstReg).addMBB(mainMBB)
14600 .addReg(restoreDstReg).addMBB(restoreMBB);
14603 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
14604 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
14605 restoreMBB->addSuccessor(sinkMBB);
14607 MI->eraseFromParent();
14611 MachineBasicBlock *
14612 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
14613 MachineBasicBlock *MBB) const {
14614 DebugLoc DL = MI->getDebugLoc();
14615 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14617 MachineFunction *MF = MBB->getParent();
14618 MachineRegisterInfo &MRI = MF->getRegInfo();
14620 // Memory Reference
14621 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14622 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14624 MVT PVT = getPointerTy();
14625 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14626 "Invalid Pointer Size!");
14628 const TargetRegisterClass *RC =
14629 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
14630 unsigned Tmp = MRI.createVirtualRegister(RC);
14631 // Since FP is only updated here but NOT referenced, it's treated as GPR.
14632 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
14633 unsigned SP = RegInfo->getStackRegister();
14635 MachineInstrBuilder MIB;
14637 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14638 const int64_t SPOffset = 2 * PVT.getStoreSize();
14640 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
14641 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
14644 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
14645 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
14646 MIB.addOperand(MI->getOperand(i));
14647 MIB.setMemRefs(MMOBegin, MMOEnd);
14649 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
14650 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14651 if (i == X86::AddrDisp)
14652 MIB.addDisp(MI->getOperand(i), LabelOffset);
14654 MIB.addOperand(MI->getOperand(i));
14656 MIB.setMemRefs(MMOBegin, MMOEnd);
14658 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
14659 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14660 if (i == X86::AddrDisp)
14661 MIB.addDisp(MI->getOperand(i), SPOffset);
14663 MIB.addOperand(MI->getOperand(i));
14665 MIB.setMemRefs(MMOBegin, MMOEnd);
14667 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
14669 MI->eraseFromParent();
14673 MachineBasicBlock *
14674 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
14675 MachineBasicBlock *BB) const {
14676 switch (MI->getOpcode()) {
14677 default: llvm_unreachable("Unexpected instr type to insert");
14678 case X86::TAILJMPd64:
14679 case X86::TAILJMPr64:
14680 case X86::TAILJMPm64:
14681 llvm_unreachable("TAILJMP64 would not be touched here.");
14682 case X86::TCRETURNdi64:
14683 case X86::TCRETURNri64:
14684 case X86::TCRETURNmi64:
14686 case X86::WIN_ALLOCA:
14687 return EmitLoweredWinAlloca(MI, BB);
14688 case X86::SEG_ALLOCA_32:
14689 return EmitLoweredSegAlloca(MI, BB, false);
14690 case X86::SEG_ALLOCA_64:
14691 return EmitLoweredSegAlloca(MI, BB, true);
14692 case X86::TLSCall_32:
14693 case X86::TLSCall_64:
14694 return EmitLoweredTLSCall(MI, BB);
14695 case X86::CMOV_GR8:
14696 case X86::CMOV_FR32:
14697 case X86::CMOV_FR64:
14698 case X86::CMOV_V4F32:
14699 case X86::CMOV_V2F64:
14700 case X86::CMOV_V2I64:
14701 case X86::CMOV_V8F32:
14702 case X86::CMOV_V4F64:
14703 case X86::CMOV_V4I64:
14704 case X86::CMOV_GR16:
14705 case X86::CMOV_GR32:
14706 case X86::CMOV_RFP32:
14707 case X86::CMOV_RFP64:
14708 case X86::CMOV_RFP80:
14709 return EmitLoweredSelect(MI, BB);
14711 case X86::FP32_TO_INT16_IN_MEM:
14712 case X86::FP32_TO_INT32_IN_MEM:
14713 case X86::FP32_TO_INT64_IN_MEM:
14714 case X86::FP64_TO_INT16_IN_MEM:
14715 case X86::FP64_TO_INT32_IN_MEM:
14716 case X86::FP64_TO_INT64_IN_MEM:
14717 case X86::FP80_TO_INT16_IN_MEM:
14718 case X86::FP80_TO_INT32_IN_MEM:
14719 case X86::FP80_TO_INT64_IN_MEM: {
14720 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14721 DebugLoc DL = MI->getDebugLoc();
14723 // Change the floating point control register to use "round towards zero"
14724 // mode when truncating to an integer value.
14725 MachineFunction *F = BB->getParent();
14726 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
14727 addFrameReference(BuildMI(*BB, MI, DL,
14728 TII->get(X86::FNSTCW16m)), CWFrameIdx);
14730 // Load the old value of the high byte of the control word...
14732 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
14733 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
14736 // Set the high part to be round to zero...
14737 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
14740 // Reload the modified control word now...
14741 addFrameReference(BuildMI(*BB, MI, DL,
14742 TII->get(X86::FLDCW16m)), CWFrameIdx);
14744 // Restore the memory image of control word to original value
14745 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
14748 // Get the X86 opcode to use.
14750 switch (MI->getOpcode()) {
14751 default: llvm_unreachable("illegal opcode!");
14752 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
14753 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
14754 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
14755 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
14756 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
14757 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
14758 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
14759 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
14760 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
14764 MachineOperand &Op = MI->getOperand(0);
14766 AM.BaseType = X86AddressMode::RegBase;
14767 AM.Base.Reg = Op.getReg();
14769 AM.BaseType = X86AddressMode::FrameIndexBase;
14770 AM.Base.FrameIndex = Op.getIndex();
14772 Op = MI->getOperand(1);
14774 AM.Scale = Op.getImm();
14775 Op = MI->getOperand(2);
14777 AM.IndexReg = Op.getImm();
14778 Op = MI->getOperand(3);
14779 if (Op.isGlobal()) {
14780 AM.GV = Op.getGlobal();
14782 AM.Disp = Op.getImm();
14784 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
14785 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
14787 // Reload the original control word now.
14788 addFrameReference(BuildMI(*BB, MI, DL,
14789 TII->get(X86::FLDCW16m)), CWFrameIdx);
14791 MI->eraseFromParent(); // The pseudo instruction is gone now.
14794 // String/text processing lowering.
14795 case X86::PCMPISTRM128REG:
14796 case X86::VPCMPISTRM128REG:
14797 case X86::PCMPISTRM128MEM:
14798 case X86::VPCMPISTRM128MEM:
14799 case X86::PCMPESTRM128REG:
14800 case X86::VPCMPESTRM128REG:
14801 case X86::PCMPESTRM128MEM:
14802 case X86::VPCMPESTRM128MEM:
14803 assert(Subtarget->hasSSE42() &&
14804 "Target must have SSE4.2 or AVX features enabled");
14805 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
14807 // String/text processing lowering.
14808 case X86::PCMPISTRIREG:
14809 case X86::VPCMPISTRIREG:
14810 case X86::PCMPISTRIMEM:
14811 case X86::VPCMPISTRIMEM:
14812 case X86::PCMPESTRIREG:
14813 case X86::VPCMPESTRIREG:
14814 case X86::PCMPESTRIMEM:
14815 case X86::VPCMPESTRIMEM:
14816 assert(Subtarget->hasSSE42() &&
14817 "Target must have SSE4.2 or AVX features enabled");
14818 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
14820 // Thread synchronization.
14822 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
14826 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
14828 // Atomic Lowering.
14829 case X86::ATOMAND8:
14830 case X86::ATOMAND16:
14831 case X86::ATOMAND32:
14832 case X86::ATOMAND64:
14835 case X86::ATOMOR16:
14836 case X86::ATOMOR32:
14837 case X86::ATOMOR64:
14839 case X86::ATOMXOR16:
14840 case X86::ATOMXOR8:
14841 case X86::ATOMXOR32:
14842 case X86::ATOMXOR64:
14844 case X86::ATOMNAND8:
14845 case X86::ATOMNAND16:
14846 case X86::ATOMNAND32:
14847 case X86::ATOMNAND64:
14849 case X86::ATOMMAX8:
14850 case X86::ATOMMAX16:
14851 case X86::ATOMMAX32:
14852 case X86::ATOMMAX64:
14854 case X86::ATOMMIN8:
14855 case X86::ATOMMIN16:
14856 case X86::ATOMMIN32:
14857 case X86::ATOMMIN64:
14859 case X86::ATOMUMAX8:
14860 case X86::ATOMUMAX16:
14861 case X86::ATOMUMAX32:
14862 case X86::ATOMUMAX64:
14864 case X86::ATOMUMIN8:
14865 case X86::ATOMUMIN16:
14866 case X86::ATOMUMIN32:
14867 case X86::ATOMUMIN64:
14868 return EmitAtomicLoadArith(MI, BB);
14870 // This group does 64-bit operations on a 32-bit host.
14871 case X86::ATOMAND6432:
14872 case X86::ATOMOR6432:
14873 case X86::ATOMXOR6432:
14874 case X86::ATOMNAND6432:
14875 case X86::ATOMADD6432:
14876 case X86::ATOMSUB6432:
14877 case X86::ATOMMAX6432:
14878 case X86::ATOMMIN6432:
14879 case X86::ATOMUMAX6432:
14880 case X86::ATOMUMIN6432:
14881 case X86::ATOMSWAP6432:
14882 return EmitAtomicLoadArith6432(MI, BB);
14884 case X86::VASTART_SAVE_XMM_REGS:
14885 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
14887 case X86::VAARG_64:
14888 return EmitVAARG64WithCustomInserter(MI, BB);
14890 case X86::EH_SjLj_SetJmp32:
14891 case X86::EH_SjLj_SetJmp64:
14892 return emitEHSjLjSetJmp(MI, BB);
14894 case X86::EH_SjLj_LongJmp32:
14895 case X86::EH_SjLj_LongJmp64:
14896 return emitEHSjLjLongJmp(MI, BB);
14900 //===----------------------------------------------------------------------===//
14901 // X86 Optimization Hooks
14902 //===----------------------------------------------------------------------===//
14904 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
14907 const SelectionDAG &DAG,
14908 unsigned Depth) const {
14909 unsigned BitWidth = KnownZero.getBitWidth();
14910 unsigned Opc = Op.getOpcode();
14911 assert((Opc >= ISD::BUILTIN_OP_END ||
14912 Opc == ISD::INTRINSIC_WO_CHAIN ||
14913 Opc == ISD::INTRINSIC_W_CHAIN ||
14914 Opc == ISD::INTRINSIC_VOID) &&
14915 "Should use MaskedValueIsZero if you don't know whether Op"
14916 " is a target node!");
14918 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
14932 // These nodes' second result is a boolean.
14933 if (Op.getResNo() == 0)
14936 case X86ISD::SETCC:
14937 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
14939 case ISD::INTRINSIC_WO_CHAIN: {
14940 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14941 unsigned NumLoBits = 0;
14944 case Intrinsic::x86_sse_movmsk_ps:
14945 case Intrinsic::x86_avx_movmsk_ps_256:
14946 case Intrinsic::x86_sse2_movmsk_pd:
14947 case Intrinsic::x86_avx_movmsk_pd_256:
14948 case Intrinsic::x86_mmx_pmovmskb:
14949 case Intrinsic::x86_sse2_pmovmskb_128:
14950 case Intrinsic::x86_avx2_pmovmskb: {
14951 // High bits of movmskp{s|d}, pmovmskb are known zero.
14953 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14954 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
14955 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
14956 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
14957 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
14958 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
14959 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
14960 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
14962 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
14971 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
14972 unsigned Depth) const {
14973 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
14974 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14975 return Op.getValueType().getScalarType().getSizeInBits();
14981 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
14982 /// node is a GlobalAddress + offset.
14983 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
14984 const GlobalValue* &GA,
14985 int64_t &Offset) const {
14986 if (N->getOpcode() == X86ISD::Wrapper) {
14987 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
14988 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
14989 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
14993 return TargetLowering::isGAPlusOffset(N, GA, Offset);
14996 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
14997 /// same as extracting the high 128-bit part of 256-bit vector and then
14998 /// inserting the result into the low part of a new 256-bit vector
14999 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
15000 EVT VT = SVOp->getValueType(0);
15001 unsigned NumElems = VT.getVectorNumElements();
15003 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15004 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
15005 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15006 SVOp->getMaskElt(j) >= 0)
15012 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
15013 /// same as extracting the low 128-bit part of 256-bit vector and then
15014 /// inserting the result into the high part of a new 256-bit vector
15015 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
15016 EVT VT = SVOp->getValueType(0);
15017 unsigned NumElems = VT.getVectorNumElements();
15019 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15020 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
15021 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15022 SVOp->getMaskElt(j) >= 0)
15028 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
15029 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
15030 TargetLowering::DAGCombinerInfo &DCI,
15031 const X86Subtarget* Subtarget) {
15032 DebugLoc dl = N->getDebugLoc();
15033 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
15034 SDValue V1 = SVOp->getOperand(0);
15035 SDValue V2 = SVOp->getOperand(1);
15036 EVT VT = SVOp->getValueType(0);
15037 unsigned NumElems = VT.getVectorNumElements();
15039 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
15040 V2.getOpcode() == ISD::CONCAT_VECTORS) {
15044 // V UNDEF BUILD_VECTOR UNDEF
15046 // CONCAT_VECTOR CONCAT_VECTOR
15049 // RESULT: V + zero extended
15051 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
15052 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
15053 V1.getOperand(1).getOpcode() != ISD::UNDEF)
15056 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
15059 // To match the shuffle mask, the first half of the mask should
15060 // be exactly the first vector, and all the rest a splat with the
15061 // first element of the second one.
15062 for (unsigned i = 0; i != NumElems/2; ++i)
15063 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
15064 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
15067 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
15068 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
15069 if (Ld->hasNUsesOfValue(1, 0)) {
15070 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
15071 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
15073 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
15074 array_lengthof(Ops),
15076 Ld->getPointerInfo(),
15077 Ld->getAlignment(),
15078 false/*isVolatile*/, true/*ReadMem*/,
15079 false/*WriteMem*/);
15081 // Make sure the newly-created LOAD is in the same position as Ld in
15082 // terms of dependency. We create a TokenFactor for Ld and ResNode,
15083 // and update uses of Ld's output chain to use the TokenFactor.
15084 if (Ld->hasAnyUseOfValue(1)) {
15085 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
15086 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
15087 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
15088 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
15089 SDValue(ResNode.getNode(), 1));
15092 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
15096 // Emit a zeroed vector and insert the desired subvector on its
15098 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15099 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
15100 return DCI.CombineTo(N, InsV);
15103 //===--------------------------------------------------------------------===//
15104 // Combine some shuffles into subvector extracts and inserts:
15107 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15108 if (isShuffleHigh128VectorInsertLow(SVOp)) {
15109 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
15110 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
15111 return DCI.CombineTo(N, InsV);
15114 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15115 if (isShuffleLow128VectorInsertHigh(SVOp)) {
15116 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
15117 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
15118 return DCI.CombineTo(N, InsV);
15124 /// PerformShuffleCombine - Performs several different shuffle combines.
15125 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
15126 TargetLowering::DAGCombinerInfo &DCI,
15127 const X86Subtarget *Subtarget) {
15128 DebugLoc dl = N->getDebugLoc();
15129 EVT VT = N->getValueType(0);
15131 // Don't create instructions with illegal types after legalize types has run.
15132 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15133 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
15136 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
15137 if (Subtarget->hasFp256() && VT.is256BitVector() &&
15138 N->getOpcode() == ISD::VECTOR_SHUFFLE)
15139 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
15141 // Only handle 128 wide vector from here on.
15142 if (!VT.is128BitVector())
15145 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
15146 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
15147 // consecutive, non-overlapping, and in the right order.
15148 SmallVector<SDValue, 16> Elts;
15149 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
15150 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
15152 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
15155 /// PerformTruncateCombine - Converts truncate operation to
15156 /// a sequence of vector shuffle operations.
15157 /// It is possible when we truncate 256-bit vector to 128-bit vector
15158 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
15159 TargetLowering::DAGCombinerInfo &DCI,
15160 const X86Subtarget *Subtarget) {
15164 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
15165 /// specific shuffle of a load can be folded into a single element load.
15166 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
15167 /// shuffles have been customed lowered so we need to handle those here.
15168 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
15169 TargetLowering::DAGCombinerInfo &DCI) {
15170 if (DCI.isBeforeLegalizeOps())
15173 SDValue InVec = N->getOperand(0);
15174 SDValue EltNo = N->getOperand(1);
15176 if (!isa<ConstantSDNode>(EltNo))
15179 EVT VT = InVec.getValueType();
15181 bool HasShuffleIntoBitcast = false;
15182 if (InVec.getOpcode() == ISD::BITCAST) {
15183 // Don't duplicate a load with other uses.
15184 if (!InVec.hasOneUse())
15186 EVT BCVT = InVec.getOperand(0).getValueType();
15187 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
15189 InVec = InVec.getOperand(0);
15190 HasShuffleIntoBitcast = true;
15193 if (!isTargetShuffle(InVec.getOpcode()))
15196 // Don't duplicate a load with other uses.
15197 if (!InVec.hasOneUse())
15200 SmallVector<int, 16> ShuffleMask;
15202 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
15206 // Select the input vector, guarding against out of range extract vector.
15207 unsigned NumElems = VT.getVectorNumElements();
15208 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
15209 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
15210 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
15211 : InVec.getOperand(1);
15213 // If inputs to shuffle are the same for both ops, then allow 2 uses
15214 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
15216 if (LdNode.getOpcode() == ISD::BITCAST) {
15217 // Don't duplicate a load with other uses.
15218 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
15221 AllowedUses = 1; // only allow 1 load use if we have a bitcast
15222 LdNode = LdNode.getOperand(0);
15225 if (!ISD::isNormalLoad(LdNode.getNode()))
15228 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
15230 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
15233 if (HasShuffleIntoBitcast) {
15234 // If there's a bitcast before the shuffle, check if the load type and
15235 // alignment is valid.
15236 unsigned Align = LN0->getAlignment();
15237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15238 unsigned NewAlign = TLI.getDataLayout()->
15239 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
15241 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
15245 // All checks match so transform back to vector_shuffle so that DAG combiner
15246 // can finish the job
15247 DebugLoc dl = N->getDebugLoc();
15249 // Create shuffle node taking into account the case that its a unary shuffle
15250 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
15251 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
15252 InVec.getOperand(0), Shuffle,
15254 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
15255 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
15259 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
15260 /// generation and convert it from being a bunch of shuffles and extracts
15261 /// to a simple store and scalar loads to extract the elements.
15262 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
15263 TargetLowering::DAGCombinerInfo &DCI) {
15264 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
15265 if (NewOp.getNode())
15268 SDValue InputVector = N->getOperand(0);
15269 // Detect whether we are trying to convert from mmx to i32 and the bitcast
15270 // from mmx to v2i32 has a single usage.
15271 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
15272 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
15273 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
15274 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(),
15275 N->getValueType(0),
15276 InputVector.getNode()->getOperand(0));
15278 // Only operate on vectors of 4 elements, where the alternative shuffling
15279 // gets to be more expensive.
15280 if (InputVector.getValueType() != MVT::v4i32)
15283 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
15284 // single use which is a sign-extend or zero-extend, and all elements are
15286 SmallVector<SDNode *, 4> Uses;
15287 unsigned ExtractedElements = 0;
15288 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
15289 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
15290 if (UI.getUse().getResNo() != InputVector.getResNo())
15293 SDNode *Extract = *UI;
15294 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
15297 if (Extract->getValueType(0) != MVT::i32)
15299 if (!Extract->hasOneUse())
15301 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
15302 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
15304 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
15307 // Record which element was extracted.
15308 ExtractedElements |=
15309 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
15311 Uses.push_back(Extract);
15314 // If not all the elements were used, this may not be worthwhile.
15315 if (ExtractedElements != 15)
15318 // Ok, we've now decided to do the transformation.
15319 DebugLoc dl = InputVector.getDebugLoc();
15321 // Store the value to a temporary stack slot.
15322 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
15323 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
15324 MachinePointerInfo(), false, false, 0);
15326 // Replace each use (extract) with a load of the appropriate element.
15327 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
15328 UE = Uses.end(); UI != UE; ++UI) {
15329 SDNode *Extract = *UI;
15331 // cOMpute the element's address.
15332 SDValue Idx = Extract->getOperand(1);
15334 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
15335 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
15336 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15337 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
15339 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
15340 StackPtr, OffsetVal);
15342 // Load the scalar.
15343 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
15344 ScalarAddr, MachinePointerInfo(),
15345 false, false, false, 0);
15347 // Replace the exact with the load.
15348 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
15351 // The replacement was made in place; don't return anything.
15355 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
15356 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
15357 SDValue RHS, SelectionDAG &DAG,
15358 const X86Subtarget *Subtarget) {
15359 if (!VT.isVector())
15362 switch (VT.getSimpleVT().SimpleTy) {
15367 if (!Subtarget->hasAVX2())
15372 if (!Subtarget->hasSSE2())
15376 // SSE2 has only a small subset of the operations.
15377 bool hasUnsigned = Subtarget->hasSSE41() ||
15378 (Subtarget->hasSSE2() && VT == MVT::v16i8);
15379 bool hasSigned = Subtarget->hasSSE41() ||
15380 (Subtarget->hasSSE2() && VT == MVT::v8i16);
15382 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15384 // Check for x CC y ? x : y.
15385 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15386 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15391 return hasUnsigned ? X86ISD::UMIN : 0;
15394 return hasUnsigned ? X86ISD::UMAX : 0;
15397 return hasSigned ? X86ISD::SMIN : 0;
15400 return hasSigned ? X86ISD::SMAX : 0;
15402 // Check for x CC y ? y : x -- a min/max with reversed arms.
15403 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15404 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15409 return hasUnsigned ? X86ISD::UMAX : 0;
15412 return hasUnsigned ? X86ISD::UMIN : 0;
15415 return hasSigned ? X86ISD::SMAX : 0;
15418 return hasSigned ? X86ISD::SMIN : 0;
15425 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
15427 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
15428 TargetLowering::DAGCombinerInfo &DCI,
15429 const X86Subtarget *Subtarget) {
15430 DebugLoc DL = N->getDebugLoc();
15431 SDValue Cond = N->getOperand(0);
15432 // Get the LHS/RHS of the select.
15433 SDValue LHS = N->getOperand(1);
15434 SDValue RHS = N->getOperand(2);
15435 EVT VT = LHS.getValueType();
15437 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
15438 // instructions match the semantics of the common C idiom x<y?x:y but not
15439 // x<=y?x:y, because of how they handle negative zero (which can be
15440 // ignored in unsafe-math mode).
15441 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
15442 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
15443 (Subtarget->hasSSE2() ||
15444 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
15445 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15447 unsigned Opcode = 0;
15448 // Check for x CC y ? x : y.
15449 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15450 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15454 // Converting this to a min would handle NaNs incorrectly, and swapping
15455 // the operands would cause it to handle comparisons between positive
15456 // and negative zero incorrectly.
15457 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15458 if (!DAG.getTarget().Options.UnsafeFPMath &&
15459 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15461 std::swap(LHS, RHS);
15463 Opcode = X86ISD::FMIN;
15466 // Converting this to a min would handle comparisons between positive
15467 // and negative zero incorrectly.
15468 if (!DAG.getTarget().Options.UnsafeFPMath &&
15469 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15471 Opcode = X86ISD::FMIN;
15474 // Converting this to a min would handle both negative zeros and NaNs
15475 // incorrectly, but we can swap the operands to fix both.
15476 std::swap(LHS, RHS);
15480 Opcode = X86ISD::FMIN;
15484 // Converting this to a max would handle comparisons between positive
15485 // and negative zero incorrectly.
15486 if (!DAG.getTarget().Options.UnsafeFPMath &&
15487 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15489 Opcode = X86ISD::FMAX;
15492 // Converting this to a max would handle NaNs incorrectly, and swapping
15493 // the operands would cause it to handle comparisons between positive
15494 // and negative zero incorrectly.
15495 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15496 if (!DAG.getTarget().Options.UnsafeFPMath &&
15497 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15499 std::swap(LHS, RHS);
15501 Opcode = X86ISD::FMAX;
15504 // Converting this to a max would handle both negative zeros and NaNs
15505 // incorrectly, but we can swap the operands to fix both.
15506 std::swap(LHS, RHS);
15510 Opcode = X86ISD::FMAX;
15513 // Check for x CC y ? y : x -- a min/max with reversed arms.
15514 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15515 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15519 // Converting this to a min would handle comparisons between positive
15520 // and negative zero incorrectly, and swapping the operands would
15521 // cause it to handle NaNs incorrectly.
15522 if (!DAG.getTarget().Options.UnsafeFPMath &&
15523 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
15524 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15526 std::swap(LHS, RHS);
15528 Opcode = X86ISD::FMIN;
15531 // Converting this to a min would handle NaNs incorrectly.
15532 if (!DAG.getTarget().Options.UnsafeFPMath &&
15533 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
15535 Opcode = X86ISD::FMIN;
15538 // Converting this to a min would handle both negative zeros and NaNs
15539 // incorrectly, but we can swap the operands to fix both.
15540 std::swap(LHS, RHS);
15544 Opcode = X86ISD::FMIN;
15548 // Converting this to a max would handle NaNs incorrectly.
15549 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15551 Opcode = X86ISD::FMAX;
15554 // Converting this to a max would handle comparisons between positive
15555 // and negative zero incorrectly, and swapping the operands would
15556 // cause it to handle NaNs incorrectly.
15557 if (!DAG.getTarget().Options.UnsafeFPMath &&
15558 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
15559 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15561 std::swap(LHS, RHS);
15563 Opcode = X86ISD::FMAX;
15566 // Converting this to a max would handle both negative zeros and NaNs
15567 // incorrectly, but we can swap the operands to fix both.
15568 std::swap(LHS, RHS);
15572 Opcode = X86ISD::FMAX;
15578 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
15581 // If this is a select between two integer constants, try to do some
15583 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
15584 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
15585 // Don't do this for crazy integer types.
15586 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
15587 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
15588 // so that TrueC (the true value) is larger than FalseC.
15589 bool NeedsCondInvert = false;
15591 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
15592 // Efficiently invertible.
15593 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15594 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15595 isa<ConstantSDNode>(Cond.getOperand(1))))) {
15596 NeedsCondInvert = true;
15597 std::swap(TrueC, FalseC);
15600 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
15601 if (FalseC->getAPIntValue() == 0 &&
15602 TrueC->getAPIntValue().isPowerOf2()) {
15603 if (NeedsCondInvert) // Invert the condition if needed.
15604 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15605 DAG.getConstant(1, Cond.getValueType()));
15607 // Zero extend the condition if needed.
15608 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
15610 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15611 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15612 DAG.getConstant(ShAmt, MVT::i8));
15615 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
15616 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15617 if (NeedsCondInvert) // Invert the condition if needed.
15618 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15619 DAG.getConstant(1, Cond.getValueType()));
15621 // Zero extend the condition if needed.
15622 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15623 FalseC->getValueType(0), Cond);
15624 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15625 SDValue(FalseC, 0));
15628 // Optimize cases that will turn into an LEA instruction. This requires
15629 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15630 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15631 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15632 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15634 bool isFastMultiplier = false;
15636 switch ((unsigned char)Diff) {
15638 case 1: // result = add base, cond
15639 case 2: // result = lea base( , cond*2)
15640 case 3: // result = lea base(cond, cond*2)
15641 case 4: // result = lea base( , cond*4)
15642 case 5: // result = lea base(cond, cond*4)
15643 case 8: // result = lea base( , cond*8)
15644 case 9: // result = lea base(cond, cond*8)
15645 isFastMultiplier = true;
15650 if (isFastMultiplier) {
15651 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15652 if (NeedsCondInvert) // Invert the condition if needed.
15653 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15654 DAG.getConstant(1, Cond.getValueType()));
15656 // Zero extend the condition if needed.
15657 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15659 // Scale the condition by the difference.
15661 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15662 DAG.getConstant(Diff, Cond.getValueType()));
15664 // Add the base if non-zero.
15665 if (FalseC->getAPIntValue() != 0)
15666 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15667 SDValue(FalseC, 0));
15674 // Canonicalize max and min:
15675 // (x > y) ? x : y -> (x >= y) ? x : y
15676 // (x < y) ? x : y -> (x <= y) ? x : y
15677 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
15678 // the need for an extra compare
15679 // against zero. e.g.
15680 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
15682 // testl %edi, %edi
15684 // cmovgl %edi, %eax
15688 // cmovsl %eax, %edi
15689 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
15690 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15691 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15692 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15697 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
15698 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
15699 Cond.getOperand(0), Cond.getOperand(1), NewCC);
15700 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
15705 // Match VSELECTs into subs with unsigned saturation.
15706 if (!DCI.isBeforeLegalize() &&
15707 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
15708 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
15709 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
15710 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
15711 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15713 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
15714 // left side invert the predicate to simplify logic below.
15716 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
15718 CC = ISD::getSetCCInverse(CC, true);
15719 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
15723 if (Other.getNode() && Other->getNumOperands() == 2 &&
15724 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
15725 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
15726 SDValue CondRHS = Cond->getOperand(1);
15728 // Look for a general sub with unsigned saturation first.
15729 // x >= y ? x-y : 0 --> subus x, y
15730 // x > y ? x-y : 0 --> subus x, y
15731 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
15732 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
15733 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15735 // If the RHS is a constant we have to reverse the const canonicalization.
15736 // x > C-1 ? x+-C : 0 --> subus x, C
15737 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
15738 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
15739 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15740 if (CondRHS.getConstantOperandVal(0) == -A-1)
15741 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
15742 DAG.getConstant(-A, VT));
15745 // Another special case: If C was a sign bit, the sub has been
15746 // canonicalized into a xor.
15747 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
15748 // it's safe to decanonicalize the xor?
15749 // x s< 0 ? x^C : 0 --> subus x, C
15750 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
15751 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
15752 isSplatVector(OpRHS.getNode())) {
15753 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15755 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15760 // Try to match a min/max vector operation.
15761 if (!DCI.isBeforeLegalize() &&
15762 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
15763 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
15764 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
15766 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
15767 if (!DCI.isBeforeLegalize() && N->getOpcode() == ISD::VSELECT &&
15768 Cond.getOpcode() == ISD::SETCC) {
15770 assert(Cond.getValueType().isVector() &&
15771 "vector select expects a vector selector!");
15773 EVT IntVT = Cond.getValueType();
15774 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
15775 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
15777 if (!TValIsAllOnes && !FValIsAllZeros) {
15778 // Try invert the condition if true value is not all 1s and false value
15780 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
15781 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
15783 if (TValIsAllZeros || FValIsAllOnes) {
15784 SDValue CC = Cond.getOperand(2);
15785 ISD::CondCode NewCC =
15786 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
15787 Cond.getOperand(0).getValueType().isInteger());
15788 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
15789 std::swap(LHS, RHS);
15790 TValIsAllOnes = FValIsAllOnes;
15791 FValIsAllZeros = TValIsAllZeros;
15795 if (TValIsAllOnes || FValIsAllZeros) {
15798 if (TValIsAllOnes && FValIsAllZeros)
15800 else if (TValIsAllOnes)
15801 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
15802 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
15803 else if (FValIsAllZeros)
15804 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
15805 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
15807 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
15811 // If we know that this node is legal then we know that it is going to be
15812 // matched by one of the SSE/AVX BLEND instructions. These instructions only
15813 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
15814 // to simplify previous instructions.
15815 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15816 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
15817 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
15818 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
15820 // Don't optimize vector selects that map to mask-registers.
15824 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
15825 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
15827 APInt KnownZero, KnownOne;
15828 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
15829 DCI.isBeforeLegalizeOps());
15830 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
15831 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
15832 DCI.CommitTargetLoweringOpt(TLO);
15838 // Check whether a boolean test is testing a boolean value generated by
15839 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
15842 // Simplify the following patterns:
15843 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
15844 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
15845 // to (Op EFLAGS Cond)
15847 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
15848 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
15849 // to (Op EFLAGS !Cond)
15851 // where Op could be BRCOND or CMOV.
15853 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
15854 // Quit if not CMP and SUB with its value result used.
15855 if (Cmp.getOpcode() != X86ISD::CMP &&
15856 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
15859 // Quit if not used as a boolean value.
15860 if (CC != X86::COND_E && CC != X86::COND_NE)
15863 // Check CMP operands. One of them should be 0 or 1 and the other should be
15864 // an SetCC or extended from it.
15865 SDValue Op1 = Cmp.getOperand(0);
15866 SDValue Op2 = Cmp.getOperand(1);
15869 const ConstantSDNode* C = 0;
15870 bool needOppositeCond = (CC == X86::COND_E);
15871 bool checkAgainstTrue = false; // Is it a comparison against 1?
15873 if ((C = dyn_cast<ConstantSDNode>(Op1)))
15875 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
15877 else // Quit if all operands are not constants.
15880 if (C->getZExtValue() == 1) {
15881 needOppositeCond = !needOppositeCond;
15882 checkAgainstTrue = true;
15883 } else if (C->getZExtValue() != 0)
15884 // Quit if the constant is neither 0 or 1.
15887 bool truncatedToBoolWithAnd = false;
15888 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
15889 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
15890 SetCC.getOpcode() == ISD::TRUNCATE ||
15891 SetCC.getOpcode() == ISD::AND) {
15892 if (SetCC.getOpcode() == ISD::AND) {
15894 ConstantSDNode *CS;
15895 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
15896 CS->getZExtValue() == 1)
15898 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
15899 CS->getZExtValue() == 1)
15903 SetCC = SetCC.getOperand(OpIdx);
15904 truncatedToBoolWithAnd = true;
15906 SetCC = SetCC.getOperand(0);
15909 switch (SetCC.getOpcode()) {
15910 case X86ISD::SETCC_CARRY:
15911 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
15912 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
15913 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
15914 // truncated to i1 using 'and'.
15915 if (checkAgainstTrue && !truncatedToBoolWithAnd)
15917 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
15918 "Invalid use of SETCC_CARRY!");
15920 case X86ISD::SETCC:
15921 // Set the condition code or opposite one if necessary.
15922 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
15923 if (needOppositeCond)
15924 CC = X86::GetOppositeBranchCondition(CC);
15925 return SetCC.getOperand(1);
15926 case X86ISD::CMOV: {
15927 // Check whether false/true value has canonical one, i.e. 0 or 1.
15928 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
15929 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
15930 // Quit if true value is not a constant.
15933 // Quit if false value is not a constant.
15935 SDValue Op = SetCC.getOperand(0);
15936 // Skip 'zext' or 'trunc' node.
15937 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
15938 Op.getOpcode() == ISD::TRUNCATE)
15939 Op = Op.getOperand(0);
15940 // A special case for rdrand/rdseed, where 0 is set if false cond is
15942 if ((Op.getOpcode() != X86ISD::RDRAND &&
15943 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
15946 // Quit if false value is not the constant 0 or 1.
15947 bool FValIsFalse = true;
15948 if (FVal && FVal->getZExtValue() != 0) {
15949 if (FVal->getZExtValue() != 1)
15951 // If FVal is 1, opposite cond is needed.
15952 needOppositeCond = !needOppositeCond;
15953 FValIsFalse = false;
15955 // Quit if TVal is not the constant opposite of FVal.
15956 if (FValIsFalse && TVal->getZExtValue() != 1)
15958 if (!FValIsFalse && TVal->getZExtValue() != 0)
15960 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
15961 if (needOppositeCond)
15962 CC = X86::GetOppositeBranchCondition(CC);
15963 return SetCC.getOperand(3);
15970 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
15971 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
15972 TargetLowering::DAGCombinerInfo &DCI,
15973 const X86Subtarget *Subtarget) {
15974 DebugLoc DL = N->getDebugLoc();
15976 // If the flag operand isn't dead, don't touch this CMOV.
15977 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
15980 SDValue FalseOp = N->getOperand(0);
15981 SDValue TrueOp = N->getOperand(1);
15982 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
15983 SDValue Cond = N->getOperand(3);
15985 if (CC == X86::COND_E || CC == X86::COND_NE) {
15986 switch (Cond.getOpcode()) {
15990 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
15991 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
15992 return (CC == X86::COND_E) ? FalseOp : TrueOp;
15998 Flags = checkBoolTestSetCCCombine(Cond, CC);
15999 if (Flags.getNode() &&
16000 // Extra check as FCMOV only supports a subset of X86 cond.
16001 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
16002 SDValue Ops[] = { FalseOp, TrueOp,
16003 DAG.getConstant(CC, MVT::i8), Flags };
16004 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
16005 Ops, array_lengthof(Ops));
16008 // If this is a select between two integer constants, try to do some
16009 // optimizations. Note that the operands are ordered the opposite of SELECT
16011 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
16012 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
16013 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
16014 // larger than FalseC (the false value).
16015 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
16016 CC = X86::GetOppositeBranchCondition(CC);
16017 std::swap(TrueC, FalseC);
16018 std::swap(TrueOp, FalseOp);
16021 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
16022 // This is efficient for any integer data type (including i8/i16) and
16024 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
16025 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16026 DAG.getConstant(CC, MVT::i8), Cond);
16028 // Zero extend the condition if needed.
16029 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
16031 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16032 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
16033 DAG.getConstant(ShAmt, MVT::i8));
16034 if (N->getNumValues() == 2) // Dead flag value?
16035 return DCI.CombineTo(N, Cond, SDValue());
16039 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
16040 // for any integer data type, including i8/i16.
16041 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16042 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16043 DAG.getConstant(CC, MVT::i8), Cond);
16045 // Zero extend the condition if needed.
16046 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16047 FalseC->getValueType(0), Cond);
16048 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16049 SDValue(FalseC, 0));
16051 if (N->getNumValues() == 2) // Dead flag value?
16052 return DCI.CombineTo(N, Cond, SDValue());
16056 // Optimize cases that will turn into an LEA instruction. This requires
16057 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16058 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16059 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16060 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16062 bool isFastMultiplier = false;
16064 switch ((unsigned char)Diff) {
16066 case 1: // result = add base, cond
16067 case 2: // result = lea base( , cond*2)
16068 case 3: // result = lea base(cond, cond*2)
16069 case 4: // result = lea base( , cond*4)
16070 case 5: // result = lea base(cond, cond*4)
16071 case 8: // result = lea base( , cond*8)
16072 case 9: // result = lea base(cond, cond*8)
16073 isFastMultiplier = true;
16078 if (isFastMultiplier) {
16079 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16080 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16081 DAG.getConstant(CC, MVT::i8), Cond);
16082 // Zero extend the condition if needed.
16083 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16085 // Scale the condition by the difference.
16087 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16088 DAG.getConstant(Diff, Cond.getValueType()));
16090 // Add the base if non-zero.
16091 if (FalseC->getAPIntValue() != 0)
16092 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16093 SDValue(FalseC, 0));
16094 if (N->getNumValues() == 2) // Dead flag value?
16095 return DCI.CombineTo(N, Cond, SDValue());
16102 // Handle these cases:
16103 // (select (x != c), e, c) -> select (x != c), e, x),
16104 // (select (x == c), c, e) -> select (x == c), x, e)
16105 // where the c is an integer constant, and the "select" is the combination
16106 // of CMOV and CMP.
16108 // The rationale for this change is that the conditional-move from a constant
16109 // needs two instructions, however, conditional-move from a register needs
16110 // only one instruction.
16112 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
16113 // some instruction-combining opportunities. This opt needs to be
16114 // postponed as late as possible.
16116 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
16117 // the DCI.xxxx conditions are provided to postpone the optimization as
16118 // late as possible.
16120 ConstantSDNode *CmpAgainst = 0;
16121 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
16122 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
16123 !isa<ConstantSDNode>(Cond.getOperand(0))) {
16125 if (CC == X86::COND_NE &&
16126 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
16127 CC = X86::GetOppositeBranchCondition(CC);
16128 std::swap(TrueOp, FalseOp);
16131 if (CC == X86::COND_E &&
16132 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
16133 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
16134 DAG.getConstant(CC, MVT::i8), Cond };
16135 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
16136 array_lengthof(Ops));
16144 /// PerformMulCombine - Optimize a single multiply with constant into two
16145 /// in order to implement it with two cheaper instructions, e.g.
16146 /// LEA + SHL, LEA + LEA.
16147 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
16148 TargetLowering::DAGCombinerInfo &DCI) {
16149 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16152 EVT VT = N->getValueType(0);
16153 if (VT != MVT::i64)
16156 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
16159 uint64_t MulAmt = C->getZExtValue();
16160 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
16163 uint64_t MulAmt1 = 0;
16164 uint64_t MulAmt2 = 0;
16165 if ((MulAmt % 9) == 0) {
16167 MulAmt2 = MulAmt / 9;
16168 } else if ((MulAmt % 5) == 0) {
16170 MulAmt2 = MulAmt / 5;
16171 } else if ((MulAmt % 3) == 0) {
16173 MulAmt2 = MulAmt / 3;
16176 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
16177 DebugLoc DL = N->getDebugLoc();
16179 if (isPowerOf2_64(MulAmt2) &&
16180 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
16181 // If second multiplifer is pow2, issue it first. We want the multiply by
16182 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
16184 std::swap(MulAmt1, MulAmt2);
16187 if (isPowerOf2_64(MulAmt1))
16188 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
16189 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
16191 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
16192 DAG.getConstant(MulAmt1, VT));
16194 if (isPowerOf2_64(MulAmt2))
16195 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
16196 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
16198 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
16199 DAG.getConstant(MulAmt2, VT));
16201 // Do not add new nodes to DAG combiner worklist.
16202 DCI.CombineTo(N, NewMul, false);
16207 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
16208 SDValue N0 = N->getOperand(0);
16209 SDValue N1 = N->getOperand(1);
16210 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
16211 EVT VT = N0.getValueType();
16213 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
16214 // since the result of setcc_c is all zero's or all ones.
16215 if (VT.isInteger() && !VT.isVector() &&
16216 N1C && N0.getOpcode() == ISD::AND &&
16217 N0.getOperand(1).getOpcode() == ISD::Constant) {
16218 SDValue N00 = N0.getOperand(0);
16219 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
16220 ((N00.getOpcode() == ISD::ANY_EXTEND ||
16221 N00.getOpcode() == ISD::ZERO_EXTEND) &&
16222 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
16223 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
16224 APInt ShAmt = N1C->getAPIntValue();
16225 Mask = Mask.shl(ShAmt);
16227 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
16228 N00, DAG.getConstant(Mask, VT));
16232 // Hardware support for vector shifts is sparse which makes us scalarize the
16233 // vector operations in many cases. Also, on sandybridge ADD is faster than
16235 // (shl V, 1) -> add V,V
16236 if (isSplatVector(N1.getNode())) {
16237 assert(N0.getValueType().isVector() && "Invalid vector shift type");
16238 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
16239 // We shift all of the values by one. In many cases we do not have
16240 // hardware support for this operation. This is better expressed as an ADD
16242 if (N1C && (1 == N1C->getZExtValue())) {
16243 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
16250 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
16252 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
16253 TargetLowering::DAGCombinerInfo &DCI,
16254 const X86Subtarget *Subtarget) {
16255 if (N->getOpcode() == ISD::SHL) {
16256 SDValue V = PerformSHLCombine(N, DAG);
16257 if (V.getNode()) return V;
16263 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
16264 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
16265 // and friends. Likewise for OR -> CMPNEQSS.
16266 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
16267 TargetLowering::DAGCombinerInfo &DCI,
16268 const X86Subtarget *Subtarget) {
16271 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
16272 // we're requiring SSE2 for both.
16273 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
16274 SDValue N0 = N->getOperand(0);
16275 SDValue N1 = N->getOperand(1);
16276 SDValue CMP0 = N0->getOperand(1);
16277 SDValue CMP1 = N1->getOperand(1);
16278 DebugLoc DL = N->getDebugLoc();
16280 // The SETCCs should both refer to the same CMP.
16281 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
16284 SDValue CMP00 = CMP0->getOperand(0);
16285 SDValue CMP01 = CMP0->getOperand(1);
16286 EVT VT = CMP00.getValueType();
16288 if (VT == MVT::f32 || VT == MVT::f64) {
16289 bool ExpectingFlags = false;
16290 // Check for any users that want flags:
16291 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
16292 !ExpectingFlags && UI != UE; ++UI)
16293 switch (UI->getOpcode()) {
16298 ExpectingFlags = true;
16300 case ISD::CopyToReg:
16301 case ISD::SIGN_EXTEND:
16302 case ISD::ZERO_EXTEND:
16303 case ISD::ANY_EXTEND:
16307 if (!ExpectingFlags) {
16308 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
16309 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
16311 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
16312 X86::CondCode tmp = cc0;
16317 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
16318 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
16319 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
16320 X86ISD::NodeType NTOperator = is64BitFP ?
16321 X86ISD::FSETCCsd : X86ISD::FSETCCss;
16322 // FIXME: need symbolic constants for these magic numbers.
16323 // See X86ATTInstPrinter.cpp:printSSECC().
16324 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
16325 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
16326 DAG.getConstant(x86cc, MVT::i8));
16327 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
16329 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
16330 DAG.getConstant(1, MVT::i32));
16331 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
16332 return OneBitOfTruth;
16340 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
16341 /// so it can be folded inside ANDNP.
16342 static bool CanFoldXORWithAllOnes(const SDNode *N) {
16343 EVT VT = N->getValueType(0);
16345 // Match direct AllOnes for 128 and 256-bit vectors
16346 if (ISD::isBuildVectorAllOnes(N))
16349 // Look through a bit convert.
16350 if (N->getOpcode() == ISD::BITCAST)
16351 N = N->getOperand(0).getNode();
16353 // Sometimes the operand may come from a insert_subvector building a 256-bit
16355 if (VT.is256BitVector() &&
16356 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
16357 SDValue V1 = N->getOperand(0);
16358 SDValue V2 = N->getOperand(1);
16360 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
16361 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
16362 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
16363 ISD::isBuildVectorAllOnes(V2.getNode()))
16370 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
16371 // register. In most cases we actually compare or select YMM-sized registers
16372 // and mixing the two types creates horrible code. This method optimizes
16373 // some of the transition sequences.
16374 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
16375 TargetLowering::DAGCombinerInfo &DCI,
16376 const X86Subtarget *Subtarget) {
16377 EVT VT = N->getValueType(0);
16378 if (!VT.is256BitVector())
16381 assert((N->getOpcode() == ISD::ANY_EXTEND ||
16382 N->getOpcode() == ISD::ZERO_EXTEND ||
16383 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
16385 SDValue Narrow = N->getOperand(0);
16386 EVT NarrowVT = Narrow->getValueType(0);
16387 if (!NarrowVT.is128BitVector())
16390 if (Narrow->getOpcode() != ISD::XOR &&
16391 Narrow->getOpcode() != ISD::AND &&
16392 Narrow->getOpcode() != ISD::OR)
16395 SDValue N0 = Narrow->getOperand(0);
16396 SDValue N1 = Narrow->getOperand(1);
16397 DebugLoc DL = Narrow->getDebugLoc();
16399 // The Left side has to be a trunc.
16400 if (N0.getOpcode() != ISD::TRUNCATE)
16403 // The type of the truncated inputs.
16404 EVT WideVT = N0->getOperand(0)->getValueType(0);
16408 // The right side has to be a 'trunc' or a constant vector.
16409 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
16410 bool RHSConst = (isSplatVector(N1.getNode()) &&
16411 isa<ConstantSDNode>(N1->getOperand(0)));
16412 if (!RHSTrunc && !RHSConst)
16415 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16417 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
16420 // Set N0 and N1 to hold the inputs to the new wide operation.
16421 N0 = N0->getOperand(0);
16423 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
16424 N1->getOperand(0));
16425 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
16426 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
16427 } else if (RHSTrunc) {
16428 N1 = N1->getOperand(0);
16431 // Generate the wide operation.
16432 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
16433 unsigned Opcode = N->getOpcode();
16435 case ISD::ANY_EXTEND:
16437 case ISD::ZERO_EXTEND: {
16438 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
16439 APInt Mask = APInt::getAllOnesValue(InBits);
16440 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
16441 return DAG.getNode(ISD::AND, DL, VT,
16442 Op, DAG.getConstant(Mask, VT));
16444 case ISD::SIGN_EXTEND:
16445 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
16446 Op, DAG.getValueType(NarrowVT));
16448 llvm_unreachable("Unexpected opcode");
16452 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
16453 TargetLowering::DAGCombinerInfo &DCI,
16454 const X86Subtarget *Subtarget) {
16455 EVT VT = N->getValueType(0);
16456 if (DCI.isBeforeLegalizeOps())
16459 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16463 // Create BLSI, and BLSR instructions
16464 // BLSI is X & (-X)
16465 // BLSR is X & (X-1)
16466 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
16467 SDValue N0 = N->getOperand(0);
16468 SDValue N1 = N->getOperand(1);
16469 DebugLoc DL = N->getDebugLoc();
16471 // Check LHS for neg
16472 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16473 isZero(N0.getOperand(0)))
16474 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
16476 // Check RHS for neg
16477 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16478 isZero(N1.getOperand(0)))
16479 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
16481 // Check LHS for X-1
16482 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16483 isAllOnes(N0.getOperand(1)))
16484 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
16486 // Check RHS for X-1
16487 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16488 isAllOnes(N1.getOperand(1)))
16489 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
16494 // Want to form ANDNP nodes:
16495 // 1) In the hopes of then easily combining them with OR and AND nodes
16496 // to form PBLEND/PSIGN.
16497 // 2) To match ANDN packed intrinsics
16498 if (VT != MVT::v2i64 && VT != MVT::v4i64)
16501 SDValue N0 = N->getOperand(0);
16502 SDValue N1 = N->getOperand(1);
16503 DebugLoc DL = N->getDebugLoc();
16505 // Check LHS for vnot
16506 if (N0.getOpcode() == ISD::XOR &&
16507 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
16508 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
16509 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
16511 // Check RHS for vnot
16512 if (N1.getOpcode() == ISD::XOR &&
16513 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
16514 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
16515 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
16520 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
16521 TargetLowering::DAGCombinerInfo &DCI,
16522 const X86Subtarget *Subtarget) {
16523 EVT VT = N->getValueType(0);
16524 if (DCI.isBeforeLegalizeOps())
16527 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16531 SDValue N0 = N->getOperand(0);
16532 SDValue N1 = N->getOperand(1);
16534 // look for psign/blend
16535 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
16536 if (!Subtarget->hasSSSE3() ||
16537 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
16540 // Canonicalize pandn to RHS
16541 if (N0.getOpcode() == X86ISD::ANDNP)
16543 // or (and (m, y), (pandn m, x))
16544 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16545 SDValue Mask = N1.getOperand(0);
16546 SDValue X = N1.getOperand(1);
16548 if (N0.getOperand(0) == Mask)
16549 Y = N0.getOperand(1);
16550 if (N0.getOperand(1) == Mask)
16551 Y = N0.getOperand(0);
16553 // Check to see if the mask appeared in both the AND and ANDNP and
16557 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
16558 // Look through mask bitcast.
16559 if (Mask.getOpcode() == ISD::BITCAST)
16560 Mask = Mask.getOperand(0);
16561 if (X.getOpcode() == ISD::BITCAST)
16562 X = X.getOperand(0);
16563 if (Y.getOpcode() == ISD::BITCAST)
16564 Y = Y.getOperand(0);
16566 EVT MaskVT = Mask.getValueType();
16568 // Validate that the Mask operand is a vector sra node.
16569 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
16570 // there is no psrai.b
16571 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
16572 unsigned SraAmt = ~0;
16573 if (Mask.getOpcode() == ISD::SRA) {
16574 SDValue Amt = Mask.getOperand(1);
16575 if (isSplatVector(Amt.getNode())) {
16576 SDValue SclrAmt = Amt->getOperand(0);
16577 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
16578 SraAmt = C->getZExtValue();
16580 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
16581 SDValue SraC = Mask.getOperand(1);
16582 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
16584 if ((SraAmt + 1) != EltBits)
16587 DebugLoc DL = N->getDebugLoc();
16589 // Now we know we at least have a plendvb with the mask val. See if
16590 // we can form a psignb/w/d.
16591 // psign = x.type == y.type == mask.type && y = sub(0, x);
16592 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16593 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
16594 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
16595 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
16596 "Unsupported VT for PSIGN");
16597 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
16598 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16600 // PBLENDVB only available on SSE 4.1
16601 if (!Subtarget->hasSSE41())
16604 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
16606 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
16607 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
16608 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
16609 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
16610 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16614 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
16617 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
16618 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16620 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16622 if (!N0.hasOneUse() || !N1.hasOneUse())
16625 SDValue ShAmt0 = N0.getOperand(1);
16626 if (ShAmt0.getValueType() != MVT::i8)
16628 SDValue ShAmt1 = N1.getOperand(1);
16629 if (ShAmt1.getValueType() != MVT::i8)
16631 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
16632 ShAmt0 = ShAmt0.getOperand(0);
16633 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
16634 ShAmt1 = ShAmt1.getOperand(0);
16636 DebugLoc DL = N->getDebugLoc();
16637 unsigned Opc = X86ISD::SHLD;
16638 SDValue Op0 = N0.getOperand(0);
16639 SDValue Op1 = N1.getOperand(0);
16640 if (ShAmt0.getOpcode() == ISD::SUB) {
16641 Opc = X86ISD::SHRD;
16642 std::swap(Op0, Op1);
16643 std::swap(ShAmt0, ShAmt1);
16646 unsigned Bits = VT.getSizeInBits();
16647 if (ShAmt1.getOpcode() == ISD::SUB) {
16648 SDValue Sum = ShAmt1.getOperand(0);
16649 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
16650 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
16651 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
16652 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
16653 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
16654 return DAG.getNode(Opc, DL, VT,
16656 DAG.getNode(ISD::TRUNCATE, DL,
16659 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
16660 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
16662 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
16663 return DAG.getNode(Opc, DL, VT,
16664 N0.getOperand(0), N1.getOperand(0),
16665 DAG.getNode(ISD::TRUNCATE, DL,
16672 // Generate NEG and CMOV for integer abs.
16673 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
16674 EVT VT = N->getValueType(0);
16676 // Since X86 does not have CMOV for 8-bit integer, we don't convert
16677 // 8-bit integer abs to NEG and CMOV.
16678 if (VT.isInteger() && VT.getSizeInBits() == 8)
16681 SDValue N0 = N->getOperand(0);
16682 SDValue N1 = N->getOperand(1);
16683 DebugLoc DL = N->getDebugLoc();
16685 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
16686 // and change it to SUB and CMOV.
16687 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
16688 N0.getOpcode() == ISD::ADD &&
16689 N0.getOperand(1) == N1 &&
16690 N1.getOpcode() == ISD::SRA &&
16691 N1.getOperand(0) == N0.getOperand(0))
16692 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
16693 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
16694 // Generate SUB & CMOV.
16695 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
16696 DAG.getConstant(0, VT), N0.getOperand(0));
16698 SDValue Ops[] = { N0.getOperand(0), Neg,
16699 DAG.getConstant(X86::COND_GE, MVT::i8),
16700 SDValue(Neg.getNode(), 1) };
16701 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
16702 Ops, array_lengthof(Ops));
16707 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
16708 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
16709 TargetLowering::DAGCombinerInfo &DCI,
16710 const X86Subtarget *Subtarget) {
16711 EVT VT = N->getValueType(0);
16712 if (DCI.isBeforeLegalizeOps())
16715 if (Subtarget->hasCMov()) {
16716 SDValue RV = performIntegerAbsCombine(N, DAG);
16721 // Try forming BMI if it is available.
16722 if (!Subtarget->hasBMI())
16725 if (VT != MVT::i32 && VT != MVT::i64)
16728 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
16730 // Create BLSMSK instructions by finding X ^ (X-1)
16731 SDValue N0 = N->getOperand(0);
16732 SDValue N1 = N->getOperand(1);
16733 DebugLoc DL = N->getDebugLoc();
16735 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16736 isAllOnes(N0.getOperand(1)))
16737 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
16739 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16740 isAllOnes(N1.getOperand(1)))
16741 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
16746 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
16747 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
16748 TargetLowering::DAGCombinerInfo &DCI,
16749 const X86Subtarget *Subtarget) {
16750 LoadSDNode *Ld = cast<LoadSDNode>(N);
16751 EVT RegVT = Ld->getValueType(0);
16752 EVT MemVT = Ld->getMemoryVT();
16753 DebugLoc dl = Ld->getDebugLoc();
16754 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16755 unsigned RegSz = RegVT.getSizeInBits();
16757 // On Sandybridge unaligned 256bit loads are inefficient.
16758 ISD::LoadExtType Ext = Ld->getExtensionType();
16759 unsigned Alignment = Ld->getAlignment();
16760 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
16761 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
16762 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
16763 unsigned NumElems = RegVT.getVectorNumElements();
16767 SDValue Ptr = Ld->getBasePtr();
16768 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
16770 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16772 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
16773 Ld->getPointerInfo(), Ld->isVolatile(),
16774 Ld->isNonTemporal(), Ld->isInvariant(),
16776 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16777 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
16778 Ld->getPointerInfo(), Ld->isVolatile(),
16779 Ld->isNonTemporal(), Ld->isInvariant(),
16780 std::min(16U, Alignment));
16781 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16783 Load2.getValue(1));
16785 SDValue NewVec = DAG.getUNDEF(RegVT);
16786 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
16787 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
16788 return DCI.CombineTo(N, NewVec, TF, true);
16791 // If this is a vector EXT Load then attempt to optimize it using a
16792 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
16793 // expansion is still better than scalar code.
16794 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
16795 // emit a shuffle and a arithmetic shift.
16796 // TODO: It is possible to support ZExt by zeroing the undef values
16797 // during the shuffle phase or after the shuffle.
16798 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
16799 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
16800 assert(MemVT != RegVT && "Cannot extend to the same type");
16801 assert(MemVT.isVector() && "Must load a vector from memory");
16803 unsigned NumElems = RegVT.getVectorNumElements();
16804 unsigned MemSz = MemVT.getSizeInBits();
16805 assert(RegSz > MemSz && "Register size must be greater than the mem size");
16807 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
16810 // All sizes must be a power of two.
16811 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
16814 // Attempt to load the original value using scalar loads.
16815 // Find the largest scalar type that divides the total loaded size.
16816 MVT SclrLoadTy = MVT::i8;
16817 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16818 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16819 MVT Tp = (MVT::SimpleValueType)tp;
16820 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16825 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16826 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16828 SclrLoadTy = MVT::f64;
16830 // Calculate the number of scalar loads that we need to perform
16831 // in order to load our vector from memory.
16832 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16833 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
16836 unsigned loadRegZize = RegSz;
16837 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16840 // Represent our vector as a sequence of elements which are the
16841 // largest scalar that we can load.
16842 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
16843 loadRegZize/SclrLoadTy.getSizeInBits());
16845 // Represent the data using the same element type that is stored in
16846 // memory. In practice, we ''widen'' MemVT.
16848 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16849 loadRegZize/MemVT.getScalarType().getSizeInBits());
16851 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16852 "Invalid vector type");
16854 // We can't shuffle using an illegal type.
16855 if (!TLI.isTypeLegal(WideVecVT))
16858 SmallVector<SDValue, 8> Chains;
16859 SDValue Ptr = Ld->getBasePtr();
16860 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
16861 TLI.getPointerTy());
16862 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16864 for (unsigned i = 0; i < NumLoads; ++i) {
16865 // Perform a single load.
16866 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
16867 Ptr, Ld->getPointerInfo(),
16868 Ld->isVolatile(), Ld->isNonTemporal(),
16869 Ld->isInvariant(), Ld->getAlignment());
16870 Chains.push_back(ScalarLoad.getValue(1));
16871 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16872 // another round of DAGCombining.
16874 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16876 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16877 ScalarLoad, DAG.getIntPtrConstant(i));
16879 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16882 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16885 // Bitcast the loaded value to a vector of the original element type, in
16886 // the size of the target vector type.
16887 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16888 unsigned SizeRatio = RegSz/MemSz;
16890 if (Ext == ISD::SEXTLOAD) {
16891 // If we have SSE4.1 we can directly emit a VSEXT node.
16892 if (Subtarget->hasSSE41()) {
16893 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16894 return DCI.CombineTo(N, Sext, TF, true);
16897 // Otherwise we'll shuffle the small elements in the high bits of the
16898 // larger type and perform an arithmetic shift. If the shift is not legal
16899 // it's better to scalarize.
16900 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
16903 // Redistribute the loaded elements into the different locations.
16904 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16905 for (unsigned i = 0; i != NumElems; ++i)
16906 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
16908 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16909 DAG.getUNDEF(WideVecVT),
16912 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16914 // Build the arithmetic shift.
16915 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16916 MemVT.getVectorElementType().getSizeInBits();
16917 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
16918 DAG.getConstant(Amt, RegVT));
16920 return DCI.CombineTo(N, Shuff, TF, true);
16923 // Redistribute the loaded elements into the different locations.
16924 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16925 for (unsigned i = 0; i != NumElems; ++i)
16926 ShuffleVec[i*SizeRatio] = i;
16928 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16929 DAG.getUNDEF(WideVecVT),
16932 // Bitcast to the requested type.
16933 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16934 // Replace the original load with the new sequence
16935 // and return the new chain.
16936 return DCI.CombineTo(N, Shuff, TF, true);
16942 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
16943 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
16944 const X86Subtarget *Subtarget) {
16945 StoreSDNode *St = cast<StoreSDNode>(N);
16946 EVT VT = St->getValue().getValueType();
16947 EVT StVT = St->getMemoryVT();
16948 DebugLoc dl = St->getDebugLoc();
16949 SDValue StoredVal = St->getOperand(1);
16950 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16952 // If we are saving a concatenation of two XMM registers, perform two stores.
16953 // On Sandy Bridge, 256-bit memory operations are executed by two
16954 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
16955 // memory operation.
16956 unsigned Alignment = St->getAlignment();
16957 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
16958 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
16959 StVT == VT && !IsAligned) {
16960 unsigned NumElems = VT.getVectorNumElements();
16964 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
16965 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
16967 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
16968 SDValue Ptr0 = St->getBasePtr();
16969 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
16971 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
16972 St->getPointerInfo(), St->isVolatile(),
16973 St->isNonTemporal(), Alignment);
16974 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
16975 St->getPointerInfo(), St->isVolatile(),
16976 St->isNonTemporal(),
16977 std::min(16U, Alignment));
16978 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16981 // Optimize trunc store (of multiple scalars) to shuffle and store.
16982 // First, pack all of the elements in one place. Next, store to memory
16983 // in fewer chunks.
16984 if (St->isTruncatingStore() && VT.isVector()) {
16985 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16986 unsigned NumElems = VT.getVectorNumElements();
16987 assert(StVT != VT && "Cannot truncate to the same type");
16988 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
16989 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
16991 // From, To sizes and ElemCount must be pow of two
16992 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
16993 // We are going to use the original vector elt for storing.
16994 // Accumulated smaller vector elements must be a multiple of the store size.
16995 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
16997 unsigned SizeRatio = FromSz / ToSz;
16999 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
17001 // Create a type on which we perform the shuffle
17002 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
17003 StVT.getScalarType(), NumElems*SizeRatio);
17005 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
17007 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
17008 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17009 for (unsigned i = 0; i != NumElems; ++i)
17010 ShuffleVec[i] = i * SizeRatio;
17012 // Can't shuffle using an illegal type.
17013 if (!TLI.isTypeLegal(WideVecVT))
17016 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
17017 DAG.getUNDEF(WideVecVT),
17019 // At this point all of the data is stored at the bottom of the
17020 // register. We now need to save it to mem.
17022 // Find the largest store unit
17023 MVT StoreType = MVT::i8;
17024 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17025 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17026 MVT Tp = (MVT::SimpleValueType)tp;
17027 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
17031 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17032 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
17033 (64 <= NumElems * ToSz))
17034 StoreType = MVT::f64;
17036 // Bitcast the original vector into a vector of store-size units
17037 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
17038 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
17039 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
17040 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
17041 SmallVector<SDValue, 8> Chains;
17042 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
17043 TLI.getPointerTy());
17044 SDValue Ptr = St->getBasePtr();
17046 // Perform one or more big stores into memory.
17047 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
17048 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
17049 StoreType, ShuffWide,
17050 DAG.getIntPtrConstant(i));
17051 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
17052 St->getPointerInfo(), St->isVolatile(),
17053 St->isNonTemporal(), St->getAlignment());
17054 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17055 Chains.push_back(Ch);
17058 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17062 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
17063 // the FP state in cases where an emms may be missing.
17064 // A preferable solution to the general problem is to figure out the right
17065 // places to insert EMMS. This qualifies as a quick hack.
17067 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
17068 if (VT.getSizeInBits() != 64)
17071 const Function *F = DAG.getMachineFunction().getFunction();
17072 bool NoImplicitFloatOps = F->getAttributes().
17073 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
17074 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
17075 && Subtarget->hasSSE2();
17076 if ((VT.isVector() ||
17077 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
17078 isa<LoadSDNode>(St->getValue()) &&
17079 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
17080 St->getChain().hasOneUse() && !St->isVolatile()) {
17081 SDNode* LdVal = St->getValue().getNode();
17082 LoadSDNode *Ld = 0;
17083 int TokenFactorIndex = -1;
17084 SmallVector<SDValue, 8> Ops;
17085 SDNode* ChainVal = St->getChain().getNode();
17086 // Must be a store of a load. We currently handle two cases: the load
17087 // is a direct child, and it's under an intervening TokenFactor. It is
17088 // possible to dig deeper under nested TokenFactors.
17089 if (ChainVal == LdVal)
17090 Ld = cast<LoadSDNode>(St->getChain());
17091 else if (St->getValue().hasOneUse() &&
17092 ChainVal->getOpcode() == ISD::TokenFactor) {
17093 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
17094 if (ChainVal->getOperand(i).getNode() == LdVal) {
17095 TokenFactorIndex = i;
17096 Ld = cast<LoadSDNode>(St->getValue());
17098 Ops.push_back(ChainVal->getOperand(i));
17102 if (!Ld || !ISD::isNormalLoad(Ld))
17105 // If this is not the MMX case, i.e. we are just turning i64 load/store
17106 // into f64 load/store, avoid the transformation if there are multiple
17107 // uses of the loaded value.
17108 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
17111 DebugLoc LdDL = Ld->getDebugLoc();
17112 DebugLoc StDL = N->getDebugLoc();
17113 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
17114 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
17116 if (Subtarget->is64Bit() || F64IsLegal) {
17117 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
17118 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
17119 Ld->getPointerInfo(), Ld->isVolatile(),
17120 Ld->isNonTemporal(), Ld->isInvariant(),
17121 Ld->getAlignment());
17122 SDValue NewChain = NewLd.getValue(1);
17123 if (TokenFactorIndex != -1) {
17124 Ops.push_back(NewChain);
17125 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17128 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
17129 St->getPointerInfo(),
17130 St->isVolatile(), St->isNonTemporal(),
17131 St->getAlignment());
17134 // Otherwise, lower to two pairs of 32-bit loads / stores.
17135 SDValue LoAddr = Ld->getBasePtr();
17136 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
17137 DAG.getConstant(4, MVT::i32));
17139 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
17140 Ld->getPointerInfo(),
17141 Ld->isVolatile(), Ld->isNonTemporal(),
17142 Ld->isInvariant(), Ld->getAlignment());
17143 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
17144 Ld->getPointerInfo().getWithOffset(4),
17145 Ld->isVolatile(), Ld->isNonTemporal(),
17147 MinAlign(Ld->getAlignment(), 4));
17149 SDValue NewChain = LoLd.getValue(1);
17150 if (TokenFactorIndex != -1) {
17151 Ops.push_back(LoLd);
17152 Ops.push_back(HiLd);
17153 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17157 LoAddr = St->getBasePtr();
17158 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
17159 DAG.getConstant(4, MVT::i32));
17161 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
17162 St->getPointerInfo(),
17163 St->isVolatile(), St->isNonTemporal(),
17164 St->getAlignment());
17165 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
17166 St->getPointerInfo().getWithOffset(4),
17168 St->isNonTemporal(),
17169 MinAlign(St->getAlignment(), 4));
17170 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
17175 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
17176 /// and return the operands for the horizontal operation in LHS and RHS. A
17177 /// horizontal operation performs the binary operation on successive elements
17178 /// of its first operand, then on successive elements of its second operand,
17179 /// returning the resulting values in a vector. For example, if
17180 /// A = < float a0, float a1, float a2, float a3 >
17182 /// B = < float b0, float b1, float b2, float b3 >
17183 /// then the result of doing a horizontal operation on A and B is
17184 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
17185 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
17186 /// A horizontal-op B, for some already available A and B, and if so then LHS is
17187 /// set to A, RHS to B, and the routine returns 'true'.
17188 /// Note that the binary operation should have the property that if one of the
17189 /// operands is UNDEF then the result is UNDEF.
17190 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
17191 // Look for the following pattern: if
17192 // A = < float a0, float a1, float a2, float a3 >
17193 // B = < float b0, float b1, float b2, float b3 >
17195 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
17196 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
17197 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
17198 // which is A horizontal-op B.
17200 // At least one of the operands should be a vector shuffle.
17201 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
17202 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
17205 EVT VT = LHS.getValueType();
17207 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17208 "Unsupported vector type for horizontal add/sub");
17210 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
17211 // operate independently on 128-bit lanes.
17212 unsigned NumElts = VT.getVectorNumElements();
17213 unsigned NumLanes = VT.getSizeInBits()/128;
17214 unsigned NumLaneElts = NumElts / NumLanes;
17215 assert((NumLaneElts % 2 == 0) &&
17216 "Vector type should have an even number of elements in each lane");
17217 unsigned HalfLaneElts = NumLaneElts/2;
17219 // View LHS in the form
17220 // LHS = VECTOR_SHUFFLE A, B, LMask
17221 // If LHS is not a shuffle then pretend it is the shuffle
17222 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
17223 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
17226 SmallVector<int, 16> LMask(NumElts);
17227 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17228 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
17229 A = LHS.getOperand(0);
17230 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
17231 B = LHS.getOperand(1);
17232 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
17233 std::copy(Mask.begin(), Mask.end(), LMask.begin());
17235 if (LHS.getOpcode() != ISD::UNDEF)
17237 for (unsigned i = 0; i != NumElts; ++i)
17241 // Likewise, view RHS in the form
17242 // RHS = VECTOR_SHUFFLE C, D, RMask
17244 SmallVector<int, 16> RMask(NumElts);
17245 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17246 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
17247 C = RHS.getOperand(0);
17248 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
17249 D = RHS.getOperand(1);
17250 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
17251 std::copy(Mask.begin(), Mask.end(), RMask.begin());
17253 if (RHS.getOpcode() != ISD::UNDEF)
17255 for (unsigned i = 0; i != NumElts; ++i)
17259 // Check that the shuffles are both shuffling the same vectors.
17260 if (!(A == C && B == D) && !(A == D && B == C))
17263 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
17264 if (!A.getNode() && !B.getNode())
17267 // If A and B occur in reverse order in RHS, then "swap" them (which means
17268 // rewriting the mask).
17270 CommuteVectorShuffleMask(RMask, NumElts);
17272 // At this point LHS and RHS are equivalent to
17273 // LHS = VECTOR_SHUFFLE A, B, LMask
17274 // RHS = VECTOR_SHUFFLE A, B, RMask
17275 // Check that the masks correspond to performing a horizontal operation.
17276 for (unsigned i = 0; i != NumElts; ++i) {
17277 int LIdx = LMask[i], RIdx = RMask[i];
17279 // Ignore any UNDEF components.
17280 if (LIdx < 0 || RIdx < 0 ||
17281 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
17282 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
17285 // Check that successive elements are being operated on. If not, this is
17286 // not a horizontal operation.
17287 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
17288 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
17289 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
17290 if (!(LIdx == Index && RIdx == Index + 1) &&
17291 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
17295 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
17296 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
17300 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
17301 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
17302 const X86Subtarget *Subtarget) {
17303 EVT VT = N->getValueType(0);
17304 SDValue LHS = N->getOperand(0);
17305 SDValue RHS = N->getOperand(1);
17307 // Try to synthesize horizontal adds from adds of shuffles.
17308 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17309 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17310 isHorizontalBinOp(LHS, RHS, true))
17311 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
17315 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
17316 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
17317 const X86Subtarget *Subtarget) {
17318 EVT VT = N->getValueType(0);
17319 SDValue LHS = N->getOperand(0);
17320 SDValue RHS = N->getOperand(1);
17322 // Try to synthesize horizontal subs from subs of shuffles.
17323 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17324 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17325 isHorizontalBinOp(LHS, RHS, false))
17326 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
17330 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
17331 /// X86ISD::FXOR nodes.
17332 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
17333 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
17334 // F[X]OR(0.0, x) -> x
17335 // F[X]OR(x, 0.0) -> x
17336 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17337 if (C->getValueAPF().isPosZero())
17338 return N->getOperand(1);
17339 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17340 if (C->getValueAPF().isPosZero())
17341 return N->getOperand(0);
17345 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
17346 /// X86ISD::FMAX nodes.
17347 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
17348 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
17350 // Only perform optimizations if UnsafeMath is used.
17351 if (!DAG.getTarget().Options.UnsafeFPMath)
17354 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
17355 // into FMINC and FMAXC, which are Commutative operations.
17356 unsigned NewOp = 0;
17357 switch (N->getOpcode()) {
17358 default: llvm_unreachable("unknown opcode");
17359 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
17360 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
17363 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
17364 N->getOperand(0), N->getOperand(1));
17367 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
17368 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
17369 // FAND(0.0, x) -> 0.0
17370 // FAND(x, 0.0) -> 0.0
17371 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17372 if (C->getValueAPF().isPosZero())
17373 return N->getOperand(0);
17374 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17375 if (C->getValueAPF().isPosZero())
17376 return N->getOperand(1);
17380 static SDValue PerformBTCombine(SDNode *N,
17382 TargetLowering::DAGCombinerInfo &DCI) {
17383 // BT ignores high bits in the bit index operand.
17384 SDValue Op1 = N->getOperand(1);
17385 if (Op1.hasOneUse()) {
17386 unsigned BitWidth = Op1.getValueSizeInBits();
17387 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
17388 APInt KnownZero, KnownOne;
17389 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
17390 !DCI.isBeforeLegalizeOps());
17391 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17392 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
17393 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
17394 DCI.CommitTargetLoweringOpt(TLO);
17399 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
17400 SDValue Op = N->getOperand(0);
17401 if (Op.getOpcode() == ISD::BITCAST)
17402 Op = Op.getOperand(0);
17403 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
17404 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
17405 VT.getVectorElementType().getSizeInBits() ==
17406 OpVT.getVectorElementType().getSizeInBits()) {
17407 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
17412 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
17413 const X86Subtarget *Subtarget) {
17414 EVT VT = N->getValueType(0);
17415 if (!VT.isVector())
17418 SDValue N0 = N->getOperand(0);
17419 SDValue N1 = N->getOperand(1);
17420 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
17421 DebugLoc dl = N->getDebugLoc();
17423 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
17424 // both SSE and AVX2 since there is no sign-extended shift right
17425 // operation on a vector with 64-bit elements.
17426 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
17427 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
17428 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
17429 N0.getOpcode() == ISD::SIGN_EXTEND)) {
17430 SDValue N00 = N0.getOperand(0);
17432 // EXTLOAD has a better solution on AVX2,
17433 // it may be replaced with X86ISD::VSEXT node.
17434 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
17435 if (!ISD::isNormalLoad(N00.getNode()))
17438 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
17439 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
17441 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
17447 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
17448 TargetLowering::DAGCombinerInfo &DCI,
17449 const X86Subtarget *Subtarget) {
17450 if (!DCI.isBeforeLegalizeOps())
17453 if (!Subtarget->hasFp256())
17456 EVT VT = N->getValueType(0);
17457 if (VT.isVector() && VT.getSizeInBits() == 256) {
17458 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17466 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
17467 const X86Subtarget* Subtarget) {
17468 DebugLoc dl = N->getDebugLoc();
17469 EVT VT = N->getValueType(0);
17471 // Let legalize expand this if it isn't a legal type yet.
17472 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17475 EVT ScalarVT = VT.getScalarType();
17476 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
17477 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
17480 SDValue A = N->getOperand(0);
17481 SDValue B = N->getOperand(1);
17482 SDValue C = N->getOperand(2);
17484 bool NegA = (A.getOpcode() == ISD::FNEG);
17485 bool NegB = (B.getOpcode() == ISD::FNEG);
17486 bool NegC = (C.getOpcode() == ISD::FNEG);
17488 // Negative multiplication when NegA xor NegB
17489 bool NegMul = (NegA != NegB);
17491 A = A.getOperand(0);
17493 B = B.getOperand(0);
17495 C = C.getOperand(0);
17499 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
17501 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
17503 return DAG.getNode(Opcode, dl, VT, A, B, C);
17506 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
17507 TargetLowering::DAGCombinerInfo &DCI,
17508 const X86Subtarget *Subtarget) {
17509 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
17510 // (and (i32 x86isd::setcc_carry), 1)
17511 // This eliminates the zext. This transformation is necessary because
17512 // ISD::SETCC is always legalized to i8.
17513 DebugLoc dl = N->getDebugLoc();
17514 SDValue N0 = N->getOperand(0);
17515 EVT VT = N->getValueType(0);
17517 if (N0.getOpcode() == ISD::AND &&
17519 N0.getOperand(0).hasOneUse()) {
17520 SDValue N00 = N0.getOperand(0);
17521 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
17522 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17523 if (!C || C->getZExtValue() != 1)
17525 return DAG.getNode(ISD::AND, dl, VT,
17526 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
17527 N00.getOperand(0), N00.getOperand(1)),
17528 DAG.getConstant(1, VT));
17532 if (VT.is256BitVector()) {
17533 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17541 // Optimize x == -y --> x+y == 0
17542 // x != -y --> x+y != 0
17543 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
17544 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
17545 SDValue LHS = N->getOperand(0);
17546 SDValue RHS = N->getOperand(1);
17548 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17549 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
17550 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
17551 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17552 LHS.getValueType(), RHS, LHS.getOperand(1));
17553 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17554 addV, DAG.getConstant(0, addV.getValueType()), CC);
17556 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17557 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
17558 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
17559 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17560 RHS.getValueType(), LHS, RHS.getOperand(1));
17561 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17562 addV, DAG.getConstant(0, addV.getValueType()), CC);
17567 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
17568 // as "sbb reg,reg", since it can be extended without zext and produces
17569 // an all-ones bit which is more useful than 0/1 in some cases.
17570 static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
17571 return DAG.getNode(ISD::AND, DL, MVT::i8,
17572 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
17573 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
17574 DAG.getConstant(1, MVT::i8));
17577 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
17578 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
17579 TargetLowering::DAGCombinerInfo &DCI,
17580 const X86Subtarget *Subtarget) {
17581 DebugLoc DL = N->getDebugLoc();
17582 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
17583 SDValue EFLAGS = N->getOperand(1);
17585 if (CC == X86::COND_A) {
17586 // Try to convert COND_A into COND_B in an attempt to facilitate
17587 // materializing "setb reg".
17589 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
17590 // cannot take an immediate as its first operand.
17592 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
17593 EFLAGS.getValueType().isInteger() &&
17594 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
17595 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(),
17596 EFLAGS.getNode()->getVTList(),
17597 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
17598 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
17599 return MaterializeSETB(DL, NewEFLAGS, DAG);
17603 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
17604 // a zext and produces an all-ones bit which is more useful than 0/1 in some
17606 if (CC == X86::COND_B)
17607 return MaterializeSETB(DL, EFLAGS, DAG);
17611 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17612 if (Flags.getNode()) {
17613 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17614 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
17620 // Optimize branch condition evaluation.
17622 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
17623 TargetLowering::DAGCombinerInfo &DCI,
17624 const X86Subtarget *Subtarget) {
17625 DebugLoc DL = N->getDebugLoc();
17626 SDValue Chain = N->getOperand(0);
17627 SDValue Dest = N->getOperand(1);
17628 SDValue EFLAGS = N->getOperand(3);
17629 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
17633 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17634 if (Flags.getNode()) {
17635 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17636 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
17643 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
17644 const X86TargetLowering *XTLI) {
17645 SDValue Op0 = N->getOperand(0);
17646 EVT InVT = Op0->getValueType(0);
17648 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
17649 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
17650 DebugLoc dl = N->getDebugLoc();
17651 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
17652 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
17653 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
17656 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
17657 // a 32-bit target where SSE doesn't support i64->FP operations.
17658 if (Op0.getOpcode() == ISD::LOAD) {
17659 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
17660 EVT VT = Ld->getValueType(0);
17661 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
17662 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
17663 !XTLI->getSubtarget()->is64Bit() &&
17664 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17665 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
17666 Ld->getChain(), Op0, DAG);
17667 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
17674 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
17675 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
17676 X86TargetLowering::DAGCombinerInfo &DCI) {
17677 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
17678 // the result is either zero or one (depending on the input carry bit).
17679 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
17680 if (X86::isZeroNode(N->getOperand(0)) &&
17681 X86::isZeroNode(N->getOperand(1)) &&
17682 // We don't have a good way to replace an EFLAGS use, so only do this when
17684 SDValue(N, 1).use_empty()) {
17685 DebugLoc DL = N->getDebugLoc();
17686 EVT VT = N->getValueType(0);
17687 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
17688 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
17689 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
17690 DAG.getConstant(X86::COND_B,MVT::i8),
17692 DAG.getConstant(1, VT));
17693 return DCI.CombineTo(N, Res1, CarryOut);
17699 // fold (add Y, (sete X, 0)) -> adc 0, Y
17700 // (add Y, (setne X, 0)) -> sbb -1, Y
17701 // (sub (sete X, 0), Y) -> sbb 0, Y
17702 // (sub (setne X, 0), Y) -> adc -1, Y
17703 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
17704 DebugLoc DL = N->getDebugLoc();
17706 // Look through ZExts.
17707 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
17708 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
17711 SDValue SetCC = Ext.getOperand(0);
17712 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
17715 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
17716 if (CC != X86::COND_E && CC != X86::COND_NE)
17719 SDValue Cmp = SetCC.getOperand(1);
17720 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
17721 !X86::isZeroNode(Cmp.getOperand(1)) ||
17722 !Cmp.getOperand(0).getValueType().isInteger())
17725 SDValue CmpOp0 = Cmp.getOperand(0);
17726 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
17727 DAG.getConstant(1, CmpOp0.getValueType()));
17729 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
17730 if (CC == X86::COND_NE)
17731 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
17732 DL, OtherVal.getValueType(), OtherVal,
17733 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
17734 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
17735 DL, OtherVal.getValueType(), OtherVal,
17736 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
17739 /// PerformADDCombine - Do target-specific dag combines on integer adds.
17740 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
17741 const X86Subtarget *Subtarget) {
17742 EVT VT = N->getValueType(0);
17743 SDValue Op0 = N->getOperand(0);
17744 SDValue Op1 = N->getOperand(1);
17746 // Try to synthesize horizontal adds from adds of shuffles.
17747 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17748 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17749 isHorizontalBinOp(Op0, Op1, true))
17750 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
17752 return OptimizeConditionalInDecrement(N, DAG);
17755 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
17756 const X86Subtarget *Subtarget) {
17757 SDValue Op0 = N->getOperand(0);
17758 SDValue Op1 = N->getOperand(1);
17760 // X86 can't encode an immediate LHS of a sub. See if we can push the
17761 // negation into a preceding instruction.
17762 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
17763 // If the RHS of the sub is a XOR with one use and a constant, invert the
17764 // immediate. Then add one to the LHS of the sub so we can turn
17765 // X-Y -> X+~Y+1, saving one register.
17766 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
17767 isa<ConstantSDNode>(Op1.getOperand(1))) {
17768 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
17769 EVT VT = Op0.getValueType();
17770 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
17772 DAG.getConstant(~XorC, VT));
17773 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
17774 DAG.getConstant(C->getAPIntValue()+1, VT));
17778 // Try to synthesize horizontal adds from adds of shuffles.
17779 EVT VT = N->getValueType(0);
17780 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17781 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17782 isHorizontalBinOp(Op0, Op1, true))
17783 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
17785 return OptimizeConditionalInDecrement(N, DAG);
17788 /// performVZEXTCombine - Performs build vector combines
17789 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
17790 TargetLowering::DAGCombinerInfo &DCI,
17791 const X86Subtarget *Subtarget) {
17792 // (vzext (bitcast (vzext (x)) -> (vzext x)
17793 SDValue In = N->getOperand(0);
17794 while (In.getOpcode() == ISD::BITCAST)
17795 In = In.getOperand(0);
17797 if (In.getOpcode() != X86ISD::VZEXT)
17800 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0),
17804 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
17805 DAGCombinerInfo &DCI) const {
17806 SelectionDAG &DAG = DCI.DAG;
17807 switch (N->getOpcode()) {
17809 case ISD::EXTRACT_VECTOR_ELT:
17810 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
17812 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
17813 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
17814 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
17815 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
17816 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
17817 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
17820 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
17821 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
17822 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
17823 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
17824 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
17825 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
17826 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
17827 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
17828 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
17830 case X86ISD::FOR: return PerformFORCombine(N, DAG);
17832 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
17833 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
17834 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
17835 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
17836 case ISD::ANY_EXTEND:
17837 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
17838 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
17839 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
17840 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
17841 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
17842 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
17843 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
17844 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
17845 case X86ISD::SHUFP: // Handle all target specific shuffles
17846 case X86ISD::PALIGNR:
17847 case X86ISD::UNPCKH:
17848 case X86ISD::UNPCKL:
17849 case X86ISD::MOVHLPS:
17850 case X86ISD::MOVLHPS:
17851 case X86ISD::PSHUFD:
17852 case X86ISD::PSHUFHW:
17853 case X86ISD::PSHUFLW:
17854 case X86ISD::MOVSS:
17855 case X86ISD::MOVSD:
17856 case X86ISD::VPERMILP:
17857 case X86ISD::VPERM2X128:
17858 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
17859 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
17865 /// isTypeDesirableForOp - Return true if the target has native support for
17866 /// the specified value type and it is 'desirable' to use the type for the
17867 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
17868 /// instruction encodings are longer and some i16 instructions are slow.
17869 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
17870 if (!isTypeLegal(VT))
17872 if (VT != MVT::i16)
17879 case ISD::SIGN_EXTEND:
17880 case ISD::ZERO_EXTEND:
17881 case ISD::ANY_EXTEND:
17894 /// IsDesirableToPromoteOp - This method query the target whether it is
17895 /// beneficial for dag combiner to promote the specified node. If true, it
17896 /// should return the desired promotion type by reference.
17897 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
17898 EVT VT = Op.getValueType();
17899 if (VT != MVT::i16)
17902 bool Promote = false;
17903 bool Commute = false;
17904 switch (Op.getOpcode()) {
17907 LoadSDNode *LD = cast<LoadSDNode>(Op);
17908 // If the non-extending load has a single use and it's not live out, then it
17909 // might be folded.
17910 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
17911 Op.hasOneUse()*/) {
17912 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
17913 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
17914 // The only case where we'd want to promote LOAD (rather then it being
17915 // promoted as an operand is when it's only use is liveout.
17916 if (UI->getOpcode() != ISD::CopyToReg)
17923 case ISD::SIGN_EXTEND:
17924 case ISD::ZERO_EXTEND:
17925 case ISD::ANY_EXTEND:
17930 SDValue N0 = Op.getOperand(0);
17931 // Look out for (store (shl (load), x)).
17932 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
17945 SDValue N0 = Op.getOperand(0);
17946 SDValue N1 = Op.getOperand(1);
17947 if (!Commute && MayFoldLoad(N1))
17949 // Avoid disabling potential load folding opportunities.
17950 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
17952 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
17962 //===----------------------------------------------------------------------===//
17963 // X86 Inline Assembly Support
17964 //===----------------------------------------------------------------------===//
17967 // Helper to match a string separated by whitespace.
17968 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
17969 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
17971 for (unsigned i = 0, e = args.size(); i != e; ++i) {
17972 StringRef piece(*args[i]);
17973 if (!s.startswith(piece)) // Check if the piece matches.
17976 s = s.substr(piece.size());
17977 StringRef::size_type pos = s.find_first_not_of(" \t");
17978 if (pos == 0) // We matched a prefix.
17986 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
17989 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
17990 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
17992 std::string AsmStr = IA->getAsmString();
17994 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
17995 if (!Ty || Ty->getBitWidth() % 16 != 0)
17998 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
17999 SmallVector<StringRef, 4> AsmPieces;
18000 SplitString(AsmStr, AsmPieces, ";\n");
18002 switch (AsmPieces.size()) {
18003 default: return false;
18005 // FIXME: this should verify that we are targeting a 486 or better. If not,
18006 // we will turn this bswap into something that will be lowered to logical
18007 // ops instead of emitting the bswap asm. For now, we don't support 486 or
18008 // lower so don't worry about this.
18010 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
18011 matchAsm(AsmPieces[0], "bswapl", "$0") ||
18012 matchAsm(AsmPieces[0], "bswapq", "$0") ||
18013 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
18014 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
18015 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
18016 // No need to check constraints, nothing other than the equivalent of
18017 // "=r,0" would be valid here.
18018 return IntrinsicLowering::LowerToByteSwap(CI);
18021 // rorw $$8, ${0:w} --> llvm.bswap.i16
18022 if (CI->getType()->isIntegerTy(16) &&
18023 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18024 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
18025 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
18027 const std::string &ConstraintsStr = IA->getConstraintString();
18028 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18029 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18030 if (AsmPieces.size() == 4 &&
18031 AsmPieces[0] == "~{cc}" &&
18032 AsmPieces[1] == "~{dirflag}" &&
18033 AsmPieces[2] == "~{flags}" &&
18034 AsmPieces[3] == "~{fpsr}")
18035 return IntrinsicLowering::LowerToByteSwap(CI);
18039 if (CI->getType()->isIntegerTy(32) &&
18040 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18041 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
18042 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
18043 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
18045 const std::string &ConstraintsStr = IA->getConstraintString();
18046 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18047 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18048 if (AsmPieces.size() == 4 &&
18049 AsmPieces[0] == "~{cc}" &&
18050 AsmPieces[1] == "~{dirflag}" &&
18051 AsmPieces[2] == "~{flags}" &&
18052 AsmPieces[3] == "~{fpsr}")
18053 return IntrinsicLowering::LowerToByteSwap(CI);
18056 if (CI->getType()->isIntegerTy(64)) {
18057 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
18058 if (Constraints.size() >= 2 &&
18059 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
18060 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
18061 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
18062 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
18063 matchAsm(AsmPieces[1], "bswap", "%edx") &&
18064 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
18065 return IntrinsicLowering::LowerToByteSwap(CI);
18073 /// getConstraintType - Given a constraint letter, return the type of
18074 /// constraint it is for this target.
18075 X86TargetLowering::ConstraintType
18076 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
18077 if (Constraint.size() == 1) {
18078 switch (Constraint[0]) {
18089 return C_RegisterClass;
18113 return TargetLowering::getConstraintType(Constraint);
18116 /// Examine constraint type and operand type and determine a weight value.
18117 /// This object must already have been set up with the operand type
18118 /// and the current alternative constraint selected.
18119 TargetLowering::ConstraintWeight
18120 X86TargetLowering::getSingleConstraintMatchWeight(
18121 AsmOperandInfo &info, const char *constraint) const {
18122 ConstraintWeight weight = CW_Invalid;
18123 Value *CallOperandVal = info.CallOperandVal;
18124 // If we don't have a value, we can't do a match,
18125 // but allow it at the lowest weight.
18126 if (CallOperandVal == NULL)
18128 Type *type = CallOperandVal->getType();
18129 // Look at the constraint type.
18130 switch (*constraint) {
18132 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
18143 if (CallOperandVal->getType()->isIntegerTy())
18144 weight = CW_SpecificReg;
18149 if (type->isFloatingPointTy())
18150 weight = CW_SpecificReg;
18153 if (type->isX86_MMXTy() && Subtarget->hasMMX())
18154 weight = CW_SpecificReg;
18158 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
18159 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
18160 weight = CW_Register;
18163 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
18164 if (C->getZExtValue() <= 31)
18165 weight = CW_Constant;
18169 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18170 if (C->getZExtValue() <= 63)
18171 weight = CW_Constant;
18175 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18176 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
18177 weight = CW_Constant;
18181 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18182 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
18183 weight = CW_Constant;
18187 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18188 if (C->getZExtValue() <= 3)
18189 weight = CW_Constant;
18193 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18194 if (C->getZExtValue() <= 0xff)
18195 weight = CW_Constant;
18200 if (dyn_cast<ConstantFP>(CallOperandVal)) {
18201 weight = CW_Constant;
18205 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18206 if ((C->getSExtValue() >= -0x80000000LL) &&
18207 (C->getSExtValue() <= 0x7fffffffLL))
18208 weight = CW_Constant;
18212 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18213 if (C->getZExtValue() <= 0xffffffff)
18214 weight = CW_Constant;
18221 /// LowerXConstraint - try to replace an X constraint, which matches anything,
18222 /// with another that has more specific requirements based on the type of the
18223 /// corresponding operand.
18224 const char *X86TargetLowering::
18225 LowerXConstraint(EVT ConstraintVT) const {
18226 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
18227 // 'f' like normal targets.
18228 if (ConstraintVT.isFloatingPoint()) {
18229 if (Subtarget->hasSSE2())
18231 if (Subtarget->hasSSE1())
18235 return TargetLowering::LowerXConstraint(ConstraintVT);
18238 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
18239 /// vector. If it is invalid, don't add anything to Ops.
18240 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
18241 std::string &Constraint,
18242 std::vector<SDValue>&Ops,
18243 SelectionDAG &DAG) const {
18244 SDValue Result(0, 0);
18246 // Only support length 1 constraints for now.
18247 if (Constraint.length() > 1) return;
18249 char ConstraintLetter = Constraint[0];
18250 switch (ConstraintLetter) {
18253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18254 if (C->getZExtValue() <= 31) {
18255 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18261 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18262 if (C->getZExtValue() <= 63) {
18263 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18269 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18270 if (isInt<8>(C->getSExtValue())) {
18271 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18277 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18278 if (C->getZExtValue() <= 255) {
18279 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18285 // 32-bit signed value
18286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18287 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18288 C->getSExtValue())) {
18289 // Widen to 64 bits here to get it sign extended.
18290 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
18293 // FIXME gcc accepts some relocatable values here too, but only in certain
18294 // memory models; it's complicated.
18299 // 32-bit unsigned value
18300 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18301 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18302 C->getZExtValue())) {
18303 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18307 // FIXME gcc accepts some relocatable values here too, but only in certain
18308 // memory models; it's complicated.
18312 // Literal immediates are always ok.
18313 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
18314 // Widen to 64 bits here to get it sign extended.
18315 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
18319 // In any sort of PIC mode addresses need to be computed at runtime by
18320 // adding in a register or some sort of table lookup. These can't
18321 // be used as immediates.
18322 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
18325 // If we are in non-pic codegen mode, we allow the address of a global (with
18326 // an optional displacement) to be used with 'i'.
18327 GlobalAddressSDNode *GA = 0;
18328 int64_t Offset = 0;
18330 // Match either (GA), (GA+C), (GA+C1+C2), etc.
18332 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
18333 Offset += GA->getOffset();
18335 } else if (Op.getOpcode() == ISD::ADD) {
18336 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
18337 Offset += C->getZExtValue();
18338 Op = Op.getOperand(0);
18341 } else if (Op.getOpcode() == ISD::SUB) {
18342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
18343 Offset += -C->getZExtValue();
18344 Op = Op.getOperand(0);
18349 // Otherwise, this isn't something we can handle, reject it.
18353 const GlobalValue *GV = GA->getGlobal();
18354 // If we require an extra load to get this address, as in PIC mode, we
18355 // can't accept it.
18356 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
18357 getTargetMachine())))
18360 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
18361 GA->getValueType(0), Offset);
18366 if (Result.getNode()) {
18367 Ops.push_back(Result);
18370 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
18373 std::pair<unsigned, const TargetRegisterClass*>
18374 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
18376 // First, see if this is a constraint that directly corresponds to an LLVM
18378 if (Constraint.size() == 1) {
18379 // GCC Constraint Letters
18380 switch (Constraint[0]) {
18382 // TODO: Slight differences here in allocation order and leaving
18383 // RIP in the class. Do they matter any more here than they do
18384 // in the normal allocation?
18385 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
18386 if (Subtarget->is64Bit()) {
18387 if (VT == MVT::i32 || VT == MVT::f32)
18388 return std::make_pair(0U, &X86::GR32RegClass);
18389 if (VT == MVT::i16)
18390 return std::make_pair(0U, &X86::GR16RegClass);
18391 if (VT == MVT::i8 || VT == MVT::i1)
18392 return std::make_pair(0U, &X86::GR8RegClass);
18393 if (VT == MVT::i64 || VT == MVT::f64)
18394 return std::make_pair(0U, &X86::GR64RegClass);
18397 // 32-bit fallthrough
18398 case 'Q': // Q_REGS
18399 if (VT == MVT::i32 || VT == MVT::f32)
18400 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
18401 if (VT == MVT::i16)
18402 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
18403 if (VT == MVT::i8 || VT == MVT::i1)
18404 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
18405 if (VT == MVT::i64)
18406 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
18408 case 'r': // GENERAL_REGS
18409 case 'l': // INDEX_REGS
18410 if (VT == MVT::i8 || VT == MVT::i1)
18411 return std::make_pair(0U, &X86::GR8RegClass);
18412 if (VT == MVT::i16)
18413 return std::make_pair(0U, &X86::GR16RegClass);
18414 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
18415 return std::make_pair(0U, &X86::GR32RegClass);
18416 return std::make_pair(0U, &X86::GR64RegClass);
18417 case 'R': // LEGACY_REGS
18418 if (VT == MVT::i8 || VT == MVT::i1)
18419 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
18420 if (VT == MVT::i16)
18421 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
18422 if (VT == MVT::i32 || !Subtarget->is64Bit())
18423 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
18424 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
18425 case 'f': // FP Stack registers.
18426 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
18427 // value to the correct fpstack register class.
18428 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
18429 return std::make_pair(0U, &X86::RFP32RegClass);
18430 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
18431 return std::make_pair(0U, &X86::RFP64RegClass);
18432 return std::make_pair(0U, &X86::RFP80RegClass);
18433 case 'y': // MMX_REGS if MMX allowed.
18434 if (!Subtarget->hasMMX()) break;
18435 return std::make_pair(0U, &X86::VR64RegClass);
18436 case 'Y': // SSE_REGS if SSE2 allowed
18437 if (!Subtarget->hasSSE2()) break;
18439 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
18440 if (!Subtarget->hasSSE1()) break;
18442 switch (VT.getSimpleVT().SimpleTy) {
18444 // Scalar SSE types.
18447 return std::make_pair(0U, &X86::FR32RegClass);
18450 return std::make_pair(0U, &X86::FR64RegClass);
18458 return std::make_pair(0U, &X86::VR128RegClass);
18466 return std::make_pair(0U, &X86::VR256RegClass);
18472 // Use the default implementation in TargetLowering to convert the register
18473 // constraint into a member of a register class.
18474 std::pair<unsigned, const TargetRegisterClass*> Res;
18475 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
18477 // Not found as a standard register?
18478 if (Res.second == 0) {
18479 // Map st(0) -> st(7) -> ST0
18480 if (Constraint.size() == 7 && Constraint[0] == '{' &&
18481 tolower(Constraint[1]) == 's' &&
18482 tolower(Constraint[2]) == 't' &&
18483 Constraint[3] == '(' &&
18484 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
18485 Constraint[5] == ')' &&
18486 Constraint[6] == '}') {
18488 Res.first = X86::ST0+Constraint[4]-'0';
18489 Res.second = &X86::RFP80RegClass;
18493 // GCC allows "st(0)" to be called just plain "st".
18494 if (StringRef("{st}").equals_lower(Constraint)) {
18495 Res.first = X86::ST0;
18496 Res.second = &X86::RFP80RegClass;
18501 if (StringRef("{flags}").equals_lower(Constraint)) {
18502 Res.first = X86::EFLAGS;
18503 Res.second = &X86::CCRRegClass;
18507 // 'A' means EAX + EDX.
18508 if (Constraint == "A") {
18509 Res.first = X86::EAX;
18510 Res.second = &X86::GR32_ADRegClass;
18516 // Otherwise, check to see if this is a register class of the wrong value
18517 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
18518 // turn into {ax},{dx}.
18519 if (Res.second->hasType(VT))
18520 return Res; // Correct type already, nothing to do.
18522 // All of the single-register GCC register classes map their values onto
18523 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
18524 // really want an 8-bit or 32-bit register, map to the appropriate register
18525 // class and return the appropriate register.
18526 if (Res.second == &X86::GR16RegClass) {
18527 if (VT == MVT::i8 || VT == MVT::i1) {
18528 unsigned DestReg = 0;
18529 switch (Res.first) {
18531 case X86::AX: DestReg = X86::AL; break;
18532 case X86::DX: DestReg = X86::DL; break;
18533 case X86::CX: DestReg = X86::CL; break;
18534 case X86::BX: DestReg = X86::BL; break;
18537 Res.first = DestReg;
18538 Res.second = &X86::GR8RegClass;
18540 } else if (VT == MVT::i32 || VT == MVT::f32) {
18541 unsigned DestReg = 0;
18542 switch (Res.first) {
18544 case X86::AX: DestReg = X86::EAX; break;
18545 case X86::DX: DestReg = X86::EDX; break;
18546 case X86::CX: DestReg = X86::ECX; break;
18547 case X86::BX: DestReg = X86::EBX; break;
18548 case X86::SI: DestReg = X86::ESI; break;
18549 case X86::DI: DestReg = X86::EDI; break;
18550 case X86::BP: DestReg = X86::EBP; break;
18551 case X86::SP: DestReg = X86::ESP; break;
18554 Res.first = DestReg;
18555 Res.second = &X86::GR32RegClass;
18557 } else if (VT == MVT::i64 || VT == MVT::f64) {
18558 unsigned DestReg = 0;
18559 switch (Res.first) {
18561 case X86::AX: DestReg = X86::RAX; break;
18562 case X86::DX: DestReg = X86::RDX; break;
18563 case X86::CX: DestReg = X86::RCX; break;
18564 case X86::BX: DestReg = X86::RBX; break;
18565 case X86::SI: DestReg = X86::RSI; break;
18566 case X86::DI: DestReg = X86::RDI; break;
18567 case X86::BP: DestReg = X86::RBP; break;
18568 case X86::SP: DestReg = X86::RSP; break;
18571 Res.first = DestReg;
18572 Res.second = &X86::GR64RegClass;
18575 } else if (Res.second == &X86::FR32RegClass ||
18576 Res.second == &X86::FR64RegClass ||
18577 Res.second == &X86::VR128RegClass) {
18578 // Handle references to XMM physical registers that got mapped into the
18579 // wrong class. This can happen with constraints like {xmm0} where the
18580 // target independent register mapper will just pick the first match it can
18581 // find, ignoring the required type.
18583 if (VT == MVT::f32 || VT == MVT::i32)
18584 Res.second = &X86::FR32RegClass;
18585 else if (VT == MVT::f64 || VT == MVT::i64)
18586 Res.second = &X86::FR64RegClass;
18587 else if (X86::VR128RegClass.hasType(VT))
18588 Res.second = &X86::VR128RegClass;
18589 else if (X86::VR256RegClass.hasType(VT))
18590 Res.second = &X86::VR256RegClass;