1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec,
69 EVT VT = Vec.getValueType();
70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
71 EVT ElVT = VT.getVectorElementType();
72 int Factor = VT.getSizeInBits()/128;
73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
74 VT.getVectorNumElements()/Factor);
76 // Extract from UNDEF is UNDEF.
77 if (Vec.getOpcode() == ISD::UNDEF)
78 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
80 if (isa<ConstantSDNode>(Idx)) {
81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
84 // we can match to VEXTRACTF128.
85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
87 // This is the index of the first element of the 128-bit chunk
89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
102 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
103 /// sets things up to match to an AVX VINSERTF128 instruction or a
104 /// simple superregister reference. Idx is an index in the 128 bits
105 /// we want. It need not be aligned to a 128-bit bounday. That makes
106 /// lowering INSERT_VECTOR_ELT operations easier.
107 static SDValue Insert128BitVector(SDValue Result,
112 if (isa<ConstantSDNode>(Idx)) {
113 EVT VT = Vec.getValueType();
114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
116 EVT ElVT = VT.getVectorElementType();
117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
118 EVT ResultVT = Result.getValueType();
120 // Insert the relevant 128 bits.
121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
123 // This is the index of the first element of the 128-bit chunk
125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X8664_MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetELF())
148 return new TargetLoweringObjectFileELF();
149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
150 return new TargetLoweringObjectFileCOFF();
151 llvm_unreachable("unknown subtarget type");
154 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
155 : TargetLowering(TM, createTLOF(TM)) {
156 Subtarget = &TM.getSubtarget<X86Subtarget>();
157 X86ScalarSSEf64 = Subtarget->hasSSE2();
158 X86ScalarSSEf32 = Subtarget->hasSSE1();
159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
161 RegInfo = TM.getRegisterInfo();
162 TD = getTargetData();
164 // Set up the TargetLowering object.
165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
167 // X86 is weird, it always uses i8 for shift amounts and setcc results.
168 setBooleanContents(ZeroOrOneBooleanContent);
169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
172 // For 64-bit since we have so many registers use the ILP scheduler, for
173 // 32-bit code use the register pressure specific scheduling.
174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
175 if (Subtarget->is64Bit())
176 setSchedulingPreference(Sched::ILP);
177 else if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::Hybrid);
180 setSchedulingPreference(Sched::RegPressure);
181 setStackPointerRegisterToSaveRestore(X86StackPtr);
183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
184 // Setup Windows compiler runtime calls.
185 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
187 setLibcallName(RTLIB::SREM_I64, "_allrem");
188 setLibcallName(RTLIB::UREM_I64, "_aullrem");
189 setLibcallName(RTLIB::MUL_I64, "_allmul");
190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
196 // The _ftol2 runtime function has an unusual calling conv, which
197 // is modeled by a special pseudo-instruction.
198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
204 if (Subtarget->isTargetDarwin()) {
205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
206 setUseUnderscoreSetJmp(false);
207 setUseUnderscoreLongJmp(false);
208 } else if (Subtarget->isTargetMingw()) {
209 // MS runtime is weird: it exports _setjmp, but longjmp!
210 setUseUnderscoreSetJmp(true);
211 setUseUnderscoreLongJmp(false);
213 setUseUnderscoreSetJmp(true);
214 setUseUnderscoreLongJmp(true);
217 // Set up the register classes.
218 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
219 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
220 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
221 if (Subtarget->is64Bit())
222 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
226 // We don't accept any truncstore of integer registers.
227 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
228 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
230 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
234 // SETOEQ and SETUNE require checking two conditions.
235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
248 if (Subtarget->is64Bit()) {
249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 } else if (!TM.Options.UseSoftFloat) {
252 // We have an algorithm for SSE2->double, and we turn this into a
253 // 64-bit FILD followed by conditional FADD for other targets.
254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
255 // We have an algorithm for SSE2, and we turn this into a 64-bit
256 // FILD for other targets.
257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
265 if (!TM.Options.UseSoftFloat) {
266 // SSE has no i16 to fp conversion, only i32
267 if (X86ScalarSSEf32) {
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
269 // f32 and f64 cases are Legal, f80 case is not
270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
281 // are Legal, f80 is custom lowered.
282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
290 if (X86ScalarSSEf32) {
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
292 // f32 and f64 cases are Legal, f80 case is not
293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
299 // Handle FP_TO_UINT by promoting the destination to a larger signed
301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
305 if (Subtarget->is64Bit()) {
306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
308 } else if (!TM.Options.UseSoftFloat) {
309 // Since AVX is a superset of SSE3, only check for SSE here.
310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
311 // Expand FP_TO_UINT into a select.
312 // FIXME: We would like to use a Custom expander here eventually to do
313 // the optimal thing for SSE vs. the default expansion in the legalizer.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
316 // With SSE3 we can use fisttpll to convert to a signed i64; without
317 // SSE, we're stuck with a fistpll.
318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
321 if (isTargetFTOL()) {
322 // Use the _ftol2 runtime function, which has a pseudo-instruction
323 // to handle its weird calling convention.
324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
327 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
328 if (!X86ScalarSSEf64) {
329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
333 // Without SSE, i64->f64 goes through memory.
334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
338 // Scalar integer divide and remainder are lowered to use operations that
339 // produce two results, to match the available instructions. This exposes
340 // the two-result form to trivial CSE, which is able to combine x/y and x%y
341 // into a single instruction.
343 // Scalar integer multiply-high is also lowered to use two-result
344 // operations, to match the available instructions. However, plain multiply
345 // (low) operations are left as Legal, as there are single-result
346 // instructions for this in x86. Using the two-result multiply instructions
347 // when both high and low results are needed must be arranged by dagcombine.
348 for (unsigned i = 0, e = 4; i != e; ++i) {
350 setOperationAction(ISD::MULHS, VT, Expand);
351 setOperationAction(ISD::MULHU, VT, Expand);
352 setOperationAction(ISD::SDIV, VT, Expand);
353 setOperationAction(ISD::UDIV, VT, Expand);
354 setOperationAction(ISD::SREM, VT, Expand);
355 setOperationAction(ISD::UREM, VT, Expand);
357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
358 setOperationAction(ISD::ADDC, VT, Custom);
359 setOperationAction(ISD::ADDE, VT, Custom);
360 setOperationAction(ISD::SUBC, VT, Custom);
361 setOperationAction(ISD::SUBE, VT, Custom);
364 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
365 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
366 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
368 if (Subtarget->is64Bit())
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f64 , Expand);
376 setOperationAction(ISD::FREM , MVT::f80 , Expand);
377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
379 // Promote the i8 variants and force them on up to i32 which has a shorter
381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
385 if (Subtarget->hasBMI()) {
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
388 if (Subtarget->is64Bit())
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
397 if (Subtarget->hasLZCNT()) {
398 // When promoting the i8 variants, force them to i32 for a shorter
400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
406 if (Subtarget->is64Bit())
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
421 if (Subtarget->hasPOPCNT()) {
422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
427 if (Subtarget->is64Bit())
428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
434 // These should be promoted to a larger select which is supported.
435 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
436 // X86 wants to expand cmov itself.
437 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
438 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
440 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
443 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
446 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
449 if (Subtarget->is64Bit()) {
450 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
460 if (Subtarget->is64Bit())
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
464 if (Subtarget->is64Bit()) {
465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
475 if (Subtarget->is64Bit()) {
476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
481 if (Subtarget->hasSSE1())
482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
487 // On X86 and X86-64, atomic operations are lowered to locked instructions.
488 // Locked instructions, in turn, have implicit fence semantics (all memory
489 // operations are flushed before issuing the locked instruction, and they
490 // are not buffered), so we can fold away the common pattern of
491 // fence-atomic-fence.
492 setShouldFoldAtomicFences(true);
494 // Expand certain atomics
495 for (unsigned i = 0, e = 4; i != e; ++i) {
497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
502 if (!Subtarget->is64Bit()) {
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
513 if (Subtarget->hasCmpxchg16b()) {
514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
517 // FIXME - use subtarget debug flags
518 if (!Subtarget->isTargetDarwin() &&
519 !Subtarget->isTargetELF() &&
520 !Subtarget->isTargetCygMing()) {
521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
528 if (Subtarget->is64Bit()) {
529 setExceptionPointerRegister(X86::RAX);
530 setExceptionSelectorRegister(X86::RDX);
532 setExceptionPointerRegister(X86::EAX);
533 setExceptionSelectorRegister(X86::EDX);
535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::TRAP, MVT::Other, Legal);
543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
544 setOperationAction(ISD::VASTART , MVT::Other, Custom);
545 setOperationAction(ISD::VAEND , MVT::Other, Expand);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::VAARG , MVT::Other, Custom);
548 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
550 setOperationAction(ISD::VAARG , MVT::Other, Expand);
551 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
559 MVT::i64 : MVT::i32, Custom);
560 else if (TM.Options.EnableSegmentedStacks)
561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
562 MVT::i64 : MVT::i32, Custom);
564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 MVT::i64 : MVT::i32, Expand);
567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
568 // f32 and f64 use SSE.
569 // Set up the FP register classes.
570 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
571 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
573 // Use ANDPD to simulate FABS.
574 setOperationAction(ISD::FABS , MVT::f64, Custom);
575 setOperationAction(ISD::FABS , MVT::f32, Custom);
577 // Use XORP to simulate FNEG.
578 setOperationAction(ISD::FNEG , MVT::f64, Custom);
579 setOperationAction(ISD::FNEG , MVT::f32, Custom);
581 // Use ANDPD and ORPD to simulate FCOPYSIGN.
582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
585 // Lower this to FGETSIGNx86 plus an AND.
586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
589 // We don't support sin/cos/fmod
590 setOperationAction(ISD::FSIN , MVT::f64, Expand);
591 setOperationAction(ISD::FCOS , MVT::f64, Expand);
592 setOperationAction(ISD::FSIN , MVT::f32, Expand);
593 setOperationAction(ISD::FCOS , MVT::f32, Expand);
595 // Expand FP immediates into loads from the stack, except for the special
597 addLegalFPImmediate(APFloat(+0.0)); // xorpd
598 addLegalFPImmediate(APFloat(+0.0f)); // xorps
599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
600 // Use SSE for f32, x87 for f64.
601 // Set up the FP register classes.
602 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
605 // Use ANDPS to simulate FABS.
606 setOperationAction(ISD::FABS , MVT::f32, Custom);
608 // Use XORP to simulate FNEG.
609 setOperationAction(ISD::FNEG , MVT::f32, Custom);
611 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
613 // Use ANDPS and ORPS to simulate FCOPYSIGN.
614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
617 // We don't support sin/cos/fmod
618 setOperationAction(ISD::FSIN , MVT::f32, Expand);
619 setOperationAction(ISD::FCOS , MVT::f32, Expand);
621 // Special cases we handle for FP constants.
622 addLegalFPImmediate(APFloat(+0.0f)); // xorps
623 addLegalFPImmediate(APFloat(+0.0)); // FLD0
624 addLegalFPImmediate(APFloat(+1.0)); // FLD1
625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
628 if (!TM.Options.UnsafeFPMath) {
629 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
630 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
632 } else if (!TM.Options.UseSoftFloat) {
633 // f32 and f64 in x87.
634 // Set up the FP register classes.
635 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
636 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
638 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
639 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
643 if (!TM.Options.UnsafeFPMath) {
644 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
645 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
647 addLegalFPImmediate(APFloat(+0.0)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
657 // We don't support FMA.
658 setOperationAction(ISD::FMA, MVT::f64, Expand);
659 setOperationAction(ISD::FMA, MVT::f32, Expand);
661 // Long double always uses X87.
662 if (!TM.Options.UseSoftFloat) {
663 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
664 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
668 addLegalFPImmediate(TmpFlt); // FLD0
670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
673 APFloat TmpFlt2(+1.0);
674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
676 addLegalFPImmediate(TmpFlt2); // FLD1
677 TmpFlt2.changeSign();
678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
681 if (!TM.Options.UnsafeFPMath) {
682 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
683 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
687 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
689 setOperationAction(ISD::FRINT, MVT::f80, Expand);
690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
691 setOperationAction(ISD::FMA, MVT::f80, Expand);
694 // Always use a library call for pow.
695 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
696 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
699 setOperationAction(ISD::FLOG, MVT::f80, Expand);
700 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
702 setOperationAction(ISD::FEXP, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
705 // First set operation action for all vector types to either promote
706 // (for widening) or expand (for scalarization). Then we will selectively
707 // turn on ones that can be effectively codegen'd.
708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
769 setTruncStoreAction((MVT::SimpleValueType)VT,
770 (MVT::SimpleValueType)InnerVT, Expand);
771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
777 // with -msoft-float, disable use of MMX as well.
778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
779 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
780 // No operations on x86mmx supported, everything uses intrinsics.
783 // MMX-sized vectors (other than x86mmx) are expected to be expanded
784 // into smaller operations.
785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
789 setOperationAction(ISD::AND, MVT::v8i8, Expand);
790 setOperationAction(ISD::AND, MVT::v4i16, Expand);
791 setOperationAction(ISD::AND, MVT::v2i32, Expand);
792 setOperationAction(ISD::AND, MVT::v1i64, Expand);
793 setOperationAction(ISD::OR, MVT::v8i8, Expand);
794 setOperationAction(ISD::OR, MVT::v4i16, Expand);
795 setOperationAction(ISD::OR, MVT::v2i32, Expand);
796 setOperationAction(ISD::OR, MVT::v1i64, Expand);
797 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
816 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
818 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
833 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
836 // registers cannot be used even for integer operations.
837 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
838 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
839 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
840 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
842 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
843 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
844 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
845 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
846 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
847 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
848 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
849 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
850 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
851 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
852 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
878 EVT VT = (MVT::SimpleValueType)i;
879 // Do not attempt to custom lower non-power-of-2 vectors
880 if (!isPowerOf2_32(VT.getVectorNumElements()))
882 // Do not attempt to custom lower non-128-bit vectors
883 if (!VT.is128BitVector())
885 setOperationAction(ISD::BUILD_VECTOR,
886 VT.getSimpleVT().SimpleTy, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE,
888 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
890 VT.getSimpleVT().SimpleTy, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
900 if (Subtarget->is64Bit()) {
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
910 // Do not attempt to promote non-128-bit vectors
911 if (!VT.is128BitVector())
914 setOperationAction(ISD::AND, SVT, Promote);
915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
916 setOperationAction(ISD::OR, SVT, Promote);
917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
918 setOperationAction(ISD::XOR, SVT, Promote);
919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
920 setOperationAction(ISD::LOAD, SVT, Promote);
921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
922 setOperationAction(ISD::SELECT, SVT, Promote);
923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
926 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
938 if (Subtarget->hasSSE41()) {
939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
940 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
942 setOperationAction(ISD::FRINT, MVT::f32, Legal);
943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
945 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
947 setOperationAction(ISD::FRINT, MVT::f64, Legal);
948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
950 // FIXME: Do we need to handle scalar-to-vector here?
951 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
959 // i8 and i16 vectors are custom , because the source register and source
960 // source memory operand types are not the same width. f32 vectors are
961 // custom since the immediate controlling the insert encodes additional
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
973 // FIXME: these should be Legal but thats only for the case where
974 // the index is constant. For now custom expand to deal with that.
975 if (Subtarget->is64Bit()) {
976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
981 if (Subtarget->hasSSE2()) {
982 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
983 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
985 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
986 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
988 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
989 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
991 if (Subtarget->hasAVX2()) {
992 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
993 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
995 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
996 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
998 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1010 if (Subtarget->hasSSE42())
1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1014 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1015 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1016 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1017 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1018 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1019 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1073 if (Subtarget->hasAVX2()) {
1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1087 // Don't lower v32i8 because there is no 128-bit byte mul
1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1112 // Don't lower v32i8 because there is no 128-bit byte mul
1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1123 // Custom lower several nodes for 256-bit types.
1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1129 // Extract subvector is special because the value type
1130 // (result) is 128-bit but the source is 256-bit wide.
1131 if (VT.is128BitVector())
1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1134 // Do not attempt to custom lower other non-256-bit vectors
1135 if (!VT.is256BitVector())
1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1151 // Do not attempt to promote non-256-bit vectors
1152 if (!VT.is256BitVector())
1155 setOperationAction(ISD::AND, SVT, Promote);
1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1157 setOperationAction(ISD::OR, SVT, Promote);
1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1159 setOperationAction(ISD::XOR, SVT, Promote);
1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1161 setOperationAction(ISD::LOAD, SVT, Promote);
1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1163 setOperationAction(ISD::SELECT, SVT, Promote);
1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1169 // of this type with custom code.
1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1176 // We want to custom lower some of our intrinsics.
1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1181 // handle type legalization for these operations here.
1183 // FIXME: We really should do custom legalization for addition and
1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1185 // than generic legalization for 64-bit multiplication-with-overflow, though.
1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1187 // Add/Sub/Mul with overflow operations are custom lowered.
1189 setOperationAction(ISD::SADDO, VT, Custom);
1190 setOperationAction(ISD::UADDO, VT, Custom);
1191 setOperationAction(ISD::SSUBO, VT, Custom);
1192 setOperationAction(ISD::USUBO, VT, Custom);
1193 setOperationAction(ISD::SMULO, VT, Custom);
1194 setOperationAction(ISD::UMULO, VT, Custom);
1197 // There are no 8-bit 3-address imul/mul instructions
1198 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1199 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1201 if (!Subtarget->is64Bit()) {
1202 // These libcalls are not available in 32-bit.
1203 setLibcallName(RTLIB::SHL_I128, 0);
1204 setLibcallName(RTLIB::SRL_I128, 0);
1205 setLibcallName(RTLIB::SRA_I128, 0);
1208 // We have target-specific dag combine patterns for the following nodes:
1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1211 setTargetDAGCombine(ISD::VSELECT);
1212 setTargetDAGCombine(ISD::SELECT);
1213 setTargetDAGCombine(ISD::SHL);
1214 setTargetDAGCombine(ISD::SRA);
1215 setTargetDAGCombine(ISD::SRL);
1216 setTargetDAGCombine(ISD::OR);
1217 setTargetDAGCombine(ISD::AND);
1218 setTargetDAGCombine(ISD::ADD);
1219 setTargetDAGCombine(ISD::FADD);
1220 setTargetDAGCombine(ISD::FSUB);
1221 setTargetDAGCombine(ISD::SUB);
1222 setTargetDAGCombine(ISD::LOAD);
1223 setTargetDAGCombine(ISD::STORE);
1224 setTargetDAGCombine(ISD::ZERO_EXTEND);
1225 setTargetDAGCombine(ISD::SIGN_EXTEND);
1226 setTargetDAGCombine(ISD::TRUNCATE);
1227 setTargetDAGCombine(ISD::SINT_TO_FP);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 setPrefFunctionAlignment(4); // 2^4 bytes.
1250 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1251 if (!VT.isVector()) return MVT::i8;
1252 return VT.changeVectorElementTypeToInteger();
1256 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1257 /// the desired ByVal argument alignment.
1258 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 if (VTy->getBitWidth() == 128)
1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1265 unsigned EltAlign = 0;
1266 getMaxByValAlign(ATy->getElementType(), EltAlign);
1267 if (EltAlign > MaxAlign)
1268 MaxAlign = EltAlign;
1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1271 unsigned EltAlign = 0;
1272 getMaxByValAlign(STy->getElementType(i), EltAlign);
1273 if (EltAlign > MaxAlign)
1274 MaxAlign = EltAlign;
1282 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1283 /// function arguments in the caller parameter area. For X86, aggregates
1284 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1285 /// are at 4-byte boundaries.
1286 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1287 if (Subtarget->is64Bit()) {
1288 // Max of 8 and alignment of type.
1289 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1296 if (Subtarget->hasSSE1())
1297 getMaxByValAlign(Ty, Align);
1301 /// getOptimalMemOpType - Returns the target specific optimal type for load
1302 /// and store operations as a result of memset, memcpy, and memmove
1303 /// lowering. If DstAlign is zero that means it's safe to destination
1304 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1305 /// means there isn't a need to check it against alignment requirement,
1306 /// probably because the source does not need to be loaded. If
1307 /// 'IsZeroVal' is true, that means it's safe to return a
1308 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1309 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1310 /// constant so it does not need to be loaded.
1311 /// It returns EVT::Other if the type should be determined using generic
1312 /// target-independent logic.
1314 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1315 unsigned DstAlign, unsigned SrcAlign,
1318 MachineFunction &MF) const {
1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1320 // linux. This is because the stack realignment code can't handle certain
1321 // cases like PR2962. This should be removed when PR2962 is fixed.
1322 const Function *F = MF.getFunction();
1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1326 (Subtarget->isUnalignedMemAccessFast() ||
1327 ((DstAlign == 0 || DstAlign >= 16) &&
1328 (SrcAlign == 0 || SrcAlign >= 16))) &&
1329 Subtarget->getStackAlignment() >= 16) {
1330 if (Subtarget->getStackAlignment() >= 32) {
1331 if (Subtarget->hasAVX2())
1333 if (Subtarget->hasAVX())
1336 if (Subtarget->hasSSE2())
1338 if (Subtarget->hasSSE1())
1340 } else if (!MemcpyStrSrc && Size >= 8 &&
1341 !Subtarget->is64Bit() &&
1342 Subtarget->getStackAlignment() >= 8 &&
1343 Subtarget->hasSSE2()) {
1344 // Do not use f64 to lower memcpy if source is string constant. It's
1345 // better to use i32 to avoid the loads.
1349 if (Subtarget->is64Bit() && Size >= 8)
1354 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1355 /// current function. The returned value is a member of the
1356 /// MachineJumpTableInfo::JTEntryKind enum.
1357 unsigned X86TargetLowering::getJumpTableEncoding() const {
1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1361 Subtarget->isPICStyleGOT())
1362 return MachineJumpTableInfo::EK_Custom32;
1364 // Otherwise, use the normal jump table encoding heuristics.
1365 return TargetLowering::getJumpTableEncoding();
1369 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1370 const MachineBasicBlock *MBB,
1371 unsigned uid,MCContext &Ctx) const{
1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1373 Subtarget->isPICStyleGOT());
1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1376 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1377 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1380 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1382 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1383 SelectionDAG &DAG) const {
1384 if (!Subtarget->is64Bit())
1385 // This doesn't have DebugLoc associated with it, but is not really the
1386 // same as a Register.
1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1391 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1392 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1394 const MCExpr *X86TargetLowering::
1395 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1396 MCContext &Ctx) const {
1397 // X86-64 uses RIP relative addressing based on the jump table label.
1398 if (Subtarget->isPICStyleRIPRel())
1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1401 // Otherwise, the reference is relative to the PIC base.
1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1405 // FIXME: Why this routine is here? Move to RegInfo!
1406 std::pair<const TargetRegisterClass*, uint8_t>
1407 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1408 const TargetRegisterClass *RRC = 0;
1410 switch (VT.getSimpleVT().SimpleTy) {
1412 return TargetLowering::findRepresentativeClass(VT);
1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1414 RRC = (Subtarget->is64Bit()
1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1418 RRC = X86::VR64RegisterClass;
1420 case MVT::f32: case MVT::f64:
1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1422 case MVT::v4f32: case MVT::v2f64:
1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1425 RRC = X86::VR128RegisterClass;
1428 return std::make_pair(RRC, Cost);
1431 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1432 unsigned &Offset) const {
1433 if (!Subtarget->isTargetLinux())
1436 if (Subtarget->is64Bit()) {
1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1452 //===----------------------------------------------------------------------===//
1453 // Return Value Calling Convention Implementation
1454 //===----------------------------------------------------------------------===//
1456 #include "X86GenCallingConv.inc"
1459 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1460 MachineFunction &MF, bool isVarArg,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 LLVMContext &Context) const {
1463 SmallVector<CCValAssign, 16> RVLocs;
1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1466 return CCInfo.CheckReturn(Outs, RetCC_X86);
1470 X86TargetLowering::LowerReturn(SDValue Chain,
1471 CallingConv::ID CallConv, bool isVarArg,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 DebugLoc dl, SelectionDAG &DAG) const {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1480 RVLocs, *DAG.getContext());
1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1483 // Add the regs to the liveout set for the function.
1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1485 for (unsigned i = 0; i != RVLocs.size(); ++i)
1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1487 MRI.addLiveOut(RVLocs[i].getLocReg());
1491 SmallVector<SDValue, 6> RetOps;
1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1493 // Operand #1 = Bytes To Pop
1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1497 // Copy the result values into the output registers.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1501 SDValue ValToCopy = OutVals[i];
1502 EVT ValVT = ValToCopy.getValueType();
1504 // If this is x86-64, and we disabled SSE, we can't return FP values,
1505 // or SSE or MMX vectors.
1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1509 report_fatal_error("SSE register return with SSE disabled");
1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1512 // llvm-gcc has never done it right and no one has noticed, so this
1513 // should be OK for now.
1514 if (ValVT == MVT::f64 &&
1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1516 report_fatal_error("SSE2 register return with SSE2 disabled");
1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1519 // the RET instruction and handled by the FP Stackifier.
1520 if (VA.getLocReg() == X86::ST0 ||
1521 VA.getLocReg() == X86::ST1) {
1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1523 // change the value to the FP stack register class.
1524 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1526 RetOps.push_back(ValToCopy);
1527 // Don't emit a copytoreg.
1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1532 // which is returned in RAX / RDX.
1533 if (Subtarget->is64Bit()) {
1534 if (ValVT == MVT::x86mmx) {
1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1539 // If we don't have SSE2 available, convert to v4f32 so the generated
1540 // register is legal.
1541 if (!Subtarget->hasSSE2())
1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1548 Flag = Chain.getValue(1);
1551 // The x86-64 ABI for returning structs by value requires that we copy
1552 // the sret argument into %rax for the return. We saved the argument into
1553 // a virtual register in the entry block, so now we copy the value out
1555 if (Subtarget->is64Bit() &&
1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1559 unsigned Reg = FuncInfo->getSRetReturnReg();
1561 "SRetReturnReg should have been set in LowerFormalArguments().");
1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1565 Flag = Chain.getValue(1);
1567 // RAX now acts like a return value.
1568 MRI.addLiveOut(X86::RAX);
1571 RetOps[0] = Chain; // Update chain.
1573 // Add the flag if we have it.
1575 RetOps.push_back(Flag);
1577 return DAG.getNode(X86ISD::RET_FLAG, dl,
1578 MVT::Other, &RetOps[0], RetOps.size());
1581 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1582 if (N->getNumValues() != 1)
1584 if (!N->hasNUsesOfValue(1, 0))
1587 SDNode *Copy = *N->use_begin();
1588 if (Copy->getOpcode() == ISD::CopyToReg) {
1589 // If the copy has a glue operand, we conservatively assume it isn't safe to
1590 // perform a tail call.
1591 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1593 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1596 bool HasRet = false;
1597 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1599 if (UI->getOpcode() != X86ISD::RET_FLAG)
1608 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1609 ISD::NodeType ExtendKind) const {
1611 // TODO: Is this also valid on 32-bit?
1612 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1613 ReturnMVT = MVT::i8;
1615 ReturnMVT = MVT::i32;
1617 EVT MinVT = getRegisterType(Context, ReturnMVT);
1618 return VT.bitsLT(MinVT) ? MinVT : VT;
1621 /// LowerCallResult - Lower the result values of a call into the
1622 /// appropriate copies out of appropriate physical registers.
1625 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1626 CallingConv::ID CallConv, bool isVarArg,
1627 const SmallVectorImpl<ISD::InputArg> &Ins,
1628 DebugLoc dl, SelectionDAG &DAG,
1629 SmallVectorImpl<SDValue> &InVals) const {
1631 // Assign locations to each value returned by this call.
1632 SmallVector<CCValAssign, 16> RVLocs;
1633 bool Is64Bit = Subtarget->is64Bit();
1634 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1635 getTargetMachine(), RVLocs, *DAG.getContext());
1636 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1638 // Copy all of the result registers out of their specified physreg.
1639 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1640 CCValAssign &VA = RVLocs[i];
1641 EVT CopyVT = VA.getValVT();
1643 // If this is x86-64, and we disabled SSE, we can't return FP values
1644 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1645 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1646 report_fatal_error("SSE register return with SSE disabled");
1651 // If this is a call to a function that returns an fp value on the floating
1652 // point stack, we must guarantee the the value is popped from the stack, so
1653 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1654 // if the return value is not used. We use the FpPOP_RETVAL instruction
1656 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1657 // If we prefer to use the value in xmm registers, copy it out as f80 and
1658 // use a truncate to move it from fp stack reg to xmm reg.
1659 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1660 SDValue Ops[] = { Chain, InFlag };
1661 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1662 MVT::Other, MVT::Glue, Ops, 2), 1);
1663 Val = Chain.getValue(0);
1665 // Round the f80 to the right size, which also moves it to the appropriate
1667 if (CopyVT != VA.getValVT())
1668 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1669 // This truncation won't change the value.
1670 DAG.getIntPtrConstant(1));
1672 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1673 CopyVT, InFlag).getValue(1);
1674 Val = Chain.getValue(0);
1676 InFlag = Chain.getValue(2);
1677 InVals.push_back(Val);
1684 //===----------------------------------------------------------------------===//
1685 // C & StdCall & Fast Calling Convention implementation
1686 //===----------------------------------------------------------------------===//
1687 // StdCall calling convention seems to be standard for many Windows' API
1688 // routines and around. It differs from C calling convention just a little:
1689 // callee should clean up the stack, not caller. Symbols should be also
1690 // decorated in some fancy way :) It doesn't support any vector arguments.
1691 // For info on fast calling convention see Fast Calling Convention (tail call)
1692 // implementation LowerX86_32FastCCCallTo.
1694 /// CallIsStructReturn - Determines whether a call uses struct return
1696 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1700 return Outs[0].Flags.isSRet();
1703 /// ArgsAreStructReturn - Determines whether a function uses struct
1704 /// return semantics.
1706 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1710 return Ins[0].Flags.isSRet();
1713 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1714 /// by "Src" to address "Dst" with size and alignment information specified by
1715 /// the specific parameter attribute. The copy will be passed as a byval
1716 /// function parameter.
1718 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1719 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1721 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1723 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1724 /*isVolatile*/false, /*AlwaysInline=*/true,
1725 MachinePointerInfo(), MachinePointerInfo());
1728 /// IsTailCallConvention - Return true if the calling convention is one that
1729 /// supports tail call optimization.
1730 static bool IsTailCallConvention(CallingConv::ID CC) {
1731 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1734 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1735 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1739 CallingConv::ID CalleeCC = CS.getCallingConv();
1740 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1746 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1747 /// a tailcall target by changing its ABI.
1748 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1749 bool GuaranteedTailCallOpt) {
1750 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1754 X86TargetLowering::LowerMemArgument(SDValue Chain,
1755 CallingConv::ID CallConv,
1756 const SmallVectorImpl<ISD::InputArg> &Ins,
1757 DebugLoc dl, SelectionDAG &DAG,
1758 const CCValAssign &VA,
1759 MachineFrameInfo *MFI,
1761 // Create the nodes corresponding to a load from this parameter slot.
1762 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1763 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1764 getTargetMachine().Options.GuaranteedTailCallOpt);
1765 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1768 // If value is passed by pointer we have address passed instead of the value
1770 if (VA.getLocInfo() == CCValAssign::Indirect)
1771 ValVT = VA.getLocVT();
1773 ValVT = VA.getValVT();
1775 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1776 // changed with more analysis.
1777 // In case of tail call optimization mark all arguments mutable. Since they
1778 // could be overwritten by lowering of arguments in case of a tail call.
1779 if (Flags.isByVal()) {
1780 unsigned Bytes = Flags.getByValSize();
1781 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1782 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1783 return DAG.getFrameIndex(FI, getPointerTy());
1785 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1786 VA.getLocMemOffset(), isImmutable);
1787 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1788 return DAG.getLoad(ValVT, dl, Chain, FIN,
1789 MachinePointerInfo::getFixedStack(FI),
1790 false, false, false, 0);
1795 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1796 CallingConv::ID CallConv,
1798 const SmallVectorImpl<ISD::InputArg> &Ins,
1801 SmallVectorImpl<SDValue> &InVals)
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1806 const Function* Fn = MF.getFunction();
1807 if (Fn->hasExternalLinkage() &&
1808 Subtarget->isTargetCygMing() &&
1809 Fn->getName() == "main")
1810 FuncInfo->setForceFramePointer(true);
1812 MachineFrameInfo *MFI = MF.getFrameInfo();
1813 bool Is64Bit = Subtarget->is64Bit();
1814 bool IsWindows = Subtarget->isTargetWindows();
1815 bool IsWin64 = Subtarget->isTargetWin64();
1817 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1818 "Var args not supported with calling convention fastcc or ghc");
1820 // Assign locations to all of the incoming arguments.
1821 SmallVector<CCValAssign, 16> ArgLocs;
1822 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1823 ArgLocs, *DAG.getContext());
1825 // Allocate shadow area for Win64
1827 CCInfo.AllocateStack(32, 8);
1830 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1832 unsigned LastVal = ~0U;
1834 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1835 CCValAssign &VA = ArgLocs[i];
1836 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1838 assert(VA.getValNo() != LastVal &&
1839 "Don't support value assigned to multiple locs yet");
1841 LastVal = VA.getValNo();
1843 if (VA.isRegLoc()) {
1844 EVT RegVT = VA.getLocVT();
1845 const TargetRegisterClass *RC;
1846 if (RegVT == MVT::i32)
1847 RC = X86::GR32RegisterClass;
1848 else if (Is64Bit && RegVT == MVT::i64)
1849 RC = X86::GR64RegisterClass;
1850 else if (RegVT == MVT::f32)
1851 RC = X86::FR32RegisterClass;
1852 else if (RegVT == MVT::f64)
1853 RC = X86::FR64RegisterClass;
1854 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1855 RC = X86::VR256RegisterClass;
1856 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1857 RC = X86::VR128RegisterClass;
1858 else if (RegVT == MVT::x86mmx)
1859 RC = X86::VR64RegisterClass;
1861 llvm_unreachable("Unknown argument type!");
1863 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1864 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1866 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1867 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1869 if (VA.getLocInfo() == CCValAssign::SExt)
1870 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1871 DAG.getValueType(VA.getValVT()));
1872 else if (VA.getLocInfo() == CCValAssign::ZExt)
1873 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1874 DAG.getValueType(VA.getValVT()));
1875 else if (VA.getLocInfo() == CCValAssign::BCvt)
1876 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1878 if (VA.isExtInLoc()) {
1879 // Handle MMX values passed in XMM regs.
1880 if (RegVT.isVector()) {
1881 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1884 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1887 assert(VA.isMemLoc());
1888 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1891 // If value is passed via pointer - do a load.
1892 if (VA.getLocInfo() == CCValAssign::Indirect)
1893 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1894 MachinePointerInfo(), false, false, false, 0);
1896 InVals.push_back(ArgValue);
1899 // The x86-64 ABI for returning structs by value requires that we copy
1900 // the sret argument into %rax for the return. Save the argument into
1901 // a virtual register so that we can access it from the return points.
1902 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1903 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1904 unsigned Reg = FuncInfo->getSRetReturnReg();
1906 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1907 FuncInfo->setSRetReturnReg(Reg);
1909 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1910 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1913 unsigned StackSize = CCInfo.getNextStackOffset();
1914 // Align stack specially for tail calls.
1915 if (FuncIsMadeTailCallSafe(CallConv,
1916 MF.getTarget().Options.GuaranteedTailCallOpt))
1917 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1919 // If the function takes variable number of arguments, make a frame index for
1920 // the start of the first vararg value... for expansion of llvm.va_start.
1922 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1923 CallConv != CallingConv::X86_ThisCall)) {
1924 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1927 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1929 // FIXME: We should really autogenerate these arrays
1930 static const uint16_t GPR64ArgRegsWin64[] = {
1931 X86::RCX, X86::RDX, X86::R8, X86::R9
1933 static const uint16_t GPR64ArgRegs64Bit[] = {
1934 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1936 static const uint16_t XMMArgRegs64Bit[] = {
1937 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1938 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1940 const uint16_t *GPR64ArgRegs;
1941 unsigned NumXMMRegs = 0;
1944 // The XMM registers which might contain var arg parameters are shadowed
1945 // in their paired GPR. So we only need to save the GPR to their home
1947 TotalNumIntRegs = 4;
1948 GPR64ArgRegs = GPR64ArgRegsWin64;
1950 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1951 GPR64ArgRegs = GPR64ArgRegs64Bit;
1953 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1956 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1959 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1960 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1961 "SSE register cannot be used when SSE is disabled!");
1962 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1963 NoImplicitFloatOps) &&
1964 "SSE register cannot be used when SSE is disabled!");
1965 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1966 !Subtarget->hasSSE1())
1967 // Kernel mode asks for SSE to be disabled, so don't push them
1969 TotalNumXMMRegs = 0;
1972 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1973 // Get to the caller-allocated home save location. Add 8 to account
1974 // for the return address.
1975 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1976 FuncInfo->setRegSaveFrameIndex(
1977 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1978 // Fixup to set vararg frame on shadow area (4 x i64).
1980 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1982 // For X86-64, if there are vararg parameters that are passed via
1983 // registers, then we must store them to their spots on the stack so
1984 // they may be loaded by deferencing the result of va_next.
1985 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1986 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1987 FuncInfo->setRegSaveFrameIndex(
1988 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1992 // Store the integer parameter registers.
1993 SmallVector<SDValue, 8> MemOps;
1994 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1996 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1997 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1998 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1999 DAG.getIntPtrConstant(Offset));
2000 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2001 X86::GR64RegisterClass);
2002 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2004 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2005 MachinePointerInfo::getFixedStack(
2006 FuncInfo->getRegSaveFrameIndex(), Offset),
2008 MemOps.push_back(Store);
2012 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2013 // Now store the XMM (fp + vector) parameter registers.
2014 SmallVector<SDValue, 11> SaveXMMOps;
2015 SaveXMMOps.push_back(Chain);
2017 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2018 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2019 SaveXMMOps.push_back(ALVal);
2021 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2022 FuncInfo->getRegSaveFrameIndex()));
2023 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2024 FuncInfo->getVarArgsFPOffset()));
2026 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2027 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2028 X86::VR128RegisterClass);
2029 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2030 SaveXMMOps.push_back(Val);
2032 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2034 &SaveXMMOps[0], SaveXMMOps.size()));
2037 if (!MemOps.empty())
2038 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2039 &MemOps[0], MemOps.size());
2043 // Some CCs need callee pop.
2044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2045 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2046 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2048 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2049 // If this is an sret function, the return should pop the hidden pointer.
2050 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2051 ArgsAreStructReturn(Ins))
2052 FuncInfo->setBytesToPopOnReturn(4);
2056 // RegSaveFrameIndex is X86-64 only.
2057 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2058 if (CallConv == CallingConv::X86_FastCall ||
2059 CallConv == CallingConv::X86_ThisCall)
2060 // fastcc functions can't have varargs.
2061 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2064 FuncInfo->setArgumentStackSize(StackSize);
2070 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2071 SDValue StackPtr, SDValue Arg,
2072 DebugLoc dl, SelectionDAG &DAG,
2073 const CCValAssign &VA,
2074 ISD::ArgFlagsTy Flags) const {
2075 unsigned LocMemOffset = VA.getLocMemOffset();
2076 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2077 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2078 if (Flags.isByVal())
2079 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2081 return DAG.getStore(Chain, dl, Arg, PtrOff,
2082 MachinePointerInfo::getStack(LocMemOffset),
2086 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2087 /// optimization is performed and it is required.
2089 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2090 SDValue &OutRetAddr, SDValue Chain,
2091 bool IsTailCall, bool Is64Bit,
2092 int FPDiff, DebugLoc dl) const {
2093 // Adjust the Return address stack slot.
2094 EVT VT = getPointerTy();
2095 OutRetAddr = getReturnAddressFrameIndex(DAG);
2097 // Load the "old" Return address.
2098 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2099 false, false, false, 0);
2100 return SDValue(OutRetAddr.getNode(), 1);
2103 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2104 /// optimization is performed and it is required (FPDiff!=0).
2106 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2107 SDValue Chain, SDValue RetAddrFrIdx,
2108 bool Is64Bit, int FPDiff, DebugLoc dl) {
2109 // Store the return address to the appropriate stack slot.
2110 if (!FPDiff) return Chain;
2111 // Calculate the new stack slot for the return address.
2112 int SlotSize = Is64Bit ? 8 : 4;
2113 int NewReturnAddrFI =
2114 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2115 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2116 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2117 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2118 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2124 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2125 CallingConv::ID CallConv, bool isVarArg,
2126 bool doesNotRet, bool &isTailCall,
2127 const SmallVectorImpl<ISD::OutputArg> &Outs,
2128 const SmallVectorImpl<SDValue> &OutVals,
2129 const SmallVectorImpl<ISD::InputArg> &Ins,
2130 DebugLoc dl, SelectionDAG &DAG,
2131 SmallVectorImpl<SDValue> &InVals) const {
2132 MachineFunction &MF = DAG.getMachineFunction();
2133 bool Is64Bit = Subtarget->is64Bit();
2134 bool IsWin64 = Subtarget->isTargetWin64();
2135 bool IsWindows = Subtarget->isTargetWindows();
2136 bool IsStructRet = CallIsStructReturn(Outs);
2137 bool IsSibcall = false;
2139 if (MF.getTarget().Options.DisableTailCalls)
2143 // Check if it's really possible to do a tail call.
2144 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2145 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2146 Outs, OutVals, Ins, DAG);
2148 // Sibcalls are automatically detected tailcalls which do not require
2150 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2157 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2158 "Var args not supported with calling convention fastcc or ghc");
2160 // Analyze operands of the call, assigning locations to each operand.
2161 SmallVector<CCValAssign, 16> ArgLocs;
2162 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2163 ArgLocs, *DAG.getContext());
2165 // Allocate shadow area for Win64
2167 CCInfo.AllocateStack(32, 8);
2170 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2172 // Get a count of how many bytes are to be pushed on the stack.
2173 unsigned NumBytes = CCInfo.getNextStackOffset();
2175 // This is a sibcall. The memory operands are available in caller's
2176 // own caller's stack.
2178 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2179 IsTailCallConvention(CallConv))
2180 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2183 if (isTailCall && !IsSibcall) {
2184 // Lower arguments at fp - stackoffset + fpdiff.
2185 unsigned NumBytesCallerPushed =
2186 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2187 FPDiff = NumBytesCallerPushed - NumBytes;
2189 // Set the delta of movement of the returnaddr stackslot.
2190 // But only set if delta is greater than previous delta.
2191 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2192 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2196 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2198 SDValue RetAddrFrIdx;
2199 // Load return address for tail calls.
2200 if (isTailCall && FPDiff)
2201 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2202 Is64Bit, FPDiff, dl);
2204 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2205 SmallVector<SDValue, 8> MemOpChains;
2208 // Walk the register/memloc assignments, inserting copies/loads. In the case
2209 // of tail call optimization arguments are handle later.
2210 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2211 CCValAssign &VA = ArgLocs[i];
2212 EVT RegVT = VA.getLocVT();
2213 SDValue Arg = OutVals[i];
2214 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2215 bool isByVal = Flags.isByVal();
2217 // Promote the value if needed.
2218 switch (VA.getLocInfo()) {
2219 default: llvm_unreachable("Unknown loc info!");
2220 case CCValAssign::Full: break;
2221 case CCValAssign::SExt:
2222 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2224 case CCValAssign::ZExt:
2225 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2227 case CCValAssign::AExt:
2228 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2229 // Special case: passing MMX values in XMM registers.
2230 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2231 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2232 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2234 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2236 case CCValAssign::BCvt:
2237 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2239 case CCValAssign::Indirect: {
2240 // Store the argument.
2241 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2242 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2243 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2244 MachinePointerInfo::getFixedStack(FI),
2251 if (VA.isRegLoc()) {
2252 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2253 if (isVarArg && IsWin64) {
2254 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2255 // shadow reg if callee is a varargs function.
2256 unsigned ShadowReg = 0;
2257 switch (VA.getLocReg()) {
2258 case X86::XMM0: ShadowReg = X86::RCX; break;
2259 case X86::XMM1: ShadowReg = X86::RDX; break;
2260 case X86::XMM2: ShadowReg = X86::R8; break;
2261 case X86::XMM3: ShadowReg = X86::R9; break;
2264 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2266 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2267 assert(VA.isMemLoc());
2268 if (StackPtr.getNode() == 0)
2269 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2270 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2271 dl, DAG, VA, Flags));
2275 if (!MemOpChains.empty())
2276 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2277 &MemOpChains[0], MemOpChains.size());
2279 // Build a sequence of copy-to-reg nodes chained together with token chain
2280 // and flag operands which copy the outgoing args into registers.
2282 // Tail call byval lowering might overwrite argument registers so in case of
2283 // tail call optimization the copies to registers are lowered later.
2285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2287 RegsToPass[i].second, InFlag);
2288 InFlag = Chain.getValue(1);
2291 if (Subtarget->isPICStyleGOT()) {
2292 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2295 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2296 DAG.getNode(X86ISD::GlobalBaseReg,
2297 DebugLoc(), getPointerTy()),
2299 InFlag = Chain.getValue(1);
2301 // If we are tail calling and generating PIC/GOT style code load the
2302 // address of the callee into ECX. The value in ecx is used as target of
2303 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2304 // for tail calls on PIC/GOT architectures. Normally we would just put the
2305 // address of GOT into ebx and then call target@PLT. But for tail calls
2306 // ebx would be restored (since ebx is callee saved) before jumping to the
2309 // Note: The actual moving to ECX is done further down.
2310 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2311 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2312 !G->getGlobal()->hasProtectedVisibility())
2313 Callee = LowerGlobalAddress(Callee, DAG);
2314 else if (isa<ExternalSymbolSDNode>(Callee))
2315 Callee = LowerExternalSymbol(Callee, DAG);
2319 if (Is64Bit && isVarArg && !IsWin64) {
2320 // From AMD64 ABI document:
2321 // For calls that may call functions that use varargs or stdargs
2322 // (prototype-less calls or calls to functions containing ellipsis (...) in
2323 // the declaration) %al is used as hidden argument to specify the number
2324 // of SSE registers used. The contents of %al do not need to match exactly
2325 // the number of registers, but must be an ubound on the number of SSE
2326 // registers used and is in the range 0 - 8 inclusive.
2328 // Count the number of XMM registers allocated.
2329 static const uint16_t XMMArgRegs[] = {
2330 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2331 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2333 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2334 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2335 && "SSE registers cannot be used when SSE is disabled");
2337 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2338 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2339 InFlag = Chain.getValue(1);
2343 // For tail calls lower the arguments to the 'real' stack slot.
2345 // Force all the incoming stack arguments to be loaded from the stack
2346 // before any new outgoing arguments are stored to the stack, because the
2347 // outgoing stack slots may alias the incoming argument stack slots, and
2348 // the alias isn't otherwise explicit. This is slightly more conservative
2349 // than necessary, because it means that each store effectively depends
2350 // on every argument instead of just those arguments it would clobber.
2351 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2353 SmallVector<SDValue, 8> MemOpChains2;
2356 // Do not flag preceding copytoreg stuff together with the following stuff.
2358 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2360 CCValAssign &VA = ArgLocs[i];
2363 assert(VA.isMemLoc());
2364 SDValue Arg = OutVals[i];
2365 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2366 // Create frame index.
2367 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2368 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2369 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2370 FIN = DAG.getFrameIndex(FI, getPointerTy());
2372 if (Flags.isByVal()) {
2373 // Copy relative to framepointer.
2374 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2375 if (StackPtr.getNode() == 0)
2376 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2378 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2380 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2384 // Store relative to framepointer.
2385 MemOpChains2.push_back(
2386 DAG.getStore(ArgChain, dl, Arg, FIN,
2387 MachinePointerInfo::getFixedStack(FI),
2393 if (!MemOpChains2.empty())
2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2395 &MemOpChains2[0], MemOpChains2.size());
2397 // Copy arguments to their registers.
2398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2399 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2400 RegsToPass[i].second, InFlag);
2401 InFlag = Chain.getValue(1);
2405 // Store the return address to the appropriate stack slot.
2406 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2410 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2411 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2412 // In the 64-bit large code model, we have to make all calls
2413 // through a register, since the call instruction's 32-bit
2414 // pc-relative offset may not be large enough to hold the whole
2416 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2417 // If the callee is a GlobalAddress node (quite common, every direct call
2418 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2421 // We should use extra load for direct calls to dllimported functions in
2423 const GlobalValue *GV = G->getGlobal();
2424 if (!GV->hasDLLImportLinkage()) {
2425 unsigned char OpFlags = 0;
2426 bool ExtraLoad = false;
2427 unsigned WrapperKind = ISD::DELETED_NODE;
2429 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2430 // external symbols most go through the PLT in PIC mode. If the symbol
2431 // has hidden or protected visibility, or if it is static or local, then
2432 // we don't need to use the PLT - we can directly call it.
2433 if (Subtarget->isTargetELF() &&
2434 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2435 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2436 OpFlags = X86II::MO_PLT;
2437 } else if (Subtarget->isPICStyleStubAny() &&
2438 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2439 (!Subtarget->getTargetTriple().isMacOSX() ||
2440 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2441 // PC-relative references to external symbols should go through $stub,
2442 // unless we're building with the leopard linker or later, which
2443 // automatically synthesizes these stubs.
2444 OpFlags = X86II::MO_DARWIN_STUB;
2445 } else if (Subtarget->isPICStyleRIPRel() &&
2446 isa<Function>(GV) &&
2447 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2448 // If the function is marked as non-lazy, generate an indirect call
2449 // which loads from the GOT directly. This avoids runtime overhead
2450 // at the cost of eager binding (and one extra byte of encoding).
2451 OpFlags = X86II::MO_GOTPCREL;
2452 WrapperKind = X86ISD::WrapperRIP;
2456 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2457 G->getOffset(), OpFlags);
2459 // Add a wrapper if needed.
2460 if (WrapperKind != ISD::DELETED_NODE)
2461 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2462 // Add extra indirection if needed.
2464 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2465 MachinePointerInfo::getGOT(),
2466 false, false, false, 0);
2468 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2469 unsigned char OpFlags = 0;
2471 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2472 // external symbols should go through the PLT.
2473 if (Subtarget->isTargetELF() &&
2474 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2475 OpFlags = X86II::MO_PLT;
2476 } else if (Subtarget->isPICStyleStubAny() &&
2477 (!Subtarget->getTargetTriple().isMacOSX() ||
2478 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2479 // PC-relative references to external symbols should go through $stub,
2480 // unless we're building with the leopard linker or later, which
2481 // automatically synthesizes these stubs.
2482 OpFlags = X86II::MO_DARWIN_STUB;
2485 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2489 // Returns a chain & a flag for retval copy to use.
2490 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2491 SmallVector<SDValue, 8> Ops;
2493 if (!IsSibcall && isTailCall) {
2494 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2495 DAG.getIntPtrConstant(0, true), InFlag);
2496 InFlag = Chain.getValue(1);
2499 Ops.push_back(Chain);
2500 Ops.push_back(Callee);
2503 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2505 // Add argument registers to the end of the list so that they are known live
2507 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2508 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2509 RegsToPass[i].second.getValueType()));
2511 // Add an implicit use GOT pointer in EBX.
2512 if (!isTailCall && Subtarget->isPICStyleGOT())
2513 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2515 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2516 if (Is64Bit && isVarArg && !IsWin64)
2517 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2519 // Add a register mask operand representing the call-preserved registers.
2520 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2521 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2522 assert(Mask && "Missing call preserved mask for calling convention");
2523 Ops.push_back(DAG.getRegisterMask(Mask));
2525 if (InFlag.getNode())
2526 Ops.push_back(InFlag);
2530 //// If this is the first return lowered for this function, add the regs
2531 //// to the liveout set for the function.
2532 // This isn't right, although it's probably harmless on x86; liveouts
2533 // should be computed from returns not tail calls. Consider a void
2534 // function making a tail call to a function returning int.
2535 return DAG.getNode(X86ISD::TC_RETURN, dl,
2536 NodeTys, &Ops[0], Ops.size());
2539 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2540 InFlag = Chain.getValue(1);
2542 // Create the CALLSEQ_END node.
2543 unsigned NumBytesForCalleeToPush;
2544 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2545 getTargetMachine().Options.GuaranteedTailCallOpt))
2546 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2547 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2549 // If this is a call to a struct-return function, the callee
2550 // pops the hidden struct pointer, so we have to push it back.
2551 // This is common for Darwin/X86, Linux & Mingw32 targets.
2552 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2553 NumBytesForCalleeToPush = 4;
2555 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2557 // Returns a flag for retval copy to use.
2559 Chain = DAG.getCALLSEQ_END(Chain,
2560 DAG.getIntPtrConstant(NumBytes, true),
2561 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2564 InFlag = Chain.getValue(1);
2567 // Handle result values, copying them out of physregs into vregs that we
2569 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2570 Ins, dl, DAG, InVals);
2574 //===----------------------------------------------------------------------===//
2575 // Fast Calling Convention (tail call) implementation
2576 //===----------------------------------------------------------------------===//
2578 // Like std call, callee cleans arguments, convention except that ECX is
2579 // reserved for storing the tail called function address. Only 2 registers are
2580 // free for argument passing (inreg). Tail call optimization is performed
2582 // * tailcallopt is enabled
2583 // * caller/callee are fastcc
2584 // On X86_64 architecture with GOT-style position independent code only local
2585 // (within module) calls are supported at the moment.
2586 // To keep the stack aligned according to platform abi the function
2587 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2588 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2589 // If a tail called function callee has more arguments than the caller the
2590 // caller needs to make sure that there is room to move the RETADDR to. This is
2591 // achieved by reserving an area the size of the argument delta right after the
2592 // original REtADDR, but before the saved framepointer or the spilled registers
2593 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2605 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2606 /// for a 16 byte align requirement.
2608 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2609 SelectionDAG& DAG) const {
2610 MachineFunction &MF = DAG.getMachineFunction();
2611 const TargetMachine &TM = MF.getTarget();
2612 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2613 unsigned StackAlignment = TFI.getStackAlignment();
2614 uint64_t AlignMask = StackAlignment - 1;
2615 int64_t Offset = StackSize;
2616 uint64_t SlotSize = TD->getPointerSize();
2617 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2618 // Number smaller than 12 so just add the difference.
2619 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2621 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2622 Offset = ((~AlignMask) & Offset) + StackAlignment +
2623 (StackAlignment-SlotSize);
2628 /// MatchingStackOffset - Return true if the given stack call argument is
2629 /// already available in the same position (relatively) of the caller's
2630 /// incoming argument stack.
2632 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2633 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2634 const X86InstrInfo *TII) {
2635 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2637 if (Arg.getOpcode() == ISD::CopyFromReg) {
2638 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2639 if (!TargetRegisterInfo::isVirtualRegister(VR))
2641 MachineInstr *Def = MRI->getVRegDef(VR);
2644 if (!Flags.isByVal()) {
2645 if (!TII->isLoadFromStackSlot(Def, FI))
2648 unsigned Opcode = Def->getOpcode();
2649 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2650 Def->getOperand(1).isFI()) {
2651 FI = Def->getOperand(1).getIndex();
2652 Bytes = Flags.getByValSize();
2656 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2657 if (Flags.isByVal())
2658 // ByVal argument is passed in as a pointer but it's now being
2659 // dereferenced. e.g.
2660 // define @foo(%struct.X* %A) {
2661 // tail call @bar(%struct.X* byval %A)
2664 SDValue Ptr = Ld->getBasePtr();
2665 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2668 FI = FINode->getIndex();
2669 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2670 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2671 FI = FINode->getIndex();
2672 Bytes = Flags.getByValSize();
2676 assert(FI != INT_MAX);
2677 if (!MFI->isFixedObjectIndex(FI))
2679 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2682 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2683 /// for tail call optimization. Targets which want to do tail call
2684 /// optimization should implement this function.
2686 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2687 CallingConv::ID CalleeCC,
2689 bool isCalleeStructRet,
2690 bool isCallerStructRet,
2691 const SmallVectorImpl<ISD::OutputArg> &Outs,
2692 const SmallVectorImpl<SDValue> &OutVals,
2693 const SmallVectorImpl<ISD::InputArg> &Ins,
2694 SelectionDAG& DAG) const {
2695 if (!IsTailCallConvention(CalleeCC) &&
2696 CalleeCC != CallingConv::C)
2699 // If -tailcallopt is specified, make fastcc functions tail-callable.
2700 const MachineFunction &MF = DAG.getMachineFunction();
2701 const Function *CallerF = DAG.getMachineFunction().getFunction();
2702 CallingConv::ID CallerCC = CallerF->getCallingConv();
2703 bool CCMatch = CallerCC == CalleeCC;
2705 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2706 if (IsTailCallConvention(CalleeCC) && CCMatch)
2711 // Look for obvious safe cases to perform tail call optimization that do not
2712 // require ABI changes. This is what gcc calls sibcall.
2714 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2715 // emit a special epilogue.
2716 if (RegInfo->needsStackRealignment(MF))
2719 // Also avoid sibcall optimization if either caller or callee uses struct
2720 // return semantics.
2721 if (isCalleeStructRet || isCallerStructRet)
2724 // An stdcall caller is expected to clean up its arguments; the callee
2725 // isn't going to do that.
2726 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2729 // Do not sibcall optimize vararg calls unless all arguments are passed via
2731 if (isVarArg && !Outs.empty()) {
2733 // Optimizing for varargs on Win64 is unlikely to be safe without
2734 // additional testing.
2735 if (Subtarget->isTargetWin64())
2738 SmallVector<CCValAssign, 16> ArgLocs;
2739 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2740 getTargetMachine(), ArgLocs, *DAG.getContext());
2742 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2743 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2744 if (!ArgLocs[i].isRegLoc())
2748 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2749 // stack. Therefore, if it's not used by the call it is not safe to optimize
2750 // this into a sibcall.
2751 bool Unused = false;
2752 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2759 SmallVector<CCValAssign, 16> RVLocs;
2760 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2761 getTargetMachine(), RVLocs, *DAG.getContext());
2762 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2763 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2764 CCValAssign &VA = RVLocs[i];
2765 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2770 // If the calling conventions do not match, then we'd better make sure the
2771 // results are returned in the same way as what the caller expects.
2773 SmallVector<CCValAssign, 16> RVLocs1;
2774 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2775 getTargetMachine(), RVLocs1, *DAG.getContext());
2776 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2778 SmallVector<CCValAssign, 16> RVLocs2;
2779 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2780 getTargetMachine(), RVLocs2, *DAG.getContext());
2781 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2783 if (RVLocs1.size() != RVLocs2.size())
2785 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2786 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2788 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2790 if (RVLocs1[i].isRegLoc()) {
2791 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2794 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2800 // If the callee takes no arguments then go on to check the results of the
2802 if (!Outs.empty()) {
2803 // Check if stack adjustment is needed. For now, do not do this if any
2804 // argument is passed on the stack.
2805 SmallVector<CCValAssign, 16> ArgLocs;
2806 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2807 getTargetMachine(), ArgLocs, *DAG.getContext());
2809 // Allocate shadow area for Win64
2810 if (Subtarget->isTargetWin64()) {
2811 CCInfo.AllocateStack(32, 8);
2814 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2815 if (CCInfo.getNextStackOffset()) {
2816 MachineFunction &MF = DAG.getMachineFunction();
2817 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2820 // Check if the arguments are already laid out in the right way as
2821 // the caller's fixed stack objects.
2822 MachineFrameInfo *MFI = MF.getFrameInfo();
2823 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2824 const X86InstrInfo *TII =
2825 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2826 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2827 CCValAssign &VA = ArgLocs[i];
2828 SDValue Arg = OutVals[i];
2829 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2830 if (VA.getLocInfo() == CCValAssign::Indirect)
2832 if (!VA.isRegLoc()) {
2833 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2840 // If the tailcall address may be in a register, then make sure it's
2841 // possible to register allocate for it. In 32-bit, the call address can
2842 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2843 // callee-saved registers are restored. These happen to be the same
2844 // registers used to pass 'inreg' arguments so watch out for those.
2845 if (!Subtarget->is64Bit() &&
2846 !isa<GlobalAddressSDNode>(Callee) &&
2847 !isa<ExternalSymbolSDNode>(Callee)) {
2848 unsigned NumInRegs = 0;
2849 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2850 CCValAssign &VA = ArgLocs[i];
2853 unsigned Reg = VA.getLocReg();
2856 case X86::EAX: case X86::EDX: case X86::ECX:
2857 if (++NumInRegs == 3)
2869 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2870 return X86::createFastISel(funcInfo);
2874 //===----------------------------------------------------------------------===//
2875 // Other Lowering Hooks
2876 //===----------------------------------------------------------------------===//
2878 static bool MayFoldLoad(SDValue Op) {
2879 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2882 static bool MayFoldIntoStore(SDValue Op) {
2883 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2886 static bool isTargetShuffle(unsigned Opcode) {
2888 default: return false;
2889 case X86ISD::PSHUFD:
2890 case X86ISD::PSHUFHW:
2891 case X86ISD::PSHUFLW:
2893 case X86ISD::PALIGN:
2894 case X86ISD::MOVLHPS:
2895 case X86ISD::MOVLHPD:
2896 case X86ISD::MOVHLPS:
2897 case X86ISD::MOVLPS:
2898 case X86ISD::MOVLPD:
2899 case X86ISD::MOVSHDUP:
2900 case X86ISD::MOVSLDUP:
2901 case X86ISD::MOVDDUP:
2904 case X86ISD::UNPCKL:
2905 case X86ISD::UNPCKH:
2906 case X86ISD::VPERMILP:
2907 case X86ISD::VPERM2X128:
2912 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2913 SDValue V1, SelectionDAG &DAG) {
2915 default: llvm_unreachable("Unknown x86 shuffle node");
2916 case X86ISD::MOVSHDUP:
2917 case X86ISD::MOVSLDUP:
2918 case X86ISD::MOVDDUP:
2919 return DAG.getNode(Opc, dl, VT, V1);
2923 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2924 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2926 default: llvm_unreachable("Unknown x86 shuffle node");
2927 case X86ISD::PSHUFD:
2928 case X86ISD::PSHUFHW:
2929 case X86ISD::PSHUFLW:
2930 case X86ISD::VPERMILP:
2931 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2935 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2936 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2938 default: llvm_unreachable("Unknown x86 shuffle node");
2939 case X86ISD::PALIGN:
2941 case X86ISD::VPERM2X128:
2942 return DAG.getNode(Opc, dl, VT, V1, V2,
2943 DAG.getConstant(TargetMask, MVT::i8));
2947 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2948 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2950 default: llvm_unreachable("Unknown x86 shuffle node");
2951 case X86ISD::MOVLHPS:
2952 case X86ISD::MOVLHPD:
2953 case X86ISD::MOVHLPS:
2954 case X86ISD::MOVLPS:
2955 case X86ISD::MOVLPD:
2958 case X86ISD::UNPCKL:
2959 case X86ISD::UNPCKH:
2960 return DAG.getNode(Opc, dl, VT, V1, V2);
2964 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2965 MachineFunction &MF = DAG.getMachineFunction();
2966 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2967 int ReturnAddrIndex = FuncInfo->getRAIndex();
2969 if (ReturnAddrIndex == 0) {
2970 // Set up a frame object for the return address.
2971 uint64_t SlotSize = TD->getPointerSize();
2972 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2974 FuncInfo->setRAIndex(ReturnAddrIndex);
2977 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2981 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2982 bool hasSymbolicDisplacement) {
2983 // Offset should fit into 32 bit immediate field.
2984 if (!isInt<32>(Offset))
2987 // If we don't have a symbolic displacement - we don't have any extra
2989 if (!hasSymbolicDisplacement)
2992 // FIXME: Some tweaks might be needed for medium code model.
2993 if (M != CodeModel::Small && M != CodeModel::Kernel)
2996 // For small code model we assume that latest object is 16MB before end of 31
2997 // bits boundary. We may also accept pretty large negative constants knowing
2998 // that all objects are in the positive half of address space.
2999 if (M == CodeModel::Small && Offset < 16*1024*1024)
3002 // For kernel code model we know that all object resist in the negative half
3003 // of 32bits address space. We may not accept negative offsets, since they may
3004 // be just off and we may accept pretty large positive ones.
3005 if (M == CodeModel::Kernel && Offset > 0)
3011 /// isCalleePop - Determines whether the callee is required to pop its
3012 /// own arguments. Callee pop is necessary to support tail calls.
3013 bool X86::isCalleePop(CallingConv::ID CallingConv,
3014 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3018 switch (CallingConv) {
3021 case CallingConv::X86_StdCall:
3023 case CallingConv::X86_FastCall:
3025 case CallingConv::X86_ThisCall:
3027 case CallingConv::Fast:
3029 case CallingConv::GHC:
3034 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3035 /// specific condition code, returning the condition code and the LHS/RHS of the
3036 /// comparison to make.
3037 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3038 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3040 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3041 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3042 // X > -1 -> X == 0, jump !sign.
3043 RHS = DAG.getConstant(0, RHS.getValueType());
3044 return X86::COND_NS;
3045 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3046 // X < 0 -> X == 0, jump on sign.
3048 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3050 RHS = DAG.getConstant(0, RHS.getValueType());
3051 return X86::COND_LE;
3055 switch (SetCCOpcode) {
3056 default: llvm_unreachable("Invalid integer condition!");
3057 case ISD::SETEQ: return X86::COND_E;
3058 case ISD::SETGT: return X86::COND_G;
3059 case ISD::SETGE: return X86::COND_GE;
3060 case ISD::SETLT: return X86::COND_L;
3061 case ISD::SETLE: return X86::COND_LE;
3062 case ISD::SETNE: return X86::COND_NE;
3063 case ISD::SETULT: return X86::COND_B;
3064 case ISD::SETUGT: return X86::COND_A;
3065 case ISD::SETULE: return X86::COND_BE;
3066 case ISD::SETUGE: return X86::COND_AE;
3070 // First determine if it is required or is profitable to flip the operands.
3072 // If LHS is a foldable load, but RHS is not, flip the condition.
3073 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3074 !ISD::isNON_EXTLoad(RHS.getNode())) {
3075 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3076 std::swap(LHS, RHS);
3079 switch (SetCCOpcode) {
3085 std::swap(LHS, RHS);
3089 // On a floating point condition, the flags are set as follows:
3091 // 0 | 0 | 0 | X > Y
3092 // 0 | 0 | 1 | X < Y
3093 // 1 | 0 | 0 | X == Y
3094 // 1 | 1 | 1 | unordered
3095 switch (SetCCOpcode) {
3096 default: llvm_unreachable("Condcode should be pre-legalized away");
3098 case ISD::SETEQ: return X86::COND_E;
3099 case ISD::SETOLT: // flipped
3101 case ISD::SETGT: return X86::COND_A;
3102 case ISD::SETOLE: // flipped
3104 case ISD::SETGE: return X86::COND_AE;
3105 case ISD::SETUGT: // flipped
3107 case ISD::SETLT: return X86::COND_B;
3108 case ISD::SETUGE: // flipped
3110 case ISD::SETLE: return X86::COND_BE;
3112 case ISD::SETNE: return X86::COND_NE;
3113 case ISD::SETUO: return X86::COND_P;
3114 case ISD::SETO: return X86::COND_NP;
3116 case ISD::SETUNE: return X86::COND_INVALID;
3120 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3121 /// code. Current x86 isa includes the following FP cmov instructions:
3122 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3123 static bool hasFPCMov(unsigned X86CC) {
3139 /// isFPImmLegal - Returns true if the target can instruction select the
3140 /// specified FP immediate natively. If false, the legalizer will
3141 /// materialize the FP immediate as a load from a constant pool.
3142 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3143 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3144 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3150 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3151 /// the specified range (L, H].
3152 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3153 return (Val < 0) || (Val >= Low && Val < Hi);
3156 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3157 /// specified value.
3158 static bool isUndefOrEqual(int Val, int CmpVal) {
3159 if (Val < 0 || Val == CmpVal)
3164 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3165 /// from position Pos and ending in Pos+Size, falls within the specified
3166 /// sequential range (L, L+Pos]. or is undef.
3167 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3168 int Pos, int Size, int Low) {
3169 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3170 if (!isUndefOrEqual(Mask[i], Low))
3175 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3176 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3177 /// the second operand.
3178 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3179 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3180 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3181 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3182 return (Mask[0] < 2 && Mask[1] < 2);
3186 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3187 /// is suitable for input to PSHUFHW.
3188 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3189 if (VT != MVT::v8i16)
3192 // Lower quadword copied in order or undef.
3193 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3196 // Upper quadword shuffled.
3197 for (unsigned i = 4; i != 8; ++i)
3198 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3204 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3205 /// is suitable for input to PSHUFLW.
3206 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3207 if (VT != MVT::v8i16)
3210 // Upper quadword copied in order.
3211 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3214 // Lower quadword shuffled.
3215 for (unsigned i = 0; i != 4; ++i)
3222 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3223 /// is suitable for input to PALIGNR.
3224 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3225 const X86Subtarget *Subtarget) {
3226 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3227 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3230 unsigned NumElts = VT.getVectorNumElements();
3231 unsigned NumLanes = VT.getSizeInBits()/128;
3232 unsigned NumLaneElts = NumElts/NumLanes;
3234 // Do not handle 64-bit element shuffles with palignr.
3235 if (NumLaneElts == 2)
3238 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3240 for (i = 0; i != NumLaneElts; ++i) {
3245 // Lane is all undef, go to next lane
3246 if (i == NumLaneElts)
3249 int Start = Mask[i+l];
3251 // Make sure its in this lane in one of the sources
3252 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3253 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3256 // If not lane 0, then we must match lane 0
3257 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3260 // Correct second source to be contiguous with first source
3261 if (Start >= (int)NumElts)
3262 Start -= NumElts - NumLaneElts;
3264 // Make sure we're shifting in the right direction.
3265 if (Start <= (int)(i+l))
3270 // Check the rest of the elements to see if they are consecutive.
3271 for (++i; i != NumLaneElts; ++i) {
3272 int Idx = Mask[i+l];
3274 // Make sure its in this lane
3275 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3276 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3279 // If not lane 0, then we must match lane 0
3280 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3283 if (Idx >= (int)NumElts)
3284 Idx -= NumElts - NumLaneElts;
3286 if (!isUndefOrEqual(Idx, Start+i))
3295 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3296 /// the two vector operands have swapped position.
3297 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3298 unsigned NumElems) {
3299 for (unsigned i = 0; i != NumElems; ++i) {
3303 else if (idx < (int)NumElems)
3304 Mask[i] = idx + NumElems;
3306 Mask[i] = idx - NumElems;
3310 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3311 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3312 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3313 /// reverse of what x86 shuffles want.
3314 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3315 bool Commuted = false) {
3316 if (!HasAVX && VT.getSizeInBits() == 256)
3319 unsigned NumElems = VT.getVectorNumElements();
3320 unsigned NumLanes = VT.getSizeInBits()/128;
3321 unsigned NumLaneElems = NumElems/NumLanes;
3323 if (NumLaneElems != 2 && NumLaneElems != 4)
3326 // VSHUFPSY divides the resulting vector into 4 chunks.
3327 // The sources are also splitted into 4 chunks, and each destination
3328 // chunk must come from a different source chunk.
3330 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3331 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3333 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3334 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3336 // VSHUFPDY divides the resulting vector into 4 chunks.
3337 // The sources are also splitted into 4 chunks, and each destination
3338 // chunk must come from a different source chunk.
3340 // SRC1 => X3 X2 X1 X0
3341 // SRC2 => Y3 Y2 Y1 Y0
3343 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3345 unsigned HalfLaneElems = NumLaneElems/2;
3346 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3347 for (unsigned i = 0; i != NumLaneElems; ++i) {
3348 int Idx = Mask[i+l];
3349 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3350 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3352 // For VSHUFPSY, the mask of the second half must be the same as the
3353 // first but with the appropriate offsets. This works in the same way as
3354 // VPERMILPS works with masks.
3355 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3357 if (!isUndefOrEqual(Idx, Mask[i]+l))
3365 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3366 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3367 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3368 unsigned NumElems = VT.getVectorNumElements();
3370 if (VT.getSizeInBits() != 128)
3376 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3377 return isUndefOrEqual(Mask[0], 6) &&
3378 isUndefOrEqual(Mask[1], 7) &&
3379 isUndefOrEqual(Mask[2], 2) &&
3380 isUndefOrEqual(Mask[3], 3);
3383 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3384 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3386 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3387 unsigned NumElems = VT.getVectorNumElements();
3389 if (VT.getSizeInBits() != 128)
3395 return isUndefOrEqual(Mask[0], 2) &&
3396 isUndefOrEqual(Mask[1], 3) &&
3397 isUndefOrEqual(Mask[2], 2) &&
3398 isUndefOrEqual(Mask[3], 3);
3401 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3402 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3403 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3404 if (VT.getSizeInBits() != 128)
3407 unsigned NumElems = VT.getVectorNumElements();
3409 if (NumElems != 2 && NumElems != 4)
3412 for (unsigned i = 0; i != NumElems/2; ++i)
3413 if (!isUndefOrEqual(Mask[i], i + NumElems))
3416 for (unsigned i = NumElems/2; i != NumElems; ++i)
3417 if (!isUndefOrEqual(Mask[i], i))
3423 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3424 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3425 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3426 unsigned NumElems = VT.getVectorNumElements();
3428 if ((NumElems != 2 && NumElems != 4)
3429 || VT.getSizeInBits() > 128)
3432 for (unsigned i = 0; i != NumElems/2; ++i)
3433 if (!isUndefOrEqual(Mask[i], i))
3436 for (unsigned i = 0; i != NumElems/2; ++i)
3437 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3443 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3444 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3445 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3446 bool HasAVX2, bool V2IsSplat = false) {
3447 unsigned NumElts = VT.getVectorNumElements();
3449 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3450 "Unsupported vector type for unpckh");
3452 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3453 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3456 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3457 // independently on 128-bit lanes.
3458 unsigned NumLanes = VT.getSizeInBits()/128;
3459 unsigned NumLaneElts = NumElts/NumLanes;
3461 for (unsigned l = 0; l != NumLanes; ++l) {
3462 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3463 i != (l+1)*NumLaneElts;
3466 int BitI1 = Mask[i+1];
3467 if (!isUndefOrEqual(BitI, j))
3470 if (!isUndefOrEqual(BitI1, NumElts))
3473 if (!isUndefOrEqual(BitI1, j + NumElts))
3482 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3483 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3484 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3485 bool HasAVX2, bool V2IsSplat = false) {
3486 unsigned NumElts = VT.getVectorNumElements();
3488 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3489 "Unsupported vector type for unpckh");
3491 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3492 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3495 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3496 // independently on 128-bit lanes.
3497 unsigned NumLanes = VT.getSizeInBits()/128;
3498 unsigned NumLaneElts = NumElts/NumLanes;
3500 for (unsigned l = 0; l != NumLanes; ++l) {
3501 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3502 i != (l+1)*NumLaneElts; i += 2, ++j) {
3504 int BitI1 = Mask[i+1];
3505 if (!isUndefOrEqual(BitI, j))
3508 if (isUndefOrEqual(BitI1, NumElts))
3511 if (!isUndefOrEqual(BitI1, j+NumElts))
3519 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3520 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3522 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3524 unsigned NumElts = VT.getVectorNumElements();
3526 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3527 "Unsupported vector type for unpckh");
3529 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3530 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3533 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3534 // FIXME: Need a better way to get rid of this, there's no latency difference
3535 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3536 // the former later. We should also remove the "_undef" special mask.
3537 if (NumElts == 4 && VT.getSizeInBits() == 256)
3540 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3541 // independently on 128-bit lanes.
3542 unsigned NumLanes = VT.getSizeInBits()/128;
3543 unsigned NumLaneElts = NumElts/NumLanes;
3545 for (unsigned l = 0; l != NumLanes; ++l) {
3546 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3547 i != (l+1)*NumLaneElts;
3550 int BitI1 = Mask[i+1];
3552 if (!isUndefOrEqual(BitI, j))
3554 if (!isUndefOrEqual(BitI1, j))
3562 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3563 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3565 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3566 unsigned NumElts = VT.getVectorNumElements();
3568 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3569 "Unsupported vector type for unpckh");
3571 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3572 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3575 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3576 // independently on 128-bit lanes.
3577 unsigned NumLanes = VT.getSizeInBits()/128;
3578 unsigned NumLaneElts = NumElts/NumLanes;
3580 for (unsigned l = 0; l != NumLanes; ++l) {
3581 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3582 i != (l+1)*NumLaneElts; i += 2, ++j) {
3584 int BitI1 = Mask[i+1];
3585 if (!isUndefOrEqual(BitI, j))
3587 if (!isUndefOrEqual(BitI1, j))
3594 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3595 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3596 /// MOVSD, and MOVD, i.e. setting the lowest element.
3597 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3598 if (VT.getVectorElementType().getSizeInBits() < 32)
3600 if (VT.getSizeInBits() == 256)
3603 unsigned NumElts = VT.getVectorNumElements();
3605 if (!isUndefOrEqual(Mask[0], NumElts))
3608 for (unsigned i = 1; i != NumElts; ++i)
3609 if (!isUndefOrEqual(Mask[i], i))
3615 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3616 /// as permutations between 128-bit chunks or halves. As an example: this
3618 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3619 /// The first half comes from the second half of V1 and the second half from the
3620 /// the second half of V2.
3621 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3622 if (!HasAVX || VT.getSizeInBits() != 256)
3625 // The shuffle result is divided into half A and half B. In total the two
3626 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3627 // B must come from C, D, E or F.
3628 unsigned HalfSize = VT.getVectorNumElements()/2;
3629 bool MatchA = false, MatchB = false;
3631 // Check if A comes from one of C, D, E, F.
3632 for (unsigned Half = 0; Half != 4; ++Half) {
3633 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3639 // Check if B comes from one of C, D, E, F.
3640 for (unsigned Half = 0; Half != 4; ++Half) {
3641 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3647 return MatchA && MatchB;
3650 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3651 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3652 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3653 EVT VT = SVOp->getValueType(0);
3655 unsigned HalfSize = VT.getVectorNumElements()/2;
3657 unsigned FstHalf = 0, SndHalf = 0;
3658 for (unsigned i = 0; i < HalfSize; ++i) {
3659 if (SVOp->getMaskElt(i) > 0) {
3660 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3664 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3665 if (SVOp->getMaskElt(i) > 0) {
3666 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3671 return (FstHalf | (SndHalf << 4));
3674 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3675 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3676 /// Note that VPERMIL mask matching is different depending whether theunderlying
3677 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3678 /// to the same elements of the low, but to the higher half of the source.
3679 /// In VPERMILPD the two lanes could be shuffled independently of each other
3680 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3681 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3685 unsigned NumElts = VT.getVectorNumElements();
3686 // Only match 256-bit with 32/64-bit types
3687 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3690 unsigned NumLanes = VT.getSizeInBits()/128;
3691 unsigned LaneSize = NumElts/NumLanes;
3692 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3693 for (unsigned i = 0; i != LaneSize; ++i) {
3694 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3696 if (NumElts != 8 || l == 0)
3698 // VPERMILPS handling
3701 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3709 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3710 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3711 /// element of vector 2 and the other elements to come from vector 1 in order.
3712 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3713 bool V2IsSplat = false, bool V2IsUndef = false) {
3714 unsigned NumOps = VT.getVectorNumElements();
3715 if (VT.getSizeInBits() == 256)
3717 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3720 if (!isUndefOrEqual(Mask[0], 0))
3723 for (unsigned i = 1; i != NumOps; ++i)
3724 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3725 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3726 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3732 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3733 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3734 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3735 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3736 const X86Subtarget *Subtarget) {
3737 if (!Subtarget->hasSSE3())
3740 unsigned NumElems = VT.getVectorNumElements();
3742 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3743 (VT.getSizeInBits() == 256 && NumElems != 8))
3746 // "i+1" is the value the indexed mask element must have
3747 for (unsigned i = 0; i != NumElems; i += 2)
3748 if (!isUndefOrEqual(Mask[i], i+1) ||
3749 !isUndefOrEqual(Mask[i+1], i+1))
3755 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3756 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3757 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3758 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3759 const X86Subtarget *Subtarget) {
3760 if (!Subtarget->hasSSE3())
3763 unsigned NumElems = VT.getVectorNumElements();
3765 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3766 (VT.getSizeInBits() == 256 && NumElems != 8))
3769 // "i" is the value the indexed mask element must have
3770 for (unsigned i = 0; i != NumElems; i += 2)
3771 if (!isUndefOrEqual(Mask[i], i) ||
3772 !isUndefOrEqual(Mask[i+1], i))
3778 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3779 /// specifies a shuffle of elements that is suitable for input to 256-bit
3780 /// version of MOVDDUP.
3781 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3782 unsigned NumElts = VT.getVectorNumElements();
3784 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3787 for (unsigned i = 0; i != NumElts/2; ++i)
3788 if (!isUndefOrEqual(Mask[i], 0))
3790 for (unsigned i = NumElts/2; i != NumElts; ++i)
3791 if (!isUndefOrEqual(Mask[i], NumElts/2))
3796 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3797 /// specifies a shuffle of elements that is suitable for input to 128-bit
3798 /// version of MOVDDUP.
3799 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3800 if (VT.getSizeInBits() != 128)
3803 unsigned e = VT.getVectorNumElements() / 2;
3804 for (unsigned i = 0; i != e; ++i)
3805 if (!isUndefOrEqual(Mask[i], i))
3807 for (unsigned i = 0; i != e; ++i)
3808 if (!isUndefOrEqual(Mask[e+i], i))
3813 /// isVEXTRACTF128Index - Return true if the specified
3814 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3815 /// suitable for input to VEXTRACTF128.
3816 bool X86::isVEXTRACTF128Index(SDNode *N) {
3817 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3820 // The index should be aligned on a 128-bit boundary.
3822 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3824 unsigned VL = N->getValueType(0).getVectorNumElements();
3825 unsigned VBits = N->getValueType(0).getSizeInBits();
3826 unsigned ElSize = VBits / VL;
3827 bool Result = (Index * ElSize) % 128 == 0;
3832 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3833 /// operand specifies a subvector insert that is suitable for input to
3835 bool X86::isVINSERTF128Index(SDNode *N) {
3836 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3839 // The index should be aligned on a 128-bit boundary.
3841 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3843 unsigned VL = N->getValueType(0).getVectorNumElements();
3844 unsigned VBits = N->getValueType(0).getSizeInBits();
3845 unsigned ElSize = VBits / VL;
3846 bool Result = (Index * ElSize) % 128 == 0;
3851 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3852 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3853 /// Handles 128-bit and 256-bit.
3854 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3855 EVT VT = N->getValueType(0);
3857 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3858 "Unsupported vector type for PSHUF/SHUFP");
3860 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3861 // independently on 128-bit lanes.
3862 unsigned NumElts = VT.getVectorNumElements();
3863 unsigned NumLanes = VT.getSizeInBits()/128;
3864 unsigned NumLaneElts = NumElts/NumLanes;
3866 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3867 "Only supports 2 or 4 elements per lane");
3869 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3871 for (unsigned i = 0; i != NumElts; ++i) {
3872 int Elt = N->getMaskElt(i);
3873 if (Elt < 0) continue;
3875 unsigned ShAmt = i << Shift;
3876 if (ShAmt >= 8) ShAmt -= 8;
3877 Mask |= Elt << ShAmt;
3883 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3884 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3885 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3887 // 8 nodes, but we only care about the last 4.
3888 for (unsigned i = 7; i >= 4; --i) {
3889 int Val = N->getMaskElt(i);
3898 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3899 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3900 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3902 // 8 nodes, but we only care about the first 4.
3903 for (int i = 3; i >= 0; --i) {
3904 int Val = N->getMaskElt(i);
3913 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3914 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3915 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3916 EVT VT = SVOp->getValueType(0);
3917 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3919 unsigned NumElts = VT.getVectorNumElements();
3920 unsigned NumLanes = VT.getSizeInBits()/128;
3921 unsigned NumLaneElts = NumElts/NumLanes;
3925 for (i = 0; i != NumElts; ++i) {
3926 Val = SVOp->getMaskElt(i);
3930 if (Val >= (int)NumElts)
3931 Val -= NumElts - NumLaneElts;
3933 assert(Val - i > 0 && "PALIGNR imm should be positive");
3934 return (Val - i) * EltSize;
3937 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3938 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3940 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3941 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3942 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3945 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3947 EVT VecVT = N->getOperand(0).getValueType();
3948 EVT ElVT = VecVT.getVectorElementType();
3950 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3951 return Index / NumElemsPerChunk;
3954 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3955 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3957 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3958 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3959 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3962 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3964 EVT VecVT = N->getValueType(0);
3965 EVT ElVT = VecVT.getVectorElementType();
3967 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3968 return Index / NumElemsPerChunk;
3971 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3973 bool X86::isZeroNode(SDValue Elt) {
3974 return ((isa<ConstantSDNode>(Elt) &&
3975 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3976 (isa<ConstantFPSDNode>(Elt) &&
3977 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3980 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3981 /// their permute mask.
3982 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3983 SelectionDAG &DAG) {
3984 EVT VT = SVOp->getValueType(0);
3985 unsigned NumElems = VT.getVectorNumElements();
3986 SmallVector<int, 8> MaskVec;
3988 for (unsigned i = 0; i != NumElems; ++i) {
3989 int idx = SVOp->getMaskElt(i);
3991 MaskVec.push_back(idx);
3992 else if (idx < (int)NumElems)
3993 MaskVec.push_back(idx + NumElems);
3995 MaskVec.push_back(idx - NumElems);
3997 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3998 SVOp->getOperand(0), &MaskVec[0]);
4001 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4002 /// match movhlps. The lower half elements should come from upper half of
4003 /// V1 (and in order), and the upper half elements should come from the upper
4004 /// half of V2 (and in order).
4005 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4006 if (VT.getSizeInBits() != 128)
4008 if (VT.getVectorNumElements() != 4)
4010 for (unsigned i = 0, e = 2; i != e; ++i)
4011 if (!isUndefOrEqual(Mask[i], i+2))
4013 for (unsigned i = 2; i != 4; ++i)
4014 if (!isUndefOrEqual(Mask[i], i+4))
4019 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4020 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4022 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4023 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4025 N = N->getOperand(0).getNode();
4026 if (!ISD::isNON_EXTLoad(N))
4029 *LD = cast<LoadSDNode>(N);
4033 // Test whether the given value is a vector value which will be legalized
4035 static bool WillBeConstantPoolLoad(SDNode *N) {
4036 if (N->getOpcode() != ISD::BUILD_VECTOR)
4039 // Check for any non-constant elements.
4040 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4041 switch (N->getOperand(i).getNode()->getOpcode()) {
4043 case ISD::ConstantFP:
4050 // Vectors of all-zeros and all-ones are materialized with special
4051 // instructions rather than being loaded.
4052 return !ISD::isBuildVectorAllZeros(N) &&
4053 !ISD::isBuildVectorAllOnes(N);
4056 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4057 /// match movlp{s|d}. The lower half elements should come from lower half of
4058 /// V1 (and in order), and the upper half elements should come from the upper
4059 /// half of V2 (and in order). And since V1 will become the source of the
4060 /// MOVLP, it must be either a vector load or a scalar load to vector.
4061 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4062 ArrayRef<int> Mask, EVT VT) {
4063 if (VT.getSizeInBits() != 128)
4066 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4068 // Is V2 is a vector load, don't do this transformation. We will try to use
4069 // load folding shufps op.
4070 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4073 unsigned NumElems = VT.getVectorNumElements();
4075 if (NumElems != 2 && NumElems != 4)
4077 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4078 if (!isUndefOrEqual(Mask[i], i))
4080 for (unsigned i = NumElems/2; i != NumElems; ++i)
4081 if (!isUndefOrEqual(Mask[i], i+NumElems))
4086 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4088 static bool isSplatVector(SDNode *N) {
4089 if (N->getOpcode() != ISD::BUILD_VECTOR)
4092 SDValue SplatValue = N->getOperand(0);
4093 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4094 if (N->getOperand(i) != SplatValue)
4099 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4100 /// to an zero vector.
4101 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4102 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4103 SDValue V1 = N->getOperand(0);
4104 SDValue V2 = N->getOperand(1);
4105 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4106 for (unsigned i = 0; i != NumElems; ++i) {
4107 int Idx = N->getMaskElt(i);
4108 if (Idx >= (int)NumElems) {
4109 unsigned Opc = V2.getOpcode();
4110 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4112 if (Opc != ISD::BUILD_VECTOR ||
4113 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4115 } else if (Idx >= 0) {
4116 unsigned Opc = V1.getOpcode();
4117 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4119 if (Opc != ISD::BUILD_VECTOR ||
4120 !X86::isZeroNode(V1.getOperand(Idx)))
4127 /// getZeroVector - Returns a vector of specified type with all zero elements.
4129 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4130 SelectionDAG &DAG, DebugLoc dl) {
4131 assert(VT.isVector() && "Expected a vector type");
4133 // Always build SSE zero vectors as <4 x i32> bitcasted
4134 // to their dest type. This ensures they get CSE'd.
4136 if (VT.getSizeInBits() == 128) { // SSE
4137 if (Subtarget->hasSSE2()) { // SSE2
4138 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4139 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4141 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4142 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4144 } else if (VT.getSizeInBits() == 256) { // AVX
4145 if (Subtarget->hasAVX2()) { // AVX2
4146 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4147 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4148 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4150 // 256-bit logic and arithmetic instructions in AVX are all
4151 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4152 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4153 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4154 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4157 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4160 /// getOnesVector - Returns a vector of specified type with all bits set.
4161 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4162 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4163 /// Then bitcast to their original type, ensuring they get CSE'd.
4164 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4166 assert(VT.isVector() && "Expected a vector type");
4167 assert((VT.is128BitVector() || VT.is256BitVector())
4168 && "Expected a 128-bit or 256-bit vector type");
4170 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4172 if (VT.getSizeInBits() == 256) {
4173 if (HasAVX2) { // AVX2
4174 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4175 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4177 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4178 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4179 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4180 Vec = Insert128BitVector(InsV, Vec,
4181 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4184 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4187 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4190 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4191 /// that point to V2 points to its first element.
4192 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4193 for (unsigned i = 0; i != NumElems; ++i) {
4194 if (Mask[i] > (int)NumElems) {
4200 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4201 /// operation of specified width.
4202 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4204 unsigned NumElems = VT.getVectorNumElements();
4205 SmallVector<int, 8> Mask;
4206 Mask.push_back(NumElems);
4207 for (unsigned i = 1; i != NumElems; ++i)
4209 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4212 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4213 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4215 unsigned NumElems = VT.getVectorNumElements();
4216 SmallVector<int, 8> Mask;
4217 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4219 Mask.push_back(i + NumElems);
4221 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4224 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4225 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4227 unsigned NumElems = VT.getVectorNumElements();
4228 unsigned Half = NumElems/2;
4229 SmallVector<int, 8> Mask;
4230 for (unsigned i = 0; i != Half; ++i) {
4231 Mask.push_back(i + Half);
4232 Mask.push_back(i + NumElems + Half);
4234 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4237 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4238 // a generic shuffle instruction because the target has no such instructions.
4239 // Generate shuffles which repeat i16 and i8 several times until they can be
4240 // represented by v4f32 and then be manipulated by target suported shuffles.
4241 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4242 EVT VT = V.getValueType();
4243 int NumElems = VT.getVectorNumElements();
4244 DebugLoc dl = V.getDebugLoc();
4246 while (NumElems > 4) {
4247 if (EltNo < NumElems/2) {
4248 V = getUnpackl(DAG, dl, VT, V, V);
4250 V = getUnpackh(DAG, dl, VT, V, V);
4251 EltNo -= NumElems/2;
4258 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4259 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4260 EVT VT = V.getValueType();
4261 DebugLoc dl = V.getDebugLoc();
4262 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4263 && "Vector size not supported");
4265 if (VT.getSizeInBits() == 128) {
4266 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4267 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4268 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4271 // To use VPERMILPS to splat scalars, the second half of indicies must
4272 // refer to the higher part, which is a duplication of the lower one,
4273 // because VPERMILPS can only handle in-lane permutations.
4274 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4275 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4277 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4278 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4282 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4285 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4286 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4287 EVT SrcVT = SV->getValueType(0);
4288 SDValue V1 = SV->getOperand(0);
4289 DebugLoc dl = SV->getDebugLoc();
4291 int EltNo = SV->getSplatIndex();
4292 int NumElems = SrcVT.getVectorNumElements();
4293 unsigned Size = SrcVT.getSizeInBits();
4295 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4296 "Unknown how to promote splat for type");
4298 // Extract the 128-bit part containing the splat element and update
4299 // the splat element index when it refers to the higher register.
4301 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4302 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4304 EltNo -= NumElems/2;
4307 // All i16 and i8 vector types can't be used directly by a generic shuffle
4308 // instruction because the target has no such instruction. Generate shuffles
4309 // which repeat i16 and i8 several times until they fit in i32, and then can
4310 // be manipulated by target suported shuffles.
4311 EVT EltVT = SrcVT.getVectorElementType();
4312 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4313 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4315 // Recreate the 256-bit vector and place the same 128-bit vector
4316 // into the low and high part. This is necessary because we want
4317 // to use VPERM* to shuffle the vectors
4319 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4320 DAG.getConstant(0, MVT::i32), DAG, dl);
4321 V1 = Insert128BitVector(InsV, V1,
4322 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4325 return getLegalSplat(DAG, V1, EltNo);
4328 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4329 /// vector of zero or undef vector. This produces a shuffle where the low
4330 /// element of V2 is swizzled into the zero/undef vector, landing at element
4331 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4332 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4334 const X86Subtarget *Subtarget,
4335 SelectionDAG &DAG) {
4336 EVT VT = V2.getValueType();
4338 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4339 unsigned NumElems = VT.getVectorNumElements();
4340 SmallVector<int, 16> MaskVec;
4341 for (unsigned i = 0; i != NumElems; ++i)
4342 // If this is the insertion idx, put the low elt of V2 here.
4343 MaskVec.push_back(i == Idx ? NumElems : i);
4344 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4347 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4348 /// target specific opcode. Returns true if the Mask could be calculated.
4349 /// Sets IsUnary to true if only uses one source.
4350 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4351 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4352 unsigned NumElems = VT.getVectorNumElements();
4356 switch(N->getOpcode()) {
4358 ImmN = N->getOperand(N->getNumOperands()-1);
4359 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4361 case X86ISD::UNPCKH:
4362 DecodeUNPCKHMask(VT, Mask);
4364 case X86ISD::UNPCKL:
4365 DecodeUNPCKLMask(VT, Mask);
4367 case X86ISD::MOVHLPS:
4368 DecodeMOVHLPSMask(NumElems, Mask);
4370 case X86ISD::MOVLHPS:
4371 DecodeMOVLHPSMask(NumElems, Mask);
4373 case X86ISD::PSHUFD:
4374 case X86ISD::VPERMILP:
4375 ImmN = N->getOperand(N->getNumOperands()-1);
4376 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4379 case X86ISD::PSHUFHW:
4380 ImmN = N->getOperand(N->getNumOperands()-1);
4381 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4384 case X86ISD::PSHUFLW:
4385 ImmN = N->getOperand(N->getNumOperands()-1);
4386 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4390 case X86ISD::MOVSD: {
4391 // The index 0 always comes from the first element of the second source,
4392 // this is why MOVSS and MOVSD are used in the first place. The other
4393 // elements come from the other positions of the first source vector
4394 Mask.push_back(NumElems);
4395 for (unsigned i = 1; i != NumElems; ++i) {
4400 case X86ISD::VPERM2X128:
4401 ImmN = N->getOperand(N->getNumOperands()-1);
4402 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4404 case X86ISD::MOVDDUP:
4405 case X86ISD::MOVLHPD:
4406 case X86ISD::MOVLPD:
4407 case X86ISD::MOVLPS:
4408 case X86ISD::MOVSHDUP:
4409 case X86ISD::MOVSLDUP:
4410 case X86ISD::PALIGN:
4411 // Not yet implemented
4413 default: llvm_unreachable("unknown target shuffle node");
4419 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4420 /// element of the result of the vector shuffle.
4421 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4424 return SDValue(); // Limit search depth.
4426 SDValue V = SDValue(N, 0);
4427 EVT VT = V.getValueType();
4428 unsigned Opcode = V.getOpcode();
4430 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4431 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4432 Index = SV->getMaskElt(Index);
4435 return DAG.getUNDEF(VT.getVectorElementType());
4437 unsigned NumElems = VT.getVectorNumElements();
4438 SDValue NewV = (Index < (int)NumElems) ? SV->getOperand(0)
4439 : SV->getOperand(1);
4440 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4443 // Recurse into target specific vector shuffles to find scalars.
4444 if (isTargetShuffle(Opcode)) {
4445 unsigned NumElems = VT.getVectorNumElements();
4446 SmallVector<int, 16> ShuffleMask;
4450 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4453 Index = ShuffleMask[Index];
4455 return DAG.getUNDEF(VT.getVectorElementType());
4457 SDValue NewV = (Index < (int)NumElems) ? N->getOperand(0)
4459 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4463 // Actual nodes that may contain scalar elements
4464 if (Opcode == ISD::BITCAST) {
4465 V = V.getOperand(0);
4466 EVT SrcVT = V.getValueType();
4467 unsigned NumElems = VT.getVectorNumElements();
4469 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4473 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4474 return (Index == 0) ? V.getOperand(0)
4475 : DAG.getUNDEF(VT.getVectorElementType());
4477 if (V.getOpcode() == ISD::BUILD_VECTOR)
4478 return V.getOperand(Index);
4483 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4484 /// shuffle operation which come from a consecutively from a zero. The
4485 /// search can start in two different directions, from left or right.
4487 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4488 bool ZerosFromLeft, SelectionDAG &DAG) {
4491 while (i < NumElems) {
4492 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4493 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4494 if (!(Elt.getNode() &&
4495 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4503 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4504 /// MaskE correspond consecutively to elements from one of the vector operands,
4505 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4507 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4508 int OpIdx, int NumElems, unsigned &OpNum) {
4509 bool SeenV1 = false;
4510 bool SeenV2 = false;
4512 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4513 int Idx = SVOp->getMaskElt(i);
4514 // Ignore undef indicies
4523 // Only accept consecutive elements from the same vector
4524 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4528 OpNum = SeenV1 ? 0 : 1;
4532 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4533 /// logical left shift of a vector.
4534 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4535 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4536 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4537 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4538 false /* check zeros from right */, DAG);
4544 // Considering the elements in the mask that are not consecutive zeros,
4545 // check if they consecutively come from only one of the source vectors.
4547 // V1 = {X, A, B, C} 0
4549 // vector_shuffle V1, V2 <1, 2, 3, X>
4551 if (!isShuffleMaskConsecutive(SVOp,
4552 0, // Mask Start Index
4553 NumElems-NumZeros-1, // Mask End Index
4554 NumZeros, // Where to start looking in the src vector
4555 NumElems, // Number of elements in vector
4556 OpSrc)) // Which source operand ?
4561 ShVal = SVOp->getOperand(OpSrc);
4565 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4566 /// logical left shift of a vector.
4567 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4568 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4569 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4570 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4571 true /* check zeros from left */, DAG);
4577 // Considering the elements in the mask that are not consecutive zeros,
4578 // check if they consecutively come from only one of the source vectors.
4580 // 0 { A, B, X, X } = V2
4582 // vector_shuffle V1, V2 <X, X, 4, 5>
4584 if (!isShuffleMaskConsecutive(SVOp,
4585 NumZeros, // Mask Start Index
4586 NumElems-1, // Mask End Index
4587 0, // Where to start looking in the src vector
4588 NumElems, // Number of elements in vector
4589 OpSrc)) // Which source operand ?
4594 ShVal = SVOp->getOperand(OpSrc);
4598 /// isVectorShift - Returns true if the shuffle can be implemented as a
4599 /// logical left or right shift of a vector.
4600 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4601 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4602 // Although the logic below support any bitwidth size, there are no
4603 // shift instructions which handle more than 128-bit vectors.
4604 if (SVOp->getValueType(0).getSizeInBits() > 128)
4607 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4608 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4614 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4616 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4617 unsigned NumNonZero, unsigned NumZero,
4619 const X86Subtarget* Subtarget,
4620 const TargetLowering &TLI) {
4624 DebugLoc dl = Op.getDebugLoc();
4627 for (unsigned i = 0; i < 16; ++i) {
4628 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4629 if (ThisIsNonZero && First) {
4631 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4633 V = DAG.getUNDEF(MVT::v8i16);
4638 SDValue ThisElt(0, 0), LastElt(0, 0);
4639 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4640 if (LastIsNonZero) {
4641 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4642 MVT::i16, Op.getOperand(i-1));
4644 if (ThisIsNonZero) {
4645 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4646 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4647 ThisElt, DAG.getConstant(8, MVT::i8));
4649 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4653 if (ThisElt.getNode())
4654 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4655 DAG.getIntPtrConstant(i/2));
4659 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4662 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4664 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4665 unsigned NumNonZero, unsigned NumZero,
4667 const X86Subtarget* Subtarget,
4668 const TargetLowering &TLI) {
4672 DebugLoc dl = Op.getDebugLoc();
4675 for (unsigned i = 0; i < 8; ++i) {
4676 bool isNonZero = (NonZeros & (1 << i)) != 0;
4680 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4682 V = DAG.getUNDEF(MVT::v8i16);
4685 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4686 MVT::v8i16, V, Op.getOperand(i),
4687 DAG.getIntPtrConstant(i));
4694 /// getVShift - Return a vector logical shift node.
4696 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4697 unsigned NumBits, SelectionDAG &DAG,
4698 const TargetLowering &TLI, DebugLoc dl) {
4699 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4700 EVT ShVT = MVT::v2i64;
4701 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4702 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4703 return DAG.getNode(ISD::BITCAST, dl, VT,
4704 DAG.getNode(Opc, dl, ShVT, SrcOp,
4705 DAG.getConstant(NumBits,
4706 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4710 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4711 SelectionDAG &DAG) const {
4713 // Check if the scalar load can be widened into a vector load. And if
4714 // the address is "base + cst" see if the cst can be "absorbed" into
4715 // the shuffle mask.
4716 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4717 SDValue Ptr = LD->getBasePtr();
4718 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4720 EVT PVT = LD->getValueType(0);
4721 if (PVT != MVT::i32 && PVT != MVT::f32)
4726 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4727 FI = FINode->getIndex();
4729 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4730 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4731 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4732 Offset = Ptr.getConstantOperandVal(1);
4733 Ptr = Ptr.getOperand(0);
4738 // FIXME: 256-bit vector instructions don't require a strict alignment,
4739 // improve this code to support it better.
4740 unsigned RequiredAlign = VT.getSizeInBits()/8;
4741 SDValue Chain = LD->getChain();
4742 // Make sure the stack object alignment is at least 16 or 32.
4743 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4744 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4745 if (MFI->isFixedObjectIndex(FI)) {
4746 // Can't change the alignment. FIXME: It's possible to compute
4747 // the exact stack offset and reference FI + adjust offset instead.
4748 // If someone *really* cares about this. That's the way to implement it.
4751 MFI->setObjectAlignment(FI, RequiredAlign);
4755 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4756 // Ptr + (Offset & ~15).
4759 if ((Offset % RequiredAlign) & 3)
4761 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4763 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4764 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4766 int EltNo = (Offset - StartOffset) >> 2;
4767 int NumElems = VT.getVectorNumElements();
4769 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4770 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4771 LD->getPointerInfo().getWithOffset(StartOffset),
4772 false, false, false, 0);
4774 SmallVector<int, 8> Mask;
4775 for (int i = 0; i < NumElems; ++i)
4776 Mask.push_back(EltNo);
4778 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4784 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4785 /// vector of type 'VT', see if the elements can be replaced by a single large
4786 /// load which has the same value as a build_vector whose operands are 'elts'.
4788 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4790 /// FIXME: we'd also like to handle the case where the last elements are zero
4791 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4792 /// There's even a handy isZeroNode for that purpose.
4793 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4794 DebugLoc &DL, SelectionDAG &DAG) {
4795 EVT EltVT = VT.getVectorElementType();
4796 unsigned NumElems = Elts.size();
4798 LoadSDNode *LDBase = NULL;
4799 unsigned LastLoadedElt = -1U;
4801 // For each element in the initializer, see if we've found a load or an undef.
4802 // If we don't find an initial load element, or later load elements are
4803 // non-consecutive, bail out.
4804 for (unsigned i = 0; i < NumElems; ++i) {
4805 SDValue Elt = Elts[i];
4807 if (!Elt.getNode() ||
4808 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4811 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4813 LDBase = cast<LoadSDNode>(Elt.getNode());
4817 if (Elt.getOpcode() == ISD::UNDEF)
4820 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4821 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4826 // If we have found an entire vector of loads and undefs, then return a large
4827 // load of the entire vector width starting at the base pointer. If we found
4828 // consecutive loads for the low half, generate a vzext_load node.
4829 if (LastLoadedElt == NumElems - 1) {
4830 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4831 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4832 LDBase->getPointerInfo(),
4833 LDBase->isVolatile(), LDBase->isNonTemporal(),
4834 LDBase->isInvariant(), 0);
4835 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4836 LDBase->getPointerInfo(),
4837 LDBase->isVolatile(), LDBase->isNonTemporal(),
4838 LDBase->isInvariant(), LDBase->getAlignment());
4839 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4840 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4841 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4842 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4844 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4845 LDBase->getPointerInfo(),
4846 LDBase->getAlignment(),
4847 false/*isVolatile*/, true/*ReadMem*/,
4849 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4854 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4855 /// a vbroadcast node. We support two patterns:
4856 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4857 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4859 /// The scalar load node is returned when a pattern is found,
4860 /// or SDValue() otherwise.
4861 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4862 if (!Subtarget->hasAVX())
4865 EVT VT = Op.getValueType();
4868 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4869 V = V.getOperand(0);
4871 //A suspected load to be broadcasted.
4874 switch (V.getOpcode()) {
4876 // Unknown pattern found.
4879 case ISD::BUILD_VECTOR: {
4880 // The BUILD_VECTOR node must be a splat.
4881 if (!isSplatVector(V.getNode()))
4884 Ld = V.getOperand(0);
4886 // The suspected load node has several users. Make sure that all
4887 // of its users are from the BUILD_VECTOR node.
4888 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4893 case ISD::VECTOR_SHUFFLE: {
4894 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4896 // Shuffles must have a splat mask where the first element is
4898 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4901 SDValue Sc = Op.getOperand(0);
4902 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4905 Ld = Sc.getOperand(0);
4907 // The scalar_to_vector node and the suspected
4908 // load node must have exactly one user.
4909 if (!Sc.hasOneUse() || !Ld.hasOneUse())
4915 // The scalar source must be a normal load.
4916 if (!ISD::isNormalLoad(Ld.getNode()))
4919 // Reject loads that have uses of the chain result
4920 if (Ld->hasAnyUseOfValue(1))
4923 bool Is256 = VT.getSizeInBits() == 256;
4924 bool Is128 = VT.getSizeInBits() == 128;
4925 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4927 // VBroadcast to YMM
4928 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4931 // VBroadcast to XMM
4932 if (Is128 && (ScalarSize == 32))
4935 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4936 // double since there is vbroadcastsd xmm
4937 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
4938 // VBroadcast to YMM
4939 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
4942 // VBroadcast to XMM
4943 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
4947 // Unsupported broadcast.
4952 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4953 DebugLoc dl = Op.getDebugLoc();
4955 EVT VT = Op.getValueType();
4956 EVT ExtVT = VT.getVectorElementType();
4957 unsigned NumElems = Op.getNumOperands();
4959 // Vectors containing all zeros can be matched by pxor and xorps later
4960 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4961 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4962 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4963 if (VT == MVT::v4i32 || VT == MVT::v8i32)
4966 return getZeroVector(VT, Subtarget, DAG, dl);
4969 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4970 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
4971 // vpcmpeqd on 256-bit vectors.
4972 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4973 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
4976 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
4979 SDValue LD = isVectorBroadcast(Op, Subtarget);
4981 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
4983 unsigned EVTBits = ExtVT.getSizeInBits();
4985 unsigned NumZero = 0;
4986 unsigned NumNonZero = 0;
4987 unsigned NonZeros = 0;
4988 bool IsAllConstants = true;
4989 SmallSet<SDValue, 8> Values;
4990 for (unsigned i = 0; i < NumElems; ++i) {
4991 SDValue Elt = Op.getOperand(i);
4992 if (Elt.getOpcode() == ISD::UNDEF)
4995 if (Elt.getOpcode() != ISD::Constant &&
4996 Elt.getOpcode() != ISD::ConstantFP)
4997 IsAllConstants = false;
4998 if (X86::isZeroNode(Elt))
5001 NonZeros |= (1 << i);
5006 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5007 if (NumNonZero == 0)
5008 return DAG.getUNDEF(VT);
5010 // Special case for single non-zero, non-undef, element.
5011 if (NumNonZero == 1) {
5012 unsigned Idx = CountTrailingZeros_32(NonZeros);
5013 SDValue Item = Op.getOperand(Idx);
5015 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5016 // the value are obviously zero, truncate the value to i32 and do the
5017 // insertion that way. Only do this if the value is non-constant or if the
5018 // value is a constant being inserted into element 0. It is cheaper to do
5019 // a constant pool load than it is to do a movd + shuffle.
5020 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5021 (!IsAllConstants || Idx == 0)) {
5022 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5024 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5025 EVT VecVT = MVT::v4i32;
5026 unsigned VecElts = 4;
5028 // Truncate the value (which may itself be a constant) to i32, and
5029 // convert it to a vector with movd (S2V+shuffle to zero extend).
5030 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5031 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5032 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5034 // Now we have our 32-bit value zero extended in the low element of
5035 // a vector. If Idx != 0, swizzle it into place.
5037 SmallVector<int, 4> Mask;
5038 Mask.push_back(Idx);
5039 for (unsigned i = 1; i != VecElts; ++i)
5041 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5042 DAG.getUNDEF(Item.getValueType()),
5045 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5049 // If we have a constant or non-constant insertion into the low element of
5050 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5051 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5052 // depending on what the source datatype is.
5055 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5057 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5058 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5059 if (VT.getSizeInBits() == 256) {
5060 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5061 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5062 Item, DAG.getIntPtrConstant(0));
5064 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5065 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5066 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5067 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5070 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5071 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5072 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5073 if (VT.getSizeInBits() == 256) {
5074 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5075 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5078 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5079 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5081 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5085 // Is it a vector logical left shift?
5086 if (NumElems == 2 && Idx == 1 &&
5087 X86::isZeroNode(Op.getOperand(0)) &&
5088 !X86::isZeroNode(Op.getOperand(1))) {
5089 unsigned NumBits = VT.getSizeInBits();
5090 return getVShift(true, VT,
5091 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5092 VT, Op.getOperand(1)),
5093 NumBits/2, DAG, *this, dl);
5096 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5099 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5100 // is a non-constant being inserted into an element other than the low one,
5101 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5102 // movd/movss) to move this into the low element, then shuffle it into
5104 if (EVTBits == 32) {
5105 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5107 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5108 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5109 SmallVector<int, 8> MaskVec;
5110 for (unsigned i = 0; i < NumElems; i++)
5111 MaskVec.push_back(i == Idx ? 0 : 1);
5112 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5116 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5117 if (Values.size() == 1) {
5118 if (EVTBits == 32) {
5119 // Instead of a shuffle like this:
5120 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5121 // Check if it's possible to issue this instead.
5122 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5123 unsigned Idx = CountTrailingZeros_32(NonZeros);
5124 SDValue Item = Op.getOperand(Idx);
5125 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5126 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5131 // A vector full of immediates; various special cases are already
5132 // handled, so this is best done with a single constant-pool load.
5136 // For AVX-length vectors, build the individual 128-bit pieces and use
5137 // shuffles to put them in place.
5138 if (VT.getSizeInBits() == 256) {
5139 SmallVector<SDValue, 32> V;
5140 for (unsigned i = 0; i != NumElems; ++i)
5141 V.push_back(Op.getOperand(i));
5143 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5145 // Build both the lower and upper subvector.
5146 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5147 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5150 // Recreate the wider vector with the lower and upper part.
5151 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5152 DAG.getConstant(0, MVT::i32), DAG, dl);
5153 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5157 // Let legalizer expand 2-wide build_vectors.
5158 if (EVTBits == 64) {
5159 if (NumNonZero == 1) {
5160 // One half is zero or undef.
5161 unsigned Idx = CountTrailingZeros_32(NonZeros);
5162 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5163 Op.getOperand(Idx));
5164 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5169 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5170 if (EVTBits == 8 && NumElems == 16) {
5171 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5173 if (V.getNode()) return V;
5176 if (EVTBits == 16 && NumElems == 8) {
5177 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5179 if (V.getNode()) return V;
5182 // If element VT is == 32 bits, turn it into a number of shuffles.
5183 SmallVector<SDValue, 8> V(NumElems);
5184 if (NumElems == 4 && NumZero > 0) {
5185 for (unsigned i = 0; i < 4; ++i) {
5186 bool isZero = !(NonZeros & (1 << i));
5188 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5190 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5193 for (unsigned i = 0; i < 2; ++i) {
5194 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5197 V[i] = V[i*2]; // Must be a zero vector.
5200 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5203 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5206 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5211 bool Reverse1 = (NonZeros & 0x3) == 2;
5212 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5216 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5217 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5219 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5222 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5223 // Check for a build vector of consecutive loads.
5224 for (unsigned i = 0; i < NumElems; ++i)
5225 V[i] = Op.getOperand(i);
5227 // Check for elements which are consecutive loads.
5228 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5232 // For SSE 4.1, use insertps to put the high elements into the low element.
5233 if (getSubtarget()->hasSSE41()) {
5235 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5236 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5238 Result = DAG.getUNDEF(VT);
5240 for (unsigned i = 1; i < NumElems; ++i) {
5241 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5242 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5243 Op.getOperand(i), DAG.getIntPtrConstant(i));
5248 // Otherwise, expand into a number of unpckl*, start by extending each of
5249 // our (non-undef) elements to the full vector width with the element in the
5250 // bottom slot of the vector (which generates no code for SSE).
5251 for (unsigned i = 0; i < NumElems; ++i) {
5252 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5253 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5255 V[i] = DAG.getUNDEF(VT);
5258 // Next, we iteratively mix elements, e.g. for v4f32:
5259 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5260 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5261 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5262 unsigned EltStride = NumElems >> 1;
5263 while (EltStride != 0) {
5264 for (unsigned i = 0; i < EltStride; ++i) {
5265 // If V[i+EltStride] is undef and this is the first round of mixing,
5266 // then it is safe to just drop this shuffle: V[i] is already in the
5267 // right place, the one element (since it's the first round) being
5268 // inserted as undef can be dropped. This isn't safe for successive
5269 // rounds because they will permute elements within both vectors.
5270 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5271 EltStride == NumElems/2)
5274 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5283 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5284 // them in a MMX register. This is better than doing a stack convert.
5285 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5286 DebugLoc dl = Op.getDebugLoc();
5287 EVT ResVT = Op.getValueType();
5289 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5290 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5292 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5293 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5294 InVec = Op.getOperand(1);
5295 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5296 unsigned NumElts = ResVT.getVectorNumElements();
5297 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5298 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5299 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5301 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5302 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5303 Mask[0] = 0; Mask[1] = 2;
5304 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5306 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5309 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5310 // to create 256-bit vectors from two other 128-bit ones.
5311 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5312 DebugLoc dl = Op.getDebugLoc();
5313 EVT ResVT = Op.getValueType();
5315 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5317 SDValue V1 = Op.getOperand(0);
5318 SDValue V2 = Op.getOperand(1);
5319 unsigned NumElems = ResVT.getVectorNumElements();
5321 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5322 DAG.getConstant(0, MVT::i32), DAG, dl);
5323 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5328 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5329 EVT ResVT = Op.getValueType();
5331 assert(Op.getNumOperands() == 2);
5332 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5333 "Unsupported CONCAT_VECTORS for value type");
5335 // We support concatenate two MMX registers and place them in a MMX register.
5336 // This is better than doing a stack convert.
5337 if (ResVT.is128BitVector())
5338 return LowerMMXCONCAT_VECTORS(Op, DAG);
5340 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5341 // from two other 128-bit ones.
5342 return LowerAVXCONCAT_VECTORS(Op, DAG);
5345 // v8i16 shuffles - Prefer shuffles in the following order:
5346 // 1. [all] pshuflw, pshufhw, optional move
5347 // 2. [ssse3] 1 x pshufb
5348 // 3. [ssse3] 2 x pshufb + 1 x por
5349 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5351 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5352 SelectionDAG &DAG) const {
5353 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5354 SDValue V1 = SVOp->getOperand(0);
5355 SDValue V2 = SVOp->getOperand(1);
5356 DebugLoc dl = SVOp->getDebugLoc();
5357 SmallVector<int, 8> MaskVals;
5359 // Determine if more than 1 of the words in each of the low and high quadwords
5360 // of the result come from the same quadword of one of the two inputs. Undef
5361 // mask values count as coming from any quadword, for better codegen.
5362 unsigned LoQuad[] = { 0, 0, 0, 0 };
5363 unsigned HiQuad[] = { 0, 0, 0, 0 };
5364 std::bitset<4> InputQuads;
5365 for (unsigned i = 0; i < 8; ++i) {
5366 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5367 int EltIdx = SVOp->getMaskElt(i);
5368 MaskVals.push_back(EltIdx);
5377 InputQuads.set(EltIdx / 4);
5380 int BestLoQuad = -1;
5381 unsigned MaxQuad = 1;
5382 for (unsigned i = 0; i < 4; ++i) {
5383 if (LoQuad[i] > MaxQuad) {
5385 MaxQuad = LoQuad[i];
5389 int BestHiQuad = -1;
5391 for (unsigned i = 0; i < 4; ++i) {
5392 if (HiQuad[i] > MaxQuad) {
5394 MaxQuad = HiQuad[i];
5398 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5399 // of the two input vectors, shuffle them into one input vector so only a
5400 // single pshufb instruction is necessary. If There are more than 2 input
5401 // quads, disable the next transformation since it does not help SSSE3.
5402 bool V1Used = InputQuads[0] || InputQuads[1];
5403 bool V2Used = InputQuads[2] || InputQuads[3];
5404 if (Subtarget->hasSSSE3()) {
5405 if (InputQuads.count() == 2 && V1Used && V2Used) {
5406 BestLoQuad = InputQuads[0] ? 0 : 1;
5407 BestHiQuad = InputQuads[2] ? 2 : 3;
5409 if (InputQuads.count() > 2) {
5415 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5416 // the shuffle mask. If a quad is scored as -1, that means that it contains
5417 // words from all 4 input quadwords.
5419 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5421 BestLoQuad < 0 ? 0 : BestLoQuad,
5422 BestHiQuad < 0 ? 1 : BestHiQuad
5424 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5425 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5426 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5427 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5429 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5430 // source words for the shuffle, to aid later transformations.
5431 bool AllWordsInNewV = true;
5432 bool InOrder[2] = { true, true };
5433 for (unsigned i = 0; i != 8; ++i) {
5434 int idx = MaskVals[i];
5436 InOrder[i/4] = false;
5437 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5439 AllWordsInNewV = false;
5443 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5444 if (AllWordsInNewV) {
5445 for (int i = 0; i != 8; ++i) {
5446 int idx = MaskVals[i];
5449 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5450 if ((idx != i) && idx < 4)
5452 if ((idx != i) && idx > 3)
5461 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5462 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5463 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5464 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5465 unsigned TargetMask = 0;
5466 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5467 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5468 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5469 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5470 getShufflePSHUFLWImmediate(SVOp);
5471 V1 = NewV.getOperand(0);
5472 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5476 // If we have SSSE3, and all words of the result are from 1 input vector,
5477 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5478 // is present, fall back to case 4.
5479 if (Subtarget->hasSSSE3()) {
5480 SmallVector<SDValue,16> pshufbMask;
5482 // If we have elements from both input vectors, set the high bit of the
5483 // shuffle mask element to zero out elements that come from V2 in the V1
5484 // mask, and elements that come from V1 in the V2 mask, so that the two
5485 // results can be OR'd together.
5486 bool TwoInputs = V1Used && V2Used;
5487 for (unsigned i = 0; i != 8; ++i) {
5488 int EltIdx = MaskVals[i] * 2;
5489 if (TwoInputs && (EltIdx >= 16)) {
5490 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5491 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5494 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5495 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5497 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5498 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5499 DAG.getNode(ISD::BUILD_VECTOR, dl,
5500 MVT::v16i8, &pshufbMask[0], 16));
5502 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5504 // Calculate the shuffle mask for the second input, shuffle it, and
5505 // OR it with the first shuffled input.
5507 for (unsigned i = 0; i != 8; ++i) {
5508 int EltIdx = MaskVals[i] * 2;
5510 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5511 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5514 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5515 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5517 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5518 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5519 DAG.getNode(ISD::BUILD_VECTOR, dl,
5520 MVT::v16i8, &pshufbMask[0], 16));
5521 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5522 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5525 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5526 // and update MaskVals with new element order.
5527 std::bitset<8> InOrder;
5528 if (BestLoQuad >= 0) {
5529 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5530 for (int i = 0; i != 4; ++i) {
5531 int idx = MaskVals[i];
5534 } else if ((idx / 4) == BestLoQuad) {
5539 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5542 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5543 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5544 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5546 getShufflePSHUFLWImmediate(SVOp), DAG);
5550 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5551 // and update MaskVals with the new element order.
5552 if (BestHiQuad >= 0) {
5553 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5554 for (unsigned i = 4; i != 8; ++i) {
5555 int idx = MaskVals[i];
5558 } else if ((idx / 4) == BestHiQuad) {
5559 MaskV[i] = (idx & 3) + 4;
5563 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5566 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5567 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5568 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5570 getShufflePSHUFHWImmediate(SVOp), DAG);
5574 // In case BestHi & BestLo were both -1, which means each quadword has a word
5575 // from each of the four input quadwords, calculate the InOrder bitvector now
5576 // before falling through to the insert/extract cleanup.
5577 if (BestLoQuad == -1 && BestHiQuad == -1) {
5579 for (int i = 0; i != 8; ++i)
5580 if (MaskVals[i] < 0 || MaskVals[i] == i)
5584 // The other elements are put in the right place using pextrw and pinsrw.
5585 for (unsigned i = 0; i != 8; ++i) {
5588 int EltIdx = MaskVals[i];
5591 SDValue ExtOp = (EltIdx < 8)
5592 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5593 DAG.getIntPtrConstant(EltIdx))
5594 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5595 DAG.getIntPtrConstant(EltIdx - 8));
5596 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5597 DAG.getIntPtrConstant(i));
5602 // v16i8 shuffles - Prefer shuffles in the following order:
5603 // 1. [ssse3] 1 x pshufb
5604 // 2. [ssse3] 2 x pshufb + 1 x por
5605 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5607 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5609 const X86TargetLowering &TLI) {
5610 SDValue V1 = SVOp->getOperand(0);
5611 SDValue V2 = SVOp->getOperand(1);
5612 DebugLoc dl = SVOp->getDebugLoc();
5613 ArrayRef<int> MaskVals = SVOp->getMask();
5615 // If we have SSSE3, case 1 is generated when all result bytes come from
5616 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5617 // present, fall back to case 3.
5618 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5621 for (unsigned i = 0; i < 16; ++i) {
5622 int EltIdx = MaskVals[i];
5631 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5632 if (TLI.getSubtarget()->hasSSSE3()) {
5633 SmallVector<SDValue,16> pshufbMask;
5635 // If all result elements are from one input vector, then only translate
5636 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5638 // Otherwise, we have elements from both input vectors, and must zero out
5639 // elements that come from V2 in the first mask, and V1 in the second mask
5640 // so that we can OR them together.
5641 bool TwoInputs = !(V1Only || V2Only);
5642 for (unsigned i = 0; i != 16; ++i) {
5643 int EltIdx = MaskVals[i];
5644 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5645 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5648 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5650 // If all the elements are from V2, assign it to V1 and return after
5651 // building the first pshufb.
5654 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5655 DAG.getNode(ISD::BUILD_VECTOR, dl,
5656 MVT::v16i8, &pshufbMask[0], 16));
5660 // Calculate the shuffle mask for the second input, shuffle it, and
5661 // OR it with the first shuffled input.
5663 for (unsigned i = 0; i != 16; ++i) {
5664 int EltIdx = MaskVals[i];
5666 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5669 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5671 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5672 DAG.getNode(ISD::BUILD_VECTOR, dl,
5673 MVT::v16i8, &pshufbMask[0], 16));
5674 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5677 // No SSSE3 - Calculate in place words and then fix all out of place words
5678 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5679 // the 16 different words that comprise the two doublequadword input vectors.
5680 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5681 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5682 SDValue NewV = V2Only ? V2 : V1;
5683 for (int i = 0; i != 8; ++i) {
5684 int Elt0 = MaskVals[i*2];
5685 int Elt1 = MaskVals[i*2+1];
5687 // This word of the result is all undef, skip it.
5688 if (Elt0 < 0 && Elt1 < 0)
5691 // This word of the result is already in the correct place, skip it.
5692 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5694 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5697 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5698 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5701 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5702 // using a single extract together, load it and store it.
5703 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5704 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5705 DAG.getIntPtrConstant(Elt1 / 2));
5706 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5707 DAG.getIntPtrConstant(i));
5711 // If Elt1 is defined, extract it from the appropriate source. If the
5712 // source byte is not also odd, shift the extracted word left 8 bits
5713 // otherwise clear the bottom 8 bits if we need to do an or.
5715 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5716 DAG.getIntPtrConstant(Elt1 / 2));
5717 if ((Elt1 & 1) == 0)
5718 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5720 TLI.getShiftAmountTy(InsElt.getValueType())));
5722 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5723 DAG.getConstant(0xFF00, MVT::i16));
5725 // If Elt0 is defined, extract it from the appropriate source. If the
5726 // source byte is not also even, shift the extracted word right 8 bits. If
5727 // Elt1 was also defined, OR the extracted values together before
5728 // inserting them in the result.
5730 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5731 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5732 if ((Elt0 & 1) != 0)
5733 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5735 TLI.getShiftAmountTy(InsElt0.getValueType())));
5737 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5738 DAG.getConstant(0x00FF, MVT::i16));
5739 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5742 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5743 DAG.getIntPtrConstant(i));
5745 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5748 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5749 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5750 /// done when every pair / quad of shuffle mask elements point to elements in
5751 /// the right sequence. e.g.
5752 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5754 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5755 SelectionDAG &DAG, DebugLoc dl) {
5756 EVT VT = SVOp->getValueType(0);
5757 SDValue V1 = SVOp->getOperand(0);
5758 SDValue V2 = SVOp->getOperand(1);
5759 unsigned NumElems = VT.getVectorNumElements();
5760 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5762 switch (VT.getSimpleVT().SimpleTy) {
5763 default: llvm_unreachable("Unexpected!");
5764 case MVT::v4f32: NewVT = MVT::v2f64; break;
5765 case MVT::v4i32: NewVT = MVT::v2i64; break;
5766 case MVT::v8i16: NewVT = MVT::v4i32; break;
5767 case MVT::v16i8: NewVT = MVT::v4i32; break;
5770 int Scale = NumElems / NewWidth;
5771 SmallVector<int, 8> MaskVec;
5772 for (unsigned i = 0; i < NumElems; i += Scale) {
5774 for (int j = 0; j < Scale; ++j) {
5775 int EltIdx = SVOp->getMaskElt(i+j);
5779 StartIdx = EltIdx - (EltIdx % Scale);
5780 if (EltIdx != StartIdx + j)
5784 MaskVec.push_back(-1);
5786 MaskVec.push_back(StartIdx / Scale);
5789 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5790 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5791 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5794 /// getVZextMovL - Return a zero-extending vector move low node.
5796 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5797 SDValue SrcOp, SelectionDAG &DAG,
5798 const X86Subtarget *Subtarget, DebugLoc dl) {
5799 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5800 LoadSDNode *LD = NULL;
5801 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5802 LD = dyn_cast<LoadSDNode>(SrcOp);
5804 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5806 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5807 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5808 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5809 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5810 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5812 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5813 return DAG.getNode(ISD::BITCAST, dl, VT,
5814 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5815 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5823 return DAG.getNode(ISD::BITCAST, dl, VT,
5824 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5825 DAG.getNode(ISD::BITCAST, dl,
5829 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5830 /// which could not be matched by any known target speficic shuffle
5832 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5833 EVT VT = SVOp->getValueType(0);
5835 unsigned NumElems = VT.getVectorNumElements();
5836 unsigned NumLaneElems = NumElems / 2;
5838 int MinRange[2][2] = { { static_cast<int>(NumElems),
5839 static_cast<int>(NumElems) },
5840 { static_cast<int>(NumElems),
5841 static_cast<int>(NumElems) } };
5842 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5844 // Collect used ranges for each source in each lane
5845 for (unsigned l = 0; l < 2; ++l) {
5846 unsigned LaneStart = l*NumLaneElems;
5847 for (unsigned i = 0; i != NumLaneElems; ++i) {
5848 int Idx = SVOp->getMaskElt(i+LaneStart);
5853 if (Idx >= (int)NumElems) {
5858 if (Idx > MaxRange[l][Input])
5859 MaxRange[l][Input] = Idx;
5860 if (Idx < MinRange[l][Input])
5861 MinRange[l][Input] = Idx;
5865 // Make sure each range is 128-bits
5866 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5867 for (unsigned l = 0; l < 2; ++l) {
5868 for (unsigned Input = 0; Input < 2; ++Input) {
5869 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5872 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems)
5873 ExtractIdx[l][Input] = 0;
5874 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5875 MaxRange[l][Input] < (int)NumElems)
5876 ExtractIdx[l][Input] = NumLaneElems;
5882 DebugLoc dl = SVOp->getDebugLoc();
5883 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5884 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5887 for (unsigned l = 0; l < 2; ++l) {
5888 for (unsigned Input = 0; Input < 2; ++Input) {
5889 if (ExtractIdx[l][Input] >= 0)
5890 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
5891 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
5894 Ops[l][Input] = DAG.getUNDEF(NVT);
5898 // Generate 128-bit shuffles
5899 SmallVector<int, 16> Mask1, Mask2;
5900 for (unsigned i = 0; i != NumLaneElems; ++i) {
5901 int Elt = SVOp->getMaskElt(i);
5902 if (Elt >= (int)NumElems) {
5903 Elt %= NumLaneElems;
5904 Elt += NumLaneElems;
5905 } else if (Elt >= 0) {
5906 Elt %= NumLaneElems;
5908 Mask1.push_back(Elt);
5910 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
5911 int Elt = SVOp->getMaskElt(i);
5912 if (Elt >= (int)NumElems) {
5913 Elt %= NumLaneElems;
5914 Elt += NumLaneElems;
5915 } else if (Elt >= 0) {
5916 Elt %= NumLaneElems;
5918 Mask2.push_back(Elt);
5921 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
5922 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
5924 // Concatenate the result back
5925 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
5926 DAG.getConstant(0, MVT::i32), DAG, dl);
5927 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
5931 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5932 /// 4 elements, and match them with several different shuffle types.
5934 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5935 SDValue V1 = SVOp->getOperand(0);
5936 SDValue V2 = SVOp->getOperand(1);
5937 DebugLoc dl = SVOp->getDebugLoc();
5938 EVT VT = SVOp->getValueType(0);
5940 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5942 std::pair<int, int> Locs[4];
5943 int Mask1[] = { -1, -1, -1, -1 };
5944 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
5948 for (unsigned i = 0; i != 4; ++i) {
5949 int Idx = PermMask[i];
5951 Locs[i] = std::make_pair(-1, -1);
5953 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5955 Locs[i] = std::make_pair(0, NumLo);
5959 Locs[i] = std::make_pair(1, NumHi);
5961 Mask1[2+NumHi] = Idx;
5967 if (NumLo <= 2 && NumHi <= 2) {
5968 // If no more than two elements come from either vector. This can be
5969 // implemented with two shuffles. First shuffle gather the elements.
5970 // The second shuffle, which takes the first shuffle as both of its
5971 // vector operands, put the elements into the right order.
5972 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5974 int Mask2[] = { -1, -1, -1, -1 };
5976 for (unsigned i = 0; i != 4; ++i)
5977 if (Locs[i].first != -1) {
5978 unsigned Idx = (i < 2) ? 0 : 4;
5979 Idx += Locs[i].first * 2 + Locs[i].second;
5983 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5984 } else if (NumLo == 3 || NumHi == 3) {
5985 // Otherwise, we must have three elements from one vector, call it X, and
5986 // one element from the other, call it Y. First, use a shufps to build an
5987 // intermediate vector with the one element from Y and the element from X
5988 // that will be in the same half in the final destination (the indexes don't
5989 // matter). Then, use a shufps to build the final vector, taking the half
5990 // containing the element from Y from the intermediate, and the other half
5993 // Normalize it so the 3 elements come from V1.
5994 CommuteVectorShuffleMask(PermMask, 4);
5998 // Find the element from V2.
6000 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6001 int Val = PermMask[HiIndex];
6008 Mask1[0] = PermMask[HiIndex];
6010 Mask1[2] = PermMask[HiIndex^1];
6012 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6015 Mask1[0] = PermMask[0];
6016 Mask1[1] = PermMask[1];
6017 Mask1[2] = HiIndex & 1 ? 6 : 4;
6018 Mask1[3] = HiIndex & 1 ? 4 : 6;
6019 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6021 Mask1[0] = HiIndex & 1 ? 2 : 0;
6022 Mask1[1] = HiIndex & 1 ? 0 : 2;
6023 Mask1[2] = PermMask[2];
6024 Mask1[3] = PermMask[3];
6029 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6033 // Break it into (shuffle shuffle_hi, shuffle_lo).
6034 int LoMask[] = { -1, -1, -1, -1 };
6035 int HiMask[] = { -1, -1, -1, -1 };
6037 int *MaskPtr = LoMask;
6038 unsigned MaskIdx = 0;
6041 for (unsigned i = 0; i != 4; ++i) {
6048 int Idx = PermMask[i];
6050 Locs[i] = std::make_pair(-1, -1);
6051 } else if (Idx < 4) {
6052 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6053 MaskPtr[LoIdx] = Idx;
6056 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6057 MaskPtr[HiIdx] = Idx;
6062 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6063 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6064 int MaskOps[] = { -1, -1, -1, -1 };
6065 for (unsigned i = 0; i != 4; ++i)
6066 if (Locs[i].first != -1)
6067 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6068 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6071 static bool MayFoldVectorLoad(SDValue V) {
6072 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6073 V = V.getOperand(0);
6074 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6075 V = V.getOperand(0);
6076 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6077 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6078 // BUILD_VECTOR (load), undef
6079 V = V.getOperand(0);
6085 // FIXME: the version above should always be used. Since there's
6086 // a bug where several vector shuffles can't be folded because the
6087 // DAG is not updated during lowering and a node claims to have two
6088 // uses while it only has one, use this version, and let isel match
6089 // another instruction if the load really happens to have more than
6090 // one use. Remove this version after this bug get fixed.
6091 // rdar://8434668, PR8156
6092 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6093 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6094 V = V.getOperand(0);
6095 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6096 V = V.getOperand(0);
6097 if (ISD::isNormalLoad(V.getNode()))
6103 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6104 EVT VT = Op.getValueType();
6106 // Canonizalize to v2f64.
6107 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6108 return DAG.getNode(ISD::BITCAST, dl, VT,
6109 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6114 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6116 SDValue V1 = Op.getOperand(0);
6117 SDValue V2 = Op.getOperand(1);
6118 EVT VT = Op.getValueType();
6120 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6122 if (HasSSE2 && VT == MVT::v2f64)
6123 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6125 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6126 return DAG.getNode(ISD::BITCAST, dl, VT,
6127 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6128 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6129 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6133 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6134 SDValue V1 = Op.getOperand(0);
6135 SDValue V2 = Op.getOperand(1);
6136 EVT VT = Op.getValueType();
6138 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6139 "unsupported shuffle type");
6141 if (V2.getOpcode() == ISD::UNDEF)
6145 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6149 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6150 SDValue V1 = Op.getOperand(0);
6151 SDValue V2 = Op.getOperand(1);
6152 EVT VT = Op.getValueType();
6153 unsigned NumElems = VT.getVectorNumElements();
6155 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6156 // operand of these instructions is only memory, so check if there's a
6157 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6159 bool CanFoldLoad = false;
6161 // Trivial case, when V2 comes from a load.
6162 if (MayFoldVectorLoad(V2))
6165 // When V1 is a load, it can be folded later into a store in isel, example:
6166 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6168 // (MOVLPSmr addr:$src1, VR128:$src2)
6169 // So, recognize this potential and also use MOVLPS or MOVLPD
6170 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6173 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6175 if (HasSSE2 && NumElems == 2)
6176 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6179 // If we don't care about the second element, procede to use movss.
6180 if (SVOp->getMaskElt(1) != -1)
6181 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6184 // movl and movlp will both match v2i64, but v2i64 is never matched by
6185 // movl earlier because we make it strict to avoid messing with the movlp load
6186 // folding logic (see the code above getMOVLP call). Match it here then,
6187 // this is horrible, but will stay like this until we move all shuffle
6188 // matching to x86 specific nodes. Note that for the 1st condition all
6189 // types are matched with movsd.
6191 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6192 // as to remove this logic from here, as much as possible
6193 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6194 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6195 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6198 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6200 // Invert the operand order and use SHUFPS to match it.
6201 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6202 getShuffleSHUFImmediate(SVOp), DAG);
6206 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6207 const TargetLowering &TLI,
6208 const X86Subtarget *Subtarget) {
6209 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6210 EVT VT = Op.getValueType();
6211 DebugLoc dl = Op.getDebugLoc();
6212 SDValue V1 = Op.getOperand(0);
6213 SDValue V2 = Op.getOperand(1);
6215 if (isZeroShuffle(SVOp))
6216 return getZeroVector(VT, Subtarget, DAG, dl);
6218 // Handle splat operations
6219 if (SVOp->isSplat()) {
6220 unsigned NumElem = VT.getVectorNumElements();
6221 int Size = VT.getSizeInBits();
6223 // Use vbroadcast whenever the splat comes from a foldable load
6224 SDValue LD = isVectorBroadcast(Op, Subtarget);
6226 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6228 // Handle splats by matching through known shuffle masks
6229 if ((Size == 128 && NumElem <= 4) ||
6230 (Size == 256 && NumElem < 8))
6233 // All remaning splats are promoted to target supported vector shuffles.
6234 return PromoteSplat(SVOp, DAG);
6237 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6239 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6240 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6241 if (NewOp.getNode())
6242 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6243 } else if ((VT == MVT::v4i32 ||
6244 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6245 // FIXME: Figure out a cleaner way to do this.
6246 // Try to make use of movq to zero out the top part.
6247 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6248 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6249 if (NewOp.getNode()) {
6250 EVT NewVT = NewOp.getValueType();
6251 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6252 NewVT, true, false))
6253 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6254 DAG, Subtarget, dl);
6256 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6257 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6258 if (NewOp.getNode()) {
6259 EVT NewVT = NewOp.getValueType();
6260 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6261 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6262 DAG, Subtarget, dl);
6270 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6271 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6272 SDValue V1 = Op.getOperand(0);
6273 SDValue V2 = Op.getOperand(1);
6274 EVT VT = Op.getValueType();
6275 DebugLoc dl = Op.getDebugLoc();
6276 unsigned NumElems = VT.getVectorNumElements();
6277 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6278 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6279 bool V1IsSplat = false;
6280 bool V2IsSplat = false;
6281 bool HasSSE2 = Subtarget->hasSSE2();
6282 bool HasAVX = Subtarget->hasAVX();
6283 bool HasAVX2 = Subtarget->hasAVX2();
6284 MachineFunction &MF = DAG.getMachineFunction();
6285 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6287 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6289 if (V1IsUndef && V2IsUndef)
6290 return DAG.getUNDEF(VT);
6292 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6294 // Vector shuffle lowering takes 3 steps:
6296 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6297 // narrowing and commutation of operands should be handled.
6298 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6300 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6301 // so the shuffle can be broken into other shuffles and the legalizer can
6302 // try the lowering again.
6304 // The general idea is that no vector_shuffle operation should be left to
6305 // be matched during isel, all of them must be converted to a target specific
6308 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6309 // narrowing and commutation of operands should be handled. The actual code
6310 // doesn't include all of those, work in progress...
6311 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6312 if (NewOp.getNode())
6315 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6317 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6318 // unpckh_undef). Only use pshufd if speed is more important than size.
6319 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6320 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6321 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6322 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6324 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6325 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6326 return getMOVDDup(Op, dl, V1, DAG);
6328 if (isMOVHLPS_v_undef_Mask(M, VT))
6329 return getMOVHighToLow(Op, dl, DAG);
6331 // Use to match splats
6332 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6333 (VT == MVT::v2f64 || VT == MVT::v2i64))
6334 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6336 if (isPSHUFDMask(M, VT)) {
6337 // The actual implementation will match the mask in the if above and then
6338 // during isel it can match several different instructions, not only pshufd
6339 // as its name says, sad but true, emulate the behavior for now...
6340 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6341 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6343 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6345 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6346 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6348 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6349 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6351 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6355 // Check if this can be converted into a logical shift.
6356 bool isLeft = false;
6359 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6360 if (isShift && ShVal.hasOneUse()) {
6361 // If the shifted value has multiple uses, it may be cheaper to use
6362 // v_set0 + movlhps or movhlps, etc.
6363 EVT EltVT = VT.getVectorElementType();
6364 ShAmt *= EltVT.getSizeInBits();
6365 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6368 if (isMOVLMask(M, VT)) {
6369 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6370 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6371 if (!isMOVLPMask(M, VT)) {
6372 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6373 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6375 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6376 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6380 // FIXME: fold these into legal mask.
6381 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6382 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6384 if (isMOVHLPSMask(M, VT))
6385 return getMOVHighToLow(Op, dl, DAG);
6387 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6388 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6390 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6391 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6393 if (isMOVLPMask(M, VT))
6394 return getMOVLP(Op, dl, DAG, HasSSE2);
6396 if (ShouldXformToMOVHLPS(M, VT) ||
6397 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6398 return CommuteVectorShuffle(SVOp, DAG);
6401 // No better options. Use a vshldq / vsrldq.
6402 EVT EltVT = VT.getVectorElementType();
6403 ShAmt *= EltVT.getSizeInBits();
6404 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6407 bool Commuted = false;
6408 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6409 // 1,1,1,1 -> v8i16 though.
6410 V1IsSplat = isSplatVector(V1.getNode());
6411 V2IsSplat = isSplatVector(V2.getNode());
6413 // Canonicalize the splat or undef, if present, to be on the RHS.
6414 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6415 CommuteVectorShuffleMask(M, NumElems);
6417 std::swap(V1IsSplat, V2IsSplat);
6421 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6422 // Shuffling low element of v1 into undef, just return v1.
6425 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6426 // the instruction selector will not match, so get a canonical MOVL with
6427 // swapped operands to undo the commute.
6428 return getMOVL(DAG, dl, VT, V2, V1);
6431 if (isUNPCKLMask(M, VT, HasAVX2))
6432 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6434 if (isUNPCKHMask(M, VT, HasAVX2))
6435 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6438 // Normalize mask so all entries that point to V2 points to its first
6439 // element then try to match unpck{h|l} again. If match, return a
6440 // new vector_shuffle with the corrected mask.p
6441 SmallVector<int, 8> NewMask(M.begin(), M.end());
6442 NormalizeMask(NewMask, NumElems);
6443 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) {
6444 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6445 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) {
6446 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6451 // Commute is back and try unpck* again.
6452 // FIXME: this seems wrong.
6453 CommuteVectorShuffleMask(M, NumElems);
6455 std::swap(V1IsSplat, V2IsSplat);
6458 if (isUNPCKLMask(M, VT, HasAVX2))
6459 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6461 if (isUNPCKHMask(M, VT, HasAVX2))
6462 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6465 // Normalize the node to match x86 shuffle ops if needed
6466 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6467 return CommuteVectorShuffle(SVOp, DAG);
6469 // The checks below are all present in isShuffleMaskLegal, but they are
6470 // inlined here right now to enable us to directly emit target specific
6471 // nodes, and remove one by one until they don't return Op anymore.
6473 if (isPALIGNRMask(M, VT, Subtarget))
6474 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6475 getShufflePALIGNRImmediate(SVOp),
6478 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6479 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6480 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6481 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6484 if (isPSHUFHWMask(M, VT))
6485 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6486 getShufflePSHUFHWImmediate(SVOp),
6489 if (isPSHUFLWMask(M, VT))
6490 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6491 getShufflePSHUFLWImmediate(SVOp),
6494 if (isSHUFPMask(M, VT, HasAVX))
6495 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6496 getShuffleSHUFImmediate(SVOp), DAG);
6498 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6499 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6500 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6501 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6503 //===--------------------------------------------------------------------===//
6504 // Generate target specific nodes for 128 or 256-bit shuffles only
6505 // supported in the AVX instruction set.
6508 // Handle VMOVDDUPY permutations
6509 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6510 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6512 // Handle VPERMILPS/D* permutations
6513 if (isVPERMILPMask(M, VT, HasAVX)) {
6514 if (HasAVX2 && VT == MVT::v8i32)
6515 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6516 getShuffleSHUFImmediate(SVOp), DAG);
6517 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6518 getShuffleSHUFImmediate(SVOp), DAG);
6521 // Handle VPERM2F128/VPERM2I128 permutations
6522 if (isVPERM2X128Mask(M, VT, HasAVX))
6523 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6524 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6526 //===--------------------------------------------------------------------===//
6527 // Since no target specific shuffle was selected for this generic one,
6528 // lower it into other known shuffles. FIXME: this isn't true yet, but
6529 // this is the plan.
6532 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6533 if (VT == MVT::v8i16) {
6534 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6535 if (NewOp.getNode())
6539 if (VT == MVT::v16i8) {
6540 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6541 if (NewOp.getNode())
6545 // Handle all 128-bit wide vectors with 4 elements, and match them with
6546 // several different shuffle types.
6547 if (NumElems == 4 && VT.getSizeInBits() == 128)
6548 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6550 // Handle general 256-bit shuffles
6551 if (VT.is256BitVector())
6552 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6558 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6559 SelectionDAG &DAG) const {
6560 EVT VT = Op.getValueType();
6561 DebugLoc dl = Op.getDebugLoc();
6563 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6566 if (VT.getSizeInBits() == 8) {
6567 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6568 Op.getOperand(0), Op.getOperand(1));
6569 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6570 DAG.getValueType(VT));
6571 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6572 } else if (VT.getSizeInBits() == 16) {
6573 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6574 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6576 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6578 DAG.getNode(ISD::BITCAST, dl,
6582 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6583 Op.getOperand(0), Op.getOperand(1));
6584 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6585 DAG.getValueType(VT));
6586 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6587 } else if (VT == MVT::f32) {
6588 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6589 // the result back to FR32 register. It's only worth matching if the
6590 // result has a single use which is a store or a bitcast to i32. And in
6591 // the case of a store, it's not worth it if the index is a constant 0,
6592 // because a MOVSSmr can be used instead, which is smaller and faster.
6593 if (!Op.hasOneUse())
6595 SDNode *User = *Op.getNode()->use_begin();
6596 if ((User->getOpcode() != ISD::STORE ||
6597 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6598 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6599 (User->getOpcode() != ISD::BITCAST ||
6600 User->getValueType(0) != MVT::i32))
6602 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6603 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6606 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6607 } else if (VT == MVT::i32 || VT == MVT::i64) {
6608 // ExtractPS/pextrq works with constant index.
6609 if (isa<ConstantSDNode>(Op.getOperand(1)))
6617 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6618 SelectionDAG &DAG) const {
6619 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6622 SDValue Vec = Op.getOperand(0);
6623 EVT VecVT = Vec.getValueType();
6625 // If this is a 256-bit vector result, first extract the 128-bit vector and
6626 // then extract the element from the 128-bit vector.
6627 if (VecVT.getSizeInBits() == 256) {
6628 DebugLoc dl = Op.getNode()->getDebugLoc();
6629 unsigned NumElems = VecVT.getVectorNumElements();
6630 SDValue Idx = Op.getOperand(1);
6631 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6633 // Get the 128-bit vector.
6634 bool Upper = IdxVal >= NumElems/2;
6635 Vec = Extract128BitVector(Vec,
6636 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6638 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6639 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6642 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6644 if (Subtarget->hasSSE41()) {
6645 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6650 EVT VT = Op.getValueType();
6651 DebugLoc dl = Op.getDebugLoc();
6652 // TODO: handle v16i8.
6653 if (VT.getSizeInBits() == 16) {
6654 SDValue Vec = Op.getOperand(0);
6655 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6657 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6658 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6659 DAG.getNode(ISD::BITCAST, dl,
6662 // Transform it so it match pextrw which produces a 32-bit result.
6663 EVT EltVT = MVT::i32;
6664 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6665 Op.getOperand(0), Op.getOperand(1));
6666 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6667 DAG.getValueType(VT));
6668 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6669 } else if (VT.getSizeInBits() == 32) {
6670 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6674 // SHUFPS the element to the lowest double word, then movss.
6675 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6676 EVT VVT = Op.getOperand(0).getValueType();
6677 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6678 DAG.getUNDEF(VVT), Mask);
6679 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6680 DAG.getIntPtrConstant(0));
6681 } else if (VT.getSizeInBits() == 64) {
6682 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6683 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6684 // to match extract_elt for f64.
6685 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6689 // UNPCKHPD the element to the lowest double word, then movsd.
6690 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6691 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6692 int Mask[2] = { 1, -1 };
6693 EVT VVT = Op.getOperand(0).getValueType();
6694 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6695 DAG.getUNDEF(VVT), Mask);
6696 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6697 DAG.getIntPtrConstant(0));
6704 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6705 SelectionDAG &DAG) const {
6706 EVT VT = Op.getValueType();
6707 EVT EltVT = VT.getVectorElementType();
6708 DebugLoc dl = Op.getDebugLoc();
6710 SDValue N0 = Op.getOperand(0);
6711 SDValue N1 = Op.getOperand(1);
6712 SDValue N2 = Op.getOperand(2);
6714 if (VT.getSizeInBits() == 256)
6717 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6718 isa<ConstantSDNode>(N2)) {
6720 if (VT == MVT::v8i16)
6721 Opc = X86ISD::PINSRW;
6722 else if (VT == MVT::v16i8)
6723 Opc = X86ISD::PINSRB;
6725 Opc = X86ISD::PINSRB;
6727 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6729 if (N1.getValueType() != MVT::i32)
6730 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6731 if (N2.getValueType() != MVT::i32)
6732 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6733 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6734 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6735 // Bits [7:6] of the constant are the source select. This will always be
6736 // zero here. The DAG Combiner may combine an extract_elt index into these
6737 // bits. For example (insert (extract, 3), 2) could be matched by putting
6738 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6739 // Bits [5:4] of the constant are the destination select. This is the
6740 // value of the incoming immediate.
6741 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6742 // combine either bitwise AND or insert of float 0.0 to set these bits.
6743 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6744 // Create this as a scalar to vector..
6745 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6746 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6747 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6748 isa<ConstantSDNode>(N2)) {
6749 // PINSR* works with constant index.
6756 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6757 EVT VT = Op.getValueType();
6758 EVT EltVT = VT.getVectorElementType();
6760 DebugLoc dl = Op.getDebugLoc();
6761 SDValue N0 = Op.getOperand(0);
6762 SDValue N1 = Op.getOperand(1);
6763 SDValue N2 = Op.getOperand(2);
6765 // If this is a 256-bit vector result, first extract the 128-bit vector,
6766 // insert the element into the extracted half and then place it back.
6767 if (VT.getSizeInBits() == 256) {
6768 if (!isa<ConstantSDNode>(N2))
6771 // Get the desired 128-bit vector half.
6772 unsigned NumElems = VT.getVectorNumElements();
6773 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6774 bool Upper = IdxVal >= NumElems/2;
6775 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6776 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6778 // Insert the element into the desired half.
6779 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6780 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6782 // Insert the changed part back to the 256-bit vector
6783 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6786 if (Subtarget->hasSSE41())
6787 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6789 if (EltVT == MVT::i8)
6792 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6793 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6794 // as its second argument.
6795 if (N1.getValueType() != MVT::i32)
6796 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6797 if (N2.getValueType() != MVT::i32)
6798 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6799 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6805 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6806 LLVMContext *Context = DAG.getContext();
6807 DebugLoc dl = Op.getDebugLoc();
6808 EVT OpVT = Op.getValueType();
6810 // If this is a 256-bit vector result, first insert into a 128-bit
6811 // vector and then insert into the 256-bit vector.
6812 if (OpVT.getSizeInBits() > 128) {
6813 // Insert into a 128-bit vector.
6814 EVT VT128 = EVT::getVectorVT(*Context,
6815 OpVT.getVectorElementType(),
6816 OpVT.getVectorNumElements() / 2);
6818 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6820 // Insert the 128-bit vector.
6821 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6822 DAG.getConstant(0, MVT::i32),
6826 if (Op.getValueType() == MVT::v1i64 &&
6827 Op.getOperand(0).getValueType() == MVT::i64)
6828 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6830 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6831 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6832 "Expected an SSE type!");
6833 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6834 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6837 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6838 // a simple subregister reference or explicit instructions to grab
6839 // upper bits of a vector.
6841 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6842 if (Subtarget->hasAVX()) {
6843 DebugLoc dl = Op.getNode()->getDebugLoc();
6844 SDValue Vec = Op.getNode()->getOperand(0);
6845 SDValue Idx = Op.getNode()->getOperand(1);
6847 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6848 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6849 return Extract128BitVector(Vec, Idx, DAG, dl);
6855 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6856 // simple superregister reference or explicit instructions to insert
6857 // the upper bits of a vector.
6859 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6860 if (Subtarget->hasAVX()) {
6861 DebugLoc dl = Op.getNode()->getDebugLoc();
6862 SDValue Vec = Op.getNode()->getOperand(0);
6863 SDValue SubVec = Op.getNode()->getOperand(1);
6864 SDValue Idx = Op.getNode()->getOperand(2);
6866 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6867 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6868 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6874 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6875 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6876 // one of the above mentioned nodes. It has to be wrapped because otherwise
6877 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6878 // be used to form addressing mode. These wrapped nodes will be selected
6881 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6882 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6884 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6886 unsigned char OpFlag = 0;
6887 unsigned WrapperKind = X86ISD::Wrapper;
6888 CodeModel::Model M = getTargetMachine().getCodeModel();
6890 if (Subtarget->isPICStyleRIPRel() &&
6891 (M == CodeModel::Small || M == CodeModel::Kernel))
6892 WrapperKind = X86ISD::WrapperRIP;
6893 else if (Subtarget->isPICStyleGOT())
6894 OpFlag = X86II::MO_GOTOFF;
6895 else if (Subtarget->isPICStyleStubPIC())
6896 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6898 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6900 CP->getOffset(), OpFlag);
6901 DebugLoc DL = CP->getDebugLoc();
6902 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6903 // With PIC, the address is actually $g + Offset.
6905 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6906 DAG.getNode(X86ISD::GlobalBaseReg,
6907 DebugLoc(), getPointerTy()),
6914 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6915 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6917 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6919 unsigned char OpFlag = 0;
6920 unsigned WrapperKind = X86ISD::Wrapper;
6921 CodeModel::Model M = getTargetMachine().getCodeModel();
6923 if (Subtarget->isPICStyleRIPRel() &&
6924 (M == CodeModel::Small || M == CodeModel::Kernel))
6925 WrapperKind = X86ISD::WrapperRIP;
6926 else if (Subtarget->isPICStyleGOT())
6927 OpFlag = X86II::MO_GOTOFF;
6928 else if (Subtarget->isPICStyleStubPIC())
6929 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6931 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6933 DebugLoc DL = JT->getDebugLoc();
6934 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6936 // With PIC, the address is actually $g + Offset.
6938 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6939 DAG.getNode(X86ISD::GlobalBaseReg,
6940 DebugLoc(), getPointerTy()),
6947 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
6948 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
6950 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6952 unsigned char OpFlag = 0;
6953 unsigned WrapperKind = X86ISD::Wrapper;
6954 CodeModel::Model M = getTargetMachine().getCodeModel();
6956 if (Subtarget->isPICStyleRIPRel() &&
6957 (M == CodeModel::Small || M == CodeModel::Kernel)) {
6958 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
6959 OpFlag = X86II::MO_GOTPCREL;
6960 WrapperKind = X86ISD::WrapperRIP;
6961 } else if (Subtarget->isPICStyleGOT()) {
6962 OpFlag = X86II::MO_GOT;
6963 } else if (Subtarget->isPICStyleStubPIC()) {
6964 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
6965 } else if (Subtarget->isPICStyleStubNoDynamic()) {
6966 OpFlag = X86II::MO_DARWIN_NONLAZY;
6969 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
6971 DebugLoc DL = Op.getDebugLoc();
6972 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6975 // With PIC, the address is actually $g + Offset.
6976 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
6977 !Subtarget->is64Bit()) {
6978 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6979 DAG.getNode(X86ISD::GlobalBaseReg,
6980 DebugLoc(), getPointerTy()),
6984 // For symbols that require a load from a stub to get the address, emit the
6986 if (isGlobalStubReference(OpFlag))
6987 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
6988 MachinePointerInfo::getGOT(), false, false, false, 0);
6994 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
6995 // Create the TargetBlockAddressAddress node.
6996 unsigned char OpFlags =
6997 Subtarget->ClassifyBlockAddressReference();
6998 CodeModel::Model M = getTargetMachine().getCodeModel();
6999 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7000 DebugLoc dl = Op.getDebugLoc();
7001 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7002 /*isTarget=*/true, OpFlags);
7004 if (Subtarget->isPICStyleRIPRel() &&
7005 (M == CodeModel::Small || M == CodeModel::Kernel))
7006 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7008 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7010 // With PIC, the address is actually $g + Offset.
7011 if (isGlobalRelativeToPICBase(OpFlags)) {
7012 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7013 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7021 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7023 SelectionDAG &DAG) const {
7024 // Create the TargetGlobalAddress node, folding in the constant
7025 // offset if it is legal.
7026 unsigned char OpFlags =
7027 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7028 CodeModel::Model M = getTargetMachine().getCodeModel();
7030 if (OpFlags == X86II::MO_NO_FLAG &&
7031 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7032 // A direct static reference to a global.
7033 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7036 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7039 if (Subtarget->isPICStyleRIPRel() &&
7040 (M == CodeModel::Small || M == CodeModel::Kernel))
7041 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7043 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7045 // With PIC, the address is actually $g + Offset.
7046 if (isGlobalRelativeToPICBase(OpFlags)) {
7047 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7048 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7052 // For globals that require a load from a stub to get the address, emit the
7054 if (isGlobalStubReference(OpFlags))
7055 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7056 MachinePointerInfo::getGOT(), false, false, false, 0);
7058 // If there was a non-zero offset that we didn't fold, create an explicit
7061 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7062 DAG.getConstant(Offset, getPointerTy()));
7068 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7069 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7070 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7071 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7075 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7076 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7077 unsigned char OperandFlags) {
7078 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7079 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7080 DebugLoc dl = GA->getDebugLoc();
7081 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7082 GA->getValueType(0),
7086 SDValue Ops[] = { Chain, TGA, *InFlag };
7087 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7089 SDValue Ops[] = { Chain, TGA };
7090 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7093 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7094 MFI->setAdjustsStack(true);
7096 SDValue Flag = Chain.getValue(1);
7097 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7100 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7102 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7105 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7106 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7107 DAG.getNode(X86ISD::GlobalBaseReg,
7108 DebugLoc(), PtrVT), InFlag);
7109 InFlag = Chain.getValue(1);
7111 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7114 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7116 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7118 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7119 X86::RAX, X86II::MO_TLSGD);
7122 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7123 // "local exec" model.
7124 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7125 const EVT PtrVT, TLSModel::Model model,
7127 DebugLoc dl = GA->getDebugLoc();
7129 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7130 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7131 is64Bit ? 257 : 256));
7133 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7134 DAG.getIntPtrConstant(0),
7135 MachinePointerInfo(Ptr),
7136 false, false, false, 0);
7138 unsigned char OperandFlags = 0;
7139 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7141 unsigned WrapperKind = X86ISD::Wrapper;
7142 if (model == TLSModel::LocalExec) {
7143 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7144 } else if (is64Bit) {
7145 assert(model == TLSModel::InitialExec);
7146 OperandFlags = X86II::MO_GOTTPOFF;
7147 WrapperKind = X86ISD::WrapperRIP;
7149 assert(model == TLSModel::InitialExec);
7150 OperandFlags = X86II::MO_INDNTPOFF;
7153 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7155 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7156 GA->getValueType(0),
7157 GA->getOffset(), OperandFlags);
7158 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7160 if (model == TLSModel::InitialExec)
7161 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7162 MachinePointerInfo::getGOT(), false, false, false, 0);
7164 // The address of the thread local variable is the add of the thread
7165 // pointer with the offset of the variable.
7166 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7170 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7172 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7173 const GlobalValue *GV = GA->getGlobal();
7175 if (Subtarget->isTargetELF()) {
7176 // TODO: implement the "local dynamic" model
7177 // TODO: implement the "initial exec"model for pic executables
7179 // If GV is an alias then use the aliasee for determining
7180 // thread-localness.
7181 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7182 GV = GA->resolveAliasedGlobal(false);
7184 TLSModel::Model model
7185 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7188 case TLSModel::GeneralDynamic:
7189 case TLSModel::LocalDynamic: // not implemented
7190 if (Subtarget->is64Bit())
7191 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7192 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7194 case TLSModel::InitialExec:
7195 case TLSModel::LocalExec:
7196 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7197 Subtarget->is64Bit());
7199 } else if (Subtarget->isTargetDarwin()) {
7200 // Darwin only has one model of TLS. Lower to that.
7201 unsigned char OpFlag = 0;
7202 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7203 X86ISD::WrapperRIP : X86ISD::Wrapper;
7205 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7207 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7208 !Subtarget->is64Bit();
7210 OpFlag = X86II::MO_TLVP_PIC_BASE;
7212 OpFlag = X86II::MO_TLVP;
7213 DebugLoc DL = Op.getDebugLoc();
7214 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7215 GA->getValueType(0),
7216 GA->getOffset(), OpFlag);
7217 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7219 // With PIC32, the address is actually $g + Offset.
7221 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7222 DAG.getNode(X86ISD::GlobalBaseReg,
7223 DebugLoc(), getPointerTy()),
7226 // Lowering the machine isd will make sure everything is in the right
7228 SDValue Chain = DAG.getEntryNode();
7229 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7230 SDValue Args[] = { Chain, Offset };
7231 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7233 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7234 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7235 MFI->setAdjustsStack(true);
7237 // And our return value (tls address) is in the standard call return value
7239 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7240 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7242 } else if (Subtarget->isTargetWindows()) {
7243 // Just use the implicit TLS architecture
7244 // Need to generate someting similar to:
7245 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7247 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7248 // mov rcx, qword [rdx+rcx*8]
7249 // mov eax, .tls$:tlsvar
7250 // [rax+rcx] contains the address
7251 // Windows 64bit: gs:0x58
7252 // Windows 32bit: fs:__tls_array
7254 // If GV is an alias then use the aliasee for determining
7255 // thread-localness.
7256 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7257 GV = GA->resolveAliasedGlobal(false);
7258 DebugLoc dl = GA->getDebugLoc();
7259 SDValue Chain = DAG.getEntryNode();
7261 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7262 // %gs:0x58 (64-bit).
7263 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7264 ? Type::getInt8PtrTy(*DAG.getContext(),
7266 : Type::getInt32PtrTy(*DAG.getContext(),
7269 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7270 Subtarget->is64Bit()
7271 ? DAG.getIntPtrConstant(0x58)
7272 : DAG.getExternalSymbol("_tls_array",
7274 MachinePointerInfo(Ptr),
7275 false, false, false, 0);
7277 // Load the _tls_index variable
7278 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7279 if (Subtarget->is64Bit())
7280 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7281 IDX, MachinePointerInfo(), MVT::i32,
7284 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7285 false, false, false, 0);
7287 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7289 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7291 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7292 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7293 false, false, false, 0);
7295 // Get the offset of start of .tls section
7296 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7297 GA->getValueType(0),
7298 GA->getOffset(), X86II::MO_SECREL);
7299 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7301 // The address of the thread local variable is the add of the thread
7302 // pointer with the offset of the variable.
7303 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7306 llvm_unreachable("TLS not implemented for this target.");
7310 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7311 /// and take a 2 x i32 value to shift plus a shift amount.
7312 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7313 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7314 EVT VT = Op.getValueType();
7315 unsigned VTBits = VT.getSizeInBits();
7316 DebugLoc dl = Op.getDebugLoc();
7317 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7318 SDValue ShOpLo = Op.getOperand(0);
7319 SDValue ShOpHi = Op.getOperand(1);
7320 SDValue ShAmt = Op.getOperand(2);
7321 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7322 DAG.getConstant(VTBits - 1, MVT::i8))
7323 : DAG.getConstant(0, VT);
7326 if (Op.getOpcode() == ISD::SHL_PARTS) {
7327 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7328 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7330 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7331 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7334 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7335 DAG.getConstant(VTBits, MVT::i8));
7336 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7337 AndNode, DAG.getConstant(0, MVT::i8));
7340 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7341 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7342 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7344 if (Op.getOpcode() == ISD::SHL_PARTS) {
7345 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7346 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7348 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7349 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7352 SDValue Ops[2] = { Lo, Hi };
7353 return DAG.getMergeValues(Ops, 2, dl);
7356 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7357 SelectionDAG &DAG) const {
7358 EVT SrcVT = Op.getOperand(0).getValueType();
7360 if (SrcVT.isVector())
7363 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7364 "Unknown SINT_TO_FP to lower!");
7366 // These are really Legal; return the operand so the caller accepts it as
7368 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7370 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7371 Subtarget->is64Bit()) {
7375 DebugLoc dl = Op.getDebugLoc();
7376 unsigned Size = SrcVT.getSizeInBits()/8;
7377 MachineFunction &MF = DAG.getMachineFunction();
7378 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7379 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7380 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7382 MachinePointerInfo::getFixedStack(SSFI),
7384 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7387 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7389 SelectionDAG &DAG) const {
7391 DebugLoc DL = Op.getDebugLoc();
7393 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7395 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7397 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7399 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7401 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7402 MachineMemOperand *MMO;
7404 int SSFI = FI->getIndex();
7406 DAG.getMachineFunction()
7407 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7408 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7410 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7411 StackSlot = StackSlot.getOperand(1);
7413 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7414 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7416 Tys, Ops, array_lengthof(Ops),
7420 Chain = Result.getValue(1);
7421 SDValue InFlag = Result.getValue(2);
7423 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7424 // shouldn't be necessary except that RFP cannot be live across
7425 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7426 MachineFunction &MF = DAG.getMachineFunction();
7427 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7428 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7429 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7430 Tys = DAG.getVTList(MVT::Other);
7432 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7434 MachineMemOperand *MMO =
7435 DAG.getMachineFunction()
7436 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7437 MachineMemOperand::MOStore, SSFISize, SSFISize);
7439 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7440 Ops, array_lengthof(Ops),
7441 Op.getValueType(), MMO);
7442 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7443 MachinePointerInfo::getFixedStack(SSFI),
7444 false, false, false, 0);
7450 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7451 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7452 SelectionDAG &DAG) const {
7453 // This algorithm is not obvious. Here it is what we're trying to output:
7456 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7457 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7461 pshufd $0x4e, %xmm0, %xmm1
7466 DebugLoc dl = Op.getDebugLoc();
7467 LLVMContext *Context = DAG.getContext();
7469 // Build some magic constants.
7470 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7471 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7472 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7474 SmallVector<Constant*,2> CV1;
7476 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7478 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7479 Constant *C1 = ConstantVector::get(CV1);
7480 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7482 // Load the 64-bit value into an XMM register.
7483 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7485 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7486 MachinePointerInfo::getConstantPool(),
7487 false, false, false, 16);
7488 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7489 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7492 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7493 MachinePointerInfo::getConstantPool(),
7494 false, false, false, 16);
7495 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7496 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7499 if (Subtarget->hasSSE3()) {
7500 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7501 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7503 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7504 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7506 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7507 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7511 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7512 DAG.getIntPtrConstant(0));
7515 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7516 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7517 SelectionDAG &DAG) const {
7518 DebugLoc dl = Op.getDebugLoc();
7519 // FP constant to bias correct the final result.
7520 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7523 // Load the 32-bit value into an XMM register.
7524 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7527 // Zero out the upper parts of the register.
7528 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7530 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7531 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7532 DAG.getIntPtrConstant(0));
7534 // Or the load with the bias.
7535 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7536 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7537 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7539 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7540 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7541 MVT::v2f64, Bias)));
7542 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7543 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7544 DAG.getIntPtrConstant(0));
7546 // Subtract the bias.
7547 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7549 // Handle final rounding.
7550 EVT DestVT = Op.getValueType();
7552 if (DestVT.bitsLT(MVT::f64)) {
7553 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7554 DAG.getIntPtrConstant(0));
7555 } else if (DestVT.bitsGT(MVT::f64)) {
7556 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7559 // Handle final rounding.
7563 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7564 SelectionDAG &DAG) const {
7565 SDValue N0 = Op.getOperand(0);
7566 DebugLoc dl = Op.getDebugLoc();
7568 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7569 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7570 // the optimization here.
7571 if (DAG.SignBitIsZero(N0))
7572 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7574 EVT SrcVT = N0.getValueType();
7575 EVT DstVT = Op.getValueType();
7576 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7577 return LowerUINT_TO_FP_i64(Op, DAG);
7578 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7579 return LowerUINT_TO_FP_i32(Op, DAG);
7580 else if (Subtarget->is64Bit() &&
7581 SrcVT == MVT::i64 && DstVT == MVT::f32)
7584 // Make a 64-bit buffer, and use it to build an FILD.
7585 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7586 if (SrcVT == MVT::i32) {
7587 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7588 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7589 getPointerTy(), StackSlot, WordOff);
7590 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7591 StackSlot, MachinePointerInfo(),
7593 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7594 OffsetSlot, MachinePointerInfo(),
7596 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7600 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7601 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7602 StackSlot, MachinePointerInfo(),
7604 // For i64 source, we need to add the appropriate power of 2 if the input
7605 // was negative. This is the same as the optimization in
7606 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7607 // we must be careful to do the computation in x87 extended precision, not
7608 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7609 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7610 MachineMemOperand *MMO =
7611 DAG.getMachineFunction()
7612 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7613 MachineMemOperand::MOLoad, 8, 8);
7615 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7616 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7617 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7620 APInt FF(32, 0x5F800000ULL);
7622 // Check whether the sign bit is set.
7623 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7624 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7627 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7628 SDValue FudgePtr = DAG.getConstantPool(
7629 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7632 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7633 SDValue Zero = DAG.getIntPtrConstant(0);
7634 SDValue Four = DAG.getIntPtrConstant(4);
7635 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7637 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7639 // Load the value out, extending it from f32 to f80.
7640 // FIXME: Avoid the extend by constructing the right constant pool?
7641 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7642 FudgePtr, MachinePointerInfo::getConstantPool(),
7643 MVT::f32, false, false, 4);
7644 // Extend everything to 80 bits to force it to be done on x87.
7645 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7646 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7649 std::pair<SDValue,SDValue> X86TargetLowering::
7650 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7651 DebugLoc DL = Op.getDebugLoc();
7653 EVT DstTy = Op.getValueType();
7655 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7656 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7660 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7661 DstTy.getSimpleVT() >= MVT::i16 &&
7662 "Unknown FP_TO_INT to lower!");
7664 // These are really Legal.
7665 if (DstTy == MVT::i32 &&
7666 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7667 return std::make_pair(SDValue(), SDValue());
7668 if (Subtarget->is64Bit() &&
7669 DstTy == MVT::i64 &&
7670 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7671 return std::make_pair(SDValue(), SDValue());
7673 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7674 // stack slot, or into the FTOL runtime function.
7675 MachineFunction &MF = DAG.getMachineFunction();
7676 unsigned MemSize = DstTy.getSizeInBits()/8;
7677 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7678 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7681 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7682 Opc = X86ISD::WIN_FTOL;
7684 switch (DstTy.getSimpleVT().SimpleTy) {
7685 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7686 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7687 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7688 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7691 SDValue Chain = DAG.getEntryNode();
7692 SDValue Value = Op.getOperand(0);
7693 EVT TheVT = Op.getOperand(0).getValueType();
7694 // FIXME This causes a redundant load/store if the SSE-class value is already
7695 // in memory, such as if it is on the callstack.
7696 if (isScalarFPTypeInSSEReg(TheVT)) {
7697 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7698 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7699 MachinePointerInfo::getFixedStack(SSFI),
7701 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7703 Chain, StackSlot, DAG.getValueType(TheVT)
7706 MachineMemOperand *MMO =
7707 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7708 MachineMemOperand::MOLoad, MemSize, MemSize);
7709 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7711 Chain = Value.getValue(1);
7712 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7713 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7716 MachineMemOperand *MMO =
7717 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7718 MachineMemOperand::MOStore, MemSize, MemSize);
7720 if (Opc != X86ISD::WIN_FTOL) {
7721 // Build the FP_TO_INT*_IN_MEM
7722 SDValue Ops[] = { Chain, Value, StackSlot };
7723 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7724 Ops, 3, DstTy, MMO);
7725 return std::make_pair(FIST, StackSlot);
7727 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7728 DAG.getVTList(MVT::Other, MVT::Glue),
7730 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7731 MVT::i32, ftol.getValue(1));
7732 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7733 MVT::i32, eax.getValue(2));
7734 SDValue Ops[] = { eax, edx };
7735 SDValue pair = IsReplace
7736 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7737 : DAG.getMergeValues(Ops, 2, DL);
7738 return std::make_pair(pair, SDValue());
7742 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7743 SelectionDAG &DAG) const {
7744 if (Op.getValueType().isVector())
7747 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7748 /*IsSigned=*/ true, /*IsReplace=*/ false);
7749 SDValue FIST = Vals.first, StackSlot = Vals.second;
7750 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7751 if (FIST.getNode() == 0) return Op;
7753 if (StackSlot.getNode())
7755 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7756 FIST, StackSlot, MachinePointerInfo(),
7757 false, false, false, 0);
7759 // The node is the result.
7763 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7764 SelectionDAG &DAG) const {
7765 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7766 /*IsSigned=*/ false, /*IsReplace=*/ false);
7767 SDValue FIST = Vals.first, StackSlot = Vals.second;
7768 assert(FIST.getNode() && "Unexpected failure");
7770 if (StackSlot.getNode())
7772 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7773 FIST, StackSlot, MachinePointerInfo(),
7774 false, false, false, 0);
7776 // The node is the result.
7780 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7781 SelectionDAG &DAG) const {
7782 LLVMContext *Context = DAG.getContext();
7783 DebugLoc dl = Op.getDebugLoc();
7784 EVT VT = Op.getValueType();
7787 EltVT = VT.getVectorElementType();
7789 if (EltVT == MVT::f64) {
7790 C = ConstantVector::getSplat(2,
7791 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7793 C = ConstantVector::getSplat(4,
7794 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7796 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7797 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7798 MachinePointerInfo::getConstantPool(),
7799 false, false, false, 16);
7800 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7803 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7804 LLVMContext *Context = DAG.getContext();
7805 DebugLoc dl = Op.getDebugLoc();
7806 EVT VT = Op.getValueType();
7808 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7809 if (VT.isVector()) {
7810 EltVT = VT.getVectorElementType();
7811 NumElts = VT.getVectorNumElements();
7814 if (EltVT == MVT::f64)
7815 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7817 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7818 C = ConstantVector::getSplat(NumElts, C);
7819 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7820 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7821 MachinePointerInfo::getConstantPool(),
7822 false, false, false, 16);
7823 if (VT.isVector()) {
7824 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7825 return DAG.getNode(ISD::BITCAST, dl, VT,
7826 DAG.getNode(ISD::XOR, dl, XORVT,
7827 DAG.getNode(ISD::BITCAST, dl, XORVT,
7829 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7831 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7835 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7836 LLVMContext *Context = DAG.getContext();
7837 SDValue Op0 = Op.getOperand(0);
7838 SDValue Op1 = Op.getOperand(1);
7839 DebugLoc dl = Op.getDebugLoc();
7840 EVT VT = Op.getValueType();
7841 EVT SrcVT = Op1.getValueType();
7843 // If second operand is smaller, extend it first.
7844 if (SrcVT.bitsLT(VT)) {
7845 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7848 // And if it is bigger, shrink it first.
7849 if (SrcVT.bitsGT(VT)) {
7850 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7854 // At this point the operands and the result should have the same
7855 // type, and that won't be f80 since that is not custom lowered.
7857 // First get the sign bit of second operand.
7858 SmallVector<Constant*,4> CV;
7859 if (SrcVT == MVT::f64) {
7860 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7861 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7863 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7864 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7865 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7866 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7868 Constant *C = ConstantVector::get(CV);
7869 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7870 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7871 MachinePointerInfo::getConstantPool(),
7872 false, false, false, 16);
7873 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7875 // Shift sign bit right or left if the two operands have different types.
7876 if (SrcVT.bitsGT(VT)) {
7877 // Op0 is MVT::f32, Op1 is MVT::f64.
7878 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7879 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7880 DAG.getConstant(32, MVT::i32));
7881 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7882 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7883 DAG.getIntPtrConstant(0));
7886 // Clear first operand sign bit.
7888 if (VT == MVT::f64) {
7889 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7890 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7892 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7893 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7894 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7895 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7897 C = ConstantVector::get(CV);
7898 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7899 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7900 MachinePointerInfo::getConstantPool(),
7901 false, false, false, 16);
7902 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7904 // Or the value with the sign bit.
7905 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7908 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7909 SDValue N0 = Op.getOperand(0);
7910 DebugLoc dl = Op.getDebugLoc();
7911 EVT VT = Op.getValueType();
7913 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7914 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7915 DAG.getConstant(1, VT));
7916 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7919 /// Emit nodes that will be selected as "test Op0,Op0", or something
7921 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7922 SelectionDAG &DAG) const {
7923 DebugLoc dl = Op.getDebugLoc();
7925 // CF and OF aren't always set the way we want. Determine which
7926 // of these we need.
7927 bool NeedCF = false;
7928 bool NeedOF = false;
7931 case X86::COND_A: case X86::COND_AE:
7932 case X86::COND_B: case X86::COND_BE:
7935 case X86::COND_G: case X86::COND_GE:
7936 case X86::COND_L: case X86::COND_LE:
7937 case X86::COND_O: case X86::COND_NO:
7942 // See if we can use the EFLAGS value from the operand instead of
7943 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
7944 // we prove that the arithmetic won't overflow, we can't use OF or CF.
7945 if (Op.getResNo() != 0 || NeedOF || NeedCF)
7946 // Emit a CMP with 0, which is the TEST pattern.
7947 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
7948 DAG.getConstant(0, Op.getValueType()));
7950 unsigned Opcode = 0;
7951 unsigned NumOperands = 0;
7952 switch (Op.getNode()->getOpcode()) {
7954 // Due to an isel shortcoming, be conservative if this add is likely to be
7955 // selected as part of a load-modify-store instruction. When the root node
7956 // in a match is a store, isel doesn't know how to remap non-chain non-flag
7957 // uses of other nodes in the match, such as the ADD in this case. This
7958 // leads to the ADD being left around and reselected, with the result being
7959 // two adds in the output. Alas, even if none our users are stores, that
7960 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
7961 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
7962 // climbing the DAG back to the root, and it doesn't seem to be worth the
7964 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7965 UE = Op.getNode()->use_end(); UI != UE; ++UI)
7966 if (UI->getOpcode() != ISD::CopyToReg &&
7967 UI->getOpcode() != ISD::SETCC &&
7968 UI->getOpcode() != ISD::STORE)
7971 if (ConstantSDNode *C =
7972 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
7973 // An add of one will be selected as an INC.
7974 if (C->getAPIntValue() == 1) {
7975 Opcode = X86ISD::INC;
7980 // An add of negative one (subtract of one) will be selected as a DEC.
7981 if (C->getAPIntValue().isAllOnesValue()) {
7982 Opcode = X86ISD::DEC;
7988 // Otherwise use a regular EFLAGS-setting add.
7989 Opcode = X86ISD::ADD;
7993 // If the primary and result isn't used, don't bother using X86ISD::AND,
7994 // because a TEST instruction will be better.
7995 bool NonFlagUse = false;
7996 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
7997 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
7999 unsigned UOpNo = UI.getOperandNo();
8000 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8001 // Look pass truncate.
8002 UOpNo = User->use_begin().getOperandNo();
8003 User = *User->use_begin();
8006 if (User->getOpcode() != ISD::BRCOND &&
8007 User->getOpcode() != ISD::SETCC &&
8008 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8021 // Due to the ISEL shortcoming noted above, be conservative if this op is
8022 // likely to be selected as part of a load-modify-store instruction.
8023 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8024 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8025 if (UI->getOpcode() == ISD::STORE)
8028 // Otherwise use a regular EFLAGS-setting instruction.
8029 switch (Op.getNode()->getOpcode()) {
8030 default: llvm_unreachable("unexpected operator!");
8031 case ISD::SUB: Opcode = X86ISD::SUB; break;
8032 case ISD::OR: Opcode = X86ISD::OR; break;
8033 case ISD::XOR: Opcode = X86ISD::XOR; break;
8034 case ISD::AND: Opcode = X86ISD::AND; break;
8046 return SDValue(Op.getNode(), 1);
8053 // Emit a CMP with 0, which is the TEST pattern.
8054 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8055 DAG.getConstant(0, Op.getValueType()));
8057 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8058 SmallVector<SDValue, 4> Ops;
8059 for (unsigned i = 0; i != NumOperands; ++i)
8060 Ops.push_back(Op.getOperand(i));
8062 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8063 DAG.ReplaceAllUsesWith(Op, New);
8064 return SDValue(New.getNode(), 1);
8067 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8069 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8070 SelectionDAG &DAG) const {
8071 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8072 if (C->getAPIntValue() == 0)
8073 return EmitTest(Op0, X86CC, DAG);
8075 DebugLoc dl = Op0.getDebugLoc();
8076 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8079 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8080 /// if it's possible.
8081 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8082 DebugLoc dl, SelectionDAG &DAG) const {
8083 SDValue Op0 = And.getOperand(0);
8084 SDValue Op1 = And.getOperand(1);
8085 if (Op0.getOpcode() == ISD::TRUNCATE)
8086 Op0 = Op0.getOperand(0);
8087 if (Op1.getOpcode() == ISD::TRUNCATE)
8088 Op1 = Op1.getOperand(0);
8091 if (Op1.getOpcode() == ISD::SHL)
8092 std::swap(Op0, Op1);
8093 if (Op0.getOpcode() == ISD::SHL) {
8094 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8095 if (And00C->getZExtValue() == 1) {
8096 // If we looked past a truncate, check that it's only truncating away
8098 unsigned BitWidth = Op0.getValueSizeInBits();
8099 unsigned AndBitWidth = And.getValueSizeInBits();
8100 if (BitWidth > AndBitWidth) {
8101 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8102 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8103 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8107 RHS = Op0.getOperand(1);
8109 } else if (Op1.getOpcode() == ISD::Constant) {
8110 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8111 uint64_t AndRHSVal = AndRHS->getZExtValue();
8112 SDValue AndLHS = Op0;
8114 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8115 LHS = AndLHS.getOperand(0);
8116 RHS = AndLHS.getOperand(1);
8119 // Use BT if the immediate can't be encoded in a TEST instruction.
8120 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8122 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8126 if (LHS.getNode()) {
8127 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8128 // instruction. Since the shift amount is in-range-or-undefined, we know
8129 // that doing a bittest on the i32 value is ok. We extend to i32 because
8130 // the encoding for the i16 version is larger than the i32 version.
8131 // Also promote i16 to i32 for performance / code size reason.
8132 if (LHS.getValueType() == MVT::i8 ||
8133 LHS.getValueType() == MVT::i16)
8134 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8136 // If the operand types disagree, extend the shift amount to match. Since
8137 // BT ignores high bits (like shifts) we can use anyextend.
8138 if (LHS.getValueType() != RHS.getValueType())
8139 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8141 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8142 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8143 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8144 DAG.getConstant(Cond, MVT::i8), BT);
8150 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8152 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8154 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8155 SDValue Op0 = Op.getOperand(0);
8156 SDValue Op1 = Op.getOperand(1);
8157 DebugLoc dl = Op.getDebugLoc();
8158 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8160 // Optimize to BT if possible.
8161 // Lower (X & (1 << N)) == 0 to BT(X, N).
8162 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8163 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8164 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8165 Op1.getOpcode() == ISD::Constant &&
8166 cast<ConstantSDNode>(Op1)->isNullValue() &&
8167 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8168 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8169 if (NewSetCC.getNode())
8173 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8175 if (Op1.getOpcode() == ISD::Constant &&
8176 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8177 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8178 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8180 // If the input is a setcc, then reuse the input setcc or use a new one with
8181 // the inverted condition.
8182 if (Op0.getOpcode() == X86ISD::SETCC) {
8183 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8184 bool Invert = (CC == ISD::SETNE) ^
8185 cast<ConstantSDNode>(Op1)->isNullValue();
8186 if (!Invert) return Op0;
8188 CCode = X86::GetOppositeBranchCondition(CCode);
8189 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8190 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8194 bool isFP = Op1.getValueType().isFloatingPoint();
8195 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8196 if (X86CC == X86::COND_INVALID)
8199 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8200 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8201 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8204 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8205 // ones, and then concatenate the result back.
8206 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8207 EVT VT = Op.getValueType();
8209 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8210 "Unsupported value type for operation");
8212 int NumElems = VT.getVectorNumElements();
8213 DebugLoc dl = Op.getDebugLoc();
8214 SDValue CC = Op.getOperand(2);
8215 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8216 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8218 // Extract the LHS vectors
8219 SDValue LHS = Op.getOperand(0);
8220 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8221 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8223 // Extract the RHS vectors
8224 SDValue RHS = Op.getOperand(1);
8225 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8226 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8228 // Issue the operation on the smaller types and concatenate the result back
8229 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8230 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8231 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8232 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8233 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8237 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8239 SDValue Op0 = Op.getOperand(0);
8240 SDValue Op1 = Op.getOperand(1);
8241 SDValue CC = Op.getOperand(2);
8242 EVT VT = Op.getValueType();
8243 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8244 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8245 DebugLoc dl = Op.getDebugLoc();
8249 EVT EltVT = Op0.getValueType().getVectorElementType();
8250 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8254 // SSE Condition code mapping:
8263 switch (SetCCOpcode) {
8266 case ISD::SETEQ: SSECC = 0; break;
8268 case ISD::SETGT: Swap = true; // Fallthrough
8270 case ISD::SETOLT: SSECC = 1; break;
8272 case ISD::SETGE: Swap = true; // Fallthrough
8274 case ISD::SETOLE: SSECC = 2; break;
8275 case ISD::SETUO: SSECC = 3; break;
8277 case ISD::SETNE: SSECC = 4; break;
8278 case ISD::SETULE: Swap = true;
8279 case ISD::SETUGE: SSECC = 5; break;
8280 case ISD::SETULT: Swap = true;
8281 case ISD::SETUGT: SSECC = 6; break;
8282 case ISD::SETO: SSECC = 7; break;
8285 std::swap(Op0, Op1);
8287 // In the two special cases we can't handle, emit two comparisons.
8289 if (SetCCOpcode == ISD::SETUEQ) {
8291 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8292 DAG.getConstant(3, MVT::i8));
8293 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8294 DAG.getConstant(0, MVT::i8));
8295 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8296 } else if (SetCCOpcode == ISD::SETONE) {
8298 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8299 DAG.getConstant(7, MVT::i8));
8300 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8301 DAG.getConstant(4, MVT::i8));
8302 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8304 llvm_unreachable("Illegal FP comparison");
8306 // Handle all other FP comparisons here.
8307 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8308 DAG.getConstant(SSECC, MVT::i8));
8311 // Break 256-bit integer vector compare into smaller ones.
8312 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8313 return Lower256IntVSETCC(Op, DAG);
8315 // We are handling one of the integer comparisons here. Since SSE only has
8316 // GT and EQ comparisons for integer, swapping operands and multiple
8317 // operations may be required for some comparisons.
8319 bool Swap = false, Invert = false, FlipSigns = false;
8321 switch (SetCCOpcode) {
8323 case ISD::SETNE: Invert = true;
8324 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8325 case ISD::SETLT: Swap = true;
8326 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8327 case ISD::SETGE: Swap = true;
8328 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8329 case ISD::SETULT: Swap = true;
8330 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8331 case ISD::SETUGE: Swap = true;
8332 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8335 std::swap(Op0, Op1);
8337 // Check that the operation in question is available (most are plain SSE2,
8338 // but PCMPGTQ and PCMPEQQ have different requirements).
8339 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8341 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8344 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8345 // bits of the inputs before performing those operations.
8347 EVT EltVT = VT.getVectorElementType();
8348 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8350 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8351 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8353 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8354 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8357 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8359 // If the logical-not of the result is required, perform that now.
8361 Result = DAG.getNOT(dl, Result, VT);
8366 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8367 static bool isX86LogicalCmp(SDValue Op) {
8368 unsigned Opc = Op.getNode()->getOpcode();
8369 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8371 if (Op.getResNo() == 1 &&
8372 (Opc == X86ISD::ADD ||
8373 Opc == X86ISD::SUB ||
8374 Opc == X86ISD::ADC ||
8375 Opc == X86ISD::SBB ||
8376 Opc == X86ISD::SMUL ||
8377 Opc == X86ISD::UMUL ||
8378 Opc == X86ISD::INC ||
8379 Opc == X86ISD::DEC ||
8380 Opc == X86ISD::OR ||
8381 Opc == X86ISD::XOR ||
8382 Opc == X86ISD::AND))
8385 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8391 static bool isZero(SDValue V) {
8392 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8393 return C && C->isNullValue();
8396 static bool isAllOnes(SDValue V) {
8397 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8398 return C && C->isAllOnesValue();
8401 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8402 bool addTest = true;
8403 SDValue Cond = Op.getOperand(0);
8404 SDValue Op1 = Op.getOperand(1);
8405 SDValue Op2 = Op.getOperand(2);
8406 DebugLoc DL = Op.getDebugLoc();
8409 if (Cond.getOpcode() == ISD::SETCC) {
8410 SDValue NewCond = LowerSETCC(Cond, DAG);
8411 if (NewCond.getNode())
8415 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8416 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8417 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8418 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8419 if (Cond.getOpcode() == X86ISD::SETCC &&
8420 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8421 isZero(Cond.getOperand(1).getOperand(1))) {
8422 SDValue Cmp = Cond.getOperand(1);
8424 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8426 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8427 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8428 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8430 SDValue CmpOp0 = Cmp.getOperand(0);
8431 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8432 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8434 SDValue Res = // Res = 0 or -1.
8435 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8436 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8438 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8439 Res = DAG.getNOT(DL, Res, Res.getValueType());
8441 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8442 if (N2C == 0 || !N2C->isNullValue())
8443 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8448 // Look past (and (setcc_carry (cmp ...)), 1).
8449 if (Cond.getOpcode() == ISD::AND &&
8450 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8451 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8452 if (C && C->getAPIntValue() == 1)
8453 Cond = Cond.getOperand(0);
8456 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8457 // setting operand in place of the X86ISD::SETCC.
8458 unsigned CondOpcode = Cond.getOpcode();
8459 if (CondOpcode == X86ISD::SETCC ||
8460 CondOpcode == X86ISD::SETCC_CARRY) {
8461 CC = Cond.getOperand(0);
8463 SDValue Cmp = Cond.getOperand(1);
8464 unsigned Opc = Cmp.getOpcode();
8465 EVT VT = Op.getValueType();
8467 bool IllegalFPCMov = false;
8468 if (VT.isFloatingPoint() && !VT.isVector() &&
8469 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8470 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8472 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8473 Opc == X86ISD::BT) { // FIXME
8477 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8478 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8479 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8480 Cond.getOperand(0).getValueType() != MVT::i8)) {
8481 SDValue LHS = Cond.getOperand(0);
8482 SDValue RHS = Cond.getOperand(1);
8486 switch (CondOpcode) {
8487 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8488 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8489 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8490 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8491 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8492 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8493 default: llvm_unreachable("unexpected overflowing operator");
8495 if (CondOpcode == ISD::UMULO)
8496 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8499 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8501 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8503 if (CondOpcode == ISD::UMULO)
8504 Cond = X86Op.getValue(2);
8506 Cond = X86Op.getValue(1);
8508 CC = DAG.getConstant(X86Cond, MVT::i8);
8513 // Look pass the truncate.
8514 if (Cond.getOpcode() == ISD::TRUNCATE)
8515 Cond = Cond.getOperand(0);
8517 // We know the result of AND is compared against zero. Try to match
8519 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8520 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8521 if (NewSetCC.getNode()) {
8522 CC = NewSetCC.getOperand(0);
8523 Cond = NewSetCC.getOperand(1);
8530 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8531 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8534 // a < b ? -1 : 0 -> RES = ~setcc_carry
8535 // a < b ? 0 : -1 -> RES = setcc_carry
8536 // a >= b ? -1 : 0 -> RES = setcc_carry
8537 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8538 if (Cond.getOpcode() == X86ISD::CMP) {
8539 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8541 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8542 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8543 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8544 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8545 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8546 return DAG.getNOT(DL, Res, Res.getValueType());
8551 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8552 // condition is true.
8553 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8554 SDValue Ops[] = { Op2, Op1, CC, Cond };
8555 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8558 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8559 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8560 // from the AND / OR.
8561 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8562 Opc = Op.getOpcode();
8563 if (Opc != ISD::OR && Opc != ISD::AND)
8565 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8566 Op.getOperand(0).hasOneUse() &&
8567 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8568 Op.getOperand(1).hasOneUse());
8571 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8572 // 1 and that the SETCC node has a single use.
8573 static bool isXor1OfSetCC(SDValue Op) {
8574 if (Op.getOpcode() != ISD::XOR)
8576 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8577 if (N1C && N1C->getAPIntValue() == 1) {
8578 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8579 Op.getOperand(0).hasOneUse();
8584 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8585 bool addTest = true;
8586 SDValue Chain = Op.getOperand(0);
8587 SDValue Cond = Op.getOperand(1);
8588 SDValue Dest = Op.getOperand(2);
8589 DebugLoc dl = Op.getDebugLoc();
8591 bool Inverted = false;
8593 if (Cond.getOpcode() == ISD::SETCC) {
8594 // Check for setcc([su]{add,sub,mul}o == 0).
8595 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8596 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8597 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8598 Cond.getOperand(0).getResNo() == 1 &&
8599 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8600 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8601 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8602 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8603 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8604 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8606 Cond = Cond.getOperand(0);
8608 SDValue NewCond = LowerSETCC(Cond, DAG);
8609 if (NewCond.getNode())
8614 // FIXME: LowerXALUO doesn't handle these!!
8615 else if (Cond.getOpcode() == X86ISD::ADD ||
8616 Cond.getOpcode() == X86ISD::SUB ||
8617 Cond.getOpcode() == X86ISD::SMUL ||
8618 Cond.getOpcode() == X86ISD::UMUL)
8619 Cond = LowerXALUO(Cond, DAG);
8622 // Look pass (and (setcc_carry (cmp ...)), 1).
8623 if (Cond.getOpcode() == ISD::AND &&
8624 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8625 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8626 if (C && C->getAPIntValue() == 1)
8627 Cond = Cond.getOperand(0);
8630 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8631 // setting operand in place of the X86ISD::SETCC.
8632 unsigned CondOpcode = Cond.getOpcode();
8633 if (CondOpcode == X86ISD::SETCC ||
8634 CondOpcode == X86ISD::SETCC_CARRY) {
8635 CC = Cond.getOperand(0);
8637 SDValue Cmp = Cond.getOperand(1);
8638 unsigned Opc = Cmp.getOpcode();
8639 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8640 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8644 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8648 // These can only come from an arithmetic instruction with overflow,
8649 // e.g. SADDO, UADDO.
8650 Cond = Cond.getNode()->getOperand(1);
8656 CondOpcode = Cond.getOpcode();
8657 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8658 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8659 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8660 Cond.getOperand(0).getValueType() != MVT::i8)) {
8661 SDValue LHS = Cond.getOperand(0);
8662 SDValue RHS = Cond.getOperand(1);
8666 switch (CondOpcode) {
8667 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8668 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8669 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8670 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8671 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8672 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8673 default: llvm_unreachable("unexpected overflowing operator");
8676 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8677 if (CondOpcode == ISD::UMULO)
8678 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8681 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8683 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8685 if (CondOpcode == ISD::UMULO)
8686 Cond = X86Op.getValue(2);
8688 Cond = X86Op.getValue(1);
8690 CC = DAG.getConstant(X86Cond, MVT::i8);
8694 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8695 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8696 if (CondOpc == ISD::OR) {
8697 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8698 // two branches instead of an explicit OR instruction with a
8700 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8701 isX86LogicalCmp(Cmp)) {
8702 CC = Cond.getOperand(0).getOperand(0);
8703 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8704 Chain, Dest, CC, Cmp);
8705 CC = Cond.getOperand(1).getOperand(0);
8709 } else { // ISD::AND
8710 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8711 // two branches instead of an explicit AND instruction with a
8712 // separate test. However, we only do this if this block doesn't
8713 // have a fall-through edge, because this requires an explicit
8714 // jmp when the condition is false.
8715 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8716 isX86LogicalCmp(Cmp) &&
8717 Op.getNode()->hasOneUse()) {
8718 X86::CondCode CCode =
8719 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8720 CCode = X86::GetOppositeBranchCondition(CCode);
8721 CC = DAG.getConstant(CCode, MVT::i8);
8722 SDNode *User = *Op.getNode()->use_begin();
8723 // Look for an unconditional branch following this conditional branch.
8724 // We need this because we need to reverse the successors in order
8725 // to implement FCMP_OEQ.
8726 if (User->getOpcode() == ISD::BR) {
8727 SDValue FalseBB = User->getOperand(1);
8729 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8730 assert(NewBR == User);
8734 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8735 Chain, Dest, CC, Cmp);
8736 X86::CondCode CCode =
8737 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8738 CCode = X86::GetOppositeBranchCondition(CCode);
8739 CC = DAG.getConstant(CCode, MVT::i8);
8745 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8746 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8747 // It should be transformed during dag combiner except when the condition
8748 // is set by a arithmetics with overflow node.
8749 X86::CondCode CCode =
8750 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8751 CCode = X86::GetOppositeBranchCondition(CCode);
8752 CC = DAG.getConstant(CCode, MVT::i8);
8753 Cond = Cond.getOperand(0).getOperand(1);
8755 } else if (Cond.getOpcode() == ISD::SETCC &&
8756 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8757 // For FCMP_OEQ, we can emit
8758 // two branches instead of an explicit AND instruction with a
8759 // separate test. However, we only do this if this block doesn't
8760 // have a fall-through edge, because this requires an explicit
8761 // jmp when the condition is false.
8762 if (Op.getNode()->hasOneUse()) {
8763 SDNode *User = *Op.getNode()->use_begin();
8764 // Look for an unconditional branch following this conditional branch.
8765 // We need this because we need to reverse the successors in order
8766 // to implement FCMP_OEQ.
8767 if (User->getOpcode() == ISD::BR) {
8768 SDValue FalseBB = User->getOperand(1);
8770 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8771 assert(NewBR == User);
8775 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8776 Cond.getOperand(0), Cond.getOperand(1));
8777 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8778 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8779 Chain, Dest, CC, Cmp);
8780 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8785 } else if (Cond.getOpcode() == ISD::SETCC &&
8786 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8787 // For FCMP_UNE, we can emit
8788 // two branches instead of an explicit AND instruction with a
8789 // separate test. However, we only do this if this block doesn't
8790 // have a fall-through edge, because this requires an explicit
8791 // jmp when the condition is false.
8792 if (Op.getNode()->hasOneUse()) {
8793 SDNode *User = *Op.getNode()->use_begin();
8794 // Look for an unconditional branch following this conditional branch.
8795 // We need this because we need to reverse the successors in order
8796 // to implement FCMP_UNE.
8797 if (User->getOpcode() == ISD::BR) {
8798 SDValue FalseBB = User->getOperand(1);
8800 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8801 assert(NewBR == User);
8804 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8805 Cond.getOperand(0), Cond.getOperand(1));
8806 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8807 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8808 Chain, Dest, CC, Cmp);
8809 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8819 // Look pass the truncate.
8820 if (Cond.getOpcode() == ISD::TRUNCATE)
8821 Cond = Cond.getOperand(0);
8823 // We know the result of AND is compared against zero. Try to match
8825 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8826 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8827 if (NewSetCC.getNode()) {
8828 CC = NewSetCC.getOperand(0);
8829 Cond = NewSetCC.getOperand(1);
8836 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8837 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8839 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8840 Chain, Dest, CC, Cond);
8844 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8845 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8846 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8847 // that the guard pages used by the OS virtual memory manager are allocated in
8848 // correct sequence.
8850 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8851 SelectionDAG &DAG) const {
8852 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8853 getTargetMachine().Options.EnableSegmentedStacks) &&
8854 "This should be used only on Windows targets or when segmented stacks "
8856 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8857 DebugLoc dl = Op.getDebugLoc();
8860 SDValue Chain = Op.getOperand(0);
8861 SDValue Size = Op.getOperand(1);
8862 // FIXME: Ensure alignment here
8864 bool Is64Bit = Subtarget->is64Bit();
8865 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8867 if (getTargetMachine().Options.EnableSegmentedStacks) {
8868 MachineFunction &MF = DAG.getMachineFunction();
8869 MachineRegisterInfo &MRI = MF.getRegInfo();
8872 // The 64 bit implementation of segmented stacks needs to clobber both r10
8873 // r11. This makes it impossible to use it along with nested parameters.
8874 const Function *F = MF.getFunction();
8876 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8878 if (I->hasNestAttr())
8879 report_fatal_error("Cannot use segmented stacks with functions that "
8880 "have nested arguments.");
8883 const TargetRegisterClass *AddrRegClass =
8884 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8885 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8886 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8887 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8888 DAG.getRegister(Vreg, SPTy));
8889 SDValue Ops1[2] = { Value, Chain };
8890 return DAG.getMergeValues(Ops1, 2, dl);
8893 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8895 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8896 Flag = Chain.getValue(1);
8897 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8899 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8900 Flag = Chain.getValue(1);
8902 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8904 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8905 return DAG.getMergeValues(Ops1, 2, dl);
8909 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8910 MachineFunction &MF = DAG.getMachineFunction();
8911 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8913 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8914 DebugLoc DL = Op.getDebugLoc();
8916 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8917 // vastart just stores the address of the VarArgsFrameIndex slot into the
8918 // memory location argument.
8919 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8921 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8922 MachinePointerInfo(SV), false, false, 0);
8926 // gp_offset (0 - 6 * 8)
8927 // fp_offset (48 - 48 + 8 * 16)
8928 // overflow_arg_area (point to parameters coming in memory).
8930 SmallVector<SDValue, 8> MemOps;
8931 SDValue FIN = Op.getOperand(1);
8933 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8934 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8936 FIN, MachinePointerInfo(SV), false, false, 0);
8937 MemOps.push_back(Store);
8940 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8941 FIN, DAG.getIntPtrConstant(4));
8942 Store = DAG.getStore(Op.getOperand(0), DL,
8943 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8945 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8946 MemOps.push_back(Store);
8948 // Store ptr to overflow_arg_area
8949 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8950 FIN, DAG.getIntPtrConstant(4));
8951 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8953 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
8954 MachinePointerInfo(SV, 8),
8956 MemOps.push_back(Store);
8958 // Store ptr to reg_save_area.
8959 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8960 FIN, DAG.getIntPtrConstant(8));
8961 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
8963 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
8964 MachinePointerInfo(SV, 16), false, false, 0);
8965 MemOps.push_back(Store);
8966 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
8967 &MemOps[0], MemOps.size());
8970 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
8971 assert(Subtarget->is64Bit() &&
8972 "LowerVAARG only handles 64-bit va_arg!");
8973 assert((Subtarget->isTargetLinux() ||
8974 Subtarget->isTargetDarwin()) &&
8975 "Unhandled target in LowerVAARG");
8976 assert(Op.getNode()->getNumOperands() == 4);
8977 SDValue Chain = Op.getOperand(0);
8978 SDValue SrcPtr = Op.getOperand(1);
8979 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8980 unsigned Align = Op.getConstantOperandVal(3);
8981 DebugLoc dl = Op.getDebugLoc();
8983 EVT ArgVT = Op.getNode()->getValueType(0);
8984 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
8985 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
8988 // Decide which area this value should be read from.
8989 // TODO: Implement the AMD64 ABI in its entirety. This simple
8990 // selection mechanism works only for the basic types.
8991 if (ArgVT == MVT::f80) {
8992 llvm_unreachable("va_arg for f80 not yet implemented");
8993 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
8994 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
8995 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
8996 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
8998 llvm_unreachable("Unhandled argument type in LowerVAARG");
9002 // Sanity Check: Make sure using fp_offset makes sense.
9003 assert(!getTargetMachine().Options.UseSoftFloat &&
9004 !(DAG.getMachineFunction()
9005 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9006 Subtarget->hasSSE1());
9009 // Insert VAARG_64 node into the DAG
9010 // VAARG_64 returns two values: Variable Argument Address, Chain
9011 SmallVector<SDValue, 11> InstOps;
9012 InstOps.push_back(Chain);
9013 InstOps.push_back(SrcPtr);
9014 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9015 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9016 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9017 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9018 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9019 VTs, &InstOps[0], InstOps.size(),
9021 MachinePointerInfo(SV),
9026 Chain = VAARG.getValue(1);
9028 // Load the next argument and return it
9029 return DAG.getLoad(ArgVT, dl,
9032 MachinePointerInfo(),
9033 false, false, false, 0);
9036 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9037 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9038 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9039 SDValue Chain = Op.getOperand(0);
9040 SDValue DstPtr = Op.getOperand(1);
9041 SDValue SrcPtr = Op.getOperand(2);
9042 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9043 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9044 DebugLoc DL = Op.getDebugLoc();
9046 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9047 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9049 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9052 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9053 // may or may not be a constant. Takes immediate version of shift as input.
9054 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9055 SDValue SrcOp, SDValue ShAmt,
9056 SelectionDAG &DAG) {
9057 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9059 if (isa<ConstantSDNode>(ShAmt)) {
9061 default: llvm_unreachable("Unknown target vector shift node");
9065 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9069 // Change opcode to non-immediate version
9071 default: llvm_unreachable("Unknown target vector shift node");
9072 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9073 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9074 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9077 // Need to build a vector containing shift amount
9078 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9081 ShOps[1] = DAG.getConstant(0, MVT::i32);
9082 ShOps[2] = DAG.getUNDEF(MVT::i32);
9083 ShOps[3] = DAG.getUNDEF(MVT::i32);
9084 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9085 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9086 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9090 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9091 DebugLoc dl = Op.getDebugLoc();
9092 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9094 default: return SDValue(); // Don't custom lower most intrinsics.
9095 // Comparison intrinsics.
9096 case Intrinsic::x86_sse_comieq_ss:
9097 case Intrinsic::x86_sse_comilt_ss:
9098 case Intrinsic::x86_sse_comile_ss:
9099 case Intrinsic::x86_sse_comigt_ss:
9100 case Intrinsic::x86_sse_comige_ss:
9101 case Intrinsic::x86_sse_comineq_ss:
9102 case Intrinsic::x86_sse_ucomieq_ss:
9103 case Intrinsic::x86_sse_ucomilt_ss:
9104 case Intrinsic::x86_sse_ucomile_ss:
9105 case Intrinsic::x86_sse_ucomigt_ss:
9106 case Intrinsic::x86_sse_ucomige_ss:
9107 case Intrinsic::x86_sse_ucomineq_ss:
9108 case Intrinsic::x86_sse2_comieq_sd:
9109 case Intrinsic::x86_sse2_comilt_sd:
9110 case Intrinsic::x86_sse2_comile_sd:
9111 case Intrinsic::x86_sse2_comigt_sd:
9112 case Intrinsic::x86_sse2_comige_sd:
9113 case Intrinsic::x86_sse2_comineq_sd:
9114 case Intrinsic::x86_sse2_ucomieq_sd:
9115 case Intrinsic::x86_sse2_ucomilt_sd:
9116 case Intrinsic::x86_sse2_ucomile_sd:
9117 case Intrinsic::x86_sse2_ucomigt_sd:
9118 case Intrinsic::x86_sse2_ucomige_sd:
9119 case Intrinsic::x86_sse2_ucomineq_sd: {
9121 ISD::CondCode CC = ISD::SETCC_INVALID;
9123 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9124 case Intrinsic::x86_sse_comieq_ss:
9125 case Intrinsic::x86_sse2_comieq_sd:
9129 case Intrinsic::x86_sse_comilt_ss:
9130 case Intrinsic::x86_sse2_comilt_sd:
9134 case Intrinsic::x86_sse_comile_ss:
9135 case Intrinsic::x86_sse2_comile_sd:
9139 case Intrinsic::x86_sse_comigt_ss:
9140 case Intrinsic::x86_sse2_comigt_sd:
9144 case Intrinsic::x86_sse_comige_ss:
9145 case Intrinsic::x86_sse2_comige_sd:
9149 case Intrinsic::x86_sse_comineq_ss:
9150 case Intrinsic::x86_sse2_comineq_sd:
9154 case Intrinsic::x86_sse_ucomieq_ss:
9155 case Intrinsic::x86_sse2_ucomieq_sd:
9156 Opc = X86ISD::UCOMI;
9159 case Intrinsic::x86_sse_ucomilt_ss:
9160 case Intrinsic::x86_sse2_ucomilt_sd:
9161 Opc = X86ISD::UCOMI;
9164 case Intrinsic::x86_sse_ucomile_ss:
9165 case Intrinsic::x86_sse2_ucomile_sd:
9166 Opc = X86ISD::UCOMI;
9169 case Intrinsic::x86_sse_ucomigt_ss:
9170 case Intrinsic::x86_sse2_ucomigt_sd:
9171 Opc = X86ISD::UCOMI;
9174 case Intrinsic::x86_sse_ucomige_ss:
9175 case Intrinsic::x86_sse2_ucomige_sd:
9176 Opc = X86ISD::UCOMI;
9179 case Intrinsic::x86_sse_ucomineq_ss:
9180 case Intrinsic::x86_sse2_ucomineq_sd:
9181 Opc = X86ISD::UCOMI;
9186 SDValue LHS = Op.getOperand(1);
9187 SDValue RHS = Op.getOperand(2);
9188 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9189 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9190 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9191 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9192 DAG.getConstant(X86CC, MVT::i8), Cond);
9193 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9195 // XOP comparison intrinsics
9196 case Intrinsic::x86_xop_vpcomltb:
9197 case Intrinsic::x86_xop_vpcomltw:
9198 case Intrinsic::x86_xop_vpcomltd:
9199 case Intrinsic::x86_xop_vpcomltq:
9200 case Intrinsic::x86_xop_vpcomltub:
9201 case Intrinsic::x86_xop_vpcomltuw:
9202 case Intrinsic::x86_xop_vpcomltud:
9203 case Intrinsic::x86_xop_vpcomltuq:
9204 case Intrinsic::x86_xop_vpcomleb:
9205 case Intrinsic::x86_xop_vpcomlew:
9206 case Intrinsic::x86_xop_vpcomled:
9207 case Intrinsic::x86_xop_vpcomleq:
9208 case Intrinsic::x86_xop_vpcomleub:
9209 case Intrinsic::x86_xop_vpcomleuw:
9210 case Intrinsic::x86_xop_vpcomleud:
9211 case Intrinsic::x86_xop_vpcomleuq:
9212 case Intrinsic::x86_xop_vpcomgtb:
9213 case Intrinsic::x86_xop_vpcomgtw:
9214 case Intrinsic::x86_xop_vpcomgtd:
9215 case Intrinsic::x86_xop_vpcomgtq:
9216 case Intrinsic::x86_xop_vpcomgtub:
9217 case Intrinsic::x86_xop_vpcomgtuw:
9218 case Intrinsic::x86_xop_vpcomgtud:
9219 case Intrinsic::x86_xop_vpcomgtuq:
9220 case Intrinsic::x86_xop_vpcomgeb:
9221 case Intrinsic::x86_xop_vpcomgew:
9222 case Intrinsic::x86_xop_vpcomged:
9223 case Intrinsic::x86_xop_vpcomgeq:
9224 case Intrinsic::x86_xop_vpcomgeub:
9225 case Intrinsic::x86_xop_vpcomgeuw:
9226 case Intrinsic::x86_xop_vpcomgeud:
9227 case Intrinsic::x86_xop_vpcomgeuq:
9228 case Intrinsic::x86_xop_vpcomeqb:
9229 case Intrinsic::x86_xop_vpcomeqw:
9230 case Intrinsic::x86_xop_vpcomeqd:
9231 case Intrinsic::x86_xop_vpcomeqq:
9232 case Intrinsic::x86_xop_vpcomequb:
9233 case Intrinsic::x86_xop_vpcomequw:
9234 case Intrinsic::x86_xop_vpcomequd:
9235 case Intrinsic::x86_xop_vpcomequq:
9236 case Intrinsic::x86_xop_vpcomneb:
9237 case Intrinsic::x86_xop_vpcomnew:
9238 case Intrinsic::x86_xop_vpcomned:
9239 case Intrinsic::x86_xop_vpcomneq:
9240 case Intrinsic::x86_xop_vpcomneub:
9241 case Intrinsic::x86_xop_vpcomneuw:
9242 case Intrinsic::x86_xop_vpcomneud:
9243 case Intrinsic::x86_xop_vpcomneuq:
9244 case Intrinsic::x86_xop_vpcomfalseb:
9245 case Intrinsic::x86_xop_vpcomfalsew:
9246 case Intrinsic::x86_xop_vpcomfalsed:
9247 case Intrinsic::x86_xop_vpcomfalseq:
9248 case Intrinsic::x86_xop_vpcomfalseub:
9249 case Intrinsic::x86_xop_vpcomfalseuw:
9250 case Intrinsic::x86_xop_vpcomfalseud:
9251 case Intrinsic::x86_xop_vpcomfalseuq:
9252 case Intrinsic::x86_xop_vpcomtrueb:
9253 case Intrinsic::x86_xop_vpcomtruew:
9254 case Intrinsic::x86_xop_vpcomtrued:
9255 case Intrinsic::x86_xop_vpcomtrueq:
9256 case Intrinsic::x86_xop_vpcomtrueub:
9257 case Intrinsic::x86_xop_vpcomtrueuw:
9258 case Intrinsic::x86_xop_vpcomtrueud:
9259 case Intrinsic::x86_xop_vpcomtrueuq: {
9264 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9265 case Intrinsic::x86_xop_vpcomltb:
9266 case Intrinsic::x86_xop_vpcomltw:
9267 case Intrinsic::x86_xop_vpcomltd:
9268 case Intrinsic::x86_xop_vpcomltq:
9270 Opc = X86ISD::VPCOM;
9272 case Intrinsic::x86_xop_vpcomltub:
9273 case Intrinsic::x86_xop_vpcomltuw:
9274 case Intrinsic::x86_xop_vpcomltud:
9275 case Intrinsic::x86_xop_vpcomltuq:
9277 Opc = X86ISD::VPCOMU;
9279 case Intrinsic::x86_xop_vpcomleb:
9280 case Intrinsic::x86_xop_vpcomlew:
9281 case Intrinsic::x86_xop_vpcomled:
9282 case Intrinsic::x86_xop_vpcomleq:
9284 Opc = X86ISD::VPCOM;
9286 case Intrinsic::x86_xop_vpcomleub:
9287 case Intrinsic::x86_xop_vpcomleuw:
9288 case Intrinsic::x86_xop_vpcomleud:
9289 case Intrinsic::x86_xop_vpcomleuq:
9291 Opc = X86ISD::VPCOMU;
9293 case Intrinsic::x86_xop_vpcomgtb:
9294 case Intrinsic::x86_xop_vpcomgtw:
9295 case Intrinsic::x86_xop_vpcomgtd:
9296 case Intrinsic::x86_xop_vpcomgtq:
9298 Opc = X86ISD::VPCOM;
9300 case Intrinsic::x86_xop_vpcomgtub:
9301 case Intrinsic::x86_xop_vpcomgtuw:
9302 case Intrinsic::x86_xop_vpcomgtud:
9303 case Intrinsic::x86_xop_vpcomgtuq:
9305 Opc = X86ISD::VPCOMU;
9307 case Intrinsic::x86_xop_vpcomgeb:
9308 case Intrinsic::x86_xop_vpcomgew:
9309 case Intrinsic::x86_xop_vpcomged:
9310 case Intrinsic::x86_xop_vpcomgeq:
9312 Opc = X86ISD::VPCOM;
9314 case Intrinsic::x86_xop_vpcomgeub:
9315 case Intrinsic::x86_xop_vpcomgeuw:
9316 case Intrinsic::x86_xop_vpcomgeud:
9317 case Intrinsic::x86_xop_vpcomgeuq:
9319 Opc = X86ISD::VPCOMU;
9321 case Intrinsic::x86_xop_vpcomeqb:
9322 case Intrinsic::x86_xop_vpcomeqw:
9323 case Intrinsic::x86_xop_vpcomeqd:
9324 case Intrinsic::x86_xop_vpcomeqq:
9326 Opc = X86ISD::VPCOM;
9328 case Intrinsic::x86_xop_vpcomequb:
9329 case Intrinsic::x86_xop_vpcomequw:
9330 case Intrinsic::x86_xop_vpcomequd:
9331 case Intrinsic::x86_xop_vpcomequq:
9333 Opc = X86ISD::VPCOMU;
9335 case Intrinsic::x86_xop_vpcomneb:
9336 case Intrinsic::x86_xop_vpcomnew:
9337 case Intrinsic::x86_xop_vpcomned:
9338 case Intrinsic::x86_xop_vpcomneq:
9340 Opc = X86ISD::VPCOM;
9342 case Intrinsic::x86_xop_vpcomneub:
9343 case Intrinsic::x86_xop_vpcomneuw:
9344 case Intrinsic::x86_xop_vpcomneud:
9345 case Intrinsic::x86_xop_vpcomneuq:
9347 Opc = X86ISD::VPCOMU;
9349 case Intrinsic::x86_xop_vpcomfalseb:
9350 case Intrinsic::x86_xop_vpcomfalsew:
9351 case Intrinsic::x86_xop_vpcomfalsed:
9352 case Intrinsic::x86_xop_vpcomfalseq:
9354 Opc = X86ISD::VPCOM;
9356 case Intrinsic::x86_xop_vpcomfalseub:
9357 case Intrinsic::x86_xop_vpcomfalseuw:
9358 case Intrinsic::x86_xop_vpcomfalseud:
9359 case Intrinsic::x86_xop_vpcomfalseuq:
9361 Opc = X86ISD::VPCOMU;
9363 case Intrinsic::x86_xop_vpcomtrueb:
9364 case Intrinsic::x86_xop_vpcomtruew:
9365 case Intrinsic::x86_xop_vpcomtrued:
9366 case Intrinsic::x86_xop_vpcomtrueq:
9368 Opc = X86ISD::VPCOM;
9370 case Intrinsic::x86_xop_vpcomtrueub:
9371 case Intrinsic::x86_xop_vpcomtrueuw:
9372 case Intrinsic::x86_xop_vpcomtrueud:
9373 case Intrinsic::x86_xop_vpcomtrueuq:
9375 Opc = X86ISD::VPCOMU;
9379 SDValue LHS = Op.getOperand(1);
9380 SDValue RHS = Op.getOperand(2);
9381 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9382 DAG.getConstant(CC, MVT::i8));
9385 // Arithmetic intrinsics.
9386 case Intrinsic::x86_sse2_pmulu_dq:
9387 case Intrinsic::x86_avx2_pmulu_dq:
9388 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9389 Op.getOperand(1), Op.getOperand(2));
9390 case Intrinsic::x86_sse3_hadd_ps:
9391 case Intrinsic::x86_sse3_hadd_pd:
9392 case Intrinsic::x86_avx_hadd_ps_256:
9393 case Intrinsic::x86_avx_hadd_pd_256:
9394 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9395 Op.getOperand(1), Op.getOperand(2));
9396 case Intrinsic::x86_sse3_hsub_ps:
9397 case Intrinsic::x86_sse3_hsub_pd:
9398 case Intrinsic::x86_avx_hsub_ps_256:
9399 case Intrinsic::x86_avx_hsub_pd_256:
9400 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9401 Op.getOperand(1), Op.getOperand(2));
9402 case Intrinsic::x86_ssse3_phadd_w_128:
9403 case Intrinsic::x86_ssse3_phadd_d_128:
9404 case Intrinsic::x86_avx2_phadd_w:
9405 case Intrinsic::x86_avx2_phadd_d:
9406 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9407 Op.getOperand(1), Op.getOperand(2));
9408 case Intrinsic::x86_ssse3_phsub_w_128:
9409 case Intrinsic::x86_ssse3_phsub_d_128:
9410 case Intrinsic::x86_avx2_phsub_w:
9411 case Intrinsic::x86_avx2_phsub_d:
9412 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9413 Op.getOperand(1), Op.getOperand(2));
9414 case Intrinsic::x86_avx2_psllv_d:
9415 case Intrinsic::x86_avx2_psllv_q:
9416 case Intrinsic::x86_avx2_psllv_d_256:
9417 case Intrinsic::x86_avx2_psllv_q_256:
9418 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9419 Op.getOperand(1), Op.getOperand(2));
9420 case Intrinsic::x86_avx2_psrlv_d:
9421 case Intrinsic::x86_avx2_psrlv_q:
9422 case Intrinsic::x86_avx2_psrlv_d_256:
9423 case Intrinsic::x86_avx2_psrlv_q_256:
9424 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9425 Op.getOperand(1), Op.getOperand(2));
9426 case Intrinsic::x86_avx2_psrav_d:
9427 case Intrinsic::x86_avx2_psrav_d_256:
9428 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9429 Op.getOperand(1), Op.getOperand(2));
9430 case Intrinsic::x86_ssse3_pshuf_b_128:
9431 case Intrinsic::x86_avx2_pshuf_b:
9432 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9433 Op.getOperand(1), Op.getOperand(2));
9434 case Intrinsic::x86_ssse3_psign_b_128:
9435 case Intrinsic::x86_ssse3_psign_w_128:
9436 case Intrinsic::x86_ssse3_psign_d_128:
9437 case Intrinsic::x86_avx2_psign_b:
9438 case Intrinsic::x86_avx2_psign_w:
9439 case Intrinsic::x86_avx2_psign_d:
9440 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9441 Op.getOperand(1), Op.getOperand(2));
9442 case Intrinsic::x86_sse41_insertps:
9443 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9444 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9445 case Intrinsic::x86_avx_vperm2f128_ps_256:
9446 case Intrinsic::x86_avx_vperm2f128_pd_256:
9447 case Intrinsic::x86_avx_vperm2f128_si_256:
9448 case Intrinsic::x86_avx2_vperm2i128:
9449 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9450 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9451 case Intrinsic::x86_avx_vpermil_ps:
9452 case Intrinsic::x86_avx_vpermil_pd:
9453 case Intrinsic::x86_avx_vpermil_ps_256:
9454 case Intrinsic::x86_avx_vpermil_pd_256:
9455 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(),
9456 Op.getOperand(1), Op.getOperand(2));
9458 // ptest and testp intrinsics. The intrinsic these come from are designed to
9459 // return an integer value, not just an instruction so lower it to the ptest
9460 // or testp pattern and a setcc for the result.
9461 case Intrinsic::x86_sse41_ptestz:
9462 case Intrinsic::x86_sse41_ptestc:
9463 case Intrinsic::x86_sse41_ptestnzc:
9464 case Intrinsic::x86_avx_ptestz_256:
9465 case Intrinsic::x86_avx_ptestc_256:
9466 case Intrinsic::x86_avx_ptestnzc_256:
9467 case Intrinsic::x86_avx_vtestz_ps:
9468 case Intrinsic::x86_avx_vtestc_ps:
9469 case Intrinsic::x86_avx_vtestnzc_ps:
9470 case Intrinsic::x86_avx_vtestz_pd:
9471 case Intrinsic::x86_avx_vtestc_pd:
9472 case Intrinsic::x86_avx_vtestnzc_pd:
9473 case Intrinsic::x86_avx_vtestz_ps_256:
9474 case Intrinsic::x86_avx_vtestc_ps_256:
9475 case Intrinsic::x86_avx_vtestnzc_ps_256:
9476 case Intrinsic::x86_avx_vtestz_pd_256:
9477 case Intrinsic::x86_avx_vtestc_pd_256:
9478 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9479 bool IsTestPacked = false;
9482 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9483 case Intrinsic::x86_avx_vtestz_ps:
9484 case Intrinsic::x86_avx_vtestz_pd:
9485 case Intrinsic::x86_avx_vtestz_ps_256:
9486 case Intrinsic::x86_avx_vtestz_pd_256:
9487 IsTestPacked = true; // Fallthrough
9488 case Intrinsic::x86_sse41_ptestz:
9489 case Intrinsic::x86_avx_ptestz_256:
9491 X86CC = X86::COND_E;
9493 case Intrinsic::x86_avx_vtestc_ps:
9494 case Intrinsic::x86_avx_vtestc_pd:
9495 case Intrinsic::x86_avx_vtestc_ps_256:
9496 case Intrinsic::x86_avx_vtestc_pd_256:
9497 IsTestPacked = true; // Fallthrough
9498 case Intrinsic::x86_sse41_ptestc:
9499 case Intrinsic::x86_avx_ptestc_256:
9501 X86CC = X86::COND_B;
9503 case Intrinsic::x86_avx_vtestnzc_ps:
9504 case Intrinsic::x86_avx_vtestnzc_pd:
9505 case Intrinsic::x86_avx_vtestnzc_ps_256:
9506 case Intrinsic::x86_avx_vtestnzc_pd_256:
9507 IsTestPacked = true; // Fallthrough
9508 case Intrinsic::x86_sse41_ptestnzc:
9509 case Intrinsic::x86_avx_ptestnzc_256:
9511 X86CC = X86::COND_A;
9515 SDValue LHS = Op.getOperand(1);
9516 SDValue RHS = Op.getOperand(2);
9517 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9518 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9519 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9520 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9521 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9524 // SSE/AVX shift intrinsics
9525 case Intrinsic::x86_sse2_psll_w:
9526 case Intrinsic::x86_sse2_psll_d:
9527 case Intrinsic::x86_sse2_psll_q:
9528 case Intrinsic::x86_avx2_psll_w:
9529 case Intrinsic::x86_avx2_psll_d:
9530 case Intrinsic::x86_avx2_psll_q:
9531 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9532 Op.getOperand(1), Op.getOperand(2));
9533 case Intrinsic::x86_sse2_psrl_w:
9534 case Intrinsic::x86_sse2_psrl_d:
9535 case Intrinsic::x86_sse2_psrl_q:
9536 case Intrinsic::x86_avx2_psrl_w:
9537 case Intrinsic::x86_avx2_psrl_d:
9538 case Intrinsic::x86_avx2_psrl_q:
9539 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9540 Op.getOperand(1), Op.getOperand(2));
9541 case Intrinsic::x86_sse2_psra_w:
9542 case Intrinsic::x86_sse2_psra_d:
9543 case Intrinsic::x86_avx2_psra_w:
9544 case Intrinsic::x86_avx2_psra_d:
9545 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9546 Op.getOperand(1), Op.getOperand(2));
9547 case Intrinsic::x86_sse2_pslli_w:
9548 case Intrinsic::x86_sse2_pslli_d:
9549 case Intrinsic::x86_sse2_pslli_q:
9550 case Intrinsic::x86_avx2_pslli_w:
9551 case Intrinsic::x86_avx2_pslli_d:
9552 case Intrinsic::x86_avx2_pslli_q:
9553 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9554 Op.getOperand(1), Op.getOperand(2), DAG);
9555 case Intrinsic::x86_sse2_psrli_w:
9556 case Intrinsic::x86_sse2_psrli_d:
9557 case Intrinsic::x86_sse2_psrli_q:
9558 case Intrinsic::x86_avx2_psrli_w:
9559 case Intrinsic::x86_avx2_psrli_d:
9560 case Intrinsic::x86_avx2_psrli_q:
9561 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9562 Op.getOperand(1), Op.getOperand(2), DAG);
9563 case Intrinsic::x86_sse2_psrai_w:
9564 case Intrinsic::x86_sse2_psrai_d:
9565 case Intrinsic::x86_avx2_psrai_w:
9566 case Intrinsic::x86_avx2_psrai_d:
9567 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9568 Op.getOperand(1), Op.getOperand(2), DAG);
9569 // Fix vector shift instructions where the last operand is a non-immediate
9571 case Intrinsic::x86_mmx_pslli_w:
9572 case Intrinsic::x86_mmx_pslli_d:
9573 case Intrinsic::x86_mmx_pslli_q:
9574 case Intrinsic::x86_mmx_psrli_w:
9575 case Intrinsic::x86_mmx_psrli_d:
9576 case Intrinsic::x86_mmx_psrli_q:
9577 case Intrinsic::x86_mmx_psrai_w:
9578 case Intrinsic::x86_mmx_psrai_d: {
9579 SDValue ShAmt = Op.getOperand(2);
9580 if (isa<ConstantSDNode>(ShAmt))
9583 unsigned NewIntNo = 0;
9585 case Intrinsic::x86_mmx_pslli_w:
9586 NewIntNo = Intrinsic::x86_mmx_psll_w;
9588 case Intrinsic::x86_mmx_pslli_d:
9589 NewIntNo = Intrinsic::x86_mmx_psll_d;
9591 case Intrinsic::x86_mmx_pslli_q:
9592 NewIntNo = Intrinsic::x86_mmx_psll_q;
9594 case Intrinsic::x86_mmx_psrli_w:
9595 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9597 case Intrinsic::x86_mmx_psrli_d:
9598 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9600 case Intrinsic::x86_mmx_psrli_q:
9601 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9603 case Intrinsic::x86_mmx_psrai_w:
9604 NewIntNo = Intrinsic::x86_mmx_psra_w;
9606 case Intrinsic::x86_mmx_psrai_d:
9607 NewIntNo = Intrinsic::x86_mmx_psra_d;
9609 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9612 // The vector shift intrinsics with scalars uses 32b shift amounts but
9613 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9615 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9616 DAG.getConstant(0, MVT::i32));
9617 // FIXME this must be lowered to get rid of the invalid type.
9619 EVT VT = Op.getValueType();
9620 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9621 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9622 DAG.getConstant(NewIntNo, MVT::i32),
9623 Op.getOperand(1), ShAmt);
9628 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9629 SelectionDAG &DAG) const {
9630 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9631 MFI->setReturnAddressIsTaken(true);
9633 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9634 DebugLoc dl = Op.getDebugLoc();
9637 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9639 DAG.getConstant(TD->getPointerSize(),
9640 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9641 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9642 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9644 MachinePointerInfo(), false, false, false, 0);
9647 // Just load the return address.
9648 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9649 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9650 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9653 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9654 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9655 MFI->setFrameAddressIsTaken(true);
9657 EVT VT = Op.getValueType();
9658 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9659 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9660 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9661 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9663 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9664 MachinePointerInfo(),
9665 false, false, false, 0);
9669 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9670 SelectionDAG &DAG) const {
9671 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9674 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9675 MachineFunction &MF = DAG.getMachineFunction();
9676 SDValue Chain = Op.getOperand(0);
9677 SDValue Offset = Op.getOperand(1);
9678 SDValue Handler = Op.getOperand(2);
9679 DebugLoc dl = Op.getDebugLoc();
9681 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9682 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9684 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9686 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9687 DAG.getIntPtrConstant(TD->getPointerSize()));
9688 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9689 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9691 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9692 MF.getRegInfo().addLiveOut(StoreAddrReg);
9694 return DAG.getNode(X86ISD::EH_RETURN, dl,
9696 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9699 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9700 SelectionDAG &DAG) const {
9701 return Op.getOperand(0);
9704 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9705 SelectionDAG &DAG) const {
9706 SDValue Root = Op.getOperand(0);
9707 SDValue Trmp = Op.getOperand(1); // trampoline
9708 SDValue FPtr = Op.getOperand(2); // nested function
9709 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9710 DebugLoc dl = Op.getDebugLoc();
9712 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9714 if (Subtarget->is64Bit()) {
9715 SDValue OutChains[6];
9717 // Large code-model.
9718 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9719 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9721 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9722 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9724 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9726 // Load the pointer to the nested function into R11.
9727 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9728 SDValue Addr = Trmp;
9729 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9730 Addr, MachinePointerInfo(TrmpAddr),
9733 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9734 DAG.getConstant(2, MVT::i64));
9735 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9736 MachinePointerInfo(TrmpAddr, 2),
9739 // Load the 'nest' parameter value into R10.
9740 // R10 is specified in X86CallingConv.td
9741 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9742 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9743 DAG.getConstant(10, MVT::i64));
9744 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9745 Addr, MachinePointerInfo(TrmpAddr, 10),
9748 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9749 DAG.getConstant(12, MVT::i64));
9750 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9751 MachinePointerInfo(TrmpAddr, 12),
9754 // Jump to the nested function.
9755 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9756 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9757 DAG.getConstant(20, MVT::i64));
9758 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9759 Addr, MachinePointerInfo(TrmpAddr, 20),
9762 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9763 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9764 DAG.getConstant(22, MVT::i64));
9765 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9766 MachinePointerInfo(TrmpAddr, 22),
9769 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9771 const Function *Func =
9772 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9773 CallingConv::ID CC = Func->getCallingConv();
9778 llvm_unreachable("Unsupported calling convention");
9779 case CallingConv::C:
9780 case CallingConv::X86_StdCall: {
9781 // Pass 'nest' parameter in ECX.
9782 // Must be kept in sync with X86CallingConv.td
9785 // Check that ECX wasn't needed by an 'inreg' parameter.
9786 FunctionType *FTy = Func->getFunctionType();
9787 const AttrListPtr &Attrs = Func->getAttributes();
9789 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9790 unsigned InRegCount = 0;
9793 for (FunctionType::param_iterator I = FTy->param_begin(),
9794 E = FTy->param_end(); I != E; ++I, ++Idx)
9795 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9796 // FIXME: should only count parameters that are lowered to integers.
9797 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9799 if (InRegCount > 2) {
9800 report_fatal_error("Nest register in use - reduce number of inreg"
9806 case CallingConv::X86_FastCall:
9807 case CallingConv::X86_ThisCall:
9808 case CallingConv::Fast:
9809 // Pass 'nest' parameter in EAX.
9810 // Must be kept in sync with X86CallingConv.td
9815 SDValue OutChains[4];
9818 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9819 DAG.getConstant(10, MVT::i32));
9820 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9822 // This is storing the opcode for MOV32ri.
9823 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9824 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9825 OutChains[0] = DAG.getStore(Root, dl,
9826 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9827 Trmp, MachinePointerInfo(TrmpAddr),
9830 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9831 DAG.getConstant(1, MVT::i32));
9832 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9833 MachinePointerInfo(TrmpAddr, 1),
9836 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9837 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9838 DAG.getConstant(5, MVT::i32));
9839 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9840 MachinePointerInfo(TrmpAddr, 5),
9843 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9844 DAG.getConstant(6, MVT::i32));
9845 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9846 MachinePointerInfo(TrmpAddr, 6),
9849 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9853 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9854 SelectionDAG &DAG) const {
9856 The rounding mode is in bits 11:10 of FPSR, and has the following
9863 FLT_ROUNDS, on the other hand, expects the following:
9870 To perform the conversion, we do:
9871 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9874 MachineFunction &MF = DAG.getMachineFunction();
9875 const TargetMachine &TM = MF.getTarget();
9876 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9877 unsigned StackAlignment = TFI.getStackAlignment();
9878 EVT VT = Op.getValueType();
9879 DebugLoc DL = Op.getDebugLoc();
9881 // Save FP Control Word to stack slot
9882 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9883 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9886 MachineMemOperand *MMO =
9887 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9888 MachineMemOperand::MOStore, 2, 2);
9890 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9891 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9892 DAG.getVTList(MVT::Other),
9893 Ops, 2, MVT::i16, MMO);
9895 // Load FP Control Word from stack slot
9896 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9897 MachinePointerInfo(), false, false, false, 0);
9899 // Transform as necessary
9901 DAG.getNode(ISD::SRL, DL, MVT::i16,
9902 DAG.getNode(ISD::AND, DL, MVT::i16,
9903 CWD, DAG.getConstant(0x800, MVT::i16)),
9904 DAG.getConstant(11, MVT::i8));
9906 DAG.getNode(ISD::SRL, DL, MVT::i16,
9907 DAG.getNode(ISD::AND, DL, MVT::i16,
9908 CWD, DAG.getConstant(0x400, MVT::i16)),
9909 DAG.getConstant(9, MVT::i8));
9912 DAG.getNode(ISD::AND, DL, MVT::i16,
9913 DAG.getNode(ISD::ADD, DL, MVT::i16,
9914 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9915 DAG.getConstant(1, MVT::i16)),
9916 DAG.getConstant(3, MVT::i16));
9919 return DAG.getNode((VT.getSizeInBits() < 16 ?
9920 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9923 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9924 EVT VT = Op.getValueType();
9926 unsigned NumBits = VT.getSizeInBits();
9927 DebugLoc dl = Op.getDebugLoc();
9929 Op = Op.getOperand(0);
9930 if (VT == MVT::i8) {
9931 // Zero extend to i32 since there is not an i8 bsr.
9933 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9936 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9937 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9938 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9940 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9943 DAG.getConstant(NumBits+NumBits-1, OpVT),
9944 DAG.getConstant(X86::COND_E, MVT::i8),
9947 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9949 // Finally xor with NumBits-1.
9950 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9953 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9957 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
9958 SelectionDAG &DAG) const {
9959 EVT VT = Op.getValueType();
9961 unsigned NumBits = VT.getSizeInBits();
9962 DebugLoc dl = Op.getDebugLoc();
9964 Op = Op.getOperand(0);
9965 if (VT == MVT::i8) {
9966 // Zero extend to i32 since there is not an i8 bsr.
9968 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9971 // Issue a bsr (scan bits in reverse).
9972 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9973 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9975 // And xor with NumBits-1.
9976 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9979 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9983 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9984 EVT VT = Op.getValueType();
9985 unsigned NumBits = VT.getSizeInBits();
9986 DebugLoc dl = Op.getDebugLoc();
9987 Op = Op.getOperand(0);
9989 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9990 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
9991 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9993 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9996 DAG.getConstant(NumBits, VT),
9997 DAG.getConstant(X86::COND_E, MVT::i8),
10000 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10003 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10004 // ones, and then concatenate the result back.
10005 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10006 EVT VT = Op.getValueType();
10008 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10009 "Unsupported value type for operation");
10011 int NumElems = VT.getVectorNumElements();
10012 DebugLoc dl = Op.getDebugLoc();
10013 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10014 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10016 // Extract the LHS vectors
10017 SDValue LHS = Op.getOperand(0);
10018 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10019 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10021 // Extract the RHS vectors
10022 SDValue RHS = Op.getOperand(1);
10023 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10024 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10026 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10027 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10029 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10030 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10031 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10034 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10035 assert(Op.getValueType().getSizeInBits() == 256 &&
10036 Op.getValueType().isInteger() &&
10037 "Only handle AVX 256-bit vector integer operation");
10038 return Lower256IntArith(Op, DAG);
10041 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10042 assert(Op.getValueType().getSizeInBits() == 256 &&
10043 Op.getValueType().isInteger() &&
10044 "Only handle AVX 256-bit vector integer operation");
10045 return Lower256IntArith(Op, DAG);
10048 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10049 EVT VT = Op.getValueType();
10051 // Decompose 256-bit ops into smaller 128-bit ops.
10052 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10053 return Lower256IntArith(Op, DAG);
10055 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10056 "Only know how to lower V2I64/V4I64 multiply");
10058 DebugLoc dl = Op.getDebugLoc();
10060 // Ahi = psrlqi(a, 32);
10061 // Bhi = psrlqi(b, 32);
10063 // AloBlo = pmuludq(a, b);
10064 // AloBhi = pmuludq(a, Bhi);
10065 // AhiBlo = pmuludq(Ahi, b);
10067 // AloBhi = psllqi(AloBhi, 32);
10068 // AhiBlo = psllqi(AhiBlo, 32);
10069 // return AloBlo + AloBhi + AhiBlo;
10071 SDValue A = Op.getOperand(0);
10072 SDValue B = Op.getOperand(1);
10074 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10076 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10077 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10079 // Bit cast to 32-bit vectors for MULUDQ
10080 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10081 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10082 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10083 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10084 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10086 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10087 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10088 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10090 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10091 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10093 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10094 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10097 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10099 EVT VT = Op.getValueType();
10100 DebugLoc dl = Op.getDebugLoc();
10101 SDValue R = Op.getOperand(0);
10102 SDValue Amt = Op.getOperand(1);
10103 LLVMContext *Context = DAG.getContext();
10105 if (!Subtarget->hasSSE2())
10108 // Optimize shl/srl/sra with constant shift amount.
10109 if (isSplatVector(Amt.getNode())) {
10110 SDValue SclrAmt = Amt->getOperand(0);
10111 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10112 uint64_t ShiftAmt = C->getZExtValue();
10114 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10115 (Subtarget->hasAVX2() &&
10116 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10117 if (Op.getOpcode() == ISD::SHL)
10118 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10119 DAG.getConstant(ShiftAmt, MVT::i32));
10120 if (Op.getOpcode() == ISD::SRL)
10121 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10122 DAG.getConstant(ShiftAmt, MVT::i32));
10123 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10124 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10125 DAG.getConstant(ShiftAmt, MVT::i32));
10128 if (VT == MVT::v16i8) {
10129 if (Op.getOpcode() == ISD::SHL) {
10130 // Make a large shift.
10131 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10132 DAG.getConstant(ShiftAmt, MVT::i32));
10133 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10134 // Zero out the rightmost bits.
10135 SmallVector<SDValue, 16> V(16,
10136 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10138 return DAG.getNode(ISD::AND, dl, VT, SHL,
10139 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10141 if (Op.getOpcode() == ISD::SRL) {
10142 // Make a large shift.
10143 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10144 DAG.getConstant(ShiftAmt, MVT::i32));
10145 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10146 // Zero out the leftmost bits.
10147 SmallVector<SDValue, 16> V(16,
10148 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10150 return DAG.getNode(ISD::AND, dl, VT, SRL,
10151 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10153 if (Op.getOpcode() == ISD::SRA) {
10154 if (ShiftAmt == 7) {
10155 // R s>> 7 === R s< 0
10156 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10157 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10160 // R s>> a === ((R u>> a) ^ m) - m
10161 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10162 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10164 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10165 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10166 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10171 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10172 if (Op.getOpcode() == ISD::SHL) {
10173 // Make a large shift.
10174 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10175 DAG.getConstant(ShiftAmt, MVT::i32));
10176 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10177 // Zero out the rightmost bits.
10178 SmallVector<SDValue, 32> V(32,
10179 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10181 return DAG.getNode(ISD::AND, dl, VT, SHL,
10182 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10184 if (Op.getOpcode() == ISD::SRL) {
10185 // Make a large shift.
10186 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10187 DAG.getConstant(ShiftAmt, MVT::i32));
10188 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10189 // Zero out the leftmost bits.
10190 SmallVector<SDValue, 32> V(32,
10191 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10193 return DAG.getNode(ISD::AND, dl, VT, SRL,
10194 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10196 if (Op.getOpcode() == ISD::SRA) {
10197 if (ShiftAmt == 7) {
10198 // R s>> 7 === R s< 0
10199 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10200 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10203 // R s>> a === ((R u>> a) ^ m) - m
10204 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10205 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10207 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10208 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10209 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10216 // Lower SHL with variable shift amount.
10217 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10218 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10219 DAG.getConstant(23, MVT::i32));
10221 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10222 Constant *C = ConstantDataVector::get(*Context, CV);
10223 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10224 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10225 MachinePointerInfo::getConstantPool(),
10226 false, false, false, 16);
10228 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10229 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10230 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10231 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10233 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10234 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10237 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10238 DAG.getConstant(5, MVT::i32));
10239 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10241 // Turn 'a' into a mask suitable for VSELECT
10242 SDValue VSelM = DAG.getConstant(0x80, VT);
10243 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10244 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10246 SDValue CM1 = DAG.getConstant(0x0f, VT);
10247 SDValue CM2 = DAG.getConstant(0x3f, VT);
10249 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10250 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10251 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10252 DAG.getConstant(4, MVT::i32), DAG);
10253 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10254 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10257 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10258 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10259 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10261 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10262 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10263 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10264 DAG.getConstant(2, MVT::i32), DAG);
10265 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10266 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10269 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10270 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10271 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10273 // return VSELECT(r, r+r, a);
10274 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10275 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10279 // Decompose 256-bit shifts into smaller 128-bit shifts.
10280 if (VT.getSizeInBits() == 256) {
10281 unsigned NumElems = VT.getVectorNumElements();
10282 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10283 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10285 // Extract the two vectors
10286 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10287 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10290 // Recreate the shift amount vectors
10291 SDValue Amt1, Amt2;
10292 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10293 // Constant shift amount
10294 SmallVector<SDValue, 4> Amt1Csts;
10295 SmallVector<SDValue, 4> Amt2Csts;
10296 for (unsigned i = 0; i != NumElems/2; ++i)
10297 Amt1Csts.push_back(Amt->getOperand(i));
10298 for (unsigned i = NumElems/2; i != NumElems; ++i)
10299 Amt2Csts.push_back(Amt->getOperand(i));
10301 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10302 &Amt1Csts[0], NumElems/2);
10303 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10304 &Amt2Csts[0], NumElems/2);
10306 // Variable shift amount
10307 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10308 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10312 // Issue new vector shifts for the smaller types
10313 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10314 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10316 // Concatenate the result back
10317 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10323 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10324 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10325 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10326 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10327 // has only one use.
10328 SDNode *N = Op.getNode();
10329 SDValue LHS = N->getOperand(0);
10330 SDValue RHS = N->getOperand(1);
10331 unsigned BaseOp = 0;
10333 DebugLoc DL = Op.getDebugLoc();
10334 switch (Op.getOpcode()) {
10335 default: llvm_unreachable("Unknown ovf instruction!");
10337 // A subtract of one will be selected as a INC. Note that INC doesn't
10338 // set CF, so we can't do this for UADDO.
10339 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10341 BaseOp = X86ISD::INC;
10342 Cond = X86::COND_O;
10345 BaseOp = X86ISD::ADD;
10346 Cond = X86::COND_O;
10349 BaseOp = X86ISD::ADD;
10350 Cond = X86::COND_B;
10353 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10354 // set CF, so we can't do this for USUBO.
10355 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10357 BaseOp = X86ISD::DEC;
10358 Cond = X86::COND_O;
10361 BaseOp = X86ISD::SUB;
10362 Cond = X86::COND_O;
10365 BaseOp = X86ISD::SUB;
10366 Cond = X86::COND_B;
10369 BaseOp = X86ISD::SMUL;
10370 Cond = X86::COND_O;
10372 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10373 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10375 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10378 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10379 DAG.getConstant(X86::COND_O, MVT::i32),
10380 SDValue(Sum.getNode(), 2));
10382 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10386 // Also sets EFLAGS.
10387 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10388 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10391 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10392 DAG.getConstant(Cond, MVT::i32),
10393 SDValue(Sum.getNode(), 1));
10395 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10398 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10399 SelectionDAG &DAG) const {
10400 DebugLoc dl = Op.getDebugLoc();
10401 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10402 EVT VT = Op.getValueType();
10404 if (!Subtarget->hasSSE2() || !VT.isVector())
10407 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10408 ExtraVT.getScalarType().getSizeInBits();
10409 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10411 switch (VT.getSimpleVT().SimpleTy) {
10412 default: return SDValue();
10415 if (!Subtarget->hasAVX())
10417 if (!Subtarget->hasAVX2()) {
10418 // needs to be split
10419 int NumElems = VT.getVectorNumElements();
10420 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10421 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10423 // Extract the LHS vectors
10424 SDValue LHS = Op.getOperand(0);
10425 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10426 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10428 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10429 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10431 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10432 int ExtraNumElems = ExtraVT.getVectorNumElements();
10433 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10435 SDValue Extra = DAG.getValueType(ExtraVT);
10437 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10438 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10440 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10445 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10446 Op.getOperand(0), ShAmt, DAG);
10447 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10453 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10454 DebugLoc dl = Op.getDebugLoc();
10456 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10457 // There isn't any reason to disable it if the target processor supports it.
10458 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10459 SDValue Chain = Op.getOperand(0);
10460 SDValue Zero = DAG.getConstant(0, MVT::i32);
10462 DAG.getRegister(X86::ESP, MVT::i32), // Base
10463 DAG.getTargetConstant(1, MVT::i8), // Scale
10464 DAG.getRegister(0, MVT::i32), // Index
10465 DAG.getTargetConstant(0, MVT::i32), // Disp
10466 DAG.getRegister(0, MVT::i32), // Segment.
10471 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10472 array_lengthof(Ops));
10473 return SDValue(Res, 0);
10476 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10478 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10480 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10481 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10482 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10483 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10485 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10486 if (!Op1 && !Op2 && !Op3 && Op4)
10487 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10489 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10490 if (Op1 && !Op2 && !Op3 && !Op4)
10491 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10493 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10495 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10498 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10499 SelectionDAG &DAG) const {
10500 DebugLoc dl = Op.getDebugLoc();
10501 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10502 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10503 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10504 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10506 // The only fence that needs an instruction is a sequentially-consistent
10507 // cross-thread fence.
10508 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10509 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10510 // no-sse2). There isn't any reason to disable it if the target processor
10512 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10513 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10515 SDValue Chain = Op.getOperand(0);
10516 SDValue Zero = DAG.getConstant(0, MVT::i32);
10518 DAG.getRegister(X86::ESP, MVT::i32), // Base
10519 DAG.getTargetConstant(1, MVT::i8), // Scale
10520 DAG.getRegister(0, MVT::i32), // Index
10521 DAG.getTargetConstant(0, MVT::i32), // Disp
10522 DAG.getRegister(0, MVT::i32), // Segment.
10527 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10528 array_lengthof(Ops));
10529 return SDValue(Res, 0);
10532 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10533 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10537 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10538 EVT T = Op.getValueType();
10539 DebugLoc DL = Op.getDebugLoc();
10542 switch(T.getSimpleVT().SimpleTy) {
10543 default: llvm_unreachable("Invalid value type!");
10544 case MVT::i8: Reg = X86::AL; size = 1; break;
10545 case MVT::i16: Reg = X86::AX; size = 2; break;
10546 case MVT::i32: Reg = X86::EAX; size = 4; break;
10548 assert(Subtarget->is64Bit() && "Node not type legal!");
10549 Reg = X86::RAX; size = 8;
10552 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10553 Op.getOperand(2), SDValue());
10554 SDValue Ops[] = { cpIn.getValue(0),
10557 DAG.getTargetConstant(size, MVT::i8),
10558 cpIn.getValue(1) };
10559 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10560 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10561 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10564 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10568 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10569 SelectionDAG &DAG) const {
10570 assert(Subtarget->is64Bit() && "Result not type legalized?");
10571 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10572 SDValue TheChain = Op.getOperand(0);
10573 DebugLoc dl = Op.getDebugLoc();
10574 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10575 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10576 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10578 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10579 DAG.getConstant(32, MVT::i8));
10581 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10584 return DAG.getMergeValues(Ops, 2, dl);
10587 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10588 SelectionDAG &DAG) const {
10589 EVT SrcVT = Op.getOperand(0).getValueType();
10590 EVT DstVT = Op.getValueType();
10591 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10592 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10593 assert((DstVT == MVT::i64 ||
10594 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10595 "Unexpected custom BITCAST");
10596 // i64 <=> MMX conversions are Legal.
10597 if (SrcVT==MVT::i64 && DstVT.isVector())
10599 if (DstVT==MVT::i64 && SrcVT.isVector())
10601 // MMX <=> MMX conversions are Legal.
10602 if (SrcVT.isVector() && DstVT.isVector())
10604 // All other conversions need to be expanded.
10608 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10609 SDNode *Node = Op.getNode();
10610 DebugLoc dl = Node->getDebugLoc();
10611 EVT T = Node->getValueType(0);
10612 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10613 DAG.getConstant(0, T), Node->getOperand(2));
10614 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10615 cast<AtomicSDNode>(Node)->getMemoryVT(),
10616 Node->getOperand(0),
10617 Node->getOperand(1), negOp,
10618 cast<AtomicSDNode>(Node)->getSrcValue(),
10619 cast<AtomicSDNode>(Node)->getAlignment(),
10620 cast<AtomicSDNode>(Node)->getOrdering(),
10621 cast<AtomicSDNode>(Node)->getSynchScope());
10624 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10625 SDNode *Node = Op.getNode();
10626 DebugLoc dl = Node->getDebugLoc();
10627 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10629 // Convert seq_cst store -> xchg
10630 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10631 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10632 // (The only way to get a 16-byte store is cmpxchg16b)
10633 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10634 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10635 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10636 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10637 cast<AtomicSDNode>(Node)->getMemoryVT(),
10638 Node->getOperand(0),
10639 Node->getOperand(1), Node->getOperand(2),
10640 cast<AtomicSDNode>(Node)->getMemOperand(),
10641 cast<AtomicSDNode>(Node)->getOrdering(),
10642 cast<AtomicSDNode>(Node)->getSynchScope());
10643 return Swap.getValue(1);
10645 // Other atomic stores have a simple pattern.
10649 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10650 EVT VT = Op.getNode()->getValueType(0);
10652 // Let legalize expand this if it isn't a legal type yet.
10653 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10656 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10659 bool ExtraOp = false;
10660 switch (Op.getOpcode()) {
10661 default: llvm_unreachable("Invalid code");
10662 case ISD::ADDC: Opc = X86ISD::ADD; break;
10663 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10664 case ISD::SUBC: Opc = X86ISD::SUB; break;
10665 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10669 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10671 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10672 Op.getOperand(1), Op.getOperand(2));
10675 /// LowerOperation - Provide custom lowering hooks for some operations.
10677 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10678 switch (Op.getOpcode()) {
10679 default: llvm_unreachable("Should not custom lower this!");
10680 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10681 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10682 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10683 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10684 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10685 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10686 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10687 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10688 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10689 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10690 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10691 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10692 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10693 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10694 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10695 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10696 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10697 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10698 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10699 case ISD::SHL_PARTS:
10700 case ISD::SRA_PARTS:
10701 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10702 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10703 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10704 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10705 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10706 case ISD::FABS: return LowerFABS(Op, DAG);
10707 case ISD::FNEG: return LowerFNEG(Op, DAG);
10708 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10709 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10710 case ISD::SETCC: return LowerSETCC(Op, DAG);
10711 case ISD::SELECT: return LowerSELECT(Op, DAG);
10712 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10713 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10714 case ISD::VASTART: return LowerVASTART(Op, DAG);
10715 case ISD::VAARG: return LowerVAARG(Op, DAG);
10716 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10717 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10718 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10719 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10720 case ISD::FRAME_TO_ARGS_OFFSET:
10721 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10722 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10723 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10724 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10725 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10726 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10727 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10728 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10729 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10730 case ISD::MUL: return LowerMUL(Op, DAG);
10733 case ISD::SHL: return LowerShift(Op, DAG);
10739 case ISD::UMULO: return LowerXALUO(Op, DAG);
10740 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10741 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10745 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10746 case ISD::ADD: return LowerADD(Op, DAG);
10747 case ISD::SUB: return LowerSUB(Op, DAG);
10751 static void ReplaceATOMIC_LOAD(SDNode *Node,
10752 SmallVectorImpl<SDValue> &Results,
10753 SelectionDAG &DAG) {
10754 DebugLoc dl = Node->getDebugLoc();
10755 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10757 // Convert wide load -> cmpxchg8b/cmpxchg16b
10758 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10759 // (The only way to get a 16-byte load is cmpxchg16b)
10760 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10761 SDValue Zero = DAG.getConstant(0, VT);
10762 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10763 Node->getOperand(0),
10764 Node->getOperand(1), Zero, Zero,
10765 cast<AtomicSDNode>(Node)->getMemOperand(),
10766 cast<AtomicSDNode>(Node)->getOrdering(),
10767 cast<AtomicSDNode>(Node)->getSynchScope());
10768 Results.push_back(Swap.getValue(0));
10769 Results.push_back(Swap.getValue(1));
10772 void X86TargetLowering::
10773 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10774 SelectionDAG &DAG, unsigned NewOp) const {
10775 DebugLoc dl = Node->getDebugLoc();
10776 assert (Node->getValueType(0) == MVT::i64 &&
10777 "Only know how to expand i64 atomics");
10779 SDValue Chain = Node->getOperand(0);
10780 SDValue In1 = Node->getOperand(1);
10781 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10782 Node->getOperand(2), DAG.getIntPtrConstant(0));
10783 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10784 Node->getOperand(2), DAG.getIntPtrConstant(1));
10785 SDValue Ops[] = { Chain, In1, In2L, In2H };
10786 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10788 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10789 cast<MemSDNode>(Node)->getMemOperand());
10790 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10791 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10792 Results.push_back(Result.getValue(2));
10795 /// ReplaceNodeResults - Replace a node with an illegal result type
10796 /// with a new node built out of custom code.
10797 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10798 SmallVectorImpl<SDValue>&Results,
10799 SelectionDAG &DAG) const {
10800 DebugLoc dl = N->getDebugLoc();
10801 switch (N->getOpcode()) {
10803 llvm_unreachable("Do not know how to custom type legalize this operation!");
10804 case ISD::SIGN_EXTEND_INREG:
10809 // We don't want to expand or promote these.
10811 case ISD::FP_TO_SINT:
10812 case ISD::FP_TO_UINT: {
10813 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10815 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10818 std::pair<SDValue,SDValue> Vals =
10819 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10820 SDValue FIST = Vals.first, StackSlot = Vals.second;
10821 if (FIST.getNode() != 0) {
10822 EVT VT = N->getValueType(0);
10823 // Return a load from the stack slot.
10824 if (StackSlot.getNode() != 0)
10825 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10826 MachinePointerInfo(),
10827 false, false, false, 0));
10829 Results.push_back(FIST);
10833 case ISD::READCYCLECOUNTER: {
10834 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10835 SDValue TheChain = N->getOperand(0);
10836 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10837 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10839 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10841 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10842 SDValue Ops[] = { eax, edx };
10843 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10844 Results.push_back(edx.getValue(1));
10847 case ISD::ATOMIC_CMP_SWAP: {
10848 EVT T = N->getValueType(0);
10849 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10850 bool Regs64bit = T == MVT::i128;
10851 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10852 SDValue cpInL, cpInH;
10853 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10854 DAG.getConstant(0, HalfT));
10855 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10856 DAG.getConstant(1, HalfT));
10857 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10858 Regs64bit ? X86::RAX : X86::EAX,
10860 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10861 Regs64bit ? X86::RDX : X86::EDX,
10862 cpInH, cpInL.getValue(1));
10863 SDValue swapInL, swapInH;
10864 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10865 DAG.getConstant(0, HalfT));
10866 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10867 DAG.getConstant(1, HalfT));
10868 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10869 Regs64bit ? X86::RBX : X86::EBX,
10870 swapInL, cpInH.getValue(1));
10871 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10872 Regs64bit ? X86::RCX : X86::ECX,
10873 swapInH, swapInL.getValue(1));
10874 SDValue Ops[] = { swapInH.getValue(0),
10876 swapInH.getValue(1) };
10877 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10878 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10879 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10880 X86ISD::LCMPXCHG8_DAG;
10881 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10883 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10884 Regs64bit ? X86::RAX : X86::EAX,
10885 HalfT, Result.getValue(1));
10886 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10887 Regs64bit ? X86::RDX : X86::EDX,
10888 HalfT, cpOutL.getValue(2));
10889 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10890 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10891 Results.push_back(cpOutH.getValue(1));
10894 case ISD::ATOMIC_LOAD_ADD:
10895 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10897 case ISD::ATOMIC_LOAD_AND:
10898 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10900 case ISD::ATOMIC_LOAD_NAND:
10901 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10903 case ISD::ATOMIC_LOAD_OR:
10904 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10906 case ISD::ATOMIC_LOAD_SUB:
10907 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10909 case ISD::ATOMIC_LOAD_XOR:
10910 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10912 case ISD::ATOMIC_SWAP:
10913 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10915 case ISD::ATOMIC_LOAD:
10916 ReplaceATOMIC_LOAD(N, Results, DAG);
10920 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10922 default: return NULL;
10923 case X86ISD::BSF: return "X86ISD::BSF";
10924 case X86ISD::BSR: return "X86ISD::BSR";
10925 case X86ISD::SHLD: return "X86ISD::SHLD";
10926 case X86ISD::SHRD: return "X86ISD::SHRD";
10927 case X86ISD::FAND: return "X86ISD::FAND";
10928 case X86ISD::FOR: return "X86ISD::FOR";
10929 case X86ISD::FXOR: return "X86ISD::FXOR";
10930 case X86ISD::FSRL: return "X86ISD::FSRL";
10931 case X86ISD::FILD: return "X86ISD::FILD";
10932 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10933 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10934 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10935 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10936 case X86ISD::FLD: return "X86ISD::FLD";
10937 case X86ISD::FST: return "X86ISD::FST";
10938 case X86ISD::CALL: return "X86ISD::CALL";
10939 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10940 case X86ISD::BT: return "X86ISD::BT";
10941 case X86ISD::CMP: return "X86ISD::CMP";
10942 case X86ISD::COMI: return "X86ISD::COMI";
10943 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10944 case X86ISD::SETCC: return "X86ISD::SETCC";
10945 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10946 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10947 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10948 case X86ISD::CMOV: return "X86ISD::CMOV";
10949 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10950 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10951 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10952 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10953 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10954 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10955 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10956 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10957 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10958 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10959 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10960 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10961 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10962 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10963 case X86ISD::PSIGN: return "X86ISD::PSIGN";
10964 case X86ISD::BLENDV: return "X86ISD::BLENDV";
10965 case X86ISD::HADD: return "X86ISD::HADD";
10966 case X86ISD::HSUB: return "X86ISD::HSUB";
10967 case X86ISD::FHADD: return "X86ISD::FHADD";
10968 case X86ISD::FHSUB: return "X86ISD::FHSUB";
10969 case X86ISD::FMAX: return "X86ISD::FMAX";
10970 case X86ISD::FMIN: return "X86ISD::FMIN";
10971 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10972 case X86ISD::FRCP: return "X86ISD::FRCP";
10973 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10974 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10975 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10976 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10977 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10978 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10979 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10980 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10981 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10982 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10983 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10984 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10985 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10986 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10987 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10988 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
10989 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
10990 case X86ISD::VSHL: return "X86ISD::VSHL";
10991 case X86ISD::VSRL: return "X86ISD::VSRL";
10992 case X86ISD::VSRA: return "X86ISD::VSRA";
10993 case X86ISD::VSHLI: return "X86ISD::VSHLI";
10994 case X86ISD::VSRLI: return "X86ISD::VSRLI";
10995 case X86ISD::VSRAI: return "X86ISD::VSRAI";
10996 case X86ISD::CMPP: return "X86ISD::CMPP";
10997 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
10998 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
10999 case X86ISD::ADD: return "X86ISD::ADD";
11000 case X86ISD::SUB: return "X86ISD::SUB";
11001 case X86ISD::ADC: return "X86ISD::ADC";
11002 case X86ISD::SBB: return "X86ISD::SBB";
11003 case X86ISD::SMUL: return "X86ISD::SMUL";
11004 case X86ISD::UMUL: return "X86ISD::UMUL";
11005 case X86ISD::INC: return "X86ISD::INC";
11006 case X86ISD::DEC: return "X86ISD::DEC";
11007 case X86ISD::OR: return "X86ISD::OR";
11008 case X86ISD::XOR: return "X86ISD::XOR";
11009 case X86ISD::AND: return "X86ISD::AND";
11010 case X86ISD::ANDN: return "X86ISD::ANDN";
11011 case X86ISD::BLSI: return "X86ISD::BLSI";
11012 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11013 case X86ISD::BLSR: return "X86ISD::BLSR";
11014 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11015 case X86ISD::PTEST: return "X86ISD::PTEST";
11016 case X86ISD::TESTP: return "X86ISD::TESTP";
11017 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11018 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11019 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11020 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11021 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11022 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11023 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11024 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11025 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11026 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11027 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11028 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11029 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11030 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11031 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11032 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11033 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11034 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11035 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11036 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11037 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11038 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11039 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11040 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11041 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11042 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11043 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11047 // isLegalAddressingMode - Return true if the addressing mode represented
11048 // by AM is legal for this target, for a load/store of the specified type.
11049 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11051 // X86 supports extremely general addressing modes.
11052 CodeModel::Model M = getTargetMachine().getCodeModel();
11053 Reloc::Model R = getTargetMachine().getRelocationModel();
11055 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11056 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11061 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11063 // If a reference to this global requires an extra load, we can't fold it.
11064 if (isGlobalStubReference(GVFlags))
11067 // If BaseGV requires a register for the PIC base, we cannot also have a
11068 // BaseReg specified.
11069 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11072 // If lower 4G is not available, then we must use rip-relative addressing.
11073 if ((M != CodeModel::Small || R != Reloc::Static) &&
11074 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11078 switch (AM.Scale) {
11084 // These scales always work.
11089 // These scales are formed with basereg+scalereg. Only accept if there is
11094 default: // Other stuff never works.
11102 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11103 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11105 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11106 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11107 if (NumBits1 <= NumBits2)
11112 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11113 if (!VT1.isInteger() || !VT2.isInteger())
11115 unsigned NumBits1 = VT1.getSizeInBits();
11116 unsigned NumBits2 = VT2.getSizeInBits();
11117 if (NumBits1 <= NumBits2)
11122 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11123 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11124 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11127 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11128 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11129 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11132 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11133 // i16 instructions are longer (0x66 prefix) and potentially slower.
11134 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11137 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11138 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11139 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11140 /// are assumed to be legal.
11142 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11144 // Very little shuffling can be done for 64-bit vectors right now.
11145 if (VT.getSizeInBits() == 64)
11148 // FIXME: pshufb, blends, shifts.
11149 return (VT.getVectorNumElements() == 2 ||
11150 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11151 isMOVLMask(M, VT) ||
11152 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11153 isPSHUFDMask(M, VT) ||
11154 isPSHUFHWMask(M, VT) ||
11155 isPSHUFLWMask(M, VT) ||
11156 isPALIGNRMask(M, VT, Subtarget) ||
11157 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11158 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11159 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11160 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11164 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11166 unsigned NumElts = VT.getVectorNumElements();
11167 // FIXME: This collection of masks seems suspect.
11170 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11171 return (isMOVLMask(Mask, VT) ||
11172 isCommutedMOVLMask(Mask, VT, true) ||
11173 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11174 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11179 //===----------------------------------------------------------------------===//
11180 // X86 Scheduler Hooks
11181 //===----------------------------------------------------------------------===//
11183 // private utility function
11184 MachineBasicBlock *
11185 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11186 MachineBasicBlock *MBB,
11193 const TargetRegisterClass *RC,
11194 bool invSrc) const {
11195 // For the atomic bitwise operator, we generate
11198 // ld t1 = [bitinstr.addr]
11199 // op t2 = t1, [bitinstr.val]
11201 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11203 // fallthrough -->nextMBB
11204 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11205 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11206 MachineFunction::iterator MBBIter = MBB;
11209 /// First build the CFG
11210 MachineFunction *F = MBB->getParent();
11211 MachineBasicBlock *thisMBB = MBB;
11212 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11213 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11214 F->insert(MBBIter, newMBB);
11215 F->insert(MBBIter, nextMBB);
11217 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11218 nextMBB->splice(nextMBB->begin(), thisMBB,
11219 llvm::next(MachineBasicBlock::iterator(bInstr)),
11221 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11223 // Update thisMBB to fall through to newMBB
11224 thisMBB->addSuccessor(newMBB);
11226 // newMBB jumps to itself and fall through to nextMBB
11227 newMBB->addSuccessor(nextMBB);
11228 newMBB->addSuccessor(newMBB);
11230 // Insert instructions into newMBB based on incoming instruction
11231 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11232 "unexpected number of operands");
11233 DebugLoc dl = bInstr->getDebugLoc();
11234 MachineOperand& destOper = bInstr->getOperand(0);
11235 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11236 int numArgs = bInstr->getNumOperands() - 1;
11237 for (int i=0; i < numArgs; ++i)
11238 argOpers[i] = &bInstr->getOperand(i+1);
11240 // x86 address has 4 operands: base, index, scale, and displacement
11241 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11242 int valArgIndx = lastAddrIndx + 1;
11244 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11245 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11246 for (int i=0; i <= lastAddrIndx; ++i)
11247 (*MIB).addOperand(*argOpers[i]);
11249 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11251 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11256 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11257 assert((argOpers[valArgIndx]->isReg() ||
11258 argOpers[valArgIndx]->isImm()) &&
11259 "invalid operand");
11260 if (argOpers[valArgIndx]->isReg())
11261 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11263 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11265 (*MIB).addOperand(*argOpers[valArgIndx]);
11267 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11270 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11271 for (int i=0; i <= lastAddrIndx; ++i)
11272 (*MIB).addOperand(*argOpers[i]);
11274 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11275 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11276 bInstr->memoperands_end());
11278 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11279 MIB.addReg(EAXreg);
11282 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11284 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11288 // private utility function: 64 bit atomics on 32 bit host.
11289 MachineBasicBlock *
11290 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11291 MachineBasicBlock *MBB,
11296 bool invSrc) const {
11297 // For the atomic bitwise operator, we generate
11298 // thisMBB (instructions are in pairs, except cmpxchg8b)
11299 // ld t1,t2 = [bitinstr.addr]
11301 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11302 // op t5, t6 <- out1, out2, [bitinstr.val]
11303 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11304 // mov ECX, EBX <- t5, t6
11305 // mov EAX, EDX <- t1, t2
11306 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11307 // mov t3, t4 <- EAX, EDX
11309 // result in out1, out2
11310 // fallthrough -->nextMBB
11312 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11313 const unsigned LoadOpc = X86::MOV32rm;
11314 const unsigned NotOpc = X86::NOT32r;
11315 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11316 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11317 MachineFunction::iterator MBBIter = MBB;
11320 /// First build the CFG
11321 MachineFunction *F = MBB->getParent();
11322 MachineBasicBlock *thisMBB = MBB;
11323 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11324 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11325 F->insert(MBBIter, newMBB);
11326 F->insert(MBBIter, nextMBB);
11328 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11329 nextMBB->splice(nextMBB->begin(), thisMBB,
11330 llvm::next(MachineBasicBlock::iterator(bInstr)),
11332 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11334 // Update thisMBB to fall through to newMBB
11335 thisMBB->addSuccessor(newMBB);
11337 // newMBB jumps to itself and fall through to nextMBB
11338 newMBB->addSuccessor(nextMBB);
11339 newMBB->addSuccessor(newMBB);
11341 DebugLoc dl = bInstr->getDebugLoc();
11342 // Insert instructions into newMBB based on incoming instruction
11343 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11344 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11345 "unexpected number of operands");
11346 MachineOperand& dest1Oper = bInstr->getOperand(0);
11347 MachineOperand& dest2Oper = bInstr->getOperand(1);
11348 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11349 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11350 argOpers[i] = &bInstr->getOperand(i+2);
11352 // We use some of the operands multiple times, so conservatively just
11353 // clear any kill flags that might be present.
11354 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11355 argOpers[i]->setIsKill(false);
11358 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11359 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11361 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11362 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11363 for (int i=0; i <= lastAddrIndx; ++i)
11364 (*MIB).addOperand(*argOpers[i]);
11365 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11366 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11367 // add 4 to displacement.
11368 for (int i=0; i <= lastAddrIndx-2; ++i)
11369 (*MIB).addOperand(*argOpers[i]);
11370 MachineOperand newOp3 = *(argOpers[3]);
11371 if (newOp3.isImm())
11372 newOp3.setImm(newOp3.getImm()+4);
11374 newOp3.setOffset(newOp3.getOffset()+4);
11375 (*MIB).addOperand(newOp3);
11376 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11378 // t3/4 are defined later, at the bottom of the loop
11379 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11380 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11381 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11382 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11383 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11384 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11386 // The subsequent operations should be using the destination registers of
11387 //the PHI instructions.
11389 t1 = F->getRegInfo().createVirtualRegister(RC);
11390 t2 = F->getRegInfo().createVirtualRegister(RC);
11391 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11392 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11394 t1 = dest1Oper.getReg();
11395 t2 = dest2Oper.getReg();
11398 int valArgIndx = lastAddrIndx + 1;
11399 assert((argOpers[valArgIndx]->isReg() ||
11400 argOpers[valArgIndx]->isImm()) &&
11401 "invalid operand");
11402 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11403 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11404 if (argOpers[valArgIndx]->isReg())
11405 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11407 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11408 if (regOpcL != X86::MOV32rr)
11410 (*MIB).addOperand(*argOpers[valArgIndx]);
11411 assert(argOpers[valArgIndx + 1]->isReg() ==
11412 argOpers[valArgIndx]->isReg());
11413 assert(argOpers[valArgIndx + 1]->isImm() ==
11414 argOpers[valArgIndx]->isImm());
11415 if (argOpers[valArgIndx + 1]->isReg())
11416 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11418 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11419 if (regOpcH != X86::MOV32rr)
11421 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11423 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11425 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11428 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11430 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11433 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11434 for (int i=0; i <= lastAddrIndx; ++i)
11435 (*MIB).addOperand(*argOpers[i]);
11437 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11438 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11439 bInstr->memoperands_end());
11441 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11442 MIB.addReg(X86::EAX);
11443 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11444 MIB.addReg(X86::EDX);
11447 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11449 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11453 // private utility function
11454 MachineBasicBlock *
11455 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11456 MachineBasicBlock *MBB,
11457 unsigned cmovOpc) const {
11458 // For the atomic min/max operator, we generate
11461 // ld t1 = [min/max.addr]
11462 // mov t2 = [min/max.val]
11464 // cmov[cond] t2 = t1
11466 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11468 // fallthrough -->nextMBB
11470 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11471 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11472 MachineFunction::iterator MBBIter = MBB;
11475 /// First build the CFG
11476 MachineFunction *F = MBB->getParent();
11477 MachineBasicBlock *thisMBB = MBB;
11478 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11479 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11480 F->insert(MBBIter, newMBB);
11481 F->insert(MBBIter, nextMBB);
11483 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11484 nextMBB->splice(nextMBB->begin(), thisMBB,
11485 llvm::next(MachineBasicBlock::iterator(mInstr)),
11487 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11489 // Update thisMBB to fall through to newMBB
11490 thisMBB->addSuccessor(newMBB);
11492 // newMBB jumps to newMBB and fall through to nextMBB
11493 newMBB->addSuccessor(nextMBB);
11494 newMBB->addSuccessor(newMBB);
11496 DebugLoc dl = mInstr->getDebugLoc();
11497 // Insert instructions into newMBB based on incoming instruction
11498 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11499 "unexpected number of operands");
11500 MachineOperand& destOper = mInstr->getOperand(0);
11501 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11502 int numArgs = mInstr->getNumOperands() - 1;
11503 for (int i=0; i < numArgs; ++i)
11504 argOpers[i] = &mInstr->getOperand(i+1);
11506 // x86 address has 4 operands: base, index, scale, and displacement
11507 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11508 int valArgIndx = lastAddrIndx + 1;
11510 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11511 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11512 for (int i=0; i <= lastAddrIndx; ++i)
11513 (*MIB).addOperand(*argOpers[i]);
11515 // We only support register and immediate values
11516 assert((argOpers[valArgIndx]->isReg() ||
11517 argOpers[valArgIndx]->isImm()) &&
11518 "invalid operand");
11520 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11521 if (argOpers[valArgIndx]->isReg())
11522 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11524 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11525 (*MIB).addOperand(*argOpers[valArgIndx]);
11527 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11530 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11535 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11536 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11540 // Cmp and exchange if none has modified the memory location
11541 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11542 for (int i=0; i <= lastAddrIndx; ++i)
11543 (*MIB).addOperand(*argOpers[i]);
11545 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11546 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11547 mInstr->memoperands_end());
11549 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11550 MIB.addReg(X86::EAX);
11553 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11555 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11559 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11560 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11561 // in the .td file.
11562 MachineBasicBlock *
11563 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11564 unsigned numArgs, bool memArg) const {
11565 assert(Subtarget->hasSSE42() &&
11566 "Target must have SSE4.2 or AVX features enabled");
11568 DebugLoc dl = MI->getDebugLoc();
11569 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11571 if (!Subtarget->hasAVX()) {
11573 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11575 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11578 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11580 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11583 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11584 for (unsigned i = 0; i < numArgs; ++i) {
11585 MachineOperand &Op = MI->getOperand(i+1);
11586 if (!(Op.isReg() && Op.isImplicit()))
11587 MIB.addOperand(Op);
11589 BuildMI(*BB, MI, dl,
11590 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11591 MI->getOperand(0).getReg())
11592 .addReg(X86::XMM0);
11594 MI->eraseFromParent();
11598 MachineBasicBlock *
11599 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11600 DebugLoc dl = MI->getDebugLoc();
11601 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11603 // Address into RAX/EAX, other two args into ECX, EDX.
11604 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11605 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11606 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11607 for (int i = 0; i < X86::AddrNumOperands; ++i)
11608 MIB.addOperand(MI->getOperand(i));
11610 unsigned ValOps = X86::AddrNumOperands;
11611 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11612 .addReg(MI->getOperand(ValOps).getReg());
11613 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11614 .addReg(MI->getOperand(ValOps+1).getReg());
11616 // The instruction doesn't actually take any operands though.
11617 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11619 MI->eraseFromParent(); // The pseudo is gone now.
11623 MachineBasicBlock *
11624 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11625 DebugLoc dl = MI->getDebugLoc();
11626 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11628 // First arg in ECX, the second in EAX.
11629 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11630 .addReg(MI->getOperand(0).getReg());
11631 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11632 .addReg(MI->getOperand(1).getReg());
11634 // The instruction doesn't actually take any operands though.
11635 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11637 MI->eraseFromParent(); // The pseudo is gone now.
11641 MachineBasicBlock *
11642 X86TargetLowering::EmitVAARG64WithCustomInserter(
11644 MachineBasicBlock *MBB) const {
11645 // Emit va_arg instruction on X86-64.
11647 // Operands to this pseudo-instruction:
11648 // 0 ) Output : destination address (reg)
11649 // 1-5) Input : va_list address (addr, i64mem)
11650 // 6 ) ArgSize : Size (in bytes) of vararg type
11651 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11652 // 8 ) Align : Alignment of type
11653 // 9 ) EFLAGS (implicit-def)
11655 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11656 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11658 unsigned DestReg = MI->getOperand(0).getReg();
11659 MachineOperand &Base = MI->getOperand(1);
11660 MachineOperand &Scale = MI->getOperand(2);
11661 MachineOperand &Index = MI->getOperand(3);
11662 MachineOperand &Disp = MI->getOperand(4);
11663 MachineOperand &Segment = MI->getOperand(5);
11664 unsigned ArgSize = MI->getOperand(6).getImm();
11665 unsigned ArgMode = MI->getOperand(7).getImm();
11666 unsigned Align = MI->getOperand(8).getImm();
11668 // Memory Reference
11669 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11670 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11671 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11673 // Machine Information
11674 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11675 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11676 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11677 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11678 DebugLoc DL = MI->getDebugLoc();
11680 // struct va_list {
11683 // i64 overflow_area (address)
11684 // i64 reg_save_area (address)
11686 // sizeof(va_list) = 24
11687 // alignment(va_list) = 8
11689 unsigned TotalNumIntRegs = 6;
11690 unsigned TotalNumXMMRegs = 8;
11691 bool UseGPOffset = (ArgMode == 1);
11692 bool UseFPOffset = (ArgMode == 2);
11693 unsigned MaxOffset = TotalNumIntRegs * 8 +
11694 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11696 /* Align ArgSize to a multiple of 8 */
11697 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11698 bool NeedsAlign = (Align > 8);
11700 MachineBasicBlock *thisMBB = MBB;
11701 MachineBasicBlock *overflowMBB;
11702 MachineBasicBlock *offsetMBB;
11703 MachineBasicBlock *endMBB;
11705 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11706 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11707 unsigned OffsetReg = 0;
11709 if (!UseGPOffset && !UseFPOffset) {
11710 // If we only pull from the overflow region, we don't create a branch.
11711 // We don't need to alter control flow.
11712 OffsetDestReg = 0; // unused
11713 OverflowDestReg = DestReg;
11716 overflowMBB = thisMBB;
11719 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11720 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11721 // If not, pull from overflow_area. (branch to overflowMBB)
11726 // offsetMBB overflowMBB
11731 // Registers for the PHI in endMBB
11732 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11733 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11735 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11736 MachineFunction *MF = MBB->getParent();
11737 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11738 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11739 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11741 MachineFunction::iterator MBBIter = MBB;
11744 // Insert the new basic blocks
11745 MF->insert(MBBIter, offsetMBB);
11746 MF->insert(MBBIter, overflowMBB);
11747 MF->insert(MBBIter, endMBB);
11749 // Transfer the remainder of MBB and its successor edges to endMBB.
11750 endMBB->splice(endMBB->begin(), thisMBB,
11751 llvm::next(MachineBasicBlock::iterator(MI)),
11753 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11755 // Make offsetMBB and overflowMBB successors of thisMBB
11756 thisMBB->addSuccessor(offsetMBB);
11757 thisMBB->addSuccessor(overflowMBB);
11759 // endMBB is a successor of both offsetMBB and overflowMBB
11760 offsetMBB->addSuccessor(endMBB);
11761 overflowMBB->addSuccessor(endMBB);
11763 // Load the offset value into a register
11764 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11765 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11769 .addDisp(Disp, UseFPOffset ? 4 : 0)
11770 .addOperand(Segment)
11771 .setMemRefs(MMOBegin, MMOEnd);
11773 // Check if there is enough room left to pull this argument.
11774 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11776 .addImm(MaxOffset + 8 - ArgSizeA8);
11778 // Branch to "overflowMBB" if offset >= max
11779 // Fall through to "offsetMBB" otherwise
11780 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11781 .addMBB(overflowMBB);
11784 // In offsetMBB, emit code to use the reg_save_area.
11786 assert(OffsetReg != 0);
11788 // Read the reg_save_area address.
11789 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11790 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11795 .addOperand(Segment)
11796 .setMemRefs(MMOBegin, MMOEnd);
11798 // Zero-extend the offset
11799 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11800 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11803 .addImm(X86::sub_32bit);
11805 // Add the offset to the reg_save_area to get the final address.
11806 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11807 .addReg(OffsetReg64)
11808 .addReg(RegSaveReg);
11810 // Compute the offset for the next argument
11811 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11812 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11814 .addImm(UseFPOffset ? 16 : 8);
11816 // Store it back into the va_list.
11817 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11821 .addDisp(Disp, UseFPOffset ? 4 : 0)
11822 .addOperand(Segment)
11823 .addReg(NextOffsetReg)
11824 .setMemRefs(MMOBegin, MMOEnd);
11827 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11832 // Emit code to use overflow area
11835 // Load the overflow_area address into a register.
11836 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11837 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11842 .addOperand(Segment)
11843 .setMemRefs(MMOBegin, MMOEnd);
11845 // If we need to align it, do so. Otherwise, just copy the address
11846 // to OverflowDestReg.
11848 // Align the overflow address
11849 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11850 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11852 // aligned_addr = (addr + (align-1)) & ~(align-1)
11853 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11854 .addReg(OverflowAddrReg)
11857 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11859 .addImm(~(uint64_t)(Align-1));
11861 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11862 .addReg(OverflowAddrReg);
11865 // Compute the next overflow address after this argument.
11866 // (the overflow address should be kept 8-byte aligned)
11867 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11868 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11869 .addReg(OverflowDestReg)
11870 .addImm(ArgSizeA8);
11872 // Store the new overflow address.
11873 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11878 .addOperand(Segment)
11879 .addReg(NextAddrReg)
11880 .setMemRefs(MMOBegin, MMOEnd);
11882 // If we branched, emit the PHI to the front of endMBB.
11884 BuildMI(*endMBB, endMBB->begin(), DL,
11885 TII->get(X86::PHI), DestReg)
11886 .addReg(OffsetDestReg).addMBB(offsetMBB)
11887 .addReg(OverflowDestReg).addMBB(overflowMBB);
11890 // Erase the pseudo instruction
11891 MI->eraseFromParent();
11896 MachineBasicBlock *
11897 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11899 MachineBasicBlock *MBB) const {
11900 // Emit code to save XMM registers to the stack. The ABI says that the
11901 // number of registers to save is given in %al, so it's theoretically
11902 // possible to do an indirect jump trick to avoid saving all of them,
11903 // however this code takes a simpler approach and just executes all
11904 // of the stores if %al is non-zero. It's less code, and it's probably
11905 // easier on the hardware branch predictor, and stores aren't all that
11906 // expensive anyway.
11908 // Create the new basic blocks. One block contains all the XMM stores,
11909 // and one block is the final destination regardless of whether any
11910 // stores were performed.
11911 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11912 MachineFunction *F = MBB->getParent();
11913 MachineFunction::iterator MBBIter = MBB;
11915 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11916 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11917 F->insert(MBBIter, XMMSaveMBB);
11918 F->insert(MBBIter, EndMBB);
11920 // Transfer the remainder of MBB and its successor edges to EndMBB.
11921 EndMBB->splice(EndMBB->begin(), MBB,
11922 llvm::next(MachineBasicBlock::iterator(MI)),
11924 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11926 // The original block will now fall through to the XMM save block.
11927 MBB->addSuccessor(XMMSaveMBB);
11928 // The XMMSaveMBB will fall through to the end block.
11929 XMMSaveMBB->addSuccessor(EndMBB);
11931 // Now add the instructions.
11932 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11933 DebugLoc DL = MI->getDebugLoc();
11935 unsigned CountReg = MI->getOperand(0).getReg();
11936 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11937 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11939 if (!Subtarget->isTargetWin64()) {
11940 // If %al is 0, branch around the XMM save block.
11941 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11942 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11943 MBB->addSuccessor(EndMBB);
11946 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11947 // In the XMM save block, save all the XMM argument registers.
11948 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11949 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11950 MachineMemOperand *MMO =
11951 F->getMachineMemOperand(
11952 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11953 MachineMemOperand::MOStore,
11954 /*Size=*/16, /*Align=*/16);
11955 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11956 .addFrameIndex(RegSaveFrameIndex)
11957 .addImm(/*Scale=*/1)
11958 .addReg(/*IndexReg=*/0)
11959 .addImm(/*Disp=*/Offset)
11960 .addReg(/*Segment=*/0)
11961 .addReg(MI->getOperand(i).getReg())
11962 .addMemOperand(MMO);
11965 MI->eraseFromParent(); // The pseudo instruction is gone now.
11970 // The EFLAGS operand of SelectItr might be missing a kill marker
11971 // because there were multiple uses of EFLAGS, and ISel didn't know
11972 // which to mark. Figure out whether SelectItr should have had a
11973 // kill marker, and set it if it should. Returns the correct kill
11975 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
11976 MachineBasicBlock* BB,
11977 const TargetRegisterInfo* TRI) {
11978 // Scan forward through BB for a use/def of EFLAGS.
11979 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
11980 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
11981 const MachineInstr& mi = *miI;
11982 if (mi.readsRegister(X86::EFLAGS))
11984 if (mi.definesRegister(X86::EFLAGS))
11985 break; // Should have kill-flag - update below.
11988 // If we hit the end of the block, check whether EFLAGS is live into a
11990 if (miI == BB->end()) {
11991 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
11992 sEnd = BB->succ_end();
11993 sItr != sEnd; ++sItr) {
11994 MachineBasicBlock* succ = *sItr;
11995 if (succ->isLiveIn(X86::EFLAGS))
12000 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12001 // out. SelectMI should have a kill flag on EFLAGS.
12002 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12006 MachineBasicBlock *
12007 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12008 MachineBasicBlock *BB) const {
12009 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12010 DebugLoc DL = MI->getDebugLoc();
12012 // To "insert" a SELECT_CC instruction, we actually have to insert the
12013 // diamond control-flow pattern. The incoming instruction knows the
12014 // destination vreg to set, the condition code register to branch on, the
12015 // true/false values to select between, and a branch opcode to use.
12016 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12017 MachineFunction::iterator It = BB;
12023 // cmpTY ccX, r1, r2
12025 // fallthrough --> copy0MBB
12026 MachineBasicBlock *thisMBB = BB;
12027 MachineFunction *F = BB->getParent();
12028 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12029 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12030 F->insert(It, copy0MBB);
12031 F->insert(It, sinkMBB);
12033 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12034 // live into the sink and copy blocks.
12035 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12036 if (!MI->killsRegister(X86::EFLAGS) &&
12037 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12038 copy0MBB->addLiveIn(X86::EFLAGS);
12039 sinkMBB->addLiveIn(X86::EFLAGS);
12042 // Transfer the remainder of BB and its successor edges to sinkMBB.
12043 sinkMBB->splice(sinkMBB->begin(), BB,
12044 llvm::next(MachineBasicBlock::iterator(MI)),
12046 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12048 // Add the true and fallthrough blocks as its successors.
12049 BB->addSuccessor(copy0MBB);
12050 BB->addSuccessor(sinkMBB);
12052 // Create the conditional branch instruction.
12054 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12055 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12058 // %FalseValue = ...
12059 // # fallthrough to sinkMBB
12060 copy0MBB->addSuccessor(sinkMBB);
12063 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12065 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12066 TII->get(X86::PHI), MI->getOperand(0).getReg())
12067 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12068 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12070 MI->eraseFromParent(); // The pseudo instruction is gone now.
12074 MachineBasicBlock *
12075 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12076 bool Is64Bit) const {
12077 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12078 DebugLoc DL = MI->getDebugLoc();
12079 MachineFunction *MF = BB->getParent();
12080 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12082 assert(getTargetMachine().Options.EnableSegmentedStacks);
12084 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12085 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12088 // ... [Till the alloca]
12089 // If stacklet is not large enough, jump to mallocMBB
12092 // Allocate by subtracting from RSP
12093 // Jump to continueMBB
12096 // Allocate by call to runtime
12100 // [rest of original BB]
12103 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12104 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12105 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12107 MachineRegisterInfo &MRI = MF->getRegInfo();
12108 const TargetRegisterClass *AddrRegClass =
12109 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12111 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12112 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12113 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12114 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12115 sizeVReg = MI->getOperand(1).getReg(),
12116 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12118 MachineFunction::iterator MBBIter = BB;
12121 MF->insert(MBBIter, bumpMBB);
12122 MF->insert(MBBIter, mallocMBB);
12123 MF->insert(MBBIter, continueMBB);
12125 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12126 (MachineBasicBlock::iterator(MI)), BB->end());
12127 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12129 // Add code to the main basic block to check if the stack limit has been hit,
12130 // and if so, jump to mallocMBB otherwise to bumpMBB.
12131 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12132 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12133 .addReg(tmpSPVReg).addReg(sizeVReg);
12134 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12135 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12136 .addReg(SPLimitVReg);
12137 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12139 // bumpMBB simply decreases the stack pointer, since we know the current
12140 // stacklet has enough space.
12141 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12142 .addReg(SPLimitVReg);
12143 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12144 .addReg(SPLimitVReg);
12145 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12147 // Calls into a routine in libgcc to allocate more space from the heap.
12148 const uint32_t *RegMask =
12149 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12151 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12153 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12154 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12155 .addRegMask(RegMask)
12156 .addReg(X86::RAX, RegState::ImplicitDefine);
12158 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12160 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12161 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12162 .addExternalSymbol("__morestack_allocate_stack_space")
12163 .addRegMask(RegMask)
12164 .addReg(X86::EAX, RegState::ImplicitDefine);
12168 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12171 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12172 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12173 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12175 // Set up the CFG correctly.
12176 BB->addSuccessor(bumpMBB);
12177 BB->addSuccessor(mallocMBB);
12178 mallocMBB->addSuccessor(continueMBB);
12179 bumpMBB->addSuccessor(continueMBB);
12181 // Take care of the PHI nodes.
12182 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12183 MI->getOperand(0).getReg())
12184 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12185 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12187 // Delete the original pseudo instruction.
12188 MI->eraseFromParent();
12191 return continueMBB;
12194 MachineBasicBlock *
12195 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12196 MachineBasicBlock *BB) const {
12197 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12198 DebugLoc DL = MI->getDebugLoc();
12200 assert(!Subtarget->isTargetEnvMacho());
12202 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12203 // non-trivial part is impdef of ESP.
12205 if (Subtarget->isTargetWin64()) {
12206 if (Subtarget->isTargetCygMing()) {
12207 // ___chkstk(Mingw64):
12208 // Clobbers R10, R11, RAX and EFLAGS.
12210 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12211 .addExternalSymbol("___chkstk")
12212 .addReg(X86::RAX, RegState::Implicit)
12213 .addReg(X86::RSP, RegState::Implicit)
12214 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12215 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12216 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12218 // __chkstk(MSVCRT): does not update stack pointer.
12219 // Clobbers R10, R11 and EFLAGS.
12220 // FIXME: RAX(allocated size) might be reused and not killed.
12221 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12222 .addExternalSymbol("__chkstk")
12223 .addReg(X86::RAX, RegState::Implicit)
12224 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12225 // RAX has the offset to subtracted from RSP.
12226 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12231 const char *StackProbeSymbol =
12232 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12234 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12235 .addExternalSymbol(StackProbeSymbol)
12236 .addReg(X86::EAX, RegState::Implicit)
12237 .addReg(X86::ESP, RegState::Implicit)
12238 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12239 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12240 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12243 MI->eraseFromParent(); // The pseudo instruction is gone now.
12247 MachineBasicBlock *
12248 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12249 MachineBasicBlock *BB) const {
12250 // This is pretty easy. We're taking the value that we received from
12251 // our load from the relocation, sticking it in either RDI (x86-64)
12252 // or EAX and doing an indirect call. The return value will then
12253 // be in the normal return register.
12254 const X86InstrInfo *TII
12255 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12256 DebugLoc DL = MI->getDebugLoc();
12257 MachineFunction *F = BB->getParent();
12259 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12260 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12262 // Get a register mask for the lowered call.
12263 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12264 // proper register mask.
12265 const uint32_t *RegMask =
12266 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12267 if (Subtarget->is64Bit()) {
12268 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12269 TII->get(X86::MOV64rm), X86::RDI)
12271 .addImm(0).addReg(0)
12272 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12273 MI->getOperand(3).getTargetFlags())
12275 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12276 addDirectMem(MIB, X86::RDI);
12277 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12278 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12279 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12280 TII->get(X86::MOV32rm), X86::EAX)
12282 .addImm(0).addReg(0)
12283 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12284 MI->getOperand(3).getTargetFlags())
12286 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12287 addDirectMem(MIB, X86::EAX);
12288 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12290 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12291 TII->get(X86::MOV32rm), X86::EAX)
12292 .addReg(TII->getGlobalBaseReg(F))
12293 .addImm(0).addReg(0)
12294 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12295 MI->getOperand(3).getTargetFlags())
12297 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12298 addDirectMem(MIB, X86::EAX);
12299 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12302 MI->eraseFromParent(); // The pseudo instruction is gone now.
12306 MachineBasicBlock *
12307 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12308 MachineBasicBlock *BB) const {
12309 switch (MI->getOpcode()) {
12310 default: llvm_unreachable("Unexpected instr type to insert");
12311 case X86::TAILJMPd64:
12312 case X86::TAILJMPr64:
12313 case X86::TAILJMPm64:
12314 llvm_unreachable("TAILJMP64 would not be touched here.");
12315 case X86::TCRETURNdi64:
12316 case X86::TCRETURNri64:
12317 case X86::TCRETURNmi64:
12319 case X86::WIN_ALLOCA:
12320 return EmitLoweredWinAlloca(MI, BB);
12321 case X86::SEG_ALLOCA_32:
12322 return EmitLoweredSegAlloca(MI, BB, false);
12323 case X86::SEG_ALLOCA_64:
12324 return EmitLoweredSegAlloca(MI, BB, true);
12325 case X86::TLSCall_32:
12326 case X86::TLSCall_64:
12327 return EmitLoweredTLSCall(MI, BB);
12328 case X86::CMOV_GR8:
12329 case X86::CMOV_FR32:
12330 case X86::CMOV_FR64:
12331 case X86::CMOV_V4F32:
12332 case X86::CMOV_V2F64:
12333 case X86::CMOV_V2I64:
12334 case X86::CMOV_V8F32:
12335 case X86::CMOV_V4F64:
12336 case X86::CMOV_V4I64:
12337 case X86::CMOV_GR16:
12338 case X86::CMOV_GR32:
12339 case X86::CMOV_RFP32:
12340 case X86::CMOV_RFP64:
12341 case X86::CMOV_RFP80:
12342 return EmitLoweredSelect(MI, BB);
12344 case X86::FP32_TO_INT16_IN_MEM:
12345 case X86::FP32_TO_INT32_IN_MEM:
12346 case X86::FP32_TO_INT64_IN_MEM:
12347 case X86::FP64_TO_INT16_IN_MEM:
12348 case X86::FP64_TO_INT32_IN_MEM:
12349 case X86::FP64_TO_INT64_IN_MEM:
12350 case X86::FP80_TO_INT16_IN_MEM:
12351 case X86::FP80_TO_INT32_IN_MEM:
12352 case X86::FP80_TO_INT64_IN_MEM: {
12353 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12354 DebugLoc DL = MI->getDebugLoc();
12356 // Change the floating point control register to use "round towards zero"
12357 // mode when truncating to an integer value.
12358 MachineFunction *F = BB->getParent();
12359 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12360 addFrameReference(BuildMI(*BB, MI, DL,
12361 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12363 // Load the old value of the high byte of the control word...
12365 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12366 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12369 // Set the high part to be round to zero...
12370 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12373 // Reload the modified control word now...
12374 addFrameReference(BuildMI(*BB, MI, DL,
12375 TII->get(X86::FLDCW16m)), CWFrameIdx);
12377 // Restore the memory image of control word to original value
12378 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12381 // Get the X86 opcode to use.
12383 switch (MI->getOpcode()) {
12384 default: llvm_unreachable("illegal opcode!");
12385 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12386 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12387 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12388 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12389 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12390 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12391 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12392 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12393 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12397 MachineOperand &Op = MI->getOperand(0);
12399 AM.BaseType = X86AddressMode::RegBase;
12400 AM.Base.Reg = Op.getReg();
12402 AM.BaseType = X86AddressMode::FrameIndexBase;
12403 AM.Base.FrameIndex = Op.getIndex();
12405 Op = MI->getOperand(1);
12407 AM.Scale = Op.getImm();
12408 Op = MI->getOperand(2);
12410 AM.IndexReg = Op.getImm();
12411 Op = MI->getOperand(3);
12412 if (Op.isGlobal()) {
12413 AM.GV = Op.getGlobal();
12415 AM.Disp = Op.getImm();
12417 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12418 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12420 // Reload the original control word now.
12421 addFrameReference(BuildMI(*BB, MI, DL,
12422 TII->get(X86::FLDCW16m)), CWFrameIdx);
12424 MI->eraseFromParent(); // The pseudo instruction is gone now.
12427 // String/text processing lowering.
12428 case X86::PCMPISTRM128REG:
12429 case X86::VPCMPISTRM128REG:
12430 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12431 case X86::PCMPISTRM128MEM:
12432 case X86::VPCMPISTRM128MEM:
12433 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12434 case X86::PCMPESTRM128REG:
12435 case X86::VPCMPESTRM128REG:
12436 return EmitPCMP(MI, BB, 5, false /* in mem */);
12437 case X86::PCMPESTRM128MEM:
12438 case X86::VPCMPESTRM128MEM:
12439 return EmitPCMP(MI, BB, 5, true /* in mem */);
12441 // Thread synchronization.
12443 return EmitMonitor(MI, BB);
12445 return EmitMwait(MI, BB);
12447 // Atomic Lowering.
12448 case X86::ATOMAND32:
12449 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12450 X86::AND32ri, X86::MOV32rm,
12452 X86::NOT32r, X86::EAX,
12453 X86::GR32RegisterClass);
12454 case X86::ATOMOR32:
12455 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12456 X86::OR32ri, X86::MOV32rm,
12458 X86::NOT32r, X86::EAX,
12459 X86::GR32RegisterClass);
12460 case X86::ATOMXOR32:
12461 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12462 X86::XOR32ri, X86::MOV32rm,
12464 X86::NOT32r, X86::EAX,
12465 X86::GR32RegisterClass);
12466 case X86::ATOMNAND32:
12467 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12468 X86::AND32ri, X86::MOV32rm,
12470 X86::NOT32r, X86::EAX,
12471 X86::GR32RegisterClass, true);
12472 case X86::ATOMMIN32:
12473 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12474 case X86::ATOMMAX32:
12475 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12476 case X86::ATOMUMIN32:
12477 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12478 case X86::ATOMUMAX32:
12479 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12481 case X86::ATOMAND16:
12482 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12483 X86::AND16ri, X86::MOV16rm,
12485 X86::NOT16r, X86::AX,
12486 X86::GR16RegisterClass);
12487 case X86::ATOMOR16:
12488 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12489 X86::OR16ri, X86::MOV16rm,
12491 X86::NOT16r, X86::AX,
12492 X86::GR16RegisterClass);
12493 case X86::ATOMXOR16:
12494 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12495 X86::XOR16ri, X86::MOV16rm,
12497 X86::NOT16r, X86::AX,
12498 X86::GR16RegisterClass);
12499 case X86::ATOMNAND16:
12500 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12501 X86::AND16ri, X86::MOV16rm,
12503 X86::NOT16r, X86::AX,
12504 X86::GR16RegisterClass, true);
12505 case X86::ATOMMIN16:
12506 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12507 case X86::ATOMMAX16:
12508 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12509 case X86::ATOMUMIN16:
12510 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12511 case X86::ATOMUMAX16:
12512 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12514 case X86::ATOMAND8:
12515 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12516 X86::AND8ri, X86::MOV8rm,
12518 X86::NOT8r, X86::AL,
12519 X86::GR8RegisterClass);
12521 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12522 X86::OR8ri, X86::MOV8rm,
12524 X86::NOT8r, X86::AL,
12525 X86::GR8RegisterClass);
12526 case X86::ATOMXOR8:
12527 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12528 X86::XOR8ri, X86::MOV8rm,
12530 X86::NOT8r, X86::AL,
12531 X86::GR8RegisterClass);
12532 case X86::ATOMNAND8:
12533 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12534 X86::AND8ri, X86::MOV8rm,
12536 X86::NOT8r, X86::AL,
12537 X86::GR8RegisterClass, true);
12538 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12539 // This group is for 64-bit host.
12540 case X86::ATOMAND64:
12541 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12542 X86::AND64ri32, X86::MOV64rm,
12544 X86::NOT64r, X86::RAX,
12545 X86::GR64RegisterClass);
12546 case X86::ATOMOR64:
12547 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12548 X86::OR64ri32, X86::MOV64rm,
12550 X86::NOT64r, X86::RAX,
12551 X86::GR64RegisterClass);
12552 case X86::ATOMXOR64:
12553 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12554 X86::XOR64ri32, X86::MOV64rm,
12556 X86::NOT64r, X86::RAX,
12557 X86::GR64RegisterClass);
12558 case X86::ATOMNAND64:
12559 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12560 X86::AND64ri32, X86::MOV64rm,
12562 X86::NOT64r, X86::RAX,
12563 X86::GR64RegisterClass, true);
12564 case X86::ATOMMIN64:
12565 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12566 case X86::ATOMMAX64:
12567 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12568 case X86::ATOMUMIN64:
12569 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12570 case X86::ATOMUMAX64:
12571 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12573 // This group does 64-bit operations on a 32-bit host.
12574 case X86::ATOMAND6432:
12575 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12576 X86::AND32rr, X86::AND32rr,
12577 X86::AND32ri, X86::AND32ri,
12579 case X86::ATOMOR6432:
12580 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12581 X86::OR32rr, X86::OR32rr,
12582 X86::OR32ri, X86::OR32ri,
12584 case X86::ATOMXOR6432:
12585 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12586 X86::XOR32rr, X86::XOR32rr,
12587 X86::XOR32ri, X86::XOR32ri,
12589 case X86::ATOMNAND6432:
12590 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12591 X86::AND32rr, X86::AND32rr,
12592 X86::AND32ri, X86::AND32ri,
12594 case X86::ATOMADD6432:
12595 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12596 X86::ADD32rr, X86::ADC32rr,
12597 X86::ADD32ri, X86::ADC32ri,
12599 case X86::ATOMSUB6432:
12600 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12601 X86::SUB32rr, X86::SBB32rr,
12602 X86::SUB32ri, X86::SBB32ri,
12604 case X86::ATOMSWAP6432:
12605 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12606 X86::MOV32rr, X86::MOV32rr,
12607 X86::MOV32ri, X86::MOV32ri,
12609 case X86::VASTART_SAVE_XMM_REGS:
12610 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12612 case X86::VAARG_64:
12613 return EmitVAARG64WithCustomInserter(MI, BB);
12617 //===----------------------------------------------------------------------===//
12618 // X86 Optimization Hooks
12619 //===----------------------------------------------------------------------===//
12621 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12625 const SelectionDAG &DAG,
12626 unsigned Depth) const {
12627 unsigned Opc = Op.getOpcode();
12628 assert((Opc >= ISD::BUILTIN_OP_END ||
12629 Opc == ISD::INTRINSIC_WO_CHAIN ||
12630 Opc == ISD::INTRINSIC_W_CHAIN ||
12631 Opc == ISD::INTRINSIC_VOID) &&
12632 "Should use MaskedValueIsZero if you don't know whether Op"
12633 " is a target node!");
12635 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12649 // These nodes' second result is a boolean.
12650 if (Op.getResNo() == 0)
12653 case X86ISD::SETCC:
12654 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12655 Mask.getBitWidth() - 1);
12657 case ISD::INTRINSIC_WO_CHAIN: {
12658 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12659 unsigned NumLoBits = 0;
12662 case Intrinsic::x86_sse_movmsk_ps:
12663 case Intrinsic::x86_avx_movmsk_ps_256:
12664 case Intrinsic::x86_sse2_movmsk_pd:
12665 case Intrinsic::x86_avx_movmsk_pd_256:
12666 case Intrinsic::x86_mmx_pmovmskb:
12667 case Intrinsic::x86_sse2_pmovmskb_128:
12668 case Intrinsic::x86_avx2_pmovmskb: {
12669 // High bits of movmskp{s|d}, pmovmskb are known zero.
12671 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12672 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12673 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12674 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12675 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12676 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12677 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12678 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12680 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12681 Mask.getBitWidth() - NumLoBits);
12690 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12691 unsigned Depth) const {
12692 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12693 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12694 return Op.getValueType().getScalarType().getSizeInBits();
12700 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12701 /// node is a GlobalAddress + offset.
12702 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12703 const GlobalValue* &GA,
12704 int64_t &Offset) const {
12705 if (N->getOpcode() == X86ISD::Wrapper) {
12706 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12707 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12708 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12712 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12715 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12716 /// same as extracting the high 128-bit part of 256-bit vector and then
12717 /// inserting the result into the low part of a new 256-bit vector
12718 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12719 EVT VT = SVOp->getValueType(0);
12720 int NumElems = VT.getVectorNumElements();
12722 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12723 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12724 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12725 SVOp->getMaskElt(j) >= 0)
12731 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12732 /// same as extracting the low 128-bit part of 256-bit vector and then
12733 /// inserting the result into the high part of a new 256-bit vector
12734 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12735 EVT VT = SVOp->getValueType(0);
12736 int NumElems = VT.getVectorNumElements();
12738 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12739 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12740 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12741 SVOp->getMaskElt(j) >= 0)
12747 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12748 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12749 TargetLowering::DAGCombinerInfo &DCI,
12750 const X86Subtarget* Subtarget) {
12751 DebugLoc dl = N->getDebugLoc();
12752 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12753 SDValue V1 = SVOp->getOperand(0);
12754 SDValue V2 = SVOp->getOperand(1);
12755 EVT VT = SVOp->getValueType(0);
12756 int NumElems = VT.getVectorNumElements();
12758 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12759 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12763 // V UNDEF BUILD_VECTOR UNDEF
12765 // CONCAT_VECTOR CONCAT_VECTOR
12768 // RESULT: V + zero extended
12770 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12771 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12772 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12775 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12778 // To match the shuffle mask, the first half of the mask should
12779 // be exactly the first vector, and all the rest a splat with the
12780 // first element of the second one.
12781 for (int i = 0; i < NumElems/2; ++i)
12782 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12783 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12786 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12787 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12788 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12789 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12791 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12793 Ld->getPointerInfo(),
12794 Ld->getAlignment(),
12795 false/*isVolatile*/, true/*ReadMem*/,
12796 false/*WriteMem*/);
12797 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12800 // Emit a zeroed vector and insert the desired subvector on its
12802 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12803 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12804 DAG.getConstant(0, MVT::i32), DAG, dl);
12805 return DCI.CombineTo(N, InsV);
12808 //===--------------------------------------------------------------------===//
12809 // Combine some shuffles into subvector extracts and inserts:
12812 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12813 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12814 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12816 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12817 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12818 return DCI.CombineTo(N, InsV);
12821 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12822 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12823 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12824 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12825 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12826 return DCI.CombineTo(N, InsV);
12832 /// PerformShuffleCombine - Performs several different shuffle combines.
12833 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12834 TargetLowering::DAGCombinerInfo &DCI,
12835 const X86Subtarget *Subtarget) {
12836 DebugLoc dl = N->getDebugLoc();
12837 EVT VT = N->getValueType(0);
12839 // Don't create instructions with illegal types after legalize types has run.
12840 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12841 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12844 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12845 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12846 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12847 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12849 // Only handle 128 wide vector from here on.
12850 if (VT.getSizeInBits() != 128)
12853 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12854 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12855 // consecutive, non-overlapping, and in the right order.
12856 SmallVector<SDValue, 16> Elts;
12857 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12858 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12860 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12864 /// PerformTruncateCombine - Converts truncate operation to
12865 /// a sequence of vector shuffle operations.
12866 /// It is possible when we truncate 256-bit vector to 128-bit vector
12868 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12869 DAGCombinerInfo &DCI) const {
12870 if (!DCI.isBeforeLegalizeOps())
12873 if (!Subtarget->hasAVX()) return SDValue();
12875 EVT VT = N->getValueType(0);
12876 SDValue Op = N->getOperand(0);
12877 EVT OpVT = Op.getValueType();
12878 DebugLoc dl = N->getDebugLoc();
12880 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
12882 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12883 DAG.getIntPtrConstant(0));
12885 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12886 DAG.getIntPtrConstant(2));
12888 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12889 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12892 int ShufMask1[] = {0, 2, 0, 0};
12894 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
12896 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
12900 int ShufMask2[] = {0, 1, 4, 5};
12902 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
12904 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
12906 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12907 DAG.getIntPtrConstant(0));
12909 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12910 DAG.getIntPtrConstant(4));
12912 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
12913 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
12916 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12917 -1, -1, -1, -1, -1, -1, -1, -1};
12919 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
12920 DAG.getUNDEF(MVT::v16i8),
12922 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
12923 DAG.getUNDEF(MVT::v16i8),
12926 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12927 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12930 int ShufMask2[] = {0, 1, 4, 5};
12932 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
12933 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
12939 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
12940 /// specific shuffle of a load can be folded into a single element load.
12941 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
12942 /// shuffles have been customed lowered so we need to handle those here.
12943 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
12944 TargetLowering::DAGCombinerInfo &DCI) {
12945 if (DCI.isBeforeLegalizeOps())
12948 SDValue InVec = N->getOperand(0);
12949 SDValue EltNo = N->getOperand(1);
12951 if (!isa<ConstantSDNode>(EltNo))
12954 EVT VT = InVec.getValueType();
12956 bool HasShuffleIntoBitcast = false;
12957 if (InVec.getOpcode() == ISD::BITCAST) {
12958 // Don't duplicate a load with other uses.
12959 if (!InVec.hasOneUse())
12961 EVT BCVT = InVec.getOperand(0).getValueType();
12962 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
12964 InVec = InVec.getOperand(0);
12965 HasShuffleIntoBitcast = true;
12968 if (!isTargetShuffle(InVec.getOpcode()))
12971 // Don't duplicate a load with other uses.
12972 if (!InVec.hasOneUse())
12975 SmallVector<int, 16> ShuffleMask;
12977 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
12980 // Select the input vector, guarding against out of range extract vector.
12981 unsigned NumElems = VT.getVectorNumElements();
12982 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
12983 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
12984 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
12985 : InVec.getOperand(1);
12987 // If inputs to shuffle are the same for both ops, then allow 2 uses
12988 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
12990 if (LdNode.getOpcode() == ISD::BITCAST) {
12991 // Don't duplicate a load with other uses.
12992 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
12995 AllowedUses = 1; // only allow 1 load use if we have a bitcast
12996 LdNode = LdNode.getOperand(0);
12999 if (!ISD::isNormalLoad(LdNode.getNode()))
13002 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13004 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13007 if (HasShuffleIntoBitcast) {
13008 // If there's a bitcast before the shuffle, check if the load type and
13009 // alignment is valid.
13010 unsigned Align = LN0->getAlignment();
13011 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13012 unsigned NewAlign = TLI.getTargetData()->
13013 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13015 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13019 // All checks match so transform back to vector_shuffle so that DAG combiner
13020 // can finish the job
13021 DebugLoc dl = N->getDebugLoc();
13023 // Create shuffle node taking into account the case that its a unary shuffle
13024 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13025 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13026 InVec.getOperand(0), Shuffle,
13028 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13029 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13033 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13034 /// generation and convert it from being a bunch of shuffles and extracts
13035 /// to a simple store and scalar loads to extract the elements.
13036 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13037 TargetLowering::DAGCombinerInfo &DCI) {
13038 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13039 if (NewOp.getNode())
13042 SDValue InputVector = N->getOperand(0);
13044 // Only operate on vectors of 4 elements, where the alternative shuffling
13045 // gets to be more expensive.
13046 if (InputVector.getValueType() != MVT::v4i32)
13049 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13050 // single use which is a sign-extend or zero-extend, and all elements are
13052 SmallVector<SDNode *, 4> Uses;
13053 unsigned ExtractedElements = 0;
13054 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13055 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13056 if (UI.getUse().getResNo() != InputVector.getResNo())
13059 SDNode *Extract = *UI;
13060 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13063 if (Extract->getValueType(0) != MVT::i32)
13065 if (!Extract->hasOneUse())
13067 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13068 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13070 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13073 // Record which element was extracted.
13074 ExtractedElements |=
13075 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13077 Uses.push_back(Extract);
13080 // If not all the elements were used, this may not be worthwhile.
13081 if (ExtractedElements != 15)
13084 // Ok, we've now decided to do the transformation.
13085 DebugLoc dl = InputVector.getDebugLoc();
13087 // Store the value to a temporary stack slot.
13088 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13089 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13090 MachinePointerInfo(), false, false, 0);
13092 // Replace each use (extract) with a load of the appropriate element.
13093 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13094 UE = Uses.end(); UI != UE; ++UI) {
13095 SDNode *Extract = *UI;
13097 // cOMpute the element's address.
13098 SDValue Idx = Extract->getOperand(1);
13100 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13101 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13102 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13103 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13105 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13106 StackPtr, OffsetVal);
13108 // Load the scalar.
13109 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13110 ScalarAddr, MachinePointerInfo(),
13111 false, false, false, 0);
13113 // Replace the exact with the load.
13114 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13117 // The replacement was made in place; don't return anything.
13121 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13123 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13124 TargetLowering::DAGCombinerInfo &DCI,
13125 const X86Subtarget *Subtarget) {
13128 DebugLoc DL = N->getDebugLoc();
13129 SDValue Cond = N->getOperand(0);
13130 // Get the LHS/RHS of the select.
13131 SDValue LHS = N->getOperand(1);
13132 SDValue RHS = N->getOperand(2);
13133 EVT VT = LHS.getValueType();
13135 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13136 // instructions match the semantics of the common C idiom x<y?x:y but not
13137 // x<=y?x:y, because of how they handle negative zero (which can be
13138 // ignored in unsafe-math mode).
13139 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13140 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13141 (Subtarget->hasSSE2() ||
13142 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13143 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13145 unsigned Opcode = 0;
13146 // Check for x CC y ? x : y.
13147 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13148 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13152 // Converting this to a min would handle NaNs incorrectly, and swapping
13153 // the operands would cause it to handle comparisons between positive
13154 // and negative zero incorrectly.
13155 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13156 if (!DAG.getTarget().Options.UnsafeFPMath &&
13157 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13159 std::swap(LHS, RHS);
13161 Opcode = X86ISD::FMIN;
13164 // Converting this to a min would handle comparisons between positive
13165 // and negative zero incorrectly.
13166 if (!DAG.getTarget().Options.UnsafeFPMath &&
13167 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13169 Opcode = X86ISD::FMIN;
13172 // Converting this to a min would handle both negative zeros and NaNs
13173 // incorrectly, but we can swap the operands to fix both.
13174 std::swap(LHS, RHS);
13178 Opcode = X86ISD::FMIN;
13182 // Converting this to a max would handle comparisons between positive
13183 // and negative zero incorrectly.
13184 if (!DAG.getTarget().Options.UnsafeFPMath &&
13185 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13187 Opcode = X86ISD::FMAX;
13190 // Converting this to a max would handle NaNs incorrectly, and swapping
13191 // the operands would cause it to handle comparisons between positive
13192 // and negative zero incorrectly.
13193 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13194 if (!DAG.getTarget().Options.UnsafeFPMath &&
13195 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13197 std::swap(LHS, RHS);
13199 Opcode = X86ISD::FMAX;
13202 // Converting this to a max would handle both negative zeros and NaNs
13203 // incorrectly, but we can swap the operands to fix both.
13204 std::swap(LHS, RHS);
13208 Opcode = X86ISD::FMAX;
13211 // Check for x CC y ? y : x -- a min/max with reversed arms.
13212 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13213 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13217 // Converting this to a min would handle comparisons between positive
13218 // and negative zero incorrectly, and swapping the operands would
13219 // cause it to handle NaNs incorrectly.
13220 if (!DAG.getTarget().Options.UnsafeFPMath &&
13221 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13222 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13224 std::swap(LHS, RHS);
13226 Opcode = X86ISD::FMIN;
13229 // Converting this to a min would handle NaNs incorrectly.
13230 if (!DAG.getTarget().Options.UnsafeFPMath &&
13231 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13233 Opcode = X86ISD::FMIN;
13236 // Converting this to a min would handle both negative zeros and NaNs
13237 // incorrectly, but we can swap the operands to fix both.
13238 std::swap(LHS, RHS);
13242 Opcode = X86ISD::FMIN;
13246 // Converting this to a max would handle NaNs incorrectly.
13247 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13249 Opcode = X86ISD::FMAX;
13252 // Converting this to a max would handle comparisons between positive
13253 // and negative zero incorrectly, and swapping the operands would
13254 // cause it to handle NaNs incorrectly.
13255 if (!DAG.getTarget().Options.UnsafeFPMath &&
13256 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13257 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13259 std::swap(LHS, RHS);
13261 Opcode = X86ISD::FMAX;
13264 // Converting this to a max would handle both negative zeros and NaNs
13265 // incorrectly, but we can swap the operands to fix both.
13266 std::swap(LHS, RHS);
13270 Opcode = X86ISD::FMAX;
13276 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13279 // If this is a select between two integer constants, try to do some
13281 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13282 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13283 // Don't do this for crazy integer types.
13284 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13285 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13286 // so that TrueC (the true value) is larger than FalseC.
13287 bool NeedsCondInvert = false;
13289 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13290 // Efficiently invertible.
13291 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13292 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13293 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13294 NeedsCondInvert = true;
13295 std::swap(TrueC, FalseC);
13298 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13299 if (FalseC->getAPIntValue() == 0 &&
13300 TrueC->getAPIntValue().isPowerOf2()) {
13301 if (NeedsCondInvert) // Invert the condition if needed.
13302 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13303 DAG.getConstant(1, Cond.getValueType()));
13305 // Zero extend the condition if needed.
13306 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13308 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13309 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13310 DAG.getConstant(ShAmt, MVT::i8));
13313 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13314 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13315 if (NeedsCondInvert) // Invert the condition if needed.
13316 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13317 DAG.getConstant(1, Cond.getValueType()));
13319 // Zero extend the condition if needed.
13320 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13321 FalseC->getValueType(0), Cond);
13322 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13323 SDValue(FalseC, 0));
13326 // Optimize cases that will turn into an LEA instruction. This requires
13327 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13328 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13329 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13330 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13332 bool isFastMultiplier = false;
13334 switch ((unsigned char)Diff) {
13336 case 1: // result = add base, cond
13337 case 2: // result = lea base( , cond*2)
13338 case 3: // result = lea base(cond, cond*2)
13339 case 4: // result = lea base( , cond*4)
13340 case 5: // result = lea base(cond, cond*4)
13341 case 8: // result = lea base( , cond*8)
13342 case 9: // result = lea base(cond, cond*8)
13343 isFastMultiplier = true;
13348 if (isFastMultiplier) {
13349 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13350 if (NeedsCondInvert) // Invert the condition if needed.
13351 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13352 DAG.getConstant(1, Cond.getValueType()));
13354 // Zero extend the condition if needed.
13355 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13357 // Scale the condition by the difference.
13359 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13360 DAG.getConstant(Diff, Cond.getValueType()));
13362 // Add the base if non-zero.
13363 if (FalseC->getAPIntValue() != 0)
13364 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13365 SDValue(FalseC, 0));
13372 // Canonicalize max and min:
13373 // (x > y) ? x : y -> (x >= y) ? x : y
13374 // (x < y) ? x : y -> (x <= y) ? x : y
13375 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13376 // the need for an extra compare
13377 // against zero. e.g.
13378 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13380 // testl %edi, %edi
13382 // cmovgl %edi, %eax
13386 // cmovsl %eax, %edi
13387 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13388 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13389 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13390 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13395 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13396 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13397 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13398 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13403 // If we know that this node is legal then we know that it is going to be
13404 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13405 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13406 // to simplify previous instructions.
13407 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13408 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13409 !DCI.isBeforeLegalize() &&
13410 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13411 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13412 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13413 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13415 APInt KnownZero, KnownOne;
13416 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13417 DCI.isBeforeLegalizeOps());
13418 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13419 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13420 DCI.CommitTargetLoweringOpt(TLO);
13426 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13427 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13428 TargetLowering::DAGCombinerInfo &DCI) {
13429 DebugLoc DL = N->getDebugLoc();
13431 // If the flag operand isn't dead, don't touch this CMOV.
13432 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13435 SDValue FalseOp = N->getOperand(0);
13436 SDValue TrueOp = N->getOperand(1);
13437 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13438 SDValue Cond = N->getOperand(3);
13439 if (CC == X86::COND_E || CC == X86::COND_NE) {
13440 switch (Cond.getOpcode()) {
13444 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13445 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13446 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13450 // If this is a select between two integer constants, try to do some
13451 // optimizations. Note that the operands are ordered the opposite of SELECT
13453 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13454 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13455 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13456 // larger than FalseC (the false value).
13457 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13458 CC = X86::GetOppositeBranchCondition(CC);
13459 std::swap(TrueC, FalseC);
13462 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13463 // This is efficient for any integer data type (including i8/i16) and
13465 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13466 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13467 DAG.getConstant(CC, MVT::i8), Cond);
13469 // Zero extend the condition if needed.
13470 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13472 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13473 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13474 DAG.getConstant(ShAmt, MVT::i8));
13475 if (N->getNumValues() == 2) // Dead flag value?
13476 return DCI.CombineTo(N, Cond, SDValue());
13480 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13481 // for any integer data type, including i8/i16.
13482 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13483 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13484 DAG.getConstant(CC, MVT::i8), Cond);
13486 // Zero extend the condition if needed.
13487 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13488 FalseC->getValueType(0), Cond);
13489 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13490 SDValue(FalseC, 0));
13492 if (N->getNumValues() == 2) // Dead flag value?
13493 return DCI.CombineTo(N, Cond, SDValue());
13497 // Optimize cases that will turn into an LEA instruction. This requires
13498 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13499 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13500 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13501 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13503 bool isFastMultiplier = false;
13505 switch ((unsigned char)Diff) {
13507 case 1: // result = add base, cond
13508 case 2: // result = lea base( , cond*2)
13509 case 3: // result = lea base(cond, cond*2)
13510 case 4: // result = lea base( , cond*4)
13511 case 5: // result = lea base(cond, cond*4)
13512 case 8: // result = lea base( , cond*8)
13513 case 9: // result = lea base(cond, cond*8)
13514 isFastMultiplier = true;
13519 if (isFastMultiplier) {
13520 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13521 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13522 DAG.getConstant(CC, MVT::i8), Cond);
13523 // Zero extend the condition if needed.
13524 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13526 // Scale the condition by the difference.
13528 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13529 DAG.getConstant(Diff, Cond.getValueType()));
13531 // Add the base if non-zero.
13532 if (FalseC->getAPIntValue() != 0)
13533 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13534 SDValue(FalseC, 0));
13535 if (N->getNumValues() == 2) // Dead flag value?
13536 return DCI.CombineTo(N, Cond, SDValue());
13546 /// PerformMulCombine - Optimize a single multiply with constant into two
13547 /// in order to implement it with two cheaper instructions, e.g.
13548 /// LEA + SHL, LEA + LEA.
13549 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13550 TargetLowering::DAGCombinerInfo &DCI) {
13551 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13554 EVT VT = N->getValueType(0);
13555 if (VT != MVT::i64)
13558 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13561 uint64_t MulAmt = C->getZExtValue();
13562 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13565 uint64_t MulAmt1 = 0;
13566 uint64_t MulAmt2 = 0;
13567 if ((MulAmt % 9) == 0) {
13569 MulAmt2 = MulAmt / 9;
13570 } else if ((MulAmt % 5) == 0) {
13572 MulAmt2 = MulAmt / 5;
13573 } else if ((MulAmt % 3) == 0) {
13575 MulAmt2 = MulAmt / 3;
13578 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13579 DebugLoc DL = N->getDebugLoc();
13581 if (isPowerOf2_64(MulAmt2) &&
13582 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13583 // If second multiplifer is pow2, issue it first. We want the multiply by
13584 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13586 std::swap(MulAmt1, MulAmt2);
13589 if (isPowerOf2_64(MulAmt1))
13590 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13591 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13593 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13594 DAG.getConstant(MulAmt1, VT));
13596 if (isPowerOf2_64(MulAmt2))
13597 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13598 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13600 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13601 DAG.getConstant(MulAmt2, VT));
13603 // Do not add new nodes to DAG combiner worklist.
13604 DCI.CombineTo(N, NewMul, false);
13609 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13610 SDValue N0 = N->getOperand(0);
13611 SDValue N1 = N->getOperand(1);
13612 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13613 EVT VT = N0.getValueType();
13615 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13616 // since the result of setcc_c is all zero's or all ones.
13617 if (VT.isInteger() && !VT.isVector() &&
13618 N1C && N0.getOpcode() == ISD::AND &&
13619 N0.getOperand(1).getOpcode() == ISD::Constant) {
13620 SDValue N00 = N0.getOperand(0);
13621 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13622 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13623 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13624 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13625 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13626 APInt ShAmt = N1C->getAPIntValue();
13627 Mask = Mask.shl(ShAmt);
13629 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13630 N00, DAG.getConstant(Mask, VT));
13635 // Hardware support for vector shifts is sparse which makes us scalarize the
13636 // vector operations in many cases. Also, on sandybridge ADD is faster than
13638 // (shl V, 1) -> add V,V
13639 if (isSplatVector(N1.getNode())) {
13640 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13641 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13642 // We shift all of the values by one. In many cases we do not have
13643 // hardware support for this operation. This is better expressed as an ADD
13645 if (N1C && (1 == N1C->getZExtValue())) {
13646 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13653 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13655 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13656 TargetLowering::DAGCombinerInfo &DCI,
13657 const X86Subtarget *Subtarget) {
13658 EVT VT = N->getValueType(0);
13659 if (N->getOpcode() == ISD::SHL) {
13660 SDValue V = PerformSHLCombine(N, DAG);
13661 if (V.getNode()) return V;
13664 // On X86 with SSE2 support, we can transform this to a vector shift if
13665 // all elements are shifted by the same amount. We can't do this in legalize
13666 // because the a constant vector is typically transformed to a constant pool
13667 // so we have no knowledge of the shift amount.
13668 if (!Subtarget->hasSSE2())
13671 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13672 (!Subtarget->hasAVX2() ||
13673 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13676 SDValue ShAmtOp = N->getOperand(1);
13677 EVT EltVT = VT.getVectorElementType();
13678 DebugLoc DL = N->getDebugLoc();
13679 SDValue BaseShAmt = SDValue();
13680 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13681 unsigned NumElts = VT.getVectorNumElements();
13683 for (; i != NumElts; ++i) {
13684 SDValue Arg = ShAmtOp.getOperand(i);
13685 if (Arg.getOpcode() == ISD::UNDEF) continue;
13689 // Handle the case where the build_vector is all undef
13690 // FIXME: Should DAG allow this?
13694 for (; i != NumElts; ++i) {
13695 SDValue Arg = ShAmtOp.getOperand(i);
13696 if (Arg.getOpcode() == ISD::UNDEF) continue;
13697 if (Arg != BaseShAmt) {
13701 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13702 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13703 SDValue InVec = ShAmtOp.getOperand(0);
13704 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13705 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13707 for (; i != NumElts; ++i) {
13708 SDValue Arg = InVec.getOperand(i);
13709 if (Arg.getOpcode() == ISD::UNDEF) continue;
13713 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13715 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13716 if (C->getZExtValue() == SplatIdx)
13717 BaseShAmt = InVec.getOperand(1);
13720 if (BaseShAmt.getNode() == 0) {
13721 // Don't create instructions with illegal types after legalize
13723 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13724 !DCI.isBeforeLegalize())
13727 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13728 DAG.getIntPtrConstant(0));
13733 // The shift amount is an i32.
13734 if (EltVT.bitsGT(MVT::i32))
13735 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13736 else if (EltVT.bitsLT(MVT::i32))
13737 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13739 // The shift amount is identical so we can do a vector shift.
13740 SDValue ValOp = N->getOperand(0);
13741 switch (N->getOpcode()) {
13743 llvm_unreachable("Unknown shift opcode!");
13745 switch (VT.getSimpleVT().SimpleTy) {
13746 default: return SDValue();
13753 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13756 switch (VT.getSimpleVT().SimpleTy) {
13757 default: return SDValue();
13762 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13765 switch (VT.getSimpleVT().SimpleTy) {
13766 default: return SDValue();
13773 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13779 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13780 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13781 // and friends. Likewise for OR -> CMPNEQSS.
13782 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13783 TargetLowering::DAGCombinerInfo &DCI,
13784 const X86Subtarget *Subtarget) {
13787 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13788 // we're requiring SSE2 for both.
13789 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13790 SDValue N0 = N->getOperand(0);
13791 SDValue N1 = N->getOperand(1);
13792 SDValue CMP0 = N0->getOperand(1);
13793 SDValue CMP1 = N1->getOperand(1);
13794 DebugLoc DL = N->getDebugLoc();
13796 // The SETCCs should both refer to the same CMP.
13797 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13800 SDValue CMP00 = CMP0->getOperand(0);
13801 SDValue CMP01 = CMP0->getOperand(1);
13802 EVT VT = CMP00.getValueType();
13804 if (VT == MVT::f32 || VT == MVT::f64) {
13805 bool ExpectingFlags = false;
13806 // Check for any users that want flags:
13807 for (SDNode::use_iterator UI = N->use_begin(),
13809 !ExpectingFlags && UI != UE; ++UI)
13810 switch (UI->getOpcode()) {
13815 ExpectingFlags = true;
13817 case ISD::CopyToReg:
13818 case ISD::SIGN_EXTEND:
13819 case ISD::ZERO_EXTEND:
13820 case ISD::ANY_EXTEND:
13824 if (!ExpectingFlags) {
13825 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13826 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13828 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13829 X86::CondCode tmp = cc0;
13834 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13835 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13836 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13837 X86ISD::NodeType NTOperator = is64BitFP ?
13838 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13839 // FIXME: need symbolic constants for these magic numbers.
13840 // See X86ATTInstPrinter.cpp:printSSECC().
13841 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13842 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13843 DAG.getConstant(x86cc, MVT::i8));
13844 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13846 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13847 DAG.getConstant(1, MVT::i32));
13848 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13849 return OneBitOfTruth;
13857 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13858 /// so it can be folded inside ANDNP.
13859 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13860 EVT VT = N->getValueType(0);
13862 // Match direct AllOnes for 128 and 256-bit vectors
13863 if (ISD::isBuildVectorAllOnes(N))
13866 // Look through a bit convert.
13867 if (N->getOpcode() == ISD::BITCAST)
13868 N = N->getOperand(0).getNode();
13870 // Sometimes the operand may come from a insert_subvector building a 256-bit
13872 if (VT.getSizeInBits() == 256 &&
13873 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13874 SDValue V1 = N->getOperand(0);
13875 SDValue V2 = N->getOperand(1);
13877 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13878 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13879 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13880 ISD::isBuildVectorAllOnes(V2.getNode()))
13887 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13888 TargetLowering::DAGCombinerInfo &DCI,
13889 const X86Subtarget *Subtarget) {
13890 if (DCI.isBeforeLegalizeOps())
13893 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13897 EVT VT = N->getValueType(0);
13899 // Create ANDN, BLSI, and BLSR instructions
13900 // BLSI is X & (-X)
13901 // BLSR is X & (X-1)
13902 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13903 SDValue N0 = N->getOperand(0);
13904 SDValue N1 = N->getOperand(1);
13905 DebugLoc DL = N->getDebugLoc();
13907 // Check LHS for not
13908 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13909 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13910 // Check RHS for not
13911 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13912 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13914 // Check LHS for neg
13915 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13916 isZero(N0.getOperand(0)))
13917 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13919 // Check RHS for neg
13920 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13921 isZero(N1.getOperand(0)))
13922 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13924 // Check LHS for X-1
13925 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13926 isAllOnes(N0.getOperand(1)))
13927 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13929 // Check RHS for X-1
13930 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13931 isAllOnes(N1.getOperand(1)))
13932 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13937 // Want to form ANDNP nodes:
13938 // 1) In the hopes of then easily combining them with OR and AND nodes
13939 // to form PBLEND/PSIGN.
13940 // 2) To match ANDN packed intrinsics
13941 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13944 SDValue N0 = N->getOperand(0);
13945 SDValue N1 = N->getOperand(1);
13946 DebugLoc DL = N->getDebugLoc();
13948 // Check LHS for vnot
13949 if (N0.getOpcode() == ISD::XOR &&
13950 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13951 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13952 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13954 // Check RHS for vnot
13955 if (N1.getOpcode() == ISD::XOR &&
13956 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13957 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13958 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13963 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13964 TargetLowering::DAGCombinerInfo &DCI,
13965 const X86Subtarget *Subtarget) {
13966 if (DCI.isBeforeLegalizeOps())
13969 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13973 EVT VT = N->getValueType(0);
13975 SDValue N0 = N->getOperand(0);
13976 SDValue N1 = N->getOperand(1);
13978 // look for psign/blend
13979 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13980 if (!Subtarget->hasSSSE3() ||
13981 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13984 // Canonicalize pandn to RHS
13985 if (N0.getOpcode() == X86ISD::ANDNP)
13987 // or (and (m, y), (pandn m, x))
13988 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13989 SDValue Mask = N1.getOperand(0);
13990 SDValue X = N1.getOperand(1);
13992 if (N0.getOperand(0) == Mask)
13993 Y = N0.getOperand(1);
13994 if (N0.getOperand(1) == Mask)
13995 Y = N0.getOperand(0);
13997 // Check to see if the mask appeared in both the AND and ANDNP and
14001 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14002 if (Mask.getOpcode() != ISD::BITCAST ||
14003 X.getOpcode() != ISD::BITCAST ||
14004 Y.getOpcode() != ISD::BITCAST)
14007 // Look through mask bitcast.
14008 Mask = Mask.getOperand(0);
14009 EVT MaskVT = Mask.getValueType();
14011 // Validate that the Mask operand is a vector sra node.
14012 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14013 // there is no psrai.b
14014 if (Mask.getOpcode() != X86ISD::VSRAI)
14017 // Check that the SRA is all signbits.
14018 SDValue SraC = Mask.getOperand(1);
14019 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14020 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14021 if ((SraAmt + 1) != EltBits)
14024 DebugLoc DL = N->getDebugLoc();
14026 // Now we know we at least have a plendvb with the mask val. See if
14027 // we can form a psignb/w/d.
14028 // psign = x.type == y.type == mask.type && y = sub(0, x);
14029 X = X.getOperand(0);
14030 Y = Y.getOperand(0);
14031 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14032 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14033 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14034 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14035 "Unsupported VT for PSIGN");
14036 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14037 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14039 // PBLENDVB only available on SSE 4.1
14040 if (!Subtarget->hasSSE41())
14043 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14045 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14046 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14047 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14048 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14049 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14053 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14056 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14057 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14059 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14061 if (!N0.hasOneUse() || !N1.hasOneUse())
14064 SDValue ShAmt0 = N0.getOperand(1);
14065 if (ShAmt0.getValueType() != MVT::i8)
14067 SDValue ShAmt1 = N1.getOperand(1);
14068 if (ShAmt1.getValueType() != MVT::i8)
14070 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14071 ShAmt0 = ShAmt0.getOperand(0);
14072 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14073 ShAmt1 = ShAmt1.getOperand(0);
14075 DebugLoc DL = N->getDebugLoc();
14076 unsigned Opc = X86ISD::SHLD;
14077 SDValue Op0 = N0.getOperand(0);
14078 SDValue Op1 = N1.getOperand(0);
14079 if (ShAmt0.getOpcode() == ISD::SUB) {
14080 Opc = X86ISD::SHRD;
14081 std::swap(Op0, Op1);
14082 std::swap(ShAmt0, ShAmt1);
14085 unsigned Bits = VT.getSizeInBits();
14086 if (ShAmt1.getOpcode() == ISD::SUB) {
14087 SDValue Sum = ShAmt1.getOperand(0);
14088 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14089 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14090 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14091 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14092 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14093 return DAG.getNode(Opc, DL, VT,
14095 DAG.getNode(ISD::TRUNCATE, DL,
14098 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14099 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14101 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14102 return DAG.getNode(Opc, DL, VT,
14103 N0.getOperand(0), N1.getOperand(0),
14104 DAG.getNode(ISD::TRUNCATE, DL,
14111 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14112 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14113 TargetLowering::DAGCombinerInfo &DCI,
14114 const X86Subtarget *Subtarget) {
14115 if (DCI.isBeforeLegalizeOps())
14118 EVT VT = N->getValueType(0);
14120 if (VT != MVT::i32 && VT != MVT::i64)
14123 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14125 // Create BLSMSK instructions by finding X ^ (X-1)
14126 SDValue N0 = N->getOperand(0);
14127 SDValue N1 = N->getOperand(1);
14128 DebugLoc DL = N->getDebugLoc();
14130 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14131 isAllOnes(N0.getOperand(1)))
14132 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14134 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14135 isAllOnes(N1.getOperand(1)))
14136 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14141 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14142 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14143 const X86Subtarget *Subtarget) {
14144 LoadSDNode *Ld = cast<LoadSDNode>(N);
14145 EVT RegVT = Ld->getValueType(0);
14146 EVT MemVT = Ld->getMemoryVT();
14147 DebugLoc dl = Ld->getDebugLoc();
14148 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14150 ISD::LoadExtType Ext = Ld->getExtensionType();
14152 // If this is a vector EXT Load then attempt to optimize it using a
14153 // shuffle. We need SSE4 for the shuffles.
14154 // TODO: It is possible to support ZExt by zeroing the undef values
14155 // during the shuffle phase or after the shuffle.
14156 if (RegVT.isVector() && RegVT.isInteger() &&
14157 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14158 assert(MemVT != RegVT && "Cannot extend to the same type");
14159 assert(MemVT.isVector() && "Must load a vector from memory");
14161 unsigned NumElems = RegVT.getVectorNumElements();
14162 unsigned RegSz = RegVT.getSizeInBits();
14163 unsigned MemSz = MemVT.getSizeInBits();
14164 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14165 // All sizes must be a power of two
14166 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14168 // Attempt to load the original value using a single load op.
14169 // Find a scalar type which is equal to the loaded word size.
14170 MVT SclrLoadTy = MVT::i8;
14171 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14172 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14173 MVT Tp = (MVT::SimpleValueType)tp;
14174 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14180 // Proceed if a load word is found.
14181 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14183 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14184 RegSz/SclrLoadTy.getSizeInBits());
14186 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14187 RegSz/MemVT.getScalarType().getSizeInBits());
14188 // Can't shuffle using an illegal type.
14189 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14191 // Perform a single load.
14192 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14194 Ld->getPointerInfo(), Ld->isVolatile(),
14195 Ld->isNonTemporal(), Ld->isInvariant(),
14196 Ld->getAlignment());
14198 // Insert the word loaded into a vector.
14199 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14200 LoadUnitVecVT, ScalarLoad);
14202 // Bitcast the loaded value to a vector of the original element type, in
14203 // the size of the target vector type.
14204 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14206 unsigned SizeRatio = RegSz/MemSz;
14208 // Redistribute the loaded elements into the different locations.
14209 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14210 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14212 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14213 DAG.getUNDEF(SlicedVec.getValueType()),
14214 ShuffleVec.data());
14216 // Bitcast to the requested type.
14217 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14218 // Replace the original load with the new sequence
14219 // and return the new chain.
14220 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14221 return SDValue(ScalarLoad.getNode(), 1);
14227 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14228 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14229 const X86Subtarget *Subtarget) {
14230 StoreSDNode *St = cast<StoreSDNode>(N);
14231 EVT VT = St->getValue().getValueType();
14232 EVT StVT = St->getMemoryVT();
14233 DebugLoc dl = St->getDebugLoc();
14234 SDValue StoredVal = St->getOperand(1);
14235 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14237 // If we are saving a concatenation of two XMM registers, perform two stores.
14238 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14239 // 128-bit ones. If in the future the cost becomes only one memory access the
14240 // first version would be better.
14241 if (VT.getSizeInBits() == 256 &&
14242 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14243 StoredVal.getNumOperands() == 2) {
14245 SDValue Value0 = StoredVal.getOperand(0);
14246 SDValue Value1 = StoredVal.getOperand(1);
14248 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14249 SDValue Ptr0 = St->getBasePtr();
14250 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14252 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14253 St->getPointerInfo(), St->isVolatile(),
14254 St->isNonTemporal(), St->getAlignment());
14255 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14256 St->getPointerInfo(), St->isVolatile(),
14257 St->isNonTemporal(), St->getAlignment());
14258 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14261 // Optimize trunc store (of multiple scalars) to shuffle and store.
14262 // First, pack all of the elements in one place. Next, store to memory
14263 // in fewer chunks.
14264 if (St->isTruncatingStore() && VT.isVector()) {
14265 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14266 unsigned NumElems = VT.getVectorNumElements();
14267 assert(StVT != VT && "Cannot truncate to the same type");
14268 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14269 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14271 // From, To sizes and ElemCount must be pow of two
14272 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14273 // We are going to use the original vector elt for storing.
14274 // Accumulated smaller vector elements must be a multiple of the store size.
14275 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14277 unsigned SizeRatio = FromSz / ToSz;
14279 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14281 // Create a type on which we perform the shuffle
14282 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14283 StVT.getScalarType(), NumElems*SizeRatio);
14285 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14287 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14288 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14289 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14291 // Can't shuffle using an illegal type
14292 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14294 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14295 DAG.getUNDEF(WideVec.getValueType()),
14296 ShuffleVec.data());
14297 // At this point all of the data is stored at the bottom of the
14298 // register. We now need to save it to mem.
14300 // Find the largest store unit
14301 MVT StoreType = MVT::i8;
14302 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14303 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14304 MVT Tp = (MVT::SimpleValueType)tp;
14305 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14309 // Bitcast the original vector into a vector of store-size units
14310 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14311 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14312 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14313 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14314 SmallVector<SDValue, 8> Chains;
14315 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14316 TLI.getPointerTy());
14317 SDValue Ptr = St->getBasePtr();
14319 // Perform one or more big stores into memory.
14320 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14321 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14322 StoreType, ShuffWide,
14323 DAG.getIntPtrConstant(i));
14324 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14325 St->getPointerInfo(), St->isVolatile(),
14326 St->isNonTemporal(), St->getAlignment());
14327 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14328 Chains.push_back(Ch);
14331 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14336 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14337 // the FP state in cases where an emms may be missing.
14338 // A preferable solution to the general problem is to figure out the right
14339 // places to insert EMMS. This qualifies as a quick hack.
14341 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14342 if (VT.getSizeInBits() != 64)
14345 const Function *F = DAG.getMachineFunction().getFunction();
14346 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14347 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14348 && Subtarget->hasSSE2();
14349 if ((VT.isVector() ||
14350 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14351 isa<LoadSDNode>(St->getValue()) &&
14352 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14353 St->getChain().hasOneUse() && !St->isVolatile()) {
14354 SDNode* LdVal = St->getValue().getNode();
14355 LoadSDNode *Ld = 0;
14356 int TokenFactorIndex = -1;
14357 SmallVector<SDValue, 8> Ops;
14358 SDNode* ChainVal = St->getChain().getNode();
14359 // Must be a store of a load. We currently handle two cases: the load
14360 // is a direct child, and it's under an intervening TokenFactor. It is
14361 // possible to dig deeper under nested TokenFactors.
14362 if (ChainVal == LdVal)
14363 Ld = cast<LoadSDNode>(St->getChain());
14364 else if (St->getValue().hasOneUse() &&
14365 ChainVal->getOpcode() == ISD::TokenFactor) {
14366 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14367 if (ChainVal->getOperand(i).getNode() == LdVal) {
14368 TokenFactorIndex = i;
14369 Ld = cast<LoadSDNode>(St->getValue());
14371 Ops.push_back(ChainVal->getOperand(i));
14375 if (!Ld || !ISD::isNormalLoad(Ld))
14378 // If this is not the MMX case, i.e. we are just turning i64 load/store
14379 // into f64 load/store, avoid the transformation if there are multiple
14380 // uses of the loaded value.
14381 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14384 DebugLoc LdDL = Ld->getDebugLoc();
14385 DebugLoc StDL = N->getDebugLoc();
14386 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14387 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14389 if (Subtarget->is64Bit() || F64IsLegal) {
14390 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14391 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14392 Ld->getPointerInfo(), Ld->isVolatile(),
14393 Ld->isNonTemporal(), Ld->isInvariant(),
14394 Ld->getAlignment());
14395 SDValue NewChain = NewLd.getValue(1);
14396 if (TokenFactorIndex != -1) {
14397 Ops.push_back(NewChain);
14398 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14401 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14402 St->getPointerInfo(),
14403 St->isVolatile(), St->isNonTemporal(),
14404 St->getAlignment());
14407 // Otherwise, lower to two pairs of 32-bit loads / stores.
14408 SDValue LoAddr = Ld->getBasePtr();
14409 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14410 DAG.getConstant(4, MVT::i32));
14412 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14413 Ld->getPointerInfo(),
14414 Ld->isVolatile(), Ld->isNonTemporal(),
14415 Ld->isInvariant(), Ld->getAlignment());
14416 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14417 Ld->getPointerInfo().getWithOffset(4),
14418 Ld->isVolatile(), Ld->isNonTemporal(),
14420 MinAlign(Ld->getAlignment(), 4));
14422 SDValue NewChain = LoLd.getValue(1);
14423 if (TokenFactorIndex != -1) {
14424 Ops.push_back(LoLd);
14425 Ops.push_back(HiLd);
14426 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14430 LoAddr = St->getBasePtr();
14431 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14432 DAG.getConstant(4, MVT::i32));
14434 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14435 St->getPointerInfo(),
14436 St->isVolatile(), St->isNonTemporal(),
14437 St->getAlignment());
14438 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14439 St->getPointerInfo().getWithOffset(4),
14441 St->isNonTemporal(),
14442 MinAlign(St->getAlignment(), 4));
14443 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14448 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14449 /// and return the operands for the horizontal operation in LHS and RHS. A
14450 /// horizontal operation performs the binary operation on successive elements
14451 /// of its first operand, then on successive elements of its second operand,
14452 /// returning the resulting values in a vector. For example, if
14453 /// A = < float a0, float a1, float a2, float a3 >
14455 /// B = < float b0, float b1, float b2, float b3 >
14456 /// then the result of doing a horizontal operation on A and B is
14457 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14458 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14459 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14460 /// set to A, RHS to B, and the routine returns 'true'.
14461 /// Note that the binary operation should have the property that if one of the
14462 /// operands is UNDEF then the result is UNDEF.
14463 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14464 // Look for the following pattern: if
14465 // A = < float a0, float a1, float a2, float a3 >
14466 // B = < float b0, float b1, float b2, float b3 >
14468 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14469 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14470 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14471 // which is A horizontal-op B.
14473 // At least one of the operands should be a vector shuffle.
14474 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14475 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14478 EVT VT = LHS.getValueType();
14480 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14481 "Unsupported vector type for horizontal add/sub");
14483 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14484 // operate independently on 128-bit lanes.
14485 unsigned NumElts = VT.getVectorNumElements();
14486 unsigned NumLanes = VT.getSizeInBits()/128;
14487 unsigned NumLaneElts = NumElts / NumLanes;
14488 assert((NumLaneElts % 2 == 0) &&
14489 "Vector type should have an even number of elements in each lane");
14490 unsigned HalfLaneElts = NumLaneElts/2;
14492 // View LHS in the form
14493 // LHS = VECTOR_SHUFFLE A, B, LMask
14494 // If LHS is not a shuffle then pretend it is the shuffle
14495 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14496 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14499 SmallVector<int, 16> LMask(NumElts);
14500 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14501 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14502 A = LHS.getOperand(0);
14503 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14504 B = LHS.getOperand(1);
14505 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14506 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14508 if (LHS.getOpcode() != ISD::UNDEF)
14510 for (unsigned i = 0; i != NumElts; ++i)
14514 // Likewise, view RHS in the form
14515 // RHS = VECTOR_SHUFFLE C, D, RMask
14517 SmallVector<int, 16> RMask(NumElts);
14518 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14519 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14520 C = RHS.getOperand(0);
14521 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14522 D = RHS.getOperand(1);
14523 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14524 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14526 if (RHS.getOpcode() != ISD::UNDEF)
14528 for (unsigned i = 0; i != NumElts; ++i)
14532 // Check that the shuffles are both shuffling the same vectors.
14533 if (!(A == C && B == D) && !(A == D && B == C))
14536 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14537 if (!A.getNode() && !B.getNode())
14540 // If A and B occur in reverse order in RHS, then "swap" them (which means
14541 // rewriting the mask).
14543 CommuteVectorShuffleMask(RMask, NumElts);
14545 // At this point LHS and RHS are equivalent to
14546 // LHS = VECTOR_SHUFFLE A, B, LMask
14547 // RHS = VECTOR_SHUFFLE A, B, RMask
14548 // Check that the masks correspond to performing a horizontal operation.
14549 for (unsigned i = 0; i != NumElts; ++i) {
14550 int LIdx = LMask[i], RIdx = RMask[i];
14552 // Ignore any UNDEF components.
14553 if (LIdx < 0 || RIdx < 0 ||
14554 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14555 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14558 // Check that successive elements are being operated on. If not, this is
14559 // not a horizontal operation.
14560 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14561 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14562 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14563 if (!(LIdx == Index && RIdx == Index + 1) &&
14564 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14568 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14569 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14573 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14574 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14575 const X86Subtarget *Subtarget) {
14576 EVT VT = N->getValueType(0);
14577 SDValue LHS = N->getOperand(0);
14578 SDValue RHS = N->getOperand(1);
14580 // Try to synthesize horizontal adds from adds of shuffles.
14581 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14582 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14583 isHorizontalBinOp(LHS, RHS, true))
14584 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14588 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14589 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14590 const X86Subtarget *Subtarget) {
14591 EVT VT = N->getValueType(0);
14592 SDValue LHS = N->getOperand(0);
14593 SDValue RHS = N->getOperand(1);
14595 // Try to synthesize horizontal subs from subs of shuffles.
14596 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14597 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14598 isHorizontalBinOp(LHS, RHS, false))
14599 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14603 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14604 /// X86ISD::FXOR nodes.
14605 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14606 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14607 // F[X]OR(0.0, x) -> x
14608 // F[X]OR(x, 0.0) -> x
14609 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14610 if (C->getValueAPF().isPosZero())
14611 return N->getOperand(1);
14612 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14613 if (C->getValueAPF().isPosZero())
14614 return N->getOperand(0);
14618 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14619 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14620 // FAND(0.0, x) -> 0.0
14621 // FAND(x, 0.0) -> 0.0
14622 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14623 if (C->getValueAPF().isPosZero())
14624 return N->getOperand(0);
14625 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14626 if (C->getValueAPF().isPosZero())
14627 return N->getOperand(1);
14631 static SDValue PerformBTCombine(SDNode *N,
14633 TargetLowering::DAGCombinerInfo &DCI) {
14634 // BT ignores high bits in the bit index operand.
14635 SDValue Op1 = N->getOperand(1);
14636 if (Op1.hasOneUse()) {
14637 unsigned BitWidth = Op1.getValueSizeInBits();
14638 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14639 APInt KnownZero, KnownOne;
14640 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14641 !DCI.isBeforeLegalizeOps());
14642 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14643 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14644 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14645 DCI.CommitTargetLoweringOpt(TLO);
14650 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14651 SDValue Op = N->getOperand(0);
14652 if (Op.getOpcode() == ISD::BITCAST)
14653 Op = Op.getOperand(0);
14654 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14655 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14656 VT.getVectorElementType().getSizeInBits() ==
14657 OpVT.getVectorElementType().getSizeInBits()) {
14658 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14663 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14664 TargetLowering::DAGCombinerInfo &DCI,
14665 const X86Subtarget *Subtarget) {
14666 if (!DCI.isBeforeLegalizeOps())
14669 if (!Subtarget->hasAVX())
14672 // Optimize vectors in AVX mode
14673 // Sign extend v8i16 to v8i32 and
14676 // Divide input vector into two parts
14677 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14678 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14679 // concat the vectors to original VT
14681 EVT VT = N->getValueType(0);
14682 SDValue Op = N->getOperand(0);
14683 EVT OpVT = Op.getValueType();
14684 DebugLoc dl = N->getDebugLoc();
14686 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14687 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14689 unsigned NumElems = OpVT.getVectorNumElements();
14690 SmallVector<int,8> ShufMask1(NumElems, -1);
14691 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14693 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14696 SmallVector<int,8> ShufMask2(NumElems, -1);
14697 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14699 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14702 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14703 VT.getVectorNumElements()/2);
14705 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14706 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14708 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14713 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14714 const X86Subtarget *Subtarget) {
14715 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14716 // (and (i32 x86isd::setcc_carry), 1)
14717 // This eliminates the zext. This transformation is necessary because
14718 // ISD::SETCC is always legalized to i8.
14719 DebugLoc dl = N->getDebugLoc();
14720 SDValue N0 = N->getOperand(0);
14721 EVT VT = N->getValueType(0);
14722 EVT OpVT = N0.getValueType();
14724 if (N0.getOpcode() == ISD::AND &&
14726 N0.getOperand(0).hasOneUse()) {
14727 SDValue N00 = N0.getOperand(0);
14728 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14730 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14731 if (!C || C->getZExtValue() != 1)
14733 return DAG.getNode(ISD::AND, dl, VT,
14734 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14735 N00.getOperand(0), N00.getOperand(1)),
14736 DAG.getConstant(1, VT));
14738 // Optimize vectors in AVX mode:
14741 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14742 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14743 // Concat upper and lower parts.
14746 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14747 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14748 // Concat upper and lower parts.
14750 if (Subtarget->hasAVX()) {
14752 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14753 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14755 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14756 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14757 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14759 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14760 VT.getVectorNumElements()/2);
14762 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14763 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14765 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14773 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14774 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14775 unsigned X86CC = N->getConstantOperandVal(0);
14776 SDValue EFLAG = N->getOperand(1);
14777 DebugLoc DL = N->getDebugLoc();
14779 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14780 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14782 if (X86CC == X86::COND_B)
14783 return DAG.getNode(ISD::AND, DL, MVT::i8,
14784 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14785 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14786 DAG.getConstant(1, MVT::i8));
14791 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14792 const X86TargetLowering *XTLI) {
14793 SDValue Op0 = N->getOperand(0);
14794 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14795 // a 32-bit target where SSE doesn't support i64->FP operations.
14796 if (Op0.getOpcode() == ISD::LOAD) {
14797 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14798 EVT VT = Ld->getValueType(0);
14799 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14800 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14801 !XTLI->getSubtarget()->is64Bit() &&
14802 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14803 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14804 Ld->getChain(), Op0, DAG);
14805 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14812 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14813 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14814 X86TargetLowering::DAGCombinerInfo &DCI) {
14815 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14816 // the result is either zero or one (depending on the input carry bit).
14817 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14818 if (X86::isZeroNode(N->getOperand(0)) &&
14819 X86::isZeroNode(N->getOperand(1)) &&
14820 // We don't have a good way to replace an EFLAGS use, so only do this when
14822 SDValue(N, 1).use_empty()) {
14823 DebugLoc DL = N->getDebugLoc();
14824 EVT VT = N->getValueType(0);
14825 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14826 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14827 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14828 DAG.getConstant(X86::COND_B,MVT::i8),
14830 DAG.getConstant(1, VT));
14831 return DCI.CombineTo(N, Res1, CarryOut);
14837 // fold (add Y, (sete X, 0)) -> adc 0, Y
14838 // (add Y, (setne X, 0)) -> sbb -1, Y
14839 // (sub (sete X, 0), Y) -> sbb 0, Y
14840 // (sub (setne X, 0), Y) -> adc -1, Y
14841 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14842 DebugLoc DL = N->getDebugLoc();
14844 // Look through ZExts.
14845 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14846 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14849 SDValue SetCC = Ext.getOperand(0);
14850 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14853 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14854 if (CC != X86::COND_E && CC != X86::COND_NE)
14857 SDValue Cmp = SetCC.getOperand(1);
14858 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14859 !X86::isZeroNode(Cmp.getOperand(1)) ||
14860 !Cmp.getOperand(0).getValueType().isInteger())
14863 SDValue CmpOp0 = Cmp.getOperand(0);
14864 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14865 DAG.getConstant(1, CmpOp0.getValueType()));
14867 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14868 if (CC == X86::COND_NE)
14869 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14870 DL, OtherVal.getValueType(), OtherVal,
14871 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14872 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14873 DL, OtherVal.getValueType(), OtherVal,
14874 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14877 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14878 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14879 const X86Subtarget *Subtarget) {
14880 EVT VT = N->getValueType(0);
14881 SDValue Op0 = N->getOperand(0);
14882 SDValue Op1 = N->getOperand(1);
14884 // Try to synthesize horizontal adds from adds of shuffles.
14885 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14886 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14887 isHorizontalBinOp(Op0, Op1, true))
14888 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14890 return OptimizeConditionalInDecrement(N, DAG);
14893 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14894 const X86Subtarget *Subtarget) {
14895 SDValue Op0 = N->getOperand(0);
14896 SDValue Op1 = N->getOperand(1);
14898 // X86 can't encode an immediate LHS of a sub. See if we can push the
14899 // negation into a preceding instruction.
14900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14901 // If the RHS of the sub is a XOR with one use and a constant, invert the
14902 // immediate. Then add one to the LHS of the sub so we can turn
14903 // X-Y -> X+~Y+1, saving one register.
14904 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14905 isa<ConstantSDNode>(Op1.getOperand(1))) {
14906 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14907 EVT VT = Op0.getValueType();
14908 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14910 DAG.getConstant(~XorC, VT));
14911 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14912 DAG.getConstant(C->getAPIntValue()+1, VT));
14916 // Try to synthesize horizontal adds from adds of shuffles.
14917 EVT VT = N->getValueType(0);
14918 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14919 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14920 isHorizontalBinOp(Op0, Op1, true))
14921 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14923 return OptimizeConditionalInDecrement(N, DAG);
14926 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14927 DAGCombinerInfo &DCI) const {
14928 SelectionDAG &DAG = DCI.DAG;
14929 switch (N->getOpcode()) {
14931 case ISD::EXTRACT_VECTOR_ELT:
14932 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
14934 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14935 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14936 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14937 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14938 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14939 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14942 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
14943 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14944 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14945 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14946 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14947 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14948 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14949 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14950 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14952 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14953 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14954 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14955 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14956 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
14957 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
14958 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
14959 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14960 case X86ISD::SHUFP: // Handle all target specific shuffles
14961 case X86ISD::PALIGN:
14962 case X86ISD::UNPCKH:
14963 case X86ISD::UNPCKL:
14964 case X86ISD::MOVHLPS:
14965 case X86ISD::MOVLHPS:
14966 case X86ISD::PSHUFD:
14967 case X86ISD::PSHUFHW:
14968 case X86ISD::PSHUFLW:
14969 case X86ISD::MOVSS:
14970 case X86ISD::MOVSD:
14971 case X86ISD::VPERMILP:
14972 case X86ISD::VPERM2X128:
14973 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14979 /// isTypeDesirableForOp - Return true if the target has native support for
14980 /// the specified value type and it is 'desirable' to use the type for the
14981 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14982 /// instruction encodings are longer and some i16 instructions are slow.
14983 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14984 if (!isTypeLegal(VT))
14986 if (VT != MVT::i16)
14993 case ISD::SIGN_EXTEND:
14994 case ISD::ZERO_EXTEND:
14995 case ISD::ANY_EXTEND:
15008 /// IsDesirableToPromoteOp - This method query the target whether it is
15009 /// beneficial for dag combiner to promote the specified node. If true, it
15010 /// should return the desired promotion type by reference.
15011 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15012 EVT VT = Op.getValueType();
15013 if (VT != MVT::i16)
15016 bool Promote = false;
15017 bool Commute = false;
15018 switch (Op.getOpcode()) {
15021 LoadSDNode *LD = cast<LoadSDNode>(Op);
15022 // If the non-extending load has a single use and it's not live out, then it
15023 // might be folded.
15024 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15025 Op.hasOneUse()*/) {
15026 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15027 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15028 // The only case where we'd want to promote LOAD (rather then it being
15029 // promoted as an operand is when it's only use is liveout.
15030 if (UI->getOpcode() != ISD::CopyToReg)
15037 case ISD::SIGN_EXTEND:
15038 case ISD::ZERO_EXTEND:
15039 case ISD::ANY_EXTEND:
15044 SDValue N0 = Op.getOperand(0);
15045 // Look out for (store (shl (load), x)).
15046 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15059 SDValue N0 = Op.getOperand(0);
15060 SDValue N1 = Op.getOperand(1);
15061 if (!Commute && MayFoldLoad(N1))
15063 // Avoid disabling potential load folding opportunities.
15064 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15066 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15076 //===----------------------------------------------------------------------===//
15077 // X86 Inline Assembly Support
15078 //===----------------------------------------------------------------------===//
15081 // Helper to match a string separated by whitespace.
15082 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15083 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15085 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15086 StringRef piece(*args[i]);
15087 if (!s.startswith(piece)) // Check if the piece matches.
15090 s = s.substr(piece.size());
15091 StringRef::size_type pos = s.find_first_not_of(" \t");
15092 if (pos == 0) // We matched a prefix.
15100 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15103 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15104 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15106 std::string AsmStr = IA->getAsmString();
15108 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15109 if (!Ty || Ty->getBitWidth() % 16 != 0)
15112 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15113 SmallVector<StringRef, 4> AsmPieces;
15114 SplitString(AsmStr, AsmPieces, ";\n");
15116 switch (AsmPieces.size()) {
15117 default: return false;
15119 // FIXME: this should verify that we are targeting a 486 or better. If not,
15120 // we will turn this bswap into something that will be lowered to logical
15121 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15122 // lower so don't worry about this.
15124 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15125 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15126 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15127 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15128 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15129 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15130 // No need to check constraints, nothing other than the equivalent of
15131 // "=r,0" would be valid here.
15132 return IntrinsicLowering::LowerToByteSwap(CI);
15135 // rorw $$8, ${0:w} --> llvm.bswap.i16
15136 if (CI->getType()->isIntegerTy(16) &&
15137 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15138 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15139 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15141 const std::string &ConstraintsStr = IA->getConstraintString();
15142 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15143 std::sort(AsmPieces.begin(), AsmPieces.end());
15144 if (AsmPieces.size() == 4 &&
15145 AsmPieces[0] == "~{cc}" &&
15146 AsmPieces[1] == "~{dirflag}" &&
15147 AsmPieces[2] == "~{flags}" &&
15148 AsmPieces[3] == "~{fpsr}")
15149 return IntrinsicLowering::LowerToByteSwap(CI);
15153 if (CI->getType()->isIntegerTy(32) &&
15154 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15155 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15156 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15157 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15159 const std::string &ConstraintsStr = IA->getConstraintString();
15160 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15161 std::sort(AsmPieces.begin(), AsmPieces.end());
15162 if (AsmPieces.size() == 4 &&
15163 AsmPieces[0] == "~{cc}" &&
15164 AsmPieces[1] == "~{dirflag}" &&
15165 AsmPieces[2] == "~{flags}" &&
15166 AsmPieces[3] == "~{fpsr}")
15167 return IntrinsicLowering::LowerToByteSwap(CI);
15170 if (CI->getType()->isIntegerTy(64)) {
15171 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15172 if (Constraints.size() >= 2 &&
15173 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15174 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15175 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15176 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15177 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15178 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15179 return IntrinsicLowering::LowerToByteSwap(CI);
15189 /// getConstraintType - Given a constraint letter, return the type of
15190 /// constraint it is for this target.
15191 X86TargetLowering::ConstraintType
15192 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15193 if (Constraint.size() == 1) {
15194 switch (Constraint[0]) {
15205 return C_RegisterClass;
15229 return TargetLowering::getConstraintType(Constraint);
15232 /// Examine constraint type and operand type and determine a weight value.
15233 /// This object must already have been set up with the operand type
15234 /// and the current alternative constraint selected.
15235 TargetLowering::ConstraintWeight
15236 X86TargetLowering::getSingleConstraintMatchWeight(
15237 AsmOperandInfo &info, const char *constraint) const {
15238 ConstraintWeight weight = CW_Invalid;
15239 Value *CallOperandVal = info.CallOperandVal;
15240 // If we don't have a value, we can't do a match,
15241 // but allow it at the lowest weight.
15242 if (CallOperandVal == NULL)
15244 Type *type = CallOperandVal->getType();
15245 // Look at the constraint type.
15246 switch (*constraint) {
15248 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15259 if (CallOperandVal->getType()->isIntegerTy())
15260 weight = CW_SpecificReg;
15265 if (type->isFloatingPointTy())
15266 weight = CW_SpecificReg;
15269 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15270 weight = CW_SpecificReg;
15274 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15275 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15276 weight = CW_Register;
15279 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15280 if (C->getZExtValue() <= 31)
15281 weight = CW_Constant;
15285 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15286 if (C->getZExtValue() <= 63)
15287 weight = CW_Constant;
15291 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15292 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15293 weight = CW_Constant;
15297 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15298 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15299 weight = CW_Constant;
15303 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15304 if (C->getZExtValue() <= 3)
15305 weight = CW_Constant;
15309 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15310 if (C->getZExtValue() <= 0xff)
15311 weight = CW_Constant;
15316 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15317 weight = CW_Constant;
15321 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15322 if ((C->getSExtValue() >= -0x80000000LL) &&
15323 (C->getSExtValue() <= 0x7fffffffLL))
15324 weight = CW_Constant;
15328 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15329 if (C->getZExtValue() <= 0xffffffff)
15330 weight = CW_Constant;
15337 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15338 /// with another that has more specific requirements based on the type of the
15339 /// corresponding operand.
15340 const char *X86TargetLowering::
15341 LowerXConstraint(EVT ConstraintVT) const {
15342 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15343 // 'f' like normal targets.
15344 if (ConstraintVT.isFloatingPoint()) {
15345 if (Subtarget->hasSSE2())
15347 if (Subtarget->hasSSE1())
15351 return TargetLowering::LowerXConstraint(ConstraintVT);
15354 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15355 /// vector. If it is invalid, don't add anything to Ops.
15356 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15357 std::string &Constraint,
15358 std::vector<SDValue>&Ops,
15359 SelectionDAG &DAG) const {
15360 SDValue Result(0, 0);
15362 // Only support length 1 constraints for now.
15363 if (Constraint.length() > 1) return;
15365 char ConstraintLetter = Constraint[0];
15366 switch (ConstraintLetter) {
15369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15370 if (C->getZExtValue() <= 31) {
15371 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15378 if (C->getZExtValue() <= 63) {
15379 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15385 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15386 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15387 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15393 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15394 if (C->getZExtValue() <= 255) {
15395 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15401 // 32-bit signed value
15402 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15403 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15404 C->getSExtValue())) {
15405 // Widen to 64 bits here to get it sign extended.
15406 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15409 // FIXME gcc accepts some relocatable values here too, but only in certain
15410 // memory models; it's complicated.
15415 // 32-bit unsigned value
15416 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15417 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15418 C->getZExtValue())) {
15419 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15423 // FIXME gcc accepts some relocatable values here too, but only in certain
15424 // memory models; it's complicated.
15428 // Literal immediates are always ok.
15429 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15430 // Widen to 64 bits here to get it sign extended.
15431 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15435 // In any sort of PIC mode addresses need to be computed at runtime by
15436 // adding in a register or some sort of table lookup. These can't
15437 // be used as immediates.
15438 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15441 // If we are in non-pic codegen mode, we allow the address of a global (with
15442 // an optional displacement) to be used with 'i'.
15443 GlobalAddressSDNode *GA = 0;
15444 int64_t Offset = 0;
15446 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15448 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15449 Offset += GA->getOffset();
15451 } else if (Op.getOpcode() == ISD::ADD) {
15452 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15453 Offset += C->getZExtValue();
15454 Op = Op.getOperand(0);
15457 } else if (Op.getOpcode() == ISD::SUB) {
15458 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15459 Offset += -C->getZExtValue();
15460 Op = Op.getOperand(0);
15465 // Otherwise, this isn't something we can handle, reject it.
15469 const GlobalValue *GV = GA->getGlobal();
15470 // If we require an extra load to get this address, as in PIC mode, we
15471 // can't accept it.
15472 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15473 getTargetMachine())))
15476 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15477 GA->getValueType(0), Offset);
15482 if (Result.getNode()) {
15483 Ops.push_back(Result);
15486 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15489 std::pair<unsigned, const TargetRegisterClass*>
15490 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15492 // First, see if this is a constraint that directly corresponds to an LLVM
15494 if (Constraint.size() == 1) {
15495 // GCC Constraint Letters
15496 switch (Constraint[0]) {
15498 // TODO: Slight differences here in allocation order and leaving
15499 // RIP in the class. Do they matter any more here than they do
15500 // in the normal allocation?
15501 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15502 if (Subtarget->is64Bit()) {
15503 if (VT == MVT::i32 || VT == MVT::f32)
15504 return std::make_pair(0U, X86::GR32RegisterClass);
15505 else if (VT == MVT::i16)
15506 return std::make_pair(0U, X86::GR16RegisterClass);
15507 else if (VT == MVT::i8 || VT == MVT::i1)
15508 return std::make_pair(0U, X86::GR8RegisterClass);
15509 else if (VT == MVT::i64 || VT == MVT::f64)
15510 return std::make_pair(0U, X86::GR64RegisterClass);
15513 // 32-bit fallthrough
15514 case 'Q': // Q_REGS
15515 if (VT == MVT::i32 || VT == MVT::f32)
15516 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15517 else if (VT == MVT::i16)
15518 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15519 else if (VT == MVT::i8 || VT == MVT::i1)
15520 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15521 else if (VT == MVT::i64)
15522 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15524 case 'r': // GENERAL_REGS
15525 case 'l': // INDEX_REGS
15526 if (VT == MVT::i8 || VT == MVT::i1)
15527 return std::make_pair(0U, X86::GR8RegisterClass);
15528 if (VT == MVT::i16)
15529 return std::make_pair(0U, X86::GR16RegisterClass);
15530 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15531 return std::make_pair(0U, X86::GR32RegisterClass);
15532 return std::make_pair(0U, X86::GR64RegisterClass);
15533 case 'R': // LEGACY_REGS
15534 if (VT == MVT::i8 || VT == MVT::i1)
15535 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15536 if (VT == MVT::i16)
15537 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15538 if (VT == MVT::i32 || !Subtarget->is64Bit())
15539 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15540 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15541 case 'f': // FP Stack registers.
15542 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15543 // value to the correct fpstack register class.
15544 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15545 return std::make_pair(0U, X86::RFP32RegisterClass);
15546 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15547 return std::make_pair(0U, X86::RFP64RegisterClass);
15548 return std::make_pair(0U, X86::RFP80RegisterClass);
15549 case 'y': // MMX_REGS if MMX allowed.
15550 if (!Subtarget->hasMMX()) break;
15551 return std::make_pair(0U, X86::VR64RegisterClass);
15552 case 'Y': // SSE_REGS if SSE2 allowed
15553 if (!Subtarget->hasSSE2()) break;
15555 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15556 if (!Subtarget->hasSSE1()) break;
15558 switch (VT.getSimpleVT().SimpleTy) {
15560 // Scalar SSE types.
15563 return std::make_pair(0U, X86::FR32RegisterClass);
15566 return std::make_pair(0U, X86::FR64RegisterClass);
15574 return std::make_pair(0U, X86::VR128RegisterClass);
15582 return std::make_pair(0U, X86::VR256RegisterClass);
15589 // Use the default implementation in TargetLowering to convert the register
15590 // constraint into a member of a register class.
15591 std::pair<unsigned, const TargetRegisterClass*> Res;
15592 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15594 // Not found as a standard register?
15595 if (Res.second == 0) {
15596 // Map st(0) -> st(7) -> ST0
15597 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15598 tolower(Constraint[1]) == 's' &&
15599 tolower(Constraint[2]) == 't' &&
15600 Constraint[3] == '(' &&
15601 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15602 Constraint[5] == ')' &&
15603 Constraint[6] == '}') {
15605 Res.first = X86::ST0+Constraint[4]-'0';
15606 Res.second = X86::RFP80RegisterClass;
15610 // GCC allows "st(0)" to be called just plain "st".
15611 if (StringRef("{st}").equals_lower(Constraint)) {
15612 Res.first = X86::ST0;
15613 Res.second = X86::RFP80RegisterClass;
15618 if (StringRef("{flags}").equals_lower(Constraint)) {
15619 Res.first = X86::EFLAGS;
15620 Res.second = X86::CCRRegisterClass;
15624 // 'A' means EAX + EDX.
15625 if (Constraint == "A") {
15626 Res.first = X86::EAX;
15627 Res.second = X86::GR32_ADRegisterClass;
15633 // Otherwise, check to see if this is a register class of the wrong value
15634 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15635 // turn into {ax},{dx}.
15636 if (Res.second->hasType(VT))
15637 return Res; // Correct type already, nothing to do.
15639 // All of the single-register GCC register classes map their values onto
15640 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15641 // really want an 8-bit or 32-bit register, map to the appropriate register
15642 // class and return the appropriate register.
15643 if (Res.second == X86::GR16RegisterClass) {
15644 if (VT == MVT::i8) {
15645 unsigned DestReg = 0;
15646 switch (Res.first) {
15648 case X86::AX: DestReg = X86::AL; break;
15649 case X86::DX: DestReg = X86::DL; break;
15650 case X86::CX: DestReg = X86::CL; break;
15651 case X86::BX: DestReg = X86::BL; break;
15654 Res.first = DestReg;
15655 Res.second = X86::GR8RegisterClass;
15657 } else if (VT == MVT::i32) {
15658 unsigned DestReg = 0;
15659 switch (Res.first) {
15661 case X86::AX: DestReg = X86::EAX; break;
15662 case X86::DX: DestReg = X86::EDX; break;
15663 case X86::CX: DestReg = X86::ECX; break;
15664 case X86::BX: DestReg = X86::EBX; break;
15665 case X86::SI: DestReg = X86::ESI; break;
15666 case X86::DI: DestReg = X86::EDI; break;
15667 case X86::BP: DestReg = X86::EBP; break;
15668 case X86::SP: DestReg = X86::ESP; break;
15671 Res.first = DestReg;
15672 Res.second = X86::GR32RegisterClass;
15674 } else if (VT == MVT::i64) {
15675 unsigned DestReg = 0;
15676 switch (Res.first) {
15678 case X86::AX: DestReg = X86::RAX; break;
15679 case X86::DX: DestReg = X86::RDX; break;
15680 case X86::CX: DestReg = X86::RCX; break;
15681 case X86::BX: DestReg = X86::RBX; break;
15682 case X86::SI: DestReg = X86::RSI; break;
15683 case X86::DI: DestReg = X86::RDI; break;
15684 case X86::BP: DestReg = X86::RBP; break;
15685 case X86::SP: DestReg = X86::RSP; break;
15688 Res.first = DestReg;
15689 Res.second = X86::GR64RegisterClass;
15692 } else if (Res.second == X86::FR32RegisterClass ||
15693 Res.second == X86::FR64RegisterClass ||
15694 Res.second == X86::VR128RegisterClass) {
15695 // Handle references to XMM physical registers that got mapped into the
15696 // wrong class. This can happen with constraints like {xmm0} where the
15697 // target independent register mapper will just pick the first match it can
15698 // find, ignoring the required type.
15699 if (VT == MVT::f32)
15700 Res.second = X86::FR32RegisterClass;
15701 else if (VT == MVT::f64)
15702 Res.second = X86::FR64RegisterClass;
15703 else if (X86::VR128RegisterClass->hasType(VT))
15704 Res.second = X86::VR128RegisterClass;