1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
54 using namespace dwarf;
56 STATISTIC(NumTailCalls, "Number of tail calls");
59 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
61 // Forward declarations.
62 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
65 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
67 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
69 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
70 if (is64Bit) return new X8664_MachoTargetObjectFile();
71 return new TargetLoweringObjectFileMachO();
72 } else if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
73 if (is64Bit) return new X8664_ELFTargetObjectFile(TM);
74 return new X8632_ELFTargetObjectFile(TM);
75 } else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
76 return new TargetLoweringObjectFileCOFF();
78 llvm_unreachable("unknown subtarget type");
81 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
82 : TargetLowering(TM, createTLOF(TM)) {
83 Subtarget = &TM.getSubtarget<X86Subtarget>();
84 X86ScalarSSEf64 = Subtarget->hasSSE2();
85 X86ScalarSSEf32 = Subtarget->hasSSE1();
86 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
88 RegInfo = TM.getRegisterInfo();
91 // Set up the TargetLowering object.
93 // X86 is weird, it always uses i8 for shift amounts and setcc results.
94 setShiftAmountType(MVT::i8);
95 setBooleanContents(ZeroOrOneBooleanContent);
96 setSchedulingPreference(Sched::RegPressure);
97 setStackPointerRegisterToSaveRestore(X86StackPtr);
99 if (Subtarget->isTargetDarwin()) {
100 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
101 setUseUnderscoreSetJmp(false);
102 setUseUnderscoreLongJmp(false);
103 } else if (Subtarget->isTargetMingw()) {
104 // MS runtime is weird: it exports _setjmp, but longjmp!
105 setUseUnderscoreSetJmp(true);
106 setUseUnderscoreLongJmp(false);
108 setUseUnderscoreSetJmp(true);
109 setUseUnderscoreLongJmp(true);
112 // Set up the register classes.
113 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
114 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
115 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
116 if (Subtarget->is64Bit())
117 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
119 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
121 // We don't accept any truncstore of integer registers.
122 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
123 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
124 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
125 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
127 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
129 // SETOEQ and SETUNE require checking two conditions.
130 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
131 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
132 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
133 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
134 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
135 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
137 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
139 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
140 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
141 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
143 if (Subtarget->is64Bit()) {
144 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
145 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
146 } else if (!UseSoftFloat) {
147 // We have an algorithm for SSE2->double, and we turn this into a
148 // 64-bit FILD followed by conditional FADD for other targets.
149 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
150 // We have an algorithm for SSE2, and we turn this into a 64-bit
151 // FILD for other targets.
152 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
155 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
157 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
158 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
161 // SSE has no i16 to fp conversion, only i32
162 if (X86ScalarSSEf32) {
163 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
164 // f32 and f64 cases are Legal, f80 case is not
165 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
168 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
172 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
175 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
176 // are Legal, f80 is custom lowered.
177 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
178 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
180 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
182 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
183 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
185 if (X86ScalarSSEf32) {
186 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
187 // f32 and f64 cases are Legal, f80 case is not
188 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
190 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
191 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
194 // Handle FP_TO_UINT by promoting the destination to a larger signed
196 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
197 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
198 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
200 if (Subtarget->is64Bit()) {
201 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
202 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
203 } else if (!UseSoftFloat) {
204 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
205 // Expand FP_TO_UINT into a select.
206 // FIXME: We would like to use a Custom expander here eventually to do
207 // the optimal thing for SSE vs. the default expansion in the legalizer.
208 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
210 // With SSE3 we can use fisttpll to convert to a signed i64; without
211 // SSE, we're stuck with a fistpll.
212 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
215 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
216 if (!X86ScalarSSEf64) {
217 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
218 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
219 if (Subtarget->is64Bit()) {
220 setOperationAction(ISD::BIT_CONVERT , MVT::f64 , Expand);
221 // Without SSE, i64->f64 goes through memory; i64->MMX is Legal.
222 if (Subtarget->hasMMX() && !DisableMMX)
223 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Custom);
225 setOperationAction(ISD::BIT_CONVERT , MVT::i64 , Expand);
229 // Scalar integer divide and remainder are lowered to use operations that
230 // produce two results, to match the available instructions. This exposes
231 // the two-result form to trivial CSE, which is able to combine x/y and x%y
232 // into a single instruction.
234 // Scalar integer multiply-high is also lowered to use two-result
235 // operations, to match the available instructions. However, plain multiply
236 // (low) operations are left as Legal, as there are single-result
237 // instructions for this in x86. Using the two-result multiply instructions
238 // when both high and low results are needed must be arranged by dagcombine.
239 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
240 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
241 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
242 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
243 setOperationAction(ISD::SREM , MVT::i8 , Expand);
244 setOperationAction(ISD::UREM , MVT::i8 , Expand);
245 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
246 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
247 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
248 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
249 setOperationAction(ISD::SREM , MVT::i16 , Expand);
250 setOperationAction(ISD::UREM , MVT::i16 , Expand);
251 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
252 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
253 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
254 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
255 setOperationAction(ISD::SREM , MVT::i32 , Expand);
256 setOperationAction(ISD::UREM , MVT::i32 , Expand);
257 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
258 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
259 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
260 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
261 setOperationAction(ISD::SREM , MVT::i64 , Expand);
262 setOperationAction(ISD::UREM , MVT::i64 , Expand);
264 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
265 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
266 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
267 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
268 if (Subtarget->is64Bit())
269 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
270 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
273 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
274 setOperationAction(ISD::FREM , MVT::f32 , Expand);
275 setOperationAction(ISD::FREM , MVT::f64 , Expand);
276 setOperationAction(ISD::FREM , MVT::f80 , Expand);
277 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
279 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
280 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
281 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
282 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
283 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
286 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
287 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
288 if (Subtarget->is64Bit()) {
289 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
290 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
291 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
294 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
295 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
297 // These should be promoted to a larger select which is supported.
298 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
299 // X86 wants to expand cmov itself.
300 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
301 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
302 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
303 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
304 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
305 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
306 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
307 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
308 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
309 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
310 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
311 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
312 if (Subtarget->is64Bit()) {
313 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
314 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
316 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
319 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
320 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
321 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
322 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
323 if (Subtarget->is64Bit())
324 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
325 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
326 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
327 if (Subtarget->is64Bit()) {
328 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
329 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
330 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
331 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
332 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
334 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
335 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
336 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
337 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
338 if (Subtarget->is64Bit()) {
339 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
340 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
341 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
344 if (Subtarget->hasSSE1())
345 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
347 // We may not have a libcall for MEMBARRIER so we should lower this.
348 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
350 // On X86 and X86-64, atomic operations are lowered to locked instructions.
351 // Locked instructions, in turn, have implicit fence semantics (all memory
352 // operations are flushed before issuing the locked instruction, and they
353 // are not buffered), so we can fold away the common pattern of
354 // fence-atomic-fence.
355 setShouldFoldAtomicFences(true);
357 // Expand certain atomics
358 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
359 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
360 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
361 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
363 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
364 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
365 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
366 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
368 if (!Subtarget->is64Bit()) {
369 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
370 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
371 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
372 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
373 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
375 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
378 // FIXME - use subtarget debug flags
379 if (!Subtarget->isTargetDarwin() &&
380 !Subtarget->isTargetELF() &&
381 !Subtarget->isTargetCygMing()) {
382 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
385 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
386 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
387 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
388 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
389 if (Subtarget->is64Bit()) {
390 setExceptionPointerRegister(X86::RAX);
391 setExceptionSelectorRegister(X86::RDX);
393 setExceptionPointerRegister(X86::EAX);
394 setExceptionSelectorRegister(X86::EDX);
396 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
397 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
399 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
401 setOperationAction(ISD::TRAP, MVT::Other, Legal);
403 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
404 setOperationAction(ISD::VASTART , MVT::Other, Custom);
405 setOperationAction(ISD::VAEND , MVT::Other, Expand);
406 if (Subtarget->is64Bit()) {
407 setOperationAction(ISD::VAARG , MVT::Other, Custom);
408 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
410 setOperationAction(ISD::VAARG , MVT::Other, Expand);
411 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
414 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
415 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
416 if (Subtarget->is64Bit())
417 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
418 if (Subtarget->isTargetCygMing())
419 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
421 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
423 if (!UseSoftFloat && X86ScalarSSEf64) {
424 // f32 and f64 use SSE.
425 // Set up the FP register classes.
426 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
427 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
429 // Use ANDPD to simulate FABS.
430 setOperationAction(ISD::FABS , MVT::f64, Custom);
431 setOperationAction(ISD::FABS , MVT::f32, Custom);
433 // Use XORP to simulate FNEG.
434 setOperationAction(ISD::FNEG , MVT::f64, Custom);
435 setOperationAction(ISD::FNEG , MVT::f32, Custom);
437 // Use ANDPD and ORPD to simulate FCOPYSIGN.
438 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
439 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
441 // We don't support sin/cos/fmod
442 setOperationAction(ISD::FSIN , MVT::f64, Expand);
443 setOperationAction(ISD::FCOS , MVT::f64, Expand);
444 setOperationAction(ISD::FSIN , MVT::f32, Expand);
445 setOperationAction(ISD::FCOS , MVT::f32, Expand);
447 // Expand FP immediates into loads from the stack, except for the special
449 addLegalFPImmediate(APFloat(+0.0)); // xorpd
450 addLegalFPImmediate(APFloat(+0.0f)); // xorps
451 } else if (!UseSoftFloat && X86ScalarSSEf32) {
452 // Use SSE for f32, x87 for f64.
453 // Set up the FP register classes.
454 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
455 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
457 // Use ANDPS to simulate FABS.
458 setOperationAction(ISD::FABS , MVT::f32, Custom);
460 // Use XORP to simulate FNEG.
461 setOperationAction(ISD::FNEG , MVT::f32, Custom);
463 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
465 // Use ANDPS and ORPS to simulate FCOPYSIGN.
466 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
467 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
469 // We don't support sin/cos/fmod
470 setOperationAction(ISD::FSIN , MVT::f32, Expand);
471 setOperationAction(ISD::FCOS , MVT::f32, Expand);
473 // Special cases we handle for FP constants.
474 addLegalFPImmediate(APFloat(+0.0f)); // xorps
475 addLegalFPImmediate(APFloat(+0.0)); // FLD0
476 addLegalFPImmediate(APFloat(+1.0)); // FLD1
477 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
478 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
481 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
482 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
484 } else if (!UseSoftFloat) {
485 // f32 and f64 in x87.
486 // Set up the FP register classes.
487 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
488 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
490 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
491 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
492 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
493 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
496 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
497 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
499 addLegalFPImmediate(APFloat(+0.0)); // FLD0
500 addLegalFPImmediate(APFloat(+1.0)); // FLD1
501 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
502 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
503 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
504 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
505 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
506 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
509 // Long double always uses X87.
511 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
512 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
513 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
516 APFloat TmpFlt(+0.0);
517 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
519 addLegalFPImmediate(TmpFlt); // FLD0
521 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
522 APFloat TmpFlt2(+1.0);
523 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
525 addLegalFPImmediate(TmpFlt2); // FLD1
526 TmpFlt2.changeSign();
527 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
531 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
532 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
536 // Always use a library call for pow.
537 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
538 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
539 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
541 setOperationAction(ISD::FLOG, MVT::f80, Expand);
542 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
543 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
544 setOperationAction(ISD::FEXP, MVT::f80, Expand);
545 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
547 // First set operation action for all vector types to either promote
548 // (for widening) or expand (for scalarization). Then we will selectively
549 // turn on ones that can be effectively codegen'd.
550 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
551 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
552 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
567 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
568 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
601 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
604 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
605 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
606 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
607 setTruncStoreAction((MVT::SimpleValueType)VT,
608 (MVT::SimpleValueType)InnerVT, Expand);
609 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
610 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
611 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
614 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
615 // with -msoft-float, disable use of MMX as well.
616 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
617 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass, false);
619 // FIXME: Remove the rest of this stuff.
620 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
621 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
622 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
624 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
626 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
627 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
628 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
629 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
631 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
632 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
633 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
634 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
636 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
637 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
639 setOperationAction(ISD::AND, MVT::v8i8, Promote);
640 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
641 setOperationAction(ISD::AND, MVT::v4i16, Promote);
642 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
643 setOperationAction(ISD::AND, MVT::v2i32, Promote);
644 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
645 setOperationAction(ISD::AND, MVT::v1i64, Legal);
647 setOperationAction(ISD::OR, MVT::v8i8, Promote);
648 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
649 setOperationAction(ISD::OR, MVT::v4i16, Promote);
650 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
651 setOperationAction(ISD::OR, MVT::v2i32, Promote);
652 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
653 setOperationAction(ISD::OR, MVT::v1i64, Legal);
655 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
656 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
657 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
658 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
659 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
660 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
661 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
663 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
664 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
665 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
666 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
667 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
668 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
669 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
671 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
673 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
674 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
676 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
677 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
678 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
679 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
681 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
682 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
683 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
685 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
687 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
688 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
689 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
690 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
691 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
692 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
693 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
695 if (!X86ScalarSSEf64 && Subtarget->is64Bit()) {
696 setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
697 setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
698 setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
699 setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
703 if (!UseSoftFloat && Subtarget->hasSSE1()) {
704 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
706 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
707 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
708 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
709 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
710 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
711 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
712 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
713 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
714 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
715 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
716 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
717 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
720 if (!UseSoftFloat && Subtarget->hasSSE2()) {
721 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
723 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
724 // registers cannot be used even for integer operations.
725 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
726 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
727 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
728 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
730 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
731 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
732 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
733 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
734 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
735 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
736 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
737 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
738 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
739 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
740 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
741 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
742 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
743 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
744 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
745 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
747 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
748 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
749 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
750 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
752 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
753 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
754 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
758 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
759 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
760 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
761 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
762 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
764 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
765 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
766 EVT VT = (MVT::SimpleValueType)i;
767 // Do not attempt to custom lower non-power-of-2 vectors
768 if (!isPowerOf2_32(VT.getVectorNumElements()))
770 // Do not attempt to custom lower non-128-bit vectors
771 if (!VT.is128BitVector())
773 setOperationAction(ISD::BUILD_VECTOR,
774 VT.getSimpleVT().SimpleTy, Custom);
775 setOperationAction(ISD::VECTOR_SHUFFLE,
776 VT.getSimpleVT().SimpleTy, Custom);
777 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
778 VT.getSimpleVT().SimpleTy, Custom);
781 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
782 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
783 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
784 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
785 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
786 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
788 if (Subtarget->is64Bit()) {
789 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
790 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
793 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
794 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
795 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
798 // Do not attempt to promote non-128-bit vectors
799 if (!VT.is128BitVector())
802 setOperationAction(ISD::AND, SVT, Promote);
803 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
804 setOperationAction(ISD::OR, SVT, Promote);
805 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
806 setOperationAction(ISD::XOR, SVT, Promote);
807 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
808 setOperationAction(ISD::LOAD, SVT, Promote);
809 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
810 setOperationAction(ISD::SELECT, SVT, Promote);
811 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
814 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
816 // Custom lower v2i64 and v2f64 selects.
817 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
818 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
819 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
820 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
822 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
823 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
824 if (!DisableMMX && Subtarget->hasMMX()) {
825 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
826 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
830 if (Subtarget->hasSSE41()) {
831 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
832 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
833 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
834 setOperationAction(ISD::FRINT, MVT::f32, Legal);
835 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
836 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
837 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
838 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
839 setOperationAction(ISD::FRINT, MVT::f64, Legal);
840 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
842 // FIXME: Do we need to handle scalar-to-vector here?
843 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
845 // Can turn SHL into an integer multiply.
846 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
847 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
849 // i8 and i16 vectors are custom , because the source register and source
850 // source memory operand types are not the same width. f32 vectors are
851 // custom since the immediate controlling the insert encodes additional
853 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
854 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
855 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
856 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
858 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
859 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
860 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
863 if (Subtarget->is64Bit()) {
864 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
865 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
869 if (Subtarget->hasSSE42()) {
870 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
873 if (!UseSoftFloat && Subtarget->hasAVX()) {
874 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
875 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
876 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
877 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
878 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
880 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
881 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
882 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
883 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
884 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
885 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
886 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
887 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
888 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
889 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
890 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
891 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
892 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
893 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
894 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
896 // Operations to consider commented out -v16i16 v32i8
897 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
898 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
899 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
900 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
901 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
902 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
903 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
904 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
905 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
906 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
907 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
908 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
909 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
910 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
912 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
913 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
914 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
915 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
917 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
918 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
919 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
920 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
924 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
925 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
926 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
927 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
928 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
931 // Not sure we want to do this since there are no 256-bit integer
934 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
935 // This includes 256-bit vectors
936 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
937 EVT VT = (MVT::SimpleValueType)i;
939 // Do not attempt to custom lower non-power-of-2 vectors
940 if (!isPowerOf2_32(VT.getVectorNumElements()))
943 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
944 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
945 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
948 if (Subtarget->is64Bit()) {
949 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
950 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
955 // Not sure we want to do this since there are no 256-bit integer
958 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
959 // Including 256-bit vectors
960 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
961 EVT VT = (MVT::SimpleValueType)i;
963 if (!VT.is256BitVector()) {
966 setOperationAction(ISD::AND, VT, Promote);
967 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
968 setOperationAction(ISD::OR, VT, Promote);
969 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
970 setOperationAction(ISD::XOR, VT, Promote);
971 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
972 setOperationAction(ISD::LOAD, VT, Promote);
973 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
974 setOperationAction(ISD::SELECT, VT, Promote);
975 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
978 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
982 // We want to custom lower some of our intrinsics.
983 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
985 // Add/Sub/Mul with overflow operations are custom lowered.
986 setOperationAction(ISD::SADDO, MVT::i32, Custom);
987 setOperationAction(ISD::UADDO, MVT::i32, Custom);
988 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
989 setOperationAction(ISD::USUBO, MVT::i32, Custom);
990 setOperationAction(ISD::SMULO, MVT::i32, Custom);
992 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
993 // handle type legalization for these operations here.
995 // FIXME: We really should do custom legalization for addition and
996 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
997 // than generic legalization for 64-bit multiplication-with-overflow, though.
998 if (Subtarget->is64Bit()) {
999 setOperationAction(ISD::SADDO, MVT::i64, Custom);
1000 setOperationAction(ISD::UADDO, MVT::i64, Custom);
1001 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
1002 setOperationAction(ISD::USUBO, MVT::i64, Custom);
1003 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1006 if (!Subtarget->is64Bit()) {
1007 // These libcalls are not available in 32-bit.
1008 setLibcallName(RTLIB::SHL_I128, 0);
1009 setLibcallName(RTLIB::SRL_I128, 0);
1010 setLibcallName(RTLIB::SRA_I128, 0);
1013 // We have target-specific dag combine patterns for the following nodes:
1014 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1015 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1016 setTargetDAGCombine(ISD::BUILD_VECTOR);
1017 setTargetDAGCombine(ISD::SELECT);
1018 setTargetDAGCombine(ISD::SHL);
1019 setTargetDAGCombine(ISD::SRA);
1020 setTargetDAGCombine(ISD::SRL);
1021 setTargetDAGCombine(ISD::OR);
1022 setTargetDAGCombine(ISD::STORE);
1023 setTargetDAGCombine(ISD::ZERO_EXTEND);
1024 if (Subtarget->is64Bit())
1025 setTargetDAGCombine(ISD::MUL);
1027 computeRegisterProperties();
1029 // FIXME: These should be based on subtarget info. Plus, the values should
1030 // be smaller when we are in optimizing for size mode.
1031 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1032 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1033 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
1034 setPrefLoopAlignment(16);
1035 benefitFromCodePlacementOpt = true;
1039 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
1044 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1045 /// the desired ByVal argument alignment.
1046 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1049 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1050 if (VTy->getBitWidth() == 128)
1052 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1053 unsigned EltAlign = 0;
1054 getMaxByValAlign(ATy->getElementType(), EltAlign);
1055 if (EltAlign > MaxAlign)
1056 MaxAlign = EltAlign;
1057 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1058 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1059 unsigned EltAlign = 0;
1060 getMaxByValAlign(STy->getElementType(i), EltAlign);
1061 if (EltAlign > MaxAlign)
1062 MaxAlign = EltAlign;
1070 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1071 /// function arguments in the caller parameter area. For X86, aggregates
1072 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1073 /// are at 4-byte boundaries.
1074 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1075 if (Subtarget->is64Bit()) {
1076 // Max of 8 and alignment of type.
1077 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1084 if (Subtarget->hasSSE1())
1085 getMaxByValAlign(Ty, Align);
1089 /// getOptimalMemOpType - Returns the target specific optimal type for load
1090 /// and store operations as a result of memset, memcpy, and memmove
1091 /// lowering. If DstAlign is zero that means it's safe to destination
1092 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1093 /// means there isn't a need to check it against alignment requirement,
1094 /// probably because the source does not need to be loaded. If
1095 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1096 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1097 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1098 /// constant so it does not need to be loaded.
1099 /// It returns EVT::Other if the type should be determined using generic
1100 /// target-independent logic.
1102 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1103 unsigned DstAlign, unsigned SrcAlign,
1104 bool NonScalarIntSafe,
1106 MachineFunction &MF) const {
1107 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1108 // linux. This is because the stack realignment code can't handle certain
1109 // cases like PR2962. This should be removed when PR2962 is fixed.
1110 const Function *F = MF.getFunction();
1111 if (NonScalarIntSafe &&
1112 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1114 (Subtarget->isUnalignedMemAccessFast() ||
1115 ((DstAlign == 0 || DstAlign >= 16) &&
1116 (SrcAlign == 0 || SrcAlign >= 16))) &&
1117 Subtarget->getStackAlignment() >= 16) {
1118 if (Subtarget->hasSSE2())
1120 if (Subtarget->hasSSE1())
1122 } else if (!MemcpyStrSrc && Size >= 8 &&
1123 !Subtarget->is64Bit() &&
1124 Subtarget->getStackAlignment() >= 8 &&
1125 Subtarget->hasSSE2()) {
1126 // Do not use f64 to lower memcpy if source is string constant. It's
1127 // better to use i32 to avoid the loads.
1131 if (Subtarget->is64Bit() && Size >= 8)
1136 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1137 /// current function. The returned value is a member of the
1138 /// MachineJumpTableInfo::JTEntryKind enum.
1139 unsigned X86TargetLowering::getJumpTableEncoding() const {
1140 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1142 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1143 Subtarget->isPICStyleGOT())
1144 return MachineJumpTableInfo::EK_Custom32;
1146 // Otherwise, use the normal jump table encoding heuristics.
1147 return TargetLowering::getJumpTableEncoding();
1150 /// getPICBaseSymbol - Return the X86-32 PIC base.
1152 X86TargetLowering::getPICBaseSymbol(const MachineFunction *MF,
1153 MCContext &Ctx) const {
1154 const MCAsmInfo &MAI = *getTargetMachine().getMCAsmInfo();
1155 return Ctx.GetOrCreateSymbol(Twine(MAI.getPrivateGlobalPrefix())+
1156 Twine(MF->getFunctionNumber())+"$pb");
1161 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1162 const MachineBasicBlock *MBB,
1163 unsigned uid,MCContext &Ctx) const{
1164 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1165 Subtarget->isPICStyleGOT());
1166 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1168 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1169 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1172 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1174 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1175 SelectionDAG &DAG) const {
1176 if (!Subtarget->is64Bit())
1177 // This doesn't have DebugLoc associated with it, but is not really the
1178 // same as a Register.
1179 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1183 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1184 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1186 const MCExpr *X86TargetLowering::
1187 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1188 MCContext &Ctx) const {
1189 // X86-64 uses RIP relative addressing based on the jump table label.
1190 if (Subtarget->isPICStyleRIPRel())
1191 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1193 // Otherwise, the reference is relative to the PIC base.
1194 return MCSymbolRefExpr::Create(getPICBaseSymbol(MF, Ctx), Ctx);
1197 /// getFunctionAlignment - Return the Log2 alignment of this function.
1198 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1199 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1202 std::pair<const TargetRegisterClass*, uint8_t>
1203 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1204 const TargetRegisterClass *RRC = 0;
1206 switch (VT.getSimpleVT().SimpleTy) {
1208 return TargetLowering::findRepresentativeClass(VT);
1209 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1210 RRC = (Subtarget->is64Bit()
1211 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1213 case MVT::v8i8: case MVT::v4i16:
1214 case MVT::v2i32: case MVT::v1i64:
1215 RRC = X86::VR64RegisterClass;
1217 case MVT::f32: case MVT::f64:
1218 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1219 case MVT::v4f32: case MVT::v2f64:
1220 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1222 RRC = X86::VR128RegisterClass;
1225 return std::make_pair(RRC, Cost);
1229 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1230 MachineFunction &MF) const {
1231 unsigned FPDiff = RegInfo->hasFP(MF) ? 1 : 0;
1232 switch (RC->getID()) {
1235 case X86::GR32RegClassID:
1237 case X86::GR64RegClassID:
1239 case X86::VR128RegClassID:
1240 return Subtarget->is64Bit() ? 10 : 4;
1241 case X86::VR64RegClassID:
1246 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1247 unsigned &Offset) const {
1248 if (!Subtarget->isTargetLinux())
1251 if (Subtarget->is64Bit()) {
1252 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1254 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1267 //===----------------------------------------------------------------------===//
1268 // Return Value Calling Convention Implementation
1269 //===----------------------------------------------------------------------===//
1271 #include "X86GenCallingConv.inc"
1274 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1275 const SmallVectorImpl<ISD::OutputArg> &Outs,
1276 LLVMContext &Context) const {
1277 SmallVector<CCValAssign, 16> RVLocs;
1278 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1280 return CCInfo.CheckReturn(Outs, RetCC_X86);
1284 X86TargetLowering::LowerReturn(SDValue Chain,
1285 CallingConv::ID CallConv, bool isVarArg,
1286 const SmallVectorImpl<ISD::OutputArg> &Outs,
1287 const SmallVectorImpl<SDValue> &OutVals,
1288 DebugLoc dl, SelectionDAG &DAG) const {
1289 MachineFunction &MF = DAG.getMachineFunction();
1290 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1292 SmallVector<CCValAssign, 16> RVLocs;
1293 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1294 RVLocs, *DAG.getContext());
1295 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1297 // Add the regs to the liveout set for the function.
1298 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1299 for (unsigned i = 0; i != RVLocs.size(); ++i)
1300 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1301 MRI.addLiveOut(RVLocs[i].getLocReg());
1305 SmallVector<SDValue, 6> RetOps;
1306 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1307 // Operand #1 = Bytes To Pop
1308 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1311 // Copy the result values into the output registers.
1312 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1313 CCValAssign &VA = RVLocs[i];
1314 assert(VA.isRegLoc() && "Can only return in registers!");
1315 SDValue ValToCopy = OutVals[i];
1316 EVT ValVT = ValToCopy.getValueType();
1318 // If this is x86-64, and we disabled SSE, we can't return FP values
1319 if ((ValVT == MVT::f32 || ValVT == MVT::f64) &&
1320 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1321 report_fatal_error("SSE register return with SSE disabled");
1323 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1324 // llvm-gcc has never done it right and no one has noticed, so this
1325 // should be OK for now.
1326 if (ValVT == MVT::f64 &&
1327 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1328 report_fatal_error("SSE2 register return with SSE2 disabled");
1330 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1331 // the RET instruction and handled by the FP Stackifier.
1332 if (VA.getLocReg() == X86::ST0 ||
1333 VA.getLocReg() == X86::ST1) {
1334 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1335 // change the value to the FP stack register class.
1336 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1337 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1338 RetOps.push_back(ValToCopy);
1339 // Don't emit a copytoreg.
1343 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1344 // which is returned in RAX / RDX.
1345 if (Subtarget->is64Bit()) {
1346 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1347 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1348 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1349 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1352 // If we don't have SSE2 available, convert to v4f32 so the generated
1353 // register is legal.
1354 if (!Subtarget->hasSSE2())
1355 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32,ValToCopy);
1360 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1361 Flag = Chain.getValue(1);
1364 // The x86-64 ABI for returning structs by value requires that we copy
1365 // the sret argument into %rax for the return. We saved the argument into
1366 // a virtual register in the entry block, so now we copy the value out
1368 if (Subtarget->is64Bit() &&
1369 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1370 MachineFunction &MF = DAG.getMachineFunction();
1371 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1372 unsigned Reg = FuncInfo->getSRetReturnReg();
1374 "SRetReturnReg should have been set in LowerFormalArguments().");
1375 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1377 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1378 Flag = Chain.getValue(1);
1380 // RAX now acts like a return value.
1381 MRI.addLiveOut(X86::RAX);
1384 RetOps[0] = Chain; // Update chain.
1386 // Add the flag if we have it.
1388 RetOps.push_back(Flag);
1390 return DAG.getNode(X86ISD::RET_FLAG, dl,
1391 MVT::Other, &RetOps[0], RetOps.size());
1394 /// LowerCallResult - Lower the result values of a call into the
1395 /// appropriate copies out of appropriate physical registers.
1398 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1399 CallingConv::ID CallConv, bool isVarArg,
1400 const SmallVectorImpl<ISD::InputArg> &Ins,
1401 DebugLoc dl, SelectionDAG &DAG,
1402 SmallVectorImpl<SDValue> &InVals) const {
1404 // Assign locations to each value returned by this call.
1405 SmallVector<CCValAssign, 16> RVLocs;
1406 bool Is64Bit = Subtarget->is64Bit();
1407 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1408 RVLocs, *DAG.getContext());
1409 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1411 // Copy all of the result registers out of their specified physreg.
1412 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1413 CCValAssign &VA = RVLocs[i];
1414 EVT CopyVT = VA.getValVT();
1416 // If this is x86-64, and we disabled SSE, we can't return FP values
1417 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1418 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1419 report_fatal_error("SSE register return with SSE disabled");
1424 // If this is a call to a function that returns an fp value on the floating
1425 // point stack, we must guarantee the the value is popped from the stack, so
1426 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1427 // if the return value is not used. We use the FpGET_ST0 instructions
1429 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1430 // If we prefer to use the value in xmm registers, copy it out as f80 and
1431 // use a truncate to move it from fp stack reg to xmm reg.
1432 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1433 bool isST0 = VA.getLocReg() == X86::ST0;
1435 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1436 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1437 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1438 SDValue Ops[] = { Chain, InFlag };
1439 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Flag,
1441 Val = Chain.getValue(0);
1443 // Round the f80 to the right size, which also moves it to the appropriate
1445 if (CopyVT != VA.getValVT())
1446 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1447 // This truncation won't change the value.
1448 DAG.getIntPtrConstant(1));
1449 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1450 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1451 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1452 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1453 MVT::v2i64, InFlag).getValue(1);
1454 Val = Chain.getValue(0);
1455 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1456 Val, DAG.getConstant(0, MVT::i64));
1458 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1459 MVT::i64, InFlag).getValue(1);
1460 Val = Chain.getValue(0);
1462 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1464 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1465 CopyVT, InFlag).getValue(1);
1466 Val = Chain.getValue(0);
1468 InFlag = Chain.getValue(2);
1469 InVals.push_back(Val);
1476 //===----------------------------------------------------------------------===//
1477 // C & StdCall & Fast Calling Convention implementation
1478 //===----------------------------------------------------------------------===//
1479 // StdCall calling convention seems to be standard for many Windows' API
1480 // routines and around. It differs from C calling convention just a little:
1481 // callee should clean up the stack, not caller. Symbols should be also
1482 // decorated in some fancy way :) It doesn't support any vector arguments.
1483 // For info on fast calling convention see Fast Calling Convention (tail call)
1484 // implementation LowerX86_32FastCCCallTo.
1486 /// CallIsStructReturn - Determines whether a call uses struct return
1488 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1492 return Outs[0].Flags.isSRet();
1495 /// ArgsAreStructReturn - Determines whether a function uses struct
1496 /// return semantics.
1498 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1502 return Ins[0].Flags.isSRet();
1505 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1506 /// given CallingConvention value.
1507 CCAssignFn *X86TargetLowering::CCAssignFnForNode(CallingConv::ID CC) const {
1508 if (Subtarget->is64Bit()) {
1509 if (CC == CallingConv::GHC)
1510 return CC_X86_64_GHC;
1511 else if (Subtarget->isTargetWin64())
1512 return CC_X86_Win64_C;
1517 if (CC == CallingConv::X86_FastCall)
1518 return CC_X86_32_FastCall;
1519 else if (CC == CallingConv::X86_ThisCall)
1520 return CC_X86_32_ThisCall;
1521 else if (CC == CallingConv::Fast)
1522 return CC_X86_32_FastCC;
1523 else if (CC == CallingConv::GHC)
1524 return CC_X86_32_GHC;
1529 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1530 /// by "Src" to address "Dst" with size and alignment information specified by
1531 /// the specific parameter attribute. The copy will be passed as a byval
1532 /// function parameter.
1534 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1535 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1537 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1539 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1540 /*isVolatile*/false, /*AlwaysInline=*/true,
1541 MachinePointerInfo(), MachinePointerInfo());
1544 /// IsTailCallConvention - Return true if the calling convention is one that
1545 /// supports tail call optimization.
1546 static bool IsTailCallConvention(CallingConv::ID CC) {
1547 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1550 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1551 /// a tailcall target by changing its ABI.
1552 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1553 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1557 X86TargetLowering::LowerMemArgument(SDValue Chain,
1558 CallingConv::ID CallConv,
1559 const SmallVectorImpl<ISD::InputArg> &Ins,
1560 DebugLoc dl, SelectionDAG &DAG,
1561 const CCValAssign &VA,
1562 MachineFrameInfo *MFI,
1564 // Create the nodes corresponding to a load from this parameter slot.
1565 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1566 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1567 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1570 // If value is passed by pointer we have address passed instead of the value
1572 if (VA.getLocInfo() == CCValAssign::Indirect)
1573 ValVT = VA.getLocVT();
1575 ValVT = VA.getValVT();
1577 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1578 // changed with more analysis.
1579 // In case of tail call optimization mark all arguments mutable. Since they
1580 // could be overwritten by lowering of arguments in case of a tail call.
1581 if (Flags.isByVal()) {
1582 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1583 VA.getLocMemOffset(), isImmutable);
1584 return DAG.getFrameIndex(FI, getPointerTy());
1586 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1587 VA.getLocMemOffset(), isImmutable);
1588 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1589 return DAG.getLoad(ValVT, dl, Chain, FIN,
1590 MachinePointerInfo::getFixedStack(FI),
1596 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1597 CallingConv::ID CallConv,
1599 const SmallVectorImpl<ISD::InputArg> &Ins,
1602 SmallVectorImpl<SDValue> &InVals)
1604 MachineFunction &MF = DAG.getMachineFunction();
1605 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1607 const Function* Fn = MF.getFunction();
1608 if (Fn->hasExternalLinkage() &&
1609 Subtarget->isTargetCygMing() &&
1610 Fn->getName() == "main")
1611 FuncInfo->setForceFramePointer(true);
1613 MachineFrameInfo *MFI = MF.getFrameInfo();
1614 bool Is64Bit = Subtarget->is64Bit();
1615 bool IsWin64 = Subtarget->isTargetWin64();
1617 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1618 "Var args not supported with calling convention fastcc or ghc");
1620 // Assign locations to all of the incoming arguments.
1621 SmallVector<CCValAssign, 16> ArgLocs;
1622 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1623 ArgLocs, *DAG.getContext());
1624 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1626 unsigned LastVal = ~0U;
1628 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1629 CCValAssign &VA = ArgLocs[i];
1630 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1632 assert(VA.getValNo() != LastVal &&
1633 "Don't support value assigned to multiple locs yet");
1634 LastVal = VA.getValNo();
1636 if (VA.isRegLoc()) {
1637 EVT RegVT = VA.getLocVT();
1638 TargetRegisterClass *RC = NULL;
1639 if (RegVT == MVT::i32)
1640 RC = X86::GR32RegisterClass;
1641 else if (Is64Bit && RegVT == MVT::i64)
1642 RC = X86::GR64RegisterClass;
1643 else if (RegVT == MVT::f32)
1644 RC = X86::FR32RegisterClass;
1645 else if (RegVT == MVT::f64)
1646 RC = X86::FR64RegisterClass;
1647 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1648 RC = X86::VR256RegisterClass;
1649 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1650 RC = X86::VR128RegisterClass;
1651 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1652 RC = X86::VR64RegisterClass;
1654 llvm_unreachable("Unknown argument type!");
1656 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1657 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1659 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1660 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1662 if (VA.getLocInfo() == CCValAssign::SExt)
1663 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1664 DAG.getValueType(VA.getValVT()));
1665 else if (VA.getLocInfo() == CCValAssign::ZExt)
1666 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1667 DAG.getValueType(VA.getValVT()));
1668 else if (VA.getLocInfo() == CCValAssign::BCvt)
1669 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1671 if (VA.isExtInLoc()) {
1672 // Handle MMX values passed in XMM regs.
1673 if (RegVT.isVector()) {
1674 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1675 ArgValue, DAG.getConstant(0, MVT::i64));
1676 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1678 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1681 assert(VA.isMemLoc());
1682 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1685 // If value is passed via pointer - do a load.
1686 if (VA.getLocInfo() == CCValAssign::Indirect)
1687 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1688 MachinePointerInfo(), false, false, 0);
1690 InVals.push_back(ArgValue);
1693 // The x86-64 ABI for returning structs by value requires that we copy
1694 // the sret argument into %rax for the return. Save the argument into
1695 // a virtual register so that we can access it from the return points.
1696 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1697 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1698 unsigned Reg = FuncInfo->getSRetReturnReg();
1700 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1701 FuncInfo->setSRetReturnReg(Reg);
1703 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1704 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1707 unsigned StackSize = CCInfo.getNextStackOffset();
1708 // Align stack specially for tail calls.
1709 if (FuncIsMadeTailCallSafe(CallConv))
1710 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1712 // If the function takes variable number of arguments, make a frame index for
1713 // the start of the first vararg value... for expansion of llvm.va_start.
1715 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1716 CallConv != CallingConv::X86_ThisCall)) {
1717 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1720 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1722 // FIXME: We should really autogenerate these arrays
1723 static const unsigned GPR64ArgRegsWin64[] = {
1724 X86::RCX, X86::RDX, X86::R8, X86::R9
1726 static const unsigned XMMArgRegsWin64[] = {
1727 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1729 static const unsigned GPR64ArgRegs64Bit[] = {
1730 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1732 static const unsigned XMMArgRegs64Bit[] = {
1733 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1734 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1736 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1739 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1740 GPR64ArgRegs = GPR64ArgRegsWin64;
1741 XMMArgRegs = XMMArgRegsWin64;
1743 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1744 GPR64ArgRegs = GPR64ArgRegs64Bit;
1745 XMMArgRegs = XMMArgRegs64Bit;
1747 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1749 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1752 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1753 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1754 "SSE register cannot be used when SSE is disabled!");
1755 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1756 "SSE register cannot be used when SSE is disabled!");
1757 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1758 // Kernel mode asks for SSE to be disabled, so don't push them
1760 TotalNumXMMRegs = 0;
1762 // For X86-64, if there are vararg parameters that are passed via
1763 // registers, then we must store them to their spots on the stack so they
1764 // may be loaded by deferencing the result of va_next.
1765 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1766 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1767 FuncInfo->setRegSaveFrameIndex(
1768 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1771 // Store the integer parameter registers.
1772 SmallVector<SDValue, 8> MemOps;
1773 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1775 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1776 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1777 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1778 DAG.getIntPtrConstant(Offset));
1779 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1780 X86::GR64RegisterClass);
1781 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1783 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1784 MachinePointerInfo::getFixedStack(
1785 FuncInfo->getRegSaveFrameIndex(), Offset),
1787 MemOps.push_back(Store);
1791 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1792 // Now store the XMM (fp + vector) parameter registers.
1793 SmallVector<SDValue, 11> SaveXMMOps;
1794 SaveXMMOps.push_back(Chain);
1796 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1797 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1798 SaveXMMOps.push_back(ALVal);
1800 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1801 FuncInfo->getRegSaveFrameIndex()));
1802 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1803 FuncInfo->getVarArgsFPOffset()));
1805 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1806 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1807 X86::VR128RegisterClass);
1808 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1809 SaveXMMOps.push_back(Val);
1811 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1813 &SaveXMMOps[0], SaveXMMOps.size()));
1816 if (!MemOps.empty())
1817 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1818 &MemOps[0], MemOps.size());
1822 // Some CCs need callee pop.
1823 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1824 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1826 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1827 // If this is an sret function, the return should pop the hidden pointer.
1828 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1829 FuncInfo->setBytesToPopOnReturn(4);
1833 // RegSaveFrameIndex is X86-64 only.
1834 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1835 if (CallConv == CallingConv::X86_FastCall ||
1836 CallConv == CallingConv::X86_ThisCall)
1837 // fastcc functions can't have varargs.
1838 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1845 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1846 SDValue StackPtr, SDValue Arg,
1847 DebugLoc dl, SelectionDAG &DAG,
1848 const CCValAssign &VA,
1849 ISD::ArgFlagsTy Flags) const {
1850 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1851 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1852 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1853 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1854 if (Flags.isByVal())
1855 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1857 return DAG.getStore(Chain, dl, Arg, PtrOff,
1858 MachinePointerInfo::getStack(LocMemOffset),
1862 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1863 /// optimization is performed and it is required.
1865 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1866 SDValue &OutRetAddr, SDValue Chain,
1867 bool IsTailCall, bool Is64Bit,
1868 int FPDiff, DebugLoc dl) const {
1869 // Adjust the Return address stack slot.
1870 EVT VT = getPointerTy();
1871 OutRetAddr = getReturnAddressFrameIndex(DAG);
1873 // Load the "old" Return address.
1874 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1876 return SDValue(OutRetAddr.getNode(), 1);
1879 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1880 /// optimization is performed and it is required (FPDiff!=0).
1882 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1883 SDValue Chain, SDValue RetAddrFrIdx,
1884 bool Is64Bit, int FPDiff, DebugLoc dl) {
1885 // Store the return address to the appropriate stack slot.
1886 if (!FPDiff) return Chain;
1887 // Calculate the new stack slot for the return address.
1888 int SlotSize = Is64Bit ? 8 : 4;
1889 int NewReturnAddrFI =
1890 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1891 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1892 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1893 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1894 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1900 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1901 CallingConv::ID CallConv, bool isVarArg,
1903 const SmallVectorImpl<ISD::OutputArg> &Outs,
1904 const SmallVectorImpl<SDValue> &OutVals,
1905 const SmallVectorImpl<ISD::InputArg> &Ins,
1906 DebugLoc dl, SelectionDAG &DAG,
1907 SmallVectorImpl<SDValue> &InVals) const {
1908 MachineFunction &MF = DAG.getMachineFunction();
1909 bool Is64Bit = Subtarget->is64Bit();
1910 bool IsStructRet = CallIsStructReturn(Outs);
1911 bool IsSibcall = false;
1914 // Check if it's really possible to do a tail call.
1915 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1916 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1917 Outs, OutVals, Ins, DAG);
1919 // Sibcalls are automatically detected tailcalls which do not require
1921 if (!GuaranteedTailCallOpt && isTailCall)
1928 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1929 "Var args not supported with calling convention fastcc or ghc");
1931 // Analyze operands of the call, assigning locations to each operand.
1932 SmallVector<CCValAssign, 16> ArgLocs;
1933 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1934 ArgLocs, *DAG.getContext());
1935 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1937 // Get a count of how many bytes are to be pushed on the stack.
1938 unsigned NumBytes = CCInfo.getNextStackOffset();
1940 // This is a sibcall. The memory operands are available in caller's
1941 // own caller's stack.
1943 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1944 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1947 if (isTailCall && !IsSibcall) {
1948 // Lower arguments at fp - stackoffset + fpdiff.
1949 unsigned NumBytesCallerPushed =
1950 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1951 FPDiff = NumBytesCallerPushed - NumBytes;
1953 // Set the delta of movement of the returnaddr stackslot.
1954 // But only set if delta is greater than previous delta.
1955 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1956 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1960 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1962 SDValue RetAddrFrIdx;
1963 // Load return adress for tail calls.
1964 if (isTailCall && FPDiff)
1965 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1966 Is64Bit, FPDiff, dl);
1968 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1969 SmallVector<SDValue, 8> MemOpChains;
1972 // Walk the register/memloc assignments, inserting copies/loads. In the case
1973 // of tail call optimization arguments are handle later.
1974 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1975 CCValAssign &VA = ArgLocs[i];
1976 EVT RegVT = VA.getLocVT();
1977 SDValue Arg = OutVals[i];
1978 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1979 bool isByVal = Flags.isByVal();
1981 // Promote the value if needed.
1982 switch (VA.getLocInfo()) {
1983 default: llvm_unreachable("Unknown loc info!");
1984 case CCValAssign::Full: break;
1985 case CCValAssign::SExt:
1986 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1988 case CCValAssign::ZExt:
1989 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1991 case CCValAssign::AExt:
1992 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1993 // Special case: passing MMX values in XMM registers.
1994 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1995 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1996 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1998 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2000 case CCValAssign::BCvt:
2001 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
2003 case CCValAssign::Indirect: {
2004 // Store the argument.
2005 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2006 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2007 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2008 MachinePointerInfo::getFixedStack(FI),
2015 if (VA.isRegLoc()) {
2016 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2017 if (isVarArg && Subtarget->isTargetWin64()) {
2018 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2019 // shadow reg if callee is a varargs function.
2020 unsigned ShadowReg = 0;
2021 switch (VA.getLocReg()) {
2022 case X86::XMM0: ShadowReg = X86::RCX; break;
2023 case X86::XMM1: ShadowReg = X86::RDX; break;
2024 case X86::XMM2: ShadowReg = X86::R8; break;
2025 case X86::XMM3: ShadowReg = X86::R9; break;
2028 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2030 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2031 assert(VA.isMemLoc());
2032 if (StackPtr.getNode() == 0)
2033 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2034 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2035 dl, DAG, VA, Flags));
2039 if (!MemOpChains.empty())
2040 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2041 &MemOpChains[0], MemOpChains.size());
2043 // Build a sequence of copy-to-reg nodes chained together with token chain
2044 // and flag operands which copy the outgoing args into registers.
2046 // Tail call byval lowering might overwrite argument registers so in case of
2047 // tail call optimization the copies to registers are lowered later.
2049 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2050 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2051 RegsToPass[i].second, InFlag);
2052 InFlag = Chain.getValue(1);
2055 if (Subtarget->isPICStyleGOT()) {
2056 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2059 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2060 DAG.getNode(X86ISD::GlobalBaseReg,
2061 DebugLoc(), getPointerTy()),
2063 InFlag = Chain.getValue(1);
2065 // If we are tail calling and generating PIC/GOT style code load the
2066 // address of the callee into ECX. The value in ecx is used as target of
2067 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2068 // for tail calls on PIC/GOT architectures. Normally we would just put the
2069 // address of GOT into ebx and then call target@PLT. But for tail calls
2070 // ebx would be restored (since ebx is callee saved) before jumping to the
2073 // Note: The actual moving to ECX is done further down.
2074 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2075 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2076 !G->getGlobal()->hasProtectedVisibility())
2077 Callee = LowerGlobalAddress(Callee, DAG);
2078 else if (isa<ExternalSymbolSDNode>(Callee))
2079 Callee = LowerExternalSymbol(Callee, DAG);
2083 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2084 // From AMD64 ABI document:
2085 // For calls that may call functions that use varargs or stdargs
2086 // (prototype-less calls or calls to functions containing ellipsis (...) in
2087 // the declaration) %al is used as hidden argument to specify the number
2088 // of SSE registers used. The contents of %al do not need to match exactly
2089 // the number of registers, but must be an ubound on the number of SSE
2090 // registers used and is in the range 0 - 8 inclusive.
2092 // Count the number of XMM registers allocated.
2093 static const unsigned XMMArgRegs[] = {
2094 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2095 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2097 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2098 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2099 && "SSE registers cannot be used when SSE is disabled");
2101 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2102 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2103 InFlag = Chain.getValue(1);
2107 // For tail calls lower the arguments to the 'real' stack slot.
2109 // Force all the incoming stack arguments to be loaded from the stack
2110 // before any new outgoing arguments are stored to the stack, because the
2111 // outgoing stack slots may alias the incoming argument stack slots, and
2112 // the alias isn't otherwise explicit. This is slightly more conservative
2113 // than necessary, because it means that each store effectively depends
2114 // on every argument instead of just those arguments it would clobber.
2115 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2117 SmallVector<SDValue, 8> MemOpChains2;
2120 // Do not flag preceeding copytoreg stuff together with the following stuff.
2122 if (GuaranteedTailCallOpt) {
2123 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2124 CCValAssign &VA = ArgLocs[i];
2127 assert(VA.isMemLoc());
2128 SDValue Arg = OutVals[i];
2129 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2130 // Create frame index.
2131 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2132 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2133 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2134 FIN = DAG.getFrameIndex(FI, getPointerTy());
2136 if (Flags.isByVal()) {
2137 // Copy relative to framepointer.
2138 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2139 if (StackPtr.getNode() == 0)
2140 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2142 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2144 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2148 // Store relative to framepointer.
2149 MemOpChains2.push_back(
2150 DAG.getStore(ArgChain, dl, Arg, FIN,
2151 MachinePointerInfo::getFixedStack(FI),
2157 if (!MemOpChains2.empty())
2158 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2159 &MemOpChains2[0], MemOpChains2.size());
2161 // Copy arguments to their registers.
2162 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2163 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2164 RegsToPass[i].second, InFlag);
2165 InFlag = Chain.getValue(1);
2169 // Store the return address to the appropriate stack slot.
2170 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2174 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2175 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2176 // In the 64-bit large code model, we have to make all calls
2177 // through a register, since the call instruction's 32-bit
2178 // pc-relative offset may not be large enough to hold the whole
2180 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2181 // If the callee is a GlobalAddress node (quite common, every direct call
2182 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2185 // We should use extra load for direct calls to dllimported functions in
2187 const GlobalValue *GV = G->getGlobal();
2188 if (!GV->hasDLLImportLinkage()) {
2189 unsigned char OpFlags = 0;
2191 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2192 // external symbols most go through the PLT in PIC mode. If the symbol
2193 // has hidden or protected visibility, or if it is static or local, then
2194 // we don't need to use the PLT - we can directly call it.
2195 if (Subtarget->isTargetELF() &&
2196 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2197 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2198 OpFlags = X86II::MO_PLT;
2199 } else if (Subtarget->isPICStyleStubAny() &&
2200 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2201 Subtarget->getDarwinVers() < 9) {
2202 // PC-relative references to external symbols should go through $stub,
2203 // unless we're building with the leopard linker or later, which
2204 // automatically synthesizes these stubs.
2205 OpFlags = X86II::MO_DARWIN_STUB;
2208 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2209 G->getOffset(), OpFlags);
2211 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2212 unsigned char OpFlags = 0;
2214 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
2215 // symbols should go through the PLT.
2216 if (Subtarget->isTargetELF() &&
2217 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2218 OpFlags = X86II::MO_PLT;
2219 } else if (Subtarget->isPICStyleStubAny() &&
2220 Subtarget->getDarwinVers() < 9) {
2221 // PC-relative references to external symbols should go through $stub,
2222 // unless we're building with the leopard linker or later, which
2223 // automatically synthesizes these stubs.
2224 OpFlags = X86II::MO_DARWIN_STUB;
2227 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2231 // Returns a chain & a flag for retval copy to use.
2232 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2233 SmallVector<SDValue, 8> Ops;
2235 if (!IsSibcall && isTailCall) {
2236 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2237 DAG.getIntPtrConstant(0, true), InFlag);
2238 InFlag = Chain.getValue(1);
2241 Ops.push_back(Chain);
2242 Ops.push_back(Callee);
2245 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2247 // Add argument registers to the end of the list so that they are known live
2249 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2250 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2251 RegsToPass[i].second.getValueType()));
2253 // Add an implicit use GOT pointer in EBX.
2254 if (!isTailCall && Subtarget->isPICStyleGOT())
2255 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2257 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2258 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2259 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2261 if (InFlag.getNode())
2262 Ops.push_back(InFlag);
2266 //// If this is the first return lowered for this function, add the regs
2267 //// to the liveout set for the function.
2268 // This isn't right, although it's probably harmless on x86; liveouts
2269 // should be computed from returns not tail calls. Consider a void
2270 // function making a tail call to a function returning int.
2271 return DAG.getNode(X86ISD::TC_RETURN, dl,
2272 NodeTys, &Ops[0], Ops.size());
2275 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2276 InFlag = Chain.getValue(1);
2278 // Create the CALLSEQ_END node.
2279 unsigned NumBytesForCalleeToPush;
2280 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2281 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2282 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2283 // If this is a call to a struct-return function, the callee
2284 // pops the hidden struct pointer, so we have to push it back.
2285 // This is common for Darwin/X86, Linux & Mingw32 targets.
2286 NumBytesForCalleeToPush = 4;
2288 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2290 // Returns a flag for retval copy to use.
2292 Chain = DAG.getCALLSEQ_END(Chain,
2293 DAG.getIntPtrConstant(NumBytes, true),
2294 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2297 InFlag = Chain.getValue(1);
2300 // Handle result values, copying them out of physregs into vregs that we
2302 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2303 Ins, dl, DAG, InVals);
2307 //===----------------------------------------------------------------------===//
2308 // Fast Calling Convention (tail call) implementation
2309 //===----------------------------------------------------------------------===//
2311 // Like std call, callee cleans arguments, convention except that ECX is
2312 // reserved for storing the tail called function address. Only 2 registers are
2313 // free for argument passing (inreg). Tail call optimization is performed
2315 // * tailcallopt is enabled
2316 // * caller/callee are fastcc
2317 // On X86_64 architecture with GOT-style position independent code only local
2318 // (within module) calls are supported at the moment.
2319 // To keep the stack aligned according to platform abi the function
2320 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2321 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2322 // If a tail called function callee has more arguments than the caller the
2323 // caller needs to make sure that there is room to move the RETADDR to. This is
2324 // achieved by reserving an area the size of the argument delta right after the
2325 // original REtADDR, but before the saved framepointer or the spilled registers
2326 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2338 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2339 /// for a 16 byte align requirement.
2341 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2342 SelectionDAG& DAG) const {
2343 MachineFunction &MF = DAG.getMachineFunction();
2344 const TargetMachine &TM = MF.getTarget();
2345 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2346 unsigned StackAlignment = TFI.getStackAlignment();
2347 uint64_t AlignMask = StackAlignment - 1;
2348 int64_t Offset = StackSize;
2349 uint64_t SlotSize = TD->getPointerSize();
2350 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2351 // Number smaller than 12 so just add the difference.
2352 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2354 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2355 Offset = ((~AlignMask) & Offset) + StackAlignment +
2356 (StackAlignment-SlotSize);
2361 /// MatchingStackOffset - Return true if the given stack call argument is
2362 /// already available in the same position (relatively) of the caller's
2363 /// incoming argument stack.
2365 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2366 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2367 const X86InstrInfo *TII) {
2368 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2370 if (Arg.getOpcode() == ISD::CopyFromReg) {
2371 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2372 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2374 MachineInstr *Def = MRI->getVRegDef(VR);
2377 if (!Flags.isByVal()) {
2378 if (!TII->isLoadFromStackSlot(Def, FI))
2381 unsigned Opcode = Def->getOpcode();
2382 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2383 Def->getOperand(1).isFI()) {
2384 FI = Def->getOperand(1).getIndex();
2385 Bytes = Flags.getByValSize();
2389 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2390 if (Flags.isByVal())
2391 // ByVal argument is passed in as a pointer but it's now being
2392 // dereferenced. e.g.
2393 // define @foo(%struct.X* %A) {
2394 // tail call @bar(%struct.X* byval %A)
2397 SDValue Ptr = Ld->getBasePtr();
2398 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2401 FI = FINode->getIndex();
2405 assert(FI != INT_MAX);
2406 if (!MFI->isFixedObjectIndex(FI))
2408 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2411 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2412 /// for tail call optimization. Targets which want to do tail call
2413 /// optimization should implement this function.
2415 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2416 CallingConv::ID CalleeCC,
2418 bool isCalleeStructRet,
2419 bool isCallerStructRet,
2420 const SmallVectorImpl<ISD::OutputArg> &Outs,
2421 const SmallVectorImpl<SDValue> &OutVals,
2422 const SmallVectorImpl<ISD::InputArg> &Ins,
2423 SelectionDAG& DAG) const {
2424 if (!IsTailCallConvention(CalleeCC) &&
2425 CalleeCC != CallingConv::C)
2428 // If -tailcallopt is specified, make fastcc functions tail-callable.
2429 const MachineFunction &MF = DAG.getMachineFunction();
2430 const Function *CallerF = DAG.getMachineFunction().getFunction();
2431 CallingConv::ID CallerCC = CallerF->getCallingConv();
2432 bool CCMatch = CallerCC == CalleeCC;
2434 if (GuaranteedTailCallOpt) {
2435 if (IsTailCallConvention(CalleeCC) && CCMatch)
2440 // Look for obvious safe cases to perform tail call optimization that do not
2441 // require ABI changes. This is what gcc calls sibcall.
2443 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2444 // emit a special epilogue.
2445 if (RegInfo->needsStackRealignment(MF))
2448 // Do not sibcall optimize vararg calls unless the call site is not passing
2450 if (isVarArg && !Outs.empty())
2453 // Also avoid sibcall optimization if either caller or callee uses struct
2454 // return semantics.
2455 if (isCalleeStructRet || isCallerStructRet)
2458 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2459 // Therefore if it's not used by the call it is not safe to optimize this into
2461 bool Unused = false;
2462 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2469 SmallVector<CCValAssign, 16> RVLocs;
2470 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2471 RVLocs, *DAG.getContext());
2472 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2473 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2474 CCValAssign &VA = RVLocs[i];
2475 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2480 // If the calling conventions do not match, then we'd better make sure the
2481 // results are returned in the same way as what the caller expects.
2483 SmallVector<CCValAssign, 16> RVLocs1;
2484 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2485 RVLocs1, *DAG.getContext());
2486 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2488 SmallVector<CCValAssign, 16> RVLocs2;
2489 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2490 RVLocs2, *DAG.getContext());
2491 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2493 if (RVLocs1.size() != RVLocs2.size())
2495 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2496 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2498 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2500 if (RVLocs1[i].isRegLoc()) {
2501 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2504 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2510 // If the callee takes no arguments then go on to check the results of the
2512 if (!Outs.empty()) {
2513 // Check if stack adjustment is needed. For now, do not do this if any
2514 // argument is passed on the stack.
2515 SmallVector<CCValAssign, 16> ArgLocs;
2516 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2517 ArgLocs, *DAG.getContext());
2518 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CalleeCC));
2519 if (CCInfo.getNextStackOffset()) {
2520 MachineFunction &MF = DAG.getMachineFunction();
2521 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2523 if (Subtarget->isTargetWin64())
2524 // Win64 ABI has additional complications.
2527 // Check if the arguments are already laid out in the right way as
2528 // the caller's fixed stack objects.
2529 MachineFrameInfo *MFI = MF.getFrameInfo();
2530 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2531 const X86InstrInfo *TII =
2532 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2533 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2534 CCValAssign &VA = ArgLocs[i];
2535 SDValue Arg = OutVals[i];
2536 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2537 if (VA.getLocInfo() == CCValAssign::Indirect)
2539 if (!VA.isRegLoc()) {
2540 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2547 // If the tailcall address may be in a register, then make sure it's
2548 // possible to register allocate for it. In 32-bit, the call address can
2549 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2550 // callee-saved registers are restored. These happen to be the same
2551 // registers used to pass 'inreg' arguments so watch out for those.
2552 if (!Subtarget->is64Bit() &&
2553 !isa<GlobalAddressSDNode>(Callee) &&
2554 !isa<ExternalSymbolSDNode>(Callee)) {
2555 unsigned NumInRegs = 0;
2556 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2557 CCValAssign &VA = ArgLocs[i];
2560 unsigned Reg = VA.getLocReg();
2563 case X86::EAX: case X86::EDX: case X86::ECX:
2564 if (++NumInRegs == 3)
2576 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2577 return X86::createFastISel(funcInfo);
2581 //===----------------------------------------------------------------------===//
2582 // Other Lowering Hooks
2583 //===----------------------------------------------------------------------===//
2585 static bool MayFoldLoad(SDValue Op) {
2586 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2589 static bool MayFoldIntoStore(SDValue Op) {
2590 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2593 static bool isTargetShuffle(unsigned Opcode) {
2595 default: return false;
2596 case X86ISD::PSHUFD:
2597 case X86ISD::PSHUFHW:
2598 case X86ISD::PSHUFLW:
2599 case X86ISD::SHUFPD:
2600 case X86ISD::PALIGN:
2601 case X86ISD::SHUFPS:
2602 case X86ISD::MOVLHPS:
2603 case X86ISD::MOVLHPD:
2604 case X86ISD::MOVHLPS:
2605 case X86ISD::MOVLPS:
2606 case X86ISD::MOVLPD:
2607 case X86ISD::MOVSHDUP:
2608 case X86ISD::MOVSLDUP:
2609 case X86ISD::MOVDDUP:
2612 case X86ISD::UNPCKLPS:
2613 case X86ISD::UNPCKLPD:
2614 case X86ISD::PUNPCKLWD:
2615 case X86ISD::PUNPCKLBW:
2616 case X86ISD::PUNPCKLDQ:
2617 case X86ISD::PUNPCKLQDQ:
2618 case X86ISD::UNPCKHPS:
2619 case X86ISD::UNPCKHPD:
2620 case X86ISD::PUNPCKHWD:
2621 case X86ISD::PUNPCKHBW:
2622 case X86ISD::PUNPCKHDQ:
2623 case X86ISD::PUNPCKHQDQ:
2629 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2630 SDValue V1, SelectionDAG &DAG) {
2632 default: llvm_unreachable("Unknown x86 shuffle node");
2633 case X86ISD::MOVSHDUP:
2634 case X86ISD::MOVSLDUP:
2635 case X86ISD::MOVDDUP:
2636 return DAG.getNode(Opc, dl, VT, V1);
2642 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2643 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2645 default: llvm_unreachable("Unknown x86 shuffle node");
2646 case X86ISD::PSHUFD:
2647 case X86ISD::PSHUFHW:
2648 case X86ISD::PSHUFLW:
2649 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2655 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2656 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2658 default: llvm_unreachable("Unknown x86 shuffle node");
2659 case X86ISD::PALIGN:
2660 case X86ISD::SHUFPD:
2661 case X86ISD::SHUFPS:
2662 return DAG.getNode(Opc, dl, VT, V1, V2,
2663 DAG.getConstant(TargetMask, MVT::i8));
2668 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2669 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2671 default: llvm_unreachable("Unknown x86 shuffle node");
2672 case X86ISD::MOVLHPS:
2673 case X86ISD::MOVLHPD:
2674 case X86ISD::MOVHLPS:
2675 case X86ISD::MOVLPS:
2676 case X86ISD::MOVLPD:
2679 case X86ISD::UNPCKLPS:
2680 case X86ISD::UNPCKLPD:
2681 case X86ISD::PUNPCKLWD:
2682 case X86ISD::PUNPCKLBW:
2683 case X86ISD::PUNPCKLDQ:
2684 case X86ISD::PUNPCKLQDQ:
2685 case X86ISD::UNPCKHPS:
2686 case X86ISD::UNPCKHPD:
2687 case X86ISD::PUNPCKHWD:
2688 case X86ISD::PUNPCKHBW:
2689 case X86ISD::PUNPCKHDQ:
2690 case X86ISD::PUNPCKHQDQ:
2691 return DAG.getNode(Opc, dl, VT, V1, V2);
2696 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2697 MachineFunction &MF = DAG.getMachineFunction();
2698 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2699 int ReturnAddrIndex = FuncInfo->getRAIndex();
2701 if (ReturnAddrIndex == 0) {
2702 // Set up a frame object for the return address.
2703 uint64_t SlotSize = TD->getPointerSize();
2704 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2706 FuncInfo->setRAIndex(ReturnAddrIndex);
2709 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2713 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2714 bool hasSymbolicDisplacement) {
2715 // Offset should fit into 32 bit immediate field.
2716 if (!isInt<32>(Offset))
2719 // If we don't have a symbolic displacement - we don't have any extra
2721 if (!hasSymbolicDisplacement)
2724 // FIXME: Some tweaks might be needed for medium code model.
2725 if (M != CodeModel::Small && M != CodeModel::Kernel)
2728 // For small code model we assume that latest object is 16MB before end of 31
2729 // bits boundary. We may also accept pretty large negative constants knowing
2730 // that all objects are in the positive half of address space.
2731 if (M == CodeModel::Small && Offset < 16*1024*1024)
2734 // For kernel code model we know that all object resist in the negative half
2735 // of 32bits address space. We may not accept negative offsets, since they may
2736 // be just off and we may accept pretty large positive ones.
2737 if (M == CodeModel::Kernel && Offset > 0)
2743 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2744 /// specific condition code, returning the condition code and the LHS/RHS of the
2745 /// comparison to make.
2746 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2747 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2749 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2750 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2751 // X > -1 -> X == 0, jump !sign.
2752 RHS = DAG.getConstant(0, RHS.getValueType());
2753 return X86::COND_NS;
2754 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2755 // X < 0 -> X == 0, jump on sign.
2757 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2759 RHS = DAG.getConstant(0, RHS.getValueType());
2760 return X86::COND_LE;
2764 switch (SetCCOpcode) {
2765 default: llvm_unreachable("Invalid integer condition!");
2766 case ISD::SETEQ: return X86::COND_E;
2767 case ISD::SETGT: return X86::COND_G;
2768 case ISD::SETGE: return X86::COND_GE;
2769 case ISD::SETLT: return X86::COND_L;
2770 case ISD::SETLE: return X86::COND_LE;
2771 case ISD::SETNE: return X86::COND_NE;
2772 case ISD::SETULT: return X86::COND_B;
2773 case ISD::SETUGT: return X86::COND_A;
2774 case ISD::SETULE: return X86::COND_BE;
2775 case ISD::SETUGE: return X86::COND_AE;
2779 // First determine if it is required or is profitable to flip the operands.
2781 // If LHS is a foldable load, but RHS is not, flip the condition.
2782 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2783 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2784 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2785 std::swap(LHS, RHS);
2788 switch (SetCCOpcode) {
2794 std::swap(LHS, RHS);
2798 // On a floating point condition, the flags are set as follows:
2800 // 0 | 0 | 0 | X > Y
2801 // 0 | 0 | 1 | X < Y
2802 // 1 | 0 | 0 | X == Y
2803 // 1 | 1 | 1 | unordered
2804 switch (SetCCOpcode) {
2805 default: llvm_unreachable("Condcode should be pre-legalized away");
2807 case ISD::SETEQ: return X86::COND_E;
2808 case ISD::SETOLT: // flipped
2810 case ISD::SETGT: return X86::COND_A;
2811 case ISD::SETOLE: // flipped
2813 case ISD::SETGE: return X86::COND_AE;
2814 case ISD::SETUGT: // flipped
2816 case ISD::SETLT: return X86::COND_B;
2817 case ISD::SETUGE: // flipped
2819 case ISD::SETLE: return X86::COND_BE;
2821 case ISD::SETNE: return X86::COND_NE;
2822 case ISD::SETUO: return X86::COND_P;
2823 case ISD::SETO: return X86::COND_NP;
2825 case ISD::SETUNE: return X86::COND_INVALID;
2829 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2830 /// code. Current x86 isa includes the following FP cmov instructions:
2831 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2832 static bool hasFPCMov(unsigned X86CC) {
2848 /// isFPImmLegal - Returns true if the target can instruction select the
2849 /// specified FP immediate natively. If false, the legalizer will
2850 /// materialize the FP immediate as a load from a constant pool.
2851 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2852 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2853 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2859 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2860 /// the specified range (L, H].
2861 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2862 return (Val < 0) || (Val >= Low && Val < Hi);
2865 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2866 /// specified value.
2867 static bool isUndefOrEqual(int Val, int CmpVal) {
2868 if (Val < 0 || Val == CmpVal)
2873 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2874 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2875 /// the second operand.
2876 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2877 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2878 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2879 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2880 return (Mask[0] < 2 && Mask[1] < 2);
2884 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2885 SmallVector<int, 8> M;
2887 return ::isPSHUFDMask(M, N->getValueType(0));
2890 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2891 /// is suitable for input to PSHUFHW.
2892 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2893 if (VT != MVT::v8i16)
2896 // Lower quadword copied in order or undef.
2897 for (int i = 0; i != 4; ++i)
2898 if (Mask[i] >= 0 && Mask[i] != i)
2901 // Upper quadword shuffled.
2902 for (int i = 4; i != 8; ++i)
2903 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2909 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2910 SmallVector<int, 8> M;
2912 return ::isPSHUFHWMask(M, N->getValueType(0));
2915 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2916 /// is suitable for input to PSHUFLW.
2917 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2918 if (VT != MVT::v8i16)
2921 // Upper quadword copied in order.
2922 for (int i = 4; i != 8; ++i)
2923 if (Mask[i] >= 0 && Mask[i] != i)
2926 // Lower quadword shuffled.
2927 for (int i = 0; i != 4; ++i)
2934 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2935 SmallVector<int, 8> M;
2937 return ::isPSHUFLWMask(M, N->getValueType(0));
2940 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2941 /// is suitable for input to PALIGNR.
2942 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2944 int i, e = VT.getVectorNumElements();
2946 // Do not handle v2i64 / v2f64 shuffles with palignr.
2947 if (e < 4 || !hasSSSE3)
2950 for (i = 0; i != e; ++i)
2954 // All undef, not a palignr.
2958 // Determine if it's ok to perform a palignr with only the LHS, since we
2959 // don't have access to the actual shuffle elements to see if RHS is undef.
2960 bool Unary = Mask[i] < (int)e;
2961 bool NeedsUnary = false;
2963 int s = Mask[i] - i;
2965 // Check the rest of the elements to see if they are consecutive.
2966 for (++i; i != e; ++i) {
2971 Unary = Unary && (m < (int)e);
2972 NeedsUnary = NeedsUnary || (m < s);
2974 if (NeedsUnary && !Unary)
2976 if (Unary && m != ((s+i) & (e-1)))
2978 if (!Unary && m != (s+i))
2984 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2985 SmallVector<int, 8> M;
2987 return ::isPALIGNRMask(M, N->getValueType(0), true);
2990 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2991 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2992 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2993 int NumElems = VT.getVectorNumElements();
2994 if (NumElems != 2 && NumElems != 4)
2997 int Half = NumElems / 2;
2998 for (int i = 0; i < Half; ++i)
2999 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3001 for (int i = Half; i < NumElems; ++i)
3002 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3008 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3009 SmallVector<int, 8> M;
3011 return ::isSHUFPMask(M, N->getValueType(0));
3014 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3015 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3016 /// half elements to come from vector 1 (which would equal the dest.) and
3017 /// the upper half to come from vector 2.
3018 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3019 int NumElems = VT.getVectorNumElements();
3021 if (NumElems != 2 && NumElems != 4)
3024 int Half = NumElems / 2;
3025 for (int i = 0; i < Half; ++i)
3026 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3028 for (int i = Half; i < NumElems; ++i)
3029 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3034 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3035 SmallVector<int, 8> M;
3037 return isCommutedSHUFPMask(M, N->getValueType(0));
3040 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3041 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3042 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3043 if (N->getValueType(0).getVectorNumElements() != 4)
3046 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3047 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3048 isUndefOrEqual(N->getMaskElt(1), 7) &&
3049 isUndefOrEqual(N->getMaskElt(2), 2) &&
3050 isUndefOrEqual(N->getMaskElt(3), 3);
3053 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3054 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3056 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3057 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3062 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3063 isUndefOrEqual(N->getMaskElt(1), 3) &&
3064 isUndefOrEqual(N->getMaskElt(2), 2) &&
3065 isUndefOrEqual(N->getMaskElt(3), 3);
3068 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3069 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3070 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3071 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3073 if (NumElems != 2 && NumElems != 4)
3076 for (unsigned i = 0; i < NumElems/2; ++i)
3077 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3080 for (unsigned i = NumElems/2; i < NumElems; ++i)
3081 if (!isUndefOrEqual(N->getMaskElt(i), i))
3087 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3088 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3089 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3090 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3092 if (NumElems != 2 && NumElems != 4)
3095 for (unsigned i = 0; i < NumElems/2; ++i)
3096 if (!isUndefOrEqual(N->getMaskElt(i), i))
3099 for (unsigned i = 0; i < NumElems/2; ++i)
3100 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3106 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3107 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3108 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3109 bool V2IsSplat = false) {
3110 int NumElts = VT.getVectorNumElements();
3111 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3114 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3116 int BitI1 = Mask[i+1];
3117 if (!isUndefOrEqual(BitI, j))
3120 if (!isUndefOrEqual(BitI1, NumElts))
3123 if (!isUndefOrEqual(BitI1, j + NumElts))
3130 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3131 SmallVector<int, 8> M;
3133 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3136 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3137 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3138 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3139 bool V2IsSplat = false) {
3140 int NumElts = VT.getVectorNumElements();
3141 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3144 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3146 int BitI1 = Mask[i+1];
3147 if (!isUndefOrEqual(BitI, j + NumElts/2))
3150 if (isUndefOrEqual(BitI1, NumElts))
3153 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3160 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3161 SmallVector<int, 8> M;
3163 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3166 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3167 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3169 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3170 int NumElems = VT.getVectorNumElements();
3171 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3174 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3176 int BitI1 = Mask[i+1];
3177 if (!isUndefOrEqual(BitI, j))
3179 if (!isUndefOrEqual(BitI1, j))
3185 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3186 SmallVector<int, 8> M;
3188 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3191 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3192 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3194 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3195 int NumElems = VT.getVectorNumElements();
3196 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3199 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3201 int BitI1 = Mask[i+1];
3202 if (!isUndefOrEqual(BitI, j))
3204 if (!isUndefOrEqual(BitI1, j))
3210 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3211 SmallVector<int, 8> M;
3213 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3216 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3217 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3218 /// MOVSD, and MOVD, i.e. setting the lowest element.
3219 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3220 if (VT.getVectorElementType().getSizeInBits() < 32)
3223 int NumElts = VT.getVectorNumElements();
3225 if (!isUndefOrEqual(Mask[0], NumElts))
3228 for (int i = 1; i < NumElts; ++i)
3229 if (!isUndefOrEqual(Mask[i], i))
3235 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3236 SmallVector<int, 8> M;
3238 return ::isMOVLMask(M, N->getValueType(0));
3241 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3242 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3243 /// element of vector 2 and the other elements to come from vector 1 in order.
3244 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3245 bool V2IsSplat = false, bool V2IsUndef = false) {
3246 int NumOps = VT.getVectorNumElements();
3247 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3250 if (!isUndefOrEqual(Mask[0], 0))
3253 for (int i = 1; i < NumOps; ++i)
3254 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3255 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3256 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3262 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3263 bool V2IsUndef = false) {
3264 SmallVector<int, 8> M;
3266 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3269 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3270 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3271 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3272 if (N->getValueType(0).getVectorNumElements() != 4)
3275 // Expect 1, 1, 3, 3
3276 for (unsigned i = 0; i < 2; ++i) {
3277 int Elt = N->getMaskElt(i);
3278 if (Elt >= 0 && Elt != 1)
3283 for (unsigned i = 2; i < 4; ++i) {
3284 int Elt = N->getMaskElt(i);
3285 if (Elt >= 0 && Elt != 3)
3290 // Don't use movshdup if it can be done with a shufps.
3291 // FIXME: verify that matching u, u, 3, 3 is what we want.
3295 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3296 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3297 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3298 if (N->getValueType(0).getVectorNumElements() != 4)
3301 // Expect 0, 0, 2, 2
3302 for (unsigned i = 0; i < 2; ++i)
3303 if (N->getMaskElt(i) > 0)
3307 for (unsigned i = 2; i < 4; ++i) {
3308 int Elt = N->getMaskElt(i);
3309 if (Elt >= 0 && Elt != 2)
3314 // Don't use movsldup if it can be done with a shufps.
3318 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3319 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3320 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3321 int e = N->getValueType(0).getVectorNumElements() / 2;
3323 for (int i = 0; i < e; ++i)
3324 if (!isUndefOrEqual(N->getMaskElt(i), i))
3326 for (int i = 0; i < e; ++i)
3327 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3332 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3333 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3334 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3336 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3338 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3340 for (int i = 0; i < NumOperands; ++i) {
3341 int Val = SVOp->getMaskElt(NumOperands-i-1);
3342 if (Val < 0) Val = 0;
3343 if (Val >= NumOperands) Val -= NumOperands;
3345 if (i != NumOperands - 1)
3351 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3352 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3353 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3356 // 8 nodes, but we only care about the last 4.
3357 for (unsigned i = 7; i >= 4; --i) {
3358 int Val = SVOp->getMaskElt(i);
3367 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3368 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3369 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3372 // 8 nodes, but we only care about the first 4.
3373 for (int i = 3; i >= 0; --i) {
3374 int Val = SVOp->getMaskElt(i);
3383 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3384 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3385 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3386 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3387 EVT VVT = N->getValueType(0);
3388 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3392 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3393 Val = SVOp->getMaskElt(i);
3397 return (Val - i) * EltSize;
3400 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3402 bool X86::isZeroNode(SDValue Elt) {
3403 return ((isa<ConstantSDNode>(Elt) &&
3404 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3405 (isa<ConstantFPSDNode>(Elt) &&
3406 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3409 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3410 /// their permute mask.
3411 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3412 SelectionDAG &DAG) {
3413 EVT VT = SVOp->getValueType(0);
3414 unsigned NumElems = VT.getVectorNumElements();
3415 SmallVector<int, 8> MaskVec;
3417 for (unsigned i = 0; i != NumElems; ++i) {
3418 int idx = SVOp->getMaskElt(i);
3420 MaskVec.push_back(idx);
3421 else if (idx < (int)NumElems)
3422 MaskVec.push_back(idx + NumElems);
3424 MaskVec.push_back(idx - NumElems);
3426 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3427 SVOp->getOperand(0), &MaskVec[0]);
3430 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3431 /// the two vector operands have swapped position.
3432 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3433 unsigned NumElems = VT.getVectorNumElements();
3434 for (unsigned i = 0; i != NumElems; ++i) {
3438 else if (idx < (int)NumElems)
3439 Mask[i] = idx + NumElems;
3441 Mask[i] = idx - NumElems;
3445 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3446 /// match movhlps. The lower half elements should come from upper half of
3447 /// V1 (and in order), and the upper half elements should come from the upper
3448 /// half of V2 (and in order).
3449 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3450 if (Op->getValueType(0).getVectorNumElements() != 4)
3452 for (unsigned i = 0, e = 2; i != e; ++i)
3453 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3455 for (unsigned i = 2; i != 4; ++i)
3456 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3461 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3462 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3464 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3465 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3467 N = N->getOperand(0).getNode();
3468 if (!ISD::isNON_EXTLoad(N))
3471 *LD = cast<LoadSDNode>(N);
3475 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3476 /// match movlp{s|d}. The lower half elements should come from lower half of
3477 /// V1 (and in order), and the upper half elements should come from the upper
3478 /// half of V2 (and in order). And since V1 will become the source of the
3479 /// MOVLP, it must be either a vector load or a scalar load to vector.
3480 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3481 ShuffleVectorSDNode *Op) {
3482 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3484 // Is V2 is a vector load, don't do this transformation. We will try to use
3485 // load folding shufps op.
3486 if (ISD::isNON_EXTLoad(V2))
3489 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3491 if (NumElems != 2 && NumElems != 4)
3493 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3494 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3496 for (unsigned i = NumElems/2; i != NumElems; ++i)
3497 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3502 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3504 static bool isSplatVector(SDNode *N) {
3505 if (N->getOpcode() != ISD::BUILD_VECTOR)
3508 SDValue SplatValue = N->getOperand(0);
3509 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3510 if (N->getOperand(i) != SplatValue)
3515 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3516 /// to an zero vector.
3517 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3518 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3519 SDValue V1 = N->getOperand(0);
3520 SDValue V2 = N->getOperand(1);
3521 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3522 for (unsigned i = 0; i != NumElems; ++i) {
3523 int Idx = N->getMaskElt(i);
3524 if (Idx >= (int)NumElems) {
3525 unsigned Opc = V2.getOpcode();
3526 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3528 if (Opc != ISD::BUILD_VECTOR ||
3529 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3531 } else if (Idx >= 0) {
3532 unsigned Opc = V1.getOpcode();
3533 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3535 if (Opc != ISD::BUILD_VECTOR ||
3536 !X86::isZeroNode(V1.getOperand(Idx)))
3543 /// getZeroVector - Returns a vector of specified type with all zero elements.
3545 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3547 assert(VT.isVector() && "Expected a vector type");
3549 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted
3550 // to their dest type. This ensures they get CSE'd.
3552 if (VT.getSizeInBits() == 64) { // MMX
3553 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3554 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3555 } else if (VT.getSizeInBits() == 128) {
3556 if (HasSSE2) { // SSE2
3557 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3558 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3560 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3561 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3563 } else if (VT.getSizeInBits() == 256) { // AVX
3564 // 256-bit logic and arithmetic instructions in AVX are
3565 // all floating-point, no support for integer ops. Default
3566 // to emitting fp zeroed vectors then.
3567 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3568 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3569 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3571 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3574 /// getOnesVector - Returns a vector of specified type with all bits set.
3576 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3577 assert(VT.isVector() && "Expected a vector type");
3579 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3580 // type. This ensures they get CSE'd.
3581 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3583 if (VT.getSizeInBits() == 64) // MMX
3584 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
3586 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3587 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
3591 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3592 /// that point to V2 points to its first element.
3593 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3594 EVT VT = SVOp->getValueType(0);
3595 unsigned NumElems = VT.getVectorNumElements();
3597 bool Changed = false;
3598 SmallVector<int, 8> MaskVec;
3599 SVOp->getMask(MaskVec);
3601 for (unsigned i = 0; i != NumElems; ++i) {
3602 if (MaskVec[i] > (int)NumElems) {
3603 MaskVec[i] = NumElems;
3608 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3609 SVOp->getOperand(1), &MaskVec[0]);
3610 return SDValue(SVOp, 0);
3613 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3614 /// operation of specified width.
3615 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3617 unsigned NumElems = VT.getVectorNumElements();
3618 SmallVector<int, 8> Mask;
3619 Mask.push_back(NumElems);
3620 for (unsigned i = 1; i != NumElems; ++i)
3622 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3625 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3626 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3628 unsigned NumElems = VT.getVectorNumElements();
3629 SmallVector<int, 8> Mask;
3630 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3632 Mask.push_back(i + NumElems);
3634 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3637 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3638 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3640 unsigned NumElems = VT.getVectorNumElements();
3641 unsigned Half = NumElems/2;
3642 SmallVector<int, 8> Mask;
3643 for (unsigned i = 0; i != Half; ++i) {
3644 Mask.push_back(i + Half);
3645 Mask.push_back(i + NumElems + Half);
3647 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3650 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3651 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3652 EVT PVT = MVT::v4f32;
3653 EVT VT = SV->getValueType(0);
3654 DebugLoc dl = SV->getDebugLoc();
3655 SDValue V1 = SV->getOperand(0);
3656 int NumElems = VT.getVectorNumElements();
3657 int EltNo = SV->getSplatIndex();
3659 // unpack elements to the correct location
3660 while (NumElems > 4) {
3661 if (EltNo < NumElems/2) {
3662 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3664 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3665 EltNo -= NumElems/2;
3670 // Perform the splat.
3671 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3672 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3673 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3674 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3677 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3678 /// vector of zero or undef vector. This produces a shuffle where the low
3679 /// element of V2 is swizzled into the zero/undef vector, landing at element
3680 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3681 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3682 bool isZero, bool HasSSE2,
3683 SelectionDAG &DAG) {
3684 EVT VT = V2.getValueType();
3686 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3687 unsigned NumElems = VT.getVectorNumElements();
3688 SmallVector<int, 16> MaskVec;
3689 for (unsigned i = 0; i != NumElems; ++i)
3690 // If this is the insertion idx, put the low elt of V2 here.
3691 MaskVec.push_back(i == Idx ? NumElems : i);
3692 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3695 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3696 /// element of the result of the vector shuffle.
3697 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3700 return SDValue(); // Limit search depth.
3702 SDValue V = SDValue(N, 0);
3703 EVT VT = V.getValueType();
3704 unsigned Opcode = V.getOpcode();
3706 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3707 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3708 Index = SV->getMaskElt(Index);
3711 return DAG.getUNDEF(VT.getVectorElementType());
3713 int NumElems = VT.getVectorNumElements();
3714 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3715 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3718 // Recurse into target specific vector shuffles to find scalars.
3719 if (isTargetShuffle(Opcode)) {
3720 int NumElems = VT.getVectorNumElements();
3721 SmallVector<unsigned, 16> ShuffleMask;
3725 case X86ISD::SHUFPS:
3726 case X86ISD::SHUFPD:
3727 ImmN = N->getOperand(N->getNumOperands()-1);
3728 DecodeSHUFPSMask(NumElems,
3729 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3732 case X86ISD::PUNPCKHBW:
3733 case X86ISD::PUNPCKHWD:
3734 case X86ISD::PUNPCKHDQ:
3735 case X86ISD::PUNPCKHQDQ:
3736 DecodePUNPCKHMask(NumElems, ShuffleMask);
3738 case X86ISD::UNPCKHPS:
3739 case X86ISD::UNPCKHPD:
3740 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3742 case X86ISD::PUNPCKLBW:
3743 case X86ISD::PUNPCKLWD:
3744 case X86ISD::PUNPCKLDQ:
3745 case X86ISD::PUNPCKLQDQ:
3746 DecodePUNPCKLMask(NumElems, ShuffleMask);
3748 case X86ISD::UNPCKLPS:
3749 case X86ISD::UNPCKLPD:
3750 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3752 case X86ISD::MOVHLPS:
3753 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3755 case X86ISD::MOVLHPS:
3756 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3758 case X86ISD::PSHUFD:
3759 ImmN = N->getOperand(N->getNumOperands()-1);
3760 DecodePSHUFMask(NumElems,
3761 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3764 case X86ISD::PSHUFHW:
3765 ImmN = N->getOperand(N->getNumOperands()-1);
3766 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3769 case X86ISD::PSHUFLW:
3770 ImmN = N->getOperand(N->getNumOperands()-1);
3771 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3775 case X86ISD::MOVSD: {
3776 // The index 0 always comes from the first element of the second source,
3777 // this is why MOVSS and MOVSD are used in the first place. The other
3778 // elements come from the other positions of the first source vector.
3779 unsigned OpNum = (Index == 0) ? 1 : 0;
3780 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3784 assert("not implemented for target shuffle node");
3788 Index = ShuffleMask[Index];
3790 return DAG.getUNDEF(VT.getVectorElementType());
3792 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3793 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3797 // Actual nodes that may contain scalar elements
3798 if (Opcode == ISD::BIT_CONVERT) {
3799 V = V.getOperand(0);
3800 EVT SrcVT = V.getValueType();
3801 unsigned NumElems = VT.getVectorNumElements();
3803 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3807 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3808 return (Index == 0) ? V.getOperand(0)
3809 : DAG.getUNDEF(VT.getVectorElementType());
3811 if (V.getOpcode() == ISD::BUILD_VECTOR)
3812 return V.getOperand(Index);
3817 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3818 /// shuffle operation which come from a consecutively from a zero. The
3819 /// search can start in two diferent directions, from left or right.
3821 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3822 bool ZerosFromLeft, SelectionDAG &DAG) {
3825 while (i < NumElems) {
3826 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3827 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3828 if (!(Elt.getNode() &&
3829 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3837 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3838 /// MaskE correspond consecutively to elements from one of the vector operands,
3839 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3841 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3842 int OpIdx, int NumElems, unsigned &OpNum) {
3843 bool SeenV1 = false;
3844 bool SeenV2 = false;
3846 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3847 int Idx = SVOp->getMaskElt(i);
3848 // Ignore undef indicies
3857 // Only accept consecutive elements from the same vector
3858 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3862 OpNum = SeenV1 ? 0 : 1;
3866 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3867 /// logical left shift of a vector.
3868 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3869 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3870 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3871 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3872 false /* check zeros from right */, DAG);
3878 // Considering the elements in the mask that are not consecutive zeros,
3879 // check if they consecutively come from only one of the source vectors.
3881 // V1 = {X, A, B, C} 0
3883 // vector_shuffle V1, V2 <1, 2, 3, X>
3885 if (!isShuffleMaskConsecutive(SVOp,
3886 0, // Mask Start Index
3887 NumElems-NumZeros-1, // Mask End Index
3888 NumZeros, // Where to start looking in the src vector
3889 NumElems, // Number of elements in vector
3890 OpSrc)) // Which source operand ?
3895 ShVal = SVOp->getOperand(OpSrc);
3899 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3900 /// logical left shift of a vector.
3901 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3902 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3903 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3904 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3905 true /* check zeros from left */, DAG);
3911 // Considering the elements in the mask that are not consecutive zeros,
3912 // check if they consecutively come from only one of the source vectors.
3914 // 0 { A, B, X, X } = V2
3916 // vector_shuffle V1, V2 <X, X, 4, 5>
3918 if (!isShuffleMaskConsecutive(SVOp,
3919 NumZeros, // Mask Start Index
3920 NumElems-1, // Mask End Index
3921 0, // Where to start looking in the src vector
3922 NumElems, // Number of elements in vector
3923 OpSrc)) // Which source operand ?
3928 ShVal = SVOp->getOperand(OpSrc);
3932 /// isVectorShift - Returns true if the shuffle can be implemented as a
3933 /// logical left or right shift of a vector.
3934 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3935 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3936 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3937 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3943 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3945 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3946 unsigned NumNonZero, unsigned NumZero,
3948 const TargetLowering &TLI) {
3952 DebugLoc dl = Op.getDebugLoc();
3955 for (unsigned i = 0; i < 16; ++i) {
3956 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3957 if (ThisIsNonZero && First) {
3959 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3961 V = DAG.getUNDEF(MVT::v8i16);
3966 SDValue ThisElt(0, 0), LastElt(0, 0);
3967 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3968 if (LastIsNonZero) {
3969 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3970 MVT::i16, Op.getOperand(i-1));
3972 if (ThisIsNonZero) {
3973 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3974 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3975 ThisElt, DAG.getConstant(8, MVT::i8));
3977 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3981 if (ThisElt.getNode())
3982 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3983 DAG.getIntPtrConstant(i/2));
3987 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3990 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3992 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3993 unsigned NumNonZero, unsigned NumZero,
3995 const TargetLowering &TLI) {
3999 DebugLoc dl = Op.getDebugLoc();
4002 for (unsigned i = 0; i < 8; ++i) {
4003 bool isNonZero = (NonZeros & (1 << i)) != 0;
4007 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4009 V = DAG.getUNDEF(MVT::v8i16);
4012 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4013 MVT::v8i16, V, Op.getOperand(i),
4014 DAG.getIntPtrConstant(i));
4021 /// getVShift - Return a vector logical shift node.
4023 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4024 unsigned NumBits, SelectionDAG &DAG,
4025 const TargetLowering &TLI, DebugLoc dl) {
4026 bool isMMX = VT.getSizeInBits() == 64;
4027 EVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
4028 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4029 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
4030 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4031 DAG.getNode(Opc, dl, ShVT, SrcOp,
4032 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
4036 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4037 SelectionDAG &DAG) const {
4039 // Check if the scalar load can be widened into a vector load. And if
4040 // the address is "base + cst" see if the cst can be "absorbed" into
4041 // the shuffle mask.
4042 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4043 SDValue Ptr = LD->getBasePtr();
4044 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4046 EVT PVT = LD->getValueType(0);
4047 if (PVT != MVT::i32 && PVT != MVT::f32)
4052 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4053 FI = FINode->getIndex();
4055 } else if (Ptr.getOpcode() == ISD::ADD &&
4056 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4057 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4058 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4059 Offset = Ptr.getConstantOperandVal(1);
4060 Ptr = Ptr.getOperand(0);
4065 SDValue Chain = LD->getChain();
4066 // Make sure the stack object alignment is at least 16.
4067 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4068 if (DAG.InferPtrAlignment(Ptr) < 16) {
4069 if (MFI->isFixedObjectIndex(FI)) {
4070 // Can't change the alignment. FIXME: It's possible to compute
4071 // the exact stack offset and reference FI + adjust offset instead.
4072 // If someone *really* cares about this. That's the way to implement it.
4075 MFI->setObjectAlignment(FI, 16);
4079 // (Offset % 16) must be multiple of 4. Then address is then
4080 // Ptr + (Offset & ~15).
4083 if ((Offset % 16) & 3)
4085 int64_t StartOffset = Offset & ~15;
4087 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4088 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4090 int EltNo = (Offset - StartOffset) >> 2;
4091 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4092 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4093 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4094 LD->getPointerInfo().getWithOffset(StartOffset),
4096 // Canonicalize it to a v4i32 shuffle.
4097 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, V1);
4098 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4099 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4100 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4106 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4107 /// vector of type 'VT', see if the elements can be replaced by a single large
4108 /// load which has the same value as a build_vector whose operands are 'elts'.
4110 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4112 /// FIXME: we'd also like to handle the case where the last elements are zero
4113 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4114 /// There's even a handy isZeroNode for that purpose.
4115 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4116 DebugLoc &DL, SelectionDAG &DAG) {
4117 EVT EltVT = VT.getVectorElementType();
4118 unsigned NumElems = Elts.size();
4120 LoadSDNode *LDBase = NULL;
4121 unsigned LastLoadedElt = -1U;
4123 // For each element in the initializer, see if we've found a load or an undef.
4124 // If we don't find an initial load element, or later load elements are
4125 // non-consecutive, bail out.
4126 for (unsigned i = 0; i < NumElems; ++i) {
4127 SDValue Elt = Elts[i];
4129 if (!Elt.getNode() ||
4130 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4133 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4135 LDBase = cast<LoadSDNode>(Elt.getNode());
4139 if (Elt.getOpcode() == ISD::UNDEF)
4142 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4143 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4148 // If we have found an entire vector of loads and undefs, then return a large
4149 // load of the entire vector width starting at the base pointer. If we found
4150 // consecutive loads for the low half, generate a vzext_load node.
4151 if (LastLoadedElt == NumElems - 1) {
4152 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4153 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4154 LDBase->getPointerInfo(),
4155 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4156 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4157 LDBase->getPointerInfo(),
4158 LDBase->isVolatile(), LDBase->isNonTemporal(),
4159 LDBase->getAlignment());
4160 } else if (NumElems == 4 && LastLoadedElt == 1) {
4161 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4162 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4163 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4165 LDBase->getMemOperand());
4166 return DAG.getNode(ISD::BIT_CONVERT, DL, VT, ResNode);
4172 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4173 DebugLoc dl = Op.getDebugLoc();
4174 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4175 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4176 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4177 // is present, so AllOnes is ignored.
4178 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4179 (Op.getValueType().getSizeInBits() != 256 &&
4180 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4181 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
4182 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4183 // eliminated on x86-32 hosts.
4184 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
4187 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4188 return getOnesVector(Op.getValueType(), DAG, dl);
4189 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4192 EVT VT = Op.getValueType();
4193 EVT ExtVT = VT.getVectorElementType();
4194 unsigned EVTBits = ExtVT.getSizeInBits();
4196 unsigned NumElems = Op.getNumOperands();
4197 unsigned NumZero = 0;
4198 unsigned NumNonZero = 0;
4199 unsigned NonZeros = 0;
4200 bool IsAllConstants = true;
4201 SmallSet<SDValue, 8> Values;
4202 for (unsigned i = 0; i < NumElems; ++i) {
4203 SDValue Elt = Op.getOperand(i);
4204 if (Elt.getOpcode() == ISD::UNDEF)
4207 if (Elt.getOpcode() != ISD::Constant &&
4208 Elt.getOpcode() != ISD::ConstantFP)
4209 IsAllConstants = false;
4210 if (X86::isZeroNode(Elt))
4213 NonZeros |= (1 << i);
4218 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4219 if (NumNonZero == 0)
4220 return DAG.getUNDEF(VT);
4222 // Special case for single non-zero, non-undef, element.
4223 if (NumNonZero == 1) {
4224 unsigned Idx = CountTrailingZeros_32(NonZeros);
4225 SDValue Item = Op.getOperand(Idx);
4227 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4228 // the value are obviously zero, truncate the value to i32 and do the
4229 // insertion that way. Only do this if the value is non-constant or if the
4230 // value is a constant being inserted into element 0. It is cheaper to do
4231 // a constant pool load than it is to do a movd + shuffle.
4232 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4233 (!IsAllConstants || Idx == 0)) {
4234 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4235 // Handle MMX and SSE both.
4236 EVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
4237 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
4239 // Truncate the value (which may itself be a constant) to i32, and
4240 // convert it to a vector with movd (S2V+shuffle to zero extend).
4241 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4242 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4243 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4244 Subtarget->hasSSE2(), DAG);
4246 // Now we have our 32-bit value zero extended in the low element of
4247 // a vector. If Idx != 0, swizzle it into place.
4249 SmallVector<int, 4> Mask;
4250 Mask.push_back(Idx);
4251 for (unsigned i = 1; i != VecElts; ++i)
4253 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4254 DAG.getUNDEF(Item.getValueType()),
4257 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
4261 // If we have a constant or non-constant insertion into the low element of
4262 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4263 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4264 // depending on what the source datatype is.
4267 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4268 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4269 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4270 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4271 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4272 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4274 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4275 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4276 EVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
4277 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4278 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4279 Subtarget->hasSSE2(), DAG);
4280 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
4284 // Is it a vector logical left shift?
4285 if (NumElems == 2 && Idx == 1 &&
4286 X86::isZeroNode(Op.getOperand(0)) &&
4287 !X86::isZeroNode(Op.getOperand(1))) {
4288 unsigned NumBits = VT.getSizeInBits();
4289 return getVShift(true, VT,
4290 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4291 VT, Op.getOperand(1)),
4292 NumBits/2, DAG, *this, dl);
4295 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4298 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4299 // is a non-constant being inserted into an element other than the low one,
4300 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4301 // movd/movss) to move this into the low element, then shuffle it into
4303 if (EVTBits == 32) {
4304 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4306 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4307 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4308 Subtarget->hasSSE2(), DAG);
4309 SmallVector<int, 8> MaskVec;
4310 for (unsigned i = 0; i < NumElems; i++)
4311 MaskVec.push_back(i == Idx ? 0 : 1);
4312 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4316 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4317 if (Values.size() == 1) {
4318 if (EVTBits == 32) {
4319 // Instead of a shuffle like this:
4320 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4321 // Check if it's possible to issue this instead.
4322 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4323 unsigned Idx = CountTrailingZeros_32(NonZeros);
4324 SDValue Item = Op.getOperand(Idx);
4325 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4326 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4331 // A vector full of immediates; various special cases are already
4332 // handled, so this is best done with a single constant-pool load.
4336 // Let legalizer expand 2-wide build_vectors.
4337 if (EVTBits == 64) {
4338 if (NumNonZero == 1) {
4339 // One half is zero or undef.
4340 unsigned Idx = CountTrailingZeros_32(NonZeros);
4341 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4342 Op.getOperand(Idx));
4343 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4344 Subtarget->hasSSE2(), DAG);
4349 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4350 if (EVTBits == 8 && NumElems == 16) {
4351 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4353 if (V.getNode()) return V;
4356 if (EVTBits == 16 && NumElems == 8) {
4357 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4359 if (V.getNode()) return V;
4362 // If element VT is == 32 bits, turn it into a number of shuffles.
4363 SmallVector<SDValue, 8> V;
4365 if (NumElems == 4 && NumZero > 0) {
4366 for (unsigned i = 0; i < 4; ++i) {
4367 bool isZero = !(NonZeros & (1 << i));
4369 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4371 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4374 for (unsigned i = 0; i < 2; ++i) {
4375 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4378 V[i] = V[i*2]; // Must be a zero vector.
4381 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4384 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4387 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4392 SmallVector<int, 8> MaskVec;
4393 bool Reverse = (NonZeros & 0x3) == 2;
4394 for (unsigned i = 0; i < 2; ++i)
4395 MaskVec.push_back(Reverse ? 1-i : i);
4396 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4397 for (unsigned i = 0; i < 2; ++i)
4398 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4399 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4402 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4403 // Check for a build vector of consecutive loads.
4404 for (unsigned i = 0; i < NumElems; ++i)
4405 V[i] = Op.getOperand(i);
4407 // Check for elements which are consecutive loads.
4408 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4412 // For SSE 4.1, use insertps to put the high elements into the low element.
4413 if (getSubtarget()->hasSSE41()) {
4415 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4416 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4418 Result = DAG.getUNDEF(VT);
4420 for (unsigned i = 1; i < NumElems; ++i) {
4421 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4422 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4423 Op.getOperand(i), DAG.getIntPtrConstant(i));
4428 // Otherwise, expand into a number of unpckl*, start by extending each of
4429 // our (non-undef) elements to the full vector width with the element in the
4430 // bottom slot of the vector (which generates no code for SSE).
4431 for (unsigned i = 0; i < NumElems; ++i) {
4432 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4433 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4435 V[i] = DAG.getUNDEF(VT);
4438 // Next, we iteratively mix elements, e.g. for v4f32:
4439 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4440 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4441 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4442 unsigned EltStride = NumElems >> 1;
4443 while (EltStride != 0) {
4444 for (unsigned i = 0; i < EltStride; ++i) {
4445 // If V[i+EltStride] is undef and this is the first round of mixing,
4446 // then it is safe to just drop this shuffle: V[i] is already in the
4447 // right place, the one element (since it's the first round) being
4448 // inserted as undef can be dropped. This isn't safe for successive
4449 // rounds because they will permute elements within both vectors.
4450 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4451 EltStride == NumElems/2)
4454 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4464 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4465 // We support concatenate two MMX registers and place them in a MMX
4466 // register. This is better than doing a stack convert.
4467 DebugLoc dl = Op.getDebugLoc();
4468 EVT ResVT = Op.getValueType();
4469 assert(Op.getNumOperands() == 2);
4470 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4471 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4473 SDValue InVec = DAG.getNode(ISD::BIT_CONVERT,dl, MVT::v1i64, Op.getOperand(0));
4474 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4475 InVec = Op.getOperand(1);
4476 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4477 unsigned NumElts = ResVT.getVectorNumElements();
4478 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4479 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4480 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4482 InVec = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64, InVec);
4483 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4484 Mask[0] = 0; Mask[1] = 2;
4485 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4487 return DAG.getNode(ISD::BIT_CONVERT, dl, ResVT, VecOp);
4490 // v8i16 shuffles - Prefer shuffles in the following order:
4491 // 1. [all] pshuflw, pshufhw, optional move
4492 // 2. [ssse3] 1 x pshufb
4493 // 3. [ssse3] 2 x pshufb + 1 x por
4494 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4496 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4497 SelectionDAG &DAG) const {
4498 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4499 SDValue V1 = SVOp->getOperand(0);
4500 SDValue V2 = SVOp->getOperand(1);
4501 DebugLoc dl = SVOp->getDebugLoc();
4502 SmallVector<int, 8> MaskVals;
4504 // Determine if more than 1 of the words in each of the low and high quadwords
4505 // of the result come from the same quadword of one of the two inputs. Undef
4506 // mask values count as coming from any quadword, for better codegen.
4507 SmallVector<unsigned, 4> LoQuad(4);
4508 SmallVector<unsigned, 4> HiQuad(4);
4509 BitVector InputQuads(4);
4510 for (unsigned i = 0; i < 8; ++i) {
4511 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4512 int EltIdx = SVOp->getMaskElt(i);
4513 MaskVals.push_back(EltIdx);
4522 InputQuads.set(EltIdx / 4);
4525 int BestLoQuad = -1;
4526 unsigned MaxQuad = 1;
4527 for (unsigned i = 0; i < 4; ++i) {
4528 if (LoQuad[i] > MaxQuad) {
4530 MaxQuad = LoQuad[i];
4534 int BestHiQuad = -1;
4536 for (unsigned i = 0; i < 4; ++i) {
4537 if (HiQuad[i] > MaxQuad) {
4539 MaxQuad = HiQuad[i];
4543 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4544 // of the two input vectors, shuffle them into one input vector so only a
4545 // single pshufb instruction is necessary. If There are more than 2 input
4546 // quads, disable the next transformation since it does not help SSSE3.
4547 bool V1Used = InputQuads[0] || InputQuads[1];
4548 bool V2Used = InputQuads[2] || InputQuads[3];
4549 if (Subtarget->hasSSSE3()) {
4550 if (InputQuads.count() == 2 && V1Used && V2Used) {
4551 BestLoQuad = InputQuads.find_first();
4552 BestHiQuad = InputQuads.find_next(BestLoQuad);
4554 if (InputQuads.count() > 2) {
4560 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4561 // the shuffle mask. If a quad is scored as -1, that means that it contains
4562 // words from all 4 input quadwords.
4564 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4565 SmallVector<int, 8> MaskV;
4566 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4567 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4568 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4569 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
4570 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
4571 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
4573 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4574 // source words for the shuffle, to aid later transformations.
4575 bool AllWordsInNewV = true;
4576 bool InOrder[2] = { true, true };
4577 for (unsigned i = 0; i != 8; ++i) {
4578 int idx = MaskVals[i];
4580 InOrder[i/4] = false;
4581 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4583 AllWordsInNewV = false;
4587 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4588 if (AllWordsInNewV) {
4589 for (int i = 0; i != 8; ++i) {
4590 int idx = MaskVals[i];
4593 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4594 if ((idx != i) && idx < 4)
4596 if ((idx != i) && idx > 3)
4605 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4606 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4607 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4608 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4609 unsigned TargetMask = 0;
4610 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4611 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4612 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4613 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4614 V1 = NewV.getOperand(0);
4615 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4619 // If we have SSSE3, and all words of the result are from 1 input vector,
4620 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4621 // is present, fall back to case 4.
4622 if (Subtarget->hasSSSE3()) {
4623 SmallVector<SDValue,16> pshufbMask;
4625 // If we have elements from both input vectors, set the high bit of the
4626 // shuffle mask element to zero out elements that come from V2 in the V1
4627 // mask, and elements that come from V1 in the V2 mask, so that the two
4628 // results can be OR'd together.
4629 bool TwoInputs = V1Used && V2Used;
4630 for (unsigned i = 0; i != 8; ++i) {
4631 int EltIdx = MaskVals[i] * 2;
4632 if (TwoInputs && (EltIdx >= 16)) {
4633 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4634 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4637 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4638 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4640 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
4641 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4642 DAG.getNode(ISD::BUILD_VECTOR, dl,
4643 MVT::v16i8, &pshufbMask[0], 16));
4645 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4647 // Calculate the shuffle mask for the second input, shuffle it, and
4648 // OR it with the first shuffled input.
4650 for (unsigned i = 0; i != 8; ++i) {
4651 int EltIdx = MaskVals[i] * 2;
4653 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4654 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4657 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4658 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4660 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
4661 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4662 DAG.getNode(ISD::BUILD_VECTOR, dl,
4663 MVT::v16i8, &pshufbMask[0], 16));
4664 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4665 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4668 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4669 // and update MaskVals with new element order.
4670 BitVector InOrder(8);
4671 if (BestLoQuad >= 0) {
4672 SmallVector<int, 8> MaskV;
4673 for (int i = 0; i != 4; ++i) {
4674 int idx = MaskVals[i];
4676 MaskV.push_back(-1);
4678 } else if ((idx / 4) == BestLoQuad) {
4679 MaskV.push_back(idx & 3);
4682 MaskV.push_back(-1);
4685 for (unsigned i = 4; i != 8; ++i)
4687 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4690 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4691 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4693 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4697 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4698 // and update MaskVals with the new element order.
4699 if (BestHiQuad >= 0) {
4700 SmallVector<int, 8> MaskV;
4701 for (unsigned i = 0; i != 4; ++i)
4703 for (unsigned i = 4; i != 8; ++i) {
4704 int idx = MaskVals[i];
4706 MaskV.push_back(-1);
4708 } else if ((idx / 4) == BestHiQuad) {
4709 MaskV.push_back((idx & 3) + 4);
4712 MaskV.push_back(-1);
4715 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4718 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4719 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4721 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4725 // In case BestHi & BestLo were both -1, which means each quadword has a word
4726 // from each of the four input quadwords, calculate the InOrder bitvector now
4727 // before falling through to the insert/extract cleanup.
4728 if (BestLoQuad == -1 && BestHiQuad == -1) {
4730 for (int i = 0; i != 8; ++i)
4731 if (MaskVals[i] < 0 || MaskVals[i] == i)
4735 // The other elements are put in the right place using pextrw and pinsrw.
4736 for (unsigned i = 0; i != 8; ++i) {
4739 int EltIdx = MaskVals[i];
4742 SDValue ExtOp = (EltIdx < 8)
4743 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4744 DAG.getIntPtrConstant(EltIdx))
4745 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4746 DAG.getIntPtrConstant(EltIdx - 8));
4747 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4748 DAG.getIntPtrConstant(i));
4753 // v16i8 shuffles - Prefer shuffles in the following order:
4754 // 1. [ssse3] 1 x pshufb
4755 // 2. [ssse3] 2 x pshufb + 1 x por
4756 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4758 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4760 const X86TargetLowering &TLI) {
4761 SDValue V1 = SVOp->getOperand(0);
4762 SDValue V2 = SVOp->getOperand(1);
4763 DebugLoc dl = SVOp->getDebugLoc();
4764 SmallVector<int, 16> MaskVals;
4765 SVOp->getMask(MaskVals);
4767 // If we have SSSE3, case 1 is generated when all result bytes come from
4768 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4769 // present, fall back to case 3.
4770 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4773 for (unsigned i = 0; i < 16; ++i) {
4774 int EltIdx = MaskVals[i];
4783 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4784 if (TLI.getSubtarget()->hasSSSE3()) {
4785 SmallVector<SDValue,16> pshufbMask;
4787 // If all result elements are from one input vector, then only translate
4788 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4790 // Otherwise, we have elements from both input vectors, and must zero out
4791 // elements that come from V2 in the first mask, and V1 in the second mask
4792 // so that we can OR them together.
4793 bool TwoInputs = !(V1Only || V2Only);
4794 for (unsigned i = 0; i != 16; ++i) {
4795 int EltIdx = MaskVals[i];
4796 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4797 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4800 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4802 // If all the elements are from V2, assign it to V1 and return after
4803 // building the first pshufb.
4806 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4807 DAG.getNode(ISD::BUILD_VECTOR, dl,
4808 MVT::v16i8, &pshufbMask[0], 16));
4812 // Calculate the shuffle mask for the second input, shuffle it, and
4813 // OR it with the first shuffled input.
4815 for (unsigned i = 0; i != 16; ++i) {
4816 int EltIdx = MaskVals[i];
4818 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4821 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4823 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4824 DAG.getNode(ISD::BUILD_VECTOR, dl,
4825 MVT::v16i8, &pshufbMask[0], 16));
4826 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4829 // No SSSE3 - Calculate in place words and then fix all out of place words
4830 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4831 // the 16 different words that comprise the two doublequadword input vectors.
4832 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
4833 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
4834 SDValue NewV = V2Only ? V2 : V1;
4835 for (int i = 0; i != 8; ++i) {
4836 int Elt0 = MaskVals[i*2];
4837 int Elt1 = MaskVals[i*2+1];
4839 // This word of the result is all undef, skip it.
4840 if (Elt0 < 0 && Elt1 < 0)
4843 // This word of the result is already in the correct place, skip it.
4844 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4846 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4849 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4850 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4853 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4854 // using a single extract together, load it and store it.
4855 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4856 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4857 DAG.getIntPtrConstant(Elt1 / 2));
4858 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4859 DAG.getIntPtrConstant(i));
4863 // If Elt1 is defined, extract it from the appropriate source. If the
4864 // source byte is not also odd, shift the extracted word left 8 bits
4865 // otherwise clear the bottom 8 bits if we need to do an or.
4867 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4868 DAG.getIntPtrConstant(Elt1 / 2));
4869 if ((Elt1 & 1) == 0)
4870 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4871 DAG.getConstant(8, TLI.getShiftAmountTy()));
4873 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4874 DAG.getConstant(0xFF00, MVT::i16));
4876 // If Elt0 is defined, extract it from the appropriate source. If the
4877 // source byte is not also even, shift the extracted word right 8 bits. If
4878 // Elt1 was also defined, OR the extracted values together before
4879 // inserting them in the result.
4881 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4882 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4883 if ((Elt0 & 1) != 0)
4884 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4885 DAG.getConstant(8, TLI.getShiftAmountTy()));
4887 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4888 DAG.getConstant(0x00FF, MVT::i16));
4889 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4892 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4893 DAG.getIntPtrConstant(i));
4895 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
4898 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4899 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
4900 /// done when every pair / quad of shuffle mask elements point to elements in
4901 /// the right sequence. e.g.
4902 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
4904 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4905 SelectionDAG &DAG, DebugLoc dl) {
4906 EVT VT = SVOp->getValueType(0);
4907 SDValue V1 = SVOp->getOperand(0);
4908 SDValue V2 = SVOp->getOperand(1);
4909 unsigned NumElems = VT.getVectorNumElements();
4910 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4912 switch (VT.getSimpleVT().SimpleTy) {
4913 default: assert(false && "Unexpected!");
4914 case MVT::v4f32: NewVT = MVT::v2f64; break;
4915 case MVT::v4i32: NewVT = MVT::v2i64; break;
4916 case MVT::v8i16: NewVT = MVT::v4i32; break;
4917 case MVT::v16i8: NewVT = MVT::v4i32; break;
4920 int Scale = NumElems / NewWidth;
4921 SmallVector<int, 8> MaskVec;
4922 for (unsigned i = 0; i < NumElems; i += Scale) {
4924 for (int j = 0; j < Scale; ++j) {
4925 int EltIdx = SVOp->getMaskElt(i+j);
4929 StartIdx = EltIdx - (EltIdx % Scale);
4930 if (EltIdx != StartIdx + j)
4934 MaskVec.push_back(-1);
4936 MaskVec.push_back(StartIdx / Scale);
4939 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
4940 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
4941 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4944 /// getVZextMovL - Return a zero-extending vector move low node.
4946 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4947 SDValue SrcOp, SelectionDAG &DAG,
4948 const X86Subtarget *Subtarget, DebugLoc dl) {
4949 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4950 LoadSDNode *LD = NULL;
4951 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4952 LD = dyn_cast<LoadSDNode>(SrcOp);
4954 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4956 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4957 if ((ExtVT.SimpleTy != MVT::i64 || Subtarget->is64Bit()) &&
4958 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4959 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
4960 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4962 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4963 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4964 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4965 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4973 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4974 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4975 DAG.getNode(ISD::BIT_CONVERT, dl,
4979 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4982 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4983 SDValue V1 = SVOp->getOperand(0);
4984 SDValue V2 = SVOp->getOperand(1);
4985 DebugLoc dl = SVOp->getDebugLoc();
4986 EVT VT = SVOp->getValueType(0);
4988 SmallVector<std::pair<int, int>, 8> Locs;
4990 SmallVector<int, 8> Mask1(4U, -1);
4991 SmallVector<int, 8> PermMask;
4992 SVOp->getMask(PermMask);
4996 for (unsigned i = 0; i != 4; ++i) {
4997 int Idx = PermMask[i];
4999 Locs[i] = std::make_pair(-1, -1);
5001 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5003 Locs[i] = std::make_pair(0, NumLo);
5007 Locs[i] = std::make_pair(1, NumHi);
5009 Mask1[2+NumHi] = Idx;
5015 if (NumLo <= 2 && NumHi <= 2) {
5016 // If no more than two elements come from either vector. This can be
5017 // implemented with two shuffles. First shuffle gather the elements.
5018 // The second shuffle, which takes the first shuffle as both of its
5019 // vector operands, put the elements into the right order.
5020 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5022 SmallVector<int, 8> Mask2(4U, -1);
5024 for (unsigned i = 0; i != 4; ++i) {
5025 if (Locs[i].first == -1)
5028 unsigned Idx = (i < 2) ? 0 : 4;
5029 Idx += Locs[i].first * 2 + Locs[i].second;
5034 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5035 } else if (NumLo == 3 || NumHi == 3) {
5036 // Otherwise, we must have three elements from one vector, call it X, and
5037 // one element from the other, call it Y. First, use a shufps to build an
5038 // intermediate vector with the one element from Y and the element from X
5039 // that will be in the same half in the final destination (the indexes don't
5040 // matter). Then, use a shufps to build the final vector, taking the half
5041 // containing the element from Y from the intermediate, and the other half
5044 // Normalize it so the 3 elements come from V1.
5045 CommuteVectorShuffleMask(PermMask, VT);
5049 // Find the element from V2.
5051 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5052 int Val = PermMask[HiIndex];
5059 Mask1[0] = PermMask[HiIndex];
5061 Mask1[2] = PermMask[HiIndex^1];
5063 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5066 Mask1[0] = PermMask[0];
5067 Mask1[1] = PermMask[1];
5068 Mask1[2] = HiIndex & 1 ? 6 : 4;
5069 Mask1[3] = HiIndex & 1 ? 4 : 6;
5070 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5072 Mask1[0] = HiIndex & 1 ? 2 : 0;
5073 Mask1[1] = HiIndex & 1 ? 0 : 2;
5074 Mask1[2] = PermMask[2];
5075 Mask1[3] = PermMask[3];
5080 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5084 // Break it into (shuffle shuffle_hi, shuffle_lo).
5086 SmallVector<int,8> LoMask(4U, -1);
5087 SmallVector<int,8> HiMask(4U, -1);
5089 SmallVector<int,8> *MaskPtr = &LoMask;
5090 unsigned MaskIdx = 0;
5093 for (unsigned i = 0; i != 4; ++i) {
5100 int Idx = PermMask[i];
5102 Locs[i] = std::make_pair(-1, -1);
5103 } else if (Idx < 4) {
5104 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5105 (*MaskPtr)[LoIdx] = Idx;
5108 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5109 (*MaskPtr)[HiIdx] = Idx;
5114 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5115 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5116 SmallVector<int, 8> MaskOps;
5117 for (unsigned i = 0; i != 4; ++i) {
5118 if (Locs[i].first == -1) {
5119 MaskOps.push_back(-1);
5121 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5122 MaskOps.push_back(Idx);
5125 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5128 static bool MayFoldVectorLoad(SDValue V) {
5129 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5130 V = V.getOperand(0);
5131 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5132 V = V.getOperand(0);
5138 // FIXME: the version above should always be used. Since there's
5139 // a bug where several vector shuffles can't be folded because the
5140 // DAG is not updated during lowering and a node claims to have two
5141 // uses while it only has one, use this version, and let isel match
5142 // another instruction if the load really happens to have more than
5143 // one use. Remove this version after this bug get fixed.
5144 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5145 if (V.hasOneUse() && V.getOpcode() == ISD::BIT_CONVERT)
5146 V = V.getOperand(0);
5147 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5148 V = V.getOperand(0);
5149 if (ISD::isNormalLoad(V.getNode()))
5154 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5155 /// a vector extract, and if both can be later optimized into a single load.
5156 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5157 /// here because otherwise a target specific shuffle node is going to be
5158 /// emitted for this shuffle, and the optimization not done.
5159 /// FIXME: This is probably not the best approach, but fix the problem
5160 /// until the right path is decided.
5162 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5163 const TargetLowering &TLI) {
5164 EVT VT = V.getValueType();
5165 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5167 // Be sure that the vector shuffle is present in a pattern like this:
5168 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5172 SDNode *N = *V.getNode()->use_begin();
5173 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5176 SDValue EltNo = N->getOperand(1);
5177 if (!isa<ConstantSDNode>(EltNo))
5180 // If the bit convert changed the number of elements, it is unsafe
5181 // to examine the mask.
5182 bool HasShuffleIntoBitcast = false;
5183 if (V.getOpcode() == ISD::BIT_CONVERT) {
5184 EVT SrcVT = V.getOperand(0).getValueType();
5185 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5187 V = V.getOperand(0);
5188 HasShuffleIntoBitcast = true;
5191 // Select the input vector, guarding against out of range extract vector.
5192 unsigned NumElems = VT.getVectorNumElements();
5193 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5194 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5195 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5197 // Skip one more bit_convert if necessary
5198 if (V.getOpcode() == ISD::BIT_CONVERT)
5199 V = V.getOperand(0);
5201 if (ISD::isNormalLoad(V.getNode())) {
5202 // Is the original load suitable?
5203 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5205 // FIXME: avoid the multi-use bug that is preventing lots of
5206 // of foldings to be detected, this is still wrong of course, but
5207 // give the temporary desired behavior, and if it happens that
5208 // the load has real more uses, during isel it will not fold, and
5209 // will generate poor code.
5210 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5213 if (!HasShuffleIntoBitcast)
5216 // If there's a bitcast before the shuffle, check if the load type and
5217 // alignment is valid.
5218 unsigned Align = LN0->getAlignment();
5220 TLI.getTargetData()->getABITypeAlignment(
5221 VT.getTypeForEVT(*DAG.getContext()));
5223 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5231 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5233 SDValue V1 = Op.getOperand(0);
5234 SDValue V2 = Op.getOperand(1);
5235 EVT VT = Op.getValueType();
5237 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5239 if (HasSSE2 && VT == MVT::v2f64)
5240 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5243 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5247 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5248 SDValue V1 = Op.getOperand(0);
5249 SDValue V2 = Op.getOperand(1);
5250 EVT VT = Op.getValueType();
5252 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5253 "unsupported shuffle type");
5255 if (V2.getOpcode() == ISD::UNDEF)
5259 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5263 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5264 SDValue V1 = Op.getOperand(0);
5265 SDValue V2 = Op.getOperand(1);
5266 EVT VT = Op.getValueType();
5267 unsigned NumElems = VT.getVectorNumElements();
5269 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5270 // operand of these instructions is only memory, so check if there's a
5271 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5273 bool CanFoldLoad = false;
5275 // Trivial case, when V2 comes from a load.
5276 if (MayFoldVectorLoad(V2))
5279 // When V1 is a load, it can be folded later into a store in isel, example:
5280 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5282 // (MOVLPSmr addr:$src1, VR128:$src2)
5283 // So, recognize this potential and also use MOVLPS or MOVLPD
5284 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5288 if (HasSSE2 && NumElems == 2)
5289 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5292 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5295 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5296 // movl and movlp will both match v2i64, but v2i64 is never matched by
5297 // movl earlier because we make it strict to avoid messing with the movlp load
5298 // folding logic (see the code above getMOVLP call). Match it here then,
5299 // this is horrible, but will stay like this until we move all shuffle
5300 // matching to x86 specific nodes. Note that for the 1st condition all
5301 // types are matched with movsd.
5302 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5303 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5305 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5308 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5310 // Invert the operand order and use SHUFPS to match it.
5311 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5312 X86::getShuffleSHUFImmediate(SVOp), DAG);
5315 static inline unsigned getUNPCKLOpcode(EVT VT) {
5316 switch(VT.getSimpleVT().SimpleTy) {
5317 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5318 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5319 case MVT::v4f32: return X86ISD::UNPCKLPS;
5320 case MVT::v2f64: return X86ISD::UNPCKLPD;
5321 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5322 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5324 llvm_unreachable("Unknow type for unpckl");
5329 static inline unsigned getUNPCKHOpcode(EVT VT) {
5330 switch(VT.getSimpleVT().SimpleTy) {
5331 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5332 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5333 case MVT::v4f32: return X86ISD::UNPCKHPS;
5334 case MVT::v2f64: return X86ISD::UNPCKHPD;
5335 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5336 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5338 llvm_unreachable("Unknow type for unpckh");
5344 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5345 const TargetLowering &TLI,
5346 const X86Subtarget *Subtarget) {
5347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5348 EVT VT = Op.getValueType();
5349 DebugLoc dl = Op.getDebugLoc();
5350 SDValue V1 = Op.getOperand(0);
5351 SDValue V2 = Op.getOperand(1);
5353 if (isZeroShuffle(SVOp))
5354 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5356 // Handle splat operations
5357 if (SVOp->isSplat()) {
5358 // Special case, this is the only place now where it's
5359 // allowed to return a vector_shuffle operation without
5360 // using a target specific node, because *hopefully* it
5361 // will be optimized away by the dag combiner.
5362 if (VT.getVectorNumElements() <= 4 &&
5363 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5366 // Handle splats by matching through known masks
5367 if (VT.getVectorNumElements() <= 4)
5370 // Canonize all of the remaining to v4f32.
5371 return PromoteSplat(SVOp, DAG);
5374 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5376 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5377 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5378 if (NewOp.getNode())
5379 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, NewOp);
5380 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5381 // FIXME: Figure out a cleaner way to do this.
5382 // Try to make use of movq to zero out the top part.
5383 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5384 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5385 if (NewOp.getNode()) {
5386 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5387 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5388 DAG, Subtarget, dl);
5390 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5391 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5392 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5393 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5394 DAG, Subtarget, dl);
5401 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5402 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5403 SDValue V1 = Op.getOperand(0);
5404 SDValue V2 = Op.getOperand(1);
5405 EVT VT = Op.getValueType();
5406 DebugLoc dl = Op.getDebugLoc();
5407 unsigned NumElems = VT.getVectorNumElements();
5408 bool isMMX = VT.getSizeInBits() == 64;
5409 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5410 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5411 bool V1IsSplat = false;
5412 bool V2IsSplat = false;
5413 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5414 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5415 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5416 MachineFunction &MF = DAG.getMachineFunction();
5417 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5419 // FIXME: this is somehow handled during isel by MMX pattern fragments. Remove
5420 // the check or come up with another solution when all MMX move to intrinsics,
5421 // but don't allow this to be considered legal, we don't want vector_shuffle
5422 // operations to be matched during isel anymore.
5423 if (isMMX && SVOp->isSplat())
5426 // Vector shuffle lowering takes 3 steps:
5428 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5429 // narrowing and commutation of operands should be handled.
5430 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5432 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5433 // so the shuffle can be broken into other shuffles and the legalizer can
5434 // try the lowering again.
5436 // The general ideia is that no vector_shuffle operation should be left to
5437 // be matched during isel, all of them must be converted to a target specific
5440 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5441 // narrowing and commutation of operands should be handled. The actual code
5442 // doesn't include all of those, work in progress...
5443 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5444 if (NewOp.getNode())
5447 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5448 // unpckh_undef). Only use pshufd if speed is more important than size.
5449 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5450 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5451 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5452 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5453 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5454 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5456 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5457 RelaxedMayFoldVectorLoad(V1) && !isMMX)
5458 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
5460 if (!isMMX && X86::isMOVHLPS_v_undef_Mask(SVOp))
5461 return getMOVHighToLow(Op, dl, DAG);
5463 // Use to match splats
5464 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5465 (VT == MVT::v2f64 || VT == MVT::v2i64))
5466 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5468 if (X86::isPSHUFDMask(SVOp)) {
5469 // The actual implementation will match the mask in the if above and then
5470 // during isel it can match several different instructions, not only pshufd
5471 // as its name says, sad but true, emulate the behavior for now...
5472 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5473 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5475 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5477 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5478 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5480 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5481 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5484 if (VT == MVT::v4f32)
5485 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5489 // Check if this can be converted into a logical shift.
5490 bool isLeft = false;
5493 bool isShift = getSubtarget()->hasSSE2() &&
5494 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5495 if (isShift && ShVal.hasOneUse()) {
5496 // If the shifted value has multiple uses, it may be cheaper to use
5497 // v_set0 + movlhps or movhlps, etc.
5498 EVT EltVT = VT.getVectorElementType();
5499 ShAmt *= EltVT.getSizeInBits();
5500 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5503 if (X86::isMOVLMask(SVOp)) {
5506 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5507 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5508 if (!isMMX && !X86::isMOVLPMask(SVOp)) {
5509 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5510 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5512 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5513 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5517 // FIXME: fold these into legal mask.
5519 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5520 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5522 if (X86::isMOVHLPSMask(SVOp))
5523 return getMOVHighToLow(Op, dl, DAG);
5525 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5526 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5528 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5529 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5531 if (X86::isMOVLPMask(SVOp))
5532 return getMOVLP(Op, dl, DAG, HasSSE2);
5535 if (ShouldXformToMOVHLPS(SVOp) ||
5536 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5537 return CommuteVectorShuffle(SVOp, DAG);
5540 // No better options. Use a vshl / vsrl.
5541 EVT EltVT = VT.getVectorElementType();
5542 ShAmt *= EltVT.getSizeInBits();
5543 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5546 bool Commuted = false;
5547 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5548 // 1,1,1,1 -> v8i16 though.
5549 V1IsSplat = isSplatVector(V1.getNode());
5550 V2IsSplat = isSplatVector(V2.getNode());
5552 // Canonicalize the splat or undef, if present, to be on the RHS.
5553 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5554 Op = CommuteVectorShuffle(SVOp, DAG);
5555 SVOp = cast<ShuffleVectorSDNode>(Op);
5556 V1 = SVOp->getOperand(0);
5557 V2 = SVOp->getOperand(1);
5558 std::swap(V1IsSplat, V2IsSplat);
5559 std::swap(V1IsUndef, V2IsUndef);
5563 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5564 // Shuffling low element of v1 into undef, just return v1.
5567 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5568 // the instruction selector will not match, so get a canonical MOVL with
5569 // swapped operands to undo the commute.
5570 return getMOVL(DAG, dl, VT, V2, V1);
5573 if (X86::isUNPCKLMask(SVOp))
5575 Op : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5577 if (X86::isUNPCKHMask(SVOp))
5579 Op : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5582 // Normalize mask so all entries that point to V2 points to its first
5583 // element then try to match unpck{h|l} again. If match, return a
5584 // new vector_shuffle with the corrected mask.
5585 SDValue NewMask = NormalizeMask(SVOp, DAG);
5586 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5587 if (NSVOp != SVOp) {
5588 if (X86::isUNPCKLMask(NSVOp, true)) {
5590 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5597 // Commute is back and try unpck* again.
5598 // FIXME: this seems wrong.
5599 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5600 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5602 if (X86::isUNPCKLMask(NewSVOp))
5604 NewOp : getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5606 if (X86::isUNPCKHMask(NewSVOp))
5608 NewOp : getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5611 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
5613 // Normalize the node to match x86 shuffle ops if needed
5614 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5615 return CommuteVectorShuffle(SVOp, DAG);
5617 // The checks below are all present in isShuffleMaskLegal, but they are
5618 // inlined here right now to enable us to directly emit target specific
5619 // nodes, and remove one by one until they don't return Op anymore.
5620 SmallVector<int, 16> M;
5623 if (isPALIGNRMask(M, VT, HasSSSE3))
5624 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5625 X86::getShufflePALIGNRImmediate(SVOp),
5628 // Only a few shuffle masks are handled for 64-bit vectors (MMX), and
5629 // 64-bit vectors which made to this point can't be handled, they are
5634 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5635 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5636 if (VT == MVT::v2f64)
5637 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5638 if (VT == MVT::v2i64)
5639 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5642 if (isPSHUFHWMask(M, VT))
5643 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5644 X86::getShufflePSHUFHWImmediate(SVOp),
5647 if (isPSHUFLWMask(M, VT))
5648 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5649 X86::getShufflePSHUFLWImmediate(SVOp),
5652 if (isSHUFPMask(M, VT)) {
5653 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5654 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5655 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5657 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5658 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5662 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5663 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5664 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5665 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5666 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5667 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5669 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5670 if (VT == MVT::v8i16) {
5671 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5672 if (NewOp.getNode())
5676 if (VT == MVT::v16i8) {
5677 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5678 if (NewOp.getNode())
5682 // Handle all 4 wide cases with a number of shuffles except for MMX.
5683 if (NumElems == 4 && !isMMX)
5684 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5690 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5691 SelectionDAG &DAG) const {
5692 EVT VT = Op.getValueType();
5693 DebugLoc dl = Op.getDebugLoc();
5694 if (VT.getSizeInBits() == 8) {
5695 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5696 Op.getOperand(0), Op.getOperand(1));
5697 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5698 DAG.getValueType(VT));
5699 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5700 } else if (VT.getSizeInBits() == 16) {
5701 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5702 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5704 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5705 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5706 DAG.getNode(ISD::BIT_CONVERT, dl,
5710 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5711 Op.getOperand(0), Op.getOperand(1));
5712 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5713 DAG.getValueType(VT));
5714 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5715 } else if (VT == MVT::f32) {
5716 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5717 // the result back to FR32 register. It's only worth matching if the
5718 // result has a single use which is a store or a bitcast to i32. And in
5719 // the case of a store, it's not worth it if the index is a constant 0,
5720 // because a MOVSSmr can be used instead, which is smaller and faster.
5721 if (!Op.hasOneUse())
5723 SDNode *User = *Op.getNode()->use_begin();
5724 if ((User->getOpcode() != ISD::STORE ||
5725 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5726 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5727 (User->getOpcode() != ISD::BIT_CONVERT ||
5728 User->getValueType(0) != MVT::i32))
5730 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5731 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
5734 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
5735 } else if (VT == MVT::i32) {
5736 // ExtractPS works with constant index.
5737 if (isa<ConstantSDNode>(Op.getOperand(1)))
5745 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5746 SelectionDAG &DAG) const {
5747 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5750 if (Subtarget->hasSSE41()) {
5751 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5756 EVT VT = Op.getValueType();
5757 DebugLoc dl = Op.getDebugLoc();
5758 // TODO: handle v16i8.
5759 if (VT.getSizeInBits() == 16) {
5760 SDValue Vec = Op.getOperand(0);
5761 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5763 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5764 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5765 DAG.getNode(ISD::BIT_CONVERT, dl,
5768 // Transform it so it match pextrw which produces a 32-bit result.
5769 EVT EltVT = MVT::i32;
5770 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5771 Op.getOperand(0), Op.getOperand(1));
5772 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5773 DAG.getValueType(VT));
5774 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5775 } else if (VT.getSizeInBits() == 32) {
5776 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5780 // SHUFPS the element to the lowest double word, then movss.
5781 int Mask[4] = { Idx, -1, -1, -1 };
5782 EVT VVT = Op.getOperand(0).getValueType();
5783 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5784 DAG.getUNDEF(VVT), Mask);
5785 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5786 DAG.getIntPtrConstant(0));
5787 } else if (VT.getSizeInBits() == 64) {
5788 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5789 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5790 // to match extract_elt for f64.
5791 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5795 // UNPCKHPD the element to the lowest double word, then movsd.
5796 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5797 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5798 int Mask[2] = { 1, -1 };
5799 EVT VVT = Op.getOperand(0).getValueType();
5800 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5801 DAG.getUNDEF(VVT), Mask);
5802 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5803 DAG.getIntPtrConstant(0));
5810 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5811 SelectionDAG &DAG) const {
5812 EVT VT = Op.getValueType();
5813 EVT EltVT = VT.getVectorElementType();
5814 DebugLoc dl = Op.getDebugLoc();
5816 SDValue N0 = Op.getOperand(0);
5817 SDValue N1 = Op.getOperand(1);
5818 SDValue N2 = Op.getOperand(2);
5820 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5821 isa<ConstantSDNode>(N2)) {
5823 if (VT == MVT::v8i16)
5824 Opc = X86ISD::PINSRW;
5825 else if (VT == MVT::v4i16)
5826 Opc = X86ISD::MMX_PINSRW;
5827 else if (VT == MVT::v16i8)
5828 Opc = X86ISD::PINSRB;
5830 Opc = X86ISD::PINSRB;
5832 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5834 if (N1.getValueType() != MVT::i32)
5835 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5836 if (N2.getValueType() != MVT::i32)
5837 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5838 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5839 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5840 // Bits [7:6] of the constant are the source select. This will always be
5841 // zero here. The DAG Combiner may combine an extract_elt index into these
5842 // bits. For example (insert (extract, 3), 2) could be matched by putting
5843 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5844 // Bits [5:4] of the constant are the destination select. This is the
5845 // value of the incoming immediate.
5846 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5847 // combine either bitwise AND or insert of float 0.0 to set these bits.
5848 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5849 // Create this as a scalar to vector..
5850 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5851 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5852 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5853 // PINSR* works with constant index.
5860 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5861 EVT VT = Op.getValueType();
5862 EVT EltVT = VT.getVectorElementType();
5864 if (Subtarget->hasSSE41())
5865 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5867 if (EltVT == MVT::i8)
5870 DebugLoc dl = Op.getDebugLoc();
5871 SDValue N0 = Op.getOperand(0);
5872 SDValue N1 = Op.getOperand(1);
5873 SDValue N2 = Op.getOperand(2);
5875 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5876 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5877 // as its second argument.
5878 if (N1.getValueType() != MVT::i32)
5879 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5880 if (N2.getValueType() != MVT::i32)
5881 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5882 return DAG.getNode(VT == MVT::v8i16 ? X86ISD::PINSRW : X86ISD::MMX_PINSRW,
5883 dl, VT, N0, N1, N2);
5889 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5890 DebugLoc dl = Op.getDebugLoc();
5892 if (Op.getValueType() == MVT::v1i64 &&
5893 Op.getOperand(0).getValueType() == MVT::i64)
5894 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5896 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5897 EVT VT = MVT::v2i32;
5898 switch (Op.getValueType().getSimpleVT().SimpleTy) {
5905 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
5906 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
5909 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5910 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5911 // one of the above mentioned nodes. It has to be wrapped because otherwise
5912 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5913 // be used to form addressing mode. These wrapped nodes will be selected
5916 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5917 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5919 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5921 unsigned char OpFlag = 0;
5922 unsigned WrapperKind = X86ISD::Wrapper;
5923 CodeModel::Model M = getTargetMachine().getCodeModel();
5925 if (Subtarget->isPICStyleRIPRel() &&
5926 (M == CodeModel::Small || M == CodeModel::Kernel))
5927 WrapperKind = X86ISD::WrapperRIP;
5928 else if (Subtarget->isPICStyleGOT())
5929 OpFlag = X86II::MO_GOTOFF;
5930 else if (Subtarget->isPICStyleStubPIC())
5931 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5933 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5935 CP->getOffset(), OpFlag);
5936 DebugLoc DL = CP->getDebugLoc();
5937 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5938 // With PIC, the address is actually $g + Offset.
5940 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5941 DAG.getNode(X86ISD::GlobalBaseReg,
5942 DebugLoc(), getPointerTy()),
5949 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5950 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5952 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5954 unsigned char OpFlag = 0;
5955 unsigned WrapperKind = X86ISD::Wrapper;
5956 CodeModel::Model M = getTargetMachine().getCodeModel();
5958 if (Subtarget->isPICStyleRIPRel() &&
5959 (M == CodeModel::Small || M == CodeModel::Kernel))
5960 WrapperKind = X86ISD::WrapperRIP;
5961 else if (Subtarget->isPICStyleGOT())
5962 OpFlag = X86II::MO_GOTOFF;
5963 else if (Subtarget->isPICStyleStubPIC())
5964 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5966 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5968 DebugLoc DL = JT->getDebugLoc();
5969 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5971 // With PIC, the address is actually $g + Offset.
5973 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5974 DAG.getNode(X86ISD::GlobalBaseReg,
5975 DebugLoc(), getPointerTy()),
5983 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5984 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5986 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5988 unsigned char OpFlag = 0;
5989 unsigned WrapperKind = X86ISD::Wrapper;
5990 CodeModel::Model M = getTargetMachine().getCodeModel();
5992 if (Subtarget->isPICStyleRIPRel() &&
5993 (M == CodeModel::Small || M == CodeModel::Kernel))
5994 WrapperKind = X86ISD::WrapperRIP;
5995 else if (Subtarget->isPICStyleGOT())
5996 OpFlag = X86II::MO_GOTOFF;
5997 else if (Subtarget->isPICStyleStubPIC())
5998 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6000 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
6002 DebugLoc DL = Op.getDebugLoc();
6003 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6006 // With PIC, the address is actually $g + Offset.
6007 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
6008 !Subtarget->is64Bit()) {
6009 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6010 DAG.getNode(X86ISD::GlobalBaseReg,
6011 DebugLoc(), getPointerTy()),
6019 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
6020 // Create the TargetBlockAddressAddress node.
6021 unsigned char OpFlags =
6022 Subtarget->ClassifyBlockAddressReference();
6023 CodeModel::Model M = getTargetMachine().getCodeModel();
6024 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
6025 DebugLoc dl = Op.getDebugLoc();
6026 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
6027 /*isTarget=*/true, OpFlags);
6029 if (Subtarget->isPICStyleRIPRel() &&
6030 (M == CodeModel::Small || M == CodeModel::Kernel))
6031 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6033 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6035 // With PIC, the address is actually $g + Offset.
6036 if (isGlobalRelativeToPICBase(OpFlags)) {
6037 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6038 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6046 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
6048 SelectionDAG &DAG) const {
6049 // Create the TargetGlobalAddress node, folding in the constant
6050 // offset if it is legal.
6051 unsigned char OpFlags =
6052 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
6053 CodeModel::Model M = getTargetMachine().getCodeModel();
6055 if (OpFlags == X86II::MO_NO_FLAG &&
6056 X86::isOffsetSuitableForCodeModel(Offset, M)) {
6057 // A direct static reference to a global.
6058 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
6061 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6064 if (Subtarget->isPICStyleRIPRel() &&
6065 (M == CodeModel::Small || M == CodeModel::Kernel))
6066 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6068 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6070 // With PIC, the address is actually $g + Offset.
6071 if (isGlobalRelativeToPICBase(OpFlags)) {
6072 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6073 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6077 // For globals that require a load from a stub to get the address, emit the
6079 if (isGlobalStubReference(OpFlags))
6080 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6081 MachinePointerInfo::getGOT(), false, false, 0);
6083 // If there was a non-zero offset that we didn't fold, create an explicit
6086 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6087 DAG.getConstant(Offset, getPointerTy()));
6093 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6094 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6095 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6096 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6100 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6101 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6102 unsigned char OperandFlags) {
6103 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6104 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
6105 DebugLoc dl = GA->getDebugLoc();
6106 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6107 GA->getValueType(0),
6111 SDValue Ops[] = { Chain, TGA, *InFlag };
6112 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6114 SDValue Ops[] = { Chain, TGA };
6115 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6118 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6119 MFI->setAdjustsStack(true);
6121 SDValue Flag = Chain.getValue(1);
6122 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6125 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6127 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6130 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6131 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6132 DAG.getNode(X86ISD::GlobalBaseReg,
6133 DebugLoc(), PtrVT), InFlag);
6134 InFlag = Chain.getValue(1);
6136 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6139 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6141 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6143 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6144 X86::RAX, X86II::MO_TLSGD);
6147 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6148 // "local exec" model.
6149 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6150 const EVT PtrVT, TLSModel::Model model,
6152 DebugLoc dl = GA->getDebugLoc();
6153 // Get the Thread Pointer
6154 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
6156 DAG.getRegister(is64Bit? X86::FS : X86::GS,
6159 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
6160 MachinePointerInfo(), false, false, 0);
6162 unsigned char OperandFlags = 0;
6163 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6165 unsigned WrapperKind = X86ISD::Wrapper;
6166 if (model == TLSModel::LocalExec) {
6167 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6168 } else if (is64Bit) {
6169 assert(model == TLSModel::InitialExec);
6170 OperandFlags = X86II::MO_GOTTPOFF;
6171 WrapperKind = X86ISD::WrapperRIP;
6173 assert(model == TLSModel::InitialExec);
6174 OperandFlags = X86II::MO_INDNTPOFF;
6177 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6179 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6180 GA->getValueType(0),
6181 GA->getOffset(), OperandFlags);
6182 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6184 if (model == TLSModel::InitialExec)
6185 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6186 MachinePointerInfo::getGOT(), false, false, 0);
6188 // The address of the thread local variable is the add of the thread
6189 // pointer with the offset of the variable.
6190 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6194 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6196 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6197 const GlobalValue *GV = GA->getGlobal();
6199 if (Subtarget->isTargetELF()) {
6200 // TODO: implement the "local dynamic" model
6201 // TODO: implement the "initial exec"model for pic executables
6203 // If GV is an alias then use the aliasee for determining
6204 // thread-localness.
6205 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6206 GV = GA->resolveAliasedGlobal(false);
6208 TLSModel::Model model
6209 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6212 case TLSModel::GeneralDynamic:
6213 case TLSModel::LocalDynamic: // not implemented
6214 if (Subtarget->is64Bit())
6215 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6216 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6218 case TLSModel::InitialExec:
6219 case TLSModel::LocalExec:
6220 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6221 Subtarget->is64Bit());
6223 } else if (Subtarget->isTargetDarwin()) {
6224 // Darwin only has one model of TLS. Lower to that.
6225 unsigned char OpFlag = 0;
6226 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6227 X86ISD::WrapperRIP : X86ISD::Wrapper;
6229 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6231 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6232 !Subtarget->is64Bit();
6234 OpFlag = X86II::MO_TLVP_PIC_BASE;
6236 OpFlag = X86II::MO_TLVP;
6237 DebugLoc DL = Op.getDebugLoc();
6238 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6240 GA->getOffset(), OpFlag);
6241 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6243 // With PIC32, the address is actually $g + Offset.
6245 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6246 DAG.getNode(X86ISD::GlobalBaseReg,
6247 DebugLoc(), getPointerTy()),
6250 // Lowering the machine isd will make sure everything is in the right
6252 SDValue Args[] = { Offset };
6253 SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
6255 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6256 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6257 MFI->setAdjustsStack(true);
6259 // And our return value (tls address) is in the standard call return value
6261 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6262 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6266 "TLS not implemented for this target.");
6268 llvm_unreachable("Unreachable");
6273 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6274 /// take a 2 x i32 value to shift plus a shift amount.
6275 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6276 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6277 EVT VT = Op.getValueType();
6278 unsigned VTBits = VT.getSizeInBits();
6279 DebugLoc dl = Op.getDebugLoc();
6280 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6281 SDValue ShOpLo = Op.getOperand(0);
6282 SDValue ShOpHi = Op.getOperand(1);
6283 SDValue ShAmt = Op.getOperand(2);
6284 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6285 DAG.getConstant(VTBits - 1, MVT::i8))
6286 : DAG.getConstant(0, VT);
6289 if (Op.getOpcode() == ISD::SHL_PARTS) {
6290 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6291 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6293 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6294 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6297 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6298 DAG.getConstant(VTBits, MVT::i8));
6299 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6300 AndNode, DAG.getConstant(0, MVT::i8));
6303 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6304 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6305 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6307 if (Op.getOpcode() == ISD::SHL_PARTS) {
6308 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6309 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6311 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6312 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6315 SDValue Ops[2] = { Lo, Hi };
6316 return DAG.getMergeValues(Ops, 2, dl);
6319 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6320 SelectionDAG &DAG) const {
6321 EVT SrcVT = Op.getOperand(0).getValueType();
6323 if (SrcVT.isVector()) {
6324 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
6330 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6331 "Unknown SINT_TO_FP to lower!");
6333 // These are really Legal; return the operand so the caller accepts it as
6335 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6337 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6338 Subtarget->is64Bit()) {
6342 DebugLoc dl = Op.getDebugLoc();
6343 unsigned Size = SrcVT.getSizeInBits()/8;
6344 MachineFunction &MF = DAG.getMachineFunction();
6345 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6346 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6347 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6349 MachinePointerInfo::getFixedStack(SSFI),
6351 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6354 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6356 SelectionDAG &DAG) const {
6358 DebugLoc dl = Op.getDebugLoc();
6360 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6362 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
6364 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6365 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6366 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
6367 Tys, Ops, array_lengthof(Ops));
6370 Chain = Result.getValue(1);
6371 SDValue InFlag = Result.getValue(2);
6373 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6374 // shouldn't be necessary except that RFP cannot be live across
6375 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6376 MachineFunction &MF = DAG.getMachineFunction();
6377 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6378 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6379 Tys = DAG.getVTList(MVT::Other);
6381 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6383 Chain = DAG.getNode(X86ISD::FST, dl, Tys, Ops, array_lengthof(Ops));
6384 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
6385 MachinePointerInfo::getFixedStack(SSFI),
6392 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6393 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6394 SelectionDAG &DAG) const {
6395 // This algorithm is not obvious. Here it is in C code, more or less:
6397 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6398 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6399 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6401 // Copy ints to xmm registers.
6402 __m128i xh = _mm_cvtsi32_si128( hi );
6403 __m128i xl = _mm_cvtsi32_si128( lo );
6405 // Combine into low half of a single xmm register.
6406 __m128i x = _mm_unpacklo_epi32( xh, xl );
6410 // Merge in appropriate exponents to give the integer bits the right
6412 x = _mm_unpacklo_epi32( x, exp );
6414 // Subtract away the biases to deal with the IEEE-754 double precision
6416 d = _mm_sub_pd( (__m128d) x, bias );
6418 // All conversions up to here are exact. The correctly rounded result is
6419 // calculated using the current rounding mode using the following
6421 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6422 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6423 // store doesn't really need to be here (except
6424 // maybe to zero the other double)
6429 DebugLoc dl = Op.getDebugLoc();
6430 LLVMContext *Context = DAG.getContext();
6432 // Build some magic constants.
6433 std::vector<Constant*> CV0;
6434 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6435 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6436 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6437 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6438 Constant *C0 = ConstantVector::get(CV0);
6439 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6441 std::vector<Constant*> CV1;
6443 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6445 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6446 Constant *C1 = ConstantVector::get(CV1);
6447 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6449 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6450 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6452 DAG.getIntPtrConstant(1)));
6453 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6454 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6456 DAG.getIntPtrConstant(0)));
6457 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6458 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6459 MachinePointerInfo::getConstantPool(),
6461 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6462 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
6463 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6464 MachinePointerInfo::getConstantPool(),
6466 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6468 // Add the halves; easiest way is to swap them into another reg first.
6469 int ShufMask[2] = { 1, -1 };
6470 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6471 DAG.getUNDEF(MVT::v2f64), ShufMask);
6472 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6473 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6474 DAG.getIntPtrConstant(0));
6477 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6478 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6479 SelectionDAG &DAG) const {
6480 DebugLoc dl = Op.getDebugLoc();
6481 // FP constant to bias correct the final result.
6482 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6485 // Load the 32-bit value into an XMM register.
6486 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6487 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6489 DAG.getIntPtrConstant(0)));
6491 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6492 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
6493 DAG.getIntPtrConstant(0));
6495 // Or the load with the bias.
6496 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6497 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6498 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6500 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6501 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6502 MVT::v2f64, Bias)));
6503 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6504 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
6505 DAG.getIntPtrConstant(0));
6507 // Subtract the bias.
6508 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6510 // Handle final rounding.
6511 EVT DestVT = Op.getValueType();
6513 if (DestVT.bitsLT(MVT::f64)) {
6514 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6515 DAG.getIntPtrConstant(0));
6516 } else if (DestVT.bitsGT(MVT::f64)) {
6517 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6520 // Handle final rounding.
6524 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6525 SelectionDAG &DAG) const {
6526 SDValue N0 = Op.getOperand(0);
6527 DebugLoc dl = Op.getDebugLoc();
6529 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6530 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6531 // the optimization here.
6532 if (DAG.SignBitIsZero(N0))
6533 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6535 EVT SrcVT = N0.getValueType();
6536 EVT DstVT = Op.getValueType();
6537 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6538 return LowerUINT_TO_FP_i64(Op, DAG);
6539 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6540 return LowerUINT_TO_FP_i32(Op, DAG);
6542 // Make a 64-bit buffer, and use it to build an FILD.
6543 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6544 if (SrcVT == MVT::i32) {
6545 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6546 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6547 getPointerTy(), StackSlot, WordOff);
6548 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6549 StackSlot, MachinePointerInfo(),
6551 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6552 OffsetSlot, MachinePointerInfo(),
6554 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6558 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6559 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6560 StackSlot, MachinePointerInfo(),
6562 // For i64 source, we need to add the appropriate power of 2 if the input
6563 // was negative. This is the same as the optimization in
6564 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6565 // we must be careful to do the computation in x87 extended precision, not
6566 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6567 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6568 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6569 SDValue Fild = DAG.getNode(X86ISD::FILD, dl, Tys, Ops, 3);
6571 APInt FF(32, 0x5F800000ULL);
6573 // Check whether the sign bit is set.
6574 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6575 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6578 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6579 SDValue FudgePtr = DAG.getConstantPool(
6580 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6583 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6584 SDValue Zero = DAG.getIntPtrConstant(0);
6585 SDValue Four = DAG.getIntPtrConstant(4);
6586 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6588 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6590 // Load the value out, extending it from f32 to f80.
6591 // FIXME: Avoid the extend by constructing the right constant pool?
6592 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6593 FudgePtr, MachinePointerInfo::getConstantPool(),
6594 MVT::f32, false, false, 4);
6595 // Extend everything to 80 bits to force it to be done on x87.
6596 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6597 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6600 std::pair<SDValue,SDValue> X86TargetLowering::
6601 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6602 DebugLoc dl = Op.getDebugLoc();
6604 EVT DstTy = Op.getValueType();
6607 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6611 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6612 DstTy.getSimpleVT() >= MVT::i16 &&
6613 "Unknown FP_TO_SINT to lower!");
6615 // These are really Legal.
6616 if (DstTy == MVT::i32 &&
6617 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6618 return std::make_pair(SDValue(), SDValue());
6619 if (Subtarget->is64Bit() &&
6620 DstTy == MVT::i64 &&
6621 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6622 return std::make_pair(SDValue(), SDValue());
6624 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6626 MachineFunction &MF = DAG.getMachineFunction();
6627 unsigned MemSize = DstTy.getSizeInBits()/8;
6628 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6629 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6632 switch (DstTy.getSimpleVT().SimpleTy) {
6633 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6634 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6635 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6636 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6639 SDValue Chain = DAG.getEntryNode();
6640 SDValue Value = Op.getOperand(0);
6641 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
6642 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6643 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
6644 MachinePointerInfo::getFixedStack(SSFI),
6646 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6648 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
6650 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
6651 Chain = Value.getValue(1);
6652 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6653 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6656 // Build the FP_TO_INT*_IN_MEM
6657 SDValue Ops[] = { Chain, Value, StackSlot };
6658 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
6660 return std::make_pair(FIST, StackSlot);
6663 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6664 SelectionDAG &DAG) const {
6665 if (Op.getValueType().isVector()) {
6666 if (Op.getValueType() == MVT::v2i32 &&
6667 Op.getOperand(0).getValueType() == MVT::v2f64) {
6673 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6674 SDValue FIST = Vals.first, StackSlot = Vals.second;
6675 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6676 if (FIST.getNode() == 0) return Op;
6679 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6680 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6683 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6684 SelectionDAG &DAG) const {
6685 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6686 SDValue FIST = Vals.first, StackSlot = Vals.second;
6687 assert(FIST.getNode() && "Unexpected failure");
6690 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6691 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6694 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6695 SelectionDAG &DAG) const {
6696 LLVMContext *Context = DAG.getContext();
6697 DebugLoc dl = Op.getDebugLoc();
6698 EVT VT = Op.getValueType();
6701 EltVT = VT.getVectorElementType();
6702 std::vector<Constant*> CV;
6703 if (EltVT == MVT::f64) {
6704 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6708 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6714 Constant *C = ConstantVector::get(CV);
6715 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6716 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6717 MachinePointerInfo::getConstantPool(),
6719 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6722 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6723 LLVMContext *Context = DAG.getContext();
6724 DebugLoc dl = Op.getDebugLoc();
6725 EVT VT = Op.getValueType();
6728 EltVT = VT.getVectorElementType();
6729 std::vector<Constant*> CV;
6730 if (EltVT == MVT::f64) {
6731 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6735 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6741 Constant *C = ConstantVector::get(CV);
6742 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6743 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6744 MachinePointerInfo::getConstantPool(),
6746 if (VT.isVector()) {
6747 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6748 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6749 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
6751 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
6753 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6757 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6758 LLVMContext *Context = DAG.getContext();
6759 SDValue Op0 = Op.getOperand(0);
6760 SDValue Op1 = Op.getOperand(1);
6761 DebugLoc dl = Op.getDebugLoc();
6762 EVT VT = Op.getValueType();
6763 EVT SrcVT = Op1.getValueType();
6765 // If second operand is smaller, extend it first.
6766 if (SrcVT.bitsLT(VT)) {
6767 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6770 // And if it is bigger, shrink it first.
6771 if (SrcVT.bitsGT(VT)) {
6772 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6776 // At this point the operands and the result should have the same
6777 // type, and that won't be f80 since that is not custom lowered.
6779 // First get the sign bit of second operand.
6780 std::vector<Constant*> CV;
6781 if (SrcVT == MVT::f64) {
6782 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6783 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6785 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6786 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6787 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6788 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6790 Constant *C = ConstantVector::get(CV);
6791 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6792 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6793 MachinePointerInfo::getConstantPool(),
6795 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6797 // Shift sign bit right or left if the two operands have different types.
6798 if (SrcVT.bitsGT(VT)) {
6799 // Op0 is MVT::f32, Op1 is MVT::f64.
6800 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6801 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6802 DAG.getConstant(32, MVT::i32));
6803 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
6804 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6805 DAG.getIntPtrConstant(0));
6808 // Clear first operand sign bit.
6810 if (VT == MVT::f64) {
6811 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6812 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6814 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6815 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6816 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6817 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6819 C = ConstantVector::get(CV);
6820 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6821 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6822 MachinePointerInfo::getConstantPool(),
6824 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6826 // Or the value with the sign bit.
6827 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6830 /// Emit nodes that will be selected as "test Op0,Op0", or something
6832 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6833 SelectionDAG &DAG) const {
6834 DebugLoc dl = Op.getDebugLoc();
6836 // CF and OF aren't always set the way we want. Determine which
6837 // of these we need.
6838 bool NeedCF = false;
6839 bool NeedOF = false;
6842 case X86::COND_A: case X86::COND_AE:
6843 case X86::COND_B: case X86::COND_BE:
6846 case X86::COND_G: case X86::COND_GE:
6847 case X86::COND_L: case X86::COND_LE:
6848 case X86::COND_O: case X86::COND_NO:
6853 // See if we can use the EFLAGS value from the operand instead of
6854 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6855 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6856 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6857 // Emit a CMP with 0, which is the TEST pattern.
6858 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6859 DAG.getConstant(0, Op.getValueType()));
6861 unsigned Opcode = 0;
6862 unsigned NumOperands = 0;
6863 switch (Op.getNode()->getOpcode()) {
6865 // Due to an isel shortcoming, be conservative if this add is likely to be
6866 // selected as part of a load-modify-store instruction. When the root node
6867 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6868 // uses of other nodes in the match, such as the ADD in this case. This
6869 // leads to the ADD being left around and reselected, with the result being
6870 // two adds in the output. Alas, even if none our users are stores, that
6871 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6872 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6873 // climbing the DAG back to the root, and it doesn't seem to be worth the
6875 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6876 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6877 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6880 if (ConstantSDNode *C =
6881 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6882 // An add of one will be selected as an INC.
6883 if (C->getAPIntValue() == 1) {
6884 Opcode = X86ISD::INC;
6889 // An add of negative one (subtract of one) will be selected as a DEC.
6890 if (C->getAPIntValue().isAllOnesValue()) {
6891 Opcode = X86ISD::DEC;
6897 // Otherwise use a regular EFLAGS-setting add.
6898 Opcode = X86ISD::ADD;
6902 // If the primary and result isn't used, don't bother using X86ISD::AND,
6903 // because a TEST instruction will be better.
6904 bool NonFlagUse = false;
6905 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6906 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6908 unsigned UOpNo = UI.getOperandNo();
6909 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6910 // Look pass truncate.
6911 UOpNo = User->use_begin().getOperandNo();
6912 User = *User->use_begin();
6915 if (User->getOpcode() != ISD::BRCOND &&
6916 User->getOpcode() != ISD::SETCC &&
6917 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6930 // Due to the ISEL shortcoming noted above, be conservative if this op is
6931 // likely to be selected as part of a load-modify-store instruction.
6932 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6933 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6934 if (UI->getOpcode() == ISD::STORE)
6937 // Otherwise use a regular EFLAGS-setting instruction.
6938 switch (Op.getNode()->getOpcode()) {
6939 default: llvm_unreachable("unexpected operator!");
6940 case ISD::SUB: Opcode = X86ISD::SUB; break;
6941 case ISD::OR: Opcode = X86ISD::OR; break;
6942 case ISD::XOR: Opcode = X86ISD::XOR; break;
6943 case ISD::AND: Opcode = X86ISD::AND; break;
6955 return SDValue(Op.getNode(), 1);
6962 // Emit a CMP with 0, which is the TEST pattern.
6963 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6964 DAG.getConstant(0, Op.getValueType()));
6966 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6967 SmallVector<SDValue, 4> Ops;
6968 for (unsigned i = 0; i != NumOperands; ++i)
6969 Ops.push_back(Op.getOperand(i));
6971 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6972 DAG.ReplaceAllUsesWith(Op, New);
6973 return SDValue(New.getNode(), 1);
6976 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6978 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6979 SelectionDAG &DAG) const {
6980 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6981 if (C->getAPIntValue() == 0)
6982 return EmitTest(Op0, X86CC, DAG);
6984 DebugLoc dl = Op0.getDebugLoc();
6985 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6988 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6989 /// if it's possible.
6990 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6991 DebugLoc dl, SelectionDAG &DAG) const {
6992 SDValue Op0 = And.getOperand(0);
6993 SDValue Op1 = And.getOperand(1);
6994 if (Op0.getOpcode() == ISD::TRUNCATE)
6995 Op0 = Op0.getOperand(0);
6996 if (Op1.getOpcode() == ISD::TRUNCATE)
6997 Op1 = Op1.getOperand(0);
7000 if (Op1.getOpcode() == ISD::SHL)
7001 std::swap(Op0, Op1);
7002 if (Op0.getOpcode() == ISD::SHL) {
7003 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
7004 if (And00C->getZExtValue() == 1) {
7005 // If we looked past a truncate, check that it's only truncating away
7007 unsigned BitWidth = Op0.getValueSizeInBits();
7008 unsigned AndBitWidth = And.getValueSizeInBits();
7009 if (BitWidth > AndBitWidth) {
7010 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
7011 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
7012 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
7016 RHS = Op0.getOperand(1);
7018 } else if (Op1.getOpcode() == ISD::Constant) {
7019 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
7020 SDValue AndLHS = Op0;
7021 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
7022 LHS = AndLHS.getOperand(0);
7023 RHS = AndLHS.getOperand(1);
7027 if (LHS.getNode()) {
7028 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
7029 // instruction. Since the shift amount is in-range-or-undefined, we know
7030 // that doing a bittest on the i32 value is ok. We extend to i32 because
7031 // the encoding for the i16 version is larger than the i32 version.
7032 // Also promote i16 to i32 for performance / code size reason.
7033 if (LHS.getValueType() == MVT::i8 ||
7034 LHS.getValueType() == MVT::i16)
7035 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7037 // If the operand types disagree, extend the shift amount to match. Since
7038 // BT ignores high bits (like shifts) we can use anyextend.
7039 if (LHS.getValueType() != RHS.getValueType())
7040 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7042 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7043 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7044 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7045 DAG.getConstant(Cond, MVT::i8), BT);
7051 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7052 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7053 SDValue Op0 = Op.getOperand(0);
7054 SDValue Op1 = Op.getOperand(1);
7055 DebugLoc dl = Op.getDebugLoc();
7056 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7058 // Optimize to BT if possible.
7059 // Lower (X & (1 << N)) == 0 to BT(X, N).
7060 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7061 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7062 if (Op0.getOpcode() == ISD::AND &&
7064 Op1.getOpcode() == ISD::Constant &&
7065 cast<ConstantSDNode>(Op1)->isNullValue() &&
7066 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7067 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7068 if (NewSetCC.getNode())
7072 // Look for "(setcc) == / != 1" to avoid unncessary setcc.
7073 if (Op0.getOpcode() == X86ISD::SETCC &&
7074 Op1.getOpcode() == ISD::Constant &&
7075 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7076 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7077 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7078 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7079 bool Invert = (CC == ISD::SETNE) ^
7080 cast<ConstantSDNode>(Op1)->isNullValue();
7082 CCode = X86::GetOppositeBranchCondition(CCode);
7083 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7084 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7087 bool isFP = Op1.getValueType().isFloatingPoint();
7088 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7089 if (X86CC == X86::COND_INVALID)
7092 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
7094 // Use sbb x, x to materialize carry bit into a GPR.
7095 if (X86CC == X86::COND_B)
7096 return DAG.getNode(ISD::AND, dl, MVT::i8,
7097 DAG.getNode(X86ISD::SETCC_CARRY, dl, MVT::i8,
7098 DAG.getConstant(X86CC, MVT::i8), Cond),
7099 DAG.getConstant(1, MVT::i8));
7101 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7102 DAG.getConstant(X86CC, MVT::i8), Cond);
7105 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7107 SDValue Op0 = Op.getOperand(0);
7108 SDValue Op1 = Op.getOperand(1);
7109 SDValue CC = Op.getOperand(2);
7110 EVT VT = Op.getValueType();
7111 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7112 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7113 DebugLoc dl = Op.getDebugLoc();
7117 EVT VT0 = Op0.getValueType();
7118 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7119 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7122 switch (SetCCOpcode) {
7125 case ISD::SETEQ: SSECC = 0; break;
7127 case ISD::SETGT: Swap = true; // Fallthrough
7129 case ISD::SETOLT: SSECC = 1; break;
7131 case ISD::SETGE: Swap = true; // Fallthrough
7133 case ISD::SETOLE: SSECC = 2; break;
7134 case ISD::SETUO: SSECC = 3; break;
7136 case ISD::SETNE: SSECC = 4; break;
7137 case ISD::SETULE: Swap = true;
7138 case ISD::SETUGE: SSECC = 5; break;
7139 case ISD::SETULT: Swap = true;
7140 case ISD::SETUGT: SSECC = 6; break;
7141 case ISD::SETO: SSECC = 7; break;
7144 std::swap(Op0, Op1);
7146 // In the two special cases we can't handle, emit two comparisons.
7148 if (SetCCOpcode == ISD::SETUEQ) {
7150 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7151 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7152 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7154 else if (SetCCOpcode == ISD::SETONE) {
7156 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7157 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7158 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7160 llvm_unreachable("Illegal FP comparison");
7162 // Handle all other FP comparisons here.
7163 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7166 // We are handling one of the integer comparisons here. Since SSE only has
7167 // GT and EQ comparisons for integer, swapping operands and multiple
7168 // operations may be required for some comparisons.
7169 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7170 bool Swap = false, Invert = false, FlipSigns = false;
7172 switch (VT.getSimpleVT().SimpleTy) {
7175 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7177 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7179 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7180 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7183 switch (SetCCOpcode) {
7185 case ISD::SETNE: Invert = true;
7186 case ISD::SETEQ: Opc = EQOpc; break;
7187 case ISD::SETLT: Swap = true;
7188 case ISD::SETGT: Opc = GTOpc; break;
7189 case ISD::SETGE: Swap = true;
7190 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7191 case ISD::SETULT: Swap = true;
7192 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7193 case ISD::SETUGE: Swap = true;
7194 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7197 std::swap(Op0, Op1);
7199 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7200 // bits of the inputs before performing those operations.
7202 EVT EltVT = VT.getVectorElementType();
7203 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7205 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7206 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7208 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7209 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7212 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7214 // If the logical-not of the result is required, perform that now.
7216 Result = DAG.getNOT(dl, Result, VT);
7221 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7222 static bool isX86LogicalCmp(SDValue Op) {
7223 unsigned Opc = Op.getNode()->getOpcode();
7224 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7226 if (Op.getResNo() == 1 &&
7227 (Opc == X86ISD::ADD ||
7228 Opc == X86ISD::SUB ||
7229 Opc == X86ISD::SMUL ||
7230 Opc == X86ISD::UMUL ||
7231 Opc == X86ISD::INC ||
7232 Opc == X86ISD::DEC ||
7233 Opc == X86ISD::OR ||
7234 Opc == X86ISD::XOR ||
7235 Opc == X86ISD::AND))
7241 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7242 bool addTest = true;
7243 SDValue Cond = Op.getOperand(0);
7244 DebugLoc dl = Op.getDebugLoc();
7247 if (Cond.getOpcode() == ISD::SETCC) {
7248 SDValue NewCond = LowerSETCC(Cond, DAG);
7249 if (NewCond.getNode())
7253 // (select (x == 0), -1, 0) -> (sign_bit (x - 1))
7254 SDValue Op1 = Op.getOperand(1);
7255 SDValue Op2 = Op.getOperand(2);
7256 if (Cond.getOpcode() == X86ISD::SETCC &&
7257 cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue() == X86::COND_E) {
7258 SDValue Cmp = Cond.getOperand(1);
7259 if (Cmp.getOpcode() == X86ISD::CMP) {
7260 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op1);
7261 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7262 ConstantSDNode *RHSC =
7263 dyn_cast<ConstantSDNode>(Cmp.getOperand(1).getNode());
7264 if (N1C && N1C->isAllOnesValue() &&
7265 N2C && N2C->isNullValue() &&
7266 RHSC && RHSC->isNullValue()) {
7267 SDValue CmpOp0 = Cmp.getOperand(0);
7268 Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7269 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7270 return DAG.getNode(X86ISD::SETCC_CARRY, dl, Op.getValueType(),
7271 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7276 // Look pass (and (setcc_carry (cmp ...)), 1).
7277 if (Cond.getOpcode() == ISD::AND &&
7278 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7279 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7280 if (C && C->getAPIntValue() == 1)
7281 Cond = Cond.getOperand(0);
7284 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7285 // setting operand in place of the X86ISD::SETCC.
7286 if (Cond.getOpcode() == X86ISD::SETCC ||
7287 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7288 CC = Cond.getOperand(0);
7290 SDValue Cmp = Cond.getOperand(1);
7291 unsigned Opc = Cmp.getOpcode();
7292 EVT VT = Op.getValueType();
7294 bool IllegalFPCMov = false;
7295 if (VT.isFloatingPoint() && !VT.isVector() &&
7296 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7297 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7299 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7300 Opc == X86ISD::BT) { // FIXME
7307 // Look pass the truncate.
7308 if (Cond.getOpcode() == ISD::TRUNCATE)
7309 Cond = Cond.getOperand(0);
7311 // We know the result of AND is compared against zero. Try to match
7313 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7314 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7315 if (NewSetCC.getNode()) {
7316 CC = NewSetCC.getOperand(0);
7317 Cond = NewSetCC.getOperand(1);
7324 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7325 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7328 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7329 // condition is true.
7330 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
7331 SDValue Ops[] = { Op2, Op1, CC, Cond };
7332 return DAG.getNode(X86ISD::CMOV, dl, VTs, Ops, array_lengthof(Ops));
7335 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7336 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7337 // from the AND / OR.
7338 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7339 Opc = Op.getOpcode();
7340 if (Opc != ISD::OR && Opc != ISD::AND)
7342 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7343 Op.getOperand(0).hasOneUse() &&
7344 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7345 Op.getOperand(1).hasOneUse());
7348 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7349 // 1 and that the SETCC node has a single use.
7350 static bool isXor1OfSetCC(SDValue Op) {
7351 if (Op.getOpcode() != ISD::XOR)
7353 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7354 if (N1C && N1C->getAPIntValue() == 1) {
7355 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7356 Op.getOperand(0).hasOneUse();
7361 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7362 bool addTest = true;
7363 SDValue Chain = Op.getOperand(0);
7364 SDValue Cond = Op.getOperand(1);
7365 SDValue Dest = Op.getOperand(2);
7366 DebugLoc dl = Op.getDebugLoc();
7369 if (Cond.getOpcode() == ISD::SETCC) {
7370 SDValue NewCond = LowerSETCC(Cond, DAG);
7371 if (NewCond.getNode())
7375 // FIXME: LowerXALUO doesn't handle these!!
7376 else if (Cond.getOpcode() == X86ISD::ADD ||
7377 Cond.getOpcode() == X86ISD::SUB ||
7378 Cond.getOpcode() == X86ISD::SMUL ||
7379 Cond.getOpcode() == X86ISD::UMUL)
7380 Cond = LowerXALUO(Cond, DAG);
7383 // Look pass (and (setcc_carry (cmp ...)), 1).
7384 if (Cond.getOpcode() == ISD::AND &&
7385 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7386 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7387 if (C && C->getAPIntValue() == 1)
7388 Cond = Cond.getOperand(0);
7391 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7392 // setting operand in place of the X86ISD::SETCC.
7393 if (Cond.getOpcode() == X86ISD::SETCC ||
7394 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7395 CC = Cond.getOperand(0);
7397 SDValue Cmp = Cond.getOperand(1);
7398 unsigned Opc = Cmp.getOpcode();
7399 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7400 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7404 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7408 // These can only come from an arithmetic instruction with overflow,
7409 // e.g. SADDO, UADDO.
7410 Cond = Cond.getNode()->getOperand(1);
7417 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7418 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7419 if (CondOpc == ISD::OR) {
7420 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7421 // two branches instead of an explicit OR instruction with a
7423 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7424 isX86LogicalCmp(Cmp)) {
7425 CC = Cond.getOperand(0).getOperand(0);
7426 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7427 Chain, Dest, CC, Cmp);
7428 CC = Cond.getOperand(1).getOperand(0);
7432 } else { // ISD::AND
7433 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7434 // two branches instead of an explicit AND instruction with a
7435 // separate test. However, we only do this if this block doesn't
7436 // have a fall-through edge, because this requires an explicit
7437 // jmp when the condition is false.
7438 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7439 isX86LogicalCmp(Cmp) &&
7440 Op.getNode()->hasOneUse()) {
7441 X86::CondCode CCode =
7442 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7443 CCode = X86::GetOppositeBranchCondition(CCode);
7444 CC = DAG.getConstant(CCode, MVT::i8);
7445 SDNode *User = *Op.getNode()->use_begin();
7446 // Look for an unconditional branch following this conditional branch.
7447 // We need this because we need to reverse the successors in order
7448 // to implement FCMP_OEQ.
7449 if (User->getOpcode() == ISD::BR) {
7450 SDValue FalseBB = User->getOperand(1);
7452 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7453 assert(NewBR == User);
7457 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7458 Chain, Dest, CC, Cmp);
7459 X86::CondCode CCode =
7460 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7461 CCode = X86::GetOppositeBranchCondition(CCode);
7462 CC = DAG.getConstant(CCode, MVT::i8);
7468 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7469 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7470 // It should be transformed during dag combiner except when the condition
7471 // is set by a arithmetics with overflow node.
7472 X86::CondCode CCode =
7473 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7474 CCode = X86::GetOppositeBranchCondition(CCode);
7475 CC = DAG.getConstant(CCode, MVT::i8);
7476 Cond = Cond.getOperand(0).getOperand(1);
7482 // Look pass the truncate.
7483 if (Cond.getOpcode() == ISD::TRUNCATE)
7484 Cond = Cond.getOperand(0);
7486 // We know the result of AND is compared against zero. Try to match
7488 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7489 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7490 if (NewSetCC.getNode()) {
7491 CC = NewSetCC.getOperand(0);
7492 Cond = NewSetCC.getOperand(1);
7499 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7500 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7502 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7503 Chain, Dest, CC, Cond);
7507 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7508 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7509 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7510 // that the guard pages used by the OS virtual memory manager are allocated in
7511 // correct sequence.
7513 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7514 SelectionDAG &DAG) const {
7515 assert(Subtarget->isTargetCygMing() &&
7516 "This should be used only on Cygwin/Mingw targets");
7517 DebugLoc dl = Op.getDebugLoc();
7520 SDValue Chain = Op.getOperand(0);
7521 SDValue Size = Op.getOperand(1);
7522 // FIXME: Ensure alignment here
7526 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7528 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7529 Flag = Chain.getValue(1);
7531 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
7533 Chain = DAG.getNode(X86ISD::MINGW_ALLOCA, dl, NodeTys, Chain, Flag);
7534 Flag = Chain.getValue(1);
7536 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7538 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7539 return DAG.getMergeValues(Ops1, 2, dl);
7542 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7543 MachineFunction &MF = DAG.getMachineFunction();
7544 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7546 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7547 DebugLoc DL = Op.getDebugLoc();
7549 if (!Subtarget->is64Bit()) {
7550 // vastart just stores the address of the VarArgsFrameIndex slot into the
7551 // memory location argument.
7552 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7554 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7555 MachinePointerInfo(SV), false, false, 0);
7559 // gp_offset (0 - 6 * 8)
7560 // fp_offset (48 - 48 + 8 * 16)
7561 // overflow_arg_area (point to parameters coming in memory).
7563 SmallVector<SDValue, 8> MemOps;
7564 SDValue FIN = Op.getOperand(1);
7566 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7567 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7569 FIN, MachinePointerInfo(SV), false, false, 0);
7570 MemOps.push_back(Store);
7573 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7574 FIN, DAG.getIntPtrConstant(4));
7575 Store = DAG.getStore(Op.getOperand(0), DL,
7576 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7578 FIN, MachinePointerInfo(SV, 4), false, false, 0);
7579 MemOps.push_back(Store);
7581 // Store ptr to overflow_arg_area
7582 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7583 FIN, DAG.getIntPtrConstant(4));
7584 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7586 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
7587 MachinePointerInfo(SV, 8),
7589 MemOps.push_back(Store);
7591 // Store ptr to reg_save_area.
7592 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7593 FIN, DAG.getIntPtrConstant(8));
7594 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7596 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
7597 MachinePointerInfo(SV, 16), false, false, 0);
7598 MemOps.push_back(Store);
7599 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
7600 &MemOps[0], MemOps.size());
7603 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7604 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7605 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
7607 report_fatal_error("VAArgInst is not yet implemented for x86-64!");
7611 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7612 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7613 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7614 SDValue Chain = Op.getOperand(0);
7615 SDValue DstPtr = Op.getOperand(1);
7616 SDValue SrcPtr = Op.getOperand(2);
7617 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7618 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7619 DebugLoc DL = Op.getDebugLoc();
7621 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
7622 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7624 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
7628 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7629 DebugLoc dl = Op.getDebugLoc();
7630 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7632 default: return SDValue(); // Don't custom lower most intrinsics.
7633 // Comparison intrinsics.
7634 case Intrinsic::x86_sse_comieq_ss:
7635 case Intrinsic::x86_sse_comilt_ss:
7636 case Intrinsic::x86_sse_comile_ss:
7637 case Intrinsic::x86_sse_comigt_ss:
7638 case Intrinsic::x86_sse_comige_ss:
7639 case Intrinsic::x86_sse_comineq_ss:
7640 case Intrinsic::x86_sse_ucomieq_ss:
7641 case Intrinsic::x86_sse_ucomilt_ss:
7642 case Intrinsic::x86_sse_ucomile_ss:
7643 case Intrinsic::x86_sse_ucomigt_ss:
7644 case Intrinsic::x86_sse_ucomige_ss:
7645 case Intrinsic::x86_sse_ucomineq_ss:
7646 case Intrinsic::x86_sse2_comieq_sd:
7647 case Intrinsic::x86_sse2_comilt_sd:
7648 case Intrinsic::x86_sse2_comile_sd:
7649 case Intrinsic::x86_sse2_comigt_sd:
7650 case Intrinsic::x86_sse2_comige_sd:
7651 case Intrinsic::x86_sse2_comineq_sd:
7652 case Intrinsic::x86_sse2_ucomieq_sd:
7653 case Intrinsic::x86_sse2_ucomilt_sd:
7654 case Intrinsic::x86_sse2_ucomile_sd:
7655 case Intrinsic::x86_sse2_ucomigt_sd:
7656 case Intrinsic::x86_sse2_ucomige_sd:
7657 case Intrinsic::x86_sse2_ucomineq_sd: {
7659 ISD::CondCode CC = ISD::SETCC_INVALID;
7662 case Intrinsic::x86_sse_comieq_ss:
7663 case Intrinsic::x86_sse2_comieq_sd:
7667 case Intrinsic::x86_sse_comilt_ss:
7668 case Intrinsic::x86_sse2_comilt_sd:
7672 case Intrinsic::x86_sse_comile_ss:
7673 case Intrinsic::x86_sse2_comile_sd:
7677 case Intrinsic::x86_sse_comigt_ss:
7678 case Intrinsic::x86_sse2_comigt_sd:
7682 case Intrinsic::x86_sse_comige_ss:
7683 case Intrinsic::x86_sse2_comige_sd:
7687 case Intrinsic::x86_sse_comineq_ss:
7688 case Intrinsic::x86_sse2_comineq_sd:
7692 case Intrinsic::x86_sse_ucomieq_ss:
7693 case Intrinsic::x86_sse2_ucomieq_sd:
7694 Opc = X86ISD::UCOMI;
7697 case Intrinsic::x86_sse_ucomilt_ss:
7698 case Intrinsic::x86_sse2_ucomilt_sd:
7699 Opc = X86ISD::UCOMI;
7702 case Intrinsic::x86_sse_ucomile_ss:
7703 case Intrinsic::x86_sse2_ucomile_sd:
7704 Opc = X86ISD::UCOMI;
7707 case Intrinsic::x86_sse_ucomigt_ss:
7708 case Intrinsic::x86_sse2_ucomigt_sd:
7709 Opc = X86ISD::UCOMI;
7712 case Intrinsic::x86_sse_ucomige_ss:
7713 case Intrinsic::x86_sse2_ucomige_sd:
7714 Opc = X86ISD::UCOMI;
7717 case Intrinsic::x86_sse_ucomineq_ss:
7718 case Intrinsic::x86_sse2_ucomineq_sd:
7719 Opc = X86ISD::UCOMI;
7724 SDValue LHS = Op.getOperand(1);
7725 SDValue RHS = Op.getOperand(2);
7726 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7727 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7728 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7729 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7730 DAG.getConstant(X86CC, MVT::i8), Cond);
7731 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7733 // ptest and testp intrinsics. The intrinsic these come from are designed to
7734 // return an integer value, not just an instruction so lower it to the ptest
7735 // or testp pattern and a setcc for the result.
7736 case Intrinsic::x86_sse41_ptestz:
7737 case Intrinsic::x86_sse41_ptestc:
7738 case Intrinsic::x86_sse41_ptestnzc:
7739 case Intrinsic::x86_avx_ptestz_256:
7740 case Intrinsic::x86_avx_ptestc_256:
7741 case Intrinsic::x86_avx_ptestnzc_256:
7742 case Intrinsic::x86_avx_vtestz_ps:
7743 case Intrinsic::x86_avx_vtestc_ps:
7744 case Intrinsic::x86_avx_vtestnzc_ps:
7745 case Intrinsic::x86_avx_vtestz_pd:
7746 case Intrinsic::x86_avx_vtestc_pd:
7747 case Intrinsic::x86_avx_vtestnzc_pd:
7748 case Intrinsic::x86_avx_vtestz_ps_256:
7749 case Intrinsic::x86_avx_vtestc_ps_256:
7750 case Intrinsic::x86_avx_vtestnzc_ps_256:
7751 case Intrinsic::x86_avx_vtestz_pd_256:
7752 case Intrinsic::x86_avx_vtestc_pd_256:
7753 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7754 bool IsTestPacked = false;
7757 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7758 case Intrinsic::x86_avx_vtestz_ps:
7759 case Intrinsic::x86_avx_vtestz_pd:
7760 case Intrinsic::x86_avx_vtestz_ps_256:
7761 case Intrinsic::x86_avx_vtestz_pd_256:
7762 IsTestPacked = true; // Fallthrough
7763 case Intrinsic::x86_sse41_ptestz:
7764 case Intrinsic::x86_avx_ptestz_256:
7766 X86CC = X86::COND_E;
7768 case Intrinsic::x86_avx_vtestc_ps:
7769 case Intrinsic::x86_avx_vtestc_pd:
7770 case Intrinsic::x86_avx_vtestc_ps_256:
7771 case Intrinsic::x86_avx_vtestc_pd_256:
7772 IsTestPacked = true; // Fallthrough
7773 case Intrinsic::x86_sse41_ptestc:
7774 case Intrinsic::x86_avx_ptestc_256:
7776 X86CC = X86::COND_B;
7778 case Intrinsic::x86_avx_vtestnzc_ps:
7779 case Intrinsic::x86_avx_vtestnzc_pd:
7780 case Intrinsic::x86_avx_vtestnzc_ps_256:
7781 case Intrinsic::x86_avx_vtestnzc_pd_256:
7782 IsTestPacked = true; // Fallthrough
7783 case Intrinsic::x86_sse41_ptestnzc:
7784 case Intrinsic::x86_avx_ptestnzc_256:
7786 X86CC = X86::COND_A;
7790 SDValue LHS = Op.getOperand(1);
7791 SDValue RHS = Op.getOperand(2);
7792 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7793 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7794 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7795 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7796 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7799 // Fix vector shift instructions where the last operand is a non-immediate
7801 case Intrinsic::x86_sse2_pslli_w:
7802 case Intrinsic::x86_sse2_pslli_d:
7803 case Intrinsic::x86_sse2_pslli_q:
7804 case Intrinsic::x86_sse2_psrli_w:
7805 case Intrinsic::x86_sse2_psrli_d:
7806 case Intrinsic::x86_sse2_psrli_q:
7807 case Intrinsic::x86_sse2_psrai_w:
7808 case Intrinsic::x86_sse2_psrai_d:
7809 case Intrinsic::x86_mmx_pslli_w:
7810 case Intrinsic::x86_mmx_pslli_d:
7811 case Intrinsic::x86_mmx_pslli_q:
7812 case Intrinsic::x86_mmx_psrli_w:
7813 case Intrinsic::x86_mmx_psrli_d:
7814 case Intrinsic::x86_mmx_psrli_q:
7815 case Intrinsic::x86_mmx_psrai_w:
7816 case Intrinsic::x86_mmx_psrai_d: {
7817 SDValue ShAmt = Op.getOperand(2);
7818 if (isa<ConstantSDNode>(ShAmt))
7821 unsigned NewIntNo = 0;
7822 EVT ShAmtVT = MVT::v4i32;
7824 case Intrinsic::x86_sse2_pslli_w:
7825 NewIntNo = Intrinsic::x86_sse2_psll_w;
7827 case Intrinsic::x86_sse2_pslli_d:
7828 NewIntNo = Intrinsic::x86_sse2_psll_d;
7830 case Intrinsic::x86_sse2_pslli_q:
7831 NewIntNo = Intrinsic::x86_sse2_psll_q;
7833 case Intrinsic::x86_sse2_psrli_w:
7834 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7836 case Intrinsic::x86_sse2_psrli_d:
7837 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7839 case Intrinsic::x86_sse2_psrli_q:
7840 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7842 case Intrinsic::x86_sse2_psrai_w:
7843 NewIntNo = Intrinsic::x86_sse2_psra_w;
7845 case Intrinsic::x86_sse2_psrai_d:
7846 NewIntNo = Intrinsic::x86_sse2_psra_d;
7849 ShAmtVT = MVT::v2i32;
7851 case Intrinsic::x86_mmx_pslli_w:
7852 NewIntNo = Intrinsic::x86_mmx_psll_w;
7854 case Intrinsic::x86_mmx_pslli_d:
7855 NewIntNo = Intrinsic::x86_mmx_psll_d;
7857 case Intrinsic::x86_mmx_pslli_q:
7858 NewIntNo = Intrinsic::x86_mmx_psll_q;
7860 case Intrinsic::x86_mmx_psrli_w:
7861 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7863 case Intrinsic::x86_mmx_psrli_d:
7864 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7866 case Intrinsic::x86_mmx_psrli_q:
7867 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7869 case Intrinsic::x86_mmx_psrai_w:
7870 NewIntNo = Intrinsic::x86_mmx_psra_w;
7872 case Intrinsic::x86_mmx_psrai_d:
7873 NewIntNo = Intrinsic::x86_mmx_psra_d;
7875 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7881 // The vector shift intrinsics with scalars uses 32b shift amounts but
7882 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7886 ShOps[1] = DAG.getConstant(0, MVT::i32);
7887 if (ShAmtVT == MVT::v4i32) {
7888 ShOps[2] = DAG.getUNDEF(MVT::i32);
7889 ShOps[3] = DAG.getUNDEF(MVT::i32);
7890 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7892 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7895 EVT VT = Op.getValueType();
7896 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
7897 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7898 DAG.getConstant(NewIntNo, MVT::i32),
7899 Op.getOperand(1), ShAmt);
7904 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7905 SelectionDAG &DAG) const {
7906 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7907 MFI->setReturnAddressIsTaken(true);
7909 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7910 DebugLoc dl = Op.getDebugLoc();
7913 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7915 DAG.getConstant(TD->getPointerSize(),
7916 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7917 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7918 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7920 MachinePointerInfo(), false, false, 0);
7923 // Just load the return address.
7924 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7925 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7926 RetAddrFI, MachinePointerInfo(), false, false, 0);
7929 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7930 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7931 MFI->setFrameAddressIsTaken(true);
7933 EVT VT = Op.getValueType();
7934 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
7935 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7936 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
7937 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
7939 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
7940 MachinePointerInfo(),
7945 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
7946 SelectionDAG &DAG) const {
7947 return DAG.getIntPtrConstant(2*TD->getPointerSize());
7950 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
7951 MachineFunction &MF = DAG.getMachineFunction();
7952 SDValue Chain = Op.getOperand(0);
7953 SDValue Offset = Op.getOperand(1);
7954 SDValue Handler = Op.getOperand(2);
7955 DebugLoc dl = Op.getDebugLoc();
7957 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
7958 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
7960 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
7962 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
7963 DAG.getIntPtrConstant(TD->getPointerSize()));
7964 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
7965 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
7967 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
7968 MF.getRegInfo().addLiveOut(StoreAddrReg);
7970 return DAG.getNode(X86ISD::EH_RETURN, dl,
7972 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
7975 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
7976 SelectionDAG &DAG) const {
7977 SDValue Root = Op.getOperand(0);
7978 SDValue Trmp = Op.getOperand(1); // trampoline
7979 SDValue FPtr = Op.getOperand(2); // nested function
7980 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
7981 DebugLoc dl = Op.getDebugLoc();
7983 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7985 if (Subtarget->is64Bit()) {
7986 SDValue OutChains[6];
7988 // Large code-model.
7989 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
7990 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
7992 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
7993 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
7995 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
7997 // Load the pointer to the nested function into R11.
7998 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
7999 SDValue Addr = Trmp;
8000 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8001 Addr, MachinePointerInfo(TrmpAddr),
8004 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8005 DAG.getConstant(2, MVT::i64));
8006 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8007 MachinePointerInfo(TrmpAddr, 2),
8010 // Load the 'nest' parameter value into R10.
8011 // R10 is specified in X86CallingConv.td
8012 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8013 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8014 DAG.getConstant(10, MVT::i64));
8015 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8016 Addr, MachinePointerInfo(TrmpAddr, 10),
8019 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8020 DAG.getConstant(12, MVT::i64));
8021 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8022 MachinePointerInfo(TrmpAddr, 12),
8025 // Jump to the nested function.
8026 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8027 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8028 DAG.getConstant(20, MVT::i64));
8029 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8030 Addr, MachinePointerInfo(TrmpAddr, 20),
8033 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8034 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8035 DAG.getConstant(22, MVT::i64));
8036 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8037 MachinePointerInfo(TrmpAddr, 22),
8041 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8042 return DAG.getMergeValues(Ops, 2, dl);
8044 const Function *Func =
8045 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8046 CallingConv::ID CC = Func->getCallingConv();
8051 llvm_unreachable("Unsupported calling convention");
8052 case CallingConv::C:
8053 case CallingConv::X86_StdCall: {
8054 // Pass 'nest' parameter in ECX.
8055 // Must be kept in sync with X86CallingConv.td
8058 // Check that ECX wasn't needed by an 'inreg' parameter.
8059 const FunctionType *FTy = Func->getFunctionType();
8060 const AttrListPtr &Attrs = Func->getAttributes();
8062 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8063 unsigned InRegCount = 0;
8066 for (FunctionType::param_iterator I = FTy->param_begin(),
8067 E = FTy->param_end(); I != E; ++I, ++Idx)
8068 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8069 // FIXME: should only count parameters that are lowered to integers.
8070 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8072 if (InRegCount > 2) {
8073 report_fatal_error("Nest register in use - reduce number of inreg"
8079 case CallingConv::X86_FastCall:
8080 case CallingConv::X86_ThisCall:
8081 case CallingConv::Fast:
8082 // Pass 'nest' parameter in EAX.
8083 // Must be kept in sync with X86CallingConv.td
8088 SDValue OutChains[4];
8091 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8092 DAG.getConstant(10, MVT::i32));
8093 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8095 // This is storing the opcode for MOV32ri.
8096 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8097 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8098 OutChains[0] = DAG.getStore(Root, dl,
8099 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8100 Trmp, MachinePointerInfo(TrmpAddr),
8103 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8104 DAG.getConstant(1, MVT::i32));
8105 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8106 MachinePointerInfo(TrmpAddr, 1),
8109 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8110 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8111 DAG.getConstant(5, MVT::i32));
8112 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8113 MachinePointerInfo(TrmpAddr, 5),
8116 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8117 DAG.getConstant(6, MVT::i32));
8118 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8119 MachinePointerInfo(TrmpAddr, 6),
8123 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8124 return DAG.getMergeValues(Ops, 2, dl);
8128 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8129 SelectionDAG &DAG) const {
8131 The rounding mode is in bits 11:10 of FPSR, and has the following
8138 FLT_ROUNDS, on the other hand, expects the following:
8145 To perform the conversion, we do:
8146 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8149 MachineFunction &MF = DAG.getMachineFunction();
8150 const TargetMachine &TM = MF.getTarget();
8151 const TargetFrameInfo &TFI = *TM.getFrameInfo();
8152 unsigned StackAlignment = TFI.getStackAlignment();
8153 EVT VT = Op.getValueType();
8154 DebugLoc dl = Op.getDebugLoc();
8156 // Save FP Control Word to stack slot
8157 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8158 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8160 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
8161 DAG.getEntryNode(), StackSlot);
8163 // Load FP Control Word from stack slot
8164 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot,
8165 MachinePointerInfo(), false, false, 0);
8167 // Transform as necessary
8169 DAG.getNode(ISD::SRL, dl, MVT::i16,
8170 DAG.getNode(ISD::AND, dl, MVT::i16,
8171 CWD, DAG.getConstant(0x800, MVT::i16)),
8172 DAG.getConstant(11, MVT::i8));
8174 DAG.getNode(ISD::SRL, dl, MVT::i16,
8175 DAG.getNode(ISD::AND, dl, MVT::i16,
8176 CWD, DAG.getConstant(0x400, MVT::i16)),
8177 DAG.getConstant(9, MVT::i8));
8180 DAG.getNode(ISD::AND, dl, MVT::i16,
8181 DAG.getNode(ISD::ADD, dl, MVT::i16,
8182 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
8183 DAG.getConstant(1, MVT::i16)),
8184 DAG.getConstant(3, MVT::i16));
8187 return DAG.getNode((VT.getSizeInBits() < 16 ?
8188 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
8191 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8192 EVT VT = Op.getValueType();
8194 unsigned NumBits = VT.getSizeInBits();
8195 DebugLoc dl = Op.getDebugLoc();
8197 Op = Op.getOperand(0);
8198 if (VT == MVT::i8) {
8199 // Zero extend to i32 since there is not an i8 bsr.
8201 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8204 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8205 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8206 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8208 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8211 DAG.getConstant(NumBits+NumBits-1, OpVT),
8212 DAG.getConstant(X86::COND_E, MVT::i8),
8215 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8217 // Finally xor with NumBits-1.
8218 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8221 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8225 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8226 EVT VT = Op.getValueType();
8228 unsigned NumBits = VT.getSizeInBits();
8229 DebugLoc dl = Op.getDebugLoc();
8231 Op = Op.getOperand(0);
8232 if (VT == MVT::i8) {
8234 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8237 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8238 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8239 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8241 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8244 DAG.getConstant(NumBits, OpVT),
8245 DAG.getConstant(X86::COND_E, MVT::i8),
8248 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8251 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8255 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8256 EVT VT = Op.getValueType();
8257 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8258 DebugLoc dl = Op.getDebugLoc();
8260 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8261 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8262 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8263 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8264 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8266 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8267 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8268 // return AloBlo + AloBhi + AhiBlo;
8270 SDValue A = Op.getOperand(0);
8271 SDValue B = Op.getOperand(1);
8273 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8274 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8275 A, DAG.getConstant(32, MVT::i32));
8276 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8277 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8278 B, DAG.getConstant(32, MVT::i32));
8279 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8280 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8282 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8283 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8285 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8286 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8288 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8289 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8290 AloBhi, DAG.getConstant(32, MVT::i32));
8291 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8292 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8293 AhiBlo, DAG.getConstant(32, MVT::i32));
8294 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8295 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8299 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8300 EVT VT = Op.getValueType();
8301 DebugLoc dl = Op.getDebugLoc();
8302 SDValue R = Op.getOperand(0);
8304 LLVMContext *Context = DAG.getContext();
8306 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8308 if (VT == MVT::v4i32) {
8309 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8310 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8311 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8313 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8315 std::vector<Constant*> CV(4, CI);
8316 Constant *C = ConstantVector::get(CV);
8317 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8318 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8319 MachinePointerInfo::getConstantPool(),
8322 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8323 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, Op);
8324 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8325 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8327 if (VT == MVT::v16i8) {
8329 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8330 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8331 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8333 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8334 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8336 std::vector<Constant*> CVM1(16, CM1);
8337 std::vector<Constant*> CVM2(16, CM2);
8338 Constant *C = ConstantVector::get(CVM1);
8339 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8340 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8341 MachinePointerInfo::getConstantPool(),
8344 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8345 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8346 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8347 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8348 DAG.getConstant(4, MVT::i32));
8349 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8350 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8353 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8355 C = ConstantVector::get(CVM2);
8356 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8357 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8358 MachinePointerInfo::getConstantPool(),
8361 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8362 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8363 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8364 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8365 DAG.getConstant(2, MVT::i32));
8366 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8367 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8370 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8372 // return pblendv(r, r+r, a);
8373 R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8374 DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
8375 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8381 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8382 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8383 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8384 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8385 // has only one use.
8386 SDNode *N = Op.getNode();
8387 SDValue LHS = N->getOperand(0);
8388 SDValue RHS = N->getOperand(1);
8389 unsigned BaseOp = 0;
8391 DebugLoc dl = Op.getDebugLoc();
8393 switch (Op.getOpcode()) {
8394 default: llvm_unreachable("Unknown ovf instruction!");
8396 // A subtract of one will be selected as a INC. Note that INC doesn't
8397 // set CF, so we can't do this for UADDO.
8398 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8399 if (C->getAPIntValue() == 1) {
8400 BaseOp = X86ISD::INC;
8404 BaseOp = X86ISD::ADD;
8408 BaseOp = X86ISD::ADD;
8412 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8413 // set CF, so we can't do this for USUBO.
8414 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8415 if (C->getAPIntValue() == 1) {
8416 BaseOp = X86ISD::DEC;
8420 BaseOp = X86ISD::SUB;
8424 BaseOp = X86ISD::SUB;
8428 BaseOp = X86ISD::SMUL;
8432 BaseOp = X86ISD::UMUL;
8437 // Also sets EFLAGS.
8438 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8439 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
8442 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
8443 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
8445 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8449 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8450 DebugLoc dl = Op.getDebugLoc();
8452 if (!Subtarget->hasSSE2()) {
8453 SDValue Chain = Op.getOperand(0);
8454 SDValue Zero = DAG.getConstant(0,
8455 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8457 DAG.getRegister(X86::ESP, MVT::i32), // Base
8458 DAG.getTargetConstant(1, MVT::i8), // Scale
8459 DAG.getRegister(0, MVT::i32), // Index
8460 DAG.getTargetConstant(0, MVT::i32), // Disp
8461 DAG.getRegister(0, MVT::i32), // Segment.
8466 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8467 array_lengthof(Ops));
8468 return SDValue(Res, 0);
8471 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8473 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8475 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8476 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8477 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8478 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8480 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8481 if (!Op1 && !Op2 && !Op3 && Op4)
8482 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8484 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8485 if (Op1 && !Op2 && !Op3 && !Op4)
8486 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8488 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8490 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8493 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8494 EVT T = Op.getValueType();
8495 DebugLoc DL = Op.getDebugLoc();
8498 switch(T.getSimpleVT().SimpleTy) {
8500 assert(false && "Invalid value type!");
8501 case MVT::i8: Reg = X86::AL; size = 1; break;
8502 case MVT::i16: Reg = X86::AX; size = 2; break;
8503 case MVT::i32: Reg = X86::EAX; size = 4; break;
8505 assert(Subtarget->is64Bit() && "Node not type legal!");
8506 Reg = X86::RAX; size = 8;
8509 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
8510 Op.getOperand(2), SDValue());
8511 SDValue Ops[] = { cpIn.getValue(0),
8514 DAG.getTargetConstant(size, MVT::i8),
8516 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8517 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
8518 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
8521 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
8525 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8526 SelectionDAG &DAG) const {
8527 assert(Subtarget->is64Bit() && "Result not type legalized?");
8528 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8529 SDValue TheChain = Op.getOperand(0);
8530 DebugLoc dl = Op.getDebugLoc();
8531 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8532 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8533 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8535 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8536 DAG.getConstant(32, MVT::i8));
8538 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8541 return DAG.getMergeValues(Ops, 2, dl);
8544 SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
8545 SelectionDAG &DAG) const {
8546 EVT SrcVT = Op.getOperand(0).getValueType();
8547 EVT DstVT = Op.getValueType();
8548 assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8549 Subtarget->hasMMX() && !DisableMMX) &&
8550 "Unexpected custom BIT_CONVERT");
8551 assert((DstVT == MVT::i64 ||
8552 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8553 "Unexpected custom BIT_CONVERT");
8554 // i64 <=> MMX conversions are Legal.
8555 if (SrcVT==MVT::i64 && DstVT.isVector())
8557 if (DstVT==MVT::i64 && SrcVT.isVector())
8559 // MMX <=> MMX conversions are Legal.
8560 if (SrcVT.isVector() && DstVT.isVector())
8562 // All other conversions need to be expanded.
8565 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8566 SDNode *Node = Op.getNode();
8567 DebugLoc dl = Node->getDebugLoc();
8568 EVT T = Node->getValueType(0);
8569 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8570 DAG.getConstant(0, T), Node->getOperand(2));
8571 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8572 cast<AtomicSDNode>(Node)->getMemoryVT(),
8573 Node->getOperand(0),
8574 Node->getOperand(1), negOp,
8575 cast<AtomicSDNode>(Node)->getSrcValue(),
8576 cast<AtomicSDNode>(Node)->getAlignment());
8579 /// LowerOperation - Provide custom lowering hooks for some operations.
8581 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8582 switch (Op.getOpcode()) {
8583 default: llvm_unreachable("Should not custom lower this!");
8584 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8585 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8586 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8587 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8588 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8589 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8590 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8591 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8592 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8593 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8594 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8595 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8596 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8597 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8598 case ISD::SHL_PARTS:
8599 case ISD::SRA_PARTS:
8600 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8601 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8602 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8603 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8604 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8605 case ISD::FABS: return LowerFABS(Op, DAG);
8606 case ISD::FNEG: return LowerFNEG(Op, DAG);
8607 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8608 case ISD::SETCC: return LowerSETCC(Op, DAG);
8609 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8610 case ISD::SELECT: return LowerSELECT(Op, DAG);
8611 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8612 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8613 case ISD::VASTART: return LowerVASTART(Op, DAG);
8614 case ISD::VAARG: return LowerVAARG(Op, DAG);
8615 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8616 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8617 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8618 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8619 case ISD::FRAME_TO_ARGS_OFFSET:
8620 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8621 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8622 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8623 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8624 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8625 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8626 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8627 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8628 case ISD::SHL: return LowerSHL(Op, DAG);
8634 case ISD::UMULO: return LowerXALUO(Op, DAG);
8635 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8636 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG);
8640 void X86TargetLowering::
8641 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8642 SelectionDAG &DAG, unsigned NewOp) const {
8643 EVT T = Node->getValueType(0);
8644 DebugLoc dl = Node->getDebugLoc();
8645 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8647 SDValue Chain = Node->getOperand(0);
8648 SDValue In1 = Node->getOperand(1);
8649 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8650 Node->getOperand(2), DAG.getIntPtrConstant(0));
8651 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8652 Node->getOperand(2), DAG.getIntPtrConstant(1));
8653 SDValue Ops[] = { Chain, In1, In2L, In2H };
8654 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8656 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8657 cast<MemSDNode>(Node)->getMemOperand());
8658 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8659 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8660 Results.push_back(Result.getValue(2));
8663 /// ReplaceNodeResults - Replace a node with an illegal result type
8664 /// with a new node built out of custom code.
8665 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8666 SmallVectorImpl<SDValue>&Results,
8667 SelectionDAG &DAG) const {
8668 DebugLoc dl = N->getDebugLoc();
8669 switch (N->getOpcode()) {
8671 assert(false && "Do not know how to custom type legalize this operation!");
8673 case ISD::FP_TO_SINT: {
8674 std::pair<SDValue,SDValue> Vals =
8675 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8676 SDValue FIST = Vals.first, StackSlot = Vals.second;
8677 if (FIST.getNode() != 0) {
8678 EVT VT = N->getValueType(0);
8679 // Return a load from the stack slot.
8680 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
8681 MachinePointerInfo(), false, false, 0));
8685 case ISD::READCYCLECOUNTER: {
8686 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8687 SDValue TheChain = N->getOperand(0);
8688 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8689 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8691 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8693 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8694 SDValue Ops[] = { eax, edx };
8695 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8696 Results.push_back(edx.getValue(1));
8699 case ISD::ATOMIC_CMP_SWAP: {
8700 EVT T = N->getValueType(0);
8701 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8702 SDValue cpInL, cpInH;
8703 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8704 DAG.getConstant(0, MVT::i32));
8705 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8706 DAG.getConstant(1, MVT::i32));
8707 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8708 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8710 SDValue swapInL, swapInH;
8711 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8712 DAG.getConstant(0, MVT::i32));
8713 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8714 DAG.getConstant(1, MVT::i32));
8715 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8717 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8718 swapInL.getValue(1));
8719 SDValue Ops[] = { swapInH.getValue(0),
8721 swapInH.getValue(1) };
8722 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
8723 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
8724 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8725 MVT::i32, Result.getValue(1));
8726 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8727 MVT::i32, cpOutL.getValue(2));
8728 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8729 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8730 Results.push_back(cpOutH.getValue(1));
8733 case ISD::ATOMIC_LOAD_ADD:
8734 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8736 case ISD::ATOMIC_LOAD_AND:
8737 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8739 case ISD::ATOMIC_LOAD_NAND:
8740 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8742 case ISD::ATOMIC_LOAD_OR:
8743 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8745 case ISD::ATOMIC_LOAD_SUB:
8746 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8748 case ISD::ATOMIC_LOAD_XOR:
8749 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8751 case ISD::ATOMIC_SWAP:
8752 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8757 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8759 default: return NULL;
8760 case X86ISD::BSF: return "X86ISD::BSF";
8761 case X86ISD::BSR: return "X86ISD::BSR";
8762 case X86ISD::SHLD: return "X86ISD::SHLD";
8763 case X86ISD::SHRD: return "X86ISD::SHRD";
8764 case X86ISD::FAND: return "X86ISD::FAND";
8765 case X86ISD::FOR: return "X86ISD::FOR";
8766 case X86ISD::FXOR: return "X86ISD::FXOR";
8767 case X86ISD::FSRL: return "X86ISD::FSRL";
8768 case X86ISD::FILD: return "X86ISD::FILD";
8769 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8770 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8771 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8772 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8773 case X86ISD::FLD: return "X86ISD::FLD";
8774 case X86ISD::FST: return "X86ISD::FST";
8775 case X86ISD::CALL: return "X86ISD::CALL";
8776 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8777 case X86ISD::BT: return "X86ISD::BT";
8778 case X86ISD::CMP: return "X86ISD::CMP";
8779 case X86ISD::COMI: return "X86ISD::COMI";
8780 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8781 case X86ISD::SETCC: return "X86ISD::SETCC";
8782 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8783 case X86ISD::CMOV: return "X86ISD::CMOV";
8784 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8785 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8786 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8787 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8788 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8789 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8790 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8791 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8792 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8793 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8794 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8795 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8796 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
8797 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8798 case X86ISD::FMAX: return "X86ISD::FMAX";
8799 case X86ISD::FMIN: return "X86ISD::FMIN";
8800 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8801 case X86ISD::FRCP: return "X86ISD::FRCP";
8802 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8803 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8804 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
8805 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8806 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8807 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8808 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8809 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8810 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8811 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8812 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8813 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8814 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8815 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8816 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8817 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8818 case X86ISD::VSHL: return "X86ISD::VSHL";
8819 case X86ISD::VSRL: return "X86ISD::VSRL";
8820 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8821 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8822 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8823 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8824 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8825 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8826 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8827 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8828 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8829 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8830 case X86ISD::ADD: return "X86ISD::ADD";
8831 case X86ISD::SUB: return "X86ISD::SUB";
8832 case X86ISD::SMUL: return "X86ISD::SMUL";
8833 case X86ISD::UMUL: return "X86ISD::UMUL";
8834 case X86ISD::INC: return "X86ISD::INC";
8835 case X86ISD::DEC: return "X86ISD::DEC";
8836 case X86ISD::OR: return "X86ISD::OR";
8837 case X86ISD::XOR: return "X86ISD::XOR";
8838 case X86ISD::AND: return "X86ISD::AND";
8839 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8840 case X86ISD::PTEST: return "X86ISD::PTEST";
8841 case X86ISD::TESTP: return "X86ISD::TESTP";
8842 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8843 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8844 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8845 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8846 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8847 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8848 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8849 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8850 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8851 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8852 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8853 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8854 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8855 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8856 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8857 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8858 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8859 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8860 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8861 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8862 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8863 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8864 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8865 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8866 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8867 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8868 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8869 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8870 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8871 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8872 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8873 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8874 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8875 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8876 case X86ISD::MINGW_ALLOCA: return "X86ISD::MINGW_ALLOCA";
8880 // isLegalAddressingMode - Return true if the addressing mode represented
8881 // by AM is legal for this target, for a load/store of the specified type.
8882 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
8883 const Type *Ty) const {
8884 // X86 supports extremely general addressing modes.
8885 CodeModel::Model M = getTargetMachine().getCodeModel();
8886 Reloc::Model R = getTargetMachine().getRelocationModel();
8888 // X86 allows a sign-extended 32-bit immediate field as a displacement.
8889 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
8894 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
8896 // If a reference to this global requires an extra load, we can't fold it.
8897 if (isGlobalStubReference(GVFlags))
8900 // If BaseGV requires a register for the PIC base, we cannot also have a
8901 // BaseReg specified.
8902 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
8905 // If lower 4G is not available, then we must use rip-relative addressing.
8906 if ((M != CodeModel::Small || R != Reloc::Static) &&
8907 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
8917 // These scales always work.
8922 // These scales are formed with basereg+scalereg. Only accept if there is
8927 default: // Other stuff never works.
8935 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
8936 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8938 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8939 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8940 if (NumBits1 <= NumBits2)
8945 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8946 if (!VT1.isInteger() || !VT2.isInteger())
8948 unsigned NumBits1 = VT1.getSizeInBits();
8949 unsigned NumBits2 = VT2.getSizeInBits();
8950 if (NumBits1 <= NumBits2)
8955 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
8956 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8957 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
8960 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
8961 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
8962 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
8965 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
8966 // i16 instructions are longer (0x66 prefix) and potentially slower.
8967 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
8970 /// isShuffleMaskLegal - Targets can use this to indicate that they only
8971 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
8972 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
8973 /// are assumed to be legal.
8975 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
8977 // Very little shuffling can be done for 64-bit vectors right now.
8978 if (VT.getSizeInBits() == 64)
8979 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
8981 // FIXME: pshufb, blends, shifts.
8982 return (VT.getVectorNumElements() == 2 ||
8983 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
8984 isMOVLMask(M, VT) ||
8985 isSHUFPMask(M, VT) ||
8986 isPSHUFDMask(M, VT) ||
8987 isPSHUFHWMask(M, VT) ||
8988 isPSHUFLWMask(M, VT) ||
8989 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
8990 isUNPCKLMask(M, VT) ||
8991 isUNPCKHMask(M, VT) ||
8992 isUNPCKL_v_undef_Mask(M, VT) ||
8993 isUNPCKH_v_undef_Mask(M, VT));
8997 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
8999 unsigned NumElts = VT.getVectorNumElements();
9000 // FIXME: This collection of masks seems suspect.
9003 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9004 return (isMOVLMask(Mask, VT) ||
9005 isCommutedMOVLMask(Mask, VT, true) ||
9006 isSHUFPMask(Mask, VT) ||
9007 isCommutedSHUFPMask(Mask, VT));
9012 //===----------------------------------------------------------------------===//
9013 // X86 Scheduler Hooks
9014 //===----------------------------------------------------------------------===//
9016 // private utility function
9018 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9019 MachineBasicBlock *MBB,
9026 TargetRegisterClass *RC,
9027 bool invSrc) const {
9028 // For the atomic bitwise operator, we generate
9031 // ld t1 = [bitinstr.addr]
9032 // op t2 = t1, [bitinstr.val]
9034 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9036 // fallthrough -->nextMBB
9037 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9038 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9039 MachineFunction::iterator MBBIter = MBB;
9042 /// First build the CFG
9043 MachineFunction *F = MBB->getParent();
9044 MachineBasicBlock *thisMBB = MBB;
9045 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9046 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9047 F->insert(MBBIter, newMBB);
9048 F->insert(MBBIter, nextMBB);
9050 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9051 nextMBB->splice(nextMBB->begin(), thisMBB,
9052 llvm::next(MachineBasicBlock::iterator(bInstr)),
9054 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9056 // Update thisMBB to fall through to newMBB
9057 thisMBB->addSuccessor(newMBB);
9059 // newMBB jumps to itself and fall through to nextMBB
9060 newMBB->addSuccessor(nextMBB);
9061 newMBB->addSuccessor(newMBB);
9063 // Insert instructions into newMBB based on incoming instruction
9064 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9065 "unexpected number of operands");
9066 DebugLoc dl = bInstr->getDebugLoc();
9067 MachineOperand& destOper = bInstr->getOperand(0);
9068 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9069 int numArgs = bInstr->getNumOperands() - 1;
9070 for (int i=0; i < numArgs; ++i)
9071 argOpers[i] = &bInstr->getOperand(i+1);
9073 // x86 address has 4 operands: base, index, scale, and displacement
9074 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9075 int valArgIndx = lastAddrIndx + 1;
9077 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9078 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9079 for (int i=0; i <= lastAddrIndx; ++i)
9080 (*MIB).addOperand(*argOpers[i]);
9082 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9084 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9089 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9090 assert((argOpers[valArgIndx]->isReg() ||
9091 argOpers[valArgIndx]->isImm()) &&
9093 if (argOpers[valArgIndx]->isReg())
9094 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9096 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9098 (*MIB).addOperand(*argOpers[valArgIndx]);
9100 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9103 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9104 for (int i=0; i <= lastAddrIndx; ++i)
9105 (*MIB).addOperand(*argOpers[i]);
9107 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9108 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9109 bInstr->memoperands_end());
9111 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9115 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9117 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9121 // private utility function: 64 bit atomics on 32 bit host.
9123 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9124 MachineBasicBlock *MBB,
9129 bool invSrc) const {
9130 // For the atomic bitwise operator, we generate
9131 // thisMBB (instructions are in pairs, except cmpxchg8b)
9132 // ld t1,t2 = [bitinstr.addr]
9134 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9135 // op t5, t6 <- out1, out2, [bitinstr.val]
9136 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9137 // mov ECX, EBX <- t5, t6
9138 // mov EAX, EDX <- t1, t2
9139 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9140 // mov t3, t4 <- EAX, EDX
9142 // result in out1, out2
9143 // fallthrough -->nextMBB
9145 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9146 const unsigned LoadOpc = X86::MOV32rm;
9147 const unsigned NotOpc = X86::NOT32r;
9148 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9149 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9150 MachineFunction::iterator MBBIter = MBB;
9153 /// First build the CFG
9154 MachineFunction *F = MBB->getParent();
9155 MachineBasicBlock *thisMBB = MBB;
9156 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9157 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9158 F->insert(MBBIter, newMBB);
9159 F->insert(MBBIter, nextMBB);
9161 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9162 nextMBB->splice(nextMBB->begin(), thisMBB,
9163 llvm::next(MachineBasicBlock::iterator(bInstr)),
9165 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9167 // Update thisMBB to fall through to newMBB
9168 thisMBB->addSuccessor(newMBB);
9170 // newMBB jumps to itself and fall through to nextMBB
9171 newMBB->addSuccessor(nextMBB);
9172 newMBB->addSuccessor(newMBB);
9174 DebugLoc dl = bInstr->getDebugLoc();
9175 // Insert instructions into newMBB based on incoming instruction
9176 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9177 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9178 "unexpected number of operands");
9179 MachineOperand& dest1Oper = bInstr->getOperand(0);
9180 MachineOperand& dest2Oper = bInstr->getOperand(1);
9181 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9182 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9183 argOpers[i] = &bInstr->getOperand(i+2);
9185 // We use some of the operands multiple times, so conservatively just
9186 // clear any kill flags that might be present.
9187 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9188 argOpers[i]->setIsKill(false);
9191 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9192 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9194 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9195 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9196 for (int i=0; i <= lastAddrIndx; ++i)
9197 (*MIB).addOperand(*argOpers[i]);
9198 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9199 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9200 // add 4 to displacement.
9201 for (int i=0; i <= lastAddrIndx-2; ++i)
9202 (*MIB).addOperand(*argOpers[i]);
9203 MachineOperand newOp3 = *(argOpers[3]);
9205 newOp3.setImm(newOp3.getImm()+4);
9207 newOp3.setOffset(newOp3.getOffset()+4);
9208 (*MIB).addOperand(newOp3);
9209 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9211 // t3/4 are defined later, at the bottom of the loop
9212 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9213 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9214 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9215 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9216 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9217 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9219 // The subsequent operations should be using the destination registers of
9220 //the PHI instructions.
9222 t1 = F->getRegInfo().createVirtualRegister(RC);
9223 t2 = F->getRegInfo().createVirtualRegister(RC);
9224 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9225 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9227 t1 = dest1Oper.getReg();
9228 t2 = dest2Oper.getReg();
9231 int valArgIndx = lastAddrIndx + 1;
9232 assert((argOpers[valArgIndx]->isReg() ||
9233 argOpers[valArgIndx]->isImm()) &&
9235 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9236 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9237 if (argOpers[valArgIndx]->isReg())
9238 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9240 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9241 if (regOpcL != X86::MOV32rr)
9243 (*MIB).addOperand(*argOpers[valArgIndx]);
9244 assert(argOpers[valArgIndx + 1]->isReg() ==
9245 argOpers[valArgIndx]->isReg());
9246 assert(argOpers[valArgIndx + 1]->isImm() ==
9247 argOpers[valArgIndx]->isImm());
9248 if (argOpers[valArgIndx + 1]->isReg())
9249 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9251 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9252 if (regOpcH != X86::MOV32rr)
9254 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9256 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9258 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9261 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9263 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9266 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9267 for (int i=0; i <= lastAddrIndx; ++i)
9268 (*MIB).addOperand(*argOpers[i]);
9270 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9271 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9272 bInstr->memoperands_end());
9274 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9275 MIB.addReg(X86::EAX);
9276 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9277 MIB.addReg(X86::EDX);
9280 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9282 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9286 // private utility function
9288 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9289 MachineBasicBlock *MBB,
9290 unsigned cmovOpc) const {
9291 // For the atomic min/max operator, we generate
9294 // ld t1 = [min/max.addr]
9295 // mov t2 = [min/max.val]
9297 // cmov[cond] t2 = t1
9299 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9301 // fallthrough -->nextMBB
9303 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9304 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9305 MachineFunction::iterator MBBIter = MBB;
9308 /// First build the CFG
9309 MachineFunction *F = MBB->getParent();
9310 MachineBasicBlock *thisMBB = MBB;
9311 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9312 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9313 F->insert(MBBIter, newMBB);
9314 F->insert(MBBIter, nextMBB);
9316 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9317 nextMBB->splice(nextMBB->begin(), thisMBB,
9318 llvm::next(MachineBasicBlock::iterator(mInstr)),
9320 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9322 // Update thisMBB to fall through to newMBB
9323 thisMBB->addSuccessor(newMBB);
9325 // newMBB jumps to newMBB and fall through to nextMBB
9326 newMBB->addSuccessor(nextMBB);
9327 newMBB->addSuccessor(newMBB);
9329 DebugLoc dl = mInstr->getDebugLoc();
9330 // Insert instructions into newMBB based on incoming instruction
9331 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9332 "unexpected number of operands");
9333 MachineOperand& destOper = mInstr->getOperand(0);
9334 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9335 int numArgs = mInstr->getNumOperands() - 1;
9336 for (int i=0; i < numArgs; ++i)
9337 argOpers[i] = &mInstr->getOperand(i+1);
9339 // x86 address has 4 operands: base, index, scale, and displacement
9340 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9341 int valArgIndx = lastAddrIndx + 1;
9343 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9344 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9345 for (int i=0; i <= lastAddrIndx; ++i)
9346 (*MIB).addOperand(*argOpers[i]);
9348 // We only support register and immediate values
9349 assert((argOpers[valArgIndx]->isReg() ||
9350 argOpers[valArgIndx]->isImm()) &&
9353 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9354 if (argOpers[valArgIndx]->isReg())
9355 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9357 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9358 (*MIB).addOperand(*argOpers[valArgIndx]);
9360 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9363 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9368 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9369 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9373 // Cmp and exchange if none has modified the memory location
9374 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9375 for (int i=0; i <= lastAddrIndx; ++i)
9376 (*MIB).addOperand(*argOpers[i]);
9378 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9379 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9380 mInstr->memoperands_end());
9382 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9383 MIB.addReg(X86::EAX);
9386 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9388 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9392 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9393 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9396 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9397 unsigned numArgs, bool memArg) const {
9399 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9400 "Target must have SSE4.2 or AVX features enabled");
9402 DebugLoc dl = MI->getDebugLoc();
9403 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9407 if (!Subtarget->hasAVX()) {
9409 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9411 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9414 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9416 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9419 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(Opc));
9421 for (unsigned i = 0; i < numArgs; ++i) {
9422 MachineOperand &Op = MI->getOperand(i+1);
9424 if (!(Op.isReg() && Op.isImplicit()))
9428 BuildMI(BB, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9431 MI->eraseFromParent();
9437 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9439 MachineBasicBlock *MBB) const {
9440 // Emit code to save XMM registers to the stack. The ABI says that the
9441 // number of registers to save is given in %al, so it's theoretically
9442 // possible to do an indirect jump trick to avoid saving all of them,
9443 // however this code takes a simpler approach and just executes all
9444 // of the stores if %al is non-zero. It's less code, and it's probably
9445 // easier on the hardware branch predictor, and stores aren't all that
9446 // expensive anyway.
9448 // Create the new basic blocks. One block contains all the XMM stores,
9449 // and one block is the final destination regardless of whether any
9450 // stores were performed.
9451 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9452 MachineFunction *F = MBB->getParent();
9453 MachineFunction::iterator MBBIter = MBB;
9455 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9456 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9457 F->insert(MBBIter, XMMSaveMBB);
9458 F->insert(MBBIter, EndMBB);
9460 // Transfer the remainder of MBB and its successor edges to EndMBB.
9461 EndMBB->splice(EndMBB->begin(), MBB,
9462 llvm::next(MachineBasicBlock::iterator(MI)),
9464 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9466 // The original block will now fall through to the XMM save block.
9467 MBB->addSuccessor(XMMSaveMBB);
9468 // The XMMSaveMBB will fall through to the end block.
9469 XMMSaveMBB->addSuccessor(EndMBB);
9471 // Now add the instructions.
9472 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9473 DebugLoc DL = MI->getDebugLoc();
9475 unsigned CountReg = MI->getOperand(0).getReg();
9476 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9477 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9479 if (!Subtarget->isTargetWin64()) {
9480 // If %al is 0, branch around the XMM save block.
9481 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9482 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9483 MBB->addSuccessor(EndMBB);
9486 // In the XMM save block, save all the XMM argument registers.
9487 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9488 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9489 MachineMemOperand *MMO =
9490 F->getMachineMemOperand(
9491 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
9492 MachineMemOperand::MOStore,
9493 /*Size=*/16, /*Align=*/16);
9494 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9495 .addFrameIndex(RegSaveFrameIndex)
9496 .addImm(/*Scale=*/1)
9497 .addReg(/*IndexReg=*/0)
9498 .addImm(/*Disp=*/Offset)
9499 .addReg(/*Segment=*/0)
9500 .addReg(MI->getOperand(i).getReg())
9501 .addMemOperand(MMO);
9504 MI->eraseFromParent(); // The pseudo instruction is gone now.
9510 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9511 MachineBasicBlock *BB) const {
9512 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9513 DebugLoc DL = MI->getDebugLoc();
9515 // To "insert" a SELECT_CC instruction, we actually have to insert the
9516 // diamond control-flow pattern. The incoming instruction knows the
9517 // destination vreg to set, the condition code register to branch on, the
9518 // true/false values to select between, and a branch opcode to use.
9519 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9520 MachineFunction::iterator It = BB;
9526 // cmpTY ccX, r1, r2
9528 // fallthrough --> copy0MBB
9529 MachineBasicBlock *thisMBB = BB;
9530 MachineFunction *F = BB->getParent();
9531 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9532 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9533 F->insert(It, copy0MBB);
9534 F->insert(It, sinkMBB);
9536 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9537 // live into the sink and copy blocks.
9538 const MachineFunction *MF = BB->getParent();
9539 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9540 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9542 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9543 const MachineOperand &MO = MI->getOperand(I);
9544 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9545 unsigned Reg = MO.getReg();
9546 if (Reg != X86::EFLAGS) continue;
9547 copy0MBB->addLiveIn(Reg);
9548 sinkMBB->addLiveIn(Reg);
9551 // Transfer the remainder of BB and its successor edges to sinkMBB.
9552 sinkMBB->splice(sinkMBB->begin(), BB,
9553 llvm::next(MachineBasicBlock::iterator(MI)),
9555 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9557 // Add the true and fallthrough blocks as its successors.
9558 BB->addSuccessor(copy0MBB);
9559 BB->addSuccessor(sinkMBB);
9561 // Create the conditional branch instruction.
9563 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9564 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9567 // %FalseValue = ...
9568 // # fallthrough to sinkMBB
9569 copy0MBB->addSuccessor(sinkMBB);
9572 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9574 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9575 TII->get(X86::PHI), MI->getOperand(0).getReg())
9576 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9577 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9579 MI->eraseFromParent(); // The pseudo instruction is gone now.
9584 X86TargetLowering::EmitLoweredMingwAlloca(MachineInstr *MI,
9585 MachineBasicBlock *BB) const {
9586 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9587 DebugLoc DL = MI->getDebugLoc();
9589 // The lowering is pretty easy: we're just emitting the call to _alloca. The
9590 // non-trivial part is impdef of ESP.
9591 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
9594 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
9595 .addExternalSymbol("_alloca")
9596 .addReg(X86::EAX, RegState::Implicit)
9597 .addReg(X86::ESP, RegState::Implicit)
9598 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
9599 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
9600 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
9602 MI->eraseFromParent(); // The pseudo instruction is gone now.
9607 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
9608 MachineBasicBlock *BB) const {
9609 // This is pretty easy. We're taking the value that we received from
9610 // our load from the relocation, sticking it in either RDI (x86-64)
9611 // or EAX and doing an indirect call. The return value will then
9612 // be in the normal return register.
9613 const X86InstrInfo *TII
9614 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
9615 DebugLoc DL = MI->getDebugLoc();
9616 MachineFunction *F = BB->getParent();
9617 bool IsWin64 = Subtarget->isTargetWin64();
9619 assert(MI->getOperand(3).isGlobal() && "This should be a global");
9621 if (Subtarget->is64Bit()) {
9622 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9623 TII->get(X86::MOV64rm), X86::RDI)
9625 .addImm(0).addReg(0)
9626 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9627 MI->getOperand(3).getTargetFlags())
9629 MIB = BuildMI(*BB, MI, DL, TII->get(IsWin64 ? X86::WINCALL64m : X86::CALL64m));
9630 addDirectMem(MIB, X86::RDI);
9631 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
9632 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9633 TII->get(X86::MOV32rm), X86::EAX)
9635 .addImm(0).addReg(0)
9636 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9637 MI->getOperand(3).getTargetFlags())
9639 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9640 addDirectMem(MIB, X86::EAX);
9642 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
9643 TII->get(X86::MOV32rm), X86::EAX)
9644 .addReg(TII->getGlobalBaseReg(F))
9645 .addImm(0).addReg(0)
9646 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
9647 MI->getOperand(3).getTargetFlags())
9649 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
9650 addDirectMem(MIB, X86::EAX);
9653 MI->eraseFromParent(); // The pseudo instruction is gone now.
9658 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
9659 MachineBasicBlock *BB) const {
9660 switch (MI->getOpcode()) {
9661 default: assert(false && "Unexpected instr type to insert");
9662 case X86::MINGW_ALLOCA:
9663 return EmitLoweredMingwAlloca(MI, BB);
9664 case X86::TLSCall_32:
9665 case X86::TLSCall_64:
9666 return EmitLoweredTLSCall(MI, BB);
9668 case X86::CMOV_V1I64:
9669 case X86::CMOV_FR32:
9670 case X86::CMOV_FR64:
9671 case X86::CMOV_V4F32:
9672 case X86::CMOV_V2F64:
9673 case X86::CMOV_V2I64:
9674 case X86::CMOV_GR16:
9675 case X86::CMOV_GR32:
9676 case X86::CMOV_RFP32:
9677 case X86::CMOV_RFP64:
9678 case X86::CMOV_RFP80:
9679 return EmitLoweredSelect(MI, BB);
9681 case X86::FP32_TO_INT16_IN_MEM:
9682 case X86::FP32_TO_INT32_IN_MEM:
9683 case X86::FP32_TO_INT64_IN_MEM:
9684 case X86::FP64_TO_INT16_IN_MEM:
9685 case X86::FP64_TO_INT32_IN_MEM:
9686 case X86::FP64_TO_INT64_IN_MEM:
9687 case X86::FP80_TO_INT16_IN_MEM:
9688 case X86::FP80_TO_INT32_IN_MEM:
9689 case X86::FP80_TO_INT64_IN_MEM: {
9690 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9691 DebugLoc DL = MI->getDebugLoc();
9693 // Change the floating point control register to use "round towards zero"
9694 // mode when truncating to an integer value.
9695 MachineFunction *F = BB->getParent();
9696 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
9697 addFrameReference(BuildMI(*BB, MI, DL,
9698 TII->get(X86::FNSTCW16m)), CWFrameIdx);
9700 // Load the old value of the high byte of the control word...
9702 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
9703 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
9706 // Set the high part to be round to zero...
9707 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
9710 // Reload the modified control word now...
9711 addFrameReference(BuildMI(*BB, MI, DL,
9712 TII->get(X86::FLDCW16m)), CWFrameIdx);
9714 // Restore the memory image of control word to original value
9715 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
9718 // Get the X86 opcode to use.
9720 switch (MI->getOpcode()) {
9721 default: llvm_unreachable("illegal opcode!");
9722 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
9723 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
9724 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
9725 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
9726 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
9727 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
9728 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
9729 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
9730 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
9734 MachineOperand &Op = MI->getOperand(0);
9736 AM.BaseType = X86AddressMode::RegBase;
9737 AM.Base.Reg = Op.getReg();
9739 AM.BaseType = X86AddressMode::FrameIndexBase;
9740 AM.Base.FrameIndex = Op.getIndex();
9742 Op = MI->getOperand(1);
9744 AM.Scale = Op.getImm();
9745 Op = MI->getOperand(2);
9747 AM.IndexReg = Op.getImm();
9748 Op = MI->getOperand(3);
9749 if (Op.isGlobal()) {
9750 AM.GV = Op.getGlobal();
9752 AM.Disp = Op.getImm();
9754 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
9755 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
9757 // Reload the original control word now.
9758 addFrameReference(BuildMI(*BB, MI, DL,
9759 TII->get(X86::FLDCW16m)), CWFrameIdx);
9761 MI->eraseFromParent(); // The pseudo instruction is gone now.
9764 // String/text processing lowering.
9765 case X86::PCMPISTRM128REG:
9766 case X86::VPCMPISTRM128REG:
9767 return EmitPCMP(MI, BB, 3, false /* in-mem */);
9768 case X86::PCMPISTRM128MEM:
9769 case X86::VPCMPISTRM128MEM:
9770 return EmitPCMP(MI, BB, 3, true /* in-mem */);
9771 case X86::PCMPESTRM128REG:
9772 case X86::VPCMPESTRM128REG:
9773 return EmitPCMP(MI, BB, 5, false /* in mem */);
9774 case X86::PCMPESTRM128MEM:
9775 case X86::VPCMPESTRM128MEM:
9776 return EmitPCMP(MI, BB, 5, true /* in mem */);
9779 case X86::ATOMAND32:
9780 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
9781 X86::AND32ri, X86::MOV32rm,
9783 X86::NOT32r, X86::EAX,
9784 X86::GR32RegisterClass);
9786 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
9787 X86::OR32ri, X86::MOV32rm,
9789 X86::NOT32r, X86::EAX,
9790 X86::GR32RegisterClass);
9791 case X86::ATOMXOR32:
9792 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
9793 X86::XOR32ri, X86::MOV32rm,
9795 X86::NOT32r, X86::EAX,
9796 X86::GR32RegisterClass);
9797 case X86::ATOMNAND32:
9798 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
9799 X86::AND32ri, X86::MOV32rm,
9801 X86::NOT32r, X86::EAX,
9802 X86::GR32RegisterClass, true);
9803 case X86::ATOMMIN32:
9804 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
9805 case X86::ATOMMAX32:
9806 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
9807 case X86::ATOMUMIN32:
9808 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
9809 case X86::ATOMUMAX32:
9810 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
9812 case X86::ATOMAND16:
9813 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
9814 X86::AND16ri, X86::MOV16rm,
9816 X86::NOT16r, X86::AX,
9817 X86::GR16RegisterClass);
9819 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
9820 X86::OR16ri, X86::MOV16rm,
9822 X86::NOT16r, X86::AX,
9823 X86::GR16RegisterClass);
9824 case X86::ATOMXOR16:
9825 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
9826 X86::XOR16ri, X86::MOV16rm,
9828 X86::NOT16r, X86::AX,
9829 X86::GR16RegisterClass);
9830 case X86::ATOMNAND16:
9831 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
9832 X86::AND16ri, X86::MOV16rm,
9834 X86::NOT16r, X86::AX,
9835 X86::GR16RegisterClass, true);
9836 case X86::ATOMMIN16:
9837 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
9838 case X86::ATOMMAX16:
9839 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
9840 case X86::ATOMUMIN16:
9841 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
9842 case X86::ATOMUMAX16:
9843 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
9846 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
9847 X86::AND8ri, X86::MOV8rm,
9849 X86::NOT8r, X86::AL,
9850 X86::GR8RegisterClass);
9852 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
9853 X86::OR8ri, X86::MOV8rm,
9855 X86::NOT8r, X86::AL,
9856 X86::GR8RegisterClass);
9858 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
9859 X86::XOR8ri, X86::MOV8rm,
9861 X86::NOT8r, X86::AL,
9862 X86::GR8RegisterClass);
9863 case X86::ATOMNAND8:
9864 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
9865 X86::AND8ri, X86::MOV8rm,
9867 X86::NOT8r, X86::AL,
9868 X86::GR8RegisterClass, true);
9869 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
9870 // This group is for 64-bit host.
9871 case X86::ATOMAND64:
9872 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
9873 X86::AND64ri32, X86::MOV64rm,
9875 X86::NOT64r, X86::RAX,
9876 X86::GR64RegisterClass);
9878 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
9879 X86::OR64ri32, X86::MOV64rm,
9881 X86::NOT64r, X86::RAX,
9882 X86::GR64RegisterClass);
9883 case X86::ATOMXOR64:
9884 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
9885 X86::XOR64ri32, X86::MOV64rm,
9887 X86::NOT64r, X86::RAX,
9888 X86::GR64RegisterClass);
9889 case X86::ATOMNAND64:
9890 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
9891 X86::AND64ri32, X86::MOV64rm,
9893 X86::NOT64r, X86::RAX,
9894 X86::GR64RegisterClass, true);
9895 case X86::ATOMMIN64:
9896 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
9897 case X86::ATOMMAX64:
9898 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
9899 case X86::ATOMUMIN64:
9900 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
9901 case X86::ATOMUMAX64:
9902 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
9904 // This group does 64-bit operations on a 32-bit host.
9905 case X86::ATOMAND6432:
9906 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9907 X86::AND32rr, X86::AND32rr,
9908 X86::AND32ri, X86::AND32ri,
9910 case X86::ATOMOR6432:
9911 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9912 X86::OR32rr, X86::OR32rr,
9913 X86::OR32ri, X86::OR32ri,
9915 case X86::ATOMXOR6432:
9916 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9917 X86::XOR32rr, X86::XOR32rr,
9918 X86::XOR32ri, X86::XOR32ri,
9920 case X86::ATOMNAND6432:
9921 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9922 X86::AND32rr, X86::AND32rr,
9923 X86::AND32ri, X86::AND32ri,
9925 case X86::ATOMADD6432:
9926 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9927 X86::ADD32rr, X86::ADC32rr,
9928 X86::ADD32ri, X86::ADC32ri,
9930 case X86::ATOMSUB6432:
9931 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9932 X86::SUB32rr, X86::SBB32rr,
9933 X86::SUB32ri, X86::SBB32ri,
9935 case X86::ATOMSWAP6432:
9936 return EmitAtomicBit6432WithCustomInserter(MI, BB,
9937 X86::MOV32rr, X86::MOV32rr,
9938 X86::MOV32ri, X86::MOV32ri,
9940 case X86::VASTART_SAVE_XMM_REGS:
9941 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
9945 //===----------------------------------------------------------------------===//
9946 // X86 Optimization Hooks
9947 //===----------------------------------------------------------------------===//
9949 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9953 const SelectionDAG &DAG,
9954 unsigned Depth) const {
9955 unsigned Opc = Op.getOpcode();
9956 assert((Opc >= ISD::BUILTIN_OP_END ||
9957 Opc == ISD::INTRINSIC_WO_CHAIN ||
9958 Opc == ISD::INTRINSIC_W_CHAIN ||
9959 Opc == ISD::INTRINSIC_VOID) &&
9960 "Should use MaskedValueIsZero if you don't know whether Op"
9961 " is a target node!");
9963 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
9975 // These nodes' second result is a boolean.
9976 if (Op.getResNo() == 0)
9980 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
9981 Mask.getBitWidth() - 1);
9986 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
9987 unsigned Depth) const {
9988 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
9989 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
9990 return Op.getValueType().getScalarType().getSizeInBits();
9996 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
9997 /// node is a GlobalAddress + offset.
9998 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
9999 const GlobalValue* &GA,
10000 int64_t &Offset) const {
10001 if (N->getOpcode() == X86ISD::Wrapper) {
10002 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
10003 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
10004 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
10008 return TargetLowering::isGAPlusOffset(N, GA, Offset);
10011 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
10012 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
10013 /// if the load addresses are consecutive, non-overlapping, and in the right
10015 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
10016 const TargetLowering &TLI) {
10017 DebugLoc dl = N->getDebugLoc();
10018 EVT VT = N->getValueType(0);
10020 if (VT.getSizeInBits() != 128)
10023 SmallVector<SDValue, 16> Elts;
10024 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
10025 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
10027 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
10030 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
10031 /// generation and convert it from being a bunch of shuffles and extracts
10032 /// to a simple store and scalar loads to extract the elements.
10033 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
10034 const TargetLowering &TLI) {
10035 SDValue InputVector = N->getOperand(0);
10037 // Only operate on vectors of 4 elements, where the alternative shuffling
10038 // gets to be more expensive.
10039 if (InputVector.getValueType() != MVT::v4i32)
10042 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
10043 // single use which is a sign-extend or zero-extend, and all elements are
10045 SmallVector<SDNode *, 4> Uses;
10046 unsigned ExtractedElements = 0;
10047 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
10048 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
10049 if (UI.getUse().getResNo() != InputVector.getResNo())
10052 SDNode *Extract = *UI;
10053 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10056 if (Extract->getValueType(0) != MVT::i32)
10058 if (!Extract->hasOneUse())
10060 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
10061 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
10063 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
10066 // Record which element was extracted.
10067 ExtractedElements |=
10068 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
10070 Uses.push_back(Extract);
10073 // If not all the elements were used, this may not be worthwhile.
10074 if (ExtractedElements != 15)
10077 // Ok, we've now decided to do the transformation.
10078 DebugLoc dl = InputVector.getDebugLoc();
10080 // Store the value to a temporary stack slot.
10081 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
10082 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
10083 MachinePointerInfo(), false, false, 0);
10085 // Replace each use (extract) with a load of the appropriate element.
10086 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
10087 UE = Uses.end(); UI != UE; ++UI) {
10088 SDNode *Extract = *UI;
10090 // Compute the element's address.
10091 SDValue Idx = Extract->getOperand(1);
10093 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
10094 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
10095 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
10097 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
10098 StackPtr, OffsetVal);
10100 // Load the scalar.
10101 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
10102 ScalarAddr, MachinePointerInfo(),
10105 // Replace the exact with the load.
10106 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
10109 // The replacement was made in place; don't return anything.
10113 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
10114 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
10115 const X86Subtarget *Subtarget) {
10116 DebugLoc DL = N->getDebugLoc();
10117 SDValue Cond = N->getOperand(0);
10118 // Get the LHS/RHS of the select.
10119 SDValue LHS = N->getOperand(1);
10120 SDValue RHS = N->getOperand(2);
10122 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
10123 // instructions match the semantics of the common C idiom x<y?x:y but not
10124 // x<=y?x:y, because of how they handle negative zero (which can be
10125 // ignored in unsafe-math mode).
10126 if (Subtarget->hasSSE2() &&
10127 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
10128 Cond.getOpcode() == ISD::SETCC) {
10129 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
10131 unsigned Opcode = 0;
10132 // Check for x CC y ? x : y.
10133 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
10134 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
10138 // Converting this to a min would handle NaNs incorrectly, and swapping
10139 // the operands would cause it to handle comparisons between positive
10140 // and negative zero incorrectly.
10141 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10142 if (!UnsafeFPMath &&
10143 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10145 std::swap(LHS, RHS);
10147 Opcode = X86ISD::FMIN;
10150 // Converting this to a min would handle comparisons between positive
10151 // and negative zero incorrectly.
10152 if (!UnsafeFPMath &&
10153 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
10155 Opcode = X86ISD::FMIN;
10158 // Converting this to a min would handle both negative zeros and NaNs
10159 // incorrectly, but we can swap the operands to fix both.
10160 std::swap(LHS, RHS);
10164 Opcode = X86ISD::FMIN;
10168 // Converting this to a max would handle comparisons between positive
10169 // and negative zero incorrectly.
10170 if (!UnsafeFPMath &&
10171 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
10173 Opcode = X86ISD::FMAX;
10176 // Converting this to a max would handle NaNs incorrectly, and swapping
10177 // the operands would cause it to handle comparisons between positive
10178 // and negative zero incorrectly.
10179 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10180 if (!UnsafeFPMath &&
10181 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10183 std::swap(LHS, RHS);
10185 Opcode = X86ISD::FMAX;
10188 // Converting this to a max would handle both negative zeros and NaNs
10189 // incorrectly, but we can swap the operands to fix both.
10190 std::swap(LHS, RHS);
10194 Opcode = X86ISD::FMAX;
10197 // Check for x CC y ? y : x -- a min/max with reversed arms.
10198 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10199 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10203 // Converting this to a min would handle comparisons between positive
10204 // and negative zero incorrectly, and swapping the operands would
10205 // cause it to handle NaNs incorrectly.
10206 if (!UnsafeFPMath &&
10207 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10208 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10210 std::swap(LHS, RHS);
10212 Opcode = X86ISD::FMIN;
10215 // Converting this to a min would handle NaNs incorrectly.
10216 if (!UnsafeFPMath &&
10217 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10219 Opcode = X86ISD::FMIN;
10222 // Converting this to a min would handle both negative zeros and NaNs
10223 // incorrectly, but we can swap the operands to fix both.
10224 std::swap(LHS, RHS);
10228 Opcode = X86ISD::FMIN;
10232 // Converting this to a max would handle NaNs incorrectly.
10233 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10235 Opcode = X86ISD::FMAX;
10238 // Converting this to a max would handle comparisons between positive
10239 // and negative zero incorrectly, and swapping the operands would
10240 // cause it to handle NaNs incorrectly.
10241 if (!UnsafeFPMath &&
10242 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10243 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10245 std::swap(LHS, RHS);
10247 Opcode = X86ISD::FMAX;
10250 // Converting this to a max would handle both negative zeros and NaNs
10251 // incorrectly, but we can swap the operands to fix both.
10252 std::swap(LHS, RHS);
10256 Opcode = X86ISD::FMAX;
10262 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10265 // If this is a select between two integer constants, try to do some
10267 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10268 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10269 // Don't do this for crazy integer types.
10270 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10271 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10272 // so that TrueC (the true value) is larger than FalseC.
10273 bool NeedsCondInvert = false;
10275 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10276 // Efficiently invertible.
10277 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10278 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10279 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10280 NeedsCondInvert = true;
10281 std::swap(TrueC, FalseC);
10284 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10285 if (FalseC->getAPIntValue() == 0 &&
10286 TrueC->getAPIntValue().isPowerOf2()) {
10287 if (NeedsCondInvert) // Invert the condition if needed.
10288 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10289 DAG.getConstant(1, Cond.getValueType()));
10291 // Zero extend the condition if needed.
10292 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10294 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10295 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10296 DAG.getConstant(ShAmt, MVT::i8));
10299 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10300 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10301 if (NeedsCondInvert) // Invert the condition if needed.
10302 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10303 DAG.getConstant(1, Cond.getValueType()));
10305 // Zero extend the condition if needed.
10306 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10307 FalseC->getValueType(0), Cond);
10308 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10309 SDValue(FalseC, 0));
10312 // Optimize cases that will turn into an LEA instruction. This requires
10313 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10314 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10315 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10316 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10318 bool isFastMultiplier = false;
10320 switch ((unsigned char)Diff) {
10322 case 1: // result = add base, cond
10323 case 2: // result = lea base( , cond*2)
10324 case 3: // result = lea base(cond, cond*2)
10325 case 4: // result = lea base( , cond*4)
10326 case 5: // result = lea base(cond, cond*4)
10327 case 8: // result = lea base( , cond*8)
10328 case 9: // result = lea base(cond, cond*8)
10329 isFastMultiplier = true;
10334 if (isFastMultiplier) {
10335 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10336 if (NeedsCondInvert) // Invert the condition if needed.
10337 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10338 DAG.getConstant(1, Cond.getValueType()));
10340 // Zero extend the condition if needed.
10341 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10343 // Scale the condition by the difference.
10345 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10346 DAG.getConstant(Diff, Cond.getValueType()));
10348 // Add the base if non-zero.
10349 if (FalseC->getAPIntValue() != 0)
10350 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10351 SDValue(FalseC, 0));
10361 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10362 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10363 TargetLowering::DAGCombinerInfo &DCI) {
10364 DebugLoc DL = N->getDebugLoc();
10366 // If the flag operand isn't dead, don't touch this CMOV.
10367 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10370 // If this is a select between two integer constants, try to do some
10371 // optimizations. Note that the operands are ordered the opposite of SELECT
10373 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10374 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10375 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10376 // larger than FalseC (the false value).
10377 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10379 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10380 CC = X86::GetOppositeBranchCondition(CC);
10381 std::swap(TrueC, FalseC);
10384 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10385 // This is efficient for any integer data type (including i8/i16) and
10387 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10388 SDValue Cond = N->getOperand(3);
10389 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10390 DAG.getConstant(CC, MVT::i8), Cond);
10392 // Zero extend the condition if needed.
10393 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10395 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10396 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10397 DAG.getConstant(ShAmt, MVT::i8));
10398 if (N->getNumValues() == 2) // Dead flag value?
10399 return DCI.CombineTo(N, Cond, SDValue());
10403 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10404 // for any integer data type, including i8/i16.
10405 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10406 SDValue Cond = N->getOperand(3);
10407 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10408 DAG.getConstant(CC, MVT::i8), Cond);
10410 // Zero extend the condition if needed.
10411 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10412 FalseC->getValueType(0), Cond);
10413 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10414 SDValue(FalseC, 0));
10416 if (N->getNumValues() == 2) // Dead flag value?
10417 return DCI.CombineTo(N, Cond, SDValue());
10421 // Optimize cases that will turn into an LEA instruction. This requires
10422 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10423 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10424 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10425 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10427 bool isFastMultiplier = false;
10429 switch ((unsigned char)Diff) {
10431 case 1: // result = add base, cond
10432 case 2: // result = lea base( , cond*2)
10433 case 3: // result = lea base(cond, cond*2)
10434 case 4: // result = lea base( , cond*4)
10435 case 5: // result = lea base(cond, cond*4)
10436 case 8: // result = lea base( , cond*8)
10437 case 9: // result = lea base(cond, cond*8)
10438 isFastMultiplier = true;
10443 if (isFastMultiplier) {
10444 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10445 SDValue Cond = N->getOperand(3);
10446 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10447 DAG.getConstant(CC, MVT::i8), Cond);
10448 // Zero extend the condition if needed.
10449 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10451 // Scale the condition by the difference.
10453 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10454 DAG.getConstant(Diff, Cond.getValueType()));
10456 // Add the base if non-zero.
10457 if (FalseC->getAPIntValue() != 0)
10458 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10459 SDValue(FalseC, 0));
10460 if (N->getNumValues() == 2) // Dead flag value?
10461 return DCI.CombineTo(N, Cond, SDValue());
10471 /// PerformMulCombine - Optimize a single multiply with constant into two
10472 /// in order to implement it with two cheaper instructions, e.g.
10473 /// LEA + SHL, LEA + LEA.
10474 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10475 TargetLowering::DAGCombinerInfo &DCI) {
10476 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10479 EVT VT = N->getValueType(0);
10480 if (VT != MVT::i64)
10483 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10486 uint64_t MulAmt = C->getZExtValue();
10487 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10490 uint64_t MulAmt1 = 0;
10491 uint64_t MulAmt2 = 0;
10492 if ((MulAmt % 9) == 0) {
10494 MulAmt2 = MulAmt / 9;
10495 } else if ((MulAmt % 5) == 0) {
10497 MulAmt2 = MulAmt / 5;
10498 } else if ((MulAmt % 3) == 0) {
10500 MulAmt2 = MulAmt / 3;
10503 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10504 DebugLoc DL = N->getDebugLoc();
10506 if (isPowerOf2_64(MulAmt2) &&
10507 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10508 // If second multiplifer is pow2, issue it first. We want the multiply by
10509 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10511 std::swap(MulAmt1, MulAmt2);
10514 if (isPowerOf2_64(MulAmt1))
10515 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10516 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10518 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10519 DAG.getConstant(MulAmt1, VT));
10521 if (isPowerOf2_64(MulAmt2))
10522 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10523 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10525 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10526 DAG.getConstant(MulAmt2, VT));
10528 // Do not add new nodes to DAG combiner worklist.
10529 DCI.CombineTo(N, NewMul, false);
10534 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10535 SDValue N0 = N->getOperand(0);
10536 SDValue N1 = N->getOperand(1);
10537 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10538 EVT VT = N0.getValueType();
10540 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10541 // since the result of setcc_c is all zero's or all ones.
10542 if (N1C && N0.getOpcode() == ISD::AND &&
10543 N0.getOperand(1).getOpcode() == ISD::Constant) {
10544 SDValue N00 = N0.getOperand(0);
10545 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10546 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10547 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10548 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10549 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10550 APInt ShAmt = N1C->getAPIntValue();
10551 Mask = Mask.shl(ShAmt);
10553 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10554 N00, DAG.getConstant(Mask, VT));
10561 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10563 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10564 const X86Subtarget *Subtarget) {
10565 EVT VT = N->getValueType(0);
10566 if (!VT.isVector() && VT.isInteger() &&
10567 N->getOpcode() == ISD::SHL)
10568 return PerformSHLCombine(N, DAG);
10570 // On X86 with SSE2 support, we can transform this to a vector shift if
10571 // all elements are shifted by the same amount. We can't do this in legalize
10572 // because the a constant vector is typically transformed to a constant pool
10573 // so we have no knowledge of the shift amount.
10574 if (!Subtarget->hasSSE2())
10577 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
10580 SDValue ShAmtOp = N->getOperand(1);
10581 EVT EltVT = VT.getVectorElementType();
10582 DebugLoc DL = N->getDebugLoc();
10583 SDValue BaseShAmt = SDValue();
10584 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
10585 unsigned NumElts = VT.getVectorNumElements();
10587 for (; i != NumElts; ++i) {
10588 SDValue Arg = ShAmtOp.getOperand(i);
10589 if (Arg.getOpcode() == ISD::UNDEF) continue;
10593 for (; i != NumElts; ++i) {
10594 SDValue Arg = ShAmtOp.getOperand(i);
10595 if (Arg.getOpcode() == ISD::UNDEF) continue;
10596 if (Arg != BaseShAmt) {
10600 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
10601 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
10602 SDValue InVec = ShAmtOp.getOperand(0);
10603 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
10604 unsigned NumElts = InVec.getValueType().getVectorNumElements();
10606 for (; i != NumElts; ++i) {
10607 SDValue Arg = InVec.getOperand(i);
10608 if (Arg.getOpcode() == ISD::UNDEF) continue;
10612 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
10613 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
10614 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
10615 if (C->getZExtValue() == SplatIdx)
10616 BaseShAmt = InVec.getOperand(1);
10619 if (BaseShAmt.getNode() == 0)
10620 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
10621 DAG.getIntPtrConstant(0));
10625 // The shift amount is an i32.
10626 if (EltVT.bitsGT(MVT::i32))
10627 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
10628 else if (EltVT.bitsLT(MVT::i32))
10629 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
10631 // The shift amount is identical so we can do a vector shift.
10632 SDValue ValOp = N->getOperand(0);
10633 switch (N->getOpcode()) {
10635 llvm_unreachable("Unknown shift opcode!");
10638 if (VT == MVT::v2i64)
10639 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10640 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
10642 if (VT == MVT::v4i32)
10643 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10644 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
10646 if (VT == MVT::v8i16)
10647 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10648 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
10652 if (VT == MVT::v4i32)
10653 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10654 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
10656 if (VT == MVT::v8i16)
10657 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10658 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
10662 if (VT == MVT::v2i64)
10663 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10664 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
10666 if (VT == MVT::v4i32)
10667 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10668 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
10670 if (VT == MVT::v8i16)
10671 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
10672 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
10679 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
10680 TargetLowering::DAGCombinerInfo &DCI,
10681 const X86Subtarget *Subtarget) {
10682 if (DCI.isBeforeLegalizeOps())
10685 EVT VT = N->getValueType(0);
10686 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
10689 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
10690 SDValue N0 = N->getOperand(0);
10691 SDValue N1 = N->getOperand(1);
10692 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
10694 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
10696 if (!N0.hasOneUse() || !N1.hasOneUse())
10699 SDValue ShAmt0 = N0.getOperand(1);
10700 if (ShAmt0.getValueType() != MVT::i8)
10702 SDValue ShAmt1 = N1.getOperand(1);
10703 if (ShAmt1.getValueType() != MVT::i8)
10705 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
10706 ShAmt0 = ShAmt0.getOperand(0);
10707 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
10708 ShAmt1 = ShAmt1.getOperand(0);
10710 DebugLoc DL = N->getDebugLoc();
10711 unsigned Opc = X86ISD::SHLD;
10712 SDValue Op0 = N0.getOperand(0);
10713 SDValue Op1 = N1.getOperand(0);
10714 if (ShAmt0.getOpcode() == ISD::SUB) {
10715 Opc = X86ISD::SHRD;
10716 std::swap(Op0, Op1);
10717 std::swap(ShAmt0, ShAmt1);
10720 unsigned Bits = VT.getSizeInBits();
10721 if (ShAmt1.getOpcode() == ISD::SUB) {
10722 SDValue Sum = ShAmt1.getOperand(0);
10723 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
10724 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
10725 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
10726 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
10727 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
10728 return DAG.getNode(Opc, DL, VT,
10730 DAG.getNode(ISD::TRUNCATE, DL,
10733 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
10734 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
10736 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
10737 return DAG.getNode(Opc, DL, VT,
10738 N0.getOperand(0), N1.getOperand(0),
10739 DAG.getNode(ISD::TRUNCATE, DL,
10746 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
10747 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
10748 const X86Subtarget *Subtarget) {
10749 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
10750 // the FP state in cases where an emms may be missing.
10751 // A preferable solution to the general problem is to figure out the right
10752 // places to insert EMMS. This qualifies as a quick hack.
10754 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
10755 StoreSDNode *St = cast<StoreSDNode>(N);
10756 EVT VT = St->getValue().getValueType();
10757 if (VT.getSizeInBits() != 64)
10760 const Function *F = DAG.getMachineFunction().getFunction();
10761 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
10762 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
10763 && Subtarget->hasSSE2();
10764 if ((VT.isVector() ||
10765 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
10766 isa<LoadSDNode>(St->getValue()) &&
10767 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
10768 St->getChain().hasOneUse() && !St->isVolatile()) {
10769 SDNode* LdVal = St->getValue().getNode();
10770 LoadSDNode *Ld = 0;
10771 int TokenFactorIndex = -1;
10772 SmallVector<SDValue, 8> Ops;
10773 SDNode* ChainVal = St->getChain().getNode();
10774 // Must be a store of a load. We currently handle two cases: the load
10775 // is a direct child, and it's under an intervening TokenFactor. It is
10776 // possible to dig deeper under nested TokenFactors.
10777 if (ChainVal == LdVal)
10778 Ld = cast<LoadSDNode>(St->getChain());
10779 else if (St->getValue().hasOneUse() &&
10780 ChainVal->getOpcode() == ISD::TokenFactor) {
10781 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
10782 if (ChainVal->getOperand(i).getNode() == LdVal) {
10783 TokenFactorIndex = i;
10784 Ld = cast<LoadSDNode>(St->getValue());
10786 Ops.push_back(ChainVal->getOperand(i));
10790 if (!Ld || !ISD::isNormalLoad(Ld))
10793 // If this is not the MMX case, i.e. we are just turning i64 load/store
10794 // into f64 load/store, avoid the transformation if there are multiple
10795 // uses of the loaded value.
10796 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
10799 DebugLoc LdDL = Ld->getDebugLoc();
10800 DebugLoc StDL = N->getDebugLoc();
10801 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
10802 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
10804 if (Subtarget->is64Bit() || F64IsLegal) {
10805 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
10806 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
10807 Ld->getPointerInfo(), Ld->isVolatile(),
10808 Ld->isNonTemporal(), Ld->getAlignment());
10809 SDValue NewChain = NewLd.getValue(1);
10810 if (TokenFactorIndex != -1) {
10811 Ops.push_back(NewChain);
10812 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
10815 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
10816 St->getPointerInfo(),
10817 St->isVolatile(), St->isNonTemporal(),
10818 St->getAlignment());
10821 // Otherwise, lower to two pairs of 32-bit loads / stores.
10822 SDValue LoAddr = Ld->getBasePtr();
10823 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
10824 DAG.getConstant(4, MVT::i32));
10826 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
10827 Ld->getPointerInfo(),
10828 Ld->isVolatile(), Ld->isNonTemporal(),
10829 Ld->getAlignment());
10830 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
10831 Ld->getPointerInfo().getWithOffset(4),
10832 Ld->isVolatile(), Ld->isNonTemporal(),
10833 MinAlign(Ld->getAlignment(), 4));
10835 SDValue NewChain = LoLd.getValue(1);
10836 if (TokenFactorIndex != -1) {
10837 Ops.push_back(LoLd);
10838 Ops.push_back(HiLd);
10839 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
10843 LoAddr = St->getBasePtr();
10844 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
10845 DAG.getConstant(4, MVT::i32));
10847 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
10848 St->getPointerInfo(),
10849 St->isVolatile(), St->isNonTemporal(),
10850 St->getAlignment());
10851 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
10852 St->getPointerInfo().getWithOffset(4),
10854 St->isNonTemporal(),
10855 MinAlign(St->getAlignment(), 4));
10856 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
10861 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
10862 /// X86ISD::FXOR nodes.
10863 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
10864 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
10865 // F[X]OR(0.0, x) -> x
10866 // F[X]OR(x, 0.0) -> x
10867 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
10868 if (C->getValueAPF().isPosZero())
10869 return N->getOperand(1);
10870 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
10871 if (C->getValueAPF().isPosZero())
10872 return N->getOperand(0);
10876 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
10877 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
10878 // FAND(0.0, x) -> 0.0
10879 // FAND(x, 0.0) -> 0.0
10880 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
10881 if (C->getValueAPF().isPosZero())
10882 return N->getOperand(0);
10883 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
10884 if (C->getValueAPF().isPosZero())
10885 return N->getOperand(1);
10889 static SDValue PerformBTCombine(SDNode *N,
10891 TargetLowering::DAGCombinerInfo &DCI) {
10892 // BT ignores high bits in the bit index operand.
10893 SDValue Op1 = N->getOperand(1);
10894 if (Op1.hasOneUse()) {
10895 unsigned BitWidth = Op1.getValueSizeInBits();
10896 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
10897 APInt KnownZero, KnownOne;
10898 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
10899 !DCI.isBeforeLegalizeOps());
10900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10901 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
10902 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
10903 DCI.CommitTargetLoweringOpt(TLO);
10908 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
10909 SDValue Op = N->getOperand(0);
10910 if (Op.getOpcode() == ISD::BIT_CONVERT)
10911 Op = Op.getOperand(0);
10912 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
10913 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
10914 VT.getVectorElementType().getSizeInBits() ==
10915 OpVT.getVectorElementType().getSizeInBits()) {
10916 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
10921 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
10922 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
10923 // (and (i32 x86isd::setcc_carry), 1)
10924 // This eliminates the zext. This transformation is necessary because
10925 // ISD::SETCC is always legalized to i8.
10926 DebugLoc dl = N->getDebugLoc();
10927 SDValue N0 = N->getOperand(0);
10928 EVT VT = N->getValueType(0);
10929 if (N0.getOpcode() == ISD::AND &&
10931 N0.getOperand(0).hasOneUse()) {
10932 SDValue N00 = N0.getOperand(0);
10933 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
10935 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
10936 if (!C || C->getZExtValue() != 1)
10938 return DAG.getNode(ISD::AND, dl, VT,
10939 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
10940 N00.getOperand(0), N00.getOperand(1)),
10941 DAG.getConstant(1, VT));
10947 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
10948 DAGCombinerInfo &DCI) const {
10949 SelectionDAG &DAG = DCI.DAG;
10950 switch (N->getOpcode()) {
10952 case ISD::EXTRACT_VECTOR_ELT:
10953 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
10954 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
10955 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
10956 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
10959 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
10960 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
10961 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
10963 case X86ISD::FOR: return PerformFORCombine(N, DAG);
10964 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
10965 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
10966 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
10967 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
10968 case X86ISD::SHUFPS: // Handle all target specific shuffles
10969 case X86ISD::SHUFPD:
10970 case X86ISD::PALIGN:
10971 case X86ISD::PUNPCKHBW:
10972 case X86ISD::PUNPCKHWD:
10973 case X86ISD::PUNPCKHDQ:
10974 case X86ISD::PUNPCKHQDQ:
10975 case X86ISD::UNPCKHPS:
10976 case X86ISD::UNPCKHPD:
10977 case X86ISD::PUNPCKLBW:
10978 case X86ISD::PUNPCKLWD:
10979 case X86ISD::PUNPCKLDQ:
10980 case X86ISD::PUNPCKLQDQ:
10981 case X86ISD::UNPCKLPS:
10982 case X86ISD::UNPCKLPD:
10983 case X86ISD::MOVHLPS:
10984 case X86ISD::MOVLHPS:
10985 case X86ISD::PSHUFD:
10986 case X86ISD::PSHUFHW:
10987 case X86ISD::PSHUFLW:
10988 case X86ISD::MOVSS:
10989 case X86ISD::MOVSD:
10990 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
10996 /// isTypeDesirableForOp - Return true if the target has native support for
10997 /// the specified value type and it is 'desirable' to use the type for the
10998 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
10999 /// instruction encodings are longer and some i16 instructions are slow.
11000 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
11001 if (!isTypeLegal(VT))
11003 if (VT != MVT::i16)
11010 case ISD::SIGN_EXTEND:
11011 case ISD::ZERO_EXTEND:
11012 case ISD::ANY_EXTEND:
11025 /// IsDesirableToPromoteOp - This method query the target whether it is
11026 /// beneficial for dag combiner to promote the specified node. If true, it
11027 /// should return the desired promotion type by reference.
11028 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
11029 EVT VT = Op.getValueType();
11030 if (VT != MVT::i16)
11033 bool Promote = false;
11034 bool Commute = false;
11035 switch (Op.getOpcode()) {
11038 LoadSDNode *LD = cast<LoadSDNode>(Op);
11039 // If the non-extending load has a single use and it's not live out, then it
11040 // might be folded.
11041 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
11042 Op.hasOneUse()*/) {
11043 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11044 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
11045 // The only case where we'd want to promote LOAD (rather then it being
11046 // promoted as an operand is when it's only use is liveout.
11047 if (UI->getOpcode() != ISD::CopyToReg)
11054 case ISD::SIGN_EXTEND:
11055 case ISD::ZERO_EXTEND:
11056 case ISD::ANY_EXTEND:
11061 SDValue N0 = Op.getOperand(0);
11062 // Look out for (store (shl (load), x)).
11063 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
11076 SDValue N0 = Op.getOperand(0);
11077 SDValue N1 = Op.getOperand(1);
11078 if (!Commute && MayFoldLoad(N1))
11080 // Avoid disabling potential load folding opportunities.
11081 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
11083 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
11093 //===----------------------------------------------------------------------===//
11094 // X86 Inline Assembly Support
11095 //===----------------------------------------------------------------------===//
11097 static bool LowerToBSwap(CallInst *CI) {
11098 // FIXME: this should verify that we are targetting a 486 or better. If not,
11099 // we will turn this bswap into something that will be lowered to logical ops
11100 // instead of emitting the bswap asm. For now, we don't support 486 or lower
11101 // so don't worry about this.
11103 // Verify this is a simple bswap.
11104 if (CI->getNumArgOperands() != 1 ||
11105 CI->getType() != CI->getArgOperand(0)->getType() ||
11106 !CI->getType()->isIntegerTy())
11109 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11110 if (!Ty || Ty->getBitWidth() % 16 != 0)
11113 // Okay, we can do this xform, do so now.
11114 const Type *Tys[] = { Ty };
11115 Module *M = CI->getParent()->getParent()->getParent();
11116 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
11118 Value *Op = CI->getArgOperand(0);
11119 Op = CallInst::Create(Int, Op, CI->getName(), CI);
11121 CI->replaceAllUsesWith(Op);
11122 CI->eraseFromParent();
11126 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
11127 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11128 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
11130 std::string AsmStr = IA->getAsmString();
11132 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
11133 SmallVector<StringRef, 4> AsmPieces;
11134 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
11136 switch (AsmPieces.size()) {
11137 default: return false;
11139 AsmStr = AsmPieces[0];
11141 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
11144 if (AsmPieces.size() == 2 &&
11145 (AsmPieces[0] == "bswap" ||
11146 AsmPieces[0] == "bswapq" ||
11147 AsmPieces[0] == "bswapl") &&
11148 (AsmPieces[1] == "$0" ||
11149 AsmPieces[1] == "${0:q}")) {
11150 // No need to check constraints, nothing other than the equivalent of
11151 // "=r,0" would be valid here.
11152 return LowerToBSwap(CI);
11154 // rorw $$8, ${0:w} --> llvm.bswap.i16
11155 if (CI->getType()->isIntegerTy(16) &&
11156 AsmPieces.size() == 3 &&
11157 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
11158 AsmPieces[1] == "$$8," &&
11159 AsmPieces[2] == "${0:w}" &&
11160 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11162 const std::string &Constraints = IA->getConstraintString();
11163 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11164 std::sort(AsmPieces.begin(), AsmPieces.end());
11165 if (AsmPieces.size() == 4 &&
11166 AsmPieces[0] == "~{cc}" &&
11167 AsmPieces[1] == "~{dirflag}" &&
11168 AsmPieces[2] == "~{flags}" &&
11169 AsmPieces[3] == "~{fpsr}") {
11170 return LowerToBSwap(CI);
11175 if (CI->getType()->isIntegerTy(64) &&
11176 Constraints.size() >= 2 &&
11177 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11178 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11179 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11180 SmallVector<StringRef, 4> Words;
11181 SplitString(AsmPieces[0], Words, " \t");
11182 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11184 SplitString(AsmPieces[1], Words, " \t");
11185 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11187 SplitString(AsmPieces[2], Words, " \t,");
11188 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11189 Words[2] == "%edx") {
11190 return LowerToBSwap(CI);
11202 /// getConstraintType - Given a constraint letter, return the type of
11203 /// constraint it is for this target.
11204 X86TargetLowering::ConstraintType
11205 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11206 if (Constraint.size() == 1) {
11207 switch (Constraint[0]) {
11219 return C_RegisterClass;
11227 return TargetLowering::getConstraintType(Constraint);
11230 /// Examine constraint type and operand type and determine a weight value,
11231 /// where: -1 = invalid match, and 0 = so-so match to 3 = good match.
11232 /// This object must already have been set up with the operand type
11233 /// and the current alternative constraint selected.
11234 int X86TargetLowering::getSingleConstraintMatchWeight(
11235 AsmOperandInfo &info, const char *constraint) const {
11237 Value *CallOperandVal = info.CallOperandVal;
11238 // If we don't have a value, we can't do a match,
11239 // but allow it at the lowest weight.
11240 if (CallOperandVal == NULL)
11242 // Look at the constraint type.
11243 switch (*constraint) {
11245 return TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11248 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
11249 if (C->getZExtValue() <= 31)
11258 /// LowerXConstraint - try to replace an X constraint, which matches anything,
11259 /// with another that has more specific requirements based on the type of the
11260 /// corresponding operand.
11261 const char *X86TargetLowering::
11262 LowerXConstraint(EVT ConstraintVT) const {
11263 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
11264 // 'f' like normal targets.
11265 if (ConstraintVT.isFloatingPoint()) {
11266 if (Subtarget->hasSSE2())
11268 if (Subtarget->hasSSE1())
11272 return TargetLowering::LowerXConstraint(ConstraintVT);
11275 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11276 /// vector. If it is invalid, don't add anything to Ops.
11277 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11279 std::vector<SDValue>&Ops,
11280 SelectionDAG &DAG) const {
11281 SDValue Result(0, 0);
11283 switch (Constraint) {
11286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11287 if (C->getZExtValue() <= 31) {
11288 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11295 if (C->getZExtValue() <= 63) {
11296 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11303 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
11304 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11311 if (C->getZExtValue() <= 255) {
11312 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11318 // 32-bit signed value
11319 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11320 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11321 C->getSExtValue())) {
11322 // Widen to 64 bits here to get it sign extended.
11323 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
11326 // FIXME gcc accepts some relocatable values here too, but only in certain
11327 // memory models; it's complicated.
11332 // 32-bit unsigned value
11333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
11334 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
11335 C->getZExtValue())) {
11336 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
11340 // FIXME gcc accepts some relocatable values here too, but only in certain
11341 // memory models; it's complicated.
11345 // Literal immediates are always ok.
11346 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
11347 // Widen to 64 bits here to get it sign extended.
11348 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
11352 // In any sort of PIC mode addresses need to be computed at runtime by
11353 // adding in a register or some sort of table lookup. These can't
11354 // be used as immediates.
11355 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
11358 // If we are in non-pic codegen mode, we allow the address of a global (with
11359 // an optional displacement) to be used with 'i'.
11360 GlobalAddressSDNode *GA = 0;
11361 int64_t Offset = 0;
11363 // Match either (GA), (GA+C), (GA+C1+C2), etc.
11365 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
11366 Offset += GA->getOffset();
11368 } else if (Op.getOpcode() == ISD::ADD) {
11369 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11370 Offset += C->getZExtValue();
11371 Op = Op.getOperand(0);
11374 } else if (Op.getOpcode() == ISD::SUB) {
11375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
11376 Offset += -C->getZExtValue();
11377 Op = Op.getOperand(0);
11382 // Otherwise, this isn't something we can handle, reject it.
11386 const GlobalValue *GV = GA->getGlobal();
11387 // If we require an extra load to get this address, as in PIC mode, we
11388 // can't accept it.
11389 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
11390 getTargetMachine())))
11393 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
11394 GA->getValueType(0), Offset);
11399 if (Result.getNode()) {
11400 Ops.push_back(Result);
11403 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11406 std::vector<unsigned> X86TargetLowering::
11407 getRegClassForInlineAsmConstraint(const std::string &Constraint,
11409 if (Constraint.size() == 1) {
11410 // FIXME: not handling fp-stack yet!
11411 switch (Constraint[0]) { // GCC X86 Constraint Letters
11412 default: break; // Unknown constraint letter
11413 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
11414 if (Subtarget->is64Bit()) {
11415 if (VT == MVT::i32)
11416 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
11417 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
11418 X86::R10D,X86::R11D,X86::R12D,
11419 X86::R13D,X86::R14D,X86::R15D,
11420 X86::EBP, X86::ESP, 0);
11421 else if (VT == MVT::i16)
11422 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
11423 X86::SI, X86::DI, X86::R8W,X86::R9W,
11424 X86::R10W,X86::R11W,X86::R12W,
11425 X86::R13W,X86::R14W,X86::R15W,
11426 X86::BP, X86::SP, 0);
11427 else if (VT == MVT::i8)
11428 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
11429 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
11430 X86::R10B,X86::R11B,X86::R12B,
11431 X86::R13B,X86::R14B,X86::R15B,
11432 X86::BPL, X86::SPL, 0);
11434 else if (VT == MVT::i64)
11435 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
11436 X86::RSI, X86::RDI, X86::R8, X86::R9,
11437 X86::R10, X86::R11, X86::R12,
11438 X86::R13, X86::R14, X86::R15,
11439 X86::RBP, X86::RSP, 0);
11443 // 32-bit fallthrough
11444 case 'Q': // Q_REGS
11445 if (VT == MVT::i32)
11446 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
11447 else if (VT == MVT::i16)
11448 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
11449 else if (VT == MVT::i8)
11450 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
11451 else if (VT == MVT::i64)
11452 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
11457 return std::vector<unsigned>();
11460 std::pair<unsigned, const TargetRegisterClass*>
11461 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
11463 // First, see if this is a constraint that directly corresponds to an LLVM
11465 if (Constraint.size() == 1) {
11466 // GCC Constraint Letters
11467 switch (Constraint[0]) {
11469 case 'r': // GENERAL_REGS
11470 case 'l': // INDEX_REGS
11472 return std::make_pair(0U, X86::GR8RegisterClass);
11473 if (VT == MVT::i16)
11474 return std::make_pair(0U, X86::GR16RegisterClass);
11475 if (VT == MVT::i32 || !Subtarget->is64Bit())
11476 return std::make_pair(0U, X86::GR32RegisterClass);
11477 return std::make_pair(0U, X86::GR64RegisterClass);
11478 case 'R': // LEGACY_REGS
11480 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
11481 if (VT == MVT::i16)
11482 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
11483 if (VT == MVT::i32 || !Subtarget->is64Bit())
11484 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
11485 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
11486 case 'f': // FP Stack registers.
11487 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
11488 // value to the correct fpstack register class.
11489 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
11490 return std::make_pair(0U, X86::RFP32RegisterClass);
11491 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
11492 return std::make_pair(0U, X86::RFP64RegisterClass);
11493 return std::make_pair(0U, X86::RFP80RegisterClass);
11494 case 'y': // MMX_REGS if MMX allowed.
11495 if (!Subtarget->hasMMX()) break;
11496 return std::make_pair(0U, X86::VR64RegisterClass);
11497 case 'Y': // SSE_REGS if SSE2 allowed
11498 if (!Subtarget->hasSSE2()) break;
11500 case 'x': // SSE_REGS if SSE1 allowed
11501 if (!Subtarget->hasSSE1()) break;
11503 switch (VT.getSimpleVT().SimpleTy) {
11505 // Scalar SSE types.
11508 return std::make_pair(0U, X86::FR32RegisterClass);
11511 return std::make_pair(0U, X86::FR64RegisterClass);
11519 return std::make_pair(0U, X86::VR128RegisterClass);
11525 // Use the default implementation in TargetLowering to convert the register
11526 // constraint into a member of a register class.
11527 std::pair<unsigned, const TargetRegisterClass*> Res;
11528 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
11530 // Not found as a standard register?
11531 if (Res.second == 0) {
11532 // Map st(0) -> st(7) -> ST0
11533 if (Constraint.size() == 7 && Constraint[0] == '{' &&
11534 tolower(Constraint[1]) == 's' &&
11535 tolower(Constraint[2]) == 't' &&
11536 Constraint[3] == '(' &&
11537 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
11538 Constraint[5] == ')' &&
11539 Constraint[6] == '}') {
11541 Res.first = X86::ST0+Constraint[4]-'0';
11542 Res.second = X86::RFP80RegisterClass;
11546 // GCC allows "st(0)" to be called just plain "st".
11547 if (StringRef("{st}").equals_lower(Constraint)) {
11548 Res.first = X86::ST0;
11549 Res.second = X86::RFP80RegisterClass;
11554 if (StringRef("{flags}").equals_lower(Constraint)) {
11555 Res.first = X86::EFLAGS;
11556 Res.second = X86::CCRRegisterClass;
11560 // 'A' means EAX + EDX.
11561 if (Constraint == "A") {
11562 Res.first = X86::EAX;
11563 Res.second = X86::GR32_ADRegisterClass;
11569 // Otherwise, check to see if this is a register class of the wrong value
11570 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
11571 // turn into {ax},{dx}.
11572 if (Res.second->hasType(VT))
11573 return Res; // Correct type already, nothing to do.
11575 // All of the single-register GCC register classes map their values onto
11576 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
11577 // really want an 8-bit or 32-bit register, map to the appropriate register
11578 // class and return the appropriate register.
11579 if (Res.second == X86::GR16RegisterClass) {
11580 if (VT == MVT::i8) {
11581 unsigned DestReg = 0;
11582 switch (Res.first) {
11584 case X86::AX: DestReg = X86::AL; break;
11585 case X86::DX: DestReg = X86::DL; break;
11586 case X86::CX: DestReg = X86::CL; break;
11587 case X86::BX: DestReg = X86::BL; break;
11590 Res.first = DestReg;
11591 Res.second = X86::GR8RegisterClass;
11593 } else if (VT == MVT::i32) {
11594 unsigned DestReg = 0;
11595 switch (Res.first) {
11597 case X86::AX: DestReg = X86::EAX; break;
11598 case X86::DX: DestReg = X86::EDX; break;
11599 case X86::CX: DestReg = X86::ECX; break;
11600 case X86::BX: DestReg = X86::EBX; break;
11601 case X86::SI: DestReg = X86::ESI; break;
11602 case X86::DI: DestReg = X86::EDI; break;
11603 case X86::BP: DestReg = X86::EBP; break;
11604 case X86::SP: DestReg = X86::ESP; break;
11607 Res.first = DestReg;
11608 Res.second = X86::GR32RegisterClass;
11610 } else if (VT == MVT::i64) {
11611 unsigned DestReg = 0;
11612 switch (Res.first) {
11614 case X86::AX: DestReg = X86::RAX; break;
11615 case X86::DX: DestReg = X86::RDX; break;
11616 case X86::CX: DestReg = X86::RCX; break;
11617 case X86::BX: DestReg = X86::RBX; break;
11618 case X86::SI: DestReg = X86::RSI; break;
11619 case X86::DI: DestReg = X86::RDI; break;
11620 case X86::BP: DestReg = X86::RBP; break;
11621 case X86::SP: DestReg = X86::RSP; break;
11624 Res.first = DestReg;
11625 Res.second = X86::GR64RegisterClass;
11628 } else if (Res.second == X86::FR32RegisterClass ||
11629 Res.second == X86::FR64RegisterClass ||
11630 Res.second == X86::VR128RegisterClass) {
11631 // Handle references to XMM physical registers that got mapped into the
11632 // wrong class. This can happen with constraints like {xmm0} where the
11633 // target independent register mapper will just pick the first match it can
11634 // find, ignoring the required type.
11635 if (VT == MVT::f32)
11636 Res.second = X86::FR32RegisterClass;
11637 else if (VT == MVT::f64)
11638 Res.second = X86::FR64RegisterClass;
11639 else if (X86::VR128RegisterClass->hasType(VT))
11640 Res.second = X86::VR128RegisterClass;