1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/StringExtras.h"
40 #include "llvm/ParameterAttributes.h"
43 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
44 : TargetLowering(TM) {
45 Subtarget = &TM.getSubtarget<X86Subtarget>();
46 X86ScalarSSEf64 = Subtarget->hasSSE2();
47 X86ScalarSSEf32 = Subtarget->hasSSE1();
48 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
51 RegInfo = TM.getRegisterInfo();
53 // Set up the TargetLowering object.
55 // X86 is weird, it always uses i8 for shift amounts and setcc results.
56 setShiftAmountType(MVT::i8);
57 setSetCCResultType(MVT::i8);
58 setSetCCResultContents(ZeroOrOneSetCCResult);
59 setSchedulingPreference(SchedulingForRegPressure);
60 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
61 setStackPointerRegisterToSaveRestore(X86StackPtr);
63 if (Subtarget->isTargetDarwin()) {
64 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(false);
66 setUseUnderscoreLongJmp(false);
67 } else if (Subtarget->isTargetMingw()) {
68 // MS runtime is weird: it exports _setjmp, but longjmp!
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(false);
72 setUseUnderscoreSetJmp(true);
73 setUseUnderscoreLongJmp(true);
76 // Set up the register classes.
77 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
78 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
79 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
80 if (Subtarget->is64Bit())
81 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
83 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
85 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
87 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
88 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
89 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
91 if (Subtarget->is64Bit()) {
92 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
93 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
96 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
97 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
99 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
102 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
104 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
105 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
106 // SSE has no i16 to fp conversion, only i32
107 if (X86ScalarSSEf32) {
108 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
109 // f32 and f64 cases are Legal, f80 case is not
110 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
112 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
113 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
116 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
117 // are Legal, f80 is custom lowered.
118 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
119 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
121 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
123 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
124 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
126 if (X86ScalarSSEf32) {
127 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
128 // f32 and f64 cases are Legal, f80 case is not
129 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
131 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
132 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
135 // Handle FP_TO_UINT by promoting the destination to a larger signed
137 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
138 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
139 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
141 if (Subtarget->is64Bit()) {
142 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
143 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
145 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
146 // Expand FP_TO_UINT into a select.
147 // FIXME: We would like to use a Custom expander here eventually to do
148 // the optimal thing for SSE vs. the default expansion in the legalizer.
149 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
151 // With SSE3 we can use fisttpll to convert to a signed i64.
152 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
155 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
156 if (!X86ScalarSSEf64) {
157 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
158 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
161 // Scalar integer multiply, multiply-high, divide, and remainder are
162 // lowered to use operations that produce two results, to match the
163 // available instructions. This exposes the two-result form to trivial
164 // CSE, which is able to combine x/y and x%y into a single instruction,
165 // for example. The single-result multiply instructions are introduced
166 // in X86ISelDAGToDAG.cpp, after CSE, for uses where the the high part
168 setOperationAction(ISD::MUL , MVT::i8 , Expand);
169 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
170 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
171 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
172 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
173 setOperationAction(ISD::SREM , MVT::i8 , Expand);
174 setOperationAction(ISD::UREM , MVT::i8 , Expand);
175 setOperationAction(ISD::MUL , MVT::i16 , Expand);
176 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
177 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
178 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
179 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
180 setOperationAction(ISD::SREM , MVT::i16 , Expand);
181 setOperationAction(ISD::UREM , MVT::i16 , Expand);
182 setOperationAction(ISD::MUL , MVT::i32 , Expand);
183 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
187 setOperationAction(ISD::SREM , MVT::i32 , Expand);
188 setOperationAction(ISD::UREM , MVT::i32 , Expand);
189 setOperationAction(ISD::MUL , MVT::i64 , Expand);
190 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
191 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
192 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
193 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
194 setOperationAction(ISD::SREM , MVT::i64 , Expand);
195 setOperationAction(ISD::UREM , MVT::i64 , Expand);
197 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
198 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
199 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
200 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
201 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
202 if (Subtarget->is64Bit())
203 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
205 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
206 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
207 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
208 setOperationAction(ISD::FREM , MVT::f64 , Expand);
209 setOperationAction(ISD::FLT_ROUNDS , MVT::i32 , Custom);
211 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
212 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
213 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
214 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
216 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
217 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
218 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
219 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
220 if (Subtarget->is64Bit()) {
221 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
222 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
223 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
226 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
227 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
229 // These should be promoted to a larger select which is supported.
230 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
231 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
232 // X86 wants to expand cmov itself.
233 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
234 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
235 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
236 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
237 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
238 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
239 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
240 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
241 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
242 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
243 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
246 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
248 // X86 ret instruction may pop stack.
249 setOperationAction(ISD::RET , MVT::Other, Custom);
250 if (!Subtarget->is64Bit())
251 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
254 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
255 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
256 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
257 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
258 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
259 if (Subtarget->is64Bit()) {
260 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
261 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
262 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
263 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
265 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
266 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
267 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
268 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
269 // X86 wants to expand memset / memcpy itself.
270 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
271 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
273 // Use the default ISD::LOCATION expansion.
274 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
275 // FIXME - use subtarget debug flags
276 if (!Subtarget->isTargetDarwin() &&
277 !Subtarget->isTargetELF() &&
278 !Subtarget->isTargetCygMing())
279 setOperationAction(ISD::LABEL, MVT::Other, Expand);
281 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
282 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
283 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
284 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
285 if (Subtarget->is64Bit()) {
287 setExceptionPointerRegister(X86::RAX);
288 setExceptionSelectorRegister(X86::RDX);
290 setExceptionPointerRegister(X86::EAX);
291 setExceptionSelectorRegister(X86::EDX);
293 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
295 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 setOperationAction(ISD::VAARG , MVT::Other, Expand);
300 setOperationAction(ISD::VAEND , MVT::Other, Expand);
301 if (Subtarget->is64Bit())
302 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
304 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
306 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
307 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
308 if (Subtarget->is64Bit())
309 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
310 if (Subtarget->isTargetCygMing())
311 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
313 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
315 if (X86ScalarSSEf64) {
316 // f32 and f64 use SSE.
317 // Set up the FP register classes.
318 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
319 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
321 // Use ANDPD to simulate FABS.
322 setOperationAction(ISD::FABS , MVT::f64, Custom);
323 setOperationAction(ISD::FABS , MVT::f32, Custom);
325 // Use XORP to simulate FNEG.
326 setOperationAction(ISD::FNEG , MVT::f64, Custom);
327 setOperationAction(ISD::FNEG , MVT::f32, Custom);
329 // Use ANDPD and ORPD to simulate FCOPYSIGN.
330 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
331 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
333 // We don't support sin/cos/fmod
334 setOperationAction(ISD::FSIN , MVT::f64, Expand);
335 setOperationAction(ISD::FCOS , MVT::f64, Expand);
336 setOperationAction(ISD::FREM , MVT::f64, Expand);
337 setOperationAction(ISD::FSIN , MVT::f32, Expand);
338 setOperationAction(ISD::FCOS , MVT::f32, Expand);
339 setOperationAction(ISD::FREM , MVT::f32, Expand);
341 // Expand FP immediates into loads from the stack, except for the special
343 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
344 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
345 addLegalFPImmediate(APFloat(+0.0)); // xorpd
346 addLegalFPImmediate(APFloat(+0.0f)); // xorps
348 // Conversions to long double (in X87) go through memory.
349 setConvertAction(MVT::f32, MVT::f80, Expand);
350 setConvertAction(MVT::f64, MVT::f80, Expand);
352 // Conversions from long double (in X87) go through memory.
353 setConvertAction(MVT::f80, MVT::f32, Expand);
354 setConvertAction(MVT::f80, MVT::f64, Expand);
355 } else if (X86ScalarSSEf32) {
356 // Use SSE for f32, x87 for f64.
357 // Set up the FP register classes.
358 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
359 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
361 // Use ANDPS to simulate FABS.
362 setOperationAction(ISD::FABS , MVT::f32, Custom);
364 // Use XORP to simulate FNEG.
365 setOperationAction(ISD::FNEG , MVT::f32, Custom);
367 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
369 // Use ANDPS and ORPS to simulate FCOPYSIGN.
370 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
371 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
373 // We don't support sin/cos/fmod
374 setOperationAction(ISD::FSIN , MVT::f32, Expand);
375 setOperationAction(ISD::FCOS , MVT::f32, Expand);
376 setOperationAction(ISD::FREM , MVT::f32, Expand);
378 // Expand FP immediates into loads from the stack, except for the special
380 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
381 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
382 addLegalFPImmediate(APFloat(+0.0f)); // xorps
383 addLegalFPImmediate(APFloat(+0.0)); // FLD0
384 addLegalFPImmediate(APFloat(+1.0)); // FLD1
385 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
386 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
388 // SSE->x87 conversions go through memory.
389 setConvertAction(MVT::f32, MVT::f64, Expand);
390 setConvertAction(MVT::f32, MVT::f80, Expand);
392 // x87->SSE truncations need to go through memory.
393 setConvertAction(MVT::f80, MVT::f32, Expand);
394 setConvertAction(MVT::f64, MVT::f32, Expand);
395 // And x87->x87 truncations also.
396 setConvertAction(MVT::f80, MVT::f64, Expand);
399 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
400 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
403 // f32 and f64 in x87.
404 // Set up the FP register classes.
405 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
406 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
408 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
409 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
410 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
411 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
413 // Floating truncations need to go through memory.
414 setConvertAction(MVT::f80, MVT::f32, Expand);
415 setConvertAction(MVT::f64, MVT::f32, Expand);
416 setConvertAction(MVT::f80, MVT::f64, Expand);
419 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
420 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
423 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
424 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
425 addLegalFPImmediate(APFloat(+0.0)); // FLD0
426 addLegalFPImmediate(APFloat(+1.0)); // FLD1
427 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
428 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
429 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
430 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
431 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
432 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
435 // Long double always uses X87.
436 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
437 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
438 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
439 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
441 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
442 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
445 // Always use a library call for pow.
446 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
447 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
448 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
450 // First set operation action for all vector types to expand. Then we
451 // will selectively turn on ones that can be effectively codegen'd.
452 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
453 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
454 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
455 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
456 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
457 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
458 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
459 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
460 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
461 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
462 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
463 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
464 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
465 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
466 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
467 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
469 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
470 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
471 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
472 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
473 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
474 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
475 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
476 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
477 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
478 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
479 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
480 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
481 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
482 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
483 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
484 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
485 setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
486 setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
487 setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
488 setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
489 setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
490 setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
493 if (Subtarget->hasMMX()) {
494 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
495 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
496 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
497 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
499 // FIXME: add MMX packed arithmetics
501 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
502 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
503 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
504 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
506 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
507 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
508 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
509 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
511 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
512 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
514 setOperationAction(ISD::AND, MVT::v8i8, Promote);
515 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
516 setOperationAction(ISD::AND, MVT::v4i16, Promote);
517 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
518 setOperationAction(ISD::AND, MVT::v2i32, Promote);
519 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
520 setOperationAction(ISD::AND, MVT::v1i64, Legal);
522 setOperationAction(ISD::OR, MVT::v8i8, Promote);
523 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
524 setOperationAction(ISD::OR, MVT::v4i16, Promote);
525 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
526 setOperationAction(ISD::OR, MVT::v2i32, Promote);
527 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
528 setOperationAction(ISD::OR, MVT::v1i64, Legal);
530 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
531 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
532 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
533 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
534 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
535 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
536 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
538 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
539 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
540 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
541 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
542 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
543 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
544 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
546 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
547 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
548 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
549 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
551 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
552 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
553 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
554 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
556 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
557 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
558 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
559 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
562 if (Subtarget->hasSSE1()) {
563 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
565 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
566 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
567 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
568 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
569 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
570 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
571 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
572 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
573 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
574 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
575 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
578 if (Subtarget->hasSSE2()) {
579 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
580 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
581 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
582 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
583 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
585 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
586 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
587 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
588 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
589 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
590 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
591 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
592 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
593 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
594 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
595 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
596 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
597 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
598 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
599 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
601 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
602 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
603 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
604 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
605 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
606 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
608 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
609 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
610 // Do not attempt to custom lower non-power-of-2 vectors
611 if (!isPowerOf2_32(MVT::getVectorNumElements(VT)))
613 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
614 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
615 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
617 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
618 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
619 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
620 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
621 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
622 if (Subtarget->is64Bit())
623 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
625 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
626 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
627 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
628 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
629 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
630 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
631 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
632 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
633 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
634 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
635 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
636 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
639 // Custom lower v2i64 and v2f64 selects.
640 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
641 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
642 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
643 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
646 // We want to custom lower some of our intrinsics.
647 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
649 // We have target-specific dag combine patterns for the following nodes:
650 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
651 setTargetDAGCombine(ISD::SELECT);
653 computeRegisterProperties();
655 // FIXME: These should be based on subtarget info. Plus, the values should
656 // be smaller when we are in optimizing for size mode.
657 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
658 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
659 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
660 allowUnalignedMemoryAccesses = true; // x86 supports it!
664 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
666 SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
667 SelectionDAG &DAG) const {
668 if (usesGlobalOffsetTable())
669 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
670 if (!Subtarget->isPICStyleRIPRel())
671 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
675 //===----------------------------------------------------------------------===//
676 // Return Value Calling Convention Implementation
677 //===----------------------------------------------------------------------===//
679 #include "X86GenCallingConv.inc"
681 /// GetPossiblePreceedingTailCall - Get preceeding X86ISD::TAILCALL node if it
682 /// exists skip possible ISD:TokenFactor.
683 static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain) {
684 if (Chain.getOpcode()==X86ISD::TAILCALL) {
686 } else if (Chain.getOpcode()==ISD::TokenFactor) {
687 if (Chain.getNumOperands() &&
688 Chain.getOperand(0).getOpcode()==X86ISD::TAILCALL)
689 return Chain.getOperand(0);
694 /// LowerRET - Lower an ISD::RET node.
695 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
696 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
698 SmallVector<CCValAssign, 16> RVLocs;
699 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
700 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
701 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
702 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
704 // If this is the first return lowered for this function, add the regs to the
705 // liveout set for the function.
706 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
707 for (unsigned i = 0; i != RVLocs.size(); ++i)
708 if (RVLocs[i].isRegLoc())
709 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
711 SDOperand Chain = Op.getOperand(0);
713 // Handle tail call return.
714 Chain = GetPossiblePreceedingTailCall(Chain);
715 if (Chain.getOpcode() == X86ISD::TAILCALL) {
716 SDOperand TailCall = Chain;
717 SDOperand TargetAddress = TailCall.getOperand(1);
718 SDOperand StackAdjustment = TailCall.getOperand(2);
719 assert ( ((TargetAddress.getOpcode() == ISD::Register &&
720 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
721 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
722 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
723 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
724 "Expecting an global address, external symbol, or register");
725 assert( StackAdjustment.getOpcode() == ISD::Constant &&
726 "Expecting a const value");
728 SmallVector<SDOperand,8> Operands;
729 Operands.push_back(Chain.getOperand(0));
730 Operands.push_back(TargetAddress);
731 Operands.push_back(StackAdjustment);
732 // Copy registers used by the call. Last operand is a flag so it is not
734 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
735 Operands.push_back(Chain.getOperand(i));
737 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
744 // Copy the result values into the output registers.
745 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
746 RVLocs[0].getLocReg() != X86::ST0) {
747 for (unsigned i = 0; i != RVLocs.size(); ++i) {
748 CCValAssign &VA = RVLocs[i];
749 assert(VA.isRegLoc() && "Can only return in registers!");
750 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
752 Flag = Chain.getValue(1);
755 // We need to handle a destination of ST0 specially, because it isn't really
757 SDOperand Value = Op.getOperand(1);
759 // If this is an FP return with ScalarSSE, we need to move the value from
760 // an XMM register onto the fp-stack.
761 if ((X86ScalarSSEf32 && RVLocs[0].getValVT()==MVT::f32) ||
762 (X86ScalarSSEf64 && RVLocs[0].getValVT()==MVT::f64)) {
765 // If this is a load into a scalarsse value, don't store the loaded value
766 // back to the stack, only to reload it: just replace the scalar-sse load.
767 if (ISD::isNON_EXTLoad(Value.Val) &&
768 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
769 Chain = Value.getOperand(0);
770 MemLoc = Value.getOperand(1);
772 // Spill the value to memory and reload it into top of stack.
773 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
774 MachineFunction &MF = DAG.getMachineFunction();
775 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
776 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
777 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
779 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other);
780 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
781 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
782 Chain = Value.getValue(1);
785 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
786 SDOperand Ops[] = { Chain, Value };
787 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
788 Flag = Chain.getValue(1);
791 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
793 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
795 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
799 /// LowerCallResult - Lower the result values of an ISD::CALL into the
800 /// appropriate copies out of appropriate physical registers. This assumes that
801 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
802 /// being lowered. The returns a SDNode with the same number of values as the
804 SDNode *X86TargetLowering::
805 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
806 unsigned CallingConv, SelectionDAG &DAG) {
808 // Assign locations to each value returned by this call.
809 SmallVector<CCValAssign, 16> RVLocs;
810 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
811 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
812 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
814 SmallVector<SDOperand, 8> ResultVals;
816 // Copy all of the result registers out of their specified physreg.
817 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
818 for (unsigned i = 0; i != RVLocs.size(); ++i) {
819 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
820 RVLocs[i].getValVT(), InFlag).getValue(1);
821 InFlag = Chain.getValue(2);
822 ResultVals.push_back(Chain.getValue(0));
825 // Copies from the FP stack are special, as ST0 isn't a valid register
826 // before the fp stackifier runs.
828 // Copy ST0 into an RFP register with FP_GET_RESULT.
829 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other, MVT::Flag);
830 SDOperand GROps[] = { Chain, InFlag };
831 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
832 Chain = RetVal.getValue(1);
833 InFlag = RetVal.getValue(2);
835 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
837 if ((X86ScalarSSEf32 && RVLocs[0].getValVT() == MVT::f32) ||
838 (X86ScalarSSEf64 && RVLocs[0].getValVT() == MVT::f64)) {
840 const Value *SrcVal = 0;
841 int SrcValOffset = 0;
842 MVT::ValueType RetStoreVT = RVLocs[0].getValVT();
844 // Determine where to store the value. If the call result is directly
845 // used by a store, see if we can store directly into the location. In
846 // this case, we'll end up producing a fst + movss[load] + movss[store] to
847 // the same location, and the two movss's will be nuked as dead. This
848 // optimizes common things like "*D = atof(..)" to not need an
849 // intermediate stack slot.
850 if (SDOperand(TheCall, 0).hasOneUse() &&
851 SDOperand(TheCall, 1).hasOneUse()) {
852 // In addition to direct uses, we also support a FP_ROUND that uses the
853 // value, if it is directly stored somewhere.
854 SDNode *User = *TheCall->use_begin();
855 if (User->getOpcode() == ISD::FP_ROUND && User->hasOneUse())
856 User = *User->use_begin();
858 // Ok, we have one use of the value and one use of the chain. See if
859 // they are the same node: a store.
860 if (StoreSDNode *N = dyn_cast<StoreSDNode>(User)) {
861 // Verify that the value being stored is either the call or a
862 // truncation of the call.
863 SDNode *StoreVal = N->getValue().Val;
864 if (StoreVal == TheCall)
866 else if (StoreVal->getOpcode() == ISD::FP_ROUND &&
867 StoreVal->hasOneUse() &&
868 StoreVal->getOperand(0).Val == TheCall)
873 if (N && N->getChain().Val == TheCall &&
874 !N->isVolatile() && !N->isTruncatingStore() &&
875 N->getAddressingMode() == ISD::UNINDEXED) {
876 StoreLoc = N->getBasePtr();
877 SrcVal = N->getSrcValue();
878 SrcValOffset = N->getSrcValueOffset();
879 RetStoreVT = N->getValue().getValueType();
884 // If we weren't able to optimize the result, just create a temporary
886 if (StoreLoc.Val == 0) {
887 MachineFunction &MF = DAG.getMachineFunction();
888 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
889 StoreLoc = DAG.getFrameIndex(SSFI, getPointerTy());
892 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
893 // shouldn't be necessary except that RFP cannot be live across
894 // multiple blocks (which could happen if a select gets lowered into
895 // multiple blocks and scheduled in between them). When stackifier is
896 // fixed, they can be uncoupled.
898 Chain, RetVal, StoreLoc, DAG.getValueType(RetStoreVT), InFlag
900 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
901 RetVal = DAG.getLoad(RetStoreVT, Chain,
902 StoreLoc, SrcVal, SrcValOffset);
903 Chain = RetVal.getValue(1);
905 // If we optimized a truncate, then extend the result back to its desired
907 if (RVLocs[0].getValVT() != RetStoreVT)
908 RetVal = DAG.getNode(ISD::FP_EXTEND, RVLocs[0].getValVT(), RetVal);
910 ResultVals.push_back(RetVal);
913 // Merge everything together with a MERGE_VALUES node.
914 ResultVals.push_back(Chain);
915 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
916 &ResultVals[0], ResultVals.size()).Val;
920 //===----------------------------------------------------------------------===//
921 // C & StdCall & Fast Calling Convention implementation
922 //===----------------------------------------------------------------------===//
923 // StdCall calling convention seems to be standard for many Windows' API
924 // routines and around. It differs from C calling convention just a little:
925 // callee should clean up the stack, not caller. Symbols should be also
926 // decorated in some fancy way :) It doesn't support any vector arguments.
927 // For info on fast calling convention see Fast Calling Convention (tail call)
928 // implementation LowerX86_32FastCCCallTo.
930 /// AddLiveIn - This helper function adds the specified physical register to the
931 /// MachineFunction as a live in value. It also creates a corresponding virtual
933 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
934 const TargetRegisterClass *RC) {
935 assert(RC->contains(PReg) && "Not the correct regclass!");
936 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
937 MF.getRegInfo().addLiveIn(PReg, VReg);
941 // Determines whether a CALL node uses struct return semantics.
942 static bool CallIsStructReturn(SDOperand Op) {
943 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
947 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(6));
948 return Flags->getValue() & ISD::ParamFlags::StructReturn;
951 // Determines whether a FORMAL_ARGUMENTS node uses struct return semantics.
952 static bool ArgsAreStructReturn(SDOperand Op) {
953 unsigned NumArgs = Op.Val->getNumValues() - 1;
957 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(3));
958 return Flags->getValue() & ISD::ParamFlags::StructReturn;
961 // Determines whether a CALL or FORMAL_ARGUMENTS node requires the callee to pop
962 // its own arguments. Callee pop is necessary to support tail calls.
963 bool X86TargetLowering::IsCalleePop(SDOperand Op) {
964 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
968 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
971 case CallingConv::X86_StdCall:
972 return !Subtarget->is64Bit();
973 case CallingConv::X86_FastCall:
974 return !Subtarget->is64Bit();
975 case CallingConv::Fast:
976 return PerformTailCallOpt;
980 // Selects the correct CCAssignFn for a CALL or FORMAL_ARGUMENTS node.
981 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
982 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
984 if (Subtarget->is64Bit())
985 if (CC == CallingConv::Fast && PerformTailCallOpt)
986 return CC_X86_64_TailCall;
990 if (CC == CallingConv::X86_FastCall)
991 return CC_X86_32_FastCall;
992 else if (CC == CallingConv::Fast && PerformTailCallOpt)
993 return CC_X86_32_TailCall;
998 // Selects the appropriate decoration to apply to a MachineFunction containing a
999 // given FORMAL_ARGUMENTS node.
1001 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
1002 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1003 if (CC == CallingConv::X86_FastCall)
1005 else if (CC == CallingConv::X86_StdCall)
1010 SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1011 const CCValAssign &VA,
1012 MachineFrameInfo *MFI,
1013 SDOperand Root, unsigned i) {
1014 // Create the nodes corresponding to a load from this parameter slot.
1015 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1016 VA.getLocMemOffset());
1017 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1019 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
1021 if (Flags & ISD::ParamFlags::ByVal)
1024 return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0);
1028 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
1029 MachineFunction &MF = DAG.getMachineFunction();
1030 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1032 const Function* Fn = MF.getFunction();
1033 if (Fn->hasExternalLinkage() &&
1034 Subtarget->isTargetCygMing() &&
1035 Fn->getName() == "main")
1036 FuncInfo->setForceFramePointer(true);
1038 // Decorate the function name.
1039 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1041 MachineFrameInfo *MFI = MF.getFrameInfo();
1042 SDOperand Root = Op.getOperand(0);
1043 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1044 unsigned CC = MF.getFunction()->getCallingConv();
1045 bool Is64Bit = Subtarget->is64Bit();
1047 assert(!(isVarArg && CC == CallingConv::Fast) &&
1048 "Var args not supported with calling convention fastcc");
1050 // Assign locations to all of the incoming arguments.
1051 SmallVector<CCValAssign, 16> ArgLocs;
1052 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1053 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
1055 SmallVector<SDOperand, 8> ArgValues;
1056 unsigned LastVal = ~0U;
1057 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1058 CCValAssign &VA = ArgLocs[i];
1059 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1061 assert(VA.getValNo() != LastVal &&
1062 "Don't support value assigned to multiple locs yet");
1063 LastVal = VA.getValNo();
1065 if (VA.isRegLoc()) {
1066 MVT::ValueType RegVT = VA.getLocVT();
1067 TargetRegisterClass *RC;
1068 if (RegVT == MVT::i32)
1069 RC = X86::GR32RegisterClass;
1070 else if (Is64Bit && RegVT == MVT::i64)
1071 RC = X86::GR64RegisterClass;
1072 else if (Is64Bit && RegVT == MVT::f32)
1073 RC = X86::FR32RegisterClass;
1074 else if (Is64Bit && RegVT == MVT::f64)
1075 RC = X86::FR64RegisterClass;
1077 assert(MVT::isVector(RegVT));
1078 if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) {
1079 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1082 RC = X86::VR128RegisterClass;
1085 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1086 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1088 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1089 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1091 if (VA.getLocInfo() == CCValAssign::SExt)
1092 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1093 DAG.getValueType(VA.getValVT()));
1094 else if (VA.getLocInfo() == CCValAssign::ZExt)
1095 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1096 DAG.getValueType(VA.getValVT()));
1098 if (VA.getLocInfo() != CCValAssign::Full)
1099 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1101 // Handle MMX values passed in GPRs.
1102 if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1103 MVT::getSizeInBits(RegVT) == 64)
1104 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1106 ArgValues.push_back(ArgValue);
1108 assert(VA.isMemLoc());
1109 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
1113 unsigned StackSize = CCInfo.getNextStackOffset();
1114 // align stack specially for tail calls
1115 if (CC == CallingConv::Fast)
1116 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1118 // If the function takes variable number of arguments, make a frame index for
1119 // the start of the first vararg value... for expansion of llvm.va_start.
1121 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1122 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1125 static const unsigned GPR64ArgRegs[] = {
1126 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1128 static const unsigned XMMArgRegs[] = {
1129 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1130 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1133 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1134 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1136 // For X86-64, if there are vararg parameters that are passed via
1137 // registers, then we must store them to their spots on the stack so they
1138 // may be loaded by deferencing the result of va_next.
1139 VarArgsGPOffset = NumIntRegs * 8;
1140 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1141 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1143 // Store the integer parameter registers.
1144 SmallVector<SDOperand, 8> MemOps;
1145 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1146 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1147 DAG.getConstant(VarArgsGPOffset,
1149 for (; NumIntRegs != 6; ++NumIntRegs) {
1150 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1151 X86::GR64RegisterClass);
1152 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1153 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1154 MemOps.push_back(Store);
1155 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1156 DAG.getConstant(8, getPointerTy()));
1159 // Now store the XMM (fp + vector) parameter registers.
1160 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1161 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1162 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1163 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1164 X86::VR128RegisterClass);
1165 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1166 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1167 MemOps.push_back(Store);
1168 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1169 DAG.getConstant(16, getPointerTy()));
1171 if (!MemOps.empty())
1172 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1173 &MemOps[0], MemOps.size());
1177 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1178 // arguments and the arguments after the retaddr has been pushed are
1180 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1181 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1182 (StackSize & 7) == 0)
1185 ArgValues.push_back(Root);
1187 // Some CCs need callee pop.
1188 if (IsCalleePop(Op)) {
1189 BytesToPopOnReturn = StackSize; // Callee pops everything.
1190 BytesCallerReserves = 0;
1192 BytesToPopOnReturn = 0; // Callee pops nothing.
1193 // If this is an sret function, the return should pop the hidden pointer.
1194 if (!Is64Bit && ArgsAreStructReturn(Op))
1195 BytesToPopOnReturn = 4;
1196 BytesCallerReserves = StackSize;
1200 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1201 if (CC == CallingConv::X86_FastCall)
1202 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1205 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1207 // Return the new list of results.
1208 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1209 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1212 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1213 MachineFunction &MF = DAG.getMachineFunction();
1214 SDOperand Chain = Op.getOperand(0);
1215 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1216 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1217 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1218 && CC == CallingConv::Fast && PerformTailCallOpt;
1219 SDOperand Callee = Op.getOperand(4);
1220 bool Is64Bit = Subtarget->is64Bit();
1222 assert(!(isVarArg && CC == CallingConv::Fast) &&
1223 "Var args not supported with calling convention fastcc");
1225 // Analyze operands of the call, assigning locations to each operand.
1226 SmallVector<CCValAssign, 16> ArgLocs;
1227 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1228 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
1230 // Get a count of how many bytes are to be pushed on the stack.
1231 unsigned NumBytes = CCInfo.getNextStackOffset();
1232 if (CC == CallingConv::Fast)
1233 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1235 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1236 // arguments and the arguments after the retaddr has been pushed are aligned.
1237 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1238 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1239 (NumBytes & 7) == 0)
1244 // Lower arguments at fp - stackoffset + fpdiff.
1245 unsigned NumBytesCallerPushed =
1246 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1247 FPDiff = NumBytesCallerPushed - NumBytes;
1249 // Set the delta of movement of the returnaddr stackslot.
1250 // But only set if delta is greater than previous delta.
1251 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1252 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1255 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1257 SDOperand RetAddrFrIdx, NewRetAddrFrIdx;
1259 // Adjust the Return address stack slot.
1261 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1262 RetAddrFrIdx = getReturnAddressFrameIndex(DAG);
1263 // Load the "old" Return address.
1265 DAG.getLoad(VT, Chain,RetAddrFrIdx, NULL, 0);
1266 // Calculate the new stack slot for the return address.
1267 int SlotSize = Is64Bit ? 8 : 4;
1268 int NewReturnAddrFI =
1269 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1270 NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1271 Chain = SDOperand(RetAddrFrIdx.Val, 1);
1275 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1276 SmallVector<SDOperand, 8> MemOpChains;
1280 // Walk the register/memloc assignments, inserting copies/loads.
1281 // For tail calls, lower arguments first to the stack slot where they would
1282 // normally - in case of a normal function call - be.
1283 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1284 CCValAssign &VA = ArgLocs[i];
1285 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1287 // Promote the value if needed.
1288 switch (VA.getLocInfo()) {
1289 default: assert(0 && "Unknown loc info!");
1290 case CCValAssign::Full: break;
1291 case CCValAssign::SExt:
1292 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1294 case CCValAssign::ZExt:
1295 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1297 case CCValAssign::AExt:
1298 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1302 if (VA.isRegLoc()) {
1303 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1305 assert(VA.isMemLoc());
1306 if (StackPtr.Val == 0)
1307 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1309 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1314 if (!MemOpChains.empty())
1315 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1316 &MemOpChains[0], MemOpChains.size());
1318 // Build a sequence of copy-to-reg nodes chained together with token chain
1319 // and flag operands which copy the outgoing args into registers.
1321 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1322 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1324 InFlag = Chain.getValue(1);
1328 InFlag = SDOperand(); // ??? Isn't this nuking the preceding loop's output?
1330 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1332 // Does not work with tail call since ebx is not restored correctly by
1333 // tailcaller. TODO: at least for x86 - verify for x86-64
1334 if (!IsTailCall && !Is64Bit &&
1335 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1336 Subtarget->isPICStyleGOT()) {
1337 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1338 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1340 InFlag = Chain.getValue(1);
1343 if (Is64Bit && isVarArg) {
1344 // From AMD64 ABI document:
1345 // For calls that may call functions that use varargs or stdargs
1346 // (prototype-less calls or calls to functions containing ellipsis (...) in
1347 // the declaration) %al is used as hidden argument to specify the number
1348 // of SSE registers used. The contents of %al do not need to match exactly
1349 // the number of registers, but must be an ubound on the number of SSE
1350 // registers used and is in the range 0 - 8 inclusive.
1352 // Count the number of XMM registers allocated.
1353 static const unsigned XMMArgRegs[] = {
1354 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1355 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1357 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1359 Chain = DAG.getCopyToReg(Chain, X86::AL,
1360 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1361 InFlag = Chain.getValue(1);
1364 // Copy from stack slots to stack slot of a tail called function. This needs
1365 // to be done because if we would lower the arguments directly to their real
1366 // stack slot we might end up overwriting each other.
1367 // TODO: To make this more efficient (sometimes saving a store/load) we could
1368 // analyse the arguments and emit this store/load/store sequence only for
1369 // arguments which would be overwritten otherwise.
1371 SmallVector<SDOperand, 8> MemOpChains2;
1375 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1376 CCValAssign &VA = ArgLocs[i];
1377 if (!VA.isRegLoc()) {
1378 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1379 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1381 // Get source stack slot.
1382 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(),
1384 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1385 // Create frame index.
1386 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1387 uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1388 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1389 FIN = DAG.getFrameIndex(FI, MVT::i32);
1390 if (Flags & ISD::ParamFlags::ByVal) {
1391 // Copy relative to framepointer.
1392 unsigned Align = 1 << ((Flags & ISD::ParamFlags::ByValAlign) >>
1393 ISD::ParamFlags::ByValAlignOffs);
1395 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1396 ISD::ParamFlags::ByValSizeOffs;
1398 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1399 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1400 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i1);
1402 MemOpChains2.push_back(DAG.getMemcpy(Chain, FIN, PtrOff, SizeNode,
1403 AlignNode,AlwaysInline));
1405 SDOperand LoadedArg = DAG.getLoad(VA.getValVT(), Chain, PtrOff,
1407 // Store relative to framepointer.
1408 MemOpChains2.push_back(DAG.getStore(Chain, LoadedArg, FIN, NULL, 0));
1413 if (!MemOpChains2.empty())
1414 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1415 &MemOpChains2[0], MemOpChains.size());
1417 // Store the return address to the appropriate stack slot.
1419 Chain = DAG.getStore(Chain,RetAddrFrIdx, NewRetAddrFrIdx, NULL, 0);
1422 // If the callee is a GlobalAddress node (quite common, every direct call is)
1423 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1424 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1425 // We should use extra load for direct calls to dllimported functions in
1427 if ((IsTailCall || !Is64Bit ||
1428 getTargetMachine().getCodeModel() != CodeModel::Large)
1429 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1430 getTargetMachine(), true))
1431 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1432 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1433 if (IsTailCall || !Is64Bit ||
1434 getTargetMachine().getCodeModel() != CodeModel::Large)
1435 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1436 } else if (IsTailCall) {
1437 assert(Callee.getOpcode() == ISD::LOAD &&
1438 "Function destination must be loaded into virtual register");
1439 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1441 Chain = DAG.getCopyToReg(Chain,
1442 DAG.getRegister(Opc, getPointerTy()) ,
1444 Callee = DAG.getRegister(Opc, getPointerTy());
1445 // Add register as live out.
1446 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1449 // Returns a chain & a flag for retval copy to use.
1450 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1451 SmallVector<SDOperand, 8> Ops;
1454 Ops.push_back(Chain);
1455 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1456 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1458 Ops.push_back(InFlag);
1459 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1460 InFlag = Chain.getValue(1);
1462 // Returns a chain & a flag for retval copy to use.
1463 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1467 Ops.push_back(Chain);
1468 Ops.push_back(Callee);
1471 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1473 // Add an implicit use GOT pointer in EBX.
1474 if (!IsTailCall && !Is64Bit &&
1475 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1476 Subtarget->isPICStyleGOT())
1477 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1479 // Add argument registers to the end of the list so that they are known live
1482 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1483 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1484 RegsToPass[i].second.getValueType()));
1487 Ops.push_back(InFlag);
1490 assert(InFlag.Val &&
1491 "Flag must be set. Depend on flag being set in LowerRET");
1492 Chain = DAG.getNode(X86ISD::TAILCALL,
1493 Op.Val->getVTList(), &Ops[0], Ops.size());
1495 return SDOperand(Chain.Val, Op.ResNo);
1498 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1499 InFlag = Chain.getValue(1);
1501 // Create the CALLSEQ_END node.
1502 unsigned NumBytesForCalleeToPush;
1503 if (IsCalleePop(Op))
1504 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1505 else if (!Is64Bit && CallIsStructReturn(Op))
1506 // If this is is a call to a struct-return function, the callee
1507 // pops the hidden struct pointer, so we have to push it back.
1508 // This is common for Darwin/X86, Linux & Mingw32 targets.
1509 NumBytesForCalleeToPush = 4;
1511 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1513 // Returns a flag for retval copy to use.
1514 Chain = DAG.getCALLSEQ_END(Chain,
1515 DAG.getConstant(NumBytes, getPointerTy()),
1516 DAG.getConstant(NumBytesForCalleeToPush,
1519 InFlag = Chain.getValue(1);
1521 // Handle result values, copying them out of physregs into vregs that we
1523 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1527 //===----------------------------------------------------------------------===//
1528 // FastCall Calling Convention implementation
1529 //===----------------------------------------------------------------------===//
1531 // The X86 'fastcall' calling convention passes up to two integer arguments in
1532 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
1533 // and requires that the callee pop its arguments off the stack (allowing proper
1534 // tail calls), and has the same return value conventions as C calling convs.
1536 // This calling convention always arranges for the callee pop value to be 8n+4
1537 // bytes, which is needed for tail recursion elimination and stack alignment
1541 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1542 const SDOperand &StackPtr,
1543 const CCValAssign &VA,
1546 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1547 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1548 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1549 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1550 if (Flags & ISD::ParamFlags::ByVal) {
1551 unsigned Align = 1 << ((Flags & ISD::ParamFlags::ByValAlign) >>
1552 ISD::ParamFlags::ByValAlignOffs);
1554 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1555 ISD::ParamFlags::ByValSizeOffs;
1557 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1558 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1559 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32);
1561 return DAG.getMemcpy(Chain, PtrOff, Arg, SizeNode, AlignNode,
1564 return DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1568 //===----------------------------------------------------------------------===//
1569 // Fast Calling Convention (tail call) implementation
1570 //===----------------------------------------------------------------------===//
1572 // Like std call, callee cleans arguments, convention except that ECX is
1573 // reserved for storing the tail called function address. Only 2 registers are
1574 // free for argument passing (inreg). Tail call optimization is performed
1576 // * tailcallopt is enabled
1577 // * caller/callee are fastcc
1578 // * elf/pic is disabled OR
1579 // * elf/pic enabled + callee is in module + callee has
1580 // visibility protected or hidden
1581 // To keep the stack aligned according to platform abi the function
1582 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1583 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1584 // If a tail called function callee has more arguments than the caller the
1585 // caller needs to make sure that there is room to move the RETADDR to. This is
1586 // achieved by reserving an area the size of the argument delta right after the
1587 // original REtADDR, but before the saved framepointer or the spilled registers
1588 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1600 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1601 /// for a 16 byte align requirement.
1602 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1603 SelectionDAG& DAG) {
1604 if (PerformTailCallOpt) {
1605 MachineFunction &MF = DAG.getMachineFunction();
1606 const TargetMachine &TM = MF.getTarget();
1607 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1608 unsigned StackAlignment = TFI.getStackAlignment();
1609 uint64_t AlignMask = StackAlignment - 1;
1610 int64_t Offset = StackSize;
1611 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1612 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1613 // Number smaller than 12 so just add the difference.
1614 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1616 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1617 Offset = ((~AlignMask) & Offset) + StackAlignment +
1618 (StackAlignment-SlotSize);
1625 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1626 /// following the call is a return. A function is eligible if caller/callee
1627 /// calling conventions match, currently only fastcc supports tail calls, and
1628 /// the function CALL is immediatly followed by a RET.
1629 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1631 SelectionDAG& DAG) const {
1632 if (!PerformTailCallOpt)
1635 // Check whether CALL node immediatly preceeds the RET node and whether the
1636 // return uses the result of the node or is a void return.
1637 unsigned NumOps = Ret.getNumOperands();
1639 (Ret.getOperand(0) == SDOperand(Call.Val,1) ||
1640 Ret.getOperand(0) == SDOperand(Call.Val,0))) ||
1642 Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) &&
1643 Ret.getOperand(1) == SDOperand(Call.Val,0))) {
1644 MachineFunction &MF = DAG.getMachineFunction();
1645 unsigned CallerCC = MF.getFunction()->getCallingConv();
1646 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1647 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1648 SDOperand Callee = Call.getOperand(4);
1649 // On elf/pic %ebx needs to be livein.
1650 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1651 !Subtarget->isPICStyleGOT())
1654 // Can only do local tail calls with PIC.
1655 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1656 return G->getGlobal()->hasHiddenVisibility()
1657 || G->getGlobal()->hasProtectedVisibility();
1664 //===----------------------------------------------------------------------===//
1665 // Other Lowering Hooks
1666 //===----------------------------------------------------------------------===//
1669 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1670 MachineFunction &MF = DAG.getMachineFunction();
1671 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1672 int ReturnAddrIndex = FuncInfo->getRAIndex();
1674 if (ReturnAddrIndex == 0) {
1675 // Set up a frame object for the return address.
1676 if (Subtarget->is64Bit())
1677 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1679 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1681 FuncInfo->setRAIndex(ReturnAddrIndex);
1684 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1689 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1690 /// specific condition code. It returns a false if it cannot do a direct
1691 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1693 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1694 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1695 SelectionDAG &DAG) {
1696 X86CC = X86::COND_INVALID;
1698 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1699 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1700 // X > -1 -> X == 0, jump !sign.
1701 RHS = DAG.getConstant(0, RHS.getValueType());
1702 X86CC = X86::COND_NS;
1704 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1705 // X < 0 -> X == 0, jump on sign.
1706 X86CC = X86::COND_S;
1708 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1710 RHS = DAG.getConstant(0, RHS.getValueType());
1711 X86CC = X86::COND_LE;
1716 switch (SetCCOpcode) {
1718 case ISD::SETEQ: X86CC = X86::COND_E; break;
1719 case ISD::SETGT: X86CC = X86::COND_G; break;
1720 case ISD::SETGE: X86CC = X86::COND_GE; break;
1721 case ISD::SETLT: X86CC = X86::COND_L; break;
1722 case ISD::SETLE: X86CC = X86::COND_LE; break;
1723 case ISD::SETNE: X86CC = X86::COND_NE; break;
1724 case ISD::SETULT: X86CC = X86::COND_B; break;
1725 case ISD::SETUGT: X86CC = X86::COND_A; break;
1726 case ISD::SETULE: X86CC = X86::COND_BE; break;
1727 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1730 // On a floating point condition, the flags are set as follows:
1732 // 0 | 0 | 0 | X > Y
1733 // 0 | 0 | 1 | X < Y
1734 // 1 | 0 | 0 | X == Y
1735 // 1 | 1 | 1 | unordered
1737 switch (SetCCOpcode) {
1740 case ISD::SETEQ: X86CC = X86::COND_E; break;
1741 case ISD::SETOLT: Flip = true; // Fallthrough
1743 case ISD::SETGT: X86CC = X86::COND_A; break;
1744 case ISD::SETOLE: Flip = true; // Fallthrough
1746 case ISD::SETGE: X86CC = X86::COND_AE; break;
1747 case ISD::SETUGT: Flip = true; // Fallthrough
1749 case ISD::SETLT: X86CC = X86::COND_B; break;
1750 case ISD::SETUGE: Flip = true; // Fallthrough
1752 case ISD::SETLE: X86CC = X86::COND_BE; break;
1754 case ISD::SETNE: X86CC = X86::COND_NE; break;
1755 case ISD::SETUO: X86CC = X86::COND_P; break;
1756 case ISD::SETO: X86CC = X86::COND_NP; break;
1759 std::swap(LHS, RHS);
1762 return X86CC != X86::COND_INVALID;
1765 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1766 /// code. Current x86 isa includes the following FP cmov instructions:
1767 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1768 static bool hasFPCMov(unsigned X86CC) {
1784 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1785 /// true if Op is undef or if its value falls within the specified range (L, H].
1786 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1787 if (Op.getOpcode() == ISD::UNDEF)
1790 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1791 return (Val >= Low && Val < Hi);
1794 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1795 /// true if Op is undef or if its value equal to the specified value.
1796 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1797 if (Op.getOpcode() == ISD::UNDEF)
1799 return cast<ConstantSDNode>(Op)->getValue() == Val;
1802 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1803 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1804 bool X86::isPSHUFDMask(SDNode *N) {
1805 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1807 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
1810 // Check if the value doesn't reference the second vector.
1811 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1812 SDOperand Arg = N->getOperand(i);
1813 if (Arg.getOpcode() == ISD::UNDEF) continue;
1814 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1815 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
1822 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1823 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1824 bool X86::isPSHUFHWMask(SDNode *N) {
1825 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1827 if (N->getNumOperands() != 8)
1830 // Lower quadword copied in order.
1831 for (unsigned i = 0; i != 4; ++i) {
1832 SDOperand Arg = N->getOperand(i);
1833 if (Arg.getOpcode() == ISD::UNDEF) continue;
1834 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1835 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1839 // Upper quadword shuffled.
1840 for (unsigned i = 4; i != 8; ++i) {
1841 SDOperand Arg = N->getOperand(i);
1842 if (Arg.getOpcode() == ISD::UNDEF) continue;
1843 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1844 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1845 if (Val < 4 || Val > 7)
1852 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1853 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1854 bool X86::isPSHUFLWMask(SDNode *N) {
1855 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1857 if (N->getNumOperands() != 8)
1860 // Upper quadword copied in order.
1861 for (unsigned i = 4; i != 8; ++i)
1862 if (!isUndefOrEqual(N->getOperand(i), i))
1865 // Lower quadword shuffled.
1866 for (unsigned i = 0; i != 4; ++i)
1867 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1873 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1874 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1875 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1876 if (NumElems != 2 && NumElems != 4) return false;
1878 unsigned Half = NumElems / 2;
1879 for (unsigned i = 0; i < Half; ++i)
1880 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1882 for (unsigned i = Half; i < NumElems; ++i)
1883 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1889 bool X86::isSHUFPMask(SDNode *N) {
1890 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1891 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1894 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
1895 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1896 /// half elements to come from vector 1 (which would equal the dest.) and
1897 /// the upper half to come from vector 2.
1898 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1899 if (NumOps != 2 && NumOps != 4) return false;
1901 unsigned Half = NumOps / 2;
1902 for (unsigned i = 0; i < Half; ++i)
1903 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1905 for (unsigned i = Half; i < NumOps; ++i)
1906 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1911 static bool isCommutedSHUFP(SDNode *N) {
1912 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1913 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1916 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1917 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1918 bool X86::isMOVHLPSMask(SDNode *N) {
1919 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1921 if (N->getNumOperands() != 4)
1924 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1925 return isUndefOrEqual(N->getOperand(0), 6) &&
1926 isUndefOrEqual(N->getOperand(1), 7) &&
1927 isUndefOrEqual(N->getOperand(2), 2) &&
1928 isUndefOrEqual(N->getOperand(3), 3);
1931 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1932 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1934 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1935 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1937 if (N->getNumOperands() != 4)
1940 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1941 return isUndefOrEqual(N->getOperand(0), 2) &&
1942 isUndefOrEqual(N->getOperand(1), 3) &&
1943 isUndefOrEqual(N->getOperand(2), 2) &&
1944 isUndefOrEqual(N->getOperand(3), 3);
1947 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1948 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1949 bool X86::isMOVLPMask(SDNode *N) {
1950 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1952 unsigned NumElems = N->getNumOperands();
1953 if (NumElems != 2 && NumElems != 4)
1956 for (unsigned i = 0; i < NumElems/2; ++i)
1957 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1960 for (unsigned i = NumElems/2; i < NumElems; ++i)
1961 if (!isUndefOrEqual(N->getOperand(i), i))
1967 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1968 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1970 bool X86::isMOVHPMask(SDNode *N) {
1971 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1973 unsigned NumElems = N->getNumOperands();
1974 if (NumElems != 2 && NumElems != 4)
1977 for (unsigned i = 0; i < NumElems/2; ++i)
1978 if (!isUndefOrEqual(N->getOperand(i), i))
1981 for (unsigned i = 0; i < NumElems/2; ++i) {
1982 SDOperand Arg = N->getOperand(i + NumElems/2);
1983 if (!isUndefOrEqual(Arg, i + NumElems))
1990 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1991 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1992 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1993 bool V2IsSplat = false) {
1994 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1997 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1998 SDOperand BitI = Elts[i];
1999 SDOperand BitI1 = Elts[i+1];
2000 if (!isUndefOrEqual(BitI, j))
2003 if (isUndefOrEqual(BitI1, NumElts))
2006 if (!isUndefOrEqual(BitI1, j + NumElts))
2014 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2015 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2016 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2019 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2020 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2021 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
2022 bool V2IsSplat = false) {
2023 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2026 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2027 SDOperand BitI = Elts[i];
2028 SDOperand BitI1 = Elts[i+1];
2029 if (!isUndefOrEqual(BitI, j + NumElts/2))
2032 if (isUndefOrEqual(BitI1, NumElts))
2035 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2043 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2044 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2045 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2048 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2049 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2051 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2052 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2054 unsigned NumElems = N->getNumOperands();
2055 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2058 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2059 SDOperand BitI = N->getOperand(i);
2060 SDOperand BitI1 = N->getOperand(i+1);
2062 if (!isUndefOrEqual(BitI, j))
2064 if (!isUndefOrEqual(BitI1, j))
2071 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2072 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2074 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2075 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2077 unsigned NumElems = N->getNumOperands();
2078 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2081 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2082 SDOperand BitI = N->getOperand(i);
2083 SDOperand BitI1 = N->getOperand(i + 1);
2085 if (!isUndefOrEqual(BitI, j))
2087 if (!isUndefOrEqual(BitI1, j))
2094 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2095 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2096 /// MOVSD, and MOVD, i.e. setting the lowest element.
2097 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
2098 if (NumElts != 2 && NumElts != 4)
2101 if (!isUndefOrEqual(Elts[0], NumElts))
2104 for (unsigned i = 1; i < NumElts; ++i) {
2105 if (!isUndefOrEqual(Elts[i], i))
2112 bool X86::isMOVLMask(SDNode *N) {
2113 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2114 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2117 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2118 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2119 /// element of vector 2 and the other elements to come from vector 1 in order.
2120 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2121 bool V2IsSplat = false,
2122 bool V2IsUndef = false) {
2123 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2126 if (!isUndefOrEqual(Ops[0], 0))
2129 for (unsigned i = 1; i < NumOps; ++i) {
2130 SDOperand Arg = Ops[i];
2131 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2132 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2133 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2140 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2141 bool V2IsUndef = false) {
2142 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2143 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2144 V2IsSplat, V2IsUndef);
2147 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2148 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2149 bool X86::isMOVSHDUPMask(SDNode *N) {
2150 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2152 if (N->getNumOperands() != 4)
2155 // Expect 1, 1, 3, 3
2156 for (unsigned i = 0; i < 2; ++i) {
2157 SDOperand Arg = N->getOperand(i);
2158 if (Arg.getOpcode() == ISD::UNDEF) continue;
2159 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2160 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2161 if (Val != 1) return false;
2165 for (unsigned i = 2; i < 4; ++i) {
2166 SDOperand Arg = N->getOperand(i);
2167 if (Arg.getOpcode() == ISD::UNDEF) continue;
2168 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2169 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2170 if (Val != 3) return false;
2174 // Don't use movshdup if it can be done with a shufps.
2178 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2179 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2180 bool X86::isMOVSLDUPMask(SDNode *N) {
2181 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2183 if (N->getNumOperands() != 4)
2186 // Expect 0, 0, 2, 2
2187 for (unsigned i = 0; i < 2; ++i) {
2188 SDOperand Arg = N->getOperand(i);
2189 if (Arg.getOpcode() == ISD::UNDEF) continue;
2190 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2191 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2192 if (Val != 0) return false;
2196 for (unsigned i = 2; i < 4; ++i) {
2197 SDOperand Arg = N->getOperand(i);
2198 if (Arg.getOpcode() == ISD::UNDEF) continue;
2199 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2200 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2201 if (Val != 2) return false;
2205 // Don't use movshdup if it can be done with a shufps.
2209 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2210 /// specifies a identity operation on the LHS or RHS.
2211 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2212 unsigned NumElems = N->getNumOperands();
2213 for (unsigned i = 0; i < NumElems; ++i)
2214 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2219 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2220 /// a splat of a single element.
2221 static bool isSplatMask(SDNode *N) {
2222 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2224 // This is a splat operation if each element of the permute is the same, and
2225 // if the value doesn't reference the second vector.
2226 unsigned NumElems = N->getNumOperands();
2227 SDOperand ElementBase;
2229 for (; i != NumElems; ++i) {
2230 SDOperand Elt = N->getOperand(i);
2231 if (isa<ConstantSDNode>(Elt)) {
2237 if (!ElementBase.Val)
2240 for (; i != NumElems; ++i) {
2241 SDOperand Arg = N->getOperand(i);
2242 if (Arg.getOpcode() == ISD::UNDEF) continue;
2243 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2244 if (Arg != ElementBase) return false;
2247 // Make sure it is a splat of the first vector operand.
2248 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2251 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2252 /// a splat of a single element and it's a 2 or 4 element mask.
2253 bool X86::isSplatMask(SDNode *N) {
2254 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2256 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2257 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2259 return ::isSplatMask(N);
2262 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2263 /// specifies a splat of zero element.
2264 bool X86::isSplatLoMask(SDNode *N) {
2265 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2267 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2268 if (!isUndefOrEqual(N->getOperand(i), 0))
2273 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2274 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2276 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2277 unsigned NumOperands = N->getNumOperands();
2278 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2280 for (unsigned i = 0; i < NumOperands; ++i) {
2282 SDOperand Arg = N->getOperand(NumOperands-i-1);
2283 if (Arg.getOpcode() != ISD::UNDEF)
2284 Val = cast<ConstantSDNode>(Arg)->getValue();
2285 if (Val >= NumOperands) Val -= NumOperands;
2287 if (i != NumOperands - 1)
2294 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2295 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2297 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2299 // 8 nodes, but we only care about the last 4.
2300 for (unsigned i = 7; i >= 4; --i) {
2302 SDOperand Arg = N->getOperand(i);
2303 if (Arg.getOpcode() != ISD::UNDEF)
2304 Val = cast<ConstantSDNode>(Arg)->getValue();
2313 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2314 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2316 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2318 // 8 nodes, but we only care about the first 4.
2319 for (int i = 3; i >= 0; --i) {
2321 SDOperand Arg = N->getOperand(i);
2322 if (Arg.getOpcode() != ISD::UNDEF)
2323 Val = cast<ConstantSDNode>(Arg)->getValue();
2332 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2333 /// specifies a 8 element shuffle that can be broken into a pair of
2334 /// PSHUFHW and PSHUFLW.
2335 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2336 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2338 if (N->getNumOperands() != 8)
2341 // Lower quadword shuffled.
2342 for (unsigned i = 0; i != 4; ++i) {
2343 SDOperand Arg = N->getOperand(i);
2344 if (Arg.getOpcode() == ISD::UNDEF) continue;
2345 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2346 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2351 // Upper quadword shuffled.
2352 for (unsigned i = 4; i != 8; ++i) {
2353 SDOperand Arg = N->getOperand(i);
2354 if (Arg.getOpcode() == ISD::UNDEF) continue;
2355 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2356 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2357 if (Val < 4 || Val > 7)
2364 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2365 /// values in ther permute mask.
2366 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2367 SDOperand &V2, SDOperand &Mask,
2368 SelectionDAG &DAG) {
2369 MVT::ValueType VT = Op.getValueType();
2370 MVT::ValueType MaskVT = Mask.getValueType();
2371 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2372 unsigned NumElems = Mask.getNumOperands();
2373 SmallVector<SDOperand, 8> MaskVec;
2375 for (unsigned i = 0; i != NumElems; ++i) {
2376 SDOperand Arg = Mask.getOperand(i);
2377 if (Arg.getOpcode() == ISD::UNDEF) {
2378 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2381 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2382 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2384 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2386 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2390 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2391 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2394 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2395 /// the two vector operands have swapped position.
2397 SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2398 MVT::ValueType MaskVT = Mask.getValueType();
2399 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2400 unsigned NumElems = Mask.getNumOperands();
2401 SmallVector<SDOperand, 8> MaskVec;
2402 for (unsigned i = 0; i != NumElems; ++i) {
2403 SDOperand Arg = Mask.getOperand(i);
2404 if (Arg.getOpcode() == ISD::UNDEF) {
2405 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2408 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2409 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2411 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2413 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2415 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2419 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2420 /// match movhlps. The lower half elements should come from upper half of
2421 /// V1 (and in order), and the upper half elements should come from the upper
2422 /// half of V2 (and in order).
2423 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2424 unsigned NumElems = Mask->getNumOperands();
2427 for (unsigned i = 0, e = 2; i != e; ++i)
2428 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2430 for (unsigned i = 2; i != 4; ++i)
2431 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2436 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2437 /// is promoted to a vector.
2438 static inline bool isScalarLoadToVector(SDNode *N) {
2439 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2440 N = N->getOperand(0).Val;
2441 return ISD::isNON_EXTLoad(N);
2446 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2447 /// match movlp{s|d}. The lower half elements should come from lower half of
2448 /// V1 (and in order), and the upper half elements should come from the upper
2449 /// half of V2 (and in order). And since V1 will become the source of the
2450 /// MOVLP, it must be either a vector load or a scalar load to vector.
2451 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2452 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2454 // Is V2 is a vector load, don't do this transformation. We will try to use
2455 // load folding shufps op.
2456 if (ISD::isNON_EXTLoad(V2))
2459 unsigned NumElems = Mask->getNumOperands();
2460 if (NumElems != 2 && NumElems != 4)
2462 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2463 if (!isUndefOrEqual(Mask->getOperand(i), i))
2465 for (unsigned i = NumElems/2; i != NumElems; ++i)
2466 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2471 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2473 static bool isSplatVector(SDNode *N) {
2474 if (N->getOpcode() != ISD::BUILD_VECTOR)
2477 SDOperand SplatValue = N->getOperand(0);
2478 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2479 if (N->getOperand(i) != SplatValue)
2484 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2486 static bool isUndefShuffle(SDNode *N) {
2487 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2490 SDOperand V1 = N->getOperand(0);
2491 SDOperand V2 = N->getOperand(1);
2492 SDOperand Mask = N->getOperand(2);
2493 unsigned NumElems = Mask.getNumOperands();
2494 for (unsigned i = 0; i != NumElems; ++i) {
2495 SDOperand Arg = Mask.getOperand(i);
2496 if (Arg.getOpcode() != ISD::UNDEF) {
2497 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2498 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2500 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2507 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2509 static inline bool isZeroNode(SDOperand Elt) {
2510 return ((isa<ConstantSDNode>(Elt) &&
2511 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2512 (isa<ConstantFPSDNode>(Elt) &&
2513 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2516 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2517 /// to an zero vector.
2518 static bool isZeroShuffle(SDNode *N) {
2519 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2522 SDOperand V1 = N->getOperand(0);
2523 SDOperand V2 = N->getOperand(1);
2524 SDOperand Mask = N->getOperand(2);
2525 unsigned NumElems = Mask.getNumOperands();
2526 for (unsigned i = 0; i != NumElems; ++i) {
2527 SDOperand Arg = Mask.getOperand(i);
2528 if (Arg.getOpcode() == ISD::UNDEF)
2531 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2532 if (Idx < NumElems) {
2533 unsigned Opc = V1.Val->getOpcode();
2534 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2536 if (Opc != ISD::BUILD_VECTOR ||
2537 !isZeroNode(V1.Val->getOperand(Idx)))
2539 } else if (Idx >= NumElems) {
2540 unsigned Opc = V2.Val->getOpcode();
2541 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2543 if (Opc != ISD::BUILD_VECTOR ||
2544 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2551 /// getZeroVector - Returns a vector of specified type with all zero elements.
2553 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2554 assert(MVT::isVector(VT) && "Expected a vector type");
2556 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2557 // type. This ensures they get CSE'd.
2558 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2560 if (MVT::getSizeInBits(VT) == 64) // MMX
2561 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2563 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2564 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2567 /// getOnesVector - Returns a vector of specified type with all bits set.
2569 static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) {
2570 assert(MVT::isVector(VT) && "Expected a vector type");
2572 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2573 // type. This ensures they get CSE'd.
2574 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2576 if (MVT::getSizeInBits(VT) == 64) // MMX
2577 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2579 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2580 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2584 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2585 /// that point to V2 points to its first element.
2586 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2587 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2589 bool Changed = false;
2590 SmallVector<SDOperand, 8> MaskVec;
2591 unsigned NumElems = Mask.getNumOperands();
2592 for (unsigned i = 0; i != NumElems; ++i) {
2593 SDOperand Arg = Mask.getOperand(i);
2594 if (Arg.getOpcode() != ISD::UNDEF) {
2595 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2596 if (Val > NumElems) {
2597 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2601 MaskVec.push_back(Arg);
2605 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2606 &MaskVec[0], MaskVec.size());
2610 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2611 /// operation of specified width.
2612 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2613 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2614 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2616 SmallVector<SDOperand, 8> MaskVec;
2617 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2618 for (unsigned i = 1; i != NumElems; ++i)
2619 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2620 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2623 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2624 /// of specified width.
2625 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2626 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2627 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2628 SmallVector<SDOperand, 8> MaskVec;
2629 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2630 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2631 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2633 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2636 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2637 /// of specified width.
2638 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2639 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2640 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2641 unsigned Half = NumElems/2;
2642 SmallVector<SDOperand, 8> MaskVec;
2643 for (unsigned i = 0; i != Half; ++i) {
2644 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2645 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2647 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2650 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2652 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2653 SDOperand V1 = Op.getOperand(0);
2654 SDOperand Mask = Op.getOperand(2);
2655 MVT::ValueType VT = Op.getValueType();
2656 unsigned NumElems = Mask.getNumOperands();
2657 Mask = getUnpacklMask(NumElems, DAG);
2658 while (NumElems != 4) {
2659 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2662 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2664 Mask = getZeroVector(MVT::v4i32, DAG);
2665 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2666 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2667 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2670 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2671 /// vector of zero or undef vector. This produces a shuffle where the low
2672 /// element of V2 is swizzled into the zero/undef vector, landing at element
2673 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2674 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2675 unsigned NumElems, unsigned Idx,
2676 bool isZero, SelectionDAG &DAG) {
2677 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2678 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2679 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2680 SmallVector<SDOperand, 16> MaskVec;
2681 for (unsigned i = 0; i != NumElems; ++i)
2682 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2683 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2685 MaskVec.push_back(DAG.getConstant(i, EVT));
2686 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2687 &MaskVec[0], MaskVec.size());
2688 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2691 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2693 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2694 unsigned NumNonZero, unsigned NumZero,
2695 SelectionDAG &DAG, TargetLowering &TLI) {
2701 for (unsigned i = 0; i < 16; ++i) {
2702 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2703 if (ThisIsNonZero && First) {
2705 V = getZeroVector(MVT::v8i16, DAG);
2707 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2712 SDOperand ThisElt(0, 0), LastElt(0, 0);
2713 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2714 if (LastIsNonZero) {
2715 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2717 if (ThisIsNonZero) {
2718 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2719 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2720 ThisElt, DAG.getConstant(8, MVT::i8));
2722 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2727 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2728 DAG.getConstant(i/2, TLI.getPointerTy()));
2732 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2735 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2737 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2738 unsigned NumNonZero, unsigned NumZero,
2739 SelectionDAG &DAG, TargetLowering &TLI) {
2745 for (unsigned i = 0; i < 8; ++i) {
2746 bool isNonZero = (NonZeros & (1 << i)) != 0;
2750 V = getZeroVector(MVT::v8i16, DAG);
2752 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2755 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2756 DAG.getConstant(i, TLI.getPointerTy()));
2764 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2765 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
2766 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
2767 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
2768 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
2769 // eliminated on x86-32 hosts.
2770 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
2773 if (ISD::isBuildVectorAllOnes(Op.Val))
2774 return getOnesVector(Op.getValueType(), DAG);
2775 return getZeroVector(Op.getValueType(), DAG);
2778 MVT::ValueType VT = Op.getValueType();
2779 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2780 unsigned EVTBits = MVT::getSizeInBits(EVT);
2782 unsigned NumElems = Op.getNumOperands();
2783 unsigned NumZero = 0;
2784 unsigned NumNonZero = 0;
2785 unsigned NonZeros = 0;
2786 bool HasNonImms = false;
2787 SmallSet<SDOperand, 8> Values;
2788 for (unsigned i = 0; i < NumElems; ++i) {
2789 SDOperand Elt = Op.getOperand(i);
2790 if (Elt.getOpcode() == ISD::UNDEF)
2793 if (Elt.getOpcode() != ISD::Constant &&
2794 Elt.getOpcode() != ISD::ConstantFP)
2796 if (isZeroNode(Elt))
2799 NonZeros |= (1 << i);
2804 if (NumNonZero == 0) {
2805 // All undef vector. Return an UNDEF. All zero vectors were handled above.
2806 return DAG.getNode(ISD::UNDEF, VT);
2809 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2810 if (Values.size() == 1)
2813 // Special case for single non-zero element.
2814 if (NumNonZero == 1 && NumElems <= 4) {
2815 unsigned Idx = CountTrailingZeros_32(NonZeros);
2816 SDOperand Item = Op.getOperand(Idx);
2817 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2819 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2820 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2822 else if (!HasNonImms) // Otherwise, it's better to do a constpool load.
2825 if (EVTBits == 32) {
2826 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2827 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2829 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2830 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2831 SmallVector<SDOperand, 8> MaskVec;
2832 for (unsigned i = 0; i < NumElems; i++)
2833 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2834 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2835 &MaskVec[0], MaskVec.size());
2836 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2837 DAG.getNode(ISD::UNDEF, VT), Mask);
2841 // A vector full of immediates; various special cases are already
2842 // handled, so this is best done with a single constant-pool load.
2846 // Let legalizer expand 2-wide build_vectors.
2850 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2851 if (EVTBits == 8 && NumElems == 16) {
2852 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2854 if (V.Val) return V;
2857 if (EVTBits == 16 && NumElems == 8) {
2858 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2860 if (V.Val) return V;
2863 // If element VT is == 32 bits, turn it into a number of shuffles.
2864 SmallVector<SDOperand, 8> V;
2866 if (NumElems == 4 && NumZero > 0) {
2867 for (unsigned i = 0; i < 4; ++i) {
2868 bool isZero = !(NonZeros & (1 << i));
2870 V[i] = getZeroVector(VT, DAG);
2872 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2875 for (unsigned i = 0; i < 2; ++i) {
2876 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2879 V[i] = V[i*2]; // Must be a zero vector.
2882 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2883 getMOVLMask(NumElems, DAG));
2886 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2887 getMOVLMask(NumElems, DAG));
2890 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2891 getUnpacklMask(NumElems, DAG));
2896 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2897 // clears the upper bits.
2898 // FIXME: we can do the same for v4f32 case when we know both parts of
2899 // the lower half come from scalar_to_vector (loadf32). We should do
2900 // that in post legalizer dag combiner with target specific hooks.
2901 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2903 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2904 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2905 SmallVector<SDOperand, 8> MaskVec;
2906 bool Reverse = (NonZeros & 0x3) == 2;
2907 for (unsigned i = 0; i < 2; ++i)
2909 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2911 MaskVec.push_back(DAG.getConstant(i, EVT));
2912 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2913 for (unsigned i = 0; i < 2; ++i)
2915 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2917 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2918 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2919 &MaskVec[0], MaskVec.size());
2920 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2923 if (Values.size() > 2) {
2924 // Expand into a number of unpckl*.
2926 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2927 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2928 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2929 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2930 for (unsigned i = 0; i < NumElems; ++i)
2931 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2933 while (NumElems != 0) {
2934 for (unsigned i = 0; i < NumElems; ++i)
2935 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2946 SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
2947 SDOperand PermMask, SelectionDAG &DAG,
2948 TargetLowering &TLI) {
2950 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
2951 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2952 MVT::ValueType PtrVT = TLI.getPointerTy();
2953 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
2954 PermMask.Val->op_end());
2956 // First record which half of which vector the low elements come from.
2957 SmallVector<unsigned, 4> LowQuad(4);
2958 for (unsigned i = 0; i < 4; ++i) {
2959 SDOperand Elt = MaskElts[i];
2960 if (Elt.getOpcode() == ISD::UNDEF)
2962 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
2963 int QuadIdx = EltIdx / 4;
2966 int BestLowQuad = -1;
2967 unsigned MaxQuad = 1;
2968 for (unsigned i = 0; i < 4; ++i) {
2969 if (LowQuad[i] > MaxQuad) {
2971 MaxQuad = LowQuad[i];
2975 // Record which half of which vector the high elements come from.
2976 SmallVector<unsigned, 4> HighQuad(4);
2977 for (unsigned i = 4; i < 8; ++i) {
2978 SDOperand Elt = MaskElts[i];
2979 if (Elt.getOpcode() == ISD::UNDEF)
2981 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
2982 int QuadIdx = EltIdx / 4;
2983 ++HighQuad[QuadIdx];
2985 int BestHighQuad = -1;
2987 for (unsigned i = 0; i < 4; ++i) {
2988 if (HighQuad[i] > MaxQuad) {
2990 MaxQuad = HighQuad[i];
2994 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
2995 if (BestLowQuad != -1 || BestHighQuad != -1) {
2996 // First sort the 4 chunks in order using shufpd.
2997 SmallVector<SDOperand, 8> MaskVec;
2998 if (BestLowQuad != -1)
2999 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3001 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3002 if (BestHighQuad != -1)
3003 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3005 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3006 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3007 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3008 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3009 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3010 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3012 // Now sort high and low parts separately.
3013 BitVector InOrder(8);
3014 if (BestLowQuad != -1) {
3015 // Sort lower half in order using PSHUFLW.
3017 bool AnyOutOrder = false;
3018 for (unsigned i = 0; i != 4; ++i) {
3019 SDOperand Elt = MaskElts[i];
3020 if (Elt.getOpcode() == ISD::UNDEF) {
3021 MaskVec.push_back(Elt);
3024 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3027 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3028 // If this element is in the right place after this shuffle, then
3030 if ((int)(EltIdx / 4) == BestLowQuad)
3035 for (unsigned i = 4; i != 8; ++i)
3036 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3037 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3038 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3042 if (BestHighQuad != -1) {
3043 // Sort high half in order using PSHUFHW if possible.
3045 for (unsigned i = 0; i != 4; ++i)
3046 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3047 bool AnyOutOrder = false;
3048 for (unsigned i = 4; i != 8; ++i) {
3049 SDOperand Elt = MaskElts[i];
3050 if (Elt.getOpcode() == ISD::UNDEF) {
3051 MaskVec.push_back(Elt);
3054 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3057 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3058 // If this element is in the right place after this shuffle, then
3060 if ((int)(EltIdx / 4) == BestHighQuad)
3065 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3066 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3070 // The other elements are put in the right place using pextrw and pinsrw.
3071 for (unsigned i = 0; i != 8; ++i) {
3074 SDOperand Elt = MaskElts[i];
3075 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3078 SDOperand ExtOp = (EltIdx < 8)
3079 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3080 DAG.getConstant(EltIdx, PtrVT))
3081 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3082 DAG.getConstant(EltIdx - 8, PtrVT));
3083 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3084 DAG.getConstant(i, PtrVT));
3089 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3090 ///as few as possible.
3091 // First, let's find out how many elements are already in the right order.
3092 unsigned V1InOrder = 0;
3093 unsigned V1FromV1 = 0;
3094 unsigned V2InOrder = 0;
3095 unsigned V2FromV2 = 0;
3096 SmallVector<SDOperand, 8> V1Elts;
3097 SmallVector<SDOperand, 8> V2Elts;
3098 for (unsigned i = 0; i < 8; ++i) {
3099 SDOperand Elt = MaskElts[i];
3100 if (Elt.getOpcode() == ISD::UNDEF) {
3101 V1Elts.push_back(Elt);
3102 V2Elts.push_back(Elt);
3107 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3109 V1Elts.push_back(Elt);
3110 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3112 } else if (EltIdx == i+8) {
3113 V1Elts.push_back(Elt);
3114 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3116 } else if (EltIdx < 8) {
3117 V1Elts.push_back(Elt);
3120 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3125 if (V2InOrder > V1InOrder) {
3126 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3128 std::swap(V1Elts, V2Elts);
3129 std::swap(V1FromV1, V2FromV2);
3132 if ((V1FromV1 + V1InOrder) != 8) {
3133 // Some elements are from V2.
3135 // If there are elements that are from V1 but out of place,
3136 // then first sort them in place
3137 SmallVector<SDOperand, 8> MaskVec;
3138 for (unsigned i = 0; i < 8; ++i) {
3139 SDOperand Elt = V1Elts[i];
3140 if (Elt.getOpcode() == ISD::UNDEF) {
3141 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3144 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3146 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3148 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3150 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3151 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3155 for (unsigned i = 0; i < 8; ++i) {
3156 SDOperand Elt = V1Elts[i];
3157 if (Elt.getOpcode() == ISD::UNDEF)
3159 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3162 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3163 DAG.getConstant(EltIdx - 8, PtrVT));
3164 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3165 DAG.getConstant(i, PtrVT));
3169 // All elements are from V1.
3171 for (unsigned i = 0; i < 8; ++i) {
3172 SDOperand Elt = V1Elts[i];
3173 if (Elt.getOpcode() == ISD::UNDEF)
3175 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3176 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3177 DAG.getConstant(EltIdx, PtrVT));
3178 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3179 DAG.getConstant(i, PtrVT));
3185 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3186 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3187 /// done when every pair / quad of shuffle mask elements point to elements in
3188 /// the right sequence. e.g.
3189 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3191 SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3193 SDOperand PermMask, SelectionDAG &DAG,
3194 TargetLowering &TLI) {
3195 unsigned NumElems = PermMask.getNumOperands();
3196 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3197 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3198 MVT::ValueType NewVT = MaskVT;
3200 case MVT::v4f32: NewVT = MVT::v2f64; break;
3201 case MVT::v4i32: NewVT = MVT::v2i64; break;
3202 case MVT::v8i16: NewVT = MVT::v4i32; break;
3203 case MVT::v16i8: NewVT = MVT::v4i32; break;
3204 default: assert(false && "Unexpected!");
3208 if (MVT::isInteger(VT))
3212 unsigned Scale = NumElems / NewWidth;
3213 SmallVector<SDOperand, 8> MaskVec;
3214 for (unsigned i = 0; i < NumElems; i += Scale) {
3215 unsigned StartIdx = ~0U;
3216 for (unsigned j = 0; j < Scale; ++j) {
3217 SDOperand Elt = PermMask.getOperand(i+j);
3218 if (Elt.getOpcode() == ISD::UNDEF)
3220 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3221 if (StartIdx == ~0U)
3222 StartIdx = EltIdx - (EltIdx % Scale);
3223 if (EltIdx != StartIdx + j)
3226 if (StartIdx == ~0U)
3227 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3229 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
3232 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3233 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3234 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3235 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3236 &MaskVec[0], MaskVec.size()));
3240 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3241 SDOperand V1 = Op.getOperand(0);
3242 SDOperand V2 = Op.getOperand(1);
3243 SDOperand PermMask = Op.getOperand(2);
3244 MVT::ValueType VT = Op.getValueType();
3245 unsigned NumElems = PermMask.getNumOperands();
3246 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3247 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3248 bool V1IsSplat = false;
3249 bool V2IsSplat = false;
3251 if (isUndefShuffle(Op.Val))
3252 return DAG.getNode(ISD::UNDEF, VT);
3254 if (isZeroShuffle(Op.Val))
3255 return getZeroVector(VT, DAG);
3257 if (isIdentityMask(PermMask.Val))
3259 else if (isIdentityMask(PermMask.Val, true))
3262 if (isSplatMask(PermMask.Val)) {
3263 if (NumElems <= 4) return Op;
3264 // Promote it to a v4i32 splat.
3265 return PromoteSplat(Op, DAG);
3268 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3270 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3271 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3273 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3274 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3275 // FIXME: Figure out a cleaner way to do this.
3276 // Try to make use of movq to zero out the top part.
3277 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3278 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3280 SDOperand NewV1 = NewOp.getOperand(0);
3281 SDOperand NewV2 = NewOp.getOperand(1);
3282 SDOperand NewMask = NewOp.getOperand(2);
3283 if (isCommutedMOVL(NewMask.Val, true, false)) {
3284 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3285 NewOp = DAG.getNode(ISD::VECTOR_SHUFFLE, NewOp.getValueType(),
3286 NewV1, NewV2, getMOVLMask(2, DAG));
3287 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3290 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3291 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3292 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3293 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3297 if (X86::isMOVLMask(PermMask.Val))
3298 return (V1IsUndef) ? V2 : Op;
3300 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3301 X86::isMOVSLDUPMask(PermMask.Val) ||
3302 X86::isMOVHLPSMask(PermMask.Val) ||
3303 X86::isMOVHPMask(PermMask.Val) ||
3304 X86::isMOVLPMask(PermMask.Val))
3307 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3308 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3309 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3311 bool Commuted = false;
3312 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3313 // 1,1,1,1 -> v8i16 though.
3314 V1IsSplat = isSplatVector(V1.Val);
3315 V2IsSplat = isSplatVector(V2.Val);
3317 // Canonicalize the splat or undef, if present, to be on the RHS.
3318 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3319 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3320 std::swap(V1IsSplat, V2IsSplat);
3321 std::swap(V1IsUndef, V2IsUndef);
3325 // FIXME: Figure out a cleaner way to do this.
3326 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3327 if (V2IsUndef) return V1;
3328 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3330 // V2 is a splat, so the mask may be malformed. That is, it may point
3331 // to any V2 element. The instruction selectior won't like this. Get
3332 // a corrected mask and commute to form a proper MOVS{S|D}.
3333 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3334 if (NewMask.Val != PermMask.Val)
3335 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3340 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3341 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3342 X86::isUNPCKLMask(PermMask.Val) ||
3343 X86::isUNPCKHMask(PermMask.Val))
3347 // Normalize mask so all entries that point to V2 points to its first
3348 // element then try to match unpck{h|l} again. If match, return a
3349 // new vector_shuffle with the corrected mask.
3350 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3351 if (NewMask.Val != PermMask.Val) {
3352 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3353 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3354 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3355 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3356 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3357 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3362 // Normalize the node to match x86 shuffle ops if needed
3363 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3364 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3367 // Commute is back and try unpck* again.
3368 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3369 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3370 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3371 X86::isUNPCKLMask(PermMask.Val) ||
3372 X86::isUNPCKHMask(PermMask.Val))
3376 // If VT is integer, try PSHUF* first, then SHUFP*.
3377 if (MVT::isInteger(VT)) {
3378 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
3379 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3380 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
3381 X86::isPSHUFDMask(PermMask.Val)) ||
3382 X86::isPSHUFHWMask(PermMask.Val) ||
3383 X86::isPSHUFLWMask(PermMask.Val)) {
3384 if (V2.getOpcode() != ISD::UNDEF)
3385 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3386 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3390 if (X86::isSHUFPMask(PermMask.Val) &&
3391 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
3394 // Floating point cases in the other order.
3395 if (X86::isSHUFPMask(PermMask.Val))
3397 if (X86::isPSHUFDMask(PermMask.Val) ||
3398 X86::isPSHUFHWMask(PermMask.Val) ||
3399 X86::isPSHUFLWMask(PermMask.Val)) {
3400 if (V2.getOpcode() != ISD::UNDEF)
3401 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3402 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3407 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3408 if (VT == MVT::v8i16) {
3409 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3414 // Handle all 4 wide cases with a number of shuffles.
3415 if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) {
3416 // Don't do this for MMX.
3417 MVT::ValueType MaskVT = PermMask.getValueType();
3418 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3419 SmallVector<std::pair<int, int>, 8> Locs;
3420 Locs.reserve(NumElems);
3421 SmallVector<SDOperand, 8> Mask1(NumElems,
3422 DAG.getNode(ISD::UNDEF, MaskEVT));
3423 SmallVector<SDOperand, 8> Mask2(NumElems,
3424 DAG.getNode(ISD::UNDEF, MaskEVT));
3427 // If no more than two elements come from either vector. This can be
3428 // implemented with two shuffles. First shuffle gather the elements.
3429 // The second shuffle, which takes the first shuffle as both of its
3430 // vector operands, put the elements into the right order.
3431 for (unsigned i = 0; i != NumElems; ++i) {
3432 SDOperand Elt = PermMask.getOperand(i);
3433 if (Elt.getOpcode() == ISD::UNDEF) {
3434 Locs[i] = std::make_pair(-1, -1);
3436 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3437 if (Val < NumElems) {
3438 Locs[i] = std::make_pair(0, NumLo);
3442 Locs[i] = std::make_pair(1, NumHi);
3443 if (2+NumHi < NumElems)
3444 Mask1[2+NumHi] = Elt;
3449 if (NumLo <= 2 && NumHi <= 2) {
3450 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3451 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3452 &Mask1[0], Mask1.size()));
3453 for (unsigned i = 0; i != NumElems; ++i) {
3454 if (Locs[i].first == -1)
3457 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3458 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3459 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3463 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3464 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3465 &Mask2[0], Mask2.size()));
3468 // Break it into (shuffle shuffle_hi, shuffle_lo).
3470 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3471 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3472 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3473 unsigned MaskIdx = 0;
3475 unsigned HiIdx = NumElems/2;
3476 for (unsigned i = 0; i != NumElems; ++i) {
3477 if (i == NumElems/2) {
3483 SDOperand Elt = PermMask.getOperand(i);
3484 if (Elt.getOpcode() == ISD::UNDEF) {
3485 Locs[i] = std::make_pair(-1, -1);
3486 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3487 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3488 (*MaskPtr)[LoIdx] = Elt;
3491 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3492 (*MaskPtr)[HiIdx] = Elt;
3497 SDOperand LoShuffle =
3498 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3499 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3500 &LoMask[0], LoMask.size()));
3501 SDOperand HiShuffle =
3502 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3503 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3504 &HiMask[0], HiMask.size()));
3505 SmallVector<SDOperand, 8> MaskOps;
3506 for (unsigned i = 0; i != NumElems; ++i) {
3507 if (Locs[i].first == -1) {
3508 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3510 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3511 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3514 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3515 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3516 &MaskOps[0], MaskOps.size()));
3523 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3524 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3527 MVT::ValueType VT = Op.getValueType();
3528 // TODO: handle v16i8.
3529 if (MVT::getSizeInBits(VT) == 16) {
3530 SDOperand Vec = Op.getOperand(0);
3531 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3533 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
3534 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3535 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
3537 // Transform it so it match pextrw which produces a 32-bit result.
3538 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3539 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3540 Op.getOperand(0), Op.getOperand(1));
3541 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3542 DAG.getValueType(VT));
3543 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3544 } else if (MVT::getSizeInBits(VT) == 32) {
3545 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3548 // SHUFPS the element to the lowest double word, then movss.
3549 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3550 SmallVector<SDOperand, 8> IdxVec;
3552 push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3554 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3556 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3558 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3559 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3560 &IdxVec[0], IdxVec.size());
3561 SDOperand Vec = Op.getOperand(0);
3562 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3563 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3564 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3565 DAG.getConstant(0, getPointerTy()));
3566 } else if (MVT::getSizeInBits(VT) == 64) {
3567 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3571 // UNPCKHPD the element to the lowest double word, then movsd.
3572 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3573 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3574 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3575 SmallVector<SDOperand, 8> IdxVec;
3576 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
3578 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3579 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3580 &IdxVec[0], IdxVec.size());
3581 SDOperand Vec = Op.getOperand(0);
3582 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3583 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3584 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3585 DAG.getConstant(0, getPointerTy()));
3592 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3593 MVT::ValueType VT = Op.getValueType();
3594 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3598 SDOperand N0 = Op.getOperand(0);
3599 SDOperand N1 = Op.getOperand(1);
3600 SDOperand N2 = Op.getOperand(2);
3602 if (MVT::getSizeInBits(EVT) == 16) {
3603 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3604 // as its second argument.
3605 if (N1.getValueType() != MVT::i32)
3606 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3607 if (N2.getValueType() != MVT::i32)
3608 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy());
3609 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3612 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
3613 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
3614 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3615 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3616 SmallVector<SDOperand, 4> MaskVec;
3617 for (unsigned i = 0; i < 4; ++i)
3618 MaskVec.push_back(DAG.getConstant((i == Idx) ? i+4 : i, MaskEVT));
3619 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
3620 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3621 &MaskVec[0], MaskVec.size()));
3625 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3626 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3627 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3630 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3631 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3632 // one of the above mentioned nodes. It has to be wrapped because otherwise
3633 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3634 // be used to form addressing mode. These wrapped nodes will be selected
3637 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3638 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3639 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3641 CP->getAlignment());
3642 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3643 // With PIC, the address is actually $g + Offset.
3644 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3645 !Subtarget->isPICStyleRIPRel()) {
3646 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3647 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3655 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3656 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3657 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3658 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3659 // With PIC, the address is actually $g + Offset.
3660 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3661 !Subtarget->isPICStyleRIPRel()) {
3662 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3663 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3667 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3668 // load the value at address GV, not the value of GV itself. This means that
3669 // the GlobalAddress must be in the base or index register of the address, not
3670 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3671 // The same applies for external symbols during PIC codegen
3672 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3673 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3678 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3680 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3681 const MVT::ValueType PtrVT) {
3683 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3684 DAG.getNode(X86ISD::GlobalBaseReg,
3686 InFlag = Chain.getValue(1);
3688 // emit leal symbol@TLSGD(,%ebx,1), %eax
3689 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3690 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3691 GA->getValueType(0),
3693 SDOperand Ops[] = { Chain, TGA, InFlag };
3694 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3695 InFlag = Result.getValue(2);
3696 Chain = Result.getValue(1);
3698 // call ___tls_get_addr. This function receives its argument in
3699 // the register EAX.
3700 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3701 InFlag = Chain.getValue(1);
3703 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3704 SDOperand Ops1[] = { Chain,
3705 DAG.getTargetExternalSymbol("___tls_get_addr",
3707 DAG.getRegister(X86::EAX, PtrVT),
3708 DAG.getRegister(X86::EBX, PtrVT),
3710 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3711 InFlag = Chain.getValue(1);
3713 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3716 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3717 // "local exec" model.
3719 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3720 const MVT::ValueType PtrVT) {
3721 // Get the Thread Pointer
3722 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3723 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3725 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3726 GA->getValueType(0),
3728 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3730 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3731 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3733 // The address of the thread local variable is the add of the thread
3734 // pointer with the offset of the variable.
3735 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3739 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3740 // TODO: implement the "local dynamic" model
3741 // TODO: implement the "initial exec"model for pic executables
3742 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3743 "TLS not implemented for non-ELF and 64-bit targets");
3744 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3745 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3746 // otherwise use the "Local Exec"TLS Model
3747 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3748 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3750 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3754 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3755 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3756 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3757 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3758 // With PIC, the address is actually $g + Offset.
3759 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3760 !Subtarget->isPICStyleRIPRel()) {
3761 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3762 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3769 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3770 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3771 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3772 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3773 // With PIC, the address is actually $g + Offset.
3774 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3775 !Subtarget->isPICStyleRIPRel()) {
3776 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3777 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3784 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
3785 /// take a 2 x i32 value to shift plus a shift amount.
3786 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3787 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3788 "Not an i64 shift!");
3789 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3790 SDOperand ShOpLo = Op.getOperand(0);
3791 SDOperand ShOpHi = Op.getOperand(1);
3792 SDOperand ShAmt = Op.getOperand(2);
3793 SDOperand Tmp1 = isSRA ?
3794 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3795 DAG.getConstant(0, MVT::i32);
3797 SDOperand Tmp2, Tmp3;
3798 if (Op.getOpcode() == ISD::SHL_PARTS) {
3799 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3800 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3802 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3803 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3806 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3807 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3808 DAG.getConstant(32, MVT::i8));
3809 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32,
3810 AndNode, DAG.getConstant(0, MVT::i8));
3813 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3814 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3815 SmallVector<SDOperand, 4> Ops;
3816 if (Op.getOpcode() == ISD::SHL_PARTS) {
3817 Ops.push_back(Tmp2);
3818 Ops.push_back(Tmp3);
3820 Ops.push_back(Cond);
3821 Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3824 Ops.push_back(Tmp3);
3825 Ops.push_back(Tmp1);
3827 Ops.push_back(Cond);
3828 Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3830 Ops.push_back(Tmp2);
3831 Ops.push_back(Tmp3);
3833 Ops.push_back(Cond);
3834 Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3837 Ops.push_back(Tmp3);
3838 Ops.push_back(Tmp1);
3840 Ops.push_back(Cond);
3841 Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3844 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3848 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3851 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3852 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3853 Op.getOperand(0).getValueType() >= MVT::i16 &&
3854 "Unknown SINT_TO_FP to lower!");
3857 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3858 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3859 MachineFunction &MF = DAG.getMachineFunction();
3860 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3861 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3862 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3863 StackSlot, NULL, 0);
3865 // These are really Legal; caller falls through into that case.
3866 if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f32 && X86ScalarSSEf32)
3868 if (SrcVT==MVT::i32 && Op.getValueType() == MVT::f64 && X86ScalarSSEf64)
3870 if (SrcVT==MVT::i64 && Op.getValueType() != MVT::f80 &&
3871 Subtarget->is64Bit())
3876 bool useSSE = (X86ScalarSSEf32 && Op.getValueType() == MVT::f32) ||
3877 (X86ScalarSSEf64 && Op.getValueType() == MVT::f64);
3879 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3881 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
3882 SmallVector<SDOperand, 8> Ops;
3883 Ops.push_back(Chain);
3884 Ops.push_back(StackSlot);
3885 Ops.push_back(DAG.getValueType(SrcVT));
3886 Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3887 Tys, &Ops[0], Ops.size());
3890 Chain = Result.getValue(1);
3891 SDOperand InFlag = Result.getValue(2);
3893 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3894 // shouldn't be necessary except that RFP cannot be live across
3895 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3896 MachineFunction &MF = DAG.getMachineFunction();
3897 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3898 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3899 Tys = DAG.getVTList(MVT::Other);
3900 SmallVector<SDOperand, 8> Ops;
3901 Ops.push_back(Chain);
3902 Ops.push_back(Result);
3903 Ops.push_back(StackSlot);
3904 Ops.push_back(DAG.getValueType(Op.getValueType()));
3905 Ops.push_back(InFlag);
3906 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3907 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3913 std::pair<SDOperand,SDOperand> X86TargetLowering::
3914 FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
3915 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3916 "Unknown FP_TO_SINT to lower!");
3918 // These are really Legal.
3919 if (Op.getValueType() == MVT::i32 &&
3920 X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32)
3921 return std::make_pair(SDOperand(), SDOperand());
3922 if (Op.getValueType() == MVT::i32 &&
3923 X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)
3924 return std::make_pair(SDOperand(), SDOperand());
3925 if (Subtarget->is64Bit() &&
3926 Op.getValueType() == MVT::i64 &&
3927 Op.getOperand(0).getValueType() != MVT::f80)
3928 return std::make_pair(SDOperand(), SDOperand());
3930 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3932 MachineFunction &MF = DAG.getMachineFunction();
3933 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3934 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3935 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3937 switch (Op.getValueType()) {
3938 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3939 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3940 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3941 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3944 SDOperand Chain = DAG.getEntryNode();
3945 SDOperand Value = Op.getOperand(0);
3946 if ((X86ScalarSSEf32 && Op.getOperand(0).getValueType() == MVT::f32) ||
3947 (X86ScalarSSEf64 && Op.getOperand(0).getValueType() == MVT::f64)) {
3948 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3949 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3950 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
3952 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3954 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3955 Chain = Value.getValue(1);
3956 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3957 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3960 // Build the FP_TO_INT*_IN_MEM
3961 SDOperand Ops[] = { Chain, Value, StackSlot };
3962 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3964 return std::make_pair(FIST, StackSlot);
3967 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3968 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
3969 SDOperand FIST = Vals.first, StackSlot = Vals.second;
3970 if (FIST.Val == 0) return SDOperand();
3973 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3976 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
3977 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
3978 SDOperand FIST = Vals.first, StackSlot = Vals.second;
3979 if (FIST.Val == 0) return 0;
3981 // Return an i64 load from the stack slot.
3982 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0);
3984 // Use a MERGE_VALUES node to drop the chain result value.
3985 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val;
3988 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3989 MVT::ValueType VT = Op.getValueType();
3990 MVT::ValueType EltVT = VT;
3991 if (MVT::isVector(VT))
3992 EltVT = MVT::getVectorElementType(VT);
3993 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3994 std::vector<Constant*> CV;
3995 if (EltVT == MVT::f64) {
3996 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63))));
4000 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31))));
4006 Constant *C = ConstantVector::get(CV);
4007 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4008 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4010 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4013 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4014 MVT::ValueType VT = Op.getValueType();
4015 MVT::ValueType EltVT = VT;
4016 unsigned EltNum = 1;
4017 if (MVT::isVector(VT)) {
4018 EltVT = MVT::getVectorElementType(VT);
4019 EltNum = MVT::getVectorNumElements(VT);
4021 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
4022 std::vector<Constant*> CV;
4023 if (EltVT == MVT::f64) {
4024 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63)));
4028 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31)));
4034 Constant *C = ConstantVector::get(CV);
4035 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4036 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4038 if (MVT::isVector(VT)) {
4039 return DAG.getNode(ISD::BIT_CONVERT, VT,
4040 DAG.getNode(ISD::XOR, MVT::v2i64,
4041 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4042 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4044 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4048 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
4049 SDOperand Op0 = Op.getOperand(0);
4050 SDOperand Op1 = Op.getOperand(1);
4051 MVT::ValueType VT = Op.getValueType();
4052 MVT::ValueType SrcVT = Op1.getValueType();
4053 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
4055 // If second operand is smaller, extend it first.
4056 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
4057 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4059 SrcTy = MVT::getTypeForValueType(SrcVT);
4061 // And if it is bigger, shrink it first.
4062 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4063 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1);
4065 SrcTy = MVT::getTypeForValueType(SrcVT);
4068 // At this point the operands and the result should have the same
4069 // type, and that won't be f80 since that is not custom lowered.
4071 // First get the sign bit of second operand.
4072 std::vector<Constant*> CV;
4073 if (SrcVT == MVT::f64) {
4074 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63))));
4075 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
4077 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31))));
4078 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4079 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4080 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4082 Constant *C = ConstantVector::get(CV);
4083 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4084 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
4086 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4088 // Shift sign bit right or left if the two operands have different types.
4089 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4090 // Op0 is MVT::f32, Op1 is MVT::f64.
4091 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4092 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4093 DAG.getConstant(32, MVT::i32));
4094 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4095 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4096 DAG.getConstant(0, getPointerTy()));
4099 // Clear first operand sign bit.
4101 if (VT == MVT::f64) {
4102 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63)))));
4103 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
4105 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31)))));
4106 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4107 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4108 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4110 C = ConstantVector::get(CV);
4111 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4112 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4114 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4116 // Or the value with the sign bit.
4117 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4120 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
4121 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4123 SDOperand Op0 = Op.getOperand(0);
4124 SDOperand Op1 = Op.getOperand(1);
4125 SDOperand CC = Op.getOperand(2);
4126 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4127 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
4130 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4132 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4133 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4134 DAG.getConstant(X86CC, MVT::i8), Cond);
4137 assert(isFP && "Illegal integer SetCC!");
4139 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4140 switch (SetCCOpcode) {
4141 default: assert(false && "Illegal floating point SetCC!");
4142 case ISD::SETOEQ: { // !PF & ZF
4143 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4144 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4145 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4146 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4147 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4149 case ISD::SETUNE: { // PF | !ZF
4150 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4151 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4152 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4153 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4154 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4160 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
4161 bool addTest = true;
4162 SDOperand Cond = Op.getOperand(0);
4165 if (Cond.getOpcode() == ISD::SETCC)
4166 Cond = LowerSETCC(Cond, DAG);
4168 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4169 // setting operand in place of the X86ISD::SETCC.
4170 if (Cond.getOpcode() == X86ISD::SETCC) {
4171 CC = Cond.getOperand(0);
4173 SDOperand Cmp = Cond.getOperand(1);
4174 unsigned Opc = Cmp.getOpcode();
4175 MVT::ValueType VT = Op.getValueType();
4176 bool IllegalFPCMov = false;
4177 if (VT == MVT::f32 && !X86ScalarSSEf32)
4178 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4179 else if (VT == MVT::f64 && !X86ScalarSSEf64)
4180 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4181 else if (VT == MVT::f80)
4182 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4183 if ((Opc == X86ISD::CMP ||
4184 Opc == X86ISD::COMI ||
4185 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4192 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4193 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4196 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4198 SmallVector<SDOperand, 4> Ops;
4199 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4200 // condition is true.
4201 Ops.push_back(Op.getOperand(2));
4202 Ops.push_back(Op.getOperand(1));
4204 Ops.push_back(Cond);
4205 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4208 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
4209 bool addTest = true;
4210 SDOperand Chain = Op.getOperand(0);
4211 SDOperand Cond = Op.getOperand(1);
4212 SDOperand Dest = Op.getOperand(2);
4215 if (Cond.getOpcode() == ISD::SETCC)
4216 Cond = LowerSETCC(Cond, DAG);
4218 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4219 // setting operand in place of the X86ISD::SETCC.
4220 if (Cond.getOpcode() == X86ISD::SETCC) {
4221 CC = Cond.getOperand(0);
4223 SDOperand Cmp = Cond.getOperand(1);
4224 unsigned Opc = Cmp.getOpcode();
4225 if (Opc == X86ISD::CMP ||
4226 Opc == X86ISD::COMI ||
4227 Opc == X86ISD::UCOMI) {
4234 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4235 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4237 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4238 Chain, Op.getOperand(2), CC, Cond);
4242 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4243 // Calls to _alloca is needed to probe the stack when allocating more than 4k
4244 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
4245 // that the guard pages used by the OS virtual memory manager are allocated in
4246 // correct sequence.
4248 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4249 SelectionDAG &DAG) {
4250 assert(Subtarget->isTargetCygMing() &&
4251 "This should be used only on Cygwin/Mingw targets");
4254 SDOperand Chain = Op.getOperand(0);
4255 SDOperand Size = Op.getOperand(1);
4256 // FIXME: Ensure alignment here
4260 MVT::ValueType IntPtr = getPointerTy();
4261 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
4263 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4264 Flag = Chain.getValue(1);
4266 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4267 SDOperand Ops[] = { Chain,
4268 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4269 DAG.getRegister(X86::EAX, IntPtr),
4271 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
4272 Flag = Chain.getValue(1);
4274 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
4276 std::vector<MVT::ValueType> Tys;
4277 Tys.push_back(SPTy);
4278 Tys.push_back(MVT::Other);
4279 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4280 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
4283 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4284 SDOperand InFlag(0, 0);
4285 SDOperand Chain = Op.getOperand(0);
4287 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4288 if (Align == 0) Align = 1;
4290 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4291 // If not DWORD aligned or size is more than the threshold, call memset.
4292 // The libc version is likely to be faster for these cases. It can use the
4293 // address value and run time information about the CPU.
4294 if ((Align & 3) != 0 ||
4295 (I && I->getValue() > Subtarget->getMaxInlineSizeThreshold())) {
4296 MVT::ValueType IntPtr = getPointerTy();
4297 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4298 TargetLowering::ArgListTy Args;
4299 TargetLowering::ArgListEntry Entry;
4300 Entry.Node = Op.getOperand(1);
4301 Entry.Ty = IntPtrTy;
4302 Args.push_back(Entry);
4303 // Extend the unsigned i8 argument to be an int value for the call.
4304 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4305 Entry.Ty = IntPtrTy;
4306 Args.push_back(Entry);
4307 Entry.Node = Op.getOperand(3);
4308 Args.push_back(Entry);
4309 std::pair<SDOperand,SDOperand> CallResult =
4310 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4311 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
4312 return CallResult.second;
4317 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4318 unsigned BytesLeft = 0;
4319 bool TwoRepStos = false;
4322 uint64_t Val = ValC->getValue() & 255;
4324 // If the value is a constant, then we can potentially use larger sets.
4325 switch (Align & 3) {
4326 case 2: // WORD aligned
4329 Val = (Val << 8) | Val;
4331 case 0: // DWORD aligned
4334 Val = (Val << 8) | Val;
4335 Val = (Val << 16) | Val;
4336 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4339 Val = (Val << 32) | Val;
4342 default: // Byte aligned
4345 Count = Op.getOperand(3);
4349 if (AVT > MVT::i8) {
4351 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4352 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
4353 BytesLeft = I->getValue() % UBytes;
4355 assert(AVT >= MVT::i32 &&
4356 "Do not use rep;stos if not at least DWORD aligned");
4357 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4358 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4363 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4365 InFlag = Chain.getValue(1);
4368 Count = Op.getOperand(3);
4369 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4370 InFlag = Chain.getValue(1);
4373 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4375 InFlag = Chain.getValue(1);
4376 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4377 Op.getOperand(1), InFlag);
4378 InFlag = Chain.getValue(1);
4380 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4381 SmallVector<SDOperand, 8> Ops;
4382 Ops.push_back(Chain);
4383 Ops.push_back(DAG.getValueType(AVT));
4384 Ops.push_back(InFlag);
4385 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4388 InFlag = Chain.getValue(1);
4389 Count = Op.getOperand(3);
4390 MVT::ValueType CVT = Count.getValueType();
4391 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4392 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4393 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4395 InFlag = Chain.getValue(1);
4396 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4398 Ops.push_back(Chain);
4399 Ops.push_back(DAG.getValueType(MVT::i8));
4400 Ops.push_back(InFlag);
4401 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4402 } else if (BytesLeft) {
4403 // Issue stores for the last 1 - 7 bytes.
4405 unsigned Val = ValC->getValue() & 255;
4406 unsigned Offset = I->getValue() - BytesLeft;
4407 SDOperand DstAddr = Op.getOperand(1);
4408 MVT::ValueType AddrVT = DstAddr.getValueType();
4409 if (BytesLeft >= 4) {
4410 Val = (Val << 8) | Val;
4411 Val = (Val << 16) | Val;
4412 Value = DAG.getConstant(Val, MVT::i32);
4413 Chain = DAG.getStore(Chain, Value,
4414 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4415 DAG.getConstant(Offset, AddrVT)),
4420 if (BytesLeft >= 2) {
4421 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4422 Chain = DAG.getStore(Chain, Value,
4423 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4424 DAG.getConstant(Offset, AddrVT)),
4429 if (BytesLeft == 1) {
4430 Value = DAG.getConstant(Val, MVT::i8);
4431 Chain = DAG.getStore(Chain, Value,
4432 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4433 DAG.getConstant(Offset, AddrVT)),
4441 SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
4446 SelectionDAG &DAG) {
4448 unsigned BytesLeft = 0;
4449 switch (Align & 3) {
4450 case 2: // WORD aligned
4453 case 0: // DWORD aligned
4455 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4458 default: // Byte aligned
4463 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4464 SDOperand Count = DAG.getConstant(Size / UBytes, getPointerTy());
4465 BytesLeft = Size % UBytes;
4467 SDOperand InFlag(0, 0);
4468 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4470 InFlag = Chain.getValue(1);
4471 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4473 InFlag = Chain.getValue(1);
4474 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4476 InFlag = Chain.getValue(1);
4478 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4479 SmallVector<SDOperand, 8> Ops;
4480 Ops.push_back(Chain);
4481 Ops.push_back(DAG.getValueType(AVT));
4482 Ops.push_back(InFlag);
4483 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4486 // Issue loads and stores for the last 1 - 7 bytes.
4487 unsigned Offset = Size - BytesLeft;
4488 SDOperand DstAddr = Dest;
4489 MVT::ValueType DstVT = DstAddr.getValueType();
4490 SDOperand SrcAddr = Source;
4491 MVT::ValueType SrcVT = SrcAddr.getValueType();
4493 if (BytesLeft >= 4) {
4494 Value = DAG.getLoad(MVT::i32, Chain,
4495 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4496 DAG.getConstant(Offset, SrcVT)),
4498 Chain = Value.getValue(1);
4499 Chain = DAG.getStore(Chain, Value,
4500 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4501 DAG.getConstant(Offset, DstVT)),
4506 if (BytesLeft >= 2) {
4507 Value = DAG.getLoad(MVT::i16, Chain,
4508 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4509 DAG.getConstant(Offset, SrcVT)),
4511 Chain = Value.getValue(1);
4512 Chain = DAG.getStore(Chain, Value,
4513 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4514 DAG.getConstant(Offset, DstVT)),
4520 if (BytesLeft == 1) {
4521 Value = DAG.getLoad(MVT::i8, Chain,
4522 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4523 DAG.getConstant(Offset, SrcVT)),
4525 Chain = Value.getValue(1);
4526 Chain = DAG.getStore(Chain, Value,
4527 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4528 DAG.getConstant(Offset, DstVT)),
4536 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
4537 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
4538 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4539 SDOperand TheChain = N->getOperand(0);
4540 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
4541 if (Subtarget->is64Bit()) {
4542 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4543 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
4544 MVT::i64, rax.getValue(2));
4545 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
4546 DAG.getConstant(32, MVT::i8));
4548 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
4551 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4552 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4555 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4556 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
4557 MVT::i32, eax.getValue(2));
4558 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
4559 SDOperand Ops[] = { eax, edx };
4560 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
4562 // Use a MERGE_VALUES to return the value and chain.
4563 Ops[1] = edx.getValue(1);
4564 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4565 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4568 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4569 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4571 if (!Subtarget->is64Bit()) {
4572 // vastart just stores the address of the VarArgsFrameIndex slot into the
4573 // memory location argument.
4574 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4575 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4580 // gp_offset (0 - 6 * 8)
4581 // fp_offset (48 - 48 + 8 * 16)
4582 // overflow_arg_area (point to parameters coming in memory).
4584 SmallVector<SDOperand, 8> MemOps;
4585 SDOperand FIN = Op.getOperand(1);
4587 SDOperand Store = DAG.getStore(Op.getOperand(0),
4588 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4589 FIN, SV->getValue(), SV->getOffset());
4590 MemOps.push_back(Store);
4593 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4594 DAG.getConstant(4, getPointerTy()));
4595 Store = DAG.getStore(Op.getOperand(0),
4596 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4597 FIN, SV->getValue(), SV->getOffset());
4598 MemOps.push_back(Store);
4600 // Store ptr to overflow_arg_area
4601 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4602 DAG.getConstant(4, getPointerTy()));
4603 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4604 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4606 MemOps.push_back(Store);
4608 // Store ptr to reg_save_area.
4609 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4610 DAG.getConstant(8, getPointerTy()));
4611 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4612 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4614 MemOps.push_back(Store);
4615 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4618 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4619 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4620 SDOperand Chain = Op.getOperand(0);
4621 SDOperand DstPtr = Op.getOperand(1);
4622 SDOperand SrcPtr = Op.getOperand(2);
4623 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4624 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4626 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4627 SrcSV->getValue(), SrcSV->getOffset());
4628 Chain = SrcPtr.getValue(1);
4629 for (unsigned i = 0; i < 3; ++i) {
4630 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4631 SrcSV->getValue(), SrcSV->getOffset());
4632 Chain = Val.getValue(1);
4633 Chain = DAG.getStore(Chain, Val, DstPtr,
4634 DstSV->getValue(), DstSV->getOffset());
4637 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4638 DAG.getConstant(8, getPointerTy()));
4639 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4640 DAG.getConstant(8, getPointerTy()));
4646 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4647 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4649 default: return SDOperand(); // Don't custom lower most intrinsics.
4650 // Comparison intrinsics.
4651 case Intrinsic::x86_sse_comieq_ss:
4652 case Intrinsic::x86_sse_comilt_ss:
4653 case Intrinsic::x86_sse_comile_ss:
4654 case Intrinsic::x86_sse_comigt_ss:
4655 case Intrinsic::x86_sse_comige_ss:
4656 case Intrinsic::x86_sse_comineq_ss:
4657 case Intrinsic::x86_sse_ucomieq_ss:
4658 case Intrinsic::x86_sse_ucomilt_ss:
4659 case Intrinsic::x86_sse_ucomile_ss:
4660 case Intrinsic::x86_sse_ucomigt_ss:
4661 case Intrinsic::x86_sse_ucomige_ss:
4662 case Intrinsic::x86_sse_ucomineq_ss:
4663 case Intrinsic::x86_sse2_comieq_sd:
4664 case Intrinsic::x86_sse2_comilt_sd:
4665 case Intrinsic::x86_sse2_comile_sd:
4666 case Intrinsic::x86_sse2_comigt_sd:
4667 case Intrinsic::x86_sse2_comige_sd:
4668 case Intrinsic::x86_sse2_comineq_sd:
4669 case Intrinsic::x86_sse2_ucomieq_sd:
4670 case Intrinsic::x86_sse2_ucomilt_sd:
4671 case Intrinsic::x86_sse2_ucomile_sd:
4672 case Intrinsic::x86_sse2_ucomigt_sd:
4673 case Intrinsic::x86_sse2_ucomige_sd:
4674 case Intrinsic::x86_sse2_ucomineq_sd: {
4676 ISD::CondCode CC = ISD::SETCC_INVALID;
4679 case Intrinsic::x86_sse_comieq_ss:
4680 case Intrinsic::x86_sse2_comieq_sd:
4684 case Intrinsic::x86_sse_comilt_ss:
4685 case Intrinsic::x86_sse2_comilt_sd:
4689 case Intrinsic::x86_sse_comile_ss:
4690 case Intrinsic::x86_sse2_comile_sd:
4694 case Intrinsic::x86_sse_comigt_ss:
4695 case Intrinsic::x86_sse2_comigt_sd:
4699 case Intrinsic::x86_sse_comige_ss:
4700 case Intrinsic::x86_sse2_comige_sd:
4704 case Intrinsic::x86_sse_comineq_ss:
4705 case Intrinsic::x86_sse2_comineq_sd:
4709 case Intrinsic::x86_sse_ucomieq_ss:
4710 case Intrinsic::x86_sse2_ucomieq_sd:
4711 Opc = X86ISD::UCOMI;
4714 case Intrinsic::x86_sse_ucomilt_ss:
4715 case Intrinsic::x86_sse2_ucomilt_sd:
4716 Opc = X86ISD::UCOMI;
4719 case Intrinsic::x86_sse_ucomile_ss:
4720 case Intrinsic::x86_sse2_ucomile_sd:
4721 Opc = X86ISD::UCOMI;
4724 case Intrinsic::x86_sse_ucomigt_ss:
4725 case Intrinsic::x86_sse2_ucomigt_sd:
4726 Opc = X86ISD::UCOMI;
4729 case Intrinsic::x86_sse_ucomige_ss:
4730 case Intrinsic::x86_sse2_ucomige_sd:
4731 Opc = X86ISD::UCOMI;
4734 case Intrinsic::x86_sse_ucomineq_ss:
4735 case Intrinsic::x86_sse2_ucomineq_sd:
4736 Opc = X86ISD::UCOMI;
4742 SDOperand LHS = Op.getOperand(1);
4743 SDOperand RHS = Op.getOperand(2);
4744 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4746 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
4747 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
4748 DAG.getConstant(X86CC, MVT::i8), Cond);
4749 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4754 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4755 // Depths > 0 not supported yet!
4756 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4759 // Just load the return address
4760 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4761 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4764 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4765 // Depths > 0 not supported yet!
4766 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4769 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4770 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4771 DAG.getConstant(4, getPointerTy()));
4774 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
4775 SelectionDAG &DAG) {
4776 // Is not yet supported on x86-64
4777 if (Subtarget->is64Bit())
4780 return DAG.getConstant(8, getPointerTy());
4783 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
4785 assert(!Subtarget->is64Bit() &&
4786 "Lowering of eh_return builtin is not supported yet on x86-64");
4788 MachineFunction &MF = DAG.getMachineFunction();
4789 SDOperand Chain = Op.getOperand(0);
4790 SDOperand Offset = Op.getOperand(1);
4791 SDOperand Handler = Op.getOperand(2);
4793 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
4796 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
4797 DAG.getConstant(-4UL, getPointerTy()));
4798 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
4799 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
4800 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
4801 MF.getRegInfo().addLiveOut(X86::ECX);
4803 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
4804 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
4807 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
4808 SelectionDAG &DAG) {
4809 SDOperand Root = Op.getOperand(0);
4810 SDOperand Trmp = Op.getOperand(1); // trampoline
4811 SDOperand FPtr = Op.getOperand(2); // nested function
4812 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
4814 SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4));
4816 if (Subtarget->is64Bit()) {
4817 return SDOperand(); // not yet supported
4819 Function *Func = (Function *)
4820 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
4821 unsigned CC = Func->getCallingConv();
4826 assert(0 && "Unsupported calling convention");
4827 case CallingConv::C:
4828 case CallingConv::X86_StdCall: {
4829 // Pass 'nest' parameter in ECX.
4830 // Must be kept in sync with X86CallingConv.td
4833 // Check that ECX wasn't needed by an 'inreg' parameter.
4834 const FunctionType *FTy = Func->getFunctionType();
4835 const ParamAttrsList *Attrs = Func->getParamAttrs();
4837 if (Attrs && !Func->isVarArg()) {
4838 unsigned InRegCount = 0;
4841 for (FunctionType::param_iterator I = FTy->param_begin(),
4842 E = FTy->param_end(); I != E; ++I, ++Idx)
4843 if (Attrs->paramHasAttr(Idx, ParamAttr::InReg))
4844 // FIXME: should only count parameters that are lowered to integers.
4845 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
4847 if (InRegCount > 2) {
4848 cerr << "Nest register in use - reduce number of inreg parameters!\n";
4854 case CallingConv::X86_FastCall:
4855 // Pass 'nest' parameter in EAX.
4856 // Must be kept in sync with X86CallingConv.td
4861 const X86InstrInfo *TII =
4862 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
4864 SDOperand OutChains[4];
4865 SDOperand Addr, Disp;
4867 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
4868 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
4870 unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
4871 unsigned char N86Reg = ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
4872 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
4873 Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
4875 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
4876 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4877 TrmpSV->getOffset() + 1, false, 1);
4879 unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
4880 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
4881 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
4882 TrmpSV->getValue() + 5, TrmpSV->getOffset());
4884 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
4885 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(),
4886 TrmpSV->getOffset() + 6, false, 1);
4889 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
4890 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
4894 SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) {
4896 The rounding mode is in bits 11:10 of FPSR, and has the following
4903 FLT_ROUNDS, on the other hand, expects the following:
4910 To perform the conversion, we do:
4911 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
4914 MachineFunction &MF = DAG.getMachineFunction();
4915 const TargetMachine &TM = MF.getTarget();
4916 const TargetFrameInfo &TFI = *TM.getFrameInfo();
4917 unsigned StackAlignment = TFI.getStackAlignment();
4918 MVT::ValueType VT = Op.getValueType();
4920 // Save FP Control Word to stack slot
4921 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
4922 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4924 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
4925 DAG.getEntryNode(), StackSlot);
4927 // Load FP Control Word from stack slot
4928 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
4930 // Transform as necessary
4932 DAG.getNode(ISD::SRL, MVT::i16,
4933 DAG.getNode(ISD::AND, MVT::i16,
4934 CWD, DAG.getConstant(0x800, MVT::i16)),
4935 DAG.getConstant(11, MVT::i8));
4937 DAG.getNode(ISD::SRL, MVT::i16,
4938 DAG.getNode(ISD::AND, MVT::i16,
4939 CWD, DAG.getConstant(0x400, MVT::i16)),
4940 DAG.getConstant(9, MVT::i8));
4943 DAG.getNode(ISD::AND, MVT::i16,
4944 DAG.getNode(ISD::ADD, MVT::i16,
4945 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
4946 DAG.getConstant(1, MVT::i16)),
4947 DAG.getConstant(3, MVT::i16));
4950 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
4951 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
4954 SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
4955 MVT::ValueType VT = Op.getValueType();
4956 MVT::ValueType OpVT = VT;
4957 unsigned NumBits = MVT::getSizeInBits(VT);
4959 Op = Op.getOperand(0);
4960 if (VT == MVT::i8) {
4961 // Zero extend to i32 since there is not an i8 bsr.
4963 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
4966 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
4967 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
4968 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
4970 // If src is zero (i.e. bsr sets ZF), returns NumBits.
4971 SmallVector<SDOperand, 4> Ops;
4973 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
4974 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
4975 Ops.push_back(Op.getValue(1));
4976 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
4978 // Finally xor with NumBits-1.
4979 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
4982 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
4986 SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
4987 MVT::ValueType VT = Op.getValueType();
4988 MVT::ValueType OpVT = VT;
4989 unsigned NumBits = MVT::getSizeInBits(VT);
4991 Op = Op.getOperand(0);
4992 if (VT == MVT::i8) {
4994 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
4997 // Issue a bsf (scan bits forward) which also sets EFLAGS.
4998 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
4999 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5001 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5002 SmallVector<SDOperand, 4> Ops;
5004 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5005 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5006 Ops.push_back(Op.getValue(1));
5007 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5010 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5014 /// LowerOperation - Provide custom lowering hooks for some operations.
5016 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5017 switch (Op.getOpcode()) {
5018 default: assert(0 && "Should not custom lower this!");
5019 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5020 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5021 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5022 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5023 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5024 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5025 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5026 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5027 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5028 case ISD::SHL_PARTS:
5029 case ISD::SRA_PARTS:
5030 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5031 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5032 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5033 case ISD::FABS: return LowerFABS(Op, DAG);
5034 case ISD::FNEG: return LowerFNEG(Op, DAG);
5035 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5036 case ISD::SETCC: return LowerSETCC(Op, DAG);
5037 case ISD::SELECT: return LowerSELECT(Op, DAG);
5038 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5039 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5040 case ISD::CALL: return LowerCALL(Op, DAG);
5041 case ISD::RET: return LowerRET(Op, DAG);
5042 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5043 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
5044 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
5045 case ISD::VASTART: return LowerVASTART(Op, DAG);
5046 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5047 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5048 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5049 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5050 case ISD::FRAME_TO_ARGS_OFFSET:
5051 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5052 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
5053 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
5054 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
5055 case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
5056 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5057 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
5059 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5060 case ISD::READCYCLECOUNTER:
5061 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
5065 /// ExpandOperation - Provide custom lowering hooks for expanding operations.
5066 SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
5067 switch (N->getOpcode()) {
5068 default: assert(0 && "Should not custom lower this!");
5069 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5070 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5074 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5076 default: return NULL;
5077 case X86ISD::BSF: return "X86ISD::BSF";
5078 case X86ISD::BSR: return "X86ISD::BSR";
5079 case X86ISD::SHLD: return "X86ISD::SHLD";
5080 case X86ISD::SHRD: return "X86ISD::SHRD";
5081 case X86ISD::FAND: return "X86ISD::FAND";
5082 case X86ISD::FOR: return "X86ISD::FOR";
5083 case X86ISD::FXOR: return "X86ISD::FXOR";
5084 case X86ISD::FSRL: return "X86ISD::FSRL";
5085 case X86ISD::FILD: return "X86ISD::FILD";
5086 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
5087 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5088 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5089 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
5090 case X86ISD::FLD: return "X86ISD::FLD";
5091 case X86ISD::FST: return "X86ISD::FST";
5092 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
5093 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
5094 case X86ISD::CALL: return "X86ISD::CALL";
5095 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5096 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5097 case X86ISD::CMP: return "X86ISD::CMP";
5098 case X86ISD::COMI: return "X86ISD::COMI";
5099 case X86ISD::UCOMI: return "X86ISD::UCOMI";
5100 case X86ISD::SETCC: return "X86ISD::SETCC";
5101 case X86ISD::CMOV: return "X86ISD::CMOV";
5102 case X86ISD::BRCOND: return "X86ISD::BRCOND";
5103 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
5104 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5105 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
5106 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
5107 case X86ISD::Wrapper: return "X86ISD::Wrapper";
5108 case X86ISD::S2VEC: return "X86ISD::S2VEC";
5109 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
5110 case X86ISD::PINSRW: return "X86ISD::PINSRW";
5111 case X86ISD::FMAX: return "X86ISD::FMAX";
5112 case X86ISD::FMIN: return "X86ISD::FMIN";
5113 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5114 case X86ISD::FRCP: return "X86ISD::FRCP";
5115 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5116 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
5117 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
5118 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
5119 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
5123 // isLegalAddressingMode - Return true if the addressing mode represented
5124 // by AM is legal for this target, for a load/store of the specified type.
5125 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5126 const Type *Ty) const {
5127 // X86 supports extremely general addressing modes.
5129 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5130 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5134 // We can only fold this if we don't need an extra load.
5135 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5138 // X86-64 only supports addr of globals in small code model.
5139 if (Subtarget->is64Bit()) {
5140 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5142 // If lower 4G is not available, then we must use rip-relative addressing.
5143 if (AM.BaseOffs || AM.Scale > 1)
5154 // These scales always work.
5159 // These scales are formed with basereg+scalereg. Only accept if there is
5164 default: // Other stuff never works.
5172 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5173 if (!Ty1->isInteger() || !Ty2->isInteger())
5175 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5176 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5177 if (NumBits1 <= NumBits2)
5179 return Subtarget->is64Bit() || NumBits1 < 64;
5182 bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1,
5183 MVT::ValueType VT2) const {
5184 if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2))
5186 unsigned NumBits1 = MVT::getSizeInBits(VT1);
5187 unsigned NumBits2 = MVT::getSizeInBits(VT2);
5188 if (NumBits1 <= NumBits2)
5190 return Subtarget->is64Bit() || NumBits1 < 64;
5193 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5194 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5195 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5196 /// are assumed to be legal.
5198 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
5199 // Only do shuffles on 128-bit vector types for now.
5200 if (MVT::getSizeInBits(VT) == 64) return false;
5201 return (Mask.Val->getNumOperands() <= 4 ||
5202 isIdentityMask(Mask.Val) ||
5203 isIdentityMask(Mask.Val, true) ||
5204 isSplatMask(Mask.Val) ||
5205 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5206 X86::isUNPCKLMask(Mask.Val) ||
5207 X86::isUNPCKHMask(Mask.Val) ||
5208 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
5209 X86::isUNPCKH_v_undef_Mask(Mask.Val));
5212 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
5214 SelectionDAG &DAG) const {
5215 unsigned NumElts = BVOps.size();
5216 // Only do shuffles on 128-bit vector types for now.
5217 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
5218 if (NumElts == 2) return true;
5220 return (isMOVLMask(&BVOps[0], 4) ||
5221 isCommutedMOVL(&BVOps[0], 4, true) ||
5222 isSHUFPMask(&BVOps[0], 4) ||
5223 isCommutedSHUFP(&BVOps[0], 4));
5228 //===----------------------------------------------------------------------===//
5229 // X86 Scheduler Hooks
5230 //===----------------------------------------------------------------------===//
5233 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
5234 MachineBasicBlock *BB) {
5235 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5236 switch (MI->getOpcode()) {
5237 default: assert(false && "Unexpected instr type to insert");
5238 case X86::CMOV_FR32:
5239 case X86::CMOV_FR64:
5240 case X86::CMOV_V4F32:
5241 case X86::CMOV_V2F64:
5242 case X86::CMOV_V2I64: {
5243 // To "insert" a SELECT_CC instruction, we actually have to insert the
5244 // diamond control-flow pattern. The incoming instruction knows the
5245 // destination vreg to set, the condition code register to branch on, the
5246 // true/false values to select between, and a branch opcode to use.
5247 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5248 ilist<MachineBasicBlock>::iterator It = BB;
5254 // cmpTY ccX, r1, r2
5256 // fallthrough --> copy0MBB
5257 MachineBasicBlock *thisMBB = BB;
5258 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
5259 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
5261 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
5262 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
5263 MachineFunction *F = BB->getParent();
5264 F->getBasicBlockList().insert(It, copy0MBB);
5265 F->getBasicBlockList().insert(It, sinkMBB);
5266 // Update machine-CFG edges by first adding all successors of the current
5267 // block to the new block which will contain the Phi node for the select.
5268 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
5269 e = BB->succ_end(); i != e; ++i)
5270 sinkMBB->addSuccessor(*i);
5271 // Next, remove all successors of the current block, and add the true
5272 // and fallthrough blocks as its successors.
5273 while(!BB->succ_empty())
5274 BB->removeSuccessor(BB->succ_begin());
5275 BB->addSuccessor(copy0MBB);
5276 BB->addSuccessor(sinkMBB);
5279 // %FalseValue = ...
5280 // # fallthrough to sinkMBB
5283 // Update machine-CFG edges
5284 BB->addSuccessor(sinkMBB);
5287 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5290 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
5291 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5292 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5294 delete MI; // The pseudo instruction is gone now.
5298 case X86::FP32_TO_INT16_IN_MEM:
5299 case X86::FP32_TO_INT32_IN_MEM:
5300 case X86::FP32_TO_INT64_IN_MEM:
5301 case X86::FP64_TO_INT16_IN_MEM:
5302 case X86::FP64_TO_INT32_IN_MEM:
5303 case X86::FP64_TO_INT64_IN_MEM:
5304 case X86::FP80_TO_INT16_IN_MEM:
5305 case X86::FP80_TO_INT32_IN_MEM:
5306 case X86::FP80_TO_INT64_IN_MEM: {
5307 // Change the floating point control register to use "round towards zero"
5308 // mode when truncating to an integer value.
5309 MachineFunction *F = BB->getParent();
5310 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
5311 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
5313 // Load the old value of the high byte of the control word...
5315 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
5316 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
5318 // Set the high part to be round to zero...
5319 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
5322 // Reload the modified control word now...
5323 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5325 // Restore the memory image of control word to original value
5326 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
5329 // Get the X86 opcode to use.
5331 switch (MI->getOpcode()) {
5332 default: assert(0 && "illegal opcode!");
5333 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
5334 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
5335 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
5336 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
5337 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
5338 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
5339 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
5340 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
5341 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
5345 MachineOperand &Op = MI->getOperand(0);
5346 if (Op.isRegister()) {
5347 AM.BaseType = X86AddressMode::RegBase;
5348 AM.Base.Reg = Op.getReg();
5350 AM.BaseType = X86AddressMode::FrameIndexBase;
5351 AM.Base.FrameIndex = Op.getIndex();
5353 Op = MI->getOperand(1);
5354 if (Op.isImmediate())
5355 AM.Scale = Op.getImm();
5356 Op = MI->getOperand(2);
5357 if (Op.isImmediate())
5358 AM.IndexReg = Op.getImm();
5359 Op = MI->getOperand(3);
5360 if (Op.isGlobalAddress()) {
5361 AM.GV = Op.getGlobal();
5363 AM.Disp = Op.getImm();
5365 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
5366 .addReg(MI->getOperand(4).getReg());
5368 // Reload the original control word now.
5369 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5371 delete MI; // The pseudo instruction is gone now.
5377 //===----------------------------------------------------------------------===//
5378 // X86 Optimization Hooks
5379 //===----------------------------------------------------------------------===//
5381 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
5383 uint64_t &KnownZero,
5385 const SelectionDAG &DAG,
5386 unsigned Depth) const {
5387 unsigned Opc = Op.getOpcode();
5388 assert((Opc >= ISD::BUILTIN_OP_END ||
5389 Opc == ISD::INTRINSIC_WO_CHAIN ||
5390 Opc == ISD::INTRINSIC_W_CHAIN ||
5391 Opc == ISD::INTRINSIC_VOID) &&
5392 "Should use MaskedValueIsZero if you don't know whether Op"
5393 " is a target node!");
5395 KnownZero = KnownOne = 0; // Don't know anything.
5399 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
5404 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5405 /// element of the result of the vector shuffle.
5406 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
5407 MVT::ValueType VT = N->getValueType(0);
5408 SDOperand PermMask = N->getOperand(2);
5409 unsigned NumElems = PermMask.getNumOperands();
5410 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
5412 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5414 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5415 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
5416 SDOperand Idx = PermMask.getOperand(i);
5417 if (Idx.getOpcode() == ISD::UNDEF)
5418 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5419 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
5424 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
5425 /// node is a GlobalAddress + an offset.
5426 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
5427 unsigned Opc = N->getOpcode();
5428 if (Opc == X86ISD::Wrapper) {
5429 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
5430 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
5433 } else if (Opc == ISD::ADD) {
5434 SDOperand N1 = N->getOperand(0);
5435 SDOperand N2 = N->getOperand(1);
5436 if (isGAPlusOffset(N1.Val, GA, Offset)) {
5437 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
5439 Offset += V->getSignExtended();
5442 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
5443 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
5445 Offset += V->getSignExtended();
5453 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
5455 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
5456 MachineFrameInfo *MFI) {
5457 if (N->getOperand(0).Val != Base->getOperand(0).Val)
5460 SDOperand Loc = N->getOperand(1);
5461 SDOperand BaseLoc = Base->getOperand(1);
5462 if (Loc.getOpcode() == ISD::FrameIndex) {
5463 if (BaseLoc.getOpcode() != ISD::FrameIndex)
5465 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
5466 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
5467 int FS = MFI->getObjectSize(FI);
5468 int BFS = MFI->getObjectSize(BFI);
5469 if (FS != BFS || FS != Size) return false;
5470 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
5472 GlobalValue *GV1 = NULL;
5473 GlobalValue *GV2 = NULL;
5474 int64_t Offset1 = 0;
5475 int64_t Offset2 = 0;
5476 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
5477 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
5478 if (isGA1 && isGA2 && GV1 == GV2)
5479 return Offset1 == (Offset2 + Dist*Size);
5485 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
5486 const X86Subtarget *Subtarget) {
5489 if (isGAPlusOffset(Base, GV, Offset))
5490 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
5492 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
5493 int BFI = cast<FrameIndexSDNode>(Base)->getIndex();
5495 // Fixed objects do not specify alignment, however the offsets are known.
5496 return ((Subtarget->getStackAlignment() % 16) == 0 &&
5497 (MFI->getObjectOffset(BFI) % 16) == 0);
5499 return MFI->getObjectAlignment(BFI) >= 16;
5505 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5506 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5507 /// if the load addresses are consecutive, non-overlapping, and in the right
5509 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5510 const X86Subtarget *Subtarget) {
5511 MachineFunction &MF = DAG.getMachineFunction();
5512 MachineFrameInfo *MFI = MF.getFrameInfo();
5513 MVT::ValueType VT = N->getValueType(0);
5514 MVT::ValueType EVT = MVT::getVectorElementType(VT);
5515 SDOperand PermMask = N->getOperand(2);
5516 int NumElems = (int)PermMask.getNumOperands();
5517 SDNode *Base = NULL;
5518 for (int i = 0; i < NumElems; ++i) {
5519 SDOperand Idx = PermMask.getOperand(i);
5520 if (Idx.getOpcode() == ISD::UNDEF) {
5521 if (!Base) return SDOperand();
5524 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
5525 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
5529 else if (!isConsecutiveLoad(Arg.Val, Base,
5530 i, MVT::getSizeInBits(EVT)/8,MFI))
5535 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
5536 LoadSDNode *LD = cast<LoadSDNode>(Base);
5538 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5539 LD->getSrcValueOffset(), LD->isVolatile());
5541 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5542 LD->getSrcValueOffset(), LD->isVolatile(),
5543 LD->getAlignment());
5547 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
5548 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
5549 const X86Subtarget *Subtarget) {
5550 SDOperand Cond = N->getOperand(0);
5552 // If we have SSE[12] support, try to form min/max nodes.
5553 if (Subtarget->hasSSE2() &&
5554 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
5555 if (Cond.getOpcode() == ISD::SETCC) {
5556 // Get the LHS/RHS of the select.
5557 SDOperand LHS = N->getOperand(1);
5558 SDOperand RHS = N->getOperand(2);
5559 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
5561 unsigned Opcode = 0;
5562 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
5565 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
5568 if (!UnsafeFPMath) break;
5570 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
5572 Opcode = X86ISD::FMIN;
5575 case ISD::SETOGT: // (X > Y) ? X : Y -> max
5578 if (!UnsafeFPMath) break;
5580 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
5582 Opcode = X86ISD::FMAX;
5585 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
5588 case ISD::SETOGT: // (X > Y) ? Y : X -> min
5591 if (!UnsafeFPMath) break;
5593 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
5595 Opcode = X86ISD::FMIN;
5598 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
5601 if (!UnsafeFPMath) break;
5603 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
5605 Opcode = X86ISD::FMAX;
5611 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
5620 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
5621 DAGCombinerInfo &DCI) const {
5622 SelectionDAG &DAG = DCI.DAG;
5623 switch (N->getOpcode()) {
5625 case ISD::VECTOR_SHUFFLE:
5626 return PerformShuffleCombine(N, DAG, Subtarget);
5628 return PerformSELECTCombine(N, DAG, Subtarget);
5634 //===----------------------------------------------------------------------===//
5635 // X86 Inline Assembly Support
5636 //===----------------------------------------------------------------------===//
5638 /// getConstraintType - Given a constraint letter, return the type of
5639 /// constraint it is for this target.
5640 X86TargetLowering::ConstraintType
5641 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
5642 if (Constraint.size() == 1) {
5643 switch (Constraint[0]) {
5652 return C_RegisterClass;
5657 return TargetLowering::getConstraintType(Constraint);
5660 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5661 /// vector. If it is invalid, don't add anything to Ops.
5662 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
5664 std::vector<SDOperand>&Ops,
5665 SelectionDAG &DAG) {
5666 SDOperand Result(0, 0);
5668 switch (Constraint) {
5671 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5672 if (C->getValue() <= 31) {
5673 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5679 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5680 if (C->getValue() <= 255) {
5681 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5687 // Literal immediates are always ok.
5688 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
5689 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
5693 // If we are in non-pic codegen mode, we allow the address of a global (with
5694 // an optional displacement) to be used with 'i'.
5695 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
5698 // Match either (GA) or (GA+C)
5700 Offset = GA->getOffset();
5701 } else if (Op.getOpcode() == ISD::ADD) {
5702 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5703 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5705 Offset = GA->getOffset()+C->getValue();
5707 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5708 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5710 Offset = GA->getOffset()+C->getValue();
5717 // If addressing this global requires a load (e.g. in PIC mode), we can't
5719 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
5723 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5729 // Otherwise, not valid for this mode.
5735 Ops.push_back(Result);
5738 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5741 std::vector<unsigned> X86TargetLowering::
5742 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5743 MVT::ValueType VT) const {
5744 if (Constraint.size() == 1) {
5745 // FIXME: not handling fp-stack yet!
5746 switch (Constraint[0]) { // GCC X86 Constraint Letters
5747 default: break; // Unknown constraint letter
5748 case 'A': // EAX/EDX
5749 if (VT == MVT::i32 || VT == MVT::i64)
5750 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5752 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5755 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5756 else if (VT == MVT::i16)
5757 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5758 else if (VT == MVT::i8)
5759 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5760 else if (VT == MVT::i64)
5761 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
5766 return std::vector<unsigned>();
5769 std::pair<unsigned, const TargetRegisterClass*>
5770 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5771 MVT::ValueType VT) const {
5772 // First, see if this is a constraint that directly corresponds to an LLVM
5774 if (Constraint.size() == 1) {
5775 // GCC Constraint Letters
5776 switch (Constraint[0]) {
5778 case 'r': // GENERAL_REGS
5779 case 'R': // LEGACY_REGS
5780 case 'l': // INDEX_REGS
5781 if (VT == MVT::i64 && Subtarget->is64Bit())
5782 return std::make_pair(0U, X86::GR64RegisterClass);
5784 return std::make_pair(0U, X86::GR32RegisterClass);
5785 else if (VT == MVT::i16)
5786 return std::make_pair(0U, X86::GR16RegisterClass);
5787 else if (VT == MVT::i8)
5788 return std::make_pair(0U, X86::GR8RegisterClass);
5790 case 'y': // MMX_REGS if MMX allowed.
5791 if (!Subtarget->hasMMX()) break;
5792 return std::make_pair(0U, X86::VR64RegisterClass);
5794 case 'Y': // SSE_REGS if SSE2 allowed
5795 if (!Subtarget->hasSSE2()) break;
5797 case 'x': // SSE_REGS if SSE1 allowed
5798 if (!Subtarget->hasSSE1()) break;
5802 // Scalar SSE types.
5805 return std::make_pair(0U, X86::FR32RegisterClass);
5808 return std::make_pair(0U, X86::FR64RegisterClass);
5816 return std::make_pair(0U, X86::VR128RegisterClass);
5822 // Use the default implementation in TargetLowering to convert the register
5823 // constraint into a member of a register class.
5824 std::pair<unsigned, const TargetRegisterClass*> Res;
5825 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5827 // Not found as a standard register?
5828 if (Res.second == 0) {
5829 // GCC calls "st(0)" just plain "st".
5830 if (StringsEqualNoCase("{st}", Constraint)) {
5831 Res.first = X86::ST0;
5832 Res.second = X86::RFP80RegisterClass;
5838 // Otherwise, check to see if this is a register class of the wrong value
5839 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5840 // turn into {ax},{dx}.
5841 if (Res.second->hasType(VT))
5842 return Res; // Correct type already, nothing to do.
5844 // All of the single-register GCC register classes map their values onto
5845 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5846 // really want an 8-bit or 32-bit register, map to the appropriate register
5847 // class and return the appropriate register.
5848 if (Res.second != X86::GR16RegisterClass)
5851 if (VT == MVT::i8) {
5852 unsigned DestReg = 0;
5853 switch (Res.first) {
5855 case X86::AX: DestReg = X86::AL; break;
5856 case X86::DX: DestReg = X86::DL; break;
5857 case X86::CX: DestReg = X86::CL; break;
5858 case X86::BX: DestReg = X86::BL; break;
5861 Res.first = DestReg;
5862 Res.second = Res.second = X86::GR8RegisterClass;
5864 } else if (VT == MVT::i32) {
5865 unsigned DestReg = 0;
5866 switch (Res.first) {
5868 case X86::AX: DestReg = X86::EAX; break;
5869 case X86::DX: DestReg = X86::EDX; break;
5870 case X86::CX: DestReg = X86::ECX; break;
5871 case X86::BX: DestReg = X86::EBX; break;
5872 case X86::SI: DestReg = X86::ESI; break;
5873 case X86::DI: DestReg = X86::EDI; break;
5874 case X86::BP: DestReg = X86::EBP; break;
5875 case X86::SP: DestReg = X86::ESP; break;
5878 Res.first = DestReg;
5879 Res.second = Res.second = X86::GR32RegisterClass;
5881 } else if (VT == MVT::i64) {
5882 unsigned DestReg = 0;
5883 switch (Res.first) {
5885 case X86::AX: DestReg = X86::RAX; break;
5886 case X86::DX: DestReg = X86::RDX; break;
5887 case X86::CX: DestReg = X86::RCX; break;
5888 case X86::BX: DestReg = X86::RBX; break;
5889 case X86::SI: DestReg = X86::RSI; break;
5890 case X86::DI: DestReg = X86::RDI; break;
5891 case X86::BP: DestReg = X86::RBP; break;
5892 case X86::SP: DestReg = X86::RSP; break;
5895 Res.first = DestReg;
5896 Res.second = Res.second = X86::GR64RegisterClass;