1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec,
69 EVT VT = Vec.getValueType();
70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
71 EVT ElVT = VT.getVectorElementType();
72 int Factor = VT.getSizeInBits()/128;
73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
74 VT.getVectorNumElements()/Factor);
76 // Extract from UNDEF is UNDEF.
77 if (Vec.getOpcode() == ISD::UNDEF)
78 return DAG.getUNDEF(ResultVT);
80 if (isa<ConstantSDNode>(Idx)) {
81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
84 // we can match to VEXTRACTF128.
85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
87 // This is the index of the first element of the 128-bit chunk
89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
102 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
103 /// sets things up to match to an AVX VINSERTF128 instruction or a
104 /// simple superregister reference. Idx is an index in the 128 bits
105 /// we want. It need not be aligned to a 128-bit bounday. That makes
106 /// lowering INSERT_VECTOR_ELT operations easier.
107 static SDValue Insert128BitVector(SDValue Result,
112 if (isa<ConstantSDNode>(Idx)) {
113 EVT VT = Vec.getValueType();
114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
116 EVT ElVT = VT.getVectorElementType();
117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
118 EVT ResultVT = Result.getValueType();
120 // Insert the relevant 128 bits.
121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
123 // This is the index of the first element of the 128-bit chunk
125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
137 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
138 /// instructions. This is used because creating CONCAT_VECTOR nodes of
139 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
140 /// large BUILD_VECTORS.
141 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
142 unsigned NumElems, SelectionDAG &DAG,
144 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1,
145 DAG.getConstant(0, MVT::i32), DAG, dl);
146 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
150 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
151 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
152 bool is64Bit = Subtarget->is64Bit();
154 if (Subtarget->isTargetEnvMacho()) {
156 return new X8664_MachoTargetObjectFile();
157 return new TargetLoweringObjectFileMachO();
160 if (Subtarget->isTargetELF())
161 return new TargetLoweringObjectFileELF();
162 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
163 return new TargetLoweringObjectFileCOFF();
164 llvm_unreachable("unknown subtarget type");
167 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
168 : TargetLowering(TM, createTLOF(TM)) {
169 Subtarget = &TM.getSubtarget<X86Subtarget>();
170 X86ScalarSSEf64 = Subtarget->hasSSE2();
171 X86ScalarSSEf32 = Subtarget->hasSSE1();
172 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
174 RegInfo = TM.getRegisterInfo();
175 TD = getTargetData();
177 // Set up the TargetLowering object.
178 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
180 // X86 is weird, it always uses i8 for shift amounts and setcc results.
181 setBooleanContents(ZeroOrOneBooleanContent);
182 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
183 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
185 // For 64-bit since we have so many registers use the ILP scheduler, for
186 // 32-bit code use the register pressure specific scheduling.
187 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
188 if (Subtarget->is64Bit())
189 setSchedulingPreference(Sched::ILP);
190 else if (Subtarget->isAtom())
191 setSchedulingPreference(Sched::Hybrid);
193 setSchedulingPreference(Sched::RegPressure);
194 setStackPointerRegisterToSaveRestore(X86StackPtr);
196 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
197 // Setup Windows compiler runtime calls.
198 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
199 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
200 setLibcallName(RTLIB::SREM_I64, "_allrem");
201 setLibcallName(RTLIB::UREM_I64, "_aullrem");
202 setLibcallName(RTLIB::MUL_I64, "_allmul");
203 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
204 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
209 // The _ftol2 runtime function has an unusual calling conv, which
210 // is modeled by a special pseudo-instruction.
211 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
212 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
213 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
214 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
217 if (Subtarget->isTargetDarwin()) {
218 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
219 setUseUnderscoreSetJmp(false);
220 setUseUnderscoreLongJmp(false);
221 } else if (Subtarget->isTargetMingw()) {
222 // MS runtime is weird: it exports _setjmp, but longjmp!
223 setUseUnderscoreSetJmp(true);
224 setUseUnderscoreLongJmp(false);
226 setUseUnderscoreSetJmp(true);
227 setUseUnderscoreLongJmp(true);
230 // Set up the register classes.
231 addRegisterClass(MVT::i8, &X86::GR8RegClass);
232 addRegisterClass(MVT::i16, &X86::GR16RegClass);
233 addRegisterClass(MVT::i32, &X86::GR32RegClass);
234 if (Subtarget->is64Bit())
235 addRegisterClass(MVT::i64, &X86::GR64RegClass);
237 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
239 // We don't accept any truncstore of integer registers.
240 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
241 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
242 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
243 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
244 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
245 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
247 // SETOEQ and SETUNE require checking two conditions.
248 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
249 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
250 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
251 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
252 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
253 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
255 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
257 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
261 if (Subtarget->is64Bit()) {
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
264 } else if (!TM.Options.UseSoftFloat) {
265 // We have an algorithm for SSE2->double, and we turn this into a
266 // 64-bit FILD followed by conditional FADD for other targets.
267 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
268 // We have an algorithm for SSE2, and we turn this into a 64-bit
269 // FILD for other targets.
270 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
273 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
275 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
278 if (!TM.Options.UseSoftFloat) {
279 // SSE has no i16 to fp conversion, only i32
280 if (X86ScalarSSEf32) {
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 // f32 and f64 cases are Legal, f80 case is not
283 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
289 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
290 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
293 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
294 // are Legal, f80 is custom lowered.
295 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
296 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
298 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
300 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
303 if (X86ScalarSSEf32) {
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
305 // f32 and f64 cases are Legal, f80 case is not
306 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
309 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
312 // Handle FP_TO_UINT by promoting the destination to a larger signed
314 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
315 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
316 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
318 if (Subtarget->is64Bit()) {
319 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
320 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
321 } else if (!TM.Options.UseSoftFloat) {
322 // Since AVX is a superset of SSE3, only check for SSE here.
323 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
324 // Expand FP_TO_UINT into a select.
325 // FIXME: We would like to use a Custom expander here eventually to do
326 // the optimal thing for SSE vs. the default expansion in the legalizer.
327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
329 // With SSE3 we can use fisttpll to convert to a signed i64; without
330 // SSE, we're stuck with a fistpll.
331 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
334 if (isTargetFTOL()) {
335 // Use the _ftol2 runtime function, which has a pseudo-instruction
336 // to handle its weird calling convention.
337 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
340 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
341 if (!X86ScalarSSEf64) {
342 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
343 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
344 if (Subtarget->is64Bit()) {
345 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
346 // Without SSE, i64->f64 goes through memory.
347 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
351 // Scalar integer divide and remainder are lowered to use operations that
352 // produce two results, to match the available instructions. This exposes
353 // the two-result form to trivial CSE, which is able to combine x/y and x%y
354 // into a single instruction.
356 // Scalar integer multiply-high is also lowered to use two-result
357 // operations, to match the available instructions. However, plain multiply
358 // (low) operations are left as Legal, as there are single-result
359 // instructions for this in x86. Using the two-result multiply instructions
360 // when both high and low results are needed must be arranged by dagcombine.
361 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
363 setOperationAction(ISD::MULHS, VT, Expand);
364 setOperationAction(ISD::MULHU, VT, Expand);
365 setOperationAction(ISD::SDIV, VT, Expand);
366 setOperationAction(ISD::UDIV, VT, Expand);
367 setOperationAction(ISD::SREM, VT, Expand);
368 setOperationAction(ISD::UREM, VT, Expand);
370 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
371 setOperationAction(ISD::ADDC, VT, Custom);
372 setOperationAction(ISD::ADDE, VT, Custom);
373 setOperationAction(ISD::SUBC, VT, Custom);
374 setOperationAction(ISD::SUBE, VT, Custom);
377 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
378 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
379 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
380 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
381 if (Subtarget->is64Bit())
382 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
383 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
384 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
386 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
387 setOperationAction(ISD::FREM , MVT::f32 , Expand);
388 setOperationAction(ISD::FREM , MVT::f64 , Expand);
389 setOperationAction(ISD::FREM , MVT::f80 , Expand);
390 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
392 // Promote the i8 variants and force them on up to i32 which has a shorter
394 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
395 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
396 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
397 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
398 if (Subtarget->hasBMI()) {
399 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
400 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
401 if (Subtarget->is64Bit())
402 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
404 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
405 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
406 if (Subtarget->is64Bit())
407 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
410 if (Subtarget->hasLZCNT()) {
411 // When promoting the i8 variants, force them to i32 for a shorter
413 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
414 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
415 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
416 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
419 if (Subtarget->is64Bit())
420 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
422 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
423 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
424 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
425 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
426 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
427 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
428 if (Subtarget->is64Bit()) {
429 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
430 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
434 if (Subtarget->hasPOPCNT()) {
435 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
437 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
438 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
439 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
440 if (Subtarget->is64Bit())
441 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
444 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
445 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
447 // These should be promoted to a larger select which is supported.
448 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
449 // X86 wants to expand cmov itself.
450 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
451 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
452 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
453 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
454 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
455 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
456 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
457 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
458 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
459 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
460 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
461 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
464 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
466 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
469 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
470 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
471 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
472 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
475 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
476 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
479 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
480 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
481 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
482 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
484 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
485 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
486 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
487 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
488 if (Subtarget->is64Bit()) {
489 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
490 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
491 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
494 if (Subtarget->hasSSE1())
495 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
497 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
498 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
500 // On X86 and X86-64, atomic operations are lowered to locked instructions.
501 // Locked instructions, in turn, have implicit fence semantics (all memory
502 // operations are flushed before issuing the locked instruction, and they
503 // are not buffered), so we can fold away the common pattern of
504 // fence-atomic-fence.
505 setShouldFoldAtomicFences(true);
507 // Expand certain atomics
508 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
512 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
515 if (!Subtarget->is64Bit()) {
516 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
517 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
518 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
519 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
520 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
521 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
522 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
523 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
526 if (Subtarget->hasCmpxchg16b()) {
527 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
530 // FIXME - use subtarget debug flags
531 if (!Subtarget->isTargetDarwin() &&
532 !Subtarget->isTargetELF() &&
533 !Subtarget->isTargetCygMing()) {
534 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
537 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
538 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
539 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
540 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
541 if (Subtarget->is64Bit()) {
542 setExceptionPointerRegister(X86::RAX);
543 setExceptionSelectorRegister(X86::RDX);
545 setExceptionPointerRegister(X86::EAX);
546 setExceptionSelectorRegister(X86::EDX);
548 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
549 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
551 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
552 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
554 setOperationAction(ISD::TRAP, MVT::Other, Legal);
556 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
557 setOperationAction(ISD::VASTART , MVT::Other, Custom);
558 setOperationAction(ISD::VAEND , MVT::Other, Expand);
559 if (Subtarget->is64Bit()) {
560 setOperationAction(ISD::VAARG , MVT::Other, Custom);
561 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
563 setOperationAction(ISD::VAARG , MVT::Other, Expand);
564 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
567 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
568 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
570 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
571 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
572 MVT::i64 : MVT::i32, Custom);
573 else if (TM.Options.EnableSegmentedStacks)
574 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
575 MVT::i64 : MVT::i32, Custom);
577 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
578 MVT::i64 : MVT::i32, Expand);
580 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
581 // f32 and f64 use SSE.
582 // Set up the FP register classes.
583 addRegisterClass(MVT::f32, &X86::FR32RegClass);
584 addRegisterClass(MVT::f64, &X86::FR64RegClass);
586 // Use ANDPD to simulate FABS.
587 setOperationAction(ISD::FABS , MVT::f64, Custom);
588 setOperationAction(ISD::FABS , MVT::f32, Custom);
590 // Use XORP to simulate FNEG.
591 setOperationAction(ISD::FNEG , MVT::f64, Custom);
592 setOperationAction(ISD::FNEG , MVT::f32, Custom);
594 // Use ANDPD and ORPD to simulate FCOPYSIGN.
595 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
598 // Lower this to FGETSIGNx86 plus an AND.
599 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
600 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
602 // We don't support sin/cos/fmod
603 setOperationAction(ISD::FSIN , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f64, Expand);
605 setOperationAction(ISD::FSIN , MVT::f32, Expand);
606 setOperationAction(ISD::FCOS , MVT::f32, Expand);
608 // Expand FP immediates into loads from the stack, except for the special
610 addLegalFPImmediate(APFloat(+0.0)); // xorpd
611 addLegalFPImmediate(APFloat(+0.0f)); // xorps
612 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
613 // Use SSE for f32, x87 for f64.
614 // Set up the FP register classes.
615 addRegisterClass(MVT::f32, &X86::FR32RegClass);
616 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
618 // Use ANDPS to simulate FABS.
619 setOperationAction(ISD::FABS , MVT::f32, Custom);
621 // Use XORP to simulate FNEG.
622 setOperationAction(ISD::FNEG , MVT::f32, Custom);
624 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
626 // Use ANDPS and ORPS to simulate FCOPYSIGN.
627 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
628 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
630 // We don't support sin/cos/fmod
631 setOperationAction(ISD::FSIN , MVT::f32, Expand);
632 setOperationAction(ISD::FCOS , MVT::f32, Expand);
634 // Special cases we handle for FP constants.
635 addLegalFPImmediate(APFloat(+0.0f)); // xorps
636 addLegalFPImmediate(APFloat(+0.0)); // FLD0
637 addLegalFPImmediate(APFloat(+1.0)); // FLD1
638 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
639 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
643 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
645 } else if (!TM.Options.UseSoftFloat) {
646 // f32 and f64 in x87.
647 // Set up the FP register classes.
648 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
649 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
651 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
652 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
653 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
654 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
656 if (!TM.Options.UnsafeFPMath) {
657 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
658 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
660 addLegalFPImmediate(APFloat(+0.0)); // FLD0
661 addLegalFPImmediate(APFloat(+1.0)); // FLD1
662 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
663 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
664 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
665 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
666 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
667 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
670 // We don't support FMA.
671 setOperationAction(ISD::FMA, MVT::f64, Expand);
672 setOperationAction(ISD::FMA, MVT::f32, Expand);
674 // Long double always uses X87.
675 if (!TM.Options.UseSoftFloat) {
676 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
677 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
678 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
680 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
681 addLegalFPImmediate(TmpFlt); // FLD0
683 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
686 APFloat TmpFlt2(+1.0);
687 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
689 addLegalFPImmediate(TmpFlt2); // FLD1
690 TmpFlt2.changeSign();
691 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
694 if (!TM.Options.UnsafeFPMath) {
695 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
696 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
699 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
700 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
701 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
702 setOperationAction(ISD::FRINT, MVT::f80, Expand);
703 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
704 setOperationAction(ISD::FMA, MVT::f80, Expand);
707 // Always use a library call for pow.
708 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
709 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
710 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
712 setOperationAction(ISD::FLOG, MVT::f80, Expand);
713 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
714 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
715 setOperationAction(ISD::FEXP, MVT::f80, Expand);
716 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
718 // First set operation action for all vector types to either promote
719 // (for widening) or expand (for scalarization). Then we will selectively
720 // turn on ones that can be effectively codegen'd.
721 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
722 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
723 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
738 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
740 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
741 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
762 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
767 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
768 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
769 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
770 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
771 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
772 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
773 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
774 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
775 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
776 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
777 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
778 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
779 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
780 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
781 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
782 setTruncStoreAction((MVT::SimpleValueType)VT,
783 (MVT::SimpleValueType)InnerVT, Expand);
784 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
785 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
786 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
789 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
790 // with -msoft-float, disable use of MMX as well.
791 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
792 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
793 // No operations on x86mmx supported, everything uses intrinsics.
796 // MMX-sized vectors (other than x86mmx) are expected to be expanded
797 // into smaller operations.
798 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
799 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
800 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
801 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
802 setOperationAction(ISD::AND, MVT::v8i8, Expand);
803 setOperationAction(ISD::AND, MVT::v4i16, Expand);
804 setOperationAction(ISD::AND, MVT::v2i32, Expand);
805 setOperationAction(ISD::AND, MVT::v1i64, Expand);
806 setOperationAction(ISD::OR, MVT::v8i8, Expand);
807 setOperationAction(ISD::OR, MVT::v4i16, Expand);
808 setOperationAction(ISD::OR, MVT::v2i32, Expand);
809 setOperationAction(ISD::OR, MVT::v1i64, Expand);
810 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
811 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
812 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
813 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
814 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
815 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
816 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
817 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
818 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
819 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
820 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
821 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
822 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
823 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
824 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
825 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
826 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
828 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
829 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
831 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
832 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
833 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
834 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
835 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
836 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
837 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
838 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
839 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
840 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
841 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
845 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
846 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
848 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
849 // registers cannot be used even for integer operations.
850 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
851 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
852 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
853 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
855 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
856 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
857 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
858 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
859 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
860 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
861 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
862 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
863 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
864 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
865 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
866 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
867 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
868 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
869 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
870 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
872 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
873 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
874 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
875 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
877 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
878 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
879 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
880 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
883 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
884 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
885 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
886 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
887 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
889 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
890 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
891 EVT VT = (MVT::SimpleValueType)i;
892 // Do not attempt to custom lower non-power-of-2 vectors
893 if (!isPowerOf2_32(VT.getVectorNumElements()))
895 // Do not attempt to custom lower non-128-bit vectors
896 if (!VT.is128BitVector())
898 setOperationAction(ISD::BUILD_VECTOR,
899 VT.getSimpleVT().SimpleTy, Custom);
900 setOperationAction(ISD::VECTOR_SHUFFLE,
901 VT.getSimpleVT().SimpleTy, Custom);
902 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
903 VT.getSimpleVT().SimpleTy, Custom);
906 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
907 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
908 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
909 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
910 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
911 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
913 if (Subtarget->is64Bit()) {
914 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
915 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
918 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
919 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
920 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
923 // Do not attempt to promote non-128-bit vectors
924 if (!VT.is128BitVector())
927 setOperationAction(ISD::AND, SVT, Promote);
928 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
929 setOperationAction(ISD::OR, SVT, Promote);
930 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
931 setOperationAction(ISD::XOR, SVT, Promote);
932 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
933 setOperationAction(ISD::LOAD, SVT, Promote);
934 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
935 setOperationAction(ISD::SELECT, SVT, Promote);
936 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
939 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
941 // Custom lower v2i64 and v2f64 selects.
942 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
943 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
944 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
945 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
947 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
948 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
951 if (Subtarget->hasSSE41()) {
952 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
953 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
954 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
955 setOperationAction(ISD::FRINT, MVT::f32, Legal);
956 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
957 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
958 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
959 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
960 setOperationAction(ISD::FRINT, MVT::f64, Legal);
961 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
967 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
969 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
970 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
972 // i8 and i16 vectors are custom , because the source register and source
973 // source memory operand types are not the same width. f32 vectors are
974 // custom since the immediate controlling the insert encodes additional
976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
977 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
978 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
979 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
981 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
982 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
983 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
984 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
986 // FIXME: these should be Legal but thats only for the case where
987 // the index is constant. For now custom expand to deal with that.
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
994 if (Subtarget->hasSSE2()) {
995 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
996 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
998 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
999 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1001 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1002 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1004 if (Subtarget->hasAVX2()) {
1005 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1006 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1008 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1009 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1011 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1013 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1014 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1016 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1019 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1023 if (Subtarget->hasSSE42())
1024 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1026 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1027 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1028 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1029 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1030 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1031 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1032 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1034 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1035 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1036 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1038 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1045 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1046 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1047 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1048 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1049 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1052 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1053 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1054 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1056 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1057 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1058 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1059 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1060 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1061 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1063 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1064 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1066 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1067 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1069 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1070 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1072 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1073 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1074 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1075 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1077 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1078 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1079 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1081 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1083 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1084 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1086 if (Subtarget->hasAVX2()) {
1087 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1088 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1089 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1090 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1092 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1093 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1094 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1095 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1097 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1098 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1099 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1100 // Don't lower v32i8 because there is no 128-bit byte mul
1102 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1104 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1105 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1107 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1108 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1110 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1112 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1113 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1114 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1115 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1120 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1122 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1123 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1124 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1125 // Don't lower v32i8 because there is no 128-bit byte mul
1127 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1128 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1130 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1131 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1133 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1136 // Custom lower several nodes for 256-bit types.
1137 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1138 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1139 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1142 // Extract subvector is special because the value type
1143 // (result) is 128-bit but the source is 256-bit wide.
1144 if (VT.is128BitVector())
1145 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1147 // Do not attempt to custom lower other non-256-bit vectors
1148 if (!VT.is256BitVector())
1151 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1152 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1153 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1154 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1155 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1156 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1159 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1160 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1161 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1164 // Do not attempt to promote non-256-bit vectors
1165 if (!VT.is256BitVector())
1168 setOperationAction(ISD::AND, SVT, Promote);
1169 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1170 setOperationAction(ISD::OR, SVT, Promote);
1171 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1172 setOperationAction(ISD::XOR, SVT, Promote);
1173 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1174 setOperationAction(ISD::LOAD, SVT, Promote);
1175 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1176 setOperationAction(ISD::SELECT, SVT, Promote);
1177 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1181 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1182 // of this type with custom code.
1183 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1184 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1185 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1189 // We want to custom lower some of our intrinsics.
1190 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1193 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1194 // handle type legalization for these operations here.
1196 // FIXME: We really should do custom legalization for addition and
1197 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1198 // than generic legalization for 64-bit multiplication-with-overflow, though.
1199 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1200 // Add/Sub/Mul with overflow operations are custom lowered.
1202 setOperationAction(ISD::SADDO, VT, Custom);
1203 setOperationAction(ISD::UADDO, VT, Custom);
1204 setOperationAction(ISD::SSUBO, VT, Custom);
1205 setOperationAction(ISD::USUBO, VT, Custom);
1206 setOperationAction(ISD::SMULO, VT, Custom);
1207 setOperationAction(ISD::UMULO, VT, Custom);
1210 // There are no 8-bit 3-address imul/mul instructions
1211 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1212 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1214 if (!Subtarget->is64Bit()) {
1215 // These libcalls are not available in 32-bit.
1216 setLibcallName(RTLIB::SHL_I128, 0);
1217 setLibcallName(RTLIB::SRL_I128, 0);
1218 setLibcallName(RTLIB::SRA_I128, 0);
1221 // We have target-specific dag combine patterns for the following nodes:
1222 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1223 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1224 setTargetDAGCombine(ISD::VSELECT);
1225 setTargetDAGCombine(ISD::SELECT);
1226 setTargetDAGCombine(ISD::SHL);
1227 setTargetDAGCombine(ISD::SRA);
1228 setTargetDAGCombine(ISD::SRL);
1229 setTargetDAGCombine(ISD::OR);
1230 setTargetDAGCombine(ISD::AND);
1231 setTargetDAGCombine(ISD::ADD);
1232 setTargetDAGCombine(ISD::FADD);
1233 setTargetDAGCombine(ISD::FSUB);
1234 setTargetDAGCombine(ISD::SUB);
1235 setTargetDAGCombine(ISD::LOAD);
1236 setTargetDAGCombine(ISD::STORE);
1237 setTargetDAGCombine(ISD::ZERO_EXTEND);
1238 setTargetDAGCombine(ISD::ANY_EXTEND);
1239 setTargetDAGCombine(ISD::SIGN_EXTEND);
1240 setTargetDAGCombine(ISD::TRUNCATE);
1241 setTargetDAGCombine(ISD::SINT_TO_FP);
1242 if (Subtarget->is64Bit())
1243 setTargetDAGCombine(ISD::MUL);
1244 if (Subtarget->hasBMI())
1245 setTargetDAGCombine(ISD::XOR);
1247 computeRegisterProperties();
1249 // On Darwin, -Os means optimize for size without hurting performance,
1250 // do not reduce the limit.
1251 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1252 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1253 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1254 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1255 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1256 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1257 setPrefLoopAlignment(4); // 2^4 bytes.
1258 benefitFromCodePlacementOpt = true;
1260 setPrefFunctionAlignment(4); // 2^4 bytes.
1264 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1265 if (!VT.isVector()) return MVT::i8;
1266 return VT.changeVectorElementTypeToInteger();
1270 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1271 /// the desired ByVal argument alignment.
1272 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1275 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1276 if (VTy->getBitWidth() == 128)
1278 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1279 unsigned EltAlign = 0;
1280 getMaxByValAlign(ATy->getElementType(), EltAlign);
1281 if (EltAlign > MaxAlign)
1282 MaxAlign = EltAlign;
1283 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1284 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1285 unsigned EltAlign = 0;
1286 getMaxByValAlign(STy->getElementType(i), EltAlign);
1287 if (EltAlign > MaxAlign)
1288 MaxAlign = EltAlign;
1296 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1297 /// function arguments in the caller parameter area. For X86, aggregates
1298 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1299 /// are at 4-byte boundaries.
1300 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1301 if (Subtarget->is64Bit()) {
1302 // Max of 8 and alignment of type.
1303 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1310 if (Subtarget->hasSSE1())
1311 getMaxByValAlign(Ty, Align);
1315 /// getOptimalMemOpType - Returns the target specific optimal type for load
1316 /// and store operations as a result of memset, memcpy, and memmove
1317 /// lowering. If DstAlign is zero that means it's safe to destination
1318 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1319 /// means there isn't a need to check it against alignment requirement,
1320 /// probably because the source does not need to be loaded. If
1321 /// 'IsZeroVal' is true, that means it's safe to return a
1322 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1323 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1324 /// constant so it does not need to be loaded.
1325 /// It returns EVT::Other if the type should be determined using generic
1326 /// target-independent logic.
1328 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1329 unsigned DstAlign, unsigned SrcAlign,
1332 MachineFunction &MF) const {
1333 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1334 // linux. This is because the stack realignment code can't handle certain
1335 // cases like PR2962. This should be removed when PR2962 is fixed.
1336 const Function *F = MF.getFunction();
1338 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1340 (Subtarget->isUnalignedMemAccessFast() ||
1341 ((DstAlign == 0 || DstAlign >= 16) &&
1342 (SrcAlign == 0 || SrcAlign >= 16))) &&
1343 Subtarget->getStackAlignment() >= 16) {
1344 if (Subtarget->getStackAlignment() >= 32) {
1345 if (Subtarget->hasAVX2())
1347 if (Subtarget->hasAVX())
1350 if (Subtarget->hasSSE2())
1352 if (Subtarget->hasSSE1())
1354 } else if (!MemcpyStrSrc && Size >= 8 &&
1355 !Subtarget->is64Bit() &&
1356 Subtarget->getStackAlignment() >= 8 &&
1357 Subtarget->hasSSE2()) {
1358 // Do not use f64 to lower memcpy if source is string constant. It's
1359 // better to use i32 to avoid the loads.
1363 if (Subtarget->is64Bit() && Size >= 8)
1368 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1369 /// current function. The returned value is a member of the
1370 /// MachineJumpTableInfo::JTEntryKind enum.
1371 unsigned X86TargetLowering::getJumpTableEncoding() const {
1372 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1374 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1375 Subtarget->isPICStyleGOT())
1376 return MachineJumpTableInfo::EK_Custom32;
1378 // Otherwise, use the normal jump table encoding heuristics.
1379 return TargetLowering::getJumpTableEncoding();
1383 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1384 const MachineBasicBlock *MBB,
1385 unsigned uid,MCContext &Ctx) const{
1386 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1387 Subtarget->isPICStyleGOT());
1388 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1390 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1391 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1394 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1396 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1397 SelectionDAG &DAG) const {
1398 if (!Subtarget->is64Bit())
1399 // This doesn't have DebugLoc associated with it, but is not really the
1400 // same as a Register.
1401 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1405 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1406 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1408 const MCExpr *X86TargetLowering::
1409 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1410 MCContext &Ctx) const {
1411 // X86-64 uses RIP relative addressing based on the jump table label.
1412 if (Subtarget->isPICStyleRIPRel())
1413 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1415 // Otherwise, the reference is relative to the PIC base.
1416 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1419 // FIXME: Why this routine is here? Move to RegInfo!
1420 std::pair<const TargetRegisterClass*, uint8_t>
1421 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1422 const TargetRegisterClass *RRC = 0;
1424 switch (VT.getSimpleVT().SimpleTy) {
1426 return TargetLowering::findRepresentativeClass(VT);
1427 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1428 RRC = Subtarget->is64Bit() ?
1429 (const TargetRegisterClass*)&X86::GR64RegClass :
1430 (const TargetRegisterClass*)&X86::GR32RegClass;
1433 RRC = &X86::VR64RegClass;
1435 case MVT::f32: case MVT::f64:
1436 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1437 case MVT::v4f32: case MVT::v2f64:
1438 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1440 RRC = &X86::VR128RegClass;
1443 return std::make_pair(RRC, Cost);
1446 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1447 unsigned &Offset) const {
1448 if (!Subtarget->isTargetLinux())
1451 if (Subtarget->is64Bit()) {
1452 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1454 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1467 //===----------------------------------------------------------------------===//
1468 // Return Value Calling Convention Implementation
1469 //===----------------------------------------------------------------------===//
1471 #include "X86GenCallingConv.inc"
1474 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1475 MachineFunction &MF, bool isVarArg,
1476 const SmallVectorImpl<ISD::OutputArg> &Outs,
1477 LLVMContext &Context) const {
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1481 return CCInfo.CheckReturn(Outs, RetCC_X86);
1485 X86TargetLowering::LowerReturn(SDValue Chain,
1486 CallingConv::ID CallConv, bool isVarArg,
1487 const SmallVectorImpl<ISD::OutputArg> &Outs,
1488 const SmallVectorImpl<SDValue> &OutVals,
1489 DebugLoc dl, SelectionDAG &DAG) const {
1490 MachineFunction &MF = DAG.getMachineFunction();
1491 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1493 SmallVector<CCValAssign, 16> RVLocs;
1494 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1495 RVLocs, *DAG.getContext());
1496 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1498 // Add the regs to the liveout set for the function.
1499 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1500 for (unsigned i = 0; i != RVLocs.size(); ++i)
1501 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1502 MRI.addLiveOut(RVLocs[i].getLocReg());
1506 SmallVector<SDValue, 6> RetOps;
1507 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1508 // Operand #1 = Bytes To Pop
1509 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1512 // Copy the result values into the output registers.
1513 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1514 CCValAssign &VA = RVLocs[i];
1515 assert(VA.isRegLoc() && "Can only return in registers!");
1516 SDValue ValToCopy = OutVals[i];
1517 EVT ValVT = ValToCopy.getValueType();
1519 // If this is x86-64, and we disabled SSE, we can't return FP values,
1520 // or SSE or MMX vectors.
1521 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1522 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1523 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1524 report_fatal_error("SSE register return with SSE disabled");
1526 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1527 // llvm-gcc has never done it right and no one has noticed, so this
1528 // should be OK for now.
1529 if (ValVT == MVT::f64 &&
1530 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1531 report_fatal_error("SSE2 register return with SSE2 disabled");
1533 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1534 // the RET instruction and handled by the FP Stackifier.
1535 if (VA.getLocReg() == X86::ST0 ||
1536 VA.getLocReg() == X86::ST1) {
1537 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1538 // change the value to the FP stack register class.
1539 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1540 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1541 RetOps.push_back(ValToCopy);
1542 // Don't emit a copytoreg.
1546 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1547 // which is returned in RAX / RDX.
1548 if (Subtarget->is64Bit()) {
1549 if (ValVT == MVT::x86mmx) {
1550 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1551 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1552 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1554 // If we don't have SSE2 available, convert to v4f32 so the generated
1555 // register is legal.
1556 if (!Subtarget->hasSSE2())
1557 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1562 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1563 Flag = Chain.getValue(1);
1566 // The x86-64 ABI for returning structs by value requires that we copy
1567 // the sret argument into %rax for the return. We saved the argument into
1568 // a virtual register in the entry block, so now we copy the value out
1570 if (Subtarget->is64Bit() &&
1571 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1572 MachineFunction &MF = DAG.getMachineFunction();
1573 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1574 unsigned Reg = FuncInfo->getSRetReturnReg();
1576 "SRetReturnReg should have been set in LowerFormalArguments().");
1577 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1579 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1580 Flag = Chain.getValue(1);
1582 // RAX now acts like a return value.
1583 MRI.addLiveOut(X86::RAX);
1586 RetOps[0] = Chain; // Update chain.
1588 // Add the flag if we have it.
1590 RetOps.push_back(Flag);
1592 return DAG.getNode(X86ISD::RET_FLAG, dl,
1593 MVT::Other, &RetOps[0], RetOps.size());
1596 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1597 if (N->getNumValues() != 1)
1599 if (!N->hasNUsesOfValue(1, 0))
1602 SDValue TCChain = Chain;
1603 SDNode *Copy = *N->use_begin();
1604 if (Copy->getOpcode() == ISD::CopyToReg) {
1605 // If the copy has a glue operand, we conservatively assume it isn't safe to
1606 // perform a tail call.
1607 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1609 TCChain = Copy->getOperand(0);
1610 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1613 bool HasRet = false;
1614 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1616 if (UI->getOpcode() != X86ISD::RET_FLAG)
1629 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1630 ISD::NodeType ExtendKind) const {
1632 // TODO: Is this also valid on 32-bit?
1633 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1634 ReturnMVT = MVT::i8;
1636 ReturnMVT = MVT::i32;
1638 EVT MinVT = getRegisterType(Context, ReturnMVT);
1639 return VT.bitsLT(MinVT) ? MinVT : VT;
1642 /// LowerCallResult - Lower the result values of a call into the
1643 /// appropriate copies out of appropriate physical registers.
1646 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1647 CallingConv::ID CallConv, bool isVarArg,
1648 const SmallVectorImpl<ISD::InputArg> &Ins,
1649 DebugLoc dl, SelectionDAG &DAG,
1650 SmallVectorImpl<SDValue> &InVals) const {
1652 // Assign locations to each value returned by this call.
1653 SmallVector<CCValAssign, 16> RVLocs;
1654 bool Is64Bit = Subtarget->is64Bit();
1655 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1656 getTargetMachine(), RVLocs, *DAG.getContext());
1657 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1659 // Copy all of the result registers out of their specified physreg.
1660 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1661 CCValAssign &VA = RVLocs[i];
1662 EVT CopyVT = VA.getValVT();
1664 // If this is x86-64, and we disabled SSE, we can't return FP values
1665 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1666 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1667 report_fatal_error("SSE register return with SSE disabled");
1672 // If this is a call to a function that returns an fp value on the floating
1673 // point stack, we must guarantee the the value is popped from the stack, so
1674 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1675 // if the return value is not used. We use the FpPOP_RETVAL instruction
1677 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1678 // If we prefer to use the value in xmm registers, copy it out as f80 and
1679 // use a truncate to move it from fp stack reg to xmm reg.
1680 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1681 SDValue Ops[] = { Chain, InFlag };
1682 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1683 MVT::Other, MVT::Glue, Ops, 2), 1);
1684 Val = Chain.getValue(0);
1686 // Round the f80 to the right size, which also moves it to the appropriate
1688 if (CopyVT != VA.getValVT())
1689 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1690 // This truncation won't change the value.
1691 DAG.getIntPtrConstant(1));
1693 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1694 CopyVT, InFlag).getValue(1);
1695 Val = Chain.getValue(0);
1697 InFlag = Chain.getValue(2);
1698 InVals.push_back(Val);
1705 //===----------------------------------------------------------------------===//
1706 // C & StdCall & Fast Calling Convention implementation
1707 //===----------------------------------------------------------------------===//
1708 // StdCall calling convention seems to be standard for many Windows' API
1709 // routines and around. It differs from C calling convention just a little:
1710 // callee should clean up the stack, not caller. Symbols should be also
1711 // decorated in some fancy way :) It doesn't support any vector arguments.
1712 // For info on fast calling convention see Fast Calling Convention (tail call)
1713 // implementation LowerX86_32FastCCCallTo.
1715 /// CallIsStructReturn - Determines whether a call uses struct return
1717 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1721 return Outs[0].Flags.isSRet();
1724 /// ArgsAreStructReturn - Determines whether a function uses struct
1725 /// return semantics.
1727 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1731 return Ins[0].Flags.isSRet();
1734 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1735 /// by "Src" to address "Dst" with size and alignment information specified by
1736 /// the specific parameter attribute. The copy will be passed as a byval
1737 /// function parameter.
1739 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1740 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1742 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1744 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1745 /*isVolatile*/false, /*AlwaysInline=*/true,
1746 MachinePointerInfo(), MachinePointerInfo());
1749 /// IsTailCallConvention - Return true if the calling convention is one that
1750 /// supports tail call optimization.
1751 static bool IsTailCallConvention(CallingConv::ID CC) {
1752 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1755 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1756 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1760 CallingConv::ID CalleeCC = CS.getCallingConv();
1761 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1767 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1768 /// a tailcall target by changing its ABI.
1769 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1770 bool GuaranteedTailCallOpt) {
1771 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1775 X86TargetLowering::LowerMemArgument(SDValue Chain,
1776 CallingConv::ID CallConv,
1777 const SmallVectorImpl<ISD::InputArg> &Ins,
1778 DebugLoc dl, SelectionDAG &DAG,
1779 const CCValAssign &VA,
1780 MachineFrameInfo *MFI,
1782 // Create the nodes corresponding to a load from this parameter slot.
1783 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1784 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1785 getTargetMachine().Options.GuaranteedTailCallOpt);
1786 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1789 // If value is passed by pointer we have address passed instead of the value
1791 if (VA.getLocInfo() == CCValAssign::Indirect)
1792 ValVT = VA.getLocVT();
1794 ValVT = VA.getValVT();
1796 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1797 // changed with more analysis.
1798 // In case of tail call optimization mark all arguments mutable. Since they
1799 // could be overwritten by lowering of arguments in case of a tail call.
1800 if (Flags.isByVal()) {
1801 unsigned Bytes = Flags.getByValSize();
1802 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1803 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1804 return DAG.getFrameIndex(FI, getPointerTy());
1806 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1807 VA.getLocMemOffset(), isImmutable);
1808 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1809 return DAG.getLoad(ValVT, dl, Chain, FIN,
1810 MachinePointerInfo::getFixedStack(FI),
1811 false, false, false, 0);
1816 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1817 CallingConv::ID CallConv,
1819 const SmallVectorImpl<ISD::InputArg> &Ins,
1822 SmallVectorImpl<SDValue> &InVals)
1824 MachineFunction &MF = DAG.getMachineFunction();
1825 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1827 const Function* Fn = MF.getFunction();
1828 if (Fn->hasExternalLinkage() &&
1829 Subtarget->isTargetCygMing() &&
1830 Fn->getName() == "main")
1831 FuncInfo->setForceFramePointer(true);
1833 MachineFrameInfo *MFI = MF.getFrameInfo();
1834 bool Is64Bit = Subtarget->is64Bit();
1835 bool IsWindows = Subtarget->isTargetWindows();
1836 bool IsWin64 = Subtarget->isTargetWin64();
1838 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1839 "Var args not supported with calling convention fastcc or ghc");
1841 // Assign locations to all of the incoming arguments.
1842 SmallVector<CCValAssign, 16> ArgLocs;
1843 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1844 ArgLocs, *DAG.getContext());
1846 // Allocate shadow area for Win64
1848 CCInfo.AllocateStack(32, 8);
1851 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1853 unsigned LastVal = ~0U;
1855 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1856 CCValAssign &VA = ArgLocs[i];
1857 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1859 assert(VA.getValNo() != LastVal &&
1860 "Don't support value assigned to multiple locs yet");
1862 LastVal = VA.getValNo();
1864 if (VA.isRegLoc()) {
1865 EVT RegVT = VA.getLocVT();
1866 const TargetRegisterClass *RC;
1867 if (RegVT == MVT::i32)
1868 RC = &X86::GR32RegClass;
1869 else if (Is64Bit && RegVT == MVT::i64)
1870 RC = &X86::GR64RegClass;
1871 else if (RegVT == MVT::f32)
1872 RC = &X86::FR32RegClass;
1873 else if (RegVT == MVT::f64)
1874 RC = &X86::FR64RegClass;
1875 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1876 RC = &X86::VR256RegClass;
1877 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1878 RC = &X86::VR128RegClass;
1879 else if (RegVT == MVT::x86mmx)
1880 RC = &X86::VR64RegClass;
1882 llvm_unreachable("Unknown argument type!");
1884 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1885 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1887 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1888 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1890 if (VA.getLocInfo() == CCValAssign::SExt)
1891 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1892 DAG.getValueType(VA.getValVT()));
1893 else if (VA.getLocInfo() == CCValAssign::ZExt)
1894 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1895 DAG.getValueType(VA.getValVT()));
1896 else if (VA.getLocInfo() == CCValAssign::BCvt)
1897 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1899 if (VA.isExtInLoc()) {
1900 // Handle MMX values passed in XMM regs.
1901 if (RegVT.isVector()) {
1902 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1905 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1908 assert(VA.isMemLoc());
1909 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1912 // If value is passed via pointer - do a load.
1913 if (VA.getLocInfo() == CCValAssign::Indirect)
1914 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1915 MachinePointerInfo(), false, false, false, 0);
1917 InVals.push_back(ArgValue);
1920 // The x86-64 ABI for returning structs by value requires that we copy
1921 // the sret argument into %rax for the return. Save the argument into
1922 // a virtual register so that we can access it from the return points.
1923 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1924 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1925 unsigned Reg = FuncInfo->getSRetReturnReg();
1927 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1928 FuncInfo->setSRetReturnReg(Reg);
1930 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1931 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1934 unsigned StackSize = CCInfo.getNextStackOffset();
1935 // Align stack specially for tail calls.
1936 if (FuncIsMadeTailCallSafe(CallConv,
1937 MF.getTarget().Options.GuaranteedTailCallOpt))
1938 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1940 // If the function takes variable number of arguments, make a frame index for
1941 // the start of the first vararg value... for expansion of llvm.va_start.
1943 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1944 CallConv != CallingConv::X86_ThisCall)) {
1945 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1948 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1950 // FIXME: We should really autogenerate these arrays
1951 static const uint16_t GPR64ArgRegsWin64[] = {
1952 X86::RCX, X86::RDX, X86::R8, X86::R9
1954 static const uint16_t GPR64ArgRegs64Bit[] = {
1955 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1957 static const uint16_t XMMArgRegs64Bit[] = {
1958 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1959 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1961 const uint16_t *GPR64ArgRegs;
1962 unsigned NumXMMRegs = 0;
1965 // The XMM registers which might contain var arg parameters are shadowed
1966 // in their paired GPR. So we only need to save the GPR to their home
1968 TotalNumIntRegs = 4;
1969 GPR64ArgRegs = GPR64ArgRegsWin64;
1971 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1972 GPR64ArgRegs = GPR64ArgRegs64Bit;
1974 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1977 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1980 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1981 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1982 "SSE register cannot be used when SSE is disabled!");
1983 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1984 NoImplicitFloatOps) &&
1985 "SSE register cannot be used when SSE is disabled!");
1986 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1987 !Subtarget->hasSSE1())
1988 // Kernel mode asks for SSE to be disabled, so don't push them
1990 TotalNumXMMRegs = 0;
1993 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1994 // Get to the caller-allocated home save location. Add 8 to account
1995 // for the return address.
1996 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1997 FuncInfo->setRegSaveFrameIndex(
1998 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1999 // Fixup to set vararg frame on shadow area (4 x i64).
2001 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2003 // For X86-64, if there are vararg parameters that are passed via
2004 // registers, then we must store them to their spots on the stack so
2005 // they may be loaded by deferencing the result of va_next.
2006 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2007 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2008 FuncInfo->setRegSaveFrameIndex(
2009 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2013 // Store the integer parameter registers.
2014 SmallVector<SDValue, 8> MemOps;
2015 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2017 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2018 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2019 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2020 DAG.getIntPtrConstant(Offset));
2021 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2022 &X86::GR64RegClass);
2023 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2025 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2026 MachinePointerInfo::getFixedStack(
2027 FuncInfo->getRegSaveFrameIndex(), Offset),
2029 MemOps.push_back(Store);
2033 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2034 // Now store the XMM (fp + vector) parameter registers.
2035 SmallVector<SDValue, 11> SaveXMMOps;
2036 SaveXMMOps.push_back(Chain);
2038 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2039 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2040 SaveXMMOps.push_back(ALVal);
2042 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2043 FuncInfo->getRegSaveFrameIndex()));
2044 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2045 FuncInfo->getVarArgsFPOffset()));
2047 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2048 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2049 &X86::VR128RegClass);
2050 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2051 SaveXMMOps.push_back(Val);
2053 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2055 &SaveXMMOps[0], SaveXMMOps.size()));
2058 if (!MemOps.empty())
2059 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2060 &MemOps[0], MemOps.size());
2064 // Some CCs need callee pop.
2065 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2066 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2067 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2069 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2070 // If this is an sret function, the return should pop the hidden pointer.
2071 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2072 ArgsAreStructReturn(Ins))
2073 FuncInfo->setBytesToPopOnReturn(4);
2077 // RegSaveFrameIndex is X86-64 only.
2078 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2079 if (CallConv == CallingConv::X86_FastCall ||
2080 CallConv == CallingConv::X86_ThisCall)
2081 // fastcc functions can't have varargs.
2082 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2085 FuncInfo->setArgumentStackSize(StackSize);
2091 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2092 SDValue StackPtr, SDValue Arg,
2093 DebugLoc dl, SelectionDAG &DAG,
2094 const CCValAssign &VA,
2095 ISD::ArgFlagsTy Flags) const {
2096 unsigned LocMemOffset = VA.getLocMemOffset();
2097 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2098 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2099 if (Flags.isByVal())
2100 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2102 return DAG.getStore(Chain, dl, Arg, PtrOff,
2103 MachinePointerInfo::getStack(LocMemOffset),
2107 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2108 /// optimization is performed and it is required.
2110 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2111 SDValue &OutRetAddr, SDValue Chain,
2112 bool IsTailCall, bool Is64Bit,
2113 int FPDiff, DebugLoc dl) const {
2114 // Adjust the Return address stack slot.
2115 EVT VT = getPointerTy();
2116 OutRetAddr = getReturnAddressFrameIndex(DAG);
2118 // Load the "old" Return address.
2119 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2120 false, false, false, 0);
2121 return SDValue(OutRetAddr.getNode(), 1);
2124 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2125 /// optimization is performed and it is required (FPDiff!=0).
2127 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2128 SDValue Chain, SDValue RetAddrFrIdx,
2129 bool Is64Bit, int FPDiff, DebugLoc dl) {
2130 // Store the return address to the appropriate stack slot.
2131 if (!FPDiff) return Chain;
2132 // Calculate the new stack slot for the return address.
2133 int SlotSize = Is64Bit ? 8 : 4;
2134 int NewReturnAddrFI =
2135 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2136 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2137 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2138 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2139 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2145 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2146 CallingConv::ID CallConv, bool isVarArg,
2147 bool doesNotRet, bool &isTailCall,
2148 const SmallVectorImpl<ISD::OutputArg> &Outs,
2149 const SmallVectorImpl<SDValue> &OutVals,
2150 const SmallVectorImpl<ISD::InputArg> &Ins,
2151 DebugLoc dl, SelectionDAG &DAG,
2152 SmallVectorImpl<SDValue> &InVals) const {
2153 MachineFunction &MF = DAG.getMachineFunction();
2154 bool Is64Bit = Subtarget->is64Bit();
2155 bool IsWin64 = Subtarget->isTargetWin64();
2156 bool IsWindows = Subtarget->isTargetWindows();
2157 bool IsStructRet = CallIsStructReturn(Outs);
2158 bool IsSibcall = false;
2160 if (MF.getTarget().Options.DisableTailCalls)
2164 // Check if it's really possible to do a tail call.
2165 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2166 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2167 Outs, OutVals, Ins, DAG);
2169 // Sibcalls are automatically detected tailcalls which do not require
2171 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2178 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2179 "Var args not supported with calling convention fastcc or ghc");
2181 // Analyze operands of the call, assigning locations to each operand.
2182 SmallVector<CCValAssign, 16> ArgLocs;
2183 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2184 ArgLocs, *DAG.getContext());
2186 // Allocate shadow area for Win64
2188 CCInfo.AllocateStack(32, 8);
2191 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2193 // Get a count of how many bytes are to be pushed on the stack.
2194 unsigned NumBytes = CCInfo.getNextStackOffset();
2196 // This is a sibcall. The memory operands are available in caller's
2197 // own caller's stack.
2199 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2200 IsTailCallConvention(CallConv))
2201 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2204 if (isTailCall && !IsSibcall) {
2205 // Lower arguments at fp - stackoffset + fpdiff.
2206 unsigned NumBytesCallerPushed =
2207 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2208 FPDiff = NumBytesCallerPushed - NumBytes;
2210 // Set the delta of movement of the returnaddr stackslot.
2211 // But only set if delta is greater than previous delta.
2212 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2213 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2217 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2219 SDValue RetAddrFrIdx;
2220 // Load return address for tail calls.
2221 if (isTailCall && FPDiff)
2222 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2223 Is64Bit, FPDiff, dl);
2225 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2226 SmallVector<SDValue, 8> MemOpChains;
2229 // Walk the register/memloc assignments, inserting copies/loads. In the case
2230 // of tail call optimization arguments are handle later.
2231 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2232 CCValAssign &VA = ArgLocs[i];
2233 EVT RegVT = VA.getLocVT();
2234 SDValue Arg = OutVals[i];
2235 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2236 bool isByVal = Flags.isByVal();
2238 // Promote the value if needed.
2239 switch (VA.getLocInfo()) {
2240 default: llvm_unreachable("Unknown loc info!");
2241 case CCValAssign::Full: break;
2242 case CCValAssign::SExt:
2243 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2245 case CCValAssign::ZExt:
2246 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2248 case CCValAssign::AExt:
2249 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2250 // Special case: passing MMX values in XMM registers.
2251 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2252 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2253 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2255 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2257 case CCValAssign::BCvt:
2258 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2260 case CCValAssign::Indirect: {
2261 // Store the argument.
2262 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2263 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2264 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2265 MachinePointerInfo::getFixedStack(FI),
2272 if (VA.isRegLoc()) {
2273 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2274 if (isVarArg && IsWin64) {
2275 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2276 // shadow reg if callee is a varargs function.
2277 unsigned ShadowReg = 0;
2278 switch (VA.getLocReg()) {
2279 case X86::XMM0: ShadowReg = X86::RCX; break;
2280 case X86::XMM1: ShadowReg = X86::RDX; break;
2281 case X86::XMM2: ShadowReg = X86::R8; break;
2282 case X86::XMM3: ShadowReg = X86::R9; break;
2285 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2287 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2288 assert(VA.isMemLoc());
2289 if (StackPtr.getNode() == 0)
2290 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2291 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2292 dl, DAG, VA, Flags));
2296 if (!MemOpChains.empty())
2297 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2298 &MemOpChains[0], MemOpChains.size());
2300 // Build a sequence of copy-to-reg nodes chained together with token chain
2301 // and flag operands which copy the outgoing args into registers.
2303 // Tail call byval lowering might overwrite argument registers so in case of
2304 // tail call optimization the copies to registers are lowered later.
2306 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2307 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2308 RegsToPass[i].second, InFlag);
2309 InFlag = Chain.getValue(1);
2312 if (Subtarget->isPICStyleGOT()) {
2313 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2316 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2317 DAG.getNode(X86ISD::GlobalBaseReg,
2318 DebugLoc(), getPointerTy()),
2320 InFlag = Chain.getValue(1);
2322 // If we are tail calling and generating PIC/GOT style code load the
2323 // address of the callee into ECX. The value in ecx is used as target of
2324 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2325 // for tail calls on PIC/GOT architectures. Normally we would just put the
2326 // address of GOT into ebx and then call target@PLT. But for tail calls
2327 // ebx would be restored (since ebx is callee saved) before jumping to the
2330 // Note: The actual moving to ECX is done further down.
2331 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2332 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2333 !G->getGlobal()->hasProtectedVisibility())
2334 Callee = LowerGlobalAddress(Callee, DAG);
2335 else if (isa<ExternalSymbolSDNode>(Callee))
2336 Callee = LowerExternalSymbol(Callee, DAG);
2340 if (Is64Bit && isVarArg && !IsWin64) {
2341 // From AMD64 ABI document:
2342 // For calls that may call functions that use varargs or stdargs
2343 // (prototype-less calls or calls to functions containing ellipsis (...) in
2344 // the declaration) %al is used as hidden argument to specify the number
2345 // of SSE registers used. The contents of %al do not need to match exactly
2346 // the number of registers, but must be an ubound on the number of SSE
2347 // registers used and is in the range 0 - 8 inclusive.
2349 // Count the number of XMM registers allocated.
2350 static const uint16_t XMMArgRegs[] = {
2351 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2352 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2354 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2355 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2356 && "SSE registers cannot be used when SSE is disabled");
2358 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2359 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2360 InFlag = Chain.getValue(1);
2364 // For tail calls lower the arguments to the 'real' stack slot.
2366 // Force all the incoming stack arguments to be loaded from the stack
2367 // before any new outgoing arguments are stored to the stack, because the
2368 // outgoing stack slots may alias the incoming argument stack slots, and
2369 // the alias isn't otherwise explicit. This is slightly more conservative
2370 // than necessary, because it means that each store effectively depends
2371 // on every argument instead of just those arguments it would clobber.
2372 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2374 SmallVector<SDValue, 8> MemOpChains2;
2377 // Do not flag preceding copytoreg stuff together with the following stuff.
2379 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2380 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2381 CCValAssign &VA = ArgLocs[i];
2384 assert(VA.isMemLoc());
2385 SDValue Arg = OutVals[i];
2386 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2387 // Create frame index.
2388 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2389 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2390 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2391 FIN = DAG.getFrameIndex(FI, getPointerTy());
2393 if (Flags.isByVal()) {
2394 // Copy relative to framepointer.
2395 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2396 if (StackPtr.getNode() == 0)
2397 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2399 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2401 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2405 // Store relative to framepointer.
2406 MemOpChains2.push_back(
2407 DAG.getStore(ArgChain, dl, Arg, FIN,
2408 MachinePointerInfo::getFixedStack(FI),
2414 if (!MemOpChains2.empty())
2415 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2416 &MemOpChains2[0], MemOpChains2.size());
2418 // Copy arguments to their registers.
2419 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2420 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2421 RegsToPass[i].second, InFlag);
2422 InFlag = Chain.getValue(1);
2426 // Store the return address to the appropriate stack slot.
2427 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2431 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2432 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2433 // In the 64-bit large code model, we have to make all calls
2434 // through a register, since the call instruction's 32-bit
2435 // pc-relative offset may not be large enough to hold the whole
2437 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2438 // If the callee is a GlobalAddress node (quite common, every direct call
2439 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2442 // We should use extra load for direct calls to dllimported functions in
2444 const GlobalValue *GV = G->getGlobal();
2445 if (!GV->hasDLLImportLinkage()) {
2446 unsigned char OpFlags = 0;
2447 bool ExtraLoad = false;
2448 unsigned WrapperKind = ISD::DELETED_NODE;
2450 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2451 // external symbols most go through the PLT in PIC mode. If the symbol
2452 // has hidden or protected visibility, or if it is static or local, then
2453 // we don't need to use the PLT - we can directly call it.
2454 if (Subtarget->isTargetELF() &&
2455 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2456 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2457 OpFlags = X86II::MO_PLT;
2458 } else if (Subtarget->isPICStyleStubAny() &&
2459 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2460 (!Subtarget->getTargetTriple().isMacOSX() ||
2461 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2462 // PC-relative references to external symbols should go through $stub,
2463 // unless we're building with the leopard linker or later, which
2464 // automatically synthesizes these stubs.
2465 OpFlags = X86II::MO_DARWIN_STUB;
2466 } else if (Subtarget->isPICStyleRIPRel() &&
2467 isa<Function>(GV) &&
2468 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2469 // If the function is marked as non-lazy, generate an indirect call
2470 // which loads from the GOT directly. This avoids runtime overhead
2471 // at the cost of eager binding (and one extra byte of encoding).
2472 OpFlags = X86II::MO_GOTPCREL;
2473 WrapperKind = X86ISD::WrapperRIP;
2477 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2478 G->getOffset(), OpFlags);
2480 // Add a wrapper if needed.
2481 if (WrapperKind != ISD::DELETED_NODE)
2482 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2483 // Add extra indirection if needed.
2485 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2486 MachinePointerInfo::getGOT(),
2487 false, false, false, 0);
2489 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2490 unsigned char OpFlags = 0;
2492 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2493 // external symbols should go through the PLT.
2494 if (Subtarget->isTargetELF() &&
2495 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2496 OpFlags = X86II::MO_PLT;
2497 } else if (Subtarget->isPICStyleStubAny() &&
2498 (!Subtarget->getTargetTriple().isMacOSX() ||
2499 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2500 // PC-relative references to external symbols should go through $stub,
2501 // unless we're building with the leopard linker or later, which
2502 // automatically synthesizes these stubs.
2503 OpFlags = X86II::MO_DARWIN_STUB;
2506 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2510 // Returns a chain & a flag for retval copy to use.
2511 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2512 SmallVector<SDValue, 8> Ops;
2514 if (!IsSibcall && isTailCall) {
2515 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2516 DAG.getIntPtrConstant(0, true), InFlag);
2517 InFlag = Chain.getValue(1);
2520 Ops.push_back(Chain);
2521 Ops.push_back(Callee);
2524 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2526 // Add argument registers to the end of the list so that they are known live
2528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2529 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2530 RegsToPass[i].second.getValueType()));
2532 // Add an implicit use GOT pointer in EBX.
2533 if (!isTailCall && Subtarget->isPICStyleGOT())
2534 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2536 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2537 if (Is64Bit && isVarArg && !IsWin64)
2538 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2540 // Add a register mask operand representing the call-preserved registers.
2541 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2542 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2543 assert(Mask && "Missing call preserved mask for calling convention");
2544 Ops.push_back(DAG.getRegisterMask(Mask));
2546 if (InFlag.getNode())
2547 Ops.push_back(InFlag);
2551 //// If this is the first return lowered for this function, add the regs
2552 //// to the liveout set for the function.
2553 // This isn't right, although it's probably harmless on x86; liveouts
2554 // should be computed from returns not tail calls. Consider a void
2555 // function making a tail call to a function returning int.
2556 return DAG.getNode(X86ISD::TC_RETURN, dl,
2557 NodeTys, &Ops[0], Ops.size());
2560 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2561 InFlag = Chain.getValue(1);
2563 // Create the CALLSEQ_END node.
2564 unsigned NumBytesForCalleeToPush;
2565 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2566 getTargetMachine().Options.GuaranteedTailCallOpt))
2567 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2568 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2570 // If this is a call to a struct-return function, the callee
2571 // pops the hidden struct pointer, so we have to push it back.
2572 // This is common for Darwin/X86, Linux & Mingw32 targets.
2573 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2574 NumBytesForCalleeToPush = 4;
2576 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2578 // Returns a flag for retval copy to use.
2580 Chain = DAG.getCALLSEQ_END(Chain,
2581 DAG.getIntPtrConstant(NumBytes, true),
2582 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2585 InFlag = Chain.getValue(1);
2588 // Handle result values, copying them out of physregs into vregs that we
2590 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2591 Ins, dl, DAG, InVals);
2595 //===----------------------------------------------------------------------===//
2596 // Fast Calling Convention (tail call) implementation
2597 //===----------------------------------------------------------------------===//
2599 // Like std call, callee cleans arguments, convention except that ECX is
2600 // reserved for storing the tail called function address. Only 2 registers are
2601 // free for argument passing (inreg). Tail call optimization is performed
2603 // * tailcallopt is enabled
2604 // * caller/callee are fastcc
2605 // On X86_64 architecture with GOT-style position independent code only local
2606 // (within module) calls are supported at the moment.
2607 // To keep the stack aligned according to platform abi the function
2608 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2609 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2610 // If a tail called function callee has more arguments than the caller the
2611 // caller needs to make sure that there is room to move the RETADDR to. This is
2612 // achieved by reserving an area the size of the argument delta right after the
2613 // original REtADDR, but before the saved framepointer or the spilled registers
2614 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2626 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2627 /// for a 16 byte align requirement.
2629 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2630 SelectionDAG& DAG) const {
2631 MachineFunction &MF = DAG.getMachineFunction();
2632 const TargetMachine &TM = MF.getTarget();
2633 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2634 unsigned StackAlignment = TFI.getStackAlignment();
2635 uint64_t AlignMask = StackAlignment - 1;
2636 int64_t Offset = StackSize;
2637 uint64_t SlotSize = TD->getPointerSize();
2638 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2639 // Number smaller than 12 so just add the difference.
2640 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2642 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2643 Offset = ((~AlignMask) & Offset) + StackAlignment +
2644 (StackAlignment-SlotSize);
2649 /// MatchingStackOffset - Return true if the given stack call argument is
2650 /// already available in the same position (relatively) of the caller's
2651 /// incoming argument stack.
2653 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2654 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2655 const X86InstrInfo *TII) {
2656 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2658 if (Arg.getOpcode() == ISD::CopyFromReg) {
2659 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2660 if (!TargetRegisterInfo::isVirtualRegister(VR))
2662 MachineInstr *Def = MRI->getVRegDef(VR);
2665 if (!Flags.isByVal()) {
2666 if (!TII->isLoadFromStackSlot(Def, FI))
2669 unsigned Opcode = Def->getOpcode();
2670 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2671 Def->getOperand(1).isFI()) {
2672 FI = Def->getOperand(1).getIndex();
2673 Bytes = Flags.getByValSize();
2677 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2678 if (Flags.isByVal())
2679 // ByVal argument is passed in as a pointer but it's now being
2680 // dereferenced. e.g.
2681 // define @foo(%struct.X* %A) {
2682 // tail call @bar(%struct.X* byval %A)
2685 SDValue Ptr = Ld->getBasePtr();
2686 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2689 FI = FINode->getIndex();
2690 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2691 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2692 FI = FINode->getIndex();
2693 Bytes = Flags.getByValSize();
2697 assert(FI != INT_MAX);
2698 if (!MFI->isFixedObjectIndex(FI))
2700 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2703 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2704 /// for tail call optimization. Targets which want to do tail call
2705 /// optimization should implement this function.
2707 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2708 CallingConv::ID CalleeCC,
2710 bool isCalleeStructRet,
2711 bool isCallerStructRet,
2712 const SmallVectorImpl<ISD::OutputArg> &Outs,
2713 const SmallVectorImpl<SDValue> &OutVals,
2714 const SmallVectorImpl<ISD::InputArg> &Ins,
2715 SelectionDAG& DAG) const {
2716 if (!IsTailCallConvention(CalleeCC) &&
2717 CalleeCC != CallingConv::C)
2720 // If -tailcallopt is specified, make fastcc functions tail-callable.
2721 const MachineFunction &MF = DAG.getMachineFunction();
2722 const Function *CallerF = DAG.getMachineFunction().getFunction();
2723 CallingConv::ID CallerCC = CallerF->getCallingConv();
2724 bool CCMatch = CallerCC == CalleeCC;
2726 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2727 if (IsTailCallConvention(CalleeCC) && CCMatch)
2732 // Look for obvious safe cases to perform tail call optimization that do not
2733 // require ABI changes. This is what gcc calls sibcall.
2735 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2736 // emit a special epilogue.
2737 if (RegInfo->needsStackRealignment(MF))
2740 // Also avoid sibcall optimization if either caller or callee uses struct
2741 // return semantics.
2742 if (isCalleeStructRet || isCallerStructRet)
2745 // An stdcall caller is expected to clean up its arguments; the callee
2746 // isn't going to do that.
2747 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2750 // Do not sibcall optimize vararg calls unless all arguments are passed via
2752 if (isVarArg && !Outs.empty()) {
2754 // Optimizing for varargs on Win64 is unlikely to be safe without
2755 // additional testing.
2756 if (Subtarget->isTargetWin64())
2759 SmallVector<CCValAssign, 16> ArgLocs;
2760 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2761 getTargetMachine(), ArgLocs, *DAG.getContext());
2763 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2764 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2765 if (!ArgLocs[i].isRegLoc())
2769 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2770 // stack. Therefore, if it's not used by the call it is not safe to optimize
2771 // this into a sibcall.
2772 bool Unused = false;
2773 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2780 SmallVector<CCValAssign, 16> RVLocs;
2781 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2782 getTargetMachine(), RVLocs, *DAG.getContext());
2783 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2784 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2785 CCValAssign &VA = RVLocs[i];
2786 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2791 // If the calling conventions do not match, then we'd better make sure the
2792 // results are returned in the same way as what the caller expects.
2794 SmallVector<CCValAssign, 16> RVLocs1;
2795 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2796 getTargetMachine(), RVLocs1, *DAG.getContext());
2797 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2799 SmallVector<CCValAssign, 16> RVLocs2;
2800 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2801 getTargetMachine(), RVLocs2, *DAG.getContext());
2802 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2804 if (RVLocs1.size() != RVLocs2.size())
2806 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2807 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2809 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2811 if (RVLocs1[i].isRegLoc()) {
2812 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2815 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2821 // If the callee takes no arguments then go on to check the results of the
2823 if (!Outs.empty()) {
2824 // Check if stack adjustment is needed. For now, do not do this if any
2825 // argument is passed on the stack.
2826 SmallVector<CCValAssign, 16> ArgLocs;
2827 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2828 getTargetMachine(), ArgLocs, *DAG.getContext());
2830 // Allocate shadow area for Win64
2831 if (Subtarget->isTargetWin64()) {
2832 CCInfo.AllocateStack(32, 8);
2835 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2836 if (CCInfo.getNextStackOffset()) {
2837 MachineFunction &MF = DAG.getMachineFunction();
2838 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2841 // Check if the arguments are already laid out in the right way as
2842 // the caller's fixed stack objects.
2843 MachineFrameInfo *MFI = MF.getFrameInfo();
2844 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2845 const X86InstrInfo *TII =
2846 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2847 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2848 CCValAssign &VA = ArgLocs[i];
2849 SDValue Arg = OutVals[i];
2850 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2851 if (VA.getLocInfo() == CCValAssign::Indirect)
2853 if (!VA.isRegLoc()) {
2854 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2861 // If the tailcall address may be in a register, then make sure it's
2862 // possible to register allocate for it. In 32-bit, the call address can
2863 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2864 // callee-saved registers are restored. These happen to be the same
2865 // registers used to pass 'inreg' arguments so watch out for those.
2866 if (!Subtarget->is64Bit() &&
2867 !isa<GlobalAddressSDNode>(Callee) &&
2868 !isa<ExternalSymbolSDNode>(Callee)) {
2869 unsigned NumInRegs = 0;
2870 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2871 CCValAssign &VA = ArgLocs[i];
2874 unsigned Reg = VA.getLocReg();
2877 case X86::EAX: case X86::EDX: case X86::ECX:
2878 if (++NumInRegs == 3)
2890 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2891 return X86::createFastISel(funcInfo);
2895 //===----------------------------------------------------------------------===//
2896 // Other Lowering Hooks
2897 //===----------------------------------------------------------------------===//
2899 static bool MayFoldLoad(SDValue Op) {
2900 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2903 static bool MayFoldIntoStore(SDValue Op) {
2904 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2907 static bool isTargetShuffle(unsigned Opcode) {
2909 default: return false;
2910 case X86ISD::PSHUFD:
2911 case X86ISD::PSHUFHW:
2912 case X86ISD::PSHUFLW:
2914 case X86ISD::PALIGN:
2915 case X86ISD::MOVLHPS:
2916 case X86ISD::MOVLHPD:
2917 case X86ISD::MOVHLPS:
2918 case X86ISD::MOVLPS:
2919 case X86ISD::MOVLPD:
2920 case X86ISD::MOVSHDUP:
2921 case X86ISD::MOVSLDUP:
2922 case X86ISD::MOVDDUP:
2925 case X86ISD::UNPCKL:
2926 case X86ISD::UNPCKH:
2927 case X86ISD::VPERMILP:
2928 case X86ISD::VPERM2X128:
2933 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2934 SDValue V1, SelectionDAG &DAG) {
2936 default: llvm_unreachable("Unknown x86 shuffle node");
2937 case X86ISD::MOVSHDUP:
2938 case X86ISD::MOVSLDUP:
2939 case X86ISD::MOVDDUP:
2940 return DAG.getNode(Opc, dl, VT, V1);
2944 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2945 SDValue V1, unsigned TargetMask,
2946 SelectionDAG &DAG) {
2948 default: llvm_unreachable("Unknown x86 shuffle node");
2949 case X86ISD::PSHUFD:
2950 case X86ISD::PSHUFHW:
2951 case X86ISD::PSHUFLW:
2952 case X86ISD::VPERMILP:
2953 case X86ISD::VPERMI:
2954 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2958 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2959 SDValue V1, SDValue V2, unsigned TargetMask,
2960 SelectionDAG &DAG) {
2962 default: llvm_unreachable("Unknown x86 shuffle node");
2963 case X86ISD::PALIGN:
2965 case X86ISD::VPERM2X128:
2966 return DAG.getNode(Opc, dl, VT, V1, V2,
2967 DAG.getConstant(TargetMask, MVT::i8));
2971 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2972 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2974 default: llvm_unreachable("Unknown x86 shuffle node");
2975 case X86ISD::MOVLHPS:
2976 case X86ISD::MOVLHPD:
2977 case X86ISD::MOVHLPS:
2978 case X86ISD::MOVLPS:
2979 case X86ISD::MOVLPD:
2982 case X86ISD::UNPCKL:
2983 case X86ISD::UNPCKH:
2984 return DAG.getNode(Opc, dl, VT, V1, V2);
2988 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2989 MachineFunction &MF = DAG.getMachineFunction();
2990 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2991 int ReturnAddrIndex = FuncInfo->getRAIndex();
2993 if (ReturnAddrIndex == 0) {
2994 // Set up a frame object for the return address.
2995 uint64_t SlotSize = TD->getPointerSize();
2996 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2998 FuncInfo->setRAIndex(ReturnAddrIndex);
3001 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3005 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3006 bool hasSymbolicDisplacement) {
3007 // Offset should fit into 32 bit immediate field.
3008 if (!isInt<32>(Offset))
3011 // If we don't have a symbolic displacement - we don't have any extra
3013 if (!hasSymbolicDisplacement)
3016 // FIXME: Some tweaks might be needed for medium code model.
3017 if (M != CodeModel::Small && M != CodeModel::Kernel)
3020 // For small code model we assume that latest object is 16MB before end of 31
3021 // bits boundary. We may also accept pretty large negative constants knowing
3022 // that all objects are in the positive half of address space.
3023 if (M == CodeModel::Small && Offset < 16*1024*1024)
3026 // For kernel code model we know that all object resist in the negative half
3027 // of 32bits address space. We may not accept negative offsets, since they may
3028 // be just off and we may accept pretty large positive ones.
3029 if (M == CodeModel::Kernel && Offset > 0)
3035 /// isCalleePop - Determines whether the callee is required to pop its
3036 /// own arguments. Callee pop is necessary to support tail calls.
3037 bool X86::isCalleePop(CallingConv::ID CallingConv,
3038 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3042 switch (CallingConv) {
3045 case CallingConv::X86_StdCall:
3047 case CallingConv::X86_FastCall:
3049 case CallingConv::X86_ThisCall:
3051 case CallingConv::Fast:
3053 case CallingConv::GHC:
3058 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3059 /// specific condition code, returning the condition code and the LHS/RHS of the
3060 /// comparison to make.
3061 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3062 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3064 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3065 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3066 // X > -1 -> X == 0, jump !sign.
3067 RHS = DAG.getConstant(0, RHS.getValueType());
3068 return X86::COND_NS;
3069 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3070 // X < 0 -> X == 0, jump on sign.
3072 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3074 RHS = DAG.getConstant(0, RHS.getValueType());
3075 return X86::COND_LE;
3079 switch (SetCCOpcode) {
3080 default: llvm_unreachable("Invalid integer condition!");
3081 case ISD::SETEQ: return X86::COND_E;
3082 case ISD::SETGT: return X86::COND_G;
3083 case ISD::SETGE: return X86::COND_GE;
3084 case ISD::SETLT: return X86::COND_L;
3085 case ISD::SETLE: return X86::COND_LE;
3086 case ISD::SETNE: return X86::COND_NE;
3087 case ISD::SETULT: return X86::COND_B;
3088 case ISD::SETUGT: return X86::COND_A;
3089 case ISD::SETULE: return X86::COND_BE;
3090 case ISD::SETUGE: return X86::COND_AE;
3094 // First determine if it is required or is profitable to flip the operands.
3096 // If LHS is a foldable load, but RHS is not, flip the condition.
3097 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3098 !ISD::isNON_EXTLoad(RHS.getNode())) {
3099 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3100 std::swap(LHS, RHS);
3103 switch (SetCCOpcode) {
3109 std::swap(LHS, RHS);
3113 // On a floating point condition, the flags are set as follows:
3115 // 0 | 0 | 0 | X > Y
3116 // 0 | 0 | 1 | X < Y
3117 // 1 | 0 | 0 | X == Y
3118 // 1 | 1 | 1 | unordered
3119 switch (SetCCOpcode) {
3120 default: llvm_unreachable("Condcode should be pre-legalized away");
3122 case ISD::SETEQ: return X86::COND_E;
3123 case ISD::SETOLT: // flipped
3125 case ISD::SETGT: return X86::COND_A;
3126 case ISD::SETOLE: // flipped
3128 case ISD::SETGE: return X86::COND_AE;
3129 case ISD::SETUGT: // flipped
3131 case ISD::SETLT: return X86::COND_B;
3132 case ISD::SETUGE: // flipped
3134 case ISD::SETLE: return X86::COND_BE;
3136 case ISD::SETNE: return X86::COND_NE;
3137 case ISD::SETUO: return X86::COND_P;
3138 case ISD::SETO: return X86::COND_NP;
3140 case ISD::SETUNE: return X86::COND_INVALID;
3144 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3145 /// code. Current x86 isa includes the following FP cmov instructions:
3146 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3147 static bool hasFPCMov(unsigned X86CC) {
3163 /// isFPImmLegal - Returns true if the target can instruction select the
3164 /// specified FP immediate natively. If false, the legalizer will
3165 /// materialize the FP immediate as a load from a constant pool.
3166 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3167 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3168 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3174 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3175 /// the specified range (L, H].
3176 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3177 return (Val < 0) || (Val >= Low && Val < Hi);
3180 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3181 /// specified value.
3182 static bool isUndefOrEqual(int Val, int CmpVal) {
3183 if (Val < 0 || Val == CmpVal)
3188 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3189 /// from position Pos and ending in Pos+Size, falls within the specified
3190 /// sequential range (L, L+Pos]. or is undef.
3191 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3192 int Pos, int Size, int Low) {
3193 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3194 if (!isUndefOrEqual(Mask[i], Low))
3199 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3200 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3201 /// the second operand.
3202 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3203 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3204 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3205 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3206 return (Mask[0] < 2 && Mask[1] < 2);
3210 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3211 /// is suitable for input to PSHUFHW.
3212 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3213 if (VT != MVT::v8i16)
3216 // Lower quadword copied in order or undef.
3217 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3220 // Upper quadword shuffled.
3221 for (unsigned i = 4; i != 8; ++i)
3222 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3228 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3229 /// is suitable for input to PSHUFLW.
3230 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3231 if (VT != MVT::v8i16)
3234 // Upper quadword copied in order.
3235 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3238 // Lower quadword shuffled.
3239 for (unsigned i = 0; i != 4; ++i)
3246 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3247 /// is suitable for input to PALIGNR.
3248 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3249 const X86Subtarget *Subtarget) {
3250 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3251 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3254 unsigned NumElts = VT.getVectorNumElements();
3255 unsigned NumLanes = VT.getSizeInBits()/128;
3256 unsigned NumLaneElts = NumElts/NumLanes;
3258 // Do not handle 64-bit element shuffles with palignr.
3259 if (NumLaneElts == 2)
3262 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3264 for (i = 0; i != NumLaneElts; ++i) {
3269 // Lane is all undef, go to next lane
3270 if (i == NumLaneElts)
3273 int Start = Mask[i+l];
3275 // Make sure its in this lane in one of the sources
3276 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3277 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3280 // If not lane 0, then we must match lane 0
3281 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3284 // Correct second source to be contiguous with first source
3285 if (Start >= (int)NumElts)
3286 Start -= NumElts - NumLaneElts;
3288 // Make sure we're shifting in the right direction.
3289 if (Start <= (int)(i+l))
3294 // Check the rest of the elements to see if they are consecutive.
3295 for (++i; i != NumLaneElts; ++i) {
3296 int Idx = Mask[i+l];
3298 // Make sure its in this lane
3299 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3300 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3303 // If not lane 0, then we must match lane 0
3304 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3307 if (Idx >= (int)NumElts)
3308 Idx -= NumElts - NumLaneElts;
3310 if (!isUndefOrEqual(Idx, Start+i))
3319 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3320 /// the two vector operands have swapped position.
3321 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3322 unsigned NumElems) {
3323 for (unsigned i = 0; i != NumElems; ++i) {
3327 else if (idx < (int)NumElems)
3328 Mask[i] = idx + NumElems;
3330 Mask[i] = idx - NumElems;
3334 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3335 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3336 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3337 /// reverse of what x86 shuffles want.
3338 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3339 bool Commuted = false) {
3340 if (!HasAVX && VT.getSizeInBits() == 256)
3343 unsigned NumElems = VT.getVectorNumElements();
3344 unsigned NumLanes = VT.getSizeInBits()/128;
3345 unsigned NumLaneElems = NumElems/NumLanes;
3347 if (NumLaneElems != 2 && NumLaneElems != 4)
3350 // VSHUFPSY divides the resulting vector into 4 chunks.
3351 // The sources are also splitted into 4 chunks, and each destination
3352 // chunk must come from a different source chunk.
3354 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3355 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3357 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3358 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3360 // VSHUFPDY divides the resulting vector into 4 chunks.
3361 // The sources are also splitted into 4 chunks, and each destination
3362 // chunk must come from a different source chunk.
3364 // SRC1 => X3 X2 X1 X0
3365 // SRC2 => Y3 Y2 Y1 Y0
3367 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3369 unsigned HalfLaneElems = NumLaneElems/2;
3370 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3371 for (unsigned i = 0; i != NumLaneElems; ++i) {
3372 int Idx = Mask[i+l];
3373 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3374 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3376 // For VSHUFPSY, the mask of the second half must be the same as the
3377 // first but with the appropriate offsets. This works in the same way as
3378 // VPERMILPS works with masks.
3379 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3381 if (!isUndefOrEqual(Idx, Mask[i]+l))
3389 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3390 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3391 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3392 unsigned NumElems = VT.getVectorNumElements();
3394 if (VT.getSizeInBits() != 128)
3400 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3401 return isUndefOrEqual(Mask[0], 6) &&
3402 isUndefOrEqual(Mask[1], 7) &&
3403 isUndefOrEqual(Mask[2], 2) &&
3404 isUndefOrEqual(Mask[3], 3);
3407 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3408 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3410 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3411 unsigned NumElems = VT.getVectorNumElements();
3413 if (VT.getSizeInBits() != 128)
3419 return isUndefOrEqual(Mask[0], 2) &&
3420 isUndefOrEqual(Mask[1], 3) &&
3421 isUndefOrEqual(Mask[2], 2) &&
3422 isUndefOrEqual(Mask[3], 3);
3425 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3426 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3427 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3428 if (VT.getSizeInBits() != 128)
3431 unsigned NumElems = VT.getVectorNumElements();
3433 if (NumElems != 2 && NumElems != 4)
3436 for (unsigned i = 0; i != NumElems/2; ++i)
3437 if (!isUndefOrEqual(Mask[i], i + NumElems))
3440 for (unsigned i = NumElems/2; i != NumElems; ++i)
3441 if (!isUndefOrEqual(Mask[i], i))
3447 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3448 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3449 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3450 unsigned NumElems = VT.getVectorNumElements();
3452 if ((NumElems != 2 && NumElems != 4)
3453 || VT.getSizeInBits() > 128)
3456 for (unsigned i = 0; i != NumElems/2; ++i)
3457 if (!isUndefOrEqual(Mask[i], i))
3460 for (unsigned i = 0; i != NumElems/2; ++i)
3461 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3467 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3468 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3469 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3470 bool HasAVX2, bool V2IsSplat = false) {
3471 unsigned NumElts = VT.getVectorNumElements();
3473 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3474 "Unsupported vector type for unpckh");
3476 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3477 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3480 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3481 // independently on 128-bit lanes.
3482 unsigned NumLanes = VT.getSizeInBits()/128;
3483 unsigned NumLaneElts = NumElts/NumLanes;
3485 for (unsigned l = 0; l != NumLanes; ++l) {
3486 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3487 i != (l+1)*NumLaneElts;
3490 int BitI1 = Mask[i+1];
3491 if (!isUndefOrEqual(BitI, j))
3494 if (!isUndefOrEqual(BitI1, NumElts))
3497 if (!isUndefOrEqual(BitI1, j + NumElts))
3506 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3507 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3508 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3509 bool HasAVX2, bool V2IsSplat = false) {
3510 unsigned NumElts = VT.getVectorNumElements();
3512 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3513 "Unsupported vector type for unpckh");
3515 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3516 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3519 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3520 // independently on 128-bit lanes.
3521 unsigned NumLanes = VT.getSizeInBits()/128;
3522 unsigned NumLaneElts = NumElts/NumLanes;
3524 for (unsigned l = 0; l != NumLanes; ++l) {
3525 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3526 i != (l+1)*NumLaneElts; i += 2, ++j) {
3528 int BitI1 = Mask[i+1];
3529 if (!isUndefOrEqual(BitI, j))
3532 if (isUndefOrEqual(BitI1, NumElts))
3535 if (!isUndefOrEqual(BitI1, j+NumElts))
3543 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3544 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3546 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3548 unsigned NumElts = VT.getVectorNumElements();
3550 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3551 "Unsupported vector type for unpckh");
3553 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3554 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3557 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3558 // FIXME: Need a better way to get rid of this, there's no latency difference
3559 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3560 // the former later. We should also remove the "_undef" special mask.
3561 if (NumElts == 4 && VT.getSizeInBits() == 256)
3564 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3565 // independently on 128-bit lanes.
3566 unsigned NumLanes = VT.getSizeInBits()/128;
3567 unsigned NumLaneElts = NumElts/NumLanes;
3569 for (unsigned l = 0; l != NumLanes; ++l) {
3570 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3571 i != (l+1)*NumLaneElts;
3574 int BitI1 = Mask[i+1];
3576 if (!isUndefOrEqual(BitI, j))
3578 if (!isUndefOrEqual(BitI1, j))
3586 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3587 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3589 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3590 unsigned NumElts = VT.getVectorNumElements();
3592 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3593 "Unsupported vector type for unpckh");
3595 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3596 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3599 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3600 // independently on 128-bit lanes.
3601 unsigned NumLanes = VT.getSizeInBits()/128;
3602 unsigned NumLaneElts = NumElts/NumLanes;
3604 for (unsigned l = 0; l != NumLanes; ++l) {
3605 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3606 i != (l+1)*NumLaneElts; i += 2, ++j) {
3608 int BitI1 = Mask[i+1];
3609 if (!isUndefOrEqual(BitI, j))
3611 if (!isUndefOrEqual(BitI1, j))
3618 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3619 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3620 /// MOVSD, and MOVD, i.e. setting the lowest element.
3621 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3622 if (VT.getVectorElementType().getSizeInBits() < 32)
3624 if (VT.getSizeInBits() == 256)
3627 unsigned NumElts = VT.getVectorNumElements();
3629 if (!isUndefOrEqual(Mask[0], NumElts))
3632 for (unsigned i = 1; i != NumElts; ++i)
3633 if (!isUndefOrEqual(Mask[i], i))
3639 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3640 /// as permutations between 128-bit chunks or halves. As an example: this
3642 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3643 /// The first half comes from the second half of V1 and the second half from the
3644 /// the second half of V2.
3645 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3646 if (!HasAVX || VT.getSizeInBits() != 256)
3649 // The shuffle result is divided into half A and half B. In total the two
3650 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3651 // B must come from C, D, E or F.
3652 unsigned HalfSize = VT.getVectorNumElements()/2;
3653 bool MatchA = false, MatchB = false;
3655 // Check if A comes from one of C, D, E, F.
3656 for (unsigned Half = 0; Half != 4; ++Half) {
3657 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3663 // Check if B comes from one of C, D, E, F.
3664 for (unsigned Half = 0; Half != 4; ++Half) {
3665 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3671 return MatchA && MatchB;
3674 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3675 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3676 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3677 EVT VT = SVOp->getValueType(0);
3679 unsigned HalfSize = VT.getVectorNumElements()/2;
3681 unsigned FstHalf = 0, SndHalf = 0;
3682 for (unsigned i = 0; i < HalfSize; ++i) {
3683 if (SVOp->getMaskElt(i) > 0) {
3684 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3688 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3689 if (SVOp->getMaskElt(i) > 0) {
3690 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3695 return (FstHalf | (SndHalf << 4));
3698 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3699 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3700 /// Note that VPERMIL mask matching is different depending whether theunderlying
3701 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3702 /// to the same elements of the low, but to the higher half of the source.
3703 /// In VPERMILPD the two lanes could be shuffled independently of each other
3704 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3705 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3709 unsigned NumElts = VT.getVectorNumElements();
3710 // Only match 256-bit with 32/64-bit types
3711 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3714 unsigned NumLanes = VT.getSizeInBits()/128;
3715 unsigned LaneSize = NumElts/NumLanes;
3716 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3717 for (unsigned i = 0; i != LaneSize; ++i) {
3718 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3720 if (NumElts != 8 || l == 0)
3722 // VPERMILPS handling
3725 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3733 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3734 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3735 /// element of vector 2 and the other elements to come from vector 1 in order.
3736 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3737 bool V2IsSplat = false, bool V2IsUndef = false) {
3738 unsigned NumOps = VT.getVectorNumElements();
3739 if (VT.getSizeInBits() == 256)
3741 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3744 if (!isUndefOrEqual(Mask[0], 0))
3747 for (unsigned i = 1; i != NumOps; ++i)
3748 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3749 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3750 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3756 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3757 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3758 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3759 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3760 const X86Subtarget *Subtarget) {
3761 if (!Subtarget->hasSSE3())
3764 unsigned NumElems = VT.getVectorNumElements();
3766 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3767 (VT.getSizeInBits() == 256 && NumElems != 8))
3770 // "i+1" is the value the indexed mask element must have
3771 for (unsigned i = 0; i != NumElems; i += 2)
3772 if (!isUndefOrEqual(Mask[i], i+1) ||
3773 !isUndefOrEqual(Mask[i+1], i+1))
3779 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3780 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3781 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3782 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3783 const X86Subtarget *Subtarget) {
3784 if (!Subtarget->hasSSE3())
3787 unsigned NumElems = VT.getVectorNumElements();
3789 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3790 (VT.getSizeInBits() == 256 && NumElems != 8))
3793 // "i" is the value the indexed mask element must have
3794 for (unsigned i = 0; i != NumElems; i += 2)
3795 if (!isUndefOrEqual(Mask[i], i) ||
3796 !isUndefOrEqual(Mask[i+1], i))
3802 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3803 /// specifies a shuffle of elements that is suitable for input to 256-bit
3804 /// version of MOVDDUP.
3805 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3806 unsigned NumElts = VT.getVectorNumElements();
3808 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3811 for (unsigned i = 0; i != NumElts/2; ++i)
3812 if (!isUndefOrEqual(Mask[i], 0))
3814 for (unsigned i = NumElts/2; i != NumElts; ++i)
3815 if (!isUndefOrEqual(Mask[i], NumElts/2))
3820 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3821 /// specifies a shuffle of elements that is suitable for input to 128-bit
3822 /// version of MOVDDUP.
3823 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3824 if (VT.getSizeInBits() != 128)
3827 unsigned e = VT.getVectorNumElements() / 2;
3828 for (unsigned i = 0; i != e; ++i)
3829 if (!isUndefOrEqual(Mask[i], i))
3831 for (unsigned i = 0; i != e; ++i)
3832 if (!isUndefOrEqual(Mask[e+i], i))
3837 /// isVEXTRACTF128Index - Return true if the specified
3838 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3839 /// suitable for input to VEXTRACTF128.
3840 bool X86::isVEXTRACTF128Index(SDNode *N) {
3841 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3844 // The index should be aligned on a 128-bit boundary.
3846 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3848 unsigned VL = N->getValueType(0).getVectorNumElements();
3849 unsigned VBits = N->getValueType(0).getSizeInBits();
3850 unsigned ElSize = VBits / VL;
3851 bool Result = (Index * ElSize) % 128 == 0;
3856 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3857 /// operand specifies a subvector insert that is suitable for input to
3859 bool X86::isVINSERTF128Index(SDNode *N) {
3860 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3863 // The index should be aligned on a 128-bit boundary.
3865 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3867 unsigned VL = N->getValueType(0).getVectorNumElements();
3868 unsigned VBits = N->getValueType(0).getSizeInBits();
3869 unsigned ElSize = VBits / VL;
3870 bool Result = (Index * ElSize) % 128 == 0;
3875 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3876 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3877 /// Handles 128-bit and 256-bit.
3878 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3879 EVT VT = N->getValueType(0);
3881 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3882 "Unsupported vector type for PSHUF/SHUFP");
3884 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3885 // independently on 128-bit lanes.
3886 unsigned NumElts = VT.getVectorNumElements();
3887 unsigned NumLanes = VT.getSizeInBits()/128;
3888 unsigned NumLaneElts = NumElts/NumLanes;
3890 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3891 "Only supports 2 or 4 elements per lane");
3893 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3895 for (unsigned i = 0; i != NumElts; ++i) {
3896 int Elt = N->getMaskElt(i);
3897 if (Elt < 0) continue;
3899 unsigned ShAmt = i << Shift;
3900 if (ShAmt >= 8) ShAmt -= 8;
3901 Mask |= Elt << ShAmt;
3907 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3908 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3909 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3911 // 8 nodes, but we only care about the last 4.
3912 for (unsigned i = 7; i >= 4; --i) {
3913 int Val = N->getMaskElt(i);
3922 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3923 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3924 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3926 // 8 nodes, but we only care about the first 4.
3927 for (int i = 3; i >= 0; --i) {
3928 int Val = N->getMaskElt(i);
3937 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3938 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3939 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3940 EVT VT = SVOp->getValueType(0);
3941 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3943 unsigned NumElts = VT.getVectorNumElements();
3944 unsigned NumLanes = VT.getSizeInBits()/128;
3945 unsigned NumLaneElts = NumElts/NumLanes;
3949 for (i = 0; i != NumElts; ++i) {
3950 Val = SVOp->getMaskElt(i);
3954 if (Val >= (int)NumElts)
3955 Val -= NumElts - NumLaneElts;
3957 assert(Val - i > 0 && "PALIGNR imm should be positive");
3958 return (Val - i) * EltSize;
3961 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3962 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3964 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3965 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3966 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3969 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3971 EVT VecVT = N->getOperand(0).getValueType();
3972 EVT ElVT = VecVT.getVectorElementType();
3974 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3975 return Index / NumElemsPerChunk;
3978 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3979 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3981 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3982 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3983 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3986 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3988 EVT VecVT = N->getValueType(0);
3989 EVT ElVT = VecVT.getVectorElementType();
3991 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3992 return Index / NumElemsPerChunk;
3995 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
3996 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
3997 /// Handles 256-bit.
3998 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
3999 EVT VT = N->getValueType(0);
4001 unsigned NumElts = VT.getVectorNumElements();
4003 assert((VT.is256BitVector() && NumElts == 4) &&
4004 "Unsupported vector type for VPERMQ/VPERMPD");
4007 for (unsigned i = 0; i != NumElts; ++i) {
4008 int Elt = N->getMaskElt(i);
4011 Mask |= Elt << (i*2);
4016 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4018 bool X86::isZeroNode(SDValue Elt) {
4019 return ((isa<ConstantSDNode>(Elt) &&
4020 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4021 (isa<ConstantFPSDNode>(Elt) &&
4022 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4025 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4026 /// their permute mask.
4027 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4028 SelectionDAG &DAG) {
4029 EVT VT = SVOp->getValueType(0);
4030 unsigned NumElems = VT.getVectorNumElements();
4031 SmallVector<int, 8> MaskVec;
4033 for (unsigned i = 0; i != NumElems; ++i) {
4034 int idx = SVOp->getMaskElt(i);
4036 MaskVec.push_back(idx);
4037 else if (idx < (int)NumElems)
4038 MaskVec.push_back(idx + NumElems);
4040 MaskVec.push_back(idx - NumElems);
4042 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4043 SVOp->getOperand(0), &MaskVec[0]);
4046 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4047 /// match movhlps. The lower half elements should come from upper half of
4048 /// V1 (and in order), and the upper half elements should come from the upper
4049 /// half of V2 (and in order).
4050 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4051 if (VT.getSizeInBits() != 128)
4053 if (VT.getVectorNumElements() != 4)
4055 for (unsigned i = 0, e = 2; i != e; ++i)
4056 if (!isUndefOrEqual(Mask[i], i+2))
4058 for (unsigned i = 2; i != 4; ++i)
4059 if (!isUndefOrEqual(Mask[i], i+4))
4064 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4065 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4067 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4068 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4070 N = N->getOperand(0).getNode();
4071 if (!ISD::isNON_EXTLoad(N))
4074 *LD = cast<LoadSDNode>(N);
4078 // Test whether the given value is a vector value which will be legalized
4080 static bool WillBeConstantPoolLoad(SDNode *N) {
4081 if (N->getOpcode() != ISD::BUILD_VECTOR)
4084 // Check for any non-constant elements.
4085 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4086 switch (N->getOperand(i).getNode()->getOpcode()) {
4088 case ISD::ConstantFP:
4095 // Vectors of all-zeros and all-ones are materialized with special
4096 // instructions rather than being loaded.
4097 return !ISD::isBuildVectorAllZeros(N) &&
4098 !ISD::isBuildVectorAllOnes(N);
4101 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4102 /// match movlp{s|d}. The lower half elements should come from lower half of
4103 /// V1 (and in order), and the upper half elements should come from the upper
4104 /// half of V2 (and in order). And since V1 will become the source of the
4105 /// MOVLP, it must be either a vector load or a scalar load to vector.
4106 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4107 ArrayRef<int> Mask, EVT VT) {
4108 if (VT.getSizeInBits() != 128)
4111 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4113 // Is V2 is a vector load, don't do this transformation. We will try to use
4114 // load folding shufps op.
4115 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4118 unsigned NumElems = VT.getVectorNumElements();
4120 if (NumElems != 2 && NumElems != 4)
4122 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4123 if (!isUndefOrEqual(Mask[i], i))
4125 for (unsigned i = NumElems/2; i != NumElems; ++i)
4126 if (!isUndefOrEqual(Mask[i], i+NumElems))
4131 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4133 static bool isSplatVector(SDNode *N) {
4134 if (N->getOpcode() != ISD::BUILD_VECTOR)
4137 SDValue SplatValue = N->getOperand(0);
4138 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4139 if (N->getOperand(i) != SplatValue)
4144 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4145 /// to an zero vector.
4146 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4147 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4148 SDValue V1 = N->getOperand(0);
4149 SDValue V2 = N->getOperand(1);
4150 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4151 for (unsigned i = 0; i != NumElems; ++i) {
4152 int Idx = N->getMaskElt(i);
4153 if (Idx >= (int)NumElems) {
4154 unsigned Opc = V2.getOpcode();
4155 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4157 if (Opc != ISD::BUILD_VECTOR ||
4158 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4160 } else if (Idx >= 0) {
4161 unsigned Opc = V1.getOpcode();
4162 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4164 if (Opc != ISD::BUILD_VECTOR ||
4165 !X86::isZeroNode(V1.getOperand(Idx)))
4172 /// getZeroVector - Returns a vector of specified type with all zero elements.
4174 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4175 SelectionDAG &DAG, DebugLoc dl) {
4176 assert(VT.isVector() && "Expected a vector type");
4178 // Always build SSE zero vectors as <4 x i32> bitcasted
4179 // to their dest type. This ensures they get CSE'd.
4181 if (VT.getSizeInBits() == 128) { // SSE
4182 if (Subtarget->hasSSE2()) { // SSE2
4183 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4184 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4186 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4187 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4189 } else if (VT.getSizeInBits() == 256) { // AVX
4190 if (Subtarget->hasAVX2()) { // AVX2
4191 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4192 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4193 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4195 // 256-bit logic and arithmetic instructions in AVX are all
4196 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4197 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4198 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4199 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4202 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4205 /// getOnesVector - Returns a vector of specified type with all bits set.
4206 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4207 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4208 /// Then bitcast to their original type, ensuring they get CSE'd.
4209 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4211 assert(VT.isVector() && "Expected a vector type");
4212 assert((VT.is128BitVector() || VT.is256BitVector())
4213 && "Expected a 128-bit or 256-bit vector type");
4215 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4217 if (VT.getSizeInBits() == 256) {
4218 if (HasAVX2) { // AVX2
4219 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4220 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4222 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4223 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4226 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4229 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4232 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4233 /// that point to V2 points to its first element.
4234 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4235 for (unsigned i = 0; i != NumElems; ++i) {
4236 if (Mask[i] > (int)NumElems) {
4242 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4243 /// operation of specified width.
4244 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4246 unsigned NumElems = VT.getVectorNumElements();
4247 SmallVector<int, 8> Mask;
4248 Mask.push_back(NumElems);
4249 for (unsigned i = 1; i != NumElems; ++i)
4251 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4254 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4255 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4257 unsigned NumElems = VT.getVectorNumElements();
4258 SmallVector<int, 8> Mask;
4259 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4261 Mask.push_back(i + NumElems);
4263 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4266 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4267 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4269 unsigned NumElems = VT.getVectorNumElements();
4270 unsigned Half = NumElems/2;
4271 SmallVector<int, 8> Mask;
4272 for (unsigned i = 0; i != Half; ++i) {
4273 Mask.push_back(i + Half);
4274 Mask.push_back(i + NumElems + Half);
4276 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4279 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4280 // a generic shuffle instruction because the target has no such instructions.
4281 // Generate shuffles which repeat i16 and i8 several times until they can be
4282 // represented by v4f32 and then be manipulated by target suported shuffles.
4283 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4284 EVT VT = V.getValueType();
4285 int NumElems = VT.getVectorNumElements();
4286 DebugLoc dl = V.getDebugLoc();
4288 while (NumElems > 4) {
4289 if (EltNo < NumElems/2) {
4290 V = getUnpackl(DAG, dl, VT, V, V);
4292 V = getUnpackh(DAG, dl, VT, V, V);
4293 EltNo -= NumElems/2;
4300 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4301 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4302 EVT VT = V.getValueType();
4303 DebugLoc dl = V.getDebugLoc();
4304 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4305 && "Vector size not supported");
4307 if (VT.getSizeInBits() == 128) {
4308 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4309 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4310 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4313 // To use VPERMILPS to splat scalars, the second half of indicies must
4314 // refer to the higher part, which is a duplication of the lower one,
4315 // because VPERMILPS can only handle in-lane permutations.
4316 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4317 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4319 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4320 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4324 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4327 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4328 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4329 EVT SrcVT = SV->getValueType(0);
4330 SDValue V1 = SV->getOperand(0);
4331 DebugLoc dl = SV->getDebugLoc();
4333 int EltNo = SV->getSplatIndex();
4334 int NumElems = SrcVT.getVectorNumElements();
4335 unsigned Size = SrcVT.getSizeInBits();
4337 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4338 "Unknown how to promote splat for type");
4340 // Extract the 128-bit part containing the splat element and update
4341 // the splat element index when it refers to the higher register.
4343 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4344 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4346 EltNo -= NumElems/2;
4349 // All i16 and i8 vector types can't be used directly by a generic shuffle
4350 // instruction because the target has no such instruction. Generate shuffles
4351 // which repeat i16 and i8 several times until they fit in i32, and then can
4352 // be manipulated by target suported shuffles.
4353 EVT EltVT = SrcVT.getVectorElementType();
4354 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4355 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4357 // Recreate the 256-bit vector and place the same 128-bit vector
4358 // into the low and high part. This is necessary because we want
4359 // to use VPERM* to shuffle the vectors
4361 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4364 return getLegalSplat(DAG, V1, EltNo);
4367 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4368 /// vector of zero or undef vector. This produces a shuffle where the low
4369 /// element of V2 is swizzled into the zero/undef vector, landing at element
4370 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4371 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4373 const X86Subtarget *Subtarget,
4374 SelectionDAG &DAG) {
4375 EVT VT = V2.getValueType();
4377 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4378 unsigned NumElems = VT.getVectorNumElements();
4379 SmallVector<int, 16> MaskVec;
4380 for (unsigned i = 0; i != NumElems; ++i)
4381 // If this is the insertion idx, put the low elt of V2 here.
4382 MaskVec.push_back(i == Idx ? NumElems : i);
4383 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4386 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4387 /// target specific opcode. Returns true if the Mask could be calculated.
4388 /// Sets IsUnary to true if only uses one source.
4389 static bool getTargetShuffleMask(SDNode *N, EVT VT,
4390 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4391 unsigned NumElems = VT.getVectorNumElements();
4395 switch(N->getOpcode()) {
4397 ImmN = N->getOperand(N->getNumOperands()-1);
4398 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4400 case X86ISD::UNPCKH:
4401 DecodeUNPCKHMask(VT, Mask);
4403 case X86ISD::UNPCKL:
4404 DecodeUNPCKLMask(VT, Mask);
4406 case X86ISD::MOVHLPS:
4407 DecodeMOVHLPSMask(NumElems, Mask);
4409 case X86ISD::MOVLHPS:
4410 DecodeMOVLHPSMask(NumElems, Mask);
4412 case X86ISD::PSHUFD:
4413 case X86ISD::VPERMILP:
4414 ImmN = N->getOperand(N->getNumOperands()-1);
4415 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4418 case X86ISD::PSHUFHW:
4419 ImmN = N->getOperand(N->getNumOperands()-1);
4420 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4423 case X86ISD::PSHUFLW:
4424 ImmN = N->getOperand(N->getNumOperands()-1);
4425 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4429 case X86ISD::MOVSD: {
4430 // The index 0 always comes from the first element of the second source,
4431 // this is why MOVSS and MOVSD are used in the first place. The other
4432 // elements come from the other positions of the first source vector
4433 Mask.push_back(NumElems);
4434 for (unsigned i = 1; i != NumElems; ++i) {
4439 case X86ISD::VPERM2X128:
4440 ImmN = N->getOperand(N->getNumOperands()-1);
4441 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4442 if (Mask.empty()) return false;
4444 case X86ISD::MOVDDUP:
4445 case X86ISD::MOVLHPD:
4446 case X86ISD::MOVLPD:
4447 case X86ISD::MOVLPS:
4448 case X86ISD::MOVSHDUP:
4449 case X86ISD::MOVSLDUP:
4450 case X86ISD::PALIGN:
4451 // Not yet implemented
4453 default: llvm_unreachable("unknown target shuffle node");
4459 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4460 /// element of the result of the vector shuffle.
4461 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4464 return SDValue(); // Limit search depth.
4466 SDValue V = SDValue(N, 0);
4467 EVT VT = V.getValueType();
4468 unsigned Opcode = V.getOpcode();
4470 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4471 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4472 int Elt = SV->getMaskElt(Index);
4475 return DAG.getUNDEF(VT.getVectorElementType());
4477 unsigned NumElems = VT.getVectorNumElements();
4478 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4479 : SV->getOperand(1);
4480 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4483 // Recurse into target specific vector shuffles to find scalars.
4484 if (isTargetShuffle(Opcode)) {
4485 unsigned NumElems = VT.getVectorNumElements();
4486 SmallVector<int, 16> ShuffleMask;
4490 if (!getTargetShuffleMask(N, VT, ShuffleMask, IsUnary))
4493 int Elt = ShuffleMask[Index];
4495 return DAG.getUNDEF(VT.getVectorElementType());
4497 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4499 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4503 // Actual nodes that may contain scalar elements
4504 if (Opcode == ISD::BITCAST) {
4505 V = V.getOperand(0);
4506 EVT SrcVT = V.getValueType();
4507 unsigned NumElems = VT.getVectorNumElements();
4509 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4513 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4514 return (Index == 0) ? V.getOperand(0)
4515 : DAG.getUNDEF(VT.getVectorElementType());
4517 if (V.getOpcode() == ISD::BUILD_VECTOR)
4518 return V.getOperand(Index);
4523 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4524 /// shuffle operation which come from a consecutively from a zero. The
4525 /// search can start in two different directions, from left or right.
4527 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4528 bool ZerosFromLeft, SelectionDAG &DAG) {
4530 for (i = 0; i != NumElems; ++i) {
4531 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4532 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4533 if (!(Elt.getNode() &&
4534 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4541 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4542 /// correspond consecutively to elements from one of the vector operands,
4543 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4545 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4546 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4547 unsigned NumElems, unsigned &OpNum) {
4548 bool SeenV1 = false;
4549 bool SeenV2 = false;
4551 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4552 int Idx = SVOp->getMaskElt(i);
4553 // Ignore undef indicies
4557 if (Idx < (int)NumElems)
4562 // Only accept consecutive elements from the same vector
4563 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4567 OpNum = SeenV1 ? 0 : 1;
4571 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4572 /// logical left shift of a vector.
4573 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4574 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4575 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4576 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4577 false /* check zeros from right */, DAG);
4583 // Considering the elements in the mask that are not consecutive zeros,
4584 // check if they consecutively come from only one of the source vectors.
4586 // V1 = {X, A, B, C} 0
4588 // vector_shuffle V1, V2 <1, 2, 3, X>
4590 if (!isShuffleMaskConsecutive(SVOp,
4591 0, // Mask Start Index
4592 NumElems-NumZeros, // Mask End Index(exclusive)
4593 NumZeros, // Where to start looking in the src vector
4594 NumElems, // Number of elements in vector
4595 OpSrc)) // Which source operand ?
4600 ShVal = SVOp->getOperand(OpSrc);
4604 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4605 /// logical left shift of a vector.
4606 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4607 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4608 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4609 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4610 true /* check zeros from left */, DAG);
4616 // Considering the elements in the mask that are not consecutive zeros,
4617 // check if they consecutively come from only one of the source vectors.
4619 // 0 { A, B, X, X } = V2
4621 // vector_shuffle V1, V2 <X, X, 4, 5>
4623 if (!isShuffleMaskConsecutive(SVOp,
4624 NumZeros, // Mask Start Index
4625 NumElems, // Mask End Index(exclusive)
4626 0, // Where to start looking in the src vector
4627 NumElems, // Number of elements in vector
4628 OpSrc)) // Which source operand ?
4633 ShVal = SVOp->getOperand(OpSrc);
4637 /// isVectorShift - Returns true if the shuffle can be implemented as a
4638 /// logical left or right shift of a vector.
4639 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4640 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4641 // Although the logic below support any bitwidth size, there are no
4642 // shift instructions which handle more than 128-bit vectors.
4643 if (SVOp->getValueType(0).getSizeInBits() > 128)
4646 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4647 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4653 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4655 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4656 unsigned NumNonZero, unsigned NumZero,
4658 const X86Subtarget* Subtarget,
4659 const TargetLowering &TLI) {
4663 DebugLoc dl = Op.getDebugLoc();
4666 for (unsigned i = 0; i < 16; ++i) {
4667 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4668 if (ThisIsNonZero && First) {
4670 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4672 V = DAG.getUNDEF(MVT::v8i16);
4677 SDValue ThisElt(0, 0), LastElt(0, 0);
4678 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4679 if (LastIsNonZero) {
4680 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4681 MVT::i16, Op.getOperand(i-1));
4683 if (ThisIsNonZero) {
4684 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4685 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4686 ThisElt, DAG.getConstant(8, MVT::i8));
4688 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4692 if (ThisElt.getNode())
4693 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4694 DAG.getIntPtrConstant(i/2));
4698 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4701 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4703 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4704 unsigned NumNonZero, unsigned NumZero,
4706 const X86Subtarget* Subtarget,
4707 const TargetLowering &TLI) {
4711 DebugLoc dl = Op.getDebugLoc();
4714 for (unsigned i = 0; i < 8; ++i) {
4715 bool isNonZero = (NonZeros & (1 << i)) != 0;
4719 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4721 V = DAG.getUNDEF(MVT::v8i16);
4724 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4725 MVT::v8i16, V, Op.getOperand(i),
4726 DAG.getIntPtrConstant(i));
4733 /// getVShift - Return a vector logical shift node.
4735 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4736 unsigned NumBits, SelectionDAG &DAG,
4737 const TargetLowering &TLI, DebugLoc dl) {
4738 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4739 EVT ShVT = MVT::v2i64;
4740 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4741 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4742 return DAG.getNode(ISD::BITCAST, dl, VT,
4743 DAG.getNode(Opc, dl, ShVT, SrcOp,
4744 DAG.getConstant(NumBits,
4745 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4749 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4750 SelectionDAG &DAG) const {
4752 // Check if the scalar load can be widened into a vector load. And if
4753 // the address is "base + cst" see if the cst can be "absorbed" into
4754 // the shuffle mask.
4755 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4756 SDValue Ptr = LD->getBasePtr();
4757 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4759 EVT PVT = LD->getValueType(0);
4760 if (PVT != MVT::i32 && PVT != MVT::f32)
4765 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4766 FI = FINode->getIndex();
4768 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4769 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4770 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4771 Offset = Ptr.getConstantOperandVal(1);
4772 Ptr = Ptr.getOperand(0);
4777 // FIXME: 256-bit vector instructions don't require a strict alignment,
4778 // improve this code to support it better.
4779 unsigned RequiredAlign = VT.getSizeInBits()/8;
4780 SDValue Chain = LD->getChain();
4781 // Make sure the stack object alignment is at least 16 or 32.
4782 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4783 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4784 if (MFI->isFixedObjectIndex(FI)) {
4785 // Can't change the alignment. FIXME: It's possible to compute
4786 // the exact stack offset and reference FI + adjust offset instead.
4787 // If someone *really* cares about this. That's the way to implement it.
4790 MFI->setObjectAlignment(FI, RequiredAlign);
4794 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4795 // Ptr + (Offset & ~15).
4798 if ((Offset % RequiredAlign) & 3)
4800 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4802 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4803 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4805 int EltNo = (Offset - StartOffset) >> 2;
4806 int NumElems = VT.getVectorNumElements();
4808 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4809 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4810 LD->getPointerInfo().getWithOffset(StartOffset),
4811 false, false, false, 0);
4813 SmallVector<int, 8> Mask;
4814 for (int i = 0; i < NumElems; ++i)
4815 Mask.push_back(EltNo);
4817 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4823 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4824 /// vector of type 'VT', see if the elements can be replaced by a single large
4825 /// load which has the same value as a build_vector whose operands are 'elts'.
4827 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4829 /// FIXME: we'd also like to handle the case where the last elements are zero
4830 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4831 /// There's even a handy isZeroNode for that purpose.
4832 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4833 DebugLoc &DL, SelectionDAG &DAG) {
4834 EVT EltVT = VT.getVectorElementType();
4835 unsigned NumElems = Elts.size();
4837 LoadSDNode *LDBase = NULL;
4838 unsigned LastLoadedElt = -1U;
4840 // For each element in the initializer, see if we've found a load or an undef.
4841 // If we don't find an initial load element, or later load elements are
4842 // non-consecutive, bail out.
4843 for (unsigned i = 0; i < NumElems; ++i) {
4844 SDValue Elt = Elts[i];
4846 if (!Elt.getNode() ||
4847 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4850 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4852 LDBase = cast<LoadSDNode>(Elt.getNode());
4856 if (Elt.getOpcode() == ISD::UNDEF)
4859 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4860 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4865 // If we have found an entire vector of loads and undefs, then return a large
4866 // load of the entire vector width starting at the base pointer. If we found
4867 // consecutive loads for the low half, generate a vzext_load node.
4868 if (LastLoadedElt == NumElems - 1) {
4869 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4870 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4871 LDBase->getPointerInfo(),
4872 LDBase->isVolatile(), LDBase->isNonTemporal(),
4873 LDBase->isInvariant(), 0);
4874 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4875 LDBase->getPointerInfo(),
4876 LDBase->isVolatile(), LDBase->isNonTemporal(),
4877 LDBase->isInvariant(), LDBase->getAlignment());
4878 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4879 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4880 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4881 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4883 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4884 LDBase->getPointerInfo(),
4885 LDBase->getAlignment(),
4886 false/*isVolatile*/, true/*ReadMem*/,
4888 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4893 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4894 /// to generate a splat value for the following cases:
4895 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4896 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4897 /// a scalar load, or a constant.
4898 /// The VBROADCAST node is returned when a pattern is found,
4899 /// or SDValue() otherwise.
4901 X86TargetLowering::LowerVectorBroadcast(SDValue &Op, SelectionDAG &DAG) const {
4902 if (!Subtarget->hasAVX())
4905 EVT VT = Op.getValueType();
4906 DebugLoc dl = Op.getDebugLoc();
4911 switch (Op.getOpcode()) {
4913 // Unknown pattern found.
4916 case ISD::BUILD_VECTOR: {
4917 // The BUILD_VECTOR node must be a splat.
4918 if (!isSplatVector(Op.getNode()))
4921 Ld = Op.getOperand(0);
4922 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4923 Ld.getOpcode() == ISD::ConstantFP);
4925 // The suspected load node has several users. Make sure that all
4926 // of its users are from the BUILD_VECTOR node.
4927 // Constants may have multiple users.
4928 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4933 case ISD::VECTOR_SHUFFLE: {
4934 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4936 // Shuffles must have a splat mask where the first element is
4938 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4941 SDValue Sc = Op.getOperand(0);
4942 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4945 Ld = Sc.getOperand(0);
4946 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
4947 Ld.getOpcode() == ISD::ConstantFP);
4949 // The scalar_to_vector node and the suspected
4950 // load node must have exactly one user.
4951 // Constants may have multiple users.
4952 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
4958 bool Is256 = VT.getSizeInBits() == 256;
4959 bool Is128 = VT.getSizeInBits() == 128;
4961 // Handle the broadcasting a single constant scalar from the constant pool
4962 // into a vector. On Sandybridge it is still better to load a constant vector
4963 // from the constant pool and not to broadcast it from a scalar.
4964 if (ConstSplatVal && Subtarget->hasAVX2()) {
4965 EVT CVT = Ld.getValueType();
4966 assert(!CVT.isVector() && "Must not broadcast a vector type");
4967 unsigned ScalarSize = CVT.getSizeInBits();
4969 if ((Is256 && (ScalarSize == 32 || ScalarSize == 64)) ||
4970 (Is128 && (ScalarSize == 32))) {
4972 const Constant *C = 0;
4973 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
4974 C = CI->getConstantIntValue();
4975 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
4976 C = CF->getConstantFPValue();
4978 assert(C && "Invalid constant type");
4980 SDValue CP = DAG.getConstantPool(C, getPointerTy());
4981 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
4982 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
4983 MachinePointerInfo::getConstantPool(),
4984 false, false, false, Alignment);
4986 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
4990 // The scalar source must be a normal load.
4991 if (!ISD::isNormalLoad(Ld.getNode()))
4994 // Reject loads that have uses of the chain result
4995 if (Ld->hasAnyUseOfValue(1))
4998 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5000 // VBroadcast to YMM
5001 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
5002 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5004 // VBroadcast to XMM
5005 if (Is128 && (ScalarSize == 32))
5006 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5008 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5009 // double since there is vbroadcastsd xmm
5010 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
5011 // VBroadcast to YMM
5012 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
5013 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5015 // VBroadcast to XMM
5016 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
5017 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5020 // Unsupported broadcast.
5025 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5026 DebugLoc dl = Op.getDebugLoc();
5028 EVT VT = Op.getValueType();
5029 EVT ExtVT = VT.getVectorElementType();
5030 unsigned NumElems = Op.getNumOperands();
5032 // Vectors containing all zeros can be matched by pxor and xorps later
5033 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5034 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5035 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5036 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5039 return getZeroVector(VT, Subtarget, DAG, dl);
5042 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5043 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5044 // vpcmpeqd on 256-bit vectors.
5045 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5046 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
5049 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
5052 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5053 if (Broadcast.getNode())
5056 unsigned EVTBits = ExtVT.getSizeInBits();
5058 unsigned NumZero = 0;
5059 unsigned NumNonZero = 0;
5060 unsigned NonZeros = 0;
5061 bool IsAllConstants = true;
5062 SmallSet<SDValue, 8> Values;
5063 for (unsigned i = 0; i < NumElems; ++i) {
5064 SDValue Elt = Op.getOperand(i);
5065 if (Elt.getOpcode() == ISD::UNDEF)
5068 if (Elt.getOpcode() != ISD::Constant &&
5069 Elt.getOpcode() != ISD::ConstantFP)
5070 IsAllConstants = false;
5071 if (X86::isZeroNode(Elt))
5074 NonZeros |= (1 << i);
5079 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5080 if (NumNonZero == 0)
5081 return DAG.getUNDEF(VT);
5083 // Special case for single non-zero, non-undef, element.
5084 if (NumNonZero == 1) {
5085 unsigned Idx = CountTrailingZeros_32(NonZeros);
5086 SDValue Item = Op.getOperand(Idx);
5088 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5089 // the value are obviously zero, truncate the value to i32 and do the
5090 // insertion that way. Only do this if the value is non-constant or if the
5091 // value is a constant being inserted into element 0. It is cheaper to do
5092 // a constant pool load than it is to do a movd + shuffle.
5093 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5094 (!IsAllConstants || Idx == 0)) {
5095 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5097 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5098 EVT VecVT = MVT::v4i32;
5099 unsigned VecElts = 4;
5101 // Truncate the value (which may itself be a constant) to i32, and
5102 // convert it to a vector with movd (S2V+shuffle to zero extend).
5103 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5104 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5105 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5107 // Now we have our 32-bit value zero extended in the low element of
5108 // a vector. If Idx != 0, swizzle it into place.
5110 SmallVector<int, 4> Mask;
5111 Mask.push_back(Idx);
5112 for (unsigned i = 1; i != VecElts; ++i)
5114 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5117 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5121 // If we have a constant or non-constant insertion into the low element of
5122 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5123 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5124 // depending on what the source datatype is.
5127 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5129 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5130 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5131 if (VT.getSizeInBits() == 256) {
5132 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5133 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5134 Item, DAG.getIntPtrConstant(0));
5136 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5137 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5138 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5139 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5142 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5143 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5144 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5145 if (VT.getSizeInBits() == 256) {
5146 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5147 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5150 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5151 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5153 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5157 // Is it a vector logical left shift?
5158 if (NumElems == 2 && Idx == 1 &&
5159 X86::isZeroNode(Op.getOperand(0)) &&
5160 !X86::isZeroNode(Op.getOperand(1))) {
5161 unsigned NumBits = VT.getSizeInBits();
5162 return getVShift(true, VT,
5163 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5164 VT, Op.getOperand(1)),
5165 NumBits/2, DAG, *this, dl);
5168 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5171 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5172 // is a non-constant being inserted into an element other than the low one,
5173 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5174 // movd/movss) to move this into the low element, then shuffle it into
5176 if (EVTBits == 32) {
5177 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5179 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5180 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5181 SmallVector<int, 8> MaskVec;
5182 for (unsigned i = 0; i < NumElems; i++)
5183 MaskVec.push_back(i == Idx ? 0 : 1);
5184 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5188 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5189 if (Values.size() == 1) {
5190 if (EVTBits == 32) {
5191 // Instead of a shuffle like this:
5192 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5193 // Check if it's possible to issue this instead.
5194 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5195 unsigned Idx = CountTrailingZeros_32(NonZeros);
5196 SDValue Item = Op.getOperand(Idx);
5197 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5198 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5203 // A vector full of immediates; various special cases are already
5204 // handled, so this is best done with a single constant-pool load.
5208 // For AVX-length vectors, build the individual 128-bit pieces and use
5209 // shuffles to put them in place.
5210 if (VT.getSizeInBits() == 256) {
5211 SmallVector<SDValue, 32> V;
5212 for (unsigned i = 0; i != NumElems; ++i)
5213 V.push_back(Op.getOperand(i));
5215 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5217 // Build both the lower and upper subvector.
5218 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5219 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5222 // Recreate the wider vector with the lower and upper part.
5223 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5226 // Let legalizer expand 2-wide build_vectors.
5227 if (EVTBits == 64) {
5228 if (NumNonZero == 1) {
5229 // One half is zero or undef.
5230 unsigned Idx = CountTrailingZeros_32(NonZeros);
5231 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5232 Op.getOperand(Idx));
5233 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5238 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5239 if (EVTBits == 8 && NumElems == 16) {
5240 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5242 if (V.getNode()) return V;
5245 if (EVTBits == 16 && NumElems == 8) {
5246 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5248 if (V.getNode()) return V;
5251 // If element VT is == 32 bits, turn it into a number of shuffles.
5252 SmallVector<SDValue, 8> V(NumElems);
5253 if (NumElems == 4 && NumZero > 0) {
5254 for (unsigned i = 0; i < 4; ++i) {
5255 bool isZero = !(NonZeros & (1 << i));
5257 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5259 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5262 for (unsigned i = 0; i < 2; ++i) {
5263 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5266 V[i] = V[i*2]; // Must be a zero vector.
5269 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5272 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5275 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5280 bool Reverse1 = (NonZeros & 0x3) == 2;
5281 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5285 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5286 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5288 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5291 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5292 // Check for a build vector of consecutive loads.
5293 for (unsigned i = 0; i < NumElems; ++i)
5294 V[i] = Op.getOperand(i);
5296 // Check for elements which are consecutive loads.
5297 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5301 // For SSE 4.1, use insertps to put the high elements into the low element.
5302 if (getSubtarget()->hasSSE41()) {
5304 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5305 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5307 Result = DAG.getUNDEF(VT);
5309 for (unsigned i = 1; i < NumElems; ++i) {
5310 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5311 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5312 Op.getOperand(i), DAG.getIntPtrConstant(i));
5317 // Otherwise, expand into a number of unpckl*, start by extending each of
5318 // our (non-undef) elements to the full vector width with the element in the
5319 // bottom slot of the vector (which generates no code for SSE).
5320 for (unsigned i = 0; i < NumElems; ++i) {
5321 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5322 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5324 V[i] = DAG.getUNDEF(VT);
5327 // Next, we iteratively mix elements, e.g. for v4f32:
5328 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5329 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5330 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5331 unsigned EltStride = NumElems >> 1;
5332 while (EltStride != 0) {
5333 for (unsigned i = 0; i < EltStride; ++i) {
5334 // If V[i+EltStride] is undef and this is the first round of mixing,
5335 // then it is safe to just drop this shuffle: V[i] is already in the
5336 // right place, the one element (since it's the first round) being
5337 // inserted as undef can be dropped. This isn't safe for successive
5338 // rounds because they will permute elements within both vectors.
5339 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5340 EltStride == NumElems/2)
5343 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5352 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5353 // them in a MMX register. This is better than doing a stack convert.
5354 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5355 DebugLoc dl = Op.getDebugLoc();
5356 EVT ResVT = Op.getValueType();
5358 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5359 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5361 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5362 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5363 InVec = Op.getOperand(1);
5364 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5365 unsigned NumElts = ResVT.getVectorNumElements();
5366 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5367 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5368 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5370 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5371 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5372 Mask[0] = 0; Mask[1] = 2;
5373 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5375 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5378 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5379 // to create 256-bit vectors from two other 128-bit ones.
5380 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5381 DebugLoc dl = Op.getDebugLoc();
5382 EVT ResVT = Op.getValueType();
5384 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5386 SDValue V1 = Op.getOperand(0);
5387 SDValue V2 = Op.getOperand(1);
5388 unsigned NumElems = ResVT.getVectorNumElements();
5390 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5394 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5395 EVT ResVT = Op.getValueType();
5397 assert(Op.getNumOperands() == 2);
5398 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5399 "Unsupported CONCAT_VECTORS for value type");
5401 // We support concatenate two MMX registers and place them in a MMX register.
5402 // This is better than doing a stack convert.
5403 if (ResVT.is128BitVector())
5404 return LowerMMXCONCAT_VECTORS(Op, DAG);
5406 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5407 // from two other 128-bit ones.
5408 return LowerAVXCONCAT_VECTORS(Op, DAG);
5411 // Try to lower a shuffle node into a simple blend instruction.
5412 static SDValue LowerVECTOR_SHUFFLEtoBlend(SDValue Op,
5413 const X86Subtarget *Subtarget,
5414 SelectionDAG &DAG) {
5415 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5416 SDValue V1 = SVOp->getOperand(0);
5417 SDValue V2 = SVOp->getOperand(1);
5418 DebugLoc dl = SVOp->getDebugLoc();
5419 EVT VT = Op.getValueType();
5420 EVT InVT = V1.getValueType();
5421 int MaskSize = VT.getVectorNumElements();
5422 int InSize = InVT.getVectorNumElements();
5424 if (!Subtarget->hasSSE41())
5427 if (MaskSize != InSize)
5433 switch (VT.getSimpleVT().SimpleTy) {
5434 default: return SDValue();
5436 ISDNo = X86ISD::BLENDPW;
5441 ISDNo = X86ISD::BLENDPS;
5446 ISDNo = X86ISD::BLENDPD;
5451 if (!Subtarget->hasAVX())
5453 ISDNo = X86ISD::BLENDPS;
5458 if (!Subtarget->hasAVX())
5460 ISDNo = X86ISD::BLENDPD;
5464 if (!Subtarget->hasAVX2())
5466 ISDNo = X86ISD::BLENDPW;
5470 assert(ISDNo && "Invalid Op Number");
5472 unsigned MaskVals = 0;
5474 for (int i = 0; i < MaskSize; ++i) {
5475 int EltIdx = SVOp->getMaskElt(i);
5476 if (EltIdx == i || EltIdx == -1)
5478 else if (EltIdx == (i + MaskSize))
5479 continue; // Bit is set to zero;
5480 else return SDValue();
5483 V1 = DAG.getNode(ISD::BITCAST, dl, OpTy, V1);
5484 V2 = DAG.getNode(ISD::BITCAST, dl, OpTy, V2);
5485 SDValue Ret = DAG.getNode(ISDNo, dl, OpTy, V1, V2,
5486 DAG.getConstant(MaskVals, MVT::i32));
5487 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5490 // v8i16 shuffles - Prefer shuffles in the following order:
5491 // 1. [all] pshuflw, pshufhw, optional move
5492 // 2. [ssse3] 1 x pshufb
5493 // 3. [ssse3] 2 x pshufb + 1 x por
5494 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5496 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5497 SelectionDAG &DAG) const {
5498 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5499 SDValue V1 = SVOp->getOperand(0);
5500 SDValue V2 = SVOp->getOperand(1);
5501 DebugLoc dl = SVOp->getDebugLoc();
5502 SmallVector<int, 8> MaskVals;
5504 // Determine if more than 1 of the words in each of the low and high quadwords
5505 // of the result come from the same quadword of one of the two inputs. Undef
5506 // mask values count as coming from any quadword, for better codegen.
5507 unsigned LoQuad[] = { 0, 0, 0, 0 };
5508 unsigned HiQuad[] = { 0, 0, 0, 0 };
5509 std::bitset<4> InputQuads;
5510 for (unsigned i = 0; i < 8; ++i) {
5511 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5512 int EltIdx = SVOp->getMaskElt(i);
5513 MaskVals.push_back(EltIdx);
5522 InputQuads.set(EltIdx / 4);
5525 int BestLoQuad = -1;
5526 unsigned MaxQuad = 1;
5527 for (unsigned i = 0; i < 4; ++i) {
5528 if (LoQuad[i] > MaxQuad) {
5530 MaxQuad = LoQuad[i];
5534 int BestHiQuad = -1;
5536 for (unsigned i = 0; i < 4; ++i) {
5537 if (HiQuad[i] > MaxQuad) {
5539 MaxQuad = HiQuad[i];
5543 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5544 // of the two input vectors, shuffle them into one input vector so only a
5545 // single pshufb instruction is necessary. If There are more than 2 input
5546 // quads, disable the next transformation since it does not help SSSE3.
5547 bool V1Used = InputQuads[0] || InputQuads[1];
5548 bool V2Used = InputQuads[2] || InputQuads[3];
5549 if (Subtarget->hasSSSE3()) {
5550 if (InputQuads.count() == 2 && V1Used && V2Used) {
5551 BestLoQuad = InputQuads[0] ? 0 : 1;
5552 BestHiQuad = InputQuads[2] ? 2 : 3;
5554 if (InputQuads.count() > 2) {
5560 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5561 // the shuffle mask. If a quad is scored as -1, that means that it contains
5562 // words from all 4 input quadwords.
5564 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5566 BestLoQuad < 0 ? 0 : BestLoQuad,
5567 BestHiQuad < 0 ? 1 : BestHiQuad
5569 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5570 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5571 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5572 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5574 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5575 // source words for the shuffle, to aid later transformations.
5576 bool AllWordsInNewV = true;
5577 bool InOrder[2] = { true, true };
5578 for (unsigned i = 0; i != 8; ++i) {
5579 int idx = MaskVals[i];
5581 InOrder[i/4] = false;
5582 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5584 AllWordsInNewV = false;
5588 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5589 if (AllWordsInNewV) {
5590 for (int i = 0; i != 8; ++i) {
5591 int idx = MaskVals[i];
5594 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5595 if ((idx != i) && idx < 4)
5597 if ((idx != i) && idx > 3)
5606 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5607 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5608 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5609 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5610 unsigned TargetMask = 0;
5611 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5612 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5613 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5614 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5615 getShufflePSHUFLWImmediate(SVOp);
5616 V1 = NewV.getOperand(0);
5617 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5621 // If we have SSSE3, and all words of the result are from 1 input vector,
5622 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5623 // is present, fall back to case 4.
5624 if (Subtarget->hasSSSE3()) {
5625 SmallVector<SDValue,16> pshufbMask;
5627 // If we have elements from both input vectors, set the high bit of the
5628 // shuffle mask element to zero out elements that come from V2 in the V1
5629 // mask, and elements that come from V1 in the V2 mask, so that the two
5630 // results can be OR'd together.
5631 bool TwoInputs = V1Used && V2Used;
5632 for (unsigned i = 0; i != 8; ++i) {
5633 int EltIdx = MaskVals[i] * 2;
5634 if (TwoInputs && (EltIdx >= 16)) {
5635 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5636 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5639 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5640 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5642 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5643 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5644 DAG.getNode(ISD::BUILD_VECTOR, dl,
5645 MVT::v16i8, &pshufbMask[0], 16));
5647 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5649 // Calculate the shuffle mask for the second input, shuffle it, and
5650 // OR it with the first shuffled input.
5652 for (unsigned i = 0; i != 8; ++i) {
5653 int EltIdx = MaskVals[i] * 2;
5655 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5656 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5659 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5660 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5662 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5663 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5664 DAG.getNode(ISD::BUILD_VECTOR, dl,
5665 MVT::v16i8, &pshufbMask[0], 16));
5666 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5667 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5670 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5671 // and update MaskVals with new element order.
5672 std::bitset<8> InOrder;
5673 if (BestLoQuad >= 0) {
5674 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5675 for (int i = 0; i != 4; ++i) {
5676 int idx = MaskVals[i];
5679 } else if ((idx / 4) == BestLoQuad) {
5684 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5687 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5688 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5689 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5691 getShufflePSHUFLWImmediate(SVOp), DAG);
5695 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5696 // and update MaskVals with the new element order.
5697 if (BestHiQuad >= 0) {
5698 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5699 for (unsigned i = 4; i != 8; ++i) {
5700 int idx = MaskVals[i];
5703 } else if ((idx / 4) == BestHiQuad) {
5704 MaskV[i] = (idx & 3) + 4;
5708 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5711 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5712 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5713 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5715 getShufflePSHUFHWImmediate(SVOp), DAG);
5719 // In case BestHi & BestLo were both -1, which means each quadword has a word
5720 // from each of the four input quadwords, calculate the InOrder bitvector now
5721 // before falling through to the insert/extract cleanup.
5722 if (BestLoQuad == -1 && BestHiQuad == -1) {
5724 for (int i = 0; i != 8; ++i)
5725 if (MaskVals[i] < 0 || MaskVals[i] == i)
5729 // The other elements are put in the right place using pextrw and pinsrw.
5730 for (unsigned i = 0; i != 8; ++i) {
5733 int EltIdx = MaskVals[i];
5736 SDValue ExtOp = (EltIdx < 8)
5737 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5738 DAG.getIntPtrConstant(EltIdx))
5739 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5740 DAG.getIntPtrConstant(EltIdx - 8));
5741 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5742 DAG.getIntPtrConstant(i));
5747 // v16i8 shuffles - Prefer shuffles in the following order:
5748 // 1. [ssse3] 1 x pshufb
5749 // 2. [ssse3] 2 x pshufb + 1 x por
5750 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5752 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5754 const X86TargetLowering &TLI) {
5755 SDValue V1 = SVOp->getOperand(0);
5756 SDValue V2 = SVOp->getOperand(1);
5757 DebugLoc dl = SVOp->getDebugLoc();
5758 ArrayRef<int> MaskVals = SVOp->getMask();
5760 // If we have SSSE3, case 1 is generated when all result bytes come from
5761 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5762 // present, fall back to case 3.
5763 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5766 for (unsigned i = 0; i < 16; ++i) {
5767 int EltIdx = MaskVals[i];
5776 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5777 if (TLI.getSubtarget()->hasSSSE3()) {
5778 SmallVector<SDValue,16> pshufbMask;
5780 // If all result elements are from one input vector, then only translate
5781 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5783 // Otherwise, we have elements from both input vectors, and must zero out
5784 // elements that come from V2 in the first mask, and V1 in the second mask
5785 // so that we can OR them together.
5786 bool TwoInputs = !(V1Only || V2Only);
5787 for (unsigned i = 0; i != 16; ++i) {
5788 int EltIdx = MaskVals[i];
5789 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5790 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5793 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5795 // If all the elements are from V2, assign it to V1 and return after
5796 // building the first pshufb.
5799 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5800 DAG.getNode(ISD::BUILD_VECTOR, dl,
5801 MVT::v16i8, &pshufbMask[0], 16));
5805 // Calculate the shuffle mask for the second input, shuffle it, and
5806 // OR it with the first shuffled input.
5808 for (unsigned i = 0; i != 16; ++i) {
5809 int EltIdx = MaskVals[i];
5811 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5814 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5816 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5817 DAG.getNode(ISD::BUILD_VECTOR, dl,
5818 MVT::v16i8, &pshufbMask[0], 16));
5819 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5822 // No SSSE3 - Calculate in place words and then fix all out of place words
5823 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5824 // the 16 different words that comprise the two doublequadword input vectors.
5825 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5826 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5827 SDValue NewV = V2Only ? V2 : V1;
5828 for (int i = 0; i != 8; ++i) {
5829 int Elt0 = MaskVals[i*2];
5830 int Elt1 = MaskVals[i*2+1];
5832 // This word of the result is all undef, skip it.
5833 if (Elt0 < 0 && Elt1 < 0)
5836 // This word of the result is already in the correct place, skip it.
5837 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5839 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5842 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5843 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5846 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5847 // using a single extract together, load it and store it.
5848 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5849 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5850 DAG.getIntPtrConstant(Elt1 / 2));
5851 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5852 DAG.getIntPtrConstant(i));
5856 // If Elt1 is defined, extract it from the appropriate source. If the
5857 // source byte is not also odd, shift the extracted word left 8 bits
5858 // otherwise clear the bottom 8 bits if we need to do an or.
5860 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5861 DAG.getIntPtrConstant(Elt1 / 2));
5862 if ((Elt1 & 1) == 0)
5863 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5865 TLI.getShiftAmountTy(InsElt.getValueType())));
5867 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5868 DAG.getConstant(0xFF00, MVT::i16));
5870 // If Elt0 is defined, extract it from the appropriate source. If the
5871 // source byte is not also even, shift the extracted word right 8 bits. If
5872 // Elt1 was also defined, OR the extracted values together before
5873 // inserting them in the result.
5875 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5876 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5877 if ((Elt0 & 1) != 0)
5878 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5880 TLI.getShiftAmountTy(InsElt0.getValueType())));
5882 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5883 DAG.getConstant(0x00FF, MVT::i16));
5884 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5887 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5888 DAG.getIntPtrConstant(i));
5890 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5893 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5894 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5895 /// done when every pair / quad of shuffle mask elements point to elements in
5896 /// the right sequence. e.g.
5897 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5899 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5900 SelectionDAG &DAG, DebugLoc dl) {
5901 EVT VT = SVOp->getValueType(0);
5902 SDValue V1 = SVOp->getOperand(0);
5903 SDValue V2 = SVOp->getOperand(1);
5904 unsigned NumElems = VT.getVectorNumElements();
5905 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5907 switch (VT.getSimpleVT().SimpleTy) {
5908 default: llvm_unreachable("Unexpected!");
5909 case MVT::v4f32: NewVT = MVT::v2f64; break;
5910 case MVT::v4i32: NewVT = MVT::v2i64; break;
5911 case MVT::v8i16: NewVT = MVT::v4i32; break;
5912 case MVT::v16i8: NewVT = MVT::v4i32; break;
5915 int Scale = NumElems / NewWidth;
5916 SmallVector<int, 8> MaskVec;
5917 for (unsigned i = 0; i < NumElems; i += Scale) {
5919 for (int j = 0; j < Scale; ++j) {
5920 int EltIdx = SVOp->getMaskElt(i+j);
5924 StartIdx = EltIdx - (EltIdx % Scale);
5925 if (EltIdx != StartIdx + j)
5929 MaskVec.push_back(-1);
5931 MaskVec.push_back(StartIdx / Scale);
5934 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5935 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5936 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5939 /// getVZextMovL - Return a zero-extending vector move low node.
5941 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5942 SDValue SrcOp, SelectionDAG &DAG,
5943 const X86Subtarget *Subtarget, DebugLoc dl) {
5944 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5945 LoadSDNode *LD = NULL;
5946 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5947 LD = dyn_cast<LoadSDNode>(SrcOp);
5949 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5951 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5952 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5953 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5954 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5955 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5957 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5958 return DAG.getNode(ISD::BITCAST, dl, VT,
5959 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5960 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5968 return DAG.getNode(ISD::BITCAST, dl, VT,
5969 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5970 DAG.getNode(ISD::BITCAST, dl,
5974 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5975 /// which could not be matched by any known target speficic shuffle
5977 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5978 EVT VT = SVOp->getValueType(0);
5980 unsigned NumElems = VT.getVectorNumElements();
5981 unsigned NumLaneElems = NumElems / 2;
5983 DebugLoc dl = SVOp->getDebugLoc();
5984 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5985 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
5988 SmallVector<int, 16> Mask;
5989 for (unsigned l = 0; l < 2; ++l) {
5990 // Build a shuffle mask for the output, discovering on the fly which
5991 // input vectors to use as shuffle operands (recorded in InputUsed).
5992 // If building a suitable shuffle vector proves too hard, then bail
5993 // out with useBuildVector set.
5994 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
5995 unsigned LaneStart = l * NumLaneElems;
5996 for (unsigned i = 0; i != NumLaneElems; ++i) {
5997 // The mask element. This indexes into the input.
5998 int Idx = SVOp->getMaskElt(i+LaneStart);
6000 // the mask element does not index into any input vector.
6005 // The input vector this mask element indexes into.
6006 int Input = Idx / NumLaneElems;
6008 // Turn the index into an offset from the start of the input vector.
6009 Idx -= Input * NumLaneElems;
6011 // Find or create a shuffle vector operand to hold this input.
6013 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6014 if (InputUsed[OpNo] == Input)
6015 // This input vector is already an operand.
6017 if (InputUsed[OpNo] < 0) {
6018 // Create a new operand for this input vector.
6019 InputUsed[OpNo] = Input;
6024 if (OpNo >= array_lengthof(InputUsed)) {
6025 // More than two input vectors used! Give up.
6029 // Add the mask index for the new shuffle vector.
6030 Mask.push_back(Idx + OpNo * NumLaneElems);
6033 if (InputUsed[0] < 0) {
6034 // No input vectors were used! The result is undefined.
6035 Shufs[l] = DAG.getUNDEF(NVT);
6037 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6038 DAG.getConstant((InputUsed[0] % 2) * NumLaneElems, MVT::i32),
6040 // If only one input was used, use an undefined vector for the other.
6041 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6042 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6043 DAG.getConstant((InputUsed[1] % 2) * NumLaneElems, MVT::i32),
6045 // At least one input vector was used. Create a new shuffle vector.
6046 Shufs[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6052 // Concatenate the result back
6053 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Shufs[0], Shufs[1]);
6056 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6057 /// 4 elements, and match them with several different shuffle types.
6059 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6060 SDValue V1 = SVOp->getOperand(0);
6061 SDValue V2 = SVOp->getOperand(1);
6062 DebugLoc dl = SVOp->getDebugLoc();
6063 EVT VT = SVOp->getValueType(0);
6065 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6067 std::pair<int, int> Locs[4];
6068 int Mask1[] = { -1, -1, -1, -1 };
6069 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6073 for (unsigned i = 0; i != 4; ++i) {
6074 int Idx = PermMask[i];
6076 Locs[i] = std::make_pair(-1, -1);
6078 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6080 Locs[i] = std::make_pair(0, NumLo);
6084 Locs[i] = std::make_pair(1, NumHi);
6086 Mask1[2+NumHi] = Idx;
6092 if (NumLo <= 2 && NumHi <= 2) {
6093 // If no more than two elements come from either vector. This can be
6094 // implemented with two shuffles. First shuffle gather the elements.
6095 // The second shuffle, which takes the first shuffle as both of its
6096 // vector operands, put the elements into the right order.
6097 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6099 int Mask2[] = { -1, -1, -1, -1 };
6101 for (unsigned i = 0; i != 4; ++i)
6102 if (Locs[i].first != -1) {
6103 unsigned Idx = (i < 2) ? 0 : 4;
6104 Idx += Locs[i].first * 2 + Locs[i].second;
6108 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6109 } else if (NumLo == 3 || NumHi == 3) {
6110 // Otherwise, we must have three elements from one vector, call it X, and
6111 // one element from the other, call it Y. First, use a shufps to build an
6112 // intermediate vector with the one element from Y and the element from X
6113 // that will be in the same half in the final destination (the indexes don't
6114 // matter). Then, use a shufps to build the final vector, taking the half
6115 // containing the element from Y from the intermediate, and the other half
6118 // Normalize it so the 3 elements come from V1.
6119 CommuteVectorShuffleMask(PermMask, 4);
6123 // Find the element from V2.
6125 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6126 int Val = PermMask[HiIndex];
6133 Mask1[0] = PermMask[HiIndex];
6135 Mask1[2] = PermMask[HiIndex^1];
6137 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6140 Mask1[0] = PermMask[0];
6141 Mask1[1] = PermMask[1];
6142 Mask1[2] = HiIndex & 1 ? 6 : 4;
6143 Mask1[3] = HiIndex & 1 ? 4 : 6;
6144 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6146 Mask1[0] = HiIndex & 1 ? 2 : 0;
6147 Mask1[1] = HiIndex & 1 ? 0 : 2;
6148 Mask1[2] = PermMask[2];
6149 Mask1[3] = PermMask[3];
6154 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6158 // Break it into (shuffle shuffle_hi, shuffle_lo).
6159 int LoMask[] = { -1, -1, -1, -1 };
6160 int HiMask[] = { -1, -1, -1, -1 };
6162 int *MaskPtr = LoMask;
6163 unsigned MaskIdx = 0;
6166 for (unsigned i = 0; i != 4; ++i) {
6173 int Idx = PermMask[i];
6175 Locs[i] = std::make_pair(-1, -1);
6176 } else if (Idx < 4) {
6177 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6178 MaskPtr[LoIdx] = Idx;
6181 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6182 MaskPtr[HiIdx] = Idx;
6187 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6188 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6189 int MaskOps[] = { -1, -1, -1, -1 };
6190 for (unsigned i = 0; i != 4; ++i)
6191 if (Locs[i].first != -1)
6192 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6193 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6196 static bool MayFoldVectorLoad(SDValue V) {
6197 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6198 V = V.getOperand(0);
6199 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6200 V = V.getOperand(0);
6201 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6202 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6203 // BUILD_VECTOR (load), undef
6204 V = V.getOperand(0);
6210 // FIXME: the version above should always be used. Since there's
6211 // a bug where several vector shuffles can't be folded because the
6212 // DAG is not updated during lowering and a node claims to have two
6213 // uses while it only has one, use this version, and let isel match
6214 // another instruction if the load really happens to have more than
6215 // one use. Remove this version after this bug get fixed.
6216 // rdar://8434668, PR8156
6217 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6218 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6219 V = V.getOperand(0);
6220 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6221 V = V.getOperand(0);
6222 if (ISD::isNormalLoad(V.getNode()))
6228 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6229 EVT VT = Op.getValueType();
6231 // Canonizalize to v2f64.
6232 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6233 return DAG.getNode(ISD::BITCAST, dl, VT,
6234 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6239 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6241 SDValue V1 = Op.getOperand(0);
6242 SDValue V2 = Op.getOperand(1);
6243 EVT VT = Op.getValueType();
6245 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6247 if (HasSSE2 && VT == MVT::v2f64)
6248 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6250 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6251 return DAG.getNode(ISD::BITCAST, dl, VT,
6252 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6253 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6254 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6258 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6259 SDValue V1 = Op.getOperand(0);
6260 SDValue V2 = Op.getOperand(1);
6261 EVT VT = Op.getValueType();
6263 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6264 "unsupported shuffle type");
6266 if (V2.getOpcode() == ISD::UNDEF)
6270 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6274 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6275 SDValue V1 = Op.getOperand(0);
6276 SDValue V2 = Op.getOperand(1);
6277 EVT VT = Op.getValueType();
6278 unsigned NumElems = VT.getVectorNumElements();
6280 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6281 // operand of these instructions is only memory, so check if there's a
6282 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6284 bool CanFoldLoad = false;
6286 // Trivial case, when V2 comes from a load.
6287 if (MayFoldVectorLoad(V2))
6290 // When V1 is a load, it can be folded later into a store in isel, example:
6291 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6293 // (MOVLPSmr addr:$src1, VR128:$src2)
6294 // So, recognize this potential and also use MOVLPS or MOVLPD
6295 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6298 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6300 if (HasSSE2 && NumElems == 2)
6301 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6304 // If we don't care about the second element, procede to use movss.
6305 if (SVOp->getMaskElt(1) != -1)
6306 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6309 // movl and movlp will both match v2i64, but v2i64 is never matched by
6310 // movl earlier because we make it strict to avoid messing with the movlp load
6311 // folding logic (see the code above getMOVLP call). Match it here then,
6312 // this is horrible, but will stay like this until we move all shuffle
6313 // matching to x86 specific nodes. Note that for the 1st condition all
6314 // types are matched with movsd.
6316 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6317 // as to remove this logic from here, as much as possible
6318 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6319 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6320 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6323 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6325 // Invert the operand order and use SHUFPS to match it.
6326 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6327 getShuffleSHUFImmediate(SVOp), DAG);
6331 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6332 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6333 EVT VT = Op.getValueType();
6334 DebugLoc dl = Op.getDebugLoc();
6335 SDValue V1 = Op.getOperand(0);
6336 SDValue V2 = Op.getOperand(1);
6338 if (isZeroShuffle(SVOp))
6339 return getZeroVector(VT, Subtarget, DAG, dl);
6341 // Handle splat operations
6342 if (SVOp->isSplat()) {
6343 unsigned NumElem = VT.getVectorNumElements();
6344 int Size = VT.getSizeInBits();
6346 // Use vbroadcast whenever the splat comes from a foldable load
6347 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6348 if (Broadcast.getNode())
6351 // Handle splats by matching through known shuffle masks
6352 if ((Size == 128 && NumElem <= 4) ||
6353 (Size == 256 && NumElem < 8))
6356 // All remaning splats are promoted to target supported vector shuffles.
6357 return PromoteSplat(SVOp, DAG);
6360 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6362 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6363 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6364 if (NewOp.getNode())
6365 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6366 } else if ((VT == MVT::v4i32 ||
6367 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6368 // FIXME: Figure out a cleaner way to do this.
6369 // Try to make use of movq to zero out the top part.
6370 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6371 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6372 if (NewOp.getNode()) {
6373 EVT NewVT = NewOp.getValueType();
6374 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6375 NewVT, true, false))
6376 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6377 DAG, Subtarget, dl);
6379 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6380 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6381 if (NewOp.getNode()) {
6382 EVT NewVT = NewOp.getValueType();
6383 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6384 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6385 DAG, Subtarget, dl);
6393 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6395 SDValue V1 = Op.getOperand(0);
6396 SDValue V2 = Op.getOperand(1);
6397 EVT VT = Op.getValueType();
6398 DebugLoc dl = Op.getDebugLoc();
6399 unsigned NumElems = VT.getVectorNumElements();
6400 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6401 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6402 bool V1IsSplat = false;
6403 bool V2IsSplat = false;
6404 bool HasSSE2 = Subtarget->hasSSE2();
6405 bool HasAVX = Subtarget->hasAVX();
6406 bool HasAVX2 = Subtarget->hasAVX2();
6407 MachineFunction &MF = DAG.getMachineFunction();
6408 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6410 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6412 if (V1IsUndef && V2IsUndef)
6413 return DAG.getUNDEF(VT);
6415 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6417 // Vector shuffle lowering takes 3 steps:
6419 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6420 // narrowing and commutation of operands should be handled.
6421 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6423 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6424 // so the shuffle can be broken into other shuffles and the legalizer can
6425 // try the lowering again.
6427 // The general idea is that no vector_shuffle operation should be left to
6428 // be matched during isel, all of them must be converted to a target specific
6431 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6432 // narrowing and commutation of operands should be handled. The actual code
6433 // doesn't include all of those, work in progress...
6434 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6435 if (NewOp.getNode())
6438 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6440 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6441 // unpckh_undef). Only use pshufd if speed is more important than size.
6442 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6443 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6444 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6445 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6447 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6448 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6449 return getMOVDDup(Op, dl, V1, DAG);
6451 if (isMOVHLPS_v_undef_Mask(M, VT))
6452 return getMOVHighToLow(Op, dl, DAG);
6454 // Use to match splats
6455 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6456 (VT == MVT::v2f64 || VT == MVT::v2i64))
6457 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6459 if (isPSHUFDMask(M, VT)) {
6460 // The actual implementation will match the mask in the if above and then
6461 // during isel it can match several different instructions, not only pshufd
6462 // as its name says, sad but true, emulate the behavior for now...
6463 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6464 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6466 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6468 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6469 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6471 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6472 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6474 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6478 // Check if this can be converted into a logical shift.
6479 bool isLeft = false;
6482 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6483 if (isShift && ShVal.hasOneUse()) {
6484 // If the shifted value has multiple uses, it may be cheaper to use
6485 // v_set0 + movlhps or movhlps, etc.
6486 EVT EltVT = VT.getVectorElementType();
6487 ShAmt *= EltVT.getSizeInBits();
6488 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6491 if (isMOVLMask(M, VT)) {
6492 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6493 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6494 if (!isMOVLPMask(M, VT)) {
6495 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6496 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6498 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6499 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6503 // FIXME: fold these into legal mask.
6504 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6505 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6507 if (isMOVHLPSMask(M, VT))
6508 return getMOVHighToLow(Op, dl, DAG);
6510 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6511 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6513 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6514 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6516 if (isMOVLPMask(M, VT))
6517 return getMOVLP(Op, dl, DAG, HasSSE2);
6519 if (ShouldXformToMOVHLPS(M, VT) ||
6520 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6521 return CommuteVectorShuffle(SVOp, DAG);
6524 // No better options. Use a vshldq / vsrldq.
6525 EVT EltVT = VT.getVectorElementType();
6526 ShAmt *= EltVT.getSizeInBits();
6527 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6530 bool Commuted = false;
6531 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6532 // 1,1,1,1 -> v8i16 though.
6533 V1IsSplat = isSplatVector(V1.getNode());
6534 V2IsSplat = isSplatVector(V2.getNode());
6536 // Canonicalize the splat or undef, if present, to be on the RHS.
6537 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6538 CommuteVectorShuffleMask(M, NumElems);
6540 std::swap(V1IsSplat, V2IsSplat);
6544 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6545 // Shuffling low element of v1 into undef, just return v1.
6548 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6549 // the instruction selector will not match, so get a canonical MOVL with
6550 // swapped operands to undo the commute.
6551 return getMOVL(DAG, dl, VT, V2, V1);
6554 if (isUNPCKLMask(M, VT, HasAVX2))
6555 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6557 if (isUNPCKHMask(M, VT, HasAVX2))
6558 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6561 // Normalize mask so all entries that point to V2 points to its first
6562 // element then try to match unpck{h|l} again. If match, return a
6563 // new vector_shuffle with the corrected mask.p
6564 SmallVector<int, 8> NewMask(M.begin(), M.end());
6565 NormalizeMask(NewMask, NumElems);
6566 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) {
6567 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6568 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) {
6569 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6574 // Commute is back and try unpck* again.
6575 // FIXME: this seems wrong.
6576 CommuteVectorShuffleMask(M, NumElems);
6578 std::swap(V1IsSplat, V2IsSplat);
6581 if (isUNPCKLMask(M, VT, HasAVX2))
6582 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6584 if (isUNPCKHMask(M, VT, HasAVX2))
6585 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6588 // Normalize the node to match x86 shuffle ops if needed
6589 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6590 return CommuteVectorShuffle(SVOp, DAG);
6592 // The checks below are all present in isShuffleMaskLegal, but they are
6593 // inlined here right now to enable us to directly emit target specific
6594 // nodes, and remove one by one until they don't return Op anymore.
6596 if (isPALIGNRMask(M, VT, Subtarget))
6597 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6598 getShufflePALIGNRImmediate(SVOp),
6601 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6602 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6603 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6604 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6607 if (isPSHUFHWMask(M, VT))
6608 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6609 getShufflePSHUFHWImmediate(SVOp),
6612 if (isPSHUFLWMask(M, VT))
6613 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6614 getShufflePSHUFLWImmediate(SVOp),
6617 if (isSHUFPMask(M, VT, HasAVX))
6618 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6619 getShuffleSHUFImmediate(SVOp), DAG);
6621 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6622 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6623 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6624 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6626 //===--------------------------------------------------------------------===//
6627 // Generate target specific nodes for 128 or 256-bit shuffles only
6628 // supported in the AVX instruction set.
6631 // Handle VMOVDDUPY permutations
6632 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6633 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6635 // Handle VPERMILPS/D* permutations
6636 if (isVPERMILPMask(M, VT, HasAVX)) {
6637 if (HasAVX2 && VT == MVT::v8i32)
6638 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6639 getShuffleSHUFImmediate(SVOp), DAG);
6640 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6641 getShuffleSHUFImmediate(SVOp), DAG);
6644 // Handle VPERM2F128/VPERM2I128 permutations
6645 if (isVPERM2X128Mask(M, VT, HasAVX))
6646 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6647 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6649 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(Op, Subtarget, DAG);
6650 if (BlendOp.getNode())
6653 if (V2IsUndef && HasAVX2 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6654 SmallVector<SDValue, 8> permclMask;
6655 for (unsigned i = 0; i != 8; ++i) {
6656 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6658 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6660 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6661 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6662 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6665 if (V2IsUndef && HasAVX2 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6666 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6667 getShuffleCLImmediate(SVOp), DAG);
6670 //===--------------------------------------------------------------------===//
6671 // Since no target specific shuffle was selected for this generic one,
6672 // lower it into other known shuffles. FIXME: this isn't true yet, but
6673 // this is the plan.
6676 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6677 if (VT == MVT::v8i16) {
6678 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6679 if (NewOp.getNode())
6683 if (VT == MVT::v16i8) {
6684 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6685 if (NewOp.getNode())
6689 // Handle all 128-bit wide vectors with 4 elements, and match them with
6690 // several different shuffle types.
6691 if (NumElems == 4 && VT.getSizeInBits() == 128)
6692 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6694 // Handle general 256-bit shuffles
6695 if (VT.is256BitVector())
6696 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6702 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6703 SelectionDAG &DAG) const {
6704 EVT VT = Op.getValueType();
6705 DebugLoc dl = Op.getDebugLoc();
6707 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6710 if (VT.getSizeInBits() == 8) {
6711 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6712 Op.getOperand(0), Op.getOperand(1));
6713 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6714 DAG.getValueType(VT));
6715 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6716 } else if (VT.getSizeInBits() == 16) {
6717 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6718 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6720 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6721 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6722 DAG.getNode(ISD::BITCAST, dl,
6726 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6727 Op.getOperand(0), Op.getOperand(1));
6728 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6729 DAG.getValueType(VT));
6730 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6731 } else if (VT == MVT::f32) {
6732 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6733 // the result back to FR32 register. It's only worth matching if the
6734 // result has a single use which is a store or a bitcast to i32. And in
6735 // the case of a store, it's not worth it if the index is a constant 0,
6736 // because a MOVSSmr can be used instead, which is smaller and faster.
6737 if (!Op.hasOneUse())
6739 SDNode *User = *Op.getNode()->use_begin();
6740 if ((User->getOpcode() != ISD::STORE ||
6741 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6742 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6743 (User->getOpcode() != ISD::BITCAST ||
6744 User->getValueType(0) != MVT::i32))
6746 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6747 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6750 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6751 } else if (VT == MVT::i32 || VT == MVT::i64) {
6752 // ExtractPS/pextrq works with constant index.
6753 if (isa<ConstantSDNode>(Op.getOperand(1)))
6761 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6762 SelectionDAG &DAG) const {
6763 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6766 SDValue Vec = Op.getOperand(0);
6767 EVT VecVT = Vec.getValueType();
6769 // If this is a 256-bit vector result, first extract the 128-bit vector and
6770 // then extract the element from the 128-bit vector.
6771 if (VecVT.getSizeInBits() == 256) {
6772 DebugLoc dl = Op.getNode()->getDebugLoc();
6773 unsigned NumElems = VecVT.getVectorNumElements();
6774 SDValue Idx = Op.getOperand(1);
6775 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6777 // Get the 128-bit vector.
6778 bool Upper = IdxVal >= NumElems/2;
6779 Vec = Extract128BitVector(Vec,
6780 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6782 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6783 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6786 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6788 if (Subtarget->hasSSE41()) {
6789 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6794 EVT VT = Op.getValueType();
6795 DebugLoc dl = Op.getDebugLoc();
6796 // TODO: handle v16i8.
6797 if (VT.getSizeInBits() == 16) {
6798 SDValue Vec = Op.getOperand(0);
6799 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6801 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6802 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6803 DAG.getNode(ISD::BITCAST, dl,
6806 // Transform it so it match pextrw which produces a 32-bit result.
6807 EVT EltVT = MVT::i32;
6808 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6809 Op.getOperand(0), Op.getOperand(1));
6810 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6811 DAG.getValueType(VT));
6812 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6813 } else if (VT.getSizeInBits() == 32) {
6814 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6818 // SHUFPS the element to the lowest double word, then movss.
6819 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6820 EVT VVT = Op.getOperand(0).getValueType();
6821 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6822 DAG.getUNDEF(VVT), Mask);
6823 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6824 DAG.getIntPtrConstant(0));
6825 } else if (VT.getSizeInBits() == 64) {
6826 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6827 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6828 // to match extract_elt for f64.
6829 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6833 // UNPCKHPD the element to the lowest double word, then movsd.
6834 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6835 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6836 int Mask[2] = { 1, -1 };
6837 EVT VVT = Op.getOperand(0).getValueType();
6838 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6839 DAG.getUNDEF(VVT), Mask);
6840 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6841 DAG.getIntPtrConstant(0));
6848 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6849 SelectionDAG &DAG) const {
6850 EVT VT = Op.getValueType();
6851 EVT EltVT = VT.getVectorElementType();
6852 DebugLoc dl = Op.getDebugLoc();
6854 SDValue N0 = Op.getOperand(0);
6855 SDValue N1 = Op.getOperand(1);
6856 SDValue N2 = Op.getOperand(2);
6858 if (VT.getSizeInBits() == 256)
6861 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6862 isa<ConstantSDNode>(N2)) {
6864 if (VT == MVT::v8i16)
6865 Opc = X86ISD::PINSRW;
6866 else if (VT == MVT::v16i8)
6867 Opc = X86ISD::PINSRB;
6869 Opc = X86ISD::PINSRB;
6871 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6873 if (N1.getValueType() != MVT::i32)
6874 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6875 if (N2.getValueType() != MVT::i32)
6876 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6877 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6878 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6879 // Bits [7:6] of the constant are the source select. This will always be
6880 // zero here. The DAG Combiner may combine an extract_elt index into these
6881 // bits. For example (insert (extract, 3), 2) could be matched by putting
6882 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6883 // Bits [5:4] of the constant are the destination select. This is the
6884 // value of the incoming immediate.
6885 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6886 // combine either bitwise AND or insert of float 0.0 to set these bits.
6887 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6888 // Create this as a scalar to vector..
6889 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6890 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6891 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6892 isa<ConstantSDNode>(N2)) {
6893 // PINSR* works with constant index.
6900 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6901 EVT VT = Op.getValueType();
6902 EVT EltVT = VT.getVectorElementType();
6904 DebugLoc dl = Op.getDebugLoc();
6905 SDValue N0 = Op.getOperand(0);
6906 SDValue N1 = Op.getOperand(1);
6907 SDValue N2 = Op.getOperand(2);
6909 // If this is a 256-bit vector result, first extract the 128-bit vector,
6910 // insert the element into the extracted half and then place it back.
6911 if (VT.getSizeInBits() == 256) {
6912 if (!isa<ConstantSDNode>(N2))
6915 // Get the desired 128-bit vector half.
6916 unsigned NumElems = VT.getVectorNumElements();
6917 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6918 bool Upper = IdxVal >= NumElems/2;
6919 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6920 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6922 // Insert the element into the desired half.
6923 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6924 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6926 // Insert the changed part back to the 256-bit vector
6927 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6930 if (Subtarget->hasSSE41())
6931 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6933 if (EltVT == MVT::i8)
6936 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6937 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6938 // as its second argument.
6939 if (N1.getValueType() != MVT::i32)
6940 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6941 if (N2.getValueType() != MVT::i32)
6942 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6943 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6949 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6950 LLVMContext *Context = DAG.getContext();
6951 DebugLoc dl = Op.getDebugLoc();
6952 EVT OpVT = Op.getValueType();
6954 // If this is a 256-bit vector result, first insert into a 128-bit
6955 // vector and then insert into the 256-bit vector.
6956 if (OpVT.getSizeInBits() > 128) {
6957 // Insert into a 128-bit vector.
6958 EVT VT128 = EVT::getVectorVT(*Context,
6959 OpVT.getVectorElementType(),
6960 OpVT.getVectorNumElements() / 2);
6962 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6964 // Insert the 128-bit vector.
6965 return Insert128BitVector(DAG.getUNDEF(OpVT), Op,
6966 DAG.getConstant(0, MVT::i32),
6970 if (Op.getValueType() == MVT::v1i64 &&
6971 Op.getOperand(0).getValueType() == MVT::i64)
6972 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6974 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6975 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6976 "Expected an SSE type!");
6977 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6978 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6981 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6982 // a simple subregister reference or explicit instructions to grab
6983 // upper bits of a vector.
6985 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6986 if (Subtarget->hasAVX()) {
6987 DebugLoc dl = Op.getNode()->getDebugLoc();
6988 SDValue Vec = Op.getNode()->getOperand(0);
6989 SDValue Idx = Op.getNode()->getOperand(1);
6991 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6992 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6993 return Extract128BitVector(Vec, Idx, DAG, dl);
6999 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7000 // simple superregister reference or explicit instructions to insert
7001 // the upper bits of a vector.
7003 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7004 if (Subtarget->hasAVX()) {
7005 DebugLoc dl = Op.getNode()->getDebugLoc();
7006 SDValue Vec = Op.getNode()->getOperand(0);
7007 SDValue SubVec = Op.getNode()->getOperand(1);
7008 SDValue Idx = Op.getNode()->getOperand(2);
7010 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7011 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7012 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7018 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7019 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7020 // one of the above mentioned nodes. It has to be wrapped because otherwise
7021 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7022 // be used to form addressing mode. These wrapped nodes will be selected
7025 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7026 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7028 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7030 unsigned char OpFlag = 0;
7031 unsigned WrapperKind = X86ISD::Wrapper;
7032 CodeModel::Model M = getTargetMachine().getCodeModel();
7034 if (Subtarget->isPICStyleRIPRel() &&
7035 (M == CodeModel::Small || M == CodeModel::Kernel))
7036 WrapperKind = X86ISD::WrapperRIP;
7037 else if (Subtarget->isPICStyleGOT())
7038 OpFlag = X86II::MO_GOTOFF;
7039 else if (Subtarget->isPICStyleStubPIC())
7040 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7042 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7044 CP->getOffset(), OpFlag);
7045 DebugLoc DL = CP->getDebugLoc();
7046 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7047 // With PIC, the address is actually $g + Offset.
7049 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7050 DAG.getNode(X86ISD::GlobalBaseReg,
7051 DebugLoc(), getPointerTy()),
7058 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7059 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7061 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7063 unsigned char OpFlag = 0;
7064 unsigned WrapperKind = X86ISD::Wrapper;
7065 CodeModel::Model M = getTargetMachine().getCodeModel();
7067 if (Subtarget->isPICStyleRIPRel() &&
7068 (M == CodeModel::Small || M == CodeModel::Kernel))
7069 WrapperKind = X86ISD::WrapperRIP;
7070 else if (Subtarget->isPICStyleGOT())
7071 OpFlag = X86II::MO_GOTOFF;
7072 else if (Subtarget->isPICStyleStubPIC())
7073 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7075 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7077 DebugLoc DL = JT->getDebugLoc();
7078 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7080 // With PIC, the address is actually $g + Offset.
7082 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7083 DAG.getNode(X86ISD::GlobalBaseReg,
7084 DebugLoc(), getPointerTy()),
7091 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7092 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7094 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7096 unsigned char OpFlag = 0;
7097 unsigned WrapperKind = X86ISD::Wrapper;
7098 CodeModel::Model M = getTargetMachine().getCodeModel();
7100 if (Subtarget->isPICStyleRIPRel() &&
7101 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7102 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7103 OpFlag = X86II::MO_GOTPCREL;
7104 WrapperKind = X86ISD::WrapperRIP;
7105 } else if (Subtarget->isPICStyleGOT()) {
7106 OpFlag = X86II::MO_GOT;
7107 } else if (Subtarget->isPICStyleStubPIC()) {
7108 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7109 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7110 OpFlag = X86II::MO_DARWIN_NONLAZY;
7113 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7115 DebugLoc DL = Op.getDebugLoc();
7116 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7119 // With PIC, the address is actually $g + Offset.
7120 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7121 !Subtarget->is64Bit()) {
7122 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7123 DAG.getNode(X86ISD::GlobalBaseReg,
7124 DebugLoc(), getPointerTy()),
7128 // For symbols that require a load from a stub to get the address, emit the
7130 if (isGlobalStubReference(OpFlag))
7131 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7132 MachinePointerInfo::getGOT(), false, false, false, 0);
7138 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7139 // Create the TargetBlockAddressAddress node.
7140 unsigned char OpFlags =
7141 Subtarget->ClassifyBlockAddressReference();
7142 CodeModel::Model M = getTargetMachine().getCodeModel();
7143 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7144 DebugLoc dl = Op.getDebugLoc();
7145 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7146 /*isTarget=*/true, OpFlags);
7148 if (Subtarget->isPICStyleRIPRel() &&
7149 (M == CodeModel::Small || M == CodeModel::Kernel))
7150 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7152 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7154 // With PIC, the address is actually $g + Offset.
7155 if (isGlobalRelativeToPICBase(OpFlags)) {
7156 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7157 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7165 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7167 SelectionDAG &DAG) const {
7168 // Create the TargetGlobalAddress node, folding in the constant
7169 // offset if it is legal.
7170 unsigned char OpFlags =
7171 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7172 CodeModel::Model M = getTargetMachine().getCodeModel();
7174 if (OpFlags == X86II::MO_NO_FLAG &&
7175 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7176 // A direct static reference to a global.
7177 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7180 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7183 if (Subtarget->isPICStyleRIPRel() &&
7184 (M == CodeModel::Small || M == CodeModel::Kernel))
7185 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7187 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7189 // With PIC, the address is actually $g + Offset.
7190 if (isGlobalRelativeToPICBase(OpFlags)) {
7191 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7192 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7196 // For globals that require a load from a stub to get the address, emit the
7198 if (isGlobalStubReference(OpFlags))
7199 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7200 MachinePointerInfo::getGOT(), false, false, false, 0);
7202 // If there was a non-zero offset that we didn't fold, create an explicit
7205 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7206 DAG.getConstant(Offset, getPointerTy()));
7212 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7213 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7214 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7215 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7219 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7220 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7221 unsigned char OperandFlags) {
7222 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7223 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7224 DebugLoc dl = GA->getDebugLoc();
7225 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7226 GA->getValueType(0),
7230 SDValue Ops[] = { Chain, TGA, *InFlag };
7231 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7233 SDValue Ops[] = { Chain, TGA };
7234 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7237 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7238 MFI->setAdjustsStack(true);
7240 SDValue Flag = Chain.getValue(1);
7241 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7244 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7246 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7249 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7250 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7251 DAG.getNode(X86ISD::GlobalBaseReg,
7252 DebugLoc(), PtrVT), InFlag);
7253 InFlag = Chain.getValue(1);
7255 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7258 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7260 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7262 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7263 X86::RAX, X86II::MO_TLSGD);
7266 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7267 // "local exec" model.
7268 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7269 const EVT PtrVT, TLSModel::Model model,
7271 DebugLoc dl = GA->getDebugLoc();
7273 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7274 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7275 is64Bit ? 257 : 256));
7277 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7278 DAG.getIntPtrConstant(0),
7279 MachinePointerInfo(Ptr),
7280 false, false, false, 0);
7282 unsigned char OperandFlags = 0;
7283 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7285 unsigned WrapperKind = X86ISD::Wrapper;
7286 if (model == TLSModel::LocalExec) {
7287 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7288 } else if (is64Bit) {
7289 assert(model == TLSModel::InitialExec);
7290 OperandFlags = X86II::MO_GOTTPOFF;
7291 WrapperKind = X86ISD::WrapperRIP;
7293 assert(model == TLSModel::InitialExec);
7294 OperandFlags = X86II::MO_INDNTPOFF;
7297 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7299 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7300 GA->getValueType(0),
7301 GA->getOffset(), OperandFlags);
7302 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7304 if (model == TLSModel::InitialExec)
7305 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7306 MachinePointerInfo::getGOT(), false, false, false, 0);
7308 // The address of the thread local variable is the add of the thread
7309 // pointer with the offset of the variable.
7310 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7314 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7316 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7317 const GlobalValue *GV = GA->getGlobal();
7319 if (Subtarget->isTargetELF()) {
7320 // TODO: implement the "local dynamic" model
7321 // TODO: implement the "initial exec"model for pic executables
7323 // If GV is an alias then use the aliasee for determining
7324 // thread-localness.
7325 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7326 GV = GA->resolveAliasedGlobal(false);
7328 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7331 case TLSModel::GeneralDynamic:
7332 case TLSModel::LocalDynamic: // not implemented
7333 if (Subtarget->is64Bit())
7334 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7335 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7337 case TLSModel::InitialExec:
7338 case TLSModel::LocalExec:
7339 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7340 Subtarget->is64Bit());
7342 } else if (Subtarget->isTargetDarwin()) {
7343 // Darwin only has one model of TLS. Lower to that.
7344 unsigned char OpFlag = 0;
7345 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7346 X86ISD::WrapperRIP : X86ISD::Wrapper;
7348 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7350 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7351 !Subtarget->is64Bit();
7353 OpFlag = X86II::MO_TLVP_PIC_BASE;
7355 OpFlag = X86II::MO_TLVP;
7356 DebugLoc DL = Op.getDebugLoc();
7357 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7358 GA->getValueType(0),
7359 GA->getOffset(), OpFlag);
7360 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7362 // With PIC32, the address is actually $g + Offset.
7364 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7365 DAG.getNode(X86ISD::GlobalBaseReg,
7366 DebugLoc(), getPointerTy()),
7369 // Lowering the machine isd will make sure everything is in the right
7371 SDValue Chain = DAG.getEntryNode();
7372 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7373 SDValue Args[] = { Chain, Offset };
7374 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7376 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7377 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7378 MFI->setAdjustsStack(true);
7380 // And our return value (tls address) is in the standard call return value
7382 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7383 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7385 } else if (Subtarget->isTargetWindows()) {
7386 // Just use the implicit TLS architecture
7387 // Need to generate someting similar to:
7388 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7390 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7391 // mov rcx, qword [rdx+rcx*8]
7392 // mov eax, .tls$:tlsvar
7393 // [rax+rcx] contains the address
7394 // Windows 64bit: gs:0x58
7395 // Windows 32bit: fs:__tls_array
7397 // If GV is an alias then use the aliasee for determining
7398 // thread-localness.
7399 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7400 GV = GA->resolveAliasedGlobal(false);
7401 DebugLoc dl = GA->getDebugLoc();
7402 SDValue Chain = DAG.getEntryNode();
7404 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7405 // %gs:0x58 (64-bit).
7406 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7407 ? Type::getInt8PtrTy(*DAG.getContext(),
7409 : Type::getInt32PtrTy(*DAG.getContext(),
7412 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7413 Subtarget->is64Bit()
7414 ? DAG.getIntPtrConstant(0x58)
7415 : DAG.getExternalSymbol("_tls_array",
7417 MachinePointerInfo(Ptr),
7418 false, false, false, 0);
7420 // Load the _tls_index variable
7421 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7422 if (Subtarget->is64Bit())
7423 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7424 IDX, MachinePointerInfo(), MVT::i32,
7427 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7428 false, false, false, 0);
7430 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7432 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7434 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7435 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7436 false, false, false, 0);
7438 // Get the offset of start of .tls section
7439 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7440 GA->getValueType(0),
7441 GA->getOffset(), X86II::MO_SECREL);
7442 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7444 // The address of the thread local variable is the add of the thread
7445 // pointer with the offset of the variable.
7446 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7449 llvm_unreachable("TLS not implemented for this target.");
7453 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7454 /// and take a 2 x i32 value to shift plus a shift amount.
7455 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7456 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7457 EVT VT = Op.getValueType();
7458 unsigned VTBits = VT.getSizeInBits();
7459 DebugLoc dl = Op.getDebugLoc();
7460 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7461 SDValue ShOpLo = Op.getOperand(0);
7462 SDValue ShOpHi = Op.getOperand(1);
7463 SDValue ShAmt = Op.getOperand(2);
7464 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7465 DAG.getConstant(VTBits - 1, MVT::i8))
7466 : DAG.getConstant(0, VT);
7469 if (Op.getOpcode() == ISD::SHL_PARTS) {
7470 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7471 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7473 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7474 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7477 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7478 DAG.getConstant(VTBits, MVT::i8));
7479 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7480 AndNode, DAG.getConstant(0, MVT::i8));
7483 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7484 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7485 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7487 if (Op.getOpcode() == ISD::SHL_PARTS) {
7488 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7489 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7491 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7492 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7495 SDValue Ops[2] = { Lo, Hi };
7496 return DAG.getMergeValues(Ops, 2, dl);
7499 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7500 SelectionDAG &DAG) const {
7501 EVT SrcVT = Op.getOperand(0).getValueType();
7503 if (SrcVT.isVector())
7506 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7507 "Unknown SINT_TO_FP to lower!");
7509 // These are really Legal; return the operand so the caller accepts it as
7511 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7513 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7514 Subtarget->is64Bit()) {
7518 DebugLoc dl = Op.getDebugLoc();
7519 unsigned Size = SrcVT.getSizeInBits()/8;
7520 MachineFunction &MF = DAG.getMachineFunction();
7521 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7522 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7523 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7525 MachinePointerInfo::getFixedStack(SSFI),
7527 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7530 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7532 SelectionDAG &DAG) const {
7534 DebugLoc DL = Op.getDebugLoc();
7536 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7538 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7540 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7542 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7544 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7545 MachineMemOperand *MMO;
7547 int SSFI = FI->getIndex();
7549 DAG.getMachineFunction()
7550 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7551 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7553 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7554 StackSlot = StackSlot.getOperand(1);
7556 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7557 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7559 Tys, Ops, array_lengthof(Ops),
7563 Chain = Result.getValue(1);
7564 SDValue InFlag = Result.getValue(2);
7566 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7567 // shouldn't be necessary except that RFP cannot be live across
7568 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7569 MachineFunction &MF = DAG.getMachineFunction();
7570 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7571 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7572 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7573 Tys = DAG.getVTList(MVT::Other);
7575 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7577 MachineMemOperand *MMO =
7578 DAG.getMachineFunction()
7579 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7580 MachineMemOperand::MOStore, SSFISize, SSFISize);
7582 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7583 Ops, array_lengthof(Ops),
7584 Op.getValueType(), MMO);
7585 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7586 MachinePointerInfo::getFixedStack(SSFI),
7587 false, false, false, 0);
7593 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7594 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7595 SelectionDAG &DAG) const {
7596 // This algorithm is not obvious. Here it is what we're trying to output:
7599 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7600 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7604 pshufd $0x4e, %xmm0, %xmm1
7609 DebugLoc dl = Op.getDebugLoc();
7610 LLVMContext *Context = DAG.getContext();
7612 // Build some magic constants.
7613 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7614 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7615 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7617 SmallVector<Constant*,2> CV1;
7619 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7621 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7622 Constant *C1 = ConstantVector::get(CV1);
7623 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7625 // Load the 64-bit value into an XMM register.
7626 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7628 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7629 MachinePointerInfo::getConstantPool(),
7630 false, false, false, 16);
7631 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7632 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7635 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7636 MachinePointerInfo::getConstantPool(),
7637 false, false, false, 16);
7638 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7639 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7642 if (Subtarget->hasSSE3()) {
7643 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7644 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7646 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7647 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7649 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7650 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7654 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7655 DAG.getIntPtrConstant(0));
7658 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7659 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7660 SelectionDAG &DAG) const {
7661 DebugLoc dl = Op.getDebugLoc();
7662 // FP constant to bias correct the final result.
7663 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7666 // Load the 32-bit value into an XMM register.
7667 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7670 // Zero out the upper parts of the register.
7671 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7673 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7674 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7675 DAG.getIntPtrConstant(0));
7677 // Or the load with the bias.
7678 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7679 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7680 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7682 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7683 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7684 MVT::v2f64, Bias)));
7685 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7686 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7687 DAG.getIntPtrConstant(0));
7689 // Subtract the bias.
7690 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7692 // Handle final rounding.
7693 EVT DestVT = Op.getValueType();
7695 if (DestVT.bitsLT(MVT::f64)) {
7696 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7697 DAG.getIntPtrConstant(0));
7698 } else if (DestVT.bitsGT(MVT::f64)) {
7699 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7702 // Handle final rounding.
7706 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7707 SelectionDAG &DAG) const {
7708 SDValue N0 = Op.getOperand(0);
7709 DebugLoc dl = Op.getDebugLoc();
7711 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7712 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7713 // the optimization here.
7714 if (DAG.SignBitIsZero(N0))
7715 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7717 EVT SrcVT = N0.getValueType();
7718 EVT DstVT = Op.getValueType();
7719 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7720 return LowerUINT_TO_FP_i64(Op, DAG);
7721 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7722 return LowerUINT_TO_FP_i32(Op, DAG);
7723 else if (Subtarget->is64Bit() &&
7724 SrcVT == MVT::i64 && DstVT == MVT::f32)
7727 // Make a 64-bit buffer, and use it to build an FILD.
7728 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7729 if (SrcVT == MVT::i32) {
7730 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7731 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7732 getPointerTy(), StackSlot, WordOff);
7733 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7734 StackSlot, MachinePointerInfo(),
7736 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7737 OffsetSlot, MachinePointerInfo(),
7739 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7743 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7744 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7745 StackSlot, MachinePointerInfo(),
7747 // For i64 source, we need to add the appropriate power of 2 if the input
7748 // was negative. This is the same as the optimization in
7749 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7750 // we must be careful to do the computation in x87 extended precision, not
7751 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7752 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7753 MachineMemOperand *MMO =
7754 DAG.getMachineFunction()
7755 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7756 MachineMemOperand::MOLoad, 8, 8);
7758 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7759 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7760 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7763 APInt FF(32, 0x5F800000ULL);
7765 // Check whether the sign bit is set.
7766 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7767 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7770 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7771 SDValue FudgePtr = DAG.getConstantPool(
7772 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7775 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7776 SDValue Zero = DAG.getIntPtrConstant(0);
7777 SDValue Four = DAG.getIntPtrConstant(4);
7778 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7780 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7782 // Load the value out, extending it from f32 to f80.
7783 // FIXME: Avoid the extend by constructing the right constant pool?
7784 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7785 FudgePtr, MachinePointerInfo::getConstantPool(),
7786 MVT::f32, false, false, 4);
7787 // Extend everything to 80 bits to force it to be done on x87.
7788 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7789 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7792 std::pair<SDValue,SDValue> X86TargetLowering::
7793 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7794 DebugLoc DL = Op.getDebugLoc();
7796 EVT DstTy = Op.getValueType();
7798 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7799 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7803 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7804 DstTy.getSimpleVT() >= MVT::i16 &&
7805 "Unknown FP_TO_INT to lower!");
7807 // These are really Legal.
7808 if (DstTy == MVT::i32 &&
7809 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7810 return std::make_pair(SDValue(), SDValue());
7811 if (Subtarget->is64Bit() &&
7812 DstTy == MVT::i64 &&
7813 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7814 return std::make_pair(SDValue(), SDValue());
7816 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7817 // stack slot, or into the FTOL runtime function.
7818 MachineFunction &MF = DAG.getMachineFunction();
7819 unsigned MemSize = DstTy.getSizeInBits()/8;
7820 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7821 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7824 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7825 Opc = X86ISD::WIN_FTOL;
7827 switch (DstTy.getSimpleVT().SimpleTy) {
7828 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7829 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7830 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7831 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7834 SDValue Chain = DAG.getEntryNode();
7835 SDValue Value = Op.getOperand(0);
7836 EVT TheVT = Op.getOperand(0).getValueType();
7837 // FIXME This causes a redundant load/store if the SSE-class value is already
7838 // in memory, such as if it is on the callstack.
7839 if (isScalarFPTypeInSSEReg(TheVT)) {
7840 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7841 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7842 MachinePointerInfo::getFixedStack(SSFI),
7844 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7846 Chain, StackSlot, DAG.getValueType(TheVT)
7849 MachineMemOperand *MMO =
7850 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7851 MachineMemOperand::MOLoad, MemSize, MemSize);
7852 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7854 Chain = Value.getValue(1);
7855 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7856 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7859 MachineMemOperand *MMO =
7860 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7861 MachineMemOperand::MOStore, MemSize, MemSize);
7863 if (Opc != X86ISD::WIN_FTOL) {
7864 // Build the FP_TO_INT*_IN_MEM
7865 SDValue Ops[] = { Chain, Value, StackSlot };
7866 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7867 Ops, 3, DstTy, MMO);
7868 return std::make_pair(FIST, StackSlot);
7870 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7871 DAG.getVTList(MVT::Other, MVT::Glue),
7873 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7874 MVT::i32, ftol.getValue(1));
7875 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7876 MVT::i32, eax.getValue(2));
7877 SDValue Ops[] = { eax, edx };
7878 SDValue pair = IsReplace
7879 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7880 : DAG.getMergeValues(Ops, 2, DL);
7881 return std::make_pair(pair, SDValue());
7885 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7886 SelectionDAG &DAG) const {
7887 if (Op.getValueType().isVector())
7890 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7891 /*IsSigned=*/ true, /*IsReplace=*/ false);
7892 SDValue FIST = Vals.first, StackSlot = Vals.second;
7893 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7894 if (FIST.getNode() == 0) return Op;
7896 if (StackSlot.getNode())
7898 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7899 FIST, StackSlot, MachinePointerInfo(),
7900 false, false, false, 0);
7902 // The node is the result.
7906 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7907 SelectionDAG &DAG) const {
7908 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7909 /*IsSigned=*/ false, /*IsReplace=*/ false);
7910 SDValue FIST = Vals.first, StackSlot = Vals.second;
7911 assert(FIST.getNode() && "Unexpected failure");
7913 if (StackSlot.getNode())
7915 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7916 FIST, StackSlot, MachinePointerInfo(),
7917 false, false, false, 0);
7919 // The node is the result.
7923 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7924 SelectionDAG &DAG) const {
7925 LLVMContext *Context = DAG.getContext();
7926 DebugLoc dl = Op.getDebugLoc();
7927 EVT VT = Op.getValueType();
7930 EltVT = VT.getVectorElementType();
7932 if (EltVT == MVT::f64) {
7933 C = ConstantVector::getSplat(2,
7934 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7936 C = ConstantVector::getSplat(4,
7937 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7939 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7940 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7941 MachinePointerInfo::getConstantPool(),
7942 false, false, false, 16);
7943 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7946 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7947 LLVMContext *Context = DAG.getContext();
7948 DebugLoc dl = Op.getDebugLoc();
7949 EVT VT = Op.getValueType();
7951 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7952 if (VT.isVector()) {
7953 EltVT = VT.getVectorElementType();
7954 NumElts = VT.getVectorNumElements();
7957 if (EltVT == MVT::f64)
7958 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7960 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7961 C = ConstantVector::getSplat(NumElts, C);
7962 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7963 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7964 MachinePointerInfo::getConstantPool(),
7965 false, false, false, 16);
7966 if (VT.isVector()) {
7967 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7968 return DAG.getNode(ISD::BITCAST, dl, VT,
7969 DAG.getNode(ISD::XOR, dl, XORVT,
7970 DAG.getNode(ISD::BITCAST, dl, XORVT,
7972 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7974 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7978 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7979 LLVMContext *Context = DAG.getContext();
7980 SDValue Op0 = Op.getOperand(0);
7981 SDValue Op1 = Op.getOperand(1);
7982 DebugLoc dl = Op.getDebugLoc();
7983 EVT VT = Op.getValueType();
7984 EVT SrcVT = Op1.getValueType();
7986 // If second operand is smaller, extend it first.
7987 if (SrcVT.bitsLT(VT)) {
7988 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7991 // And if it is bigger, shrink it first.
7992 if (SrcVT.bitsGT(VT)) {
7993 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7997 // At this point the operands and the result should have the same
7998 // type, and that won't be f80 since that is not custom lowered.
8000 // First get the sign bit of second operand.
8001 SmallVector<Constant*,4> CV;
8002 if (SrcVT == MVT::f64) {
8003 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8004 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8006 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8007 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8008 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8009 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8011 Constant *C = ConstantVector::get(CV);
8012 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8013 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8014 MachinePointerInfo::getConstantPool(),
8015 false, false, false, 16);
8016 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8018 // Shift sign bit right or left if the two operands have different types.
8019 if (SrcVT.bitsGT(VT)) {
8020 // Op0 is MVT::f32, Op1 is MVT::f64.
8021 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8022 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8023 DAG.getConstant(32, MVT::i32));
8024 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8025 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8026 DAG.getIntPtrConstant(0));
8029 // Clear first operand sign bit.
8031 if (VT == MVT::f64) {
8032 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8033 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8035 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8036 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8037 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8038 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8040 C = ConstantVector::get(CV);
8041 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8042 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8043 MachinePointerInfo::getConstantPool(),
8044 false, false, false, 16);
8045 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8047 // Or the value with the sign bit.
8048 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8051 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8052 SDValue N0 = Op.getOperand(0);
8053 DebugLoc dl = Op.getDebugLoc();
8054 EVT VT = Op.getValueType();
8056 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8057 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8058 DAG.getConstant(1, VT));
8059 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8062 /// Emit nodes that will be selected as "test Op0,Op0", or something
8064 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8065 SelectionDAG &DAG) const {
8066 DebugLoc dl = Op.getDebugLoc();
8068 // CF and OF aren't always set the way we want. Determine which
8069 // of these we need.
8070 bool NeedCF = false;
8071 bool NeedOF = false;
8074 case X86::COND_A: case X86::COND_AE:
8075 case X86::COND_B: case X86::COND_BE:
8078 case X86::COND_G: case X86::COND_GE:
8079 case X86::COND_L: case X86::COND_LE:
8080 case X86::COND_O: case X86::COND_NO:
8085 // See if we can use the EFLAGS value from the operand instead of
8086 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8087 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8088 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8089 // Emit a CMP with 0, which is the TEST pattern.
8090 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8091 DAG.getConstant(0, Op.getValueType()));
8093 unsigned Opcode = 0;
8094 unsigned NumOperands = 0;
8095 switch (Op.getNode()->getOpcode()) {
8097 // Due to an isel shortcoming, be conservative if this add is likely to be
8098 // selected as part of a load-modify-store instruction. When the root node
8099 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8100 // uses of other nodes in the match, such as the ADD in this case. This
8101 // leads to the ADD being left around and reselected, with the result being
8102 // two adds in the output. Alas, even if none our users are stores, that
8103 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8104 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8105 // climbing the DAG back to the root, and it doesn't seem to be worth the
8107 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8108 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8109 if (UI->getOpcode() != ISD::CopyToReg &&
8110 UI->getOpcode() != ISD::SETCC &&
8111 UI->getOpcode() != ISD::STORE)
8114 if (ConstantSDNode *C =
8115 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8116 // An add of one will be selected as an INC.
8117 if (C->getAPIntValue() == 1) {
8118 Opcode = X86ISD::INC;
8123 // An add of negative one (subtract of one) will be selected as a DEC.
8124 if (C->getAPIntValue().isAllOnesValue()) {
8125 Opcode = X86ISD::DEC;
8131 // Otherwise use a regular EFLAGS-setting add.
8132 Opcode = X86ISD::ADD;
8136 // If the primary and result isn't used, don't bother using X86ISD::AND,
8137 // because a TEST instruction will be better.
8138 bool NonFlagUse = false;
8139 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8140 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8142 unsigned UOpNo = UI.getOperandNo();
8143 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8144 // Look pass truncate.
8145 UOpNo = User->use_begin().getOperandNo();
8146 User = *User->use_begin();
8149 if (User->getOpcode() != ISD::BRCOND &&
8150 User->getOpcode() != ISD::SETCC &&
8151 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8164 // Due to the ISEL shortcoming noted above, be conservative if this op is
8165 // likely to be selected as part of a load-modify-store instruction.
8166 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8167 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8168 if (UI->getOpcode() == ISD::STORE)
8171 // Otherwise use a regular EFLAGS-setting instruction.
8172 switch (Op.getNode()->getOpcode()) {
8173 default: llvm_unreachable("unexpected operator!");
8174 case ISD::SUB: Opcode = X86ISD::SUB; break;
8175 case ISD::OR: Opcode = X86ISD::OR; break;
8176 case ISD::XOR: Opcode = X86ISD::XOR; break;
8177 case ISD::AND: Opcode = X86ISD::AND; break;
8189 return SDValue(Op.getNode(), 1);
8196 // Emit a CMP with 0, which is the TEST pattern.
8197 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8198 DAG.getConstant(0, Op.getValueType()));
8200 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8201 SmallVector<SDValue, 4> Ops;
8202 for (unsigned i = 0; i != NumOperands; ++i)
8203 Ops.push_back(Op.getOperand(i));
8205 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8206 DAG.ReplaceAllUsesWith(Op, New);
8207 return SDValue(New.getNode(), 1);
8210 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8212 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8213 SelectionDAG &DAG) const {
8214 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8215 if (C->getAPIntValue() == 0)
8216 return EmitTest(Op0, X86CC, DAG);
8218 DebugLoc dl = Op0.getDebugLoc();
8219 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8222 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8223 /// if it's possible.
8224 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8225 DebugLoc dl, SelectionDAG &DAG) const {
8226 SDValue Op0 = And.getOperand(0);
8227 SDValue Op1 = And.getOperand(1);
8228 if (Op0.getOpcode() == ISD::TRUNCATE)
8229 Op0 = Op0.getOperand(0);
8230 if (Op1.getOpcode() == ISD::TRUNCATE)
8231 Op1 = Op1.getOperand(0);
8234 if (Op1.getOpcode() == ISD::SHL)
8235 std::swap(Op0, Op1);
8236 if (Op0.getOpcode() == ISD::SHL) {
8237 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8238 if (And00C->getZExtValue() == 1) {
8239 // If we looked past a truncate, check that it's only truncating away
8241 unsigned BitWidth = Op0.getValueSizeInBits();
8242 unsigned AndBitWidth = And.getValueSizeInBits();
8243 if (BitWidth > AndBitWidth) {
8245 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
8246 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8250 RHS = Op0.getOperand(1);
8252 } else if (Op1.getOpcode() == ISD::Constant) {
8253 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8254 uint64_t AndRHSVal = AndRHS->getZExtValue();
8255 SDValue AndLHS = Op0;
8257 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8258 LHS = AndLHS.getOperand(0);
8259 RHS = AndLHS.getOperand(1);
8262 // Use BT if the immediate can't be encoded in a TEST instruction.
8263 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8265 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8269 if (LHS.getNode()) {
8270 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8271 // instruction. Since the shift amount is in-range-or-undefined, we know
8272 // that doing a bittest on the i32 value is ok. We extend to i32 because
8273 // the encoding for the i16 version is larger than the i32 version.
8274 // Also promote i16 to i32 for performance / code size reason.
8275 if (LHS.getValueType() == MVT::i8 ||
8276 LHS.getValueType() == MVT::i16)
8277 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8279 // If the operand types disagree, extend the shift amount to match. Since
8280 // BT ignores high bits (like shifts) we can use anyextend.
8281 if (LHS.getValueType() != RHS.getValueType())
8282 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8284 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8285 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8286 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8287 DAG.getConstant(Cond, MVT::i8), BT);
8293 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8295 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8297 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8298 SDValue Op0 = Op.getOperand(0);
8299 SDValue Op1 = Op.getOperand(1);
8300 DebugLoc dl = Op.getDebugLoc();
8301 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8303 // Optimize to BT if possible.
8304 // Lower (X & (1 << N)) == 0 to BT(X, N).
8305 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8306 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8307 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8308 Op1.getOpcode() == ISD::Constant &&
8309 cast<ConstantSDNode>(Op1)->isNullValue() &&
8310 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8311 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8312 if (NewSetCC.getNode())
8316 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8318 if (Op1.getOpcode() == ISD::Constant &&
8319 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8320 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8321 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8323 // If the input is a setcc, then reuse the input setcc or use a new one with
8324 // the inverted condition.
8325 if (Op0.getOpcode() == X86ISD::SETCC) {
8326 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8327 bool Invert = (CC == ISD::SETNE) ^
8328 cast<ConstantSDNode>(Op1)->isNullValue();
8329 if (!Invert) return Op0;
8331 CCode = X86::GetOppositeBranchCondition(CCode);
8332 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8333 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8337 bool isFP = Op1.getValueType().isFloatingPoint();
8338 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8339 if (X86CC == X86::COND_INVALID)
8342 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8343 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8344 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8347 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8348 // ones, and then concatenate the result back.
8349 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8350 EVT VT = Op.getValueType();
8352 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8353 "Unsupported value type for operation");
8355 int NumElems = VT.getVectorNumElements();
8356 DebugLoc dl = Op.getDebugLoc();
8357 SDValue CC = Op.getOperand(2);
8358 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8359 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8361 // Extract the LHS vectors
8362 SDValue LHS = Op.getOperand(0);
8363 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8364 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8366 // Extract the RHS vectors
8367 SDValue RHS = Op.getOperand(1);
8368 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8369 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8371 // Issue the operation on the smaller types and concatenate the result back
8372 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8373 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8374 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8375 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8376 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8380 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8382 SDValue Op0 = Op.getOperand(0);
8383 SDValue Op1 = Op.getOperand(1);
8384 SDValue CC = Op.getOperand(2);
8385 EVT VT = Op.getValueType();
8386 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8387 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8388 DebugLoc dl = Op.getDebugLoc();
8392 EVT EltVT = Op0.getValueType().getVectorElementType();
8393 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8397 // SSE Condition code mapping:
8406 switch (SetCCOpcode) {
8409 case ISD::SETEQ: SSECC = 0; break;
8411 case ISD::SETGT: Swap = true; // Fallthrough
8413 case ISD::SETOLT: SSECC = 1; break;
8415 case ISD::SETGE: Swap = true; // Fallthrough
8417 case ISD::SETOLE: SSECC = 2; break;
8418 case ISD::SETUO: SSECC = 3; break;
8420 case ISD::SETNE: SSECC = 4; break;
8421 case ISD::SETULE: Swap = true;
8422 case ISD::SETUGE: SSECC = 5; break;
8423 case ISD::SETULT: Swap = true;
8424 case ISD::SETUGT: SSECC = 6; break;
8425 case ISD::SETO: SSECC = 7; break;
8428 std::swap(Op0, Op1);
8430 // In the two special cases we can't handle, emit two comparisons.
8432 if (SetCCOpcode == ISD::SETUEQ) {
8434 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8435 DAG.getConstant(3, MVT::i8));
8436 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8437 DAG.getConstant(0, MVT::i8));
8438 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8439 } else if (SetCCOpcode == ISD::SETONE) {
8441 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8442 DAG.getConstant(7, MVT::i8));
8443 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8444 DAG.getConstant(4, MVT::i8));
8445 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8447 llvm_unreachable("Illegal FP comparison");
8449 // Handle all other FP comparisons here.
8450 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8451 DAG.getConstant(SSECC, MVT::i8));
8454 // Break 256-bit integer vector compare into smaller ones.
8455 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8456 return Lower256IntVSETCC(Op, DAG);
8458 // We are handling one of the integer comparisons here. Since SSE only has
8459 // GT and EQ comparisons for integer, swapping operands and multiple
8460 // operations may be required for some comparisons.
8462 bool Swap = false, Invert = false, FlipSigns = false;
8464 switch (SetCCOpcode) {
8466 case ISD::SETNE: Invert = true;
8467 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8468 case ISD::SETLT: Swap = true;
8469 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8470 case ISD::SETGE: Swap = true;
8471 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8472 case ISD::SETULT: Swap = true;
8473 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8474 case ISD::SETUGE: Swap = true;
8475 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8478 std::swap(Op0, Op1);
8480 // Check that the operation in question is available (most are plain SSE2,
8481 // but PCMPGTQ and PCMPEQQ have different requirements).
8482 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8484 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8487 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8488 // bits of the inputs before performing those operations.
8490 EVT EltVT = VT.getVectorElementType();
8491 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8493 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8494 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8496 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8497 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8500 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8502 // If the logical-not of the result is required, perform that now.
8504 Result = DAG.getNOT(dl, Result, VT);
8509 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8510 static bool isX86LogicalCmp(SDValue Op) {
8511 unsigned Opc = Op.getNode()->getOpcode();
8512 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8514 if (Op.getResNo() == 1 &&
8515 (Opc == X86ISD::ADD ||
8516 Opc == X86ISD::SUB ||
8517 Opc == X86ISD::ADC ||
8518 Opc == X86ISD::SBB ||
8519 Opc == X86ISD::SMUL ||
8520 Opc == X86ISD::UMUL ||
8521 Opc == X86ISD::INC ||
8522 Opc == X86ISD::DEC ||
8523 Opc == X86ISD::OR ||
8524 Opc == X86ISD::XOR ||
8525 Opc == X86ISD::AND))
8528 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8534 static bool isZero(SDValue V) {
8535 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8536 return C && C->isNullValue();
8539 static bool isAllOnes(SDValue V) {
8540 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8541 return C && C->isAllOnesValue();
8544 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8545 bool addTest = true;
8546 SDValue Cond = Op.getOperand(0);
8547 SDValue Op1 = Op.getOperand(1);
8548 SDValue Op2 = Op.getOperand(2);
8549 DebugLoc DL = Op.getDebugLoc();
8552 if (Cond.getOpcode() == ISD::SETCC) {
8553 SDValue NewCond = LowerSETCC(Cond, DAG);
8554 if (NewCond.getNode())
8558 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8559 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8560 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8561 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8562 if (Cond.getOpcode() == X86ISD::SETCC &&
8563 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8564 isZero(Cond.getOperand(1).getOperand(1))) {
8565 SDValue Cmp = Cond.getOperand(1);
8567 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8569 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8570 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8571 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8573 SDValue CmpOp0 = Cmp.getOperand(0);
8574 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8575 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8577 SDValue Res = // Res = 0 or -1.
8578 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8579 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8581 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8582 Res = DAG.getNOT(DL, Res, Res.getValueType());
8584 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8585 if (N2C == 0 || !N2C->isNullValue())
8586 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8591 // Look past (and (setcc_carry (cmp ...)), 1).
8592 if (Cond.getOpcode() == ISD::AND &&
8593 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8595 if (C && C->getAPIntValue() == 1)
8596 Cond = Cond.getOperand(0);
8599 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8600 // setting operand in place of the X86ISD::SETCC.
8601 unsigned CondOpcode = Cond.getOpcode();
8602 if (CondOpcode == X86ISD::SETCC ||
8603 CondOpcode == X86ISD::SETCC_CARRY) {
8604 CC = Cond.getOperand(0);
8606 SDValue Cmp = Cond.getOperand(1);
8607 unsigned Opc = Cmp.getOpcode();
8608 EVT VT = Op.getValueType();
8610 bool IllegalFPCMov = false;
8611 if (VT.isFloatingPoint() && !VT.isVector() &&
8612 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8613 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8615 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8616 Opc == X86ISD::BT) { // FIXME
8620 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8621 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8622 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8623 Cond.getOperand(0).getValueType() != MVT::i8)) {
8624 SDValue LHS = Cond.getOperand(0);
8625 SDValue RHS = Cond.getOperand(1);
8629 switch (CondOpcode) {
8630 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8631 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8632 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8633 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8634 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8635 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8636 default: llvm_unreachable("unexpected overflowing operator");
8638 if (CondOpcode == ISD::UMULO)
8639 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8642 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8644 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8646 if (CondOpcode == ISD::UMULO)
8647 Cond = X86Op.getValue(2);
8649 Cond = X86Op.getValue(1);
8651 CC = DAG.getConstant(X86Cond, MVT::i8);
8656 // Look pass the truncate.
8657 if (Cond.getOpcode() == ISD::TRUNCATE)
8658 Cond = Cond.getOperand(0);
8660 // We know the result of AND is compared against zero. Try to match
8662 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8663 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8664 if (NewSetCC.getNode()) {
8665 CC = NewSetCC.getOperand(0);
8666 Cond = NewSetCC.getOperand(1);
8673 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8674 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8677 // a < b ? -1 : 0 -> RES = ~setcc_carry
8678 // a < b ? 0 : -1 -> RES = setcc_carry
8679 // a >= b ? -1 : 0 -> RES = setcc_carry
8680 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8681 if (Cond.getOpcode() == X86ISD::CMP) {
8682 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8684 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8685 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8686 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8687 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8688 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8689 return DAG.getNOT(DL, Res, Res.getValueType());
8694 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8695 // condition is true.
8696 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8697 SDValue Ops[] = { Op2, Op1, CC, Cond };
8698 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8701 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8702 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8703 // from the AND / OR.
8704 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8705 Opc = Op.getOpcode();
8706 if (Opc != ISD::OR && Opc != ISD::AND)
8708 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8709 Op.getOperand(0).hasOneUse() &&
8710 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8711 Op.getOperand(1).hasOneUse());
8714 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8715 // 1 and that the SETCC node has a single use.
8716 static bool isXor1OfSetCC(SDValue Op) {
8717 if (Op.getOpcode() != ISD::XOR)
8719 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8720 if (N1C && N1C->getAPIntValue() == 1) {
8721 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8722 Op.getOperand(0).hasOneUse();
8727 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8728 bool addTest = true;
8729 SDValue Chain = Op.getOperand(0);
8730 SDValue Cond = Op.getOperand(1);
8731 SDValue Dest = Op.getOperand(2);
8732 DebugLoc dl = Op.getDebugLoc();
8734 bool Inverted = false;
8736 if (Cond.getOpcode() == ISD::SETCC) {
8737 // Check for setcc([su]{add,sub,mul}o == 0).
8738 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8739 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8740 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8741 Cond.getOperand(0).getResNo() == 1 &&
8742 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8743 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8744 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8745 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8746 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8747 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8749 Cond = Cond.getOperand(0);
8751 SDValue NewCond = LowerSETCC(Cond, DAG);
8752 if (NewCond.getNode())
8757 // FIXME: LowerXALUO doesn't handle these!!
8758 else if (Cond.getOpcode() == X86ISD::ADD ||
8759 Cond.getOpcode() == X86ISD::SUB ||
8760 Cond.getOpcode() == X86ISD::SMUL ||
8761 Cond.getOpcode() == X86ISD::UMUL)
8762 Cond = LowerXALUO(Cond, DAG);
8765 // Look pass (and (setcc_carry (cmp ...)), 1).
8766 if (Cond.getOpcode() == ISD::AND &&
8767 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8768 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8769 if (C && C->getAPIntValue() == 1)
8770 Cond = Cond.getOperand(0);
8773 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8774 // setting operand in place of the X86ISD::SETCC.
8775 unsigned CondOpcode = Cond.getOpcode();
8776 if (CondOpcode == X86ISD::SETCC ||
8777 CondOpcode == X86ISD::SETCC_CARRY) {
8778 CC = Cond.getOperand(0);
8780 SDValue Cmp = Cond.getOperand(1);
8781 unsigned Opc = Cmp.getOpcode();
8782 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8783 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8787 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8791 // These can only come from an arithmetic instruction with overflow,
8792 // e.g. SADDO, UADDO.
8793 Cond = Cond.getNode()->getOperand(1);
8799 CondOpcode = Cond.getOpcode();
8800 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8801 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8802 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8803 Cond.getOperand(0).getValueType() != MVT::i8)) {
8804 SDValue LHS = Cond.getOperand(0);
8805 SDValue RHS = Cond.getOperand(1);
8809 switch (CondOpcode) {
8810 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8811 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8812 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8813 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8814 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8815 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8816 default: llvm_unreachable("unexpected overflowing operator");
8819 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8820 if (CondOpcode == ISD::UMULO)
8821 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8824 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8826 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8828 if (CondOpcode == ISD::UMULO)
8829 Cond = X86Op.getValue(2);
8831 Cond = X86Op.getValue(1);
8833 CC = DAG.getConstant(X86Cond, MVT::i8);
8837 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8838 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8839 if (CondOpc == ISD::OR) {
8840 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8841 // two branches instead of an explicit OR instruction with a
8843 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8844 isX86LogicalCmp(Cmp)) {
8845 CC = Cond.getOperand(0).getOperand(0);
8846 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8847 Chain, Dest, CC, Cmp);
8848 CC = Cond.getOperand(1).getOperand(0);
8852 } else { // ISD::AND
8853 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8854 // two branches instead of an explicit AND instruction with a
8855 // separate test. However, we only do this if this block doesn't
8856 // have a fall-through edge, because this requires an explicit
8857 // jmp when the condition is false.
8858 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8859 isX86LogicalCmp(Cmp) &&
8860 Op.getNode()->hasOneUse()) {
8861 X86::CondCode CCode =
8862 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8863 CCode = X86::GetOppositeBranchCondition(CCode);
8864 CC = DAG.getConstant(CCode, MVT::i8);
8865 SDNode *User = *Op.getNode()->use_begin();
8866 // Look for an unconditional branch following this conditional branch.
8867 // We need this because we need to reverse the successors in order
8868 // to implement FCMP_OEQ.
8869 if (User->getOpcode() == ISD::BR) {
8870 SDValue FalseBB = User->getOperand(1);
8872 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8873 assert(NewBR == User);
8877 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8878 Chain, Dest, CC, Cmp);
8879 X86::CondCode CCode =
8880 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8881 CCode = X86::GetOppositeBranchCondition(CCode);
8882 CC = DAG.getConstant(CCode, MVT::i8);
8888 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8889 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8890 // It should be transformed during dag combiner except when the condition
8891 // is set by a arithmetics with overflow node.
8892 X86::CondCode CCode =
8893 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8894 CCode = X86::GetOppositeBranchCondition(CCode);
8895 CC = DAG.getConstant(CCode, MVT::i8);
8896 Cond = Cond.getOperand(0).getOperand(1);
8898 } else if (Cond.getOpcode() == ISD::SETCC &&
8899 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8900 // For FCMP_OEQ, we can emit
8901 // two branches instead of an explicit AND instruction with a
8902 // separate test. However, we only do this if this block doesn't
8903 // have a fall-through edge, because this requires an explicit
8904 // jmp when the condition is false.
8905 if (Op.getNode()->hasOneUse()) {
8906 SDNode *User = *Op.getNode()->use_begin();
8907 // Look for an unconditional branch following this conditional branch.
8908 // We need this because we need to reverse the successors in order
8909 // to implement FCMP_OEQ.
8910 if (User->getOpcode() == ISD::BR) {
8911 SDValue FalseBB = User->getOperand(1);
8913 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8914 assert(NewBR == User);
8918 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8919 Cond.getOperand(0), Cond.getOperand(1));
8920 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8921 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8922 Chain, Dest, CC, Cmp);
8923 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8928 } else if (Cond.getOpcode() == ISD::SETCC &&
8929 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8930 // For FCMP_UNE, we can emit
8931 // two branches instead of an explicit AND instruction with a
8932 // separate test. However, we only do this if this block doesn't
8933 // have a fall-through edge, because this requires an explicit
8934 // jmp when the condition is false.
8935 if (Op.getNode()->hasOneUse()) {
8936 SDNode *User = *Op.getNode()->use_begin();
8937 // Look for an unconditional branch following this conditional branch.
8938 // We need this because we need to reverse the successors in order
8939 // to implement FCMP_UNE.
8940 if (User->getOpcode() == ISD::BR) {
8941 SDValue FalseBB = User->getOperand(1);
8943 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8944 assert(NewBR == User);
8947 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8948 Cond.getOperand(0), Cond.getOperand(1));
8949 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8950 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8951 Chain, Dest, CC, Cmp);
8952 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8962 // Look pass the truncate.
8963 if (Cond.getOpcode() == ISD::TRUNCATE)
8964 Cond = Cond.getOperand(0);
8966 // We know the result of AND is compared against zero. Try to match
8968 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8969 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8970 if (NewSetCC.getNode()) {
8971 CC = NewSetCC.getOperand(0);
8972 Cond = NewSetCC.getOperand(1);
8979 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8980 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8982 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8983 Chain, Dest, CC, Cond);
8987 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8988 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8989 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8990 // that the guard pages used by the OS virtual memory manager are allocated in
8991 // correct sequence.
8993 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8994 SelectionDAG &DAG) const {
8995 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8996 getTargetMachine().Options.EnableSegmentedStacks) &&
8997 "This should be used only on Windows targets or when segmented stacks "
8999 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9000 DebugLoc dl = Op.getDebugLoc();
9003 SDValue Chain = Op.getOperand(0);
9004 SDValue Size = Op.getOperand(1);
9005 // FIXME: Ensure alignment here
9007 bool Is64Bit = Subtarget->is64Bit();
9008 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9010 if (getTargetMachine().Options.EnableSegmentedStacks) {
9011 MachineFunction &MF = DAG.getMachineFunction();
9012 MachineRegisterInfo &MRI = MF.getRegInfo();
9015 // The 64 bit implementation of segmented stacks needs to clobber both r10
9016 // r11. This makes it impossible to use it along with nested parameters.
9017 const Function *F = MF.getFunction();
9019 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9021 if (I->hasNestAttr())
9022 report_fatal_error("Cannot use segmented stacks with functions that "
9023 "have nested arguments.");
9026 const TargetRegisterClass *AddrRegClass =
9027 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9028 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9029 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9030 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9031 DAG.getRegister(Vreg, SPTy));
9032 SDValue Ops1[2] = { Value, Chain };
9033 return DAG.getMergeValues(Ops1, 2, dl);
9036 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9038 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9039 Flag = Chain.getValue(1);
9040 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
9042 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
9043 Flag = Chain.getValue(1);
9045 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
9047 SDValue Ops1[2] = { Chain.getValue(0), Chain };
9048 return DAG.getMergeValues(Ops1, 2, dl);
9052 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
9053 MachineFunction &MF = DAG.getMachineFunction();
9054 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
9056 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9057 DebugLoc DL = Op.getDebugLoc();
9059 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
9060 // vastart just stores the address of the VarArgsFrameIndex slot into the
9061 // memory location argument.
9062 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9064 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
9065 MachinePointerInfo(SV), false, false, 0);
9069 // gp_offset (0 - 6 * 8)
9070 // fp_offset (48 - 48 + 8 * 16)
9071 // overflow_arg_area (point to parameters coming in memory).
9073 SmallVector<SDValue, 8> MemOps;
9074 SDValue FIN = Op.getOperand(1);
9076 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
9077 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9079 FIN, MachinePointerInfo(SV), false, false, 0);
9080 MemOps.push_back(Store);
9083 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9084 FIN, DAG.getIntPtrConstant(4));
9085 Store = DAG.getStore(Op.getOperand(0), DL,
9086 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9088 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9089 MemOps.push_back(Store);
9091 // Store ptr to overflow_arg_area
9092 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9093 FIN, DAG.getIntPtrConstant(4));
9094 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9096 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9097 MachinePointerInfo(SV, 8),
9099 MemOps.push_back(Store);
9101 // Store ptr to reg_save_area.
9102 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9103 FIN, DAG.getIntPtrConstant(8));
9104 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9106 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9107 MachinePointerInfo(SV, 16), false, false, 0);
9108 MemOps.push_back(Store);
9109 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9110 &MemOps[0], MemOps.size());
9113 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9114 assert(Subtarget->is64Bit() &&
9115 "LowerVAARG only handles 64-bit va_arg!");
9116 assert((Subtarget->isTargetLinux() ||
9117 Subtarget->isTargetDarwin()) &&
9118 "Unhandled target in LowerVAARG");
9119 assert(Op.getNode()->getNumOperands() == 4);
9120 SDValue Chain = Op.getOperand(0);
9121 SDValue SrcPtr = Op.getOperand(1);
9122 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9123 unsigned Align = Op.getConstantOperandVal(3);
9124 DebugLoc dl = Op.getDebugLoc();
9126 EVT ArgVT = Op.getNode()->getValueType(0);
9127 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9128 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9131 // Decide which area this value should be read from.
9132 // TODO: Implement the AMD64 ABI in its entirety. This simple
9133 // selection mechanism works only for the basic types.
9134 if (ArgVT == MVT::f80) {
9135 llvm_unreachable("va_arg for f80 not yet implemented");
9136 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9137 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9138 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9139 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9141 llvm_unreachable("Unhandled argument type in LowerVAARG");
9145 // Sanity Check: Make sure using fp_offset makes sense.
9146 assert(!getTargetMachine().Options.UseSoftFloat &&
9147 !(DAG.getMachineFunction()
9148 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9149 Subtarget->hasSSE1());
9152 // Insert VAARG_64 node into the DAG
9153 // VAARG_64 returns two values: Variable Argument Address, Chain
9154 SmallVector<SDValue, 11> InstOps;
9155 InstOps.push_back(Chain);
9156 InstOps.push_back(SrcPtr);
9157 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9158 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9159 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9160 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9161 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9162 VTs, &InstOps[0], InstOps.size(),
9164 MachinePointerInfo(SV),
9169 Chain = VAARG.getValue(1);
9171 // Load the next argument and return it
9172 return DAG.getLoad(ArgVT, dl,
9175 MachinePointerInfo(),
9176 false, false, false, 0);
9179 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9180 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9181 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9182 SDValue Chain = Op.getOperand(0);
9183 SDValue DstPtr = Op.getOperand(1);
9184 SDValue SrcPtr = Op.getOperand(2);
9185 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9186 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9187 DebugLoc DL = Op.getDebugLoc();
9189 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9190 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9192 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9195 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9196 // may or may not be a constant. Takes immediate version of shift as input.
9197 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9198 SDValue SrcOp, SDValue ShAmt,
9199 SelectionDAG &DAG) {
9200 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9202 if (isa<ConstantSDNode>(ShAmt)) {
9204 default: llvm_unreachable("Unknown target vector shift node");
9208 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9212 // Change opcode to non-immediate version
9214 default: llvm_unreachable("Unknown target vector shift node");
9215 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9216 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9217 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9220 // Need to build a vector containing shift amount
9221 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9224 ShOps[1] = DAG.getConstant(0, MVT::i32);
9225 ShOps[2] = DAG.getUNDEF(MVT::i32);
9226 ShOps[3] = DAG.getUNDEF(MVT::i32);
9227 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9228 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9229 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9233 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9234 DebugLoc dl = Op.getDebugLoc();
9235 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9237 default: return SDValue(); // Don't custom lower most intrinsics.
9238 // Comparison intrinsics.
9239 case Intrinsic::x86_sse_comieq_ss:
9240 case Intrinsic::x86_sse_comilt_ss:
9241 case Intrinsic::x86_sse_comile_ss:
9242 case Intrinsic::x86_sse_comigt_ss:
9243 case Intrinsic::x86_sse_comige_ss:
9244 case Intrinsic::x86_sse_comineq_ss:
9245 case Intrinsic::x86_sse_ucomieq_ss:
9246 case Intrinsic::x86_sse_ucomilt_ss:
9247 case Intrinsic::x86_sse_ucomile_ss:
9248 case Intrinsic::x86_sse_ucomigt_ss:
9249 case Intrinsic::x86_sse_ucomige_ss:
9250 case Intrinsic::x86_sse_ucomineq_ss:
9251 case Intrinsic::x86_sse2_comieq_sd:
9252 case Intrinsic::x86_sse2_comilt_sd:
9253 case Intrinsic::x86_sse2_comile_sd:
9254 case Intrinsic::x86_sse2_comigt_sd:
9255 case Intrinsic::x86_sse2_comige_sd:
9256 case Intrinsic::x86_sse2_comineq_sd:
9257 case Intrinsic::x86_sse2_ucomieq_sd:
9258 case Intrinsic::x86_sse2_ucomilt_sd:
9259 case Intrinsic::x86_sse2_ucomile_sd:
9260 case Intrinsic::x86_sse2_ucomigt_sd:
9261 case Intrinsic::x86_sse2_ucomige_sd:
9262 case Intrinsic::x86_sse2_ucomineq_sd: {
9264 ISD::CondCode CC = ISD::SETCC_INVALID;
9266 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9267 case Intrinsic::x86_sse_comieq_ss:
9268 case Intrinsic::x86_sse2_comieq_sd:
9272 case Intrinsic::x86_sse_comilt_ss:
9273 case Intrinsic::x86_sse2_comilt_sd:
9277 case Intrinsic::x86_sse_comile_ss:
9278 case Intrinsic::x86_sse2_comile_sd:
9282 case Intrinsic::x86_sse_comigt_ss:
9283 case Intrinsic::x86_sse2_comigt_sd:
9287 case Intrinsic::x86_sse_comige_ss:
9288 case Intrinsic::x86_sse2_comige_sd:
9292 case Intrinsic::x86_sse_comineq_ss:
9293 case Intrinsic::x86_sse2_comineq_sd:
9297 case Intrinsic::x86_sse_ucomieq_ss:
9298 case Intrinsic::x86_sse2_ucomieq_sd:
9299 Opc = X86ISD::UCOMI;
9302 case Intrinsic::x86_sse_ucomilt_ss:
9303 case Intrinsic::x86_sse2_ucomilt_sd:
9304 Opc = X86ISD::UCOMI;
9307 case Intrinsic::x86_sse_ucomile_ss:
9308 case Intrinsic::x86_sse2_ucomile_sd:
9309 Opc = X86ISD::UCOMI;
9312 case Intrinsic::x86_sse_ucomigt_ss:
9313 case Intrinsic::x86_sse2_ucomigt_sd:
9314 Opc = X86ISD::UCOMI;
9317 case Intrinsic::x86_sse_ucomige_ss:
9318 case Intrinsic::x86_sse2_ucomige_sd:
9319 Opc = X86ISD::UCOMI;
9322 case Intrinsic::x86_sse_ucomineq_ss:
9323 case Intrinsic::x86_sse2_ucomineq_sd:
9324 Opc = X86ISD::UCOMI;
9329 SDValue LHS = Op.getOperand(1);
9330 SDValue RHS = Op.getOperand(2);
9331 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9332 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9333 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9334 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9335 DAG.getConstant(X86CC, MVT::i8), Cond);
9336 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9338 // XOP comparison intrinsics
9339 case Intrinsic::x86_xop_vpcomltb:
9340 case Intrinsic::x86_xop_vpcomltw:
9341 case Intrinsic::x86_xop_vpcomltd:
9342 case Intrinsic::x86_xop_vpcomltq:
9343 case Intrinsic::x86_xop_vpcomltub:
9344 case Intrinsic::x86_xop_vpcomltuw:
9345 case Intrinsic::x86_xop_vpcomltud:
9346 case Intrinsic::x86_xop_vpcomltuq:
9347 case Intrinsic::x86_xop_vpcomleb:
9348 case Intrinsic::x86_xop_vpcomlew:
9349 case Intrinsic::x86_xop_vpcomled:
9350 case Intrinsic::x86_xop_vpcomleq:
9351 case Intrinsic::x86_xop_vpcomleub:
9352 case Intrinsic::x86_xop_vpcomleuw:
9353 case Intrinsic::x86_xop_vpcomleud:
9354 case Intrinsic::x86_xop_vpcomleuq:
9355 case Intrinsic::x86_xop_vpcomgtb:
9356 case Intrinsic::x86_xop_vpcomgtw:
9357 case Intrinsic::x86_xop_vpcomgtd:
9358 case Intrinsic::x86_xop_vpcomgtq:
9359 case Intrinsic::x86_xop_vpcomgtub:
9360 case Intrinsic::x86_xop_vpcomgtuw:
9361 case Intrinsic::x86_xop_vpcomgtud:
9362 case Intrinsic::x86_xop_vpcomgtuq:
9363 case Intrinsic::x86_xop_vpcomgeb:
9364 case Intrinsic::x86_xop_vpcomgew:
9365 case Intrinsic::x86_xop_vpcomged:
9366 case Intrinsic::x86_xop_vpcomgeq:
9367 case Intrinsic::x86_xop_vpcomgeub:
9368 case Intrinsic::x86_xop_vpcomgeuw:
9369 case Intrinsic::x86_xop_vpcomgeud:
9370 case Intrinsic::x86_xop_vpcomgeuq:
9371 case Intrinsic::x86_xop_vpcomeqb:
9372 case Intrinsic::x86_xop_vpcomeqw:
9373 case Intrinsic::x86_xop_vpcomeqd:
9374 case Intrinsic::x86_xop_vpcomeqq:
9375 case Intrinsic::x86_xop_vpcomequb:
9376 case Intrinsic::x86_xop_vpcomequw:
9377 case Intrinsic::x86_xop_vpcomequd:
9378 case Intrinsic::x86_xop_vpcomequq:
9379 case Intrinsic::x86_xop_vpcomneb:
9380 case Intrinsic::x86_xop_vpcomnew:
9381 case Intrinsic::x86_xop_vpcomned:
9382 case Intrinsic::x86_xop_vpcomneq:
9383 case Intrinsic::x86_xop_vpcomneub:
9384 case Intrinsic::x86_xop_vpcomneuw:
9385 case Intrinsic::x86_xop_vpcomneud:
9386 case Intrinsic::x86_xop_vpcomneuq:
9387 case Intrinsic::x86_xop_vpcomfalseb:
9388 case Intrinsic::x86_xop_vpcomfalsew:
9389 case Intrinsic::x86_xop_vpcomfalsed:
9390 case Intrinsic::x86_xop_vpcomfalseq:
9391 case Intrinsic::x86_xop_vpcomfalseub:
9392 case Intrinsic::x86_xop_vpcomfalseuw:
9393 case Intrinsic::x86_xop_vpcomfalseud:
9394 case Intrinsic::x86_xop_vpcomfalseuq:
9395 case Intrinsic::x86_xop_vpcomtrueb:
9396 case Intrinsic::x86_xop_vpcomtruew:
9397 case Intrinsic::x86_xop_vpcomtrued:
9398 case Intrinsic::x86_xop_vpcomtrueq:
9399 case Intrinsic::x86_xop_vpcomtrueub:
9400 case Intrinsic::x86_xop_vpcomtrueuw:
9401 case Intrinsic::x86_xop_vpcomtrueud:
9402 case Intrinsic::x86_xop_vpcomtrueuq: {
9407 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9408 case Intrinsic::x86_xop_vpcomltb:
9409 case Intrinsic::x86_xop_vpcomltw:
9410 case Intrinsic::x86_xop_vpcomltd:
9411 case Intrinsic::x86_xop_vpcomltq:
9413 Opc = X86ISD::VPCOM;
9415 case Intrinsic::x86_xop_vpcomltub:
9416 case Intrinsic::x86_xop_vpcomltuw:
9417 case Intrinsic::x86_xop_vpcomltud:
9418 case Intrinsic::x86_xop_vpcomltuq:
9420 Opc = X86ISD::VPCOMU;
9422 case Intrinsic::x86_xop_vpcomleb:
9423 case Intrinsic::x86_xop_vpcomlew:
9424 case Intrinsic::x86_xop_vpcomled:
9425 case Intrinsic::x86_xop_vpcomleq:
9427 Opc = X86ISD::VPCOM;
9429 case Intrinsic::x86_xop_vpcomleub:
9430 case Intrinsic::x86_xop_vpcomleuw:
9431 case Intrinsic::x86_xop_vpcomleud:
9432 case Intrinsic::x86_xop_vpcomleuq:
9434 Opc = X86ISD::VPCOMU;
9436 case Intrinsic::x86_xop_vpcomgtb:
9437 case Intrinsic::x86_xop_vpcomgtw:
9438 case Intrinsic::x86_xop_vpcomgtd:
9439 case Intrinsic::x86_xop_vpcomgtq:
9441 Opc = X86ISD::VPCOM;
9443 case Intrinsic::x86_xop_vpcomgtub:
9444 case Intrinsic::x86_xop_vpcomgtuw:
9445 case Intrinsic::x86_xop_vpcomgtud:
9446 case Intrinsic::x86_xop_vpcomgtuq:
9448 Opc = X86ISD::VPCOMU;
9450 case Intrinsic::x86_xop_vpcomgeb:
9451 case Intrinsic::x86_xop_vpcomgew:
9452 case Intrinsic::x86_xop_vpcomged:
9453 case Intrinsic::x86_xop_vpcomgeq:
9455 Opc = X86ISD::VPCOM;
9457 case Intrinsic::x86_xop_vpcomgeub:
9458 case Intrinsic::x86_xop_vpcomgeuw:
9459 case Intrinsic::x86_xop_vpcomgeud:
9460 case Intrinsic::x86_xop_vpcomgeuq:
9462 Opc = X86ISD::VPCOMU;
9464 case Intrinsic::x86_xop_vpcomeqb:
9465 case Intrinsic::x86_xop_vpcomeqw:
9466 case Intrinsic::x86_xop_vpcomeqd:
9467 case Intrinsic::x86_xop_vpcomeqq:
9469 Opc = X86ISD::VPCOM;
9471 case Intrinsic::x86_xop_vpcomequb:
9472 case Intrinsic::x86_xop_vpcomequw:
9473 case Intrinsic::x86_xop_vpcomequd:
9474 case Intrinsic::x86_xop_vpcomequq:
9476 Opc = X86ISD::VPCOMU;
9478 case Intrinsic::x86_xop_vpcomneb:
9479 case Intrinsic::x86_xop_vpcomnew:
9480 case Intrinsic::x86_xop_vpcomned:
9481 case Intrinsic::x86_xop_vpcomneq:
9483 Opc = X86ISD::VPCOM;
9485 case Intrinsic::x86_xop_vpcomneub:
9486 case Intrinsic::x86_xop_vpcomneuw:
9487 case Intrinsic::x86_xop_vpcomneud:
9488 case Intrinsic::x86_xop_vpcomneuq:
9490 Opc = X86ISD::VPCOMU;
9492 case Intrinsic::x86_xop_vpcomfalseb:
9493 case Intrinsic::x86_xop_vpcomfalsew:
9494 case Intrinsic::x86_xop_vpcomfalsed:
9495 case Intrinsic::x86_xop_vpcomfalseq:
9497 Opc = X86ISD::VPCOM;
9499 case Intrinsic::x86_xop_vpcomfalseub:
9500 case Intrinsic::x86_xop_vpcomfalseuw:
9501 case Intrinsic::x86_xop_vpcomfalseud:
9502 case Intrinsic::x86_xop_vpcomfalseuq:
9504 Opc = X86ISD::VPCOMU;
9506 case Intrinsic::x86_xop_vpcomtrueb:
9507 case Intrinsic::x86_xop_vpcomtruew:
9508 case Intrinsic::x86_xop_vpcomtrued:
9509 case Intrinsic::x86_xop_vpcomtrueq:
9511 Opc = X86ISD::VPCOM;
9513 case Intrinsic::x86_xop_vpcomtrueub:
9514 case Intrinsic::x86_xop_vpcomtrueuw:
9515 case Intrinsic::x86_xop_vpcomtrueud:
9516 case Intrinsic::x86_xop_vpcomtrueuq:
9518 Opc = X86ISD::VPCOMU;
9522 SDValue LHS = Op.getOperand(1);
9523 SDValue RHS = Op.getOperand(2);
9524 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9525 DAG.getConstant(CC, MVT::i8));
9528 // Arithmetic intrinsics.
9529 case Intrinsic::x86_sse2_pmulu_dq:
9530 case Intrinsic::x86_avx2_pmulu_dq:
9531 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9532 Op.getOperand(1), Op.getOperand(2));
9533 case Intrinsic::x86_sse3_hadd_ps:
9534 case Intrinsic::x86_sse3_hadd_pd:
9535 case Intrinsic::x86_avx_hadd_ps_256:
9536 case Intrinsic::x86_avx_hadd_pd_256:
9537 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9538 Op.getOperand(1), Op.getOperand(2));
9539 case Intrinsic::x86_sse3_hsub_ps:
9540 case Intrinsic::x86_sse3_hsub_pd:
9541 case Intrinsic::x86_avx_hsub_ps_256:
9542 case Intrinsic::x86_avx_hsub_pd_256:
9543 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9544 Op.getOperand(1), Op.getOperand(2));
9545 case Intrinsic::x86_ssse3_phadd_w_128:
9546 case Intrinsic::x86_ssse3_phadd_d_128:
9547 case Intrinsic::x86_avx2_phadd_w:
9548 case Intrinsic::x86_avx2_phadd_d:
9549 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9550 Op.getOperand(1), Op.getOperand(2));
9551 case Intrinsic::x86_ssse3_phsub_w_128:
9552 case Intrinsic::x86_ssse3_phsub_d_128:
9553 case Intrinsic::x86_avx2_phsub_w:
9554 case Intrinsic::x86_avx2_phsub_d:
9555 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9556 Op.getOperand(1), Op.getOperand(2));
9557 case Intrinsic::x86_avx2_psllv_d:
9558 case Intrinsic::x86_avx2_psllv_q:
9559 case Intrinsic::x86_avx2_psllv_d_256:
9560 case Intrinsic::x86_avx2_psllv_q_256:
9561 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9562 Op.getOperand(1), Op.getOperand(2));
9563 case Intrinsic::x86_avx2_psrlv_d:
9564 case Intrinsic::x86_avx2_psrlv_q:
9565 case Intrinsic::x86_avx2_psrlv_d_256:
9566 case Intrinsic::x86_avx2_psrlv_q_256:
9567 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9568 Op.getOperand(1), Op.getOperand(2));
9569 case Intrinsic::x86_avx2_psrav_d:
9570 case Intrinsic::x86_avx2_psrav_d_256:
9571 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9572 Op.getOperand(1), Op.getOperand(2));
9573 case Intrinsic::x86_ssse3_pshuf_b_128:
9574 case Intrinsic::x86_avx2_pshuf_b:
9575 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9576 Op.getOperand(1), Op.getOperand(2));
9577 case Intrinsic::x86_ssse3_psign_b_128:
9578 case Intrinsic::x86_ssse3_psign_w_128:
9579 case Intrinsic::x86_ssse3_psign_d_128:
9580 case Intrinsic::x86_avx2_psign_b:
9581 case Intrinsic::x86_avx2_psign_w:
9582 case Intrinsic::x86_avx2_psign_d:
9583 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9584 Op.getOperand(1), Op.getOperand(2));
9585 case Intrinsic::x86_sse41_insertps:
9586 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9587 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9588 case Intrinsic::x86_avx_vperm2f128_ps_256:
9589 case Intrinsic::x86_avx_vperm2f128_pd_256:
9590 case Intrinsic::x86_avx_vperm2f128_si_256:
9591 case Intrinsic::x86_avx2_vperm2i128:
9592 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9593 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9594 case Intrinsic::x86_avx2_permd:
9595 case Intrinsic::x86_avx2_permps:
9596 // Operands intentionally swapped. Mask is last operand to intrinsic,
9597 // but second operand for node/intruction.
9598 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
9599 Op.getOperand(2), Op.getOperand(1));
9601 // ptest and testp intrinsics. The intrinsic these come from are designed to
9602 // return an integer value, not just an instruction so lower it to the ptest
9603 // or testp pattern and a setcc for the result.
9604 case Intrinsic::x86_sse41_ptestz:
9605 case Intrinsic::x86_sse41_ptestc:
9606 case Intrinsic::x86_sse41_ptestnzc:
9607 case Intrinsic::x86_avx_ptestz_256:
9608 case Intrinsic::x86_avx_ptestc_256:
9609 case Intrinsic::x86_avx_ptestnzc_256:
9610 case Intrinsic::x86_avx_vtestz_ps:
9611 case Intrinsic::x86_avx_vtestc_ps:
9612 case Intrinsic::x86_avx_vtestnzc_ps:
9613 case Intrinsic::x86_avx_vtestz_pd:
9614 case Intrinsic::x86_avx_vtestc_pd:
9615 case Intrinsic::x86_avx_vtestnzc_pd:
9616 case Intrinsic::x86_avx_vtestz_ps_256:
9617 case Intrinsic::x86_avx_vtestc_ps_256:
9618 case Intrinsic::x86_avx_vtestnzc_ps_256:
9619 case Intrinsic::x86_avx_vtestz_pd_256:
9620 case Intrinsic::x86_avx_vtestc_pd_256:
9621 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9622 bool IsTestPacked = false;
9625 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9626 case Intrinsic::x86_avx_vtestz_ps:
9627 case Intrinsic::x86_avx_vtestz_pd:
9628 case Intrinsic::x86_avx_vtestz_ps_256:
9629 case Intrinsic::x86_avx_vtestz_pd_256:
9630 IsTestPacked = true; // Fallthrough
9631 case Intrinsic::x86_sse41_ptestz:
9632 case Intrinsic::x86_avx_ptestz_256:
9634 X86CC = X86::COND_E;
9636 case Intrinsic::x86_avx_vtestc_ps:
9637 case Intrinsic::x86_avx_vtestc_pd:
9638 case Intrinsic::x86_avx_vtestc_ps_256:
9639 case Intrinsic::x86_avx_vtestc_pd_256:
9640 IsTestPacked = true; // Fallthrough
9641 case Intrinsic::x86_sse41_ptestc:
9642 case Intrinsic::x86_avx_ptestc_256:
9644 X86CC = X86::COND_B;
9646 case Intrinsic::x86_avx_vtestnzc_ps:
9647 case Intrinsic::x86_avx_vtestnzc_pd:
9648 case Intrinsic::x86_avx_vtestnzc_ps_256:
9649 case Intrinsic::x86_avx_vtestnzc_pd_256:
9650 IsTestPacked = true; // Fallthrough
9651 case Intrinsic::x86_sse41_ptestnzc:
9652 case Intrinsic::x86_avx_ptestnzc_256:
9654 X86CC = X86::COND_A;
9658 SDValue LHS = Op.getOperand(1);
9659 SDValue RHS = Op.getOperand(2);
9660 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9661 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9662 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9663 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9664 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9667 // SSE/AVX shift intrinsics
9668 case Intrinsic::x86_sse2_psll_w:
9669 case Intrinsic::x86_sse2_psll_d:
9670 case Intrinsic::x86_sse2_psll_q:
9671 case Intrinsic::x86_avx2_psll_w:
9672 case Intrinsic::x86_avx2_psll_d:
9673 case Intrinsic::x86_avx2_psll_q:
9674 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9675 Op.getOperand(1), Op.getOperand(2));
9676 case Intrinsic::x86_sse2_psrl_w:
9677 case Intrinsic::x86_sse2_psrl_d:
9678 case Intrinsic::x86_sse2_psrl_q:
9679 case Intrinsic::x86_avx2_psrl_w:
9680 case Intrinsic::x86_avx2_psrl_d:
9681 case Intrinsic::x86_avx2_psrl_q:
9682 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9683 Op.getOperand(1), Op.getOperand(2));
9684 case Intrinsic::x86_sse2_psra_w:
9685 case Intrinsic::x86_sse2_psra_d:
9686 case Intrinsic::x86_avx2_psra_w:
9687 case Intrinsic::x86_avx2_psra_d:
9688 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9689 Op.getOperand(1), Op.getOperand(2));
9690 case Intrinsic::x86_sse2_pslli_w:
9691 case Intrinsic::x86_sse2_pslli_d:
9692 case Intrinsic::x86_sse2_pslli_q:
9693 case Intrinsic::x86_avx2_pslli_w:
9694 case Intrinsic::x86_avx2_pslli_d:
9695 case Intrinsic::x86_avx2_pslli_q:
9696 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9697 Op.getOperand(1), Op.getOperand(2), DAG);
9698 case Intrinsic::x86_sse2_psrli_w:
9699 case Intrinsic::x86_sse2_psrli_d:
9700 case Intrinsic::x86_sse2_psrli_q:
9701 case Intrinsic::x86_avx2_psrli_w:
9702 case Intrinsic::x86_avx2_psrli_d:
9703 case Intrinsic::x86_avx2_psrli_q:
9704 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9705 Op.getOperand(1), Op.getOperand(2), DAG);
9706 case Intrinsic::x86_sse2_psrai_w:
9707 case Intrinsic::x86_sse2_psrai_d:
9708 case Intrinsic::x86_avx2_psrai_w:
9709 case Intrinsic::x86_avx2_psrai_d:
9710 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9711 Op.getOperand(1), Op.getOperand(2), DAG);
9712 // Fix vector shift instructions where the last operand is a non-immediate
9714 case Intrinsic::x86_mmx_pslli_w:
9715 case Intrinsic::x86_mmx_pslli_d:
9716 case Intrinsic::x86_mmx_pslli_q:
9717 case Intrinsic::x86_mmx_psrli_w:
9718 case Intrinsic::x86_mmx_psrli_d:
9719 case Intrinsic::x86_mmx_psrli_q:
9720 case Intrinsic::x86_mmx_psrai_w:
9721 case Intrinsic::x86_mmx_psrai_d: {
9722 SDValue ShAmt = Op.getOperand(2);
9723 if (isa<ConstantSDNode>(ShAmt))
9726 unsigned NewIntNo = 0;
9728 case Intrinsic::x86_mmx_pslli_w:
9729 NewIntNo = Intrinsic::x86_mmx_psll_w;
9731 case Intrinsic::x86_mmx_pslli_d:
9732 NewIntNo = Intrinsic::x86_mmx_psll_d;
9734 case Intrinsic::x86_mmx_pslli_q:
9735 NewIntNo = Intrinsic::x86_mmx_psll_q;
9737 case Intrinsic::x86_mmx_psrli_w:
9738 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9740 case Intrinsic::x86_mmx_psrli_d:
9741 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9743 case Intrinsic::x86_mmx_psrli_q:
9744 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9746 case Intrinsic::x86_mmx_psrai_w:
9747 NewIntNo = Intrinsic::x86_mmx_psra_w;
9749 case Intrinsic::x86_mmx_psrai_d:
9750 NewIntNo = Intrinsic::x86_mmx_psra_d;
9752 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9755 // The vector shift intrinsics with scalars uses 32b shift amounts but
9756 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9758 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9759 DAG.getConstant(0, MVT::i32));
9760 // FIXME this must be lowered to get rid of the invalid type.
9762 EVT VT = Op.getValueType();
9763 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9764 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9765 DAG.getConstant(NewIntNo, MVT::i32),
9766 Op.getOperand(1), ShAmt);
9771 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9772 SelectionDAG &DAG) const {
9773 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9774 MFI->setReturnAddressIsTaken(true);
9776 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9777 DebugLoc dl = Op.getDebugLoc();
9780 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9782 DAG.getConstant(TD->getPointerSize(),
9783 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9784 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9785 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9787 MachinePointerInfo(), false, false, false, 0);
9790 // Just load the return address.
9791 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9792 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9793 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9796 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9797 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9798 MFI->setFrameAddressIsTaken(true);
9800 EVT VT = Op.getValueType();
9801 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9802 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9803 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9804 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9806 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9807 MachinePointerInfo(),
9808 false, false, false, 0);
9812 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9813 SelectionDAG &DAG) const {
9814 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9817 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9818 MachineFunction &MF = DAG.getMachineFunction();
9819 SDValue Chain = Op.getOperand(0);
9820 SDValue Offset = Op.getOperand(1);
9821 SDValue Handler = Op.getOperand(2);
9822 DebugLoc dl = Op.getDebugLoc();
9824 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9825 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9827 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9829 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9830 DAG.getIntPtrConstant(TD->getPointerSize()));
9831 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9832 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9834 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9835 MF.getRegInfo().addLiveOut(StoreAddrReg);
9837 return DAG.getNode(X86ISD::EH_RETURN, dl,
9839 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9842 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9843 SelectionDAG &DAG) const {
9844 return Op.getOperand(0);
9847 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9848 SelectionDAG &DAG) const {
9849 SDValue Root = Op.getOperand(0);
9850 SDValue Trmp = Op.getOperand(1); // trampoline
9851 SDValue FPtr = Op.getOperand(2); // nested function
9852 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9853 DebugLoc dl = Op.getDebugLoc();
9855 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9857 if (Subtarget->is64Bit()) {
9858 SDValue OutChains[6];
9860 // Large code-model.
9861 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9862 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9864 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9865 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9867 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9869 // Load the pointer to the nested function into R11.
9870 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9871 SDValue Addr = Trmp;
9872 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9873 Addr, MachinePointerInfo(TrmpAddr),
9876 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9877 DAG.getConstant(2, MVT::i64));
9878 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9879 MachinePointerInfo(TrmpAddr, 2),
9882 // Load the 'nest' parameter value into R10.
9883 // R10 is specified in X86CallingConv.td
9884 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9885 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9886 DAG.getConstant(10, MVT::i64));
9887 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9888 Addr, MachinePointerInfo(TrmpAddr, 10),
9891 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9892 DAG.getConstant(12, MVT::i64));
9893 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9894 MachinePointerInfo(TrmpAddr, 12),
9897 // Jump to the nested function.
9898 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9899 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9900 DAG.getConstant(20, MVT::i64));
9901 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9902 Addr, MachinePointerInfo(TrmpAddr, 20),
9905 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9906 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9907 DAG.getConstant(22, MVT::i64));
9908 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9909 MachinePointerInfo(TrmpAddr, 22),
9912 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9914 const Function *Func =
9915 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9916 CallingConv::ID CC = Func->getCallingConv();
9921 llvm_unreachable("Unsupported calling convention");
9922 case CallingConv::C:
9923 case CallingConv::X86_StdCall: {
9924 // Pass 'nest' parameter in ECX.
9925 // Must be kept in sync with X86CallingConv.td
9928 // Check that ECX wasn't needed by an 'inreg' parameter.
9929 FunctionType *FTy = Func->getFunctionType();
9930 const AttrListPtr &Attrs = Func->getAttributes();
9932 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9933 unsigned InRegCount = 0;
9936 for (FunctionType::param_iterator I = FTy->param_begin(),
9937 E = FTy->param_end(); I != E; ++I, ++Idx)
9938 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9939 // FIXME: should only count parameters that are lowered to integers.
9940 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9942 if (InRegCount > 2) {
9943 report_fatal_error("Nest register in use - reduce number of inreg"
9949 case CallingConv::X86_FastCall:
9950 case CallingConv::X86_ThisCall:
9951 case CallingConv::Fast:
9952 // Pass 'nest' parameter in EAX.
9953 // Must be kept in sync with X86CallingConv.td
9958 SDValue OutChains[4];
9961 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9962 DAG.getConstant(10, MVT::i32));
9963 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9965 // This is storing the opcode for MOV32ri.
9966 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9967 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9968 OutChains[0] = DAG.getStore(Root, dl,
9969 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9970 Trmp, MachinePointerInfo(TrmpAddr),
9973 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9974 DAG.getConstant(1, MVT::i32));
9975 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9976 MachinePointerInfo(TrmpAddr, 1),
9979 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9980 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9981 DAG.getConstant(5, MVT::i32));
9982 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9983 MachinePointerInfo(TrmpAddr, 5),
9986 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9987 DAG.getConstant(6, MVT::i32));
9988 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9989 MachinePointerInfo(TrmpAddr, 6),
9992 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9996 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9997 SelectionDAG &DAG) const {
9999 The rounding mode is in bits 11:10 of FPSR, and has the following
10001 00 Round to nearest
10006 FLT_ROUNDS, on the other hand, expects the following:
10013 To perform the conversion, we do:
10014 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
10017 MachineFunction &MF = DAG.getMachineFunction();
10018 const TargetMachine &TM = MF.getTarget();
10019 const TargetFrameLowering &TFI = *TM.getFrameLowering();
10020 unsigned StackAlignment = TFI.getStackAlignment();
10021 EVT VT = Op.getValueType();
10022 DebugLoc DL = Op.getDebugLoc();
10024 // Save FP Control Word to stack slot
10025 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
10026 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10029 MachineMemOperand *MMO =
10030 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
10031 MachineMemOperand::MOStore, 2, 2);
10033 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
10034 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
10035 DAG.getVTList(MVT::Other),
10036 Ops, 2, MVT::i16, MMO);
10038 // Load FP Control Word from stack slot
10039 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
10040 MachinePointerInfo(), false, false, false, 0);
10042 // Transform as necessary
10044 DAG.getNode(ISD::SRL, DL, MVT::i16,
10045 DAG.getNode(ISD::AND, DL, MVT::i16,
10046 CWD, DAG.getConstant(0x800, MVT::i16)),
10047 DAG.getConstant(11, MVT::i8));
10049 DAG.getNode(ISD::SRL, DL, MVT::i16,
10050 DAG.getNode(ISD::AND, DL, MVT::i16,
10051 CWD, DAG.getConstant(0x400, MVT::i16)),
10052 DAG.getConstant(9, MVT::i8));
10055 DAG.getNode(ISD::AND, DL, MVT::i16,
10056 DAG.getNode(ISD::ADD, DL, MVT::i16,
10057 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
10058 DAG.getConstant(1, MVT::i16)),
10059 DAG.getConstant(3, MVT::i16));
10062 return DAG.getNode((VT.getSizeInBits() < 16 ?
10063 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
10066 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
10067 EVT VT = Op.getValueType();
10069 unsigned NumBits = VT.getSizeInBits();
10070 DebugLoc dl = Op.getDebugLoc();
10072 Op = Op.getOperand(0);
10073 if (VT == MVT::i8) {
10074 // Zero extend to i32 since there is not an i8 bsr.
10076 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10079 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10080 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10081 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10083 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10086 DAG.getConstant(NumBits+NumBits-1, OpVT),
10087 DAG.getConstant(X86::COND_E, MVT::i8),
10090 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10092 // Finally xor with NumBits-1.
10093 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10096 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10100 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10101 SelectionDAG &DAG) const {
10102 EVT VT = Op.getValueType();
10104 unsigned NumBits = VT.getSizeInBits();
10105 DebugLoc dl = Op.getDebugLoc();
10107 Op = Op.getOperand(0);
10108 if (VT == MVT::i8) {
10109 // Zero extend to i32 since there is not an i8 bsr.
10111 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10114 // Issue a bsr (scan bits in reverse).
10115 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10116 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10118 // And xor with NumBits-1.
10119 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10122 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10126 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10127 EVT VT = Op.getValueType();
10128 unsigned NumBits = VT.getSizeInBits();
10129 DebugLoc dl = Op.getDebugLoc();
10130 Op = Op.getOperand(0);
10132 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10133 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10134 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10136 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10139 DAG.getConstant(NumBits, VT),
10140 DAG.getConstant(X86::COND_E, MVT::i8),
10143 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10146 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10147 // ones, and then concatenate the result back.
10148 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10149 EVT VT = Op.getValueType();
10151 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10152 "Unsupported value type for operation");
10154 int NumElems = VT.getVectorNumElements();
10155 DebugLoc dl = Op.getDebugLoc();
10156 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10157 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10159 // Extract the LHS vectors
10160 SDValue LHS = Op.getOperand(0);
10161 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10162 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10164 // Extract the RHS vectors
10165 SDValue RHS = Op.getOperand(1);
10166 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10167 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10169 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10170 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10172 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10173 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10174 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10177 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10178 assert(Op.getValueType().getSizeInBits() == 256 &&
10179 Op.getValueType().isInteger() &&
10180 "Only handle AVX 256-bit vector integer operation");
10181 return Lower256IntArith(Op, DAG);
10184 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10185 assert(Op.getValueType().getSizeInBits() == 256 &&
10186 Op.getValueType().isInteger() &&
10187 "Only handle AVX 256-bit vector integer operation");
10188 return Lower256IntArith(Op, DAG);
10191 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10192 EVT VT = Op.getValueType();
10194 // Decompose 256-bit ops into smaller 128-bit ops.
10195 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10196 return Lower256IntArith(Op, DAG);
10198 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10199 "Only know how to lower V2I64/V4I64 multiply");
10201 DebugLoc dl = Op.getDebugLoc();
10203 // Ahi = psrlqi(a, 32);
10204 // Bhi = psrlqi(b, 32);
10206 // AloBlo = pmuludq(a, b);
10207 // AloBhi = pmuludq(a, Bhi);
10208 // AhiBlo = pmuludq(Ahi, b);
10210 // AloBhi = psllqi(AloBhi, 32);
10211 // AhiBlo = psllqi(AhiBlo, 32);
10212 // return AloBlo + AloBhi + AhiBlo;
10214 SDValue A = Op.getOperand(0);
10215 SDValue B = Op.getOperand(1);
10217 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10219 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10220 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10222 // Bit cast to 32-bit vectors for MULUDQ
10223 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10224 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10225 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10226 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10227 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10229 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10230 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10231 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10233 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10234 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10236 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10237 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10240 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10242 EVT VT = Op.getValueType();
10243 DebugLoc dl = Op.getDebugLoc();
10244 SDValue R = Op.getOperand(0);
10245 SDValue Amt = Op.getOperand(1);
10246 LLVMContext *Context = DAG.getContext();
10248 if (!Subtarget->hasSSE2())
10251 // Optimize shl/srl/sra with constant shift amount.
10252 if (isSplatVector(Amt.getNode())) {
10253 SDValue SclrAmt = Amt->getOperand(0);
10254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10255 uint64_t ShiftAmt = C->getZExtValue();
10257 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10258 (Subtarget->hasAVX2() &&
10259 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10260 if (Op.getOpcode() == ISD::SHL)
10261 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10262 DAG.getConstant(ShiftAmt, MVT::i32));
10263 if (Op.getOpcode() == ISD::SRL)
10264 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10265 DAG.getConstant(ShiftAmt, MVT::i32));
10266 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10267 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10268 DAG.getConstant(ShiftAmt, MVT::i32));
10271 if (VT == MVT::v16i8) {
10272 if (Op.getOpcode() == ISD::SHL) {
10273 // Make a large shift.
10274 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10275 DAG.getConstant(ShiftAmt, MVT::i32));
10276 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10277 // Zero out the rightmost bits.
10278 SmallVector<SDValue, 16> V(16,
10279 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10281 return DAG.getNode(ISD::AND, dl, VT, SHL,
10282 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10284 if (Op.getOpcode() == ISD::SRL) {
10285 // Make a large shift.
10286 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10287 DAG.getConstant(ShiftAmt, MVT::i32));
10288 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10289 // Zero out the leftmost bits.
10290 SmallVector<SDValue, 16> V(16,
10291 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10293 return DAG.getNode(ISD::AND, dl, VT, SRL,
10294 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10296 if (Op.getOpcode() == ISD::SRA) {
10297 if (ShiftAmt == 7) {
10298 // R s>> 7 === R s< 0
10299 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10300 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10303 // R s>> a === ((R u>> a) ^ m) - m
10304 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10305 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10307 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10308 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10309 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10314 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10315 if (Op.getOpcode() == ISD::SHL) {
10316 // Make a large shift.
10317 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10318 DAG.getConstant(ShiftAmt, MVT::i32));
10319 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10320 // Zero out the rightmost bits.
10321 SmallVector<SDValue, 32> V(32,
10322 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10324 return DAG.getNode(ISD::AND, dl, VT, SHL,
10325 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10327 if (Op.getOpcode() == ISD::SRL) {
10328 // Make a large shift.
10329 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10330 DAG.getConstant(ShiftAmt, MVT::i32));
10331 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10332 // Zero out the leftmost bits.
10333 SmallVector<SDValue, 32> V(32,
10334 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10336 return DAG.getNode(ISD::AND, dl, VT, SRL,
10337 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10339 if (Op.getOpcode() == ISD::SRA) {
10340 if (ShiftAmt == 7) {
10341 // R s>> 7 === R s< 0
10342 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10343 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10346 // R s>> a === ((R u>> a) ^ m) - m
10347 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10348 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10350 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10351 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10352 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10359 // Lower SHL with variable shift amount.
10360 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10361 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10362 DAG.getConstant(23, MVT::i32));
10364 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10365 Constant *C = ConstantDataVector::get(*Context, CV);
10366 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10367 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10368 MachinePointerInfo::getConstantPool(),
10369 false, false, false, 16);
10371 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10372 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10373 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10374 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10376 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10377 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10380 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10381 DAG.getConstant(5, MVT::i32));
10382 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10384 // Turn 'a' into a mask suitable for VSELECT
10385 SDValue VSelM = DAG.getConstant(0x80, VT);
10386 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10387 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10389 SDValue CM1 = DAG.getConstant(0x0f, VT);
10390 SDValue CM2 = DAG.getConstant(0x3f, VT);
10392 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10393 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10394 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10395 DAG.getConstant(4, MVT::i32), DAG);
10396 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10397 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10400 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10401 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10402 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10404 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10405 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10406 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10407 DAG.getConstant(2, MVT::i32), DAG);
10408 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10409 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10412 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10413 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10414 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10416 // return VSELECT(r, r+r, a);
10417 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10418 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10422 // Decompose 256-bit shifts into smaller 128-bit shifts.
10423 if (VT.getSizeInBits() == 256) {
10424 unsigned NumElems = VT.getVectorNumElements();
10425 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10426 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10428 // Extract the two vectors
10429 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10430 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10433 // Recreate the shift amount vectors
10434 SDValue Amt1, Amt2;
10435 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10436 // Constant shift amount
10437 SmallVector<SDValue, 4> Amt1Csts;
10438 SmallVector<SDValue, 4> Amt2Csts;
10439 for (unsigned i = 0; i != NumElems/2; ++i)
10440 Amt1Csts.push_back(Amt->getOperand(i));
10441 for (unsigned i = NumElems/2; i != NumElems; ++i)
10442 Amt2Csts.push_back(Amt->getOperand(i));
10444 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10445 &Amt1Csts[0], NumElems/2);
10446 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10447 &Amt2Csts[0], NumElems/2);
10449 // Variable shift amount
10450 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10451 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10455 // Issue new vector shifts for the smaller types
10456 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10457 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10459 // Concatenate the result back
10460 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10466 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10467 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10468 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10469 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10470 // has only one use.
10471 SDNode *N = Op.getNode();
10472 SDValue LHS = N->getOperand(0);
10473 SDValue RHS = N->getOperand(1);
10474 unsigned BaseOp = 0;
10476 DebugLoc DL = Op.getDebugLoc();
10477 switch (Op.getOpcode()) {
10478 default: llvm_unreachable("Unknown ovf instruction!");
10480 // A subtract of one will be selected as a INC. Note that INC doesn't
10481 // set CF, so we can't do this for UADDO.
10482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10484 BaseOp = X86ISD::INC;
10485 Cond = X86::COND_O;
10488 BaseOp = X86ISD::ADD;
10489 Cond = X86::COND_O;
10492 BaseOp = X86ISD::ADD;
10493 Cond = X86::COND_B;
10496 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10497 // set CF, so we can't do this for USUBO.
10498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10500 BaseOp = X86ISD::DEC;
10501 Cond = X86::COND_O;
10504 BaseOp = X86ISD::SUB;
10505 Cond = X86::COND_O;
10508 BaseOp = X86ISD::SUB;
10509 Cond = X86::COND_B;
10512 BaseOp = X86ISD::SMUL;
10513 Cond = X86::COND_O;
10515 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10516 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10518 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10521 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10522 DAG.getConstant(X86::COND_O, MVT::i32),
10523 SDValue(Sum.getNode(), 2));
10525 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10529 // Also sets EFLAGS.
10530 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10531 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10534 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10535 DAG.getConstant(Cond, MVT::i32),
10536 SDValue(Sum.getNode(), 1));
10538 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10541 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10542 SelectionDAG &DAG) const {
10543 DebugLoc dl = Op.getDebugLoc();
10544 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10545 EVT VT = Op.getValueType();
10547 if (!Subtarget->hasSSE2() || !VT.isVector())
10550 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10551 ExtraVT.getScalarType().getSizeInBits();
10552 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10554 switch (VT.getSimpleVT().SimpleTy) {
10555 default: return SDValue();
10558 if (!Subtarget->hasAVX())
10560 if (!Subtarget->hasAVX2()) {
10561 // needs to be split
10562 int NumElems = VT.getVectorNumElements();
10563 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10564 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10566 // Extract the LHS vectors
10567 SDValue LHS = Op.getOperand(0);
10568 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10569 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10571 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10572 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10574 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10575 int ExtraNumElems = ExtraVT.getVectorNumElements();
10576 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10578 SDValue Extra = DAG.getValueType(ExtraVT);
10580 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10581 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10583 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10588 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10589 Op.getOperand(0), ShAmt, DAG);
10590 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10596 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10597 DebugLoc dl = Op.getDebugLoc();
10599 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10600 // There isn't any reason to disable it if the target processor supports it.
10601 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10602 SDValue Chain = Op.getOperand(0);
10603 SDValue Zero = DAG.getConstant(0, MVT::i32);
10605 DAG.getRegister(X86::ESP, MVT::i32), // Base
10606 DAG.getTargetConstant(1, MVT::i8), // Scale
10607 DAG.getRegister(0, MVT::i32), // Index
10608 DAG.getTargetConstant(0, MVT::i32), // Disp
10609 DAG.getRegister(0, MVT::i32), // Segment.
10614 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10615 array_lengthof(Ops));
10616 return SDValue(Res, 0);
10619 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10621 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10623 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10624 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10625 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10626 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10628 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10629 if (!Op1 && !Op2 && !Op3 && Op4)
10630 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10632 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10633 if (Op1 && !Op2 && !Op3 && !Op4)
10634 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10636 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10638 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10641 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10642 SelectionDAG &DAG) const {
10643 DebugLoc dl = Op.getDebugLoc();
10644 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10645 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10646 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10647 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10649 // The only fence that needs an instruction is a sequentially-consistent
10650 // cross-thread fence.
10651 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10652 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10653 // no-sse2). There isn't any reason to disable it if the target processor
10655 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10656 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10658 SDValue Chain = Op.getOperand(0);
10659 SDValue Zero = DAG.getConstant(0, MVT::i32);
10661 DAG.getRegister(X86::ESP, MVT::i32), // Base
10662 DAG.getTargetConstant(1, MVT::i8), // Scale
10663 DAG.getRegister(0, MVT::i32), // Index
10664 DAG.getTargetConstant(0, MVT::i32), // Disp
10665 DAG.getRegister(0, MVT::i32), // Segment.
10670 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10671 array_lengthof(Ops));
10672 return SDValue(Res, 0);
10675 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10676 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10680 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10681 EVT T = Op.getValueType();
10682 DebugLoc DL = Op.getDebugLoc();
10685 switch(T.getSimpleVT().SimpleTy) {
10686 default: llvm_unreachable("Invalid value type!");
10687 case MVT::i8: Reg = X86::AL; size = 1; break;
10688 case MVT::i16: Reg = X86::AX; size = 2; break;
10689 case MVT::i32: Reg = X86::EAX; size = 4; break;
10691 assert(Subtarget->is64Bit() && "Node not type legal!");
10692 Reg = X86::RAX; size = 8;
10695 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10696 Op.getOperand(2), SDValue());
10697 SDValue Ops[] = { cpIn.getValue(0),
10700 DAG.getTargetConstant(size, MVT::i8),
10701 cpIn.getValue(1) };
10702 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10703 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10704 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10707 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10711 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10712 SelectionDAG &DAG) const {
10713 assert(Subtarget->is64Bit() && "Result not type legalized?");
10714 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10715 SDValue TheChain = Op.getOperand(0);
10716 DebugLoc dl = Op.getDebugLoc();
10717 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10718 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10719 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10721 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10722 DAG.getConstant(32, MVT::i8));
10724 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10727 return DAG.getMergeValues(Ops, 2, dl);
10730 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10731 SelectionDAG &DAG) const {
10732 EVT SrcVT = Op.getOperand(0).getValueType();
10733 EVT DstVT = Op.getValueType();
10734 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10735 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10736 assert((DstVT == MVT::i64 ||
10737 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10738 "Unexpected custom BITCAST");
10739 // i64 <=> MMX conversions are Legal.
10740 if (SrcVT==MVT::i64 && DstVT.isVector())
10742 if (DstVT==MVT::i64 && SrcVT.isVector())
10744 // MMX <=> MMX conversions are Legal.
10745 if (SrcVT.isVector() && DstVT.isVector())
10747 // All other conversions need to be expanded.
10751 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10752 SDNode *Node = Op.getNode();
10753 DebugLoc dl = Node->getDebugLoc();
10754 EVT T = Node->getValueType(0);
10755 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10756 DAG.getConstant(0, T), Node->getOperand(2));
10757 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10758 cast<AtomicSDNode>(Node)->getMemoryVT(),
10759 Node->getOperand(0),
10760 Node->getOperand(1), negOp,
10761 cast<AtomicSDNode>(Node)->getSrcValue(),
10762 cast<AtomicSDNode>(Node)->getAlignment(),
10763 cast<AtomicSDNode>(Node)->getOrdering(),
10764 cast<AtomicSDNode>(Node)->getSynchScope());
10767 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10768 SDNode *Node = Op.getNode();
10769 DebugLoc dl = Node->getDebugLoc();
10770 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10772 // Convert seq_cst store -> xchg
10773 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10774 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10775 // (The only way to get a 16-byte store is cmpxchg16b)
10776 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10777 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10778 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10779 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10780 cast<AtomicSDNode>(Node)->getMemoryVT(),
10781 Node->getOperand(0),
10782 Node->getOperand(1), Node->getOperand(2),
10783 cast<AtomicSDNode>(Node)->getMemOperand(),
10784 cast<AtomicSDNode>(Node)->getOrdering(),
10785 cast<AtomicSDNode>(Node)->getSynchScope());
10786 return Swap.getValue(1);
10788 // Other atomic stores have a simple pattern.
10792 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10793 EVT VT = Op.getNode()->getValueType(0);
10795 // Let legalize expand this if it isn't a legal type yet.
10796 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10799 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10802 bool ExtraOp = false;
10803 switch (Op.getOpcode()) {
10804 default: llvm_unreachable("Invalid code");
10805 case ISD::ADDC: Opc = X86ISD::ADD; break;
10806 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10807 case ISD::SUBC: Opc = X86ISD::SUB; break;
10808 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10812 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10814 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10815 Op.getOperand(1), Op.getOperand(2));
10818 /// LowerOperation - Provide custom lowering hooks for some operations.
10820 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10821 switch (Op.getOpcode()) {
10822 default: llvm_unreachable("Should not custom lower this!");
10823 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10824 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10825 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10826 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10827 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10828 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10829 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10830 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10831 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10832 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10833 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10834 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10835 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10836 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10837 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10838 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10839 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10840 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10841 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10842 case ISD::SHL_PARTS:
10843 case ISD::SRA_PARTS:
10844 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10845 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10846 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10847 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10848 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10849 case ISD::FABS: return LowerFABS(Op, DAG);
10850 case ISD::FNEG: return LowerFNEG(Op, DAG);
10851 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10852 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10853 case ISD::SETCC: return LowerSETCC(Op, DAG);
10854 case ISD::SELECT: return LowerSELECT(Op, DAG);
10855 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10856 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10857 case ISD::VASTART: return LowerVASTART(Op, DAG);
10858 case ISD::VAARG: return LowerVAARG(Op, DAG);
10859 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10860 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10861 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10862 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10863 case ISD::FRAME_TO_ARGS_OFFSET:
10864 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10865 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10866 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10867 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10868 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10869 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10870 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10871 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10872 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10873 case ISD::MUL: return LowerMUL(Op, DAG);
10876 case ISD::SHL: return LowerShift(Op, DAG);
10882 case ISD::UMULO: return LowerXALUO(Op, DAG);
10883 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10884 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10888 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10889 case ISD::ADD: return LowerADD(Op, DAG);
10890 case ISD::SUB: return LowerSUB(Op, DAG);
10894 static void ReplaceATOMIC_LOAD(SDNode *Node,
10895 SmallVectorImpl<SDValue> &Results,
10896 SelectionDAG &DAG) {
10897 DebugLoc dl = Node->getDebugLoc();
10898 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10900 // Convert wide load -> cmpxchg8b/cmpxchg16b
10901 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10902 // (The only way to get a 16-byte load is cmpxchg16b)
10903 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10904 SDValue Zero = DAG.getConstant(0, VT);
10905 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10906 Node->getOperand(0),
10907 Node->getOperand(1), Zero, Zero,
10908 cast<AtomicSDNode>(Node)->getMemOperand(),
10909 cast<AtomicSDNode>(Node)->getOrdering(),
10910 cast<AtomicSDNode>(Node)->getSynchScope());
10911 Results.push_back(Swap.getValue(0));
10912 Results.push_back(Swap.getValue(1));
10915 void X86TargetLowering::
10916 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10917 SelectionDAG &DAG, unsigned NewOp) const {
10918 DebugLoc dl = Node->getDebugLoc();
10919 assert (Node->getValueType(0) == MVT::i64 &&
10920 "Only know how to expand i64 atomics");
10922 SDValue Chain = Node->getOperand(0);
10923 SDValue In1 = Node->getOperand(1);
10924 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10925 Node->getOperand(2), DAG.getIntPtrConstant(0));
10926 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10927 Node->getOperand(2), DAG.getIntPtrConstant(1));
10928 SDValue Ops[] = { Chain, In1, In2L, In2H };
10929 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10931 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10932 cast<MemSDNode>(Node)->getMemOperand());
10933 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10934 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10935 Results.push_back(Result.getValue(2));
10938 /// ReplaceNodeResults - Replace a node with an illegal result type
10939 /// with a new node built out of custom code.
10940 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10941 SmallVectorImpl<SDValue>&Results,
10942 SelectionDAG &DAG) const {
10943 DebugLoc dl = N->getDebugLoc();
10944 switch (N->getOpcode()) {
10946 llvm_unreachable("Do not know how to custom type legalize this operation!");
10947 case ISD::SIGN_EXTEND_INREG:
10952 // We don't want to expand or promote these.
10954 case ISD::FP_TO_SINT:
10955 case ISD::FP_TO_UINT: {
10956 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10958 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10961 std::pair<SDValue,SDValue> Vals =
10962 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10963 SDValue FIST = Vals.first, StackSlot = Vals.second;
10964 if (FIST.getNode() != 0) {
10965 EVT VT = N->getValueType(0);
10966 // Return a load from the stack slot.
10967 if (StackSlot.getNode() != 0)
10968 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10969 MachinePointerInfo(),
10970 false, false, false, 0));
10972 Results.push_back(FIST);
10976 case ISD::READCYCLECOUNTER: {
10977 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10978 SDValue TheChain = N->getOperand(0);
10979 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10980 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10982 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10984 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10985 SDValue Ops[] = { eax, edx };
10986 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10987 Results.push_back(edx.getValue(1));
10990 case ISD::ATOMIC_CMP_SWAP: {
10991 EVT T = N->getValueType(0);
10992 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10993 bool Regs64bit = T == MVT::i128;
10994 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10995 SDValue cpInL, cpInH;
10996 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10997 DAG.getConstant(0, HalfT));
10998 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10999 DAG.getConstant(1, HalfT));
11000 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
11001 Regs64bit ? X86::RAX : X86::EAX,
11003 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
11004 Regs64bit ? X86::RDX : X86::EDX,
11005 cpInH, cpInL.getValue(1));
11006 SDValue swapInL, swapInH;
11007 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11008 DAG.getConstant(0, HalfT));
11009 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
11010 DAG.getConstant(1, HalfT));
11011 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
11012 Regs64bit ? X86::RBX : X86::EBX,
11013 swapInL, cpInH.getValue(1));
11014 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
11015 Regs64bit ? X86::RCX : X86::ECX,
11016 swapInH, swapInL.getValue(1));
11017 SDValue Ops[] = { swapInH.getValue(0),
11019 swapInH.getValue(1) };
11020 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11021 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
11022 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
11023 X86ISD::LCMPXCHG8_DAG;
11024 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
11026 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
11027 Regs64bit ? X86::RAX : X86::EAX,
11028 HalfT, Result.getValue(1));
11029 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
11030 Regs64bit ? X86::RDX : X86::EDX,
11031 HalfT, cpOutL.getValue(2));
11032 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
11033 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
11034 Results.push_back(cpOutH.getValue(1));
11037 case ISD::ATOMIC_LOAD_ADD:
11038 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
11040 case ISD::ATOMIC_LOAD_AND:
11041 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
11043 case ISD::ATOMIC_LOAD_NAND:
11044 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
11046 case ISD::ATOMIC_LOAD_OR:
11047 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
11049 case ISD::ATOMIC_LOAD_SUB:
11050 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
11052 case ISD::ATOMIC_LOAD_XOR:
11053 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
11055 case ISD::ATOMIC_SWAP:
11056 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
11058 case ISD::ATOMIC_LOAD:
11059 ReplaceATOMIC_LOAD(N, Results, DAG);
11063 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
11065 default: return NULL;
11066 case X86ISD::BSF: return "X86ISD::BSF";
11067 case X86ISD::BSR: return "X86ISD::BSR";
11068 case X86ISD::SHLD: return "X86ISD::SHLD";
11069 case X86ISD::SHRD: return "X86ISD::SHRD";
11070 case X86ISD::FAND: return "X86ISD::FAND";
11071 case X86ISD::FOR: return "X86ISD::FOR";
11072 case X86ISD::FXOR: return "X86ISD::FXOR";
11073 case X86ISD::FSRL: return "X86ISD::FSRL";
11074 case X86ISD::FILD: return "X86ISD::FILD";
11075 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
11076 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
11077 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11078 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11079 case X86ISD::FLD: return "X86ISD::FLD";
11080 case X86ISD::FST: return "X86ISD::FST";
11081 case X86ISD::CALL: return "X86ISD::CALL";
11082 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11083 case X86ISD::BT: return "X86ISD::BT";
11084 case X86ISD::CMP: return "X86ISD::CMP";
11085 case X86ISD::COMI: return "X86ISD::COMI";
11086 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11087 case X86ISD::SETCC: return "X86ISD::SETCC";
11088 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11089 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11090 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11091 case X86ISD::CMOV: return "X86ISD::CMOV";
11092 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11093 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11094 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11095 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11096 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11097 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11098 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11099 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11100 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11101 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11102 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11103 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11104 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11105 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11106 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11107 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11108 case X86ISD::BLENDPW: return "X86ISD::BLENDPW";
11109 case X86ISD::BLENDPS: return "X86ISD::BLENDPS";
11110 case X86ISD::BLENDPD: return "X86ISD::BLENDPD";
11111 case X86ISD::HADD: return "X86ISD::HADD";
11112 case X86ISD::HSUB: return "X86ISD::HSUB";
11113 case X86ISD::FHADD: return "X86ISD::FHADD";
11114 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11115 case X86ISD::FMAX: return "X86ISD::FMAX";
11116 case X86ISD::FMIN: return "X86ISD::FMIN";
11117 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11118 case X86ISD::FRCP: return "X86ISD::FRCP";
11119 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11120 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11121 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11122 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11123 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11124 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11125 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11126 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11127 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11128 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11129 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11130 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11131 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11132 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11133 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11134 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11135 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11136 case X86ISD::VSHL: return "X86ISD::VSHL";
11137 case X86ISD::VSRL: return "X86ISD::VSRL";
11138 case X86ISD::VSRA: return "X86ISD::VSRA";
11139 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11140 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11141 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11142 case X86ISD::CMPP: return "X86ISD::CMPP";
11143 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11144 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11145 case X86ISD::ADD: return "X86ISD::ADD";
11146 case X86ISD::SUB: return "X86ISD::SUB";
11147 case X86ISD::ADC: return "X86ISD::ADC";
11148 case X86ISD::SBB: return "X86ISD::SBB";
11149 case X86ISD::SMUL: return "X86ISD::SMUL";
11150 case X86ISD::UMUL: return "X86ISD::UMUL";
11151 case X86ISD::INC: return "X86ISD::INC";
11152 case X86ISD::DEC: return "X86ISD::DEC";
11153 case X86ISD::OR: return "X86ISD::OR";
11154 case X86ISD::XOR: return "X86ISD::XOR";
11155 case X86ISD::AND: return "X86ISD::AND";
11156 case X86ISD::ANDN: return "X86ISD::ANDN";
11157 case X86ISD::BLSI: return "X86ISD::BLSI";
11158 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11159 case X86ISD::BLSR: return "X86ISD::BLSR";
11160 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11161 case X86ISD::PTEST: return "X86ISD::PTEST";
11162 case X86ISD::TESTP: return "X86ISD::TESTP";
11163 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11164 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11165 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11166 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11167 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11168 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11169 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11170 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11171 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11172 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11173 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11174 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11175 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11176 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11177 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11178 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11179 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11180 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11181 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11182 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11183 case X86ISD::VPERMV: return "X86ISD::VPERMV";
11184 case X86ISD::VPERMI: return "X86ISD::VPERMI";
11185 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11186 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11187 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11188 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11189 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11190 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11191 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11195 // isLegalAddressingMode - Return true if the addressing mode represented
11196 // by AM is legal for this target, for a load/store of the specified type.
11197 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11199 // X86 supports extremely general addressing modes.
11200 CodeModel::Model M = getTargetMachine().getCodeModel();
11201 Reloc::Model R = getTargetMachine().getRelocationModel();
11203 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11204 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11209 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11211 // If a reference to this global requires an extra load, we can't fold it.
11212 if (isGlobalStubReference(GVFlags))
11215 // If BaseGV requires a register for the PIC base, we cannot also have a
11216 // BaseReg specified.
11217 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11220 // If lower 4G is not available, then we must use rip-relative addressing.
11221 if ((M != CodeModel::Small || R != Reloc::Static) &&
11222 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11226 switch (AM.Scale) {
11232 // These scales always work.
11237 // These scales are formed with basereg+scalereg. Only accept if there is
11242 default: // Other stuff never works.
11250 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11251 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11253 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11254 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11255 if (NumBits1 <= NumBits2)
11260 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11261 if (!VT1.isInteger() || !VT2.isInteger())
11263 unsigned NumBits1 = VT1.getSizeInBits();
11264 unsigned NumBits2 = VT2.getSizeInBits();
11265 if (NumBits1 <= NumBits2)
11270 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11271 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11272 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11275 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11276 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11277 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11280 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11281 // i16 instructions are longer (0x66 prefix) and potentially slower.
11282 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11285 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11286 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11287 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11288 /// are assumed to be legal.
11290 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11292 // Very little shuffling can be done for 64-bit vectors right now.
11293 if (VT.getSizeInBits() == 64)
11296 // FIXME: pshufb, blends, shifts.
11297 return (VT.getVectorNumElements() == 2 ||
11298 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11299 isMOVLMask(M, VT) ||
11300 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11301 isPSHUFDMask(M, VT) ||
11302 isPSHUFHWMask(M, VT) ||
11303 isPSHUFLWMask(M, VT) ||
11304 isPALIGNRMask(M, VT, Subtarget) ||
11305 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11306 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11307 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11308 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11312 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11314 unsigned NumElts = VT.getVectorNumElements();
11315 // FIXME: This collection of masks seems suspect.
11318 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11319 return (isMOVLMask(Mask, VT) ||
11320 isCommutedMOVLMask(Mask, VT, true) ||
11321 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11322 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11327 //===----------------------------------------------------------------------===//
11328 // X86 Scheduler Hooks
11329 //===----------------------------------------------------------------------===//
11331 // private utility function
11332 MachineBasicBlock *
11333 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11334 MachineBasicBlock *MBB,
11341 const TargetRegisterClass *RC,
11342 bool Invert) const {
11343 // For the atomic bitwise operator, we generate
11346 // ld t1 = [bitinstr.addr]
11347 // op t2 = t1, [bitinstr.val]
11348 // not t3 = t2 (if Invert)
11350 // lcs dest = [bitinstr.addr], t3 [EAX is implicit]
11352 // fallthrough -->nextMBB
11353 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11354 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11355 MachineFunction::iterator MBBIter = MBB;
11358 /// First build the CFG
11359 MachineFunction *F = MBB->getParent();
11360 MachineBasicBlock *thisMBB = MBB;
11361 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11362 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11363 F->insert(MBBIter, newMBB);
11364 F->insert(MBBIter, nextMBB);
11366 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11367 nextMBB->splice(nextMBB->begin(), thisMBB,
11368 llvm::next(MachineBasicBlock::iterator(bInstr)),
11370 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11372 // Update thisMBB to fall through to newMBB
11373 thisMBB->addSuccessor(newMBB);
11375 // newMBB jumps to itself and fall through to nextMBB
11376 newMBB->addSuccessor(nextMBB);
11377 newMBB->addSuccessor(newMBB);
11379 // Insert instructions into newMBB based on incoming instruction
11380 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11381 "unexpected number of operands");
11382 DebugLoc dl = bInstr->getDebugLoc();
11383 MachineOperand& destOper = bInstr->getOperand(0);
11384 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11385 int numArgs = bInstr->getNumOperands() - 1;
11386 for (int i=0; i < numArgs; ++i)
11387 argOpers[i] = &bInstr->getOperand(i+1);
11389 // x86 address has 4 operands: base, index, scale, and displacement
11390 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11391 int valArgIndx = lastAddrIndx + 1;
11393 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11394 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11395 for (int i=0; i <= lastAddrIndx; ++i)
11396 (*MIB).addOperand(*argOpers[i]);
11398 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11399 assert((argOpers[valArgIndx]->isReg() ||
11400 argOpers[valArgIndx]->isImm()) &&
11401 "invalid operand");
11402 if (argOpers[valArgIndx]->isReg())
11403 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11405 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11407 (*MIB).addOperand(*argOpers[valArgIndx]);
11409 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11411 MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
11416 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11419 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11420 for (int i=0; i <= lastAddrIndx; ++i)
11421 (*MIB).addOperand(*argOpers[i]);
11423 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11424 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11425 bInstr->memoperands_end());
11427 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11428 MIB.addReg(EAXreg);
11431 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11433 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11437 // private utility function: 64 bit atomics on 32 bit host.
11438 MachineBasicBlock *
11439 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11440 MachineBasicBlock *MBB,
11445 bool Invert) const {
11446 // For the atomic bitwise operator, we generate
11447 // thisMBB (instructions are in pairs, except cmpxchg8b)
11448 // ld t1,t2 = [bitinstr.addr]
11450 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11451 // op t5, t6 <- out1, out2, [bitinstr.val]
11452 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11453 // neg t7, t8 < t5, t6 (if Invert)
11454 // mov ECX, EBX <- t5, t6
11455 // mov EAX, EDX <- t1, t2
11456 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11457 // mov t3, t4 <- EAX, EDX
11459 // result in out1, out2
11460 // fallthrough -->nextMBB
11462 const TargetRegisterClass *RC = &X86::GR32RegClass;
11463 const unsigned LoadOpc = X86::MOV32rm;
11464 const unsigned NotOpc = X86::NOT32r;
11465 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11466 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11467 MachineFunction::iterator MBBIter = MBB;
11470 /// First build the CFG
11471 MachineFunction *F = MBB->getParent();
11472 MachineBasicBlock *thisMBB = MBB;
11473 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11474 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11475 F->insert(MBBIter, newMBB);
11476 F->insert(MBBIter, nextMBB);
11478 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11479 nextMBB->splice(nextMBB->begin(), thisMBB,
11480 llvm::next(MachineBasicBlock::iterator(bInstr)),
11482 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11484 // Update thisMBB to fall through to newMBB
11485 thisMBB->addSuccessor(newMBB);
11487 // newMBB jumps to itself and fall through to nextMBB
11488 newMBB->addSuccessor(nextMBB);
11489 newMBB->addSuccessor(newMBB);
11491 DebugLoc dl = bInstr->getDebugLoc();
11492 // Insert instructions into newMBB based on incoming instruction
11493 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11494 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11495 "unexpected number of operands");
11496 MachineOperand& dest1Oper = bInstr->getOperand(0);
11497 MachineOperand& dest2Oper = bInstr->getOperand(1);
11498 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11499 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11500 argOpers[i] = &bInstr->getOperand(i+2);
11502 // We use some of the operands multiple times, so conservatively just
11503 // clear any kill flags that might be present.
11504 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11505 argOpers[i]->setIsKill(false);
11508 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11509 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11511 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11512 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11513 for (int i=0; i <= lastAddrIndx; ++i)
11514 (*MIB).addOperand(*argOpers[i]);
11515 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11516 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11517 // add 4 to displacement.
11518 for (int i=0; i <= lastAddrIndx-2; ++i)
11519 (*MIB).addOperand(*argOpers[i]);
11520 MachineOperand newOp3 = *(argOpers[3]);
11521 if (newOp3.isImm())
11522 newOp3.setImm(newOp3.getImm()+4);
11524 newOp3.setOffset(newOp3.getOffset()+4);
11525 (*MIB).addOperand(newOp3);
11526 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11528 // t3/4 are defined later, at the bottom of the loop
11529 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11530 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11531 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11532 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11533 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11534 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11536 // The subsequent operations should be using the destination registers of
11537 // the PHI instructions.
11538 t1 = dest1Oper.getReg();
11539 t2 = dest2Oper.getReg();
11541 int valArgIndx = lastAddrIndx + 1;
11542 assert((argOpers[valArgIndx]->isReg() ||
11543 argOpers[valArgIndx]->isImm()) &&
11544 "invalid operand");
11545 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11546 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11547 if (argOpers[valArgIndx]->isReg())
11548 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11550 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11551 if (regOpcL != X86::MOV32rr)
11553 (*MIB).addOperand(*argOpers[valArgIndx]);
11554 assert(argOpers[valArgIndx + 1]->isReg() ==
11555 argOpers[valArgIndx]->isReg());
11556 assert(argOpers[valArgIndx + 1]->isImm() ==
11557 argOpers[valArgIndx]->isImm());
11558 if (argOpers[valArgIndx + 1]->isReg())
11559 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11561 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11562 if (regOpcH != X86::MOV32rr)
11564 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11568 t7 = F->getRegInfo().createVirtualRegister(RC);
11569 t8 = F->getRegInfo().createVirtualRegister(RC);
11570 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
11571 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
11577 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11579 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11582 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11584 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11587 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11588 for (int i=0; i <= lastAddrIndx; ++i)
11589 (*MIB).addOperand(*argOpers[i]);
11591 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11592 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11593 bInstr->memoperands_end());
11595 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11596 MIB.addReg(X86::EAX);
11597 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11598 MIB.addReg(X86::EDX);
11601 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11603 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11607 // private utility function
11608 MachineBasicBlock *
11609 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11610 MachineBasicBlock *MBB,
11611 unsigned cmovOpc) const {
11612 // For the atomic min/max operator, we generate
11615 // ld t1 = [min/max.addr]
11616 // mov t2 = [min/max.val]
11618 // cmov[cond] t2 = t1
11620 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11622 // fallthrough -->nextMBB
11624 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11625 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11626 MachineFunction::iterator MBBIter = MBB;
11629 /// First build the CFG
11630 MachineFunction *F = MBB->getParent();
11631 MachineBasicBlock *thisMBB = MBB;
11632 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11633 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11634 F->insert(MBBIter, newMBB);
11635 F->insert(MBBIter, nextMBB);
11637 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11638 nextMBB->splice(nextMBB->begin(), thisMBB,
11639 llvm::next(MachineBasicBlock::iterator(mInstr)),
11641 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11643 // Update thisMBB to fall through to newMBB
11644 thisMBB->addSuccessor(newMBB);
11646 // newMBB jumps to newMBB and fall through to nextMBB
11647 newMBB->addSuccessor(nextMBB);
11648 newMBB->addSuccessor(newMBB);
11650 DebugLoc dl = mInstr->getDebugLoc();
11651 // Insert instructions into newMBB based on incoming instruction
11652 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11653 "unexpected number of operands");
11654 MachineOperand& destOper = mInstr->getOperand(0);
11655 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11656 int numArgs = mInstr->getNumOperands() - 1;
11657 for (int i=0; i < numArgs; ++i)
11658 argOpers[i] = &mInstr->getOperand(i+1);
11660 // x86 address has 4 operands: base, index, scale, and displacement
11661 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11662 int valArgIndx = lastAddrIndx + 1;
11664 unsigned t1 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11665 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11666 for (int i=0; i <= lastAddrIndx; ++i)
11667 (*MIB).addOperand(*argOpers[i]);
11669 // We only support register and immediate values
11670 assert((argOpers[valArgIndx]->isReg() ||
11671 argOpers[valArgIndx]->isImm()) &&
11672 "invalid operand");
11674 unsigned t2 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11675 if (argOpers[valArgIndx]->isReg())
11676 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11678 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11679 (*MIB).addOperand(*argOpers[valArgIndx]);
11681 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11684 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11689 unsigned t3 = F->getRegInfo().createVirtualRegister(&X86::GR32RegClass);
11690 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11694 // Cmp and exchange if none has modified the memory location
11695 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11696 for (int i=0; i <= lastAddrIndx; ++i)
11697 (*MIB).addOperand(*argOpers[i]);
11699 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11700 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11701 mInstr->memoperands_end());
11703 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11704 MIB.addReg(X86::EAX);
11707 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11709 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11713 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11714 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11715 // in the .td file.
11716 MachineBasicBlock *
11717 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11718 unsigned numArgs, bool memArg) const {
11719 assert(Subtarget->hasSSE42() &&
11720 "Target must have SSE4.2 or AVX features enabled");
11722 DebugLoc dl = MI->getDebugLoc();
11723 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11725 if (!Subtarget->hasAVX()) {
11727 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11729 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11732 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11734 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11737 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11738 for (unsigned i = 0; i < numArgs; ++i) {
11739 MachineOperand &Op = MI->getOperand(i+1);
11740 if (!(Op.isReg() && Op.isImplicit()))
11741 MIB.addOperand(Op);
11743 BuildMI(*BB, MI, dl,
11744 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11745 MI->getOperand(0).getReg())
11746 .addReg(X86::XMM0);
11748 MI->eraseFromParent();
11752 MachineBasicBlock *
11753 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11754 DebugLoc dl = MI->getDebugLoc();
11755 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11757 // Address into RAX/EAX, other two args into ECX, EDX.
11758 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11759 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11760 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11761 for (int i = 0; i < X86::AddrNumOperands; ++i)
11762 MIB.addOperand(MI->getOperand(i));
11764 unsigned ValOps = X86::AddrNumOperands;
11765 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11766 .addReg(MI->getOperand(ValOps).getReg());
11767 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11768 .addReg(MI->getOperand(ValOps+1).getReg());
11770 // The instruction doesn't actually take any operands though.
11771 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11773 MI->eraseFromParent(); // The pseudo is gone now.
11777 MachineBasicBlock *
11778 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11779 DebugLoc dl = MI->getDebugLoc();
11780 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11782 // First arg in ECX, the second in EAX.
11783 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11784 .addReg(MI->getOperand(0).getReg());
11785 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11786 .addReg(MI->getOperand(1).getReg());
11788 // The instruction doesn't actually take any operands though.
11789 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11791 MI->eraseFromParent(); // The pseudo is gone now.
11795 MachineBasicBlock *
11796 X86TargetLowering::EmitVAARG64WithCustomInserter(
11798 MachineBasicBlock *MBB) const {
11799 // Emit va_arg instruction on X86-64.
11801 // Operands to this pseudo-instruction:
11802 // 0 ) Output : destination address (reg)
11803 // 1-5) Input : va_list address (addr, i64mem)
11804 // 6 ) ArgSize : Size (in bytes) of vararg type
11805 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11806 // 8 ) Align : Alignment of type
11807 // 9 ) EFLAGS (implicit-def)
11809 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11810 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11812 unsigned DestReg = MI->getOperand(0).getReg();
11813 MachineOperand &Base = MI->getOperand(1);
11814 MachineOperand &Scale = MI->getOperand(2);
11815 MachineOperand &Index = MI->getOperand(3);
11816 MachineOperand &Disp = MI->getOperand(4);
11817 MachineOperand &Segment = MI->getOperand(5);
11818 unsigned ArgSize = MI->getOperand(6).getImm();
11819 unsigned ArgMode = MI->getOperand(7).getImm();
11820 unsigned Align = MI->getOperand(8).getImm();
11822 // Memory Reference
11823 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11824 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11825 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11827 // Machine Information
11828 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11829 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11830 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11831 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11832 DebugLoc DL = MI->getDebugLoc();
11834 // struct va_list {
11837 // i64 overflow_area (address)
11838 // i64 reg_save_area (address)
11840 // sizeof(va_list) = 24
11841 // alignment(va_list) = 8
11843 unsigned TotalNumIntRegs = 6;
11844 unsigned TotalNumXMMRegs = 8;
11845 bool UseGPOffset = (ArgMode == 1);
11846 bool UseFPOffset = (ArgMode == 2);
11847 unsigned MaxOffset = TotalNumIntRegs * 8 +
11848 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11850 /* Align ArgSize to a multiple of 8 */
11851 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11852 bool NeedsAlign = (Align > 8);
11854 MachineBasicBlock *thisMBB = MBB;
11855 MachineBasicBlock *overflowMBB;
11856 MachineBasicBlock *offsetMBB;
11857 MachineBasicBlock *endMBB;
11859 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11860 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11861 unsigned OffsetReg = 0;
11863 if (!UseGPOffset && !UseFPOffset) {
11864 // If we only pull from the overflow region, we don't create a branch.
11865 // We don't need to alter control flow.
11866 OffsetDestReg = 0; // unused
11867 OverflowDestReg = DestReg;
11870 overflowMBB = thisMBB;
11873 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11874 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11875 // If not, pull from overflow_area. (branch to overflowMBB)
11880 // offsetMBB overflowMBB
11885 // Registers for the PHI in endMBB
11886 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11887 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11889 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11890 MachineFunction *MF = MBB->getParent();
11891 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11892 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11893 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11895 MachineFunction::iterator MBBIter = MBB;
11898 // Insert the new basic blocks
11899 MF->insert(MBBIter, offsetMBB);
11900 MF->insert(MBBIter, overflowMBB);
11901 MF->insert(MBBIter, endMBB);
11903 // Transfer the remainder of MBB and its successor edges to endMBB.
11904 endMBB->splice(endMBB->begin(), thisMBB,
11905 llvm::next(MachineBasicBlock::iterator(MI)),
11907 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11909 // Make offsetMBB and overflowMBB successors of thisMBB
11910 thisMBB->addSuccessor(offsetMBB);
11911 thisMBB->addSuccessor(overflowMBB);
11913 // endMBB is a successor of both offsetMBB and overflowMBB
11914 offsetMBB->addSuccessor(endMBB);
11915 overflowMBB->addSuccessor(endMBB);
11917 // Load the offset value into a register
11918 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11919 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11923 .addDisp(Disp, UseFPOffset ? 4 : 0)
11924 .addOperand(Segment)
11925 .setMemRefs(MMOBegin, MMOEnd);
11927 // Check if there is enough room left to pull this argument.
11928 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11930 .addImm(MaxOffset + 8 - ArgSizeA8);
11932 // Branch to "overflowMBB" if offset >= max
11933 // Fall through to "offsetMBB" otherwise
11934 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11935 .addMBB(overflowMBB);
11938 // In offsetMBB, emit code to use the reg_save_area.
11940 assert(OffsetReg != 0);
11942 // Read the reg_save_area address.
11943 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11944 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11949 .addOperand(Segment)
11950 .setMemRefs(MMOBegin, MMOEnd);
11952 // Zero-extend the offset
11953 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11954 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11957 .addImm(X86::sub_32bit);
11959 // Add the offset to the reg_save_area to get the final address.
11960 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11961 .addReg(OffsetReg64)
11962 .addReg(RegSaveReg);
11964 // Compute the offset for the next argument
11965 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11966 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11968 .addImm(UseFPOffset ? 16 : 8);
11970 // Store it back into the va_list.
11971 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11975 .addDisp(Disp, UseFPOffset ? 4 : 0)
11976 .addOperand(Segment)
11977 .addReg(NextOffsetReg)
11978 .setMemRefs(MMOBegin, MMOEnd);
11981 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11986 // Emit code to use overflow area
11989 // Load the overflow_area address into a register.
11990 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11991 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11996 .addOperand(Segment)
11997 .setMemRefs(MMOBegin, MMOEnd);
11999 // If we need to align it, do so. Otherwise, just copy the address
12000 // to OverflowDestReg.
12002 // Align the overflow address
12003 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
12004 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
12006 // aligned_addr = (addr + (align-1)) & ~(align-1)
12007 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
12008 .addReg(OverflowAddrReg)
12011 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
12013 .addImm(~(uint64_t)(Align-1));
12015 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
12016 .addReg(OverflowAddrReg);
12019 // Compute the next overflow address after this argument.
12020 // (the overflow address should be kept 8-byte aligned)
12021 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
12022 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
12023 .addReg(OverflowDestReg)
12024 .addImm(ArgSizeA8);
12026 // Store the new overflow address.
12027 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
12032 .addOperand(Segment)
12033 .addReg(NextAddrReg)
12034 .setMemRefs(MMOBegin, MMOEnd);
12036 // If we branched, emit the PHI to the front of endMBB.
12038 BuildMI(*endMBB, endMBB->begin(), DL,
12039 TII->get(X86::PHI), DestReg)
12040 .addReg(OffsetDestReg).addMBB(offsetMBB)
12041 .addReg(OverflowDestReg).addMBB(overflowMBB);
12044 // Erase the pseudo instruction
12045 MI->eraseFromParent();
12050 MachineBasicBlock *
12051 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
12053 MachineBasicBlock *MBB) const {
12054 // Emit code to save XMM registers to the stack. The ABI says that the
12055 // number of registers to save is given in %al, so it's theoretically
12056 // possible to do an indirect jump trick to avoid saving all of them,
12057 // however this code takes a simpler approach and just executes all
12058 // of the stores if %al is non-zero. It's less code, and it's probably
12059 // easier on the hardware branch predictor, and stores aren't all that
12060 // expensive anyway.
12062 // Create the new basic blocks. One block contains all the XMM stores,
12063 // and one block is the final destination regardless of whether any
12064 // stores were performed.
12065 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
12066 MachineFunction *F = MBB->getParent();
12067 MachineFunction::iterator MBBIter = MBB;
12069 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
12070 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
12071 F->insert(MBBIter, XMMSaveMBB);
12072 F->insert(MBBIter, EndMBB);
12074 // Transfer the remainder of MBB and its successor edges to EndMBB.
12075 EndMBB->splice(EndMBB->begin(), MBB,
12076 llvm::next(MachineBasicBlock::iterator(MI)),
12078 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
12080 // The original block will now fall through to the XMM save block.
12081 MBB->addSuccessor(XMMSaveMBB);
12082 // The XMMSaveMBB will fall through to the end block.
12083 XMMSaveMBB->addSuccessor(EndMBB);
12085 // Now add the instructions.
12086 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12087 DebugLoc DL = MI->getDebugLoc();
12089 unsigned CountReg = MI->getOperand(0).getReg();
12090 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12091 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12093 if (!Subtarget->isTargetWin64()) {
12094 // If %al is 0, branch around the XMM save block.
12095 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12096 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12097 MBB->addSuccessor(EndMBB);
12100 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12101 // In the XMM save block, save all the XMM argument registers.
12102 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12103 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12104 MachineMemOperand *MMO =
12105 F->getMachineMemOperand(
12106 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12107 MachineMemOperand::MOStore,
12108 /*Size=*/16, /*Align=*/16);
12109 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12110 .addFrameIndex(RegSaveFrameIndex)
12111 .addImm(/*Scale=*/1)
12112 .addReg(/*IndexReg=*/0)
12113 .addImm(/*Disp=*/Offset)
12114 .addReg(/*Segment=*/0)
12115 .addReg(MI->getOperand(i).getReg())
12116 .addMemOperand(MMO);
12119 MI->eraseFromParent(); // The pseudo instruction is gone now.
12124 // The EFLAGS operand of SelectItr might be missing a kill marker
12125 // because there were multiple uses of EFLAGS, and ISel didn't know
12126 // which to mark. Figure out whether SelectItr should have had a
12127 // kill marker, and set it if it should. Returns the correct kill
12129 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12130 MachineBasicBlock* BB,
12131 const TargetRegisterInfo* TRI) {
12132 // Scan forward through BB for a use/def of EFLAGS.
12133 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12134 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12135 const MachineInstr& mi = *miI;
12136 if (mi.readsRegister(X86::EFLAGS))
12138 if (mi.definesRegister(X86::EFLAGS))
12139 break; // Should have kill-flag - update below.
12142 // If we hit the end of the block, check whether EFLAGS is live into a
12144 if (miI == BB->end()) {
12145 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12146 sEnd = BB->succ_end();
12147 sItr != sEnd; ++sItr) {
12148 MachineBasicBlock* succ = *sItr;
12149 if (succ->isLiveIn(X86::EFLAGS))
12154 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12155 // out. SelectMI should have a kill flag on EFLAGS.
12156 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12160 MachineBasicBlock *
12161 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12162 MachineBasicBlock *BB) const {
12163 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12164 DebugLoc DL = MI->getDebugLoc();
12166 // To "insert" a SELECT_CC instruction, we actually have to insert the
12167 // diamond control-flow pattern. The incoming instruction knows the
12168 // destination vreg to set, the condition code register to branch on, the
12169 // true/false values to select between, and a branch opcode to use.
12170 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12171 MachineFunction::iterator It = BB;
12177 // cmpTY ccX, r1, r2
12179 // fallthrough --> copy0MBB
12180 MachineBasicBlock *thisMBB = BB;
12181 MachineFunction *F = BB->getParent();
12182 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12183 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12184 F->insert(It, copy0MBB);
12185 F->insert(It, sinkMBB);
12187 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12188 // live into the sink and copy blocks.
12189 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12190 if (!MI->killsRegister(X86::EFLAGS) &&
12191 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12192 copy0MBB->addLiveIn(X86::EFLAGS);
12193 sinkMBB->addLiveIn(X86::EFLAGS);
12196 // Transfer the remainder of BB and its successor edges to sinkMBB.
12197 sinkMBB->splice(sinkMBB->begin(), BB,
12198 llvm::next(MachineBasicBlock::iterator(MI)),
12200 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12202 // Add the true and fallthrough blocks as its successors.
12203 BB->addSuccessor(copy0MBB);
12204 BB->addSuccessor(sinkMBB);
12206 // Create the conditional branch instruction.
12208 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12209 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12212 // %FalseValue = ...
12213 // # fallthrough to sinkMBB
12214 copy0MBB->addSuccessor(sinkMBB);
12217 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12219 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12220 TII->get(X86::PHI), MI->getOperand(0).getReg())
12221 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12222 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12224 MI->eraseFromParent(); // The pseudo instruction is gone now.
12228 MachineBasicBlock *
12229 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12230 bool Is64Bit) const {
12231 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12232 DebugLoc DL = MI->getDebugLoc();
12233 MachineFunction *MF = BB->getParent();
12234 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12236 assert(getTargetMachine().Options.EnableSegmentedStacks);
12238 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12239 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12242 // ... [Till the alloca]
12243 // If stacklet is not large enough, jump to mallocMBB
12246 // Allocate by subtracting from RSP
12247 // Jump to continueMBB
12250 // Allocate by call to runtime
12254 // [rest of original BB]
12257 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12258 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12259 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12261 MachineRegisterInfo &MRI = MF->getRegInfo();
12262 const TargetRegisterClass *AddrRegClass =
12263 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12265 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12266 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12267 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12268 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12269 sizeVReg = MI->getOperand(1).getReg(),
12270 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12272 MachineFunction::iterator MBBIter = BB;
12275 MF->insert(MBBIter, bumpMBB);
12276 MF->insert(MBBIter, mallocMBB);
12277 MF->insert(MBBIter, continueMBB);
12279 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12280 (MachineBasicBlock::iterator(MI)), BB->end());
12281 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12283 // Add code to the main basic block to check if the stack limit has been hit,
12284 // and if so, jump to mallocMBB otherwise to bumpMBB.
12285 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12286 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12287 .addReg(tmpSPVReg).addReg(sizeVReg);
12288 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12289 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12290 .addReg(SPLimitVReg);
12291 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12293 // bumpMBB simply decreases the stack pointer, since we know the current
12294 // stacklet has enough space.
12295 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12296 .addReg(SPLimitVReg);
12297 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12298 .addReg(SPLimitVReg);
12299 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12301 // Calls into a routine in libgcc to allocate more space from the heap.
12302 const uint32_t *RegMask =
12303 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12305 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12307 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12308 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12309 .addRegMask(RegMask)
12310 .addReg(X86::RAX, RegState::ImplicitDefine);
12312 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12314 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12315 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12316 .addExternalSymbol("__morestack_allocate_stack_space")
12317 .addRegMask(RegMask)
12318 .addReg(X86::EAX, RegState::ImplicitDefine);
12322 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12325 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12326 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12327 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12329 // Set up the CFG correctly.
12330 BB->addSuccessor(bumpMBB);
12331 BB->addSuccessor(mallocMBB);
12332 mallocMBB->addSuccessor(continueMBB);
12333 bumpMBB->addSuccessor(continueMBB);
12335 // Take care of the PHI nodes.
12336 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12337 MI->getOperand(0).getReg())
12338 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12339 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12341 // Delete the original pseudo instruction.
12342 MI->eraseFromParent();
12345 return continueMBB;
12348 MachineBasicBlock *
12349 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12350 MachineBasicBlock *BB) const {
12351 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12352 DebugLoc DL = MI->getDebugLoc();
12354 assert(!Subtarget->isTargetEnvMacho());
12356 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12357 // non-trivial part is impdef of ESP.
12359 if (Subtarget->isTargetWin64()) {
12360 if (Subtarget->isTargetCygMing()) {
12361 // ___chkstk(Mingw64):
12362 // Clobbers R10, R11, RAX and EFLAGS.
12364 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12365 .addExternalSymbol("___chkstk")
12366 .addReg(X86::RAX, RegState::Implicit)
12367 .addReg(X86::RSP, RegState::Implicit)
12368 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12369 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12370 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12372 // __chkstk(MSVCRT): does not update stack pointer.
12373 // Clobbers R10, R11 and EFLAGS.
12374 // FIXME: RAX(allocated size) might be reused and not killed.
12375 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12376 .addExternalSymbol("__chkstk")
12377 .addReg(X86::RAX, RegState::Implicit)
12378 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12379 // RAX has the offset to subtracted from RSP.
12380 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12385 const char *StackProbeSymbol =
12386 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12388 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12389 .addExternalSymbol(StackProbeSymbol)
12390 .addReg(X86::EAX, RegState::Implicit)
12391 .addReg(X86::ESP, RegState::Implicit)
12392 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12393 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12394 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12397 MI->eraseFromParent(); // The pseudo instruction is gone now.
12401 MachineBasicBlock *
12402 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12403 MachineBasicBlock *BB) const {
12404 // This is pretty easy. We're taking the value that we received from
12405 // our load from the relocation, sticking it in either RDI (x86-64)
12406 // or EAX and doing an indirect call. The return value will then
12407 // be in the normal return register.
12408 const X86InstrInfo *TII
12409 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12410 DebugLoc DL = MI->getDebugLoc();
12411 MachineFunction *F = BB->getParent();
12413 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12414 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12416 // Get a register mask for the lowered call.
12417 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12418 // proper register mask.
12419 const uint32_t *RegMask =
12420 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12421 if (Subtarget->is64Bit()) {
12422 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12423 TII->get(X86::MOV64rm), X86::RDI)
12425 .addImm(0).addReg(0)
12426 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12427 MI->getOperand(3).getTargetFlags())
12429 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12430 addDirectMem(MIB, X86::RDI);
12431 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12432 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12433 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12434 TII->get(X86::MOV32rm), X86::EAX)
12436 .addImm(0).addReg(0)
12437 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12438 MI->getOperand(3).getTargetFlags())
12440 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12441 addDirectMem(MIB, X86::EAX);
12442 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12444 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12445 TII->get(X86::MOV32rm), X86::EAX)
12446 .addReg(TII->getGlobalBaseReg(F))
12447 .addImm(0).addReg(0)
12448 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12449 MI->getOperand(3).getTargetFlags())
12451 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12452 addDirectMem(MIB, X86::EAX);
12453 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12456 MI->eraseFromParent(); // The pseudo instruction is gone now.
12460 MachineBasicBlock *
12461 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12462 MachineBasicBlock *BB) const {
12463 switch (MI->getOpcode()) {
12464 default: llvm_unreachable("Unexpected instr type to insert");
12465 case X86::TAILJMPd64:
12466 case X86::TAILJMPr64:
12467 case X86::TAILJMPm64:
12468 llvm_unreachable("TAILJMP64 would not be touched here.");
12469 case X86::TCRETURNdi64:
12470 case X86::TCRETURNri64:
12471 case X86::TCRETURNmi64:
12473 case X86::WIN_ALLOCA:
12474 return EmitLoweredWinAlloca(MI, BB);
12475 case X86::SEG_ALLOCA_32:
12476 return EmitLoweredSegAlloca(MI, BB, false);
12477 case X86::SEG_ALLOCA_64:
12478 return EmitLoweredSegAlloca(MI, BB, true);
12479 case X86::TLSCall_32:
12480 case X86::TLSCall_64:
12481 return EmitLoweredTLSCall(MI, BB);
12482 case X86::CMOV_GR8:
12483 case X86::CMOV_FR32:
12484 case X86::CMOV_FR64:
12485 case X86::CMOV_V4F32:
12486 case X86::CMOV_V2F64:
12487 case X86::CMOV_V2I64:
12488 case X86::CMOV_V8F32:
12489 case X86::CMOV_V4F64:
12490 case X86::CMOV_V4I64:
12491 case X86::CMOV_GR16:
12492 case X86::CMOV_GR32:
12493 case X86::CMOV_RFP32:
12494 case X86::CMOV_RFP64:
12495 case X86::CMOV_RFP80:
12496 return EmitLoweredSelect(MI, BB);
12498 case X86::FP32_TO_INT16_IN_MEM:
12499 case X86::FP32_TO_INT32_IN_MEM:
12500 case X86::FP32_TO_INT64_IN_MEM:
12501 case X86::FP64_TO_INT16_IN_MEM:
12502 case X86::FP64_TO_INT32_IN_MEM:
12503 case X86::FP64_TO_INT64_IN_MEM:
12504 case X86::FP80_TO_INT16_IN_MEM:
12505 case X86::FP80_TO_INT32_IN_MEM:
12506 case X86::FP80_TO_INT64_IN_MEM: {
12507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12508 DebugLoc DL = MI->getDebugLoc();
12510 // Change the floating point control register to use "round towards zero"
12511 // mode when truncating to an integer value.
12512 MachineFunction *F = BB->getParent();
12513 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12514 addFrameReference(BuildMI(*BB, MI, DL,
12515 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12517 // Load the old value of the high byte of the control word...
12519 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
12520 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12523 // Set the high part to be round to zero...
12524 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12527 // Reload the modified control word now...
12528 addFrameReference(BuildMI(*BB, MI, DL,
12529 TII->get(X86::FLDCW16m)), CWFrameIdx);
12531 // Restore the memory image of control word to original value
12532 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12535 // Get the X86 opcode to use.
12537 switch (MI->getOpcode()) {
12538 default: llvm_unreachable("illegal opcode!");
12539 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12540 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12541 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12542 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12543 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12544 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12545 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12546 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12547 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12551 MachineOperand &Op = MI->getOperand(0);
12553 AM.BaseType = X86AddressMode::RegBase;
12554 AM.Base.Reg = Op.getReg();
12556 AM.BaseType = X86AddressMode::FrameIndexBase;
12557 AM.Base.FrameIndex = Op.getIndex();
12559 Op = MI->getOperand(1);
12561 AM.Scale = Op.getImm();
12562 Op = MI->getOperand(2);
12564 AM.IndexReg = Op.getImm();
12565 Op = MI->getOperand(3);
12566 if (Op.isGlobal()) {
12567 AM.GV = Op.getGlobal();
12569 AM.Disp = Op.getImm();
12571 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12572 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12574 // Reload the original control word now.
12575 addFrameReference(BuildMI(*BB, MI, DL,
12576 TII->get(X86::FLDCW16m)), CWFrameIdx);
12578 MI->eraseFromParent(); // The pseudo instruction is gone now.
12581 // String/text processing lowering.
12582 case X86::PCMPISTRM128REG:
12583 case X86::VPCMPISTRM128REG:
12584 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12585 case X86::PCMPISTRM128MEM:
12586 case X86::VPCMPISTRM128MEM:
12587 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12588 case X86::PCMPESTRM128REG:
12589 case X86::VPCMPESTRM128REG:
12590 return EmitPCMP(MI, BB, 5, false /* in mem */);
12591 case X86::PCMPESTRM128MEM:
12592 case X86::VPCMPESTRM128MEM:
12593 return EmitPCMP(MI, BB, 5, true /* in mem */);
12595 // Thread synchronization.
12597 return EmitMonitor(MI, BB);
12599 return EmitMwait(MI, BB);
12601 // Atomic Lowering.
12602 case X86::ATOMAND32:
12603 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12604 X86::AND32ri, X86::MOV32rm,
12606 X86::NOT32r, X86::EAX,
12607 &X86::GR32RegClass);
12608 case X86::ATOMOR32:
12609 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12610 X86::OR32ri, X86::MOV32rm,
12612 X86::NOT32r, X86::EAX,
12613 &X86::GR32RegClass);
12614 case X86::ATOMXOR32:
12615 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12616 X86::XOR32ri, X86::MOV32rm,
12618 X86::NOT32r, X86::EAX,
12619 &X86::GR32RegClass);
12620 case X86::ATOMNAND32:
12621 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12622 X86::AND32ri, X86::MOV32rm,
12624 X86::NOT32r, X86::EAX,
12625 &X86::GR32RegClass, true);
12626 case X86::ATOMMIN32:
12627 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12628 case X86::ATOMMAX32:
12629 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12630 case X86::ATOMUMIN32:
12631 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12632 case X86::ATOMUMAX32:
12633 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12635 case X86::ATOMAND16:
12636 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12637 X86::AND16ri, X86::MOV16rm,
12639 X86::NOT16r, X86::AX,
12640 &X86::GR16RegClass);
12641 case X86::ATOMOR16:
12642 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12643 X86::OR16ri, X86::MOV16rm,
12645 X86::NOT16r, X86::AX,
12646 &X86::GR16RegClass);
12647 case X86::ATOMXOR16:
12648 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12649 X86::XOR16ri, X86::MOV16rm,
12651 X86::NOT16r, X86::AX,
12652 &X86::GR16RegClass);
12653 case X86::ATOMNAND16:
12654 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12655 X86::AND16ri, X86::MOV16rm,
12657 X86::NOT16r, X86::AX,
12658 &X86::GR16RegClass, true);
12659 case X86::ATOMMIN16:
12660 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12661 case X86::ATOMMAX16:
12662 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12663 case X86::ATOMUMIN16:
12664 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12665 case X86::ATOMUMAX16:
12666 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12668 case X86::ATOMAND8:
12669 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12670 X86::AND8ri, X86::MOV8rm,
12672 X86::NOT8r, X86::AL,
12673 &X86::GR8RegClass);
12675 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12676 X86::OR8ri, X86::MOV8rm,
12678 X86::NOT8r, X86::AL,
12679 &X86::GR8RegClass);
12680 case X86::ATOMXOR8:
12681 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12682 X86::XOR8ri, X86::MOV8rm,
12684 X86::NOT8r, X86::AL,
12685 &X86::GR8RegClass);
12686 case X86::ATOMNAND8:
12687 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12688 X86::AND8ri, X86::MOV8rm,
12690 X86::NOT8r, X86::AL,
12691 &X86::GR8RegClass, true);
12692 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12693 // This group is for 64-bit host.
12694 case X86::ATOMAND64:
12695 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12696 X86::AND64ri32, X86::MOV64rm,
12698 X86::NOT64r, X86::RAX,
12699 &X86::GR64RegClass);
12700 case X86::ATOMOR64:
12701 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12702 X86::OR64ri32, X86::MOV64rm,
12704 X86::NOT64r, X86::RAX,
12705 &X86::GR64RegClass);
12706 case X86::ATOMXOR64:
12707 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12708 X86::XOR64ri32, X86::MOV64rm,
12710 X86::NOT64r, X86::RAX,
12711 &X86::GR64RegClass);
12712 case X86::ATOMNAND64:
12713 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12714 X86::AND64ri32, X86::MOV64rm,
12716 X86::NOT64r, X86::RAX,
12717 &X86::GR64RegClass, true);
12718 case X86::ATOMMIN64:
12719 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12720 case X86::ATOMMAX64:
12721 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12722 case X86::ATOMUMIN64:
12723 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12724 case X86::ATOMUMAX64:
12725 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12727 // This group does 64-bit operations on a 32-bit host.
12728 case X86::ATOMAND6432:
12729 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12730 X86::AND32rr, X86::AND32rr,
12731 X86::AND32ri, X86::AND32ri,
12733 case X86::ATOMOR6432:
12734 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12735 X86::OR32rr, X86::OR32rr,
12736 X86::OR32ri, X86::OR32ri,
12738 case X86::ATOMXOR6432:
12739 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12740 X86::XOR32rr, X86::XOR32rr,
12741 X86::XOR32ri, X86::XOR32ri,
12743 case X86::ATOMNAND6432:
12744 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12745 X86::AND32rr, X86::AND32rr,
12746 X86::AND32ri, X86::AND32ri,
12748 case X86::ATOMADD6432:
12749 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12750 X86::ADD32rr, X86::ADC32rr,
12751 X86::ADD32ri, X86::ADC32ri,
12753 case X86::ATOMSUB6432:
12754 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12755 X86::SUB32rr, X86::SBB32rr,
12756 X86::SUB32ri, X86::SBB32ri,
12758 case X86::ATOMSWAP6432:
12759 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12760 X86::MOV32rr, X86::MOV32rr,
12761 X86::MOV32ri, X86::MOV32ri,
12763 case X86::VASTART_SAVE_XMM_REGS:
12764 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12766 case X86::VAARG_64:
12767 return EmitVAARG64WithCustomInserter(MI, BB);
12771 //===----------------------------------------------------------------------===//
12772 // X86 Optimization Hooks
12773 //===----------------------------------------------------------------------===//
12775 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12778 const SelectionDAG &DAG,
12779 unsigned Depth) const {
12780 unsigned BitWidth = KnownZero.getBitWidth();
12781 unsigned Opc = Op.getOpcode();
12782 assert((Opc >= ISD::BUILTIN_OP_END ||
12783 Opc == ISD::INTRINSIC_WO_CHAIN ||
12784 Opc == ISD::INTRINSIC_W_CHAIN ||
12785 Opc == ISD::INTRINSIC_VOID) &&
12786 "Should use MaskedValueIsZero if you don't know whether Op"
12787 " is a target node!");
12789 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
12803 // These nodes' second result is a boolean.
12804 if (Op.getResNo() == 0)
12807 case X86ISD::SETCC:
12808 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
12810 case ISD::INTRINSIC_WO_CHAIN: {
12811 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12812 unsigned NumLoBits = 0;
12815 case Intrinsic::x86_sse_movmsk_ps:
12816 case Intrinsic::x86_avx_movmsk_ps_256:
12817 case Intrinsic::x86_sse2_movmsk_pd:
12818 case Intrinsic::x86_avx_movmsk_pd_256:
12819 case Intrinsic::x86_mmx_pmovmskb:
12820 case Intrinsic::x86_sse2_pmovmskb_128:
12821 case Intrinsic::x86_avx2_pmovmskb: {
12822 // High bits of movmskp{s|d}, pmovmskb are known zero.
12824 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12825 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12826 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12827 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12828 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12829 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12830 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12831 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12833 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
12842 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12843 unsigned Depth) const {
12844 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12845 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12846 return Op.getValueType().getScalarType().getSizeInBits();
12852 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12853 /// node is a GlobalAddress + offset.
12854 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12855 const GlobalValue* &GA,
12856 int64_t &Offset) const {
12857 if (N->getOpcode() == X86ISD::Wrapper) {
12858 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12859 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12860 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12864 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12867 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12868 /// same as extracting the high 128-bit part of 256-bit vector and then
12869 /// inserting the result into the low part of a new 256-bit vector
12870 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12871 EVT VT = SVOp->getValueType(0);
12872 int NumElems = VT.getVectorNumElements();
12874 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12875 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12876 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12877 SVOp->getMaskElt(j) >= 0)
12883 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12884 /// same as extracting the low 128-bit part of 256-bit vector and then
12885 /// inserting the result into the high part of a new 256-bit vector
12886 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12887 EVT VT = SVOp->getValueType(0);
12888 int NumElems = VT.getVectorNumElements();
12890 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12891 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12892 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12893 SVOp->getMaskElt(j) >= 0)
12899 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12900 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12901 TargetLowering::DAGCombinerInfo &DCI,
12902 const X86Subtarget* Subtarget) {
12903 DebugLoc dl = N->getDebugLoc();
12904 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12905 SDValue V1 = SVOp->getOperand(0);
12906 SDValue V2 = SVOp->getOperand(1);
12907 EVT VT = SVOp->getValueType(0);
12908 int NumElems = VT.getVectorNumElements();
12910 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12911 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12915 // V UNDEF BUILD_VECTOR UNDEF
12917 // CONCAT_VECTOR CONCAT_VECTOR
12920 // RESULT: V + zero extended
12922 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12923 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12924 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12927 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12930 // To match the shuffle mask, the first half of the mask should
12931 // be exactly the first vector, and all the rest a splat with the
12932 // first element of the second one.
12933 for (int i = 0; i < NumElems/2; ++i)
12934 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12935 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12938 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12939 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12940 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12941 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12943 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12945 Ld->getPointerInfo(),
12946 Ld->getAlignment(),
12947 false/*isVolatile*/, true/*ReadMem*/,
12948 false/*WriteMem*/);
12949 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12952 // Emit a zeroed vector and insert the desired subvector on its
12954 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12955 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12956 DAG.getConstant(0, MVT::i32), DAG, dl);
12957 return DCI.CombineTo(N, InsV);
12960 //===--------------------------------------------------------------------===//
12961 // Combine some shuffles into subvector extracts and inserts:
12964 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12965 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12966 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12968 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V,
12969 DAG.getConstant(0, MVT::i32), DAG, dl);
12970 return DCI.CombineTo(N, InsV);
12973 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12974 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12975 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12976 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V,
12977 DAG.getConstant(NumElems/2, MVT::i32),
12979 return DCI.CombineTo(N, InsV);
12985 /// PerformShuffleCombine - Performs several different shuffle combines.
12986 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12987 TargetLowering::DAGCombinerInfo &DCI,
12988 const X86Subtarget *Subtarget) {
12989 DebugLoc dl = N->getDebugLoc();
12990 EVT VT = N->getValueType(0);
12992 // Don't create instructions with illegal types after legalize types has run.
12993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12994 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12997 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12998 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12999 N->getOpcode() == ISD::VECTOR_SHUFFLE)
13000 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
13002 // Only handle 128 wide vector from here on.
13003 if (VT.getSizeInBits() != 128)
13006 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
13007 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
13008 // consecutive, non-overlapping, and in the right order.
13009 SmallVector<SDValue, 16> Elts;
13010 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
13011 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
13013 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
13017 /// PerformTruncateCombine - Converts truncate operation to
13018 /// a sequence of vector shuffle operations.
13019 /// It is possible when we truncate 256-bit vector to 128-bit vector
13021 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
13022 DAGCombinerInfo &DCI) const {
13023 if (!DCI.isBeforeLegalizeOps())
13026 if (!Subtarget->hasAVX()) return SDValue();
13028 EVT VT = N->getValueType(0);
13029 SDValue Op = N->getOperand(0);
13030 EVT OpVT = Op.getValueType();
13031 DebugLoc dl = N->getDebugLoc();
13033 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
13035 if (Subtarget->hasAVX2()) {
13036 // AVX2: v4i64 -> v4i32
13039 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13041 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v8i32, Op);
13042 Op = DAG.getVectorShuffle(MVT::v8i32, dl, Op, DAG.getUNDEF(MVT::v8i32),
13045 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op,
13046 DAG.getIntPtrConstant(0));
13049 // AVX: v4i64 -> v4i32
13050 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13051 DAG.getIntPtrConstant(0));
13053 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13054 DAG.getIntPtrConstant(2));
13056 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13057 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13060 static const int ShufMask1[] = {0, 2, 0, 0};
13062 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT), ShufMask1);
13063 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT), ShufMask1);
13066 static const int ShufMask2[] = {0, 1, 4, 5};
13068 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
13071 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
13073 if (Subtarget->hasAVX2()) {
13074 // AVX2: v8i32 -> v8i16
13076 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v32i8, Op);
13079 SmallVector<SDValue,32> pshufbMask;
13080 for (unsigned i = 0; i < 2; ++i) {
13081 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
13082 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
13083 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
13084 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
13085 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
13086 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
13087 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
13088 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
13089 for (unsigned j = 0; j < 8; ++j)
13090 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
13092 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v32i8,
13093 &pshufbMask[0], 32);
13094 Op = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, Op, BV);
13096 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i64, Op);
13098 static const int ShufMask[] = {0, 2, -1, -1};
13099 Op = DAG.getVectorShuffle(MVT::v4i64, dl, Op, DAG.getUNDEF(MVT::v4i64),
13102 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
13103 DAG.getIntPtrConstant(0));
13105 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
13108 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13109 DAG.getIntPtrConstant(0));
13111 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
13112 DAG.getIntPtrConstant(4));
13114 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
13115 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
13118 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13119 -1, -1, -1, -1, -1, -1, -1, -1};
13121 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, DAG.getUNDEF(MVT::v16i8),
13123 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, DAG.getUNDEF(MVT::v16i8),
13126 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
13127 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
13130 static const int ShufMask2[] = {0, 1, 4, 5};
13132 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
13133 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13139 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
13140 /// specific shuffle of a load can be folded into a single element load.
13141 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
13142 /// shuffles have been customed lowered so we need to handle those here.
13143 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
13144 TargetLowering::DAGCombinerInfo &DCI) {
13145 if (DCI.isBeforeLegalizeOps())
13148 SDValue InVec = N->getOperand(0);
13149 SDValue EltNo = N->getOperand(1);
13151 if (!isa<ConstantSDNode>(EltNo))
13154 EVT VT = InVec.getValueType();
13156 bool HasShuffleIntoBitcast = false;
13157 if (InVec.getOpcode() == ISD::BITCAST) {
13158 // Don't duplicate a load with other uses.
13159 if (!InVec.hasOneUse())
13161 EVT BCVT = InVec.getOperand(0).getValueType();
13162 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
13164 InVec = InVec.getOperand(0);
13165 HasShuffleIntoBitcast = true;
13168 if (!isTargetShuffle(InVec.getOpcode()))
13171 // Don't duplicate a load with other uses.
13172 if (!InVec.hasOneUse())
13175 SmallVector<int, 16> ShuffleMask;
13177 if (!getTargetShuffleMask(InVec.getNode(), VT, ShuffleMask, UnaryShuffle))
13180 // Select the input vector, guarding against out of range extract vector.
13181 unsigned NumElems = VT.getVectorNumElements();
13182 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
13183 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
13184 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
13185 : InVec.getOperand(1);
13187 // If inputs to shuffle are the same for both ops, then allow 2 uses
13188 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
13190 if (LdNode.getOpcode() == ISD::BITCAST) {
13191 // Don't duplicate a load with other uses.
13192 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
13195 AllowedUses = 1; // only allow 1 load use if we have a bitcast
13196 LdNode = LdNode.getOperand(0);
13199 if (!ISD::isNormalLoad(LdNode.getNode()))
13202 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
13204 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
13207 if (HasShuffleIntoBitcast) {
13208 // If there's a bitcast before the shuffle, check if the load type and
13209 // alignment is valid.
13210 unsigned Align = LN0->getAlignment();
13211 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13212 unsigned NewAlign = TLI.getTargetData()->
13213 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
13215 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
13219 // All checks match so transform back to vector_shuffle so that DAG combiner
13220 // can finish the job
13221 DebugLoc dl = N->getDebugLoc();
13223 // Create shuffle node taking into account the case that its a unary shuffle
13224 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
13225 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
13226 InVec.getOperand(0), Shuffle,
13228 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
13229 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
13233 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13234 /// generation and convert it from being a bunch of shuffles and extracts
13235 /// to a simple store and scalar loads to extract the elements.
13236 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13237 TargetLowering::DAGCombinerInfo &DCI) {
13238 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
13239 if (NewOp.getNode())
13242 SDValue InputVector = N->getOperand(0);
13244 // Only operate on vectors of 4 elements, where the alternative shuffling
13245 // gets to be more expensive.
13246 if (InputVector.getValueType() != MVT::v4i32)
13249 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13250 // single use which is a sign-extend or zero-extend, and all elements are
13252 SmallVector<SDNode *, 4> Uses;
13253 unsigned ExtractedElements = 0;
13254 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13255 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13256 if (UI.getUse().getResNo() != InputVector.getResNo())
13259 SDNode *Extract = *UI;
13260 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13263 if (Extract->getValueType(0) != MVT::i32)
13265 if (!Extract->hasOneUse())
13267 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13268 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13270 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13273 // Record which element was extracted.
13274 ExtractedElements |=
13275 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13277 Uses.push_back(Extract);
13280 // If not all the elements were used, this may not be worthwhile.
13281 if (ExtractedElements != 15)
13284 // Ok, we've now decided to do the transformation.
13285 DebugLoc dl = InputVector.getDebugLoc();
13287 // Store the value to a temporary stack slot.
13288 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13289 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13290 MachinePointerInfo(), false, false, 0);
13292 // Replace each use (extract) with a load of the appropriate element.
13293 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13294 UE = Uses.end(); UI != UE; ++UI) {
13295 SDNode *Extract = *UI;
13297 // cOMpute the element's address.
13298 SDValue Idx = Extract->getOperand(1);
13300 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13301 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13303 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13305 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13306 StackPtr, OffsetVal);
13308 // Load the scalar.
13309 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13310 ScalarAddr, MachinePointerInfo(),
13311 false, false, false, 0);
13313 // Replace the exact with the load.
13314 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13317 // The replacement was made in place; don't return anything.
13321 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13323 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13324 TargetLowering::DAGCombinerInfo &DCI,
13325 const X86Subtarget *Subtarget) {
13328 DebugLoc DL = N->getDebugLoc();
13329 SDValue Cond = N->getOperand(0);
13330 // Get the LHS/RHS of the select.
13331 SDValue LHS = N->getOperand(1);
13332 SDValue RHS = N->getOperand(2);
13333 EVT VT = LHS.getValueType();
13335 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13336 // instructions match the semantics of the common C idiom x<y?x:y but not
13337 // x<=y?x:y, because of how they handle negative zero (which can be
13338 // ignored in unsafe-math mode).
13339 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13340 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13341 (Subtarget->hasSSE2() ||
13342 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13343 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13345 unsigned Opcode = 0;
13346 // Check for x CC y ? x : y.
13347 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13348 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13352 // Converting this to a min would handle NaNs incorrectly, and swapping
13353 // the operands would cause it to handle comparisons between positive
13354 // and negative zero incorrectly.
13355 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13356 if (!DAG.getTarget().Options.UnsafeFPMath &&
13357 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13359 std::swap(LHS, RHS);
13361 Opcode = X86ISD::FMIN;
13364 // Converting this to a min would handle comparisons between positive
13365 // and negative zero incorrectly.
13366 if (!DAG.getTarget().Options.UnsafeFPMath &&
13367 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13369 Opcode = X86ISD::FMIN;
13372 // Converting this to a min would handle both negative zeros and NaNs
13373 // incorrectly, but we can swap the operands to fix both.
13374 std::swap(LHS, RHS);
13378 Opcode = X86ISD::FMIN;
13382 // Converting this to a max would handle comparisons between positive
13383 // and negative zero incorrectly.
13384 if (!DAG.getTarget().Options.UnsafeFPMath &&
13385 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13387 Opcode = X86ISD::FMAX;
13390 // Converting this to a max would handle NaNs incorrectly, and swapping
13391 // the operands would cause it to handle comparisons between positive
13392 // and negative zero incorrectly.
13393 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13394 if (!DAG.getTarget().Options.UnsafeFPMath &&
13395 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13397 std::swap(LHS, RHS);
13399 Opcode = X86ISD::FMAX;
13402 // Converting this to a max would handle both negative zeros and NaNs
13403 // incorrectly, but we can swap the operands to fix both.
13404 std::swap(LHS, RHS);
13408 Opcode = X86ISD::FMAX;
13411 // Check for x CC y ? y : x -- a min/max with reversed arms.
13412 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13413 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13417 // Converting this to a min would handle comparisons between positive
13418 // and negative zero incorrectly, and swapping the operands would
13419 // cause it to handle NaNs incorrectly.
13420 if (!DAG.getTarget().Options.UnsafeFPMath &&
13421 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13422 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13424 std::swap(LHS, RHS);
13426 Opcode = X86ISD::FMIN;
13429 // Converting this to a min would handle NaNs incorrectly.
13430 if (!DAG.getTarget().Options.UnsafeFPMath &&
13431 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13433 Opcode = X86ISD::FMIN;
13436 // Converting this to a min would handle both negative zeros and NaNs
13437 // incorrectly, but we can swap the operands to fix both.
13438 std::swap(LHS, RHS);
13442 Opcode = X86ISD::FMIN;
13446 // Converting this to a max would handle NaNs incorrectly.
13447 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13449 Opcode = X86ISD::FMAX;
13452 // Converting this to a max would handle comparisons between positive
13453 // and negative zero incorrectly, and swapping the operands would
13454 // cause it to handle NaNs incorrectly.
13455 if (!DAG.getTarget().Options.UnsafeFPMath &&
13456 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13457 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13459 std::swap(LHS, RHS);
13461 Opcode = X86ISD::FMAX;
13464 // Converting this to a max would handle both negative zeros and NaNs
13465 // incorrectly, but we can swap the operands to fix both.
13466 std::swap(LHS, RHS);
13470 Opcode = X86ISD::FMAX;
13476 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13479 // If this is a select between two integer constants, try to do some
13481 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13482 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13483 // Don't do this for crazy integer types.
13484 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13485 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13486 // so that TrueC (the true value) is larger than FalseC.
13487 bool NeedsCondInvert = false;
13489 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13490 // Efficiently invertible.
13491 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13492 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13493 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13494 NeedsCondInvert = true;
13495 std::swap(TrueC, FalseC);
13498 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13499 if (FalseC->getAPIntValue() == 0 &&
13500 TrueC->getAPIntValue().isPowerOf2()) {
13501 if (NeedsCondInvert) // Invert the condition if needed.
13502 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13503 DAG.getConstant(1, Cond.getValueType()));
13505 // Zero extend the condition if needed.
13506 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13508 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13509 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13510 DAG.getConstant(ShAmt, MVT::i8));
13513 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13514 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13515 if (NeedsCondInvert) // Invert the condition if needed.
13516 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13517 DAG.getConstant(1, Cond.getValueType()));
13519 // Zero extend the condition if needed.
13520 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13521 FalseC->getValueType(0), Cond);
13522 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13523 SDValue(FalseC, 0));
13526 // Optimize cases that will turn into an LEA instruction. This requires
13527 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13528 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13529 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13530 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13532 bool isFastMultiplier = false;
13534 switch ((unsigned char)Diff) {
13536 case 1: // result = add base, cond
13537 case 2: // result = lea base( , cond*2)
13538 case 3: // result = lea base(cond, cond*2)
13539 case 4: // result = lea base( , cond*4)
13540 case 5: // result = lea base(cond, cond*4)
13541 case 8: // result = lea base( , cond*8)
13542 case 9: // result = lea base(cond, cond*8)
13543 isFastMultiplier = true;
13548 if (isFastMultiplier) {
13549 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13550 if (NeedsCondInvert) // Invert the condition if needed.
13551 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13552 DAG.getConstant(1, Cond.getValueType()));
13554 // Zero extend the condition if needed.
13555 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13557 // Scale the condition by the difference.
13559 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13560 DAG.getConstant(Diff, Cond.getValueType()));
13562 // Add the base if non-zero.
13563 if (FalseC->getAPIntValue() != 0)
13564 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13565 SDValue(FalseC, 0));
13572 // Canonicalize max and min:
13573 // (x > y) ? x : y -> (x >= y) ? x : y
13574 // (x < y) ? x : y -> (x <= y) ? x : y
13575 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13576 // the need for an extra compare
13577 // against zero. e.g.
13578 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13580 // testl %edi, %edi
13582 // cmovgl %edi, %eax
13586 // cmovsl %eax, %edi
13587 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13588 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13589 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13590 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13595 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13596 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13597 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13598 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13603 // If we know that this node is legal then we know that it is going to be
13604 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13605 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13606 // to simplify previous instructions.
13607 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13608 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13609 !DCI.isBeforeLegalize() &&
13610 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13611 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13612 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13613 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13615 APInt KnownZero, KnownOne;
13616 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13617 DCI.isBeforeLegalizeOps());
13618 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13619 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13620 DCI.CommitTargetLoweringOpt(TLO);
13626 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13627 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13628 TargetLowering::DAGCombinerInfo &DCI) {
13629 DebugLoc DL = N->getDebugLoc();
13631 // If the flag operand isn't dead, don't touch this CMOV.
13632 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13635 SDValue FalseOp = N->getOperand(0);
13636 SDValue TrueOp = N->getOperand(1);
13637 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13638 SDValue Cond = N->getOperand(3);
13639 if (CC == X86::COND_E || CC == X86::COND_NE) {
13640 switch (Cond.getOpcode()) {
13644 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13645 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13646 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13650 // If this is a select between two integer constants, try to do some
13651 // optimizations. Note that the operands are ordered the opposite of SELECT
13653 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13654 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13655 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13656 // larger than FalseC (the false value).
13657 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13658 CC = X86::GetOppositeBranchCondition(CC);
13659 std::swap(TrueC, FalseC);
13662 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13663 // This is efficient for any integer data type (including i8/i16) and
13665 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13666 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13667 DAG.getConstant(CC, MVT::i8), Cond);
13669 // Zero extend the condition if needed.
13670 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13672 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13673 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13674 DAG.getConstant(ShAmt, MVT::i8));
13675 if (N->getNumValues() == 2) // Dead flag value?
13676 return DCI.CombineTo(N, Cond, SDValue());
13680 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13681 // for any integer data type, including i8/i16.
13682 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13683 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13684 DAG.getConstant(CC, MVT::i8), Cond);
13686 // Zero extend the condition if needed.
13687 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13688 FalseC->getValueType(0), Cond);
13689 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13690 SDValue(FalseC, 0));
13692 if (N->getNumValues() == 2) // Dead flag value?
13693 return DCI.CombineTo(N, Cond, SDValue());
13697 // Optimize cases that will turn into an LEA instruction. This requires
13698 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13699 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13700 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13701 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13703 bool isFastMultiplier = false;
13705 switch ((unsigned char)Diff) {
13707 case 1: // result = add base, cond
13708 case 2: // result = lea base( , cond*2)
13709 case 3: // result = lea base(cond, cond*2)
13710 case 4: // result = lea base( , cond*4)
13711 case 5: // result = lea base(cond, cond*4)
13712 case 8: // result = lea base( , cond*8)
13713 case 9: // result = lea base(cond, cond*8)
13714 isFastMultiplier = true;
13719 if (isFastMultiplier) {
13720 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13721 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13722 DAG.getConstant(CC, MVT::i8), Cond);
13723 // Zero extend the condition if needed.
13724 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13726 // Scale the condition by the difference.
13728 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13729 DAG.getConstant(Diff, Cond.getValueType()));
13731 // Add the base if non-zero.
13732 if (FalseC->getAPIntValue() != 0)
13733 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13734 SDValue(FalseC, 0));
13735 if (N->getNumValues() == 2) // Dead flag value?
13736 return DCI.CombineTo(N, Cond, SDValue());
13746 /// PerformMulCombine - Optimize a single multiply with constant into two
13747 /// in order to implement it with two cheaper instructions, e.g.
13748 /// LEA + SHL, LEA + LEA.
13749 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13750 TargetLowering::DAGCombinerInfo &DCI) {
13751 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13754 EVT VT = N->getValueType(0);
13755 if (VT != MVT::i64)
13758 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13761 uint64_t MulAmt = C->getZExtValue();
13762 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13765 uint64_t MulAmt1 = 0;
13766 uint64_t MulAmt2 = 0;
13767 if ((MulAmt % 9) == 0) {
13769 MulAmt2 = MulAmt / 9;
13770 } else if ((MulAmt % 5) == 0) {
13772 MulAmt2 = MulAmt / 5;
13773 } else if ((MulAmt % 3) == 0) {
13775 MulAmt2 = MulAmt / 3;
13778 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13779 DebugLoc DL = N->getDebugLoc();
13781 if (isPowerOf2_64(MulAmt2) &&
13782 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13783 // If second multiplifer is pow2, issue it first. We want the multiply by
13784 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13786 std::swap(MulAmt1, MulAmt2);
13789 if (isPowerOf2_64(MulAmt1))
13790 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13791 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13793 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13794 DAG.getConstant(MulAmt1, VT));
13796 if (isPowerOf2_64(MulAmt2))
13797 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13798 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13800 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13801 DAG.getConstant(MulAmt2, VT));
13803 // Do not add new nodes to DAG combiner worklist.
13804 DCI.CombineTo(N, NewMul, false);
13809 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13810 SDValue N0 = N->getOperand(0);
13811 SDValue N1 = N->getOperand(1);
13812 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13813 EVT VT = N0.getValueType();
13815 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13816 // since the result of setcc_c is all zero's or all ones.
13817 if (VT.isInteger() && !VT.isVector() &&
13818 N1C && N0.getOpcode() == ISD::AND &&
13819 N0.getOperand(1).getOpcode() == ISD::Constant) {
13820 SDValue N00 = N0.getOperand(0);
13821 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13822 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13823 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13824 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13825 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13826 APInt ShAmt = N1C->getAPIntValue();
13827 Mask = Mask.shl(ShAmt);
13829 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13830 N00, DAG.getConstant(Mask, VT));
13835 // Hardware support for vector shifts is sparse which makes us scalarize the
13836 // vector operations in many cases. Also, on sandybridge ADD is faster than
13838 // (shl V, 1) -> add V,V
13839 if (isSplatVector(N1.getNode())) {
13840 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13841 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13842 // We shift all of the values by one. In many cases we do not have
13843 // hardware support for this operation. This is better expressed as an ADD
13845 if (N1C && (1 == N1C->getZExtValue())) {
13846 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13853 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13855 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13856 TargetLowering::DAGCombinerInfo &DCI,
13857 const X86Subtarget *Subtarget) {
13858 EVT VT = N->getValueType(0);
13859 if (N->getOpcode() == ISD::SHL) {
13860 SDValue V = PerformSHLCombine(N, DAG);
13861 if (V.getNode()) return V;
13864 // On X86 with SSE2 support, we can transform this to a vector shift if
13865 // all elements are shifted by the same amount. We can't do this in legalize
13866 // because the a constant vector is typically transformed to a constant pool
13867 // so we have no knowledge of the shift amount.
13868 if (!Subtarget->hasSSE2())
13871 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13872 (!Subtarget->hasAVX2() ||
13873 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13876 SDValue ShAmtOp = N->getOperand(1);
13877 EVT EltVT = VT.getVectorElementType();
13878 DebugLoc DL = N->getDebugLoc();
13879 SDValue BaseShAmt = SDValue();
13880 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13881 unsigned NumElts = VT.getVectorNumElements();
13883 for (; i != NumElts; ++i) {
13884 SDValue Arg = ShAmtOp.getOperand(i);
13885 if (Arg.getOpcode() == ISD::UNDEF) continue;
13889 // Handle the case where the build_vector is all undef
13890 // FIXME: Should DAG allow this?
13894 for (; i != NumElts; ++i) {
13895 SDValue Arg = ShAmtOp.getOperand(i);
13896 if (Arg.getOpcode() == ISD::UNDEF) continue;
13897 if (Arg != BaseShAmt) {
13901 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13902 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13903 SDValue InVec = ShAmtOp.getOperand(0);
13904 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13905 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13907 for (; i != NumElts; ++i) {
13908 SDValue Arg = InVec.getOperand(i);
13909 if (Arg.getOpcode() == ISD::UNDEF) continue;
13913 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13914 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13915 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13916 if (C->getZExtValue() == SplatIdx)
13917 BaseShAmt = InVec.getOperand(1);
13920 if (BaseShAmt.getNode() == 0) {
13921 // Don't create instructions with illegal types after legalize
13923 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13924 !DCI.isBeforeLegalize())
13927 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13928 DAG.getIntPtrConstant(0));
13933 // The shift amount is an i32.
13934 if (EltVT.bitsGT(MVT::i32))
13935 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13936 else if (EltVT.bitsLT(MVT::i32))
13937 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13939 // The shift amount is identical so we can do a vector shift.
13940 SDValue ValOp = N->getOperand(0);
13941 switch (N->getOpcode()) {
13943 llvm_unreachable("Unknown shift opcode!");
13945 switch (VT.getSimpleVT().SimpleTy) {
13946 default: return SDValue();
13953 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13956 switch (VT.getSimpleVT().SimpleTy) {
13957 default: return SDValue();
13962 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13965 switch (VT.getSimpleVT().SimpleTy) {
13966 default: return SDValue();
13973 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13979 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13980 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13981 // and friends. Likewise for OR -> CMPNEQSS.
13982 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13983 TargetLowering::DAGCombinerInfo &DCI,
13984 const X86Subtarget *Subtarget) {
13987 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13988 // we're requiring SSE2 for both.
13989 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13990 SDValue N0 = N->getOperand(0);
13991 SDValue N1 = N->getOperand(1);
13992 SDValue CMP0 = N0->getOperand(1);
13993 SDValue CMP1 = N1->getOperand(1);
13994 DebugLoc DL = N->getDebugLoc();
13996 // The SETCCs should both refer to the same CMP.
13997 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
14000 SDValue CMP00 = CMP0->getOperand(0);
14001 SDValue CMP01 = CMP0->getOperand(1);
14002 EVT VT = CMP00.getValueType();
14004 if (VT == MVT::f32 || VT == MVT::f64) {
14005 bool ExpectingFlags = false;
14006 // Check for any users that want flags:
14007 for (SDNode::use_iterator UI = N->use_begin(),
14009 !ExpectingFlags && UI != UE; ++UI)
14010 switch (UI->getOpcode()) {
14015 ExpectingFlags = true;
14017 case ISD::CopyToReg:
14018 case ISD::SIGN_EXTEND:
14019 case ISD::ZERO_EXTEND:
14020 case ISD::ANY_EXTEND:
14024 if (!ExpectingFlags) {
14025 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
14026 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
14028 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
14029 X86::CondCode tmp = cc0;
14034 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
14035 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
14036 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
14037 X86ISD::NodeType NTOperator = is64BitFP ?
14038 X86ISD::FSETCCsd : X86ISD::FSETCCss;
14039 // FIXME: need symbolic constants for these magic numbers.
14040 // See X86ATTInstPrinter.cpp:printSSECC().
14041 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
14042 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
14043 DAG.getConstant(x86cc, MVT::i8));
14044 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
14046 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
14047 DAG.getConstant(1, MVT::i32));
14048 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
14049 return OneBitOfTruth;
14057 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
14058 /// so it can be folded inside ANDNP.
14059 static bool CanFoldXORWithAllOnes(const SDNode *N) {
14060 EVT VT = N->getValueType(0);
14062 // Match direct AllOnes for 128 and 256-bit vectors
14063 if (ISD::isBuildVectorAllOnes(N))
14066 // Look through a bit convert.
14067 if (N->getOpcode() == ISD::BITCAST)
14068 N = N->getOperand(0).getNode();
14070 // Sometimes the operand may come from a insert_subvector building a 256-bit
14072 if (VT.getSizeInBits() == 256 &&
14073 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
14074 SDValue V1 = N->getOperand(0);
14075 SDValue V2 = N->getOperand(1);
14077 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
14078 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
14079 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
14080 ISD::isBuildVectorAllOnes(V2.getNode()))
14087 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
14088 TargetLowering::DAGCombinerInfo &DCI,
14089 const X86Subtarget *Subtarget) {
14090 if (DCI.isBeforeLegalizeOps())
14093 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14097 EVT VT = N->getValueType(0);
14099 // Create ANDN, BLSI, and BLSR instructions
14100 // BLSI is X & (-X)
14101 // BLSR is X & (X-1)
14102 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
14103 SDValue N0 = N->getOperand(0);
14104 SDValue N1 = N->getOperand(1);
14105 DebugLoc DL = N->getDebugLoc();
14107 // Check LHS for not
14108 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
14109 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
14110 // Check RHS for not
14111 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
14112 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
14114 // Check LHS for neg
14115 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
14116 isZero(N0.getOperand(0)))
14117 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
14119 // Check RHS for neg
14120 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
14121 isZero(N1.getOperand(0)))
14122 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
14124 // Check LHS for X-1
14125 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14126 isAllOnes(N0.getOperand(1)))
14127 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
14129 // Check RHS for X-1
14130 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14131 isAllOnes(N1.getOperand(1)))
14132 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
14137 // Want to form ANDNP nodes:
14138 // 1) In the hopes of then easily combining them with OR and AND nodes
14139 // to form PBLEND/PSIGN.
14140 // 2) To match ANDN packed intrinsics
14141 if (VT != MVT::v2i64 && VT != MVT::v4i64)
14144 SDValue N0 = N->getOperand(0);
14145 SDValue N1 = N->getOperand(1);
14146 DebugLoc DL = N->getDebugLoc();
14148 // Check LHS for vnot
14149 if (N0.getOpcode() == ISD::XOR &&
14150 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
14151 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
14152 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
14154 // Check RHS for vnot
14155 if (N1.getOpcode() == ISD::XOR &&
14156 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
14157 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
14158 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
14163 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
14164 TargetLowering::DAGCombinerInfo &DCI,
14165 const X86Subtarget *Subtarget) {
14166 if (DCI.isBeforeLegalizeOps())
14169 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
14173 EVT VT = N->getValueType(0);
14175 SDValue N0 = N->getOperand(0);
14176 SDValue N1 = N->getOperand(1);
14178 // look for psign/blend
14179 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
14180 if (!Subtarget->hasSSSE3() ||
14181 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
14184 // Canonicalize pandn to RHS
14185 if (N0.getOpcode() == X86ISD::ANDNP)
14187 // or (and (m, y), (pandn m, x))
14188 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
14189 SDValue Mask = N1.getOperand(0);
14190 SDValue X = N1.getOperand(1);
14192 if (N0.getOperand(0) == Mask)
14193 Y = N0.getOperand(1);
14194 if (N0.getOperand(1) == Mask)
14195 Y = N0.getOperand(0);
14197 // Check to see if the mask appeared in both the AND and ANDNP and
14201 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
14202 // Look through mask bitcast.
14203 if (Mask.getOpcode() == ISD::BITCAST)
14204 Mask = Mask.getOperand(0);
14205 if (X.getOpcode() == ISD::BITCAST)
14206 X = X.getOperand(0);
14207 if (Y.getOpcode() == ISD::BITCAST)
14208 Y = Y.getOperand(0);
14210 EVT MaskVT = Mask.getValueType();
14212 // Validate that the Mask operand is a vector sra node.
14213 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
14214 // there is no psrai.b
14215 if (Mask.getOpcode() != X86ISD::VSRAI)
14218 // Check that the SRA is all signbits.
14219 SDValue SraC = Mask.getOperand(1);
14220 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
14221 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
14222 if ((SraAmt + 1) != EltBits)
14225 DebugLoc DL = N->getDebugLoc();
14227 // Now we know we at least have a plendvb with the mask val. See if
14228 // we can form a psignb/w/d.
14229 // psign = x.type == y.type == mask.type && y = sub(0, x);
14230 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
14231 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
14232 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
14233 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
14234 "Unsupported VT for PSIGN");
14235 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14236 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14238 // PBLENDVB only available on SSE 4.1
14239 if (!Subtarget->hasSSE41())
14242 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14244 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14245 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14246 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14247 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14248 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14252 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14255 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14256 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14258 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14260 if (!N0.hasOneUse() || !N1.hasOneUse())
14263 SDValue ShAmt0 = N0.getOperand(1);
14264 if (ShAmt0.getValueType() != MVT::i8)
14266 SDValue ShAmt1 = N1.getOperand(1);
14267 if (ShAmt1.getValueType() != MVT::i8)
14269 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14270 ShAmt0 = ShAmt0.getOperand(0);
14271 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14272 ShAmt1 = ShAmt1.getOperand(0);
14274 DebugLoc DL = N->getDebugLoc();
14275 unsigned Opc = X86ISD::SHLD;
14276 SDValue Op0 = N0.getOperand(0);
14277 SDValue Op1 = N1.getOperand(0);
14278 if (ShAmt0.getOpcode() == ISD::SUB) {
14279 Opc = X86ISD::SHRD;
14280 std::swap(Op0, Op1);
14281 std::swap(ShAmt0, ShAmt1);
14284 unsigned Bits = VT.getSizeInBits();
14285 if (ShAmt1.getOpcode() == ISD::SUB) {
14286 SDValue Sum = ShAmt1.getOperand(0);
14287 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14288 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14289 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14290 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14291 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14292 return DAG.getNode(Opc, DL, VT,
14294 DAG.getNode(ISD::TRUNCATE, DL,
14297 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14298 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14300 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14301 return DAG.getNode(Opc, DL, VT,
14302 N0.getOperand(0), N1.getOperand(0),
14303 DAG.getNode(ISD::TRUNCATE, DL,
14310 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14311 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14312 TargetLowering::DAGCombinerInfo &DCI,
14313 const X86Subtarget *Subtarget) {
14314 if (DCI.isBeforeLegalizeOps())
14317 EVT VT = N->getValueType(0);
14319 if (VT != MVT::i32 && VT != MVT::i64)
14322 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14324 // Create BLSMSK instructions by finding X ^ (X-1)
14325 SDValue N0 = N->getOperand(0);
14326 SDValue N1 = N->getOperand(1);
14327 DebugLoc DL = N->getDebugLoc();
14329 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14330 isAllOnes(N0.getOperand(1)))
14331 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14333 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14334 isAllOnes(N1.getOperand(1)))
14335 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14340 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14341 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14342 const X86Subtarget *Subtarget) {
14343 LoadSDNode *Ld = cast<LoadSDNode>(N);
14344 EVT RegVT = Ld->getValueType(0);
14345 EVT MemVT = Ld->getMemoryVT();
14346 DebugLoc dl = Ld->getDebugLoc();
14347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14349 ISD::LoadExtType Ext = Ld->getExtensionType();
14351 // If this is a vector EXT Load then attempt to optimize it using a
14352 // shuffle. We need SSE4 for the shuffles.
14353 // TODO: It is possible to support ZExt by zeroing the undef values
14354 // during the shuffle phase or after the shuffle.
14355 if (RegVT.isVector() && RegVT.isInteger() &&
14356 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14357 assert(MemVT != RegVT && "Cannot extend to the same type");
14358 assert(MemVT.isVector() && "Must load a vector from memory");
14360 unsigned NumElems = RegVT.getVectorNumElements();
14361 unsigned RegSz = RegVT.getSizeInBits();
14362 unsigned MemSz = MemVT.getSizeInBits();
14363 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14364 // All sizes must be a power of two
14365 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14367 // Attempt to load the original value using a single load op.
14368 // Find a scalar type which is equal to the loaded word size.
14369 MVT SclrLoadTy = MVT::i8;
14370 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14371 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14372 MVT Tp = (MVT::SimpleValueType)tp;
14373 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14379 // Proceed if a load word is found.
14380 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14382 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14383 RegSz/SclrLoadTy.getSizeInBits());
14385 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14386 RegSz/MemVT.getScalarType().getSizeInBits());
14387 // Can't shuffle using an illegal type.
14388 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14390 // Perform a single load.
14391 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14393 Ld->getPointerInfo(), Ld->isVolatile(),
14394 Ld->isNonTemporal(), Ld->isInvariant(),
14395 Ld->getAlignment());
14397 // Insert the word loaded into a vector.
14398 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14399 LoadUnitVecVT, ScalarLoad);
14401 // Bitcast the loaded value to a vector of the original element type, in
14402 // the size of the target vector type.
14403 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14405 unsigned SizeRatio = RegSz/MemSz;
14407 // Redistribute the loaded elements into the different locations.
14408 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14409 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14411 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14412 DAG.getUNDEF(WideVecVT),
14415 // Bitcast to the requested type.
14416 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14417 // Replace the original load with the new sequence
14418 // and return the new chain.
14419 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14420 return SDValue(ScalarLoad.getNode(), 1);
14426 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14427 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14428 const X86Subtarget *Subtarget) {
14429 StoreSDNode *St = cast<StoreSDNode>(N);
14430 EVT VT = St->getValue().getValueType();
14431 EVT StVT = St->getMemoryVT();
14432 DebugLoc dl = St->getDebugLoc();
14433 SDValue StoredVal = St->getOperand(1);
14434 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14436 // If we are saving a concatenation of two XMM registers, perform two stores.
14437 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14438 // 128-bit ones. If in the future the cost becomes only one memory access the
14439 // first version would be better.
14440 if (VT.getSizeInBits() == 256 &&
14441 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14442 StoredVal.getNumOperands() == 2) {
14444 SDValue Value0 = StoredVal.getOperand(0);
14445 SDValue Value1 = StoredVal.getOperand(1);
14447 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14448 SDValue Ptr0 = St->getBasePtr();
14449 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14451 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14452 St->getPointerInfo(), St->isVolatile(),
14453 St->isNonTemporal(), St->getAlignment());
14454 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14455 St->getPointerInfo(), St->isVolatile(),
14456 St->isNonTemporal(), St->getAlignment());
14457 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14460 // Optimize trunc store (of multiple scalars) to shuffle and store.
14461 // First, pack all of the elements in one place. Next, store to memory
14462 // in fewer chunks.
14463 if (St->isTruncatingStore() && VT.isVector()) {
14464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14465 unsigned NumElems = VT.getVectorNumElements();
14466 assert(StVT != VT && "Cannot truncate to the same type");
14467 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14468 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14470 // From, To sizes and ElemCount must be pow of two
14471 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14472 // We are going to use the original vector elt for storing.
14473 // Accumulated smaller vector elements must be a multiple of the store size.
14474 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14476 unsigned SizeRatio = FromSz / ToSz;
14478 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14480 // Create a type on which we perform the shuffle
14481 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14482 StVT.getScalarType(), NumElems*SizeRatio);
14484 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14486 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14487 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14488 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14490 // Can't shuffle using an illegal type
14491 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14493 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14494 DAG.getUNDEF(WideVecVT),
14496 // At this point all of the data is stored at the bottom of the
14497 // register. We now need to save it to mem.
14499 // Find the largest store unit
14500 MVT StoreType = MVT::i8;
14501 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14502 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14503 MVT Tp = (MVT::SimpleValueType)tp;
14504 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14508 // Bitcast the original vector into a vector of store-size units
14509 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14510 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14511 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14512 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14513 SmallVector<SDValue, 8> Chains;
14514 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14515 TLI.getPointerTy());
14516 SDValue Ptr = St->getBasePtr();
14518 // Perform one or more big stores into memory.
14519 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14520 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14521 StoreType, ShuffWide,
14522 DAG.getIntPtrConstant(i));
14523 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14524 St->getPointerInfo(), St->isVolatile(),
14525 St->isNonTemporal(), St->getAlignment());
14526 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14527 Chains.push_back(Ch);
14530 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14535 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14536 // the FP state in cases where an emms may be missing.
14537 // A preferable solution to the general problem is to figure out the right
14538 // places to insert EMMS. This qualifies as a quick hack.
14540 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14541 if (VT.getSizeInBits() != 64)
14544 const Function *F = DAG.getMachineFunction().getFunction();
14545 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14546 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14547 && Subtarget->hasSSE2();
14548 if ((VT.isVector() ||
14549 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14550 isa<LoadSDNode>(St->getValue()) &&
14551 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14552 St->getChain().hasOneUse() && !St->isVolatile()) {
14553 SDNode* LdVal = St->getValue().getNode();
14554 LoadSDNode *Ld = 0;
14555 int TokenFactorIndex = -1;
14556 SmallVector<SDValue, 8> Ops;
14557 SDNode* ChainVal = St->getChain().getNode();
14558 // Must be a store of a load. We currently handle two cases: the load
14559 // is a direct child, and it's under an intervening TokenFactor. It is
14560 // possible to dig deeper under nested TokenFactors.
14561 if (ChainVal == LdVal)
14562 Ld = cast<LoadSDNode>(St->getChain());
14563 else if (St->getValue().hasOneUse() &&
14564 ChainVal->getOpcode() == ISD::TokenFactor) {
14565 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14566 if (ChainVal->getOperand(i).getNode() == LdVal) {
14567 TokenFactorIndex = i;
14568 Ld = cast<LoadSDNode>(St->getValue());
14570 Ops.push_back(ChainVal->getOperand(i));
14574 if (!Ld || !ISD::isNormalLoad(Ld))
14577 // If this is not the MMX case, i.e. we are just turning i64 load/store
14578 // into f64 load/store, avoid the transformation if there are multiple
14579 // uses of the loaded value.
14580 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14583 DebugLoc LdDL = Ld->getDebugLoc();
14584 DebugLoc StDL = N->getDebugLoc();
14585 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14586 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14588 if (Subtarget->is64Bit() || F64IsLegal) {
14589 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14590 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14591 Ld->getPointerInfo(), Ld->isVolatile(),
14592 Ld->isNonTemporal(), Ld->isInvariant(),
14593 Ld->getAlignment());
14594 SDValue NewChain = NewLd.getValue(1);
14595 if (TokenFactorIndex != -1) {
14596 Ops.push_back(NewChain);
14597 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14600 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14601 St->getPointerInfo(),
14602 St->isVolatile(), St->isNonTemporal(),
14603 St->getAlignment());
14606 // Otherwise, lower to two pairs of 32-bit loads / stores.
14607 SDValue LoAddr = Ld->getBasePtr();
14608 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14609 DAG.getConstant(4, MVT::i32));
14611 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14612 Ld->getPointerInfo(),
14613 Ld->isVolatile(), Ld->isNonTemporal(),
14614 Ld->isInvariant(), Ld->getAlignment());
14615 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14616 Ld->getPointerInfo().getWithOffset(4),
14617 Ld->isVolatile(), Ld->isNonTemporal(),
14619 MinAlign(Ld->getAlignment(), 4));
14621 SDValue NewChain = LoLd.getValue(1);
14622 if (TokenFactorIndex != -1) {
14623 Ops.push_back(LoLd);
14624 Ops.push_back(HiLd);
14625 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14629 LoAddr = St->getBasePtr();
14630 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14631 DAG.getConstant(4, MVT::i32));
14633 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14634 St->getPointerInfo(),
14635 St->isVolatile(), St->isNonTemporal(),
14636 St->getAlignment());
14637 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14638 St->getPointerInfo().getWithOffset(4),
14640 St->isNonTemporal(),
14641 MinAlign(St->getAlignment(), 4));
14642 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14647 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14648 /// and return the operands for the horizontal operation in LHS and RHS. A
14649 /// horizontal operation performs the binary operation on successive elements
14650 /// of its first operand, then on successive elements of its second operand,
14651 /// returning the resulting values in a vector. For example, if
14652 /// A = < float a0, float a1, float a2, float a3 >
14654 /// B = < float b0, float b1, float b2, float b3 >
14655 /// then the result of doing a horizontal operation on A and B is
14656 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14657 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14658 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14659 /// set to A, RHS to B, and the routine returns 'true'.
14660 /// Note that the binary operation should have the property that if one of the
14661 /// operands is UNDEF then the result is UNDEF.
14662 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14663 // Look for the following pattern: if
14664 // A = < float a0, float a1, float a2, float a3 >
14665 // B = < float b0, float b1, float b2, float b3 >
14667 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14668 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14669 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14670 // which is A horizontal-op B.
14672 // At least one of the operands should be a vector shuffle.
14673 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14674 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14677 EVT VT = LHS.getValueType();
14679 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14680 "Unsupported vector type for horizontal add/sub");
14682 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14683 // operate independently on 128-bit lanes.
14684 unsigned NumElts = VT.getVectorNumElements();
14685 unsigned NumLanes = VT.getSizeInBits()/128;
14686 unsigned NumLaneElts = NumElts / NumLanes;
14687 assert((NumLaneElts % 2 == 0) &&
14688 "Vector type should have an even number of elements in each lane");
14689 unsigned HalfLaneElts = NumLaneElts/2;
14691 // View LHS in the form
14692 // LHS = VECTOR_SHUFFLE A, B, LMask
14693 // If LHS is not a shuffle then pretend it is the shuffle
14694 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14695 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14698 SmallVector<int, 16> LMask(NumElts);
14699 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14700 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14701 A = LHS.getOperand(0);
14702 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14703 B = LHS.getOperand(1);
14704 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14705 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14707 if (LHS.getOpcode() != ISD::UNDEF)
14709 for (unsigned i = 0; i != NumElts; ++i)
14713 // Likewise, view RHS in the form
14714 // RHS = VECTOR_SHUFFLE C, D, RMask
14716 SmallVector<int, 16> RMask(NumElts);
14717 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14718 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14719 C = RHS.getOperand(0);
14720 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14721 D = RHS.getOperand(1);
14722 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14723 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14725 if (RHS.getOpcode() != ISD::UNDEF)
14727 for (unsigned i = 0; i != NumElts; ++i)
14731 // Check that the shuffles are both shuffling the same vectors.
14732 if (!(A == C && B == D) && !(A == D && B == C))
14735 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14736 if (!A.getNode() && !B.getNode())
14739 // If A and B occur in reverse order in RHS, then "swap" them (which means
14740 // rewriting the mask).
14742 CommuteVectorShuffleMask(RMask, NumElts);
14744 // At this point LHS and RHS are equivalent to
14745 // LHS = VECTOR_SHUFFLE A, B, LMask
14746 // RHS = VECTOR_SHUFFLE A, B, RMask
14747 // Check that the masks correspond to performing a horizontal operation.
14748 for (unsigned i = 0; i != NumElts; ++i) {
14749 int LIdx = LMask[i], RIdx = RMask[i];
14751 // Ignore any UNDEF components.
14752 if (LIdx < 0 || RIdx < 0 ||
14753 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14754 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14757 // Check that successive elements are being operated on. If not, this is
14758 // not a horizontal operation.
14759 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14760 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14761 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14762 if (!(LIdx == Index && RIdx == Index + 1) &&
14763 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14767 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14768 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14772 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14773 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14774 const X86Subtarget *Subtarget) {
14775 EVT VT = N->getValueType(0);
14776 SDValue LHS = N->getOperand(0);
14777 SDValue RHS = N->getOperand(1);
14779 // Try to synthesize horizontal adds from adds of shuffles.
14780 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14781 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14782 isHorizontalBinOp(LHS, RHS, true))
14783 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14787 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14788 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14789 const X86Subtarget *Subtarget) {
14790 EVT VT = N->getValueType(0);
14791 SDValue LHS = N->getOperand(0);
14792 SDValue RHS = N->getOperand(1);
14794 // Try to synthesize horizontal subs from subs of shuffles.
14795 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14796 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14797 isHorizontalBinOp(LHS, RHS, false))
14798 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14802 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14803 /// X86ISD::FXOR nodes.
14804 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14805 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14806 // F[X]OR(0.0, x) -> x
14807 // F[X]OR(x, 0.0) -> x
14808 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14809 if (C->getValueAPF().isPosZero())
14810 return N->getOperand(1);
14811 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14812 if (C->getValueAPF().isPosZero())
14813 return N->getOperand(0);
14817 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14818 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14819 // FAND(0.0, x) -> 0.0
14820 // FAND(x, 0.0) -> 0.0
14821 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14822 if (C->getValueAPF().isPosZero())
14823 return N->getOperand(0);
14824 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14825 if (C->getValueAPF().isPosZero())
14826 return N->getOperand(1);
14830 static SDValue PerformBTCombine(SDNode *N,
14832 TargetLowering::DAGCombinerInfo &DCI) {
14833 // BT ignores high bits in the bit index operand.
14834 SDValue Op1 = N->getOperand(1);
14835 if (Op1.hasOneUse()) {
14836 unsigned BitWidth = Op1.getValueSizeInBits();
14837 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14838 APInt KnownZero, KnownOne;
14839 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14840 !DCI.isBeforeLegalizeOps());
14841 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14842 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14843 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14844 DCI.CommitTargetLoweringOpt(TLO);
14849 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14850 SDValue Op = N->getOperand(0);
14851 if (Op.getOpcode() == ISD::BITCAST)
14852 Op = Op.getOperand(0);
14853 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14854 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14855 VT.getVectorElementType().getSizeInBits() ==
14856 OpVT.getVectorElementType().getSizeInBits()) {
14857 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14862 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14863 TargetLowering::DAGCombinerInfo &DCI,
14864 const X86Subtarget *Subtarget) {
14865 if (!DCI.isBeforeLegalizeOps())
14868 if (!Subtarget->hasAVX())
14871 EVT VT = N->getValueType(0);
14872 SDValue Op = N->getOperand(0);
14873 EVT OpVT = Op.getValueType();
14874 DebugLoc dl = N->getDebugLoc();
14876 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14877 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14879 if (Subtarget->hasAVX2()) {
14880 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, Op);
14883 // Optimize vectors in AVX mode
14884 // Sign extend v8i16 to v8i32 and
14887 // Divide input vector into two parts
14888 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14889 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14890 // concat the vectors to original VT
14892 unsigned NumElems = OpVT.getVectorNumElements();
14893 SmallVector<int,8> ShufMask1(NumElems, -1);
14894 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14896 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14899 SmallVector<int,8> ShufMask2(NumElems, -1);
14900 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14902 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14905 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14906 VT.getVectorNumElements()/2);
14908 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14909 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14911 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14916 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14917 const X86Subtarget *Subtarget) {
14918 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14919 // (and (i32 x86isd::setcc_carry), 1)
14920 // This eliminates the zext. This transformation is necessary because
14921 // ISD::SETCC is always legalized to i8.
14922 DebugLoc dl = N->getDebugLoc();
14923 SDValue N0 = N->getOperand(0);
14924 EVT VT = N->getValueType(0);
14925 EVT OpVT = N0.getValueType();
14927 if (N0.getOpcode() == ISD::AND &&
14929 N0.getOperand(0).hasOneUse()) {
14930 SDValue N00 = N0.getOperand(0);
14931 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14933 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14934 if (!C || C->getZExtValue() != 1)
14936 return DAG.getNode(ISD::AND, dl, VT,
14937 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14938 N00.getOperand(0), N00.getOperand(1)),
14939 DAG.getConstant(1, VT));
14942 // Optimize vectors in AVX mode:
14945 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14946 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14947 // Concat upper and lower parts.
14950 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14951 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14952 // Concat upper and lower parts.
14954 if (Subtarget->hasAVX()) {
14956 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14957 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14959 if (Subtarget->hasAVX2())
14960 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, N0);
14962 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14963 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec,
14965 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec,
14968 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14969 VT.getVectorNumElements()/2);
14971 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14972 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14974 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14981 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14982 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14983 unsigned X86CC = N->getConstantOperandVal(0);
14984 SDValue EFLAG = N->getOperand(1);
14985 DebugLoc DL = N->getDebugLoc();
14987 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14988 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14990 if (X86CC == X86::COND_B)
14991 return DAG.getNode(ISD::AND, DL, MVT::i8,
14992 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14993 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14994 DAG.getConstant(1, MVT::i8));
14999 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
15000 const X86TargetLowering *XTLI) {
15001 SDValue Op0 = N->getOperand(0);
15002 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
15003 // a 32-bit target where SSE doesn't support i64->FP operations.
15004 if (Op0.getOpcode() == ISD::LOAD) {
15005 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
15006 EVT VT = Ld->getValueType(0);
15007 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
15008 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
15009 !XTLI->getSubtarget()->is64Bit() &&
15010 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
15011 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
15012 Ld->getChain(), Op0, DAG);
15013 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
15020 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
15021 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
15022 X86TargetLowering::DAGCombinerInfo &DCI) {
15023 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
15024 // the result is either zero or one (depending on the input carry bit).
15025 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
15026 if (X86::isZeroNode(N->getOperand(0)) &&
15027 X86::isZeroNode(N->getOperand(1)) &&
15028 // We don't have a good way to replace an EFLAGS use, so only do this when
15030 SDValue(N, 1).use_empty()) {
15031 DebugLoc DL = N->getDebugLoc();
15032 EVT VT = N->getValueType(0);
15033 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
15034 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
15035 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
15036 DAG.getConstant(X86::COND_B,MVT::i8),
15038 DAG.getConstant(1, VT));
15039 return DCI.CombineTo(N, Res1, CarryOut);
15045 // fold (add Y, (sete X, 0)) -> adc 0, Y
15046 // (add Y, (setne X, 0)) -> sbb -1, Y
15047 // (sub (sete X, 0), Y) -> sbb 0, Y
15048 // (sub (setne X, 0), Y) -> adc -1, Y
15049 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
15050 DebugLoc DL = N->getDebugLoc();
15052 // Look through ZExts.
15053 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
15054 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
15057 SDValue SetCC = Ext.getOperand(0);
15058 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
15061 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
15062 if (CC != X86::COND_E && CC != X86::COND_NE)
15065 SDValue Cmp = SetCC.getOperand(1);
15066 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
15067 !X86::isZeroNode(Cmp.getOperand(1)) ||
15068 !Cmp.getOperand(0).getValueType().isInteger())
15071 SDValue CmpOp0 = Cmp.getOperand(0);
15072 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
15073 DAG.getConstant(1, CmpOp0.getValueType()));
15075 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
15076 if (CC == X86::COND_NE)
15077 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
15078 DL, OtherVal.getValueType(), OtherVal,
15079 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
15080 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
15081 DL, OtherVal.getValueType(), OtherVal,
15082 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
15085 /// PerformADDCombine - Do target-specific dag combines on integer adds.
15086 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
15087 const X86Subtarget *Subtarget) {
15088 EVT VT = N->getValueType(0);
15089 SDValue Op0 = N->getOperand(0);
15090 SDValue Op1 = N->getOperand(1);
15092 // Try to synthesize horizontal adds from adds of shuffles.
15093 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15094 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15095 isHorizontalBinOp(Op0, Op1, true))
15096 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
15098 return OptimizeConditionalInDecrement(N, DAG);
15101 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
15102 const X86Subtarget *Subtarget) {
15103 SDValue Op0 = N->getOperand(0);
15104 SDValue Op1 = N->getOperand(1);
15106 // X86 can't encode an immediate LHS of a sub. See if we can push the
15107 // negation into a preceding instruction.
15108 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
15109 // If the RHS of the sub is a XOR with one use and a constant, invert the
15110 // immediate. Then add one to the LHS of the sub so we can turn
15111 // X-Y -> X+~Y+1, saving one register.
15112 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
15113 isa<ConstantSDNode>(Op1.getOperand(1))) {
15114 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
15115 EVT VT = Op0.getValueType();
15116 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
15118 DAG.getConstant(~XorC, VT));
15119 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
15120 DAG.getConstant(C->getAPIntValue()+1, VT));
15124 // Try to synthesize horizontal adds from adds of shuffles.
15125 EVT VT = N->getValueType(0);
15126 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
15127 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
15128 isHorizontalBinOp(Op0, Op1, true))
15129 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
15131 return OptimizeConditionalInDecrement(N, DAG);
15134 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
15135 DAGCombinerInfo &DCI) const {
15136 SelectionDAG &DAG = DCI.DAG;
15137 switch (N->getOpcode()) {
15139 case ISD::EXTRACT_VECTOR_ELT:
15140 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
15142 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
15143 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
15144 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
15145 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
15146 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
15147 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
15150 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
15151 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
15152 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
15153 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
15154 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
15155 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
15156 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
15157 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
15158 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
15160 case X86ISD::FOR: return PerformFORCombine(N, DAG);
15161 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
15162 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
15163 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
15164 case ISD::ANY_EXTEND:
15165 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
15166 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
15167 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
15168 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
15169 case X86ISD::SHUFP: // Handle all target specific shuffles
15170 case X86ISD::PALIGN:
15171 case X86ISD::UNPCKH:
15172 case X86ISD::UNPCKL:
15173 case X86ISD::MOVHLPS:
15174 case X86ISD::MOVLHPS:
15175 case X86ISD::PSHUFD:
15176 case X86ISD::PSHUFHW:
15177 case X86ISD::PSHUFLW:
15178 case X86ISD::MOVSS:
15179 case X86ISD::MOVSD:
15180 case X86ISD::VPERMILP:
15181 case X86ISD::VPERM2X128:
15182 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
15188 /// isTypeDesirableForOp - Return true if the target has native support for
15189 /// the specified value type and it is 'desirable' to use the type for the
15190 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
15191 /// instruction encodings are longer and some i16 instructions are slow.
15192 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
15193 if (!isTypeLegal(VT))
15195 if (VT != MVT::i16)
15202 case ISD::SIGN_EXTEND:
15203 case ISD::ZERO_EXTEND:
15204 case ISD::ANY_EXTEND:
15217 /// IsDesirableToPromoteOp - This method query the target whether it is
15218 /// beneficial for dag combiner to promote the specified node. If true, it
15219 /// should return the desired promotion type by reference.
15220 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
15221 EVT VT = Op.getValueType();
15222 if (VT != MVT::i16)
15225 bool Promote = false;
15226 bool Commute = false;
15227 switch (Op.getOpcode()) {
15230 LoadSDNode *LD = cast<LoadSDNode>(Op);
15231 // If the non-extending load has a single use and it's not live out, then it
15232 // might be folded.
15233 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
15234 Op.hasOneUse()*/) {
15235 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
15236 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
15237 // The only case where we'd want to promote LOAD (rather then it being
15238 // promoted as an operand is when it's only use is liveout.
15239 if (UI->getOpcode() != ISD::CopyToReg)
15246 case ISD::SIGN_EXTEND:
15247 case ISD::ZERO_EXTEND:
15248 case ISD::ANY_EXTEND:
15253 SDValue N0 = Op.getOperand(0);
15254 // Look out for (store (shl (load), x)).
15255 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15268 SDValue N0 = Op.getOperand(0);
15269 SDValue N1 = Op.getOperand(1);
15270 if (!Commute && MayFoldLoad(N1))
15272 // Avoid disabling potential load folding opportunities.
15273 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15275 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15285 //===----------------------------------------------------------------------===//
15286 // X86 Inline Assembly Support
15287 //===----------------------------------------------------------------------===//
15290 // Helper to match a string separated by whitespace.
15291 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15292 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15294 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15295 StringRef piece(*args[i]);
15296 if (!s.startswith(piece)) // Check if the piece matches.
15299 s = s.substr(piece.size());
15300 StringRef::size_type pos = s.find_first_not_of(" \t");
15301 if (pos == 0) // We matched a prefix.
15309 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15312 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15313 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15315 std::string AsmStr = IA->getAsmString();
15317 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15318 if (!Ty || Ty->getBitWidth() % 16 != 0)
15321 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15322 SmallVector<StringRef, 4> AsmPieces;
15323 SplitString(AsmStr, AsmPieces, ";\n");
15325 switch (AsmPieces.size()) {
15326 default: return false;
15328 // FIXME: this should verify that we are targeting a 486 or better. If not,
15329 // we will turn this bswap into something that will be lowered to logical
15330 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15331 // lower so don't worry about this.
15333 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15334 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15335 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15336 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15337 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15338 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15339 // No need to check constraints, nothing other than the equivalent of
15340 // "=r,0" would be valid here.
15341 return IntrinsicLowering::LowerToByteSwap(CI);
15344 // rorw $$8, ${0:w} --> llvm.bswap.i16
15345 if (CI->getType()->isIntegerTy(16) &&
15346 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15347 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15348 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15350 const std::string &ConstraintsStr = IA->getConstraintString();
15351 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15352 std::sort(AsmPieces.begin(), AsmPieces.end());
15353 if (AsmPieces.size() == 4 &&
15354 AsmPieces[0] == "~{cc}" &&
15355 AsmPieces[1] == "~{dirflag}" &&
15356 AsmPieces[2] == "~{flags}" &&
15357 AsmPieces[3] == "~{fpsr}")
15358 return IntrinsicLowering::LowerToByteSwap(CI);
15362 if (CI->getType()->isIntegerTy(32) &&
15363 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15364 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15365 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15366 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15368 const std::string &ConstraintsStr = IA->getConstraintString();
15369 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15370 std::sort(AsmPieces.begin(), AsmPieces.end());
15371 if (AsmPieces.size() == 4 &&
15372 AsmPieces[0] == "~{cc}" &&
15373 AsmPieces[1] == "~{dirflag}" &&
15374 AsmPieces[2] == "~{flags}" &&
15375 AsmPieces[3] == "~{fpsr}")
15376 return IntrinsicLowering::LowerToByteSwap(CI);
15379 if (CI->getType()->isIntegerTy(64)) {
15380 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15381 if (Constraints.size() >= 2 &&
15382 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15383 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15384 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15385 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15386 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15387 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15388 return IntrinsicLowering::LowerToByteSwap(CI);
15398 /// getConstraintType - Given a constraint letter, return the type of
15399 /// constraint it is for this target.
15400 X86TargetLowering::ConstraintType
15401 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15402 if (Constraint.size() == 1) {
15403 switch (Constraint[0]) {
15414 return C_RegisterClass;
15438 return TargetLowering::getConstraintType(Constraint);
15441 /// Examine constraint type and operand type and determine a weight value.
15442 /// This object must already have been set up with the operand type
15443 /// and the current alternative constraint selected.
15444 TargetLowering::ConstraintWeight
15445 X86TargetLowering::getSingleConstraintMatchWeight(
15446 AsmOperandInfo &info, const char *constraint) const {
15447 ConstraintWeight weight = CW_Invalid;
15448 Value *CallOperandVal = info.CallOperandVal;
15449 // If we don't have a value, we can't do a match,
15450 // but allow it at the lowest weight.
15451 if (CallOperandVal == NULL)
15453 Type *type = CallOperandVal->getType();
15454 // Look at the constraint type.
15455 switch (*constraint) {
15457 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15468 if (CallOperandVal->getType()->isIntegerTy())
15469 weight = CW_SpecificReg;
15474 if (type->isFloatingPointTy())
15475 weight = CW_SpecificReg;
15478 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15479 weight = CW_SpecificReg;
15483 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15484 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15485 weight = CW_Register;
15488 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15489 if (C->getZExtValue() <= 31)
15490 weight = CW_Constant;
15494 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15495 if (C->getZExtValue() <= 63)
15496 weight = CW_Constant;
15500 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15501 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15502 weight = CW_Constant;
15506 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15507 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15508 weight = CW_Constant;
15512 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15513 if (C->getZExtValue() <= 3)
15514 weight = CW_Constant;
15518 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15519 if (C->getZExtValue() <= 0xff)
15520 weight = CW_Constant;
15525 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15526 weight = CW_Constant;
15530 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15531 if ((C->getSExtValue() >= -0x80000000LL) &&
15532 (C->getSExtValue() <= 0x7fffffffLL))
15533 weight = CW_Constant;
15537 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15538 if (C->getZExtValue() <= 0xffffffff)
15539 weight = CW_Constant;
15546 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15547 /// with another that has more specific requirements based on the type of the
15548 /// corresponding operand.
15549 const char *X86TargetLowering::
15550 LowerXConstraint(EVT ConstraintVT) const {
15551 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15552 // 'f' like normal targets.
15553 if (ConstraintVT.isFloatingPoint()) {
15554 if (Subtarget->hasSSE2())
15556 if (Subtarget->hasSSE1())
15560 return TargetLowering::LowerXConstraint(ConstraintVT);
15563 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15564 /// vector. If it is invalid, don't add anything to Ops.
15565 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15566 std::string &Constraint,
15567 std::vector<SDValue>&Ops,
15568 SelectionDAG &DAG) const {
15569 SDValue Result(0, 0);
15571 // Only support length 1 constraints for now.
15572 if (Constraint.length() > 1) return;
15574 char ConstraintLetter = Constraint[0];
15575 switch (ConstraintLetter) {
15578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15579 if (C->getZExtValue() <= 31) {
15580 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15586 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15587 if (C->getZExtValue() <= 63) {
15588 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15595 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15596 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15602 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15603 if (C->getZExtValue() <= 255) {
15604 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15610 // 32-bit signed value
15611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15612 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15613 C->getSExtValue())) {
15614 // Widen to 64 bits here to get it sign extended.
15615 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15618 // FIXME gcc accepts some relocatable values here too, but only in certain
15619 // memory models; it's complicated.
15624 // 32-bit unsigned value
15625 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15626 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15627 C->getZExtValue())) {
15628 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15632 // FIXME gcc accepts some relocatable values here too, but only in certain
15633 // memory models; it's complicated.
15637 // Literal immediates are always ok.
15638 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15639 // Widen to 64 bits here to get it sign extended.
15640 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15644 // In any sort of PIC mode addresses need to be computed at runtime by
15645 // adding in a register or some sort of table lookup. These can't
15646 // be used as immediates.
15647 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15650 // If we are in non-pic codegen mode, we allow the address of a global (with
15651 // an optional displacement) to be used with 'i'.
15652 GlobalAddressSDNode *GA = 0;
15653 int64_t Offset = 0;
15655 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15657 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15658 Offset += GA->getOffset();
15660 } else if (Op.getOpcode() == ISD::ADD) {
15661 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15662 Offset += C->getZExtValue();
15663 Op = Op.getOperand(0);
15666 } else if (Op.getOpcode() == ISD::SUB) {
15667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15668 Offset += -C->getZExtValue();
15669 Op = Op.getOperand(0);
15674 // Otherwise, this isn't something we can handle, reject it.
15678 const GlobalValue *GV = GA->getGlobal();
15679 // If we require an extra load to get this address, as in PIC mode, we
15680 // can't accept it.
15681 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15682 getTargetMachine())))
15685 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15686 GA->getValueType(0), Offset);
15691 if (Result.getNode()) {
15692 Ops.push_back(Result);
15695 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15698 std::pair<unsigned, const TargetRegisterClass*>
15699 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15701 // First, see if this is a constraint that directly corresponds to an LLVM
15703 if (Constraint.size() == 1) {
15704 // GCC Constraint Letters
15705 switch (Constraint[0]) {
15707 // TODO: Slight differences here in allocation order and leaving
15708 // RIP in the class. Do they matter any more here than they do
15709 // in the normal allocation?
15710 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15711 if (Subtarget->is64Bit()) {
15712 if (VT == MVT::i32 || VT == MVT::f32)
15713 return std::make_pair(0U, &X86::GR32RegClass);
15714 if (VT == MVT::i16)
15715 return std::make_pair(0U, &X86::GR16RegClass);
15716 if (VT == MVT::i8 || VT == MVT::i1)
15717 return std::make_pair(0U, &X86::GR8RegClass);
15718 if (VT == MVT::i64 || VT == MVT::f64)
15719 return std::make_pair(0U, &X86::GR64RegClass);
15722 // 32-bit fallthrough
15723 case 'Q': // Q_REGS
15724 if (VT == MVT::i32 || VT == MVT::f32)
15725 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
15726 if (VT == MVT::i16)
15727 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
15728 if (VT == MVT::i8 || VT == MVT::i1)
15729 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
15730 if (VT == MVT::i64)
15731 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
15733 case 'r': // GENERAL_REGS
15734 case 'l': // INDEX_REGS
15735 if (VT == MVT::i8 || VT == MVT::i1)
15736 return std::make_pair(0U, &X86::GR8RegClass);
15737 if (VT == MVT::i16)
15738 return std::make_pair(0U, &X86::GR16RegClass);
15739 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15740 return std::make_pair(0U, &X86::GR32RegClass);
15741 return std::make_pair(0U, &X86::GR64RegClass);
15742 case 'R': // LEGACY_REGS
15743 if (VT == MVT::i8 || VT == MVT::i1)
15744 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
15745 if (VT == MVT::i16)
15746 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
15747 if (VT == MVT::i32 || !Subtarget->is64Bit())
15748 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
15749 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
15750 case 'f': // FP Stack registers.
15751 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15752 // value to the correct fpstack register class.
15753 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15754 return std::make_pair(0U, &X86::RFP32RegClass);
15755 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15756 return std::make_pair(0U, &X86::RFP64RegClass);
15757 return std::make_pair(0U, &X86::RFP80RegClass);
15758 case 'y': // MMX_REGS if MMX allowed.
15759 if (!Subtarget->hasMMX()) break;
15760 return std::make_pair(0U, &X86::VR64RegClass);
15761 case 'Y': // SSE_REGS if SSE2 allowed
15762 if (!Subtarget->hasSSE2()) break;
15764 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15765 if (!Subtarget->hasSSE1()) break;
15767 switch (VT.getSimpleVT().SimpleTy) {
15769 // Scalar SSE types.
15772 return std::make_pair(0U, &X86::FR32RegClass);
15775 return std::make_pair(0U, &X86::FR64RegClass);
15783 return std::make_pair(0U, &X86::VR128RegClass);
15791 return std::make_pair(0U, &X86::VR256RegClass);
15797 // Use the default implementation in TargetLowering to convert the register
15798 // constraint into a member of a register class.
15799 std::pair<unsigned, const TargetRegisterClass*> Res;
15800 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15802 // Not found as a standard register?
15803 if (Res.second == 0) {
15804 // Map st(0) -> st(7) -> ST0
15805 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15806 tolower(Constraint[1]) == 's' &&
15807 tolower(Constraint[2]) == 't' &&
15808 Constraint[3] == '(' &&
15809 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15810 Constraint[5] == ')' &&
15811 Constraint[6] == '}') {
15813 Res.first = X86::ST0+Constraint[4]-'0';
15814 Res.second = &X86::RFP80RegClass;
15818 // GCC allows "st(0)" to be called just plain "st".
15819 if (StringRef("{st}").equals_lower(Constraint)) {
15820 Res.first = X86::ST0;
15821 Res.second = &X86::RFP80RegClass;
15826 if (StringRef("{flags}").equals_lower(Constraint)) {
15827 Res.first = X86::EFLAGS;
15828 Res.second = &X86::CCRRegClass;
15832 // 'A' means EAX + EDX.
15833 if (Constraint == "A") {
15834 Res.first = X86::EAX;
15835 Res.second = &X86::GR32_ADRegClass;
15841 // Otherwise, check to see if this is a register class of the wrong value
15842 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15843 // turn into {ax},{dx}.
15844 if (Res.second->hasType(VT))
15845 return Res; // Correct type already, nothing to do.
15847 // All of the single-register GCC register classes map their values onto
15848 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15849 // really want an 8-bit or 32-bit register, map to the appropriate register
15850 // class and return the appropriate register.
15851 if (Res.second == &X86::GR16RegClass) {
15852 if (VT == MVT::i8) {
15853 unsigned DestReg = 0;
15854 switch (Res.first) {
15856 case X86::AX: DestReg = X86::AL; break;
15857 case X86::DX: DestReg = X86::DL; break;
15858 case X86::CX: DestReg = X86::CL; break;
15859 case X86::BX: DestReg = X86::BL; break;
15862 Res.first = DestReg;
15863 Res.second = &X86::GR8RegClass;
15865 } else if (VT == MVT::i32) {
15866 unsigned DestReg = 0;
15867 switch (Res.first) {
15869 case X86::AX: DestReg = X86::EAX; break;
15870 case X86::DX: DestReg = X86::EDX; break;
15871 case X86::CX: DestReg = X86::ECX; break;
15872 case X86::BX: DestReg = X86::EBX; break;
15873 case X86::SI: DestReg = X86::ESI; break;
15874 case X86::DI: DestReg = X86::EDI; break;
15875 case X86::BP: DestReg = X86::EBP; break;
15876 case X86::SP: DestReg = X86::ESP; break;
15879 Res.first = DestReg;
15880 Res.second = &X86::GR32RegClass;
15882 } else if (VT == MVT::i64) {
15883 unsigned DestReg = 0;
15884 switch (Res.first) {
15886 case X86::AX: DestReg = X86::RAX; break;
15887 case X86::DX: DestReg = X86::RDX; break;
15888 case X86::CX: DestReg = X86::RCX; break;
15889 case X86::BX: DestReg = X86::RBX; break;
15890 case X86::SI: DestReg = X86::RSI; break;
15891 case X86::DI: DestReg = X86::RDI; break;
15892 case X86::BP: DestReg = X86::RBP; break;
15893 case X86::SP: DestReg = X86::RSP; break;
15896 Res.first = DestReg;
15897 Res.second = &X86::GR64RegClass;
15900 } else if (Res.second == &X86::FR32RegClass ||
15901 Res.second == &X86::FR64RegClass ||
15902 Res.second == &X86::VR128RegClass) {
15903 // Handle references to XMM physical registers that got mapped into the
15904 // wrong class. This can happen with constraints like {xmm0} where the
15905 // target independent register mapper will just pick the first match it can
15906 // find, ignoring the required type.
15907 if (VT == MVT::f32)
15908 Res.second = &X86::FR32RegClass;
15909 else if (VT == MVT::f64)
15910 Res.second = &X86::FR64RegClass;
15911 else if (X86::VR128RegClass.hasType(VT))
15912 Res.second = &X86::VR128RegClass;