1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1201 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::f64, Legal);
1210 if (Subtarget->hasInt256()) {
1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1224 // Don't lower v32i8 because there is no 128-bit byte mul
1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1243 // Don't lower v32i8 because there is no 128-bit byte mul
1246 // In the customized shift lowering, the legal cases in AVX2 will be
1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1256 // Custom lower several nodes for 256-bit types.
1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType)i;
1261 // Extract subvector is special because the value type
1262 // (result) is 128-bit but the source is 256-bit wide.
1263 if (VT.is128BitVector())
1264 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1266 // Do not attempt to custom lower other non-256-bit vectors
1267 if (!VT.is256BitVector())
1270 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1281 MVT VT = (MVT::SimpleValueType)i;
1283 // Do not attempt to promote non-256-bit vectors
1284 if (!VT.is256BitVector())
1287 setOperationAction(ISD::AND, VT, Promote);
1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1289 setOperationAction(ISD::OR, VT, Promote);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1291 setOperationAction(ISD::XOR, VT, Promote);
1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1293 setOperationAction(ISD::LOAD, VT, Promote);
1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1295 setOperationAction(ISD::SELECT, VT, Promote);
1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1300 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1333 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1334 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1335 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1336 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1337 if (Subtarget->is64Bit()) {
1338 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1339 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1340 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1341 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1343 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1344 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1345 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1346 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1347 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1348 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1349 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1350 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1352 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1353 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1354 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1355 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1356 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1357 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1358 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1359 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1360 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1361 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1362 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1363 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1365 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1366 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1367 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1368 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1369 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1371 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1372 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1374 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1376 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1377 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1378 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1379 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1380 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1382 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1383 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1385 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1386 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1388 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1390 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1391 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1393 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1396 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1397 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1399 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1400 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1401 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1402 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1403 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1404 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1406 // Custom lower several nodes.
1407 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1408 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1409 MVT VT = (MVT::SimpleValueType)i;
1411 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1412 // Extract subvector is special because the value type
1413 // (result) is 256/128-bit but the source is 512-bit wide.
1414 if (VT.is128BitVector() || VT.is256BitVector())
1415 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1417 if (VT.getVectorElementType() == MVT::i1)
1418 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1420 // Do not attempt to custom lower other non-512-bit vectors
1421 if (!VT.is512BitVector())
1424 if ( EltSize >= 32) {
1425 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1426 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1427 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1428 setOperationAction(ISD::VSELECT, VT, Legal);
1429 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1430 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1431 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1434 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1435 MVT VT = (MVT::SimpleValueType)i;
1437 // Do not attempt to promote non-256-bit vectors
1438 if (!VT.is512BitVector())
1441 setOperationAction(ISD::SELECT, VT, Promote);
1442 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1446 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1447 // of this type with custom code.
1448 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1449 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1450 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1454 // We want to custom lower some of our intrinsics.
1455 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1456 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1457 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1459 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1460 // handle type legalization for these operations here.
1462 // FIXME: We really should do custom legalization for addition and
1463 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1464 // than generic legalization for 64-bit multiplication-with-overflow, though.
1465 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1466 // Add/Sub/Mul with overflow operations are custom lowered.
1468 setOperationAction(ISD::SADDO, VT, Custom);
1469 setOperationAction(ISD::UADDO, VT, Custom);
1470 setOperationAction(ISD::SSUBO, VT, Custom);
1471 setOperationAction(ISD::USUBO, VT, Custom);
1472 setOperationAction(ISD::SMULO, VT, Custom);
1473 setOperationAction(ISD::UMULO, VT, Custom);
1476 // There are no 8-bit 3-address imul/mul instructions
1477 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1478 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1480 if (!Subtarget->is64Bit()) {
1481 // These libcalls are not available in 32-bit.
1482 setLibcallName(RTLIB::SHL_I128, 0);
1483 setLibcallName(RTLIB::SRL_I128, 0);
1484 setLibcallName(RTLIB::SRA_I128, 0);
1487 // Combine sin / cos into one node or libcall if possible.
1488 if (Subtarget->hasSinCos()) {
1489 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1490 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1491 if (Subtarget->isTargetDarwin()) {
1492 // For MacOSX, we don't want to the normal expansion of a libcall to
1493 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1495 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1496 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1500 // We have target-specific dag combine patterns for the following nodes:
1501 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1502 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1503 setTargetDAGCombine(ISD::VSELECT);
1504 setTargetDAGCombine(ISD::SELECT);
1505 setTargetDAGCombine(ISD::SHL);
1506 setTargetDAGCombine(ISD::SRA);
1507 setTargetDAGCombine(ISD::SRL);
1508 setTargetDAGCombine(ISD::OR);
1509 setTargetDAGCombine(ISD::AND);
1510 setTargetDAGCombine(ISD::ADD);
1511 setTargetDAGCombine(ISD::FADD);
1512 setTargetDAGCombine(ISD::FSUB);
1513 setTargetDAGCombine(ISD::FMA);
1514 setTargetDAGCombine(ISD::SUB);
1515 setTargetDAGCombine(ISD::LOAD);
1516 setTargetDAGCombine(ISD::STORE);
1517 setTargetDAGCombine(ISD::ZERO_EXTEND);
1518 setTargetDAGCombine(ISD::ANY_EXTEND);
1519 setTargetDAGCombine(ISD::SIGN_EXTEND);
1520 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1521 setTargetDAGCombine(ISD::TRUNCATE);
1522 setTargetDAGCombine(ISD::SINT_TO_FP);
1523 setTargetDAGCombine(ISD::SETCC);
1524 if (Subtarget->is64Bit())
1525 setTargetDAGCombine(ISD::MUL);
1526 setTargetDAGCombine(ISD::XOR);
1528 computeRegisterProperties();
1530 // On Darwin, -Os means optimize for size without hurting performance,
1531 // do not reduce the limit.
1532 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1533 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1534 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1535 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1536 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1537 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1538 setPrefLoopAlignment(4); // 2^4 bytes.
1540 // Predictable cmov don't hurt on atom because it's in-order.
1541 PredictableSelectIsExpensive = !Subtarget->isAtom();
1543 setPrefFunctionAlignment(4); // 2^4 bytes.
1546 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1547 if (!VT.isVector()) return MVT::i8;
1548 return VT.changeVectorElementTypeToInteger();
1551 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1552 /// the desired ByVal argument alignment.
1553 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1556 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1557 if (VTy->getBitWidth() == 128)
1559 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1560 unsigned EltAlign = 0;
1561 getMaxByValAlign(ATy->getElementType(), EltAlign);
1562 if (EltAlign > MaxAlign)
1563 MaxAlign = EltAlign;
1564 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1565 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1566 unsigned EltAlign = 0;
1567 getMaxByValAlign(STy->getElementType(i), EltAlign);
1568 if (EltAlign > MaxAlign)
1569 MaxAlign = EltAlign;
1576 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1577 /// function arguments in the caller parameter area. For X86, aggregates
1578 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1579 /// are at 4-byte boundaries.
1580 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1581 if (Subtarget->is64Bit()) {
1582 // Max of 8 and alignment of type.
1583 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1590 if (Subtarget->hasSSE1())
1591 getMaxByValAlign(Ty, Align);
1595 /// getOptimalMemOpType - Returns the target specific optimal type for load
1596 /// and store operations as a result of memset, memcpy, and memmove
1597 /// lowering. If DstAlign is zero that means it's safe to destination
1598 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1599 /// means there isn't a need to check it against alignment requirement,
1600 /// probably because the source does not need to be loaded. If 'IsMemset' is
1601 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1602 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1603 /// source is constant so it does not need to be loaded.
1604 /// It returns EVT::Other if the type should be determined using generic
1605 /// target-independent logic.
1607 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1608 unsigned DstAlign, unsigned SrcAlign,
1609 bool IsMemset, bool ZeroMemset,
1611 MachineFunction &MF) const {
1612 const Function *F = MF.getFunction();
1613 if ((!IsMemset || ZeroMemset) &&
1614 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1615 Attribute::NoImplicitFloat)) {
1617 (Subtarget->isUnalignedMemAccessFast() ||
1618 ((DstAlign == 0 || DstAlign >= 16) &&
1619 (SrcAlign == 0 || SrcAlign >= 16)))) {
1621 if (Subtarget->hasInt256())
1623 if (Subtarget->hasFp256())
1626 if (Subtarget->hasSSE2())
1628 if (Subtarget->hasSSE1())
1630 } else if (!MemcpyStrSrc && Size >= 8 &&
1631 !Subtarget->is64Bit() &&
1632 Subtarget->hasSSE2()) {
1633 // Do not use f64 to lower memcpy if source is string constant. It's
1634 // better to use i32 to avoid the loads.
1638 if (Subtarget->is64Bit() && Size >= 8)
1643 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1645 return X86ScalarSSEf32;
1646 else if (VT == MVT::f64)
1647 return X86ScalarSSEf64;
1652 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1654 *Fast = Subtarget->isUnalignedMemAccessFast();
1658 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1659 /// current function. The returned value is a member of the
1660 /// MachineJumpTableInfo::JTEntryKind enum.
1661 unsigned X86TargetLowering::getJumpTableEncoding() const {
1662 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1664 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1665 Subtarget->isPICStyleGOT())
1666 return MachineJumpTableInfo::EK_Custom32;
1668 // Otherwise, use the normal jump table encoding heuristics.
1669 return TargetLowering::getJumpTableEncoding();
1673 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1674 const MachineBasicBlock *MBB,
1675 unsigned uid,MCContext &Ctx) const{
1676 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1677 Subtarget->isPICStyleGOT());
1678 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1680 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1681 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1684 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1686 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1687 SelectionDAG &DAG) const {
1688 if (!Subtarget->is64Bit())
1689 // This doesn't have SDLoc associated with it, but is not really the
1690 // same as a Register.
1691 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1695 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1696 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1698 const MCExpr *X86TargetLowering::
1699 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1700 MCContext &Ctx) const {
1701 // X86-64 uses RIP relative addressing based on the jump table label.
1702 if (Subtarget->isPICStyleRIPRel())
1703 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1705 // Otherwise, the reference is relative to the PIC base.
1706 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1709 // FIXME: Why this routine is here? Move to RegInfo!
1710 std::pair<const TargetRegisterClass*, uint8_t>
1711 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1712 const TargetRegisterClass *RRC = 0;
1714 switch (VT.SimpleTy) {
1716 return TargetLowering::findRepresentativeClass(VT);
1717 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1718 RRC = Subtarget->is64Bit() ?
1719 (const TargetRegisterClass*)&X86::GR64RegClass :
1720 (const TargetRegisterClass*)&X86::GR32RegClass;
1723 RRC = &X86::VR64RegClass;
1725 case MVT::f32: case MVT::f64:
1726 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1727 case MVT::v4f32: case MVT::v2f64:
1728 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1730 RRC = &X86::VR128RegClass;
1733 return std::make_pair(RRC, Cost);
1736 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1737 unsigned &Offset) const {
1738 if (!Subtarget->isTargetLinux())
1741 if (Subtarget->is64Bit()) {
1742 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1744 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1756 //===----------------------------------------------------------------------===//
1757 // Return Value Calling Convention Implementation
1758 //===----------------------------------------------------------------------===//
1760 #include "X86GenCallingConv.inc"
1763 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1764 MachineFunction &MF, bool isVarArg,
1765 const SmallVectorImpl<ISD::OutputArg> &Outs,
1766 LLVMContext &Context) const {
1767 SmallVector<CCValAssign, 16> RVLocs;
1768 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1770 return CCInfo.CheckReturn(Outs, RetCC_X86);
1774 X86TargetLowering::LowerReturn(SDValue Chain,
1775 CallingConv::ID CallConv, bool isVarArg,
1776 const SmallVectorImpl<ISD::OutputArg> &Outs,
1777 const SmallVectorImpl<SDValue> &OutVals,
1778 SDLoc dl, SelectionDAG &DAG) const {
1779 MachineFunction &MF = DAG.getMachineFunction();
1780 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1782 SmallVector<CCValAssign, 16> RVLocs;
1783 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1784 RVLocs, *DAG.getContext());
1785 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1788 SmallVector<SDValue, 6> RetOps;
1789 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1790 // Operand #1 = Bytes To Pop
1791 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1794 // Copy the result values into the output registers.
1795 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1796 CCValAssign &VA = RVLocs[i];
1797 assert(VA.isRegLoc() && "Can only return in registers!");
1798 SDValue ValToCopy = OutVals[i];
1799 EVT ValVT = ValToCopy.getValueType();
1801 // Promote values to the appropriate types
1802 if (VA.getLocInfo() == CCValAssign::SExt)
1803 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1804 else if (VA.getLocInfo() == CCValAssign::ZExt)
1805 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1806 else if (VA.getLocInfo() == CCValAssign::AExt)
1807 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1808 else if (VA.getLocInfo() == CCValAssign::BCvt)
1809 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1811 // If this is x86-64, and we disabled SSE, we can't return FP values,
1812 // or SSE or MMX vectors.
1813 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1814 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1815 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1816 report_fatal_error("SSE register return with SSE disabled");
1818 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1819 // llvm-gcc has never done it right and no one has noticed, so this
1820 // should be OK for now.
1821 if (ValVT == MVT::f64 &&
1822 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1823 report_fatal_error("SSE2 register return with SSE2 disabled");
1825 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1826 // the RET instruction and handled by the FP Stackifier.
1827 if (VA.getLocReg() == X86::ST0 ||
1828 VA.getLocReg() == X86::ST1) {
1829 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1830 // change the value to the FP stack register class.
1831 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1832 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1833 RetOps.push_back(ValToCopy);
1834 // Don't emit a copytoreg.
1838 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1839 // which is returned in RAX / RDX.
1840 if (Subtarget->is64Bit()) {
1841 if (ValVT == MVT::x86mmx) {
1842 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1843 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1844 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1846 // If we don't have SSE2 available, convert to v4f32 so the generated
1847 // register is legal.
1848 if (!Subtarget->hasSSE2())
1849 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1854 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1855 Flag = Chain.getValue(1);
1856 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1859 // The x86-64 ABIs require that for returning structs by value we copy
1860 // the sret argument into %rax/%eax (depending on ABI) for the return.
1861 // Win32 requires us to put the sret argument to %eax as well.
1862 // We saved the argument into a virtual register in the entry block,
1863 // so now we copy the value out and into %rax/%eax.
1864 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1865 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1866 MachineFunction &MF = DAG.getMachineFunction();
1867 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1868 unsigned Reg = FuncInfo->getSRetReturnReg();
1870 "SRetReturnReg should have been set in LowerFormalArguments().");
1871 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1874 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1875 X86::RAX : X86::EAX;
1876 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1877 Flag = Chain.getValue(1);
1879 // RAX/EAX now acts like a return value.
1880 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1883 RetOps[0] = Chain; // Update chain.
1885 // Add the flag if we have it.
1887 RetOps.push_back(Flag);
1889 return DAG.getNode(X86ISD::RET_FLAG, dl,
1890 MVT::Other, &RetOps[0], RetOps.size());
1893 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1894 if (N->getNumValues() != 1)
1896 if (!N->hasNUsesOfValue(1, 0))
1899 SDValue TCChain = Chain;
1900 SDNode *Copy = *N->use_begin();
1901 if (Copy->getOpcode() == ISD::CopyToReg) {
1902 // If the copy has a glue operand, we conservatively assume it isn't safe to
1903 // perform a tail call.
1904 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1906 TCChain = Copy->getOperand(0);
1907 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1910 bool HasRet = false;
1911 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1913 if (UI->getOpcode() != X86ISD::RET_FLAG)
1926 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1927 ISD::NodeType ExtendKind) const {
1929 // TODO: Is this also valid on 32-bit?
1930 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1931 ReturnMVT = MVT::i8;
1933 ReturnMVT = MVT::i32;
1935 MVT MinVT = getRegisterType(ReturnMVT);
1936 return VT.bitsLT(MinVT) ? MinVT : VT;
1939 /// LowerCallResult - Lower the result values of a call into the
1940 /// appropriate copies out of appropriate physical registers.
1943 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1944 CallingConv::ID CallConv, bool isVarArg,
1945 const SmallVectorImpl<ISD::InputArg> &Ins,
1946 SDLoc dl, SelectionDAG &DAG,
1947 SmallVectorImpl<SDValue> &InVals) const {
1949 // Assign locations to each value returned by this call.
1950 SmallVector<CCValAssign, 16> RVLocs;
1951 bool Is64Bit = Subtarget->is64Bit();
1952 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1953 getTargetMachine(), RVLocs, *DAG.getContext());
1954 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1956 // Copy all of the result registers out of their specified physreg.
1957 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1958 CCValAssign &VA = RVLocs[i];
1959 EVT CopyVT = VA.getValVT();
1961 // If this is x86-64, and we disabled SSE, we can't return FP values
1962 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1963 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1964 report_fatal_error("SSE register return with SSE disabled");
1969 // If this is a call to a function that returns an fp value on the floating
1970 // point stack, we must guarantee the value is popped from the stack, so
1971 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1972 // if the return value is not used. We use the FpPOP_RETVAL instruction
1974 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1975 // If we prefer to use the value in xmm registers, copy it out as f80 and
1976 // use a truncate to move it from fp stack reg to xmm reg.
1977 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1978 SDValue Ops[] = { Chain, InFlag };
1979 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1980 MVT::Other, MVT::Glue, Ops), 1);
1981 Val = Chain.getValue(0);
1983 // Round the f80 to the right size, which also moves it to the appropriate
1985 if (CopyVT != VA.getValVT())
1986 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1987 // This truncation won't change the value.
1988 DAG.getIntPtrConstant(1));
1990 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1991 CopyVT, InFlag).getValue(1);
1992 Val = Chain.getValue(0);
1994 InFlag = Chain.getValue(2);
1995 InVals.push_back(Val);
2001 //===----------------------------------------------------------------------===//
2002 // C & StdCall & Fast Calling Convention implementation
2003 //===----------------------------------------------------------------------===//
2004 // StdCall calling convention seems to be standard for many Windows' API
2005 // routines and around. It differs from C calling convention just a little:
2006 // callee should clean up the stack, not caller. Symbols should be also
2007 // decorated in some fancy way :) It doesn't support any vector arguments.
2008 // For info on fast calling convention see Fast Calling Convention (tail call)
2009 // implementation LowerX86_32FastCCCallTo.
2011 /// CallIsStructReturn - Determines whether a call uses struct return
2013 enum StructReturnType {
2018 static StructReturnType
2019 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2021 return NotStructReturn;
2023 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2024 if (!Flags.isSRet())
2025 return NotStructReturn;
2026 if (Flags.isInReg())
2027 return RegStructReturn;
2028 return StackStructReturn;
2031 /// ArgsAreStructReturn - Determines whether a function uses struct
2032 /// return semantics.
2033 static StructReturnType
2034 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2036 return NotStructReturn;
2038 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2039 if (!Flags.isSRet())
2040 return NotStructReturn;
2041 if (Flags.isInReg())
2042 return RegStructReturn;
2043 return StackStructReturn;
2046 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2047 /// by "Src" to address "Dst" with size and alignment information specified by
2048 /// the specific parameter attribute. The copy will be passed as a byval
2049 /// function parameter.
2051 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2052 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2054 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2056 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2057 /*isVolatile*/false, /*AlwaysInline=*/true,
2058 MachinePointerInfo(), MachinePointerInfo());
2061 /// IsTailCallConvention - Return true if the calling convention is one that
2062 /// supports tail call optimization.
2063 static bool IsTailCallConvention(CallingConv::ID CC) {
2064 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2065 CC == CallingConv::HiPE);
2068 /// \brief Return true if the calling convention is a C calling convention.
2069 static bool IsCCallConvention(CallingConv::ID CC) {
2070 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2071 CC == CallingConv::X86_64_SysV);
2074 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2075 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2079 CallingConv::ID CalleeCC = CS.getCallingConv();
2080 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2086 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2087 /// a tailcall target by changing its ABI.
2088 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2089 bool GuaranteedTailCallOpt) {
2090 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2094 X86TargetLowering::LowerMemArgument(SDValue Chain,
2095 CallingConv::ID CallConv,
2096 const SmallVectorImpl<ISD::InputArg> &Ins,
2097 SDLoc dl, SelectionDAG &DAG,
2098 const CCValAssign &VA,
2099 MachineFrameInfo *MFI,
2101 // Create the nodes corresponding to a load from this parameter slot.
2102 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2103 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2104 getTargetMachine().Options.GuaranteedTailCallOpt);
2105 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2108 // If value is passed by pointer we have address passed instead of the value
2110 if (VA.getLocInfo() == CCValAssign::Indirect)
2111 ValVT = VA.getLocVT();
2113 ValVT = VA.getValVT();
2115 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2116 // changed with more analysis.
2117 // In case of tail call optimization mark all arguments mutable. Since they
2118 // could be overwritten by lowering of arguments in case of a tail call.
2119 if (Flags.isByVal()) {
2120 unsigned Bytes = Flags.getByValSize();
2121 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2122 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2123 return DAG.getFrameIndex(FI, getPointerTy());
2125 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2126 VA.getLocMemOffset(), isImmutable);
2127 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2128 return DAG.getLoad(ValVT, dl, Chain, FIN,
2129 MachinePointerInfo::getFixedStack(FI),
2130 false, false, false, 0);
2135 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2136 CallingConv::ID CallConv,
2138 const SmallVectorImpl<ISD::InputArg> &Ins,
2141 SmallVectorImpl<SDValue> &InVals)
2143 MachineFunction &MF = DAG.getMachineFunction();
2144 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2146 const Function* Fn = MF.getFunction();
2147 if (Fn->hasExternalLinkage() &&
2148 Subtarget->isTargetCygMing() &&
2149 Fn->getName() == "main")
2150 FuncInfo->setForceFramePointer(true);
2152 MachineFrameInfo *MFI = MF.getFrameInfo();
2153 bool Is64Bit = Subtarget->is64Bit();
2154 bool IsWindows = Subtarget->isTargetWindows();
2155 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2157 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2158 "Var args not supported with calling convention fastcc, ghc or hipe");
2160 // Assign locations to all of the incoming arguments.
2161 SmallVector<CCValAssign, 16> ArgLocs;
2162 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2163 ArgLocs, *DAG.getContext());
2165 // Allocate shadow area for Win64
2167 CCInfo.AllocateStack(32, 8);
2169 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2171 unsigned LastVal = ~0U;
2173 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2174 CCValAssign &VA = ArgLocs[i];
2175 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2177 assert(VA.getValNo() != LastVal &&
2178 "Don't support value assigned to multiple locs yet");
2180 LastVal = VA.getValNo();
2182 if (VA.isRegLoc()) {
2183 EVT RegVT = VA.getLocVT();
2184 const TargetRegisterClass *RC;
2185 if (RegVT == MVT::i32)
2186 RC = &X86::GR32RegClass;
2187 else if (Is64Bit && RegVT == MVT::i64)
2188 RC = &X86::GR64RegClass;
2189 else if (RegVT == MVT::f32)
2190 RC = &X86::FR32RegClass;
2191 else if (RegVT == MVT::f64)
2192 RC = &X86::FR64RegClass;
2193 else if (RegVT.is512BitVector())
2194 RC = &X86::VR512RegClass;
2195 else if (RegVT.is256BitVector())
2196 RC = &X86::VR256RegClass;
2197 else if (RegVT.is128BitVector())
2198 RC = &X86::VR128RegClass;
2199 else if (RegVT == MVT::x86mmx)
2200 RC = &X86::VR64RegClass;
2201 else if (RegVT == MVT::v8i1)
2202 RC = &X86::VK8RegClass;
2203 else if (RegVT == MVT::v16i1)
2204 RC = &X86::VK16RegClass;
2206 llvm_unreachable("Unknown argument type!");
2208 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2209 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2211 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2212 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2214 if (VA.getLocInfo() == CCValAssign::SExt)
2215 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2216 DAG.getValueType(VA.getValVT()));
2217 else if (VA.getLocInfo() == CCValAssign::ZExt)
2218 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2219 DAG.getValueType(VA.getValVT()));
2220 else if (VA.getLocInfo() == CCValAssign::BCvt)
2221 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2223 if (VA.isExtInLoc()) {
2224 // Handle MMX values passed in XMM regs.
2225 if (RegVT.isVector())
2226 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2228 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2231 assert(VA.isMemLoc());
2232 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2235 // If value is passed via pointer - do a load.
2236 if (VA.getLocInfo() == CCValAssign::Indirect)
2237 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2238 MachinePointerInfo(), false, false, false, 0);
2240 InVals.push_back(ArgValue);
2243 // The x86-64 ABIs require that for returning structs by value we copy
2244 // the sret argument into %rax/%eax (depending on ABI) for the return.
2245 // Win32 requires us to put the sret argument to %eax as well.
2246 // Save the argument into a virtual register so that we can access it
2247 // from the return points.
2248 if (MF.getFunction()->hasStructRetAttr() &&
2249 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2250 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2251 unsigned Reg = FuncInfo->getSRetReturnReg();
2253 MVT PtrTy = getPointerTy();
2254 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2255 FuncInfo->setSRetReturnReg(Reg);
2257 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2258 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2261 unsigned StackSize = CCInfo.getNextStackOffset();
2262 // Align stack specially for tail calls.
2263 if (FuncIsMadeTailCallSafe(CallConv,
2264 MF.getTarget().Options.GuaranteedTailCallOpt))
2265 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2267 // If the function takes variable number of arguments, make a frame index for
2268 // the start of the first vararg value... for expansion of llvm.va_start.
2270 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2271 CallConv != CallingConv::X86_ThisCall)) {
2272 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2275 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2277 // FIXME: We should really autogenerate these arrays
2278 static const uint16_t GPR64ArgRegsWin64[] = {
2279 X86::RCX, X86::RDX, X86::R8, X86::R9
2281 static const uint16_t GPR64ArgRegs64Bit[] = {
2282 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2284 static const uint16_t XMMArgRegs64Bit[] = {
2285 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2286 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2288 const uint16_t *GPR64ArgRegs;
2289 unsigned NumXMMRegs = 0;
2292 // The XMM registers which might contain var arg parameters are shadowed
2293 // in their paired GPR. So we only need to save the GPR to their home
2295 TotalNumIntRegs = 4;
2296 GPR64ArgRegs = GPR64ArgRegsWin64;
2298 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2299 GPR64ArgRegs = GPR64ArgRegs64Bit;
2301 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2304 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2307 bool NoImplicitFloatOps = Fn->getAttributes().
2308 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2309 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2310 "SSE register cannot be used when SSE is disabled!");
2311 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2312 NoImplicitFloatOps) &&
2313 "SSE register cannot be used when SSE is disabled!");
2314 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2315 !Subtarget->hasSSE1())
2316 // Kernel mode asks for SSE to be disabled, so don't push them
2318 TotalNumXMMRegs = 0;
2321 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2322 // Get to the caller-allocated home save location. Add 8 to account
2323 // for the return address.
2324 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2325 FuncInfo->setRegSaveFrameIndex(
2326 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2327 // Fixup to set vararg frame on shadow area (4 x i64).
2329 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2331 // For X86-64, if there are vararg parameters that are passed via
2332 // registers, then we must store them to their spots on the stack so
2333 // they may be loaded by deferencing the result of va_next.
2334 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2335 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2336 FuncInfo->setRegSaveFrameIndex(
2337 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2341 // Store the integer parameter registers.
2342 SmallVector<SDValue, 8> MemOps;
2343 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2345 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2346 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2347 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2348 DAG.getIntPtrConstant(Offset));
2349 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2350 &X86::GR64RegClass);
2351 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2353 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2354 MachinePointerInfo::getFixedStack(
2355 FuncInfo->getRegSaveFrameIndex(), Offset),
2357 MemOps.push_back(Store);
2361 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2362 // Now store the XMM (fp + vector) parameter registers.
2363 SmallVector<SDValue, 11> SaveXMMOps;
2364 SaveXMMOps.push_back(Chain);
2366 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2367 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2368 SaveXMMOps.push_back(ALVal);
2370 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2371 FuncInfo->getRegSaveFrameIndex()));
2372 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2373 FuncInfo->getVarArgsFPOffset()));
2375 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2376 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2377 &X86::VR128RegClass);
2378 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2379 SaveXMMOps.push_back(Val);
2381 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2383 &SaveXMMOps[0], SaveXMMOps.size()));
2386 if (!MemOps.empty())
2387 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2388 &MemOps[0], MemOps.size());
2392 // Some CCs need callee pop.
2393 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2394 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2395 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2397 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2398 // If this is an sret function, the return should pop the hidden pointer.
2399 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2400 argsAreStructReturn(Ins) == StackStructReturn)
2401 FuncInfo->setBytesToPopOnReturn(4);
2405 // RegSaveFrameIndex is X86-64 only.
2406 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2407 if (CallConv == CallingConv::X86_FastCall ||
2408 CallConv == CallingConv::X86_ThisCall)
2409 // fastcc functions can't have varargs.
2410 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2413 FuncInfo->setArgumentStackSize(StackSize);
2419 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2420 SDValue StackPtr, SDValue Arg,
2421 SDLoc dl, SelectionDAG &DAG,
2422 const CCValAssign &VA,
2423 ISD::ArgFlagsTy Flags) const {
2424 unsigned LocMemOffset = VA.getLocMemOffset();
2425 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2426 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2427 if (Flags.isByVal())
2428 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2430 return DAG.getStore(Chain, dl, Arg, PtrOff,
2431 MachinePointerInfo::getStack(LocMemOffset),
2435 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2436 /// optimization is performed and it is required.
2438 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2439 SDValue &OutRetAddr, SDValue Chain,
2440 bool IsTailCall, bool Is64Bit,
2441 int FPDiff, SDLoc dl) const {
2442 // Adjust the Return address stack slot.
2443 EVT VT = getPointerTy();
2444 OutRetAddr = getReturnAddressFrameIndex(DAG);
2446 // Load the "old" Return address.
2447 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2448 false, false, false, 0);
2449 return SDValue(OutRetAddr.getNode(), 1);
2452 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2453 /// optimization is performed and it is required (FPDiff!=0).
2455 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2456 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2457 unsigned SlotSize, int FPDiff, SDLoc dl) {
2458 // Store the return address to the appropriate stack slot.
2459 if (!FPDiff) return Chain;
2460 // Calculate the new stack slot for the return address.
2461 int NewReturnAddrFI =
2462 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2464 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2465 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2466 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2472 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2473 SmallVectorImpl<SDValue> &InVals) const {
2474 SelectionDAG &DAG = CLI.DAG;
2476 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2477 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2478 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2479 SDValue Chain = CLI.Chain;
2480 SDValue Callee = CLI.Callee;
2481 CallingConv::ID CallConv = CLI.CallConv;
2482 bool &isTailCall = CLI.IsTailCall;
2483 bool isVarArg = CLI.IsVarArg;
2485 MachineFunction &MF = DAG.getMachineFunction();
2486 bool Is64Bit = Subtarget->is64Bit();
2487 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2488 bool IsWindows = Subtarget->isTargetWindows();
2489 StructReturnType SR = callIsStructReturn(Outs);
2490 bool IsSibcall = false;
2492 if (MF.getTarget().Options.DisableTailCalls)
2496 // Check if it's really possible to do a tail call.
2497 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2498 isVarArg, SR != NotStructReturn,
2499 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2500 Outs, OutVals, Ins, DAG);
2502 // Sibcalls are automatically detected tailcalls which do not require
2504 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2511 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2512 "Var args not supported with calling convention fastcc, ghc or hipe");
2514 // Analyze operands of the call, assigning locations to each operand.
2515 SmallVector<CCValAssign, 16> ArgLocs;
2516 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2517 ArgLocs, *DAG.getContext());
2519 // Allocate shadow area for Win64
2521 CCInfo.AllocateStack(32, 8);
2523 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2525 // Get a count of how many bytes are to be pushed on the stack.
2526 unsigned NumBytes = CCInfo.getNextStackOffset();
2528 // This is a sibcall. The memory operands are available in caller's
2529 // own caller's stack.
2531 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2532 IsTailCallConvention(CallConv))
2533 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2536 if (isTailCall && !IsSibcall) {
2537 // Lower arguments at fp - stackoffset + fpdiff.
2538 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2539 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2541 FPDiff = NumBytesCallerPushed - NumBytes;
2543 // Set the delta of movement of the returnaddr stackslot.
2544 // But only set if delta is greater than previous delta.
2545 if (FPDiff < X86Info->getTCReturnAddrDelta())
2546 X86Info->setTCReturnAddrDelta(FPDiff);
2550 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2553 SDValue RetAddrFrIdx;
2554 // Load return address for tail calls.
2555 if (isTailCall && FPDiff)
2556 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2557 Is64Bit, FPDiff, dl);
2559 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2560 SmallVector<SDValue, 8> MemOpChains;
2563 // Walk the register/memloc assignments, inserting copies/loads. In the case
2564 // of tail call optimization arguments are handle later.
2565 const X86RegisterInfo *RegInfo =
2566 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2567 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2568 CCValAssign &VA = ArgLocs[i];
2569 EVT RegVT = VA.getLocVT();
2570 SDValue Arg = OutVals[i];
2571 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2572 bool isByVal = Flags.isByVal();
2574 // Promote the value if needed.
2575 switch (VA.getLocInfo()) {
2576 default: llvm_unreachable("Unknown loc info!");
2577 case CCValAssign::Full: break;
2578 case CCValAssign::SExt:
2579 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2581 case CCValAssign::ZExt:
2582 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2584 case CCValAssign::AExt:
2585 if (RegVT.is128BitVector()) {
2586 // Special case: passing MMX values in XMM registers.
2587 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2588 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2589 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2591 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2593 case CCValAssign::BCvt:
2594 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2596 case CCValAssign::Indirect: {
2597 // Store the argument.
2598 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2599 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2600 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2601 MachinePointerInfo::getFixedStack(FI),
2608 if (VA.isRegLoc()) {
2609 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2610 if (isVarArg && IsWin64) {
2611 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2612 // shadow reg if callee is a varargs function.
2613 unsigned ShadowReg = 0;
2614 switch (VA.getLocReg()) {
2615 case X86::XMM0: ShadowReg = X86::RCX; break;
2616 case X86::XMM1: ShadowReg = X86::RDX; break;
2617 case X86::XMM2: ShadowReg = X86::R8; break;
2618 case X86::XMM3: ShadowReg = X86::R9; break;
2621 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2623 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2624 assert(VA.isMemLoc());
2625 if (StackPtr.getNode() == 0)
2626 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2628 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2629 dl, DAG, VA, Flags));
2633 if (!MemOpChains.empty())
2634 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2635 &MemOpChains[0], MemOpChains.size());
2637 if (Subtarget->isPICStyleGOT()) {
2638 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2641 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2642 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2644 // If we are tail calling and generating PIC/GOT style code load the
2645 // address of the callee into ECX. The value in ecx is used as target of
2646 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2647 // for tail calls on PIC/GOT architectures. Normally we would just put the
2648 // address of GOT into ebx and then call target@PLT. But for tail calls
2649 // ebx would be restored (since ebx is callee saved) before jumping to the
2652 // Note: The actual moving to ECX is done further down.
2653 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2654 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2655 !G->getGlobal()->hasProtectedVisibility())
2656 Callee = LowerGlobalAddress(Callee, DAG);
2657 else if (isa<ExternalSymbolSDNode>(Callee))
2658 Callee = LowerExternalSymbol(Callee, DAG);
2662 if (Is64Bit && isVarArg && !IsWin64) {
2663 // From AMD64 ABI document:
2664 // For calls that may call functions that use varargs or stdargs
2665 // (prototype-less calls or calls to functions containing ellipsis (...) in
2666 // the declaration) %al is used as hidden argument to specify the number
2667 // of SSE registers used. The contents of %al do not need to match exactly
2668 // the number of registers, but must be an ubound on the number of SSE
2669 // registers used and is in the range 0 - 8 inclusive.
2671 // Count the number of XMM registers allocated.
2672 static const uint16_t XMMArgRegs[] = {
2673 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2674 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2676 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2677 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2678 && "SSE registers cannot be used when SSE is disabled");
2680 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2681 DAG.getConstant(NumXMMRegs, MVT::i8)));
2684 // For tail calls lower the arguments to the 'real' stack slot.
2686 // Force all the incoming stack arguments to be loaded from the stack
2687 // before any new outgoing arguments are stored to the stack, because the
2688 // outgoing stack slots may alias the incoming argument stack slots, and
2689 // the alias isn't otherwise explicit. This is slightly more conservative
2690 // than necessary, because it means that each store effectively depends
2691 // on every argument instead of just those arguments it would clobber.
2692 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2694 SmallVector<SDValue, 8> MemOpChains2;
2697 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2698 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2699 CCValAssign &VA = ArgLocs[i];
2702 assert(VA.isMemLoc());
2703 SDValue Arg = OutVals[i];
2704 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2705 // Create frame index.
2706 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2707 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2708 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2709 FIN = DAG.getFrameIndex(FI, getPointerTy());
2711 if (Flags.isByVal()) {
2712 // Copy relative to framepointer.
2713 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2714 if (StackPtr.getNode() == 0)
2715 StackPtr = DAG.getCopyFromReg(Chain, dl,
2716 RegInfo->getStackRegister(),
2718 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2720 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2724 // Store relative to framepointer.
2725 MemOpChains2.push_back(
2726 DAG.getStore(ArgChain, dl, Arg, FIN,
2727 MachinePointerInfo::getFixedStack(FI),
2733 if (!MemOpChains2.empty())
2734 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2735 &MemOpChains2[0], MemOpChains2.size());
2737 // Store the return address to the appropriate stack slot.
2738 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2739 getPointerTy(), RegInfo->getSlotSize(),
2743 // Build a sequence of copy-to-reg nodes chained together with token chain
2744 // and flag operands which copy the outgoing args into registers.
2746 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2747 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2748 RegsToPass[i].second, InFlag);
2749 InFlag = Chain.getValue(1);
2752 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2753 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2754 // In the 64-bit large code model, we have to make all calls
2755 // through a register, since the call instruction's 32-bit
2756 // pc-relative offset may not be large enough to hold the whole
2758 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2759 // If the callee is a GlobalAddress node (quite common, every direct call
2760 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2763 // We should use extra load for direct calls to dllimported functions in
2765 const GlobalValue *GV = G->getGlobal();
2766 if (!GV->hasDLLImportLinkage()) {
2767 unsigned char OpFlags = 0;
2768 bool ExtraLoad = false;
2769 unsigned WrapperKind = ISD::DELETED_NODE;
2771 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2772 // external symbols most go through the PLT in PIC mode. If the symbol
2773 // has hidden or protected visibility, or if it is static or local, then
2774 // we don't need to use the PLT - we can directly call it.
2775 if (Subtarget->isTargetELF() &&
2776 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2777 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2778 OpFlags = X86II::MO_PLT;
2779 } else if (Subtarget->isPICStyleStubAny() &&
2780 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2781 (!Subtarget->getTargetTriple().isMacOSX() ||
2782 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2783 // PC-relative references to external symbols should go through $stub,
2784 // unless we're building with the leopard linker or later, which
2785 // automatically synthesizes these stubs.
2786 OpFlags = X86II::MO_DARWIN_STUB;
2787 } else if (Subtarget->isPICStyleRIPRel() &&
2788 isa<Function>(GV) &&
2789 cast<Function>(GV)->getAttributes().
2790 hasAttribute(AttributeSet::FunctionIndex,
2791 Attribute::NonLazyBind)) {
2792 // If the function is marked as non-lazy, generate an indirect call
2793 // which loads from the GOT directly. This avoids runtime overhead
2794 // at the cost of eager binding (and one extra byte of encoding).
2795 OpFlags = X86II::MO_GOTPCREL;
2796 WrapperKind = X86ISD::WrapperRIP;
2800 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2801 G->getOffset(), OpFlags);
2803 // Add a wrapper if needed.
2804 if (WrapperKind != ISD::DELETED_NODE)
2805 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2806 // Add extra indirection if needed.
2808 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2809 MachinePointerInfo::getGOT(),
2810 false, false, false, 0);
2812 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2813 unsigned char OpFlags = 0;
2815 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2816 // external symbols should go through the PLT.
2817 if (Subtarget->isTargetELF() &&
2818 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2819 OpFlags = X86II::MO_PLT;
2820 } else if (Subtarget->isPICStyleStubAny() &&
2821 (!Subtarget->getTargetTriple().isMacOSX() ||
2822 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2823 // PC-relative references to external symbols should go through $stub,
2824 // unless we're building with the leopard linker or later, which
2825 // automatically synthesizes these stubs.
2826 OpFlags = X86II::MO_DARWIN_STUB;
2829 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2833 // Returns a chain & a flag for retval copy to use.
2834 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2835 SmallVector<SDValue, 8> Ops;
2837 if (!IsSibcall && isTailCall) {
2838 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2839 DAG.getIntPtrConstant(0, true), InFlag, dl);
2840 InFlag = Chain.getValue(1);
2843 Ops.push_back(Chain);
2844 Ops.push_back(Callee);
2847 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2849 // Add argument registers to the end of the list so that they are known live
2851 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2852 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2853 RegsToPass[i].second.getValueType()));
2855 // Add a register mask operand representing the call-preserved registers.
2856 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2857 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2858 assert(Mask && "Missing call preserved mask for calling convention");
2859 Ops.push_back(DAG.getRegisterMask(Mask));
2861 if (InFlag.getNode())
2862 Ops.push_back(InFlag);
2866 //// If this is the first return lowered for this function, add the regs
2867 //// to the liveout set for the function.
2868 // This isn't right, although it's probably harmless on x86; liveouts
2869 // should be computed from returns not tail calls. Consider a void
2870 // function making a tail call to a function returning int.
2871 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2874 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2875 InFlag = Chain.getValue(1);
2877 // Create the CALLSEQ_END node.
2878 unsigned NumBytesForCalleeToPush;
2879 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2880 getTargetMachine().Options.GuaranteedTailCallOpt))
2881 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2882 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2883 SR == StackStructReturn)
2884 // If this is a call to a struct-return function, the callee
2885 // pops the hidden struct pointer, so we have to push it back.
2886 // This is common for Darwin/X86, Linux & Mingw32 targets.
2887 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2888 NumBytesForCalleeToPush = 4;
2890 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2892 // Returns a flag for retval copy to use.
2894 Chain = DAG.getCALLSEQ_END(Chain,
2895 DAG.getIntPtrConstant(NumBytes, true),
2896 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2899 InFlag = Chain.getValue(1);
2902 // Handle result values, copying them out of physregs into vregs that we
2904 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2905 Ins, dl, DAG, InVals);
2908 //===----------------------------------------------------------------------===//
2909 // Fast Calling Convention (tail call) implementation
2910 //===----------------------------------------------------------------------===//
2912 // Like std call, callee cleans arguments, convention except that ECX is
2913 // reserved for storing the tail called function address. Only 2 registers are
2914 // free for argument passing (inreg). Tail call optimization is performed
2916 // * tailcallopt is enabled
2917 // * caller/callee are fastcc
2918 // On X86_64 architecture with GOT-style position independent code only local
2919 // (within module) calls are supported at the moment.
2920 // To keep the stack aligned according to platform abi the function
2921 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2922 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2923 // If a tail called function callee has more arguments than the caller the
2924 // caller needs to make sure that there is room to move the RETADDR to. This is
2925 // achieved by reserving an area the size of the argument delta right after the
2926 // original REtADDR, but before the saved framepointer or the spilled registers
2927 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2939 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2940 /// for a 16 byte align requirement.
2942 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2943 SelectionDAG& DAG) const {
2944 MachineFunction &MF = DAG.getMachineFunction();
2945 const TargetMachine &TM = MF.getTarget();
2946 const X86RegisterInfo *RegInfo =
2947 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2948 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2949 unsigned StackAlignment = TFI.getStackAlignment();
2950 uint64_t AlignMask = StackAlignment - 1;
2951 int64_t Offset = StackSize;
2952 unsigned SlotSize = RegInfo->getSlotSize();
2953 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2954 // Number smaller than 12 so just add the difference.
2955 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2957 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2958 Offset = ((~AlignMask) & Offset) + StackAlignment +
2959 (StackAlignment-SlotSize);
2964 /// MatchingStackOffset - Return true if the given stack call argument is
2965 /// already available in the same position (relatively) of the caller's
2966 /// incoming argument stack.
2968 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2969 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2970 const X86InstrInfo *TII) {
2971 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2973 if (Arg.getOpcode() == ISD::CopyFromReg) {
2974 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2975 if (!TargetRegisterInfo::isVirtualRegister(VR))
2977 MachineInstr *Def = MRI->getVRegDef(VR);
2980 if (!Flags.isByVal()) {
2981 if (!TII->isLoadFromStackSlot(Def, FI))
2984 unsigned Opcode = Def->getOpcode();
2985 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2986 Def->getOperand(1).isFI()) {
2987 FI = Def->getOperand(1).getIndex();
2988 Bytes = Flags.getByValSize();
2992 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2993 if (Flags.isByVal())
2994 // ByVal argument is passed in as a pointer but it's now being
2995 // dereferenced. e.g.
2996 // define @foo(%struct.X* %A) {
2997 // tail call @bar(%struct.X* byval %A)
3000 SDValue Ptr = Ld->getBasePtr();
3001 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3004 FI = FINode->getIndex();
3005 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3006 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3007 FI = FINode->getIndex();
3008 Bytes = Flags.getByValSize();
3012 assert(FI != INT_MAX);
3013 if (!MFI->isFixedObjectIndex(FI))
3015 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3018 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3019 /// for tail call optimization. Targets which want to do tail call
3020 /// optimization should implement this function.
3022 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3023 CallingConv::ID CalleeCC,
3025 bool isCalleeStructRet,
3026 bool isCallerStructRet,
3028 const SmallVectorImpl<ISD::OutputArg> &Outs,
3029 const SmallVectorImpl<SDValue> &OutVals,
3030 const SmallVectorImpl<ISD::InputArg> &Ins,
3031 SelectionDAG &DAG) const {
3032 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3035 // If -tailcallopt is specified, make fastcc functions tail-callable.
3036 const MachineFunction &MF = DAG.getMachineFunction();
3037 const Function *CallerF = MF.getFunction();
3039 // If the function return type is x86_fp80 and the callee return type is not,
3040 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3041 // perform a tailcall optimization here.
3042 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3045 CallingConv::ID CallerCC = CallerF->getCallingConv();
3046 bool CCMatch = CallerCC == CalleeCC;
3047 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3048 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3050 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3051 if (IsTailCallConvention(CalleeCC) && CCMatch)
3056 // Look for obvious safe cases to perform tail call optimization that do not
3057 // require ABI changes. This is what gcc calls sibcall.
3059 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3060 // emit a special epilogue.
3061 const X86RegisterInfo *RegInfo =
3062 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3063 if (RegInfo->needsStackRealignment(MF))
3066 // Also avoid sibcall optimization if either caller or callee uses struct
3067 // return semantics.
3068 if (isCalleeStructRet || isCallerStructRet)
3071 // An stdcall caller is expected to clean up its arguments; the callee
3072 // isn't going to do that.
3073 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3076 // Do not sibcall optimize vararg calls unless all arguments are passed via
3078 if (isVarArg && !Outs.empty()) {
3080 // Optimizing for varargs on Win64 is unlikely to be safe without
3081 // additional testing.
3082 if (IsCalleeWin64 || IsCallerWin64)
3085 SmallVector<CCValAssign, 16> ArgLocs;
3086 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3087 getTargetMachine(), ArgLocs, *DAG.getContext());
3089 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3090 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3091 if (!ArgLocs[i].isRegLoc())
3095 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3096 // stack. Therefore, if it's not used by the call it is not safe to optimize
3097 // this into a sibcall.
3098 bool Unused = false;
3099 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3106 SmallVector<CCValAssign, 16> RVLocs;
3107 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3108 getTargetMachine(), RVLocs, *DAG.getContext());
3109 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3110 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3111 CCValAssign &VA = RVLocs[i];
3112 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3117 // If the calling conventions do not match, then we'd better make sure the
3118 // results are returned in the same way as what the caller expects.
3120 SmallVector<CCValAssign, 16> RVLocs1;
3121 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3122 getTargetMachine(), RVLocs1, *DAG.getContext());
3123 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3125 SmallVector<CCValAssign, 16> RVLocs2;
3126 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3127 getTargetMachine(), RVLocs2, *DAG.getContext());
3128 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3130 if (RVLocs1.size() != RVLocs2.size())
3132 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3133 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3135 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3137 if (RVLocs1[i].isRegLoc()) {
3138 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3141 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3147 // If the callee takes no arguments then go on to check the results of the
3149 if (!Outs.empty()) {
3150 // Check if stack adjustment is needed. For now, do not do this if any
3151 // argument is passed on the stack.
3152 SmallVector<CCValAssign, 16> ArgLocs;
3153 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3154 getTargetMachine(), ArgLocs, *DAG.getContext());
3156 // Allocate shadow area for Win64
3158 CCInfo.AllocateStack(32, 8);
3160 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3161 if (CCInfo.getNextStackOffset()) {
3162 MachineFunction &MF = DAG.getMachineFunction();
3163 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3166 // Check if the arguments are already laid out in the right way as
3167 // the caller's fixed stack objects.
3168 MachineFrameInfo *MFI = MF.getFrameInfo();
3169 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3170 const X86InstrInfo *TII =
3171 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3172 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3173 CCValAssign &VA = ArgLocs[i];
3174 SDValue Arg = OutVals[i];
3175 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3176 if (VA.getLocInfo() == CCValAssign::Indirect)
3178 if (!VA.isRegLoc()) {
3179 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3186 // If the tailcall address may be in a register, then make sure it's
3187 // possible to register allocate for it. In 32-bit, the call address can
3188 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3189 // callee-saved registers are restored. These happen to be the same
3190 // registers used to pass 'inreg' arguments so watch out for those.
3191 if (!Subtarget->is64Bit() &&
3192 ((!isa<GlobalAddressSDNode>(Callee) &&
3193 !isa<ExternalSymbolSDNode>(Callee)) ||
3194 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3195 unsigned NumInRegs = 0;
3196 // In PIC we need an extra register to formulate the address computation
3198 unsigned MaxInRegs =
3199 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3201 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3202 CCValAssign &VA = ArgLocs[i];
3205 unsigned Reg = VA.getLocReg();
3208 case X86::EAX: case X86::EDX: case X86::ECX:
3209 if (++NumInRegs == MaxInRegs)
3221 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3222 const TargetLibraryInfo *libInfo) const {
3223 return X86::createFastISel(funcInfo, libInfo);
3226 //===----------------------------------------------------------------------===//
3227 // Other Lowering Hooks
3228 //===----------------------------------------------------------------------===//
3230 static bool MayFoldLoad(SDValue Op) {
3231 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3234 static bool MayFoldIntoStore(SDValue Op) {
3235 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3238 static bool isTargetShuffle(unsigned Opcode) {
3240 default: return false;
3241 case X86ISD::PSHUFD:
3242 case X86ISD::PSHUFHW:
3243 case X86ISD::PSHUFLW:
3245 case X86ISD::PALIGNR:
3246 case X86ISD::MOVLHPS:
3247 case X86ISD::MOVLHPD:
3248 case X86ISD::MOVHLPS:
3249 case X86ISD::MOVLPS:
3250 case X86ISD::MOVLPD:
3251 case X86ISD::MOVSHDUP:
3252 case X86ISD::MOVSLDUP:
3253 case X86ISD::MOVDDUP:
3256 case X86ISD::UNPCKL:
3257 case X86ISD::UNPCKH:
3258 case X86ISD::VPERMILP:
3259 case X86ISD::VPERM2X128:
3260 case X86ISD::VPERMI:
3265 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3266 SDValue V1, SelectionDAG &DAG) {
3268 default: llvm_unreachable("Unknown x86 shuffle node");
3269 case X86ISD::MOVSHDUP:
3270 case X86ISD::MOVSLDUP:
3271 case X86ISD::MOVDDUP:
3272 return DAG.getNode(Opc, dl, VT, V1);
3276 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3277 SDValue V1, unsigned TargetMask,
3278 SelectionDAG &DAG) {
3280 default: llvm_unreachable("Unknown x86 shuffle node");
3281 case X86ISD::PSHUFD:
3282 case X86ISD::PSHUFHW:
3283 case X86ISD::PSHUFLW:
3284 case X86ISD::VPERMILP:
3285 case X86ISD::VPERMI:
3286 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3290 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3291 SDValue V1, SDValue V2, unsigned TargetMask,
3292 SelectionDAG &DAG) {
3294 default: llvm_unreachable("Unknown x86 shuffle node");
3295 case X86ISD::PALIGNR:
3297 case X86ISD::VPERM2X128:
3298 return DAG.getNode(Opc, dl, VT, V1, V2,
3299 DAG.getConstant(TargetMask, MVT::i8));
3303 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3304 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3306 default: llvm_unreachable("Unknown x86 shuffle node");
3307 case X86ISD::MOVLHPS:
3308 case X86ISD::MOVLHPD:
3309 case X86ISD::MOVHLPS:
3310 case X86ISD::MOVLPS:
3311 case X86ISD::MOVLPD:
3314 case X86ISD::UNPCKL:
3315 case X86ISD::UNPCKH:
3316 return DAG.getNode(Opc, dl, VT, V1, V2);
3320 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3321 MachineFunction &MF = DAG.getMachineFunction();
3322 const X86RegisterInfo *RegInfo =
3323 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3324 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3325 int ReturnAddrIndex = FuncInfo->getRAIndex();
3327 if (ReturnAddrIndex == 0) {
3328 // Set up a frame object for the return address.
3329 unsigned SlotSize = RegInfo->getSlotSize();
3330 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3333 FuncInfo->setRAIndex(ReturnAddrIndex);
3336 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3339 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3340 bool hasSymbolicDisplacement) {
3341 // Offset should fit into 32 bit immediate field.
3342 if (!isInt<32>(Offset))
3345 // If we don't have a symbolic displacement - we don't have any extra
3347 if (!hasSymbolicDisplacement)
3350 // FIXME: Some tweaks might be needed for medium code model.
3351 if (M != CodeModel::Small && M != CodeModel::Kernel)
3354 // For small code model we assume that latest object is 16MB before end of 31
3355 // bits boundary. We may also accept pretty large negative constants knowing
3356 // that all objects are in the positive half of address space.
3357 if (M == CodeModel::Small && Offset < 16*1024*1024)
3360 // For kernel code model we know that all object resist in the negative half
3361 // of 32bits address space. We may not accept negative offsets, since they may
3362 // be just off and we may accept pretty large positive ones.
3363 if (M == CodeModel::Kernel && Offset > 0)
3369 /// isCalleePop - Determines whether the callee is required to pop its
3370 /// own arguments. Callee pop is necessary to support tail calls.
3371 bool X86::isCalleePop(CallingConv::ID CallingConv,
3372 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3376 switch (CallingConv) {
3379 case CallingConv::X86_StdCall:
3381 case CallingConv::X86_FastCall:
3383 case CallingConv::X86_ThisCall:
3385 case CallingConv::Fast:
3387 case CallingConv::GHC:
3389 case CallingConv::HiPE:
3394 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3395 /// specific condition code, returning the condition code and the LHS/RHS of the
3396 /// comparison to make.
3397 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3398 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3400 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3401 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3402 // X > -1 -> X == 0, jump !sign.
3403 RHS = DAG.getConstant(0, RHS.getValueType());
3404 return X86::COND_NS;
3406 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3407 // X < 0 -> X == 0, jump on sign.
3410 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3412 RHS = DAG.getConstant(0, RHS.getValueType());
3413 return X86::COND_LE;
3417 switch (SetCCOpcode) {
3418 default: llvm_unreachable("Invalid integer condition!");
3419 case ISD::SETEQ: return X86::COND_E;
3420 case ISD::SETGT: return X86::COND_G;
3421 case ISD::SETGE: return X86::COND_GE;
3422 case ISD::SETLT: return X86::COND_L;
3423 case ISD::SETLE: return X86::COND_LE;
3424 case ISD::SETNE: return X86::COND_NE;
3425 case ISD::SETULT: return X86::COND_B;
3426 case ISD::SETUGT: return X86::COND_A;
3427 case ISD::SETULE: return X86::COND_BE;
3428 case ISD::SETUGE: return X86::COND_AE;
3432 // First determine if it is required or is profitable to flip the operands.
3434 // If LHS is a foldable load, but RHS is not, flip the condition.
3435 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3436 !ISD::isNON_EXTLoad(RHS.getNode())) {
3437 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3438 std::swap(LHS, RHS);
3441 switch (SetCCOpcode) {
3447 std::swap(LHS, RHS);
3451 // On a floating point condition, the flags are set as follows:
3453 // 0 | 0 | 0 | X > Y
3454 // 0 | 0 | 1 | X < Y
3455 // 1 | 0 | 0 | X == Y
3456 // 1 | 1 | 1 | unordered
3457 switch (SetCCOpcode) {
3458 default: llvm_unreachable("Condcode should be pre-legalized away");
3460 case ISD::SETEQ: return X86::COND_E;
3461 case ISD::SETOLT: // flipped
3463 case ISD::SETGT: return X86::COND_A;
3464 case ISD::SETOLE: // flipped
3466 case ISD::SETGE: return X86::COND_AE;
3467 case ISD::SETUGT: // flipped
3469 case ISD::SETLT: return X86::COND_B;
3470 case ISD::SETUGE: // flipped
3472 case ISD::SETLE: return X86::COND_BE;
3474 case ISD::SETNE: return X86::COND_NE;
3475 case ISD::SETUO: return X86::COND_P;
3476 case ISD::SETO: return X86::COND_NP;
3478 case ISD::SETUNE: return X86::COND_INVALID;
3482 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3483 /// code. Current x86 isa includes the following FP cmov instructions:
3484 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3485 static bool hasFPCMov(unsigned X86CC) {
3501 /// isFPImmLegal - Returns true if the target can instruction select the
3502 /// specified FP immediate natively. If false, the legalizer will
3503 /// materialize the FP immediate as a load from a constant pool.
3504 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3505 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3506 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3512 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3513 /// the specified range (L, H].
3514 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3515 return (Val < 0) || (Val >= Low && Val < Hi);
3518 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3519 /// specified value.
3520 static bool isUndefOrEqual(int Val, int CmpVal) {
3521 return (Val < 0 || Val == CmpVal);
3524 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3525 /// from position Pos and ending in Pos+Size, falls within the specified
3526 /// sequential range (L, L+Pos]. or is undef.
3527 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3528 unsigned Pos, unsigned Size, int Low) {
3529 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3530 if (!isUndefOrEqual(Mask[i], Low))
3535 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3536 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3537 /// the second operand.
3538 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3539 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3540 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3541 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3542 return (Mask[0] < 2 && Mask[1] < 2);
3546 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3547 /// is suitable for input to PSHUFHW.
3548 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3549 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3552 // Lower quadword copied in order or undef.
3553 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3556 // Upper quadword shuffled.
3557 for (unsigned i = 4; i != 8; ++i)
3558 if (!isUndefOrInRange(Mask[i], 4, 8))
3561 if (VT == MVT::v16i16) {
3562 // Lower quadword copied in order or undef.
3563 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3566 // Upper quadword shuffled.
3567 for (unsigned i = 12; i != 16; ++i)
3568 if (!isUndefOrInRange(Mask[i], 12, 16))
3575 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3576 /// is suitable for input to PSHUFLW.
3577 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3578 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3581 // Upper quadword copied in order.
3582 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3585 // Lower quadword shuffled.
3586 for (unsigned i = 0; i != 4; ++i)
3587 if (!isUndefOrInRange(Mask[i], 0, 4))
3590 if (VT == MVT::v16i16) {
3591 // Upper quadword copied in order.
3592 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3595 // Lower quadword shuffled.
3596 for (unsigned i = 8; i != 12; ++i)
3597 if (!isUndefOrInRange(Mask[i], 8, 12))
3604 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3605 /// is suitable for input to PALIGNR.
3606 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3607 const X86Subtarget *Subtarget) {
3608 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3609 (VT.is256BitVector() && !Subtarget->hasInt256()))
3612 unsigned NumElts = VT.getVectorNumElements();
3613 unsigned NumLanes = VT.is512BitVector() ? 1: VT.getSizeInBits()/128;
3614 unsigned NumLaneElts = NumElts/NumLanes;
3616 // Do not handle 64-bit element shuffles with palignr.
3617 if (NumLaneElts == 2)
3620 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3622 for (i = 0; i != NumLaneElts; ++i) {
3627 // Lane is all undef, go to next lane
3628 if (i == NumLaneElts)
3631 int Start = Mask[i+l];
3633 // Make sure its in this lane in one of the sources
3634 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3635 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3638 // If not lane 0, then we must match lane 0
3639 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3642 // Correct second source to be contiguous with first source
3643 if (Start >= (int)NumElts)
3644 Start -= NumElts - NumLaneElts;
3646 // Make sure we're shifting in the right direction.
3647 if (Start <= (int)(i+l))
3652 // Check the rest of the elements to see if they are consecutive.
3653 for (++i; i != NumLaneElts; ++i) {
3654 int Idx = Mask[i+l];
3656 // Make sure its in this lane
3657 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3658 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3661 // If not lane 0, then we must match lane 0
3662 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3665 if (Idx >= (int)NumElts)
3666 Idx -= NumElts - NumLaneElts;
3668 if (!isUndefOrEqual(Idx, Start+i))
3677 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3678 /// the two vector operands have swapped position.
3679 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3680 unsigned NumElems) {
3681 for (unsigned i = 0; i != NumElems; ++i) {
3685 else if (idx < (int)NumElems)
3686 Mask[i] = idx + NumElems;
3688 Mask[i] = idx - NumElems;
3692 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3693 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3694 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3695 /// reverse of what x86 shuffles want.
3696 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3698 unsigned NumElems = VT.getVectorNumElements();
3699 unsigned NumLanes = VT.getSizeInBits()/128;
3700 unsigned NumLaneElems = NumElems/NumLanes;
3702 if (NumLaneElems != 2 && NumLaneElems != 4)
3705 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3706 bool symetricMaskRequired =
3707 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3709 // VSHUFPSY divides the resulting vector into 4 chunks.
3710 // The sources are also splitted into 4 chunks, and each destination
3711 // chunk must come from a different source chunk.
3713 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3714 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3716 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3717 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3719 // VSHUFPDY divides the resulting vector into 4 chunks.
3720 // The sources are also splitted into 4 chunks, and each destination
3721 // chunk must come from a different source chunk.
3723 // SRC1 => X3 X2 X1 X0
3724 // SRC2 => Y3 Y2 Y1 Y0
3726 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3728 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3729 unsigned HalfLaneElems = NumLaneElems/2;
3730 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3731 for (unsigned i = 0; i != NumLaneElems; ++i) {
3732 int Idx = Mask[i+l];
3733 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3734 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3736 // For VSHUFPSY, the mask of the second half must be the same as the
3737 // first but with the appropriate offsets. This works in the same way as
3738 // VPERMILPS works with masks.
3739 if (!symetricMaskRequired || Idx < 0)
3741 if (MaskVal[i] < 0) {
3742 MaskVal[i] = Idx - l;
3745 if ((signed)(Idx - l) != MaskVal[i])
3753 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3754 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3755 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3756 if (!VT.is128BitVector())
3759 unsigned NumElems = VT.getVectorNumElements();
3764 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3765 return isUndefOrEqual(Mask[0], 6) &&
3766 isUndefOrEqual(Mask[1], 7) &&
3767 isUndefOrEqual(Mask[2], 2) &&
3768 isUndefOrEqual(Mask[3], 3);
3771 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3772 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3774 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3775 if (!VT.is128BitVector())
3778 unsigned NumElems = VT.getVectorNumElements();
3783 return isUndefOrEqual(Mask[0], 2) &&
3784 isUndefOrEqual(Mask[1], 3) &&
3785 isUndefOrEqual(Mask[2], 2) &&
3786 isUndefOrEqual(Mask[3], 3);
3789 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3790 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3791 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
3792 if (!VT.is128BitVector())
3795 unsigned NumElems = VT.getVectorNumElements();
3797 if (NumElems != 2 && NumElems != 4)
3800 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3801 if (!isUndefOrEqual(Mask[i], i + NumElems))
3804 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3805 if (!isUndefOrEqual(Mask[i], i))
3811 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3812 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3813 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
3814 if (!VT.is128BitVector())
3817 unsigned NumElems = VT.getVectorNumElements();
3819 if (NumElems != 2 && NumElems != 4)
3822 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3823 if (!isUndefOrEqual(Mask[i], i))
3826 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3827 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3834 // Some special combinations that can be optimized.
3837 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3838 SelectionDAG &DAG) {
3839 MVT VT = SVOp->getSimpleValueType(0);
3842 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3845 ArrayRef<int> Mask = SVOp->getMask();
3847 // These are the special masks that may be optimized.
3848 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3849 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3850 bool MatchEvenMask = true;
3851 bool MatchOddMask = true;
3852 for (int i=0; i<8; ++i) {
3853 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3854 MatchEvenMask = false;
3855 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3856 MatchOddMask = false;
3859 if (!MatchEvenMask && !MatchOddMask)
3862 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3864 SDValue Op0 = SVOp->getOperand(0);
3865 SDValue Op1 = SVOp->getOperand(1);
3867 if (MatchEvenMask) {
3868 // Shift the second operand right to 32 bits.
3869 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3870 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3872 // Shift the first operand left to 32 bits.
3873 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3874 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3876 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3877 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3880 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3881 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3882 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
3883 bool HasInt256, bool V2IsSplat = false) {
3885 assert(VT.getSizeInBits() >= 128 &&
3886 "Unsupported vector type for unpckl");
3888 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3890 unsigned NumOf256BitLanes;
3891 unsigned NumElts = VT.getVectorNumElements();
3892 if (VT.is256BitVector()) {
3893 if (NumElts != 4 && NumElts != 8 &&
3894 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3897 NumOf256BitLanes = 1;
3898 } else if (VT.is512BitVector()) {
3899 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3900 "Unsupported vector type for unpckh");
3902 NumOf256BitLanes = 2;
3905 NumOf256BitLanes = 1;
3908 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3909 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3911 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3912 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3913 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
3914 int BitI = Mask[l256*NumEltsInStride+l+i];
3915 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3916 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3918 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3920 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3928 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3929 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3930 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
3931 bool HasInt256, bool V2IsSplat = false) {
3932 assert(VT.getSizeInBits() >= 128 &&
3933 "Unsupported vector type for unpckh");
3935 // AVX defines UNPCK* to operate independently on 128-bit lanes.
3937 unsigned NumOf256BitLanes;
3938 unsigned NumElts = VT.getVectorNumElements();
3939 if (VT.is256BitVector()) {
3940 if (NumElts != 4 && NumElts != 8 &&
3941 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3944 NumOf256BitLanes = 1;
3945 } else if (VT.is512BitVector()) {
3946 assert(VT.getScalarType().getSizeInBits() >= 32 &&
3947 "Unsupported vector type for unpckh");
3949 NumOf256BitLanes = 2;
3952 NumOf256BitLanes = 1;
3955 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
3956 unsigned NumLaneElts = NumEltsInStride/NumLanes;
3958 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
3959 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
3960 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
3961 int BitI = Mask[l256*NumEltsInStride+l+i];
3962 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
3963 if (!isUndefOrEqual(BitI, j+l256*NumElts))
3965 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
3967 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
3975 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3976 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3978 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3979 unsigned NumElts = VT.getVectorNumElements();
3980 bool Is256BitVec = VT.is256BitVector();
3982 if (VT.is512BitVector())
3984 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3985 "Unsupported vector type for unpckh");
3987 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3988 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3991 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3992 // FIXME: Need a better way to get rid of this, there's no latency difference
3993 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3994 // the former later. We should also remove the "_undef" special mask.
3995 if (NumElts == 4 && Is256BitVec)
3998 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3999 // independently on 128-bit lanes.
4000 unsigned NumLanes = VT.getSizeInBits()/128;
4001 unsigned NumLaneElts = NumElts/NumLanes;
4003 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4004 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4005 int BitI = Mask[l+i];
4006 int BitI1 = Mask[l+i+1];
4008 if (!isUndefOrEqual(BitI, j))
4010 if (!isUndefOrEqual(BitI1, j))
4018 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4019 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4021 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4022 unsigned NumElts = VT.getVectorNumElements();
4024 if (VT.is512BitVector())
4027 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4028 "Unsupported vector type for unpckh");
4030 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4031 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4034 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4035 // independently on 128-bit lanes.
4036 unsigned NumLanes = VT.getSizeInBits()/128;
4037 unsigned NumLaneElts = NumElts/NumLanes;
4039 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4040 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4041 int BitI = Mask[l+i];
4042 int BitI1 = Mask[l+i+1];
4043 if (!isUndefOrEqual(BitI, j))
4045 if (!isUndefOrEqual(BitI1, j))
4052 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4053 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4054 /// MOVSD, and MOVD, i.e. setting the lowest element.
4055 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4056 if (VT.getVectorElementType().getSizeInBits() < 32)
4058 if (!VT.is128BitVector())
4061 unsigned NumElts = VT.getVectorNumElements();
4063 if (!isUndefOrEqual(Mask[0], NumElts))
4066 for (unsigned i = 1; i != NumElts; ++i)
4067 if (!isUndefOrEqual(Mask[i], i))
4073 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4074 /// as permutations between 128-bit chunks or halves. As an example: this
4076 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4077 /// The first half comes from the second half of V1 and the second half from the
4078 /// the second half of V2.
4079 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4080 if (!HasFp256 || !VT.is256BitVector())
4083 // The shuffle result is divided into half A and half B. In total the two
4084 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4085 // B must come from C, D, E or F.
4086 unsigned HalfSize = VT.getVectorNumElements()/2;
4087 bool MatchA = false, MatchB = false;
4089 // Check if A comes from one of C, D, E, F.
4090 for (unsigned Half = 0; Half != 4; ++Half) {
4091 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4097 // Check if B comes from one of C, D, E, F.
4098 for (unsigned Half = 0; Half != 4; ++Half) {
4099 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4105 return MatchA && MatchB;
4108 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4109 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4110 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4111 MVT VT = SVOp->getSimpleValueType(0);
4113 unsigned HalfSize = VT.getVectorNumElements()/2;
4115 unsigned FstHalf = 0, SndHalf = 0;
4116 for (unsigned i = 0; i < HalfSize; ++i) {
4117 if (SVOp->getMaskElt(i) > 0) {
4118 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4122 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4123 if (SVOp->getMaskElt(i) > 0) {
4124 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4129 return (FstHalf | (SndHalf << 4));
4132 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4133 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4134 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4138 unsigned NumElts = VT.getVectorNumElements();
4140 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4141 for (unsigned i = 0; i != NumElts; ++i) {
4144 Imm8 |= Mask[i] << (i*2);
4149 unsigned LaneSize = 4;
4150 SmallVector<int, 4> MaskVal(LaneSize, -1);
4152 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4153 for (unsigned i = 0; i != LaneSize; ++i) {
4154 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4158 if (MaskVal[i] < 0) {
4159 MaskVal[i] = Mask[i+l] - l;
4160 Imm8 |= MaskVal[i] << (i*2);
4163 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4170 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4171 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4172 /// Note that VPERMIL mask matching is different depending whether theunderlying
4173 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4174 /// to the same elements of the low, but to the higher half of the source.
4175 /// In VPERMILPD the two lanes could be shuffled independently of each other
4176 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4177 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4178 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4179 if (VT.getSizeInBits() < 256 || EltSize < 32)
4181 bool symetricMaskRequired = (EltSize == 32);
4182 unsigned NumElts = VT.getVectorNumElements();
4184 unsigned NumLanes = VT.getSizeInBits()/128;
4185 unsigned LaneSize = NumElts/NumLanes;
4186 // 2 or 4 elements in one lane
4188 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4189 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4190 for (unsigned i = 0; i != LaneSize; ++i) {
4191 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4193 if (symetricMaskRequired) {
4194 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4195 ExpectedMaskVal[i] = Mask[i+l] - l;
4198 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4206 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4207 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4208 /// element of vector 2 and the other elements to come from vector 1 in order.
4209 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4210 bool V2IsSplat = false, bool V2IsUndef = false) {
4211 if (!VT.is128BitVector())
4214 unsigned NumOps = VT.getVectorNumElements();
4215 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4218 if (!isUndefOrEqual(Mask[0], 0))
4221 for (unsigned i = 1; i != NumOps; ++i)
4222 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4223 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4224 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4230 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4231 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4232 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4233 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4234 const X86Subtarget *Subtarget) {
4235 if (!Subtarget->hasSSE3())
4238 unsigned NumElems = VT.getVectorNumElements();
4240 if ((VT.is128BitVector() && NumElems != 4) ||
4241 (VT.is256BitVector() && NumElems != 8) ||
4242 (VT.is512BitVector() && NumElems != 16))
4245 // "i+1" is the value the indexed mask element must have
4246 for (unsigned i = 0; i != NumElems; i += 2)
4247 if (!isUndefOrEqual(Mask[i], i+1) ||
4248 !isUndefOrEqual(Mask[i+1], i+1))
4254 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4255 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4256 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4257 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4258 const X86Subtarget *Subtarget) {
4259 if (!Subtarget->hasSSE3())
4262 unsigned NumElems = VT.getVectorNumElements();
4264 if ((VT.is128BitVector() && NumElems != 4) ||
4265 (VT.is256BitVector() && NumElems != 8) ||
4266 (VT.is512BitVector() && NumElems != 16))
4269 // "i" is the value the indexed mask element must have
4270 for (unsigned i = 0; i != NumElems; i += 2)
4271 if (!isUndefOrEqual(Mask[i], i) ||
4272 !isUndefOrEqual(Mask[i+1], i))
4278 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4279 /// specifies a shuffle of elements that is suitable for input to 256-bit
4280 /// version of MOVDDUP.
4281 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4282 if (!HasFp256 || !VT.is256BitVector())
4285 unsigned NumElts = VT.getVectorNumElements();
4289 for (unsigned i = 0; i != NumElts/2; ++i)
4290 if (!isUndefOrEqual(Mask[i], 0))
4292 for (unsigned i = NumElts/2; i != NumElts; ++i)
4293 if (!isUndefOrEqual(Mask[i], NumElts/2))
4298 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4299 /// specifies a shuffle of elements that is suitable for input to 128-bit
4300 /// version of MOVDDUP.
4301 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4302 if (!VT.is128BitVector())
4305 unsigned e = VT.getVectorNumElements() / 2;
4306 for (unsigned i = 0; i != e; ++i)
4307 if (!isUndefOrEqual(Mask[i], i))
4309 for (unsigned i = 0; i != e; ++i)
4310 if (!isUndefOrEqual(Mask[e+i], i))
4315 /// isVEXTRACTIndex - Return true if the specified
4316 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4317 /// suitable for instruction that extract 128 or 256 bit vectors
4318 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4319 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4320 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4323 // The index should be aligned on a vecWidth-bit boundary.
4325 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4327 MVT VT = N->getSimpleValueType(0);
4328 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4329 bool Result = (Index * ElSize) % vecWidth == 0;
4334 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4335 /// operand specifies a subvector insert that is suitable for input to
4336 /// insertion of 128 or 256-bit subvectors
4337 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4338 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4339 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4341 // The index should be aligned on a vecWidth-bit boundary.
4343 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4345 MVT VT = N->getSimpleValueType(0);
4346 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4347 bool Result = (Index * ElSize) % vecWidth == 0;
4352 bool X86::isVINSERT128Index(SDNode *N) {
4353 return isVINSERTIndex(N, 128);
4356 bool X86::isVINSERT256Index(SDNode *N) {
4357 return isVINSERTIndex(N, 256);
4360 bool X86::isVEXTRACT128Index(SDNode *N) {
4361 return isVEXTRACTIndex(N, 128);
4364 bool X86::isVEXTRACT256Index(SDNode *N) {
4365 return isVEXTRACTIndex(N, 256);
4368 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4369 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4370 /// Handles 128-bit and 256-bit.
4371 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4372 MVT VT = N->getSimpleValueType(0);
4374 assert((VT.getSizeInBits() >= 128) &&
4375 "Unsupported vector type for PSHUF/SHUFP");
4377 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4378 // independently on 128-bit lanes.
4379 unsigned NumElts = VT.getVectorNumElements();
4380 unsigned NumLanes = VT.getSizeInBits()/128;
4381 unsigned NumLaneElts = NumElts/NumLanes;
4383 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4384 "Only supports 2, 4 or 8 elements per lane");
4386 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4388 for (unsigned i = 0; i != NumElts; ++i) {
4389 int Elt = N->getMaskElt(i);
4390 if (Elt < 0) continue;
4391 Elt &= NumLaneElts - 1;
4392 unsigned ShAmt = (i << Shift) % 8;
4393 Mask |= Elt << ShAmt;
4399 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4400 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4401 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4402 MVT VT = N->getSimpleValueType(0);
4404 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4405 "Unsupported vector type for PSHUFHW");
4407 unsigned NumElts = VT.getVectorNumElements();
4410 for (unsigned l = 0; l != NumElts; l += 8) {
4411 // 8 nodes per lane, but we only care about the last 4.
4412 for (unsigned i = 0; i < 4; ++i) {
4413 int Elt = N->getMaskElt(l+i+4);
4414 if (Elt < 0) continue;
4415 Elt &= 0x3; // only 2-bits.
4416 Mask |= Elt << (i * 2);
4423 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4424 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4425 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4426 MVT VT = N->getSimpleValueType(0);
4428 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4429 "Unsupported vector type for PSHUFHW");
4431 unsigned NumElts = VT.getVectorNumElements();
4434 for (unsigned l = 0; l != NumElts; l += 8) {
4435 // 8 nodes per lane, but we only care about the first 4.
4436 for (unsigned i = 0; i < 4; ++i) {
4437 int Elt = N->getMaskElt(l+i);
4438 if (Elt < 0) continue;
4439 Elt &= 0x3; // only 2-bits
4440 Mask |= Elt << (i * 2);
4447 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4448 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4449 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4450 MVT VT = SVOp->getSimpleValueType(0);
4451 unsigned EltSize = VT.is512BitVector() ? 1 :
4452 VT.getVectorElementType().getSizeInBits() >> 3;
4454 unsigned NumElts = VT.getVectorNumElements();
4455 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4456 unsigned NumLaneElts = NumElts/NumLanes;
4460 for (i = 0; i != NumElts; ++i) {
4461 Val = SVOp->getMaskElt(i);
4465 if (Val >= (int)NumElts)
4466 Val -= NumElts - NumLaneElts;
4468 assert(Val - i > 0 && "PALIGNR imm should be positive");
4469 return (Val - i) * EltSize;
4472 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4473 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4474 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4475 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4478 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4480 MVT VecVT = N->getOperand(0).getSimpleValueType();
4481 MVT ElVT = VecVT.getVectorElementType();
4483 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4484 return Index / NumElemsPerChunk;
4487 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4488 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4489 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4490 llvm_unreachable("Illegal insert subvector for VINSERT");
4493 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4495 MVT VecVT = N->getSimpleValueType(0);
4496 MVT ElVT = VecVT.getVectorElementType();
4498 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4499 return Index / NumElemsPerChunk;
4502 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4503 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4504 /// and VINSERTI128 instructions.
4505 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4506 return getExtractVEXTRACTImmediate(N, 128);
4509 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4510 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4511 /// and VINSERTI64x4 instructions.
4512 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4513 return getExtractVEXTRACTImmediate(N, 256);
4516 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4517 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4518 /// and VINSERTI128 instructions.
4519 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4520 return getInsertVINSERTImmediate(N, 128);
4523 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4524 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4525 /// and VINSERTI64x4 instructions.
4526 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4527 return getInsertVINSERTImmediate(N, 256);
4530 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4532 bool X86::isZeroNode(SDValue Elt) {
4533 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4534 return CN->isNullValue();
4535 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4536 return CFP->getValueAPF().isPosZero();
4540 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4541 /// their permute mask.
4542 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4543 SelectionDAG &DAG) {
4544 MVT VT = SVOp->getSimpleValueType(0);
4545 unsigned NumElems = VT.getVectorNumElements();
4546 SmallVector<int, 8> MaskVec;
4548 for (unsigned i = 0; i != NumElems; ++i) {
4549 int Idx = SVOp->getMaskElt(i);
4551 if (Idx < (int)NumElems)
4556 MaskVec.push_back(Idx);
4558 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4559 SVOp->getOperand(0), &MaskVec[0]);
4562 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4563 /// match movhlps. The lower half elements should come from upper half of
4564 /// V1 (and in order), and the upper half elements should come from the upper
4565 /// half of V2 (and in order).
4566 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4567 if (!VT.is128BitVector())
4569 if (VT.getVectorNumElements() != 4)
4571 for (unsigned i = 0, e = 2; i != e; ++i)
4572 if (!isUndefOrEqual(Mask[i], i+2))
4574 for (unsigned i = 2; i != 4; ++i)
4575 if (!isUndefOrEqual(Mask[i], i+4))
4580 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4581 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4583 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4584 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4586 N = N->getOperand(0).getNode();
4587 if (!ISD::isNON_EXTLoad(N))
4590 *LD = cast<LoadSDNode>(N);
4594 // Test whether the given value is a vector value which will be legalized
4596 static bool WillBeConstantPoolLoad(SDNode *N) {
4597 if (N->getOpcode() != ISD::BUILD_VECTOR)
4600 // Check for any non-constant elements.
4601 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4602 switch (N->getOperand(i).getNode()->getOpcode()) {
4604 case ISD::ConstantFP:
4611 // Vectors of all-zeros and all-ones are materialized with special
4612 // instructions rather than being loaded.
4613 return !ISD::isBuildVectorAllZeros(N) &&
4614 !ISD::isBuildVectorAllOnes(N);
4617 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4618 /// match movlp{s|d}. The lower half elements should come from lower half of
4619 /// V1 (and in order), and the upper half elements should come from the upper
4620 /// half of V2 (and in order). And since V1 will become the source of the
4621 /// MOVLP, it must be either a vector load or a scalar load to vector.
4622 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4623 ArrayRef<int> Mask, MVT VT) {
4624 if (!VT.is128BitVector())
4627 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4629 // Is V2 is a vector load, don't do this transformation. We will try to use
4630 // load folding shufps op.
4631 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4634 unsigned NumElems = VT.getVectorNumElements();
4636 if (NumElems != 2 && NumElems != 4)
4638 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4639 if (!isUndefOrEqual(Mask[i], i))
4641 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4642 if (!isUndefOrEqual(Mask[i], i+NumElems))
4647 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4649 static bool isSplatVector(SDNode *N) {
4650 if (N->getOpcode() != ISD::BUILD_VECTOR)
4653 SDValue SplatValue = N->getOperand(0);
4654 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4655 if (N->getOperand(i) != SplatValue)
4660 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4661 /// to an zero vector.
4662 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4663 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4664 SDValue V1 = N->getOperand(0);
4665 SDValue V2 = N->getOperand(1);
4666 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4667 for (unsigned i = 0; i != NumElems; ++i) {
4668 int Idx = N->getMaskElt(i);
4669 if (Idx >= (int)NumElems) {
4670 unsigned Opc = V2.getOpcode();
4671 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4673 if (Opc != ISD::BUILD_VECTOR ||
4674 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4676 } else if (Idx >= 0) {
4677 unsigned Opc = V1.getOpcode();
4678 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4680 if (Opc != ISD::BUILD_VECTOR ||
4681 !X86::isZeroNode(V1.getOperand(Idx)))
4688 /// getZeroVector - Returns a vector of specified type with all zero elements.
4690 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4691 SelectionDAG &DAG, SDLoc dl) {
4692 assert(VT.isVector() && "Expected a vector type");
4694 // Always build SSE zero vectors as <4 x i32> bitcasted
4695 // to their dest type. This ensures they get CSE'd.
4697 if (VT.is128BitVector()) { // SSE
4698 if (Subtarget->hasSSE2()) { // SSE2
4699 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4700 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4702 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4703 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4705 } else if (VT.is256BitVector()) { // AVX
4706 if (Subtarget->hasInt256()) { // AVX2
4707 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4708 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4709 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4710 array_lengthof(Ops));
4712 // 256-bit logic and arithmetic instructions in AVX are all
4713 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4714 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4715 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4716 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4717 array_lengthof(Ops));
4719 } else if (VT.is512BitVector()) { // AVX-512
4720 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4721 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4722 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4723 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops, 16);
4725 llvm_unreachable("Unexpected vector type");
4727 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4730 /// getOnesVector - Returns a vector of specified type with all bits set.
4731 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4732 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4733 /// Then bitcast to their original type, ensuring they get CSE'd.
4734 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4736 assert(VT.isVector() && "Expected a vector type");
4738 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4740 if (VT.is256BitVector()) {
4741 if (HasInt256) { // AVX2
4742 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4743 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4744 array_lengthof(Ops));
4746 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4747 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4749 } else if (VT.is128BitVector()) {
4750 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4752 llvm_unreachable("Unexpected vector type");
4754 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4757 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4758 /// that point to V2 points to its first element.
4759 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4760 for (unsigned i = 0; i != NumElems; ++i) {
4761 if (Mask[i] > (int)NumElems) {
4767 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4768 /// operation of specified width.
4769 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4771 unsigned NumElems = VT.getVectorNumElements();
4772 SmallVector<int, 8> Mask;
4773 Mask.push_back(NumElems);
4774 for (unsigned i = 1; i != NumElems; ++i)
4776 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4779 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4780 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4782 unsigned NumElems = VT.getVectorNumElements();
4783 SmallVector<int, 8> Mask;
4784 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4786 Mask.push_back(i + NumElems);
4788 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4791 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4792 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4794 unsigned NumElems = VT.getVectorNumElements();
4795 SmallVector<int, 8> Mask;
4796 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4797 Mask.push_back(i + Half);
4798 Mask.push_back(i + NumElems + Half);
4800 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4803 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4804 // a generic shuffle instruction because the target has no such instructions.
4805 // Generate shuffles which repeat i16 and i8 several times until they can be
4806 // represented by v4f32 and then be manipulated by target suported shuffles.
4807 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4808 MVT VT = V.getSimpleValueType();
4809 int NumElems = VT.getVectorNumElements();
4812 while (NumElems > 4) {
4813 if (EltNo < NumElems/2) {
4814 V = getUnpackl(DAG, dl, VT, V, V);
4816 V = getUnpackh(DAG, dl, VT, V, V);
4817 EltNo -= NumElems/2;
4824 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4825 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4826 MVT VT = V.getSimpleValueType();
4829 if (VT.is128BitVector()) {
4830 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4831 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4832 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4834 } else if (VT.is256BitVector()) {
4835 // To use VPERMILPS to splat scalars, the second half of indicies must
4836 // refer to the higher part, which is a duplication of the lower one,
4837 // because VPERMILPS can only handle in-lane permutations.
4838 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4839 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4841 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4842 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4845 llvm_unreachable("Vector size not supported");
4847 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4850 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4851 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4852 MVT SrcVT = SV->getSimpleValueType(0);
4853 SDValue V1 = SV->getOperand(0);
4856 int EltNo = SV->getSplatIndex();
4857 int NumElems = SrcVT.getVectorNumElements();
4858 bool Is256BitVec = SrcVT.is256BitVector();
4860 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4861 "Unknown how to promote splat for type");
4863 // Extract the 128-bit part containing the splat element and update
4864 // the splat element index when it refers to the higher register.
4866 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4867 if (EltNo >= NumElems/2)
4868 EltNo -= NumElems/2;
4871 // All i16 and i8 vector types can't be used directly by a generic shuffle
4872 // instruction because the target has no such instruction. Generate shuffles
4873 // which repeat i16 and i8 several times until they fit in i32, and then can
4874 // be manipulated by target suported shuffles.
4875 MVT EltVT = SrcVT.getVectorElementType();
4876 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4877 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4879 // Recreate the 256-bit vector and place the same 128-bit vector
4880 // into the low and high part. This is necessary because we want
4881 // to use VPERM* to shuffle the vectors
4883 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4886 return getLegalSplat(DAG, V1, EltNo);
4889 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4890 /// vector of zero or undef vector. This produces a shuffle where the low
4891 /// element of V2 is swizzled into the zero/undef vector, landing at element
4892 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4893 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4895 const X86Subtarget *Subtarget,
4896 SelectionDAG &DAG) {
4897 MVT VT = V2.getSimpleValueType();
4899 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4900 unsigned NumElems = VT.getVectorNumElements();
4901 SmallVector<int, 16> MaskVec;
4902 for (unsigned i = 0; i != NumElems; ++i)
4903 // If this is the insertion idx, put the low elt of V2 here.
4904 MaskVec.push_back(i == Idx ? NumElems : i);
4905 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4908 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4909 /// target specific opcode. Returns true if the Mask could be calculated.
4910 /// Sets IsUnary to true if only uses one source.
4911 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4912 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4913 unsigned NumElems = VT.getVectorNumElements();
4917 switch(N->getOpcode()) {
4919 ImmN = N->getOperand(N->getNumOperands()-1);
4920 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4922 case X86ISD::UNPCKH:
4923 DecodeUNPCKHMask(VT, Mask);
4925 case X86ISD::UNPCKL:
4926 DecodeUNPCKLMask(VT, Mask);
4928 case X86ISD::MOVHLPS:
4929 DecodeMOVHLPSMask(NumElems, Mask);
4931 case X86ISD::MOVLHPS:
4932 DecodeMOVLHPSMask(NumElems, Mask);
4934 case X86ISD::PALIGNR:
4935 ImmN = N->getOperand(N->getNumOperands()-1);
4936 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4938 case X86ISD::PSHUFD:
4939 case X86ISD::VPERMILP:
4940 ImmN = N->getOperand(N->getNumOperands()-1);
4941 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4944 case X86ISD::PSHUFHW:
4945 ImmN = N->getOperand(N->getNumOperands()-1);
4946 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4949 case X86ISD::PSHUFLW:
4950 ImmN = N->getOperand(N->getNumOperands()-1);
4951 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4954 case X86ISD::VPERMI:
4955 ImmN = N->getOperand(N->getNumOperands()-1);
4956 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4960 case X86ISD::MOVSD: {
4961 // The index 0 always comes from the first element of the second source,
4962 // this is why MOVSS and MOVSD are used in the first place. The other
4963 // elements come from the other positions of the first source vector
4964 Mask.push_back(NumElems);
4965 for (unsigned i = 1; i != NumElems; ++i) {
4970 case X86ISD::VPERM2X128:
4971 ImmN = N->getOperand(N->getNumOperands()-1);
4972 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4973 if (Mask.empty()) return false;
4975 case X86ISD::MOVDDUP:
4976 case X86ISD::MOVLHPD:
4977 case X86ISD::MOVLPD:
4978 case X86ISD::MOVLPS:
4979 case X86ISD::MOVSHDUP:
4980 case X86ISD::MOVSLDUP:
4981 // Not yet implemented
4983 default: llvm_unreachable("unknown target shuffle node");
4989 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4990 /// element of the result of the vector shuffle.
4991 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4994 return SDValue(); // Limit search depth.
4996 SDValue V = SDValue(N, 0);
4997 EVT VT = V.getValueType();
4998 unsigned Opcode = V.getOpcode();
5000 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5001 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5002 int Elt = SV->getMaskElt(Index);
5005 return DAG.getUNDEF(VT.getVectorElementType());
5007 unsigned NumElems = VT.getVectorNumElements();
5008 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5009 : SV->getOperand(1);
5010 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5013 // Recurse into target specific vector shuffles to find scalars.
5014 if (isTargetShuffle(Opcode)) {
5015 MVT ShufVT = V.getSimpleValueType();
5016 unsigned NumElems = ShufVT.getVectorNumElements();
5017 SmallVector<int, 16> ShuffleMask;
5020 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5023 int Elt = ShuffleMask[Index];
5025 return DAG.getUNDEF(ShufVT.getVectorElementType());
5027 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5029 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5033 // Actual nodes that may contain scalar elements
5034 if (Opcode == ISD::BITCAST) {
5035 V = V.getOperand(0);
5036 EVT SrcVT = V.getValueType();
5037 unsigned NumElems = VT.getVectorNumElements();
5039 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5043 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5044 return (Index == 0) ? V.getOperand(0)
5045 : DAG.getUNDEF(VT.getVectorElementType());
5047 if (V.getOpcode() == ISD::BUILD_VECTOR)
5048 return V.getOperand(Index);
5053 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5054 /// shuffle operation which come from a consecutively from a zero. The
5055 /// search can start in two different directions, from left or right.
5056 /// We count undefs as zeros until PreferredNum is reached.
5057 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5058 unsigned NumElems, bool ZerosFromLeft,
5060 unsigned PreferredNum = -1U) {
5061 unsigned NumZeros = 0;
5062 for (unsigned i = 0; i != NumElems; ++i) {
5063 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5064 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5068 if (X86::isZeroNode(Elt))
5070 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5071 NumZeros = std::min(NumZeros + 1, PreferredNum);
5079 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5080 /// correspond consecutively to elements from one of the vector operands,
5081 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5083 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5084 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5085 unsigned NumElems, unsigned &OpNum) {
5086 bool SeenV1 = false;
5087 bool SeenV2 = false;
5089 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5090 int Idx = SVOp->getMaskElt(i);
5091 // Ignore undef indicies
5095 if (Idx < (int)NumElems)
5100 // Only accept consecutive elements from the same vector
5101 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5105 OpNum = SeenV1 ? 0 : 1;
5109 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5110 /// logical left shift of a vector.
5111 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5112 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5114 SVOp->getSimpleValueType(0).getVectorNumElements();
5115 unsigned NumZeros = getNumOfConsecutiveZeros(
5116 SVOp, NumElems, false /* check zeros from right */, DAG,
5117 SVOp->getMaskElt(0));
5123 // Considering the elements in the mask that are not consecutive zeros,
5124 // check if they consecutively come from only one of the source vectors.
5126 // V1 = {X, A, B, C} 0
5128 // vector_shuffle V1, V2 <1, 2, 3, X>
5130 if (!isShuffleMaskConsecutive(SVOp,
5131 0, // Mask Start Index
5132 NumElems-NumZeros, // Mask End Index(exclusive)
5133 NumZeros, // Where to start looking in the src vector
5134 NumElems, // Number of elements in vector
5135 OpSrc)) // Which source operand ?
5140 ShVal = SVOp->getOperand(OpSrc);
5144 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5145 /// logical left shift of a vector.
5146 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5147 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5149 SVOp->getSimpleValueType(0).getVectorNumElements();
5150 unsigned NumZeros = getNumOfConsecutiveZeros(
5151 SVOp, NumElems, true /* check zeros from left */, DAG,
5152 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5158 // Considering the elements in the mask that are not consecutive zeros,
5159 // check if they consecutively come from only one of the source vectors.
5161 // 0 { A, B, X, X } = V2
5163 // vector_shuffle V1, V2 <X, X, 4, 5>
5165 if (!isShuffleMaskConsecutive(SVOp,
5166 NumZeros, // Mask Start Index
5167 NumElems, // Mask End Index(exclusive)
5168 0, // Where to start looking in the src vector
5169 NumElems, // Number of elements in vector
5170 OpSrc)) // Which source operand ?
5175 ShVal = SVOp->getOperand(OpSrc);
5179 /// isVectorShift - Returns true if the shuffle can be implemented as a
5180 /// logical left or right shift of a vector.
5181 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5182 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5183 // Although the logic below support any bitwidth size, there are no
5184 // shift instructions which handle more than 128-bit vectors.
5185 if (!SVOp->getSimpleValueType(0).is128BitVector())
5188 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5189 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5195 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5197 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5198 unsigned NumNonZero, unsigned NumZero,
5200 const X86Subtarget* Subtarget,
5201 const TargetLowering &TLI) {
5208 for (unsigned i = 0; i < 16; ++i) {
5209 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5210 if (ThisIsNonZero && First) {
5212 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5214 V = DAG.getUNDEF(MVT::v8i16);
5219 SDValue ThisElt(0, 0), LastElt(0, 0);
5220 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5221 if (LastIsNonZero) {
5222 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5223 MVT::i16, Op.getOperand(i-1));
5225 if (ThisIsNonZero) {
5226 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5227 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5228 ThisElt, DAG.getConstant(8, MVT::i8));
5230 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5234 if (ThisElt.getNode())
5235 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5236 DAG.getIntPtrConstant(i/2));
5240 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5243 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5245 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5246 unsigned NumNonZero, unsigned NumZero,
5248 const X86Subtarget* Subtarget,
5249 const TargetLowering &TLI) {
5256 for (unsigned i = 0; i < 8; ++i) {
5257 bool isNonZero = (NonZeros & (1 << i)) != 0;
5261 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5263 V = DAG.getUNDEF(MVT::v8i16);
5266 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5267 MVT::v8i16, V, Op.getOperand(i),
5268 DAG.getIntPtrConstant(i));
5275 /// getVShift - Return a vector logical shift node.
5277 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5278 unsigned NumBits, SelectionDAG &DAG,
5279 const TargetLowering &TLI, SDLoc dl) {
5280 assert(VT.is128BitVector() && "Unknown type for VShift");
5281 EVT ShVT = MVT::v2i64;
5282 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5283 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5284 return DAG.getNode(ISD::BITCAST, dl, VT,
5285 DAG.getNode(Opc, dl, ShVT, SrcOp,
5286 DAG.getConstant(NumBits,
5287 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5291 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5293 // Check if the scalar load can be widened into a vector load. And if
5294 // the address is "base + cst" see if the cst can be "absorbed" into
5295 // the shuffle mask.
5296 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5297 SDValue Ptr = LD->getBasePtr();
5298 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5300 EVT PVT = LD->getValueType(0);
5301 if (PVT != MVT::i32 && PVT != MVT::f32)
5306 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5307 FI = FINode->getIndex();
5309 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5310 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5311 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5312 Offset = Ptr.getConstantOperandVal(1);
5313 Ptr = Ptr.getOperand(0);
5318 // FIXME: 256-bit vector instructions don't require a strict alignment,
5319 // improve this code to support it better.
5320 unsigned RequiredAlign = VT.getSizeInBits()/8;
5321 SDValue Chain = LD->getChain();
5322 // Make sure the stack object alignment is at least 16 or 32.
5323 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5324 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5325 if (MFI->isFixedObjectIndex(FI)) {
5326 // Can't change the alignment. FIXME: It's possible to compute
5327 // the exact stack offset and reference FI + adjust offset instead.
5328 // If someone *really* cares about this. That's the way to implement it.
5331 MFI->setObjectAlignment(FI, RequiredAlign);
5335 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5336 // Ptr + (Offset & ~15).
5339 if ((Offset % RequiredAlign) & 3)
5341 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5343 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5344 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5346 int EltNo = (Offset - StartOffset) >> 2;
5347 unsigned NumElems = VT.getVectorNumElements();
5349 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5350 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5351 LD->getPointerInfo().getWithOffset(StartOffset),
5352 false, false, false, 0);
5354 SmallVector<int, 8> Mask;
5355 for (unsigned i = 0; i != NumElems; ++i)
5356 Mask.push_back(EltNo);
5358 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5364 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5365 /// vector of type 'VT', see if the elements can be replaced by a single large
5366 /// load which has the same value as a build_vector whose operands are 'elts'.
5368 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5370 /// FIXME: we'd also like to handle the case where the last elements are zero
5371 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5372 /// There's even a handy isZeroNode for that purpose.
5373 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5374 SDLoc &DL, SelectionDAG &DAG) {
5375 EVT EltVT = VT.getVectorElementType();
5376 unsigned NumElems = Elts.size();
5378 LoadSDNode *LDBase = NULL;
5379 unsigned LastLoadedElt = -1U;
5381 // For each element in the initializer, see if we've found a load or an undef.
5382 // If we don't find an initial load element, or later load elements are
5383 // non-consecutive, bail out.
5384 for (unsigned i = 0; i < NumElems; ++i) {
5385 SDValue Elt = Elts[i];
5387 if (!Elt.getNode() ||
5388 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5391 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5393 LDBase = cast<LoadSDNode>(Elt.getNode());
5397 if (Elt.getOpcode() == ISD::UNDEF)
5400 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5401 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5406 // If we have found an entire vector of loads and undefs, then return a large
5407 // load of the entire vector width starting at the base pointer. If we found
5408 // consecutive loads for the low half, generate a vzext_load node.
5409 if (LastLoadedElt == NumElems - 1) {
5410 SDValue NewLd = SDValue();
5411 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5412 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5413 LDBase->getPointerInfo(),
5414 LDBase->isVolatile(), LDBase->isNonTemporal(),
5415 LDBase->isInvariant(), 0);
5416 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5417 LDBase->getPointerInfo(),
5418 LDBase->isVolatile(), LDBase->isNonTemporal(),
5419 LDBase->isInvariant(), LDBase->getAlignment());
5421 if (LDBase->hasAnyUseOfValue(1)) {
5422 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5424 SDValue(NewLd.getNode(), 1));
5425 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5426 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5427 SDValue(NewLd.getNode(), 1));
5432 if (NumElems == 4 && LastLoadedElt == 1 &&
5433 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5434 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5435 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5437 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5438 array_lengthof(Ops), MVT::i64,
5439 LDBase->getPointerInfo(),
5440 LDBase->getAlignment(),
5441 false/*isVolatile*/, true/*ReadMem*/,
5444 // Make sure the newly-created LOAD is in the same position as LDBase in
5445 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5446 // update uses of LDBase's output chain to use the TokenFactor.
5447 if (LDBase->hasAnyUseOfValue(1)) {
5448 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5449 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5450 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5451 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5452 SDValue(ResNode.getNode(), 1));
5455 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5460 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5461 /// to generate a splat value for the following cases:
5462 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5463 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5464 /// a scalar load, or a constant.
5465 /// The VBROADCAST node is returned when a pattern is found,
5466 /// or SDValue() otherwise.
5467 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5468 SelectionDAG &DAG) {
5469 if (!Subtarget->hasFp256())
5472 MVT VT = Op.getSimpleValueType();
5475 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5476 "Unsupported vector type for broadcast.");
5481 switch (Op.getOpcode()) {
5483 // Unknown pattern found.
5486 case ISD::BUILD_VECTOR: {
5487 // The BUILD_VECTOR node must be a splat.
5488 if (!isSplatVector(Op.getNode()))
5491 Ld = Op.getOperand(0);
5492 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5493 Ld.getOpcode() == ISD::ConstantFP);
5495 // The suspected load node has several users. Make sure that all
5496 // of its users are from the BUILD_VECTOR node.
5497 // Constants may have multiple users.
5498 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5503 case ISD::VECTOR_SHUFFLE: {
5504 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5506 // Shuffles must have a splat mask where the first element is
5508 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5511 SDValue Sc = Op.getOperand(0);
5512 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5513 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5515 if (!Subtarget->hasInt256())
5518 // Use the register form of the broadcast instruction available on AVX2.
5519 if (VT.getSizeInBits() >= 256)
5520 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5521 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5524 Ld = Sc.getOperand(0);
5525 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5526 Ld.getOpcode() == ISD::ConstantFP);
5528 // The scalar_to_vector node and the suspected
5529 // load node must have exactly one user.
5530 // Constants may have multiple users.
5532 // AVX-512 has register version of the broadcast
5533 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5534 Ld.getValueType().getSizeInBits() >= 32;
5535 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5542 bool IsGE256 = (VT.getSizeInBits() >= 256);
5544 // Handle the broadcasting a single constant scalar from the constant pool
5545 // into a vector. On Sandybridge it is still better to load a constant vector
5546 // from the constant pool and not to broadcast it from a scalar.
5547 if (ConstSplatVal && Subtarget->hasInt256()) {
5548 EVT CVT = Ld.getValueType();
5549 assert(!CVT.isVector() && "Must not broadcast a vector type");
5550 unsigned ScalarSize = CVT.getSizeInBits();
5552 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5553 const Constant *C = 0;
5554 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5555 C = CI->getConstantIntValue();
5556 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5557 C = CF->getConstantFPValue();
5559 assert(C && "Invalid constant type");
5561 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5562 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5563 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5564 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5565 MachinePointerInfo::getConstantPool(),
5566 false, false, false, Alignment);
5568 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5572 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5573 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5575 // Handle AVX2 in-register broadcasts.
5576 if (!IsLoad && Subtarget->hasInt256() &&
5577 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5578 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5580 // The scalar source must be a normal load.
5584 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
5585 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5587 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5588 // double since there is no vbroadcastsd xmm
5589 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5590 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5591 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5594 // Unsupported broadcast.
5598 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5599 MVT VT = Op.getSimpleValueType();
5601 // Skip if insert_vec_elt is not supported.
5602 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5603 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5607 unsigned NumElems = Op.getNumOperands();
5611 SmallVector<unsigned, 4> InsertIndices;
5612 SmallVector<int, 8> Mask(NumElems, -1);
5614 for (unsigned i = 0; i != NumElems; ++i) {
5615 unsigned Opc = Op.getOperand(i).getOpcode();
5617 if (Opc == ISD::UNDEF)
5620 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5621 // Quit if more than 1 elements need inserting.
5622 if (InsertIndices.size() > 1)
5625 InsertIndices.push_back(i);
5629 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5630 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5632 // Quit if extracted from vector of different type.
5633 if (ExtractedFromVec.getValueType() != VT)
5636 // Quit if non-constant index.
5637 if (!isa<ConstantSDNode>(ExtIdx))
5640 if (VecIn1.getNode() == 0)
5641 VecIn1 = ExtractedFromVec;
5642 else if (VecIn1 != ExtractedFromVec) {
5643 if (VecIn2.getNode() == 0)
5644 VecIn2 = ExtractedFromVec;
5645 else if (VecIn2 != ExtractedFromVec)
5646 // Quit if more than 2 vectors to shuffle
5650 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5652 if (ExtractedFromVec == VecIn1)
5654 else if (ExtractedFromVec == VecIn2)
5655 Mask[i] = Idx + NumElems;
5658 if (VecIn1.getNode() == 0)
5661 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5662 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5663 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5664 unsigned Idx = InsertIndices[i];
5665 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5666 DAG.getIntPtrConstant(Idx));
5672 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5674 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5676 MVT VT = Op.getSimpleValueType();
5677 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
5678 "Unexpected type in LowerBUILD_VECTORvXi1!");
5681 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5682 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
5683 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5684 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5685 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5686 Ops, VT.getVectorNumElements());
5689 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5690 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
5691 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5692 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5693 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
5694 Ops, VT.getVectorNumElements());
5697 bool AllContants = true;
5698 uint64_t Immediate = 0;
5699 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5700 SDValue In = Op.getOperand(idx);
5701 if (In.getOpcode() == ISD::UNDEF)
5703 if (!isa<ConstantSDNode>(In)) {
5704 AllContants = false;
5707 if (cast<ConstantSDNode>(In)->getZExtValue())
5708 Immediate |= (1ULL << idx);
5712 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
5713 DAG.getConstant(Immediate, MVT::i16));
5714 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
5715 DAG.getIntPtrConstant(0));
5718 // Splat vector (with undefs)
5719 SDValue In = Op.getOperand(0);
5720 for (unsigned i = 1, e = Op.getNumOperands(); i != e; ++i) {
5721 if (Op.getOperand(i) != In && Op.getOperand(i).getOpcode() != ISD::UNDEF)
5722 llvm_unreachable("Unsupported predicate operation");
5725 SDValue EFLAGS, X86CC;
5726 if (In.getOpcode() == ISD::SETCC) {
5727 SDValue Op0 = In.getOperand(0);
5728 SDValue Op1 = In.getOperand(1);
5729 ISD::CondCode CC = cast<CondCodeSDNode>(In.getOperand(2))->get();
5730 bool isFP = Op1.getValueType().isFloatingPoint();
5731 unsigned X86CCVal = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5733 assert(X86CCVal != X86::COND_INVALID && "Unsupported predicate operation");
5735 X86CC = DAG.getConstant(X86CCVal, MVT::i8);
5736 EFLAGS = EmitCmp(Op0, Op1, X86CCVal, DAG);
5737 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
5738 } else if (In.getOpcode() == X86ISD::SETCC) {
5739 X86CC = In.getOperand(0);
5740 EFLAGS = In.getOperand(1);
5749 // res = allOnes ### CMOVNE -1, %res
5752 MVT InVT = In.getSimpleValueType();
5753 SDValue Bit1 = DAG.getNode(ISD::AND, dl, InVT, In, DAG.getConstant(1, InVT));
5754 EFLAGS = EmitTest(Bit1, X86::COND_NE, DAG);
5755 X86CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5758 if (VT == MVT::v16i1) {
5759 SDValue Cst1 = DAG.getConstant(-1, MVT::i16);
5760 SDValue Cst0 = DAG.getConstant(0, MVT::i16);
5761 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i16,
5762 Cst0, Cst1, X86CC, EFLAGS);
5763 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5766 if (VT == MVT::v8i1) {
5767 SDValue Cst1 = DAG.getConstant(-1, MVT::i32);
5768 SDValue Cst0 = DAG.getConstant(0, MVT::i32);
5769 SDValue CmovOp = DAG.getNode(X86ISD::CMOV, dl, MVT::i32,
5770 Cst0, Cst1, X86CC, EFLAGS);
5771 CmovOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CmovOp);
5772 return DAG.getNode(ISD::BITCAST, dl, VT, CmovOp);
5774 llvm_unreachable("Unsupported predicate operation");
5778 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5781 MVT VT = Op.getSimpleValueType();
5782 MVT ExtVT = VT.getVectorElementType();
5783 unsigned NumElems = Op.getNumOperands();
5785 // Generate vectors for predicate vectors.
5786 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5787 return LowerBUILD_VECTORvXi1(Op, DAG);
5789 // Vectors containing all zeros can be matched by pxor and xorps later
5790 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5791 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5792 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5793 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5796 return getZeroVector(VT, Subtarget, DAG, dl);
5799 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5800 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5801 // vpcmpeqd on 256-bit vectors.
5802 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5803 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5806 if (!VT.is512BitVector())
5807 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5810 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
5811 if (Broadcast.getNode())
5814 unsigned EVTBits = ExtVT.getSizeInBits();
5816 unsigned NumZero = 0;
5817 unsigned NumNonZero = 0;
5818 unsigned NonZeros = 0;
5819 bool IsAllConstants = true;
5820 SmallSet<SDValue, 8> Values;
5821 for (unsigned i = 0; i < NumElems; ++i) {
5822 SDValue Elt = Op.getOperand(i);
5823 if (Elt.getOpcode() == ISD::UNDEF)
5826 if (Elt.getOpcode() != ISD::Constant &&
5827 Elt.getOpcode() != ISD::ConstantFP)
5828 IsAllConstants = false;
5829 if (X86::isZeroNode(Elt))
5832 NonZeros |= (1 << i);
5837 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5838 if (NumNonZero == 0)
5839 return DAG.getUNDEF(VT);
5841 // Special case for single non-zero, non-undef, element.
5842 if (NumNonZero == 1) {
5843 unsigned Idx = countTrailingZeros(NonZeros);
5844 SDValue Item = Op.getOperand(Idx);
5846 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5847 // the value are obviously zero, truncate the value to i32 and do the
5848 // insertion that way. Only do this if the value is non-constant or if the
5849 // value is a constant being inserted into element 0. It is cheaper to do
5850 // a constant pool load than it is to do a movd + shuffle.
5851 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5852 (!IsAllConstants || Idx == 0)) {
5853 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5855 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5856 EVT VecVT = MVT::v4i32;
5857 unsigned VecElts = 4;
5859 // Truncate the value (which may itself be a constant) to i32, and
5860 // convert it to a vector with movd (S2V+shuffle to zero extend).
5861 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5862 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5863 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5865 // Now we have our 32-bit value zero extended in the low element of
5866 // a vector. If Idx != 0, swizzle it into place.
5868 SmallVector<int, 4> Mask;
5869 Mask.push_back(Idx);
5870 for (unsigned i = 1; i != VecElts; ++i)
5872 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5875 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5879 // If we have a constant or non-constant insertion into the low element of
5880 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5881 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5882 // depending on what the source datatype is.
5885 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5887 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5888 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5889 if (VT.is256BitVector() || VT.is512BitVector()) {
5890 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5891 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5892 Item, DAG.getIntPtrConstant(0));
5894 assert(VT.is128BitVector() && "Expected an SSE value type!");
5895 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5896 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5897 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5900 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5901 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5902 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5903 if (VT.is256BitVector()) {
5904 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5905 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5907 assert(VT.is128BitVector() && "Expected an SSE value type!");
5908 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5910 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5914 // Is it a vector logical left shift?
5915 if (NumElems == 2 && Idx == 1 &&
5916 X86::isZeroNode(Op.getOperand(0)) &&
5917 !X86::isZeroNode(Op.getOperand(1))) {
5918 unsigned NumBits = VT.getSizeInBits();
5919 return getVShift(true, VT,
5920 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5921 VT, Op.getOperand(1)),
5922 NumBits/2, DAG, *this, dl);
5925 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5928 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5929 // is a non-constant being inserted into an element other than the low one,
5930 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5931 // movd/movss) to move this into the low element, then shuffle it into
5933 if (EVTBits == 32) {
5934 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5936 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5937 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5938 SmallVector<int, 8> MaskVec;
5939 for (unsigned i = 0; i != NumElems; ++i)
5940 MaskVec.push_back(i == Idx ? 0 : 1);
5941 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5945 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5946 if (Values.size() == 1) {
5947 if (EVTBits == 32) {
5948 // Instead of a shuffle like this:
5949 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5950 // Check if it's possible to issue this instead.
5951 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5952 unsigned Idx = countTrailingZeros(NonZeros);
5953 SDValue Item = Op.getOperand(Idx);
5954 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5955 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5960 // A vector full of immediates; various special cases are already
5961 // handled, so this is best done with a single constant-pool load.
5965 // For AVX-length vectors, build the individual 128-bit pieces and use
5966 // shuffles to put them in place.
5967 if (VT.is256BitVector()) {
5968 SmallVector<SDValue, 32> V;
5969 for (unsigned i = 0; i != NumElems; ++i)
5970 V.push_back(Op.getOperand(i));
5972 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5974 // Build both the lower and upper subvector.
5975 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5976 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5979 // Recreate the wider vector with the lower and upper part.
5980 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5983 // Let legalizer expand 2-wide build_vectors.
5984 if (EVTBits == 64) {
5985 if (NumNonZero == 1) {
5986 // One half is zero or undef.
5987 unsigned Idx = countTrailingZeros(NonZeros);
5988 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5989 Op.getOperand(Idx));
5990 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5995 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5996 if (EVTBits == 8 && NumElems == 16) {
5997 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5999 if (V.getNode()) return V;
6002 if (EVTBits == 16 && NumElems == 8) {
6003 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6005 if (V.getNode()) return V;
6008 // If element VT is == 32 bits, turn it into a number of shuffles.
6009 SmallVector<SDValue, 8> V(NumElems);
6010 if (NumElems == 4 && NumZero > 0) {
6011 for (unsigned i = 0; i < 4; ++i) {
6012 bool isZero = !(NonZeros & (1 << i));
6014 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6016 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6019 for (unsigned i = 0; i < 2; ++i) {
6020 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6023 V[i] = V[i*2]; // Must be a zero vector.
6026 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6029 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6032 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6037 bool Reverse1 = (NonZeros & 0x3) == 2;
6038 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6042 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6043 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6045 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6048 if (Values.size() > 1 && VT.is128BitVector()) {
6049 // Check for a build vector of consecutive loads.
6050 for (unsigned i = 0; i < NumElems; ++i)
6051 V[i] = Op.getOperand(i);
6053 // Check for elements which are consecutive loads.
6054 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
6058 // Check for a build vector from mostly shuffle plus few inserting.
6059 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6063 // For SSE 4.1, use insertps to put the high elements into the low element.
6064 if (getSubtarget()->hasSSE41()) {
6066 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6067 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6069 Result = DAG.getUNDEF(VT);
6071 for (unsigned i = 1; i < NumElems; ++i) {
6072 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6073 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6074 Op.getOperand(i), DAG.getIntPtrConstant(i));
6079 // Otherwise, expand into a number of unpckl*, start by extending each of
6080 // our (non-undef) elements to the full vector width with the element in the
6081 // bottom slot of the vector (which generates no code for SSE).
6082 for (unsigned i = 0; i < NumElems; ++i) {
6083 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6084 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6086 V[i] = DAG.getUNDEF(VT);
6089 // Next, we iteratively mix elements, e.g. for v4f32:
6090 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6091 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6092 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6093 unsigned EltStride = NumElems >> 1;
6094 while (EltStride != 0) {
6095 for (unsigned i = 0; i < EltStride; ++i) {
6096 // If V[i+EltStride] is undef and this is the first round of mixing,
6097 // then it is safe to just drop this shuffle: V[i] is already in the
6098 // right place, the one element (since it's the first round) being
6099 // inserted as undef can be dropped. This isn't safe for successive
6100 // rounds because they will permute elements within both vectors.
6101 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6102 EltStride == NumElems/2)
6105 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6114 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6115 // to create 256-bit vectors from two other 128-bit ones.
6116 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6118 MVT ResVT = Op.getSimpleValueType();
6120 assert((ResVT.is256BitVector() ||
6121 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6123 SDValue V1 = Op.getOperand(0);
6124 SDValue V2 = Op.getOperand(1);
6125 unsigned NumElems = ResVT.getVectorNumElements();
6126 if(ResVT.is256BitVector())
6127 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6129 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6132 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6133 assert(Op.getNumOperands() == 2);
6135 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
6136 // from two other 128-bit ones.
6137 return LowerAVXCONCAT_VECTORS(Op, DAG);
6140 // Try to lower a shuffle node into a simple blend instruction.
6142 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
6143 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6144 SDValue V1 = SVOp->getOperand(0);
6145 SDValue V2 = SVOp->getOperand(1);
6147 MVT VT = SVOp->getSimpleValueType(0);
6148 MVT EltVT = VT.getVectorElementType();
6149 unsigned NumElems = VT.getVectorNumElements();
6151 // There is no blend with immediate in AVX-512.
6152 if (VT.is512BitVector())
6155 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
6157 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
6160 // Check the mask for BLEND and build the value.
6161 unsigned MaskValue = 0;
6162 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
6163 unsigned NumLanes = (NumElems-1)/8 + 1;
6164 unsigned NumElemsInLane = NumElems / NumLanes;
6166 // Blend for v16i16 should be symetric for the both lanes.
6167 for (unsigned i = 0; i < NumElemsInLane; ++i) {
6169 int SndLaneEltIdx = (NumLanes == 2) ?
6170 SVOp->getMaskElt(i + NumElemsInLane) : -1;
6171 int EltIdx = SVOp->getMaskElt(i);
6173 if ((EltIdx < 0 || EltIdx == (int)i) &&
6174 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
6177 if (((unsigned)EltIdx == (i + NumElems)) &&
6178 (SndLaneEltIdx < 0 ||
6179 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6180 MaskValue |= (1<<i);
6185 // Convert i32 vectors to floating point if it is not AVX2.
6186 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6188 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6189 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6191 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6192 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6195 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6196 DAG.getConstant(MaskValue, MVT::i32));
6197 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6200 // v8i16 shuffles - Prefer shuffles in the following order:
6201 // 1. [all] pshuflw, pshufhw, optional move
6202 // 2. [ssse3] 1 x pshufb
6203 // 3. [ssse3] 2 x pshufb + 1 x por
6204 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6206 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6207 SelectionDAG &DAG) {
6208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6209 SDValue V1 = SVOp->getOperand(0);
6210 SDValue V2 = SVOp->getOperand(1);
6212 SmallVector<int, 8> MaskVals;
6214 // Determine if more than 1 of the words in each of the low and high quadwords
6215 // of the result come from the same quadword of one of the two inputs. Undef
6216 // mask values count as coming from any quadword, for better codegen.
6217 unsigned LoQuad[] = { 0, 0, 0, 0 };
6218 unsigned HiQuad[] = { 0, 0, 0, 0 };
6219 std::bitset<4> InputQuads;
6220 for (unsigned i = 0; i < 8; ++i) {
6221 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6222 int EltIdx = SVOp->getMaskElt(i);
6223 MaskVals.push_back(EltIdx);
6232 InputQuads.set(EltIdx / 4);
6235 int BestLoQuad = -1;
6236 unsigned MaxQuad = 1;
6237 for (unsigned i = 0; i < 4; ++i) {
6238 if (LoQuad[i] > MaxQuad) {
6240 MaxQuad = LoQuad[i];
6244 int BestHiQuad = -1;
6246 for (unsigned i = 0; i < 4; ++i) {
6247 if (HiQuad[i] > MaxQuad) {
6249 MaxQuad = HiQuad[i];
6253 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6254 // of the two input vectors, shuffle them into one input vector so only a
6255 // single pshufb instruction is necessary. If There are more than 2 input
6256 // quads, disable the next transformation since it does not help SSSE3.
6257 bool V1Used = InputQuads[0] || InputQuads[1];
6258 bool V2Used = InputQuads[2] || InputQuads[3];
6259 if (Subtarget->hasSSSE3()) {
6260 if (InputQuads.count() == 2 && V1Used && V2Used) {
6261 BestLoQuad = InputQuads[0] ? 0 : 1;
6262 BestHiQuad = InputQuads[2] ? 2 : 3;
6264 if (InputQuads.count() > 2) {
6270 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6271 // the shuffle mask. If a quad is scored as -1, that means that it contains
6272 // words from all 4 input quadwords.
6274 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6276 BestLoQuad < 0 ? 0 : BestLoQuad,
6277 BestHiQuad < 0 ? 1 : BestHiQuad
6279 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6280 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6281 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6282 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6284 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6285 // source words for the shuffle, to aid later transformations.
6286 bool AllWordsInNewV = true;
6287 bool InOrder[2] = { true, true };
6288 for (unsigned i = 0; i != 8; ++i) {
6289 int idx = MaskVals[i];
6291 InOrder[i/4] = false;
6292 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6294 AllWordsInNewV = false;
6298 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6299 if (AllWordsInNewV) {
6300 for (int i = 0; i != 8; ++i) {
6301 int idx = MaskVals[i];
6304 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6305 if ((idx != i) && idx < 4)
6307 if ((idx != i) && idx > 3)
6316 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6317 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6318 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6319 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6320 unsigned TargetMask = 0;
6321 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6322 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6323 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6324 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6325 getShufflePSHUFLWImmediate(SVOp);
6326 V1 = NewV.getOperand(0);
6327 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6331 // Promote splats to a larger type which usually leads to more efficient code.
6332 // FIXME: Is this true if pshufb is available?
6333 if (SVOp->isSplat())
6334 return PromoteSplat(SVOp, DAG);
6336 // If we have SSSE3, and all words of the result are from 1 input vector,
6337 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6338 // is present, fall back to case 4.
6339 if (Subtarget->hasSSSE3()) {
6340 SmallVector<SDValue,16> pshufbMask;
6342 // If we have elements from both input vectors, set the high bit of the
6343 // shuffle mask element to zero out elements that come from V2 in the V1
6344 // mask, and elements that come from V1 in the V2 mask, so that the two
6345 // results can be OR'd together.
6346 bool TwoInputs = V1Used && V2Used;
6347 for (unsigned i = 0; i != 8; ++i) {
6348 int EltIdx = MaskVals[i] * 2;
6349 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6350 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6351 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6352 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6354 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6355 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6356 DAG.getNode(ISD::BUILD_VECTOR, dl,
6357 MVT::v16i8, &pshufbMask[0], 16));
6359 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6361 // Calculate the shuffle mask for the second input, shuffle it, and
6362 // OR it with the first shuffled input.
6364 for (unsigned i = 0; i != 8; ++i) {
6365 int EltIdx = MaskVals[i] * 2;
6366 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6367 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6368 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6369 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6371 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6372 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6373 DAG.getNode(ISD::BUILD_VECTOR, dl,
6374 MVT::v16i8, &pshufbMask[0], 16));
6375 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6376 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6379 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6380 // and update MaskVals with new element order.
6381 std::bitset<8> InOrder;
6382 if (BestLoQuad >= 0) {
6383 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6384 for (int i = 0; i != 4; ++i) {
6385 int idx = MaskVals[i];
6388 } else if ((idx / 4) == BestLoQuad) {
6393 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6396 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6397 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6398 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6400 getShufflePSHUFLWImmediate(SVOp), DAG);
6404 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6405 // and update MaskVals with the new element order.
6406 if (BestHiQuad >= 0) {
6407 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6408 for (unsigned i = 4; i != 8; ++i) {
6409 int idx = MaskVals[i];
6412 } else if ((idx / 4) == BestHiQuad) {
6413 MaskV[i] = (idx & 3) + 4;
6417 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6420 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6421 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6422 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6424 getShufflePSHUFHWImmediate(SVOp), DAG);
6428 // In case BestHi & BestLo were both -1, which means each quadword has a word
6429 // from each of the four input quadwords, calculate the InOrder bitvector now
6430 // before falling through to the insert/extract cleanup.
6431 if (BestLoQuad == -1 && BestHiQuad == -1) {
6433 for (int i = 0; i != 8; ++i)
6434 if (MaskVals[i] < 0 || MaskVals[i] == i)
6438 // The other elements are put in the right place using pextrw and pinsrw.
6439 for (unsigned i = 0; i != 8; ++i) {
6442 int EltIdx = MaskVals[i];
6445 SDValue ExtOp = (EltIdx < 8) ?
6446 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6447 DAG.getIntPtrConstant(EltIdx)) :
6448 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6449 DAG.getIntPtrConstant(EltIdx - 8));
6450 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6451 DAG.getIntPtrConstant(i));
6456 // v16i8 shuffles - Prefer shuffles in the following order:
6457 // 1. [ssse3] 1 x pshufb
6458 // 2. [ssse3] 2 x pshufb + 1 x por
6459 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6460 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6461 const X86Subtarget* Subtarget,
6462 SelectionDAG &DAG) {
6463 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6464 SDValue V1 = SVOp->getOperand(0);
6465 SDValue V2 = SVOp->getOperand(1);
6467 ArrayRef<int> MaskVals = SVOp->getMask();
6469 // Promote splats to a larger type which usually leads to more efficient code.
6470 // FIXME: Is this true if pshufb is available?
6471 if (SVOp->isSplat())
6472 return PromoteSplat(SVOp, DAG);
6474 // If we have SSSE3, case 1 is generated when all result bytes come from
6475 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6476 // present, fall back to case 3.
6478 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6479 if (Subtarget->hasSSSE3()) {
6480 SmallVector<SDValue,16> pshufbMask;
6482 // If all result elements are from one input vector, then only translate
6483 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6485 // Otherwise, we have elements from both input vectors, and must zero out
6486 // elements that come from V2 in the first mask, and V1 in the second mask
6487 // so that we can OR them together.
6488 for (unsigned i = 0; i != 16; ++i) {
6489 int EltIdx = MaskVals[i];
6490 if (EltIdx < 0 || EltIdx >= 16)
6492 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6494 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6495 DAG.getNode(ISD::BUILD_VECTOR, dl,
6496 MVT::v16i8, &pshufbMask[0], 16));
6498 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6499 // the 2nd operand if it's undefined or zero.
6500 if (V2.getOpcode() == ISD::UNDEF ||
6501 ISD::isBuildVectorAllZeros(V2.getNode()))
6504 // Calculate the shuffle mask for the second input, shuffle it, and
6505 // OR it with the first shuffled input.
6507 for (unsigned i = 0; i != 16; ++i) {
6508 int EltIdx = MaskVals[i];
6509 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6510 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6512 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6513 DAG.getNode(ISD::BUILD_VECTOR, dl,
6514 MVT::v16i8, &pshufbMask[0], 16));
6515 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6518 // No SSSE3 - Calculate in place words and then fix all out of place words
6519 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6520 // the 16 different words that comprise the two doublequadword input vectors.
6521 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6522 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6524 for (int i = 0; i != 8; ++i) {
6525 int Elt0 = MaskVals[i*2];
6526 int Elt1 = MaskVals[i*2+1];
6528 // This word of the result is all undef, skip it.
6529 if (Elt0 < 0 && Elt1 < 0)
6532 // This word of the result is already in the correct place, skip it.
6533 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6536 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6537 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6540 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6541 // using a single extract together, load it and store it.
6542 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6543 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6544 DAG.getIntPtrConstant(Elt1 / 2));
6545 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6546 DAG.getIntPtrConstant(i));
6550 // If Elt1 is defined, extract it from the appropriate source. If the
6551 // source byte is not also odd, shift the extracted word left 8 bits
6552 // otherwise clear the bottom 8 bits if we need to do an or.
6554 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6555 DAG.getIntPtrConstant(Elt1 / 2));
6556 if ((Elt1 & 1) == 0)
6557 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6559 TLI.getShiftAmountTy(InsElt.getValueType())));
6561 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6562 DAG.getConstant(0xFF00, MVT::i16));
6564 // If Elt0 is defined, extract it from the appropriate source. If the
6565 // source byte is not also even, shift the extracted word right 8 bits. If
6566 // Elt1 was also defined, OR the extracted values together before
6567 // inserting them in the result.
6569 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6570 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6571 if ((Elt0 & 1) != 0)
6572 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6574 TLI.getShiftAmountTy(InsElt0.getValueType())));
6576 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6577 DAG.getConstant(0x00FF, MVT::i16));
6578 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6581 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6582 DAG.getIntPtrConstant(i));
6584 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6587 // v32i8 shuffles - Translate to VPSHUFB if possible.
6589 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6590 const X86Subtarget *Subtarget,
6591 SelectionDAG &DAG) {
6592 MVT VT = SVOp->getSimpleValueType(0);
6593 SDValue V1 = SVOp->getOperand(0);
6594 SDValue V2 = SVOp->getOperand(1);
6596 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6598 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6599 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6600 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6602 // VPSHUFB may be generated if
6603 // (1) one of input vector is undefined or zeroinitializer.
6604 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6605 // And (2) the mask indexes don't cross the 128-bit lane.
6606 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6607 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6610 if (V1IsAllZero && !V2IsAllZero) {
6611 CommuteVectorShuffleMask(MaskVals, 32);
6614 SmallVector<SDValue, 32> pshufbMask;
6615 for (unsigned i = 0; i != 32; i++) {
6616 int EltIdx = MaskVals[i];
6617 if (EltIdx < 0 || EltIdx >= 32)
6620 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6621 // Cross lane is not allowed.
6625 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6627 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6628 DAG.getNode(ISD::BUILD_VECTOR, dl,
6629 MVT::v32i8, &pshufbMask[0], 32));
6632 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6633 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6634 /// done when every pair / quad of shuffle mask elements point to elements in
6635 /// the right sequence. e.g.
6636 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6638 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6639 SelectionDAG &DAG) {
6640 MVT VT = SVOp->getSimpleValueType(0);
6642 unsigned NumElems = VT.getVectorNumElements();
6645 switch (VT.SimpleTy) {
6646 default: llvm_unreachable("Unexpected!");
6647 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6648 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6649 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6650 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6651 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6652 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6655 SmallVector<int, 8> MaskVec;
6656 for (unsigned i = 0; i != NumElems; i += Scale) {
6658 for (unsigned j = 0; j != Scale; ++j) {
6659 int EltIdx = SVOp->getMaskElt(i+j);
6663 StartIdx = (EltIdx / Scale);
6664 if (EltIdx != (int)(StartIdx*Scale + j))
6667 MaskVec.push_back(StartIdx);
6670 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6671 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6672 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6675 /// getVZextMovL - Return a zero-extending vector move low node.
6677 static SDValue getVZextMovL(MVT VT, MVT OpVT,
6678 SDValue SrcOp, SelectionDAG &DAG,
6679 const X86Subtarget *Subtarget, SDLoc dl) {
6680 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6681 LoadSDNode *LD = NULL;
6682 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6683 LD = dyn_cast<LoadSDNode>(SrcOp);
6685 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6687 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6688 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6689 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6690 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6691 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6693 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6694 return DAG.getNode(ISD::BITCAST, dl, VT,
6695 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6696 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6704 return DAG.getNode(ISD::BITCAST, dl, VT,
6705 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6706 DAG.getNode(ISD::BITCAST, dl,
6710 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6711 /// which could not be matched by any known target speficic shuffle
6713 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6715 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6716 if (NewOp.getNode())
6719 MVT VT = SVOp->getSimpleValueType(0);
6721 unsigned NumElems = VT.getVectorNumElements();
6722 unsigned NumLaneElems = NumElems / 2;
6725 MVT EltVT = VT.getVectorElementType();
6726 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6729 SmallVector<int, 16> Mask;
6730 for (unsigned l = 0; l < 2; ++l) {
6731 // Build a shuffle mask for the output, discovering on the fly which
6732 // input vectors to use as shuffle operands (recorded in InputUsed).
6733 // If building a suitable shuffle vector proves too hard, then bail
6734 // out with UseBuildVector set.
6735 bool UseBuildVector = false;
6736 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6737 unsigned LaneStart = l * NumLaneElems;
6738 for (unsigned i = 0; i != NumLaneElems; ++i) {
6739 // The mask element. This indexes into the input.
6740 int Idx = SVOp->getMaskElt(i+LaneStart);
6742 // the mask element does not index into any input vector.
6747 // The input vector this mask element indexes into.
6748 int Input = Idx / NumLaneElems;
6750 // Turn the index into an offset from the start of the input vector.
6751 Idx -= Input * NumLaneElems;
6753 // Find or create a shuffle vector operand to hold this input.
6755 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6756 if (InputUsed[OpNo] == Input)
6757 // This input vector is already an operand.
6759 if (InputUsed[OpNo] < 0) {
6760 // Create a new operand for this input vector.
6761 InputUsed[OpNo] = Input;
6766 if (OpNo >= array_lengthof(InputUsed)) {
6767 // More than two input vectors used! Give up on trying to create a
6768 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6769 UseBuildVector = true;
6773 // Add the mask index for the new shuffle vector.
6774 Mask.push_back(Idx + OpNo * NumLaneElems);
6777 if (UseBuildVector) {
6778 SmallVector<SDValue, 16> SVOps;
6779 for (unsigned i = 0; i != NumLaneElems; ++i) {
6780 // The mask element. This indexes into the input.
6781 int Idx = SVOp->getMaskElt(i+LaneStart);
6783 SVOps.push_back(DAG.getUNDEF(EltVT));
6787 // The input vector this mask element indexes into.
6788 int Input = Idx / NumElems;
6790 // Turn the index into an offset from the start of the input vector.
6791 Idx -= Input * NumElems;
6793 // Extract the vector element by hand.
6794 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6795 SVOp->getOperand(Input),
6796 DAG.getIntPtrConstant(Idx)));
6799 // Construct the output using a BUILD_VECTOR.
6800 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6802 } else if (InputUsed[0] < 0) {
6803 // No input vectors were used! The result is undefined.
6804 Output[l] = DAG.getUNDEF(NVT);
6806 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6807 (InputUsed[0] % 2) * NumLaneElems,
6809 // If only one input was used, use an undefined vector for the other.
6810 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6811 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6812 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6813 // At least one input vector was used. Create a new shuffle vector.
6814 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6820 // Concatenate the result back
6821 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6824 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6825 /// 4 elements, and match them with several different shuffle types.
6827 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6828 SDValue V1 = SVOp->getOperand(0);
6829 SDValue V2 = SVOp->getOperand(1);
6831 MVT VT = SVOp->getSimpleValueType(0);
6833 assert(VT.is128BitVector() && "Unsupported vector size");
6835 std::pair<int, int> Locs[4];
6836 int Mask1[] = { -1, -1, -1, -1 };
6837 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6841 for (unsigned i = 0; i != 4; ++i) {
6842 int Idx = PermMask[i];
6844 Locs[i] = std::make_pair(-1, -1);
6846 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6848 Locs[i] = std::make_pair(0, NumLo);
6852 Locs[i] = std::make_pair(1, NumHi);
6854 Mask1[2+NumHi] = Idx;
6860 if (NumLo <= 2 && NumHi <= 2) {
6861 // If no more than two elements come from either vector. This can be
6862 // implemented with two shuffles. First shuffle gather the elements.
6863 // The second shuffle, which takes the first shuffle as both of its
6864 // vector operands, put the elements into the right order.
6865 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6867 int Mask2[] = { -1, -1, -1, -1 };
6869 for (unsigned i = 0; i != 4; ++i)
6870 if (Locs[i].first != -1) {
6871 unsigned Idx = (i < 2) ? 0 : 4;
6872 Idx += Locs[i].first * 2 + Locs[i].second;
6876 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6879 if (NumLo == 3 || NumHi == 3) {
6880 // Otherwise, we must have three elements from one vector, call it X, and
6881 // one element from the other, call it Y. First, use a shufps to build an
6882 // intermediate vector with the one element from Y and the element from X
6883 // that will be in the same half in the final destination (the indexes don't
6884 // matter). Then, use a shufps to build the final vector, taking the half
6885 // containing the element from Y from the intermediate, and the other half
6888 // Normalize it so the 3 elements come from V1.
6889 CommuteVectorShuffleMask(PermMask, 4);
6893 // Find the element from V2.
6895 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6896 int Val = PermMask[HiIndex];
6903 Mask1[0] = PermMask[HiIndex];
6905 Mask1[2] = PermMask[HiIndex^1];
6907 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6910 Mask1[0] = PermMask[0];
6911 Mask1[1] = PermMask[1];
6912 Mask1[2] = HiIndex & 1 ? 6 : 4;
6913 Mask1[3] = HiIndex & 1 ? 4 : 6;
6914 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6917 Mask1[0] = HiIndex & 1 ? 2 : 0;
6918 Mask1[1] = HiIndex & 1 ? 0 : 2;
6919 Mask1[2] = PermMask[2];
6920 Mask1[3] = PermMask[3];
6925 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6928 // Break it into (shuffle shuffle_hi, shuffle_lo).
6929 int LoMask[] = { -1, -1, -1, -1 };
6930 int HiMask[] = { -1, -1, -1, -1 };
6932 int *MaskPtr = LoMask;
6933 unsigned MaskIdx = 0;
6936 for (unsigned i = 0; i != 4; ++i) {
6943 int Idx = PermMask[i];
6945 Locs[i] = std::make_pair(-1, -1);
6946 } else if (Idx < 4) {
6947 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6948 MaskPtr[LoIdx] = Idx;
6951 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6952 MaskPtr[HiIdx] = Idx;
6957 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6958 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6959 int MaskOps[] = { -1, -1, -1, -1 };
6960 for (unsigned i = 0; i != 4; ++i)
6961 if (Locs[i].first != -1)
6962 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6963 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6966 static bool MayFoldVectorLoad(SDValue V) {
6967 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6968 V = V.getOperand(0);
6970 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6971 V = V.getOperand(0);
6972 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6973 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6974 // BUILD_VECTOR (load), undef
6975 V = V.getOperand(0);
6977 return MayFoldLoad(V);
6981 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6982 MVT VT = Op.getSimpleValueType();
6984 // Canonizalize to v2f64.
6985 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6986 return DAG.getNode(ISD::BITCAST, dl, VT,
6987 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6992 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6994 SDValue V1 = Op.getOperand(0);
6995 SDValue V2 = Op.getOperand(1);
6996 MVT VT = Op.getSimpleValueType();
6998 assert(VT != MVT::v2i64 && "unsupported shuffle type");
7000 if (HasSSE2 && VT == MVT::v2f64)
7001 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
7003 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
7004 return DAG.getNode(ISD::BITCAST, dl, VT,
7005 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
7006 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
7007 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
7011 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
7012 SDValue V1 = Op.getOperand(0);
7013 SDValue V2 = Op.getOperand(1);
7014 MVT VT = Op.getSimpleValueType();
7016 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
7017 "unsupported shuffle type");
7019 if (V2.getOpcode() == ISD::UNDEF)
7023 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
7027 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
7028 SDValue V1 = Op.getOperand(0);
7029 SDValue V2 = Op.getOperand(1);
7030 MVT VT = Op.getSimpleValueType();
7031 unsigned NumElems = VT.getVectorNumElements();
7033 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
7034 // operand of these instructions is only memory, so check if there's a
7035 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
7037 bool CanFoldLoad = false;
7039 // Trivial case, when V2 comes from a load.
7040 if (MayFoldVectorLoad(V2))
7043 // When V1 is a load, it can be folded later into a store in isel, example:
7044 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
7046 // (MOVLPSmr addr:$src1, VR128:$src2)
7047 // So, recognize this potential and also use MOVLPS or MOVLPD
7048 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
7051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7053 if (HasSSE2 && NumElems == 2)
7054 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
7057 // If we don't care about the second element, proceed to use movss.
7058 if (SVOp->getMaskElt(1) != -1)
7059 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
7062 // movl and movlp will both match v2i64, but v2i64 is never matched by
7063 // movl earlier because we make it strict to avoid messing with the movlp load
7064 // folding logic (see the code above getMOVLP call). Match it here then,
7065 // this is horrible, but will stay like this until we move all shuffle
7066 // matching to x86 specific nodes. Note that for the 1st condition all
7067 // types are matched with movsd.
7069 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
7070 // as to remove this logic from here, as much as possible
7071 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
7072 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7073 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7076 assert(VT != MVT::v4i32 && "unsupported shuffle type");
7078 // Invert the operand order and use SHUFPS to match it.
7079 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
7080 getShuffleSHUFImmediate(SVOp), DAG);
7083 // Reduce a vector shuffle to zext.
7084 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
7085 SelectionDAG &DAG) {
7086 // PMOVZX is only available from SSE41.
7087 if (!Subtarget->hasSSE41())
7090 MVT VT = Op.getSimpleValueType();
7092 // Only AVX2 support 256-bit vector integer extending.
7093 if (!Subtarget->hasInt256() && VT.is256BitVector())
7096 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7098 SDValue V1 = Op.getOperand(0);
7099 SDValue V2 = Op.getOperand(1);
7100 unsigned NumElems = VT.getVectorNumElements();
7102 // Extending is an unary operation and the element type of the source vector
7103 // won't be equal to or larger than i64.
7104 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
7105 VT.getVectorElementType() == MVT::i64)
7108 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
7109 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
7110 while ((1U << Shift) < NumElems) {
7111 if (SVOp->getMaskElt(1U << Shift) == 1)
7114 // The maximal ratio is 8, i.e. from i8 to i64.
7119 // Check the shuffle mask.
7120 unsigned Mask = (1U << Shift) - 1;
7121 for (unsigned i = 0; i != NumElems; ++i) {
7122 int EltIdx = SVOp->getMaskElt(i);
7123 if ((i & Mask) != 0 && EltIdx != -1)
7125 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
7129 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
7130 MVT NeVT = MVT::getIntegerVT(NBits);
7131 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
7133 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
7136 // Simplify the operand as it's prepared to be fed into shuffle.
7137 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
7138 if (V1.getOpcode() == ISD::BITCAST &&
7139 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
7140 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
7141 V1.getOperand(0).getOperand(0)
7142 .getSimpleValueType().getSizeInBits() == SignificantBits) {
7143 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
7144 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
7145 ConstantSDNode *CIdx =
7146 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
7147 // If it's foldable, i.e. normal load with single use, we will let code
7148 // selection to fold it. Otherwise, we will short the conversion sequence.
7149 if (CIdx && CIdx->getZExtValue() == 0 &&
7150 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
7151 MVT FullVT = V.getSimpleValueType();
7152 MVT V1VT = V1.getSimpleValueType();
7153 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
7154 // The "ext_vec_elt" node is wider than the result node.
7155 // In this case we should extract subvector from V.
7156 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
7157 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
7158 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
7159 FullVT.getVectorNumElements()/Ratio);
7160 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
7161 DAG.getIntPtrConstant(0));
7163 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
7167 return DAG.getNode(ISD::BITCAST, DL, VT,
7168 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
7172 NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
7173 SelectionDAG &DAG) {
7174 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7175 MVT VT = Op.getSimpleValueType();
7177 SDValue V1 = Op.getOperand(0);
7178 SDValue V2 = Op.getOperand(1);
7180 if (isZeroShuffle(SVOp))
7181 return getZeroVector(VT, Subtarget, DAG, dl);
7183 // Handle splat operations
7184 if (SVOp->isSplat()) {
7185 // Use vbroadcast whenever the splat comes from a foldable load
7186 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
7187 if (Broadcast.getNode())
7191 // Check integer expanding shuffles.
7192 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
7193 if (NewOp.getNode())
7196 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7198 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7199 VT == MVT::v16i16 || VT == MVT::v32i8) {
7200 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7201 if (NewOp.getNode())
7202 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7203 } else if ((VT == MVT::v4i32 ||
7204 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7205 // FIXME: Figure out a cleaner way to do this.
7206 // Try to make use of movq to zero out the top part.
7207 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7208 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7209 if (NewOp.getNode()) {
7210 MVT NewVT = NewOp.getSimpleValueType();
7211 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7212 NewVT, true, false))
7213 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7214 DAG, Subtarget, dl);
7216 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7217 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7218 if (NewOp.getNode()) {
7219 MVT NewVT = NewOp.getSimpleValueType();
7220 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7221 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7222 DAG, Subtarget, dl);
7230 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7231 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7232 SDValue V1 = Op.getOperand(0);
7233 SDValue V2 = Op.getOperand(1);
7234 MVT VT = Op.getSimpleValueType();
7236 unsigned NumElems = VT.getVectorNumElements();
7237 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7238 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7239 bool V1IsSplat = false;
7240 bool V2IsSplat = false;
7241 bool HasSSE2 = Subtarget->hasSSE2();
7242 bool HasFp256 = Subtarget->hasFp256();
7243 bool HasInt256 = Subtarget->hasInt256();
7244 MachineFunction &MF = DAG.getMachineFunction();
7245 bool OptForSize = MF.getFunction()->getAttributes().
7246 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7248 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7250 if (V1IsUndef && V2IsUndef)
7251 return DAG.getUNDEF(VT);
7253 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7255 // Vector shuffle lowering takes 3 steps:
7257 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7258 // narrowing and commutation of operands should be handled.
7259 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7261 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7262 // so the shuffle can be broken into other shuffles and the legalizer can
7263 // try the lowering again.
7265 // The general idea is that no vector_shuffle operation should be left to
7266 // be matched during isel, all of them must be converted to a target specific
7269 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7270 // narrowing and commutation of operands should be handled. The actual code
7271 // doesn't include all of those, work in progress...
7272 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
7273 if (NewOp.getNode())
7276 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7278 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7279 // unpckh_undef). Only use pshufd if speed is more important than size.
7280 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7281 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7282 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7283 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7285 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7286 V2IsUndef && MayFoldVectorLoad(V1))
7287 return getMOVDDup(Op, dl, V1, DAG);
7289 if (isMOVHLPS_v_undef_Mask(M, VT))
7290 return getMOVHighToLow(Op, dl, DAG);
7292 // Use to match splats
7293 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7294 (VT == MVT::v2f64 || VT == MVT::v2i64))
7295 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7297 if (isPSHUFDMask(M, VT)) {
7298 // The actual implementation will match the mask in the if above and then
7299 // during isel it can match several different instructions, not only pshufd
7300 // as its name says, sad but true, emulate the behavior for now...
7301 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7302 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7304 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7306 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7307 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7309 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7310 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7313 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7317 if (isPALIGNRMask(M, VT, Subtarget))
7318 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7319 getShufflePALIGNRImmediate(SVOp),
7322 // Check if this can be converted into a logical shift.
7323 bool isLeft = false;
7326 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7327 if (isShift && ShVal.hasOneUse()) {
7328 // If the shifted value has multiple uses, it may be cheaper to use
7329 // v_set0 + movlhps or movhlps, etc.
7330 MVT EltVT = VT.getVectorElementType();
7331 ShAmt *= EltVT.getSizeInBits();
7332 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7335 if (isMOVLMask(M, VT)) {
7336 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7337 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7338 if (!isMOVLPMask(M, VT)) {
7339 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7340 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7342 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7343 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7347 // FIXME: fold these into legal mask.
7348 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7349 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7351 if (isMOVHLPSMask(M, VT))
7352 return getMOVHighToLow(Op, dl, DAG);
7354 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7355 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7357 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7358 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7360 if (isMOVLPMask(M, VT))
7361 return getMOVLP(Op, dl, DAG, HasSSE2);
7363 if (ShouldXformToMOVHLPS(M, VT) ||
7364 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7365 return CommuteVectorShuffle(SVOp, DAG);
7368 // No better options. Use a vshldq / vsrldq.
7369 MVT EltVT = VT.getVectorElementType();
7370 ShAmt *= EltVT.getSizeInBits();
7371 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7374 bool Commuted = false;
7375 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7376 // 1,1,1,1 -> v8i16 though.
7377 V1IsSplat = isSplatVector(V1.getNode());
7378 V2IsSplat = isSplatVector(V2.getNode());
7380 // Canonicalize the splat or undef, if present, to be on the RHS.
7381 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7382 CommuteVectorShuffleMask(M, NumElems);
7384 std::swap(V1IsSplat, V2IsSplat);
7388 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7389 // Shuffling low element of v1 into undef, just return v1.
7392 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7393 // the instruction selector will not match, so get a canonical MOVL with
7394 // swapped operands to undo the commute.
7395 return getMOVL(DAG, dl, VT, V2, V1);
7398 if (isUNPCKLMask(M, VT, HasInt256))
7399 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7401 if (isUNPCKHMask(M, VT, HasInt256))
7402 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7405 // Normalize mask so all entries that point to V2 points to its first
7406 // element then try to match unpck{h|l} again. If match, return a
7407 // new vector_shuffle with the corrected mask.p
7408 SmallVector<int, 8> NewMask(M.begin(), M.end());
7409 NormalizeMask(NewMask, NumElems);
7410 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7411 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7412 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7413 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7417 // Commute is back and try unpck* again.
7418 // FIXME: this seems wrong.
7419 CommuteVectorShuffleMask(M, NumElems);
7421 std::swap(V1IsSplat, V2IsSplat);
7424 if (isUNPCKLMask(M, VT, HasInt256))
7425 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7427 if (isUNPCKHMask(M, VT, HasInt256))
7428 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7431 // Normalize the node to match x86 shuffle ops if needed
7432 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
7433 return CommuteVectorShuffle(SVOp, DAG);
7435 // The checks below are all present in isShuffleMaskLegal, but they are
7436 // inlined here right now to enable us to directly emit target specific
7437 // nodes, and remove one by one until they don't return Op anymore.
7439 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7440 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7441 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7442 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7445 if (isPSHUFHWMask(M, VT, HasInt256))
7446 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7447 getShufflePSHUFHWImmediate(SVOp),
7450 if (isPSHUFLWMask(M, VT, HasInt256))
7451 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7452 getShufflePSHUFLWImmediate(SVOp),
7455 if (isSHUFPMask(M, VT))
7456 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7457 getShuffleSHUFImmediate(SVOp), DAG);
7459 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7460 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7461 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7462 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7464 //===--------------------------------------------------------------------===//
7465 // Generate target specific nodes for 128 or 256-bit shuffles only
7466 // supported in the AVX instruction set.
7469 // Handle VMOVDDUPY permutations
7470 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7471 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7473 // Handle VPERMILPS/D* permutations
7474 if (isVPERMILPMask(M, VT)) {
7475 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
7476 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7477 getShuffleSHUFImmediate(SVOp), DAG);
7478 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7479 getShuffleSHUFImmediate(SVOp), DAG);
7482 // Handle VPERM2F128/VPERM2I128 permutations
7483 if (isVPERM2X128Mask(M, VT, HasFp256))
7484 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7485 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7487 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7488 if (BlendOp.getNode())
7492 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
7493 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
7495 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
7496 VT.is512BitVector()) {
7497 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
7498 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
7499 SmallVector<SDValue, 16> permclMask;
7500 for (unsigned i = 0; i != NumElems; ++i) {
7501 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
7504 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT,
7505 &permclMask[0], NumElems);
7507 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7508 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7509 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7510 return DAG.getNode(X86ISD::VPERMV3, dl, VT,
7511 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1, V2);
7514 //===--------------------------------------------------------------------===//
7515 // Since no target specific shuffle was selected for this generic one,
7516 // lower it into other known shuffles. FIXME: this isn't true yet, but
7517 // this is the plan.
7520 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7521 if (VT == MVT::v8i16) {
7522 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7523 if (NewOp.getNode())
7527 if (VT == MVT::v16i8) {
7528 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
7529 if (NewOp.getNode())
7533 if (VT == MVT::v32i8) {
7534 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7535 if (NewOp.getNode())
7539 // Handle all 128-bit wide vectors with 4 elements, and match them with
7540 // several different shuffle types.
7541 if (NumElems == 4 && VT.is128BitVector())
7542 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7544 // Handle general 256-bit shuffles
7545 if (VT.is256BitVector())
7546 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7551 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7552 MVT VT = Op.getSimpleValueType();
7555 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
7558 if (VT.getSizeInBits() == 8) {
7559 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7560 Op.getOperand(0), Op.getOperand(1));
7561 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7562 DAG.getValueType(VT));
7563 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7566 if (VT.getSizeInBits() == 16) {
7567 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7568 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7570 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7571 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7572 DAG.getNode(ISD::BITCAST, dl,
7576 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7577 Op.getOperand(0), Op.getOperand(1));
7578 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7579 DAG.getValueType(VT));
7580 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7583 if (VT == MVT::f32) {
7584 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7585 // the result back to FR32 register. It's only worth matching if the
7586 // result has a single use which is a store or a bitcast to i32. And in
7587 // the case of a store, it's not worth it if the index is a constant 0,
7588 // because a MOVSSmr can be used instead, which is smaller and faster.
7589 if (!Op.hasOneUse())
7591 SDNode *User = *Op.getNode()->use_begin();
7592 if ((User->getOpcode() != ISD::STORE ||
7593 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7594 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7595 (User->getOpcode() != ISD::BITCAST ||
7596 User->getValueType(0) != MVT::i32))
7598 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7599 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7602 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7605 if (VT == MVT::i32 || VT == MVT::i64) {
7606 // ExtractPS/pextrq works with constant index.
7607 if (isa<ConstantSDNode>(Op.getOperand(1)))
7614 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7615 SelectionDAG &DAG) const {
7617 SDValue Vec = Op.getOperand(0);
7618 MVT VecVT = Vec.getSimpleValueType();
7619 SDValue Idx = Op.getOperand(1);
7620 if (!isa<ConstantSDNode>(Idx)) {
7621 if (VecVT.is512BitVector() ||
7622 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
7623 VecVT.getVectorElementType().getSizeInBits() == 32)) {
7626 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
7627 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
7628 MaskEltVT.getSizeInBits());
7630 if (Idx.getSimpleValueType() != MaskEltVT)
7631 if (Idx.getOpcode() == ISD::ZERO_EXTEND ||
7632 Idx.getOpcode() == ISD::SIGN_EXTEND)
7633 Idx = Idx.getOperand(0);
7634 assert(Idx.getSimpleValueType() == MaskEltVT &&
7635 "Unexpected index in insertelement");
7636 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
7637 getZeroVector(MaskVT, Subtarget, DAG, dl),
7638 Idx, DAG.getConstant(0, getPointerTy()));
7639 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
7640 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
7641 Perm, DAG.getConstant(0, getPointerTy()));
7646 // If this is a 256-bit vector result, first extract the 128-bit vector and
7647 // then extract the element from the 128-bit vector.
7648 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7650 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7651 // Get the 128-bit vector.
7652 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7653 MVT EltVT = VecVT.getVectorElementType();
7655 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7657 //if (IdxVal >= NumElems/2)
7658 // IdxVal -= NumElems/2;
7659 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7660 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7661 DAG.getConstant(IdxVal, MVT::i32));
7664 assert(VecVT.is128BitVector() && "Unexpected vector length");
7666 if (Subtarget->hasSSE41()) {
7667 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7672 MVT VT = Op.getSimpleValueType();
7673 // TODO: handle v16i8.
7674 if (VT.getSizeInBits() == 16) {
7675 SDValue Vec = Op.getOperand(0);
7676 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7678 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7679 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7680 DAG.getNode(ISD::BITCAST, dl,
7683 // Transform it so it match pextrw which produces a 32-bit result.
7684 MVT EltVT = MVT::i32;
7685 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7686 Op.getOperand(0), Op.getOperand(1));
7687 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7688 DAG.getValueType(VT));
7689 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7692 if (VT.getSizeInBits() == 32) {
7693 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7697 // SHUFPS the element to the lowest double word, then movss.
7698 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7699 MVT VVT = Op.getOperand(0).getSimpleValueType();
7700 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7701 DAG.getUNDEF(VVT), Mask);
7702 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7703 DAG.getIntPtrConstant(0));
7706 if (VT.getSizeInBits() == 64) {
7707 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7708 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7709 // to match extract_elt for f64.
7710 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7714 // UNPCKHPD the element to the lowest double word, then movsd.
7715 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7716 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7717 int Mask[2] = { 1, -1 };
7718 MVT VVT = Op.getOperand(0).getSimpleValueType();
7719 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7720 DAG.getUNDEF(VVT), Mask);
7721 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7722 DAG.getIntPtrConstant(0));
7728 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7729 MVT VT = Op.getSimpleValueType();
7730 MVT EltVT = VT.getVectorElementType();
7733 SDValue N0 = Op.getOperand(0);
7734 SDValue N1 = Op.getOperand(1);
7735 SDValue N2 = Op.getOperand(2);
7737 if (!VT.is128BitVector())
7740 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7741 isa<ConstantSDNode>(N2)) {
7743 if (VT == MVT::v8i16)
7744 Opc = X86ISD::PINSRW;
7745 else if (VT == MVT::v16i8)
7746 Opc = X86ISD::PINSRB;
7748 Opc = X86ISD::PINSRB;
7750 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7752 if (N1.getValueType() != MVT::i32)
7753 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7754 if (N2.getValueType() != MVT::i32)
7755 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7756 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7759 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7760 // Bits [7:6] of the constant are the source select. This will always be
7761 // zero here. The DAG Combiner may combine an extract_elt index into these
7762 // bits. For example (insert (extract, 3), 2) could be matched by putting
7763 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7764 // Bits [5:4] of the constant are the destination select. This is the
7765 // value of the incoming immediate.
7766 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7767 // combine either bitwise AND or insert of float 0.0 to set these bits.
7768 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7769 // Create this as a scalar to vector..
7770 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7771 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7774 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7775 // PINSR* works with constant index.
7782 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7783 MVT VT = Op.getSimpleValueType();
7784 MVT EltVT = VT.getVectorElementType();
7787 SDValue N0 = Op.getOperand(0);
7788 SDValue N1 = Op.getOperand(1);
7789 SDValue N2 = Op.getOperand(2);
7791 // If this is a 256-bit vector result, first extract the 128-bit vector,
7792 // insert the element into the extracted half and then place it back.
7793 if (VT.is256BitVector() || VT.is512BitVector()) {
7794 if (!isa<ConstantSDNode>(N2))
7797 // Get the desired 128-bit vector half.
7798 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7799 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7801 // Insert the element into the desired half.
7802 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7803 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7805 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7806 DAG.getConstant(IdxIn128, MVT::i32));
7808 // Insert the changed part back to the 256-bit vector
7809 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7812 if (Subtarget->hasSSE41())
7813 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7815 if (EltVT == MVT::i8)
7818 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7819 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7820 // as its second argument.
7821 if (N1.getValueType() != MVT::i32)
7822 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7823 if (N2.getValueType() != MVT::i32)
7824 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7825 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7830 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7832 MVT OpVT = Op.getSimpleValueType();
7834 // If this is a 256-bit vector result, first insert into a 128-bit
7835 // vector and then insert into the 256-bit vector.
7836 if (!OpVT.is128BitVector()) {
7837 // Insert into a 128-bit vector.
7838 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7839 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
7840 OpVT.getVectorNumElements() / SizeFactor);
7842 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7844 // Insert the 128-bit vector.
7845 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7848 if (OpVT == MVT::v1i64 &&
7849 Op.getOperand(0).getValueType() == MVT::i64)
7850 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7852 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7853 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7854 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7855 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7858 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7859 // a simple subregister reference or explicit instructions to grab
7860 // upper bits of a vector.
7861 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7862 SelectionDAG &DAG) {
7864 SDValue In = Op.getOperand(0);
7865 SDValue Idx = Op.getOperand(1);
7866 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7867 MVT ResVT = Op.getSimpleValueType();
7868 MVT InVT = In.getSimpleValueType();
7870 if (Subtarget->hasFp256()) {
7871 if (ResVT.is128BitVector() &&
7872 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7873 isa<ConstantSDNode>(Idx)) {
7874 return Extract128BitVector(In, IdxVal, DAG, dl);
7876 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7877 isa<ConstantSDNode>(Idx)) {
7878 return Extract256BitVector(In, IdxVal, DAG, dl);
7884 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7885 // simple superregister reference or explicit instructions to insert
7886 // the upper bits of a vector.
7887 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7888 SelectionDAG &DAG) {
7889 if (Subtarget->hasFp256()) {
7890 SDLoc dl(Op.getNode());
7891 SDValue Vec = Op.getNode()->getOperand(0);
7892 SDValue SubVec = Op.getNode()->getOperand(1);
7893 SDValue Idx = Op.getNode()->getOperand(2);
7895 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
7896 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
7897 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
7898 isa<ConstantSDNode>(Idx)) {
7899 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7900 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7903 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
7904 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
7905 isa<ConstantSDNode>(Idx)) {
7906 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7907 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7913 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7914 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7915 // one of the above mentioned nodes. It has to be wrapped because otherwise
7916 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7917 // be used to form addressing mode. These wrapped nodes will be selected
7920 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7921 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7923 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7925 unsigned char OpFlag = 0;
7926 unsigned WrapperKind = X86ISD::Wrapper;
7927 CodeModel::Model M = getTargetMachine().getCodeModel();
7929 if (Subtarget->isPICStyleRIPRel() &&
7930 (M == CodeModel::Small || M == CodeModel::Kernel))
7931 WrapperKind = X86ISD::WrapperRIP;
7932 else if (Subtarget->isPICStyleGOT())
7933 OpFlag = X86II::MO_GOTOFF;
7934 else if (Subtarget->isPICStyleStubPIC())
7935 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7937 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7939 CP->getOffset(), OpFlag);
7941 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7942 // With PIC, the address is actually $g + Offset.
7944 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7945 DAG.getNode(X86ISD::GlobalBaseReg,
7946 SDLoc(), getPointerTy()),
7953 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7954 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7956 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7958 unsigned char OpFlag = 0;
7959 unsigned WrapperKind = X86ISD::Wrapper;
7960 CodeModel::Model M = getTargetMachine().getCodeModel();
7962 if (Subtarget->isPICStyleRIPRel() &&
7963 (M == CodeModel::Small || M == CodeModel::Kernel))
7964 WrapperKind = X86ISD::WrapperRIP;
7965 else if (Subtarget->isPICStyleGOT())
7966 OpFlag = X86II::MO_GOTOFF;
7967 else if (Subtarget->isPICStyleStubPIC())
7968 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7970 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7973 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7975 // With PIC, the address is actually $g + Offset.
7977 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7978 DAG.getNode(X86ISD::GlobalBaseReg,
7979 SDLoc(), getPointerTy()),
7986 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7987 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7989 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7991 unsigned char OpFlag = 0;
7992 unsigned WrapperKind = X86ISD::Wrapper;
7993 CodeModel::Model M = getTargetMachine().getCodeModel();
7995 if (Subtarget->isPICStyleRIPRel() &&
7996 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7997 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7998 OpFlag = X86II::MO_GOTPCREL;
7999 WrapperKind = X86ISD::WrapperRIP;
8000 } else if (Subtarget->isPICStyleGOT()) {
8001 OpFlag = X86II::MO_GOT;
8002 } else if (Subtarget->isPICStyleStubPIC()) {
8003 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
8004 } else if (Subtarget->isPICStyleStubNoDynamic()) {
8005 OpFlag = X86II::MO_DARWIN_NONLAZY;
8008 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
8011 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8013 // With PIC, the address is actually $g + Offset.
8014 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
8015 !Subtarget->is64Bit()) {
8016 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8017 DAG.getNode(X86ISD::GlobalBaseReg,
8018 SDLoc(), getPointerTy()),
8022 // For symbols that require a load from a stub to get the address, emit the
8024 if (isGlobalStubReference(OpFlag))
8025 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
8026 MachinePointerInfo::getGOT(), false, false, false, 0);
8032 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
8033 // Create the TargetBlockAddressAddress node.
8034 unsigned char OpFlags =
8035 Subtarget->ClassifyBlockAddressReference();
8036 CodeModel::Model M = getTargetMachine().getCodeModel();
8037 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
8038 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
8040 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
8043 if (Subtarget->isPICStyleRIPRel() &&
8044 (M == CodeModel::Small || M == CodeModel::Kernel))
8045 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8047 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8049 // With PIC, the address is actually $g + Offset.
8050 if (isGlobalRelativeToPICBase(OpFlags)) {
8051 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8052 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8060 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
8061 int64_t Offset, SelectionDAG &DAG) const {
8062 // Create the TargetGlobalAddress node, folding in the constant
8063 // offset if it is legal.
8064 unsigned char OpFlags =
8065 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
8066 CodeModel::Model M = getTargetMachine().getCodeModel();
8068 if (OpFlags == X86II::MO_NO_FLAG &&
8069 X86::isOffsetSuitableForCodeModel(Offset, M)) {
8070 // A direct static reference to a global.
8071 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
8074 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
8077 if (Subtarget->isPICStyleRIPRel() &&
8078 (M == CodeModel::Small || M == CodeModel::Kernel))
8079 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
8081 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
8083 // With PIC, the address is actually $g + Offset.
8084 if (isGlobalRelativeToPICBase(OpFlags)) {
8085 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
8086 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
8090 // For globals that require a load from a stub to get the address, emit the
8092 if (isGlobalStubReference(OpFlags))
8093 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
8094 MachinePointerInfo::getGOT(), false, false, false, 0);
8096 // If there was a non-zero offset that we didn't fold, create an explicit
8099 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
8100 DAG.getConstant(Offset, getPointerTy()));
8106 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
8107 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
8108 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
8109 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
8113 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
8114 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
8115 unsigned char OperandFlags, bool LocalDynamic = false) {
8116 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8117 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8119 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8120 GA->getValueType(0),
8124 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
8128 SDValue Ops[] = { Chain, TGA, *InFlag };
8129 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8131 SDValue Ops[] = { Chain, TGA };
8132 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
8135 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
8136 MFI->setAdjustsStack(true);
8138 SDValue Flag = Chain.getValue(1);
8139 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
8142 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
8144 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8147 SDLoc dl(GA); // ? function entry point might be better
8148 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8149 DAG.getNode(X86ISD::GlobalBaseReg,
8150 SDLoc(), PtrVT), InFlag);
8151 InFlag = Chain.getValue(1);
8153 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
8156 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
8158 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8160 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
8161 X86::RAX, X86II::MO_TLSGD);
8164 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
8170 // Get the start address of the TLS block for this module.
8171 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
8172 .getInfo<X86MachineFunctionInfo>();
8173 MFI->incNumLocalDynamicTLSAccesses();
8177 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
8178 X86II::MO_TLSLD, /*LocalDynamic=*/true);
8181 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
8182 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
8183 InFlag = Chain.getValue(1);
8184 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
8185 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
8188 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
8192 unsigned char OperandFlags = X86II::MO_DTPOFF;
8193 unsigned WrapperKind = X86ISD::Wrapper;
8194 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8195 GA->getValueType(0),
8196 GA->getOffset(), OperandFlags);
8197 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8199 // Add x@dtpoff with the base.
8200 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
8203 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
8204 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
8205 const EVT PtrVT, TLSModel::Model model,
8206 bool is64Bit, bool isPIC) {
8209 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8210 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8211 is64Bit ? 257 : 256));
8213 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
8214 DAG.getIntPtrConstant(0),
8215 MachinePointerInfo(Ptr),
8216 false, false, false, 0);
8218 unsigned char OperandFlags = 0;
8219 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8221 unsigned WrapperKind = X86ISD::Wrapper;
8222 if (model == TLSModel::LocalExec) {
8223 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8224 } else if (model == TLSModel::InitialExec) {
8226 OperandFlags = X86II::MO_GOTTPOFF;
8227 WrapperKind = X86ISD::WrapperRIP;
8229 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8232 llvm_unreachable("Unexpected model");
8235 // emit "addl x@ntpoff,%eax" (local exec)
8236 // or "addl x@indntpoff,%eax" (initial exec)
8237 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8238 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8239 GA->getValueType(0),
8240 GA->getOffset(), OperandFlags);
8241 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8243 if (model == TLSModel::InitialExec) {
8244 if (isPIC && !is64Bit) {
8245 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8246 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8250 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8251 MachinePointerInfo::getGOT(), false, false, false,
8255 // The address of the thread local variable is the add of the thread
8256 // pointer with the offset of the variable.
8257 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8261 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8263 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8264 const GlobalValue *GV = GA->getGlobal();
8266 if (Subtarget->isTargetELF()) {
8267 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8270 case TLSModel::GeneralDynamic:
8271 if (Subtarget->is64Bit())
8272 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8273 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8274 case TLSModel::LocalDynamic:
8275 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8276 Subtarget->is64Bit());
8277 case TLSModel::InitialExec:
8278 case TLSModel::LocalExec:
8279 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8280 Subtarget->is64Bit(),
8281 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8283 llvm_unreachable("Unknown TLS model.");
8286 if (Subtarget->isTargetDarwin()) {
8287 // Darwin only has one model of TLS. Lower to that.
8288 unsigned char OpFlag = 0;
8289 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8290 X86ISD::WrapperRIP : X86ISD::Wrapper;
8292 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8294 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8295 !Subtarget->is64Bit();
8297 OpFlag = X86II::MO_TLVP_PIC_BASE;
8299 OpFlag = X86II::MO_TLVP;
8301 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8302 GA->getValueType(0),
8303 GA->getOffset(), OpFlag);
8304 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8306 // With PIC32, the address is actually $g + Offset.
8308 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8309 DAG.getNode(X86ISD::GlobalBaseReg,
8310 SDLoc(), getPointerTy()),
8313 // Lowering the machine isd will make sure everything is in the right
8315 SDValue Chain = DAG.getEntryNode();
8316 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8317 SDValue Args[] = { Chain, Offset };
8318 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8320 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8321 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8322 MFI->setAdjustsStack(true);
8324 // And our return value (tls address) is in the standard call return value
8326 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8327 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8331 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8332 // Just use the implicit TLS architecture
8333 // Need to generate someting similar to:
8334 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8336 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8337 // mov rcx, qword [rdx+rcx*8]
8338 // mov eax, .tls$:tlsvar
8339 // [rax+rcx] contains the address
8340 // Windows 64bit: gs:0x58
8341 // Windows 32bit: fs:__tls_array
8343 // If GV is an alias then use the aliasee for determining
8344 // thread-localness.
8345 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8346 GV = GA->resolveAliasedGlobal(false);
8348 SDValue Chain = DAG.getEntryNode();
8350 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8351 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8352 // use its literal value of 0x2C.
8353 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8354 ? Type::getInt8PtrTy(*DAG.getContext(),
8356 : Type::getInt32PtrTy(*DAG.getContext(),
8359 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8360 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8361 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8363 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8364 MachinePointerInfo(Ptr),
8365 false, false, false, 0);
8367 // Load the _tls_index variable
8368 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8369 if (Subtarget->is64Bit())
8370 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8371 IDX, MachinePointerInfo(), MVT::i32,
8374 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8375 false, false, false, 0);
8377 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8379 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8381 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8382 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8383 false, false, false, 0);
8385 // Get the offset of start of .tls section
8386 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8387 GA->getValueType(0),
8388 GA->getOffset(), X86II::MO_SECREL);
8389 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8391 // The address of the thread local variable is the add of the thread
8392 // pointer with the offset of the variable.
8393 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8396 llvm_unreachable("TLS not implemented for this target.");
8399 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8400 /// and take a 2 x i32 value to shift plus a shift amount.
8401 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8402 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8403 EVT VT = Op.getValueType();
8404 unsigned VTBits = VT.getSizeInBits();
8406 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8407 SDValue ShOpLo = Op.getOperand(0);
8408 SDValue ShOpHi = Op.getOperand(1);
8409 SDValue ShAmt = Op.getOperand(2);
8410 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8411 DAG.getConstant(VTBits - 1, MVT::i8))
8412 : DAG.getConstant(0, VT);
8415 if (Op.getOpcode() == ISD::SHL_PARTS) {
8416 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8417 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8419 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8420 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8423 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8424 DAG.getConstant(VTBits, MVT::i8));
8425 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8426 AndNode, DAG.getConstant(0, MVT::i8));
8429 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8430 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8431 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8433 if (Op.getOpcode() == ISD::SHL_PARTS) {
8434 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8435 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8437 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8438 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8441 SDValue Ops[2] = { Lo, Hi };
8442 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8445 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8446 SelectionDAG &DAG) const {
8447 EVT SrcVT = Op.getOperand(0).getValueType();
8449 if (SrcVT.isVector())
8452 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8453 "Unknown SINT_TO_FP to lower!");
8455 // These are really Legal; return the operand so the caller accepts it as
8457 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8459 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8460 Subtarget->is64Bit()) {
8465 unsigned Size = SrcVT.getSizeInBits()/8;
8466 MachineFunction &MF = DAG.getMachineFunction();
8467 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8468 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8469 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8471 MachinePointerInfo::getFixedStack(SSFI),
8473 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8476 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8478 SelectionDAG &DAG) const {
8482 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8484 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8486 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8488 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8490 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8491 MachineMemOperand *MMO;
8493 int SSFI = FI->getIndex();
8495 DAG.getMachineFunction()
8496 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8497 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8499 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8500 StackSlot = StackSlot.getOperand(1);
8502 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8503 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8505 Tys, Ops, array_lengthof(Ops),
8509 Chain = Result.getValue(1);
8510 SDValue InFlag = Result.getValue(2);
8512 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8513 // shouldn't be necessary except that RFP cannot be live across
8514 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8515 MachineFunction &MF = DAG.getMachineFunction();
8516 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8517 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8518 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8519 Tys = DAG.getVTList(MVT::Other);
8521 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8523 MachineMemOperand *MMO =
8524 DAG.getMachineFunction()
8525 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8526 MachineMemOperand::MOStore, SSFISize, SSFISize);
8528 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8529 Ops, array_lengthof(Ops),
8530 Op.getValueType(), MMO);
8531 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8532 MachinePointerInfo::getFixedStack(SSFI),
8533 false, false, false, 0);
8539 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8540 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8541 SelectionDAG &DAG) const {
8542 // This algorithm is not obvious. Here it is what we're trying to output:
8545 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8546 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8550 pshufd $0x4e, %xmm0, %xmm1
8556 LLVMContext *Context = DAG.getContext();
8558 // Build some magic constants.
8559 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8560 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8561 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8563 SmallVector<Constant*,2> CV1;
8565 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8566 APInt(64, 0x4330000000000000ULL))));
8568 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8569 APInt(64, 0x4530000000000000ULL))));
8570 Constant *C1 = ConstantVector::get(CV1);
8571 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8573 // Load the 64-bit value into an XMM register.
8574 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8576 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8577 MachinePointerInfo::getConstantPool(),
8578 false, false, false, 16);
8579 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8580 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8583 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8584 MachinePointerInfo::getConstantPool(),
8585 false, false, false, 16);
8586 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8587 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8590 if (Subtarget->hasSSE3()) {
8591 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8592 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8594 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8595 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8597 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8598 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8602 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8603 DAG.getIntPtrConstant(0));
8606 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8607 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8608 SelectionDAG &DAG) const {
8610 // FP constant to bias correct the final result.
8611 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8614 // Load the 32-bit value into an XMM register.
8615 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8618 // Zero out the upper parts of the register.
8619 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8621 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8622 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8623 DAG.getIntPtrConstant(0));
8625 // Or the load with the bias.
8626 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8627 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8628 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8630 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8631 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8632 MVT::v2f64, Bias)));
8633 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8634 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8635 DAG.getIntPtrConstant(0));
8637 // Subtract the bias.
8638 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8640 // Handle final rounding.
8641 EVT DestVT = Op.getValueType();
8643 if (DestVT.bitsLT(MVT::f64))
8644 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8645 DAG.getIntPtrConstant(0));
8646 if (DestVT.bitsGT(MVT::f64))
8647 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8649 // Handle final rounding.
8653 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8654 SelectionDAG &DAG) const {
8655 SDValue N0 = Op.getOperand(0);
8656 EVT SVT = N0.getValueType();
8659 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8660 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8661 "Custom UINT_TO_FP is not supported!");
8663 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8664 SVT.getVectorNumElements());
8665 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8666 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8669 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8670 SelectionDAG &DAG) const {
8671 SDValue N0 = Op.getOperand(0);
8674 if (Op.getValueType().isVector())
8675 return lowerUINT_TO_FP_vec(Op, DAG);
8677 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8678 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8679 // the optimization here.
8680 if (DAG.SignBitIsZero(N0))
8681 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8683 EVT SrcVT = N0.getValueType();
8684 EVT DstVT = Op.getValueType();
8685 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8686 return LowerUINT_TO_FP_i64(Op, DAG);
8687 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8688 return LowerUINT_TO_FP_i32(Op, DAG);
8689 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8692 // Make a 64-bit buffer, and use it to build an FILD.
8693 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8694 if (SrcVT == MVT::i32) {
8695 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8696 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8697 getPointerTy(), StackSlot, WordOff);
8698 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8699 StackSlot, MachinePointerInfo(),
8701 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8702 OffsetSlot, MachinePointerInfo(),
8704 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8708 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8709 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8710 StackSlot, MachinePointerInfo(),
8712 // For i64 source, we need to add the appropriate power of 2 if the input
8713 // was negative. This is the same as the optimization in
8714 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8715 // we must be careful to do the computation in x87 extended precision, not
8716 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8717 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8718 MachineMemOperand *MMO =
8719 DAG.getMachineFunction()
8720 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8721 MachineMemOperand::MOLoad, 8, 8);
8723 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8724 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8725 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8726 array_lengthof(Ops), MVT::i64, MMO);
8728 APInt FF(32, 0x5F800000ULL);
8730 // Check whether the sign bit is set.
8731 SDValue SignSet = DAG.getSetCC(dl,
8732 getSetCCResultType(*DAG.getContext(), MVT::i64),
8733 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8736 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8737 SDValue FudgePtr = DAG.getConstantPool(
8738 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8741 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8742 SDValue Zero = DAG.getIntPtrConstant(0);
8743 SDValue Four = DAG.getIntPtrConstant(4);
8744 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8746 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8748 // Load the value out, extending it from f32 to f80.
8749 // FIXME: Avoid the extend by constructing the right constant pool?
8750 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8751 FudgePtr, MachinePointerInfo::getConstantPool(),
8752 MVT::f32, false, false, 4);
8753 // Extend everything to 80 bits to force it to be done on x87.
8754 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8755 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8758 std::pair<SDValue,SDValue>
8759 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8760 bool IsSigned, bool IsReplace) const {
8763 EVT DstTy = Op.getValueType();
8765 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8766 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8770 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8771 DstTy.getSimpleVT() >= MVT::i16 &&
8772 "Unknown FP_TO_INT to lower!");
8774 // These are really Legal.
8775 if (DstTy == MVT::i32 &&
8776 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8777 return std::make_pair(SDValue(), SDValue());
8778 if (Subtarget->is64Bit() &&
8779 DstTy == MVT::i64 &&
8780 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8781 return std::make_pair(SDValue(), SDValue());
8783 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8784 // stack slot, or into the FTOL runtime function.
8785 MachineFunction &MF = DAG.getMachineFunction();
8786 unsigned MemSize = DstTy.getSizeInBits()/8;
8787 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8788 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8791 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8792 Opc = X86ISD::WIN_FTOL;
8794 switch (DstTy.getSimpleVT().SimpleTy) {
8795 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8796 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8797 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8798 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8801 SDValue Chain = DAG.getEntryNode();
8802 SDValue Value = Op.getOperand(0);
8803 EVT TheVT = Op.getOperand(0).getValueType();
8804 // FIXME This causes a redundant load/store if the SSE-class value is already
8805 // in memory, such as if it is on the callstack.
8806 if (isScalarFPTypeInSSEReg(TheVT)) {
8807 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8808 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8809 MachinePointerInfo::getFixedStack(SSFI),
8811 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8813 Chain, StackSlot, DAG.getValueType(TheVT)
8816 MachineMemOperand *MMO =
8817 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8818 MachineMemOperand::MOLoad, MemSize, MemSize);
8819 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8820 array_lengthof(Ops), DstTy, MMO);
8821 Chain = Value.getValue(1);
8822 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8823 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8826 MachineMemOperand *MMO =
8827 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8828 MachineMemOperand::MOStore, MemSize, MemSize);
8830 if (Opc != X86ISD::WIN_FTOL) {
8831 // Build the FP_TO_INT*_IN_MEM
8832 SDValue Ops[] = { Chain, Value, StackSlot };
8833 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8834 Ops, array_lengthof(Ops), DstTy,
8836 return std::make_pair(FIST, StackSlot);
8838 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8839 DAG.getVTList(MVT::Other, MVT::Glue),
8841 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8842 MVT::i32, ftol.getValue(1));
8843 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8844 MVT::i32, eax.getValue(2));
8845 SDValue Ops[] = { eax, edx };
8846 SDValue pair = IsReplace
8847 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8848 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8849 return std::make_pair(pair, SDValue());
8853 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8854 const X86Subtarget *Subtarget) {
8855 MVT VT = Op->getSimpleValueType(0);
8856 SDValue In = Op->getOperand(0);
8857 MVT InVT = In.getSimpleValueType();
8860 // Optimize vectors in AVX mode:
8863 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8864 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8865 // Concat upper and lower parts.
8868 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8869 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8870 // Concat upper and lower parts.
8873 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8874 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8877 if (Subtarget->hasInt256())
8878 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8880 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8881 SDValue Undef = DAG.getUNDEF(InVT);
8882 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8883 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8884 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8886 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8887 VT.getVectorNumElements()/2);
8889 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8890 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8892 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8895 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
8896 SelectionDAG &DAG) {
8897 MVT VT = Op->getValueType(0).getSimpleVT();
8898 SDValue In = Op->getOperand(0);
8899 MVT InVT = In.getValueType().getSimpleVT();
8901 unsigned int NumElts = VT.getVectorNumElements();
8902 if (NumElts != 8 && NumElts != 16)
8905 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
8906 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8908 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
8909 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8910 // Now we have only mask extension
8911 assert(InVT.getVectorElementType() == MVT::i1);
8912 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
8913 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8914 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
8915 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8916 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8917 MachinePointerInfo::getConstantPool(),
8918 false, false, false, Alignment);
8920 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
8921 if (VT.is512BitVector())
8923 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
8926 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8927 SelectionDAG &DAG) {
8928 if (Subtarget->hasFp256()) {
8929 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8937 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
8938 SelectionDAG &DAG) {
8940 MVT VT = Op.getSimpleValueType();
8941 SDValue In = Op.getOperand(0);
8942 MVT SVT = In.getSimpleValueType();
8944 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
8945 return LowerZERO_EXTEND_AVX512(Op, DAG);
8947 if (Subtarget->hasFp256()) {
8948 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8953 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8954 VT.getVectorNumElements() != SVT.getVectorNumElements())
8957 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8959 // AVX2 has better support of integer extending.
8960 if (Subtarget->hasInt256())
8961 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8963 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8964 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8965 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8966 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8967 DAG.getUNDEF(MVT::v8i16),
8970 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8973 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8975 MVT VT = Op.getSimpleValueType();
8976 SDValue In = Op.getOperand(0);
8977 MVT InVT = In.getSimpleValueType();
8978 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
8979 "Invalid TRUNCATE operation");
8981 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
8982 if (VT.getVectorElementType().getSizeInBits() >=8)
8983 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
8985 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
8986 unsigned NumElts = InVT.getVectorNumElements();
8987 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
8988 if (InVT.getSizeInBits() < 512) {
8989 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
8990 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
8993 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
8994 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
8995 SDValue CP = DAG.getConstantPool(C, getPointerTy());
8996 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
8997 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
8998 MachinePointerInfo::getConstantPool(),
8999 false, false, false, Alignment);
9000 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
9001 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
9002 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
9005 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
9006 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
9007 if (Subtarget->hasInt256()) {
9008 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
9009 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
9010 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
9012 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
9013 DAG.getIntPtrConstant(0));
9016 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
9017 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9018 DAG.getIntPtrConstant(0));
9019 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9020 DAG.getIntPtrConstant(2));
9022 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9023 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9026 static const int ShufMask1[] = {0, 2, 0, 0};
9027 SDValue Undef = DAG.getUNDEF(VT);
9028 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
9029 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
9031 // The MOVLHPS mask:
9032 static const int ShufMask2[] = {0, 1, 4, 5};
9033 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
9036 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
9037 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
9038 if (Subtarget->hasInt256()) {
9039 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
9041 SmallVector<SDValue,32> pshufbMask;
9042 for (unsigned i = 0; i < 2; ++i) {
9043 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
9044 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
9045 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
9046 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
9047 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
9048 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
9049 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
9050 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
9051 for (unsigned j = 0; j < 8; ++j)
9052 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
9054 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
9055 &pshufbMask[0], 32);
9056 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
9057 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
9059 static const int ShufMask[] = {0, 2, -1, -1};
9060 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
9062 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
9063 DAG.getIntPtrConstant(0));
9064 return DAG.getNode(ISD::BITCAST, DL, VT, In);
9067 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9068 DAG.getIntPtrConstant(0));
9070 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
9071 DAG.getIntPtrConstant(4));
9073 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
9074 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
9077 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
9078 -1, -1, -1, -1, -1, -1, -1, -1};
9080 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
9081 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
9082 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
9084 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
9085 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
9087 // The MOVLHPS Mask:
9088 static const int ShufMask2[] = {0, 1, 4, 5};
9089 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
9090 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
9093 // Handle truncation of V256 to V128 using shuffles.
9094 if (!VT.is128BitVector() || !InVT.is256BitVector())
9097 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
9099 unsigned NumElems = VT.getVectorNumElements();
9100 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
9103 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
9104 // Prepare truncation shuffle mask
9105 for (unsigned i = 0; i != NumElems; ++i)
9107 SDValue V = DAG.getVectorShuffle(NVT, DL,
9108 DAG.getNode(ISD::BITCAST, DL, NVT, In),
9109 DAG.getUNDEF(NVT), &MaskVec[0]);
9110 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
9111 DAG.getIntPtrConstant(0));
9114 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
9115 SelectionDAG &DAG) const {
9116 MVT VT = Op.getSimpleValueType();
9117 if (VT.isVector()) {
9118 if (VT == MVT::v8i16)
9119 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
9120 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
9121 MVT::v8i32, Op.getOperand(0)));
9125 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9126 /*IsSigned=*/ true, /*IsReplace=*/ false);
9127 SDValue FIST = Vals.first, StackSlot = Vals.second;
9128 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
9129 if (FIST.getNode() == 0) return Op;
9131 if (StackSlot.getNode())
9133 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9134 FIST, StackSlot, MachinePointerInfo(),
9135 false, false, false, 0);
9137 // The node is the result.
9141 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
9142 SelectionDAG &DAG) const {
9143 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
9144 /*IsSigned=*/ false, /*IsReplace=*/ false);
9145 SDValue FIST = Vals.first, StackSlot = Vals.second;
9146 assert(FIST.getNode() && "Unexpected failure");
9148 if (StackSlot.getNode())
9150 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
9151 FIST, StackSlot, MachinePointerInfo(),
9152 false, false, false, 0);
9154 // The node is the result.
9158 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
9160 MVT VT = Op.getSimpleValueType();
9161 SDValue In = Op.getOperand(0);
9162 MVT SVT = In.getSimpleValueType();
9164 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
9166 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
9167 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
9168 In, DAG.getUNDEF(SVT)));
9171 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
9172 LLVMContext *Context = DAG.getContext();
9174 MVT VT = Op.getSimpleValueType();
9176 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9177 if (VT.isVector()) {
9178 EltVT = VT.getVectorElementType();
9179 NumElts = VT.getVectorNumElements();
9182 if (EltVT == MVT::f64)
9183 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9184 APInt(64, ~(1ULL << 63))));
9186 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9187 APInt(32, ~(1U << 31))));
9188 C = ConstantVector::getSplat(NumElts, C);
9189 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9190 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9191 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9192 MachinePointerInfo::getConstantPool(),
9193 false, false, false, Alignment);
9194 if (VT.isVector()) {
9195 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9196 return DAG.getNode(ISD::BITCAST, dl, VT,
9197 DAG.getNode(ISD::AND, dl, ANDVT,
9198 DAG.getNode(ISD::BITCAST, dl, ANDVT,
9200 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
9202 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
9205 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
9206 LLVMContext *Context = DAG.getContext();
9208 MVT VT = Op.getSimpleValueType();
9210 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
9211 if (VT.isVector()) {
9212 EltVT = VT.getVectorElementType();
9213 NumElts = VT.getVectorNumElements();
9216 if (EltVT == MVT::f64)
9217 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
9218 APInt(64, 1ULL << 63)));
9220 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
9221 APInt(32, 1U << 31)));
9222 C = ConstantVector::getSplat(NumElts, C);
9223 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
9224 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
9225 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9226 MachinePointerInfo::getConstantPool(),
9227 false, false, false, Alignment);
9228 if (VT.isVector()) {
9229 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
9230 return DAG.getNode(ISD::BITCAST, dl, VT,
9231 DAG.getNode(ISD::XOR, dl, XORVT,
9232 DAG.getNode(ISD::BITCAST, dl, XORVT,
9234 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
9237 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
9240 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
9241 LLVMContext *Context = DAG.getContext();
9242 SDValue Op0 = Op.getOperand(0);
9243 SDValue Op1 = Op.getOperand(1);
9245 MVT VT = Op.getSimpleValueType();
9246 MVT SrcVT = Op1.getSimpleValueType();
9248 // If second operand is smaller, extend it first.
9249 if (SrcVT.bitsLT(VT)) {
9250 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
9253 // And if it is bigger, shrink it first.
9254 if (SrcVT.bitsGT(VT)) {
9255 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
9259 // At this point the operands and the result should have the same
9260 // type, and that won't be f80 since that is not custom lowered.
9262 // First get the sign bit of second operand.
9263 SmallVector<Constant*,4> CV;
9264 if (SrcVT == MVT::f64) {
9265 const fltSemantics &Sem = APFloat::IEEEdouble;
9266 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9267 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9269 const fltSemantics &Sem = APFloat::IEEEsingle;
9270 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9271 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9272 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9273 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9275 Constant *C = ConstantVector::get(CV);
9276 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9277 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9278 MachinePointerInfo::getConstantPool(),
9279 false, false, false, 16);
9280 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9282 // Shift sign bit right or left if the two operands have different types.
9283 if (SrcVT.bitsGT(VT)) {
9284 // Op0 is MVT::f32, Op1 is MVT::f64.
9285 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9286 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9287 DAG.getConstant(32, MVT::i32));
9288 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9289 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9290 DAG.getIntPtrConstant(0));
9293 // Clear first operand sign bit.
9295 if (VT == MVT::f64) {
9296 const fltSemantics &Sem = APFloat::IEEEdouble;
9297 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9298 APInt(64, ~(1ULL << 63)))));
9299 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9301 const fltSemantics &Sem = APFloat::IEEEsingle;
9302 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9303 APInt(32, ~(1U << 31)))));
9304 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9305 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9306 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9308 C = ConstantVector::get(CV);
9309 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9310 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9311 MachinePointerInfo::getConstantPool(),
9312 false, false, false, 16);
9313 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9315 // Or the value with the sign bit.
9316 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9319 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9320 SDValue N0 = Op.getOperand(0);
9322 MVT VT = Op.getSimpleValueType();
9324 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9325 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9326 DAG.getConstant(1, VT));
9327 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9330 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9332 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
9333 SelectionDAG &DAG) {
9334 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9336 if (!Subtarget->hasSSE41())
9339 if (!Op->hasOneUse())
9342 SDNode *N = Op.getNode();
9345 SmallVector<SDValue, 8> Opnds;
9346 DenseMap<SDValue, unsigned> VecInMap;
9347 EVT VT = MVT::Other;
9349 // Recognize a special case where a vector is casted into wide integer to
9351 Opnds.push_back(N->getOperand(0));
9352 Opnds.push_back(N->getOperand(1));
9354 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9355 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9356 // BFS traverse all OR'd operands.
9357 if (I->getOpcode() == ISD::OR) {
9358 Opnds.push_back(I->getOperand(0));
9359 Opnds.push_back(I->getOperand(1));
9360 // Re-evaluate the number of nodes to be traversed.
9361 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9365 // Quit if a non-EXTRACT_VECTOR_ELT
9366 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9369 // Quit if without a constant index.
9370 SDValue Idx = I->getOperand(1);
9371 if (!isa<ConstantSDNode>(Idx))
9374 SDValue ExtractedFromVec = I->getOperand(0);
9375 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9376 if (M == VecInMap.end()) {
9377 VT = ExtractedFromVec.getValueType();
9378 // Quit if not 128/256-bit vector.
9379 if (!VT.is128BitVector() && !VT.is256BitVector())
9381 // Quit if not the same type.
9382 if (VecInMap.begin() != VecInMap.end() &&
9383 VT != VecInMap.begin()->first.getValueType())
9385 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9387 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9390 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9391 "Not extracted from 128-/256-bit vector.");
9393 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9394 SmallVector<SDValue, 8> VecIns;
9396 for (DenseMap<SDValue, unsigned>::const_iterator
9397 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9398 // Quit if not all elements are used.
9399 if (I->second != FullMask)
9401 VecIns.push_back(I->first);
9404 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9406 // Cast all vectors into TestVT for PTEST.
9407 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9408 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9410 // If more than one full vectors are evaluated, OR them first before PTEST.
9411 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9412 // Each iteration will OR 2 nodes and append the result until there is only
9413 // 1 node left, i.e. the final OR'd value of all vectors.
9414 SDValue LHS = VecIns[Slot];
9415 SDValue RHS = VecIns[Slot + 1];
9416 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9419 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9420 VecIns.back(), VecIns.back());
9423 /// Emit nodes that will be selected as "test Op0,Op0", or something
9425 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9426 SelectionDAG &DAG) const {
9429 // CF and OF aren't always set the way we want. Determine which
9430 // of these we need.
9431 bool NeedCF = false;
9432 bool NeedOF = false;
9435 case X86::COND_A: case X86::COND_AE:
9436 case X86::COND_B: case X86::COND_BE:
9439 case X86::COND_G: case X86::COND_GE:
9440 case X86::COND_L: case X86::COND_LE:
9441 case X86::COND_O: case X86::COND_NO:
9446 // See if we can use the EFLAGS value from the operand instead of
9447 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9448 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9449 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9450 // Emit a CMP with 0, which is the TEST pattern.
9451 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9452 DAG.getConstant(0, Op.getValueType()));
9454 unsigned Opcode = 0;
9455 unsigned NumOperands = 0;
9457 // Truncate operations may prevent the merge of the SETCC instruction
9458 // and the arithmetic instruction before it. Attempt to truncate the operands
9459 // of the arithmetic instruction and use a reduced bit-width instruction.
9460 bool NeedTruncation = false;
9461 SDValue ArithOp = Op;
9462 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9463 SDValue Arith = Op->getOperand(0);
9464 // Both the trunc and the arithmetic op need to have one user each.
9465 if (Arith->hasOneUse())
9466 switch (Arith.getOpcode()) {
9473 NeedTruncation = true;
9479 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9480 // which may be the result of a CAST. We use the variable 'Op', which is the
9481 // non-casted variable when we check for possible users.
9482 switch (ArithOp.getOpcode()) {
9484 // Due to an isel shortcoming, be conservative if this add is likely to be
9485 // selected as part of a load-modify-store instruction. When the root node
9486 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9487 // uses of other nodes in the match, such as the ADD in this case. This
9488 // leads to the ADD being left around and reselected, with the result being
9489 // two adds in the output. Alas, even if none our users are stores, that
9490 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9491 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9492 // climbing the DAG back to the root, and it doesn't seem to be worth the
9494 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9495 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9496 if (UI->getOpcode() != ISD::CopyToReg &&
9497 UI->getOpcode() != ISD::SETCC &&
9498 UI->getOpcode() != ISD::STORE)
9501 if (ConstantSDNode *C =
9502 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9503 // An add of one will be selected as an INC.
9504 if (C->getAPIntValue() == 1) {
9505 Opcode = X86ISD::INC;
9510 // An add of negative one (subtract of one) will be selected as a DEC.
9511 if (C->getAPIntValue().isAllOnesValue()) {
9512 Opcode = X86ISD::DEC;
9518 // Otherwise use a regular EFLAGS-setting add.
9519 Opcode = X86ISD::ADD;
9523 // If the primary and result isn't used, don't bother using X86ISD::AND,
9524 // because a TEST instruction will be better.
9525 bool NonFlagUse = false;
9526 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9527 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9529 unsigned UOpNo = UI.getOperandNo();
9530 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9531 // Look pass truncate.
9532 UOpNo = User->use_begin().getOperandNo();
9533 User = *User->use_begin();
9536 if (User->getOpcode() != ISD::BRCOND &&
9537 User->getOpcode() != ISD::SETCC &&
9538 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9551 // Due to the ISEL shortcoming noted above, be conservative if this op is
9552 // likely to be selected as part of a load-modify-store instruction.
9553 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9554 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9555 if (UI->getOpcode() == ISD::STORE)
9558 // Otherwise use a regular EFLAGS-setting instruction.
9559 switch (ArithOp.getOpcode()) {
9560 default: llvm_unreachable("unexpected operator!");
9561 case ISD::SUB: Opcode = X86ISD::SUB; break;
9562 case ISD::XOR: Opcode = X86ISD::XOR; break;
9563 case ISD::AND: Opcode = X86ISD::AND; break;
9565 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9566 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
9567 if (EFLAGS.getNode())
9570 Opcode = X86ISD::OR;
9584 return SDValue(Op.getNode(), 1);
9590 // If we found that truncation is beneficial, perform the truncation and
9592 if (NeedTruncation) {
9593 EVT VT = Op.getValueType();
9594 SDValue WideVal = Op->getOperand(0);
9595 EVT WideVT = WideVal.getValueType();
9596 unsigned ConvertedOp = 0;
9597 // Use a target machine opcode to prevent further DAGCombine
9598 // optimizations that may separate the arithmetic operations
9599 // from the setcc node.
9600 switch (WideVal.getOpcode()) {
9602 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9603 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9604 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9605 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9606 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9610 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9611 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9612 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9613 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9614 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9620 // Emit a CMP with 0, which is the TEST pattern.
9621 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9622 DAG.getConstant(0, Op.getValueType()));
9624 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9625 SmallVector<SDValue, 4> Ops;
9626 for (unsigned i = 0; i != NumOperands; ++i)
9627 Ops.push_back(Op.getOperand(i));
9629 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9630 DAG.ReplaceAllUsesWith(Op, New);
9631 return SDValue(New.getNode(), 1);
9634 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9636 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9637 SelectionDAG &DAG) const {
9638 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9639 if (C->getAPIntValue() == 0)
9640 return EmitTest(Op0, X86CC, DAG);
9643 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9644 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9645 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9646 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9647 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9649 return SDValue(Sub.getNode(), 1);
9651 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9654 /// Convert a comparison if required by the subtarget.
9655 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9656 SelectionDAG &DAG) const {
9657 // If the subtarget does not support the FUCOMI instruction, floating-point
9658 // comparisons have to be converted.
9659 if (Subtarget->hasCMov() ||
9660 Cmp.getOpcode() != X86ISD::CMP ||
9661 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9662 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9665 // The instruction selector will select an FUCOM instruction instead of
9666 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9667 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9668 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9670 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9671 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9672 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9673 DAG.getConstant(8, MVT::i8));
9674 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9675 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9678 static bool isAllOnes(SDValue V) {
9679 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9680 return C && C->isAllOnesValue();
9683 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9684 /// if it's possible.
9685 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9686 SDLoc dl, SelectionDAG &DAG) const {
9687 SDValue Op0 = And.getOperand(0);
9688 SDValue Op1 = And.getOperand(1);
9689 if (Op0.getOpcode() == ISD::TRUNCATE)
9690 Op0 = Op0.getOperand(0);
9691 if (Op1.getOpcode() == ISD::TRUNCATE)
9692 Op1 = Op1.getOperand(0);
9695 if (Op1.getOpcode() == ISD::SHL)
9696 std::swap(Op0, Op1);
9697 if (Op0.getOpcode() == ISD::SHL) {
9698 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9699 if (And00C->getZExtValue() == 1) {
9700 // If we looked past a truncate, check that it's only truncating away
9702 unsigned BitWidth = Op0.getValueSizeInBits();
9703 unsigned AndBitWidth = And.getValueSizeInBits();
9704 if (BitWidth > AndBitWidth) {
9706 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9707 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9711 RHS = Op0.getOperand(1);
9713 } else if (Op1.getOpcode() == ISD::Constant) {
9714 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9715 uint64_t AndRHSVal = AndRHS->getZExtValue();
9716 SDValue AndLHS = Op0;
9718 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9719 LHS = AndLHS.getOperand(0);
9720 RHS = AndLHS.getOperand(1);
9723 // Use BT if the immediate can't be encoded in a TEST instruction.
9724 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9726 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9730 if (LHS.getNode()) {
9731 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9732 // instruction. Since the shift amount is in-range-or-undefined, we know
9733 // that doing a bittest on the i32 value is ok. We extend to i32 because
9734 // the encoding for the i16 version is larger than the i32 version.
9735 // Also promote i16 to i32 for performance / code size reason.
9736 if (LHS.getValueType() == MVT::i8 ||
9737 LHS.getValueType() == MVT::i16)
9738 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9740 // If the operand types disagree, extend the shift amount to match. Since
9741 // BT ignores high bits (like shifts) we can use anyextend.
9742 if (LHS.getValueType() != RHS.getValueType())
9743 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9745 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9746 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9747 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9748 DAG.getConstant(Cond, MVT::i8), BT);
9754 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
9756 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
9761 // SSE Condition code mapping:
9770 switch (SetCCOpcode) {
9771 default: llvm_unreachable("Unexpected SETCC condition");
9773 case ISD::SETEQ: SSECC = 0; break;
9775 case ISD::SETGT: Swap = true; // Fallthrough
9777 case ISD::SETOLT: SSECC = 1; break;
9779 case ISD::SETGE: Swap = true; // Fallthrough
9781 case ISD::SETOLE: SSECC = 2; break;
9782 case ISD::SETUO: SSECC = 3; break;
9784 case ISD::SETNE: SSECC = 4; break;
9785 case ISD::SETULE: Swap = true; // Fallthrough
9786 case ISD::SETUGE: SSECC = 5; break;
9787 case ISD::SETULT: Swap = true; // Fallthrough
9788 case ISD::SETUGT: SSECC = 6; break;
9789 case ISD::SETO: SSECC = 7; break;
9791 case ISD::SETONE: SSECC = 8; break;
9794 std::swap(Op0, Op1);
9799 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9800 // ones, and then concatenate the result back.
9801 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9802 MVT VT = Op.getSimpleValueType();
9804 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9805 "Unsupported value type for operation");
9807 unsigned NumElems = VT.getVectorNumElements();
9809 SDValue CC = Op.getOperand(2);
9811 // Extract the LHS vectors
9812 SDValue LHS = Op.getOperand(0);
9813 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9814 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9816 // Extract the RHS vectors
9817 SDValue RHS = Op.getOperand(1);
9818 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9819 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9821 // Issue the operation on the smaller types and concatenate the result back
9822 MVT EltVT = VT.getVectorElementType();
9823 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9824 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9825 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9826 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9829 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
9830 SDValue Op0 = Op.getOperand(0);
9831 SDValue Op1 = Op.getOperand(1);
9832 SDValue CC = Op.getOperand(2);
9833 MVT VT = Op.getSimpleValueType();
9835 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
9836 Op.getValueType().getScalarType() == MVT::i1 &&
9837 "Cannot set masked compare for this operation");
9839 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9842 bool Unsigned = false;
9844 switch (SetCCOpcode) {
9845 default: llvm_unreachable("Unexpected SETCC condition");
9846 case ISD::SETNE: SSECC = 4; break;
9847 case ISD::SETEQ: SSECC = 0; break;
9848 case ISD::SETUGT: Unsigned = true;
9849 case ISD::SETGT: SSECC = 6; break; // NLE
9850 case ISD::SETULT: Unsigned = true;
9851 case ISD::SETLT: SSECC = 1; break;
9852 case ISD::SETUGE: Unsigned = true;
9853 case ISD::SETGE: SSECC = 5; break; // NLT
9854 case ISD::SETULE: Unsigned = true;
9855 case ISD::SETLE: SSECC = 2; break;
9857 unsigned Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
9858 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9859 DAG.getConstant(SSECC, MVT::i8));
9863 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9864 SelectionDAG &DAG) {
9865 SDValue Op0 = Op.getOperand(0);
9866 SDValue Op1 = Op.getOperand(1);
9867 SDValue CC = Op.getOperand(2);
9868 MVT VT = Op.getSimpleValueType();
9869 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9870 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
9875 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
9876 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9879 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
9880 unsigned Opc = X86ISD::CMPP;
9881 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
9882 assert(VT.getVectorNumElements() <= 16);
9885 // In the two special cases we can't handle, emit two comparisons.
9888 unsigned CombineOpc;
9889 if (SetCCOpcode == ISD::SETUEQ) {
9890 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9892 assert(SetCCOpcode == ISD::SETONE);
9893 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9896 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9897 DAG.getConstant(CC0, MVT::i8));
9898 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
9899 DAG.getConstant(CC1, MVT::i8));
9900 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9902 // Handle all other FP comparisons here.
9903 return DAG.getNode(Opc, dl, VT, Op0, Op1,
9904 DAG.getConstant(SSECC, MVT::i8));
9907 // Break 256-bit integer vector compare into smaller ones.
9908 if (VT.is256BitVector() && !Subtarget->hasInt256())
9909 return Lower256IntVSETCC(Op, DAG);
9911 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
9912 EVT OpVT = Op1.getValueType();
9913 if (Subtarget->hasAVX512()) {
9914 if (Op1.getValueType().is512BitVector() ||
9915 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
9916 return LowerIntVSETCC_AVX512(Op, DAG);
9918 // In AVX-512 architecture setcc returns mask with i1 elements,
9919 // But there is no compare instruction for i8 and i16 elements.
9920 // We are not talking about 512-bit operands in this case, these
9921 // types are illegal.
9923 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
9924 OpVT.getVectorElementType().getSizeInBits() >= 8))
9925 return DAG.getNode(ISD::TRUNCATE, dl, VT,
9926 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
9929 // We are handling one of the integer comparisons here. Since SSE only has
9930 // GT and EQ comparisons for integer, swapping operands and multiple
9931 // operations may be required for some comparisons.
9933 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9935 switch (SetCCOpcode) {
9936 default: llvm_unreachable("Unexpected SETCC condition");
9937 case ISD::SETNE: Invert = true;
9938 case ISD::SETEQ: Opc = MaskResult? X86ISD::PCMPEQM: X86ISD::PCMPEQ; break;
9939 case ISD::SETLT: Swap = true;
9940 case ISD::SETGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT; break;
9941 case ISD::SETGE: Swap = true;
9942 case ISD::SETLE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9943 Invert = true; break;
9944 case ISD::SETULT: Swap = true;
9945 case ISD::SETUGT: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9946 FlipSigns = true; break;
9947 case ISD::SETUGE: Swap = true;
9948 case ISD::SETULE: Opc = MaskResult? X86ISD::PCMPGTM: X86ISD::PCMPGT;
9949 FlipSigns = true; Invert = true; break;
9952 // Special case: Use min/max operations for SETULE/SETUGE
9953 MVT VET = VT.getVectorElementType();
9955 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9956 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9959 switch (SetCCOpcode) {
9961 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9962 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9965 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9969 std::swap(Op0, Op1);
9971 // Check that the operation in question is available (most are plain SSE2,
9972 // but PCMPGTQ and PCMPEQQ have different requirements).
9973 if (VT == MVT::v2i64) {
9974 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9975 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9977 // First cast everything to the right type.
9978 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9979 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9981 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9982 // bits of the inputs before performing those operations. The lower
9983 // compare is always unsigned.
9986 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9988 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9989 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9990 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9991 Sign, Zero, Sign, Zero);
9993 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9994 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9996 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9997 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9998 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
10000 // Create masks for only the low parts/high parts of the 64 bit integers.
10001 static const int MaskHi[] = { 1, 1, 3, 3 };
10002 static const int MaskLo[] = { 0, 0, 2, 2 };
10003 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
10004 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
10005 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
10007 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
10008 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
10011 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10013 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10016 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
10017 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
10018 // pcmpeqd + pshufd + pand.
10019 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
10021 // First cast everything to the right type.
10022 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
10023 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
10026 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
10028 // Make sure the lower and upper halves are both all-ones.
10029 static const int Mask[] = { 1, 0, 3, 2 };
10030 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
10031 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
10034 Result = DAG.getNOT(dl, Result, MVT::v4i32);
10036 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
10040 // Since SSE has no unsigned integer comparisons, we need to flip the sign
10041 // bits of the inputs before performing those operations.
10043 EVT EltVT = VT.getVectorElementType();
10044 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
10045 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
10046 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
10049 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
10051 // If the logical-not of the result is required, perform that now.
10053 Result = DAG.getNOT(dl, Result, VT);
10056 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
10061 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
10063 MVT VT = Op.getSimpleValueType();
10065 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
10067 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
10068 SDValue Op0 = Op.getOperand(0);
10069 SDValue Op1 = Op.getOperand(1);
10071 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
10073 // Optimize to BT if possible.
10074 // Lower (X & (1 << N)) == 0 to BT(X, N).
10075 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
10076 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
10077 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
10078 Op1.getOpcode() == ISD::Constant &&
10079 cast<ConstantSDNode>(Op1)->isNullValue() &&
10080 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10081 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
10082 if (NewSetCC.getNode())
10086 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
10088 if (Op1.getOpcode() == ISD::Constant &&
10089 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
10090 cast<ConstantSDNode>(Op1)->isNullValue()) &&
10091 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
10093 // If the input is a setcc, then reuse the input setcc or use a new one with
10094 // the inverted condition.
10095 if (Op0.getOpcode() == X86ISD::SETCC) {
10096 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
10097 bool Invert = (CC == ISD::SETNE) ^
10098 cast<ConstantSDNode>(Op1)->isNullValue();
10099 if (!Invert) return Op0;
10101 CCode = X86::GetOppositeBranchCondition(CCode);
10102 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10103 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
10107 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
10108 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
10109 if (X86CC == X86::COND_INVALID)
10112 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
10113 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
10114 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10115 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
10118 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
10119 static bool isX86LogicalCmp(SDValue Op) {
10120 unsigned Opc = Op.getNode()->getOpcode();
10121 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
10122 Opc == X86ISD::SAHF)
10124 if (Op.getResNo() == 1 &&
10125 (Opc == X86ISD::ADD ||
10126 Opc == X86ISD::SUB ||
10127 Opc == X86ISD::ADC ||
10128 Opc == X86ISD::SBB ||
10129 Opc == X86ISD::SMUL ||
10130 Opc == X86ISD::UMUL ||
10131 Opc == X86ISD::INC ||
10132 Opc == X86ISD::DEC ||
10133 Opc == X86ISD::OR ||
10134 Opc == X86ISD::XOR ||
10135 Opc == X86ISD::AND))
10138 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
10144 static bool isZero(SDValue V) {
10145 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
10146 return C && C->isNullValue();
10149 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
10150 if (V.getOpcode() != ISD::TRUNCATE)
10153 SDValue VOp0 = V.getOperand(0);
10154 unsigned InBits = VOp0.getValueSizeInBits();
10155 unsigned Bits = V.getValueSizeInBits();
10156 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
10159 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
10160 bool addTest = true;
10161 SDValue Cond = Op.getOperand(0);
10162 SDValue Op1 = Op.getOperand(1);
10163 SDValue Op2 = Op.getOperand(2);
10165 EVT VT = Op1.getValueType();
10168 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
10169 // are available. Otherwise fp cmovs get lowered into a less efficient branch
10170 // sequence later on.
10171 if (Cond.getOpcode() == ISD::SETCC &&
10172 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
10173 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
10174 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
10175 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
10176 int SSECC = translateX86FSETCC(
10177 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
10180 unsigned Opcode = VT == MVT::f32 ? X86ISD::FSETCCss : X86ISD::FSETCCsd;
10181 SDValue Cmp = DAG.getNode(Opcode, DL, VT, CondOp0, CondOp1,
10182 DAG.getConstant(SSECC, MVT::i8));
10183 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
10184 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
10185 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
10189 if (Cond.getOpcode() == ISD::SETCC) {
10190 SDValue NewCond = LowerSETCC(Cond, DAG);
10191 if (NewCond.getNode())
10195 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
10196 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
10197 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
10198 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
10199 if (Cond.getOpcode() == X86ISD::SETCC &&
10200 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
10201 isZero(Cond.getOperand(1).getOperand(1))) {
10202 SDValue Cmp = Cond.getOperand(1);
10204 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
10206 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
10207 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
10208 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
10210 SDValue CmpOp0 = Cmp.getOperand(0);
10211 // Apply further optimizations for special cases
10212 // (select (x != 0), -1, 0) -> neg & sbb
10213 // (select (x == 0), 0, -1) -> neg & sbb
10214 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
10215 if (YC->isNullValue() &&
10216 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
10217 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
10218 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
10219 DAG.getConstant(0, CmpOp0.getValueType()),
10221 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10222 DAG.getConstant(X86::COND_B, MVT::i8),
10223 SDValue(Neg.getNode(), 1));
10227 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
10228 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
10229 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10231 SDValue Res = // Res = 0 or -1.
10232 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10233 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
10235 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
10236 Res = DAG.getNOT(DL, Res, Res.getValueType());
10238 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
10239 if (N2C == 0 || !N2C->isNullValue())
10240 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
10245 // Look past (and (setcc_carry (cmp ...)), 1).
10246 if (Cond.getOpcode() == ISD::AND &&
10247 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10248 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10249 if (C && C->getAPIntValue() == 1)
10250 Cond = Cond.getOperand(0);
10253 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10254 // setting operand in place of the X86ISD::SETCC.
10255 unsigned CondOpcode = Cond.getOpcode();
10256 if (CondOpcode == X86ISD::SETCC ||
10257 CondOpcode == X86ISD::SETCC_CARRY) {
10258 CC = Cond.getOperand(0);
10260 SDValue Cmp = Cond.getOperand(1);
10261 unsigned Opc = Cmp.getOpcode();
10262 MVT VT = Op.getSimpleValueType();
10264 bool IllegalFPCMov = false;
10265 if (VT.isFloatingPoint() && !VT.isVector() &&
10266 !isScalarFPTypeInSSEReg(VT)) // FPStack?
10267 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
10269 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
10270 Opc == X86ISD::BT) { // FIXME
10274 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10275 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10276 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10277 Cond.getOperand(0).getValueType() != MVT::i8)) {
10278 SDValue LHS = Cond.getOperand(0);
10279 SDValue RHS = Cond.getOperand(1);
10280 unsigned X86Opcode;
10283 switch (CondOpcode) {
10284 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10285 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10286 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10287 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10288 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10289 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10290 default: llvm_unreachable("unexpected overflowing operator");
10292 if (CondOpcode == ISD::UMULO)
10293 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10296 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10298 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
10300 if (CondOpcode == ISD::UMULO)
10301 Cond = X86Op.getValue(2);
10303 Cond = X86Op.getValue(1);
10305 CC = DAG.getConstant(X86Cond, MVT::i8);
10310 // Look pass the truncate if the high bits are known zero.
10311 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10312 Cond = Cond.getOperand(0);
10314 // We know the result of AND is compared against zero. Try to match
10316 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10317 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
10318 if (NewSetCC.getNode()) {
10319 CC = NewSetCC.getOperand(0);
10320 Cond = NewSetCC.getOperand(1);
10327 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10328 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10331 // a < b ? -1 : 0 -> RES = ~setcc_carry
10332 // a < b ? 0 : -1 -> RES = setcc_carry
10333 // a >= b ? -1 : 0 -> RES = setcc_carry
10334 // a >= b ? 0 : -1 -> RES = ~setcc_carry
10335 if (Cond.getOpcode() == X86ISD::SUB) {
10336 Cond = ConvertCmpIfNecessary(Cond, DAG);
10337 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
10339 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
10340 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
10341 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
10342 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
10343 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
10344 return DAG.getNOT(DL, Res, Res.getValueType());
10349 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
10350 // widen the cmov and push the truncate through. This avoids introducing a new
10351 // branch during isel and doesn't add any extensions.
10352 if (Op.getValueType() == MVT::i8 &&
10353 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10354 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10355 if (T1.getValueType() == T2.getValueType() &&
10356 // Blacklist CopyFromReg to avoid partial register stalls.
10357 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10358 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10359 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10360 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10364 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10365 // condition is true.
10366 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10367 SDValue Ops[] = { Op2, Op1, CC, Cond };
10368 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10371 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
10372 MVT VT = Op->getSimpleValueType(0);
10373 SDValue In = Op->getOperand(0);
10374 MVT InVT = In.getSimpleValueType();
10377 unsigned int NumElts = VT.getVectorNumElements();
10378 if (NumElts != 8 && NumElts != 16)
10381 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
10382 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
10384 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10385 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
10387 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
10388 Constant *C = ConstantInt::get(*DAG.getContext(),
10389 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
10391 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
10392 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
10393 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
10394 MachinePointerInfo::getConstantPool(),
10395 false, false, false, Alignment);
10396 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
10397 if (VT.is512BitVector())
10399 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
10402 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
10403 SelectionDAG &DAG) {
10404 MVT VT = Op->getSimpleValueType(0);
10405 SDValue In = Op->getOperand(0);
10406 MVT InVT = In.getSimpleValueType();
10409 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
10410 return LowerSIGN_EXTEND_AVX512(Op, DAG);
10412 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10413 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10416 if (Subtarget->hasInt256())
10417 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10419 // Optimize vectors in AVX mode
10420 // Sign extend v8i16 to v8i32 and
10423 // Divide input vector into two parts
10424 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10425 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10426 // concat the vectors to original VT
10428 unsigned NumElems = InVT.getVectorNumElements();
10429 SDValue Undef = DAG.getUNDEF(InVT);
10431 SmallVector<int,8> ShufMask1(NumElems, -1);
10432 for (unsigned i = 0; i != NumElems/2; ++i)
10435 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10437 SmallVector<int,8> ShufMask2(NumElems, -1);
10438 for (unsigned i = 0; i != NumElems/2; ++i)
10439 ShufMask2[i] = i + NumElems/2;
10441 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10443 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10444 VT.getVectorNumElements()/2);
10446 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10447 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10449 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10452 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10453 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10454 // from the AND / OR.
10455 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10456 Opc = Op.getOpcode();
10457 if (Opc != ISD::OR && Opc != ISD::AND)
10459 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10460 Op.getOperand(0).hasOneUse() &&
10461 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10462 Op.getOperand(1).hasOneUse());
10465 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10466 // 1 and that the SETCC node has a single use.
10467 static bool isXor1OfSetCC(SDValue Op) {
10468 if (Op.getOpcode() != ISD::XOR)
10470 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10471 if (N1C && N1C->getAPIntValue() == 1) {
10472 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10473 Op.getOperand(0).hasOneUse();
10478 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10479 bool addTest = true;
10480 SDValue Chain = Op.getOperand(0);
10481 SDValue Cond = Op.getOperand(1);
10482 SDValue Dest = Op.getOperand(2);
10485 bool Inverted = false;
10487 if (Cond.getOpcode() == ISD::SETCC) {
10488 // Check for setcc([su]{add,sub,mul}o == 0).
10489 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10490 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10491 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10492 Cond.getOperand(0).getResNo() == 1 &&
10493 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10494 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10495 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10496 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10497 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10498 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10500 Cond = Cond.getOperand(0);
10502 SDValue NewCond = LowerSETCC(Cond, DAG);
10503 if (NewCond.getNode())
10508 // FIXME: LowerXALUO doesn't handle these!!
10509 else if (Cond.getOpcode() == X86ISD::ADD ||
10510 Cond.getOpcode() == X86ISD::SUB ||
10511 Cond.getOpcode() == X86ISD::SMUL ||
10512 Cond.getOpcode() == X86ISD::UMUL)
10513 Cond = LowerXALUO(Cond, DAG);
10516 // Look pass (and (setcc_carry (cmp ...)), 1).
10517 if (Cond.getOpcode() == ISD::AND &&
10518 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10519 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10520 if (C && C->getAPIntValue() == 1)
10521 Cond = Cond.getOperand(0);
10524 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10525 // setting operand in place of the X86ISD::SETCC.
10526 unsigned CondOpcode = Cond.getOpcode();
10527 if (CondOpcode == X86ISD::SETCC ||
10528 CondOpcode == X86ISD::SETCC_CARRY) {
10529 CC = Cond.getOperand(0);
10531 SDValue Cmp = Cond.getOperand(1);
10532 unsigned Opc = Cmp.getOpcode();
10533 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10534 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10538 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10542 // These can only come from an arithmetic instruction with overflow,
10543 // e.g. SADDO, UADDO.
10544 Cond = Cond.getNode()->getOperand(1);
10550 CondOpcode = Cond.getOpcode();
10551 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10552 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10553 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10554 Cond.getOperand(0).getValueType() != MVT::i8)) {
10555 SDValue LHS = Cond.getOperand(0);
10556 SDValue RHS = Cond.getOperand(1);
10557 unsigned X86Opcode;
10560 switch (CondOpcode) {
10561 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10562 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10563 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10564 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10565 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10566 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10567 default: llvm_unreachable("unexpected overflowing operator");
10570 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10571 if (CondOpcode == ISD::UMULO)
10572 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10575 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10577 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10579 if (CondOpcode == ISD::UMULO)
10580 Cond = X86Op.getValue(2);
10582 Cond = X86Op.getValue(1);
10584 CC = DAG.getConstant(X86Cond, MVT::i8);
10588 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10589 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10590 if (CondOpc == ISD::OR) {
10591 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10592 // two branches instead of an explicit OR instruction with a
10594 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10595 isX86LogicalCmp(Cmp)) {
10596 CC = Cond.getOperand(0).getOperand(0);
10597 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10598 Chain, Dest, CC, Cmp);
10599 CC = Cond.getOperand(1).getOperand(0);
10603 } else { // ISD::AND
10604 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10605 // two branches instead of an explicit AND instruction with a
10606 // separate test. However, we only do this if this block doesn't
10607 // have a fall-through edge, because this requires an explicit
10608 // jmp when the condition is false.
10609 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10610 isX86LogicalCmp(Cmp) &&
10611 Op.getNode()->hasOneUse()) {
10612 X86::CondCode CCode =
10613 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10614 CCode = X86::GetOppositeBranchCondition(CCode);
10615 CC = DAG.getConstant(CCode, MVT::i8);
10616 SDNode *User = *Op.getNode()->use_begin();
10617 // Look for an unconditional branch following this conditional branch.
10618 // We need this because we need to reverse the successors in order
10619 // to implement FCMP_OEQ.
10620 if (User->getOpcode() == ISD::BR) {
10621 SDValue FalseBB = User->getOperand(1);
10623 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10624 assert(NewBR == User);
10628 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10629 Chain, Dest, CC, Cmp);
10630 X86::CondCode CCode =
10631 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10632 CCode = X86::GetOppositeBranchCondition(CCode);
10633 CC = DAG.getConstant(CCode, MVT::i8);
10639 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10640 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10641 // It should be transformed during dag combiner except when the condition
10642 // is set by a arithmetics with overflow node.
10643 X86::CondCode CCode =
10644 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10645 CCode = X86::GetOppositeBranchCondition(CCode);
10646 CC = DAG.getConstant(CCode, MVT::i8);
10647 Cond = Cond.getOperand(0).getOperand(1);
10649 } else if (Cond.getOpcode() == ISD::SETCC &&
10650 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10651 // For FCMP_OEQ, we can emit
10652 // two branches instead of an explicit AND instruction with a
10653 // separate test. However, we only do this if this block doesn't
10654 // have a fall-through edge, because this requires an explicit
10655 // jmp when the condition is false.
10656 if (Op.getNode()->hasOneUse()) {
10657 SDNode *User = *Op.getNode()->use_begin();
10658 // Look for an unconditional branch following this conditional branch.
10659 // We need this because we need to reverse the successors in order
10660 // to implement FCMP_OEQ.
10661 if (User->getOpcode() == ISD::BR) {
10662 SDValue FalseBB = User->getOperand(1);
10664 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10665 assert(NewBR == User);
10669 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10670 Cond.getOperand(0), Cond.getOperand(1));
10671 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10672 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10673 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10674 Chain, Dest, CC, Cmp);
10675 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10680 } else if (Cond.getOpcode() == ISD::SETCC &&
10681 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10682 // For FCMP_UNE, we can emit
10683 // two branches instead of an explicit AND instruction with a
10684 // separate test. However, we only do this if this block doesn't
10685 // have a fall-through edge, because this requires an explicit
10686 // jmp when the condition is false.
10687 if (Op.getNode()->hasOneUse()) {
10688 SDNode *User = *Op.getNode()->use_begin();
10689 // Look for an unconditional branch following this conditional branch.
10690 // We need this because we need to reverse the successors in order
10691 // to implement FCMP_UNE.
10692 if (User->getOpcode() == ISD::BR) {
10693 SDValue FalseBB = User->getOperand(1);
10695 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10696 assert(NewBR == User);
10699 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10700 Cond.getOperand(0), Cond.getOperand(1));
10701 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10702 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10703 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10704 Chain, Dest, CC, Cmp);
10705 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10715 // Look pass the truncate if the high bits are known zero.
10716 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10717 Cond = Cond.getOperand(0);
10719 // We know the result of AND is compared against zero. Try to match
10721 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10722 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10723 if (NewSetCC.getNode()) {
10724 CC = NewSetCC.getOperand(0);
10725 Cond = NewSetCC.getOperand(1);
10732 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10733 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10735 Cond = ConvertCmpIfNecessary(Cond, DAG);
10736 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10737 Chain, Dest, CC, Cond);
10740 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10741 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10742 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10743 // that the guard pages used by the OS virtual memory manager are allocated in
10744 // correct sequence.
10746 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10747 SelectionDAG &DAG) const {
10748 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10749 getTargetMachine().Options.EnableSegmentedStacks) &&
10750 "This should be used only on Windows targets or when segmented stacks "
10752 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10756 SDValue Chain = Op.getOperand(0);
10757 SDValue Size = Op.getOperand(1);
10758 // FIXME: Ensure alignment here
10760 bool Is64Bit = Subtarget->is64Bit();
10761 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10763 if (getTargetMachine().Options.EnableSegmentedStacks) {
10764 MachineFunction &MF = DAG.getMachineFunction();
10765 MachineRegisterInfo &MRI = MF.getRegInfo();
10768 // The 64 bit implementation of segmented stacks needs to clobber both r10
10769 // r11. This makes it impossible to use it along with nested parameters.
10770 const Function *F = MF.getFunction();
10772 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10774 if (I->hasNestAttr())
10775 report_fatal_error("Cannot use segmented stacks with functions that "
10776 "have nested arguments.");
10779 const TargetRegisterClass *AddrRegClass =
10780 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10781 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10782 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10783 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10784 DAG.getRegister(Vreg, SPTy));
10785 SDValue Ops1[2] = { Value, Chain };
10786 return DAG.getMergeValues(Ops1, 2, dl);
10789 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10791 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10792 Flag = Chain.getValue(1);
10793 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10795 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10796 Flag = Chain.getValue(1);
10798 const X86RegisterInfo *RegInfo =
10799 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10800 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10803 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10804 return DAG.getMergeValues(Ops1, 2, dl);
10808 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10809 MachineFunction &MF = DAG.getMachineFunction();
10810 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10812 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10815 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10816 // vastart just stores the address of the VarArgsFrameIndex slot into the
10817 // memory location argument.
10818 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10820 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10821 MachinePointerInfo(SV), false, false, 0);
10825 // gp_offset (0 - 6 * 8)
10826 // fp_offset (48 - 48 + 8 * 16)
10827 // overflow_arg_area (point to parameters coming in memory).
10829 SmallVector<SDValue, 8> MemOps;
10830 SDValue FIN = Op.getOperand(1);
10832 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10833 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10835 FIN, MachinePointerInfo(SV), false, false, 0);
10836 MemOps.push_back(Store);
10839 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10840 FIN, DAG.getIntPtrConstant(4));
10841 Store = DAG.getStore(Op.getOperand(0), DL,
10842 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10844 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10845 MemOps.push_back(Store);
10847 // Store ptr to overflow_arg_area
10848 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10849 FIN, DAG.getIntPtrConstant(4));
10850 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10852 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10853 MachinePointerInfo(SV, 8),
10855 MemOps.push_back(Store);
10857 // Store ptr to reg_save_area.
10858 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10859 FIN, DAG.getIntPtrConstant(8));
10860 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10862 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10863 MachinePointerInfo(SV, 16), false, false, 0);
10864 MemOps.push_back(Store);
10865 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10866 &MemOps[0], MemOps.size());
10869 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10870 assert(Subtarget->is64Bit() &&
10871 "LowerVAARG only handles 64-bit va_arg!");
10872 assert((Subtarget->isTargetLinux() ||
10873 Subtarget->isTargetDarwin()) &&
10874 "Unhandled target in LowerVAARG");
10875 assert(Op.getNode()->getNumOperands() == 4);
10876 SDValue Chain = Op.getOperand(0);
10877 SDValue SrcPtr = Op.getOperand(1);
10878 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10879 unsigned Align = Op.getConstantOperandVal(3);
10882 EVT ArgVT = Op.getNode()->getValueType(0);
10883 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10884 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10887 // Decide which area this value should be read from.
10888 // TODO: Implement the AMD64 ABI in its entirety. This simple
10889 // selection mechanism works only for the basic types.
10890 if (ArgVT == MVT::f80) {
10891 llvm_unreachable("va_arg for f80 not yet implemented");
10892 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10893 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10894 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10895 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10897 llvm_unreachable("Unhandled argument type in LowerVAARG");
10900 if (ArgMode == 2) {
10901 // Sanity Check: Make sure using fp_offset makes sense.
10902 assert(!getTargetMachine().Options.UseSoftFloat &&
10903 !(DAG.getMachineFunction()
10904 .getFunction()->getAttributes()
10905 .hasAttribute(AttributeSet::FunctionIndex,
10906 Attribute::NoImplicitFloat)) &&
10907 Subtarget->hasSSE1());
10910 // Insert VAARG_64 node into the DAG
10911 // VAARG_64 returns two values: Variable Argument Address, Chain
10912 SmallVector<SDValue, 11> InstOps;
10913 InstOps.push_back(Chain);
10914 InstOps.push_back(SrcPtr);
10915 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10916 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10917 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10918 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10919 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10920 VTs, &InstOps[0], InstOps.size(),
10922 MachinePointerInfo(SV),
10924 /*Volatile=*/false,
10926 /*WriteMem=*/true);
10927 Chain = VAARG.getValue(1);
10929 // Load the next argument and return it
10930 return DAG.getLoad(ArgVT, dl,
10933 MachinePointerInfo(),
10934 false, false, false, 0);
10937 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10938 SelectionDAG &DAG) {
10939 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10940 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10941 SDValue Chain = Op.getOperand(0);
10942 SDValue DstPtr = Op.getOperand(1);
10943 SDValue SrcPtr = Op.getOperand(2);
10944 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10945 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10948 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10949 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10951 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10954 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10955 // may or may not be a constant. Takes immediate version of shift as input.
10956 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10957 SDValue SrcOp, SDValue ShAmt,
10958 SelectionDAG &DAG) {
10959 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10961 if (isa<ConstantSDNode>(ShAmt)) {
10962 // Constant may be a TargetConstant. Use a regular constant.
10963 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10965 default: llvm_unreachable("Unknown target vector shift node");
10966 case X86ISD::VSHLI:
10967 case X86ISD::VSRLI:
10968 case X86ISD::VSRAI:
10969 return DAG.getNode(Opc, dl, VT, SrcOp,
10970 DAG.getConstant(ShiftAmt, MVT::i32));
10974 // Change opcode to non-immediate version
10976 default: llvm_unreachable("Unknown target vector shift node");
10977 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10978 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10979 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10982 // Need to build a vector containing shift amount
10983 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10986 ShOps[1] = DAG.getConstant(0, MVT::i32);
10987 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10988 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10990 // The return type has to be a 128-bit type with the same element
10991 // type as the input type.
10992 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10993 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10995 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10996 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10999 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
11001 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11003 default: return SDValue(); // Don't custom lower most intrinsics.
11004 // Comparison intrinsics.
11005 case Intrinsic::x86_sse_comieq_ss:
11006 case Intrinsic::x86_sse_comilt_ss:
11007 case Intrinsic::x86_sse_comile_ss:
11008 case Intrinsic::x86_sse_comigt_ss:
11009 case Intrinsic::x86_sse_comige_ss:
11010 case Intrinsic::x86_sse_comineq_ss:
11011 case Intrinsic::x86_sse_ucomieq_ss:
11012 case Intrinsic::x86_sse_ucomilt_ss:
11013 case Intrinsic::x86_sse_ucomile_ss:
11014 case Intrinsic::x86_sse_ucomigt_ss:
11015 case Intrinsic::x86_sse_ucomige_ss:
11016 case Intrinsic::x86_sse_ucomineq_ss:
11017 case Intrinsic::x86_sse2_comieq_sd:
11018 case Intrinsic::x86_sse2_comilt_sd:
11019 case Intrinsic::x86_sse2_comile_sd:
11020 case Intrinsic::x86_sse2_comigt_sd:
11021 case Intrinsic::x86_sse2_comige_sd:
11022 case Intrinsic::x86_sse2_comineq_sd:
11023 case Intrinsic::x86_sse2_ucomieq_sd:
11024 case Intrinsic::x86_sse2_ucomilt_sd:
11025 case Intrinsic::x86_sse2_ucomile_sd:
11026 case Intrinsic::x86_sse2_ucomigt_sd:
11027 case Intrinsic::x86_sse2_ucomige_sd:
11028 case Intrinsic::x86_sse2_ucomineq_sd: {
11032 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11033 case Intrinsic::x86_sse_comieq_ss:
11034 case Intrinsic::x86_sse2_comieq_sd:
11035 Opc = X86ISD::COMI;
11038 case Intrinsic::x86_sse_comilt_ss:
11039 case Intrinsic::x86_sse2_comilt_sd:
11040 Opc = X86ISD::COMI;
11043 case Intrinsic::x86_sse_comile_ss:
11044 case Intrinsic::x86_sse2_comile_sd:
11045 Opc = X86ISD::COMI;
11048 case Intrinsic::x86_sse_comigt_ss:
11049 case Intrinsic::x86_sse2_comigt_sd:
11050 Opc = X86ISD::COMI;
11053 case Intrinsic::x86_sse_comige_ss:
11054 case Intrinsic::x86_sse2_comige_sd:
11055 Opc = X86ISD::COMI;
11058 case Intrinsic::x86_sse_comineq_ss:
11059 case Intrinsic::x86_sse2_comineq_sd:
11060 Opc = X86ISD::COMI;
11063 case Intrinsic::x86_sse_ucomieq_ss:
11064 case Intrinsic::x86_sse2_ucomieq_sd:
11065 Opc = X86ISD::UCOMI;
11068 case Intrinsic::x86_sse_ucomilt_ss:
11069 case Intrinsic::x86_sse2_ucomilt_sd:
11070 Opc = X86ISD::UCOMI;
11073 case Intrinsic::x86_sse_ucomile_ss:
11074 case Intrinsic::x86_sse2_ucomile_sd:
11075 Opc = X86ISD::UCOMI;
11078 case Intrinsic::x86_sse_ucomigt_ss:
11079 case Intrinsic::x86_sse2_ucomigt_sd:
11080 Opc = X86ISD::UCOMI;
11083 case Intrinsic::x86_sse_ucomige_ss:
11084 case Intrinsic::x86_sse2_ucomige_sd:
11085 Opc = X86ISD::UCOMI;
11088 case Intrinsic::x86_sse_ucomineq_ss:
11089 case Intrinsic::x86_sse2_ucomineq_sd:
11090 Opc = X86ISD::UCOMI;
11095 SDValue LHS = Op.getOperand(1);
11096 SDValue RHS = Op.getOperand(2);
11097 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
11098 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
11099 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
11100 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11101 DAG.getConstant(X86CC, MVT::i8), Cond);
11102 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11105 // Arithmetic intrinsics.
11106 case Intrinsic::x86_sse2_pmulu_dq:
11107 case Intrinsic::x86_avx2_pmulu_dq:
11108 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
11109 Op.getOperand(1), Op.getOperand(2));
11111 // SSE2/AVX2 sub with unsigned saturation intrinsics
11112 case Intrinsic::x86_sse2_psubus_b:
11113 case Intrinsic::x86_sse2_psubus_w:
11114 case Intrinsic::x86_avx2_psubus_b:
11115 case Intrinsic::x86_avx2_psubus_w:
11116 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
11117 Op.getOperand(1), Op.getOperand(2));
11119 // SSE3/AVX horizontal add/sub intrinsics
11120 case Intrinsic::x86_sse3_hadd_ps:
11121 case Intrinsic::x86_sse3_hadd_pd:
11122 case Intrinsic::x86_avx_hadd_ps_256:
11123 case Intrinsic::x86_avx_hadd_pd_256:
11124 case Intrinsic::x86_sse3_hsub_ps:
11125 case Intrinsic::x86_sse3_hsub_pd:
11126 case Intrinsic::x86_avx_hsub_ps_256:
11127 case Intrinsic::x86_avx_hsub_pd_256:
11128 case Intrinsic::x86_ssse3_phadd_w_128:
11129 case Intrinsic::x86_ssse3_phadd_d_128:
11130 case Intrinsic::x86_avx2_phadd_w:
11131 case Intrinsic::x86_avx2_phadd_d:
11132 case Intrinsic::x86_ssse3_phsub_w_128:
11133 case Intrinsic::x86_ssse3_phsub_d_128:
11134 case Intrinsic::x86_avx2_phsub_w:
11135 case Intrinsic::x86_avx2_phsub_d: {
11138 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11139 case Intrinsic::x86_sse3_hadd_ps:
11140 case Intrinsic::x86_sse3_hadd_pd:
11141 case Intrinsic::x86_avx_hadd_ps_256:
11142 case Intrinsic::x86_avx_hadd_pd_256:
11143 Opcode = X86ISD::FHADD;
11145 case Intrinsic::x86_sse3_hsub_ps:
11146 case Intrinsic::x86_sse3_hsub_pd:
11147 case Intrinsic::x86_avx_hsub_ps_256:
11148 case Intrinsic::x86_avx_hsub_pd_256:
11149 Opcode = X86ISD::FHSUB;
11151 case Intrinsic::x86_ssse3_phadd_w_128:
11152 case Intrinsic::x86_ssse3_phadd_d_128:
11153 case Intrinsic::x86_avx2_phadd_w:
11154 case Intrinsic::x86_avx2_phadd_d:
11155 Opcode = X86ISD::HADD;
11157 case Intrinsic::x86_ssse3_phsub_w_128:
11158 case Intrinsic::x86_ssse3_phsub_d_128:
11159 case Intrinsic::x86_avx2_phsub_w:
11160 case Intrinsic::x86_avx2_phsub_d:
11161 Opcode = X86ISD::HSUB;
11164 return DAG.getNode(Opcode, dl, Op.getValueType(),
11165 Op.getOperand(1), Op.getOperand(2));
11168 // SSE2/SSE41/AVX2 integer max/min intrinsics.
11169 case Intrinsic::x86_sse2_pmaxu_b:
11170 case Intrinsic::x86_sse41_pmaxuw:
11171 case Intrinsic::x86_sse41_pmaxud:
11172 case Intrinsic::x86_avx2_pmaxu_b:
11173 case Intrinsic::x86_avx2_pmaxu_w:
11174 case Intrinsic::x86_avx2_pmaxu_d:
11175 case Intrinsic::x86_sse2_pminu_b:
11176 case Intrinsic::x86_sse41_pminuw:
11177 case Intrinsic::x86_sse41_pminud:
11178 case Intrinsic::x86_avx2_pminu_b:
11179 case Intrinsic::x86_avx2_pminu_w:
11180 case Intrinsic::x86_avx2_pminu_d:
11181 case Intrinsic::x86_sse41_pmaxsb:
11182 case Intrinsic::x86_sse2_pmaxs_w:
11183 case Intrinsic::x86_sse41_pmaxsd:
11184 case Intrinsic::x86_avx2_pmaxs_b:
11185 case Intrinsic::x86_avx2_pmaxs_w:
11186 case Intrinsic::x86_avx2_pmaxs_d:
11187 case Intrinsic::x86_sse41_pminsb:
11188 case Intrinsic::x86_sse2_pmins_w:
11189 case Intrinsic::x86_sse41_pminsd:
11190 case Intrinsic::x86_avx2_pmins_b:
11191 case Intrinsic::x86_avx2_pmins_w:
11192 case Intrinsic::x86_avx2_pmins_d: {
11195 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11196 case Intrinsic::x86_sse2_pmaxu_b:
11197 case Intrinsic::x86_sse41_pmaxuw:
11198 case Intrinsic::x86_sse41_pmaxud:
11199 case Intrinsic::x86_avx2_pmaxu_b:
11200 case Intrinsic::x86_avx2_pmaxu_w:
11201 case Intrinsic::x86_avx2_pmaxu_d:
11202 Opcode = X86ISD::UMAX;
11204 case Intrinsic::x86_sse2_pminu_b:
11205 case Intrinsic::x86_sse41_pminuw:
11206 case Intrinsic::x86_sse41_pminud:
11207 case Intrinsic::x86_avx2_pminu_b:
11208 case Intrinsic::x86_avx2_pminu_w:
11209 case Intrinsic::x86_avx2_pminu_d:
11210 Opcode = X86ISD::UMIN;
11212 case Intrinsic::x86_sse41_pmaxsb:
11213 case Intrinsic::x86_sse2_pmaxs_w:
11214 case Intrinsic::x86_sse41_pmaxsd:
11215 case Intrinsic::x86_avx2_pmaxs_b:
11216 case Intrinsic::x86_avx2_pmaxs_w:
11217 case Intrinsic::x86_avx2_pmaxs_d:
11218 Opcode = X86ISD::SMAX;
11220 case Intrinsic::x86_sse41_pminsb:
11221 case Intrinsic::x86_sse2_pmins_w:
11222 case Intrinsic::x86_sse41_pminsd:
11223 case Intrinsic::x86_avx2_pmins_b:
11224 case Intrinsic::x86_avx2_pmins_w:
11225 case Intrinsic::x86_avx2_pmins_d:
11226 Opcode = X86ISD::SMIN;
11229 return DAG.getNode(Opcode, dl, Op.getValueType(),
11230 Op.getOperand(1), Op.getOperand(2));
11233 // SSE/SSE2/AVX floating point max/min intrinsics.
11234 case Intrinsic::x86_sse_max_ps:
11235 case Intrinsic::x86_sse2_max_pd:
11236 case Intrinsic::x86_avx_max_ps_256:
11237 case Intrinsic::x86_avx_max_pd_256:
11238 case Intrinsic::x86_avx512_max_ps_512:
11239 case Intrinsic::x86_avx512_max_pd_512:
11240 case Intrinsic::x86_sse_min_ps:
11241 case Intrinsic::x86_sse2_min_pd:
11242 case Intrinsic::x86_avx_min_ps_256:
11243 case Intrinsic::x86_avx_min_pd_256:
11244 case Intrinsic::x86_avx512_min_ps_512:
11245 case Intrinsic::x86_avx512_min_pd_512: {
11248 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11249 case Intrinsic::x86_sse_max_ps:
11250 case Intrinsic::x86_sse2_max_pd:
11251 case Intrinsic::x86_avx_max_ps_256:
11252 case Intrinsic::x86_avx_max_pd_256:
11253 case Intrinsic::x86_avx512_max_ps_512:
11254 case Intrinsic::x86_avx512_max_pd_512:
11255 Opcode = X86ISD::FMAX;
11257 case Intrinsic::x86_sse_min_ps:
11258 case Intrinsic::x86_sse2_min_pd:
11259 case Intrinsic::x86_avx_min_ps_256:
11260 case Intrinsic::x86_avx_min_pd_256:
11261 case Intrinsic::x86_avx512_min_ps_512:
11262 case Intrinsic::x86_avx512_min_pd_512:
11263 Opcode = X86ISD::FMIN;
11266 return DAG.getNode(Opcode, dl, Op.getValueType(),
11267 Op.getOperand(1), Op.getOperand(2));
11270 // AVX2 variable shift intrinsics
11271 case Intrinsic::x86_avx2_psllv_d:
11272 case Intrinsic::x86_avx2_psllv_q:
11273 case Intrinsic::x86_avx2_psllv_d_256:
11274 case Intrinsic::x86_avx2_psllv_q_256:
11275 case Intrinsic::x86_avx2_psrlv_d:
11276 case Intrinsic::x86_avx2_psrlv_q:
11277 case Intrinsic::x86_avx2_psrlv_d_256:
11278 case Intrinsic::x86_avx2_psrlv_q_256:
11279 case Intrinsic::x86_avx2_psrav_d:
11280 case Intrinsic::x86_avx2_psrav_d_256: {
11283 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11284 case Intrinsic::x86_avx2_psllv_d:
11285 case Intrinsic::x86_avx2_psllv_q:
11286 case Intrinsic::x86_avx2_psllv_d_256:
11287 case Intrinsic::x86_avx2_psllv_q_256:
11290 case Intrinsic::x86_avx2_psrlv_d:
11291 case Intrinsic::x86_avx2_psrlv_q:
11292 case Intrinsic::x86_avx2_psrlv_d_256:
11293 case Intrinsic::x86_avx2_psrlv_q_256:
11296 case Intrinsic::x86_avx2_psrav_d:
11297 case Intrinsic::x86_avx2_psrav_d_256:
11301 return DAG.getNode(Opcode, dl, Op.getValueType(),
11302 Op.getOperand(1), Op.getOperand(2));
11305 case Intrinsic::x86_ssse3_pshuf_b_128:
11306 case Intrinsic::x86_avx2_pshuf_b:
11307 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
11308 Op.getOperand(1), Op.getOperand(2));
11310 case Intrinsic::x86_ssse3_psign_b_128:
11311 case Intrinsic::x86_ssse3_psign_w_128:
11312 case Intrinsic::x86_ssse3_psign_d_128:
11313 case Intrinsic::x86_avx2_psign_b:
11314 case Intrinsic::x86_avx2_psign_w:
11315 case Intrinsic::x86_avx2_psign_d:
11316 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
11317 Op.getOperand(1), Op.getOperand(2));
11319 case Intrinsic::x86_sse41_insertps:
11320 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
11321 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11323 case Intrinsic::x86_avx_vperm2f128_ps_256:
11324 case Intrinsic::x86_avx_vperm2f128_pd_256:
11325 case Intrinsic::x86_avx_vperm2f128_si_256:
11326 case Intrinsic::x86_avx2_vperm2i128:
11327 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
11328 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
11330 case Intrinsic::x86_avx2_permd:
11331 case Intrinsic::x86_avx2_permps:
11332 // Operands intentionally swapped. Mask is last operand to intrinsic,
11333 // but second operand for node/instruction.
11334 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
11335 Op.getOperand(2), Op.getOperand(1));
11337 case Intrinsic::x86_sse_sqrt_ps:
11338 case Intrinsic::x86_sse2_sqrt_pd:
11339 case Intrinsic::x86_avx_sqrt_ps_256:
11340 case Intrinsic::x86_avx_sqrt_pd_256:
11341 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
11343 // ptest and testp intrinsics. The intrinsic these come from are designed to
11344 // return an integer value, not just an instruction so lower it to the ptest
11345 // or testp pattern and a setcc for the result.
11346 case Intrinsic::x86_sse41_ptestz:
11347 case Intrinsic::x86_sse41_ptestc:
11348 case Intrinsic::x86_sse41_ptestnzc:
11349 case Intrinsic::x86_avx_ptestz_256:
11350 case Intrinsic::x86_avx_ptestc_256:
11351 case Intrinsic::x86_avx_ptestnzc_256:
11352 case Intrinsic::x86_avx_vtestz_ps:
11353 case Intrinsic::x86_avx_vtestc_ps:
11354 case Intrinsic::x86_avx_vtestnzc_ps:
11355 case Intrinsic::x86_avx_vtestz_pd:
11356 case Intrinsic::x86_avx_vtestc_pd:
11357 case Intrinsic::x86_avx_vtestnzc_pd:
11358 case Intrinsic::x86_avx_vtestz_ps_256:
11359 case Intrinsic::x86_avx_vtestc_ps_256:
11360 case Intrinsic::x86_avx_vtestnzc_ps_256:
11361 case Intrinsic::x86_avx_vtestz_pd_256:
11362 case Intrinsic::x86_avx_vtestc_pd_256:
11363 case Intrinsic::x86_avx_vtestnzc_pd_256: {
11364 bool IsTestPacked = false;
11367 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
11368 case Intrinsic::x86_avx_vtestz_ps:
11369 case Intrinsic::x86_avx_vtestz_pd:
11370 case Intrinsic::x86_avx_vtestz_ps_256:
11371 case Intrinsic::x86_avx_vtestz_pd_256:
11372 IsTestPacked = true; // Fallthrough
11373 case Intrinsic::x86_sse41_ptestz:
11374 case Intrinsic::x86_avx_ptestz_256:
11376 X86CC = X86::COND_E;
11378 case Intrinsic::x86_avx_vtestc_ps:
11379 case Intrinsic::x86_avx_vtestc_pd:
11380 case Intrinsic::x86_avx_vtestc_ps_256:
11381 case Intrinsic::x86_avx_vtestc_pd_256:
11382 IsTestPacked = true; // Fallthrough
11383 case Intrinsic::x86_sse41_ptestc:
11384 case Intrinsic::x86_avx_ptestc_256:
11386 X86CC = X86::COND_B;
11388 case Intrinsic::x86_avx_vtestnzc_ps:
11389 case Intrinsic::x86_avx_vtestnzc_pd:
11390 case Intrinsic::x86_avx_vtestnzc_ps_256:
11391 case Intrinsic::x86_avx_vtestnzc_pd_256:
11392 IsTestPacked = true; // Fallthrough
11393 case Intrinsic::x86_sse41_ptestnzc:
11394 case Intrinsic::x86_avx_ptestnzc_256:
11396 X86CC = X86::COND_A;
11400 SDValue LHS = Op.getOperand(1);
11401 SDValue RHS = Op.getOperand(2);
11402 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11403 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11404 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11405 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11406 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11408 case Intrinsic::x86_avx512_kortestz:
11409 case Intrinsic::x86_avx512_kortestc: {
11410 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz)? X86::COND_E: X86::COND_B;
11411 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
11412 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
11413 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11414 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
11415 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11416 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11419 // SSE/AVX shift intrinsics
11420 case Intrinsic::x86_sse2_psll_w:
11421 case Intrinsic::x86_sse2_psll_d:
11422 case Intrinsic::x86_sse2_psll_q:
11423 case Intrinsic::x86_avx2_psll_w:
11424 case Intrinsic::x86_avx2_psll_d:
11425 case Intrinsic::x86_avx2_psll_q:
11426 case Intrinsic::x86_sse2_psrl_w:
11427 case Intrinsic::x86_sse2_psrl_d:
11428 case Intrinsic::x86_sse2_psrl_q:
11429 case Intrinsic::x86_avx2_psrl_w:
11430 case Intrinsic::x86_avx2_psrl_d:
11431 case Intrinsic::x86_avx2_psrl_q:
11432 case Intrinsic::x86_sse2_psra_w:
11433 case Intrinsic::x86_sse2_psra_d:
11434 case Intrinsic::x86_avx2_psra_w:
11435 case Intrinsic::x86_avx2_psra_d: {
11438 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11439 case Intrinsic::x86_sse2_psll_w:
11440 case Intrinsic::x86_sse2_psll_d:
11441 case Intrinsic::x86_sse2_psll_q:
11442 case Intrinsic::x86_avx2_psll_w:
11443 case Intrinsic::x86_avx2_psll_d:
11444 case Intrinsic::x86_avx2_psll_q:
11445 Opcode = X86ISD::VSHL;
11447 case Intrinsic::x86_sse2_psrl_w:
11448 case Intrinsic::x86_sse2_psrl_d:
11449 case Intrinsic::x86_sse2_psrl_q:
11450 case Intrinsic::x86_avx2_psrl_w:
11451 case Intrinsic::x86_avx2_psrl_d:
11452 case Intrinsic::x86_avx2_psrl_q:
11453 Opcode = X86ISD::VSRL;
11455 case Intrinsic::x86_sse2_psra_w:
11456 case Intrinsic::x86_sse2_psra_d:
11457 case Intrinsic::x86_avx2_psra_w:
11458 case Intrinsic::x86_avx2_psra_d:
11459 Opcode = X86ISD::VSRA;
11462 return DAG.getNode(Opcode, dl, Op.getValueType(),
11463 Op.getOperand(1), Op.getOperand(2));
11466 // SSE/AVX immediate shift intrinsics
11467 case Intrinsic::x86_sse2_pslli_w:
11468 case Intrinsic::x86_sse2_pslli_d:
11469 case Intrinsic::x86_sse2_pslli_q:
11470 case Intrinsic::x86_avx2_pslli_w:
11471 case Intrinsic::x86_avx2_pslli_d:
11472 case Intrinsic::x86_avx2_pslli_q:
11473 case Intrinsic::x86_sse2_psrli_w:
11474 case Intrinsic::x86_sse2_psrli_d:
11475 case Intrinsic::x86_sse2_psrli_q:
11476 case Intrinsic::x86_avx2_psrli_w:
11477 case Intrinsic::x86_avx2_psrli_d:
11478 case Intrinsic::x86_avx2_psrli_q:
11479 case Intrinsic::x86_sse2_psrai_w:
11480 case Intrinsic::x86_sse2_psrai_d:
11481 case Intrinsic::x86_avx2_psrai_w:
11482 case Intrinsic::x86_avx2_psrai_d: {
11485 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11486 case Intrinsic::x86_sse2_pslli_w:
11487 case Intrinsic::x86_sse2_pslli_d:
11488 case Intrinsic::x86_sse2_pslli_q:
11489 case Intrinsic::x86_avx2_pslli_w:
11490 case Intrinsic::x86_avx2_pslli_d:
11491 case Intrinsic::x86_avx2_pslli_q:
11492 Opcode = X86ISD::VSHLI;
11494 case Intrinsic::x86_sse2_psrli_w:
11495 case Intrinsic::x86_sse2_psrli_d:
11496 case Intrinsic::x86_sse2_psrli_q:
11497 case Intrinsic::x86_avx2_psrli_w:
11498 case Intrinsic::x86_avx2_psrli_d:
11499 case Intrinsic::x86_avx2_psrli_q:
11500 Opcode = X86ISD::VSRLI;
11502 case Intrinsic::x86_sse2_psrai_w:
11503 case Intrinsic::x86_sse2_psrai_d:
11504 case Intrinsic::x86_avx2_psrai_w:
11505 case Intrinsic::x86_avx2_psrai_d:
11506 Opcode = X86ISD::VSRAI;
11509 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11510 Op.getOperand(1), Op.getOperand(2), DAG);
11513 case Intrinsic::x86_sse42_pcmpistria128:
11514 case Intrinsic::x86_sse42_pcmpestria128:
11515 case Intrinsic::x86_sse42_pcmpistric128:
11516 case Intrinsic::x86_sse42_pcmpestric128:
11517 case Intrinsic::x86_sse42_pcmpistrio128:
11518 case Intrinsic::x86_sse42_pcmpestrio128:
11519 case Intrinsic::x86_sse42_pcmpistris128:
11520 case Intrinsic::x86_sse42_pcmpestris128:
11521 case Intrinsic::x86_sse42_pcmpistriz128:
11522 case Intrinsic::x86_sse42_pcmpestriz128: {
11526 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11527 case Intrinsic::x86_sse42_pcmpistria128:
11528 Opcode = X86ISD::PCMPISTRI;
11529 X86CC = X86::COND_A;
11531 case Intrinsic::x86_sse42_pcmpestria128:
11532 Opcode = X86ISD::PCMPESTRI;
11533 X86CC = X86::COND_A;
11535 case Intrinsic::x86_sse42_pcmpistric128:
11536 Opcode = X86ISD::PCMPISTRI;
11537 X86CC = X86::COND_B;
11539 case Intrinsic::x86_sse42_pcmpestric128:
11540 Opcode = X86ISD::PCMPESTRI;
11541 X86CC = X86::COND_B;
11543 case Intrinsic::x86_sse42_pcmpistrio128:
11544 Opcode = X86ISD::PCMPISTRI;
11545 X86CC = X86::COND_O;
11547 case Intrinsic::x86_sse42_pcmpestrio128:
11548 Opcode = X86ISD::PCMPESTRI;
11549 X86CC = X86::COND_O;
11551 case Intrinsic::x86_sse42_pcmpistris128:
11552 Opcode = X86ISD::PCMPISTRI;
11553 X86CC = X86::COND_S;
11555 case Intrinsic::x86_sse42_pcmpestris128:
11556 Opcode = X86ISD::PCMPESTRI;
11557 X86CC = X86::COND_S;
11559 case Intrinsic::x86_sse42_pcmpistriz128:
11560 Opcode = X86ISD::PCMPISTRI;
11561 X86CC = X86::COND_E;
11563 case Intrinsic::x86_sse42_pcmpestriz128:
11564 Opcode = X86ISD::PCMPESTRI;
11565 X86CC = X86::COND_E;
11568 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11569 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11570 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11571 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11572 DAG.getConstant(X86CC, MVT::i8),
11573 SDValue(PCMP.getNode(), 1));
11574 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11577 case Intrinsic::x86_sse42_pcmpistri128:
11578 case Intrinsic::x86_sse42_pcmpestri128: {
11580 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11581 Opcode = X86ISD::PCMPISTRI;
11583 Opcode = X86ISD::PCMPESTRI;
11585 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
11586 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11587 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11589 case Intrinsic::x86_fma_vfmadd_ps:
11590 case Intrinsic::x86_fma_vfmadd_pd:
11591 case Intrinsic::x86_fma_vfmsub_ps:
11592 case Intrinsic::x86_fma_vfmsub_pd:
11593 case Intrinsic::x86_fma_vfnmadd_ps:
11594 case Intrinsic::x86_fma_vfnmadd_pd:
11595 case Intrinsic::x86_fma_vfnmsub_ps:
11596 case Intrinsic::x86_fma_vfnmsub_pd:
11597 case Intrinsic::x86_fma_vfmaddsub_ps:
11598 case Intrinsic::x86_fma_vfmaddsub_pd:
11599 case Intrinsic::x86_fma_vfmsubadd_ps:
11600 case Intrinsic::x86_fma_vfmsubadd_pd:
11601 case Intrinsic::x86_fma_vfmadd_ps_256:
11602 case Intrinsic::x86_fma_vfmadd_pd_256:
11603 case Intrinsic::x86_fma_vfmsub_ps_256:
11604 case Intrinsic::x86_fma_vfmsub_pd_256:
11605 case Intrinsic::x86_fma_vfnmadd_ps_256:
11606 case Intrinsic::x86_fma_vfnmadd_pd_256:
11607 case Intrinsic::x86_fma_vfnmsub_ps_256:
11608 case Intrinsic::x86_fma_vfnmsub_pd_256:
11609 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11610 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11611 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11612 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11615 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11616 case Intrinsic::x86_fma_vfmadd_ps:
11617 case Intrinsic::x86_fma_vfmadd_pd:
11618 case Intrinsic::x86_fma_vfmadd_ps_256:
11619 case Intrinsic::x86_fma_vfmadd_pd_256:
11620 Opc = X86ISD::FMADD;
11622 case Intrinsic::x86_fma_vfmsub_ps:
11623 case Intrinsic::x86_fma_vfmsub_pd:
11624 case Intrinsic::x86_fma_vfmsub_ps_256:
11625 case Intrinsic::x86_fma_vfmsub_pd_256:
11626 Opc = X86ISD::FMSUB;
11628 case Intrinsic::x86_fma_vfnmadd_ps:
11629 case Intrinsic::x86_fma_vfnmadd_pd:
11630 case Intrinsic::x86_fma_vfnmadd_ps_256:
11631 case Intrinsic::x86_fma_vfnmadd_pd_256:
11632 Opc = X86ISD::FNMADD;
11634 case Intrinsic::x86_fma_vfnmsub_ps:
11635 case Intrinsic::x86_fma_vfnmsub_pd:
11636 case Intrinsic::x86_fma_vfnmsub_ps_256:
11637 case Intrinsic::x86_fma_vfnmsub_pd_256:
11638 Opc = X86ISD::FNMSUB;
11640 case Intrinsic::x86_fma_vfmaddsub_ps:
11641 case Intrinsic::x86_fma_vfmaddsub_pd:
11642 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11643 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11644 Opc = X86ISD::FMADDSUB;
11646 case Intrinsic::x86_fma_vfmsubadd_ps:
11647 case Intrinsic::x86_fma_vfmsubadd_pd:
11648 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11649 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11650 Opc = X86ISD::FMSUBADD;
11654 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11655 Op.getOperand(2), Op.getOperand(3));
11660 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11661 SDValue Base, SDValue Index,
11662 SDValue ScaleOp, SDValue Chain,
11663 const X86Subtarget * Subtarget) {
11665 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11666 assert(C && "Invalid scale type");
11667 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11668 SDValue Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11669 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11670 Index.getValueType().getVectorNumElements());
11671 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11672 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11673 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11674 SDValue Segment = DAG.getRegister(0, MVT::i32);
11675 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11676 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11677 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11678 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11681 static SDValue getMGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11682 SDValue Src, SDValue Mask, SDValue Base,
11683 SDValue Index, SDValue ScaleOp, SDValue Chain,
11684 const X86Subtarget * Subtarget) {
11686 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11687 assert(C && "Invalid scale type");
11688 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11689 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11690 Index.getValueType().getVectorNumElements());
11691 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11692 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
11693 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11694 SDValue Segment = DAG.getRegister(0, MVT::i32);
11695 if (Src.getOpcode() == ISD::UNDEF)
11696 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
11697 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
11698 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11699 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
11700 return DAG.getMergeValues(RetOps, array_lengthof(RetOps), dl);
11703 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11704 SDValue Src, SDValue Base, SDValue Index,
11705 SDValue ScaleOp, SDValue Chain) {
11707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11708 assert(C && "Invalid scale type");
11709 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11710 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11711 SDValue Segment = DAG.getRegister(0, MVT::i32);
11712 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11713 Index.getValueType().getVectorNumElements());
11714 SDValue MaskInReg = DAG.getConstant(~0, MaskVT);
11715 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11716 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11717 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11718 return SDValue(Res, 1);
11721 static SDValue getMScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
11722 SDValue Src, SDValue Mask, SDValue Base,
11723 SDValue Index, SDValue ScaleOp, SDValue Chain) {
11725 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
11726 assert(C && "Invalid scale type");
11727 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
11728 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
11729 SDValue Segment = DAG.getRegister(0, MVT::i32);
11730 EVT MaskVT = MVT::getVectorVT(MVT::i1,
11731 Index.getValueType().getVectorNumElements());
11732 SDValue MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
11733 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
11734 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
11735 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
11736 return SDValue(Res, 1);
11739 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
11740 SelectionDAG &DAG) {
11742 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11744 default: return SDValue(); // Don't custom lower most intrinsics.
11746 // RDRAND/RDSEED intrinsics.
11747 case Intrinsic::x86_rdrand_16:
11748 case Intrinsic::x86_rdrand_32:
11749 case Intrinsic::x86_rdrand_64:
11750 case Intrinsic::x86_rdseed_16:
11751 case Intrinsic::x86_rdseed_32:
11752 case Intrinsic::x86_rdseed_64: {
11753 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11754 IntNo == Intrinsic::x86_rdseed_32 ||
11755 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11757 // Emit the node with the right value type.
11758 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11759 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11761 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11762 // Otherwise return the value from Rand, which is always 0, casted to i32.
11763 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11764 DAG.getConstant(1, Op->getValueType(1)),
11765 DAG.getConstant(X86::COND_B, MVT::i32),
11766 SDValue(Result.getNode(), 1) };
11767 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11768 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11769 Ops, array_lengthof(Ops));
11771 // Return { result, isValid, chain }.
11772 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11773 SDValue(Result.getNode(), 2));
11775 //int_gather(index, base, scale);
11776 case Intrinsic::x86_avx512_gather_qpd_512:
11777 case Intrinsic::x86_avx512_gather_qps_512:
11778 case Intrinsic::x86_avx512_gather_dpd_512:
11779 case Intrinsic::x86_avx512_gather_qpi_512:
11780 case Intrinsic::x86_avx512_gather_qpq_512:
11781 case Intrinsic::x86_avx512_gather_dpq_512:
11782 case Intrinsic::x86_avx512_gather_dps_512:
11783 case Intrinsic::x86_avx512_gather_dpi_512: {
11786 default: llvm_unreachable("Unexpected intrinsic!");
11787 case Intrinsic::x86_avx512_gather_qps_512: Opc = X86::VGATHERQPSZrm; break;
11788 case Intrinsic::x86_avx512_gather_qpd_512: Opc = X86::VGATHERQPDZrm; break;
11789 case Intrinsic::x86_avx512_gather_dpd_512: Opc = X86::VGATHERDPDZrm; break;
11790 case Intrinsic::x86_avx512_gather_dps_512: Opc = X86::VGATHERDPSZrm; break;
11791 case Intrinsic::x86_avx512_gather_qpi_512: Opc = X86::VPGATHERQDZrm; break;
11792 case Intrinsic::x86_avx512_gather_qpq_512: Opc = X86::VPGATHERQQZrm; break;
11793 case Intrinsic::x86_avx512_gather_dpi_512: Opc = X86::VPGATHERDDZrm; break;
11794 case Intrinsic::x86_avx512_gather_dpq_512: Opc = X86::VPGATHERDQZrm; break;
11796 SDValue Chain = Op.getOperand(0);
11797 SDValue Index = Op.getOperand(2);
11798 SDValue Base = Op.getOperand(3);
11799 SDValue Scale = Op.getOperand(4);
11800 return getGatherNode(Opc, Op, DAG, Base, Index, Scale, Chain, Subtarget);
11802 //int_gather_mask(v1, mask, index, base, scale);
11803 case Intrinsic::x86_avx512_gather_qps_mask_512:
11804 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11805 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11806 case Intrinsic::x86_avx512_gather_dps_mask_512:
11807 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11808 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11809 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11810 case Intrinsic::x86_avx512_gather_dpq_mask_512: {
11813 default: llvm_unreachable("Unexpected intrinsic!");
11814 case Intrinsic::x86_avx512_gather_qps_mask_512:
11815 Opc = X86::VGATHERQPSZrm; break;
11816 case Intrinsic::x86_avx512_gather_qpd_mask_512:
11817 Opc = X86::VGATHERQPDZrm; break;
11818 case Intrinsic::x86_avx512_gather_dpd_mask_512:
11819 Opc = X86::VGATHERDPDZrm; break;
11820 case Intrinsic::x86_avx512_gather_dps_mask_512:
11821 Opc = X86::VGATHERDPSZrm; break;
11822 case Intrinsic::x86_avx512_gather_qpi_mask_512:
11823 Opc = X86::VPGATHERQDZrm; break;
11824 case Intrinsic::x86_avx512_gather_qpq_mask_512:
11825 Opc = X86::VPGATHERQQZrm; break;
11826 case Intrinsic::x86_avx512_gather_dpi_mask_512:
11827 Opc = X86::VPGATHERDDZrm; break;
11828 case Intrinsic::x86_avx512_gather_dpq_mask_512:
11829 Opc = X86::VPGATHERDQZrm; break;
11831 SDValue Chain = Op.getOperand(0);
11832 SDValue Src = Op.getOperand(2);
11833 SDValue Mask = Op.getOperand(3);
11834 SDValue Index = Op.getOperand(4);
11835 SDValue Base = Op.getOperand(5);
11836 SDValue Scale = Op.getOperand(6);
11837 return getMGatherNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
11840 //int_scatter(base, index, v1, scale);
11841 case Intrinsic::x86_avx512_scatter_qpd_512:
11842 case Intrinsic::x86_avx512_scatter_qps_512:
11843 case Intrinsic::x86_avx512_scatter_dpd_512:
11844 case Intrinsic::x86_avx512_scatter_qpi_512:
11845 case Intrinsic::x86_avx512_scatter_qpq_512:
11846 case Intrinsic::x86_avx512_scatter_dpq_512:
11847 case Intrinsic::x86_avx512_scatter_dps_512:
11848 case Intrinsic::x86_avx512_scatter_dpi_512: {
11851 default: llvm_unreachable("Unexpected intrinsic!");
11852 case Intrinsic::x86_avx512_scatter_qpd_512:
11853 Opc = X86::VSCATTERQPDZmr; break;
11854 case Intrinsic::x86_avx512_scatter_qps_512:
11855 Opc = X86::VSCATTERQPSZmr; break;
11856 case Intrinsic::x86_avx512_scatter_dpd_512:
11857 Opc = X86::VSCATTERDPDZmr; break;
11858 case Intrinsic::x86_avx512_scatter_dps_512:
11859 Opc = X86::VSCATTERDPSZmr; break;
11860 case Intrinsic::x86_avx512_scatter_qpi_512:
11861 Opc = X86::VPSCATTERQDZmr; break;
11862 case Intrinsic::x86_avx512_scatter_qpq_512:
11863 Opc = X86::VPSCATTERQQZmr; break;
11864 case Intrinsic::x86_avx512_scatter_dpq_512:
11865 Opc = X86::VPSCATTERDQZmr; break;
11866 case Intrinsic::x86_avx512_scatter_dpi_512:
11867 Opc = X86::VPSCATTERDDZmr; break;
11869 SDValue Chain = Op.getOperand(0);
11870 SDValue Base = Op.getOperand(2);
11871 SDValue Index = Op.getOperand(3);
11872 SDValue Src = Op.getOperand(4);
11873 SDValue Scale = Op.getOperand(5);
11874 return getScatterNode(Opc, Op, DAG, Src, Base, Index, Scale, Chain);
11876 //int_scatter_mask(base, mask, index, v1, scale);
11877 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11878 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11879 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11880 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11881 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11882 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11883 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11884 case Intrinsic::x86_avx512_scatter_dpq_mask_512: {
11887 default: llvm_unreachable("Unexpected intrinsic!");
11888 case Intrinsic::x86_avx512_scatter_qpd_mask_512:
11889 Opc = X86::VSCATTERQPDZmr; break;
11890 case Intrinsic::x86_avx512_scatter_qps_mask_512:
11891 Opc = X86::VSCATTERQPSZmr; break;
11892 case Intrinsic::x86_avx512_scatter_dpd_mask_512:
11893 Opc = X86::VSCATTERDPDZmr; break;
11894 case Intrinsic::x86_avx512_scatter_dps_mask_512:
11895 Opc = X86::VSCATTERDPSZmr; break;
11896 case Intrinsic::x86_avx512_scatter_qpi_mask_512:
11897 Opc = X86::VPSCATTERQDZmr; break;
11898 case Intrinsic::x86_avx512_scatter_qpq_mask_512:
11899 Opc = X86::VPSCATTERQQZmr; break;
11900 case Intrinsic::x86_avx512_scatter_dpq_mask_512:
11901 Opc = X86::VPSCATTERDQZmr; break;
11902 case Intrinsic::x86_avx512_scatter_dpi_mask_512:
11903 Opc = X86::VPSCATTERDDZmr; break;
11905 SDValue Chain = Op.getOperand(0);
11906 SDValue Base = Op.getOperand(2);
11907 SDValue Mask = Op.getOperand(3);
11908 SDValue Index = Op.getOperand(4);
11909 SDValue Src = Op.getOperand(5);
11910 SDValue Scale = Op.getOperand(6);
11911 return getMScatterNode(Opc, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
11913 // XTEST intrinsics.
11914 case Intrinsic::x86_xtest: {
11915 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11916 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11917 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11918 DAG.getConstant(X86::COND_NE, MVT::i8),
11920 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11921 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11922 Ret, SDValue(InTrans.getNode(), 1));
11927 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11928 SelectionDAG &DAG) const {
11929 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11930 MFI->setReturnAddressIsTaken(true);
11932 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11934 EVT PtrVT = getPointerTy();
11937 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11938 const X86RegisterInfo *RegInfo =
11939 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11940 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11941 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11942 DAG.getNode(ISD::ADD, dl, PtrVT,
11943 FrameAddr, Offset),
11944 MachinePointerInfo(), false, false, false, 0);
11947 // Just load the return address.
11948 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11949 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11950 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11953 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11954 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11955 MFI->setFrameAddressIsTaken(true);
11957 EVT VT = Op.getValueType();
11958 SDLoc dl(Op); // FIXME probably not meaningful
11959 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11960 const X86RegisterInfo *RegInfo =
11961 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11962 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11963 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11964 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11965 "Invalid Frame Register!");
11966 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11968 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11969 MachinePointerInfo(),
11970 false, false, false, 0);
11974 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11975 SelectionDAG &DAG) const {
11976 const X86RegisterInfo *RegInfo =
11977 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11978 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11981 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11982 SDValue Chain = Op.getOperand(0);
11983 SDValue Offset = Op.getOperand(1);
11984 SDValue Handler = Op.getOperand(2);
11987 EVT PtrVT = getPointerTy();
11988 const X86RegisterInfo *RegInfo =
11989 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11990 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11991 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11992 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11993 "Invalid Frame Register!");
11994 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11995 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11997 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11998 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11999 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
12000 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
12002 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
12004 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
12005 DAG.getRegister(StoreAddrReg, PtrVT));
12008 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
12009 SelectionDAG &DAG) const {
12011 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
12012 DAG.getVTList(MVT::i32, MVT::Other),
12013 Op.getOperand(0), Op.getOperand(1));
12016 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
12017 SelectionDAG &DAG) const {
12019 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
12020 Op.getOperand(0), Op.getOperand(1));
12023 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
12024 return Op.getOperand(0);
12027 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
12028 SelectionDAG &DAG) const {
12029 SDValue Root = Op.getOperand(0);
12030 SDValue Trmp = Op.getOperand(1); // trampoline
12031 SDValue FPtr = Op.getOperand(2); // nested function
12032 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
12035 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
12036 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12038 if (Subtarget->is64Bit()) {
12039 SDValue OutChains[6];
12041 // Large code-model.
12042 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
12043 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
12045 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
12046 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
12048 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
12050 // Load the pointer to the nested function into R11.
12051 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
12052 SDValue Addr = Trmp;
12053 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12054 Addr, MachinePointerInfo(TrmpAddr),
12057 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12058 DAG.getConstant(2, MVT::i64));
12059 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
12060 MachinePointerInfo(TrmpAddr, 2),
12063 // Load the 'nest' parameter value into R10.
12064 // R10 is specified in X86CallingConv.td
12065 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
12066 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12067 DAG.getConstant(10, MVT::i64));
12068 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12069 Addr, MachinePointerInfo(TrmpAddr, 10),
12072 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12073 DAG.getConstant(12, MVT::i64));
12074 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
12075 MachinePointerInfo(TrmpAddr, 12),
12078 // Jump to the nested function.
12079 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
12080 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12081 DAG.getConstant(20, MVT::i64));
12082 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
12083 Addr, MachinePointerInfo(TrmpAddr, 20),
12086 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
12087 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
12088 DAG.getConstant(22, MVT::i64));
12089 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
12090 MachinePointerInfo(TrmpAddr, 22),
12093 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
12095 const Function *Func =
12096 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
12097 CallingConv::ID CC = Func->getCallingConv();
12102 llvm_unreachable("Unsupported calling convention");
12103 case CallingConv::C:
12104 case CallingConv::X86_StdCall: {
12105 // Pass 'nest' parameter in ECX.
12106 // Must be kept in sync with X86CallingConv.td
12107 NestReg = X86::ECX;
12109 // Check that ECX wasn't needed by an 'inreg' parameter.
12110 FunctionType *FTy = Func->getFunctionType();
12111 const AttributeSet &Attrs = Func->getAttributes();
12113 if (!Attrs.isEmpty() && !Func->isVarArg()) {
12114 unsigned InRegCount = 0;
12117 for (FunctionType::param_iterator I = FTy->param_begin(),
12118 E = FTy->param_end(); I != E; ++I, ++Idx)
12119 if (Attrs.hasAttribute(Idx, Attribute::InReg))
12120 // FIXME: should only count parameters that are lowered to integers.
12121 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
12123 if (InRegCount > 2) {
12124 report_fatal_error("Nest register in use - reduce number of inreg"
12130 case CallingConv::X86_FastCall:
12131 case CallingConv::X86_ThisCall:
12132 case CallingConv::Fast:
12133 // Pass 'nest' parameter in EAX.
12134 // Must be kept in sync with X86CallingConv.td
12135 NestReg = X86::EAX;
12139 SDValue OutChains[4];
12140 SDValue Addr, Disp;
12142 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12143 DAG.getConstant(10, MVT::i32));
12144 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
12146 // This is storing the opcode for MOV32ri.
12147 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
12148 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
12149 OutChains[0] = DAG.getStore(Root, dl,
12150 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
12151 Trmp, MachinePointerInfo(TrmpAddr),
12154 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12155 DAG.getConstant(1, MVT::i32));
12156 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
12157 MachinePointerInfo(TrmpAddr, 1),
12160 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
12161 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12162 DAG.getConstant(5, MVT::i32));
12163 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
12164 MachinePointerInfo(TrmpAddr, 5),
12167 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
12168 DAG.getConstant(6, MVT::i32));
12169 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
12170 MachinePointerInfo(TrmpAddr, 6),
12173 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
12177 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
12178 SelectionDAG &DAG) const {
12180 The rounding mode is in bits 11:10 of FPSR, and has the following
12182 00 Round to nearest
12187 FLT_ROUNDS, on the other hand, expects the following:
12194 To perform the conversion, we do:
12195 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
12198 MachineFunction &MF = DAG.getMachineFunction();
12199 const TargetMachine &TM = MF.getTarget();
12200 const TargetFrameLowering &TFI = *TM.getFrameLowering();
12201 unsigned StackAlignment = TFI.getStackAlignment();
12202 EVT VT = Op.getValueType();
12205 // Save FP Control Word to stack slot
12206 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
12207 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12209 MachineMemOperand *MMO =
12210 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12211 MachineMemOperand::MOStore, 2, 2);
12213 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
12214 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
12215 DAG.getVTList(MVT::Other),
12216 Ops, array_lengthof(Ops), MVT::i16,
12219 // Load FP Control Word from stack slot
12220 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
12221 MachinePointerInfo(), false, false, false, 0);
12223 // Transform as necessary
12225 DAG.getNode(ISD::SRL, DL, MVT::i16,
12226 DAG.getNode(ISD::AND, DL, MVT::i16,
12227 CWD, DAG.getConstant(0x800, MVT::i16)),
12228 DAG.getConstant(11, MVT::i8));
12230 DAG.getNode(ISD::SRL, DL, MVT::i16,
12231 DAG.getNode(ISD::AND, DL, MVT::i16,
12232 CWD, DAG.getConstant(0x400, MVT::i16)),
12233 DAG.getConstant(9, MVT::i8));
12236 DAG.getNode(ISD::AND, DL, MVT::i16,
12237 DAG.getNode(ISD::ADD, DL, MVT::i16,
12238 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
12239 DAG.getConstant(1, MVT::i16)),
12240 DAG.getConstant(3, MVT::i16));
12242 return DAG.getNode((VT.getSizeInBits() < 16 ?
12243 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
12246 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
12247 EVT VT = Op.getValueType();
12249 unsigned NumBits = VT.getSizeInBits();
12252 Op = Op.getOperand(0);
12253 if (VT == MVT::i8) {
12254 // Zero extend to i32 since there is not an i8 bsr.
12256 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12259 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
12260 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12261 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12263 // If src is zero (i.e. bsr sets ZF), returns NumBits.
12266 DAG.getConstant(NumBits+NumBits-1, OpVT),
12267 DAG.getConstant(X86::COND_E, MVT::i8),
12270 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
12272 // Finally xor with NumBits-1.
12273 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12276 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12280 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
12281 EVT VT = Op.getValueType();
12283 unsigned NumBits = VT.getSizeInBits();
12286 Op = Op.getOperand(0);
12287 if (VT == MVT::i8) {
12288 // Zero extend to i32 since there is not an i8 bsr.
12290 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
12293 // Issue a bsr (scan bits in reverse).
12294 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
12295 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
12297 // And xor with NumBits-1.
12298 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
12301 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
12305 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
12306 EVT VT = Op.getValueType();
12307 unsigned NumBits = VT.getSizeInBits();
12309 Op = Op.getOperand(0);
12311 // Issue a bsf (scan bits forward) which also sets EFLAGS.
12312 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12313 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
12315 // If src is zero (i.e. bsf sets ZF), returns NumBits.
12318 DAG.getConstant(NumBits, VT),
12319 DAG.getConstant(X86::COND_E, MVT::i8),
12322 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
12325 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
12326 // ones, and then concatenate the result back.
12327 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
12328 EVT VT = Op.getValueType();
12330 assert(VT.is256BitVector() && VT.isInteger() &&
12331 "Unsupported value type for operation");
12333 unsigned NumElems = VT.getVectorNumElements();
12336 // Extract the LHS vectors
12337 SDValue LHS = Op.getOperand(0);
12338 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12339 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12341 // Extract the RHS vectors
12342 SDValue RHS = Op.getOperand(1);
12343 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12344 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12346 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12347 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12349 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12350 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
12351 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
12354 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
12355 assert(Op.getValueType().is256BitVector() &&
12356 Op.getValueType().isInteger() &&
12357 "Only handle AVX 256-bit vector integer operation");
12358 return Lower256IntArith(Op, DAG);
12361 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
12362 assert(Op.getValueType().is256BitVector() &&
12363 Op.getValueType().isInteger() &&
12364 "Only handle AVX 256-bit vector integer operation");
12365 return Lower256IntArith(Op, DAG);
12368 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
12369 SelectionDAG &DAG) {
12371 EVT VT = Op.getValueType();
12373 // Decompose 256-bit ops into smaller 128-bit ops.
12374 if (VT.is256BitVector() && !Subtarget->hasInt256())
12375 return Lower256IntArith(Op, DAG);
12377 SDValue A = Op.getOperand(0);
12378 SDValue B = Op.getOperand(1);
12380 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
12381 if (VT == MVT::v4i32) {
12382 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
12383 "Should not custom lower when pmuldq is available!");
12385 // Extract the odd parts.
12386 static const int UnpackMask[] = { 1, -1, 3, -1 };
12387 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
12388 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
12390 // Multiply the even parts.
12391 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
12392 // Now multiply odd parts.
12393 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
12395 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
12396 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
12398 // Merge the two vectors back together with a shuffle. This expands into 2
12400 static const int ShufMask[] = { 0, 4, 2, 6 };
12401 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
12404 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
12405 "Only know how to lower V2I64/V4I64 multiply");
12407 // Ahi = psrlqi(a, 32);
12408 // Bhi = psrlqi(b, 32);
12410 // AloBlo = pmuludq(a, b);
12411 // AloBhi = pmuludq(a, Bhi);
12412 // AhiBlo = pmuludq(Ahi, b);
12414 // AloBhi = psllqi(AloBhi, 32);
12415 // AhiBlo = psllqi(AhiBlo, 32);
12416 // return AloBlo + AloBhi + AhiBlo;
12418 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
12420 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
12421 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
12423 // Bit cast to 32-bit vectors for MULUDQ
12424 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
12425 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
12426 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
12427 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
12428 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
12430 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
12431 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
12432 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
12434 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
12435 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
12437 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
12438 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
12441 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
12442 EVT VT = Op.getValueType();
12443 EVT EltTy = VT.getVectorElementType();
12444 unsigned NumElts = VT.getVectorNumElements();
12445 SDValue N0 = Op.getOperand(0);
12448 // Lower sdiv X, pow2-const.
12449 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
12453 APInt SplatValue, SplatUndef;
12454 unsigned SplatBitSize;
12456 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
12458 EltTy.getSizeInBits() < SplatBitSize)
12461 if ((SplatValue != 0) &&
12462 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
12463 unsigned lg2 = SplatValue.countTrailingZeros();
12464 // Splat the sign bit.
12465 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
12466 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
12467 // Add (N0 < 0) ? abs2 - 1 : 0;
12468 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
12469 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
12470 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
12471 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
12472 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
12474 // If we're dividing by a positive value, we're done. Otherwise, we must
12475 // negate the result.
12476 if (SplatValue.isNonNegative())
12479 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
12480 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
12481 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
12486 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
12487 const X86Subtarget *Subtarget) {
12488 EVT VT = Op.getValueType();
12490 SDValue R = Op.getOperand(0);
12491 SDValue Amt = Op.getOperand(1);
12493 // Optimize shl/srl/sra with constant shift amount.
12494 if (isSplatVector(Amt.getNode())) {
12495 SDValue SclrAmt = Amt->getOperand(0);
12496 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
12497 uint64_t ShiftAmt = C->getZExtValue();
12499 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
12500 (Subtarget->hasInt256() &&
12501 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12502 (Subtarget->hasAVX512() &&
12503 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12504 if (Op.getOpcode() == ISD::SHL)
12505 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12506 DAG.getConstant(ShiftAmt, MVT::i32));
12507 if (Op.getOpcode() == ISD::SRL)
12508 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12509 DAG.getConstant(ShiftAmt, MVT::i32));
12510 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
12511 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12512 DAG.getConstant(ShiftAmt, MVT::i32));
12515 if (VT == MVT::v16i8) {
12516 if (Op.getOpcode() == ISD::SHL) {
12517 // Make a large shift.
12518 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
12519 DAG.getConstant(ShiftAmt, MVT::i32));
12520 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12521 // Zero out the rightmost bits.
12522 SmallVector<SDValue, 16> V(16,
12523 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12525 return DAG.getNode(ISD::AND, dl, VT, SHL,
12526 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12528 if (Op.getOpcode() == ISD::SRL) {
12529 // Make a large shift.
12530 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
12531 DAG.getConstant(ShiftAmt, MVT::i32));
12532 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12533 // Zero out the leftmost bits.
12534 SmallVector<SDValue, 16> V(16,
12535 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12537 return DAG.getNode(ISD::AND, dl, VT, SRL,
12538 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
12540 if (Op.getOpcode() == ISD::SRA) {
12541 if (ShiftAmt == 7) {
12542 // R s>> 7 === R s< 0
12543 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12544 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12547 // R s>> a === ((R u>> a) ^ m) - m
12548 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12549 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
12551 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
12552 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12553 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12556 llvm_unreachable("Unknown shift opcode.");
12559 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
12560 if (Op.getOpcode() == ISD::SHL) {
12561 // Make a large shift.
12562 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
12563 DAG.getConstant(ShiftAmt, MVT::i32));
12564 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
12565 // Zero out the rightmost bits.
12566 SmallVector<SDValue, 32> V(32,
12567 DAG.getConstant(uint8_t(-1U << ShiftAmt),
12569 return DAG.getNode(ISD::AND, dl, VT, SHL,
12570 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12572 if (Op.getOpcode() == ISD::SRL) {
12573 // Make a large shift.
12574 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
12575 DAG.getConstant(ShiftAmt, MVT::i32));
12576 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
12577 // Zero out the leftmost bits.
12578 SmallVector<SDValue, 32> V(32,
12579 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
12581 return DAG.getNode(ISD::AND, dl, VT, SRL,
12582 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
12584 if (Op.getOpcode() == ISD::SRA) {
12585 if (ShiftAmt == 7) {
12586 // R s>> 7 === R s< 0
12587 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12588 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
12591 // R s>> a === ((R u>> a) ^ m) - m
12592 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
12593 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
12595 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
12596 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
12597 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
12600 llvm_unreachable("Unknown shift opcode.");
12605 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12606 if (!Subtarget->is64Bit() &&
12607 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12608 Amt.getOpcode() == ISD::BITCAST &&
12609 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12610 Amt = Amt.getOperand(0);
12611 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12612 VT.getVectorNumElements();
12613 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
12614 uint64_t ShiftAmt = 0;
12615 for (unsigned i = 0; i != Ratio; ++i) {
12616 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
12620 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
12622 // Check remaining shift amounts.
12623 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12624 uint64_t ShAmt = 0;
12625 for (unsigned j = 0; j != Ratio; ++j) {
12626 ConstantSDNode *C =
12627 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12631 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12633 if (ShAmt != ShiftAmt)
12636 switch (Op.getOpcode()) {
12638 llvm_unreachable("Unknown shift opcode!");
12640 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12641 DAG.getConstant(ShiftAmt, MVT::i32));
12643 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12644 DAG.getConstant(ShiftAmt, MVT::i32));
12646 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12647 DAG.getConstant(ShiftAmt, MVT::i32));
12654 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12655 const X86Subtarget* Subtarget) {
12656 EVT VT = Op.getValueType();
12658 SDValue R = Op.getOperand(0);
12659 SDValue Amt = Op.getOperand(1);
12661 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12662 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12663 (Subtarget->hasInt256() &&
12664 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12665 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
12666 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
12668 EVT EltVT = VT.getVectorElementType();
12670 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12671 unsigned NumElts = VT.getVectorNumElements();
12673 for (i = 0; i != NumElts; ++i) {
12674 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12678 for (j = i; j != NumElts; ++j) {
12679 SDValue Arg = Amt.getOperand(j);
12680 if (Arg.getOpcode() == ISD::UNDEF) continue;
12681 if (Arg != Amt.getOperand(i))
12684 if (i != NumElts && j == NumElts)
12685 BaseShAmt = Amt.getOperand(i);
12687 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12688 Amt = Amt.getOperand(0);
12689 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12690 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12691 SDValue InVec = Amt.getOperand(0);
12692 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12693 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12695 for (; i != NumElts; ++i) {
12696 SDValue Arg = InVec.getOperand(i);
12697 if (Arg.getOpcode() == ISD::UNDEF) continue;
12701 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12702 if (ConstantSDNode *C =
12703 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12704 unsigned SplatIdx =
12705 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12706 if (C->getZExtValue() == SplatIdx)
12707 BaseShAmt = InVec.getOperand(1);
12710 if (BaseShAmt.getNode() == 0)
12711 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12712 DAG.getIntPtrConstant(0));
12716 if (BaseShAmt.getNode()) {
12717 if (EltVT.bitsGT(MVT::i32))
12718 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12719 else if (EltVT.bitsLT(MVT::i32))
12720 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12722 switch (Op.getOpcode()) {
12724 llvm_unreachable("Unknown shift opcode!");
12726 switch (VT.getSimpleVT().SimpleTy) {
12727 default: return SDValue();
12736 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12739 switch (VT.getSimpleVT().SimpleTy) {
12740 default: return SDValue();
12747 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12750 switch (VT.getSimpleVT().SimpleTy) {
12751 default: return SDValue();
12760 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12766 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12767 if (!Subtarget->is64Bit() &&
12768 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
12769 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
12770 Amt.getOpcode() == ISD::BITCAST &&
12771 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12772 Amt = Amt.getOperand(0);
12773 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12774 VT.getVectorNumElements();
12775 std::vector<SDValue> Vals(Ratio);
12776 for (unsigned i = 0; i != Ratio; ++i)
12777 Vals[i] = Amt.getOperand(i);
12778 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12779 for (unsigned j = 0; j != Ratio; ++j)
12780 if (Vals[j] != Amt.getOperand(i + j))
12783 switch (Op.getOpcode()) {
12785 llvm_unreachable("Unknown shift opcode!");
12787 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12789 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12791 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12798 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
12799 SelectionDAG &DAG) {
12801 EVT VT = Op.getValueType();
12803 SDValue R = Op.getOperand(0);
12804 SDValue Amt = Op.getOperand(1);
12807 if (!Subtarget->hasSSE2())
12810 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12814 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12818 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
12820 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12821 if (Subtarget->hasInt256()) {
12822 if (Op.getOpcode() == ISD::SRL &&
12823 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12824 VT == MVT::v4i64 || VT == MVT::v8i32))
12826 if (Op.getOpcode() == ISD::SHL &&
12827 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12828 VT == MVT::v4i64 || VT == MVT::v8i32))
12830 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12834 // Lower SHL with variable shift amount.
12835 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12836 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12838 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12839 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12840 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12841 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12843 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12844 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12847 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12848 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12850 // Turn 'a' into a mask suitable for VSELECT
12851 SDValue VSelM = DAG.getConstant(0x80, VT);
12852 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12853 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12855 SDValue CM1 = DAG.getConstant(0x0f, VT);
12856 SDValue CM2 = DAG.getConstant(0x3f, VT);
12858 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12859 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12860 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12861 DAG.getConstant(4, MVT::i32), DAG);
12862 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12863 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12866 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12867 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12868 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12870 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12871 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12872 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12873 DAG.getConstant(2, MVT::i32), DAG);
12874 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12875 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12878 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12879 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12880 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12882 // return VSELECT(r, r+r, a);
12883 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12884 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12888 // Decompose 256-bit shifts into smaller 128-bit shifts.
12889 if (VT.is256BitVector()) {
12890 unsigned NumElems = VT.getVectorNumElements();
12891 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12892 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12894 // Extract the two vectors
12895 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12896 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12898 // Recreate the shift amount vectors
12899 SDValue Amt1, Amt2;
12900 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12901 // Constant shift amount
12902 SmallVector<SDValue, 4> Amt1Csts;
12903 SmallVector<SDValue, 4> Amt2Csts;
12904 for (unsigned i = 0; i != NumElems/2; ++i)
12905 Amt1Csts.push_back(Amt->getOperand(i));
12906 for (unsigned i = NumElems/2; i != NumElems; ++i)
12907 Amt2Csts.push_back(Amt->getOperand(i));
12909 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12910 &Amt1Csts[0], NumElems/2);
12911 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12912 &Amt2Csts[0], NumElems/2);
12914 // Variable shift amount
12915 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12916 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12919 // Issue new vector shifts for the smaller types
12920 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12921 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12923 // Concatenate the result back
12924 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12930 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12931 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12932 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12933 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12934 // has only one use.
12935 SDNode *N = Op.getNode();
12936 SDValue LHS = N->getOperand(0);
12937 SDValue RHS = N->getOperand(1);
12938 unsigned BaseOp = 0;
12941 switch (Op.getOpcode()) {
12942 default: llvm_unreachable("Unknown ovf instruction!");
12944 // A subtract of one will be selected as a INC. Note that INC doesn't
12945 // set CF, so we can't do this for UADDO.
12946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12948 BaseOp = X86ISD::INC;
12949 Cond = X86::COND_O;
12952 BaseOp = X86ISD::ADD;
12953 Cond = X86::COND_O;
12956 BaseOp = X86ISD::ADD;
12957 Cond = X86::COND_B;
12960 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12961 // set CF, so we can't do this for USUBO.
12962 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12964 BaseOp = X86ISD::DEC;
12965 Cond = X86::COND_O;
12968 BaseOp = X86ISD::SUB;
12969 Cond = X86::COND_O;
12972 BaseOp = X86ISD::SUB;
12973 Cond = X86::COND_B;
12976 BaseOp = X86ISD::SMUL;
12977 Cond = X86::COND_O;
12979 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12980 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12982 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12985 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12986 DAG.getConstant(X86::COND_O, MVT::i32),
12987 SDValue(Sum.getNode(), 2));
12989 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12993 // Also sets EFLAGS.
12994 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12995 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
12998 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12999 DAG.getConstant(Cond, MVT::i32),
13000 SDValue(Sum.getNode(), 1));
13002 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
13005 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
13006 SelectionDAG &DAG) const {
13008 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
13009 EVT VT = Op.getValueType();
13011 if (!Subtarget->hasSSE2() || !VT.isVector())
13014 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
13015 ExtraVT.getScalarType().getSizeInBits();
13016 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
13018 switch (VT.getSimpleVT().SimpleTy) {
13019 default: return SDValue();
13022 if (!Subtarget->hasFp256())
13024 if (!Subtarget->hasInt256()) {
13025 // needs to be split
13026 unsigned NumElems = VT.getVectorNumElements();
13028 // Extract the LHS vectors
13029 SDValue LHS = Op.getOperand(0);
13030 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13031 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13033 MVT EltVT = VT.getVectorElementType().getSimpleVT();
13034 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13036 EVT ExtraEltVT = ExtraVT.getVectorElementType();
13037 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
13038 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
13040 SDValue Extra = DAG.getValueType(ExtraVT);
13042 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
13043 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
13045 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
13050 // (sext (vzext x)) -> (vsext x)
13051 SDValue Op0 = Op.getOperand(0);
13052 SDValue Op00 = Op0.getOperand(0);
13054 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
13055 if (Op0.getOpcode() == ISD::BITCAST &&
13056 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
13057 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
13058 if (Tmp1.getNode()) {
13059 SDValue Tmp1Op0 = Tmp1.getOperand(0);
13060 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
13061 "This optimization is invalid without a VZEXT.");
13062 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
13065 // If the above didn't work, then just use Shift-Left + Shift-Right.
13066 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
13067 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
13072 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
13073 SelectionDAG &DAG) {
13075 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
13076 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
13077 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
13078 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
13080 // The only fence that needs an instruction is a sequentially-consistent
13081 // cross-thread fence.
13082 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
13083 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
13084 // no-sse2). There isn't any reason to disable it if the target processor
13086 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
13087 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
13089 SDValue Chain = Op.getOperand(0);
13090 SDValue Zero = DAG.getConstant(0, MVT::i32);
13092 DAG.getRegister(X86::ESP, MVT::i32), // Base
13093 DAG.getTargetConstant(1, MVT::i8), // Scale
13094 DAG.getRegister(0, MVT::i32), // Index
13095 DAG.getTargetConstant(0, MVT::i32), // Disp
13096 DAG.getRegister(0, MVT::i32), // Segment.
13100 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
13101 return SDValue(Res, 0);
13104 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
13105 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
13108 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
13109 SelectionDAG &DAG) {
13110 EVT T = Op.getValueType();
13114 switch(T.getSimpleVT().SimpleTy) {
13115 default: llvm_unreachable("Invalid value type!");
13116 case MVT::i8: Reg = X86::AL; size = 1; break;
13117 case MVT::i16: Reg = X86::AX; size = 2; break;
13118 case MVT::i32: Reg = X86::EAX; size = 4; break;
13120 assert(Subtarget->is64Bit() && "Node not type legal!");
13121 Reg = X86::RAX; size = 8;
13124 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
13125 Op.getOperand(2), SDValue());
13126 SDValue Ops[] = { cpIn.getValue(0),
13129 DAG.getTargetConstant(size, MVT::i8),
13130 cpIn.getValue(1) };
13131 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13132 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
13133 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
13134 Ops, array_lengthof(Ops), T, MMO);
13136 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
13140 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
13141 SelectionDAG &DAG) {
13142 assert(Subtarget->is64Bit() && "Result not type legalized?");
13143 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13144 SDValue TheChain = Op.getOperand(0);
13146 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13147 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
13148 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
13150 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
13151 DAG.getConstant(32, MVT::i8));
13153 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
13156 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
13159 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
13160 SelectionDAG &DAG) {
13161 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13162 MVT DstVT = Op.getSimpleValueType();
13163 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
13164 Subtarget->hasMMX() && "Unexpected custom BITCAST");
13165 assert((DstVT == MVT::i64 ||
13166 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
13167 "Unexpected custom BITCAST");
13168 // i64 <=> MMX conversions are Legal.
13169 if (SrcVT==MVT::i64 && DstVT.isVector())
13171 if (DstVT==MVT::i64 && SrcVT.isVector())
13173 // MMX <=> MMX conversions are Legal.
13174 if (SrcVT.isVector() && DstVT.isVector())
13176 // All other conversions need to be expanded.
13180 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
13181 SDNode *Node = Op.getNode();
13183 EVT T = Node->getValueType(0);
13184 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
13185 DAG.getConstant(0, T), Node->getOperand(2));
13186 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
13187 cast<AtomicSDNode>(Node)->getMemoryVT(),
13188 Node->getOperand(0),
13189 Node->getOperand(1), negOp,
13190 cast<AtomicSDNode>(Node)->getSrcValue(),
13191 cast<AtomicSDNode>(Node)->getAlignment(),
13192 cast<AtomicSDNode>(Node)->getOrdering(),
13193 cast<AtomicSDNode>(Node)->getSynchScope());
13196 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
13197 SDNode *Node = Op.getNode();
13199 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13201 // Convert seq_cst store -> xchg
13202 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
13203 // FIXME: On 32-bit, store -> fist or movq would be more efficient
13204 // (The only way to get a 16-byte store is cmpxchg16b)
13205 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
13206 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
13207 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13208 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
13209 cast<AtomicSDNode>(Node)->getMemoryVT(),
13210 Node->getOperand(0),
13211 Node->getOperand(1), Node->getOperand(2),
13212 cast<AtomicSDNode>(Node)->getMemOperand(),
13213 cast<AtomicSDNode>(Node)->getOrdering(),
13214 cast<AtomicSDNode>(Node)->getSynchScope());
13215 return Swap.getValue(1);
13217 // Other atomic stores have a simple pattern.
13221 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
13222 EVT VT = Op.getNode()->getValueType(0);
13224 // Let legalize expand this if it isn't a legal type yet.
13225 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
13228 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
13231 bool ExtraOp = false;
13232 switch (Op.getOpcode()) {
13233 default: llvm_unreachable("Invalid code");
13234 case ISD::ADDC: Opc = X86ISD::ADD; break;
13235 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
13236 case ISD::SUBC: Opc = X86ISD::SUB; break;
13237 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
13241 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13243 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
13244 Op.getOperand(1), Op.getOperand(2));
13247 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
13248 SelectionDAG &DAG) {
13249 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
13251 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
13252 // which returns the values as { float, float } (in XMM0) or
13253 // { double, double } (which is returned in XMM0, XMM1).
13255 SDValue Arg = Op.getOperand(0);
13256 EVT ArgVT = Arg.getValueType();
13257 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13259 TargetLowering::ArgListTy Args;
13260 TargetLowering::ArgListEntry Entry;
13264 Entry.isSExt = false;
13265 Entry.isZExt = false;
13266 Args.push_back(Entry);
13268 bool isF64 = ArgVT == MVT::f64;
13269 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
13270 // the small struct {f32, f32} is returned in (eax, edx). For f64,
13271 // the results are returned via SRet in memory.
13272 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
13273 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13274 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
13276 Type *RetTy = isF64
13277 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
13278 : (Type*)VectorType::get(ArgTy, 4);
13280 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
13281 false, false, false, false, 0,
13282 CallingConv::C, /*isTaillCall=*/false,
13283 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
13284 Callee, Args, DAG, dl);
13285 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
13288 // Returned in xmm0 and xmm1.
13289 return CallResult.first;
13291 // Returned in bits 0:31 and 32:64 xmm0.
13292 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13293 CallResult.first, DAG.getIntPtrConstant(0));
13294 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
13295 CallResult.first, DAG.getIntPtrConstant(1));
13296 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
13297 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
13300 /// LowerOperation - Provide custom lowering hooks for some operations.
13302 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
13303 switch (Op.getOpcode()) {
13304 default: llvm_unreachable("Should not custom lower this!");
13305 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
13306 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
13307 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
13308 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
13309 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
13310 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
13311 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
13312 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
13313 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
13314 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
13315 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
13316 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
13317 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
13318 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
13319 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
13320 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
13321 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
13322 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
13323 case ISD::SHL_PARTS:
13324 case ISD::SRA_PARTS:
13325 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
13326 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
13327 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
13328 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
13329 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
13330 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
13331 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
13332 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
13333 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
13334 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
13335 case ISD::FABS: return LowerFABS(Op, DAG);
13336 case ISD::FNEG: return LowerFNEG(Op, DAG);
13337 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
13338 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
13339 case ISD::SETCC: return LowerSETCC(Op, DAG);
13340 case ISD::SELECT: return LowerSELECT(Op, DAG);
13341 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
13342 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
13343 case ISD::VASTART: return LowerVASTART(Op, DAG);
13344 case ISD::VAARG: return LowerVAARG(Op, DAG);
13345 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
13346 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
13347 case ISD::INTRINSIC_VOID:
13348 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
13349 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
13350 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
13351 case ISD::FRAME_TO_ARGS_OFFSET:
13352 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
13353 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
13354 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
13355 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
13356 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
13357 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
13358 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
13359 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
13360 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
13361 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
13362 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
13363 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
13366 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
13372 case ISD::UMULO: return LowerXALUO(Op, DAG);
13373 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
13374 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
13378 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
13379 case ISD::ADD: return LowerADD(Op, DAG);
13380 case ISD::SUB: return LowerSUB(Op, DAG);
13381 case ISD::SDIV: return LowerSDIV(Op, DAG);
13382 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
13386 static void ReplaceATOMIC_LOAD(SDNode *Node,
13387 SmallVectorImpl<SDValue> &Results,
13388 SelectionDAG &DAG) {
13390 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
13392 // Convert wide load -> cmpxchg8b/cmpxchg16b
13393 // FIXME: On 32-bit, load -> fild or movq would be more efficient
13394 // (The only way to get a 16-byte load is cmpxchg16b)
13395 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
13396 SDValue Zero = DAG.getConstant(0, VT);
13397 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
13398 Node->getOperand(0),
13399 Node->getOperand(1), Zero, Zero,
13400 cast<AtomicSDNode>(Node)->getMemOperand(),
13401 cast<AtomicSDNode>(Node)->getOrdering(),
13402 cast<AtomicSDNode>(Node)->getSynchScope());
13403 Results.push_back(Swap.getValue(0));
13404 Results.push_back(Swap.getValue(1));
13408 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
13409 SelectionDAG &DAG, unsigned NewOp) {
13411 assert (Node->getValueType(0) == MVT::i64 &&
13412 "Only know how to expand i64 atomics");
13414 SDValue Chain = Node->getOperand(0);
13415 SDValue In1 = Node->getOperand(1);
13416 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13417 Node->getOperand(2), DAG.getIntPtrConstant(0));
13418 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
13419 Node->getOperand(2), DAG.getIntPtrConstant(1));
13420 SDValue Ops[] = { Chain, In1, In2L, In2H };
13421 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
13423 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
13424 cast<MemSDNode>(Node)->getMemOperand());
13425 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
13426 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
13427 Results.push_back(Result.getValue(2));
13430 /// ReplaceNodeResults - Replace a node with an illegal result type
13431 /// with a new node built out of custom code.
13432 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
13433 SmallVectorImpl<SDValue>&Results,
13434 SelectionDAG &DAG) const {
13436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13437 switch (N->getOpcode()) {
13439 llvm_unreachable("Do not know how to custom type legalize this operation!");
13440 case ISD::SIGN_EXTEND_INREG:
13445 // We don't want to expand or promote these.
13447 case ISD::FP_TO_SINT:
13448 case ISD::FP_TO_UINT: {
13449 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
13451 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
13454 std::pair<SDValue,SDValue> Vals =
13455 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
13456 SDValue FIST = Vals.first, StackSlot = Vals.second;
13457 if (FIST.getNode() != 0) {
13458 EVT VT = N->getValueType(0);
13459 // Return a load from the stack slot.
13460 if (StackSlot.getNode() != 0)
13461 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
13462 MachinePointerInfo(),
13463 false, false, false, 0));
13465 Results.push_back(FIST);
13469 case ISD::UINT_TO_FP: {
13470 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
13471 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
13472 N->getValueType(0) != MVT::v2f32)
13474 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
13476 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13478 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
13479 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
13480 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
13481 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
13482 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
13483 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
13486 case ISD::FP_ROUND: {
13487 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
13489 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
13490 Results.push_back(V);
13493 case ISD::READCYCLECOUNTER: {
13494 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13495 SDValue TheChain = N->getOperand(0);
13496 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
13497 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
13499 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
13501 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
13502 SDValue Ops[] = { eax, edx };
13503 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
13504 array_lengthof(Ops)));
13505 Results.push_back(edx.getValue(1));
13508 case ISD::ATOMIC_CMP_SWAP: {
13509 EVT T = N->getValueType(0);
13510 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
13511 bool Regs64bit = T == MVT::i128;
13512 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
13513 SDValue cpInL, cpInH;
13514 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13515 DAG.getConstant(0, HalfT));
13516 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
13517 DAG.getConstant(1, HalfT));
13518 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
13519 Regs64bit ? X86::RAX : X86::EAX,
13521 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
13522 Regs64bit ? X86::RDX : X86::EDX,
13523 cpInH, cpInL.getValue(1));
13524 SDValue swapInL, swapInH;
13525 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13526 DAG.getConstant(0, HalfT));
13527 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
13528 DAG.getConstant(1, HalfT));
13529 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
13530 Regs64bit ? X86::RBX : X86::EBX,
13531 swapInL, cpInH.getValue(1));
13532 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
13533 Regs64bit ? X86::RCX : X86::ECX,
13534 swapInH, swapInL.getValue(1));
13535 SDValue Ops[] = { swapInH.getValue(0),
13537 swapInH.getValue(1) };
13538 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
13539 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
13540 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
13541 X86ISD::LCMPXCHG8_DAG;
13542 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
13543 Ops, array_lengthof(Ops), T, MMO);
13544 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
13545 Regs64bit ? X86::RAX : X86::EAX,
13546 HalfT, Result.getValue(1));
13547 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
13548 Regs64bit ? X86::RDX : X86::EDX,
13549 HalfT, cpOutL.getValue(2));
13550 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
13551 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
13552 Results.push_back(cpOutH.getValue(1));
13555 case ISD::ATOMIC_LOAD_ADD:
13556 case ISD::ATOMIC_LOAD_AND:
13557 case ISD::ATOMIC_LOAD_NAND:
13558 case ISD::ATOMIC_LOAD_OR:
13559 case ISD::ATOMIC_LOAD_SUB:
13560 case ISD::ATOMIC_LOAD_XOR:
13561 case ISD::ATOMIC_LOAD_MAX:
13562 case ISD::ATOMIC_LOAD_MIN:
13563 case ISD::ATOMIC_LOAD_UMAX:
13564 case ISD::ATOMIC_LOAD_UMIN:
13565 case ISD::ATOMIC_SWAP: {
13567 switch (N->getOpcode()) {
13568 default: llvm_unreachable("Unexpected opcode");
13569 case ISD::ATOMIC_LOAD_ADD:
13570 Opc = X86ISD::ATOMADD64_DAG;
13572 case ISD::ATOMIC_LOAD_AND:
13573 Opc = X86ISD::ATOMAND64_DAG;
13575 case ISD::ATOMIC_LOAD_NAND:
13576 Opc = X86ISD::ATOMNAND64_DAG;
13578 case ISD::ATOMIC_LOAD_OR:
13579 Opc = X86ISD::ATOMOR64_DAG;
13581 case ISD::ATOMIC_LOAD_SUB:
13582 Opc = X86ISD::ATOMSUB64_DAG;
13584 case ISD::ATOMIC_LOAD_XOR:
13585 Opc = X86ISD::ATOMXOR64_DAG;
13587 case ISD::ATOMIC_LOAD_MAX:
13588 Opc = X86ISD::ATOMMAX64_DAG;
13590 case ISD::ATOMIC_LOAD_MIN:
13591 Opc = X86ISD::ATOMMIN64_DAG;
13593 case ISD::ATOMIC_LOAD_UMAX:
13594 Opc = X86ISD::ATOMUMAX64_DAG;
13596 case ISD::ATOMIC_LOAD_UMIN:
13597 Opc = X86ISD::ATOMUMIN64_DAG;
13599 case ISD::ATOMIC_SWAP:
13600 Opc = X86ISD::ATOMSWAP64_DAG;
13603 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
13606 case ISD::ATOMIC_LOAD:
13607 ReplaceATOMIC_LOAD(N, Results, DAG);
13611 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
13613 default: return NULL;
13614 case X86ISD::BSF: return "X86ISD::BSF";
13615 case X86ISD::BSR: return "X86ISD::BSR";
13616 case X86ISD::SHLD: return "X86ISD::SHLD";
13617 case X86ISD::SHRD: return "X86ISD::SHRD";
13618 case X86ISD::FAND: return "X86ISD::FAND";
13619 case X86ISD::FANDN: return "X86ISD::FANDN";
13620 case X86ISD::FOR: return "X86ISD::FOR";
13621 case X86ISD::FXOR: return "X86ISD::FXOR";
13622 case X86ISD::FSRL: return "X86ISD::FSRL";
13623 case X86ISD::FILD: return "X86ISD::FILD";
13624 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
13625 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
13626 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
13627 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
13628 case X86ISD::FLD: return "X86ISD::FLD";
13629 case X86ISD::FST: return "X86ISD::FST";
13630 case X86ISD::CALL: return "X86ISD::CALL";
13631 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
13632 case X86ISD::BT: return "X86ISD::BT";
13633 case X86ISD::CMP: return "X86ISD::CMP";
13634 case X86ISD::COMI: return "X86ISD::COMI";
13635 case X86ISD::UCOMI: return "X86ISD::UCOMI";
13636 case X86ISD::CMPM: return "X86ISD::CMPM";
13637 case X86ISD::CMPMU: return "X86ISD::CMPMU";
13638 case X86ISD::SETCC: return "X86ISD::SETCC";
13639 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
13640 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13641 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13642 case X86ISD::CMOV: return "X86ISD::CMOV";
13643 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13644 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13645 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13646 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13647 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13648 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13649 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13650 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13651 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13652 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13653 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13654 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13655 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13656 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13657 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13658 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13659 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13660 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13661 case X86ISD::HADD: return "X86ISD::HADD";
13662 case X86ISD::HSUB: return "X86ISD::HSUB";
13663 case X86ISD::FHADD: return "X86ISD::FHADD";
13664 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13665 case X86ISD::UMAX: return "X86ISD::UMAX";
13666 case X86ISD::UMIN: return "X86ISD::UMIN";
13667 case X86ISD::SMAX: return "X86ISD::SMAX";
13668 case X86ISD::SMIN: return "X86ISD::SMIN";
13669 case X86ISD::FMAX: return "X86ISD::FMAX";
13670 case X86ISD::FMIN: return "X86ISD::FMIN";
13671 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13672 case X86ISD::FMINC: return "X86ISD::FMINC";
13673 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13674 case X86ISD::FRCP: return "X86ISD::FRCP";
13675 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13676 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13677 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13678 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13679 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13680 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13681 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13682 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13683 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13684 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13685 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13686 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13687 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13688 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13689 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13690 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13691 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13692 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13693 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13694 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13695 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13696 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13697 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
13698 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
13699 case X86ISD::VINSERT: return "X86ISD::VINSERT";
13700 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13701 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13702 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13703 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13704 case X86ISD::VSHL: return "X86ISD::VSHL";
13705 case X86ISD::VSRL: return "X86ISD::VSRL";
13706 case X86ISD::VSRA: return "X86ISD::VSRA";
13707 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13708 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13709 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13710 case X86ISD::CMPP: return "X86ISD::CMPP";
13711 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13712 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13713 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
13714 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
13715 case X86ISD::ADD: return "X86ISD::ADD";
13716 case X86ISD::SUB: return "X86ISD::SUB";
13717 case X86ISD::ADC: return "X86ISD::ADC";
13718 case X86ISD::SBB: return "X86ISD::SBB";
13719 case X86ISD::SMUL: return "X86ISD::SMUL";
13720 case X86ISD::UMUL: return "X86ISD::UMUL";
13721 case X86ISD::INC: return "X86ISD::INC";
13722 case X86ISD::DEC: return "X86ISD::DEC";
13723 case X86ISD::OR: return "X86ISD::OR";
13724 case X86ISD::XOR: return "X86ISD::XOR";
13725 case X86ISD::AND: return "X86ISD::AND";
13726 case X86ISD::BLSI: return "X86ISD::BLSI";
13727 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13728 case X86ISD::BLSR: return "X86ISD::BLSR";
13729 case X86ISD::BZHI: return "X86ISD::BZHI";
13730 case X86ISD::BEXTR: return "X86ISD::BEXTR";
13731 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13732 case X86ISD::PTEST: return "X86ISD::PTEST";
13733 case X86ISD::TESTP: return "X86ISD::TESTP";
13734 case X86ISD::TESTM: return "X86ISD::TESTM";
13735 case X86ISD::KORTEST: return "X86ISD::KORTEST";
13736 case X86ISD::KTEST: return "X86ISD::KTEST";
13737 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13738 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13739 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13740 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13741 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13742 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13743 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13744 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13745 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13746 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13747 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13748 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13749 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13750 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13751 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13752 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13753 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13754 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13755 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
13756 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13757 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13758 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13759 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
13760 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13761 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13762 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13763 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13764 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13765 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13766 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13767 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13768 case X86ISD::SAHF: return "X86ISD::SAHF";
13769 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13770 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13771 case X86ISD::FMADD: return "X86ISD::FMADD";
13772 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13773 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13774 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13775 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13776 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13777 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13778 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13779 case X86ISD::XTEST: return "X86ISD::XTEST";
13783 // isLegalAddressingMode - Return true if the addressing mode represented
13784 // by AM is legal for this target, for a load/store of the specified type.
13785 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13787 // X86 supports extremely general addressing modes.
13788 CodeModel::Model M = getTargetMachine().getCodeModel();
13789 Reloc::Model R = getTargetMachine().getRelocationModel();
13791 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13792 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13797 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13799 // If a reference to this global requires an extra load, we can't fold it.
13800 if (isGlobalStubReference(GVFlags))
13803 // If BaseGV requires a register for the PIC base, we cannot also have a
13804 // BaseReg specified.
13805 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13808 // If lower 4G is not available, then we must use rip-relative addressing.
13809 if ((M != CodeModel::Small || R != Reloc::Static) &&
13810 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13814 switch (AM.Scale) {
13820 // These scales always work.
13825 // These scales are formed with basereg+scalereg. Only accept if there is
13830 default: // Other stuff never works.
13837 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13838 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13840 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13841 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13842 return NumBits1 > NumBits2;
13845 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
13846 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13849 if (!isTypeLegal(EVT::getEVT(Ty1)))
13852 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
13854 // Assuming the caller doesn't have a zeroext or signext return parameter,
13855 // truncation all the way down to i1 is valid.
13859 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13860 return isInt<32>(Imm);
13863 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13864 // Can also use sub to handle negated immediates.
13865 return isInt<32>(Imm);
13868 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13869 if (!VT1.isInteger() || !VT2.isInteger())
13871 unsigned NumBits1 = VT1.getSizeInBits();
13872 unsigned NumBits2 = VT2.getSizeInBits();
13873 return NumBits1 > NumBits2;
13876 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13877 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13878 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13881 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13882 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13883 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13886 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13887 EVT VT1 = Val.getValueType();
13888 if (isZExtFree(VT1, VT2))
13891 if (Val.getOpcode() != ISD::LOAD)
13894 if (!VT1.isSimple() || !VT1.isInteger() ||
13895 !VT2.isSimple() || !VT2.isInteger())
13898 switch (VT1.getSimpleVT().SimpleTy) {
13903 // X86 has 8, 16, and 32-bit zero-extending loads.
13911 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13912 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13915 VT = VT.getScalarType();
13917 if (!VT.isSimple())
13920 switch (VT.getSimpleVT().SimpleTy) {
13931 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13932 // i16 instructions are longer (0x66 prefix) and potentially slower.
13933 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13936 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13937 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13938 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13939 /// are assumed to be legal.
13941 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13943 if (!VT.isSimple())
13946 MVT SVT = VT.getSimpleVT();
13948 // Very little shuffling can be done for 64-bit vectors right now.
13949 if (VT.getSizeInBits() == 64)
13952 // FIXME: pshufb, blends, shifts.
13953 return (SVT.getVectorNumElements() == 2 ||
13954 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13955 isMOVLMask(M, SVT) ||
13956 isSHUFPMask(M, SVT) ||
13957 isPSHUFDMask(M, SVT) ||
13958 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
13959 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
13960 isPALIGNRMask(M, SVT, Subtarget) ||
13961 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
13962 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
13963 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
13964 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()));
13968 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13970 if (!VT.isSimple())
13973 MVT SVT = VT.getSimpleVT();
13974 unsigned NumElts = SVT.getVectorNumElements();
13975 // FIXME: This collection of masks seems suspect.
13978 if (NumElts == 4 && SVT.is128BitVector()) {
13979 return (isMOVLMask(Mask, SVT) ||
13980 isCommutedMOVLMask(Mask, SVT, true) ||
13981 isSHUFPMask(Mask, SVT) ||
13982 isSHUFPMask(Mask, SVT, /* Commuted */ true));
13987 //===----------------------------------------------------------------------===//
13988 // X86 Scheduler Hooks
13989 //===----------------------------------------------------------------------===//
13991 /// Utility function to emit xbegin specifying the start of an RTM region.
13992 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
13993 const TargetInstrInfo *TII) {
13994 DebugLoc DL = MI->getDebugLoc();
13996 const BasicBlock *BB = MBB->getBasicBlock();
13997 MachineFunction::iterator I = MBB;
14000 // For the v = xbegin(), we generate
14011 MachineBasicBlock *thisMBB = MBB;
14012 MachineFunction *MF = MBB->getParent();
14013 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14014 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14015 MF->insert(I, mainMBB);
14016 MF->insert(I, sinkMBB);
14018 // Transfer the remainder of BB and its successor edges to sinkMBB.
14019 sinkMBB->splice(sinkMBB->begin(), MBB,
14020 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14021 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14025 // # fallthrough to mainMBB
14026 // # abortion to sinkMBB
14027 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
14028 thisMBB->addSuccessor(mainMBB);
14029 thisMBB->addSuccessor(sinkMBB);
14033 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
14034 mainMBB->addSuccessor(sinkMBB);
14037 // EAX is live into the sinkMBB
14038 sinkMBB->addLiveIn(X86::EAX);
14039 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14040 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14043 MI->eraseFromParent();
14047 // Get CMPXCHG opcode for the specified data type.
14048 static unsigned getCmpXChgOpcode(EVT VT) {
14049 switch (VT.getSimpleVT().SimpleTy) {
14050 case MVT::i8: return X86::LCMPXCHG8;
14051 case MVT::i16: return X86::LCMPXCHG16;
14052 case MVT::i32: return X86::LCMPXCHG32;
14053 case MVT::i64: return X86::LCMPXCHG64;
14057 llvm_unreachable("Invalid operand size!");
14060 // Get LOAD opcode for the specified data type.
14061 static unsigned getLoadOpcode(EVT VT) {
14062 switch (VT.getSimpleVT().SimpleTy) {
14063 case MVT::i8: return X86::MOV8rm;
14064 case MVT::i16: return X86::MOV16rm;
14065 case MVT::i32: return X86::MOV32rm;
14066 case MVT::i64: return X86::MOV64rm;
14070 llvm_unreachable("Invalid operand size!");
14073 // Get opcode of the non-atomic one from the specified atomic instruction.
14074 static unsigned getNonAtomicOpcode(unsigned Opc) {
14076 case X86::ATOMAND8: return X86::AND8rr;
14077 case X86::ATOMAND16: return X86::AND16rr;
14078 case X86::ATOMAND32: return X86::AND32rr;
14079 case X86::ATOMAND64: return X86::AND64rr;
14080 case X86::ATOMOR8: return X86::OR8rr;
14081 case X86::ATOMOR16: return X86::OR16rr;
14082 case X86::ATOMOR32: return X86::OR32rr;
14083 case X86::ATOMOR64: return X86::OR64rr;
14084 case X86::ATOMXOR8: return X86::XOR8rr;
14085 case X86::ATOMXOR16: return X86::XOR16rr;
14086 case X86::ATOMXOR32: return X86::XOR32rr;
14087 case X86::ATOMXOR64: return X86::XOR64rr;
14089 llvm_unreachable("Unhandled atomic-load-op opcode!");
14092 // Get opcode of the non-atomic one from the specified atomic instruction with
14094 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
14095 unsigned &ExtraOpc) {
14097 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
14098 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
14099 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
14100 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
14101 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
14102 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
14103 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
14104 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
14105 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
14106 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
14107 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
14108 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
14109 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
14110 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
14111 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
14112 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
14113 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
14114 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
14115 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
14116 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
14118 llvm_unreachable("Unhandled atomic-load-op opcode!");
14121 // Get opcode of the non-atomic one from the specified atomic instruction for
14122 // 64-bit data type on 32-bit target.
14123 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
14125 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
14126 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
14127 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
14128 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
14129 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
14130 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
14131 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
14132 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
14133 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
14134 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
14136 llvm_unreachable("Unhandled atomic-load-op opcode!");
14139 // Get opcode of the non-atomic one from the specified atomic instruction for
14140 // 64-bit data type on 32-bit target with extra opcode.
14141 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
14143 unsigned &ExtraOpc) {
14145 case X86::ATOMNAND6432:
14146 ExtraOpc = X86::NOT32r;
14147 HiOpc = X86::AND32rr;
14148 return X86::AND32rr;
14150 llvm_unreachable("Unhandled atomic-load-op opcode!");
14153 // Get pseudo CMOV opcode from the specified data type.
14154 static unsigned getPseudoCMOVOpc(EVT VT) {
14155 switch (VT.getSimpleVT().SimpleTy) {
14156 case MVT::i8: return X86::CMOV_GR8;
14157 case MVT::i16: return X86::CMOV_GR16;
14158 case MVT::i32: return X86::CMOV_GR32;
14162 llvm_unreachable("Unknown CMOV opcode!");
14165 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
14166 // They will be translated into a spin-loop or compare-exchange loop from
14169 // dst = atomic-fetch-op MI.addr, MI.val
14175 // t1 = LOAD MI.addr
14177 // t4 = phi(t1, t3 / loop)
14178 // t2 = OP MI.val, t4
14180 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
14186 MachineBasicBlock *
14187 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
14188 MachineBasicBlock *MBB) const {
14189 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14190 DebugLoc DL = MI->getDebugLoc();
14192 MachineFunction *MF = MBB->getParent();
14193 MachineRegisterInfo &MRI = MF->getRegInfo();
14195 const BasicBlock *BB = MBB->getBasicBlock();
14196 MachineFunction::iterator I = MBB;
14199 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
14200 "Unexpected number of operands");
14202 assert(MI->hasOneMemOperand() &&
14203 "Expected atomic-load-op to have one memoperand");
14205 // Memory Reference
14206 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14207 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14209 unsigned DstReg, SrcReg;
14210 unsigned MemOpndSlot;
14212 unsigned CurOp = 0;
14214 DstReg = MI->getOperand(CurOp++).getReg();
14215 MemOpndSlot = CurOp;
14216 CurOp += X86::AddrNumOperands;
14217 SrcReg = MI->getOperand(CurOp++).getReg();
14219 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14220 MVT::SimpleValueType VT = *RC->vt_begin();
14221 unsigned t1 = MRI.createVirtualRegister(RC);
14222 unsigned t2 = MRI.createVirtualRegister(RC);
14223 unsigned t3 = MRI.createVirtualRegister(RC);
14224 unsigned t4 = MRI.createVirtualRegister(RC);
14225 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
14227 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
14228 unsigned LOADOpc = getLoadOpcode(VT);
14230 // For the atomic load-arith operator, we generate
14233 // t1 = LOAD [MI.addr]
14235 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
14236 // t1 = OP MI.val, EAX
14238 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
14244 MachineBasicBlock *thisMBB = MBB;
14245 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14246 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14247 MF->insert(I, mainMBB);
14248 MF->insert(I, sinkMBB);
14250 MachineInstrBuilder MIB;
14252 // Transfer the remainder of BB and its successor edges to sinkMBB.
14253 sinkMBB->splice(sinkMBB->begin(), MBB,
14254 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14255 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14258 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
14259 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14260 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14262 NewMO.setIsKill(false);
14263 MIB.addOperand(NewMO);
14265 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14266 unsigned flags = (*MMOI)->getFlags();
14267 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14268 MachineMemOperand *MMO =
14269 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14270 (*MMOI)->getSize(),
14271 (*MMOI)->getBaseAlignment(),
14272 (*MMOI)->getTBAAInfo(),
14273 (*MMOI)->getRanges());
14274 MIB.addMemOperand(MMO);
14277 thisMBB->addSuccessor(mainMBB);
14280 MachineBasicBlock *origMainMBB = mainMBB;
14283 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
14284 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14286 unsigned Opc = MI->getOpcode();
14289 llvm_unreachable("Unhandled atomic-load-op opcode!");
14290 case X86::ATOMAND8:
14291 case X86::ATOMAND16:
14292 case X86::ATOMAND32:
14293 case X86::ATOMAND64:
14295 case X86::ATOMOR16:
14296 case X86::ATOMOR32:
14297 case X86::ATOMOR64:
14298 case X86::ATOMXOR8:
14299 case X86::ATOMXOR16:
14300 case X86::ATOMXOR32:
14301 case X86::ATOMXOR64: {
14302 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
14303 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
14307 case X86::ATOMNAND8:
14308 case X86::ATOMNAND16:
14309 case X86::ATOMNAND32:
14310 case X86::ATOMNAND64: {
14311 unsigned Tmp = MRI.createVirtualRegister(RC);
14313 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
14314 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
14316 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
14319 case X86::ATOMMAX8:
14320 case X86::ATOMMAX16:
14321 case X86::ATOMMAX32:
14322 case X86::ATOMMAX64:
14323 case X86::ATOMMIN8:
14324 case X86::ATOMMIN16:
14325 case X86::ATOMMIN32:
14326 case X86::ATOMMIN64:
14327 case X86::ATOMUMAX8:
14328 case X86::ATOMUMAX16:
14329 case X86::ATOMUMAX32:
14330 case X86::ATOMUMAX64:
14331 case X86::ATOMUMIN8:
14332 case X86::ATOMUMIN16:
14333 case X86::ATOMUMIN32:
14334 case X86::ATOMUMIN64: {
14336 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
14338 BuildMI(mainMBB, DL, TII->get(CMPOpc))
14342 if (Subtarget->hasCMov()) {
14343 if (VT != MVT::i8) {
14345 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
14349 // Promote i8 to i32 to use CMOV32
14350 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14351 const TargetRegisterClass *RC32 =
14352 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
14353 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
14354 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
14355 unsigned Tmp = MRI.createVirtualRegister(RC32);
14357 unsigned Undef = MRI.createVirtualRegister(RC32);
14358 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
14360 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
14363 .addImm(X86::sub_8bit);
14364 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
14367 .addImm(X86::sub_8bit);
14369 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
14373 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
14374 .addReg(Tmp, 0, X86::sub_8bit);
14377 // Use pseudo select and lower them.
14378 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
14379 "Invalid atomic-load-op transformation!");
14380 unsigned SelOpc = getPseudoCMOVOpc(VT);
14381 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
14382 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
14383 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
14384 .addReg(SrcReg).addReg(t4)
14386 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14387 // Replace the original PHI node as mainMBB is changed after CMOV
14389 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
14390 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
14391 Phi->eraseFromParent();
14397 // Copy PhyReg back from virtual register.
14398 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
14401 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14402 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14403 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14405 NewMO.setIsKill(false);
14406 MIB.addOperand(NewMO);
14409 MIB.setMemRefs(MMOBegin, MMOEnd);
14411 // Copy PhyReg back to virtual register.
14412 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
14415 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14417 mainMBB->addSuccessor(origMainMBB);
14418 mainMBB->addSuccessor(sinkMBB);
14421 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14422 TII->get(TargetOpcode::COPY), DstReg)
14425 MI->eraseFromParent();
14429 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
14430 // instructions. They will be translated into a spin-loop or compare-exchange
14434 // dst = atomic-fetch-op MI.addr, MI.val
14440 // t1L = LOAD [MI.addr + 0]
14441 // t1H = LOAD [MI.addr + 4]
14443 // t4L = phi(t1L, t3L / loop)
14444 // t4H = phi(t1H, t3H / loop)
14445 // t2L = OP MI.val.lo, t4L
14446 // t2H = OP MI.val.hi, t4H
14451 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14459 MachineBasicBlock *
14460 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
14461 MachineBasicBlock *MBB) const {
14462 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14463 DebugLoc DL = MI->getDebugLoc();
14465 MachineFunction *MF = MBB->getParent();
14466 MachineRegisterInfo &MRI = MF->getRegInfo();
14468 const BasicBlock *BB = MBB->getBasicBlock();
14469 MachineFunction::iterator I = MBB;
14472 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
14473 "Unexpected number of operands");
14475 assert(MI->hasOneMemOperand() &&
14476 "Expected atomic-load-op32 to have one memoperand");
14478 // Memory Reference
14479 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14480 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14482 unsigned DstLoReg, DstHiReg;
14483 unsigned SrcLoReg, SrcHiReg;
14484 unsigned MemOpndSlot;
14486 unsigned CurOp = 0;
14488 DstLoReg = MI->getOperand(CurOp++).getReg();
14489 DstHiReg = MI->getOperand(CurOp++).getReg();
14490 MemOpndSlot = CurOp;
14491 CurOp += X86::AddrNumOperands;
14492 SrcLoReg = MI->getOperand(CurOp++).getReg();
14493 SrcHiReg = MI->getOperand(CurOp++).getReg();
14495 const TargetRegisterClass *RC = &X86::GR32RegClass;
14496 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
14498 unsigned t1L = MRI.createVirtualRegister(RC);
14499 unsigned t1H = MRI.createVirtualRegister(RC);
14500 unsigned t2L = MRI.createVirtualRegister(RC);
14501 unsigned t2H = MRI.createVirtualRegister(RC);
14502 unsigned t3L = MRI.createVirtualRegister(RC);
14503 unsigned t3H = MRI.createVirtualRegister(RC);
14504 unsigned t4L = MRI.createVirtualRegister(RC);
14505 unsigned t4H = MRI.createVirtualRegister(RC);
14507 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
14508 unsigned LOADOpc = X86::MOV32rm;
14510 // For the atomic load-arith operator, we generate
14513 // t1L = LOAD [MI.addr + 0]
14514 // t1H = LOAD [MI.addr + 4]
14516 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
14517 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
14518 // t2L = OP MI.val.lo, t4L
14519 // t2H = OP MI.val.hi, t4H
14522 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
14530 MachineBasicBlock *thisMBB = MBB;
14531 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14532 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14533 MF->insert(I, mainMBB);
14534 MF->insert(I, sinkMBB);
14536 MachineInstrBuilder MIB;
14538 // Transfer the remainder of BB and its successor edges to sinkMBB.
14539 sinkMBB->splice(sinkMBB->begin(), MBB,
14540 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14541 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14545 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
14546 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14547 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14549 NewMO.setIsKill(false);
14550 MIB.addOperand(NewMO);
14552 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
14553 unsigned flags = (*MMOI)->getFlags();
14554 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
14555 MachineMemOperand *MMO =
14556 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
14557 (*MMOI)->getSize(),
14558 (*MMOI)->getBaseAlignment(),
14559 (*MMOI)->getTBAAInfo(),
14560 (*MMOI)->getRanges());
14561 MIB.addMemOperand(MMO);
14563 MachineInstr *LowMI = MIB;
14566 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
14567 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14568 if (i == X86::AddrDisp) {
14569 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
14571 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14573 NewMO.setIsKill(false);
14574 MIB.addOperand(NewMO);
14577 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
14579 thisMBB->addSuccessor(mainMBB);
14582 MachineBasicBlock *origMainMBB = mainMBB;
14585 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
14586 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14587 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
14588 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14590 unsigned Opc = MI->getOpcode();
14593 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
14594 case X86::ATOMAND6432:
14595 case X86::ATOMOR6432:
14596 case X86::ATOMXOR6432:
14597 case X86::ATOMADD6432:
14598 case X86::ATOMSUB6432: {
14600 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14601 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
14603 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
14607 case X86::ATOMNAND6432: {
14608 unsigned HiOpc, NOTOpc;
14609 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
14610 unsigned TmpL = MRI.createVirtualRegister(RC);
14611 unsigned TmpH = MRI.createVirtualRegister(RC);
14612 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
14614 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
14616 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
14617 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
14620 case X86::ATOMMAX6432:
14621 case X86::ATOMMIN6432:
14622 case X86::ATOMUMAX6432:
14623 case X86::ATOMUMIN6432: {
14625 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14626 unsigned cL = MRI.createVirtualRegister(RC8);
14627 unsigned cH = MRI.createVirtualRegister(RC8);
14628 unsigned cL32 = MRI.createVirtualRegister(RC);
14629 unsigned cH32 = MRI.createVirtualRegister(RC);
14630 unsigned cc = MRI.createVirtualRegister(RC);
14631 // cl := cmp src_lo, lo
14632 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14633 .addReg(SrcLoReg).addReg(t4L);
14634 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
14635 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
14636 // ch := cmp src_hi, hi
14637 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
14638 .addReg(SrcHiReg).addReg(t4H);
14639 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
14640 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
14641 // cc := if (src_hi == hi) ? cl : ch;
14642 if (Subtarget->hasCMov()) {
14643 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
14644 .addReg(cH32).addReg(cL32);
14646 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
14647 .addReg(cH32).addReg(cL32)
14648 .addImm(X86::COND_E);
14649 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14651 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
14652 if (Subtarget->hasCMov()) {
14653 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
14654 .addReg(SrcLoReg).addReg(t4L);
14655 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
14656 .addReg(SrcHiReg).addReg(t4H);
14658 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
14659 .addReg(SrcLoReg).addReg(t4L)
14660 .addImm(X86::COND_NE);
14661 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14662 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
14663 // 2nd CMOV lowering.
14664 mainMBB->addLiveIn(X86::EFLAGS);
14665 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
14666 .addReg(SrcHiReg).addReg(t4H)
14667 .addImm(X86::COND_NE);
14668 mainMBB = EmitLoweredSelect(MIB, mainMBB);
14669 // Replace the original PHI node as mainMBB is changed after CMOV
14671 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
14672 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
14673 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
14674 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
14675 PhiL->eraseFromParent();
14676 PhiH->eraseFromParent();
14680 case X86::ATOMSWAP6432: {
14682 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14683 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14684 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14689 // Copy EDX:EAX back from HiReg:LoReg
14690 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14691 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14692 // Copy ECX:EBX from t1H:t1L
14693 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14694 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14696 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14697 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14698 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14700 NewMO.setIsKill(false);
14701 MIB.addOperand(NewMO);
14703 MIB.setMemRefs(MMOBegin, MMOEnd);
14705 // Copy EDX:EAX back to t3H:t3L
14706 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14707 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14709 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14711 mainMBB->addSuccessor(origMainMBB);
14712 mainMBB->addSuccessor(sinkMBB);
14715 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14716 TII->get(TargetOpcode::COPY), DstLoReg)
14718 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14719 TII->get(TargetOpcode::COPY), DstHiReg)
14722 MI->eraseFromParent();
14726 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14727 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14728 // in the .td file.
14729 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14730 const TargetInstrInfo *TII) {
14732 switch (MI->getOpcode()) {
14733 default: llvm_unreachable("illegal opcode!");
14734 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14735 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14736 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14737 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14738 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14739 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14740 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14741 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14744 DebugLoc dl = MI->getDebugLoc();
14745 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14747 unsigned NumArgs = MI->getNumOperands();
14748 for (unsigned i = 1; i < NumArgs; ++i) {
14749 MachineOperand &Op = MI->getOperand(i);
14750 if (!(Op.isReg() && Op.isImplicit()))
14751 MIB.addOperand(Op);
14753 if (MI->hasOneMemOperand())
14754 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14756 BuildMI(*BB, MI, dl,
14757 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14758 .addReg(X86::XMM0);
14760 MI->eraseFromParent();
14764 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14765 // defs in an instruction pattern
14766 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14767 const TargetInstrInfo *TII) {
14769 switch (MI->getOpcode()) {
14770 default: llvm_unreachable("illegal opcode!");
14771 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14772 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14773 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14774 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14775 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14776 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14777 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14778 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14781 DebugLoc dl = MI->getDebugLoc();
14782 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14784 unsigned NumArgs = MI->getNumOperands(); // remove the results
14785 for (unsigned i = 1; i < NumArgs; ++i) {
14786 MachineOperand &Op = MI->getOperand(i);
14787 if (!(Op.isReg() && Op.isImplicit()))
14788 MIB.addOperand(Op);
14790 if (MI->hasOneMemOperand())
14791 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14793 BuildMI(*BB, MI, dl,
14794 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14797 MI->eraseFromParent();
14801 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14802 const TargetInstrInfo *TII,
14803 const X86Subtarget* Subtarget) {
14804 DebugLoc dl = MI->getDebugLoc();
14806 // Address into RAX/EAX, other two args into ECX, EDX.
14807 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14808 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14809 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14810 for (int i = 0; i < X86::AddrNumOperands; ++i)
14811 MIB.addOperand(MI->getOperand(i));
14813 unsigned ValOps = X86::AddrNumOperands;
14814 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14815 .addReg(MI->getOperand(ValOps).getReg());
14816 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14817 .addReg(MI->getOperand(ValOps+1).getReg());
14819 // The instruction doesn't actually take any operands though.
14820 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14822 MI->eraseFromParent(); // The pseudo is gone now.
14826 MachineBasicBlock *
14827 X86TargetLowering::EmitVAARG64WithCustomInserter(
14829 MachineBasicBlock *MBB) const {
14830 // Emit va_arg instruction on X86-64.
14832 // Operands to this pseudo-instruction:
14833 // 0 ) Output : destination address (reg)
14834 // 1-5) Input : va_list address (addr, i64mem)
14835 // 6 ) ArgSize : Size (in bytes) of vararg type
14836 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14837 // 8 ) Align : Alignment of type
14838 // 9 ) EFLAGS (implicit-def)
14840 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14841 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14843 unsigned DestReg = MI->getOperand(0).getReg();
14844 MachineOperand &Base = MI->getOperand(1);
14845 MachineOperand &Scale = MI->getOperand(2);
14846 MachineOperand &Index = MI->getOperand(3);
14847 MachineOperand &Disp = MI->getOperand(4);
14848 MachineOperand &Segment = MI->getOperand(5);
14849 unsigned ArgSize = MI->getOperand(6).getImm();
14850 unsigned ArgMode = MI->getOperand(7).getImm();
14851 unsigned Align = MI->getOperand(8).getImm();
14853 // Memory Reference
14854 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14855 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14856 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14858 // Machine Information
14859 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14860 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14861 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14862 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14863 DebugLoc DL = MI->getDebugLoc();
14865 // struct va_list {
14868 // i64 overflow_area (address)
14869 // i64 reg_save_area (address)
14871 // sizeof(va_list) = 24
14872 // alignment(va_list) = 8
14874 unsigned TotalNumIntRegs = 6;
14875 unsigned TotalNumXMMRegs = 8;
14876 bool UseGPOffset = (ArgMode == 1);
14877 bool UseFPOffset = (ArgMode == 2);
14878 unsigned MaxOffset = TotalNumIntRegs * 8 +
14879 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14881 /* Align ArgSize to a multiple of 8 */
14882 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14883 bool NeedsAlign = (Align > 8);
14885 MachineBasicBlock *thisMBB = MBB;
14886 MachineBasicBlock *overflowMBB;
14887 MachineBasicBlock *offsetMBB;
14888 MachineBasicBlock *endMBB;
14890 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14891 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14892 unsigned OffsetReg = 0;
14894 if (!UseGPOffset && !UseFPOffset) {
14895 // If we only pull from the overflow region, we don't create a branch.
14896 // We don't need to alter control flow.
14897 OffsetDestReg = 0; // unused
14898 OverflowDestReg = DestReg;
14901 overflowMBB = thisMBB;
14904 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14905 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14906 // If not, pull from overflow_area. (branch to overflowMBB)
14911 // offsetMBB overflowMBB
14916 // Registers for the PHI in endMBB
14917 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14918 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14920 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14921 MachineFunction *MF = MBB->getParent();
14922 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14923 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14924 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14926 MachineFunction::iterator MBBIter = MBB;
14929 // Insert the new basic blocks
14930 MF->insert(MBBIter, offsetMBB);
14931 MF->insert(MBBIter, overflowMBB);
14932 MF->insert(MBBIter, endMBB);
14934 // Transfer the remainder of MBB and its successor edges to endMBB.
14935 endMBB->splice(endMBB->begin(), thisMBB,
14936 llvm::next(MachineBasicBlock::iterator(MI)),
14938 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14940 // Make offsetMBB and overflowMBB successors of thisMBB
14941 thisMBB->addSuccessor(offsetMBB);
14942 thisMBB->addSuccessor(overflowMBB);
14944 // endMBB is a successor of both offsetMBB and overflowMBB
14945 offsetMBB->addSuccessor(endMBB);
14946 overflowMBB->addSuccessor(endMBB);
14948 // Load the offset value into a register
14949 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14950 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14954 .addDisp(Disp, UseFPOffset ? 4 : 0)
14955 .addOperand(Segment)
14956 .setMemRefs(MMOBegin, MMOEnd);
14958 // Check if there is enough room left to pull this argument.
14959 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14961 .addImm(MaxOffset + 8 - ArgSizeA8);
14963 // Branch to "overflowMBB" if offset >= max
14964 // Fall through to "offsetMBB" otherwise
14965 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14966 .addMBB(overflowMBB);
14969 // In offsetMBB, emit code to use the reg_save_area.
14971 assert(OffsetReg != 0);
14973 // Read the reg_save_area address.
14974 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14975 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14980 .addOperand(Segment)
14981 .setMemRefs(MMOBegin, MMOEnd);
14983 // Zero-extend the offset
14984 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14985 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
14988 .addImm(X86::sub_32bit);
14990 // Add the offset to the reg_save_area to get the final address.
14991 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
14992 .addReg(OffsetReg64)
14993 .addReg(RegSaveReg);
14995 // Compute the offset for the next argument
14996 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14997 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
14999 .addImm(UseFPOffset ? 16 : 8);
15001 // Store it back into the va_list.
15002 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
15006 .addDisp(Disp, UseFPOffset ? 4 : 0)
15007 .addOperand(Segment)
15008 .addReg(NextOffsetReg)
15009 .setMemRefs(MMOBegin, MMOEnd);
15012 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
15017 // Emit code to use overflow area
15020 // Load the overflow_area address into a register.
15021 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
15022 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
15027 .addOperand(Segment)
15028 .setMemRefs(MMOBegin, MMOEnd);
15030 // If we need to align it, do so. Otherwise, just copy the address
15031 // to OverflowDestReg.
15033 // Align the overflow address
15034 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
15035 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
15037 // aligned_addr = (addr + (align-1)) & ~(align-1)
15038 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
15039 .addReg(OverflowAddrReg)
15042 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
15044 .addImm(~(uint64_t)(Align-1));
15046 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
15047 .addReg(OverflowAddrReg);
15050 // Compute the next overflow address after this argument.
15051 // (the overflow address should be kept 8-byte aligned)
15052 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
15053 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
15054 .addReg(OverflowDestReg)
15055 .addImm(ArgSizeA8);
15057 // Store the new overflow address.
15058 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
15063 .addOperand(Segment)
15064 .addReg(NextAddrReg)
15065 .setMemRefs(MMOBegin, MMOEnd);
15067 // If we branched, emit the PHI to the front of endMBB.
15069 BuildMI(*endMBB, endMBB->begin(), DL,
15070 TII->get(X86::PHI), DestReg)
15071 .addReg(OffsetDestReg).addMBB(offsetMBB)
15072 .addReg(OverflowDestReg).addMBB(overflowMBB);
15075 // Erase the pseudo instruction
15076 MI->eraseFromParent();
15081 MachineBasicBlock *
15082 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
15084 MachineBasicBlock *MBB) const {
15085 // Emit code to save XMM registers to the stack. The ABI says that the
15086 // number of registers to save is given in %al, so it's theoretically
15087 // possible to do an indirect jump trick to avoid saving all of them,
15088 // however this code takes a simpler approach and just executes all
15089 // of the stores if %al is non-zero. It's less code, and it's probably
15090 // easier on the hardware branch predictor, and stores aren't all that
15091 // expensive anyway.
15093 // Create the new basic blocks. One block contains all the XMM stores,
15094 // and one block is the final destination regardless of whether any
15095 // stores were performed.
15096 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
15097 MachineFunction *F = MBB->getParent();
15098 MachineFunction::iterator MBBIter = MBB;
15100 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
15101 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
15102 F->insert(MBBIter, XMMSaveMBB);
15103 F->insert(MBBIter, EndMBB);
15105 // Transfer the remainder of MBB and its successor edges to EndMBB.
15106 EndMBB->splice(EndMBB->begin(), MBB,
15107 llvm::next(MachineBasicBlock::iterator(MI)),
15109 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
15111 // The original block will now fall through to the XMM save block.
15112 MBB->addSuccessor(XMMSaveMBB);
15113 // The XMMSaveMBB will fall through to the end block.
15114 XMMSaveMBB->addSuccessor(EndMBB);
15116 // Now add the instructions.
15117 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15118 DebugLoc DL = MI->getDebugLoc();
15120 unsigned CountReg = MI->getOperand(0).getReg();
15121 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
15122 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
15124 if (!Subtarget->isTargetWin64()) {
15125 // If %al is 0, branch around the XMM save block.
15126 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
15127 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
15128 MBB->addSuccessor(EndMBB);
15131 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
15132 // In the XMM save block, save all the XMM argument registers.
15133 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
15134 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
15135 MachineMemOperand *MMO =
15136 F->getMachineMemOperand(
15137 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
15138 MachineMemOperand::MOStore,
15139 /*Size=*/16, /*Align=*/16);
15140 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
15141 .addFrameIndex(RegSaveFrameIndex)
15142 .addImm(/*Scale=*/1)
15143 .addReg(/*IndexReg=*/0)
15144 .addImm(/*Disp=*/Offset)
15145 .addReg(/*Segment=*/0)
15146 .addReg(MI->getOperand(i).getReg())
15147 .addMemOperand(MMO);
15150 MI->eraseFromParent(); // The pseudo instruction is gone now.
15155 // The EFLAGS operand of SelectItr might be missing a kill marker
15156 // because there were multiple uses of EFLAGS, and ISel didn't know
15157 // which to mark. Figure out whether SelectItr should have had a
15158 // kill marker, and set it if it should. Returns the correct kill
15160 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
15161 MachineBasicBlock* BB,
15162 const TargetRegisterInfo* TRI) {
15163 // Scan forward through BB for a use/def of EFLAGS.
15164 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
15165 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
15166 const MachineInstr& mi = *miI;
15167 if (mi.readsRegister(X86::EFLAGS))
15169 if (mi.definesRegister(X86::EFLAGS))
15170 break; // Should have kill-flag - update below.
15173 // If we hit the end of the block, check whether EFLAGS is live into a
15175 if (miI == BB->end()) {
15176 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
15177 sEnd = BB->succ_end();
15178 sItr != sEnd; ++sItr) {
15179 MachineBasicBlock* succ = *sItr;
15180 if (succ->isLiveIn(X86::EFLAGS))
15185 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
15186 // out. SelectMI should have a kill flag on EFLAGS.
15187 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
15191 MachineBasicBlock *
15192 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
15193 MachineBasicBlock *BB) const {
15194 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15195 DebugLoc DL = MI->getDebugLoc();
15197 // To "insert" a SELECT_CC instruction, we actually have to insert the
15198 // diamond control-flow pattern. The incoming instruction knows the
15199 // destination vreg to set, the condition code register to branch on, the
15200 // true/false values to select between, and a branch opcode to use.
15201 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15202 MachineFunction::iterator It = BB;
15208 // cmpTY ccX, r1, r2
15210 // fallthrough --> copy0MBB
15211 MachineBasicBlock *thisMBB = BB;
15212 MachineFunction *F = BB->getParent();
15213 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
15214 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
15215 F->insert(It, copy0MBB);
15216 F->insert(It, sinkMBB);
15218 // If the EFLAGS register isn't dead in the terminator, then claim that it's
15219 // live into the sink and copy blocks.
15220 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
15221 if (!MI->killsRegister(X86::EFLAGS) &&
15222 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
15223 copy0MBB->addLiveIn(X86::EFLAGS);
15224 sinkMBB->addLiveIn(X86::EFLAGS);
15227 // Transfer the remainder of BB and its successor edges to sinkMBB.
15228 sinkMBB->splice(sinkMBB->begin(), BB,
15229 llvm::next(MachineBasicBlock::iterator(MI)),
15231 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
15233 // Add the true and fallthrough blocks as its successors.
15234 BB->addSuccessor(copy0MBB);
15235 BB->addSuccessor(sinkMBB);
15237 // Create the conditional branch instruction.
15239 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
15240 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
15243 // %FalseValue = ...
15244 // # fallthrough to sinkMBB
15245 copy0MBB->addSuccessor(sinkMBB);
15248 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
15250 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15251 TII->get(X86::PHI), MI->getOperand(0).getReg())
15252 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
15253 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
15255 MI->eraseFromParent(); // The pseudo instruction is gone now.
15259 MachineBasicBlock *
15260 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
15261 bool Is64Bit) const {
15262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15263 DebugLoc DL = MI->getDebugLoc();
15264 MachineFunction *MF = BB->getParent();
15265 const BasicBlock *LLVM_BB = BB->getBasicBlock();
15267 assert(getTargetMachine().Options.EnableSegmentedStacks);
15269 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
15270 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
15273 // ... [Till the alloca]
15274 // If stacklet is not large enough, jump to mallocMBB
15277 // Allocate by subtracting from RSP
15278 // Jump to continueMBB
15281 // Allocate by call to runtime
15285 // [rest of original BB]
15288 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15289 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15290 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
15292 MachineRegisterInfo &MRI = MF->getRegInfo();
15293 const TargetRegisterClass *AddrRegClass =
15294 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
15296 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15297 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
15298 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
15299 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
15300 sizeVReg = MI->getOperand(1).getReg(),
15301 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
15303 MachineFunction::iterator MBBIter = BB;
15306 MF->insert(MBBIter, bumpMBB);
15307 MF->insert(MBBIter, mallocMBB);
15308 MF->insert(MBBIter, continueMBB);
15310 continueMBB->splice(continueMBB->begin(), BB, llvm::next
15311 (MachineBasicBlock::iterator(MI)), BB->end());
15312 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
15314 // Add code to the main basic block to check if the stack limit has been hit,
15315 // and if so, jump to mallocMBB otherwise to bumpMBB.
15316 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
15317 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
15318 .addReg(tmpSPVReg).addReg(sizeVReg);
15319 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
15320 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
15321 .addReg(SPLimitVReg);
15322 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
15324 // bumpMBB simply decreases the stack pointer, since we know the current
15325 // stacklet has enough space.
15326 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
15327 .addReg(SPLimitVReg);
15328 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
15329 .addReg(SPLimitVReg);
15330 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15332 // Calls into a routine in libgcc to allocate more space from the heap.
15333 const uint32_t *RegMask =
15334 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15336 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
15338 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
15339 .addExternalSymbol("__morestack_allocate_stack_space")
15340 .addRegMask(RegMask)
15341 .addReg(X86::RDI, RegState::Implicit)
15342 .addReg(X86::RAX, RegState::ImplicitDefine);
15344 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
15346 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
15347 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
15348 .addExternalSymbol("__morestack_allocate_stack_space")
15349 .addRegMask(RegMask)
15350 .addReg(X86::EAX, RegState::ImplicitDefine);
15354 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
15357 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
15358 .addReg(Is64Bit ? X86::RAX : X86::EAX);
15359 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
15361 // Set up the CFG correctly.
15362 BB->addSuccessor(bumpMBB);
15363 BB->addSuccessor(mallocMBB);
15364 mallocMBB->addSuccessor(continueMBB);
15365 bumpMBB->addSuccessor(continueMBB);
15367 // Take care of the PHI nodes.
15368 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
15369 MI->getOperand(0).getReg())
15370 .addReg(mallocPtrVReg).addMBB(mallocMBB)
15371 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
15373 // Delete the original pseudo instruction.
15374 MI->eraseFromParent();
15377 return continueMBB;
15380 MachineBasicBlock *
15381 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
15382 MachineBasicBlock *BB) const {
15383 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15384 DebugLoc DL = MI->getDebugLoc();
15386 assert(!Subtarget->isTargetEnvMacho());
15388 // The lowering is pretty easy: we're just emitting the call to _alloca. The
15389 // non-trivial part is impdef of ESP.
15391 if (Subtarget->isTargetWin64()) {
15392 if (Subtarget->isTargetCygMing()) {
15393 // ___chkstk(Mingw64):
15394 // Clobbers R10, R11, RAX and EFLAGS.
15396 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15397 .addExternalSymbol("___chkstk")
15398 .addReg(X86::RAX, RegState::Implicit)
15399 .addReg(X86::RSP, RegState::Implicit)
15400 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
15401 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
15402 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15404 // __chkstk(MSVCRT): does not update stack pointer.
15405 // Clobbers R10, R11 and EFLAGS.
15406 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
15407 .addExternalSymbol("__chkstk")
15408 .addReg(X86::RAX, RegState::Implicit)
15409 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15410 // RAX has the offset to be subtracted from RSP.
15411 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
15416 const char *StackProbeSymbol =
15417 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
15419 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
15420 .addExternalSymbol(StackProbeSymbol)
15421 .addReg(X86::EAX, RegState::Implicit)
15422 .addReg(X86::ESP, RegState::Implicit)
15423 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
15424 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
15425 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
15428 MI->eraseFromParent(); // The pseudo instruction is gone now.
15432 MachineBasicBlock *
15433 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
15434 MachineBasicBlock *BB) const {
15435 // This is pretty easy. We're taking the value that we received from
15436 // our load from the relocation, sticking it in either RDI (x86-64)
15437 // or EAX and doing an indirect call. The return value will then
15438 // be in the normal return register.
15439 const X86InstrInfo *TII
15440 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
15441 DebugLoc DL = MI->getDebugLoc();
15442 MachineFunction *F = BB->getParent();
15444 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
15445 assert(MI->getOperand(3).isGlobal() && "This should be a global");
15447 // Get a register mask for the lowered call.
15448 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
15449 // proper register mask.
15450 const uint32_t *RegMask =
15451 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
15452 if (Subtarget->is64Bit()) {
15453 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15454 TII->get(X86::MOV64rm), X86::RDI)
15456 .addImm(0).addReg(0)
15457 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15458 MI->getOperand(3).getTargetFlags())
15460 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
15461 addDirectMem(MIB, X86::RDI);
15462 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
15463 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
15464 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15465 TII->get(X86::MOV32rm), X86::EAX)
15467 .addImm(0).addReg(0)
15468 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15469 MI->getOperand(3).getTargetFlags())
15471 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15472 addDirectMem(MIB, X86::EAX);
15473 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15475 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
15476 TII->get(X86::MOV32rm), X86::EAX)
15477 .addReg(TII->getGlobalBaseReg(F))
15478 .addImm(0).addReg(0)
15479 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
15480 MI->getOperand(3).getTargetFlags())
15482 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
15483 addDirectMem(MIB, X86::EAX);
15484 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
15487 MI->eraseFromParent(); // The pseudo instruction is gone now.
15491 MachineBasicBlock *
15492 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
15493 MachineBasicBlock *MBB) const {
15494 DebugLoc DL = MI->getDebugLoc();
15495 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15497 MachineFunction *MF = MBB->getParent();
15498 MachineRegisterInfo &MRI = MF->getRegInfo();
15500 const BasicBlock *BB = MBB->getBasicBlock();
15501 MachineFunction::iterator I = MBB;
15504 // Memory Reference
15505 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15506 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15509 unsigned MemOpndSlot = 0;
15511 unsigned CurOp = 0;
15513 DstReg = MI->getOperand(CurOp++).getReg();
15514 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
15515 assert(RC->hasType(MVT::i32) && "Invalid destination!");
15516 unsigned mainDstReg = MRI.createVirtualRegister(RC);
15517 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
15519 MemOpndSlot = CurOp;
15521 MVT PVT = getPointerTy();
15522 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15523 "Invalid Pointer Size!");
15525 // For v = setjmp(buf), we generate
15528 // buf[LabelOffset] = restoreMBB
15529 // SjLjSetup restoreMBB
15535 // v = phi(main, restore)
15540 MachineBasicBlock *thisMBB = MBB;
15541 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
15542 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
15543 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
15544 MF->insert(I, mainMBB);
15545 MF->insert(I, sinkMBB);
15546 MF->push_back(restoreMBB);
15548 MachineInstrBuilder MIB;
15550 // Transfer the remainder of BB and its successor edges to sinkMBB.
15551 sinkMBB->splice(sinkMBB->begin(), MBB,
15552 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
15553 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
15556 unsigned PtrStoreOpc = 0;
15557 unsigned LabelReg = 0;
15558 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15559 Reloc::Model RM = getTargetMachine().getRelocationModel();
15560 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
15561 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
15563 // Prepare IP either in reg or imm.
15564 if (!UseImmLabel) {
15565 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
15566 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
15567 LabelReg = MRI.createVirtualRegister(PtrRC);
15568 if (Subtarget->is64Bit()) {
15569 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
15573 .addMBB(restoreMBB)
15576 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
15577 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
15578 .addReg(XII->getGlobalBaseReg(MF))
15581 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
15585 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
15587 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
15588 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15589 if (i == X86::AddrDisp)
15590 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
15592 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
15595 MIB.addReg(LabelReg);
15597 MIB.addMBB(restoreMBB);
15598 MIB.setMemRefs(MMOBegin, MMOEnd);
15600 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
15601 .addMBB(restoreMBB);
15603 const X86RegisterInfo *RegInfo =
15604 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15605 MIB.addRegMask(RegInfo->getNoPreservedMask());
15606 thisMBB->addSuccessor(mainMBB);
15607 thisMBB->addSuccessor(restoreMBB);
15611 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
15612 mainMBB->addSuccessor(sinkMBB);
15615 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
15616 TII->get(X86::PHI), DstReg)
15617 .addReg(mainDstReg).addMBB(mainMBB)
15618 .addReg(restoreDstReg).addMBB(restoreMBB);
15621 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
15622 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
15623 restoreMBB->addSuccessor(sinkMBB);
15625 MI->eraseFromParent();
15629 MachineBasicBlock *
15630 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
15631 MachineBasicBlock *MBB) const {
15632 DebugLoc DL = MI->getDebugLoc();
15633 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15635 MachineFunction *MF = MBB->getParent();
15636 MachineRegisterInfo &MRI = MF->getRegInfo();
15638 // Memory Reference
15639 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
15640 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
15642 MVT PVT = getPointerTy();
15643 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
15644 "Invalid Pointer Size!");
15646 const TargetRegisterClass *RC =
15647 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
15648 unsigned Tmp = MRI.createVirtualRegister(RC);
15649 // Since FP is only updated here but NOT referenced, it's treated as GPR.
15650 const X86RegisterInfo *RegInfo =
15651 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
15652 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
15653 unsigned SP = RegInfo->getStackRegister();
15655 MachineInstrBuilder MIB;
15657 const int64_t LabelOffset = 1 * PVT.getStoreSize();
15658 const int64_t SPOffset = 2 * PVT.getStoreSize();
15660 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
15661 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
15664 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
15665 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
15666 MIB.addOperand(MI->getOperand(i));
15667 MIB.setMemRefs(MMOBegin, MMOEnd);
15669 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
15670 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15671 if (i == X86::AddrDisp)
15672 MIB.addDisp(MI->getOperand(i), LabelOffset);
15674 MIB.addOperand(MI->getOperand(i));
15676 MIB.setMemRefs(MMOBegin, MMOEnd);
15678 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15679 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15680 if (i == X86::AddrDisp)
15681 MIB.addDisp(MI->getOperand(i), SPOffset);
15683 MIB.addOperand(MI->getOperand(i));
15685 MIB.setMemRefs(MMOBegin, MMOEnd);
15687 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15689 MI->eraseFromParent();
15693 MachineBasicBlock *
15694 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15695 MachineBasicBlock *BB) const {
15696 switch (MI->getOpcode()) {
15697 default: llvm_unreachable("Unexpected instr type to insert");
15698 case X86::TAILJMPd64:
15699 case X86::TAILJMPr64:
15700 case X86::TAILJMPm64:
15701 llvm_unreachable("TAILJMP64 would not be touched here.");
15702 case X86::TCRETURNdi64:
15703 case X86::TCRETURNri64:
15704 case X86::TCRETURNmi64:
15706 case X86::WIN_ALLOCA:
15707 return EmitLoweredWinAlloca(MI, BB);
15708 case X86::SEG_ALLOCA_32:
15709 return EmitLoweredSegAlloca(MI, BB, false);
15710 case X86::SEG_ALLOCA_64:
15711 return EmitLoweredSegAlloca(MI, BB, true);
15712 case X86::TLSCall_32:
15713 case X86::TLSCall_64:
15714 return EmitLoweredTLSCall(MI, BB);
15715 case X86::CMOV_GR8:
15716 case X86::CMOV_FR32:
15717 case X86::CMOV_FR64:
15718 case X86::CMOV_V4F32:
15719 case X86::CMOV_V2F64:
15720 case X86::CMOV_V2I64:
15721 case X86::CMOV_V8F32:
15722 case X86::CMOV_V4F64:
15723 case X86::CMOV_V4I64:
15724 case X86::CMOV_GR16:
15725 case X86::CMOV_GR32:
15726 case X86::CMOV_RFP32:
15727 case X86::CMOV_RFP64:
15728 case X86::CMOV_RFP80:
15729 return EmitLoweredSelect(MI, BB);
15731 case X86::FP32_TO_INT16_IN_MEM:
15732 case X86::FP32_TO_INT32_IN_MEM:
15733 case X86::FP32_TO_INT64_IN_MEM:
15734 case X86::FP64_TO_INT16_IN_MEM:
15735 case X86::FP64_TO_INT32_IN_MEM:
15736 case X86::FP64_TO_INT64_IN_MEM:
15737 case X86::FP80_TO_INT16_IN_MEM:
15738 case X86::FP80_TO_INT32_IN_MEM:
15739 case X86::FP80_TO_INT64_IN_MEM: {
15740 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15741 DebugLoc DL = MI->getDebugLoc();
15743 // Change the floating point control register to use "round towards zero"
15744 // mode when truncating to an integer value.
15745 MachineFunction *F = BB->getParent();
15746 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15747 addFrameReference(BuildMI(*BB, MI, DL,
15748 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15750 // Load the old value of the high byte of the control word...
15752 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15753 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15756 // Set the high part to be round to zero...
15757 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15760 // Reload the modified control word now...
15761 addFrameReference(BuildMI(*BB, MI, DL,
15762 TII->get(X86::FLDCW16m)), CWFrameIdx);
15764 // Restore the memory image of control word to original value
15765 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15768 // Get the X86 opcode to use.
15770 switch (MI->getOpcode()) {
15771 default: llvm_unreachable("illegal opcode!");
15772 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15773 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15774 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15775 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15776 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15777 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15778 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15779 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15780 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15784 MachineOperand &Op = MI->getOperand(0);
15786 AM.BaseType = X86AddressMode::RegBase;
15787 AM.Base.Reg = Op.getReg();
15789 AM.BaseType = X86AddressMode::FrameIndexBase;
15790 AM.Base.FrameIndex = Op.getIndex();
15792 Op = MI->getOperand(1);
15794 AM.Scale = Op.getImm();
15795 Op = MI->getOperand(2);
15797 AM.IndexReg = Op.getImm();
15798 Op = MI->getOperand(3);
15799 if (Op.isGlobal()) {
15800 AM.GV = Op.getGlobal();
15802 AM.Disp = Op.getImm();
15804 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15805 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15807 // Reload the original control word now.
15808 addFrameReference(BuildMI(*BB, MI, DL,
15809 TII->get(X86::FLDCW16m)), CWFrameIdx);
15811 MI->eraseFromParent(); // The pseudo instruction is gone now.
15814 // String/text processing lowering.
15815 case X86::PCMPISTRM128REG:
15816 case X86::VPCMPISTRM128REG:
15817 case X86::PCMPISTRM128MEM:
15818 case X86::VPCMPISTRM128MEM:
15819 case X86::PCMPESTRM128REG:
15820 case X86::VPCMPESTRM128REG:
15821 case X86::PCMPESTRM128MEM:
15822 case X86::VPCMPESTRM128MEM:
15823 assert(Subtarget->hasSSE42() &&
15824 "Target must have SSE4.2 or AVX features enabled");
15825 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15827 // String/text processing lowering.
15828 case X86::PCMPISTRIREG:
15829 case X86::VPCMPISTRIREG:
15830 case X86::PCMPISTRIMEM:
15831 case X86::VPCMPISTRIMEM:
15832 case X86::PCMPESTRIREG:
15833 case X86::VPCMPESTRIREG:
15834 case X86::PCMPESTRIMEM:
15835 case X86::VPCMPESTRIMEM:
15836 assert(Subtarget->hasSSE42() &&
15837 "Target must have SSE4.2 or AVX features enabled");
15838 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15840 // Thread synchronization.
15842 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15846 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15848 // Atomic Lowering.
15849 case X86::ATOMAND8:
15850 case X86::ATOMAND16:
15851 case X86::ATOMAND32:
15852 case X86::ATOMAND64:
15855 case X86::ATOMOR16:
15856 case X86::ATOMOR32:
15857 case X86::ATOMOR64:
15859 case X86::ATOMXOR16:
15860 case X86::ATOMXOR8:
15861 case X86::ATOMXOR32:
15862 case X86::ATOMXOR64:
15864 case X86::ATOMNAND8:
15865 case X86::ATOMNAND16:
15866 case X86::ATOMNAND32:
15867 case X86::ATOMNAND64:
15869 case X86::ATOMMAX8:
15870 case X86::ATOMMAX16:
15871 case X86::ATOMMAX32:
15872 case X86::ATOMMAX64:
15874 case X86::ATOMMIN8:
15875 case X86::ATOMMIN16:
15876 case X86::ATOMMIN32:
15877 case X86::ATOMMIN64:
15879 case X86::ATOMUMAX8:
15880 case X86::ATOMUMAX16:
15881 case X86::ATOMUMAX32:
15882 case X86::ATOMUMAX64:
15884 case X86::ATOMUMIN8:
15885 case X86::ATOMUMIN16:
15886 case X86::ATOMUMIN32:
15887 case X86::ATOMUMIN64:
15888 return EmitAtomicLoadArith(MI, BB);
15890 // This group does 64-bit operations on a 32-bit host.
15891 case X86::ATOMAND6432:
15892 case X86::ATOMOR6432:
15893 case X86::ATOMXOR6432:
15894 case X86::ATOMNAND6432:
15895 case X86::ATOMADD6432:
15896 case X86::ATOMSUB6432:
15897 case X86::ATOMMAX6432:
15898 case X86::ATOMMIN6432:
15899 case X86::ATOMUMAX6432:
15900 case X86::ATOMUMIN6432:
15901 case X86::ATOMSWAP6432:
15902 return EmitAtomicLoadArith6432(MI, BB);
15904 case X86::VASTART_SAVE_XMM_REGS:
15905 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15907 case X86::VAARG_64:
15908 return EmitVAARG64WithCustomInserter(MI, BB);
15910 case X86::EH_SjLj_SetJmp32:
15911 case X86::EH_SjLj_SetJmp64:
15912 return emitEHSjLjSetJmp(MI, BB);
15914 case X86::EH_SjLj_LongJmp32:
15915 case X86::EH_SjLj_LongJmp64:
15916 return emitEHSjLjLongJmp(MI, BB);
15920 //===----------------------------------------------------------------------===//
15921 // X86 Optimization Hooks
15922 //===----------------------------------------------------------------------===//
15924 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15927 const SelectionDAG &DAG,
15928 unsigned Depth) const {
15929 unsigned BitWidth = KnownZero.getBitWidth();
15930 unsigned Opc = Op.getOpcode();
15931 assert((Opc >= ISD::BUILTIN_OP_END ||
15932 Opc == ISD::INTRINSIC_WO_CHAIN ||
15933 Opc == ISD::INTRINSIC_W_CHAIN ||
15934 Opc == ISD::INTRINSIC_VOID) &&
15935 "Should use MaskedValueIsZero if you don't know whether Op"
15936 " is a target node!");
15938 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15952 // These nodes' second result is a boolean.
15953 if (Op.getResNo() == 0)
15956 case X86ISD::SETCC:
15957 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15959 case ISD::INTRINSIC_WO_CHAIN: {
15960 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15961 unsigned NumLoBits = 0;
15964 case Intrinsic::x86_sse_movmsk_ps:
15965 case Intrinsic::x86_avx_movmsk_ps_256:
15966 case Intrinsic::x86_sse2_movmsk_pd:
15967 case Intrinsic::x86_avx_movmsk_pd_256:
15968 case Intrinsic::x86_mmx_pmovmskb:
15969 case Intrinsic::x86_sse2_pmovmskb_128:
15970 case Intrinsic::x86_avx2_pmovmskb: {
15971 // High bits of movmskp{s|d}, pmovmskb are known zero.
15973 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15974 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15975 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15976 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15977 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15978 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15979 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15980 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15982 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
15991 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
15992 unsigned Depth) const {
15993 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
15994 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
15995 return Op.getValueType().getScalarType().getSizeInBits();
16001 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
16002 /// node is a GlobalAddress + offset.
16003 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
16004 const GlobalValue* &GA,
16005 int64_t &Offset) const {
16006 if (N->getOpcode() == X86ISD::Wrapper) {
16007 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
16008 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
16009 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
16013 return TargetLowering::isGAPlusOffset(N, GA, Offset);
16016 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
16017 /// same as extracting the high 128-bit part of 256-bit vector and then
16018 /// inserting the result into the low part of a new 256-bit vector
16019 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
16020 EVT VT = SVOp->getValueType(0);
16021 unsigned NumElems = VT.getVectorNumElements();
16023 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16024 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
16025 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16026 SVOp->getMaskElt(j) >= 0)
16032 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
16033 /// same as extracting the low 128-bit part of 256-bit vector and then
16034 /// inserting the result into the high part of a new 256-bit vector
16035 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
16036 EVT VT = SVOp->getValueType(0);
16037 unsigned NumElems = VT.getVectorNumElements();
16039 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16040 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
16041 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
16042 SVOp->getMaskElt(j) >= 0)
16048 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
16049 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
16050 TargetLowering::DAGCombinerInfo &DCI,
16051 const X86Subtarget* Subtarget) {
16053 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
16054 SDValue V1 = SVOp->getOperand(0);
16055 SDValue V2 = SVOp->getOperand(1);
16056 EVT VT = SVOp->getValueType(0);
16057 unsigned NumElems = VT.getVectorNumElements();
16059 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
16060 V2.getOpcode() == ISD::CONCAT_VECTORS) {
16064 // V UNDEF BUILD_VECTOR UNDEF
16066 // CONCAT_VECTOR CONCAT_VECTOR
16069 // RESULT: V + zero extended
16071 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
16072 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
16073 V1.getOperand(1).getOpcode() != ISD::UNDEF)
16076 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
16079 // To match the shuffle mask, the first half of the mask should
16080 // be exactly the first vector, and all the rest a splat with the
16081 // first element of the second one.
16082 for (unsigned i = 0; i != NumElems/2; ++i)
16083 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
16084 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
16087 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
16088 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
16089 if (Ld->hasNUsesOfValue(1, 0)) {
16090 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
16091 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
16093 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
16094 array_lengthof(Ops),
16096 Ld->getPointerInfo(),
16097 Ld->getAlignment(),
16098 false/*isVolatile*/, true/*ReadMem*/,
16099 false/*WriteMem*/);
16101 // Make sure the newly-created LOAD is in the same position as Ld in
16102 // terms of dependency. We create a TokenFactor for Ld and ResNode,
16103 // and update uses of Ld's output chain to use the TokenFactor.
16104 if (Ld->hasAnyUseOfValue(1)) {
16105 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16106 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
16107 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
16108 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
16109 SDValue(ResNode.getNode(), 1));
16112 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
16116 // Emit a zeroed vector and insert the desired subvector on its
16118 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16119 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
16120 return DCI.CombineTo(N, InsV);
16123 //===--------------------------------------------------------------------===//
16124 // Combine some shuffles into subvector extracts and inserts:
16127 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
16128 if (isShuffleHigh128VectorInsertLow(SVOp)) {
16129 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
16130 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
16131 return DCI.CombineTo(N, InsV);
16134 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
16135 if (isShuffleLow128VectorInsertHigh(SVOp)) {
16136 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
16137 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
16138 return DCI.CombineTo(N, InsV);
16144 /// PerformShuffleCombine - Performs several different shuffle combines.
16145 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
16146 TargetLowering::DAGCombinerInfo &DCI,
16147 const X86Subtarget *Subtarget) {
16149 EVT VT = N->getValueType(0);
16151 // Don't create instructions with illegal types after legalize types has run.
16152 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16153 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
16156 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
16157 if (Subtarget->hasFp256() && VT.is256BitVector() &&
16158 N->getOpcode() == ISD::VECTOR_SHUFFLE)
16159 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
16161 // Only handle 128 wide vector from here on.
16162 if (!VT.is128BitVector())
16165 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
16166 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
16167 // consecutive, non-overlapping, and in the right order.
16168 SmallVector<SDValue, 16> Elts;
16169 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
16170 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
16172 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
16175 /// PerformTruncateCombine - Converts truncate operation to
16176 /// a sequence of vector shuffle operations.
16177 /// It is possible when we truncate 256-bit vector to 128-bit vector
16178 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
16179 TargetLowering::DAGCombinerInfo &DCI,
16180 const X86Subtarget *Subtarget) {
16184 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
16185 /// specific shuffle of a load can be folded into a single element load.
16186 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
16187 /// shuffles have been customed lowered so we need to handle those here.
16188 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
16189 TargetLowering::DAGCombinerInfo &DCI) {
16190 if (DCI.isBeforeLegalizeOps())
16193 SDValue InVec = N->getOperand(0);
16194 SDValue EltNo = N->getOperand(1);
16196 if (!isa<ConstantSDNode>(EltNo))
16199 EVT VT = InVec.getValueType();
16201 bool HasShuffleIntoBitcast = false;
16202 if (InVec.getOpcode() == ISD::BITCAST) {
16203 // Don't duplicate a load with other uses.
16204 if (!InVec.hasOneUse())
16206 EVT BCVT = InVec.getOperand(0).getValueType();
16207 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
16209 InVec = InVec.getOperand(0);
16210 HasShuffleIntoBitcast = true;
16213 if (!isTargetShuffle(InVec.getOpcode()))
16216 // Don't duplicate a load with other uses.
16217 if (!InVec.hasOneUse())
16220 SmallVector<int, 16> ShuffleMask;
16222 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
16226 // Select the input vector, guarding against out of range extract vector.
16227 unsigned NumElems = VT.getVectorNumElements();
16228 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
16229 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
16230 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
16231 : InVec.getOperand(1);
16233 // If inputs to shuffle are the same for both ops, then allow 2 uses
16234 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
16236 if (LdNode.getOpcode() == ISD::BITCAST) {
16237 // Don't duplicate a load with other uses.
16238 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
16241 AllowedUses = 1; // only allow 1 load use if we have a bitcast
16242 LdNode = LdNode.getOperand(0);
16245 if (!ISD::isNormalLoad(LdNode.getNode()))
16248 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
16250 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
16253 if (HasShuffleIntoBitcast) {
16254 // If there's a bitcast before the shuffle, check if the load type and
16255 // alignment is valid.
16256 unsigned Align = LN0->getAlignment();
16257 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16258 unsigned NewAlign = TLI.getDataLayout()->
16259 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
16261 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
16265 // All checks match so transform back to vector_shuffle so that DAG combiner
16266 // can finish the job
16269 // Create shuffle node taking into account the case that its a unary shuffle
16270 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
16271 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
16272 InVec.getOperand(0), Shuffle,
16274 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
16275 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
16279 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
16280 /// generation and convert it from being a bunch of shuffles and extracts
16281 /// to a simple store and scalar loads to extract the elements.
16282 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
16283 TargetLowering::DAGCombinerInfo &DCI) {
16284 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
16285 if (NewOp.getNode())
16288 SDValue InputVector = N->getOperand(0);
16289 // Detect whether we are trying to convert from mmx to i32 and the bitcast
16290 // from mmx to v2i32 has a single usage.
16291 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
16292 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
16293 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
16294 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
16295 N->getValueType(0),
16296 InputVector.getNode()->getOperand(0));
16298 // Only operate on vectors of 4 elements, where the alternative shuffling
16299 // gets to be more expensive.
16300 if (InputVector.getValueType() != MVT::v4i32)
16303 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
16304 // single use which is a sign-extend or zero-extend, and all elements are
16306 SmallVector<SDNode *, 4> Uses;
16307 unsigned ExtractedElements = 0;
16308 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
16309 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
16310 if (UI.getUse().getResNo() != InputVector.getResNo())
16313 SDNode *Extract = *UI;
16314 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
16317 if (Extract->getValueType(0) != MVT::i32)
16319 if (!Extract->hasOneUse())
16321 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
16322 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
16324 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
16327 // Record which element was extracted.
16328 ExtractedElements |=
16329 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
16331 Uses.push_back(Extract);
16334 // If not all the elements were used, this may not be worthwhile.
16335 if (ExtractedElements != 15)
16338 // Ok, we've now decided to do the transformation.
16339 SDLoc dl(InputVector);
16341 // Store the value to a temporary stack slot.
16342 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
16343 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
16344 MachinePointerInfo(), false, false, 0);
16346 // Replace each use (extract) with a load of the appropriate element.
16347 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
16348 UE = Uses.end(); UI != UE; ++UI) {
16349 SDNode *Extract = *UI;
16351 // cOMpute the element's address.
16352 SDValue Idx = Extract->getOperand(1);
16354 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
16355 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
16356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16357 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
16359 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
16360 StackPtr, OffsetVal);
16362 // Load the scalar.
16363 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
16364 ScalarAddr, MachinePointerInfo(),
16365 false, false, false, 0);
16367 // Replace the exact with the load.
16368 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
16371 // The replacement was made in place; don't return anything.
16375 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
16376 static std::pair<unsigned, bool>
16377 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
16378 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
16379 if (!VT.isVector())
16380 return std::make_pair(0, false);
16382 bool NeedSplit = false;
16383 switch (VT.getSimpleVT().SimpleTy) {
16384 default: return std::make_pair(0, false);
16388 if (!Subtarget->hasAVX2())
16390 if (!Subtarget->hasAVX())
16391 return std::make_pair(0, false);
16396 if (!Subtarget->hasSSE2())
16397 return std::make_pair(0, false);
16400 // SSE2 has only a small subset of the operations.
16401 bool hasUnsigned = Subtarget->hasSSE41() ||
16402 (Subtarget->hasSSE2() && VT == MVT::v16i8);
16403 bool hasSigned = Subtarget->hasSSE41() ||
16404 (Subtarget->hasSSE2() && VT == MVT::v8i16);
16406 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16409 // Check for x CC y ? x : y.
16410 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16411 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16416 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16419 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16422 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16425 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16427 // Check for x CC y ? y : x -- a min/max with reversed arms.
16428 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16429 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16434 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
16437 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
16440 Opc = hasSigned ? X86ISD::SMAX : 0; break;
16443 Opc = hasSigned ? X86ISD::SMIN : 0; break;
16447 return std::make_pair(Opc, NeedSplit);
16450 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
16452 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
16453 TargetLowering::DAGCombinerInfo &DCI,
16454 const X86Subtarget *Subtarget) {
16456 SDValue Cond = N->getOperand(0);
16457 // Get the LHS/RHS of the select.
16458 SDValue LHS = N->getOperand(1);
16459 SDValue RHS = N->getOperand(2);
16460 EVT VT = LHS.getValueType();
16461 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16463 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
16464 // instructions match the semantics of the common C idiom x<y?x:y but not
16465 // x<=y?x:y, because of how they handle negative zero (which can be
16466 // ignored in unsafe-math mode).
16467 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
16468 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
16469 (Subtarget->hasSSE2() ||
16470 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
16471 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16473 unsigned Opcode = 0;
16474 // Check for x CC y ? x : y.
16475 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16476 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16480 // Converting this to a min would handle NaNs incorrectly, and swapping
16481 // the operands would cause it to handle comparisons between positive
16482 // and negative zero incorrectly.
16483 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16484 if (!DAG.getTarget().Options.UnsafeFPMath &&
16485 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16487 std::swap(LHS, RHS);
16489 Opcode = X86ISD::FMIN;
16492 // Converting this to a min would handle comparisons between positive
16493 // and negative zero incorrectly.
16494 if (!DAG.getTarget().Options.UnsafeFPMath &&
16495 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16497 Opcode = X86ISD::FMIN;
16500 // Converting this to a min would handle both negative zeros and NaNs
16501 // incorrectly, but we can swap the operands to fix both.
16502 std::swap(LHS, RHS);
16506 Opcode = X86ISD::FMIN;
16510 // Converting this to a max would handle comparisons between positive
16511 // and negative zero incorrectly.
16512 if (!DAG.getTarget().Options.UnsafeFPMath &&
16513 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
16515 Opcode = X86ISD::FMAX;
16518 // Converting this to a max would handle NaNs incorrectly, and swapping
16519 // the operands would cause it to handle comparisons between positive
16520 // and negative zero incorrectly.
16521 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
16522 if (!DAG.getTarget().Options.UnsafeFPMath &&
16523 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
16525 std::swap(LHS, RHS);
16527 Opcode = X86ISD::FMAX;
16530 // Converting this to a max would handle both negative zeros and NaNs
16531 // incorrectly, but we can swap the operands to fix both.
16532 std::swap(LHS, RHS);
16536 Opcode = X86ISD::FMAX;
16539 // Check for x CC y ? y : x -- a min/max with reversed arms.
16540 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
16541 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
16545 // Converting this to a min would handle comparisons between positive
16546 // and negative zero incorrectly, and swapping the operands would
16547 // cause it to handle NaNs incorrectly.
16548 if (!DAG.getTarget().Options.UnsafeFPMath &&
16549 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
16550 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16552 std::swap(LHS, RHS);
16554 Opcode = X86ISD::FMIN;
16557 // Converting this to a min would handle NaNs incorrectly.
16558 if (!DAG.getTarget().Options.UnsafeFPMath &&
16559 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
16561 Opcode = X86ISD::FMIN;
16564 // Converting this to a min would handle both negative zeros and NaNs
16565 // incorrectly, but we can swap the operands to fix both.
16566 std::swap(LHS, RHS);
16570 Opcode = X86ISD::FMIN;
16574 // Converting this to a max would handle NaNs incorrectly.
16575 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16577 Opcode = X86ISD::FMAX;
16580 // Converting this to a max would handle comparisons between positive
16581 // and negative zero incorrectly, and swapping the operands would
16582 // cause it to handle NaNs incorrectly.
16583 if (!DAG.getTarget().Options.UnsafeFPMath &&
16584 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
16585 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
16587 std::swap(LHS, RHS);
16589 Opcode = X86ISD::FMAX;
16592 // Converting this to a max would handle both negative zeros and NaNs
16593 // incorrectly, but we can swap the operands to fix both.
16594 std::swap(LHS, RHS);
16598 Opcode = X86ISD::FMAX;
16604 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
16607 if (Subtarget->hasAVX512() && VT.isVector() &&
16608 Cond.getValueType().getVectorElementType() == MVT::i1) {
16609 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
16610 // lowering on AVX-512. In this case we convert it to
16611 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
16612 // The same situation for all 128 and 256-bit vectors of i8 and i16
16613 EVT OpVT = LHS.getValueType();
16614 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
16615 (OpVT.getVectorElementType() == MVT::i8 ||
16616 OpVT.getVectorElementType() == MVT::i16)) {
16617 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
16618 DCI.AddToWorklist(Cond.getNode());
16619 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
16622 // If this is a select between two integer constants, try to do some
16624 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
16625 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
16626 // Don't do this for crazy integer types.
16627 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
16628 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
16629 // so that TrueC (the true value) is larger than FalseC.
16630 bool NeedsCondInvert = false;
16632 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
16633 // Efficiently invertible.
16634 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
16635 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
16636 isa<ConstantSDNode>(Cond.getOperand(1))))) {
16637 NeedsCondInvert = true;
16638 std::swap(TrueC, FalseC);
16641 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
16642 if (FalseC->getAPIntValue() == 0 &&
16643 TrueC->getAPIntValue().isPowerOf2()) {
16644 if (NeedsCondInvert) // Invert the condition if needed.
16645 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16646 DAG.getConstant(1, Cond.getValueType()));
16648 // Zero extend the condition if needed.
16649 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
16651 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16652 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
16653 DAG.getConstant(ShAmt, MVT::i8));
16656 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
16657 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16658 if (NeedsCondInvert) // Invert the condition if needed.
16659 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16660 DAG.getConstant(1, Cond.getValueType()));
16662 // Zero extend the condition if needed.
16663 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16664 FalseC->getValueType(0), Cond);
16665 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16666 SDValue(FalseC, 0));
16669 // Optimize cases that will turn into an LEA instruction. This requires
16670 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16671 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16672 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16673 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16675 bool isFastMultiplier = false;
16677 switch ((unsigned char)Diff) {
16679 case 1: // result = add base, cond
16680 case 2: // result = lea base( , cond*2)
16681 case 3: // result = lea base(cond, cond*2)
16682 case 4: // result = lea base( , cond*4)
16683 case 5: // result = lea base(cond, cond*4)
16684 case 8: // result = lea base( , cond*8)
16685 case 9: // result = lea base(cond, cond*8)
16686 isFastMultiplier = true;
16691 if (isFastMultiplier) {
16692 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16693 if (NeedsCondInvert) // Invert the condition if needed.
16694 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
16695 DAG.getConstant(1, Cond.getValueType()));
16697 // Zero extend the condition if needed.
16698 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16700 // Scale the condition by the difference.
16702 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16703 DAG.getConstant(Diff, Cond.getValueType()));
16705 // Add the base if non-zero.
16706 if (FalseC->getAPIntValue() != 0)
16707 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16708 SDValue(FalseC, 0));
16715 // Canonicalize max and min:
16716 // (x > y) ? x : y -> (x >= y) ? x : y
16717 // (x < y) ? x : y -> (x <= y) ? x : y
16718 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16719 // the need for an extra compare
16720 // against zero. e.g.
16721 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16723 // testl %edi, %edi
16725 // cmovgl %edi, %eax
16729 // cmovsl %eax, %edi
16730 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16731 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16732 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16733 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16738 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16739 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16740 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16741 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16746 // Early exit check
16747 if (!TLI.isTypeLegal(VT))
16750 // Match VSELECTs into subs with unsigned saturation.
16751 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16752 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16753 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16754 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16755 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16757 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16758 // left side invert the predicate to simplify logic below.
16760 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16762 CC = ISD::getSetCCInverse(CC, true);
16763 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16767 if (Other.getNode() && Other->getNumOperands() == 2 &&
16768 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16769 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16770 SDValue CondRHS = Cond->getOperand(1);
16772 // Look for a general sub with unsigned saturation first.
16773 // x >= y ? x-y : 0 --> subus x, y
16774 // x > y ? x-y : 0 --> subus x, y
16775 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16776 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16777 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16779 // If the RHS is a constant we have to reverse the const canonicalization.
16780 // x > C-1 ? x+-C : 0 --> subus x, C
16781 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16782 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16783 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16784 if (CondRHS.getConstantOperandVal(0) == -A-1)
16785 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16786 DAG.getConstant(-A, VT));
16789 // Another special case: If C was a sign bit, the sub has been
16790 // canonicalized into a xor.
16791 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16792 // it's safe to decanonicalize the xor?
16793 // x s< 0 ? x^C : 0 --> subus x, C
16794 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16795 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16796 isSplatVector(OpRHS.getNode())) {
16797 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16799 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16804 // Try to match a min/max vector operation.
16805 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
16806 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
16807 unsigned Opc = ret.first;
16808 bool NeedSplit = ret.second;
16810 if (Opc && NeedSplit) {
16811 unsigned NumElems = VT.getVectorNumElements();
16812 // Extract the LHS vectors
16813 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
16814 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
16816 // Extract the RHS vectors
16817 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
16818 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
16820 // Create min/max for each subvector
16821 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
16822 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
16824 // Merge the result
16825 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
16827 return DAG.getNode(Opc, DL, VT, LHS, RHS);
16830 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16831 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16832 // Check if SETCC has already been promoted
16833 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
16835 assert(Cond.getValueType().isVector() &&
16836 "vector select expects a vector selector!");
16838 EVT IntVT = Cond.getValueType();
16839 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16840 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16842 if (!TValIsAllOnes && !FValIsAllZeros) {
16843 // Try invert the condition if true value is not all 1s and false value
16845 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16846 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16848 if (TValIsAllZeros || FValIsAllOnes) {
16849 SDValue CC = Cond.getOperand(2);
16850 ISD::CondCode NewCC =
16851 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16852 Cond.getOperand(0).getValueType().isInteger());
16853 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16854 std::swap(LHS, RHS);
16855 TValIsAllOnes = FValIsAllOnes;
16856 FValIsAllZeros = TValIsAllZeros;
16860 if (TValIsAllOnes || FValIsAllZeros) {
16863 if (TValIsAllOnes && FValIsAllZeros)
16865 else if (TValIsAllOnes)
16866 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16867 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16868 else if (FValIsAllZeros)
16869 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16870 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16872 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16876 // If we know that this node is legal then we know that it is going to be
16877 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16878 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16879 // to simplify previous instructions.
16880 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16881 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16882 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16884 // Don't optimize vector selects that map to mask-registers.
16888 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16889 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16891 APInt KnownZero, KnownOne;
16892 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16893 DCI.isBeforeLegalizeOps());
16894 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16895 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16896 DCI.CommitTargetLoweringOpt(TLO);
16902 // Check whether a boolean test is testing a boolean value generated by
16903 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16906 // Simplify the following patterns:
16907 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16908 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16909 // to (Op EFLAGS Cond)
16911 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16912 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16913 // to (Op EFLAGS !Cond)
16915 // where Op could be BRCOND or CMOV.
16917 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16918 // Quit if not CMP and SUB with its value result used.
16919 if (Cmp.getOpcode() != X86ISD::CMP &&
16920 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16923 // Quit if not used as a boolean value.
16924 if (CC != X86::COND_E && CC != X86::COND_NE)
16927 // Check CMP operands. One of them should be 0 or 1 and the other should be
16928 // an SetCC or extended from it.
16929 SDValue Op1 = Cmp.getOperand(0);
16930 SDValue Op2 = Cmp.getOperand(1);
16933 const ConstantSDNode* C = 0;
16934 bool needOppositeCond = (CC == X86::COND_E);
16935 bool checkAgainstTrue = false; // Is it a comparison against 1?
16937 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16939 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16941 else // Quit if all operands are not constants.
16944 if (C->getZExtValue() == 1) {
16945 needOppositeCond = !needOppositeCond;
16946 checkAgainstTrue = true;
16947 } else if (C->getZExtValue() != 0)
16948 // Quit if the constant is neither 0 or 1.
16951 bool truncatedToBoolWithAnd = false;
16952 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
16953 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
16954 SetCC.getOpcode() == ISD::TRUNCATE ||
16955 SetCC.getOpcode() == ISD::AND) {
16956 if (SetCC.getOpcode() == ISD::AND) {
16958 ConstantSDNode *CS;
16959 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
16960 CS->getZExtValue() == 1)
16962 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
16963 CS->getZExtValue() == 1)
16967 SetCC = SetCC.getOperand(OpIdx);
16968 truncatedToBoolWithAnd = true;
16970 SetCC = SetCC.getOperand(0);
16973 switch (SetCC.getOpcode()) {
16974 case X86ISD::SETCC_CARRY:
16975 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
16976 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
16977 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
16978 // truncated to i1 using 'and'.
16979 if (checkAgainstTrue && !truncatedToBoolWithAnd)
16981 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
16982 "Invalid use of SETCC_CARRY!");
16984 case X86ISD::SETCC:
16985 // Set the condition code or opposite one if necessary.
16986 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
16987 if (needOppositeCond)
16988 CC = X86::GetOppositeBranchCondition(CC);
16989 return SetCC.getOperand(1);
16990 case X86ISD::CMOV: {
16991 // Check whether false/true value has canonical one, i.e. 0 or 1.
16992 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
16993 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
16994 // Quit if true value is not a constant.
16997 // Quit if false value is not a constant.
16999 SDValue Op = SetCC.getOperand(0);
17000 // Skip 'zext' or 'trunc' node.
17001 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
17002 Op.getOpcode() == ISD::TRUNCATE)
17003 Op = Op.getOperand(0);
17004 // A special case for rdrand/rdseed, where 0 is set if false cond is
17006 if ((Op.getOpcode() != X86ISD::RDRAND &&
17007 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
17010 // Quit if false value is not the constant 0 or 1.
17011 bool FValIsFalse = true;
17012 if (FVal && FVal->getZExtValue() != 0) {
17013 if (FVal->getZExtValue() != 1)
17015 // If FVal is 1, opposite cond is needed.
17016 needOppositeCond = !needOppositeCond;
17017 FValIsFalse = false;
17019 // Quit if TVal is not the constant opposite of FVal.
17020 if (FValIsFalse && TVal->getZExtValue() != 1)
17022 if (!FValIsFalse && TVal->getZExtValue() != 0)
17024 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
17025 if (needOppositeCond)
17026 CC = X86::GetOppositeBranchCondition(CC);
17027 return SetCC.getOperand(3);
17034 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
17035 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
17036 TargetLowering::DAGCombinerInfo &DCI,
17037 const X86Subtarget *Subtarget) {
17040 // If the flag operand isn't dead, don't touch this CMOV.
17041 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
17044 SDValue FalseOp = N->getOperand(0);
17045 SDValue TrueOp = N->getOperand(1);
17046 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
17047 SDValue Cond = N->getOperand(3);
17049 if (CC == X86::COND_E || CC == X86::COND_NE) {
17050 switch (Cond.getOpcode()) {
17054 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
17055 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
17056 return (CC == X86::COND_E) ? FalseOp : TrueOp;
17062 Flags = checkBoolTestSetCCCombine(Cond, CC);
17063 if (Flags.getNode() &&
17064 // Extra check as FCMOV only supports a subset of X86 cond.
17065 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
17066 SDValue Ops[] = { FalseOp, TrueOp,
17067 DAG.getConstant(CC, MVT::i8), Flags };
17068 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
17069 Ops, array_lengthof(Ops));
17072 // If this is a select between two integer constants, try to do some
17073 // optimizations. Note that the operands are ordered the opposite of SELECT
17075 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
17076 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
17077 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
17078 // larger than FalseC (the false value).
17079 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
17080 CC = X86::GetOppositeBranchCondition(CC);
17081 std::swap(TrueC, FalseC);
17082 std::swap(TrueOp, FalseOp);
17085 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
17086 // This is efficient for any integer data type (including i8/i16) and
17088 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
17089 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17090 DAG.getConstant(CC, MVT::i8), Cond);
17092 // Zero extend the condition if needed.
17093 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
17095 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
17096 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
17097 DAG.getConstant(ShAmt, MVT::i8));
17098 if (N->getNumValues() == 2) // Dead flag value?
17099 return DCI.CombineTo(N, Cond, SDValue());
17103 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
17104 // for any integer data type, including i8/i16.
17105 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
17106 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17107 DAG.getConstant(CC, MVT::i8), Cond);
17109 // Zero extend the condition if needed.
17110 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
17111 FalseC->getValueType(0), Cond);
17112 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17113 SDValue(FalseC, 0));
17115 if (N->getNumValues() == 2) // Dead flag value?
17116 return DCI.CombineTo(N, Cond, SDValue());
17120 // Optimize cases that will turn into an LEA instruction. This requires
17121 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
17122 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
17123 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
17124 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
17126 bool isFastMultiplier = false;
17128 switch ((unsigned char)Diff) {
17130 case 1: // result = add base, cond
17131 case 2: // result = lea base( , cond*2)
17132 case 3: // result = lea base(cond, cond*2)
17133 case 4: // result = lea base( , cond*4)
17134 case 5: // result = lea base(cond, cond*4)
17135 case 8: // result = lea base( , cond*8)
17136 case 9: // result = lea base(cond, cond*8)
17137 isFastMultiplier = true;
17142 if (isFastMultiplier) {
17143 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
17144 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17145 DAG.getConstant(CC, MVT::i8), Cond);
17146 // Zero extend the condition if needed.
17147 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
17149 // Scale the condition by the difference.
17151 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
17152 DAG.getConstant(Diff, Cond.getValueType()));
17154 // Add the base if non-zero.
17155 if (FalseC->getAPIntValue() != 0)
17156 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
17157 SDValue(FalseC, 0));
17158 if (N->getNumValues() == 2) // Dead flag value?
17159 return DCI.CombineTo(N, Cond, SDValue());
17166 // Handle these cases:
17167 // (select (x != c), e, c) -> select (x != c), e, x),
17168 // (select (x == c), c, e) -> select (x == c), x, e)
17169 // where the c is an integer constant, and the "select" is the combination
17170 // of CMOV and CMP.
17172 // The rationale for this change is that the conditional-move from a constant
17173 // needs two instructions, however, conditional-move from a register needs
17174 // only one instruction.
17176 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
17177 // some instruction-combining opportunities. This opt needs to be
17178 // postponed as late as possible.
17180 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
17181 // the DCI.xxxx conditions are provided to postpone the optimization as
17182 // late as possible.
17184 ConstantSDNode *CmpAgainst = 0;
17185 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
17186 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
17187 !isa<ConstantSDNode>(Cond.getOperand(0))) {
17189 if (CC == X86::COND_NE &&
17190 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
17191 CC = X86::GetOppositeBranchCondition(CC);
17192 std::swap(TrueOp, FalseOp);
17195 if (CC == X86::COND_E &&
17196 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
17197 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
17198 DAG.getConstant(CC, MVT::i8), Cond };
17199 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
17200 array_lengthof(Ops));
17208 /// PerformMulCombine - Optimize a single multiply with constant into two
17209 /// in order to implement it with two cheaper instructions, e.g.
17210 /// LEA + SHL, LEA + LEA.
17211 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
17212 TargetLowering::DAGCombinerInfo &DCI) {
17213 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
17216 EVT VT = N->getValueType(0);
17217 if (VT != MVT::i64)
17220 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
17223 uint64_t MulAmt = C->getZExtValue();
17224 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
17227 uint64_t MulAmt1 = 0;
17228 uint64_t MulAmt2 = 0;
17229 if ((MulAmt % 9) == 0) {
17231 MulAmt2 = MulAmt / 9;
17232 } else if ((MulAmt % 5) == 0) {
17234 MulAmt2 = MulAmt / 5;
17235 } else if ((MulAmt % 3) == 0) {
17237 MulAmt2 = MulAmt / 3;
17240 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
17243 if (isPowerOf2_64(MulAmt2) &&
17244 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
17245 // If second multiplifer is pow2, issue it first. We want the multiply by
17246 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
17248 std::swap(MulAmt1, MulAmt2);
17251 if (isPowerOf2_64(MulAmt1))
17252 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
17253 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
17255 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
17256 DAG.getConstant(MulAmt1, VT));
17258 if (isPowerOf2_64(MulAmt2))
17259 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
17260 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
17262 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
17263 DAG.getConstant(MulAmt2, VT));
17265 // Do not add new nodes to DAG combiner worklist.
17266 DCI.CombineTo(N, NewMul, false);
17271 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
17272 SDValue N0 = N->getOperand(0);
17273 SDValue N1 = N->getOperand(1);
17274 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
17275 EVT VT = N0.getValueType();
17277 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
17278 // since the result of setcc_c is all zero's or all ones.
17279 if (VT.isInteger() && !VT.isVector() &&
17280 N1C && N0.getOpcode() == ISD::AND &&
17281 N0.getOperand(1).getOpcode() == ISD::Constant) {
17282 SDValue N00 = N0.getOperand(0);
17283 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
17284 ((N00.getOpcode() == ISD::ANY_EXTEND ||
17285 N00.getOpcode() == ISD::ZERO_EXTEND) &&
17286 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
17287 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
17288 APInt ShAmt = N1C->getAPIntValue();
17289 Mask = Mask.shl(ShAmt);
17291 return DAG.getNode(ISD::AND, SDLoc(N), VT,
17292 N00, DAG.getConstant(Mask, VT));
17296 // Hardware support for vector shifts is sparse which makes us scalarize the
17297 // vector operations in many cases. Also, on sandybridge ADD is faster than
17299 // (shl V, 1) -> add V,V
17300 if (isSplatVector(N1.getNode())) {
17301 assert(N0.getValueType().isVector() && "Invalid vector shift type");
17302 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
17303 // We shift all of the values by one. In many cases we do not have
17304 // hardware support for this operation. This is better expressed as an ADD
17306 if (N1C && (1 == N1C->getZExtValue())) {
17307 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
17314 /// \brief Returns a vector of 0s if the node in input is a vector logical
17315 /// shift by a constant amount which is known to be bigger than or equal
17316 /// to the vector element size in bits.
17317 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
17318 const X86Subtarget *Subtarget) {
17319 EVT VT = N->getValueType(0);
17321 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
17322 (!Subtarget->hasInt256() ||
17323 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
17326 SDValue Amt = N->getOperand(1);
17328 if (isSplatVector(Amt.getNode())) {
17329 SDValue SclrAmt = Amt->getOperand(0);
17330 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
17331 APInt ShiftAmt = C->getAPIntValue();
17332 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
17334 // SSE2/AVX2 logical shifts always return a vector of 0s
17335 // if the shift amount is bigger than or equal to
17336 // the element size. The constant shift amount will be
17337 // encoded as a 8-bit immediate.
17338 if (ShiftAmt.trunc(8).uge(MaxAmount))
17339 return getZeroVector(VT, Subtarget, DAG, DL);
17346 /// PerformShiftCombine - Combine shifts.
17347 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
17348 TargetLowering::DAGCombinerInfo &DCI,
17349 const X86Subtarget *Subtarget) {
17350 if (N->getOpcode() == ISD::SHL) {
17351 SDValue V = PerformSHLCombine(N, DAG);
17352 if (V.getNode()) return V;
17355 if (N->getOpcode() != ISD::SRA) {
17356 // Try to fold this logical shift into a zero vector.
17357 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
17358 if (V.getNode()) return V;
17364 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
17365 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
17366 // and friends. Likewise for OR -> CMPNEQSS.
17367 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
17368 TargetLowering::DAGCombinerInfo &DCI,
17369 const X86Subtarget *Subtarget) {
17372 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
17373 // we're requiring SSE2 for both.
17374 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
17375 SDValue N0 = N->getOperand(0);
17376 SDValue N1 = N->getOperand(1);
17377 SDValue CMP0 = N0->getOperand(1);
17378 SDValue CMP1 = N1->getOperand(1);
17381 // The SETCCs should both refer to the same CMP.
17382 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
17385 SDValue CMP00 = CMP0->getOperand(0);
17386 SDValue CMP01 = CMP0->getOperand(1);
17387 EVT VT = CMP00.getValueType();
17389 if (VT == MVT::f32 || VT == MVT::f64) {
17390 bool ExpectingFlags = false;
17391 // Check for any users that want flags:
17392 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
17393 !ExpectingFlags && UI != UE; ++UI)
17394 switch (UI->getOpcode()) {
17399 ExpectingFlags = true;
17401 case ISD::CopyToReg:
17402 case ISD::SIGN_EXTEND:
17403 case ISD::ZERO_EXTEND:
17404 case ISD::ANY_EXTEND:
17408 if (!ExpectingFlags) {
17409 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
17410 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
17412 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
17413 X86::CondCode tmp = cc0;
17418 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
17419 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
17420 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
17421 X86ISD::NodeType NTOperator = is64BitFP ?
17422 X86ISD::FSETCCsd : X86ISD::FSETCCss;
17423 // FIXME: need symbolic constants for these magic numbers.
17424 // See X86ATTInstPrinter.cpp:printSSECC().
17425 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
17426 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
17427 DAG.getConstant(x86cc, MVT::i8));
17428 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
17430 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
17431 DAG.getConstant(1, MVT::i32));
17432 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
17433 return OneBitOfTruth;
17441 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
17442 /// so it can be folded inside ANDNP.
17443 static bool CanFoldXORWithAllOnes(const SDNode *N) {
17444 EVT VT = N->getValueType(0);
17446 // Match direct AllOnes for 128 and 256-bit vectors
17447 if (ISD::isBuildVectorAllOnes(N))
17450 // Look through a bit convert.
17451 if (N->getOpcode() == ISD::BITCAST)
17452 N = N->getOperand(0).getNode();
17454 // Sometimes the operand may come from a insert_subvector building a 256-bit
17456 if (VT.is256BitVector() &&
17457 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
17458 SDValue V1 = N->getOperand(0);
17459 SDValue V2 = N->getOperand(1);
17461 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
17462 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
17463 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
17464 ISD::isBuildVectorAllOnes(V2.getNode()))
17471 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
17472 // register. In most cases we actually compare or select YMM-sized registers
17473 // and mixing the two types creates horrible code. This method optimizes
17474 // some of the transition sequences.
17475 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
17476 TargetLowering::DAGCombinerInfo &DCI,
17477 const X86Subtarget *Subtarget) {
17478 EVT VT = N->getValueType(0);
17479 if (!VT.is256BitVector())
17482 assert((N->getOpcode() == ISD::ANY_EXTEND ||
17483 N->getOpcode() == ISD::ZERO_EXTEND ||
17484 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
17486 SDValue Narrow = N->getOperand(0);
17487 EVT NarrowVT = Narrow->getValueType(0);
17488 if (!NarrowVT.is128BitVector())
17491 if (Narrow->getOpcode() != ISD::XOR &&
17492 Narrow->getOpcode() != ISD::AND &&
17493 Narrow->getOpcode() != ISD::OR)
17496 SDValue N0 = Narrow->getOperand(0);
17497 SDValue N1 = Narrow->getOperand(1);
17500 // The Left side has to be a trunc.
17501 if (N0.getOpcode() != ISD::TRUNCATE)
17504 // The type of the truncated inputs.
17505 EVT WideVT = N0->getOperand(0)->getValueType(0);
17509 // The right side has to be a 'trunc' or a constant vector.
17510 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
17511 bool RHSConst = (isSplatVector(N1.getNode()) &&
17512 isa<ConstantSDNode>(N1->getOperand(0)));
17513 if (!RHSTrunc && !RHSConst)
17516 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17518 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
17521 // Set N0 and N1 to hold the inputs to the new wide operation.
17522 N0 = N0->getOperand(0);
17524 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
17525 N1->getOperand(0));
17526 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
17527 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
17528 } else if (RHSTrunc) {
17529 N1 = N1->getOperand(0);
17532 // Generate the wide operation.
17533 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
17534 unsigned Opcode = N->getOpcode();
17536 case ISD::ANY_EXTEND:
17538 case ISD::ZERO_EXTEND: {
17539 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
17540 APInt Mask = APInt::getAllOnesValue(InBits);
17541 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
17542 return DAG.getNode(ISD::AND, DL, VT,
17543 Op, DAG.getConstant(Mask, VT));
17545 case ISD::SIGN_EXTEND:
17546 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
17547 Op, DAG.getValueType(NarrowVT));
17549 llvm_unreachable("Unexpected opcode");
17553 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
17554 TargetLowering::DAGCombinerInfo &DCI,
17555 const X86Subtarget *Subtarget) {
17556 EVT VT = N->getValueType(0);
17557 if (DCI.isBeforeLegalizeOps())
17560 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17564 // Create BLSI, BLSR, and BZHI instructions
17565 // BLSI is X & (-X)
17566 // BLSR is X & (X-1)
17567 // BZHI is X & ((1 << Y) - 1)
17568 // BEXTR is ((X >> imm) & (2**size-1))
17569 if (VT == MVT::i32 || VT == MVT::i64) {
17570 SDValue N0 = N->getOperand(0);
17571 SDValue N1 = N->getOperand(1);
17574 if (Subtarget->hasBMI()) {
17575 // Check LHS for neg
17576 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
17577 isZero(N0.getOperand(0)))
17578 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
17580 // Check RHS for neg
17581 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
17582 isZero(N1.getOperand(0)))
17583 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
17585 // Check LHS for X-1
17586 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17587 isAllOnes(N0.getOperand(1)))
17588 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
17590 // Check RHS for X-1
17591 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17592 isAllOnes(N1.getOperand(1)))
17593 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
17596 if (Subtarget->hasBMI2()) {
17597 // Check for (and (add (shl 1, Y), -1), X)
17598 if (N0.getOpcode() == ISD::ADD && isAllOnes(N0.getOperand(1))) {
17599 SDValue N00 = N0.getOperand(0);
17600 if (N00.getOpcode() == ISD::SHL) {
17601 SDValue N001 = N00.getOperand(1);
17602 assert(N001.getValueType() == MVT::i8 && "unexpected type");
17603 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N00.getOperand(0));
17604 if (C && C->getZExtValue() == 1)
17605 return DAG.getNode(X86ISD::BZHI, DL, VT, N1, N001);
17609 // Check for (and X, (add (shl 1, Y), -1))
17610 if (N1.getOpcode() == ISD::ADD && isAllOnes(N1.getOperand(1))) {
17611 SDValue N10 = N1.getOperand(0);
17612 if (N10.getOpcode() == ISD::SHL) {
17613 SDValue N101 = N10.getOperand(1);
17614 assert(N101.getValueType() == MVT::i8 && "unexpected type");
17615 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N10.getOperand(0));
17616 if (C && C->getZExtValue() == 1)
17617 return DAG.getNode(X86ISD::BZHI, DL, VT, N0, N101);
17622 // Check for BEXTR.
17623 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
17624 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
17625 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
17626 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17627 if (MaskNode && ShiftNode) {
17628 uint64_t Mask = MaskNode->getZExtValue();
17629 uint64_t Shift = ShiftNode->getZExtValue();
17630 if (isMask_64(Mask)) {
17631 uint64_t MaskSize = CountPopulation_64(Mask);
17632 if (Shift + MaskSize <= VT.getSizeInBits())
17633 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
17634 DAG.getConstant(Shift | (MaskSize << 8), VT));
17642 // Want to form ANDNP nodes:
17643 // 1) In the hopes of then easily combining them with OR and AND nodes
17644 // to form PBLEND/PSIGN.
17645 // 2) To match ANDN packed intrinsics
17646 if (VT != MVT::v2i64 && VT != MVT::v4i64)
17649 SDValue N0 = N->getOperand(0);
17650 SDValue N1 = N->getOperand(1);
17653 // Check LHS for vnot
17654 if (N0.getOpcode() == ISD::XOR &&
17655 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
17656 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
17657 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
17659 // Check RHS for vnot
17660 if (N1.getOpcode() == ISD::XOR &&
17661 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
17662 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
17663 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
17668 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
17669 TargetLowering::DAGCombinerInfo &DCI,
17670 const X86Subtarget *Subtarget) {
17671 EVT VT = N->getValueType(0);
17672 if (DCI.isBeforeLegalizeOps())
17675 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
17679 SDValue N0 = N->getOperand(0);
17680 SDValue N1 = N->getOperand(1);
17682 // look for psign/blend
17683 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
17684 if (!Subtarget->hasSSSE3() ||
17685 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
17688 // Canonicalize pandn to RHS
17689 if (N0.getOpcode() == X86ISD::ANDNP)
17691 // or (and (m, y), (pandn m, x))
17692 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
17693 SDValue Mask = N1.getOperand(0);
17694 SDValue X = N1.getOperand(1);
17696 if (N0.getOperand(0) == Mask)
17697 Y = N0.getOperand(1);
17698 if (N0.getOperand(1) == Mask)
17699 Y = N0.getOperand(0);
17701 // Check to see if the mask appeared in both the AND and ANDNP and
17705 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
17706 // Look through mask bitcast.
17707 if (Mask.getOpcode() == ISD::BITCAST)
17708 Mask = Mask.getOperand(0);
17709 if (X.getOpcode() == ISD::BITCAST)
17710 X = X.getOperand(0);
17711 if (Y.getOpcode() == ISD::BITCAST)
17712 Y = Y.getOperand(0);
17714 EVT MaskVT = Mask.getValueType();
17716 // Validate that the Mask operand is a vector sra node.
17717 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
17718 // there is no psrai.b
17719 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
17720 unsigned SraAmt = ~0;
17721 if (Mask.getOpcode() == ISD::SRA) {
17722 SDValue Amt = Mask.getOperand(1);
17723 if (isSplatVector(Amt.getNode())) {
17724 SDValue SclrAmt = Amt->getOperand(0);
17725 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
17726 SraAmt = C->getZExtValue();
17728 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
17729 SDValue SraC = Mask.getOperand(1);
17730 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
17732 if ((SraAmt + 1) != EltBits)
17737 // Now we know we at least have a plendvb with the mask val. See if
17738 // we can form a psignb/w/d.
17739 // psign = x.type == y.type == mask.type && y = sub(0, x);
17740 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
17741 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
17742 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
17743 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
17744 "Unsupported VT for PSIGN");
17745 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
17746 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17748 // PBLENDVB only available on SSE 4.1
17749 if (!Subtarget->hasSSE41())
17752 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
17754 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
17755 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
17756 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
17757 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
17758 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
17762 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
17765 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
17766 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17768 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17770 if (!N0.hasOneUse() || !N1.hasOneUse())
17773 SDValue ShAmt0 = N0.getOperand(1);
17774 if (ShAmt0.getValueType() != MVT::i8)
17776 SDValue ShAmt1 = N1.getOperand(1);
17777 if (ShAmt1.getValueType() != MVT::i8)
17779 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17780 ShAmt0 = ShAmt0.getOperand(0);
17781 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17782 ShAmt1 = ShAmt1.getOperand(0);
17785 unsigned Opc = X86ISD::SHLD;
17786 SDValue Op0 = N0.getOperand(0);
17787 SDValue Op1 = N1.getOperand(0);
17788 if (ShAmt0.getOpcode() == ISD::SUB) {
17789 Opc = X86ISD::SHRD;
17790 std::swap(Op0, Op1);
17791 std::swap(ShAmt0, ShAmt1);
17794 unsigned Bits = VT.getSizeInBits();
17795 if (ShAmt1.getOpcode() == ISD::SUB) {
17796 SDValue Sum = ShAmt1.getOperand(0);
17797 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17798 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17799 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17800 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17801 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17802 return DAG.getNode(Opc, DL, VT,
17804 DAG.getNode(ISD::TRUNCATE, DL,
17807 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17808 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17810 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17811 return DAG.getNode(Opc, DL, VT,
17812 N0.getOperand(0), N1.getOperand(0),
17813 DAG.getNode(ISD::TRUNCATE, DL,
17820 // Generate NEG and CMOV for integer abs.
17821 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17822 EVT VT = N->getValueType(0);
17824 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17825 // 8-bit integer abs to NEG and CMOV.
17826 if (VT.isInteger() && VT.getSizeInBits() == 8)
17829 SDValue N0 = N->getOperand(0);
17830 SDValue N1 = N->getOperand(1);
17833 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17834 // and change it to SUB and CMOV.
17835 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17836 N0.getOpcode() == ISD::ADD &&
17837 N0.getOperand(1) == N1 &&
17838 N1.getOpcode() == ISD::SRA &&
17839 N1.getOperand(0) == N0.getOperand(0))
17840 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17841 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17842 // Generate SUB & CMOV.
17843 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17844 DAG.getConstant(0, VT), N0.getOperand(0));
17846 SDValue Ops[] = { N0.getOperand(0), Neg,
17847 DAG.getConstant(X86::COND_GE, MVT::i8),
17848 SDValue(Neg.getNode(), 1) };
17849 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17850 Ops, array_lengthof(Ops));
17855 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17856 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17857 TargetLowering::DAGCombinerInfo &DCI,
17858 const X86Subtarget *Subtarget) {
17859 EVT VT = N->getValueType(0);
17860 if (DCI.isBeforeLegalizeOps())
17863 if (Subtarget->hasCMov()) {
17864 SDValue RV = performIntegerAbsCombine(N, DAG);
17869 // Try forming BMI if it is available.
17870 if (!Subtarget->hasBMI())
17873 if (VT != MVT::i32 && VT != MVT::i64)
17876 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17878 // Create BLSMSK instructions by finding X ^ (X-1)
17879 SDValue N0 = N->getOperand(0);
17880 SDValue N1 = N->getOperand(1);
17883 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17884 isAllOnes(N0.getOperand(1)))
17885 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17887 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17888 isAllOnes(N1.getOperand(1)))
17889 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17894 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17895 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17896 TargetLowering::DAGCombinerInfo &DCI,
17897 const X86Subtarget *Subtarget) {
17898 LoadSDNode *Ld = cast<LoadSDNode>(N);
17899 EVT RegVT = Ld->getValueType(0);
17900 EVT MemVT = Ld->getMemoryVT();
17902 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17903 unsigned RegSz = RegVT.getSizeInBits();
17905 // On Sandybridge unaligned 256bit loads are inefficient.
17906 ISD::LoadExtType Ext = Ld->getExtensionType();
17907 unsigned Alignment = Ld->getAlignment();
17908 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17909 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17910 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17911 unsigned NumElems = RegVT.getVectorNumElements();
17915 SDValue Ptr = Ld->getBasePtr();
17916 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17918 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17920 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17921 Ld->getPointerInfo(), Ld->isVolatile(),
17922 Ld->isNonTemporal(), Ld->isInvariant(),
17924 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17925 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17926 Ld->getPointerInfo(), Ld->isVolatile(),
17927 Ld->isNonTemporal(), Ld->isInvariant(),
17928 std::min(16U, Alignment));
17929 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17931 Load2.getValue(1));
17933 SDValue NewVec = DAG.getUNDEF(RegVT);
17934 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17935 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17936 return DCI.CombineTo(N, NewVec, TF, true);
17939 // If this is a vector EXT Load then attempt to optimize it using a
17940 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17941 // expansion is still better than scalar code.
17942 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17943 // emit a shuffle and a arithmetic shift.
17944 // TODO: It is possible to support ZExt by zeroing the undef values
17945 // during the shuffle phase or after the shuffle.
17946 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
17947 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
17948 assert(MemVT != RegVT && "Cannot extend to the same type");
17949 assert(MemVT.isVector() && "Must load a vector from memory");
17951 unsigned NumElems = RegVT.getVectorNumElements();
17952 unsigned MemSz = MemVT.getSizeInBits();
17953 assert(RegSz > MemSz && "Register size must be greater than the mem size");
17955 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
17958 // All sizes must be a power of two.
17959 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
17962 // Attempt to load the original value using scalar loads.
17963 // Find the largest scalar type that divides the total loaded size.
17964 MVT SclrLoadTy = MVT::i8;
17965 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17966 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17967 MVT Tp = (MVT::SimpleValueType)tp;
17968 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
17973 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17974 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
17976 SclrLoadTy = MVT::f64;
17978 // Calculate the number of scalar loads that we need to perform
17979 // in order to load our vector from memory.
17980 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
17981 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
17984 unsigned loadRegZize = RegSz;
17985 if (Ext == ISD::SEXTLOAD && RegSz == 256)
17988 // Represent our vector as a sequence of elements which are the
17989 // largest scalar that we can load.
17990 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
17991 loadRegZize/SclrLoadTy.getSizeInBits());
17993 // Represent the data using the same element type that is stored in
17994 // memory. In practice, we ''widen'' MemVT.
17996 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17997 loadRegZize/MemVT.getScalarType().getSizeInBits());
17999 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
18000 "Invalid vector type");
18002 // We can't shuffle using an illegal type.
18003 if (!TLI.isTypeLegal(WideVecVT))
18006 SmallVector<SDValue, 8> Chains;
18007 SDValue Ptr = Ld->getBasePtr();
18008 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
18009 TLI.getPointerTy());
18010 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
18012 for (unsigned i = 0; i < NumLoads; ++i) {
18013 // Perform a single load.
18014 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
18015 Ptr, Ld->getPointerInfo(),
18016 Ld->isVolatile(), Ld->isNonTemporal(),
18017 Ld->isInvariant(), Ld->getAlignment());
18018 Chains.push_back(ScalarLoad.getValue(1));
18019 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
18020 // another round of DAGCombining.
18022 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
18024 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
18025 ScalarLoad, DAG.getIntPtrConstant(i));
18027 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18030 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18033 // Bitcast the loaded value to a vector of the original element type, in
18034 // the size of the target vector type.
18035 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
18036 unsigned SizeRatio = RegSz/MemSz;
18038 if (Ext == ISD::SEXTLOAD) {
18039 // If we have SSE4.1 we can directly emit a VSEXT node.
18040 if (Subtarget->hasSSE41()) {
18041 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
18042 return DCI.CombineTo(N, Sext, TF, true);
18045 // Otherwise we'll shuffle the small elements in the high bits of the
18046 // larger type and perform an arithmetic shift. If the shift is not legal
18047 // it's better to scalarize.
18048 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
18051 // Redistribute the loaded elements into the different locations.
18052 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18053 for (unsigned i = 0; i != NumElems; ++i)
18054 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
18056 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18057 DAG.getUNDEF(WideVecVT),
18060 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18062 // Build the arithmetic shift.
18063 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
18064 MemVT.getVectorElementType().getSizeInBits();
18065 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
18066 DAG.getConstant(Amt, RegVT));
18068 return DCI.CombineTo(N, Shuff, TF, true);
18071 // Redistribute the loaded elements into the different locations.
18072 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18073 for (unsigned i = 0; i != NumElems; ++i)
18074 ShuffleVec[i*SizeRatio] = i;
18076 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
18077 DAG.getUNDEF(WideVecVT),
18080 // Bitcast to the requested type.
18081 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
18082 // Replace the original load with the new sequence
18083 // and return the new chain.
18084 return DCI.CombineTo(N, Shuff, TF, true);
18090 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
18091 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
18092 const X86Subtarget *Subtarget) {
18093 StoreSDNode *St = cast<StoreSDNode>(N);
18094 EVT VT = St->getValue().getValueType();
18095 EVT StVT = St->getMemoryVT();
18097 SDValue StoredVal = St->getOperand(1);
18098 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18100 // If we are saving a concatenation of two XMM registers, perform two stores.
18101 // On Sandy Bridge, 256-bit memory operations are executed by two
18102 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
18103 // memory operation.
18104 unsigned Alignment = St->getAlignment();
18105 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
18106 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
18107 StVT == VT && !IsAligned) {
18108 unsigned NumElems = VT.getVectorNumElements();
18112 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
18113 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
18115 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
18116 SDValue Ptr0 = St->getBasePtr();
18117 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
18119 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
18120 St->getPointerInfo(), St->isVolatile(),
18121 St->isNonTemporal(), Alignment);
18122 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
18123 St->getPointerInfo(), St->isVolatile(),
18124 St->isNonTemporal(),
18125 std::min(16U, Alignment));
18126 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
18129 // Optimize trunc store (of multiple scalars) to shuffle and store.
18130 // First, pack all of the elements in one place. Next, store to memory
18131 // in fewer chunks.
18132 if (St->isTruncatingStore() && VT.isVector()) {
18133 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18134 unsigned NumElems = VT.getVectorNumElements();
18135 assert(StVT != VT && "Cannot truncate to the same type");
18136 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
18137 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
18139 // From, To sizes and ElemCount must be pow of two
18140 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
18141 // We are going to use the original vector elt for storing.
18142 // Accumulated smaller vector elements must be a multiple of the store size.
18143 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
18145 unsigned SizeRatio = FromSz / ToSz;
18147 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
18149 // Create a type on which we perform the shuffle
18150 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
18151 StVT.getScalarType(), NumElems*SizeRatio);
18153 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
18155 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
18156 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
18157 for (unsigned i = 0; i != NumElems; ++i)
18158 ShuffleVec[i] = i * SizeRatio;
18160 // Can't shuffle using an illegal type.
18161 if (!TLI.isTypeLegal(WideVecVT))
18164 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
18165 DAG.getUNDEF(WideVecVT),
18167 // At this point all of the data is stored at the bottom of the
18168 // register. We now need to save it to mem.
18170 // Find the largest store unit
18171 MVT StoreType = MVT::i8;
18172 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
18173 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
18174 MVT Tp = (MVT::SimpleValueType)tp;
18175 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
18179 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
18180 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
18181 (64 <= NumElems * ToSz))
18182 StoreType = MVT::f64;
18184 // Bitcast the original vector into a vector of store-size units
18185 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
18186 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
18187 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
18188 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
18189 SmallVector<SDValue, 8> Chains;
18190 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
18191 TLI.getPointerTy());
18192 SDValue Ptr = St->getBasePtr();
18194 // Perform one or more big stores into memory.
18195 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
18196 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
18197 StoreType, ShuffWide,
18198 DAG.getIntPtrConstant(i));
18199 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
18200 St->getPointerInfo(), St->isVolatile(),
18201 St->isNonTemporal(), St->getAlignment());
18202 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
18203 Chains.push_back(Ch);
18206 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
18210 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
18211 // the FP state in cases where an emms may be missing.
18212 // A preferable solution to the general problem is to figure out the right
18213 // places to insert EMMS. This qualifies as a quick hack.
18215 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
18216 if (VT.getSizeInBits() != 64)
18219 const Function *F = DAG.getMachineFunction().getFunction();
18220 bool NoImplicitFloatOps = F->getAttributes().
18221 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
18222 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
18223 && Subtarget->hasSSE2();
18224 if ((VT.isVector() ||
18225 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
18226 isa<LoadSDNode>(St->getValue()) &&
18227 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
18228 St->getChain().hasOneUse() && !St->isVolatile()) {
18229 SDNode* LdVal = St->getValue().getNode();
18230 LoadSDNode *Ld = 0;
18231 int TokenFactorIndex = -1;
18232 SmallVector<SDValue, 8> Ops;
18233 SDNode* ChainVal = St->getChain().getNode();
18234 // Must be a store of a load. We currently handle two cases: the load
18235 // is a direct child, and it's under an intervening TokenFactor. It is
18236 // possible to dig deeper under nested TokenFactors.
18237 if (ChainVal == LdVal)
18238 Ld = cast<LoadSDNode>(St->getChain());
18239 else if (St->getValue().hasOneUse() &&
18240 ChainVal->getOpcode() == ISD::TokenFactor) {
18241 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
18242 if (ChainVal->getOperand(i).getNode() == LdVal) {
18243 TokenFactorIndex = i;
18244 Ld = cast<LoadSDNode>(St->getValue());
18246 Ops.push_back(ChainVal->getOperand(i));
18250 if (!Ld || !ISD::isNormalLoad(Ld))
18253 // If this is not the MMX case, i.e. we are just turning i64 load/store
18254 // into f64 load/store, avoid the transformation if there are multiple
18255 // uses of the loaded value.
18256 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
18261 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
18262 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
18264 if (Subtarget->is64Bit() || F64IsLegal) {
18265 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
18266 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
18267 Ld->getPointerInfo(), Ld->isVolatile(),
18268 Ld->isNonTemporal(), Ld->isInvariant(),
18269 Ld->getAlignment());
18270 SDValue NewChain = NewLd.getValue(1);
18271 if (TokenFactorIndex != -1) {
18272 Ops.push_back(NewChain);
18273 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18276 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
18277 St->getPointerInfo(),
18278 St->isVolatile(), St->isNonTemporal(),
18279 St->getAlignment());
18282 // Otherwise, lower to two pairs of 32-bit loads / stores.
18283 SDValue LoAddr = Ld->getBasePtr();
18284 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
18285 DAG.getConstant(4, MVT::i32));
18287 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
18288 Ld->getPointerInfo(),
18289 Ld->isVolatile(), Ld->isNonTemporal(),
18290 Ld->isInvariant(), Ld->getAlignment());
18291 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
18292 Ld->getPointerInfo().getWithOffset(4),
18293 Ld->isVolatile(), Ld->isNonTemporal(),
18295 MinAlign(Ld->getAlignment(), 4));
18297 SDValue NewChain = LoLd.getValue(1);
18298 if (TokenFactorIndex != -1) {
18299 Ops.push_back(LoLd);
18300 Ops.push_back(HiLd);
18301 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
18305 LoAddr = St->getBasePtr();
18306 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
18307 DAG.getConstant(4, MVT::i32));
18309 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
18310 St->getPointerInfo(),
18311 St->isVolatile(), St->isNonTemporal(),
18312 St->getAlignment());
18313 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
18314 St->getPointerInfo().getWithOffset(4),
18316 St->isNonTemporal(),
18317 MinAlign(St->getAlignment(), 4));
18318 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
18323 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
18324 /// and return the operands for the horizontal operation in LHS and RHS. A
18325 /// horizontal operation performs the binary operation on successive elements
18326 /// of its first operand, then on successive elements of its second operand,
18327 /// returning the resulting values in a vector. For example, if
18328 /// A = < float a0, float a1, float a2, float a3 >
18330 /// B = < float b0, float b1, float b2, float b3 >
18331 /// then the result of doing a horizontal operation on A and B is
18332 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
18333 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
18334 /// A horizontal-op B, for some already available A and B, and if so then LHS is
18335 /// set to A, RHS to B, and the routine returns 'true'.
18336 /// Note that the binary operation should have the property that if one of the
18337 /// operands is UNDEF then the result is UNDEF.
18338 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
18339 // Look for the following pattern: if
18340 // A = < float a0, float a1, float a2, float a3 >
18341 // B = < float b0, float b1, float b2, float b3 >
18343 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
18344 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
18345 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
18346 // which is A horizontal-op B.
18348 // At least one of the operands should be a vector shuffle.
18349 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
18350 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
18353 MVT VT = LHS.getSimpleValueType();
18355 assert((VT.is128BitVector() || VT.is256BitVector()) &&
18356 "Unsupported vector type for horizontal add/sub");
18358 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
18359 // operate independently on 128-bit lanes.
18360 unsigned NumElts = VT.getVectorNumElements();
18361 unsigned NumLanes = VT.getSizeInBits()/128;
18362 unsigned NumLaneElts = NumElts / NumLanes;
18363 assert((NumLaneElts % 2 == 0) &&
18364 "Vector type should have an even number of elements in each lane");
18365 unsigned HalfLaneElts = NumLaneElts/2;
18367 // View LHS in the form
18368 // LHS = VECTOR_SHUFFLE A, B, LMask
18369 // If LHS is not a shuffle then pretend it is the shuffle
18370 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
18371 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
18374 SmallVector<int, 16> LMask(NumElts);
18375 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18376 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
18377 A = LHS.getOperand(0);
18378 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
18379 B = LHS.getOperand(1);
18380 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
18381 std::copy(Mask.begin(), Mask.end(), LMask.begin());
18383 if (LHS.getOpcode() != ISD::UNDEF)
18385 for (unsigned i = 0; i != NumElts; ++i)
18389 // Likewise, view RHS in the form
18390 // RHS = VECTOR_SHUFFLE C, D, RMask
18392 SmallVector<int, 16> RMask(NumElts);
18393 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
18394 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
18395 C = RHS.getOperand(0);
18396 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
18397 D = RHS.getOperand(1);
18398 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
18399 std::copy(Mask.begin(), Mask.end(), RMask.begin());
18401 if (RHS.getOpcode() != ISD::UNDEF)
18403 for (unsigned i = 0; i != NumElts; ++i)
18407 // Check that the shuffles are both shuffling the same vectors.
18408 if (!(A == C && B == D) && !(A == D && B == C))
18411 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
18412 if (!A.getNode() && !B.getNode())
18415 // If A and B occur in reverse order in RHS, then "swap" them (which means
18416 // rewriting the mask).
18418 CommuteVectorShuffleMask(RMask, NumElts);
18420 // At this point LHS and RHS are equivalent to
18421 // LHS = VECTOR_SHUFFLE A, B, LMask
18422 // RHS = VECTOR_SHUFFLE A, B, RMask
18423 // Check that the masks correspond to performing a horizontal operation.
18424 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
18425 for (unsigned i = 0; i != NumLaneElts; ++i) {
18426 int LIdx = LMask[i+l], RIdx = RMask[i+l];
18428 // Ignore any UNDEF components.
18429 if (LIdx < 0 || RIdx < 0 ||
18430 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
18431 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
18434 // Check that successive elements are being operated on. If not, this is
18435 // not a horizontal operation.
18436 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
18437 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
18438 if (!(LIdx == Index && RIdx == Index + 1) &&
18439 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
18444 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
18445 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
18449 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
18450 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
18451 const X86Subtarget *Subtarget) {
18452 EVT VT = N->getValueType(0);
18453 SDValue LHS = N->getOperand(0);
18454 SDValue RHS = N->getOperand(1);
18456 // Try to synthesize horizontal adds from adds of shuffles.
18457 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18458 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18459 isHorizontalBinOp(LHS, RHS, true))
18460 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
18464 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
18465 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
18466 const X86Subtarget *Subtarget) {
18467 EVT VT = N->getValueType(0);
18468 SDValue LHS = N->getOperand(0);
18469 SDValue RHS = N->getOperand(1);
18471 // Try to synthesize horizontal subs from subs of shuffles.
18472 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
18473 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
18474 isHorizontalBinOp(LHS, RHS, false))
18475 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
18479 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
18480 /// X86ISD::FXOR nodes.
18481 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
18482 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
18483 // F[X]OR(0.0, x) -> x
18484 // F[X]OR(x, 0.0) -> x
18485 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18486 if (C->getValueAPF().isPosZero())
18487 return N->getOperand(1);
18488 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18489 if (C->getValueAPF().isPosZero())
18490 return N->getOperand(0);
18494 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
18495 /// X86ISD::FMAX nodes.
18496 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
18497 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
18499 // Only perform optimizations if UnsafeMath is used.
18500 if (!DAG.getTarget().Options.UnsafeFPMath)
18503 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
18504 // into FMINC and FMAXC, which are Commutative operations.
18505 unsigned NewOp = 0;
18506 switch (N->getOpcode()) {
18507 default: llvm_unreachable("unknown opcode");
18508 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
18509 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
18512 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
18513 N->getOperand(0), N->getOperand(1));
18516 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
18517 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
18518 // FAND(0.0, x) -> 0.0
18519 // FAND(x, 0.0) -> 0.0
18520 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18521 if (C->getValueAPF().isPosZero())
18522 return N->getOperand(0);
18523 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18524 if (C->getValueAPF().isPosZero())
18525 return N->getOperand(1);
18529 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
18530 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
18531 // FANDN(x, 0.0) -> 0.0
18532 // FANDN(0.0, x) -> x
18533 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
18534 if (C->getValueAPF().isPosZero())
18535 return N->getOperand(1);
18536 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
18537 if (C->getValueAPF().isPosZero())
18538 return N->getOperand(1);
18542 static SDValue PerformBTCombine(SDNode *N,
18544 TargetLowering::DAGCombinerInfo &DCI) {
18545 // BT ignores high bits in the bit index operand.
18546 SDValue Op1 = N->getOperand(1);
18547 if (Op1.hasOneUse()) {
18548 unsigned BitWidth = Op1.getValueSizeInBits();
18549 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
18550 APInt KnownZero, KnownOne;
18551 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
18552 !DCI.isBeforeLegalizeOps());
18553 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18554 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
18555 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
18556 DCI.CommitTargetLoweringOpt(TLO);
18561 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
18562 SDValue Op = N->getOperand(0);
18563 if (Op.getOpcode() == ISD::BITCAST)
18564 Op = Op.getOperand(0);
18565 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
18566 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
18567 VT.getVectorElementType().getSizeInBits() ==
18568 OpVT.getVectorElementType().getSizeInBits()) {
18569 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
18574 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
18575 const X86Subtarget *Subtarget) {
18576 EVT VT = N->getValueType(0);
18577 if (!VT.isVector())
18580 SDValue N0 = N->getOperand(0);
18581 SDValue N1 = N->getOperand(1);
18582 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
18585 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
18586 // both SSE and AVX2 since there is no sign-extended shift right
18587 // operation on a vector with 64-bit elements.
18588 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
18589 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
18590 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
18591 N0.getOpcode() == ISD::SIGN_EXTEND)) {
18592 SDValue N00 = N0.getOperand(0);
18594 // EXTLOAD has a better solution on AVX2,
18595 // it may be replaced with X86ISD::VSEXT node.
18596 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
18597 if (!ISD::isNormalLoad(N00.getNode()))
18600 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
18601 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
18603 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
18609 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
18610 TargetLowering::DAGCombinerInfo &DCI,
18611 const X86Subtarget *Subtarget) {
18612 if (!DCI.isBeforeLegalizeOps())
18615 if (!Subtarget->hasFp256())
18618 EVT VT = N->getValueType(0);
18619 if (VT.isVector() && VT.getSizeInBits() == 256) {
18620 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18628 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
18629 const X86Subtarget* Subtarget) {
18631 EVT VT = N->getValueType(0);
18633 // Let legalize expand this if it isn't a legal type yet.
18634 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18637 EVT ScalarVT = VT.getScalarType();
18638 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
18639 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
18642 SDValue A = N->getOperand(0);
18643 SDValue B = N->getOperand(1);
18644 SDValue C = N->getOperand(2);
18646 bool NegA = (A.getOpcode() == ISD::FNEG);
18647 bool NegB = (B.getOpcode() == ISD::FNEG);
18648 bool NegC = (C.getOpcode() == ISD::FNEG);
18650 // Negative multiplication when NegA xor NegB
18651 bool NegMul = (NegA != NegB);
18653 A = A.getOperand(0);
18655 B = B.getOperand(0);
18657 C = C.getOperand(0);
18661 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
18663 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
18665 return DAG.getNode(Opcode, dl, VT, A, B, C);
18668 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
18669 TargetLowering::DAGCombinerInfo &DCI,
18670 const X86Subtarget *Subtarget) {
18671 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
18672 // (and (i32 x86isd::setcc_carry), 1)
18673 // This eliminates the zext. This transformation is necessary because
18674 // ISD::SETCC is always legalized to i8.
18676 SDValue N0 = N->getOperand(0);
18677 EVT VT = N->getValueType(0);
18679 if (N0.getOpcode() == ISD::AND &&
18681 N0.getOperand(0).hasOneUse()) {
18682 SDValue N00 = N0.getOperand(0);
18683 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
18684 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
18685 if (!C || C->getZExtValue() != 1)
18687 return DAG.getNode(ISD::AND, dl, VT,
18688 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
18689 N00.getOperand(0), N00.getOperand(1)),
18690 DAG.getConstant(1, VT));
18694 if (VT.is256BitVector()) {
18695 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
18703 // Optimize x == -y --> x+y == 0
18704 // x != -y --> x+y != 0
18705 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
18706 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
18707 SDValue LHS = N->getOperand(0);
18708 SDValue RHS = N->getOperand(1);
18710 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
18711 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
18712 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
18713 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18714 LHS.getValueType(), RHS, LHS.getOperand(1));
18715 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18716 addV, DAG.getConstant(0, addV.getValueType()), CC);
18718 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
18719 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
18720 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
18721 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
18722 RHS.getValueType(), LHS, RHS.getOperand(1));
18723 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
18724 addV, DAG.getConstant(0, addV.getValueType()), CC);
18729 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
18730 // as "sbb reg,reg", since it can be extended without zext and produces
18731 // an all-ones bit which is more useful than 0/1 in some cases.
18732 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
18733 return DAG.getNode(ISD::AND, DL, MVT::i8,
18734 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
18735 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
18736 DAG.getConstant(1, MVT::i8));
18739 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
18740 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
18741 TargetLowering::DAGCombinerInfo &DCI,
18742 const X86Subtarget *Subtarget) {
18744 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
18745 SDValue EFLAGS = N->getOperand(1);
18747 if (CC == X86::COND_A) {
18748 // Try to convert COND_A into COND_B in an attempt to facilitate
18749 // materializing "setb reg".
18751 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
18752 // cannot take an immediate as its first operand.
18754 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
18755 EFLAGS.getValueType().isInteger() &&
18756 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
18757 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
18758 EFLAGS.getNode()->getVTList(),
18759 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
18760 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
18761 return MaterializeSETB(DL, NewEFLAGS, DAG);
18765 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
18766 // a zext and produces an all-ones bit which is more useful than 0/1 in some
18768 if (CC == X86::COND_B)
18769 return MaterializeSETB(DL, EFLAGS, DAG);
18773 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18774 if (Flags.getNode()) {
18775 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18776 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18782 // Optimize branch condition evaluation.
18784 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18785 TargetLowering::DAGCombinerInfo &DCI,
18786 const X86Subtarget *Subtarget) {
18788 SDValue Chain = N->getOperand(0);
18789 SDValue Dest = N->getOperand(1);
18790 SDValue EFLAGS = N->getOperand(3);
18791 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18795 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18796 if (Flags.getNode()) {
18797 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18798 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18805 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18806 const X86TargetLowering *XTLI) {
18807 SDValue Op0 = N->getOperand(0);
18808 EVT InVT = Op0->getValueType(0);
18810 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18811 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18813 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18814 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18815 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18818 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18819 // a 32-bit target where SSE doesn't support i64->FP operations.
18820 if (Op0.getOpcode() == ISD::LOAD) {
18821 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18822 EVT VT = Ld->getValueType(0);
18823 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18824 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18825 !XTLI->getSubtarget()->is64Bit() &&
18826 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18827 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18828 Ld->getChain(), Op0, DAG);
18829 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18836 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18837 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18838 X86TargetLowering::DAGCombinerInfo &DCI) {
18839 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18840 // the result is either zero or one (depending on the input carry bit).
18841 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18842 if (X86::isZeroNode(N->getOperand(0)) &&
18843 X86::isZeroNode(N->getOperand(1)) &&
18844 // We don't have a good way to replace an EFLAGS use, so only do this when
18846 SDValue(N, 1).use_empty()) {
18848 EVT VT = N->getValueType(0);
18849 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18850 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18851 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18852 DAG.getConstant(X86::COND_B,MVT::i8),
18854 DAG.getConstant(1, VT));
18855 return DCI.CombineTo(N, Res1, CarryOut);
18861 // fold (add Y, (sete X, 0)) -> adc 0, Y
18862 // (add Y, (setne X, 0)) -> sbb -1, Y
18863 // (sub (sete X, 0), Y) -> sbb 0, Y
18864 // (sub (setne X, 0), Y) -> adc -1, Y
18865 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18868 // Look through ZExts.
18869 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18870 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18873 SDValue SetCC = Ext.getOperand(0);
18874 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18877 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18878 if (CC != X86::COND_E && CC != X86::COND_NE)
18881 SDValue Cmp = SetCC.getOperand(1);
18882 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18883 !X86::isZeroNode(Cmp.getOperand(1)) ||
18884 !Cmp.getOperand(0).getValueType().isInteger())
18887 SDValue CmpOp0 = Cmp.getOperand(0);
18888 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18889 DAG.getConstant(1, CmpOp0.getValueType()));
18891 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18892 if (CC == X86::COND_NE)
18893 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18894 DL, OtherVal.getValueType(), OtherVal,
18895 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18896 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18897 DL, OtherVal.getValueType(), OtherVal,
18898 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18901 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18902 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18903 const X86Subtarget *Subtarget) {
18904 EVT VT = N->getValueType(0);
18905 SDValue Op0 = N->getOperand(0);
18906 SDValue Op1 = N->getOperand(1);
18908 // Try to synthesize horizontal adds from adds of shuffles.
18909 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18910 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18911 isHorizontalBinOp(Op0, Op1, true))
18912 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18914 return OptimizeConditionalInDecrement(N, DAG);
18917 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18918 const X86Subtarget *Subtarget) {
18919 SDValue Op0 = N->getOperand(0);
18920 SDValue Op1 = N->getOperand(1);
18922 // X86 can't encode an immediate LHS of a sub. See if we can push the
18923 // negation into a preceding instruction.
18924 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18925 // If the RHS of the sub is a XOR with one use and a constant, invert the
18926 // immediate. Then add one to the LHS of the sub so we can turn
18927 // X-Y -> X+~Y+1, saving one register.
18928 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18929 isa<ConstantSDNode>(Op1.getOperand(1))) {
18930 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18931 EVT VT = Op0.getValueType();
18932 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18934 DAG.getConstant(~XorC, VT));
18935 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18936 DAG.getConstant(C->getAPIntValue()+1, VT));
18940 // Try to synthesize horizontal adds from adds of shuffles.
18941 EVT VT = N->getValueType(0);
18942 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18943 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18944 isHorizontalBinOp(Op0, Op1, true))
18945 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
18947 return OptimizeConditionalInDecrement(N, DAG);
18950 /// performVZEXTCombine - Performs build vector combines
18951 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
18952 TargetLowering::DAGCombinerInfo &DCI,
18953 const X86Subtarget *Subtarget) {
18954 // (vzext (bitcast (vzext (x)) -> (vzext x)
18955 SDValue In = N->getOperand(0);
18956 while (In.getOpcode() == ISD::BITCAST)
18957 In = In.getOperand(0);
18959 if (In.getOpcode() != X86ISD::VZEXT)
18962 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
18966 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
18967 DAGCombinerInfo &DCI) const {
18968 SelectionDAG &DAG = DCI.DAG;
18969 switch (N->getOpcode()) {
18971 case ISD::EXTRACT_VECTOR_ELT:
18972 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
18974 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
18975 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
18976 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
18977 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
18978 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
18979 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
18982 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
18983 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
18984 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
18985 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
18986 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
18987 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
18988 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
18989 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
18990 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
18992 case X86ISD::FOR: return PerformFORCombine(N, DAG);
18994 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
18995 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
18996 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
18997 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
18998 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
18999 case ISD::ANY_EXTEND:
19000 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
19001 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
19002 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
19003 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
19004 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
19005 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
19006 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
19007 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
19008 case X86ISD::SHUFP: // Handle all target specific shuffles
19009 case X86ISD::PALIGNR:
19010 case X86ISD::UNPCKH:
19011 case X86ISD::UNPCKL:
19012 case X86ISD::MOVHLPS:
19013 case X86ISD::MOVLHPS:
19014 case X86ISD::PSHUFD:
19015 case X86ISD::PSHUFHW:
19016 case X86ISD::PSHUFLW:
19017 case X86ISD::MOVSS:
19018 case X86ISD::MOVSD:
19019 case X86ISD::VPERMILP:
19020 case X86ISD::VPERM2X128:
19021 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
19022 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
19028 /// isTypeDesirableForOp - Return true if the target has native support for
19029 /// the specified value type and it is 'desirable' to use the type for the
19030 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
19031 /// instruction encodings are longer and some i16 instructions are slow.
19032 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
19033 if (!isTypeLegal(VT))
19035 if (VT != MVT::i16)
19042 case ISD::SIGN_EXTEND:
19043 case ISD::ZERO_EXTEND:
19044 case ISD::ANY_EXTEND:
19057 /// IsDesirableToPromoteOp - This method query the target whether it is
19058 /// beneficial for dag combiner to promote the specified node. If true, it
19059 /// should return the desired promotion type by reference.
19060 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
19061 EVT VT = Op.getValueType();
19062 if (VT != MVT::i16)
19065 bool Promote = false;
19066 bool Commute = false;
19067 switch (Op.getOpcode()) {
19070 LoadSDNode *LD = cast<LoadSDNode>(Op);
19071 // If the non-extending load has a single use and it's not live out, then it
19072 // might be folded.
19073 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
19074 Op.hasOneUse()*/) {
19075 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
19076 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
19077 // The only case where we'd want to promote LOAD (rather then it being
19078 // promoted as an operand is when it's only use is liveout.
19079 if (UI->getOpcode() != ISD::CopyToReg)
19086 case ISD::SIGN_EXTEND:
19087 case ISD::ZERO_EXTEND:
19088 case ISD::ANY_EXTEND:
19093 SDValue N0 = Op.getOperand(0);
19094 // Look out for (store (shl (load), x)).
19095 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
19108 SDValue N0 = Op.getOperand(0);
19109 SDValue N1 = Op.getOperand(1);
19110 if (!Commute && MayFoldLoad(N1))
19112 // Avoid disabling potential load folding opportunities.
19113 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
19115 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
19125 //===----------------------------------------------------------------------===//
19126 // X86 Inline Assembly Support
19127 //===----------------------------------------------------------------------===//
19130 // Helper to match a string separated by whitespace.
19131 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
19132 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
19134 for (unsigned i = 0, e = args.size(); i != e; ++i) {
19135 StringRef piece(*args[i]);
19136 if (!s.startswith(piece)) // Check if the piece matches.
19139 s = s.substr(piece.size());
19140 StringRef::size_type pos = s.find_first_not_of(" \t");
19141 if (pos == 0) // We matched a prefix.
19149 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
19152 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
19153 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
19155 std::string AsmStr = IA->getAsmString();
19157 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
19158 if (!Ty || Ty->getBitWidth() % 16 != 0)
19161 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
19162 SmallVector<StringRef, 4> AsmPieces;
19163 SplitString(AsmStr, AsmPieces, ";\n");
19165 switch (AsmPieces.size()) {
19166 default: return false;
19168 // FIXME: this should verify that we are targeting a 486 or better. If not,
19169 // we will turn this bswap into something that will be lowered to logical
19170 // ops instead of emitting the bswap asm. For now, we don't support 486 or
19171 // lower so don't worry about this.
19173 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
19174 matchAsm(AsmPieces[0], "bswapl", "$0") ||
19175 matchAsm(AsmPieces[0], "bswapq", "$0") ||
19176 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
19177 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
19178 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
19179 // No need to check constraints, nothing other than the equivalent of
19180 // "=r,0" would be valid here.
19181 return IntrinsicLowering::LowerToByteSwap(CI);
19184 // rorw $$8, ${0:w} --> llvm.bswap.i16
19185 if (CI->getType()->isIntegerTy(16) &&
19186 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19187 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
19188 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
19190 const std::string &ConstraintsStr = IA->getConstraintString();
19191 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19192 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19193 if (AsmPieces.size() == 4 &&
19194 AsmPieces[0] == "~{cc}" &&
19195 AsmPieces[1] == "~{dirflag}" &&
19196 AsmPieces[2] == "~{flags}" &&
19197 AsmPieces[3] == "~{fpsr}")
19198 return IntrinsicLowering::LowerToByteSwap(CI);
19202 if (CI->getType()->isIntegerTy(32) &&
19203 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
19204 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
19205 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
19206 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
19208 const std::string &ConstraintsStr = IA->getConstraintString();
19209 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
19210 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
19211 if (AsmPieces.size() == 4 &&
19212 AsmPieces[0] == "~{cc}" &&
19213 AsmPieces[1] == "~{dirflag}" &&
19214 AsmPieces[2] == "~{flags}" &&
19215 AsmPieces[3] == "~{fpsr}")
19216 return IntrinsicLowering::LowerToByteSwap(CI);
19219 if (CI->getType()->isIntegerTy(64)) {
19220 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
19221 if (Constraints.size() >= 2 &&
19222 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
19223 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
19224 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
19225 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
19226 matchAsm(AsmPieces[1], "bswap", "%edx") &&
19227 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
19228 return IntrinsicLowering::LowerToByteSwap(CI);
19236 /// getConstraintType - Given a constraint letter, return the type of
19237 /// constraint it is for this target.
19238 X86TargetLowering::ConstraintType
19239 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
19240 if (Constraint.size() == 1) {
19241 switch (Constraint[0]) {
19252 return C_RegisterClass;
19276 return TargetLowering::getConstraintType(Constraint);
19279 /// Examine constraint type and operand type and determine a weight value.
19280 /// This object must already have been set up with the operand type
19281 /// and the current alternative constraint selected.
19282 TargetLowering::ConstraintWeight
19283 X86TargetLowering::getSingleConstraintMatchWeight(
19284 AsmOperandInfo &info, const char *constraint) const {
19285 ConstraintWeight weight = CW_Invalid;
19286 Value *CallOperandVal = info.CallOperandVal;
19287 // If we don't have a value, we can't do a match,
19288 // but allow it at the lowest weight.
19289 if (CallOperandVal == NULL)
19291 Type *type = CallOperandVal->getType();
19292 // Look at the constraint type.
19293 switch (*constraint) {
19295 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
19306 if (CallOperandVal->getType()->isIntegerTy())
19307 weight = CW_SpecificReg;
19312 if (type->isFloatingPointTy())
19313 weight = CW_SpecificReg;
19316 if (type->isX86_MMXTy() && Subtarget->hasMMX())
19317 weight = CW_SpecificReg;
19321 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
19322 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
19323 weight = CW_Register;
19326 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
19327 if (C->getZExtValue() <= 31)
19328 weight = CW_Constant;
19332 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19333 if (C->getZExtValue() <= 63)
19334 weight = CW_Constant;
19338 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19339 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
19340 weight = CW_Constant;
19344 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19345 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
19346 weight = CW_Constant;
19350 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19351 if (C->getZExtValue() <= 3)
19352 weight = CW_Constant;
19356 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19357 if (C->getZExtValue() <= 0xff)
19358 weight = CW_Constant;
19363 if (dyn_cast<ConstantFP>(CallOperandVal)) {
19364 weight = CW_Constant;
19368 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19369 if ((C->getSExtValue() >= -0x80000000LL) &&
19370 (C->getSExtValue() <= 0x7fffffffLL))
19371 weight = CW_Constant;
19375 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
19376 if (C->getZExtValue() <= 0xffffffff)
19377 weight = CW_Constant;
19384 /// LowerXConstraint - try to replace an X constraint, which matches anything,
19385 /// with another that has more specific requirements based on the type of the
19386 /// corresponding operand.
19387 const char *X86TargetLowering::
19388 LowerXConstraint(EVT ConstraintVT) const {
19389 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
19390 // 'f' like normal targets.
19391 if (ConstraintVT.isFloatingPoint()) {
19392 if (Subtarget->hasSSE2())
19394 if (Subtarget->hasSSE1())
19398 return TargetLowering::LowerXConstraint(ConstraintVT);
19401 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
19402 /// vector. If it is invalid, don't add anything to Ops.
19403 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
19404 std::string &Constraint,
19405 std::vector<SDValue>&Ops,
19406 SelectionDAG &DAG) const {
19407 SDValue Result(0, 0);
19409 // Only support length 1 constraints for now.
19410 if (Constraint.length() > 1) return;
19412 char ConstraintLetter = Constraint[0];
19413 switch (ConstraintLetter) {
19416 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19417 if (C->getZExtValue() <= 31) {
19418 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19424 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19425 if (C->getZExtValue() <= 63) {
19426 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19432 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19433 if (isInt<8>(C->getSExtValue())) {
19434 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19441 if (C->getZExtValue() <= 255) {
19442 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19448 // 32-bit signed value
19449 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19450 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19451 C->getSExtValue())) {
19452 // Widen to 64 bits here to get it sign extended.
19453 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
19456 // FIXME gcc accepts some relocatable values here too, but only in certain
19457 // memory models; it's complicated.
19462 // 32-bit unsigned value
19463 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
19464 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
19465 C->getZExtValue())) {
19466 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
19470 // FIXME gcc accepts some relocatable values here too, but only in certain
19471 // memory models; it's complicated.
19475 // Literal immediates are always ok.
19476 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
19477 // Widen to 64 bits here to get it sign extended.
19478 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
19482 // In any sort of PIC mode addresses need to be computed at runtime by
19483 // adding in a register or some sort of table lookup. These can't
19484 // be used as immediates.
19485 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
19488 // If we are in non-pic codegen mode, we allow the address of a global (with
19489 // an optional displacement) to be used with 'i'.
19490 GlobalAddressSDNode *GA = 0;
19491 int64_t Offset = 0;
19493 // Match either (GA), (GA+C), (GA+C1+C2), etc.
19495 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
19496 Offset += GA->getOffset();
19498 } else if (Op.getOpcode() == ISD::ADD) {
19499 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19500 Offset += C->getZExtValue();
19501 Op = Op.getOperand(0);
19504 } else if (Op.getOpcode() == ISD::SUB) {
19505 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
19506 Offset += -C->getZExtValue();
19507 Op = Op.getOperand(0);
19512 // Otherwise, this isn't something we can handle, reject it.
19516 const GlobalValue *GV = GA->getGlobal();
19517 // If we require an extra load to get this address, as in PIC mode, we
19518 // can't accept it.
19519 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
19520 getTargetMachine())))
19523 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
19524 GA->getValueType(0), Offset);
19529 if (Result.getNode()) {
19530 Ops.push_back(Result);
19533 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
19536 std::pair<unsigned, const TargetRegisterClass*>
19537 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
19539 // First, see if this is a constraint that directly corresponds to an LLVM
19541 if (Constraint.size() == 1) {
19542 // GCC Constraint Letters
19543 switch (Constraint[0]) {
19545 // TODO: Slight differences here in allocation order and leaving
19546 // RIP in the class. Do they matter any more here than they do
19547 // in the normal allocation?
19548 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
19549 if (Subtarget->is64Bit()) {
19550 if (VT == MVT::i32 || VT == MVT::f32)
19551 return std::make_pair(0U, &X86::GR32RegClass);
19552 if (VT == MVT::i16)
19553 return std::make_pair(0U, &X86::GR16RegClass);
19554 if (VT == MVT::i8 || VT == MVT::i1)
19555 return std::make_pair(0U, &X86::GR8RegClass);
19556 if (VT == MVT::i64 || VT == MVT::f64)
19557 return std::make_pair(0U, &X86::GR64RegClass);
19560 // 32-bit fallthrough
19561 case 'Q': // Q_REGS
19562 if (VT == MVT::i32 || VT == MVT::f32)
19563 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
19564 if (VT == MVT::i16)
19565 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
19566 if (VT == MVT::i8 || VT == MVT::i1)
19567 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
19568 if (VT == MVT::i64)
19569 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
19571 case 'r': // GENERAL_REGS
19572 case 'l': // INDEX_REGS
19573 if (VT == MVT::i8 || VT == MVT::i1)
19574 return std::make_pair(0U, &X86::GR8RegClass);
19575 if (VT == MVT::i16)
19576 return std::make_pair(0U, &X86::GR16RegClass);
19577 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
19578 return std::make_pair(0U, &X86::GR32RegClass);
19579 return std::make_pair(0U, &X86::GR64RegClass);
19580 case 'R': // LEGACY_REGS
19581 if (VT == MVT::i8 || VT == MVT::i1)
19582 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
19583 if (VT == MVT::i16)
19584 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
19585 if (VT == MVT::i32 || !Subtarget->is64Bit())
19586 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
19587 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
19588 case 'f': // FP Stack registers.
19589 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
19590 // value to the correct fpstack register class.
19591 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
19592 return std::make_pair(0U, &X86::RFP32RegClass);
19593 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
19594 return std::make_pair(0U, &X86::RFP64RegClass);
19595 return std::make_pair(0U, &X86::RFP80RegClass);
19596 case 'y': // MMX_REGS if MMX allowed.
19597 if (!Subtarget->hasMMX()) break;
19598 return std::make_pair(0U, &X86::VR64RegClass);
19599 case 'Y': // SSE_REGS if SSE2 allowed
19600 if (!Subtarget->hasSSE2()) break;
19602 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
19603 if (!Subtarget->hasSSE1()) break;
19605 switch (VT.SimpleTy) {
19607 // Scalar SSE types.
19610 return std::make_pair(0U, &X86::FR32RegClass);
19613 return std::make_pair(0U, &X86::FR64RegClass);
19621 return std::make_pair(0U, &X86::VR128RegClass);
19629 return std::make_pair(0U, &X86::VR256RegClass);
19634 return std::make_pair(0U, &X86::VR512RegClass);
19640 // Use the default implementation in TargetLowering to convert the register
19641 // constraint into a member of a register class.
19642 std::pair<unsigned, const TargetRegisterClass*> Res;
19643 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
19645 // Not found as a standard register?
19646 if (Res.second == 0) {
19647 // Map st(0) -> st(7) -> ST0
19648 if (Constraint.size() == 7 && Constraint[0] == '{' &&
19649 tolower(Constraint[1]) == 's' &&
19650 tolower(Constraint[2]) == 't' &&
19651 Constraint[3] == '(' &&
19652 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
19653 Constraint[5] == ')' &&
19654 Constraint[6] == '}') {
19656 Res.first = X86::ST0+Constraint[4]-'0';
19657 Res.second = &X86::RFP80RegClass;
19661 // GCC allows "st(0)" to be called just plain "st".
19662 if (StringRef("{st}").equals_lower(Constraint)) {
19663 Res.first = X86::ST0;
19664 Res.second = &X86::RFP80RegClass;
19669 if (StringRef("{flags}").equals_lower(Constraint)) {
19670 Res.first = X86::EFLAGS;
19671 Res.second = &X86::CCRRegClass;
19675 // 'A' means EAX + EDX.
19676 if (Constraint == "A") {
19677 Res.first = X86::EAX;
19678 Res.second = &X86::GR32_ADRegClass;
19684 // Otherwise, check to see if this is a register class of the wrong value
19685 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
19686 // turn into {ax},{dx}.
19687 if (Res.second->hasType(VT))
19688 return Res; // Correct type already, nothing to do.
19690 // All of the single-register GCC register classes map their values onto
19691 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
19692 // really want an 8-bit or 32-bit register, map to the appropriate register
19693 // class and return the appropriate register.
19694 if (Res.second == &X86::GR16RegClass) {
19695 if (VT == MVT::i8 || VT == MVT::i1) {
19696 unsigned DestReg = 0;
19697 switch (Res.first) {
19699 case X86::AX: DestReg = X86::AL; break;
19700 case X86::DX: DestReg = X86::DL; break;
19701 case X86::CX: DestReg = X86::CL; break;
19702 case X86::BX: DestReg = X86::BL; break;
19705 Res.first = DestReg;
19706 Res.second = &X86::GR8RegClass;
19708 } else if (VT == MVT::i32 || VT == MVT::f32) {
19709 unsigned DestReg = 0;
19710 switch (Res.first) {
19712 case X86::AX: DestReg = X86::EAX; break;
19713 case X86::DX: DestReg = X86::EDX; break;
19714 case X86::CX: DestReg = X86::ECX; break;
19715 case X86::BX: DestReg = X86::EBX; break;
19716 case X86::SI: DestReg = X86::ESI; break;
19717 case X86::DI: DestReg = X86::EDI; break;
19718 case X86::BP: DestReg = X86::EBP; break;
19719 case X86::SP: DestReg = X86::ESP; break;
19722 Res.first = DestReg;
19723 Res.second = &X86::GR32RegClass;
19725 } else if (VT == MVT::i64 || VT == MVT::f64) {
19726 unsigned DestReg = 0;
19727 switch (Res.first) {
19729 case X86::AX: DestReg = X86::RAX; break;
19730 case X86::DX: DestReg = X86::RDX; break;
19731 case X86::CX: DestReg = X86::RCX; break;
19732 case X86::BX: DestReg = X86::RBX; break;
19733 case X86::SI: DestReg = X86::RSI; break;
19734 case X86::DI: DestReg = X86::RDI; break;
19735 case X86::BP: DestReg = X86::RBP; break;
19736 case X86::SP: DestReg = X86::RSP; break;
19739 Res.first = DestReg;
19740 Res.second = &X86::GR64RegClass;
19743 } else if (Res.second == &X86::FR32RegClass ||
19744 Res.second == &X86::FR64RegClass ||
19745 Res.second == &X86::VR128RegClass ||
19746 Res.second == &X86::VR256RegClass ||
19747 Res.second == &X86::FR32XRegClass ||
19748 Res.second == &X86::FR64XRegClass ||
19749 Res.second == &X86::VR128XRegClass ||
19750 Res.second == &X86::VR256XRegClass ||
19751 Res.second == &X86::VR512RegClass) {
19752 // Handle references to XMM physical registers that got mapped into the
19753 // wrong class. This can happen with constraints like {xmm0} where the
19754 // target independent register mapper will just pick the first match it can
19755 // find, ignoring the required type.
19757 if (VT == MVT::f32 || VT == MVT::i32)
19758 Res.second = &X86::FR32RegClass;
19759 else if (VT == MVT::f64 || VT == MVT::i64)
19760 Res.second = &X86::FR64RegClass;
19761 else if (X86::VR128RegClass.hasType(VT))
19762 Res.second = &X86::VR128RegClass;
19763 else if (X86::VR256RegClass.hasType(VT))
19764 Res.second = &X86::VR256RegClass;
19765 else if (X86::VR512RegClass.hasType(VT))
19766 Res.second = &X86::VR512RegClass;