1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/LibCallSemantics.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
427 if (Subtarget->is64Bit()) {
428 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
432 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
433 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
434 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
435 // support continuation, user-level threading, and etc.. As a result, no
436 // other SjLj exception interfaces are implemented and please don't build
437 // your own exception handling based on them.
438 // LLVM/Clang supports zero-cost DWARF exception handling.
439 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
440 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
443 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
449 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
455 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
456 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
458 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
459 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
468 if (Subtarget->hasSSE1())
469 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
471 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
473 // Expand certain atomics
474 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
475 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
480 if (Subtarget->hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
484 // FIXME - use subtarget debug flags
485 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
486 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
487 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
494 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
497 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
500 setOperationAction(ISD::VASTART , MVT::Other, Custom);
501 setOperationAction(ISD::VAEND , MVT::Other, Expand);
502 if (Subtarget->is64Bit()) {
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
835 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
836 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
837 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
839 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
840 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
841 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
845 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
853 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
858 // ISD::CTTZ v2i64 - scalarization is faster.
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
861 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
862 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
866 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
867 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
868 setOperationAction(ISD::VSELECT, VT, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
872 // We support custom legalizing of sext and anyext loads for specific
873 // memory vector types which we can load as a scalar (or sequence of
874 // scalars) and extend in-register to a legal 128-bit vector type. For sext
875 // loads these must work with a single scalar load.
876 for (MVT VT : MVT::integer_vector_valuetypes()) {
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
902 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (Subtarget->hasXOP()) {
1042 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1048 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1049 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1052 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1091 // even though v8i16 is a legal type.
1092 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1093 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1098 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 for (MVT VT : MVT::fp_vector_valuetypes())
1104 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1124 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1127 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1130 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1133 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1137 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1146 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1151 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1152 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1155 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1156 setOperationAction(ISD::FMA, MVT::f32, Legal);
1157 setOperationAction(ISD::FMA, MVT::f64, Legal);
1160 if (Subtarget->hasInt256()) {
1161 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1179 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1184 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1187 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1190 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1194 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1195 // when we have a 256bit-wide blend with immediate.
1196 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1198 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1231 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1234 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1237 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1242 // In the customized shift lowering, the legal cases in AVX2 will be
1244 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1248 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1253 // Custom lower several nodes for 256-bit types.
1254 for (MVT VT : MVT::vector_valuetypes()) {
1255 if (VT.getScalarSizeInBits() >= 32) {
1256 setOperationAction(ISD::MLOAD, VT, Legal);
1257 setOperationAction(ISD::MSTORE, VT, Legal);
1259 // Extract subvector is special because the value type
1260 // (result) is 128-bit but the source is 256-bit wide.
1261 if (VT.is128BitVector()) {
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1264 // Do not attempt to custom lower other non-256-bit vectors
1265 if (!VT.is256BitVector())
1268 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1270 setOperationAction(ISD::VSELECT, VT, Custom);
1271 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1272 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1274 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1275 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1278 if (Subtarget->hasInt256())
1279 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1283 setOperationAction(ISD::AND, VT, Promote);
1284 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1285 setOperationAction(ISD::OR, VT, Promote);
1286 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1287 setOperationAction(ISD::XOR, VT, Promote);
1288 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1289 setOperationAction(ISD::LOAD, VT, Promote);
1290 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1291 setOperationAction(ISD::SELECT, VT, Promote);
1292 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1296 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1297 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1298 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1299 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1300 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1302 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1303 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1304 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1306 for (MVT VT : MVT::fp_vector_valuetypes())
1307 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1317 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1319 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1320 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1322 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1323 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1325 setOperationAction(ISD::XOR, MVT::i1, Legal);
1326 setOperationAction(ISD::OR, MVT::i1, Legal);
1327 setOperationAction(ISD::AND, MVT::i1, Legal);
1328 setOperationAction(ISD::SUB, MVT::i1, Custom);
1329 setOperationAction(ISD::ADD, MVT::i1, Custom);
1330 setOperationAction(ISD::MUL, MVT::i1, Custom);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1344 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1350 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1359 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1361 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1363 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1365 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1366 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1367 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1368 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1370 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1371 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1372 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1373 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1374 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1375 if (Subtarget->hasVLX()){
1376 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1377 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1378 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1379 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1380 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1382 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1383 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1384 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1385 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1386 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1388 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1392 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1393 if (Subtarget->hasDQI()) {
1394 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1397 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1398 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1401 if (Subtarget->hasVLX()) {
1402 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1412 if (Subtarget->hasVLX()) {
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1419 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1422 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1423 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1425 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1428 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1434 if (Subtarget->hasDQI()) {
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1438 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1444 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1450 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1451 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1452 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1453 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1458 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1462 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1463 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1464 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1465 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1467 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1469 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1472 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1476 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1477 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1478 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1479 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1481 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1482 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1484 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1485 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1487 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1489 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1490 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1492 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1495 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1498 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1499 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1500 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1501 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1502 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1503 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1505 if (Subtarget->hasCDI()) {
1506 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1511 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1516 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1517 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1520 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1521 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1523 if (Subtarget->hasVLX()) {
1524 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1530 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1531 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1534 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1535 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1536 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1542 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1543 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1544 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1545 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1547 } // Subtarget->hasCDI()
1549 if (Subtarget->hasDQI()) {
1550 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1551 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1552 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1554 // Custom lower several nodes.
1555 for (MVT VT : MVT::vector_valuetypes()) {
1556 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1558 setOperationAction(ISD::AND, VT, Legal);
1559 setOperationAction(ISD::OR, VT, Legal);
1560 setOperationAction(ISD::XOR, VT, Legal);
1562 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1563 setOperationAction(ISD::MGATHER, VT, Custom);
1564 setOperationAction(ISD::MSCATTER, VT, Custom);
1566 // Extract subvector is special because the value type
1567 // (result) is 256/128-bit but the source is 512-bit wide.
1568 if (VT.is128BitVector() || VT.is256BitVector()) {
1569 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1571 if (VT.getVectorElementType() == MVT::i1)
1572 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1574 // Do not attempt to custom lower other non-512-bit vectors
1575 if (!VT.is512BitVector())
1578 if (EltSize >= 32) {
1579 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1580 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1581 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1582 setOperationAction(ISD::VSELECT, VT, Legal);
1583 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1584 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1585 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1586 setOperationAction(ISD::MLOAD, VT, Legal);
1587 setOperationAction(ISD::MSTORE, VT, Legal);
1590 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1591 setOperationAction(ISD::SELECT, VT, Promote);
1592 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1596 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1597 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1598 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1600 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1601 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1603 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1606 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1607 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1608 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1609 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1610 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1611 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1612 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1613 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1614 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1615 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1616 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1617 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1618 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1619 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1620 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1621 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1622 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1623 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1624 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1625 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1626 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1627 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1630 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1631 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1632 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1633 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1635 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1636 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1637 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1638 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1639 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1640 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1641 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1646 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1650 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1651 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1652 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1653 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1655 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1656 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1657 if (Subtarget->hasVLX())
1658 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1660 if (Subtarget->hasCDI()) {
1661 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1662 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1663 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1664 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1667 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1668 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1669 setOperationAction(ISD::VSELECT, VT, Legal);
1673 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1674 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1675 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1677 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1678 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1679 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1680 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1681 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1682 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1683 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1684 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1685 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1686 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1690 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1691 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1692 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1693 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1694 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1695 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1696 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1697 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1699 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1703 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1704 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1705 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1706 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1709 // We want to custom lower some of our intrinsics.
1710 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1711 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1712 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1713 if (!Subtarget->is64Bit())
1714 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1716 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1717 // handle type legalization for these operations here.
1719 // FIXME: We really should do custom legalization for addition and
1720 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1721 // than generic legalization for 64-bit multiplication-with-overflow, though.
1722 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1723 if (VT == MVT::i64 && !Subtarget->is64Bit())
1725 // Add/Sub/Mul with overflow operations are custom lowered.
1726 setOperationAction(ISD::SADDO, VT, Custom);
1727 setOperationAction(ISD::UADDO, VT, Custom);
1728 setOperationAction(ISD::SSUBO, VT, Custom);
1729 setOperationAction(ISD::USUBO, VT, Custom);
1730 setOperationAction(ISD::SMULO, VT, Custom);
1731 setOperationAction(ISD::UMULO, VT, Custom);
1734 if (!Subtarget->is64Bit()) {
1735 // These libcalls are not available in 32-bit.
1736 setLibcallName(RTLIB::SHL_I128, nullptr);
1737 setLibcallName(RTLIB::SRL_I128, nullptr);
1738 setLibcallName(RTLIB::SRA_I128, nullptr);
1741 // Combine sin / cos into one node or libcall if possible.
1742 if (Subtarget->hasSinCos()) {
1743 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1744 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1745 if (Subtarget->isTargetDarwin()) {
1746 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1747 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1748 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1749 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1753 if (Subtarget->isTargetWin64()) {
1754 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1755 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1756 setOperationAction(ISD::SREM, MVT::i128, Custom);
1757 setOperationAction(ISD::UREM, MVT::i128, Custom);
1758 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1759 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1762 // We have target-specific dag combine patterns for the following nodes:
1763 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1764 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1765 setTargetDAGCombine(ISD::BITCAST);
1766 setTargetDAGCombine(ISD::VSELECT);
1767 setTargetDAGCombine(ISD::SELECT);
1768 setTargetDAGCombine(ISD::SHL);
1769 setTargetDAGCombine(ISD::SRA);
1770 setTargetDAGCombine(ISD::SRL);
1771 setTargetDAGCombine(ISD::OR);
1772 setTargetDAGCombine(ISD::AND);
1773 setTargetDAGCombine(ISD::ADD);
1774 setTargetDAGCombine(ISD::FADD);
1775 setTargetDAGCombine(ISD::FSUB);
1776 setTargetDAGCombine(ISD::FMA);
1777 setTargetDAGCombine(ISD::SUB);
1778 setTargetDAGCombine(ISD::LOAD);
1779 setTargetDAGCombine(ISD::MLOAD);
1780 setTargetDAGCombine(ISD::STORE);
1781 setTargetDAGCombine(ISD::MSTORE);
1782 setTargetDAGCombine(ISD::TRUNCATE);
1783 setTargetDAGCombine(ISD::ZERO_EXTEND);
1784 setTargetDAGCombine(ISD::ANY_EXTEND);
1785 setTargetDAGCombine(ISD::SIGN_EXTEND);
1786 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1787 setTargetDAGCombine(ISD::SINT_TO_FP);
1788 setTargetDAGCombine(ISD::UINT_TO_FP);
1789 setTargetDAGCombine(ISD::SETCC);
1790 setTargetDAGCombine(ISD::BUILD_VECTOR);
1791 setTargetDAGCombine(ISD::MUL);
1792 setTargetDAGCombine(ISD::XOR);
1794 computeRegisterProperties(Subtarget->getRegisterInfo());
1796 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1797 MaxStoresPerMemsetOptSize = 8;
1798 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1799 MaxStoresPerMemcpyOptSize = 4;
1800 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1801 MaxStoresPerMemmoveOptSize = 4;
1802 setPrefLoopAlignment(4); // 2^4 bytes.
1804 // A predictable cmov does not hurt on an in-order CPU.
1805 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1806 PredictableSelectIsExpensive = !Subtarget->isAtom();
1807 EnableExtLdPromotion = true;
1808 setPrefFunctionAlignment(4); // 2^4 bytes.
1810 verifyIntrinsicTables();
1813 // This has so far only been implemented for 64-bit MachO.
1814 bool X86TargetLowering::useLoadStackGuardNode() const {
1815 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1818 TargetLoweringBase::LegalizeTypeAction
1819 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1820 if (ExperimentalVectorWideningLegalization &&
1821 VT.getVectorNumElements() != 1 &&
1822 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1823 return TypeWidenVector;
1825 return TargetLoweringBase::getPreferredVectorAction(VT);
1828 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1831 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1833 if (VT.isSimple()) {
1834 MVT VVT = VT.getSimpleVT();
1835 const unsigned NumElts = VVT.getVectorNumElements();
1836 const MVT EltVT = VVT.getVectorElementType();
1837 if (VVT.is512BitVector()) {
1838 if (Subtarget->hasAVX512())
1839 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1840 EltVT == MVT::f32 || EltVT == MVT::f64)
1842 case 8: return MVT::v8i1;
1843 case 16: return MVT::v16i1;
1845 if (Subtarget->hasBWI())
1846 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1848 case 32: return MVT::v32i1;
1849 case 64: return MVT::v64i1;
1853 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1854 if (Subtarget->hasVLX())
1855 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1856 EltVT == MVT::f32 || EltVT == MVT::f64)
1858 case 2: return MVT::v2i1;
1859 case 4: return MVT::v4i1;
1860 case 8: return MVT::v8i1;
1862 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1863 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1865 case 8: return MVT::v8i1;
1866 case 16: return MVT::v16i1;
1867 case 32: return MVT::v32i1;
1872 return VT.changeVectorElementTypeToInteger();
1875 /// Helper for getByValTypeAlignment to determine
1876 /// the desired ByVal argument alignment.
1877 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1880 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1881 if (VTy->getBitWidth() == 128)
1883 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1884 unsigned EltAlign = 0;
1885 getMaxByValAlign(ATy->getElementType(), EltAlign);
1886 if (EltAlign > MaxAlign)
1887 MaxAlign = EltAlign;
1888 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1889 for (auto *EltTy : STy->elements()) {
1890 unsigned EltAlign = 0;
1891 getMaxByValAlign(EltTy, EltAlign);
1892 if (EltAlign > MaxAlign)
1893 MaxAlign = EltAlign;
1900 /// Return the desired alignment for ByVal aggregate
1901 /// function arguments in the caller parameter area. For X86, aggregates
1902 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1903 /// are at 4-byte boundaries.
1904 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1905 const DataLayout &DL) const {
1906 if (Subtarget->is64Bit()) {
1907 // Max of 8 and alignment of type.
1908 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1915 if (Subtarget->hasSSE1())
1916 getMaxByValAlign(Ty, Align);
1920 /// Returns the target specific optimal type for load
1921 /// and store operations as a result of memset, memcpy, and memmove
1922 /// lowering. If DstAlign is zero that means it's safe to destination
1923 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1924 /// means there isn't a need to check it against alignment requirement,
1925 /// probably because the source does not need to be loaded. If 'IsMemset' is
1926 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1927 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1928 /// source is constant so it does not need to be loaded.
1929 /// It returns EVT::Other if the type should be determined using generic
1930 /// target-independent logic.
1932 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1933 unsigned DstAlign, unsigned SrcAlign,
1934 bool IsMemset, bool ZeroMemset,
1936 MachineFunction &MF) const {
1937 const Function *F = MF.getFunction();
1938 if ((!IsMemset || ZeroMemset) &&
1939 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1941 (!Subtarget->isUnalignedMem16Slow() ||
1942 ((DstAlign == 0 || DstAlign >= 16) &&
1943 (SrcAlign == 0 || SrcAlign >= 16)))) {
1945 // FIXME: Check if unaligned 32-byte accesses are slow.
1946 if (Subtarget->hasInt256())
1948 if (Subtarget->hasFp256())
1951 if (Subtarget->hasSSE2())
1953 if (Subtarget->hasSSE1())
1955 } else if (!MemcpyStrSrc && Size >= 8 &&
1956 !Subtarget->is64Bit() &&
1957 Subtarget->hasSSE2()) {
1958 // Do not use f64 to lower memcpy if source is string constant. It's
1959 // better to use i32 to avoid the loads.
1963 // This is a compromise. If we reach here, unaligned accesses may be slow on
1964 // this target. However, creating smaller, aligned accesses could be even
1965 // slower and would certainly be a lot more code.
1966 if (Subtarget->is64Bit() && Size >= 8)
1971 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1973 return X86ScalarSSEf32;
1974 else if (VT == MVT::f64)
1975 return X86ScalarSSEf64;
1980 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1985 switch (VT.getSizeInBits()) {
1987 // 8-byte and under are always assumed to be fast.
1991 *Fast = !Subtarget->isUnalignedMem16Slow();
1994 *Fast = !Subtarget->isUnalignedMem32Slow();
1996 // TODO: What about AVX-512 (512-bit) accesses?
1999 // Misaligned accesses of any size are always allowed.
2003 /// Return the entry encoding for a jump table in the
2004 /// current function. The returned value is a member of the
2005 /// MachineJumpTableInfo::JTEntryKind enum.
2006 unsigned X86TargetLowering::getJumpTableEncoding() const {
2007 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2009 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2010 Subtarget->isPICStyleGOT())
2011 return MachineJumpTableInfo::EK_Custom32;
2013 // Otherwise, use the normal jump table encoding heuristics.
2014 return TargetLowering::getJumpTableEncoding();
2017 bool X86TargetLowering::useSoftFloat() const {
2018 return Subtarget->useSoftFloat();
2022 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2023 const MachineBasicBlock *MBB,
2024 unsigned uid,MCContext &Ctx) const{
2025 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2026 Subtarget->isPICStyleGOT());
2027 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2029 return MCSymbolRefExpr::create(MBB->getSymbol(),
2030 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2033 /// Returns relocation base for the given PIC jumptable.
2034 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2035 SelectionDAG &DAG) const {
2036 if (!Subtarget->is64Bit())
2037 // This doesn't have SDLoc associated with it, but is not really the
2038 // same as a Register.
2039 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2040 getPointerTy(DAG.getDataLayout()));
2044 /// This returns the relocation base for the given PIC jumptable,
2045 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2046 const MCExpr *X86TargetLowering::
2047 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2048 MCContext &Ctx) const {
2049 // X86-64 uses RIP relative addressing based on the jump table label.
2050 if (Subtarget->isPICStyleRIPRel())
2051 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2053 // Otherwise, the reference is relative to the PIC base.
2054 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2057 std::pair<const TargetRegisterClass *, uint8_t>
2058 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2060 const TargetRegisterClass *RRC = nullptr;
2062 switch (VT.SimpleTy) {
2064 return TargetLowering::findRepresentativeClass(TRI, VT);
2065 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2066 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2069 RRC = &X86::VR64RegClass;
2071 case MVT::f32: case MVT::f64:
2072 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2073 case MVT::v4f32: case MVT::v2f64:
2074 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2076 RRC = &X86::VR128RegClass;
2079 return std::make_pair(RRC, Cost);
2082 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2083 unsigned &Offset) const {
2084 if (!Subtarget->isTargetLinux())
2087 if (Subtarget->is64Bit()) {
2088 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2090 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2102 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2103 if (!Subtarget->isTargetAndroid())
2104 return TargetLowering::getSafeStackPointerLocation(IRB);
2106 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2107 // definition of TLS_SLOT_SAFESTACK in
2108 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2109 unsigned AddressSpace, Offset;
2110 if (Subtarget->is64Bit()) {
2111 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2113 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2123 return ConstantExpr::getIntToPtr(
2124 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2125 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2128 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2129 unsigned DestAS) const {
2130 assert(SrcAS != DestAS && "Expected different address spaces!");
2132 return SrcAS < 256 && DestAS < 256;
2135 //===----------------------------------------------------------------------===//
2136 // Return Value Calling Convention Implementation
2137 //===----------------------------------------------------------------------===//
2139 #include "X86GenCallingConv.inc"
2141 bool X86TargetLowering::CanLowerReturn(
2142 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2143 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2144 SmallVector<CCValAssign, 16> RVLocs;
2145 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2146 return CCInfo.CheckReturn(Outs, RetCC_X86);
2149 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2150 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2155 X86TargetLowering::LowerReturn(SDValue Chain,
2156 CallingConv::ID CallConv, bool isVarArg,
2157 const SmallVectorImpl<ISD::OutputArg> &Outs,
2158 const SmallVectorImpl<SDValue> &OutVals,
2159 SDLoc dl, SelectionDAG &DAG) const {
2160 MachineFunction &MF = DAG.getMachineFunction();
2161 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2163 SmallVector<CCValAssign, 16> RVLocs;
2164 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2165 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2168 SmallVector<SDValue, 6> RetOps;
2169 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2170 // Operand #1 = Bytes To Pop
2171 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2174 // Copy the result values into the output registers.
2175 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2176 CCValAssign &VA = RVLocs[i];
2177 assert(VA.isRegLoc() && "Can only return in registers!");
2178 SDValue ValToCopy = OutVals[i];
2179 EVT ValVT = ValToCopy.getValueType();
2181 // Promote values to the appropriate types.
2182 if (VA.getLocInfo() == CCValAssign::SExt)
2183 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2184 else if (VA.getLocInfo() == CCValAssign::ZExt)
2185 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2186 else if (VA.getLocInfo() == CCValAssign::AExt) {
2187 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2188 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2190 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2192 else if (VA.getLocInfo() == CCValAssign::BCvt)
2193 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2195 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2196 "Unexpected FP-extend for return value.");
2198 // If this is x86-64, and we disabled SSE, we can't return FP values,
2199 // or SSE or MMX vectors.
2200 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2201 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2202 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2203 report_fatal_error("SSE register return with SSE disabled");
2205 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2206 // llvm-gcc has never done it right and no one has noticed, so this
2207 // should be OK for now.
2208 if (ValVT == MVT::f64 &&
2209 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2210 report_fatal_error("SSE2 register return with SSE2 disabled");
2212 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2213 // the RET instruction and handled by the FP Stackifier.
2214 if (VA.getLocReg() == X86::FP0 ||
2215 VA.getLocReg() == X86::FP1) {
2216 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2217 // change the value to the FP stack register class.
2218 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2219 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2220 RetOps.push_back(ValToCopy);
2221 // Don't emit a copytoreg.
2225 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2226 // which is returned in RAX / RDX.
2227 if (Subtarget->is64Bit()) {
2228 if (ValVT == MVT::x86mmx) {
2229 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2230 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2231 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2233 // If we don't have SSE2 available, convert to v4f32 so the generated
2234 // register is legal.
2235 if (!Subtarget->hasSSE2())
2236 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2241 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2242 Flag = Chain.getValue(1);
2243 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2246 // All x86 ABIs require that for returning structs by value we copy
2247 // the sret argument into %rax/%eax (depending on ABI) for the return.
2248 // We saved the argument into a virtual register in the entry block,
2249 // so now we copy the value out and into %rax/%eax.
2251 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2252 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2253 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2254 // either case FuncInfo->setSRetReturnReg() will have been called.
2255 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2256 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2257 getPointerTy(MF.getDataLayout()));
2260 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2261 X86::RAX : X86::EAX;
2262 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2263 Flag = Chain.getValue(1);
2265 // RAX/EAX now acts like a return value.
2267 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2270 RetOps[0] = Chain; // Update chain.
2272 // Add the flag if we have it.
2274 RetOps.push_back(Flag);
2276 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2279 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2280 if (N->getNumValues() != 1)
2282 if (!N->hasNUsesOfValue(1, 0))
2285 SDValue TCChain = Chain;
2286 SDNode *Copy = *N->use_begin();
2287 if (Copy->getOpcode() == ISD::CopyToReg) {
2288 // If the copy has a glue operand, we conservatively assume it isn't safe to
2289 // perform a tail call.
2290 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2292 TCChain = Copy->getOperand(0);
2293 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2296 bool HasRet = false;
2297 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2299 if (UI->getOpcode() != X86ISD::RET_FLAG)
2301 // If we are returning more than one value, we can definitely
2302 // not make a tail call see PR19530
2303 if (UI->getNumOperands() > 4)
2305 if (UI->getNumOperands() == 4 &&
2306 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2319 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2320 ISD::NodeType ExtendKind) const {
2322 // TODO: Is this also valid on 32-bit?
2323 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2324 ReturnMVT = MVT::i8;
2326 ReturnMVT = MVT::i32;
2328 EVT MinVT = getRegisterType(Context, ReturnMVT);
2329 return VT.bitsLT(MinVT) ? MinVT : VT;
2332 /// Lower the result values of a call into the
2333 /// appropriate copies out of appropriate physical registers.
2336 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2337 CallingConv::ID CallConv, bool isVarArg,
2338 const SmallVectorImpl<ISD::InputArg> &Ins,
2339 SDLoc dl, SelectionDAG &DAG,
2340 SmallVectorImpl<SDValue> &InVals) const {
2342 // Assign locations to each value returned by this call.
2343 SmallVector<CCValAssign, 16> RVLocs;
2344 bool Is64Bit = Subtarget->is64Bit();
2345 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2347 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2349 // Copy all of the result registers out of their specified physreg.
2350 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2351 CCValAssign &VA = RVLocs[i];
2352 EVT CopyVT = VA.getLocVT();
2354 // If this is x86-64, and we disabled SSE, we can't return FP values
2355 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2356 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2357 report_fatal_error("SSE register return with SSE disabled");
2360 // If we prefer to use the value in xmm registers, copy it out as f80 and
2361 // use a truncate to move it from fp stack reg to xmm reg.
2362 bool RoundAfterCopy = false;
2363 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2364 isScalarFPTypeInSSEReg(VA.getValVT())) {
2366 RoundAfterCopy = (CopyVT != VA.getLocVT());
2369 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2370 CopyVT, InFlag).getValue(1);
2371 SDValue Val = Chain.getValue(0);
2374 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2375 // This truncation won't change the value.
2376 DAG.getIntPtrConstant(1, dl));
2378 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2379 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2381 InFlag = Chain.getValue(2);
2382 InVals.push_back(Val);
2388 //===----------------------------------------------------------------------===//
2389 // C & StdCall & Fast Calling Convention implementation
2390 //===----------------------------------------------------------------------===//
2391 // StdCall calling convention seems to be standard for many Windows' API
2392 // routines and around. It differs from C calling convention just a little:
2393 // callee should clean up the stack, not caller. Symbols should be also
2394 // decorated in some fancy way :) It doesn't support any vector arguments.
2395 // For info on fast calling convention see Fast Calling Convention (tail call)
2396 // implementation LowerX86_32FastCCCallTo.
2398 /// CallIsStructReturn - Determines whether a call uses struct return
2400 enum StructReturnType {
2405 static StructReturnType
2406 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2408 return NotStructReturn;
2410 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2411 if (!Flags.isSRet())
2412 return NotStructReturn;
2413 if (Flags.isInReg())
2414 return RegStructReturn;
2415 return StackStructReturn;
2418 /// Determines whether a function uses struct return semantics.
2419 static StructReturnType
2420 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2422 return NotStructReturn;
2424 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2425 if (!Flags.isSRet())
2426 return NotStructReturn;
2427 if (Flags.isInReg())
2428 return RegStructReturn;
2429 return StackStructReturn;
2432 /// Make a copy of an aggregate at address specified by "Src" to address
2433 /// "Dst" with size and alignment information specified by the specific
2434 /// parameter attribute. The copy will be passed as a byval function parameter.
2436 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2437 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2439 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2441 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2442 /*isVolatile*/false, /*AlwaysInline=*/true,
2443 /*isTailCall*/false,
2444 MachinePointerInfo(), MachinePointerInfo());
2447 /// Return true if the calling convention is one that we can guarantee TCO for.
2448 static bool canGuaranteeTCO(CallingConv::ID CC) {
2449 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2450 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2453 /// Return true if we might ever do TCO for calls with this calling convention.
2454 static bool mayTailCallThisCC(CallingConv::ID CC) {
2456 // C calling conventions:
2457 case CallingConv::C:
2458 case CallingConv::X86_64_Win64:
2459 case CallingConv::X86_64_SysV:
2460 // Callee pop conventions:
2461 case CallingConv::X86_ThisCall:
2462 case CallingConv::X86_StdCall:
2463 case CallingConv::X86_VectorCall:
2464 case CallingConv::X86_FastCall:
2467 return canGuaranteeTCO(CC);
2471 /// Return true if the function is being made into a tailcall target by
2472 /// changing its ABI.
2473 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2474 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2477 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2479 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2480 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2484 CallingConv::ID CalleeCC = CS.getCallingConv();
2485 if (!mayTailCallThisCC(CalleeCC))
2492 X86TargetLowering::LowerMemArgument(SDValue Chain,
2493 CallingConv::ID CallConv,
2494 const SmallVectorImpl<ISD::InputArg> &Ins,
2495 SDLoc dl, SelectionDAG &DAG,
2496 const CCValAssign &VA,
2497 MachineFrameInfo *MFI,
2499 // Create the nodes corresponding to a load from this parameter slot.
2500 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2501 bool AlwaysUseMutable = shouldGuaranteeTCO(
2502 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2503 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2506 // If value is passed by pointer we have address passed instead of the value
2508 bool ExtendedInMem = VA.isExtInLoc() &&
2509 VA.getValVT().getScalarType() == MVT::i1;
2511 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2512 ValVT = VA.getLocVT();
2514 ValVT = VA.getValVT();
2516 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2517 // changed with more analysis.
2518 // In case of tail call optimization mark all arguments mutable. Since they
2519 // could be overwritten by lowering of arguments in case of a tail call.
2520 if (Flags.isByVal()) {
2521 unsigned Bytes = Flags.getByValSize();
2522 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2523 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2524 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2526 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2527 VA.getLocMemOffset(), isImmutable);
2528 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2529 SDValue Val = DAG.getLoad(
2530 ValVT, dl, Chain, FIN,
2531 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2533 return ExtendedInMem ?
2534 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2538 // FIXME: Get this from tablegen.
2539 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2540 const X86Subtarget *Subtarget) {
2541 assert(Subtarget->is64Bit());
2543 if (Subtarget->isCallingConvWin64(CallConv)) {
2544 static const MCPhysReg GPR64ArgRegsWin64[] = {
2545 X86::RCX, X86::RDX, X86::R8, X86::R9
2547 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2550 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2551 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2553 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2556 // FIXME: Get this from tablegen.
2557 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2558 CallingConv::ID CallConv,
2559 const X86Subtarget *Subtarget) {
2560 assert(Subtarget->is64Bit());
2561 if (Subtarget->isCallingConvWin64(CallConv)) {
2562 // The XMM registers which might contain var arg parameters are shadowed
2563 // in their paired GPR. So we only need to save the GPR to their home
2565 // TODO: __vectorcall will change this.
2569 const Function *Fn = MF.getFunction();
2570 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2571 bool isSoftFloat = Subtarget->useSoftFloat();
2572 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2573 "SSE register cannot be used when SSE is disabled!");
2574 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2575 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2579 static const MCPhysReg XMMArgRegs64Bit[] = {
2580 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2581 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2583 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2586 SDValue X86TargetLowering::LowerFormalArguments(
2587 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2588 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2589 SmallVectorImpl<SDValue> &InVals) const {
2590 MachineFunction &MF = DAG.getMachineFunction();
2591 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2592 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2594 const Function* Fn = MF.getFunction();
2595 if (Fn->hasExternalLinkage() &&
2596 Subtarget->isTargetCygMing() &&
2597 Fn->getName() == "main")
2598 FuncInfo->setForceFramePointer(true);
2600 MachineFrameInfo *MFI = MF.getFrameInfo();
2601 bool Is64Bit = Subtarget->is64Bit();
2602 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2604 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2605 "Var args not supported with calling convention fastcc, ghc or hipe");
2607 // Assign locations to all of the incoming arguments.
2608 SmallVector<CCValAssign, 16> ArgLocs;
2609 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2611 // Allocate shadow area for Win64
2613 CCInfo.AllocateStack(32, 8);
2615 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2617 unsigned LastVal = ~0U;
2619 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2620 CCValAssign &VA = ArgLocs[i];
2621 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2623 assert(VA.getValNo() != LastVal &&
2624 "Don't support value assigned to multiple locs yet");
2626 LastVal = VA.getValNo();
2628 if (VA.isRegLoc()) {
2629 EVT RegVT = VA.getLocVT();
2630 const TargetRegisterClass *RC;
2631 if (RegVT == MVT::i32)
2632 RC = &X86::GR32RegClass;
2633 else if (Is64Bit && RegVT == MVT::i64)
2634 RC = &X86::GR64RegClass;
2635 else if (RegVT == MVT::f32)
2636 RC = &X86::FR32RegClass;
2637 else if (RegVT == MVT::f64)
2638 RC = &X86::FR64RegClass;
2639 else if (RegVT.is512BitVector())
2640 RC = &X86::VR512RegClass;
2641 else if (RegVT.is256BitVector())
2642 RC = &X86::VR256RegClass;
2643 else if (RegVT.is128BitVector())
2644 RC = &X86::VR128RegClass;
2645 else if (RegVT == MVT::x86mmx)
2646 RC = &X86::VR64RegClass;
2647 else if (RegVT == MVT::i1)
2648 RC = &X86::VK1RegClass;
2649 else if (RegVT == MVT::v8i1)
2650 RC = &X86::VK8RegClass;
2651 else if (RegVT == MVT::v16i1)
2652 RC = &X86::VK16RegClass;
2653 else if (RegVT == MVT::v32i1)
2654 RC = &X86::VK32RegClass;
2655 else if (RegVT == MVT::v64i1)
2656 RC = &X86::VK64RegClass;
2658 llvm_unreachable("Unknown argument type!");
2660 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2661 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2663 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2664 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2666 if (VA.getLocInfo() == CCValAssign::SExt)
2667 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2668 DAG.getValueType(VA.getValVT()));
2669 else if (VA.getLocInfo() == CCValAssign::ZExt)
2670 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2671 DAG.getValueType(VA.getValVT()));
2672 else if (VA.getLocInfo() == CCValAssign::BCvt)
2673 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2675 if (VA.isExtInLoc()) {
2676 // Handle MMX values passed in XMM regs.
2677 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2678 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2680 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2683 assert(VA.isMemLoc());
2684 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2687 // If value is passed via pointer - do a load.
2688 if (VA.getLocInfo() == CCValAssign::Indirect)
2689 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2690 MachinePointerInfo(), false, false, false, 0);
2692 InVals.push_back(ArgValue);
2695 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2696 // All x86 ABIs require that for returning structs by value we copy the
2697 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2698 // the argument into a virtual register so that we can access it from the
2700 if (Ins[i].Flags.isSRet()) {
2701 unsigned Reg = FuncInfo->getSRetReturnReg();
2703 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2704 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2705 FuncInfo->setSRetReturnReg(Reg);
2707 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2708 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2713 unsigned StackSize = CCInfo.getNextStackOffset();
2714 // Align stack specially for tail calls.
2715 if (shouldGuaranteeTCO(CallConv,
2716 MF.getTarget().Options.GuaranteedTailCallOpt))
2717 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2719 // If the function takes variable number of arguments, make a frame index for
2720 // the start of the first vararg value... for expansion of llvm.va_start. We
2721 // can skip this if there are no va_start calls.
2722 if (MFI->hasVAStart() &&
2723 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2724 CallConv != CallingConv::X86_ThisCall))) {
2725 FuncInfo->setVarArgsFrameIndex(
2726 MFI->CreateFixedObject(1, StackSize, true));
2729 // Figure out if XMM registers are in use.
2730 assert(!(Subtarget->useSoftFloat() &&
2731 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2732 "SSE register cannot be used when SSE is disabled!");
2734 // 64-bit calling conventions support varargs and register parameters, so we
2735 // have to do extra work to spill them in the prologue.
2736 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2737 // Find the first unallocated argument registers.
2738 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2739 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2740 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2741 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2742 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2743 "SSE register cannot be used when SSE is disabled!");
2745 // Gather all the live in physical registers.
2746 SmallVector<SDValue, 6> LiveGPRs;
2747 SmallVector<SDValue, 8> LiveXMMRegs;
2749 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2750 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2752 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2754 if (!ArgXMMs.empty()) {
2755 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2756 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2757 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2758 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2759 LiveXMMRegs.push_back(
2760 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2765 // Get to the caller-allocated home save location. Add 8 to account
2766 // for the return address.
2767 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2768 FuncInfo->setRegSaveFrameIndex(
2769 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2770 // Fixup to set vararg frame on shadow area (4 x i64).
2772 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2774 // For X86-64, if there are vararg parameters that are passed via
2775 // registers, then we must store them to their spots on the stack so
2776 // they may be loaded by deferencing the result of va_next.
2777 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2778 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2779 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2780 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2783 // Store the integer parameter registers.
2784 SmallVector<SDValue, 8> MemOps;
2785 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2786 getPointerTy(DAG.getDataLayout()));
2787 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2788 for (SDValue Val : LiveGPRs) {
2789 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2790 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2792 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2793 MachinePointerInfo::getFixedStack(
2794 DAG.getMachineFunction(),
2795 FuncInfo->getRegSaveFrameIndex(), Offset),
2797 MemOps.push_back(Store);
2801 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2802 // Now store the XMM (fp + vector) parameter registers.
2803 SmallVector<SDValue, 12> SaveXMMOps;
2804 SaveXMMOps.push_back(Chain);
2805 SaveXMMOps.push_back(ALVal);
2806 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2807 FuncInfo->getRegSaveFrameIndex(), dl));
2808 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2809 FuncInfo->getVarArgsFPOffset(), dl));
2810 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2812 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2813 MVT::Other, SaveXMMOps));
2816 if (!MemOps.empty())
2817 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2820 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2821 // Find the largest legal vector type.
2822 MVT VecVT = MVT::Other;
2823 // FIXME: Only some x86_32 calling conventions support AVX512.
2824 if (Subtarget->hasAVX512() &&
2825 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2826 CallConv == CallingConv::Intel_OCL_BI)))
2827 VecVT = MVT::v16f32;
2828 else if (Subtarget->hasAVX())
2830 else if (Subtarget->hasSSE2())
2833 // We forward some GPRs and some vector types.
2834 SmallVector<MVT, 2> RegParmTypes;
2835 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2836 RegParmTypes.push_back(IntVT);
2837 if (VecVT != MVT::Other)
2838 RegParmTypes.push_back(VecVT);
2840 // Compute the set of forwarded registers. The rest are scratch.
2841 SmallVectorImpl<ForwardedRegister> &Forwards =
2842 FuncInfo->getForwardedMustTailRegParms();
2843 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2845 // Conservatively forward AL on x86_64, since it might be used for varargs.
2846 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2847 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2848 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2851 // Copy all forwards from physical to virtual registers.
2852 for (ForwardedRegister &F : Forwards) {
2853 // FIXME: Can we use a less constrained schedule?
2854 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2855 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2856 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2860 // Some CCs need callee pop.
2861 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2862 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2863 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2865 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2866 // If this is an sret function, the return should pop the hidden pointer.
2867 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2868 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2869 argsAreStructReturn(Ins) == StackStructReturn)
2870 FuncInfo->setBytesToPopOnReturn(4);
2874 // RegSaveFrameIndex is X86-64 only.
2875 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2876 if (CallConv == CallingConv::X86_FastCall ||
2877 CallConv == CallingConv::X86_ThisCall)
2878 // fastcc functions can't have varargs.
2879 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2882 FuncInfo->setArgumentStackSize(StackSize);
2884 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2885 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2886 if (Personality == EHPersonality::CoreCLR) {
2888 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2889 // that we'd prefer this slot be allocated towards the bottom of the frame
2890 // (i.e. near the stack pointer after allocating the frame). Every
2891 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2892 // offset from the bottom of this and each funclet's frame must be the
2893 // same, so the size of funclets' (mostly empty) frames is dictated by
2894 // how far this slot is from the bottom (since they allocate just enough
2895 // space to accomodate holding this slot at the correct offset).
2896 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2897 EHInfo->PSPSymFrameIdx = PSPSymFI;
2905 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2906 SDValue StackPtr, SDValue Arg,
2907 SDLoc dl, SelectionDAG &DAG,
2908 const CCValAssign &VA,
2909 ISD::ArgFlagsTy Flags) const {
2910 unsigned LocMemOffset = VA.getLocMemOffset();
2911 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2912 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2914 if (Flags.isByVal())
2915 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2917 return DAG.getStore(
2918 Chain, dl, Arg, PtrOff,
2919 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2923 /// Emit a load of return address if tail call
2924 /// optimization is performed and it is required.
2926 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2927 SDValue &OutRetAddr, SDValue Chain,
2928 bool IsTailCall, bool Is64Bit,
2929 int FPDiff, SDLoc dl) const {
2930 // Adjust the Return address stack slot.
2931 EVT VT = getPointerTy(DAG.getDataLayout());
2932 OutRetAddr = getReturnAddressFrameIndex(DAG);
2934 // Load the "old" Return address.
2935 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2936 false, false, false, 0);
2937 return SDValue(OutRetAddr.getNode(), 1);
2940 /// Emit a store of the return address if tail call
2941 /// optimization is performed and it is required (FPDiff!=0).
2942 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2943 SDValue Chain, SDValue RetAddrFrIdx,
2944 EVT PtrVT, unsigned SlotSize,
2945 int FPDiff, SDLoc dl) {
2946 // Store the return address to the appropriate stack slot.
2947 if (!FPDiff) return Chain;
2948 // Calculate the new stack slot for the return address.
2949 int NewReturnAddrFI =
2950 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2952 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2953 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2954 MachinePointerInfo::getFixedStack(
2955 DAG.getMachineFunction(), NewReturnAddrFI),
2960 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2961 /// operation of specified width.
2962 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2964 unsigned NumElems = VT.getVectorNumElements();
2965 SmallVector<int, 8> Mask;
2966 Mask.push_back(NumElems);
2967 for (unsigned i = 1; i != NumElems; ++i)
2969 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2973 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2974 SmallVectorImpl<SDValue> &InVals) const {
2975 SelectionDAG &DAG = CLI.DAG;
2977 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2978 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2979 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2980 SDValue Chain = CLI.Chain;
2981 SDValue Callee = CLI.Callee;
2982 CallingConv::ID CallConv = CLI.CallConv;
2983 bool &isTailCall = CLI.IsTailCall;
2984 bool isVarArg = CLI.IsVarArg;
2986 MachineFunction &MF = DAG.getMachineFunction();
2987 bool Is64Bit = Subtarget->is64Bit();
2988 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2989 StructReturnType SR = callIsStructReturn(Outs);
2990 bool IsSibcall = false;
2991 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2992 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2994 if (Attr.getValueAsString() == "true")
2997 if (Subtarget->isPICStyleGOT() &&
2998 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2999 // If we are using a GOT, disable tail calls to external symbols with
3000 // default visibility. Tail calling such a symbol requires using a GOT
3001 // relocation, which forces early binding of the symbol. This breaks code
3002 // that require lazy function symbol resolution. Using musttail or
3003 // GuaranteedTailCallOpt will override this.
3004 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3005 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3006 G->getGlobal()->hasDefaultVisibility()))
3010 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3012 // Force this to be a tail call. The verifier rules are enough to ensure
3013 // that we can lower this successfully without moving the return address
3016 } else if (isTailCall) {
3017 // Check if it's really possible to do a tail call.
3018 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3019 isVarArg, SR != NotStructReturn,
3020 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3021 Outs, OutVals, Ins, DAG);
3023 // Sibcalls are automatically detected tailcalls which do not require
3025 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3032 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3033 "Var args not supported with calling convention fastcc, ghc or hipe");
3035 // Analyze operands of the call, assigning locations to each operand.
3036 SmallVector<CCValAssign, 16> ArgLocs;
3037 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3039 // Allocate shadow area for Win64
3041 CCInfo.AllocateStack(32, 8);
3043 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3045 // Get a count of how many bytes are to be pushed on the stack.
3046 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3048 // This is a sibcall. The memory operands are available in caller's
3049 // own caller's stack.
3051 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3052 canGuaranteeTCO(CallConv))
3053 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3056 if (isTailCall && !IsSibcall && !IsMustTail) {
3057 // Lower arguments at fp - stackoffset + fpdiff.
3058 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3060 FPDiff = NumBytesCallerPushed - NumBytes;
3062 // Set the delta of movement of the returnaddr stackslot.
3063 // But only set if delta is greater than previous delta.
3064 if (FPDiff < X86Info->getTCReturnAddrDelta())
3065 X86Info->setTCReturnAddrDelta(FPDiff);
3068 unsigned NumBytesToPush = NumBytes;
3069 unsigned NumBytesToPop = NumBytes;
3071 // If we have an inalloca argument, all stack space has already been allocated
3072 // for us and be right at the top of the stack. We don't support multiple
3073 // arguments passed in memory when using inalloca.
3074 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3076 if (!ArgLocs.back().isMemLoc())
3077 report_fatal_error("cannot use inalloca attribute on a register "
3079 if (ArgLocs.back().getLocMemOffset() != 0)
3080 report_fatal_error("any parameter with the inalloca attribute must be "
3081 "the only memory argument");
3085 Chain = DAG.getCALLSEQ_START(
3086 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3088 SDValue RetAddrFrIdx;
3089 // Load return address for tail calls.
3090 if (isTailCall && FPDiff)
3091 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3092 Is64Bit, FPDiff, dl);
3094 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3095 SmallVector<SDValue, 8> MemOpChains;
3098 // Walk the register/memloc assignments, inserting copies/loads. In the case
3099 // of tail call optimization arguments are handle later.
3100 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3101 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3102 // Skip inalloca arguments, they have already been written.
3103 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3104 if (Flags.isInAlloca())
3107 CCValAssign &VA = ArgLocs[i];
3108 EVT RegVT = VA.getLocVT();
3109 SDValue Arg = OutVals[i];
3110 bool isByVal = Flags.isByVal();
3112 // Promote the value if needed.
3113 switch (VA.getLocInfo()) {
3114 default: llvm_unreachable("Unknown loc info!");
3115 case CCValAssign::Full: break;
3116 case CCValAssign::SExt:
3117 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3119 case CCValAssign::ZExt:
3120 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3122 case CCValAssign::AExt:
3123 if (Arg.getValueType().isVector() &&
3124 Arg.getValueType().getVectorElementType() == MVT::i1)
3125 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3126 else if (RegVT.is128BitVector()) {
3127 // Special case: passing MMX values in XMM registers.
3128 Arg = DAG.getBitcast(MVT::i64, Arg);
3129 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3130 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3132 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3134 case CCValAssign::BCvt:
3135 Arg = DAG.getBitcast(RegVT, Arg);
3137 case CCValAssign::Indirect: {
3138 // Store the argument.
3139 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3140 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3141 Chain = DAG.getStore(
3142 Chain, dl, Arg, SpillSlot,
3143 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3150 if (VA.isRegLoc()) {
3151 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3152 if (isVarArg && IsWin64) {
3153 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3154 // shadow reg if callee is a varargs function.
3155 unsigned ShadowReg = 0;
3156 switch (VA.getLocReg()) {
3157 case X86::XMM0: ShadowReg = X86::RCX; break;
3158 case X86::XMM1: ShadowReg = X86::RDX; break;
3159 case X86::XMM2: ShadowReg = X86::R8; break;
3160 case X86::XMM3: ShadowReg = X86::R9; break;
3163 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3165 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3166 assert(VA.isMemLoc());
3167 if (!StackPtr.getNode())
3168 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3169 getPointerTy(DAG.getDataLayout()));
3170 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3171 dl, DAG, VA, Flags));
3175 if (!MemOpChains.empty())
3176 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3178 if (Subtarget->isPICStyleGOT()) {
3179 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3182 RegsToPass.push_back(std::make_pair(
3183 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3184 getPointerTy(DAG.getDataLayout()))));
3186 // If we are tail calling and generating PIC/GOT style code load the
3187 // address of the callee into ECX. The value in ecx is used as target of
3188 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3189 // for tail calls on PIC/GOT architectures. Normally we would just put the
3190 // address of GOT into ebx and then call target@PLT. But for tail calls
3191 // ebx would be restored (since ebx is callee saved) before jumping to the
3194 // Note: The actual moving to ECX is done further down.
3195 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3196 if (G && !G->getGlobal()->hasLocalLinkage() &&
3197 G->getGlobal()->hasDefaultVisibility())
3198 Callee = LowerGlobalAddress(Callee, DAG);
3199 else if (isa<ExternalSymbolSDNode>(Callee))
3200 Callee = LowerExternalSymbol(Callee, DAG);
3204 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3205 // From AMD64 ABI document:
3206 // For calls that may call functions that use varargs or stdargs
3207 // (prototype-less calls or calls to functions containing ellipsis (...) in
3208 // the declaration) %al is used as hidden argument to specify the number
3209 // of SSE registers used. The contents of %al do not need to match exactly
3210 // the number of registers, but must be an ubound on the number of SSE
3211 // registers used and is in the range 0 - 8 inclusive.
3213 // Count the number of XMM registers allocated.
3214 static const MCPhysReg XMMArgRegs[] = {
3215 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3216 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3218 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3219 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3220 && "SSE registers cannot be used when SSE is disabled");
3222 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3223 DAG.getConstant(NumXMMRegs, dl,
3227 if (isVarArg && IsMustTail) {
3228 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3229 for (const auto &F : Forwards) {
3230 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3231 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3235 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3236 // don't need this because the eligibility check rejects calls that require
3237 // shuffling arguments passed in memory.
3238 if (!IsSibcall && isTailCall) {
3239 // Force all the incoming stack arguments to be loaded from the stack
3240 // before any new outgoing arguments are stored to the stack, because the
3241 // outgoing stack slots may alias the incoming argument stack slots, and
3242 // the alias isn't otherwise explicit. This is slightly more conservative
3243 // than necessary, because it means that each store effectively depends
3244 // on every argument instead of just those arguments it would clobber.
3245 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3247 SmallVector<SDValue, 8> MemOpChains2;
3250 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3251 CCValAssign &VA = ArgLocs[i];
3254 assert(VA.isMemLoc());
3255 SDValue Arg = OutVals[i];
3256 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3257 // Skip inalloca arguments. They don't require any work.
3258 if (Flags.isInAlloca())
3260 // Create frame index.
3261 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3262 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3263 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3264 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3266 if (Flags.isByVal()) {
3267 // Copy relative to framepointer.
3268 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3269 if (!StackPtr.getNode())
3270 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3271 getPointerTy(DAG.getDataLayout()));
3272 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3275 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3279 // Store relative to framepointer.
3280 MemOpChains2.push_back(DAG.getStore(
3281 ArgChain, dl, Arg, FIN,
3282 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3287 if (!MemOpChains2.empty())
3288 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3290 // Store the return address to the appropriate stack slot.
3291 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3292 getPointerTy(DAG.getDataLayout()),
3293 RegInfo->getSlotSize(), FPDiff, dl);
3296 // Build a sequence of copy-to-reg nodes chained together with token chain
3297 // and flag operands which copy the outgoing args into registers.
3299 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3300 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3301 RegsToPass[i].second, InFlag);
3302 InFlag = Chain.getValue(1);
3305 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3306 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3307 // In the 64-bit large code model, we have to make all calls
3308 // through a register, since the call instruction's 32-bit
3309 // pc-relative offset may not be large enough to hold the whole
3311 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3312 // If the callee is a GlobalAddress node (quite common, every direct call
3313 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3315 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3317 // We should use extra load for direct calls to dllimported functions in
3319 const GlobalValue *GV = G->getGlobal();
3320 if (!GV->hasDLLImportStorageClass()) {
3321 unsigned char OpFlags = 0;
3322 bool ExtraLoad = false;
3323 unsigned WrapperKind = ISD::DELETED_NODE;
3325 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3326 // external symbols most go through the PLT in PIC mode. If the symbol
3327 // has hidden or protected visibility, or if it is static or local, then
3328 // we don't need to use the PLT - we can directly call it.
3329 if (Subtarget->isTargetELF() &&
3330 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3331 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3332 OpFlags = X86II::MO_PLT;
3333 } else if (Subtarget->isPICStyleStubAny() &&
3334 !GV->isStrongDefinitionForLinker() &&
3335 (!Subtarget->getTargetTriple().isMacOSX() ||
3336 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3337 // PC-relative references to external symbols should go through $stub,
3338 // unless we're building with the leopard linker or later, which
3339 // automatically synthesizes these stubs.
3340 OpFlags = X86II::MO_DARWIN_STUB;
3341 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3342 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3343 // If the function is marked as non-lazy, generate an indirect call
3344 // which loads from the GOT directly. This avoids runtime overhead
3345 // at the cost of eager binding (and one extra byte of encoding).
3346 OpFlags = X86II::MO_GOTPCREL;
3347 WrapperKind = X86ISD::WrapperRIP;
3351 Callee = DAG.getTargetGlobalAddress(
3352 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3354 // Add a wrapper if needed.
3355 if (WrapperKind != ISD::DELETED_NODE)
3356 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3357 getPointerTy(DAG.getDataLayout()), Callee);
3358 // Add extra indirection if needed.
3360 Callee = DAG.getLoad(
3361 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3362 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3365 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3366 unsigned char OpFlags = 0;
3368 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3369 // external symbols should go through the PLT.
3370 if (Subtarget->isTargetELF() &&
3371 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3372 OpFlags = X86II::MO_PLT;
3373 } else if (Subtarget->isPICStyleStubAny() &&
3374 (!Subtarget->getTargetTriple().isMacOSX() ||
3375 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3376 // PC-relative references to external symbols should go through $stub,
3377 // unless we're building with the leopard linker or later, which
3378 // automatically synthesizes these stubs.
3379 OpFlags = X86II::MO_DARWIN_STUB;
3382 Callee = DAG.getTargetExternalSymbol(
3383 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3384 } else if (Subtarget->isTarget64BitILP32() &&
3385 Callee->getValueType(0) == MVT::i32) {
3386 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3387 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3390 // Returns a chain & a flag for retval copy to use.
3391 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3392 SmallVector<SDValue, 8> Ops;
3394 if (!IsSibcall && isTailCall) {
3395 Chain = DAG.getCALLSEQ_END(Chain,
3396 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3397 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3398 InFlag = Chain.getValue(1);
3401 Ops.push_back(Chain);
3402 Ops.push_back(Callee);
3405 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3407 // Add argument registers to the end of the list so that they are known live
3409 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3410 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3411 RegsToPass[i].second.getValueType()));
3413 // Add a register mask operand representing the call-preserved registers.
3414 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3415 assert(Mask && "Missing call preserved mask for calling convention");
3417 // If this is an invoke in a 32-bit function using a funclet-based
3418 // personality, assume the function clobbers all registers. If an exception
3419 // is thrown, the runtime will not restore CSRs.
3420 // FIXME: Model this more precisely so that we can register allocate across
3421 // the normal edge and spill and fill across the exceptional edge.
3422 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3423 const Function *CallerFn = MF.getFunction();
3424 EHPersonality Pers =
3425 CallerFn->hasPersonalityFn()
3426 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3427 : EHPersonality::Unknown;
3428 if (isFuncletEHPersonality(Pers))
3429 Mask = RegInfo->getNoPreservedMask();
3432 Ops.push_back(DAG.getRegisterMask(Mask));
3434 if (InFlag.getNode())
3435 Ops.push_back(InFlag);
3439 //// If this is the first return lowered for this function, add the regs
3440 //// to the liveout set for the function.
3441 // This isn't right, although it's probably harmless on x86; liveouts
3442 // should be computed from returns not tail calls. Consider a void
3443 // function making a tail call to a function returning int.
3444 MF.getFrameInfo()->setHasTailCall();
3445 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3448 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3449 InFlag = Chain.getValue(1);
3451 // Create the CALLSEQ_END node.
3452 unsigned NumBytesForCalleeToPop;
3453 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3454 DAG.getTarget().Options.GuaranteedTailCallOpt))
3455 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3456 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3457 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3458 SR == StackStructReturn)
3459 // If this is a call to a struct-return function, the callee
3460 // pops the hidden struct pointer, so we have to push it back.
3461 // This is common for Darwin/X86, Linux & Mingw32 targets.
3462 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3463 NumBytesForCalleeToPop = 4;
3465 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3467 // Returns a flag for retval copy to use.
3469 Chain = DAG.getCALLSEQ_END(Chain,
3470 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3471 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3474 InFlag = Chain.getValue(1);
3477 // Handle result values, copying them out of physregs into vregs that we
3479 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3480 Ins, dl, DAG, InVals);
3483 //===----------------------------------------------------------------------===//
3484 // Fast Calling Convention (tail call) implementation
3485 //===----------------------------------------------------------------------===//
3487 // Like std call, callee cleans arguments, convention except that ECX is
3488 // reserved for storing the tail called function address. Only 2 registers are
3489 // free for argument passing (inreg). Tail call optimization is performed
3491 // * tailcallopt is enabled
3492 // * caller/callee are fastcc
3493 // On X86_64 architecture with GOT-style position independent code only local
3494 // (within module) calls are supported at the moment.
3495 // To keep the stack aligned according to platform abi the function
3496 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3497 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3498 // If a tail called function callee has more arguments than the caller the
3499 // caller needs to make sure that there is room to move the RETADDR to. This is
3500 // achieved by reserving an area the size of the argument delta right after the
3501 // original RETADDR, but before the saved framepointer or the spilled registers
3502 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3514 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3517 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3518 SelectionDAG& DAG) const {
3519 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3520 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3521 unsigned StackAlignment = TFI.getStackAlignment();
3522 uint64_t AlignMask = StackAlignment - 1;
3523 int64_t Offset = StackSize;
3524 unsigned SlotSize = RegInfo->getSlotSize();
3525 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3526 // Number smaller than 12 so just add the difference.
3527 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3529 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3530 Offset = ((~AlignMask) & Offset) + StackAlignment +
3531 (StackAlignment-SlotSize);
3536 /// Return true if the given stack call argument is already available in the
3537 /// same position (relatively) of the caller's incoming argument stack.
3539 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3540 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3541 const X86InstrInfo *TII) {
3542 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3544 if (Arg.getOpcode() == ISD::CopyFromReg) {
3545 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3546 if (!TargetRegisterInfo::isVirtualRegister(VR))
3548 MachineInstr *Def = MRI->getVRegDef(VR);
3551 if (!Flags.isByVal()) {
3552 if (!TII->isLoadFromStackSlot(Def, FI))
3555 unsigned Opcode = Def->getOpcode();
3556 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3557 Opcode == X86::LEA64_32r) &&
3558 Def->getOperand(1).isFI()) {
3559 FI = Def->getOperand(1).getIndex();
3560 Bytes = Flags.getByValSize();
3564 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3565 if (Flags.isByVal())
3566 // ByVal argument is passed in as a pointer but it's now being
3567 // dereferenced. e.g.
3568 // define @foo(%struct.X* %A) {
3569 // tail call @bar(%struct.X* byval %A)
3572 SDValue Ptr = Ld->getBasePtr();
3573 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3576 FI = FINode->getIndex();
3577 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3578 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3579 FI = FINode->getIndex();
3580 Bytes = Flags.getByValSize();
3584 assert(FI != INT_MAX);
3585 if (!MFI->isFixedObjectIndex(FI))
3587 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3590 /// Check whether the call is eligible for tail call optimization. Targets
3591 /// that want to do tail call optimization should implement this function.
3592 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3593 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3594 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3595 const SmallVectorImpl<ISD::OutputArg> &Outs,
3596 const SmallVectorImpl<SDValue> &OutVals,
3597 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3598 if (!mayTailCallThisCC(CalleeCC))
3601 // If -tailcallopt is specified, make fastcc functions tail-callable.
3602 MachineFunction &MF = DAG.getMachineFunction();
3603 const Function *CallerF = MF.getFunction();
3605 // If the function return type is x86_fp80 and the callee return type is not,
3606 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3607 // perform a tailcall optimization here.
3608 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3611 CallingConv::ID CallerCC = CallerF->getCallingConv();
3612 bool CCMatch = CallerCC == CalleeCC;
3613 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3614 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3616 // Win64 functions have extra shadow space for argument homing. Don't do the
3617 // sibcall if the caller and callee have mismatched expectations for this
3619 if (IsCalleeWin64 != IsCallerWin64)
3622 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3623 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3628 // Look for obvious safe cases to perform tail call optimization that do not
3629 // require ABI changes. This is what gcc calls sibcall.
3631 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3632 // emit a special epilogue.
3633 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3634 if (RegInfo->needsStackRealignment(MF))
3637 // Also avoid sibcall optimization if either caller or callee uses struct
3638 // return semantics.
3639 if (isCalleeStructRet || isCallerStructRet)
3642 // Do not sibcall optimize vararg calls unless all arguments are passed via
3644 if (isVarArg && !Outs.empty()) {
3645 // Optimizing for varargs on Win64 is unlikely to be safe without
3646 // additional testing.
3647 if (IsCalleeWin64 || IsCallerWin64)
3650 SmallVector<CCValAssign, 16> ArgLocs;
3651 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3654 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3655 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3656 if (!ArgLocs[i].isRegLoc())
3660 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3661 // stack. Therefore, if it's not used by the call it is not safe to optimize
3662 // this into a sibcall.
3663 bool Unused = false;
3664 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3671 SmallVector<CCValAssign, 16> RVLocs;
3672 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3674 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3675 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3676 CCValAssign &VA = RVLocs[i];
3677 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3682 // If the calling conventions do not match, then we'd better make sure the
3683 // results are returned in the same way as what the caller expects.
3685 SmallVector<CCValAssign, 16> RVLocs1;
3686 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3688 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3690 SmallVector<CCValAssign, 16> RVLocs2;
3691 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3693 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3695 if (RVLocs1.size() != RVLocs2.size())
3697 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3698 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3700 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3702 if (RVLocs1[i].isRegLoc()) {
3703 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3706 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3712 unsigned StackArgsSize = 0;
3714 // If the callee takes no arguments then go on to check the results of the
3716 if (!Outs.empty()) {
3717 // Check if stack adjustment is needed. For now, do not do this if any
3718 // argument is passed on the stack.
3719 SmallVector<CCValAssign, 16> ArgLocs;
3720 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3723 // Allocate shadow area for Win64
3725 CCInfo.AllocateStack(32, 8);
3727 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3728 StackArgsSize = CCInfo.getNextStackOffset();
3730 if (CCInfo.getNextStackOffset()) {
3731 // Check if the arguments are already laid out in the right way as
3732 // the caller's fixed stack objects.
3733 MachineFrameInfo *MFI = MF.getFrameInfo();
3734 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3735 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3736 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3737 CCValAssign &VA = ArgLocs[i];
3738 SDValue Arg = OutVals[i];
3739 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3740 if (VA.getLocInfo() == CCValAssign::Indirect)
3742 if (!VA.isRegLoc()) {
3743 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3750 // If the tailcall address may be in a register, then make sure it's
3751 // possible to register allocate for it. In 32-bit, the call address can
3752 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3753 // callee-saved registers are restored. These happen to be the same
3754 // registers used to pass 'inreg' arguments so watch out for those.
3755 if (!Subtarget->is64Bit() &&
3756 ((!isa<GlobalAddressSDNode>(Callee) &&
3757 !isa<ExternalSymbolSDNode>(Callee)) ||
3758 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3759 unsigned NumInRegs = 0;
3760 // In PIC we need an extra register to formulate the address computation
3762 unsigned MaxInRegs =
3763 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3765 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3766 CCValAssign &VA = ArgLocs[i];
3769 unsigned Reg = VA.getLocReg();
3772 case X86::EAX: case X86::EDX: case X86::ECX:
3773 if (++NumInRegs == MaxInRegs)
3781 bool CalleeWillPop =
3782 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3783 MF.getTarget().Options.GuaranteedTailCallOpt);
3785 if (unsigned BytesToPop =
3786 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3787 // If we have bytes to pop, the callee must pop them.
3788 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3789 if (!CalleePopMatches)
3791 } else if (CalleeWillPop && StackArgsSize > 0) {
3792 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3800 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3801 const TargetLibraryInfo *libInfo) const {
3802 return X86::createFastISel(funcInfo, libInfo);
3805 //===----------------------------------------------------------------------===//
3806 // Other Lowering Hooks
3807 //===----------------------------------------------------------------------===//
3809 static bool MayFoldLoad(SDValue Op) {
3810 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3813 static bool MayFoldIntoStore(SDValue Op) {
3814 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3817 static bool isTargetShuffle(unsigned Opcode) {
3819 default: return false;
3820 case X86ISD::BLENDI:
3821 case X86ISD::PSHUFB:
3822 case X86ISD::PSHUFD:
3823 case X86ISD::PSHUFHW:
3824 case X86ISD::PSHUFLW:
3826 case X86ISD::PALIGNR:
3827 case X86ISD::MOVLHPS:
3828 case X86ISD::MOVLHPD:
3829 case X86ISD::MOVHLPS:
3830 case X86ISD::MOVLPS:
3831 case X86ISD::MOVLPD:
3832 case X86ISD::MOVSHDUP:
3833 case X86ISD::MOVSLDUP:
3834 case X86ISD::MOVDDUP:
3837 case X86ISD::UNPCKL:
3838 case X86ISD::UNPCKH:
3839 case X86ISD::VPERMILPI:
3840 case X86ISD::VPERM2X128:
3841 case X86ISD::VPERMI:
3842 case X86ISD::VPERMV:
3843 case X86ISD::VPERMV3:
3848 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3849 SDValue V1, unsigned TargetMask,
3850 SelectionDAG &DAG) {
3852 default: llvm_unreachable("Unknown x86 shuffle node");
3853 case X86ISD::PSHUFD:
3854 case X86ISD::PSHUFHW:
3855 case X86ISD::PSHUFLW:
3856 case X86ISD::VPERMILPI:
3857 case X86ISD::VPERMI:
3858 return DAG.getNode(Opc, dl, VT, V1,
3859 DAG.getConstant(TargetMask, dl, MVT::i8));
3863 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3864 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3866 default: llvm_unreachable("Unknown x86 shuffle node");
3867 case X86ISD::MOVLHPS:
3868 case X86ISD::MOVLHPD:
3869 case X86ISD::MOVHLPS:
3870 case X86ISD::MOVLPS:
3871 case X86ISD::MOVLPD:
3874 case X86ISD::UNPCKL:
3875 case X86ISD::UNPCKH:
3876 return DAG.getNode(Opc, dl, VT, V1, V2);
3880 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3881 MachineFunction &MF = DAG.getMachineFunction();
3882 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3883 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3884 int ReturnAddrIndex = FuncInfo->getRAIndex();
3886 if (ReturnAddrIndex == 0) {
3887 // Set up a frame object for the return address.
3888 unsigned SlotSize = RegInfo->getSlotSize();
3889 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3892 FuncInfo->setRAIndex(ReturnAddrIndex);
3895 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3898 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3899 bool hasSymbolicDisplacement) {
3900 // Offset should fit into 32 bit immediate field.
3901 if (!isInt<32>(Offset))
3904 // If we don't have a symbolic displacement - we don't have any extra
3906 if (!hasSymbolicDisplacement)
3909 // FIXME: Some tweaks might be needed for medium code model.
3910 if (M != CodeModel::Small && M != CodeModel::Kernel)
3913 // For small code model we assume that latest object is 16MB before end of 31
3914 // bits boundary. We may also accept pretty large negative constants knowing
3915 // that all objects are in the positive half of address space.
3916 if (M == CodeModel::Small && Offset < 16*1024*1024)
3919 // For kernel code model we know that all object resist in the negative half
3920 // of 32bits address space. We may not accept negative offsets, since they may
3921 // be just off and we may accept pretty large positive ones.
3922 if (M == CodeModel::Kernel && Offset >= 0)
3928 /// Determines whether the callee is required to pop its own arguments.
3929 /// Callee pop is necessary to support tail calls.
3930 bool X86::isCalleePop(CallingConv::ID CallingConv,
3931 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3932 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3933 // can guarantee TCO.
3934 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3937 switch (CallingConv) {
3940 case CallingConv::X86_StdCall:
3941 case CallingConv::X86_FastCall:
3942 case CallingConv::X86_ThisCall:
3943 case CallingConv::X86_VectorCall:
3948 /// \brief Return true if the condition is an unsigned comparison operation.
3949 static bool isX86CCUnsigned(unsigned X86CC) {
3951 default: llvm_unreachable("Invalid integer condition!");
3952 case X86::COND_E: return true;
3953 case X86::COND_G: return false;
3954 case X86::COND_GE: return false;
3955 case X86::COND_L: return false;
3956 case X86::COND_LE: return false;
3957 case X86::COND_NE: return true;
3958 case X86::COND_B: return true;
3959 case X86::COND_A: return true;
3960 case X86::COND_BE: return true;
3961 case X86::COND_AE: return true;
3965 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
3966 switch (SetCCOpcode) {
3967 default: llvm_unreachable("Invalid integer condition!");
3968 case ISD::SETEQ: return X86::COND_E;
3969 case ISD::SETGT: return X86::COND_G;
3970 case ISD::SETGE: return X86::COND_GE;
3971 case ISD::SETLT: return X86::COND_L;
3972 case ISD::SETLE: return X86::COND_LE;
3973 case ISD::SETNE: return X86::COND_NE;
3974 case ISD::SETULT: return X86::COND_B;
3975 case ISD::SETUGT: return X86::COND_A;
3976 case ISD::SETULE: return X86::COND_BE;
3977 case ISD::SETUGE: return X86::COND_AE;
3981 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3982 /// condition code, returning the condition code and the LHS/RHS of the
3983 /// comparison to make.
3984 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3985 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3987 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3988 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3989 // X > -1 -> X == 0, jump !sign.
3990 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3991 return X86::COND_NS;
3993 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3994 // X < 0 -> X == 0, jump on sign.
3997 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3999 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4000 return X86::COND_LE;
4004 return TranslateIntegerX86CC(SetCCOpcode);
4007 // First determine if it is required or is profitable to flip the operands.
4009 // If LHS is a foldable load, but RHS is not, flip the condition.
4010 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4011 !ISD::isNON_EXTLoad(RHS.getNode())) {
4012 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4013 std::swap(LHS, RHS);
4016 switch (SetCCOpcode) {
4022 std::swap(LHS, RHS);
4026 // On a floating point condition, the flags are set as follows:
4028 // 0 | 0 | 0 | X > Y
4029 // 0 | 0 | 1 | X < Y
4030 // 1 | 0 | 0 | X == Y
4031 // 1 | 1 | 1 | unordered
4032 switch (SetCCOpcode) {
4033 default: llvm_unreachable("Condcode should be pre-legalized away");
4035 case ISD::SETEQ: return X86::COND_E;
4036 case ISD::SETOLT: // flipped
4038 case ISD::SETGT: return X86::COND_A;
4039 case ISD::SETOLE: // flipped
4041 case ISD::SETGE: return X86::COND_AE;
4042 case ISD::SETUGT: // flipped
4044 case ISD::SETLT: return X86::COND_B;
4045 case ISD::SETUGE: // flipped
4047 case ISD::SETLE: return X86::COND_BE;
4049 case ISD::SETNE: return X86::COND_NE;
4050 case ISD::SETUO: return X86::COND_P;
4051 case ISD::SETO: return X86::COND_NP;
4053 case ISD::SETUNE: return X86::COND_INVALID;
4057 /// Is there a floating point cmov for the specific X86 condition code?
4058 /// Current x86 isa includes the following FP cmov instructions:
4059 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4060 static bool hasFPCMov(unsigned X86CC) {
4076 /// Returns true if the target can instruction select the
4077 /// specified FP immediate natively. If false, the legalizer will
4078 /// materialize the FP immediate as a load from a constant pool.
4079 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4080 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4081 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4087 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4088 ISD::LoadExtType ExtTy,
4090 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4091 // relocation target a movq or addq instruction: don't let the load shrink.
4092 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4093 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4094 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4095 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4099 /// \brief Returns true if it is beneficial to convert a load of a constant
4100 /// to just the constant itself.
4101 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4103 assert(Ty->isIntegerTy());
4105 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4106 if (BitSize == 0 || BitSize > 64)
4111 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4112 unsigned Index) const {
4113 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4116 return (Index == 0 || Index == ResVT.getVectorNumElements());
4119 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4120 // Speculate cttz only if we can directly use TZCNT.
4121 return Subtarget->hasBMI();
4124 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4125 // Speculate ctlz only if we can directly use LZCNT.
4126 return Subtarget->hasLZCNT();
4129 /// Return true if every element in Mask, beginning
4130 /// from position Pos and ending in Pos+Size is undef.
4131 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4132 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4138 /// Return true if Val is undef or if its value falls within the
4139 /// specified range (L, H].
4140 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4141 return (Val < 0) || (Val >= Low && Val < Hi);
4144 /// Val is either less than zero (undef) or equal to the specified value.
4145 static bool isUndefOrEqual(int Val, int CmpVal) {
4146 return (Val < 0 || Val == CmpVal);
4149 /// Return true if every element in Mask, beginning
4150 /// from position Pos and ending in Pos+Size, falls within the specified
4151 /// sequential range (Low, Low+Size]. or is undef.
4152 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4153 unsigned Pos, unsigned Size, int Low) {
4154 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4155 if (!isUndefOrEqual(Mask[i], Low))
4160 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4161 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4162 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4163 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4164 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4167 // The index should be aligned on a vecWidth-bit boundary.
4169 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4171 MVT VT = N->getSimpleValueType(0);
4172 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4173 bool Result = (Index * ElSize) % vecWidth == 0;
4178 /// Return true if the specified INSERT_SUBVECTOR
4179 /// operand specifies a subvector insert that is suitable for input to
4180 /// insertion of 128 or 256-bit subvectors
4181 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4182 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4183 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4185 // The index should be aligned on a vecWidth-bit boundary.
4187 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4189 MVT VT = N->getSimpleValueType(0);
4190 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4191 bool Result = (Index * ElSize) % vecWidth == 0;
4196 bool X86::isVINSERT128Index(SDNode *N) {
4197 return isVINSERTIndex(N, 128);
4200 bool X86::isVINSERT256Index(SDNode *N) {
4201 return isVINSERTIndex(N, 256);
4204 bool X86::isVEXTRACT128Index(SDNode *N) {
4205 return isVEXTRACTIndex(N, 128);
4208 bool X86::isVEXTRACT256Index(SDNode *N) {
4209 return isVEXTRACTIndex(N, 256);
4212 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4213 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4214 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4215 "Illegal extract subvector for VEXTRACT");
4218 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4220 MVT VecVT = N->getOperand(0).getSimpleValueType();
4221 MVT ElVT = VecVT.getVectorElementType();
4223 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4224 return Index / NumElemsPerChunk;
4227 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4228 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4229 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4230 "Illegal insert subvector for VINSERT");
4233 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4235 MVT VecVT = N->getSimpleValueType(0);
4236 MVT ElVT = VecVT.getVectorElementType();
4238 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4239 return Index / NumElemsPerChunk;
4242 /// Return the appropriate immediate to extract the specified
4243 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4244 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4245 return getExtractVEXTRACTImmediate(N, 128);
4248 /// Return the appropriate immediate to extract the specified
4249 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4250 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4251 return getExtractVEXTRACTImmediate(N, 256);
4254 /// Return the appropriate immediate to insert at the specified
4255 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4256 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4257 return getInsertVINSERTImmediate(N, 128);
4260 /// Return the appropriate immediate to insert at the specified
4261 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4262 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4263 return getInsertVINSERTImmediate(N, 256);
4266 /// Returns true if V is a constant integer zero.
4267 static bool isZero(SDValue V) {
4268 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4269 return C && C->isNullValue();
4272 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4273 bool X86::isZeroNode(SDValue Elt) {
4276 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4277 return CFP->getValueAPF().isPosZero();
4281 // Build a vector of constants
4282 // Use an UNDEF node if MaskElt == -1.
4283 // Spilt 64-bit constants in the 32-bit mode.
4284 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4286 SDLoc dl, bool IsMask = false) {
4288 SmallVector<SDValue, 32> Ops;
4291 MVT ConstVecVT = VT;
4292 unsigned NumElts = VT.getVectorNumElements();
4293 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4294 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4295 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4299 MVT EltVT = ConstVecVT.getVectorElementType();
4300 for (unsigned i = 0; i < NumElts; ++i) {
4301 bool IsUndef = Values[i] < 0 && IsMask;
4302 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4303 DAG.getConstant(Values[i], dl, EltVT);
4304 Ops.push_back(OpNode);
4306 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4307 DAG.getConstant(0, dl, EltVT));
4309 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4311 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4315 /// Returns a vector of specified type with all zero elements.
4316 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4317 SelectionDAG &DAG, SDLoc dl) {
4318 assert(VT.isVector() && "Expected a vector type");
4320 // Always build SSE zero vectors as <4 x i32> bitcasted
4321 // to their dest type. This ensures they get CSE'd.
4323 if (VT.is128BitVector()) { // SSE
4324 if (Subtarget->hasSSE2()) { // SSE2
4325 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4326 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4328 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4329 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4331 } else if (VT.is256BitVector()) { // AVX
4332 if (Subtarget->hasInt256()) { // AVX2
4333 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4334 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4335 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4337 // 256-bit logic and arithmetic instructions in AVX are all
4338 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4339 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4340 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4341 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4343 } else if (VT.is512BitVector()) { // AVX-512
4344 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4345 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4346 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4347 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4348 } else if (VT.getVectorElementType() == MVT::i1) {
4350 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4351 && "Unexpected vector type");
4352 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4353 && "Unexpected vector type");
4354 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4355 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4356 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4358 llvm_unreachable("Unexpected vector type");
4360 return DAG.getBitcast(VT, Vec);
4363 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4364 SelectionDAG &DAG, SDLoc dl,
4365 unsigned vectorWidth) {
4366 assert((vectorWidth == 128 || vectorWidth == 256) &&
4367 "Unsupported vector width");
4368 EVT VT = Vec.getValueType();
4369 EVT ElVT = VT.getVectorElementType();
4370 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4371 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4372 VT.getVectorNumElements()/Factor);
4374 // Extract from UNDEF is UNDEF.
4375 if (Vec.getOpcode() == ISD::UNDEF)
4376 return DAG.getUNDEF(ResultVT);
4378 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4379 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4380 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4382 // This is the index of the first element of the vectorWidth-bit chunk
4383 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4384 IdxVal &= ~(ElemsPerChunk - 1);
4386 // If the input is a buildvector just emit a smaller one.
4387 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4388 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4389 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4391 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4392 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4395 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4396 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4397 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4398 /// instructions or a simple subregister reference. Idx is an index in the
4399 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4400 /// lowering EXTRACT_VECTOR_ELT operations easier.
4401 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4402 SelectionDAG &DAG, SDLoc dl) {
4403 assert((Vec.getValueType().is256BitVector() ||
4404 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4405 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4408 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4409 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4410 SelectionDAG &DAG, SDLoc dl) {
4411 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4412 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4415 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4416 unsigned IdxVal, SelectionDAG &DAG,
4417 SDLoc dl, unsigned vectorWidth) {
4418 assert((vectorWidth == 128 || vectorWidth == 256) &&
4419 "Unsupported vector width");
4420 // Inserting UNDEF is Result
4421 if (Vec.getOpcode() == ISD::UNDEF)
4423 EVT VT = Vec.getValueType();
4424 EVT ElVT = VT.getVectorElementType();
4425 EVT ResultVT = Result.getValueType();
4427 // Insert the relevant vectorWidth bits.
4428 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4429 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4431 // This is the index of the first element of the vectorWidth-bit chunk
4432 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4433 IdxVal &= ~(ElemsPerChunk - 1);
4435 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4436 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4439 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4440 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4441 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4442 /// simple superregister reference. Idx is an index in the 128 bits
4443 /// we want. It need not be aligned to a 128-bit boundary. That makes
4444 /// lowering INSERT_VECTOR_ELT operations easier.
4445 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4446 SelectionDAG &DAG, SDLoc dl) {
4447 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4449 // For insertion into the zero index (low half) of a 256-bit vector, it is
4450 // more efficient to generate a blend with immediate instead of an insert*128.
4451 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4452 // extend the subvector to the size of the result vector. Make sure that
4453 // we are not recursing on that node by checking for undef here.
4454 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4455 Result.getOpcode() != ISD::UNDEF) {
4456 EVT ResultVT = Result.getValueType();
4457 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4458 SDValue Undef = DAG.getUNDEF(ResultVT);
4459 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4462 // The blend instruction, and therefore its mask, depend on the data type.
4463 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4464 if (ScalarType.isFloatingPoint()) {
4465 // Choose either vblendps (float) or vblendpd (double).
4466 unsigned ScalarSize = ScalarType.getSizeInBits();
4467 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4468 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4469 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4470 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4473 const X86Subtarget &Subtarget =
4474 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4476 // AVX2 is needed for 256-bit integer blend support.
4477 // Integers must be cast to 32-bit because there is only vpblendd;
4478 // vpblendw can't be used for this because it has a handicapped mask.
4480 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4481 // is still more efficient than using the wrong domain vinsertf128 that
4482 // will be created by InsertSubVector().
4483 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4485 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4486 Vec256 = DAG.getBitcast(CastVT, Vec256);
4487 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4488 return DAG.getBitcast(ResultVT, Vec256);
4491 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4494 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4495 SelectionDAG &DAG, SDLoc dl) {
4496 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4497 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4500 /// Insert i1-subvector to i1-vector.
4501 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4504 SDValue Vec = Op.getOperand(0);
4505 SDValue SubVec = Op.getOperand(1);
4506 SDValue Idx = Op.getOperand(2);
4508 if (!isa<ConstantSDNode>(Idx))
4511 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4512 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4515 MVT OpVT = Op.getSimpleValueType();
4516 MVT SubVecVT = SubVec.getSimpleValueType();
4517 unsigned NumElems = OpVT.getVectorNumElements();
4518 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4520 assert(IdxVal + SubVecNumElems <= NumElems &&
4521 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4522 "Unexpected index value in INSERT_SUBVECTOR");
4524 // There are 3 possible cases:
4525 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4526 // 2. Subvector should be inserted in the upper part
4527 // (IdxVal + SubVecNumElems == NumElems)
4528 // 3. Subvector should be inserted in the middle (for example v2i1
4529 // to v16i1, index 2)
4531 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4532 SDValue Undef = DAG.getUNDEF(OpVT);
4533 SDValue WideSubVec =
4534 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4536 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4537 DAG.getConstant(IdxVal, dl, MVT::i8));
4539 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4540 unsigned ShiftLeft = NumElems - SubVecNumElems;
4541 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4542 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4543 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4544 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4545 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4549 // Zero lower bits of the Vec
4550 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4551 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4552 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4553 // Merge them together
4554 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4557 // Simple case when we put subvector in the upper part
4558 if (IdxVal + SubVecNumElems == NumElems) {
4559 // Zero upper bits of the Vec
4560 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4561 DAG.getConstant(IdxVal, dl, MVT::i8));
4562 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4563 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4564 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4565 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4567 // Subvector should be inserted in the middle - use shuffle
4568 SmallVector<int, 64> Mask;
4569 for (unsigned i = 0; i < NumElems; ++i)
4570 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4572 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4575 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4576 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4577 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4578 /// large BUILD_VECTORS.
4579 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4580 unsigned NumElems, SelectionDAG &DAG,
4582 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4583 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4586 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4587 unsigned NumElems, SelectionDAG &DAG,
4589 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4590 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4593 /// Returns a vector of specified type with all bits set.
4594 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4595 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4596 /// Then bitcast to their original type, ensuring they get CSE'd.
4597 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4598 SelectionDAG &DAG, SDLoc dl) {
4599 assert(VT.isVector() && "Expected a vector type");
4601 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4603 if (VT.is512BitVector()) {
4604 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4605 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4606 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4607 } else if (VT.is256BitVector()) {
4608 if (Subtarget->hasInt256()) { // AVX2
4609 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4610 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4612 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4613 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4615 } else if (VT.is128BitVector()) {
4616 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4618 llvm_unreachable("Unexpected vector type");
4620 return DAG.getBitcast(VT, Vec);
4623 /// Returns a vector_shuffle node for an unpackl operation.
4624 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4626 unsigned NumElems = VT.getVectorNumElements();
4627 SmallVector<int, 8> Mask;
4628 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4630 Mask.push_back(i + NumElems);
4632 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4635 /// Returns a vector_shuffle node for an unpackh operation.
4636 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4638 unsigned NumElems = VT.getVectorNumElements();
4639 SmallVector<int, 8> Mask;
4640 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4641 Mask.push_back(i + Half);
4642 Mask.push_back(i + NumElems + Half);
4644 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4647 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4648 /// This produces a shuffle where the low element of V2 is swizzled into the
4649 /// zero/undef vector, landing at element Idx.
4650 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4651 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4653 const X86Subtarget *Subtarget,
4654 SelectionDAG &DAG) {
4655 MVT VT = V2.getSimpleValueType();
4657 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4658 unsigned NumElems = VT.getVectorNumElements();
4659 SmallVector<int, 16> MaskVec;
4660 for (unsigned i = 0; i != NumElems; ++i)
4661 // If this is the insertion idx, put the low elt of V2 here.
4662 MaskVec.push_back(i == Idx ? NumElems : i);
4663 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4666 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4667 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4668 /// uses one source. Note that this will set IsUnary for shuffles which use a
4669 /// single input multiple times, and in those cases it will
4670 /// adjust the mask to only have indices within that single input.
4671 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4672 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4673 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4674 unsigned NumElems = VT.getVectorNumElements();
4678 bool IsFakeUnary = false;
4679 switch(N->getOpcode()) {
4680 case X86ISD::BLENDI:
4681 ImmN = N->getOperand(N->getNumOperands()-1);
4682 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4685 ImmN = N->getOperand(N->getNumOperands()-1);
4686 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4687 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4689 case X86ISD::UNPCKH:
4690 DecodeUNPCKHMask(VT, Mask);
4691 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4693 case X86ISD::UNPCKL:
4694 DecodeUNPCKLMask(VT, Mask);
4695 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4697 case X86ISD::MOVHLPS:
4698 DecodeMOVHLPSMask(NumElems, Mask);
4699 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4701 case X86ISD::MOVLHPS:
4702 DecodeMOVLHPSMask(NumElems, Mask);
4703 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4705 case X86ISD::PALIGNR:
4706 ImmN = N->getOperand(N->getNumOperands()-1);
4707 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4709 case X86ISD::PSHUFD:
4710 case X86ISD::VPERMILPI:
4711 ImmN = N->getOperand(N->getNumOperands()-1);
4712 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4715 case X86ISD::PSHUFHW:
4716 ImmN = N->getOperand(N->getNumOperands()-1);
4717 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4720 case X86ISD::PSHUFLW:
4721 ImmN = N->getOperand(N->getNumOperands()-1);
4722 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4725 case X86ISD::PSHUFB: {
4727 SDValue MaskNode = N->getOperand(1);
4728 while (MaskNode->getOpcode() == ISD::BITCAST)
4729 MaskNode = MaskNode->getOperand(0);
4731 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4732 // If we have a build-vector, then things are easy.
4733 MVT VT = MaskNode.getSimpleValueType();
4734 assert(VT.isVector() &&
4735 "Can't produce a non-vector with a build_vector!");
4736 if (!VT.isInteger())
4739 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4741 SmallVector<uint64_t, 32> RawMask;
4742 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4743 SDValue Op = MaskNode->getOperand(i);
4744 if (Op->getOpcode() == ISD::UNDEF) {
4745 RawMask.push_back((uint64_t)SM_SentinelUndef);
4748 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4751 APInt MaskElement = CN->getAPIntValue();
4753 // We now have to decode the element which could be any integer size and
4754 // extract each byte of it.
4755 for (int j = 0; j < NumBytesPerElement; ++j) {
4756 // Note that this is x86 and so always little endian: the low byte is
4757 // the first byte of the mask.
4758 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4759 MaskElement = MaskElement.lshr(8);
4762 DecodePSHUFBMask(RawMask, Mask);
4766 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4770 SDValue Ptr = MaskLoad->getBasePtr();
4771 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4772 Ptr->getOpcode() == X86ISD::WrapperRIP)
4773 Ptr = Ptr->getOperand(0);
4775 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4776 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4779 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4780 DecodePSHUFBMask(C, Mask);
4788 case X86ISD::VPERMI:
4789 ImmN = N->getOperand(N->getNumOperands()-1);
4790 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4795 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4797 case X86ISD::VPERM2X128:
4798 ImmN = N->getOperand(N->getNumOperands()-1);
4799 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4800 if (Mask.empty()) return false;
4801 // Mask only contains negative index if an element is zero.
4802 if (std::any_of(Mask.begin(), Mask.end(),
4803 [](int M){ return M == SM_SentinelZero; }))
4806 case X86ISD::MOVSLDUP:
4807 DecodeMOVSLDUPMask(VT, Mask);
4810 case X86ISD::MOVSHDUP:
4811 DecodeMOVSHDUPMask(VT, Mask);
4814 case X86ISD::MOVDDUP:
4815 DecodeMOVDDUPMask(VT, Mask);
4818 case X86ISD::MOVLHPD:
4819 case X86ISD::MOVLPD:
4820 case X86ISD::MOVLPS:
4821 // Not yet implemented
4823 case X86ISD::VPERMV: {
4825 SDValue MaskNode = N->getOperand(0);
4826 while (MaskNode->getOpcode() == ISD::BITCAST)
4827 MaskNode = MaskNode->getOperand(0);
4829 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4830 SmallVector<uint64_t, 32> RawMask;
4831 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4832 // If we have a build-vector, then things are easy.
4833 assert(MaskNode.getSimpleValueType().isInteger() &&
4834 MaskNode.getSimpleValueType().getVectorNumElements() ==
4835 VT.getVectorNumElements());
4837 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4838 SDValue Op = MaskNode->getOperand(i);
4839 if (Op->getOpcode() == ISD::UNDEF)
4840 RawMask.push_back((uint64_t)SM_SentinelUndef);
4841 else if (isa<ConstantSDNode>(Op)) {
4842 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4843 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4847 DecodeVPERMVMask(RawMask, Mask);
4850 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4851 unsigned NumEltsInMask = MaskNode->getNumOperands();
4852 MaskNode = MaskNode->getOperand(0);
4853 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4855 APInt MaskEltValue = CN->getAPIntValue();
4856 for (unsigned i = 0; i < NumEltsInMask; ++i)
4857 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4858 DecodeVPERMVMask(RawMask, Mask);
4861 // It may be a scalar load
4864 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4868 SDValue Ptr = MaskLoad->getBasePtr();
4869 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4870 Ptr->getOpcode() == X86ISD::WrapperRIP)
4871 Ptr = Ptr->getOperand(0);
4873 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4874 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4877 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4879 DecodeVPERMVMask(C, VT, Mask);
4886 case X86ISD::VPERMV3: {
4888 SDValue MaskNode = N->getOperand(1);
4889 while (MaskNode->getOpcode() == ISD::BITCAST)
4890 MaskNode = MaskNode->getOperand(1);
4892 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4893 // If we have a build-vector, then things are easy.
4894 assert(MaskNode.getSimpleValueType().isInteger() &&
4895 MaskNode.getSimpleValueType().getVectorNumElements() ==
4896 VT.getVectorNumElements());
4898 SmallVector<uint64_t, 32> RawMask;
4899 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4901 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4902 SDValue Op = MaskNode->getOperand(i);
4903 if (Op->getOpcode() == ISD::UNDEF)
4904 RawMask.push_back((uint64_t)SM_SentinelUndef);
4906 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4909 APInt MaskElement = CN->getAPIntValue();
4910 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4913 DecodeVPERMV3Mask(RawMask, Mask);
4917 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4921 SDValue Ptr = MaskLoad->getBasePtr();
4922 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4923 Ptr->getOpcode() == X86ISD::WrapperRIP)
4924 Ptr = Ptr->getOperand(0);
4926 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4927 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4930 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4932 DecodeVPERMV3Mask(C, VT, Mask);
4939 default: llvm_unreachable("unknown target shuffle node");
4942 // If we have a fake unary shuffle, the shuffle mask is spread across two
4943 // inputs that are actually the same node. Re-map the mask to always point
4944 // into the first input.
4947 if (M >= (int)Mask.size())
4953 /// Returns the scalar element that will make up the ith
4954 /// element of the result of the vector shuffle.
4955 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4958 return SDValue(); // Limit search depth.
4960 SDValue V = SDValue(N, 0);
4961 EVT VT = V.getValueType();
4962 unsigned Opcode = V.getOpcode();
4964 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4965 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4966 int Elt = SV->getMaskElt(Index);
4969 return DAG.getUNDEF(VT.getVectorElementType());
4971 unsigned NumElems = VT.getVectorNumElements();
4972 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4973 : SV->getOperand(1);
4974 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4977 // Recurse into target specific vector shuffles to find scalars.
4978 if (isTargetShuffle(Opcode)) {
4979 MVT ShufVT = V.getSimpleValueType();
4980 unsigned NumElems = ShufVT.getVectorNumElements();
4981 SmallVector<int, 16> ShuffleMask;
4984 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4987 int Elt = ShuffleMask[Index];
4989 return DAG.getUNDEF(ShufVT.getVectorElementType());
4991 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4993 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4997 // Actual nodes that may contain scalar elements
4998 if (Opcode == ISD::BITCAST) {
4999 V = V.getOperand(0);
5000 EVT SrcVT = V.getValueType();
5001 unsigned NumElems = VT.getVectorNumElements();
5003 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5007 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5008 return (Index == 0) ? V.getOperand(0)
5009 : DAG.getUNDEF(VT.getVectorElementType());
5011 if (V.getOpcode() == ISD::BUILD_VECTOR)
5012 return V.getOperand(Index);
5017 /// Custom lower build_vector of v16i8.
5018 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5019 unsigned NumNonZero, unsigned NumZero,
5021 const X86Subtarget* Subtarget,
5022 const TargetLowering &TLI) {
5030 // SSE4.1 - use PINSRB to insert each byte directly.
5031 if (Subtarget->hasSSE41()) {
5032 for (unsigned i = 0; i < 16; ++i) {
5033 bool isNonZero = (NonZeros & (1 << i)) != 0;
5037 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5039 V = DAG.getUNDEF(MVT::v16i8);
5042 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5043 MVT::v16i8, V, Op.getOperand(i),
5044 DAG.getIntPtrConstant(i, dl));
5051 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5052 for (unsigned i = 0; i < 16; ++i) {
5053 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5054 if (ThisIsNonZero && First) {
5056 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5058 V = DAG.getUNDEF(MVT::v8i16);
5063 SDValue ThisElt, LastElt;
5064 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5065 if (LastIsNonZero) {
5066 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5067 MVT::i16, Op.getOperand(i-1));
5069 if (ThisIsNonZero) {
5070 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5071 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5072 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5074 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5078 if (ThisElt.getNode())
5079 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5080 DAG.getIntPtrConstant(i/2, dl));
5084 return DAG.getBitcast(MVT::v16i8, V);
5087 /// Custom lower build_vector of v8i16.
5088 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5089 unsigned NumNonZero, unsigned NumZero,
5091 const X86Subtarget* Subtarget,
5092 const TargetLowering &TLI) {
5099 for (unsigned i = 0; i < 8; ++i) {
5100 bool isNonZero = (NonZeros & (1 << i)) != 0;
5104 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5106 V = DAG.getUNDEF(MVT::v8i16);
5109 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5110 MVT::v8i16, V, Op.getOperand(i),
5111 DAG.getIntPtrConstant(i, dl));
5118 /// Custom lower build_vector of v4i32 or v4f32.
5119 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5120 const X86Subtarget *Subtarget,
5121 const TargetLowering &TLI) {
5122 // Find all zeroable elements.
5123 std::bitset<4> Zeroable;
5124 for (int i=0; i < 4; ++i) {
5125 SDValue Elt = Op->getOperand(i);
5126 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5128 assert(Zeroable.size() - Zeroable.count() > 1 &&
5129 "We expect at least two non-zero elements!");
5131 // We only know how to deal with build_vector nodes where elements are either
5132 // zeroable or extract_vector_elt with constant index.
5133 SDValue FirstNonZero;
5134 unsigned FirstNonZeroIdx;
5135 for (unsigned i=0; i < 4; ++i) {
5138 SDValue Elt = Op->getOperand(i);
5139 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5140 !isa<ConstantSDNode>(Elt.getOperand(1)))
5142 // Make sure that this node is extracting from a 128-bit vector.
5143 MVT VT = Elt.getOperand(0).getSimpleValueType();
5144 if (!VT.is128BitVector())
5146 if (!FirstNonZero.getNode()) {
5148 FirstNonZeroIdx = i;
5152 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5153 SDValue V1 = FirstNonZero.getOperand(0);
5154 MVT VT = V1.getSimpleValueType();
5156 // See if this build_vector can be lowered as a blend with zero.
5158 unsigned EltMaskIdx, EltIdx;
5160 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5161 if (Zeroable[EltIdx]) {
5162 // The zero vector will be on the right hand side.
5163 Mask[EltIdx] = EltIdx+4;
5167 Elt = Op->getOperand(EltIdx);
5168 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5169 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5170 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5172 Mask[EltIdx] = EltIdx;
5176 // Let the shuffle legalizer deal with blend operations.
5177 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5178 if (V1.getSimpleValueType() != VT)
5179 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5180 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5183 // See if we can lower this build_vector to a INSERTPS.
5184 if (!Subtarget->hasSSE41())
5187 SDValue V2 = Elt.getOperand(0);
5188 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5191 bool CanFold = true;
5192 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5196 SDValue Current = Op->getOperand(i);
5197 SDValue SrcVector = Current->getOperand(0);
5200 CanFold = SrcVector == V1 &&
5201 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5207 assert(V1.getNode() && "Expected at least two non-zero elements!");
5208 if (V1.getSimpleValueType() != MVT::v4f32)
5209 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5210 if (V2.getSimpleValueType() != MVT::v4f32)
5211 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5213 // Ok, we can emit an INSERTPS instruction.
5214 unsigned ZMask = Zeroable.to_ulong();
5216 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5217 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5219 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5220 DAG.getIntPtrConstant(InsertPSMask, DL));
5221 return DAG.getBitcast(VT, Result);
5224 /// Return a vector logical shift node.
5225 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5226 unsigned NumBits, SelectionDAG &DAG,
5227 const TargetLowering &TLI, SDLoc dl) {
5228 assert(VT.is128BitVector() && "Unknown type for VShift");
5229 MVT ShVT = MVT::v2i64;
5230 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5231 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5232 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5233 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5234 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5235 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5239 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5241 // Check if the scalar load can be widened into a vector load. And if
5242 // the address is "base + cst" see if the cst can be "absorbed" into
5243 // the shuffle mask.
5244 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5245 SDValue Ptr = LD->getBasePtr();
5246 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5248 EVT PVT = LD->getValueType(0);
5249 if (PVT != MVT::i32 && PVT != MVT::f32)
5254 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5255 FI = FINode->getIndex();
5257 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5258 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5259 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5260 Offset = Ptr.getConstantOperandVal(1);
5261 Ptr = Ptr.getOperand(0);
5266 // FIXME: 256-bit vector instructions don't require a strict alignment,
5267 // improve this code to support it better.
5268 unsigned RequiredAlign = VT.getSizeInBits()/8;
5269 SDValue Chain = LD->getChain();
5270 // Make sure the stack object alignment is at least 16 or 32.
5271 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5272 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5273 if (MFI->isFixedObjectIndex(FI)) {
5274 // Can't change the alignment. FIXME: It's possible to compute
5275 // the exact stack offset and reference FI + adjust offset instead.
5276 // If someone *really* cares about this. That's the way to implement it.
5279 MFI->setObjectAlignment(FI, RequiredAlign);
5283 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5284 // Ptr + (Offset & ~15).
5287 if ((Offset % RequiredAlign) & 3)
5289 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5292 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5293 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5296 int EltNo = (Offset - StartOffset) >> 2;
5297 unsigned NumElems = VT.getVectorNumElements();
5299 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5300 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5301 LD->getPointerInfo().getWithOffset(StartOffset),
5302 false, false, false, 0);
5304 SmallVector<int, 8> Mask(NumElems, EltNo);
5306 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5312 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5313 /// elements can be replaced by a single large load which has the same value as
5314 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5316 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5318 /// FIXME: we'd also like to handle the case where the last elements are zero
5319 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5320 /// There's even a handy isZeroNode for that purpose.
5321 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5322 SDLoc &DL, SelectionDAG &DAG,
5323 bool isAfterLegalize) {
5324 unsigned NumElems = Elts.size();
5326 LoadSDNode *LDBase = nullptr;
5327 unsigned LastLoadedElt = -1U;
5329 // For each element in the initializer, see if we've found a load or an undef.
5330 // If we don't find an initial load element, or later load elements are
5331 // non-consecutive, bail out.
5332 for (unsigned i = 0; i < NumElems; ++i) {
5333 SDValue Elt = Elts[i];
5334 // Look through a bitcast.
5335 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5336 Elt = Elt.getOperand(0);
5337 if (!Elt.getNode() ||
5338 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5341 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5343 LDBase = cast<LoadSDNode>(Elt.getNode());
5347 if (Elt.getOpcode() == ISD::UNDEF)
5350 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5351 EVT LdVT = Elt.getValueType();
5352 // Each loaded element must be the correct fractional portion of the
5353 // requested vector load.
5354 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5356 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5361 // If we have found an entire vector of loads and undefs, then return a large
5362 // load of the entire vector width starting at the base pointer. If we found
5363 // consecutive loads for the low half, generate a vzext_load node.
5364 if (LastLoadedElt == NumElems - 1) {
5365 assert(LDBase && "Did not find base load for merging consecutive loads");
5366 EVT EltVT = LDBase->getValueType(0);
5367 // Ensure that the input vector size for the merged loads matches the
5368 // cumulative size of the input elements.
5369 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5372 if (isAfterLegalize &&
5373 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5376 SDValue NewLd = SDValue();
5378 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5379 LDBase->getPointerInfo(), LDBase->isVolatile(),
5380 LDBase->isNonTemporal(), LDBase->isInvariant(),
5381 LDBase->getAlignment());
5383 if (LDBase->hasAnyUseOfValue(1)) {
5384 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5386 SDValue(NewLd.getNode(), 1));
5387 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5388 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5389 SDValue(NewLd.getNode(), 1));
5395 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5396 //of a v4i32 / v4f32. It's probably worth generalizing.
5397 EVT EltVT = VT.getVectorElementType();
5398 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5399 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5400 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5401 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5403 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5404 LDBase->getPointerInfo(),
5405 LDBase->getAlignment(),
5406 false/*isVolatile*/, true/*ReadMem*/,
5409 // Make sure the newly-created LOAD is in the same position as LDBase in
5410 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5411 // update uses of LDBase's output chain to use the TokenFactor.
5412 if (LDBase->hasAnyUseOfValue(1)) {
5413 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5414 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5415 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5416 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5417 SDValue(ResNode.getNode(), 1));
5420 return DAG.getBitcast(VT, ResNode);
5425 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5426 /// to generate a splat value for the following cases:
5427 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5428 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5429 /// a scalar load, or a constant.
5430 /// The VBROADCAST node is returned when a pattern is found,
5431 /// or SDValue() otherwise.
5432 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5433 SelectionDAG &DAG) {
5434 // VBROADCAST requires AVX.
5435 // TODO: Splats could be generated for non-AVX CPUs using SSE
5436 // instructions, but there's less potential gain for only 128-bit vectors.
5437 if (!Subtarget->hasAVX())
5440 MVT VT = Op.getSimpleValueType();
5443 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5444 "Unsupported vector type for broadcast.");
5449 switch (Op.getOpcode()) {
5451 // Unknown pattern found.
5454 case ISD::BUILD_VECTOR: {
5455 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5456 BitVector UndefElements;
5457 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5459 // We need a splat of a single value to use broadcast, and it doesn't
5460 // make any sense if the value is only in one element of the vector.
5461 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5465 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5466 Ld.getOpcode() == ISD::ConstantFP);
5468 // Make sure that all of the users of a non-constant load are from the
5469 // BUILD_VECTOR node.
5470 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5475 case ISD::VECTOR_SHUFFLE: {
5476 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5478 // Shuffles must have a splat mask where the first element is
5480 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5483 SDValue Sc = Op.getOperand(0);
5484 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5485 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5487 if (!Subtarget->hasInt256())
5490 // Use the register form of the broadcast instruction available on AVX2.
5491 if (VT.getSizeInBits() >= 256)
5492 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5493 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5496 Ld = Sc.getOperand(0);
5497 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5498 Ld.getOpcode() == ISD::ConstantFP);
5500 // The scalar_to_vector node and the suspected
5501 // load node must have exactly one user.
5502 // Constants may have multiple users.
5504 // AVX-512 has register version of the broadcast
5505 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5506 Ld.getValueType().getSizeInBits() >= 32;
5507 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5514 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5515 bool IsGE256 = (VT.getSizeInBits() >= 256);
5517 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5518 // instruction to save 8 or more bytes of constant pool data.
5519 // TODO: If multiple splats are generated to load the same constant,
5520 // it may be detrimental to overall size. There needs to be a way to detect
5521 // that condition to know if this is truly a size win.
5522 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5524 // Handle broadcasting a single constant scalar from the constant pool
5526 // On Sandybridge (no AVX2), it is still better to load a constant vector
5527 // from the constant pool and not to broadcast it from a scalar.
5528 // But override that restriction when optimizing for size.
5529 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5530 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5531 EVT CVT = Ld.getValueType();
5532 assert(!CVT.isVector() && "Must not broadcast a vector type");
5534 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5535 // For size optimization, also splat v2f64 and v2i64, and for size opt
5536 // with AVX2, also splat i8 and i16.
5537 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5538 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5539 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5540 const Constant *C = nullptr;
5541 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5542 C = CI->getConstantIntValue();
5543 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5544 C = CF->getConstantFPValue();
5546 assert(C && "Invalid constant type");
5548 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5550 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5551 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5553 CVT, dl, DAG.getEntryNode(), CP,
5554 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5555 false, false, Alignment);
5557 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5561 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5563 // Handle AVX2 in-register broadcasts.
5564 if (!IsLoad && Subtarget->hasInt256() &&
5565 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5566 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5568 // The scalar source must be a normal load.
5572 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5573 (Subtarget->hasVLX() && ScalarSize == 64))
5574 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5576 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5577 // double since there is no vbroadcastsd xmm
5578 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5579 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5580 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5583 // Unsupported broadcast.
5587 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5588 /// underlying vector and index.
5590 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5592 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5594 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5595 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5598 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5600 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5602 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5603 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5606 // In this case the vector is the extract_subvector expression and the index
5607 // is 2, as specified by the shuffle.
5608 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5609 SDValue ShuffleVec = SVOp->getOperand(0);
5610 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5611 assert(ShuffleVecVT.getVectorElementType() ==
5612 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5614 int ShuffleIdx = SVOp->getMaskElt(Idx);
5615 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5616 ExtractedFromVec = ShuffleVec;
5622 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5623 MVT VT = Op.getSimpleValueType();
5625 // Skip if insert_vec_elt is not supported.
5626 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5627 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5631 unsigned NumElems = Op.getNumOperands();
5635 SmallVector<unsigned, 4> InsertIndices;
5636 SmallVector<int, 8> Mask(NumElems, -1);
5638 for (unsigned i = 0; i != NumElems; ++i) {
5639 unsigned Opc = Op.getOperand(i).getOpcode();
5641 if (Opc == ISD::UNDEF)
5644 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5645 // Quit if more than 1 elements need inserting.
5646 if (InsertIndices.size() > 1)
5649 InsertIndices.push_back(i);
5653 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5654 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5655 // Quit if non-constant index.
5656 if (!isa<ConstantSDNode>(ExtIdx))
5658 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5660 // Quit if extracted from vector of different type.
5661 if (ExtractedFromVec.getValueType() != VT)
5664 if (!VecIn1.getNode())
5665 VecIn1 = ExtractedFromVec;
5666 else if (VecIn1 != ExtractedFromVec) {
5667 if (!VecIn2.getNode())
5668 VecIn2 = ExtractedFromVec;
5669 else if (VecIn2 != ExtractedFromVec)
5670 // Quit if more than 2 vectors to shuffle
5674 if (ExtractedFromVec == VecIn1)
5676 else if (ExtractedFromVec == VecIn2)
5677 Mask[i] = Idx + NumElems;
5680 if (!VecIn1.getNode())
5683 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5684 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5685 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5686 unsigned Idx = InsertIndices[i];
5687 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5688 DAG.getIntPtrConstant(Idx, DL));
5694 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5695 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5696 Op.getScalarValueSizeInBits() == 1 &&
5697 "Can not convert non-constant vector");
5698 uint64_t Immediate = 0;
5699 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5700 SDValue In = Op.getOperand(idx);
5701 if (In.getOpcode() != ISD::UNDEF)
5702 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5706 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5707 return DAG.getConstant(Immediate, dl, VT);
5709 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5711 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5713 MVT VT = Op.getSimpleValueType();
5714 assert((VT.getVectorElementType() == MVT::i1) &&
5715 "Unexpected type in LowerBUILD_VECTORvXi1!");
5718 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5719 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5720 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5721 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5724 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5725 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5726 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5727 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5730 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5731 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5732 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5733 return DAG.getBitcast(VT, Imm);
5734 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5735 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5736 DAG.getIntPtrConstant(0, dl));
5739 // Vector has one or more non-const elements
5740 uint64_t Immediate = 0;
5741 SmallVector<unsigned, 16> NonConstIdx;
5742 bool IsSplat = true;
5743 bool HasConstElts = false;
5745 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5746 SDValue In = Op.getOperand(idx);
5747 if (In.getOpcode() == ISD::UNDEF)
5749 if (!isa<ConstantSDNode>(In))
5750 NonConstIdx.push_back(idx);
5752 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5753 HasConstElts = true;
5757 else if (In != Op.getOperand(SplatIdx))
5761 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5763 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5764 DAG.getConstant(1, dl, VT),
5765 DAG.getConstant(0, dl, VT));
5767 // insert elements one by one
5771 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5772 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5774 else if (HasConstElts)
5775 Imm = DAG.getConstant(0, dl, VT);
5777 Imm = DAG.getUNDEF(VT);
5778 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5779 DstVec = DAG.getBitcast(VT, Imm);
5781 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5782 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5783 DAG.getIntPtrConstant(0, dl));
5786 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5787 unsigned InsertIdx = NonConstIdx[i];
5788 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5789 Op.getOperand(InsertIdx),
5790 DAG.getIntPtrConstant(InsertIdx, dl));
5795 /// \brief Return true if \p N implements a horizontal binop and return the
5796 /// operands for the horizontal binop into V0 and V1.
5798 /// This is a helper function of LowerToHorizontalOp().
5799 /// This function checks that the build_vector \p N in input implements a
5800 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5801 /// operation to match.
5802 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5803 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5804 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5807 /// This function only analyzes elements of \p N whose indices are
5808 /// in range [BaseIdx, LastIdx).
5809 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5811 unsigned BaseIdx, unsigned LastIdx,
5812 SDValue &V0, SDValue &V1) {
5813 EVT VT = N->getValueType(0);
5815 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5816 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5817 "Invalid Vector in input!");
5819 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5820 bool CanFold = true;
5821 unsigned ExpectedVExtractIdx = BaseIdx;
5822 unsigned NumElts = LastIdx - BaseIdx;
5823 V0 = DAG.getUNDEF(VT);
5824 V1 = DAG.getUNDEF(VT);
5826 // Check if N implements a horizontal binop.
5827 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5828 SDValue Op = N->getOperand(i + BaseIdx);
5831 if (Op->getOpcode() == ISD::UNDEF) {
5832 // Update the expected vector extract index.
5833 if (i * 2 == NumElts)
5834 ExpectedVExtractIdx = BaseIdx;
5835 ExpectedVExtractIdx += 2;
5839 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5844 SDValue Op0 = Op.getOperand(0);
5845 SDValue Op1 = Op.getOperand(1);
5847 // Try to match the following pattern:
5848 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5849 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5850 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5851 Op0.getOperand(0) == Op1.getOperand(0) &&
5852 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5853 isa<ConstantSDNode>(Op1.getOperand(1)));
5857 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5858 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5860 if (i * 2 < NumElts) {
5861 if (V0.getOpcode() == ISD::UNDEF) {
5862 V0 = Op0.getOperand(0);
5863 if (V0.getValueType() != VT)
5867 if (V1.getOpcode() == ISD::UNDEF) {
5868 V1 = Op0.getOperand(0);
5869 if (V1.getValueType() != VT)
5872 if (i * 2 == NumElts)
5873 ExpectedVExtractIdx = BaseIdx;
5876 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5877 if (I0 == ExpectedVExtractIdx)
5878 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5879 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5880 // Try to match the following dag sequence:
5881 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5882 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5886 ExpectedVExtractIdx += 2;
5892 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5893 /// a concat_vector.
5895 /// This is a helper function of LowerToHorizontalOp().
5896 /// This function expects two 256-bit vectors called V0 and V1.
5897 /// At first, each vector is split into two separate 128-bit vectors.
5898 /// Then, the resulting 128-bit vectors are used to implement two
5899 /// horizontal binary operations.
5901 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5903 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5904 /// the two new horizontal binop.
5905 /// When Mode is set, the first horizontal binop dag node would take as input
5906 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5907 /// horizontal binop dag node would take as input the lower 128-bit of V1
5908 /// and the upper 128-bit of V1.
5910 /// HADD V0_LO, V0_HI
5911 /// HADD V1_LO, V1_HI
5913 /// Otherwise, the first horizontal binop dag node takes as input the lower
5914 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5915 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5917 /// HADD V0_LO, V1_LO
5918 /// HADD V0_HI, V1_HI
5920 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5921 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5922 /// the upper 128-bits of the result.
5923 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5924 SDLoc DL, SelectionDAG &DAG,
5925 unsigned X86Opcode, bool Mode,
5926 bool isUndefLO, bool isUndefHI) {
5927 EVT VT = V0.getValueType();
5928 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5929 "Invalid nodes in input!");
5931 unsigned NumElts = VT.getVectorNumElements();
5932 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5933 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5934 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5935 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5936 EVT NewVT = V0_LO.getValueType();
5938 SDValue LO = DAG.getUNDEF(NewVT);
5939 SDValue HI = DAG.getUNDEF(NewVT);
5942 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5943 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5944 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5945 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5946 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5948 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5949 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5950 V1_LO->getOpcode() != ISD::UNDEF))
5951 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5953 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5954 V1_HI->getOpcode() != ISD::UNDEF))
5955 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5958 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5961 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5963 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5964 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5965 MVT VT = BV->getSimpleValueType(0);
5966 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5967 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5971 unsigned NumElts = VT.getVectorNumElements();
5972 SDValue InVec0 = DAG.getUNDEF(VT);
5973 SDValue InVec1 = DAG.getUNDEF(VT);
5975 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5976 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5978 // Odd-numbered elements in the input build vector are obtained from
5979 // adding two integer/float elements.
5980 // Even-numbered elements in the input build vector are obtained from
5981 // subtracting two integer/float elements.
5982 unsigned ExpectedOpcode = ISD::FSUB;
5983 unsigned NextExpectedOpcode = ISD::FADD;
5984 bool AddFound = false;
5985 bool SubFound = false;
5987 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5988 SDValue Op = BV->getOperand(i);
5990 // Skip 'undef' values.
5991 unsigned Opcode = Op.getOpcode();
5992 if (Opcode == ISD::UNDEF) {
5993 std::swap(ExpectedOpcode, NextExpectedOpcode);
5997 // Early exit if we found an unexpected opcode.
5998 if (Opcode != ExpectedOpcode)
6001 SDValue Op0 = Op.getOperand(0);
6002 SDValue Op1 = Op.getOperand(1);
6004 // Try to match the following pattern:
6005 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6006 // Early exit if we cannot match that sequence.
6007 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6008 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6009 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6010 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6011 Op0.getOperand(1) != Op1.getOperand(1))
6014 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6018 // We found a valid add/sub node. Update the information accordingly.
6024 // Update InVec0 and InVec1.
6025 if (InVec0.getOpcode() == ISD::UNDEF) {
6026 InVec0 = Op0.getOperand(0);
6027 if (InVec0.getSimpleValueType() != VT)
6030 if (InVec1.getOpcode() == ISD::UNDEF) {
6031 InVec1 = Op1.getOperand(0);
6032 if (InVec1.getSimpleValueType() != VT)
6036 // Make sure that operands in input to each add/sub node always
6037 // come from a same pair of vectors.
6038 if (InVec0 != Op0.getOperand(0)) {
6039 if (ExpectedOpcode == ISD::FSUB)
6042 // FADD is commutable. Try to commute the operands
6043 // and then test again.
6044 std::swap(Op0, Op1);
6045 if (InVec0 != Op0.getOperand(0))
6049 if (InVec1 != Op1.getOperand(0))
6052 // Update the pair of expected opcodes.
6053 std::swap(ExpectedOpcode, NextExpectedOpcode);
6056 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6057 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6058 InVec1.getOpcode() != ISD::UNDEF)
6059 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6064 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6065 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6066 const X86Subtarget *Subtarget,
6067 SelectionDAG &DAG) {
6068 MVT VT = BV->getSimpleValueType(0);
6069 unsigned NumElts = VT.getVectorNumElements();
6070 unsigned NumUndefsLO = 0;
6071 unsigned NumUndefsHI = 0;
6072 unsigned Half = NumElts/2;
6074 // Count the number of UNDEF operands in the build_vector in input.
6075 for (unsigned i = 0, e = Half; i != e; ++i)
6076 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6079 for (unsigned i = Half, e = NumElts; i != e; ++i)
6080 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6083 // Early exit if this is either a build_vector of all UNDEFs or all the
6084 // operands but one are UNDEF.
6085 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6089 SDValue InVec0, InVec1;
6090 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6091 // Try to match an SSE3 float HADD/HSUB.
6092 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6093 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6095 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6096 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6097 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6098 // Try to match an SSSE3 integer HADD/HSUB.
6099 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6100 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6102 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6103 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6106 if (!Subtarget->hasAVX())
6109 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6110 // Try to match an AVX horizontal add/sub of packed single/double
6111 // precision floating point values from 256-bit vectors.
6112 SDValue InVec2, InVec3;
6113 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6114 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6115 ((InVec0.getOpcode() == ISD::UNDEF ||
6116 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6117 ((InVec1.getOpcode() == ISD::UNDEF ||
6118 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6119 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6121 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6122 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6123 ((InVec0.getOpcode() == ISD::UNDEF ||
6124 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6125 ((InVec1.getOpcode() == ISD::UNDEF ||
6126 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6127 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6128 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6129 // Try to match an AVX2 horizontal add/sub of signed integers.
6130 SDValue InVec2, InVec3;
6132 bool CanFold = true;
6134 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6135 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6136 ((InVec0.getOpcode() == ISD::UNDEF ||
6137 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6138 ((InVec1.getOpcode() == ISD::UNDEF ||
6139 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6140 X86Opcode = X86ISD::HADD;
6141 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6142 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6143 ((InVec0.getOpcode() == ISD::UNDEF ||
6144 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6145 ((InVec1.getOpcode() == ISD::UNDEF ||
6146 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6147 X86Opcode = X86ISD::HSUB;
6152 // Fold this build_vector into a single horizontal add/sub.
6153 // Do this only if the target has AVX2.
6154 if (Subtarget->hasAVX2())
6155 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6157 // Do not try to expand this build_vector into a pair of horizontal
6158 // add/sub if we can emit a pair of scalar add/sub.
6159 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6162 // Convert this build_vector into a pair of horizontal binop followed by
6164 bool isUndefLO = NumUndefsLO == Half;
6165 bool isUndefHI = NumUndefsHI == Half;
6166 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6167 isUndefLO, isUndefHI);
6171 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6172 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6174 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6175 X86Opcode = X86ISD::HADD;
6176 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6177 X86Opcode = X86ISD::HSUB;
6178 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6179 X86Opcode = X86ISD::FHADD;
6180 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6181 X86Opcode = X86ISD::FHSUB;
6185 // Don't try to expand this build_vector into a pair of horizontal add/sub
6186 // if we can simply emit a pair of scalar add/sub.
6187 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6190 // Convert this build_vector into two horizontal add/sub followed by
6192 bool isUndefLO = NumUndefsLO == Half;
6193 bool isUndefHI = NumUndefsHI == Half;
6194 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6195 isUndefLO, isUndefHI);
6202 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6205 MVT VT = Op.getSimpleValueType();
6206 MVT ExtVT = VT.getVectorElementType();
6207 unsigned NumElems = Op.getNumOperands();
6209 // Generate vectors for predicate vectors.
6210 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6211 return LowerBUILD_VECTORvXi1(Op, DAG);
6213 // Vectors containing all zeros can be matched by pxor and xorps later
6214 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6215 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6216 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6217 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6220 return getZeroVector(VT, Subtarget, DAG, dl);
6223 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6224 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6225 // vpcmpeqd on 256-bit vectors.
6226 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6227 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6230 if (!VT.is512BitVector())
6231 return getOnesVector(VT, Subtarget, DAG, dl);
6234 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6235 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6237 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6238 return HorizontalOp;
6239 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6242 unsigned EVTBits = ExtVT.getSizeInBits();
6244 unsigned NumZero = 0;
6245 unsigned NumNonZero = 0;
6246 unsigned NonZeros = 0;
6247 bool IsAllConstants = true;
6248 SmallSet<SDValue, 8> Values;
6249 for (unsigned i = 0; i < NumElems; ++i) {
6250 SDValue Elt = Op.getOperand(i);
6251 if (Elt.getOpcode() == ISD::UNDEF)
6254 if (Elt.getOpcode() != ISD::Constant &&
6255 Elt.getOpcode() != ISD::ConstantFP)
6256 IsAllConstants = false;
6257 if (X86::isZeroNode(Elt))
6260 NonZeros |= (1 << i);
6265 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6266 if (NumNonZero == 0)
6267 return DAG.getUNDEF(VT);
6269 // Special case for single non-zero, non-undef, element.
6270 if (NumNonZero == 1) {
6271 unsigned Idx = countTrailingZeros(NonZeros);
6272 SDValue Item = Op.getOperand(Idx);
6274 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6275 // the value are obviously zero, truncate the value to i32 and do the
6276 // insertion that way. Only do this if the value is non-constant or if the
6277 // value is a constant being inserted into element 0. It is cheaper to do
6278 // a constant pool load than it is to do a movd + shuffle.
6279 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6280 (!IsAllConstants || Idx == 0)) {
6281 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6283 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6284 MVT VecVT = MVT::v4i32;
6286 // Truncate the value (which may itself be a constant) to i32, and
6287 // convert it to a vector with movd (S2V+shuffle to zero extend).
6288 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6289 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6290 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6291 Item, Idx * 2, true, Subtarget, DAG));
6295 // If we have a constant or non-constant insertion into the low element of
6296 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6297 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6298 // depending on what the source datatype is.
6301 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6303 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6304 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6305 if (VT.is512BitVector()) {
6306 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6307 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6308 Item, DAG.getIntPtrConstant(0, dl));
6310 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6311 "Expected an SSE value type!");
6312 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6313 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6314 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6317 // We can't directly insert an i8 or i16 into a vector, so zero extend
6319 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6320 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6321 if (VT.is256BitVector()) {
6322 if (Subtarget->hasAVX()) {
6323 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6324 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6326 // Without AVX, we need to extend to a 128-bit vector and then
6327 // insert into the 256-bit vector.
6328 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6329 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6330 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6333 assert(VT.is128BitVector() && "Expected an SSE value type!");
6334 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6335 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6337 return DAG.getBitcast(VT, Item);
6341 // Is it a vector logical left shift?
6342 if (NumElems == 2 && Idx == 1 &&
6343 X86::isZeroNode(Op.getOperand(0)) &&
6344 !X86::isZeroNode(Op.getOperand(1))) {
6345 unsigned NumBits = VT.getSizeInBits();
6346 return getVShift(true, VT,
6347 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6348 VT, Op.getOperand(1)),
6349 NumBits/2, DAG, *this, dl);
6352 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6355 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6356 // is a non-constant being inserted into an element other than the low one,
6357 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6358 // movd/movss) to move this into the low element, then shuffle it into
6360 if (EVTBits == 32) {
6361 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6362 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6366 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6367 if (Values.size() == 1) {
6368 if (EVTBits == 32) {
6369 // Instead of a shuffle like this:
6370 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6371 // Check if it's possible to issue this instead.
6372 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6373 unsigned Idx = countTrailingZeros(NonZeros);
6374 SDValue Item = Op.getOperand(Idx);
6375 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6376 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6381 // A vector full of immediates; various special cases are already
6382 // handled, so this is best done with a single constant-pool load.
6386 // For AVX-length vectors, see if we can use a vector load to get all of the
6387 // elements, otherwise build the individual 128-bit pieces and use
6388 // shuffles to put them in place.
6389 if (VT.is256BitVector() || VT.is512BitVector()) {
6390 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6392 // Check for a build vector of consecutive loads.
6393 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6396 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6398 // Build both the lower and upper subvector.
6399 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6400 makeArrayRef(&V[0], NumElems/2));
6401 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6402 makeArrayRef(&V[NumElems / 2], NumElems/2));
6404 // Recreate the wider vector with the lower and upper part.
6405 if (VT.is256BitVector())
6406 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6407 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6410 // Let legalizer expand 2-wide build_vectors.
6411 if (EVTBits == 64) {
6412 if (NumNonZero == 1) {
6413 // One half is zero or undef.
6414 unsigned Idx = countTrailingZeros(NonZeros);
6415 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6416 Op.getOperand(Idx));
6417 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6422 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6423 if (EVTBits == 8 && NumElems == 16)
6424 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6425 DAG, Subtarget, *this))
6428 if (EVTBits == 16 && NumElems == 8)
6429 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6430 DAG, Subtarget, *this))
6433 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6434 if (EVTBits == 32 && NumElems == 4)
6435 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6438 // If element VT is == 32 bits, turn it into a number of shuffles.
6439 SmallVector<SDValue, 8> V(NumElems);
6440 if (NumElems == 4 && NumZero > 0) {
6441 for (unsigned i = 0; i < 4; ++i) {
6442 bool isZero = !(NonZeros & (1 << i));
6444 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6446 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6449 for (unsigned i = 0; i < 2; ++i) {
6450 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6453 V[i] = V[i*2]; // Must be a zero vector.
6456 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6459 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6462 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6467 bool Reverse1 = (NonZeros & 0x3) == 2;
6468 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6472 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6473 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6475 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6478 if (Values.size() > 1 && VT.is128BitVector()) {
6479 // Check for a build vector of consecutive loads.
6480 for (unsigned i = 0; i < NumElems; ++i)
6481 V[i] = Op.getOperand(i);
6483 // Check for elements which are consecutive loads.
6484 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6487 // Check for a build vector from mostly shuffle plus few inserting.
6488 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6491 // For SSE 4.1, use insertps to put the high elements into the low element.
6492 if (Subtarget->hasSSE41()) {
6494 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6495 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6497 Result = DAG.getUNDEF(VT);
6499 for (unsigned i = 1; i < NumElems; ++i) {
6500 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6501 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6502 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6507 // Otherwise, expand into a number of unpckl*, start by extending each of
6508 // our (non-undef) elements to the full vector width with the element in the
6509 // bottom slot of the vector (which generates no code for SSE).
6510 for (unsigned i = 0; i < NumElems; ++i) {
6511 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6512 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6514 V[i] = DAG.getUNDEF(VT);
6517 // Next, we iteratively mix elements, e.g. for v4f32:
6518 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6519 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6520 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6521 unsigned EltStride = NumElems >> 1;
6522 while (EltStride != 0) {
6523 for (unsigned i = 0; i < EltStride; ++i) {
6524 // If V[i+EltStride] is undef and this is the first round of mixing,
6525 // then it is safe to just drop this shuffle: V[i] is already in the
6526 // right place, the one element (since it's the first round) being
6527 // inserted as undef can be dropped. This isn't safe for successive
6528 // rounds because they will permute elements within both vectors.
6529 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6530 EltStride == NumElems/2)
6533 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6542 // 256-bit AVX can use the vinsertf128 instruction
6543 // to create 256-bit vectors from two other 128-bit ones.
6544 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6546 MVT ResVT = Op.getSimpleValueType();
6548 assert((ResVT.is256BitVector() ||
6549 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6551 SDValue V1 = Op.getOperand(0);
6552 SDValue V2 = Op.getOperand(1);
6553 unsigned NumElems = ResVT.getVectorNumElements();
6554 if (ResVT.is256BitVector())
6555 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6557 if (Op.getNumOperands() == 4) {
6558 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6559 ResVT.getVectorNumElements()/2);
6560 SDValue V3 = Op.getOperand(2);
6561 SDValue V4 = Op.getOperand(3);
6562 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6563 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6565 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6568 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6569 const X86Subtarget *Subtarget,
6570 SelectionDAG & DAG) {
6572 MVT ResVT = Op.getSimpleValueType();
6573 unsigned NumOfOperands = Op.getNumOperands();
6575 assert(isPowerOf2_32(NumOfOperands) &&
6576 "Unexpected number of operands in CONCAT_VECTORS");
6578 SDValue Undef = DAG.getUNDEF(ResVT);
6579 if (NumOfOperands > 2) {
6580 // Specialize the cases when all, or all but one, of the operands are undef.
6581 unsigned NumOfDefinedOps = 0;
6583 for (unsigned i = 0; i < NumOfOperands; i++)
6584 if (!Op.getOperand(i).isUndef()) {
6588 if (NumOfDefinedOps == 0)
6590 if (NumOfDefinedOps == 1) {
6591 unsigned SubVecNumElts =
6592 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6593 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6594 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6595 Op.getOperand(OpIdx), IdxVal);
6598 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6599 ResVT.getVectorNumElements()/2);
6600 SmallVector<SDValue, 2> Ops;
6601 for (unsigned i = 0; i < NumOfOperands/2; i++)
6602 Ops.push_back(Op.getOperand(i));
6603 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6605 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6606 Ops.push_back(Op.getOperand(i));
6607 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6608 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6612 SDValue V1 = Op.getOperand(0);
6613 SDValue V2 = Op.getOperand(1);
6614 unsigned NumElems = ResVT.getVectorNumElements();
6615 assert(V1.getValueType() == V2.getValueType() &&
6616 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6617 "Unexpected operands in CONCAT_VECTORS");
6619 if (ResVT.getSizeInBits() >= 16)
6620 return Op; // The operation is legal with KUNPCK
6622 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6623 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6624 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6625 if (IsZeroV1 && IsZeroV2)
6628 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6630 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6632 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6634 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6636 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6639 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6641 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6642 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6645 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6646 const X86Subtarget *Subtarget,
6647 SelectionDAG &DAG) {
6648 MVT VT = Op.getSimpleValueType();
6649 if (VT.getVectorElementType() == MVT::i1)
6650 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6652 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6653 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6654 Op.getNumOperands() == 4)));
6656 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6657 // from two other 128-bit ones.
6659 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6660 return LowerAVXCONCAT_VECTORS(Op, DAG);
6663 //===----------------------------------------------------------------------===//
6664 // Vector shuffle lowering
6666 // This is an experimental code path for lowering vector shuffles on x86. It is
6667 // designed to handle arbitrary vector shuffles and blends, gracefully
6668 // degrading performance as necessary. It works hard to recognize idiomatic
6669 // shuffles and lower them to optimal instruction patterns without leaving
6670 // a framework that allows reasonably efficient handling of all vector shuffle
6672 //===----------------------------------------------------------------------===//
6674 /// \brief Tiny helper function to identify a no-op mask.
6676 /// This is a somewhat boring predicate function. It checks whether the mask
6677 /// array input, which is assumed to be a single-input shuffle mask of the kind
6678 /// used by the X86 shuffle instructions (not a fully general
6679 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6680 /// in-place shuffle are 'no-op's.
6681 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6682 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6683 if (Mask[i] != -1 && Mask[i] != i)
6688 /// \brief Helper function to classify a mask as a single-input mask.
6690 /// This isn't a generic single-input test because in the vector shuffle
6691 /// lowering we canonicalize single inputs to be the first input operand. This
6692 /// means we can more quickly test for a single input by only checking whether
6693 /// an input from the second operand exists. We also assume that the size of
6694 /// mask corresponds to the size of the input vectors which isn't true in the
6695 /// fully general case.
6696 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6698 if (M >= (int)Mask.size())
6703 /// \brief Test whether there are elements crossing 128-bit lanes in this
6706 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6707 /// and we routinely test for these.
6708 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6709 int LaneSize = 128 / VT.getScalarSizeInBits();
6710 int Size = Mask.size();
6711 for (int i = 0; i < Size; ++i)
6712 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6717 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6719 /// This checks a shuffle mask to see if it is performing the same
6720 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6721 /// that it is also not lane-crossing. It may however involve a blend from the
6722 /// same lane of a second vector.
6724 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6725 /// non-trivial to compute in the face of undef lanes. The representation is
6726 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6727 /// entries from both V1 and V2 inputs to the wider mask.
6729 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6730 SmallVectorImpl<int> &RepeatedMask) {
6731 int LaneSize = 128 / VT.getScalarSizeInBits();
6732 RepeatedMask.resize(LaneSize, -1);
6733 int Size = Mask.size();
6734 for (int i = 0; i < Size; ++i) {
6737 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6738 // This entry crosses lanes, so there is no way to model this shuffle.
6741 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6742 if (RepeatedMask[i % LaneSize] == -1)
6743 // This is the first non-undef entry in this slot of a 128-bit lane.
6744 RepeatedMask[i % LaneSize] =
6745 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6746 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6747 // Found a mismatch with the repeated mask.
6753 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6756 /// This is a fast way to test a shuffle mask against a fixed pattern:
6758 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6760 /// It returns true if the mask is exactly as wide as the argument list, and
6761 /// each element of the mask is either -1 (signifying undef) or the value given
6762 /// in the argument.
6763 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6764 ArrayRef<int> ExpectedMask) {
6765 if (Mask.size() != ExpectedMask.size())
6768 int Size = Mask.size();
6770 // If the values are build vectors, we can look through them to find
6771 // equivalent inputs that make the shuffles equivalent.
6772 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6773 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6775 for (int i = 0; i < Size; ++i)
6776 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6777 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6778 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6779 if (!MaskBV || !ExpectedBV ||
6780 MaskBV->getOperand(Mask[i] % Size) !=
6781 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6788 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6790 /// This helper function produces an 8-bit shuffle immediate corresponding to
6791 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6792 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6795 /// NB: We rely heavily on "undef" masks preserving the input lane.
6796 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6797 SelectionDAG &DAG) {
6798 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6799 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6800 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6801 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6802 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6805 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6806 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6807 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6808 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6809 return DAG.getConstant(Imm, DL, MVT::i8);
6812 /// \brief Compute whether each element of a shuffle is zeroable.
6814 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6815 /// Either it is an undef element in the shuffle mask, the element of the input
6816 /// referenced is undef, or the element of the input referenced is known to be
6817 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6818 /// as many lanes with this technique as possible to simplify the remaining
6820 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6821 SDValue V1, SDValue V2) {
6822 SmallBitVector Zeroable(Mask.size(), false);
6824 while (V1.getOpcode() == ISD::BITCAST)
6825 V1 = V1->getOperand(0);
6826 while (V2.getOpcode() == ISD::BITCAST)
6827 V2 = V2->getOperand(0);
6829 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6830 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6832 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6834 // Handle the easy cases.
6835 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6840 // If this is an index into a build_vector node (which has the same number
6841 // of elements), dig out the input value and use it.
6842 SDValue V = M < Size ? V1 : V2;
6843 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6846 SDValue Input = V.getOperand(M % Size);
6847 // The UNDEF opcode check really should be dead code here, but not quite
6848 // worth asserting on (it isn't invalid, just unexpected).
6849 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6856 // X86 has dedicated unpack instructions that can handle specific blend
6857 // operations: UNPCKH and UNPCKL.
6858 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6859 SDValue V1, SDValue V2,
6860 SelectionDAG &DAG) {
6861 int NumElts = VT.getVectorNumElements();
6862 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6863 SmallVector<int, 8> Unpckl;
6864 SmallVector<int, 8> Unpckh;
6866 for (int i = 0; i < NumElts; ++i) {
6867 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6868 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6869 int HiPos = LoPos + NumEltsInLane / 2;
6870 Unpckl.push_back(LoPos);
6871 Unpckh.push_back(HiPos);
6874 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6875 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6876 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6877 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6879 // Commute and try again.
6880 ShuffleVectorSDNode::commuteMask(Unpckl);
6881 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6882 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6884 ShuffleVectorSDNode::commuteMask(Unpckh);
6885 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6886 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6891 /// \brief Try to emit a bitmask instruction for a shuffle.
6893 /// This handles cases where we can model a blend exactly as a bitmask due to
6894 /// one of the inputs being zeroable.
6895 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6896 SDValue V2, ArrayRef<int> Mask,
6897 SelectionDAG &DAG) {
6898 MVT EltVT = VT.getVectorElementType();
6899 int NumEltBits = EltVT.getSizeInBits();
6900 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6901 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6902 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6904 if (EltVT.isFloatingPoint()) {
6905 Zero = DAG.getBitcast(EltVT, Zero);
6906 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6908 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6909 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6911 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6914 if (Mask[i] % Size != i)
6915 return SDValue(); // Not a blend.
6917 V = Mask[i] < Size ? V1 : V2;
6918 else if (V != (Mask[i] < Size ? V1 : V2))
6919 return SDValue(); // Can only let one input through the mask.
6921 VMaskOps[i] = AllOnes;
6924 return SDValue(); // No non-zeroable elements!
6926 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6927 V = DAG.getNode(VT.isFloatingPoint()
6928 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6933 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6935 /// This is used as a fallback approach when first class blend instructions are
6936 /// unavailable. Currently it is only suitable for integer vectors, but could
6937 /// be generalized for floating point vectors if desirable.
6938 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6939 SDValue V2, ArrayRef<int> Mask,
6940 SelectionDAG &DAG) {
6941 assert(VT.isInteger() && "Only supports integer vector types!");
6942 MVT EltVT = VT.getVectorElementType();
6943 int NumEltBits = EltVT.getSizeInBits();
6944 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6945 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6947 SmallVector<SDValue, 16> MaskOps;
6948 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6949 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6950 return SDValue(); // Shuffled input!
6951 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6954 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6955 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6956 // We have to cast V2 around.
6957 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6958 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6959 DAG.getBitcast(MaskVT, V1Mask),
6960 DAG.getBitcast(MaskVT, V2)));
6961 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6964 /// \brief Try to emit a blend instruction for a shuffle.
6966 /// This doesn't do any checks for the availability of instructions for blending
6967 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6968 /// be matched in the backend with the type given. What it does check for is
6969 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6970 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6971 SDValue V2, ArrayRef<int> Original,
6972 const X86Subtarget *Subtarget,
6973 SelectionDAG &DAG) {
6974 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6975 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6976 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6977 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6978 bool ForceV1Zero = false, ForceV2Zero = false;
6980 // Attempt to generate the binary blend mask. If an input is zero then
6981 // we can use any lane.
6982 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6983 unsigned BlendMask = 0;
6984 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6990 if (M == i + Size) {
6991 BlendMask |= 1u << i;
7002 BlendMask |= 1u << i;
7007 return SDValue(); // Shuffled input!
7010 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7012 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7014 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7016 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7017 unsigned ScaledMask = 0;
7018 for (int i = 0; i != Size; ++i)
7019 if (BlendMask & (1u << i))
7020 for (int j = 0; j != Scale; ++j)
7021 ScaledMask |= 1u << (i * Scale + j);
7025 switch (VT.SimpleTy) {
7030 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7031 DAG.getConstant(BlendMask, DL, MVT::i8));
7035 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7039 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7040 // that instruction.
7041 if (Subtarget->hasAVX2()) {
7042 // Scale the blend by the number of 32-bit dwords per element.
7043 int Scale = VT.getScalarSizeInBits() / 32;
7044 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7045 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7046 V1 = DAG.getBitcast(BlendVT, V1);
7047 V2 = DAG.getBitcast(BlendVT, V2);
7048 return DAG.getBitcast(
7049 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7050 DAG.getConstant(BlendMask, DL, MVT::i8)));
7054 // For integer shuffles we need to expand the mask and cast the inputs to
7055 // v8i16s prior to blending.
7056 int Scale = 8 / VT.getVectorNumElements();
7057 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7058 V1 = DAG.getBitcast(MVT::v8i16, V1);
7059 V2 = DAG.getBitcast(MVT::v8i16, V2);
7060 return DAG.getBitcast(VT,
7061 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7062 DAG.getConstant(BlendMask, DL, MVT::i8)));
7066 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7067 SmallVector<int, 8> RepeatedMask;
7068 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7069 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7070 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7072 for (int i = 0; i < 8; ++i)
7073 if (RepeatedMask[i] >= 16)
7074 BlendMask |= 1u << i;
7075 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7076 DAG.getConstant(BlendMask, DL, MVT::i8));
7082 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7083 "256-bit byte-blends require AVX2 support!");
7085 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7086 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7089 // Scale the blend by the number of bytes per element.
7090 int Scale = VT.getScalarSizeInBits() / 8;
7092 // This form of blend is always done on bytes. Compute the byte vector
7094 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7096 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7097 // mix of LLVM's code generator and the x86 backend. We tell the code
7098 // generator that boolean values in the elements of an x86 vector register
7099 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7100 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7101 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7102 // of the element (the remaining are ignored) and 0 in that high bit would
7103 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7104 // the LLVM model for boolean values in vector elements gets the relevant
7105 // bit set, it is set backwards and over constrained relative to x86's
7107 SmallVector<SDValue, 32> VSELECTMask;
7108 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7109 for (int j = 0; j < Scale; ++j)
7110 VSELECTMask.push_back(
7111 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7112 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7115 V1 = DAG.getBitcast(BlendVT, V1);
7116 V2 = DAG.getBitcast(BlendVT, V2);
7117 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7118 DAG.getNode(ISD::BUILD_VECTOR, DL,
7119 BlendVT, VSELECTMask),
7124 llvm_unreachable("Not a supported integer vector type!");
7128 /// \brief Try to lower as a blend of elements from two inputs followed by
7129 /// a single-input permutation.
7131 /// This matches the pattern where we can blend elements from two inputs and
7132 /// then reduce the shuffle to a single-input permutation.
7133 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7136 SelectionDAG &DAG) {
7137 // We build up the blend mask while checking whether a blend is a viable way
7138 // to reduce the shuffle.
7139 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7140 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7142 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7146 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7148 if (BlendMask[Mask[i] % Size] == -1)
7149 BlendMask[Mask[i] % Size] = Mask[i];
7150 else if (BlendMask[Mask[i] % Size] != Mask[i])
7151 return SDValue(); // Can't blend in the needed input!
7153 PermuteMask[i] = Mask[i] % Size;
7156 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7157 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7160 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7161 /// blends and permutes.
7163 /// This matches the extremely common pattern for handling combined
7164 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7165 /// operations. It will try to pick the best arrangement of shuffles and
7167 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7171 SelectionDAG &DAG) {
7172 // Shuffle the input elements into the desired positions in V1 and V2 and
7173 // blend them together.
7174 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7175 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7176 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7177 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7178 if (Mask[i] >= 0 && Mask[i] < Size) {
7179 V1Mask[i] = Mask[i];
7181 } else if (Mask[i] >= Size) {
7182 V2Mask[i] = Mask[i] - Size;
7183 BlendMask[i] = i + Size;
7186 // Try to lower with the simpler initial blend strategy unless one of the
7187 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7188 // shuffle may be able to fold with a load or other benefit. However, when
7189 // we'll have to do 2x as many shuffles in order to achieve this, blending
7190 // first is a better strategy.
7191 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7192 if (SDValue BlendPerm =
7193 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7196 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7197 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7198 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7201 /// \brief Try to lower a vector shuffle as a byte rotation.
7203 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7204 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7205 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7206 /// try to generically lower a vector shuffle through such an pattern. It
7207 /// does not check for the profitability of lowering either as PALIGNR or
7208 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7209 /// This matches shuffle vectors that look like:
7211 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7213 /// Essentially it concatenates V1 and V2, shifts right by some number of
7214 /// elements, and takes the low elements as the result. Note that while this is
7215 /// specified as a *right shift* because x86 is little-endian, it is a *left
7216 /// rotate* of the vector lanes.
7217 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7220 const X86Subtarget *Subtarget,
7221 SelectionDAG &DAG) {
7222 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7224 int NumElts = Mask.size();
7225 int NumLanes = VT.getSizeInBits() / 128;
7226 int NumLaneElts = NumElts / NumLanes;
7228 // We need to detect various ways of spelling a rotation:
7229 // [11, 12, 13, 14, 15, 0, 1, 2]
7230 // [-1, 12, 13, 14, -1, -1, 1, -1]
7231 // [-1, -1, -1, -1, -1, -1, 1, 2]
7232 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7233 // [-1, 4, 5, 6, -1, -1, 9, -1]
7234 // [-1, 4, 5, 6, -1, -1, -1, -1]
7237 for (int l = 0; l < NumElts; l += NumLaneElts) {
7238 for (int i = 0; i < NumLaneElts; ++i) {
7239 if (Mask[l + i] == -1)
7241 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7243 // Get the mod-Size index and lane correct it.
7244 int LaneIdx = (Mask[l + i] % NumElts) - l;
7245 // Make sure it was in this lane.
7246 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7249 // Determine where a rotated vector would have started.
7250 int StartIdx = i - LaneIdx;
7252 // The identity rotation isn't interesting, stop.
7255 // If we found the tail of a vector the rotation must be the missing
7256 // front. If we found the head of a vector, it must be how much of the
7258 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7261 Rotation = CandidateRotation;
7262 else if (Rotation != CandidateRotation)
7263 // The rotations don't match, so we can't match this mask.
7266 // Compute which value this mask is pointing at.
7267 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7269 // Compute which of the two target values this index should be assigned
7270 // to. This reflects whether the high elements are remaining or the low
7271 // elements are remaining.
7272 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7274 // Either set up this value if we've not encountered it before, or check
7275 // that it remains consistent.
7278 else if (TargetV != MaskV)
7279 // This may be a rotation, but it pulls from the inputs in some
7280 // unsupported interleaving.
7285 // Check that we successfully analyzed the mask, and normalize the results.
7286 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7287 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7293 // The actual rotate instruction rotates bytes, so we need to scale the
7294 // rotation based on how many bytes are in the vector lane.
7295 int Scale = 16 / NumLaneElts;
7297 // SSSE3 targets can use the palignr instruction.
7298 if (Subtarget->hasSSSE3()) {
7299 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7300 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7301 Lo = DAG.getBitcast(AlignVT, Lo);
7302 Hi = DAG.getBitcast(AlignVT, Hi);
7304 return DAG.getBitcast(
7305 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7306 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7309 assert(VT.is128BitVector() &&
7310 "Rotate-based lowering only supports 128-bit lowering!");
7311 assert(Mask.size() <= 16 &&
7312 "Can shuffle at most 16 bytes in a 128-bit vector!");
7314 // Default SSE2 implementation
7315 int LoByteShift = 16 - Rotation * Scale;
7316 int HiByteShift = Rotation * Scale;
7318 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7319 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7320 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7322 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7323 DAG.getConstant(LoByteShift, DL, MVT::i8));
7324 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7325 DAG.getConstant(HiByteShift, DL, MVT::i8));
7326 return DAG.getBitcast(VT,
7327 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7330 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7332 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7333 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7334 /// matches elements from one of the input vectors shuffled to the left or
7335 /// right with zeroable elements 'shifted in'. It handles both the strictly
7336 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7339 /// PSHL : (little-endian) left bit shift.
7340 /// [ zz, 0, zz, 2 ]
7341 /// [ -1, 4, zz, -1 ]
7342 /// PSRL : (little-endian) right bit shift.
7344 /// [ -1, -1, 7, zz]
7345 /// PSLLDQ : (little-endian) left byte shift
7346 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7347 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7348 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7349 /// PSRLDQ : (little-endian) right byte shift
7350 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7351 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7352 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7353 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7354 SDValue V2, ArrayRef<int> Mask,
7355 SelectionDAG &DAG) {
7356 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7358 int Size = Mask.size();
7359 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7361 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7362 for (int i = 0; i < Size; i += Scale)
7363 for (int j = 0; j < Shift; ++j)
7364 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7370 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7371 for (int i = 0; i != Size; i += Scale) {
7372 unsigned Pos = Left ? i + Shift : i;
7373 unsigned Low = Left ? i : i + Shift;
7374 unsigned Len = Scale - Shift;
7375 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7376 Low + (V == V1 ? 0 : Size)))
7380 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7381 bool ByteShift = ShiftEltBits > 64;
7382 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7383 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7384 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7386 // Normalize the scale for byte shifts to still produce an i64 element
7388 Scale = ByteShift ? Scale / 2 : Scale;
7390 // We need to round trip through the appropriate type for the shift.
7391 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7392 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7393 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7394 "Illegal integer vector type");
7395 V = DAG.getBitcast(ShiftVT, V);
7397 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7398 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7399 return DAG.getBitcast(VT, V);
7402 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7403 // keep doubling the size of the integer elements up to that. We can
7404 // then shift the elements of the integer vector by whole multiples of
7405 // their width within the elements of the larger integer vector. Test each
7406 // multiple to see if we can find a match with the moved element indices
7407 // and that the shifted in elements are all zeroable.
7408 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7409 for (int Shift = 1; Shift != Scale; ++Shift)
7410 for (bool Left : {true, false})
7411 if (CheckZeros(Shift, Scale, Left))
7412 for (SDValue V : {V1, V2})
7413 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7420 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7421 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7422 SDValue V2, ArrayRef<int> Mask,
7423 SelectionDAG &DAG) {
7424 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7425 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7427 int Size = Mask.size();
7428 int HalfSize = Size / 2;
7429 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7431 // Upper half must be undefined.
7432 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7435 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7436 // Remainder of lower half result is zero and upper half is all undef.
7437 auto LowerAsEXTRQ = [&]() {
7438 // Determine the extraction length from the part of the
7439 // lower half that isn't zeroable.
7441 for (; Len > 0; --Len)
7442 if (!Zeroable[Len - 1])
7444 assert(Len > 0 && "Zeroable shuffle mask");
7446 // Attempt to match first Len sequential elements from the lower half.
7449 for (int i = 0; i != Len; ++i) {
7453 SDValue &V = (M < Size ? V1 : V2);
7456 // The extracted elements must start at a valid index and all mask
7457 // elements must be in the lower half.
7458 if (i > M || M >= HalfSize)
7461 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7472 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7473 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7474 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7475 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7476 DAG.getConstant(BitLen, DL, MVT::i8),
7477 DAG.getConstant(BitIdx, DL, MVT::i8));
7480 if (SDValue ExtrQ = LowerAsEXTRQ())
7483 // INSERTQ: Extract lowest Len elements from lower half of second source and
7484 // insert over first source, starting at Idx.
7485 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7486 auto LowerAsInsertQ = [&]() {
7487 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7490 // Attempt to match first source from mask before insertion point.
7491 if (isUndefInRange(Mask, 0, Idx)) {
7493 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7495 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7501 // Extend the extraction length looking to match both the insertion of
7502 // the second source and the remaining elements of the first.
7503 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7508 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7510 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7516 // Match the remaining elements of the lower half.
7517 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7519 } else if ((!Base || (Base == V1)) &&
7520 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7522 } else if ((!Base || (Base == V2)) &&
7523 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7530 // We may not have a base (first source) - this can safely be undefined.
7532 Base = DAG.getUNDEF(VT);
7534 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7535 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7536 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7537 DAG.getConstant(BitLen, DL, MVT::i8),
7538 DAG.getConstant(BitIdx, DL, MVT::i8));
7545 if (SDValue InsertQ = LowerAsInsertQ())
7551 /// \brief Lower a vector shuffle as a zero or any extension.
7553 /// Given a specific number of elements, element bit width, and extension
7554 /// stride, produce either a zero or any extension based on the available
7555 /// features of the subtarget. The extended elements are consecutive and
7556 /// begin and can start from an offseted element index in the input; to
7557 /// avoid excess shuffling the offset must either being in the bottom lane
7558 /// or at the start of a higher lane. All extended elements must be from
7560 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7561 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7562 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7563 assert(Scale > 1 && "Need a scale to extend.");
7564 int EltBits = VT.getScalarSizeInBits();
7565 int NumElements = VT.getVectorNumElements();
7566 int NumEltsPerLane = 128 / EltBits;
7567 int OffsetLane = Offset / NumEltsPerLane;
7568 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7569 "Only 8, 16, and 32 bit elements can be extended.");
7570 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7571 assert(0 <= Offset && "Extension offset must be positive.");
7572 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7573 "Extension offset must be in the first lane or start an upper lane.");
7575 // Check that an index is in same lane as the base offset.
7576 auto SafeOffset = [&](int Idx) {
7577 return OffsetLane == (Idx / NumEltsPerLane);
7580 // Shift along an input so that the offset base moves to the first element.
7581 auto ShuffleOffset = [&](SDValue V) {
7585 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7586 for (int i = 0; i * Scale < NumElements; ++i) {
7587 int SrcIdx = i + Offset;
7588 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7590 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7593 // Found a valid zext mask! Try various lowering strategies based on the
7594 // input type and available ISA extensions.
7595 if (Subtarget->hasSSE41()) {
7596 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7597 // PUNPCK will catch this in a later shuffle match.
7598 if (Offset && Scale == 2 && VT.is128BitVector())
7600 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7601 NumElements / Scale);
7602 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7603 return DAG.getBitcast(VT, InputV);
7606 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7608 // For any extends we can cheat for larger element sizes and use shuffle
7609 // instructions that can fold with a load and/or copy.
7610 if (AnyExt && EltBits == 32) {
7611 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7613 return DAG.getBitcast(
7614 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7615 DAG.getBitcast(MVT::v4i32, InputV),
7616 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7618 if (AnyExt && EltBits == 16 && Scale > 2) {
7619 int PSHUFDMask[4] = {Offset / 2, -1,
7620 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7621 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7622 DAG.getBitcast(MVT::v4i32, InputV),
7623 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7624 int PSHUFWMask[4] = {1, -1, -1, -1};
7625 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7626 return DAG.getBitcast(
7627 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7628 DAG.getBitcast(MVT::v8i16, InputV),
7629 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7632 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7634 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7635 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7636 assert(VT.is128BitVector() && "Unexpected vector width!");
7638 int LoIdx = Offset * EltBits;
7639 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7640 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7641 DAG.getConstant(EltBits, DL, MVT::i8),
7642 DAG.getConstant(LoIdx, DL, MVT::i8)));
7644 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7645 !SafeOffset(Offset + 1))
7646 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7648 int HiIdx = (Offset + 1) * EltBits;
7649 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7650 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7651 DAG.getConstant(EltBits, DL, MVT::i8),
7652 DAG.getConstant(HiIdx, DL, MVT::i8)));
7653 return DAG.getNode(ISD::BITCAST, DL, VT,
7654 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7657 // If this would require more than 2 unpack instructions to expand, use
7658 // pshufb when available. We can only use more than 2 unpack instructions
7659 // when zero extending i8 elements which also makes it easier to use pshufb.
7660 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7661 assert(NumElements == 16 && "Unexpected byte vector width!");
7662 SDValue PSHUFBMask[16];
7663 for (int i = 0; i < 16; ++i) {
7664 int Idx = Offset + (i / Scale);
7665 PSHUFBMask[i] = DAG.getConstant(
7666 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7668 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7669 return DAG.getBitcast(VT,
7670 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7671 DAG.getNode(ISD::BUILD_VECTOR, DL,
7672 MVT::v16i8, PSHUFBMask)));
7675 // If we are extending from an offset, ensure we start on a boundary that
7676 // we can unpack from.
7677 int AlignToUnpack = Offset % (NumElements / Scale);
7678 if (AlignToUnpack) {
7679 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7680 for (int i = AlignToUnpack; i < NumElements; ++i)
7681 ShMask[i - AlignToUnpack] = i;
7682 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7683 Offset -= AlignToUnpack;
7686 // Otherwise emit a sequence of unpacks.
7688 unsigned UnpackLoHi = X86ISD::UNPCKL;
7689 if (Offset >= (NumElements / 2)) {
7690 UnpackLoHi = X86ISD::UNPCKH;
7691 Offset -= (NumElements / 2);
7694 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7695 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7696 : getZeroVector(InputVT, Subtarget, DAG, DL);
7697 InputV = DAG.getBitcast(InputVT, InputV);
7698 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7702 } while (Scale > 1);
7703 return DAG.getBitcast(VT, InputV);
7706 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7708 /// This routine will try to do everything in its power to cleverly lower
7709 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7710 /// check for the profitability of this lowering, it tries to aggressively
7711 /// match this pattern. It will use all of the micro-architectural details it
7712 /// can to emit an efficient lowering. It handles both blends with all-zero
7713 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7714 /// masking out later).
7716 /// The reason we have dedicated lowering for zext-style shuffles is that they
7717 /// are both incredibly common and often quite performance sensitive.
7718 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7719 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7720 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7721 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7723 int Bits = VT.getSizeInBits();
7724 int NumLanes = Bits / 128;
7725 int NumElements = VT.getVectorNumElements();
7726 int NumEltsPerLane = NumElements / NumLanes;
7727 assert(VT.getScalarSizeInBits() <= 32 &&
7728 "Exceeds 32-bit integer zero extension limit");
7729 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7731 // Define a helper function to check a particular ext-scale and lower to it if
7733 auto Lower = [&](int Scale) -> SDValue {
7738 for (int i = 0; i < NumElements; ++i) {
7741 continue; // Valid anywhere but doesn't tell us anything.
7742 if (i % Scale != 0) {
7743 // Each of the extended elements need to be zeroable.
7747 // We no longer are in the anyext case.
7752 // Each of the base elements needs to be consecutive indices into the
7753 // same input vector.
7754 SDValue V = M < NumElements ? V1 : V2;
7755 M = M % NumElements;
7758 Offset = M - (i / Scale);
7759 } else if (InputV != V)
7760 return SDValue(); // Flip-flopping inputs.
7762 // Offset must start in the lowest 128-bit lane or at the start of an
7764 // FIXME: Is it ever worth allowing a negative base offset?
7765 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7766 (Offset % NumEltsPerLane) == 0))
7769 // If we are offsetting, all referenced entries must come from the same
7771 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7774 if ((M % NumElements) != (Offset + (i / Scale)))
7775 return SDValue(); // Non-consecutive strided elements.
7779 // If we fail to find an input, we have a zero-shuffle which should always
7780 // have already been handled.
7781 // FIXME: Maybe handle this here in case during blending we end up with one?
7785 // If we are offsetting, don't extend if we only match a single input, we
7786 // can always do better by using a basic PSHUF or PUNPCK.
7787 if (Offset != 0 && Matches < 2)
7790 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7791 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7794 // The widest scale possible for extending is to a 64-bit integer.
7795 assert(Bits % 64 == 0 &&
7796 "The number of bits in a vector must be divisible by 64 on x86!");
7797 int NumExtElements = Bits / 64;
7799 // Each iteration, try extending the elements half as much, but into twice as
7801 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7802 assert(NumElements % NumExtElements == 0 &&
7803 "The input vector size must be divisible by the extended size.");
7804 if (SDValue V = Lower(NumElements / NumExtElements))
7808 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7812 // Returns one of the source operands if the shuffle can be reduced to a
7813 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7814 auto CanZExtLowHalf = [&]() {
7815 for (int i = NumElements / 2; i != NumElements; ++i)
7818 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7820 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7825 if (SDValue V = CanZExtLowHalf()) {
7826 V = DAG.getBitcast(MVT::v2i64, V);
7827 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7828 return DAG.getBitcast(VT, V);
7831 // No viable ext lowering found.
7835 /// \brief Try to get a scalar value for a specific element of a vector.
7837 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7838 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7839 SelectionDAG &DAG) {
7840 MVT VT = V.getSimpleValueType();
7841 MVT EltVT = VT.getVectorElementType();
7842 while (V.getOpcode() == ISD::BITCAST)
7843 V = V.getOperand(0);
7844 // If the bitcasts shift the element size, we can't extract an equivalent
7846 MVT NewVT = V.getSimpleValueType();
7847 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7850 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7851 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7852 // Ensure the scalar operand is the same size as the destination.
7853 // FIXME: Add support for scalar truncation where possible.
7854 SDValue S = V.getOperand(Idx);
7855 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7856 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7862 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7864 /// This is particularly important because the set of instructions varies
7865 /// significantly based on whether the operand is a load or not.
7866 static bool isShuffleFoldableLoad(SDValue V) {
7867 while (V.getOpcode() == ISD::BITCAST)
7868 V = V.getOperand(0);
7870 return ISD::isNON_EXTLoad(V.getNode());
7873 /// \brief Try to lower insertion of a single element into a zero vector.
7875 /// This is a common pattern that we have especially efficient patterns to lower
7876 /// across all subtarget feature sets.
7877 static SDValue lowerVectorShuffleAsElementInsertion(
7878 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7879 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7880 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7882 MVT EltVT = VT.getVectorElementType();
7884 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7885 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7887 bool IsV1Zeroable = true;
7888 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7889 if (i != V2Index && !Zeroable[i]) {
7890 IsV1Zeroable = false;
7894 // Check for a single input from a SCALAR_TO_VECTOR node.
7895 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7896 // all the smarts here sunk into that routine. However, the current
7897 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7898 // vector shuffle lowering is dead.
7899 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7901 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7902 // We need to zext the scalar if it is smaller than an i32.
7903 V2S = DAG.getBitcast(EltVT, V2S);
7904 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7905 // Using zext to expand a narrow element won't work for non-zero
7910 // Zero-extend directly to i32.
7912 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7914 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7915 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7916 EltVT == MVT::i16) {
7917 // Either not inserting from the low element of the input or the input
7918 // element size is too small to use VZEXT_MOVL to clear the high bits.
7922 if (!IsV1Zeroable) {
7923 // If V1 can't be treated as a zero vector we have fewer options to lower
7924 // this. We can't support integer vectors or non-zero targets cheaply, and
7925 // the V1 elements can't be permuted in any way.
7926 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7927 if (!VT.isFloatingPoint() || V2Index != 0)
7929 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7930 V1Mask[V2Index] = -1;
7931 if (!isNoopShuffleMask(V1Mask))
7933 // This is essentially a special case blend operation, but if we have
7934 // general purpose blend operations, they are always faster. Bail and let
7935 // the rest of the lowering handle these as blends.
7936 if (Subtarget->hasSSE41())
7939 // Otherwise, use MOVSD or MOVSS.
7940 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7941 "Only two types of floating point element types to handle!");
7942 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7946 // This lowering only works for the low element with floating point vectors.
7947 if (VT.isFloatingPoint() && V2Index != 0)
7950 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7952 V2 = DAG.getBitcast(VT, V2);
7955 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7956 // the desired position. Otherwise it is more efficient to do a vector
7957 // shift left. We know that we can do a vector shift left because all
7958 // the inputs are zero.
7959 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7960 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7961 V2Shuffle[V2Index] = 0;
7962 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7964 V2 = DAG.getBitcast(MVT::v2i64, V2);
7966 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7967 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7968 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7969 DAG.getDataLayout(), VT)));
7970 V2 = DAG.getBitcast(VT, V2);
7976 /// \brief Try to lower broadcast of a single - truncated - integer element,
7977 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7979 /// This assumes we have AVX2.
7980 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7982 const X86Subtarget *Subtarget,
7983 SelectionDAG &DAG) {
7984 assert(Subtarget->hasAVX2() &&
7985 "We can only lower integer broadcasts with AVX2!");
7987 EVT EltVT = VT.getVectorElementType();
7988 EVT V0VT = V0.getValueType();
7990 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7991 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7993 EVT V0EltVT = V0VT.getVectorElementType();
7994 if (!V0EltVT.isInteger())
7997 const unsigned EltSize = EltVT.getSizeInBits();
7998 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8000 // This is only a truncation if the original element type is larger.
8001 if (V0EltSize <= EltSize)
8004 assert(((V0EltSize % EltSize) == 0) &&
8005 "Scalar type sizes must all be powers of 2 on x86!");
8007 const unsigned V0Opc = V0.getOpcode();
8008 const unsigned Scale = V0EltSize / EltSize;
8009 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8011 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8012 V0Opc != ISD::BUILD_VECTOR)
8015 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8017 // If we're extracting non-least-significant bits, shift so we can truncate.
8018 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8019 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8020 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8021 if (const int OffsetIdx = BroadcastIdx % Scale)
8022 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8023 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8025 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8026 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8029 /// \brief Try to lower broadcast of a single element.
8031 /// For convenience, this code also bundles all of the subtarget feature set
8032 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8033 /// a convenient way to factor it out.
8034 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8036 const X86Subtarget *Subtarget,
8037 SelectionDAG &DAG) {
8038 if (!Subtarget->hasAVX())
8040 if (VT.isInteger() && !Subtarget->hasAVX2())
8043 // Check that the mask is a broadcast.
8044 int BroadcastIdx = -1;
8046 if (M >= 0 && BroadcastIdx == -1)
8048 else if (M >= 0 && M != BroadcastIdx)
8051 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8052 "a sorted mask where the broadcast "
8055 // Go up the chain of (vector) values to find a scalar load that we can
8056 // combine with the broadcast.
8058 switch (V.getOpcode()) {
8059 case ISD::CONCAT_VECTORS: {
8060 int OperandSize = Mask.size() / V.getNumOperands();
8061 V = V.getOperand(BroadcastIdx / OperandSize);
8062 BroadcastIdx %= OperandSize;
8066 case ISD::INSERT_SUBVECTOR: {
8067 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8068 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8072 int BeginIdx = (int)ConstantIdx->getZExtValue();
8074 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8075 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8076 BroadcastIdx -= BeginIdx;
8087 // Check if this is a broadcast of a scalar. We special case lowering
8088 // for scalars so that we can more effectively fold with loads.
8089 // First, look through bitcast: if the original value has a larger element
8090 // type than the shuffle, the broadcast element is in essence truncated.
8091 // Make that explicit to ease folding.
8092 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8093 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8094 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8095 return TruncBroadcast;
8097 // Also check the simpler case, where we can directly reuse the scalar.
8098 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8099 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8100 V = V.getOperand(BroadcastIdx);
8102 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8103 // Only AVX2 has register broadcasts.
8104 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8106 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8107 // We can't broadcast from a vector register without AVX2, and we can only
8108 // broadcast from the zero-element of a vector register.
8112 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8115 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8116 // INSERTPS when the V1 elements are already in the correct locations
8117 // because otherwise we can just always use two SHUFPS instructions which
8118 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8119 // perform INSERTPS if a single V1 element is out of place and all V2
8120 // elements are zeroable.
8121 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8123 SelectionDAG &DAG) {
8124 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8125 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8126 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8127 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8129 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8132 int V1DstIndex = -1;
8133 int V2DstIndex = -1;
8134 bool V1UsedInPlace = false;
8136 for (int i = 0; i < 4; ++i) {
8137 // Synthesize a zero mask from the zeroable elements (includes undefs).
8143 // Flag if we use any V1 inputs in place.
8145 V1UsedInPlace = true;
8149 // We can only insert a single non-zeroable element.
8150 if (V1DstIndex != -1 || V2DstIndex != -1)
8154 // V1 input out of place for insertion.
8157 // V2 input for insertion.
8162 // Don't bother if we have no (non-zeroable) element for insertion.
8163 if (V1DstIndex == -1 && V2DstIndex == -1)
8166 // Determine element insertion src/dst indices. The src index is from the
8167 // start of the inserted vector, not the start of the concatenated vector.
8168 unsigned V2SrcIndex = 0;
8169 if (V1DstIndex != -1) {
8170 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8171 // and don't use the original V2 at all.
8172 V2SrcIndex = Mask[V1DstIndex];
8173 V2DstIndex = V1DstIndex;
8176 V2SrcIndex = Mask[V2DstIndex] - 4;
8179 // If no V1 inputs are used in place, then the result is created only from
8180 // the zero mask and the V2 insertion - so remove V1 dependency.
8182 V1 = DAG.getUNDEF(MVT::v4f32);
8184 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8185 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8187 // Insert the V2 element into the desired position.
8189 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8190 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8193 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8194 /// UNPCK instruction.
8196 /// This specifically targets cases where we end up with alternating between
8197 /// the two inputs, and so can permute them into something that feeds a single
8198 /// UNPCK instruction. Note that this routine only targets integer vectors
8199 /// because for floating point vectors we have a generalized SHUFPS lowering
8200 /// strategy that handles everything that doesn't *exactly* match an unpack,
8201 /// making this clever lowering unnecessary.
8202 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8203 SDValue V1, SDValue V2,
8205 SelectionDAG &DAG) {
8206 assert(!VT.isFloatingPoint() &&
8207 "This routine only supports integer vectors.");
8208 assert(!isSingleInputShuffleMask(Mask) &&
8209 "This routine should only be used when blending two inputs.");
8210 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8212 int Size = Mask.size();
8214 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8215 return M >= 0 && M % Size < Size / 2;
8217 int NumHiInputs = std::count_if(
8218 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8220 bool UnpackLo = NumLoInputs >= NumHiInputs;
8222 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8223 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8224 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8226 for (int i = 0; i < Size; ++i) {
8230 // Each element of the unpack contains Scale elements from this mask.
8231 int UnpackIdx = i / Scale;
8233 // We only handle the case where V1 feeds the first slots of the unpack.
8234 // We rely on canonicalization to ensure this is the case.
8235 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8238 // Setup the mask for this input. The indexing is tricky as we have to
8239 // handle the unpack stride.
8240 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8241 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8245 // If we will have to shuffle both inputs to use the unpack, check whether
8246 // we can just unpack first and shuffle the result. If so, skip this unpack.
8247 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8248 !isNoopShuffleMask(V2Mask))
8251 // Shuffle the inputs into place.
8252 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8253 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8255 // Cast the inputs to the type we will use to unpack them.
8256 V1 = DAG.getBitcast(UnpackVT, V1);
8257 V2 = DAG.getBitcast(UnpackVT, V2);
8259 // Unpack the inputs and cast the result back to the desired type.
8260 return DAG.getBitcast(
8261 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8265 // We try each unpack from the largest to the smallest to try and find one
8266 // that fits this mask.
8267 int OrigNumElements = VT.getVectorNumElements();
8268 int OrigScalarSize = VT.getScalarSizeInBits();
8269 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8270 int Scale = ScalarSize / OrigScalarSize;
8271 int NumElements = OrigNumElements / Scale;
8272 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8273 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8277 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8279 if (NumLoInputs == 0 || NumHiInputs == 0) {
8280 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8281 "We have to have *some* inputs!");
8282 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8284 // FIXME: We could consider the total complexity of the permute of each
8285 // possible unpacking. Or at the least we should consider how many
8286 // half-crossings are created.
8287 // FIXME: We could consider commuting the unpacks.
8289 SmallVector<int, 32> PermMask;
8290 PermMask.assign(Size, -1);
8291 for (int i = 0; i < Size; ++i) {
8295 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8298 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8300 return DAG.getVectorShuffle(
8301 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8303 DAG.getUNDEF(VT), PermMask);
8309 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8311 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8312 /// support for floating point shuffles but not integer shuffles. These
8313 /// instructions will incur a domain crossing penalty on some chips though so
8314 /// it is better to avoid lowering through this for integer vectors where
8316 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8317 const X86Subtarget *Subtarget,
8318 SelectionDAG &DAG) {
8320 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8321 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8322 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8323 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8324 ArrayRef<int> Mask = SVOp->getMask();
8325 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8327 if (isSingleInputShuffleMask(Mask)) {
8328 // Use low duplicate instructions for masks that match their pattern.
8329 if (Subtarget->hasSSE3())
8330 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8331 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8333 // Straight shuffle of a single input vector. Simulate this by using the
8334 // single input as both of the "inputs" to this instruction..
8335 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8337 if (Subtarget->hasAVX()) {
8338 // If we have AVX, we can use VPERMILPS which will allow folding a load
8339 // into the shuffle.
8340 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8341 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8344 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8345 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8347 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8348 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8350 // If we have a single input, insert that into V1 if we can do so cheaply.
8351 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8352 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8353 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8355 // Try inverting the insertion since for v2 masks it is easy to do and we
8356 // can't reliably sort the mask one way or the other.
8357 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8358 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8359 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8360 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8364 // Try to use one of the special instruction patterns to handle two common
8365 // blend patterns if a zero-blend above didn't work.
8366 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8367 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8368 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8369 // We can either use a special instruction to load over the low double or
8370 // to move just the low double.
8372 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8374 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8376 if (Subtarget->hasSSE41())
8377 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8381 // Use dedicated unpack instructions for masks that match their pattern.
8383 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8386 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8387 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8388 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8391 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8393 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8394 /// the integer unit to minimize domain crossing penalties. However, for blends
8395 /// it falls back to the floating point shuffle operation with appropriate bit
8397 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8398 const X86Subtarget *Subtarget,
8399 SelectionDAG &DAG) {
8401 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8402 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8403 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8404 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8405 ArrayRef<int> Mask = SVOp->getMask();
8406 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8408 if (isSingleInputShuffleMask(Mask)) {
8409 // Check for being able to broadcast a single element.
8410 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8411 Mask, Subtarget, DAG))
8414 // Straight shuffle of a single input vector. For everything from SSE2
8415 // onward this has a single fast instruction with no scary immediates.
8416 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8417 V1 = DAG.getBitcast(MVT::v4i32, V1);
8418 int WidenedMask[4] = {
8419 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8420 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8421 return DAG.getBitcast(
8423 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8424 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8426 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8427 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8428 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8429 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8431 // If we have a blend of two PACKUS operations an the blend aligns with the
8432 // low and half halves, we can just merge the PACKUS operations. This is
8433 // particularly important as it lets us merge shuffles that this routine itself
8435 auto GetPackNode = [](SDValue V) {
8436 while (V.getOpcode() == ISD::BITCAST)
8437 V = V.getOperand(0);
8439 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8441 if (SDValue V1Pack = GetPackNode(V1))
8442 if (SDValue V2Pack = GetPackNode(V2))
8443 return DAG.getBitcast(MVT::v2i64,
8444 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8445 Mask[0] == 0 ? V1Pack.getOperand(0)
8446 : V1Pack.getOperand(1),
8447 Mask[1] == 2 ? V2Pack.getOperand(0)
8448 : V2Pack.getOperand(1)));
8450 // Try to use shift instructions.
8452 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8455 // When loading a scalar and then shuffling it into a vector we can often do
8456 // the insertion cheaply.
8457 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8458 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8460 // Try inverting the insertion since for v2 masks it is easy to do and we
8461 // can't reliably sort the mask one way or the other.
8462 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8463 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8464 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8467 // We have different paths for blend lowering, but they all must use the
8468 // *exact* same predicate.
8469 bool IsBlendSupported = Subtarget->hasSSE41();
8470 if (IsBlendSupported)
8471 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8475 // Use dedicated unpack instructions for masks that match their pattern.
8477 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8480 // Try to use byte rotation instructions.
8481 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8482 if (Subtarget->hasSSSE3())
8483 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8484 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8487 // If we have direct support for blends, we should lower by decomposing into
8488 // a permute. That will be faster than the domain cross.
8489 if (IsBlendSupported)
8490 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8493 // We implement this with SHUFPD which is pretty lame because it will likely
8494 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8495 // However, all the alternatives are still more cycles and newer chips don't
8496 // have this problem. It would be really nice if x86 had better shuffles here.
8497 V1 = DAG.getBitcast(MVT::v2f64, V1);
8498 V2 = DAG.getBitcast(MVT::v2f64, V2);
8499 return DAG.getBitcast(MVT::v2i64,
8500 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8503 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8505 /// This is used to disable more specialized lowerings when the shufps lowering
8506 /// will happen to be efficient.
8507 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8508 // This routine only handles 128-bit shufps.
8509 assert(Mask.size() == 4 && "Unsupported mask size!");
8511 // To lower with a single SHUFPS we need to have the low half and high half
8512 // each requiring a single input.
8513 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8515 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8521 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8523 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8524 /// It makes no assumptions about whether this is the *best* lowering, it simply
8526 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8527 ArrayRef<int> Mask, SDValue V1,
8528 SDValue V2, SelectionDAG &DAG) {
8529 SDValue LowV = V1, HighV = V2;
8530 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8533 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8535 if (NumV2Elements == 1) {
8537 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8540 // Compute the index adjacent to V2Index and in the same half by toggling
8542 int V2AdjIndex = V2Index ^ 1;
8544 if (Mask[V2AdjIndex] == -1) {
8545 // Handles all the cases where we have a single V2 element and an undef.
8546 // This will only ever happen in the high lanes because we commute the
8547 // vector otherwise.
8549 std::swap(LowV, HighV);
8550 NewMask[V2Index] -= 4;
8552 // Handle the case where the V2 element ends up adjacent to a V1 element.
8553 // To make this work, blend them together as the first step.
8554 int V1Index = V2AdjIndex;
8555 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8556 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8557 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8559 // Now proceed to reconstruct the final blend as we have the necessary
8560 // high or low half formed.
8567 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8568 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8570 } else if (NumV2Elements == 2) {
8571 if (Mask[0] < 4 && Mask[1] < 4) {
8572 // Handle the easy case where we have V1 in the low lanes and V2 in the
8576 } else if (Mask[2] < 4 && Mask[3] < 4) {
8577 // We also handle the reversed case because this utility may get called
8578 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8579 // arrange things in the right direction.
8585 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8586 // trying to place elements directly, just blend them and set up the final
8587 // shuffle to place them.
8589 // The first two blend mask elements are for V1, the second two are for
8591 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8592 Mask[2] < 4 ? Mask[2] : Mask[3],
8593 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8594 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8595 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8596 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8598 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8601 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8602 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8603 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8604 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8607 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8608 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8611 /// \brief Lower 4-lane 32-bit floating point shuffles.
8613 /// Uses instructions exclusively from the floating point unit to minimize
8614 /// domain crossing penalties, as these are sufficient to implement all v4f32
8616 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8617 const X86Subtarget *Subtarget,
8618 SelectionDAG &DAG) {
8620 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8621 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8622 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8623 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8624 ArrayRef<int> Mask = SVOp->getMask();
8625 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8628 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8630 if (NumV2Elements == 0) {
8631 // Check for being able to broadcast a single element.
8632 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8633 Mask, Subtarget, DAG))
8636 // Use even/odd duplicate instructions for masks that match their pattern.
8637 if (Subtarget->hasSSE3()) {
8638 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8639 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8640 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8641 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8644 if (Subtarget->hasAVX()) {
8645 // If we have AVX, we can use VPERMILPS which will allow folding a load
8646 // into the shuffle.
8647 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8648 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8651 // Otherwise, use a straight shuffle of a single input vector. We pass the
8652 // input vector to both operands to simulate this with a SHUFPS.
8653 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8654 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8657 // There are special ways we can lower some single-element blends. However, we
8658 // have custom ways we can lower more complex single-element blends below that
8659 // we defer to if both this and BLENDPS fail to match, so restrict this to
8660 // when the V2 input is targeting element 0 of the mask -- that is the fast
8662 if (NumV2Elements == 1 && Mask[0] >= 4)
8663 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8664 Mask, Subtarget, DAG))
8667 if (Subtarget->hasSSE41()) {
8668 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8672 // Use INSERTPS if we can complete the shuffle efficiently.
8673 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8676 if (!isSingleSHUFPSMask(Mask))
8677 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8678 DL, MVT::v4f32, V1, V2, Mask, DAG))
8682 // Use dedicated unpack instructions for masks that match their pattern.
8684 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8687 // Otherwise fall back to a SHUFPS lowering strategy.
8688 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8691 /// \brief Lower 4-lane i32 vector shuffles.
8693 /// We try to handle these with integer-domain shuffles where we can, but for
8694 /// blends we use the floating point domain blend instructions.
8695 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8696 const X86Subtarget *Subtarget,
8697 SelectionDAG &DAG) {
8699 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8700 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8701 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8702 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8703 ArrayRef<int> Mask = SVOp->getMask();
8704 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8706 // Whenever we can lower this as a zext, that instruction is strictly faster
8707 // than any alternative. It also allows us to fold memory operands into the
8708 // shuffle in many cases.
8709 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8710 Mask, Subtarget, DAG))
8714 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8716 if (NumV2Elements == 0) {
8717 // Check for being able to broadcast a single element.
8718 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8719 Mask, Subtarget, DAG))
8722 // Straight shuffle of a single input vector. For everything from SSE2
8723 // onward this has a single fast instruction with no scary immediates.
8724 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8725 // but we aren't actually going to use the UNPCK instruction because doing
8726 // so prevents folding a load into this instruction or making a copy.
8727 const int UnpackLoMask[] = {0, 0, 1, 1};
8728 const int UnpackHiMask[] = {2, 2, 3, 3};
8729 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8730 Mask = UnpackLoMask;
8731 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8732 Mask = UnpackHiMask;
8734 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8735 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8738 // Try to use shift instructions.
8740 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8743 // There are special ways we can lower some single-element blends.
8744 if (NumV2Elements == 1)
8745 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8746 Mask, Subtarget, DAG))
8749 // We have different paths for blend lowering, but they all must use the
8750 // *exact* same predicate.
8751 bool IsBlendSupported = Subtarget->hasSSE41();
8752 if (IsBlendSupported)
8753 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8757 if (SDValue Masked =
8758 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8761 // Use dedicated unpack instructions for masks that match their pattern.
8763 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8766 // Try to use byte rotation instructions.
8767 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8768 if (Subtarget->hasSSSE3())
8769 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8770 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8773 // If we have direct support for blends, we should lower by decomposing into
8774 // a permute. That will be faster than the domain cross.
8775 if (IsBlendSupported)
8776 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8779 // Try to lower by permuting the inputs into an unpack instruction.
8780 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8784 // We implement this with SHUFPS because it can blend from two vectors.
8785 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8786 // up the inputs, bypassing domain shift penalties that we would encur if we
8787 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8789 return DAG.getBitcast(
8791 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8792 DAG.getBitcast(MVT::v4f32, V2), Mask));
8795 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8796 /// shuffle lowering, and the most complex part.
8798 /// The lowering strategy is to try to form pairs of input lanes which are
8799 /// targeted at the same half of the final vector, and then use a dword shuffle
8800 /// to place them onto the right half, and finally unpack the paired lanes into
8801 /// their final position.
8803 /// The exact breakdown of how to form these dword pairs and align them on the
8804 /// correct sides is really tricky. See the comments within the function for
8805 /// more of the details.
8807 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8808 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8809 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8810 /// vector, form the analogous 128-bit 8-element Mask.
8811 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8812 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8813 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8814 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8815 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8817 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8818 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8819 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8821 SmallVector<int, 4> LoInputs;
8822 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8823 [](int M) { return M >= 0; });
8824 std::sort(LoInputs.begin(), LoInputs.end());
8825 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8826 SmallVector<int, 4> HiInputs;
8827 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8828 [](int M) { return M >= 0; });
8829 std::sort(HiInputs.begin(), HiInputs.end());
8830 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8832 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8833 int NumHToL = LoInputs.size() - NumLToL;
8835 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8836 int NumHToH = HiInputs.size() - NumLToH;
8837 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8838 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8839 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8840 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8842 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8843 // such inputs we can swap two of the dwords across the half mark and end up
8844 // with <=2 inputs to each half in each half. Once there, we can fall through
8845 // to the generic code below. For example:
8847 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8848 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8850 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8851 // and an existing 2-into-2 on the other half. In this case we may have to
8852 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8853 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8854 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8855 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8856 // half than the one we target for fixing) will be fixed when we re-enter this
8857 // path. We will also combine away any sequence of PSHUFD instructions that
8858 // result into a single instruction. Here is an example of the tricky case:
8860 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8861 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8863 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8865 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8866 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8868 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8869 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8871 // The result is fine to be handled by the generic logic.
8872 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8873 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8874 int AOffset, int BOffset) {
8875 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8876 "Must call this with A having 3 or 1 inputs from the A half.");
8877 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8878 "Must call this with B having 1 or 3 inputs from the B half.");
8879 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8880 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8882 bool ThreeAInputs = AToAInputs.size() == 3;
8884 // Compute the index of dword with only one word among the three inputs in
8885 // a half by taking the sum of the half with three inputs and subtracting
8886 // the sum of the actual three inputs. The difference is the remaining
8889 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8890 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8891 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8892 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8893 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8894 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8895 int TripleNonInputIdx =
8896 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8897 TripleDWord = TripleNonInputIdx / 2;
8899 // We use xor with one to compute the adjacent DWord to whichever one the
8901 OneInputDWord = (OneInput / 2) ^ 1;
8903 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8904 // and BToA inputs. If there is also such a problem with the BToB and AToB
8905 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8906 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8907 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8908 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8909 // Compute how many inputs will be flipped by swapping these DWords. We
8911 // to balance this to ensure we don't form a 3-1 shuffle in the other
8913 int NumFlippedAToBInputs =
8914 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8915 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8916 int NumFlippedBToBInputs =
8917 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8918 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8919 if ((NumFlippedAToBInputs == 1 &&
8920 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8921 (NumFlippedBToBInputs == 1 &&
8922 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8923 // We choose whether to fix the A half or B half based on whether that
8924 // half has zero flipped inputs. At zero, we may not be able to fix it
8925 // with that half. We also bias towards fixing the B half because that
8926 // will more commonly be the high half, and we have to bias one way.
8927 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8928 ArrayRef<int> Inputs) {
8929 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8930 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8931 PinnedIdx ^ 1) != Inputs.end();
8932 // Determine whether the free index is in the flipped dword or the
8933 // unflipped dword based on where the pinned index is. We use this bit
8934 // in an xor to conditionally select the adjacent dword.
8935 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8936 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8937 FixFreeIdx) != Inputs.end();
8938 if (IsFixIdxInput == IsFixFreeIdxInput)
8940 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8941 FixFreeIdx) != Inputs.end();
8942 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8943 "We need to be changing the number of flipped inputs!");
8944 int PSHUFHalfMask[] = {0, 1, 2, 3};
8945 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8946 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8948 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8951 if (M != -1 && M == FixIdx)
8953 else if (M != -1 && M == FixFreeIdx)
8956 if (NumFlippedBToBInputs != 0) {
8958 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8959 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8961 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8962 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8963 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8968 int PSHUFDMask[] = {0, 1, 2, 3};
8969 PSHUFDMask[ADWord] = BDWord;
8970 PSHUFDMask[BDWord] = ADWord;
8973 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8974 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8976 // Adjust the mask to match the new locations of A and B.
8978 if (M != -1 && M/2 == ADWord)
8979 M = 2 * BDWord + M % 2;
8980 else if (M != -1 && M/2 == BDWord)
8981 M = 2 * ADWord + M % 2;
8983 // Recurse back into this routine to re-compute state now that this isn't
8984 // a 3 and 1 problem.
8985 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8988 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8989 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8990 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8991 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8993 // At this point there are at most two inputs to the low and high halves from
8994 // each half. That means the inputs can always be grouped into dwords and
8995 // those dwords can then be moved to the correct half with a dword shuffle.
8996 // We use at most one low and one high word shuffle to collect these paired
8997 // inputs into dwords, and finally a dword shuffle to place them.
8998 int PSHUFLMask[4] = {-1, -1, -1, -1};
8999 int PSHUFHMask[4] = {-1, -1, -1, -1};
9000 int PSHUFDMask[4] = {-1, -1, -1, -1};
9002 // First fix the masks for all the inputs that are staying in their
9003 // original halves. This will then dictate the targets of the cross-half
9005 auto fixInPlaceInputs =
9006 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9007 MutableArrayRef<int> SourceHalfMask,
9008 MutableArrayRef<int> HalfMask, int HalfOffset) {
9009 if (InPlaceInputs.empty())
9011 if (InPlaceInputs.size() == 1) {
9012 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9013 InPlaceInputs[0] - HalfOffset;
9014 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9017 if (IncomingInputs.empty()) {
9018 // Just fix all of the in place inputs.
9019 for (int Input : InPlaceInputs) {
9020 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9021 PSHUFDMask[Input / 2] = Input / 2;
9026 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9027 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9028 InPlaceInputs[0] - HalfOffset;
9029 // Put the second input next to the first so that they are packed into
9030 // a dword. We find the adjacent index by toggling the low bit.
9031 int AdjIndex = InPlaceInputs[0] ^ 1;
9032 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9033 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9034 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9036 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9037 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9039 // Now gather the cross-half inputs and place them into a free dword of
9040 // their target half.
9041 // FIXME: This operation could almost certainly be simplified dramatically to
9042 // look more like the 3-1 fixing operation.
9043 auto moveInputsToRightHalf = [&PSHUFDMask](
9044 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9045 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9046 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9048 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9049 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9051 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9053 int LowWord = Word & ~1;
9054 int HighWord = Word | 1;
9055 return isWordClobbered(SourceHalfMask, LowWord) ||
9056 isWordClobbered(SourceHalfMask, HighWord);
9059 if (IncomingInputs.empty())
9062 if (ExistingInputs.empty()) {
9063 // Map any dwords with inputs from them into the right half.
9064 for (int Input : IncomingInputs) {
9065 // If the source half mask maps over the inputs, turn those into
9066 // swaps and use the swapped lane.
9067 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9068 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9069 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9070 Input - SourceOffset;
9071 // We have to swap the uses in our half mask in one sweep.
9072 for (int &M : HalfMask)
9073 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9075 else if (M == Input)
9076 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9078 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9079 Input - SourceOffset &&
9080 "Previous placement doesn't match!");
9082 // Note that this correctly re-maps both when we do a swap and when
9083 // we observe the other side of the swap above. We rely on that to
9084 // avoid swapping the members of the input list directly.
9085 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9088 // Map the input's dword into the correct half.
9089 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9090 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9092 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9094 "Previous placement doesn't match!");
9097 // And just directly shift any other-half mask elements to be same-half
9098 // as we will have mirrored the dword containing the element into the
9099 // same position within that half.
9100 for (int &M : HalfMask)
9101 if (M >= SourceOffset && M < SourceOffset + 4) {
9102 M = M - SourceOffset + DestOffset;
9103 assert(M >= 0 && "This should never wrap below zero!");
9108 // Ensure we have the input in a viable dword of its current half. This
9109 // is particularly tricky because the original position may be clobbered
9110 // by inputs being moved and *staying* in that half.
9111 if (IncomingInputs.size() == 1) {
9112 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9113 int InputFixed = std::find(std::begin(SourceHalfMask),
9114 std::end(SourceHalfMask), -1) -
9115 std::begin(SourceHalfMask) + SourceOffset;
9116 SourceHalfMask[InputFixed - SourceOffset] =
9117 IncomingInputs[0] - SourceOffset;
9118 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9120 IncomingInputs[0] = InputFixed;
9122 } else if (IncomingInputs.size() == 2) {
9123 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9124 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9125 // We have two non-adjacent or clobbered inputs we need to extract from
9126 // the source half. To do this, we need to map them into some adjacent
9127 // dword slot in the source mask.
9128 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9129 IncomingInputs[1] - SourceOffset};
9131 // If there is a free slot in the source half mask adjacent to one of
9132 // the inputs, place the other input in it. We use (Index XOR 1) to
9133 // compute an adjacent index.
9134 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9135 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9136 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9137 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9138 InputsFixed[1] = InputsFixed[0] ^ 1;
9139 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9140 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9141 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9142 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9143 InputsFixed[0] = InputsFixed[1] ^ 1;
9144 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9145 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9146 // The two inputs are in the same DWord but it is clobbered and the
9147 // adjacent DWord isn't used at all. Move both inputs to the free
9149 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9150 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9151 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9152 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9154 // The only way we hit this point is if there is no clobbering
9155 // (because there are no off-half inputs to this half) and there is no
9156 // free slot adjacent to one of the inputs. In this case, we have to
9157 // swap an input with a non-input.
9158 for (int i = 0; i < 4; ++i)
9159 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9160 "We can't handle any clobbers here!");
9161 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9162 "Cannot have adjacent inputs here!");
9164 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9165 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9167 // We also have to update the final source mask in this case because
9168 // it may need to undo the above swap.
9169 for (int &M : FinalSourceHalfMask)
9170 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9171 M = InputsFixed[1] + SourceOffset;
9172 else if (M == InputsFixed[1] + SourceOffset)
9173 M = (InputsFixed[0] ^ 1) + SourceOffset;
9175 InputsFixed[1] = InputsFixed[0] ^ 1;
9178 // Point everything at the fixed inputs.
9179 for (int &M : HalfMask)
9180 if (M == IncomingInputs[0])
9181 M = InputsFixed[0] + SourceOffset;
9182 else if (M == IncomingInputs[1])
9183 M = InputsFixed[1] + SourceOffset;
9185 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9186 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9189 llvm_unreachable("Unhandled input size!");
9192 // Now hoist the DWord down to the right half.
9193 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9194 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9195 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9196 for (int &M : HalfMask)
9197 for (int Input : IncomingInputs)
9199 M = FreeDWord * 2 + Input % 2;
9201 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9202 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9203 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9204 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9206 // Now enact all the shuffles we've computed to move the inputs into their
9208 if (!isNoopShuffleMask(PSHUFLMask))
9209 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9210 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9211 if (!isNoopShuffleMask(PSHUFHMask))
9212 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9213 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9214 if (!isNoopShuffleMask(PSHUFDMask))
9217 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9218 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9220 // At this point, each half should contain all its inputs, and we can then
9221 // just shuffle them into their final position.
9222 assert(std::count_if(LoMask.begin(), LoMask.end(),
9223 [](int M) { return M >= 4; }) == 0 &&
9224 "Failed to lift all the high half inputs to the low mask!");
9225 assert(std::count_if(HiMask.begin(), HiMask.end(),
9226 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9227 "Failed to lift all the low half inputs to the high mask!");
9229 // Do a half shuffle for the low mask.
9230 if (!isNoopShuffleMask(LoMask))
9231 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9232 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9234 // Do a half shuffle with the high mask after shifting its values down.
9235 for (int &M : HiMask)
9238 if (!isNoopShuffleMask(HiMask))
9239 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9240 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9245 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9246 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9247 SDValue V2, ArrayRef<int> Mask,
9248 SelectionDAG &DAG, bool &V1InUse,
9250 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9256 int Size = Mask.size();
9257 int Scale = 16 / Size;
9258 for (int i = 0; i < 16; ++i) {
9259 if (Mask[i / Scale] == -1) {
9260 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9262 const int ZeroMask = 0x80;
9263 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9265 int V2Idx = Mask[i / Scale] < Size
9267 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9268 if (Zeroable[i / Scale])
9269 V1Idx = V2Idx = ZeroMask;
9270 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9271 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9272 V1InUse |= (ZeroMask != V1Idx);
9273 V2InUse |= (ZeroMask != V2Idx);
9278 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9279 DAG.getBitcast(MVT::v16i8, V1),
9280 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9282 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9283 DAG.getBitcast(MVT::v16i8, V2),
9284 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9286 // If we need shuffled inputs from both, blend the two.
9288 if (V1InUse && V2InUse)
9289 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9291 V = V1InUse ? V1 : V2;
9293 // Cast the result back to the correct type.
9294 return DAG.getBitcast(VT, V);
9297 /// \brief Generic lowering of 8-lane i16 shuffles.
9299 /// This handles both single-input shuffles and combined shuffle/blends with
9300 /// two inputs. The single input shuffles are immediately delegated to
9301 /// a dedicated lowering routine.
9303 /// The blends are lowered in one of three fundamental ways. If there are few
9304 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9305 /// of the input is significantly cheaper when lowered as an interleaving of
9306 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9307 /// halves of the inputs separately (making them have relatively few inputs)
9308 /// and then concatenate them.
9309 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9310 const X86Subtarget *Subtarget,
9311 SelectionDAG &DAG) {
9313 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9314 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9315 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9316 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9317 ArrayRef<int> OrigMask = SVOp->getMask();
9318 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9319 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9320 MutableArrayRef<int> Mask(MaskStorage);
9322 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9324 // Whenever we can lower this as a zext, that instruction is strictly faster
9325 // than any alternative.
9326 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9327 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9330 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9332 auto isV2 = [](int M) { return M >= 8; };
9334 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9336 if (NumV2Inputs == 0) {
9337 // Check for being able to broadcast a single element.
9338 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9339 Mask, Subtarget, DAG))
9342 // Try to use shift instructions.
9344 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9347 // Use dedicated unpack instructions for masks that match their pattern.
9349 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9352 // Try to use byte rotation instructions.
9353 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9354 Mask, Subtarget, DAG))
9357 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9361 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9362 "All single-input shuffles should be canonicalized to be V1-input "
9365 // Try to use shift instructions.
9367 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9370 // See if we can use SSE4A Extraction / Insertion.
9371 if (Subtarget->hasSSE4A())
9372 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9375 // There are special ways we can lower some single-element blends.
9376 if (NumV2Inputs == 1)
9377 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9378 Mask, Subtarget, DAG))
9381 // We have different paths for blend lowering, but they all must use the
9382 // *exact* same predicate.
9383 bool IsBlendSupported = Subtarget->hasSSE41();
9384 if (IsBlendSupported)
9385 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9389 if (SDValue Masked =
9390 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9393 // Use dedicated unpack instructions for masks that match their pattern.
9395 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9398 // Try to use byte rotation instructions.
9399 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9400 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9403 if (SDValue BitBlend =
9404 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9407 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9411 // If we can't directly blend but can use PSHUFB, that will be better as it
9412 // can both shuffle and set up the inefficient blend.
9413 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9414 bool V1InUse, V2InUse;
9415 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9419 // We can always bit-blend if we have to so the fallback strategy is to
9420 // decompose into single-input permutes and blends.
9421 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9425 /// \brief Check whether a compaction lowering can be done by dropping even
9426 /// elements and compute how many times even elements must be dropped.
9428 /// This handles shuffles which take every Nth element where N is a power of
9429 /// two. Example shuffle masks:
9431 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9432 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9433 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9434 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9435 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9436 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9438 /// Any of these lanes can of course be undef.
9440 /// This routine only supports N <= 3.
9441 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9444 /// \returns N above, or the number of times even elements must be dropped if
9445 /// there is such a number. Otherwise returns zero.
9446 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9447 // Figure out whether we're looping over two inputs or just one.
9448 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9450 // The modulus for the shuffle vector entries is based on whether this is
9451 // a single input or not.
9452 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9453 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9454 "We should only be called with masks with a power-of-2 size!");
9456 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9458 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9459 // and 2^3 simultaneously. This is because we may have ambiguity with
9460 // partially undef inputs.
9461 bool ViableForN[3] = {true, true, true};
9463 for (int i = 0, e = Mask.size(); i < e; ++i) {
9464 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9469 bool IsAnyViable = false;
9470 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9471 if (ViableForN[j]) {
9474 // The shuffle mask must be equal to (i * 2^N) % M.
9475 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9478 ViableForN[j] = false;
9480 // Early exit if we exhaust the possible powers of two.
9485 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9489 // Return 0 as there is no viable power of two.
9493 /// \brief Generic lowering of v16i8 shuffles.
9495 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9496 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9497 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9498 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9500 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9501 const X86Subtarget *Subtarget,
9502 SelectionDAG &DAG) {
9504 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9505 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9506 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9507 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9508 ArrayRef<int> Mask = SVOp->getMask();
9509 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9511 // Try to use shift instructions.
9513 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9516 // Try to use byte rotation instructions.
9517 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9518 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9521 // Try to use a zext lowering.
9522 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9523 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9526 // See if we can use SSE4A Extraction / Insertion.
9527 if (Subtarget->hasSSE4A())
9528 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9532 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9534 // For single-input shuffles, there are some nicer lowering tricks we can use.
9535 if (NumV2Elements == 0) {
9536 // Check for being able to broadcast a single element.
9537 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9538 Mask, Subtarget, DAG))
9541 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9542 // Notably, this handles splat and partial-splat shuffles more efficiently.
9543 // However, it only makes sense if the pre-duplication shuffle simplifies
9544 // things significantly. Currently, this means we need to be able to
9545 // express the pre-duplication shuffle as an i16 shuffle.
9547 // FIXME: We should check for other patterns which can be widened into an
9548 // i16 shuffle as well.
9549 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9550 for (int i = 0; i < 16; i += 2)
9551 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9556 auto tryToWidenViaDuplication = [&]() -> SDValue {
9557 if (!canWidenViaDuplication(Mask))
9559 SmallVector<int, 4> LoInputs;
9560 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9561 [](int M) { return M >= 0 && M < 8; });
9562 std::sort(LoInputs.begin(), LoInputs.end());
9563 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9565 SmallVector<int, 4> HiInputs;
9566 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9567 [](int M) { return M >= 8; });
9568 std::sort(HiInputs.begin(), HiInputs.end());
9569 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9572 bool TargetLo = LoInputs.size() >= HiInputs.size();
9573 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9574 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9576 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9577 SmallDenseMap<int, int, 8> LaneMap;
9578 for (int I : InPlaceInputs) {
9579 PreDupI16Shuffle[I/2] = I/2;
9582 int j = TargetLo ? 0 : 4, je = j + 4;
9583 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9584 // Check if j is already a shuffle of this input. This happens when
9585 // there are two adjacent bytes after we move the low one.
9586 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9587 // If we haven't yet mapped the input, search for a slot into which
9589 while (j < je && PreDupI16Shuffle[j] != -1)
9593 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9596 // Map this input with the i16 shuffle.
9597 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9600 // Update the lane map based on the mapping we ended up with.
9601 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9603 V1 = DAG.getBitcast(
9605 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9606 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9608 // Unpack the bytes to form the i16s that will be shuffled into place.
9609 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9610 MVT::v16i8, V1, V1);
9612 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9613 for (int i = 0; i < 16; ++i)
9614 if (Mask[i] != -1) {
9615 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9616 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9617 if (PostDupI16Shuffle[i / 2] == -1)
9618 PostDupI16Shuffle[i / 2] = MappedMask;
9620 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9621 "Conflicting entrties in the original shuffle!");
9623 return DAG.getBitcast(
9625 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9626 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9628 if (SDValue V = tryToWidenViaDuplication())
9632 if (SDValue Masked =
9633 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9636 // Use dedicated unpack instructions for masks that match their pattern.
9638 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9641 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9642 // with PSHUFB. It is important to do this before we attempt to generate any
9643 // blends but after all of the single-input lowerings. If the single input
9644 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9645 // want to preserve that and we can DAG combine any longer sequences into
9646 // a PSHUFB in the end. But once we start blending from multiple inputs,
9647 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9648 // and there are *very* few patterns that would actually be faster than the
9649 // PSHUFB approach because of its ability to zero lanes.
9651 // FIXME: The only exceptions to the above are blends which are exact
9652 // interleavings with direct instructions supporting them. We currently don't
9653 // handle those well here.
9654 if (Subtarget->hasSSSE3()) {
9655 bool V1InUse = false;
9656 bool V2InUse = false;
9658 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9659 DAG, V1InUse, V2InUse);
9661 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9662 // do so. This avoids using them to handle blends-with-zero which is
9663 // important as a single pshufb is significantly faster for that.
9664 if (V1InUse && V2InUse) {
9665 if (Subtarget->hasSSE41())
9666 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9667 Mask, Subtarget, DAG))
9670 // We can use an unpack to do the blending rather than an or in some
9671 // cases. Even though the or may be (very minorly) more efficient, we
9672 // preference this lowering because there are common cases where part of
9673 // the complexity of the shuffles goes away when we do the final blend as
9675 // FIXME: It might be worth trying to detect if the unpack-feeding
9676 // shuffles will both be pshufb, in which case we shouldn't bother with
9678 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9679 DL, MVT::v16i8, V1, V2, Mask, DAG))
9686 // There are special ways we can lower some single-element blends.
9687 if (NumV2Elements == 1)
9688 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9689 Mask, Subtarget, DAG))
9692 if (SDValue BitBlend =
9693 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9696 // Check whether a compaction lowering can be done. This handles shuffles
9697 // which take every Nth element for some even N. See the helper function for
9700 // We special case these as they can be particularly efficiently handled with
9701 // the PACKUSB instruction on x86 and they show up in common patterns of
9702 // rearranging bytes to truncate wide elements.
9703 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9704 // NumEvenDrops is the power of two stride of the elements. Another way of
9705 // thinking about it is that we need to drop the even elements this many
9706 // times to get the original input.
9707 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9709 // First we need to zero all the dropped bytes.
9710 assert(NumEvenDrops <= 3 &&
9711 "No support for dropping even elements more than 3 times.");
9712 // We use the mask type to pick which bytes are preserved based on how many
9713 // elements are dropped.
9714 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9715 SDValue ByteClearMask = DAG.getBitcast(
9716 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9717 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9719 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9721 // Now pack things back together.
9722 V1 = DAG.getBitcast(MVT::v8i16, V1);
9723 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9724 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9725 for (int i = 1; i < NumEvenDrops; ++i) {
9726 Result = DAG.getBitcast(MVT::v8i16, Result);
9727 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9733 // Handle multi-input cases by blending single-input shuffles.
9734 if (NumV2Elements > 0)
9735 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9738 // The fallback path for single-input shuffles widens this into two v8i16
9739 // vectors with unpacks, shuffles those, and then pulls them back together
9743 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9744 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9745 for (int i = 0; i < 16; ++i)
9747 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9749 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9751 SDValue VLoHalf, VHiHalf;
9752 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9753 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9755 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9756 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9757 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9758 [](int M) { return M >= 0 && M % 2 == 1; })) {
9759 // Use a mask to drop the high bytes.
9760 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9761 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9762 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9764 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9765 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9767 // Squash the masks to point directly into VLoHalf.
9768 for (int &M : LoBlendMask)
9771 for (int &M : HiBlendMask)
9775 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9776 // VHiHalf so that we can blend them as i16s.
9777 VLoHalf = DAG.getBitcast(
9778 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9779 VHiHalf = DAG.getBitcast(
9780 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9783 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9784 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9786 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9789 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9791 /// This routine breaks down the specific type of 128-bit shuffle and
9792 /// dispatches to the lowering routines accordingly.
9793 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9794 MVT VT, const X86Subtarget *Subtarget,
9795 SelectionDAG &DAG) {
9796 switch (VT.SimpleTy) {
9798 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9800 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9802 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9804 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9806 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9808 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9811 llvm_unreachable("Unimplemented!");
9815 /// \brief Helper function to test whether a shuffle mask could be
9816 /// simplified by widening the elements being shuffled.
9818 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9819 /// leaves it in an unspecified state.
9821 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9822 /// shuffle masks. The latter have the special property of a '-2' representing
9823 /// a zero-ed lane of a vector.
9824 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9825 SmallVectorImpl<int> &WidenedMask) {
9826 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9827 // If both elements are undef, its trivial.
9828 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9829 WidenedMask.push_back(SM_SentinelUndef);
9833 // Check for an undef mask and a mask value properly aligned to fit with
9834 // a pair of values. If we find such a case, use the non-undef mask's value.
9835 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9836 WidenedMask.push_back(Mask[i + 1] / 2);
9839 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9840 WidenedMask.push_back(Mask[i] / 2);
9844 // When zeroing, we need to spread the zeroing across both lanes to widen.
9845 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9846 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9847 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9848 WidenedMask.push_back(SM_SentinelZero);
9854 // Finally check if the two mask values are adjacent and aligned with
9856 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9857 WidenedMask.push_back(Mask[i] / 2);
9861 // Otherwise we can't safely widen the elements used in this shuffle.
9864 assert(WidenedMask.size() == Mask.size() / 2 &&
9865 "Incorrect size of mask after widening the elements!");
9870 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9872 /// This routine just extracts two subvectors, shuffles them independently, and
9873 /// then concatenates them back together. This should work effectively with all
9874 /// AVX vector shuffle types.
9875 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9876 SDValue V2, ArrayRef<int> Mask,
9877 SelectionDAG &DAG) {
9878 assert(VT.getSizeInBits() >= 256 &&
9879 "Only for 256-bit or wider vector shuffles!");
9880 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9881 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9883 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9884 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9886 int NumElements = VT.getVectorNumElements();
9887 int SplitNumElements = NumElements / 2;
9888 MVT ScalarVT = VT.getVectorElementType();
9889 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9891 // Rather than splitting build-vectors, just build two narrower build
9892 // vectors. This helps shuffling with splats and zeros.
9893 auto SplitVector = [&](SDValue V) {
9894 while (V.getOpcode() == ISD::BITCAST)
9895 V = V->getOperand(0);
9897 MVT OrigVT = V.getSimpleValueType();
9898 int OrigNumElements = OrigVT.getVectorNumElements();
9899 int OrigSplitNumElements = OrigNumElements / 2;
9900 MVT OrigScalarVT = OrigVT.getVectorElementType();
9901 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9905 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9907 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9908 DAG.getIntPtrConstant(0, DL));
9909 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9910 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9913 SmallVector<SDValue, 16> LoOps, HiOps;
9914 for (int i = 0; i < OrigSplitNumElements; ++i) {
9915 LoOps.push_back(BV->getOperand(i));
9916 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9918 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9919 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9921 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9922 DAG.getBitcast(SplitVT, HiV));
9925 SDValue LoV1, HiV1, LoV2, HiV2;
9926 std::tie(LoV1, HiV1) = SplitVector(V1);
9927 std::tie(LoV2, HiV2) = SplitVector(V2);
9929 // Now create two 4-way blends of these half-width vectors.
9930 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9931 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9932 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9933 for (int i = 0; i < SplitNumElements; ++i) {
9934 int M = HalfMask[i];
9935 if (M >= NumElements) {
9936 if (M >= NumElements + SplitNumElements)
9940 V2BlendMask.push_back(M - NumElements);
9941 V1BlendMask.push_back(-1);
9942 BlendMask.push_back(SplitNumElements + i);
9943 } else if (M >= 0) {
9944 if (M >= SplitNumElements)
9948 V2BlendMask.push_back(-1);
9949 V1BlendMask.push_back(M);
9950 BlendMask.push_back(i);
9952 V2BlendMask.push_back(-1);
9953 V1BlendMask.push_back(-1);
9954 BlendMask.push_back(-1);
9958 // Because the lowering happens after all combining takes place, we need to
9959 // manually combine these blend masks as much as possible so that we create
9960 // a minimal number of high-level vector shuffle nodes.
9962 // First try just blending the halves of V1 or V2.
9963 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9964 return DAG.getUNDEF(SplitVT);
9965 if (!UseLoV2 && !UseHiV2)
9966 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9967 if (!UseLoV1 && !UseHiV1)
9968 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9970 SDValue V1Blend, V2Blend;
9971 if (UseLoV1 && UseHiV1) {
9973 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9975 // We only use half of V1 so map the usage down into the final blend mask.
9976 V1Blend = UseLoV1 ? LoV1 : HiV1;
9977 for (int i = 0; i < SplitNumElements; ++i)
9978 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9979 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9981 if (UseLoV2 && UseHiV2) {
9983 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9985 // We only use half of V2 so map the usage down into the final blend mask.
9986 V2Blend = UseLoV2 ? LoV2 : HiV2;
9987 for (int i = 0; i < SplitNumElements; ++i)
9988 if (BlendMask[i] >= SplitNumElements)
9989 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9991 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9993 SDValue Lo = HalfBlend(LoMask);
9994 SDValue Hi = HalfBlend(HiMask);
9995 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9998 /// \brief Either split a vector in halves or decompose the shuffles and the
10001 /// This is provided as a good fallback for many lowerings of non-single-input
10002 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10003 /// between splitting the shuffle into 128-bit components and stitching those
10004 /// back together vs. extracting the single-input shuffles and blending those
10006 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10007 SDValue V2, ArrayRef<int> Mask,
10008 SelectionDAG &DAG) {
10009 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10010 "lower single-input shuffles as it "
10011 "could then recurse on itself.");
10012 int Size = Mask.size();
10014 // If this can be modeled as a broadcast of two elements followed by a blend,
10015 // prefer that lowering. This is especially important because broadcasts can
10016 // often fold with memory operands.
10017 auto DoBothBroadcast = [&] {
10018 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10021 if (V2BroadcastIdx == -1)
10022 V2BroadcastIdx = M - Size;
10023 else if (M - Size != V2BroadcastIdx)
10025 } else if (M >= 0) {
10026 if (V1BroadcastIdx == -1)
10027 V1BroadcastIdx = M;
10028 else if (M != V1BroadcastIdx)
10033 if (DoBothBroadcast())
10034 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10037 // If the inputs all stem from a single 128-bit lane of each input, then we
10038 // split them rather than blending because the split will decompose to
10039 // unusually few instructions.
10040 int LaneCount = VT.getSizeInBits() / 128;
10041 int LaneSize = Size / LaneCount;
10042 SmallBitVector LaneInputs[2];
10043 LaneInputs[0].resize(LaneCount, false);
10044 LaneInputs[1].resize(LaneCount, false);
10045 for (int i = 0; i < Size; ++i)
10047 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10048 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10049 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10051 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10052 // that the decomposed single-input shuffles don't end up here.
10053 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10056 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10057 /// a permutation and blend of those lanes.
10059 /// This essentially blends the out-of-lane inputs to each lane into the lane
10060 /// from a permuted copy of the vector. This lowering strategy results in four
10061 /// instructions in the worst case for a single-input cross lane shuffle which
10062 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10063 /// of. Special cases for each particular shuffle pattern should be handled
10064 /// prior to trying this lowering.
10065 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10066 SDValue V1, SDValue V2,
10067 ArrayRef<int> Mask,
10068 SelectionDAG &DAG) {
10069 // FIXME: This should probably be generalized for 512-bit vectors as well.
10070 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10071 int LaneSize = Mask.size() / 2;
10073 // If there are only inputs from one 128-bit lane, splitting will in fact be
10074 // less expensive. The flags track whether the given lane contains an element
10075 // that crosses to another lane.
10076 bool LaneCrossing[2] = {false, false};
10077 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10078 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10079 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10080 if (!LaneCrossing[0] || !LaneCrossing[1])
10081 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10083 if (isSingleInputShuffleMask(Mask)) {
10084 SmallVector<int, 32> FlippedBlendMask;
10085 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10086 FlippedBlendMask.push_back(
10087 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10089 : Mask[i] % LaneSize +
10090 (i / LaneSize) * LaneSize + Size));
10092 // Flip the vector, and blend the results which should now be in-lane. The
10093 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10094 // 5 for the high source. The value 3 selects the high half of source 2 and
10095 // the value 2 selects the low half of source 2. We only use source 2 to
10096 // allow folding it into a memory operand.
10097 unsigned PERMMask = 3 | 2 << 4;
10098 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10099 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10100 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10103 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10104 // will be handled by the above logic and a blend of the results, much like
10105 // other patterns in AVX.
10106 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10109 /// \brief Handle lowering 2-lane 128-bit shuffles.
10110 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10111 SDValue V2, ArrayRef<int> Mask,
10112 const X86Subtarget *Subtarget,
10113 SelectionDAG &DAG) {
10114 // TODO: If minimizing size and one of the inputs is a zero vector and the
10115 // the zero vector has only one use, we could use a VPERM2X128 to save the
10116 // instruction bytes needed to explicitly generate the zero vector.
10118 // Blends are faster and handle all the non-lane-crossing cases.
10119 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10123 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10124 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10126 // If either input operand is a zero vector, use VPERM2X128 because its mask
10127 // allows us to replace the zero input with an implicit zero.
10128 if (!IsV1Zero && !IsV2Zero) {
10129 // Check for patterns which can be matched with a single insert of a 128-bit
10131 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10132 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10133 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10134 VT.getVectorNumElements() / 2);
10135 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10136 DAG.getIntPtrConstant(0, DL));
10137 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10138 OnlyUsesV1 ? V1 : V2,
10139 DAG.getIntPtrConstant(0, DL));
10140 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10144 // Otherwise form a 128-bit permutation. After accounting for undefs,
10145 // convert the 64-bit shuffle mask selection values into 128-bit
10146 // selection bits by dividing the indexes by 2 and shifting into positions
10147 // defined by a vperm2*128 instruction's immediate control byte.
10149 // The immediate permute control byte looks like this:
10150 // [1:0] - select 128 bits from sources for low half of destination
10152 // [3] - zero low half of destination
10153 // [5:4] - select 128 bits from sources for high half of destination
10155 // [7] - zero high half of destination
10157 int MaskLO = Mask[0];
10158 if (MaskLO == SM_SentinelUndef)
10159 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10161 int MaskHI = Mask[2];
10162 if (MaskHI == SM_SentinelUndef)
10163 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10165 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10167 // If either input is a zero vector, replace it with an undef input.
10168 // Shuffle mask values < 4 are selecting elements of V1.
10169 // Shuffle mask values >= 4 are selecting elements of V2.
10170 // Adjust each half of the permute mask by clearing the half that was
10171 // selecting the zero vector and setting the zero mask bit.
10173 V1 = DAG.getUNDEF(VT);
10175 PermMask = (PermMask & 0xf0) | 0x08;
10177 PermMask = (PermMask & 0x0f) | 0x80;
10180 V2 = DAG.getUNDEF(VT);
10182 PermMask = (PermMask & 0xf0) | 0x08;
10184 PermMask = (PermMask & 0x0f) | 0x80;
10187 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10188 DAG.getConstant(PermMask, DL, MVT::i8));
10191 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10192 /// shuffling each lane.
10194 /// This will only succeed when the result of fixing the 128-bit lanes results
10195 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10196 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10197 /// the lane crosses early and then use simpler shuffles within each lane.
10199 /// FIXME: It might be worthwhile at some point to support this without
10200 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10201 /// in x86 only floating point has interesting non-repeating shuffles, and even
10202 /// those are still *marginally* more expensive.
10203 static SDValue lowerVectorShuffleByMerging128BitLanes(
10204 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10205 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10206 assert(!isSingleInputShuffleMask(Mask) &&
10207 "This is only useful with multiple inputs.");
10209 int Size = Mask.size();
10210 int LaneSize = 128 / VT.getScalarSizeInBits();
10211 int NumLanes = Size / LaneSize;
10212 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10214 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10215 // check whether the in-128-bit lane shuffles share a repeating pattern.
10216 SmallVector<int, 4> Lanes;
10217 Lanes.resize(NumLanes, -1);
10218 SmallVector<int, 4> InLaneMask;
10219 InLaneMask.resize(LaneSize, -1);
10220 for (int i = 0; i < Size; ++i) {
10224 int j = i / LaneSize;
10226 if (Lanes[j] < 0) {
10227 // First entry we've seen for this lane.
10228 Lanes[j] = Mask[i] / LaneSize;
10229 } else if (Lanes[j] != Mask[i] / LaneSize) {
10230 // This doesn't match the lane selected previously!
10234 // Check that within each lane we have a consistent shuffle mask.
10235 int k = i % LaneSize;
10236 if (InLaneMask[k] < 0) {
10237 InLaneMask[k] = Mask[i] % LaneSize;
10238 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10239 // This doesn't fit a repeating in-lane mask.
10244 // First shuffle the lanes into place.
10245 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10246 VT.getSizeInBits() / 64);
10247 SmallVector<int, 8> LaneMask;
10248 LaneMask.resize(NumLanes * 2, -1);
10249 for (int i = 0; i < NumLanes; ++i)
10250 if (Lanes[i] >= 0) {
10251 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10252 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10255 V1 = DAG.getBitcast(LaneVT, V1);
10256 V2 = DAG.getBitcast(LaneVT, V2);
10257 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10259 // Cast it back to the type we actually want.
10260 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10262 // Now do a simple shuffle that isn't lane crossing.
10263 SmallVector<int, 8> NewMask;
10264 NewMask.resize(Size, -1);
10265 for (int i = 0; i < Size; ++i)
10267 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10268 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10269 "Must not introduce lane crosses at this point!");
10271 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10274 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10277 /// This returns true if the elements from a particular input are already in the
10278 /// slot required by the given mask and require no permutation.
10279 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10280 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10281 int Size = Mask.size();
10282 for (int i = 0; i < Size; ++i)
10283 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10289 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10290 ArrayRef<int> Mask, SDValue V1,
10291 SDValue V2, SelectionDAG &DAG) {
10293 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10294 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10295 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10296 int NumElts = VT.getVectorNumElements();
10297 bool ShufpdMask = true;
10298 bool CommutableMask = true;
10299 unsigned Immediate = 0;
10300 for (int i = 0; i < NumElts; ++i) {
10303 int Val = (i & 6) + NumElts * (i & 1);
10304 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10305 if (Mask[i] < Val || Mask[i] > Val + 1)
10306 ShufpdMask = false;
10307 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10308 CommutableMask = false;
10309 Immediate |= (Mask[i] % 2) << i;
10312 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10313 DAG.getConstant(Immediate, DL, MVT::i8));
10314 if (CommutableMask)
10315 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10316 DAG.getConstant(Immediate, DL, MVT::i8));
10320 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10322 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10323 /// isn't available.
10324 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10325 const X86Subtarget *Subtarget,
10326 SelectionDAG &DAG) {
10328 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10329 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10330 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10331 ArrayRef<int> Mask = SVOp->getMask();
10332 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10334 SmallVector<int, 4> WidenedMask;
10335 if (canWidenShuffleElements(Mask, WidenedMask))
10336 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10339 if (isSingleInputShuffleMask(Mask)) {
10340 // Check for being able to broadcast a single element.
10341 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10342 Mask, Subtarget, DAG))
10345 // Use low duplicate instructions for masks that match their pattern.
10346 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10347 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10349 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10350 // Non-half-crossing single input shuffles can be lowerid with an
10351 // interleaved permutation.
10352 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10353 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10354 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10355 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10358 // With AVX2 we have direct support for this permutation.
10359 if (Subtarget->hasAVX2())
10360 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10361 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10363 // Otherwise, fall back.
10364 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10368 // Use dedicated unpack instructions for masks that match their pattern.
10370 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10373 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10377 // Check if the blend happens to exactly fit that of SHUFPD.
10379 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10382 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10383 // shuffle. However, if we have AVX2 and either inputs are already in place,
10384 // we will be able to shuffle even across lanes the other input in a single
10385 // instruction so skip this pattern.
10386 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10387 isShuffleMaskInputInPlace(1, Mask))))
10388 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10389 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10392 // If we have AVX2 then we always want to lower with a blend because an v4 we
10393 // can fully permute the elements.
10394 if (Subtarget->hasAVX2())
10395 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10398 // Otherwise fall back on generic lowering.
10399 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10402 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10404 /// This routine is only called when we have AVX2 and thus a reasonable
10405 /// instruction set for v4i64 shuffling..
10406 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10407 const X86Subtarget *Subtarget,
10408 SelectionDAG &DAG) {
10410 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10411 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10412 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10413 ArrayRef<int> Mask = SVOp->getMask();
10414 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10415 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10417 SmallVector<int, 4> WidenedMask;
10418 if (canWidenShuffleElements(Mask, WidenedMask))
10419 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10422 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10426 // Check for being able to broadcast a single element.
10427 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10428 Mask, Subtarget, DAG))
10431 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10432 // use lower latency instructions that will operate on both 128-bit lanes.
10433 SmallVector<int, 2> RepeatedMask;
10434 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10435 if (isSingleInputShuffleMask(Mask)) {
10436 int PSHUFDMask[] = {-1, -1, -1, -1};
10437 for (int i = 0; i < 2; ++i)
10438 if (RepeatedMask[i] >= 0) {
10439 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10440 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10442 return DAG.getBitcast(
10444 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10445 DAG.getBitcast(MVT::v8i32, V1),
10446 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10450 // AVX2 provides a direct instruction for permuting a single input across
10452 if (isSingleInputShuffleMask(Mask))
10453 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10454 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10456 // Try to use shift instructions.
10457 if (SDValue Shift =
10458 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10461 // Use dedicated unpack instructions for masks that match their pattern.
10463 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10466 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10467 // shuffle. However, if we have AVX2 and either inputs are already in place,
10468 // we will be able to shuffle even across lanes the other input in a single
10469 // instruction so skip this pattern.
10470 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10471 isShuffleMaskInputInPlace(1, Mask))))
10472 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10473 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10476 // Otherwise fall back on generic blend lowering.
10477 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10481 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10483 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10484 /// isn't available.
10485 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10486 const X86Subtarget *Subtarget,
10487 SelectionDAG &DAG) {
10489 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10490 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10491 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10492 ArrayRef<int> Mask = SVOp->getMask();
10493 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10495 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10499 // Check for being able to broadcast a single element.
10500 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10501 Mask, Subtarget, DAG))
10504 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10505 // options to efficiently lower the shuffle.
10506 SmallVector<int, 4> RepeatedMask;
10507 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10508 assert(RepeatedMask.size() == 4 &&
10509 "Repeated masks must be half the mask width!");
10511 // Use even/odd duplicate instructions for masks that match their pattern.
10512 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10513 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10514 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10515 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10517 if (isSingleInputShuffleMask(Mask))
10518 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10519 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10521 // Use dedicated unpack instructions for masks that match their pattern.
10523 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10526 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10527 // have already handled any direct blends. We also need to squash the
10528 // repeated mask into a simulated v4f32 mask.
10529 for (int i = 0; i < 4; ++i)
10530 if (RepeatedMask[i] >= 8)
10531 RepeatedMask[i] -= 4;
10532 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10535 // If we have a single input shuffle with different shuffle patterns in the
10536 // two 128-bit lanes use the variable mask to VPERMILPS.
10537 if (isSingleInputShuffleMask(Mask)) {
10538 SDValue VPermMask[8];
10539 for (int i = 0; i < 8; ++i)
10540 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10541 : DAG.getConstant(Mask[i], DL, MVT::i32);
10542 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10543 return DAG.getNode(
10544 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10545 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10547 if (Subtarget->hasAVX2())
10548 return DAG.getNode(
10549 X86ISD::VPERMV, DL, MVT::v8f32,
10550 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10551 MVT::v8i32, VPermMask)),
10554 // Otherwise, fall back.
10555 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10559 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10561 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10562 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10565 // If we have AVX2 then we always want to lower with a blend because at v8 we
10566 // can fully permute the elements.
10567 if (Subtarget->hasAVX2())
10568 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10571 // Otherwise fall back on generic lowering.
10572 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10575 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10577 /// This routine is only called when we have AVX2 and thus a reasonable
10578 /// instruction set for v8i32 shuffling..
10579 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10580 const X86Subtarget *Subtarget,
10581 SelectionDAG &DAG) {
10583 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10584 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10585 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10586 ArrayRef<int> Mask = SVOp->getMask();
10587 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10588 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10590 // Whenever we can lower this as a zext, that instruction is strictly faster
10591 // than any alternative. It also allows us to fold memory operands into the
10592 // shuffle in many cases.
10593 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10594 Mask, Subtarget, DAG))
10597 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10601 // Check for being able to broadcast a single element.
10602 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10603 Mask, Subtarget, DAG))
10606 // If the shuffle mask is repeated in each 128-bit lane we can use more
10607 // efficient instructions that mirror the shuffles across the two 128-bit
10609 SmallVector<int, 4> RepeatedMask;
10610 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10611 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10612 if (isSingleInputShuffleMask(Mask))
10613 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10614 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10616 // Use dedicated unpack instructions for masks that match their pattern.
10618 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10622 // Try to use shift instructions.
10623 if (SDValue Shift =
10624 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10627 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10628 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10631 // If the shuffle patterns aren't repeated but it is a single input, directly
10632 // generate a cross-lane VPERMD instruction.
10633 if (isSingleInputShuffleMask(Mask)) {
10634 SDValue VPermMask[8];
10635 for (int i = 0; i < 8; ++i)
10636 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10637 : DAG.getConstant(Mask[i], DL, MVT::i32);
10638 return DAG.getNode(
10639 X86ISD::VPERMV, DL, MVT::v8i32,
10640 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10643 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10645 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10646 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10649 // Otherwise fall back on generic blend lowering.
10650 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10654 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10656 /// This routine is only called when we have AVX2 and thus a reasonable
10657 /// instruction set for v16i16 shuffling..
10658 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10659 const X86Subtarget *Subtarget,
10660 SelectionDAG &DAG) {
10662 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10663 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10664 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10665 ArrayRef<int> Mask = SVOp->getMask();
10666 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10667 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10669 // Whenever we can lower this as a zext, that instruction is strictly faster
10670 // than any alternative. It also allows us to fold memory operands into the
10671 // shuffle in many cases.
10672 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10673 Mask, Subtarget, DAG))
10676 // Check for being able to broadcast a single element.
10677 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10678 Mask, Subtarget, DAG))
10681 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10685 // Use dedicated unpack instructions for masks that match their pattern.
10687 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10690 // Try to use shift instructions.
10691 if (SDValue Shift =
10692 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10695 // Try to use byte rotation instructions.
10696 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10697 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10700 if (isSingleInputShuffleMask(Mask)) {
10701 // There are no generalized cross-lane shuffle operations available on i16
10703 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10704 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10707 SmallVector<int, 8> RepeatedMask;
10708 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10709 // As this is a single-input shuffle, the repeated mask should be
10710 // a strictly valid v8i16 mask that we can pass through to the v8i16
10711 // lowering to handle even the v16 case.
10712 return lowerV8I16GeneralSingleInputVectorShuffle(
10713 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10716 SDValue PSHUFBMask[32];
10717 for (int i = 0; i < 16; ++i) {
10718 if (Mask[i] == -1) {
10719 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10723 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10724 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10725 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10726 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10728 return DAG.getBitcast(MVT::v16i16,
10729 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10730 DAG.getBitcast(MVT::v32i8, V1),
10731 DAG.getNode(ISD::BUILD_VECTOR, DL,
10732 MVT::v32i8, PSHUFBMask)));
10735 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10737 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10738 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10741 // Otherwise fall back on generic lowering.
10742 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10745 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10747 /// This routine is only called when we have AVX2 and thus a reasonable
10748 /// instruction set for v32i8 shuffling..
10749 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10750 const X86Subtarget *Subtarget,
10751 SelectionDAG &DAG) {
10753 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10754 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10755 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10756 ArrayRef<int> Mask = SVOp->getMask();
10757 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10758 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10760 // Whenever we can lower this as a zext, that instruction is strictly faster
10761 // than any alternative. It also allows us to fold memory operands into the
10762 // shuffle in many cases.
10763 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10764 Mask, Subtarget, DAG))
10767 // Check for being able to broadcast a single element.
10768 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10769 Mask, Subtarget, DAG))
10772 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10776 // Use dedicated unpack instructions for masks that match their pattern.
10778 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10781 // Try to use shift instructions.
10782 if (SDValue Shift =
10783 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10786 // Try to use byte rotation instructions.
10787 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10788 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10791 if (isSingleInputShuffleMask(Mask)) {
10792 // There are no generalized cross-lane shuffle operations available on i8
10794 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10795 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10798 SDValue PSHUFBMask[32];
10799 for (int i = 0; i < 32; ++i)
10802 ? DAG.getUNDEF(MVT::i8)
10803 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10806 return DAG.getNode(
10807 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10808 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10811 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10813 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10814 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10817 // Otherwise fall back on generic lowering.
10818 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10821 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10823 /// This routine either breaks down the specific type of a 256-bit x86 vector
10824 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10825 /// together based on the available instructions.
10826 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10827 MVT VT, const X86Subtarget *Subtarget,
10828 SelectionDAG &DAG) {
10830 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10831 ArrayRef<int> Mask = SVOp->getMask();
10833 // If we have a single input to the zero element, insert that into V1 if we
10834 // can do so cheaply.
10835 int NumElts = VT.getVectorNumElements();
10836 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10837 return M >= NumElts;
10840 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10841 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10842 DL, VT, V1, V2, Mask, Subtarget, DAG))
10845 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10846 // can check for those subtargets here and avoid much of the subtarget
10847 // querying in the per-vector-type lowering routines. With AVX1 we have
10848 // essentially *zero* ability to manipulate a 256-bit vector with integer
10849 // types. Since we'll use floating point types there eventually, just
10850 // immediately cast everything to a float and operate entirely in that domain.
10851 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10852 int ElementBits = VT.getScalarSizeInBits();
10853 if (ElementBits < 32)
10854 // No floating point type available, decompose into 128-bit vectors.
10855 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10857 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10858 VT.getVectorNumElements());
10859 V1 = DAG.getBitcast(FpVT, V1);
10860 V2 = DAG.getBitcast(FpVT, V2);
10861 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10864 switch (VT.SimpleTy) {
10866 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10868 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10870 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10872 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10874 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10876 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10879 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10883 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10884 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10885 ArrayRef<int> Mask,
10886 SDValue V1, SDValue V2,
10887 SelectionDAG &DAG) {
10888 assert(VT.getScalarSizeInBits() == 64 &&
10889 "Unexpected element type size for 128bit shuffle.");
10891 // To handle 256 bit vector requires VLX and most probably
10892 // function lowerV2X128VectorShuffle() is better solution.
10893 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10895 SmallVector<int, 4> WidenedMask;
10896 if (!canWidenShuffleElements(Mask, WidenedMask))
10899 // Form a 128-bit permutation.
10900 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10901 // bits defined by a vshuf64x2 instruction's immediate control byte.
10902 unsigned PermMask = 0, Imm = 0;
10903 unsigned ControlBitsNum = WidenedMask.size() / 2;
10905 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10906 if (WidenedMask[i] == SM_SentinelZero)
10909 // Use first element in place of undef mask.
10910 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10911 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10914 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10915 DAG.getConstant(PermMask, DL, MVT::i8));
10918 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10919 ArrayRef<int> Mask, SDValue V1,
10920 SDValue V2, SelectionDAG &DAG) {
10922 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10924 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10925 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10927 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10928 if (isSingleInputShuffleMask(Mask))
10929 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10931 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10934 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10935 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10936 const X86Subtarget *Subtarget,
10937 SelectionDAG &DAG) {
10939 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10940 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10941 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10942 ArrayRef<int> Mask = SVOp->getMask();
10943 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10945 if (SDValue Shuf128 =
10946 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10949 if (SDValue Unpck =
10950 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10953 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10956 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10957 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10958 const X86Subtarget *Subtarget,
10959 SelectionDAG &DAG) {
10961 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10962 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10963 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10964 ArrayRef<int> Mask = SVOp->getMask();
10965 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10967 if (SDValue Unpck =
10968 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10971 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10974 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10975 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10976 const X86Subtarget *Subtarget,
10977 SelectionDAG &DAG) {
10979 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10980 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10982 ArrayRef<int> Mask = SVOp->getMask();
10983 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10985 if (SDValue Shuf128 =
10986 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10989 if (SDValue Unpck =
10990 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10993 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10996 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10997 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10998 const X86Subtarget *Subtarget,
10999 SelectionDAG &DAG) {
11001 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11002 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11003 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11004 ArrayRef<int> Mask = SVOp->getMask();
11005 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11007 if (SDValue Unpck =
11008 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11011 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11014 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11015 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11016 const X86Subtarget *Subtarget,
11017 SelectionDAG &DAG) {
11019 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11020 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11021 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11022 ArrayRef<int> Mask = SVOp->getMask();
11023 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11024 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11026 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11029 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11030 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11031 const X86Subtarget *Subtarget,
11032 SelectionDAG &DAG) {
11034 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11035 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11037 ArrayRef<int> Mask = SVOp->getMask();
11038 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11039 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11041 // FIXME: Implement direct support for this type!
11042 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11045 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11047 /// This routine either breaks down the specific type of a 512-bit x86 vector
11048 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11049 /// together based on the available instructions.
11050 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11051 MVT VT, const X86Subtarget *Subtarget,
11052 SelectionDAG &DAG) {
11054 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11055 ArrayRef<int> Mask = SVOp->getMask();
11056 assert(Subtarget->hasAVX512() &&
11057 "Cannot lower 512-bit vectors w/ basic ISA!");
11059 // Check for being able to broadcast a single element.
11060 if (SDValue Broadcast =
11061 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11064 // Dispatch to each element type for lowering. If we don't have supprot for
11065 // specific element type shuffles at 512 bits, immediately split them and
11066 // lower them. Each lowering routine of a given type is allowed to assume that
11067 // the requisite ISA extensions for that element type are available.
11068 switch (VT.SimpleTy) {
11070 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11072 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11074 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11076 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11078 if (Subtarget->hasBWI())
11079 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11082 if (Subtarget->hasBWI())
11083 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11087 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11090 // Otherwise fall back on splitting.
11091 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11094 // Lower vXi1 vector shuffles.
11095 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11096 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11097 // vector, shuffle and then truncate it back.
11098 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11099 MVT VT, const X86Subtarget *Subtarget,
11100 SelectionDAG &DAG) {
11102 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11103 ArrayRef<int> Mask = SVOp->getMask();
11104 assert(Subtarget->hasAVX512() &&
11105 "Cannot lower 512-bit vectors w/o basic ISA!");
11107 switch (VT.SimpleTy) {
11109 llvm_unreachable("Expected a vector of i1 elements");
11111 ExtVT = MVT::v2i64;
11114 ExtVT = MVT::v4i32;
11117 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11120 ExtVT = MVT::v16i32;
11123 ExtVT = MVT::v32i16;
11126 ExtVT = MVT::v64i8;
11130 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11131 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11132 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11133 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11135 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11138 V2 = DAG.getUNDEF(ExtVT);
11139 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11140 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11141 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11142 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11144 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11145 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11146 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11148 /// \brief Top-level lowering for x86 vector shuffles.
11150 /// This handles decomposition, canonicalization, and lowering of all x86
11151 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11152 /// above in helper routines. The canonicalization attempts to widen shuffles
11153 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11154 /// s.t. only one of the two inputs needs to be tested, etc.
11155 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11156 SelectionDAG &DAG) {
11157 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11158 ArrayRef<int> Mask = SVOp->getMask();
11159 SDValue V1 = Op.getOperand(0);
11160 SDValue V2 = Op.getOperand(1);
11161 MVT VT = Op.getSimpleValueType();
11162 int NumElements = VT.getVectorNumElements();
11164 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11166 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11167 "Can't lower MMX shuffles");
11169 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11170 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11171 if (V1IsUndef && V2IsUndef)
11172 return DAG.getUNDEF(VT);
11174 // When we create a shuffle node we put the UNDEF node to second operand,
11175 // but in some cases the first operand may be transformed to UNDEF.
11176 // In this case we should just commute the node.
11178 return DAG.getCommutedVectorShuffle(*SVOp);
11180 // Check for non-undef masks pointing at an undef vector and make the masks
11181 // undef as well. This makes it easier to match the shuffle based solely on
11185 if (M >= NumElements) {
11186 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11187 for (int &M : NewMask)
11188 if (M >= NumElements)
11190 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11193 // We actually see shuffles that are entirely re-arrangements of a set of
11194 // zero inputs. This mostly happens while decomposing complex shuffles into
11195 // simple ones. Directly lower these as a buildvector of zeros.
11196 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11197 if (Zeroable.all())
11198 return getZeroVector(VT, Subtarget, DAG, dl);
11200 // Try to collapse shuffles into using a vector type with fewer elements but
11201 // wider element types. We cap this to not form integers or floating point
11202 // elements wider than 64 bits, but it might be interesting to form i128
11203 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11204 SmallVector<int, 16> WidenedMask;
11205 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11206 canWidenShuffleElements(Mask, WidenedMask)) {
11207 MVT NewEltVT = VT.isFloatingPoint()
11208 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11209 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11210 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11211 // Make sure that the new vector type is legal. For example, v2f64 isn't
11213 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11214 V1 = DAG.getBitcast(NewVT, V1);
11215 V2 = DAG.getBitcast(NewVT, V2);
11216 return DAG.getBitcast(
11217 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11221 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11222 for (int M : SVOp->getMask())
11224 ++NumUndefElements;
11225 else if (M < NumElements)
11230 // Commute the shuffle as needed such that more elements come from V1 than
11231 // V2. This allows us to match the shuffle pattern strictly on how many
11232 // elements come from V1 without handling the symmetric cases.
11233 if (NumV2Elements > NumV1Elements)
11234 return DAG.getCommutedVectorShuffle(*SVOp);
11236 // When the number of V1 and V2 elements are the same, try to minimize the
11237 // number of uses of V2 in the low half of the vector. When that is tied,
11238 // ensure that the sum of indices for V1 is equal to or lower than the sum
11239 // indices for V2. When those are equal, try to ensure that the number of odd
11240 // indices for V1 is lower than the number of odd indices for V2.
11241 if (NumV1Elements == NumV2Elements) {
11242 int LowV1Elements = 0, LowV2Elements = 0;
11243 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11244 if (M >= NumElements)
11248 if (LowV2Elements > LowV1Elements) {
11249 return DAG.getCommutedVectorShuffle(*SVOp);
11250 } else if (LowV2Elements == LowV1Elements) {
11251 int SumV1Indices = 0, SumV2Indices = 0;
11252 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11253 if (SVOp->getMask()[i] >= NumElements)
11255 else if (SVOp->getMask()[i] >= 0)
11257 if (SumV2Indices < SumV1Indices) {
11258 return DAG.getCommutedVectorShuffle(*SVOp);
11259 } else if (SumV2Indices == SumV1Indices) {
11260 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11261 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11262 if (SVOp->getMask()[i] >= NumElements)
11263 NumV2OddIndices += i % 2;
11264 else if (SVOp->getMask()[i] >= 0)
11265 NumV1OddIndices += i % 2;
11266 if (NumV2OddIndices < NumV1OddIndices)
11267 return DAG.getCommutedVectorShuffle(*SVOp);
11272 // For each vector width, delegate to a specialized lowering routine.
11273 if (VT.is128BitVector())
11274 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11276 if (VT.is256BitVector())
11277 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11279 if (VT.is512BitVector())
11280 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11283 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11284 llvm_unreachable("Unimplemented!");
11287 // This function assumes its argument is a BUILD_VECTOR of constants or
11288 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11290 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11291 unsigned &MaskValue) {
11293 unsigned NumElems = BuildVector->getNumOperands();
11295 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11296 // We don't handle the >2 lanes case right now.
11297 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11301 unsigned NumElemsInLane = NumElems / NumLanes;
11303 // Blend for v16i16 should be symmetric for the both lanes.
11304 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11305 SDValue EltCond = BuildVector->getOperand(i);
11306 SDValue SndLaneEltCond =
11307 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11309 int Lane1Cond = -1, Lane2Cond = -1;
11310 if (isa<ConstantSDNode>(EltCond))
11311 Lane1Cond = !isZero(EltCond);
11312 if (isa<ConstantSDNode>(SndLaneEltCond))
11313 Lane2Cond = !isZero(SndLaneEltCond);
11315 unsigned LaneMask = 0;
11316 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11317 // Lane1Cond != 0, means we want the first argument.
11318 // Lane1Cond == 0, means we want the second argument.
11319 // The encoding of this argument is 0 for the first argument, 1
11320 // for the second. Therefore, invert the condition.
11321 LaneMask = !Lane1Cond << i;
11322 else if (Lane1Cond < 0)
11323 LaneMask = !Lane2Cond << i;
11327 MaskValue |= LaneMask;
11329 MaskValue |= LaneMask << NumElemsInLane;
11334 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11335 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11336 const X86Subtarget *Subtarget,
11337 SelectionDAG &DAG) {
11338 SDValue Cond = Op.getOperand(0);
11339 SDValue LHS = Op.getOperand(1);
11340 SDValue RHS = Op.getOperand(2);
11342 MVT VT = Op.getSimpleValueType();
11344 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11346 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11348 // Only non-legal VSELECTs reach this lowering, convert those into generic
11349 // shuffles and re-use the shuffle lowering path for blends.
11350 SmallVector<int, 32> Mask;
11351 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11352 SDValue CondElt = CondBV->getOperand(i);
11354 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11356 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11359 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11360 // A vselect where all conditions and data are constants can be optimized into
11361 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11362 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11363 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11364 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11367 // Try to lower this to a blend-style vector shuffle. This can handle all
11368 // constant condition cases.
11369 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11372 // Variable blends are only legal from SSE4.1 onward.
11373 if (!Subtarget->hasSSE41())
11376 // Only some types will be legal on some subtargets. If we can emit a legal
11377 // VSELECT-matching blend, return Op, and but if we need to expand, return
11379 switch (Op.getSimpleValueType().SimpleTy) {
11381 // Most of the vector types have blends past SSE4.1.
11385 // The byte blends for AVX vectors were introduced only in AVX2.
11386 if (Subtarget->hasAVX2())
11393 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11394 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11397 // FIXME: We should custom lower this by fixing the condition and using i8
11403 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11404 MVT VT = Op.getSimpleValueType();
11407 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11410 if (VT.getSizeInBits() == 8) {
11411 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11412 Op.getOperand(0), Op.getOperand(1));
11413 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11414 DAG.getValueType(VT));
11415 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11418 if (VT.getSizeInBits() == 16) {
11419 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11420 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11422 return DAG.getNode(
11423 ISD::TRUNCATE, dl, MVT::i16,
11424 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11425 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11426 Op.getOperand(1)));
11427 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11428 Op.getOperand(0), Op.getOperand(1));
11429 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11430 DAG.getValueType(VT));
11431 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11434 if (VT == MVT::f32) {
11435 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11436 // the result back to FR32 register. It's only worth matching if the
11437 // result has a single use which is a store or a bitcast to i32. And in
11438 // the case of a store, it's not worth it if the index is a constant 0,
11439 // because a MOVSSmr can be used instead, which is smaller and faster.
11440 if (!Op.hasOneUse())
11442 SDNode *User = *Op.getNode()->use_begin();
11443 if ((User->getOpcode() != ISD::STORE ||
11444 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11445 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11446 (User->getOpcode() != ISD::BITCAST ||
11447 User->getValueType(0) != MVT::i32))
11449 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11450 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11452 return DAG.getBitcast(MVT::f32, Extract);
11455 if (VT == MVT::i32 || VT == MVT::i64) {
11456 // ExtractPS/pextrq works with constant index.
11457 if (isa<ConstantSDNode>(Op.getOperand(1)))
11463 /// Extract one bit from mask vector, like v16i1 or v8i1.
11464 /// AVX-512 feature.
11466 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11467 SDValue Vec = Op.getOperand(0);
11469 MVT VecVT = Vec.getSimpleValueType();
11470 SDValue Idx = Op.getOperand(1);
11471 MVT EltVT = Op.getSimpleValueType();
11473 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11474 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11475 "Unexpected vector type in ExtractBitFromMaskVector");
11477 // variable index can't be handled in mask registers,
11478 // extend vector to VR512
11479 if (!isa<ConstantSDNode>(Idx)) {
11480 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11481 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11482 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11483 ExtVT.getVectorElementType(), Ext, Idx);
11484 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11487 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11488 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11489 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11490 rc = getRegClassFor(MVT::v16i1);
11491 unsigned MaxSift = rc->getSize()*8 - 1;
11492 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11493 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11494 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11495 DAG.getConstant(MaxSift, dl, MVT::i8));
11496 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11497 DAG.getIntPtrConstant(0, dl));
11501 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11502 SelectionDAG &DAG) const {
11504 SDValue Vec = Op.getOperand(0);
11505 MVT VecVT = Vec.getSimpleValueType();
11506 SDValue Idx = Op.getOperand(1);
11508 if (Op.getSimpleValueType() == MVT::i1)
11509 return ExtractBitFromMaskVector(Op, DAG);
11511 if (!isa<ConstantSDNode>(Idx)) {
11512 if (VecVT.is512BitVector() ||
11513 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11514 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11517 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11518 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11519 MaskEltVT.getSizeInBits());
11521 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11522 auto PtrVT = getPointerTy(DAG.getDataLayout());
11523 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11524 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11525 DAG.getConstant(0, dl, PtrVT));
11526 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11527 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11528 DAG.getConstant(0, dl, PtrVT));
11533 // If this is a 256-bit vector result, first extract the 128-bit vector and
11534 // then extract the element from the 128-bit vector.
11535 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11537 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11538 // Get the 128-bit vector.
11539 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11540 MVT EltVT = VecVT.getVectorElementType();
11542 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11543 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11545 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11546 // this can be done with a mask.
11547 IdxVal &= ElemsPerChunk - 1;
11548 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11549 DAG.getConstant(IdxVal, dl, MVT::i32));
11552 assert(VecVT.is128BitVector() && "Unexpected vector length");
11554 if (Subtarget->hasSSE41())
11555 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11558 MVT VT = Op.getSimpleValueType();
11559 // TODO: handle v16i8.
11560 if (VT.getSizeInBits() == 16) {
11561 SDValue Vec = Op.getOperand(0);
11562 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11564 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11565 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11566 DAG.getBitcast(MVT::v4i32, Vec),
11567 Op.getOperand(1)));
11568 // Transform it so it match pextrw which produces a 32-bit result.
11569 MVT EltVT = MVT::i32;
11570 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11571 Op.getOperand(0), Op.getOperand(1));
11572 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11573 DAG.getValueType(VT));
11574 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11577 if (VT.getSizeInBits() == 32) {
11578 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11582 // SHUFPS the element to the lowest double word, then movss.
11583 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11584 MVT VVT = Op.getOperand(0).getSimpleValueType();
11585 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11586 DAG.getUNDEF(VVT), Mask);
11587 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11588 DAG.getIntPtrConstant(0, dl));
11591 if (VT.getSizeInBits() == 64) {
11592 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11593 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11594 // to match extract_elt for f64.
11595 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11599 // UNPCKHPD the element to the lowest double word, then movsd.
11600 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11601 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11602 int Mask[2] = { 1, -1 };
11603 MVT VVT = Op.getOperand(0).getSimpleValueType();
11604 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11605 DAG.getUNDEF(VVT), Mask);
11606 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11607 DAG.getIntPtrConstant(0, dl));
11613 /// Insert one bit to mask vector, like v16i1 or v8i1.
11614 /// AVX-512 feature.
11616 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11618 SDValue Vec = Op.getOperand(0);
11619 SDValue Elt = Op.getOperand(1);
11620 SDValue Idx = Op.getOperand(2);
11621 MVT VecVT = Vec.getSimpleValueType();
11623 if (!isa<ConstantSDNode>(Idx)) {
11624 // Non constant index. Extend source and destination,
11625 // insert element and then truncate the result.
11626 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11627 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11628 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11629 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11630 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11631 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11634 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11635 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11637 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11638 DAG.getConstant(IdxVal, dl, MVT::i8));
11639 if (Vec.getOpcode() == ISD::UNDEF)
11641 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11644 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11645 SelectionDAG &DAG) const {
11646 MVT VT = Op.getSimpleValueType();
11647 MVT EltVT = VT.getVectorElementType();
11649 if (EltVT == MVT::i1)
11650 return InsertBitToMaskVector(Op, DAG);
11653 SDValue N0 = Op.getOperand(0);
11654 SDValue N1 = Op.getOperand(1);
11655 SDValue N2 = Op.getOperand(2);
11656 if (!isa<ConstantSDNode>(N2))
11658 auto *N2C = cast<ConstantSDNode>(N2);
11659 unsigned IdxVal = N2C->getZExtValue();
11661 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11662 // into that, and then insert the subvector back into the result.
11663 if (VT.is256BitVector() || VT.is512BitVector()) {
11664 // With a 256-bit vector, we can insert into the zero element efficiently
11665 // using a blend if we have AVX or AVX2 and the right data type.
11666 if (VT.is256BitVector() && IdxVal == 0) {
11667 // TODO: It is worthwhile to cast integer to floating point and back
11668 // and incur a domain crossing penalty if that's what we'll end up
11669 // doing anyway after extracting to a 128-bit vector.
11670 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11671 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11672 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11673 N2 = DAG.getIntPtrConstant(1, dl);
11674 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11678 // Get the desired 128-bit vector chunk.
11679 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11681 // Insert the element into the desired chunk.
11682 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11683 assert(isPowerOf2_32(NumEltsIn128));
11684 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11685 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11687 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11688 DAG.getConstant(IdxIn128, dl, MVT::i32));
11690 // Insert the changed part back into the bigger vector
11691 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11693 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11695 if (Subtarget->hasSSE41()) {
11696 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11698 if (VT == MVT::v8i16) {
11699 Opc = X86ISD::PINSRW;
11701 assert(VT == MVT::v16i8);
11702 Opc = X86ISD::PINSRB;
11705 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11707 if (N1.getValueType() != MVT::i32)
11708 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11709 if (N2.getValueType() != MVT::i32)
11710 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11711 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11714 if (EltVT == MVT::f32) {
11715 // Bits [7:6] of the constant are the source select. This will always be
11716 // zero here. The DAG Combiner may combine an extract_elt index into
11717 // these bits. For example (insert (extract, 3), 2) could be matched by
11718 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11719 // Bits [5:4] of the constant are the destination select. This is the
11720 // value of the incoming immediate.
11721 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11722 // combine either bitwise AND or insert of float 0.0 to set these bits.
11724 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11725 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11726 // If this is an insertion of 32-bits into the low 32-bits of
11727 // a vector, we prefer to generate a blend with immediate rather
11728 // than an insertps. Blends are simpler operations in hardware and so
11729 // will always have equal or better performance than insertps.
11730 // But if optimizing for size and there's a load folding opportunity,
11731 // generate insertps because blendps does not have a 32-bit memory
11733 N2 = DAG.getIntPtrConstant(1, dl);
11734 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11735 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11737 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11738 // Create this as a scalar to vector..
11739 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11740 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11743 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11744 // PINSR* works with constant index.
11749 if (EltVT == MVT::i8)
11752 if (EltVT.getSizeInBits() == 16) {
11753 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11754 // as its second argument.
11755 if (N1.getValueType() != MVT::i32)
11756 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11757 if (N2.getValueType() != MVT::i32)
11758 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11759 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11764 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11766 MVT OpVT = Op.getSimpleValueType();
11768 // If this is a 256-bit vector result, first insert into a 128-bit
11769 // vector and then insert into the 256-bit vector.
11770 if (!OpVT.is128BitVector()) {
11771 // Insert into a 128-bit vector.
11772 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11773 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11774 OpVT.getVectorNumElements() / SizeFactor);
11776 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11778 // Insert the 128-bit vector.
11779 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11782 if (OpVT == MVT::v1i64 &&
11783 Op.getOperand(0).getValueType() == MVT::i64)
11784 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11786 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11787 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11788 return DAG.getBitcast(
11789 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11792 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11793 // a simple subregister reference or explicit instructions to grab
11794 // upper bits of a vector.
11795 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11796 SelectionDAG &DAG) {
11798 SDValue In = Op.getOperand(0);
11799 SDValue Idx = Op.getOperand(1);
11800 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11801 MVT ResVT = Op.getSimpleValueType();
11802 MVT InVT = In.getSimpleValueType();
11804 if (Subtarget->hasFp256()) {
11805 if (ResVT.is128BitVector() &&
11806 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11807 isa<ConstantSDNode>(Idx)) {
11808 return Extract128BitVector(In, IdxVal, DAG, dl);
11810 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11811 isa<ConstantSDNode>(Idx)) {
11812 return Extract256BitVector(In, IdxVal, DAG, dl);
11818 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11819 // simple superregister reference or explicit instructions to insert
11820 // the upper bits of a vector.
11821 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11822 SelectionDAG &DAG) {
11823 if (!Subtarget->hasAVX())
11827 SDValue Vec = Op.getOperand(0);
11828 SDValue SubVec = Op.getOperand(1);
11829 SDValue Idx = Op.getOperand(2);
11831 if (!isa<ConstantSDNode>(Idx))
11834 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11835 MVT OpVT = Op.getSimpleValueType();
11836 MVT SubVecVT = SubVec.getSimpleValueType();
11838 // Fold two 16-byte subvector loads into one 32-byte load:
11839 // (insert_subvector (insert_subvector undef, (load addr), 0),
11840 // (load addr + 16), Elts/2)
11842 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11843 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11844 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11845 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11846 if (Idx2 && Idx2->getZExtValue() == 0) {
11847 SDValue SubVec2 = Vec.getOperand(1);
11848 // If needed, look through a bitcast to get to the load.
11849 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11850 SubVec2 = SubVec2.getOperand(0);
11852 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11854 unsigned Alignment = FirstLd->getAlignment();
11855 unsigned AS = FirstLd->getAddressSpace();
11856 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11857 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11858 OpVT, AS, Alignment, &Fast) && Fast) {
11859 SDValue Ops[] = { SubVec2, SubVec };
11860 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11867 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11868 SubVecVT.is128BitVector())
11869 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11871 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11872 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11874 if (OpVT.getVectorElementType() == MVT::i1)
11875 return Insert1BitVector(Op, DAG);
11880 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11881 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11882 // one of the above mentioned nodes. It has to be wrapped because otherwise
11883 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11884 // be used to form addressing mode. These wrapped nodes will be selected
11887 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11888 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11890 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11891 // global base reg.
11892 unsigned char OpFlag = 0;
11893 unsigned WrapperKind = X86ISD::Wrapper;
11894 CodeModel::Model M = DAG.getTarget().getCodeModel();
11896 if (Subtarget->isPICStyleRIPRel() &&
11897 (M == CodeModel::Small || M == CodeModel::Kernel))
11898 WrapperKind = X86ISD::WrapperRIP;
11899 else if (Subtarget->isPICStyleGOT())
11900 OpFlag = X86II::MO_GOTOFF;
11901 else if (Subtarget->isPICStyleStubPIC())
11902 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11904 auto PtrVT = getPointerTy(DAG.getDataLayout());
11905 SDValue Result = DAG.getTargetConstantPool(
11906 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11908 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11909 // With PIC, the address is actually $g + Offset.
11912 DAG.getNode(ISD::ADD, DL, PtrVT,
11913 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11919 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11920 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11922 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11923 // global base reg.
11924 unsigned char OpFlag = 0;
11925 unsigned WrapperKind = X86ISD::Wrapper;
11926 CodeModel::Model M = DAG.getTarget().getCodeModel();
11928 if (Subtarget->isPICStyleRIPRel() &&
11929 (M == CodeModel::Small || M == CodeModel::Kernel))
11930 WrapperKind = X86ISD::WrapperRIP;
11931 else if (Subtarget->isPICStyleGOT())
11932 OpFlag = X86II::MO_GOTOFF;
11933 else if (Subtarget->isPICStyleStubPIC())
11934 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11936 auto PtrVT = getPointerTy(DAG.getDataLayout());
11937 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11939 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11941 // With PIC, the address is actually $g + Offset.
11944 DAG.getNode(ISD::ADD, DL, PtrVT,
11945 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11951 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11952 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11954 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11955 // global base reg.
11956 unsigned char OpFlag = 0;
11957 unsigned WrapperKind = X86ISD::Wrapper;
11958 CodeModel::Model M = DAG.getTarget().getCodeModel();
11960 if (Subtarget->isPICStyleRIPRel() &&
11961 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11962 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11963 OpFlag = X86II::MO_GOTPCREL;
11964 WrapperKind = X86ISD::WrapperRIP;
11965 } else if (Subtarget->isPICStyleGOT()) {
11966 OpFlag = X86II::MO_GOT;
11967 } else if (Subtarget->isPICStyleStubPIC()) {
11968 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11969 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11970 OpFlag = X86II::MO_DARWIN_NONLAZY;
11973 auto PtrVT = getPointerTy(DAG.getDataLayout());
11974 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11977 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11979 // With PIC, the address is actually $g + Offset.
11980 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11981 !Subtarget->is64Bit()) {
11983 DAG.getNode(ISD::ADD, DL, PtrVT,
11984 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11987 // For symbols that require a load from a stub to get the address, emit the
11989 if (isGlobalStubReference(OpFlag))
11990 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11991 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11992 false, false, false, 0);
11998 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11999 // Create the TargetBlockAddressAddress node.
12000 unsigned char OpFlags =
12001 Subtarget->ClassifyBlockAddressReference();
12002 CodeModel::Model M = DAG.getTarget().getCodeModel();
12003 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12004 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12006 auto PtrVT = getPointerTy(DAG.getDataLayout());
12007 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12009 if (Subtarget->isPICStyleRIPRel() &&
12010 (M == CodeModel::Small || M == CodeModel::Kernel))
12011 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12013 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12015 // With PIC, the address is actually $g + Offset.
12016 if (isGlobalRelativeToPICBase(OpFlags)) {
12017 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12018 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12025 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12026 int64_t Offset, SelectionDAG &DAG) const {
12027 // Create the TargetGlobalAddress node, folding in the constant
12028 // offset if it is legal.
12029 unsigned char OpFlags =
12030 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12031 CodeModel::Model M = DAG.getTarget().getCodeModel();
12032 auto PtrVT = getPointerTy(DAG.getDataLayout());
12034 if (OpFlags == X86II::MO_NO_FLAG &&
12035 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12036 // A direct static reference to a global.
12037 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12040 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12043 if (Subtarget->isPICStyleRIPRel() &&
12044 (M == CodeModel::Small || M == CodeModel::Kernel))
12045 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12047 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12049 // With PIC, the address is actually $g + Offset.
12050 if (isGlobalRelativeToPICBase(OpFlags)) {
12051 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12052 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12055 // For globals that require a load from a stub to get the address, emit the
12057 if (isGlobalStubReference(OpFlags))
12058 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12059 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12060 false, false, false, 0);
12062 // If there was a non-zero offset that we didn't fold, create an explicit
12063 // addition for it.
12065 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12066 DAG.getConstant(Offset, dl, PtrVT));
12072 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12073 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12074 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12075 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12079 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12080 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12081 unsigned char OperandFlags, bool LocalDynamic = false) {
12082 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12083 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12085 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12086 GA->getValueType(0),
12090 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12094 SDValue Ops[] = { Chain, TGA, *InFlag };
12095 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12097 SDValue Ops[] = { Chain, TGA };
12098 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12101 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12102 MFI->setAdjustsStack(true);
12103 MFI->setHasCalls(true);
12105 SDValue Flag = Chain.getValue(1);
12106 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12109 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12111 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12114 SDLoc dl(GA); // ? function entry point might be better
12115 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12116 DAG.getNode(X86ISD::GlobalBaseReg,
12117 SDLoc(), PtrVT), InFlag);
12118 InFlag = Chain.getValue(1);
12120 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12123 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12125 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12127 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12128 X86::RAX, X86II::MO_TLSGD);
12131 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12137 // Get the start address of the TLS block for this module.
12138 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12139 .getInfo<X86MachineFunctionInfo>();
12140 MFI->incNumLocalDynamicTLSAccesses();
12144 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12145 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12148 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12149 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12150 InFlag = Chain.getValue(1);
12151 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12152 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12155 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12159 unsigned char OperandFlags = X86II::MO_DTPOFF;
12160 unsigned WrapperKind = X86ISD::Wrapper;
12161 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12162 GA->getValueType(0),
12163 GA->getOffset(), OperandFlags);
12164 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12166 // Add x@dtpoff with the base.
12167 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12170 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12171 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12172 const EVT PtrVT, TLSModel::Model model,
12173 bool is64Bit, bool isPIC) {
12176 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12177 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12178 is64Bit ? 257 : 256));
12180 SDValue ThreadPointer =
12181 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12182 MachinePointerInfo(Ptr), false, false, false, 0);
12184 unsigned char OperandFlags = 0;
12185 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12187 unsigned WrapperKind = X86ISD::Wrapper;
12188 if (model == TLSModel::LocalExec) {
12189 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12190 } else if (model == TLSModel::InitialExec) {
12192 OperandFlags = X86II::MO_GOTTPOFF;
12193 WrapperKind = X86ISD::WrapperRIP;
12195 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12198 llvm_unreachable("Unexpected model");
12201 // emit "addl x@ntpoff,%eax" (local exec)
12202 // or "addl x@indntpoff,%eax" (initial exec)
12203 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12205 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12206 GA->getOffset(), OperandFlags);
12207 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12209 if (model == TLSModel::InitialExec) {
12210 if (isPIC && !is64Bit) {
12211 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12212 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12216 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12217 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12218 false, false, false, 0);
12221 // The address of the thread local variable is the add of the thread
12222 // pointer with the offset of the variable.
12223 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12227 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12229 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12230 const GlobalValue *GV = GA->getGlobal();
12231 auto PtrVT = getPointerTy(DAG.getDataLayout());
12233 if (Subtarget->isTargetELF()) {
12234 if (DAG.getTarget().Options.EmulatedTLS)
12235 return LowerToTLSEmulatedModel(GA, DAG);
12236 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12238 case TLSModel::GeneralDynamic:
12239 if (Subtarget->is64Bit())
12240 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12241 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12242 case TLSModel::LocalDynamic:
12243 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12244 Subtarget->is64Bit());
12245 case TLSModel::InitialExec:
12246 case TLSModel::LocalExec:
12247 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12248 DAG.getTarget().getRelocationModel() ==
12251 llvm_unreachable("Unknown TLS model.");
12254 if (Subtarget->isTargetDarwin()) {
12255 // Darwin only has one model of TLS. Lower to that.
12256 unsigned char OpFlag = 0;
12257 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12258 X86ISD::WrapperRIP : X86ISD::Wrapper;
12260 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12261 // global base reg.
12262 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12263 !Subtarget->is64Bit();
12265 OpFlag = X86II::MO_TLVP_PIC_BASE;
12267 OpFlag = X86II::MO_TLVP;
12269 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12270 GA->getValueType(0),
12271 GA->getOffset(), OpFlag);
12272 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12274 // With PIC32, the address is actually $g + Offset.
12276 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12277 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12280 // Lowering the machine isd will make sure everything is in the right
12282 SDValue Chain = DAG.getEntryNode();
12283 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12284 SDValue Args[] = { Chain, Offset };
12285 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12287 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12288 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12289 MFI->setAdjustsStack(true);
12291 // And our return value (tls address) is in the standard call return value
12293 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12294 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12297 if (Subtarget->isTargetKnownWindowsMSVC() ||
12298 Subtarget->isTargetWindowsGNU()) {
12299 // Just use the implicit TLS architecture
12300 // Need to generate someting similar to:
12301 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12303 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12304 // mov rcx, qword [rdx+rcx*8]
12305 // mov eax, .tls$:tlsvar
12306 // [rax+rcx] contains the address
12307 // Windows 64bit: gs:0x58
12308 // Windows 32bit: fs:__tls_array
12311 SDValue Chain = DAG.getEntryNode();
12313 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12314 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12315 // use its literal value of 0x2C.
12316 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12317 ? Type::getInt8PtrTy(*DAG.getContext(),
12319 : Type::getInt32PtrTy(*DAG.getContext(),
12322 SDValue TlsArray = Subtarget->is64Bit()
12323 ? DAG.getIntPtrConstant(0x58, dl)
12324 : (Subtarget->isTargetWindowsGNU()
12325 ? DAG.getIntPtrConstant(0x2C, dl)
12326 : DAG.getExternalSymbol("_tls_array", PtrVT));
12328 SDValue ThreadPointer =
12329 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12333 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12334 res = ThreadPointer;
12336 // Load the _tls_index variable
12337 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12338 if (Subtarget->is64Bit())
12339 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12340 MachinePointerInfo(), MVT::i32, false, false,
12343 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12346 auto &DL = DAG.getDataLayout();
12348 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12349 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12351 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12354 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12357 // Get the offset of start of .tls section
12358 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12359 GA->getValueType(0),
12360 GA->getOffset(), X86II::MO_SECREL);
12361 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12363 // The address of the thread local variable is the add of the thread
12364 // pointer with the offset of the variable.
12365 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12368 llvm_unreachable("TLS not implemented for this target.");
12371 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12372 /// and take a 2 x i32 value to shift plus a shift amount.
12373 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12374 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12375 MVT VT = Op.getSimpleValueType();
12376 unsigned VTBits = VT.getSizeInBits();
12378 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12379 SDValue ShOpLo = Op.getOperand(0);
12380 SDValue ShOpHi = Op.getOperand(1);
12381 SDValue ShAmt = Op.getOperand(2);
12382 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12383 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12385 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12386 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12387 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12388 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12389 : DAG.getConstant(0, dl, VT);
12391 SDValue Tmp2, Tmp3;
12392 if (Op.getOpcode() == ISD::SHL_PARTS) {
12393 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12394 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12396 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12397 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12400 // If the shift amount is larger or equal than the width of a part we can't
12401 // rely on the results of shld/shrd. Insert a test and select the appropriate
12402 // values for large shift amounts.
12403 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12404 DAG.getConstant(VTBits, dl, MVT::i8));
12405 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12406 AndNode, DAG.getConstant(0, dl, MVT::i8));
12409 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12410 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12411 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12413 if (Op.getOpcode() == ISD::SHL_PARTS) {
12414 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12415 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12417 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12418 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12421 SDValue Ops[2] = { Lo, Hi };
12422 return DAG.getMergeValues(Ops, dl);
12425 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12426 SelectionDAG &DAG) const {
12427 SDValue Src = Op.getOperand(0);
12428 MVT SrcVT = Src.getSimpleValueType();
12429 MVT VT = Op.getSimpleValueType();
12432 if (SrcVT.isVector()) {
12433 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12434 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12435 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12436 DAG.getUNDEF(SrcVT)));
12438 if (SrcVT.getVectorElementType() == MVT::i1) {
12439 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12440 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12441 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12446 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12447 "Unknown SINT_TO_FP to lower!");
12449 // These are really Legal; return the operand so the caller accepts it as
12451 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12453 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12454 Subtarget->is64Bit()) {
12458 unsigned Size = SrcVT.getSizeInBits()/8;
12459 MachineFunction &MF = DAG.getMachineFunction();
12460 auto PtrVT = getPointerTy(MF.getDataLayout());
12461 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12462 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12463 SDValue Chain = DAG.getStore(
12464 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12465 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12467 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12470 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12472 SelectionDAG &DAG) const {
12476 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12478 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12480 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12482 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12484 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12485 MachineMemOperand *MMO;
12487 int SSFI = FI->getIndex();
12488 MMO = DAG.getMachineFunction().getMachineMemOperand(
12489 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12490 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12492 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12493 StackSlot = StackSlot.getOperand(1);
12495 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12496 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12498 Tys, Ops, SrcVT, MMO);
12501 Chain = Result.getValue(1);
12502 SDValue InFlag = Result.getValue(2);
12504 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12505 // shouldn't be necessary except that RFP cannot be live across
12506 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12507 MachineFunction &MF = DAG.getMachineFunction();
12508 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12509 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12510 auto PtrVT = getPointerTy(MF.getDataLayout());
12511 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12512 Tys = DAG.getVTList(MVT::Other);
12514 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12516 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12517 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12518 MachineMemOperand::MOStore, SSFISize, SSFISize);
12520 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12521 Ops, Op.getValueType(), MMO);
12522 Result = DAG.getLoad(
12523 Op.getValueType(), DL, Chain, StackSlot,
12524 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12525 false, false, false, 0);
12531 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12532 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12533 SelectionDAG &DAG) const {
12534 // This algorithm is not obvious. Here it is what we're trying to output:
12537 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12538 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12540 haddpd %xmm0, %xmm0
12542 pshufd $0x4e, %xmm0, %xmm1
12548 LLVMContext *Context = DAG.getContext();
12550 // Build some magic constants.
12551 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12552 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12553 auto PtrVT = getPointerTy(DAG.getDataLayout());
12554 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12556 SmallVector<Constant*,2> CV1;
12558 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12559 APInt(64, 0x4330000000000000ULL))));
12561 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12562 APInt(64, 0x4530000000000000ULL))));
12563 Constant *C1 = ConstantVector::get(CV1);
12564 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12566 // Load the 64-bit value into an XMM register.
12567 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12570 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12571 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12572 false, false, false, 16);
12574 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12577 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12578 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12579 false, false, false, 16);
12580 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12581 // TODO: Are there any fast-math-flags to propagate here?
12582 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12585 if (Subtarget->hasSSE3()) {
12586 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12587 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12589 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12590 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12592 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12593 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12596 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12597 DAG.getIntPtrConstant(0, dl));
12600 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12601 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12602 SelectionDAG &DAG) const {
12604 // FP constant to bias correct the final result.
12605 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12608 // Load the 32-bit value into an XMM register.
12609 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12612 // Zero out the upper parts of the register.
12613 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12615 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12616 DAG.getBitcast(MVT::v2f64, Load),
12617 DAG.getIntPtrConstant(0, dl));
12619 // Or the load with the bias.
12620 SDValue Or = DAG.getNode(
12621 ISD::OR, dl, MVT::v2i64,
12622 DAG.getBitcast(MVT::v2i64,
12623 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12624 DAG.getBitcast(MVT::v2i64,
12625 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12627 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12628 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12630 // Subtract the bias.
12631 // TODO: Are there any fast-math-flags to propagate here?
12632 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12634 // Handle final rounding.
12635 MVT DestVT = Op.getSimpleValueType();
12637 if (DestVT.bitsLT(MVT::f64))
12638 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12639 DAG.getIntPtrConstant(0, dl));
12640 if (DestVT.bitsGT(MVT::f64))
12641 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12643 // Handle final rounding.
12647 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12648 const X86Subtarget &Subtarget) {
12649 // The algorithm is the following:
12650 // #ifdef __SSE4_1__
12651 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12652 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12653 // (uint4) 0x53000000, 0xaa);
12655 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12656 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12658 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12659 // return (float4) lo + fhi;
12661 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12662 // reassociate the two FADDs, and if we do that, the algorithm fails
12663 // spectacularly (PR24512).
12664 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12665 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12666 // there's also the MachineCombiner reassociations happening on Machine IR.
12667 if (DAG.getTarget().Options.UnsafeFPMath)
12671 SDValue V = Op->getOperand(0);
12672 MVT VecIntVT = V.getSimpleValueType();
12673 bool Is128 = VecIntVT == MVT::v4i32;
12674 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12675 // If we convert to something else than the supported type, e.g., to v4f64,
12677 if (VecFloatVT != Op->getSimpleValueType(0))
12680 unsigned NumElts = VecIntVT.getVectorNumElements();
12681 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12682 "Unsupported custom type");
12683 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12685 // In the #idef/#else code, we have in common:
12686 // - The vector of constants:
12692 // Create the splat vector for 0x4b000000.
12693 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12694 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12695 CstLow, CstLow, CstLow, CstLow};
12696 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12697 makeArrayRef(&CstLowArray[0], NumElts));
12698 // Create the splat vector for 0x53000000.
12699 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12700 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12701 CstHigh, CstHigh, CstHigh, CstHigh};
12702 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12703 makeArrayRef(&CstHighArray[0], NumElts));
12705 // Create the right shift.
12706 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12707 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12708 CstShift, CstShift, CstShift, CstShift};
12709 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12710 makeArrayRef(&CstShiftArray[0], NumElts));
12711 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12714 if (Subtarget.hasSSE41()) {
12715 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12716 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12717 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12718 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12719 // Low will be bitcasted right away, so do not bother bitcasting back to its
12721 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12722 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12723 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12724 // (uint4) 0x53000000, 0xaa);
12725 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12726 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12727 // High will be bitcasted right away, so do not bother bitcasting back to
12728 // its original type.
12729 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12730 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12732 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12733 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12734 CstMask, CstMask, CstMask);
12735 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12736 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12737 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12739 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12740 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12743 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12744 SDValue CstFAdd = DAG.getConstantFP(
12745 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12746 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12747 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12748 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12749 makeArrayRef(&CstFAddArray[0], NumElts));
12751 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12752 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12753 // TODO: Are there any fast-math-flags to propagate here?
12755 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12756 // return (float4) lo + fhi;
12757 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12758 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12761 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12762 SelectionDAG &DAG) const {
12763 SDValue N0 = Op.getOperand(0);
12764 MVT SVT = N0.getSimpleValueType();
12767 switch (SVT.SimpleTy) {
12769 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12774 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12775 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12776 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12780 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12783 assert(Subtarget->hasAVX512());
12784 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12785 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12789 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12790 SelectionDAG &DAG) const {
12791 SDValue N0 = Op.getOperand(0);
12793 auto PtrVT = getPointerTy(DAG.getDataLayout());
12795 if (Op.getSimpleValueType().isVector())
12796 return lowerUINT_TO_FP_vec(Op, DAG);
12798 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12799 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12800 // the optimization here.
12801 if (DAG.SignBitIsZero(N0))
12802 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12804 MVT SrcVT = N0.getSimpleValueType();
12805 MVT DstVT = Op.getSimpleValueType();
12807 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12808 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12809 // Conversions from unsigned i32 to f32/f64 are legal,
12810 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12814 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12815 return LowerUINT_TO_FP_i64(Op, DAG);
12816 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12817 return LowerUINT_TO_FP_i32(Op, DAG);
12818 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12821 // Make a 64-bit buffer, and use it to build an FILD.
12822 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12823 if (SrcVT == MVT::i32) {
12824 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12825 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12826 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12827 StackSlot, MachinePointerInfo(),
12829 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12830 OffsetSlot, MachinePointerInfo(),
12832 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12836 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12837 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12838 StackSlot, MachinePointerInfo(),
12840 // For i64 source, we need to add the appropriate power of 2 if the input
12841 // was negative. This is the same as the optimization in
12842 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12843 // we must be careful to do the computation in x87 extended precision, not
12844 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12845 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12846 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12847 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12848 MachineMemOperand::MOLoad, 8, 8);
12850 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12851 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12852 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12855 APInt FF(32, 0x5F800000ULL);
12857 // Check whether the sign bit is set.
12858 SDValue SignSet = DAG.getSetCC(
12859 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12860 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12862 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12863 SDValue FudgePtr = DAG.getConstantPool(
12864 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12866 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12867 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12868 SDValue Four = DAG.getIntPtrConstant(4, dl);
12869 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12871 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12873 // Load the value out, extending it from f32 to f80.
12874 // FIXME: Avoid the extend by constructing the right constant pool?
12875 SDValue Fudge = DAG.getExtLoad(
12876 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12877 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12878 false, false, false, 4);
12879 // Extend everything to 80 bits to force it to be done on x87.
12880 // TODO: Are there any fast-math-flags to propagate here?
12881 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12882 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12883 DAG.getIntPtrConstant(0, dl));
12886 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12887 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12888 // just return an <SDValue(), SDValue()> pair.
12889 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12890 // to i16, i32 or i64, and we lower it to a legal sequence.
12891 // If lowered to the final integer result we return a <result, SDValue()> pair.
12892 // Otherwise we lower it to a sequence ending with a FIST, return a
12893 // <FIST, StackSlot> pair, and the caller is responsible for loading
12894 // the final integer result from StackSlot.
12895 std::pair<SDValue,SDValue>
12896 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12897 bool IsSigned, bool IsReplace) const {
12900 EVT DstTy = Op.getValueType();
12901 EVT TheVT = Op.getOperand(0).getValueType();
12902 auto PtrVT = getPointerTy(DAG.getDataLayout());
12904 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12905 // f16 must be promoted before using the lowering in this routine.
12906 // fp128 does not use this lowering.
12907 return std::make_pair(SDValue(), SDValue());
12910 // If using FIST to compute an unsigned i64, we'll need some fixup
12911 // to handle values above the maximum signed i64. A FIST is always
12912 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12913 bool UnsignedFixup = !IsSigned &&
12914 DstTy == MVT::i64 &&
12915 (!Subtarget->is64Bit() ||
12916 !isScalarFPTypeInSSEReg(TheVT));
12918 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12919 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12920 // The low 32 bits of the fist result will have the correct uint32 result.
12921 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12925 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12926 DstTy.getSimpleVT() >= MVT::i16 &&
12927 "Unknown FP_TO_INT to lower!");
12929 // These are really Legal.
12930 if (DstTy == MVT::i32 &&
12931 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12932 return std::make_pair(SDValue(), SDValue());
12933 if (Subtarget->is64Bit() &&
12934 DstTy == MVT::i64 &&
12935 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12936 return std::make_pair(SDValue(), SDValue());
12938 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12940 MachineFunction &MF = DAG.getMachineFunction();
12941 unsigned MemSize = DstTy.getSizeInBits()/8;
12942 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12943 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12946 switch (DstTy.getSimpleVT().SimpleTy) {
12947 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12948 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12949 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12950 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12953 SDValue Chain = DAG.getEntryNode();
12954 SDValue Value = Op.getOperand(0);
12955 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12957 if (UnsignedFixup) {
12959 // Conversion to unsigned i64 is implemented with a select,
12960 // depending on whether the source value fits in the range
12961 // of a signed i64. Let Thresh be the FP equivalent of
12962 // 0x8000000000000000ULL.
12964 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12965 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12966 // Fist-to-mem64 FistSrc
12967 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12968 // to XOR'ing the high 32 bits with Adjust.
12970 // Being a power of 2, Thresh is exactly representable in all FP formats.
12971 // For X87 we'd like to use the smallest FP type for this constant, but
12972 // for DAG type consistency we have to match the FP operand type.
12974 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12975 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12976 bool LosesInfo = false;
12977 if (TheVT == MVT::f64)
12978 // The rounding mode is irrelevant as the conversion should be exact.
12979 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12981 else if (TheVT == MVT::f80)
12982 Status = Thresh.convert(APFloat::x87DoubleExtended,
12983 APFloat::rmNearestTiesToEven, &LosesInfo);
12985 assert(Status == APFloat::opOK && !LosesInfo &&
12986 "FP conversion should have been exact");
12988 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12990 SDValue Cmp = DAG.getSetCC(DL,
12991 getSetCCResultType(DAG.getDataLayout(),
12992 *DAG.getContext(), TheVT),
12993 Value, ThreshVal, ISD::SETLT);
12994 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12995 DAG.getConstant(0, DL, MVT::i32),
12996 DAG.getConstant(0x80000000, DL, MVT::i32));
12997 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12998 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12999 *DAG.getContext(), TheVT),
13000 Value, ThreshVal, ISD::SETLT);
13001 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13004 // FIXME This causes a redundant load/store if the SSE-class value is already
13005 // in memory, such as if it is on the callstack.
13006 if (isScalarFPTypeInSSEReg(TheVT)) {
13007 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13008 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13009 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13011 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13013 Chain, StackSlot, DAG.getValueType(TheVT)
13016 MachineMemOperand *MMO =
13017 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13018 MachineMemOperand::MOLoad, MemSize, MemSize);
13019 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13020 Chain = Value.getValue(1);
13021 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13022 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13025 MachineMemOperand *MMO =
13026 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13027 MachineMemOperand::MOStore, MemSize, MemSize);
13029 if (UnsignedFixup) {
13031 // Insert the FIST, load its result as two i32's,
13032 // and XOR the high i32 with Adjust.
13034 SDValue FistOps[] = { Chain, Value, StackSlot };
13035 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13036 FistOps, DstTy, MMO);
13038 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13039 MachinePointerInfo(),
13040 false, false, false, 0);
13041 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13042 DAG.getConstant(4, DL, PtrVT));
13044 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13045 MachinePointerInfo(),
13046 false, false, false, 0);
13047 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13049 if (Subtarget->is64Bit()) {
13050 // Join High32 and Low32 into a 64-bit result.
13051 // (High32 << 32) | Low32
13052 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13053 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13054 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13055 DAG.getConstant(32, DL, MVT::i8));
13056 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13057 return std::make_pair(Result, SDValue());
13060 SDValue ResultOps[] = { Low32, High32 };
13062 SDValue pair = IsReplace
13063 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13064 : DAG.getMergeValues(ResultOps, DL);
13065 return std::make_pair(pair, SDValue());
13067 // Build the FP_TO_INT*_IN_MEM
13068 SDValue Ops[] = { Chain, Value, StackSlot };
13069 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13071 return std::make_pair(FIST, StackSlot);
13075 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13076 const X86Subtarget *Subtarget) {
13077 MVT VT = Op->getSimpleValueType(0);
13078 SDValue In = Op->getOperand(0);
13079 MVT InVT = In.getSimpleValueType();
13082 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13083 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13085 // Optimize vectors in AVX mode:
13088 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13089 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13090 // Concat upper and lower parts.
13093 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13094 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13095 // Concat upper and lower parts.
13098 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13099 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13100 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13103 if (Subtarget->hasInt256())
13104 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13106 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13107 SDValue Undef = DAG.getUNDEF(InVT);
13108 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13109 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13110 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13112 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13113 VT.getVectorNumElements()/2);
13115 OpLo = DAG.getBitcast(HVT, OpLo);
13116 OpHi = DAG.getBitcast(HVT, OpHi);
13118 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13121 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13122 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13123 MVT VT = Op->getSimpleValueType(0);
13124 SDValue In = Op->getOperand(0);
13125 MVT InVT = In.getSimpleValueType();
13127 unsigned int NumElts = VT.getVectorNumElements();
13128 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13131 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13132 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13134 assert(InVT.getVectorElementType() == MVT::i1);
13135 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13137 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13139 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13141 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13142 if (VT.is512BitVector())
13144 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13147 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13148 SelectionDAG &DAG) {
13149 if (Subtarget->hasFp256())
13150 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13156 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13157 SelectionDAG &DAG) {
13159 MVT VT = Op.getSimpleValueType();
13160 SDValue In = Op.getOperand(0);
13161 MVT SVT = In.getSimpleValueType();
13163 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13164 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13166 if (Subtarget->hasFp256())
13167 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13170 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13171 VT.getVectorNumElements() != SVT.getVectorNumElements());
13175 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13177 MVT VT = Op.getSimpleValueType();
13178 SDValue In = Op.getOperand(0);
13179 MVT InVT = In.getSimpleValueType();
13181 if (VT == MVT::i1) {
13182 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13183 "Invalid scalar TRUNCATE operation");
13184 if (InVT.getSizeInBits() >= 32)
13186 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13187 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13189 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13190 "Invalid TRUNCATE operation");
13192 // move vector to mask - truncate solution for SKX
13193 if (VT.getVectorElementType() == MVT::i1) {
13194 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13195 Subtarget->hasBWI())
13196 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13197 if ((InVT.is256BitVector() || InVT.is128BitVector())
13198 && InVT.getScalarSizeInBits() <= 16 &&
13199 Subtarget->hasBWI() && Subtarget->hasVLX())
13200 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13201 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13202 Subtarget->hasDQI())
13203 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13204 if ((InVT.is256BitVector() || InVT.is128BitVector())
13205 && InVT.getScalarSizeInBits() >= 32 &&
13206 Subtarget->hasDQI() && Subtarget->hasVLX())
13207 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13210 if (VT.getVectorElementType() == MVT::i1) {
13211 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13212 unsigned NumElts = InVT.getVectorNumElements();
13213 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13214 if (InVT.getSizeInBits() < 512) {
13215 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13216 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13221 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13222 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13223 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13226 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13227 if (Subtarget->hasAVX512()) {
13228 // word to byte only under BWI
13229 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13230 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13231 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13232 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13234 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13235 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13236 if (Subtarget->hasInt256()) {
13237 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13238 In = DAG.getBitcast(MVT::v8i32, In);
13239 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13241 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13242 DAG.getIntPtrConstant(0, DL));
13245 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13246 DAG.getIntPtrConstant(0, DL));
13247 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13248 DAG.getIntPtrConstant(2, DL));
13249 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13250 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13251 static const int ShufMask[] = {0, 2, 4, 6};
13252 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13255 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13256 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13257 if (Subtarget->hasInt256()) {
13258 In = DAG.getBitcast(MVT::v32i8, In);
13260 SmallVector<SDValue,32> pshufbMask;
13261 for (unsigned i = 0; i < 2; ++i) {
13262 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13263 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13264 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13265 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13266 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13267 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13268 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13269 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13270 for (unsigned j = 0; j < 8; ++j)
13271 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13273 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13274 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13275 In = DAG.getBitcast(MVT::v4i64, In);
13277 static const int ShufMask[] = {0, 2, -1, -1};
13278 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13280 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13281 DAG.getIntPtrConstant(0, DL));
13282 return DAG.getBitcast(VT, In);
13285 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13286 DAG.getIntPtrConstant(0, DL));
13288 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13289 DAG.getIntPtrConstant(4, DL));
13291 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13292 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13294 // The PSHUFB mask:
13295 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13296 -1, -1, -1, -1, -1, -1, -1, -1};
13298 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13299 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13300 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13302 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13303 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13305 // The MOVLHPS Mask:
13306 static const int ShufMask2[] = {0, 1, 4, 5};
13307 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13308 return DAG.getBitcast(MVT::v8i16, res);
13311 // Handle truncation of V256 to V128 using shuffles.
13312 if (!VT.is128BitVector() || !InVT.is256BitVector())
13315 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13317 unsigned NumElems = VT.getVectorNumElements();
13318 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13320 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13321 // Prepare truncation shuffle mask
13322 for (unsigned i = 0; i != NumElems; ++i)
13323 MaskVec[i] = i * 2;
13324 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13325 DAG.getUNDEF(NVT), &MaskVec[0]);
13326 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13327 DAG.getIntPtrConstant(0, DL));
13330 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13331 SelectionDAG &DAG) const {
13332 assert(!Op.getSimpleValueType().isVector());
13334 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13335 /*IsSigned=*/ true, /*IsReplace=*/ false);
13336 SDValue FIST = Vals.first, StackSlot = Vals.second;
13337 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13338 if (!FIST.getNode())
13341 if (StackSlot.getNode())
13342 // Load the result.
13343 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13344 FIST, StackSlot, MachinePointerInfo(),
13345 false, false, false, 0);
13347 // The node is the result.
13351 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13352 SelectionDAG &DAG) const {
13353 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13354 /*IsSigned=*/ false, /*IsReplace=*/ false);
13355 SDValue FIST = Vals.first, StackSlot = Vals.second;
13356 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13357 if (!FIST.getNode())
13360 if (StackSlot.getNode())
13361 // Load the result.
13362 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13363 FIST, StackSlot, MachinePointerInfo(),
13364 false, false, false, 0);
13366 // The node is the result.
13370 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13372 MVT VT = Op.getSimpleValueType();
13373 SDValue In = Op.getOperand(0);
13374 MVT SVT = In.getSimpleValueType();
13376 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13378 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13379 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13380 In, DAG.getUNDEF(SVT)));
13383 /// The only differences between FABS and FNEG are the mask and the logic op.
13384 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13385 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13386 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13387 "Wrong opcode for lowering FABS or FNEG.");
13389 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13391 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13392 // into an FNABS. We'll lower the FABS after that if it is still in use.
13394 for (SDNode *User : Op->uses())
13395 if (User->getOpcode() == ISD::FNEG)
13399 MVT VT = Op.getSimpleValueType();
13401 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13402 // decide if we should generate a 16-byte constant mask when we only need 4 or
13403 // 8 bytes for the scalar case.
13409 if (VT.isVector()) {
13411 EltVT = VT.getVectorElementType();
13412 NumElts = VT.getVectorNumElements();
13414 // There are no scalar bitwise logical SSE/AVX instructions, so we
13415 // generate a 16-byte vector constant and logic op even for the scalar case.
13416 // Using a 16-byte mask allows folding the load of the mask with
13417 // the logic op, so it can save (~4 bytes) on code size.
13418 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13420 NumElts = (VT == MVT::f64) ? 2 : 4;
13423 unsigned EltBits = EltVT.getSizeInBits();
13424 LLVMContext *Context = DAG.getContext();
13425 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13427 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13428 Constant *C = ConstantInt::get(*Context, MaskElt);
13429 C = ConstantVector::getSplat(NumElts, C);
13430 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13431 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13432 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13434 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13435 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13436 false, false, false, Alignment);
13438 SDValue Op0 = Op.getOperand(0);
13439 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13441 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13442 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13445 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13447 // For the scalar case extend to a 128-bit vector, perform the logic op,
13448 // and extract the scalar result back out.
13449 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13450 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13451 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13452 DAG.getIntPtrConstant(0, dl));
13455 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13456 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13457 LLVMContext *Context = DAG.getContext();
13458 SDValue Op0 = Op.getOperand(0);
13459 SDValue Op1 = Op.getOperand(1);
13461 MVT VT = Op.getSimpleValueType();
13462 MVT SrcVT = Op1.getSimpleValueType();
13464 // If second operand is smaller, extend it first.
13465 if (SrcVT.bitsLT(VT)) {
13466 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13469 // And if it is bigger, shrink it first.
13470 if (SrcVT.bitsGT(VT)) {
13471 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13475 // At this point the operands and the result should have the same
13476 // type, and that won't be f80 since that is not custom lowered.
13478 const fltSemantics &Sem =
13479 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13480 const unsigned SizeInBits = VT.getSizeInBits();
13482 SmallVector<Constant *, 4> CV(
13483 VT == MVT::f64 ? 2 : 4,
13484 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13486 // First, clear all bits but the sign bit from the second operand (sign).
13487 CV[0] = ConstantFP::get(*Context,
13488 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13489 Constant *C = ConstantVector::get(CV);
13490 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13491 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13493 // Perform all logic operations as 16-byte vectors because there are no
13494 // scalar FP logic instructions in SSE. This allows load folding of the
13495 // constants into the logic instructions.
13496 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13498 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13499 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13500 false, false, false, 16);
13501 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13502 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13504 // Next, clear the sign bit from the first operand (magnitude).
13505 // If it's a constant, we can clear it here.
13506 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13507 APFloat APF = Op0CN->getValueAPF();
13508 // If the magnitude is a positive zero, the sign bit alone is enough.
13509 if (APF.isPosZero())
13510 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13511 DAG.getIntPtrConstant(0, dl));
13513 CV[0] = ConstantFP::get(*Context, APF);
13515 CV[0] = ConstantFP::get(
13517 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13519 C = ConstantVector::get(CV);
13520 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13522 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13523 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13524 false, false, false, 16);
13525 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13526 if (!isa<ConstantFPSDNode>(Op0)) {
13527 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13528 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13530 // OR the magnitude value with the sign bit.
13531 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13532 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13533 DAG.getIntPtrConstant(0, dl));
13536 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13537 SDValue N0 = Op.getOperand(0);
13539 MVT VT = Op.getSimpleValueType();
13541 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13542 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13543 DAG.getConstant(1, dl, VT));
13544 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13547 // Check whether an OR'd tree is PTEST-able.
13548 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13549 SelectionDAG &DAG) {
13550 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13552 if (!Subtarget->hasSSE41())
13555 if (!Op->hasOneUse())
13558 SDNode *N = Op.getNode();
13561 SmallVector<SDValue, 8> Opnds;
13562 DenseMap<SDValue, unsigned> VecInMap;
13563 SmallVector<SDValue, 8> VecIns;
13564 EVT VT = MVT::Other;
13566 // Recognize a special case where a vector is casted into wide integer to
13568 Opnds.push_back(N->getOperand(0));
13569 Opnds.push_back(N->getOperand(1));
13571 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13572 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13573 // BFS traverse all OR'd operands.
13574 if (I->getOpcode() == ISD::OR) {
13575 Opnds.push_back(I->getOperand(0));
13576 Opnds.push_back(I->getOperand(1));
13577 // Re-evaluate the number of nodes to be traversed.
13578 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13582 // Quit if a non-EXTRACT_VECTOR_ELT
13583 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13586 // Quit if without a constant index.
13587 SDValue Idx = I->getOperand(1);
13588 if (!isa<ConstantSDNode>(Idx))
13591 SDValue ExtractedFromVec = I->getOperand(0);
13592 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13593 if (M == VecInMap.end()) {
13594 VT = ExtractedFromVec.getValueType();
13595 // Quit if not 128/256-bit vector.
13596 if (!VT.is128BitVector() && !VT.is256BitVector())
13598 // Quit if not the same type.
13599 if (VecInMap.begin() != VecInMap.end() &&
13600 VT != VecInMap.begin()->first.getValueType())
13602 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13603 VecIns.push_back(ExtractedFromVec);
13605 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13608 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13609 "Not extracted from 128-/256-bit vector.");
13611 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13613 for (DenseMap<SDValue, unsigned>::const_iterator
13614 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13615 // Quit if not all elements are used.
13616 if (I->second != FullMask)
13620 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13622 // Cast all vectors into TestVT for PTEST.
13623 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13624 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13626 // If more than one full vectors are evaluated, OR them first before PTEST.
13627 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13628 // Each iteration will OR 2 nodes and append the result until there is only
13629 // 1 node left, i.e. the final OR'd value of all vectors.
13630 SDValue LHS = VecIns[Slot];
13631 SDValue RHS = VecIns[Slot + 1];
13632 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13635 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13636 VecIns.back(), VecIns.back());
13639 /// \brief return true if \c Op has a use that doesn't just read flags.
13640 static bool hasNonFlagsUse(SDValue Op) {
13641 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13643 SDNode *User = *UI;
13644 unsigned UOpNo = UI.getOperandNo();
13645 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13646 // Look pass truncate.
13647 UOpNo = User->use_begin().getOperandNo();
13648 User = *User->use_begin();
13651 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13652 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13658 /// Emit nodes that will be selected as "test Op0,Op0", or something
13660 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13661 SelectionDAG &DAG) const {
13662 if (Op.getValueType() == MVT::i1) {
13663 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13664 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13665 DAG.getConstant(0, dl, MVT::i8));
13667 // CF and OF aren't always set the way we want. Determine which
13668 // of these we need.
13669 bool NeedCF = false;
13670 bool NeedOF = false;
13673 case X86::COND_A: case X86::COND_AE:
13674 case X86::COND_B: case X86::COND_BE:
13677 case X86::COND_G: case X86::COND_GE:
13678 case X86::COND_L: case X86::COND_LE:
13679 case X86::COND_O: case X86::COND_NO: {
13680 // Check if we really need to set the
13681 // Overflow flag. If NoSignedWrap is present
13682 // that is not actually needed.
13683 switch (Op->getOpcode()) {
13688 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13689 if (BinNode->Flags.hasNoSignedWrap())
13699 // See if we can use the EFLAGS value from the operand instead of
13700 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13701 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13702 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13703 // Emit a CMP with 0, which is the TEST pattern.
13704 //if (Op.getValueType() == MVT::i1)
13705 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13706 // DAG.getConstant(0, MVT::i1));
13707 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13708 DAG.getConstant(0, dl, Op.getValueType()));
13710 unsigned Opcode = 0;
13711 unsigned NumOperands = 0;
13713 // Truncate operations may prevent the merge of the SETCC instruction
13714 // and the arithmetic instruction before it. Attempt to truncate the operands
13715 // of the arithmetic instruction and use a reduced bit-width instruction.
13716 bool NeedTruncation = false;
13717 SDValue ArithOp = Op;
13718 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13719 SDValue Arith = Op->getOperand(0);
13720 // Both the trunc and the arithmetic op need to have one user each.
13721 if (Arith->hasOneUse())
13722 switch (Arith.getOpcode()) {
13729 NeedTruncation = true;
13735 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13736 // which may be the result of a CAST. We use the variable 'Op', which is the
13737 // non-casted variable when we check for possible users.
13738 switch (ArithOp.getOpcode()) {
13740 // Due to an isel shortcoming, be conservative if this add is likely to be
13741 // selected as part of a load-modify-store instruction. When the root node
13742 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13743 // uses of other nodes in the match, such as the ADD in this case. This
13744 // leads to the ADD being left around and reselected, with the result being
13745 // two adds in the output. Alas, even if none our users are stores, that
13746 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13747 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13748 // climbing the DAG back to the root, and it doesn't seem to be worth the
13750 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13751 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13752 if (UI->getOpcode() != ISD::CopyToReg &&
13753 UI->getOpcode() != ISD::SETCC &&
13754 UI->getOpcode() != ISD::STORE)
13757 if (ConstantSDNode *C =
13758 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13759 // An add of one will be selected as an INC.
13760 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13761 Opcode = X86ISD::INC;
13766 // An add of negative one (subtract of one) will be selected as a DEC.
13767 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13768 Opcode = X86ISD::DEC;
13774 // Otherwise use a regular EFLAGS-setting add.
13775 Opcode = X86ISD::ADD;
13780 // If we have a constant logical shift that's only used in a comparison
13781 // against zero turn it into an equivalent AND. This allows turning it into
13782 // a TEST instruction later.
13783 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13784 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13785 EVT VT = Op.getValueType();
13786 unsigned BitWidth = VT.getSizeInBits();
13787 unsigned ShAmt = Op->getConstantOperandVal(1);
13788 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13790 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13791 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13792 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13793 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13795 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13796 DAG.getConstant(Mask, dl, VT));
13797 DAG.ReplaceAllUsesWith(Op, New);
13803 // If the primary and result isn't used, don't bother using X86ISD::AND,
13804 // because a TEST instruction will be better.
13805 if (!hasNonFlagsUse(Op))
13811 // Due to the ISEL shortcoming noted above, be conservative if this op is
13812 // likely to be selected as part of a load-modify-store instruction.
13813 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13814 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13815 if (UI->getOpcode() == ISD::STORE)
13818 // Otherwise use a regular EFLAGS-setting instruction.
13819 switch (ArithOp.getOpcode()) {
13820 default: llvm_unreachable("unexpected operator!");
13821 case ISD::SUB: Opcode = X86ISD::SUB; break;
13822 case ISD::XOR: Opcode = X86ISD::XOR; break;
13823 case ISD::AND: Opcode = X86ISD::AND; break;
13825 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13826 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13827 if (EFLAGS.getNode())
13830 Opcode = X86ISD::OR;
13844 return SDValue(Op.getNode(), 1);
13850 // If we found that truncation is beneficial, perform the truncation and
13852 if (NeedTruncation) {
13853 EVT VT = Op.getValueType();
13854 SDValue WideVal = Op->getOperand(0);
13855 EVT WideVT = WideVal.getValueType();
13856 unsigned ConvertedOp = 0;
13857 // Use a target machine opcode to prevent further DAGCombine
13858 // optimizations that may separate the arithmetic operations
13859 // from the setcc node.
13860 switch (WideVal.getOpcode()) {
13862 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13863 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13864 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13865 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13866 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13871 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13872 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13873 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13874 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13880 // Emit a CMP with 0, which is the TEST pattern.
13881 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13882 DAG.getConstant(0, dl, Op.getValueType()));
13884 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13885 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13887 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13888 DAG.ReplaceAllUsesWith(Op, New);
13889 return SDValue(New.getNode(), 1);
13892 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13894 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13895 SDLoc dl, SelectionDAG &DAG) const {
13896 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13897 if (C->getAPIntValue() == 0)
13898 return EmitTest(Op0, X86CC, dl, DAG);
13900 assert(Op0.getValueType() != MVT::i1 &&
13901 "Unexpected comparison operation for MVT::i1 operands");
13904 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13905 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13906 // Do the comparison at i32 if it's smaller, besides the Atom case.
13907 // This avoids subregister aliasing issues. Keep the smaller reference
13908 // if we're optimizing for size, however, as that'll allow better folding
13909 // of memory operations.
13910 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13911 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13912 !Subtarget->isAtom()) {
13913 unsigned ExtendOp =
13914 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13915 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13916 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13918 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13919 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13920 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13922 return SDValue(Sub.getNode(), 1);
13924 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13927 /// Convert a comparison if required by the subtarget.
13928 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13929 SelectionDAG &DAG) const {
13930 // If the subtarget does not support the FUCOMI instruction, floating-point
13931 // comparisons have to be converted.
13932 if (Subtarget->hasCMov() ||
13933 Cmp.getOpcode() != X86ISD::CMP ||
13934 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13935 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13938 // The instruction selector will select an FUCOM instruction instead of
13939 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13940 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13941 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13943 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13944 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13945 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13946 DAG.getConstant(8, dl, MVT::i8));
13947 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13948 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13951 /// The minimum architected relative accuracy is 2^-12. We need one
13952 /// Newton-Raphson step to have a good float result (24 bits of precision).
13953 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13954 DAGCombinerInfo &DCI,
13955 unsigned &RefinementSteps,
13956 bool &UseOneConstNR) const {
13957 EVT VT = Op.getValueType();
13958 const char *RecipOp;
13960 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13961 // TODO: Add support for AVX512 (v16f32).
13962 // It is likely not profitable to do this for f64 because a double-precision
13963 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13964 // instructions: convert to single, rsqrtss, convert back to double, refine
13965 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13966 // along with FMA, this could be a throughput win.
13967 if (VT == MVT::f32 && Subtarget->hasSSE1())
13969 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13970 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13971 RecipOp = "vec-sqrtf";
13975 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13976 if (!Recips.isEnabled(RecipOp))
13979 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13980 UseOneConstNR = false;
13981 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13984 /// The minimum architected relative accuracy is 2^-12. We need one
13985 /// Newton-Raphson step to have a good float result (24 bits of precision).
13986 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13987 DAGCombinerInfo &DCI,
13988 unsigned &RefinementSteps) const {
13989 EVT VT = Op.getValueType();
13990 const char *RecipOp;
13992 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13993 // TODO: Add support for AVX512 (v16f32).
13994 // It is likely not profitable to do this for f64 because a double-precision
13995 // reciprocal estimate with refinement on x86 prior to FMA requires
13996 // 15 instructions: convert to single, rcpss, convert back to double, refine
13997 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13998 // along with FMA, this could be a throughput win.
13999 if (VT == MVT::f32 && Subtarget->hasSSE1())
14001 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14002 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14003 RecipOp = "vec-divf";
14007 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14008 if (!Recips.isEnabled(RecipOp))
14011 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14012 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14015 /// If we have at least two divisions that use the same divisor, convert to
14016 /// multplication by a reciprocal. This may need to be adjusted for a given
14017 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14018 /// This is because we still need one division to calculate the reciprocal and
14019 /// then we need two multiplies by that reciprocal as replacements for the
14020 /// original divisions.
14021 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14025 static bool isAllOnes(SDValue V) {
14026 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14027 return C && C->isAllOnesValue();
14030 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14031 /// if it's possible.
14032 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14033 SDLoc dl, SelectionDAG &DAG) const {
14034 SDValue Op0 = And.getOperand(0);
14035 SDValue Op1 = And.getOperand(1);
14036 if (Op0.getOpcode() == ISD::TRUNCATE)
14037 Op0 = Op0.getOperand(0);
14038 if (Op1.getOpcode() == ISD::TRUNCATE)
14039 Op1 = Op1.getOperand(0);
14042 if (Op1.getOpcode() == ISD::SHL)
14043 std::swap(Op0, Op1);
14044 if (Op0.getOpcode() == ISD::SHL) {
14045 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14046 if (And00C->getZExtValue() == 1) {
14047 // If we looked past a truncate, check that it's only truncating away
14049 unsigned BitWidth = Op0.getValueSizeInBits();
14050 unsigned AndBitWidth = And.getValueSizeInBits();
14051 if (BitWidth > AndBitWidth) {
14053 DAG.computeKnownBits(Op0, Zeros, Ones);
14054 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14058 RHS = Op0.getOperand(1);
14060 } else if (Op1.getOpcode() == ISD::Constant) {
14061 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14062 uint64_t AndRHSVal = AndRHS->getZExtValue();
14063 SDValue AndLHS = Op0;
14065 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14066 LHS = AndLHS.getOperand(0);
14067 RHS = AndLHS.getOperand(1);
14070 // Use BT if the immediate can't be encoded in a TEST instruction.
14071 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14073 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14077 if (LHS.getNode()) {
14078 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14079 // instruction. Since the shift amount is in-range-or-undefined, we know
14080 // that doing a bittest on the i32 value is ok. We extend to i32 because
14081 // the encoding for the i16 version is larger than the i32 version.
14082 // Also promote i16 to i32 for performance / code size reason.
14083 if (LHS.getValueType() == MVT::i8 ||
14084 LHS.getValueType() == MVT::i16)
14085 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14087 // If the operand types disagree, extend the shift amount to match. Since
14088 // BT ignores high bits (like shifts) we can use anyextend.
14089 if (LHS.getValueType() != RHS.getValueType())
14090 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14092 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14093 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14094 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14095 DAG.getConstant(Cond, dl, MVT::i8), BT);
14101 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14103 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14108 // SSE Condition code mapping:
14117 switch (SetCCOpcode) {
14118 default: llvm_unreachable("Unexpected SETCC condition");
14120 case ISD::SETEQ: SSECC = 0; break;
14122 case ISD::SETGT: Swap = true; // Fallthrough
14124 case ISD::SETOLT: SSECC = 1; break;
14126 case ISD::SETGE: Swap = true; // Fallthrough
14128 case ISD::SETOLE: SSECC = 2; break;
14129 case ISD::SETUO: SSECC = 3; break;
14131 case ISD::SETNE: SSECC = 4; break;
14132 case ISD::SETULE: Swap = true; // Fallthrough
14133 case ISD::SETUGE: SSECC = 5; break;
14134 case ISD::SETULT: Swap = true; // Fallthrough
14135 case ISD::SETUGT: SSECC = 6; break;
14136 case ISD::SETO: SSECC = 7; break;
14138 case ISD::SETONE: SSECC = 8; break;
14141 std::swap(Op0, Op1);
14146 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14147 // ones, and then concatenate the result back.
14148 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14149 MVT VT = Op.getSimpleValueType();
14151 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14152 "Unsupported value type for operation");
14154 unsigned NumElems = VT.getVectorNumElements();
14156 SDValue CC = Op.getOperand(2);
14158 // Extract the LHS vectors
14159 SDValue LHS = Op.getOperand(0);
14160 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14161 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14163 // Extract the RHS vectors
14164 SDValue RHS = Op.getOperand(1);
14165 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14166 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14168 // Issue the operation on the smaller types and concatenate the result back
14169 MVT EltVT = VT.getVectorElementType();
14170 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14171 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14172 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14173 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14176 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14177 SDValue Op0 = Op.getOperand(0);
14178 SDValue Op1 = Op.getOperand(1);
14179 SDValue CC = Op.getOperand(2);
14180 MVT VT = Op.getSimpleValueType();
14183 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14184 "Unexpected type for boolean compare operation");
14185 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14186 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14187 DAG.getConstant(-1, dl, VT));
14188 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14189 DAG.getConstant(-1, dl, VT));
14190 switch (SetCCOpcode) {
14191 default: llvm_unreachable("Unexpected SETCC condition");
14193 // (x == y) -> ~(x ^ y)
14194 return DAG.getNode(ISD::XOR, dl, VT,
14195 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14196 DAG.getConstant(-1, dl, VT));
14198 // (x != y) -> (x ^ y)
14199 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14202 // (x > y) -> (x & ~y)
14203 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14206 // (x < y) -> (~x & y)
14207 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14210 // (x <= y) -> (~x | y)
14211 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14214 // (x >=y) -> (x | ~y)
14215 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14219 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14220 const X86Subtarget *Subtarget) {
14221 SDValue Op0 = Op.getOperand(0);
14222 SDValue Op1 = Op.getOperand(1);
14223 SDValue CC = Op.getOperand(2);
14224 MVT VT = Op.getSimpleValueType();
14227 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14228 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14229 "Cannot set masked compare for this operation");
14231 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14233 bool Unsigned = false;
14236 switch (SetCCOpcode) {
14237 default: llvm_unreachable("Unexpected SETCC condition");
14238 case ISD::SETNE: SSECC = 4; break;
14239 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14240 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14241 case ISD::SETLT: Swap = true; //fall-through
14242 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14243 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14244 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14245 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14246 case ISD::SETULE: Unsigned = true; //fall-through
14247 case ISD::SETLE: SSECC = 2; break;
14251 std::swap(Op0, Op1);
14253 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14254 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14255 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14256 DAG.getConstant(SSECC, dl, MVT::i8));
14259 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14260 /// operand \p Op1. If non-trivial (for example because it's not constant)
14261 /// return an empty value.
14262 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14264 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14268 MVT VT = Op1.getSimpleValueType();
14269 MVT EVT = VT.getVectorElementType();
14270 unsigned n = VT.getVectorNumElements();
14271 SmallVector<SDValue, 8> ULTOp1;
14273 for (unsigned i = 0; i < n; ++i) {
14274 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14275 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14278 // Avoid underflow.
14279 APInt Val = Elt->getAPIntValue();
14283 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14286 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14289 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14290 SelectionDAG &DAG) {
14291 SDValue Op0 = Op.getOperand(0);
14292 SDValue Op1 = Op.getOperand(1);
14293 SDValue CC = Op.getOperand(2);
14294 MVT VT = Op.getSimpleValueType();
14295 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14296 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14301 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14302 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14305 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14306 unsigned Opc = X86ISD::CMPP;
14307 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14308 assert(VT.getVectorNumElements() <= 16);
14309 Opc = X86ISD::CMPM;
14311 // In the two special cases we can't handle, emit two comparisons.
14314 unsigned CombineOpc;
14315 if (SetCCOpcode == ISD::SETUEQ) {
14316 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14318 assert(SetCCOpcode == ISD::SETONE);
14319 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14322 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14323 DAG.getConstant(CC0, dl, MVT::i8));
14324 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14325 DAG.getConstant(CC1, dl, MVT::i8));
14326 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14328 // Handle all other FP comparisons here.
14329 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14330 DAG.getConstant(SSECC, dl, MVT::i8));
14333 MVT VTOp0 = Op0.getSimpleValueType();
14334 assert(VTOp0 == Op1.getSimpleValueType() &&
14335 "Expected operands with same type!");
14336 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14337 "Invalid number of packed elements for source and destination!");
14339 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14340 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14341 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14342 // legalizer firstly checks if the first operand in input to the setcc has
14343 // a legal type. If so, then it promotes the return type to that same type.
14344 // Otherwise, the return type is promoted to the 'next legal type' which,
14345 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14347 // We reach this code only if the following two conditions are met:
14348 // 1. Both return type and operand type have been promoted to wider types
14349 // by the type legalizer.
14350 // 2. The original operand type has been promoted to a 256-bit vector.
14352 // Note that condition 2. only applies for AVX targets.
14353 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14354 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14357 // The non-AVX512 code below works under the assumption that source and
14358 // destination types are the same.
14359 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14360 "Value types for source and destination must be the same!");
14362 // Break 256-bit integer vector compare into smaller ones.
14363 if (VT.is256BitVector() && !Subtarget->hasInt256())
14364 return Lower256IntVSETCC(Op, DAG);
14366 MVT OpVT = Op1.getSimpleValueType();
14367 if (OpVT.getVectorElementType() == MVT::i1)
14368 return LowerBoolVSETCC_AVX512(Op, DAG);
14370 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14371 if (Subtarget->hasAVX512()) {
14372 if (Op1.getSimpleValueType().is512BitVector() ||
14373 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14374 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14375 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14377 // In AVX-512 architecture setcc returns mask with i1 elements,
14378 // But there is no compare instruction for i8 and i16 elements in KNL.
14379 // We are not talking about 512-bit operands in this case, these
14380 // types are illegal.
14382 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14383 OpVT.getVectorElementType().getSizeInBits() >= 8))
14384 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14385 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14388 // Lower using XOP integer comparisons.
14389 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14390 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14391 // Translate compare code to XOP PCOM compare mode.
14392 unsigned CmpMode = 0;
14393 switch (SetCCOpcode) {
14394 default: llvm_unreachable("Unexpected SETCC condition");
14396 case ISD::SETLT: CmpMode = 0x00; break;
14398 case ISD::SETLE: CmpMode = 0x01; break;
14400 case ISD::SETGT: CmpMode = 0x02; break;
14402 case ISD::SETGE: CmpMode = 0x03; break;
14403 case ISD::SETEQ: CmpMode = 0x04; break;
14404 case ISD::SETNE: CmpMode = 0x05; break;
14407 // Are we comparing unsigned or signed integers?
14408 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14409 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14411 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14412 DAG.getConstant(CmpMode, dl, MVT::i8));
14415 // We are handling one of the integer comparisons here. Since SSE only has
14416 // GT and EQ comparisons for integer, swapping operands and multiple
14417 // operations may be required for some comparisons.
14419 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14420 bool Subus = false;
14422 switch (SetCCOpcode) {
14423 default: llvm_unreachable("Unexpected SETCC condition");
14424 case ISD::SETNE: Invert = true;
14425 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14426 case ISD::SETLT: Swap = true;
14427 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14428 case ISD::SETGE: Swap = true;
14429 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14430 Invert = true; break;
14431 case ISD::SETULT: Swap = true;
14432 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14433 FlipSigns = true; break;
14434 case ISD::SETUGE: Swap = true;
14435 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14436 FlipSigns = true; Invert = true; break;
14439 // Special case: Use min/max operations for SETULE/SETUGE
14440 MVT VET = VT.getVectorElementType();
14442 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14443 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14446 switch (SetCCOpcode) {
14448 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14449 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14452 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14455 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14456 if (!MinMax && hasSubus) {
14457 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14459 // t = psubus Op0, Op1
14460 // pcmpeq t, <0..0>
14461 switch (SetCCOpcode) {
14463 case ISD::SETULT: {
14464 // If the comparison is against a constant we can turn this into a
14465 // setule. With psubus, setule does not require a swap. This is
14466 // beneficial because the constant in the register is no longer
14467 // destructed as the destination so it can be hoisted out of a loop.
14468 // Only do this pre-AVX since vpcmp* is no longer destructive.
14469 if (Subtarget->hasAVX())
14471 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14472 if (ULEOp1.getNode()) {
14474 Subus = true; Invert = false; Swap = false;
14478 // Psubus is better than flip-sign because it requires no inversion.
14479 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14480 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14484 Opc = X86ISD::SUBUS;
14490 std::swap(Op0, Op1);
14492 // Check that the operation in question is available (most are plain SSE2,
14493 // but PCMPGTQ and PCMPEQQ have different requirements).
14494 if (VT == MVT::v2i64) {
14495 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14496 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14498 // First cast everything to the right type.
14499 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14500 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14502 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14503 // bits of the inputs before performing those operations. The lower
14504 // compare is always unsigned.
14507 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14509 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14510 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14511 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14512 Sign, Zero, Sign, Zero);
14514 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14515 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14517 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14518 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14519 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14521 // Create masks for only the low parts/high parts of the 64 bit integers.
14522 static const int MaskHi[] = { 1, 1, 3, 3 };
14523 static const int MaskLo[] = { 0, 0, 2, 2 };
14524 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14525 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14526 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14528 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14529 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14532 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14534 return DAG.getBitcast(VT, Result);
14537 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14538 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14539 // pcmpeqd + pshufd + pand.
14540 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14542 // First cast everything to the right type.
14543 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14544 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14547 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14549 // Make sure the lower and upper halves are both all-ones.
14550 static const int Mask[] = { 1, 0, 3, 2 };
14551 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14552 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14555 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14557 return DAG.getBitcast(VT, Result);
14561 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14562 // bits of the inputs before performing those operations.
14564 MVT EltVT = VT.getVectorElementType();
14565 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14567 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14568 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14571 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14573 // If the logical-not of the result is required, perform that now.
14575 Result = DAG.getNOT(dl, Result, VT);
14578 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14581 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14582 getZeroVector(VT, Subtarget, DAG, dl));
14587 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14589 MVT VT = Op.getSimpleValueType();
14591 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14593 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14594 && "SetCC type must be 8-bit or 1-bit integer");
14595 SDValue Op0 = Op.getOperand(0);
14596 SDValue Op1 = Op.getOperand(1);
14598 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14600 // Optimize to BT if possible.
14601 // Lower (X & (1 << N)) == 0 to BT(X, N).
14602 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14603 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14604 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14605 Op1.getOpcode() == ISD::Constant &&
14606 cast<ConstantSDNode>(Op1)->isNullValue() &&
14607 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14608 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14610 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14615 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14617 if (Op1.getOpcode() == ISD::Constant &&
14618 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14619 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14620 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14622 // If the input is a setcc, then reuse the input setcc or use a new one with
14623 // the inverted condition.
14624 if (Op0.getOpcode() == X86ISD::SETCC) {
14625 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14626 bool Invert = (CC == ISD::SETNE) ^
14627 cast<ConstantSDNode>(Op1)->isNullValue();
14631 CCode = X86::GetOppositeBranchCondition(CCode);
14632 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14633 DAG.getConstant(CCode, dl, MVT::i8),
14634 Op0.getOperand(1));
14636 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14640 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14641 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14642 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14644 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14645 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14648 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14649 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14650 if (X86CC == X86::COND_INVALID)
14653 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14654 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14655 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14656 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14658 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14662 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14663 SDValue LHS = Op.getOperand(0);
14664 SDValue RHS = Op.getOperand(1);
14665 SDValue Carry = Op.getOperand(2);
14666 SDValue Cond = Op.getOperand(3);
14669 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14670 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14672 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14673 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14674 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14675 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14676 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14679 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14680 static bool isX86LogicalCmp(SDValue Op) {
14681 unsigned Opc = Op.getNode()->getOpcode();
14682 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14683 Opc == X86ISD::SAHF)
14685 if (Op.getResNo() == 1 &&
14686 (Opc == X86ISD::ADD ||
14687 Opc == X86ISD::SUB ||
14688 Opc == X86ISD::ADC ||
14689 Opc == X86ISD::SBB ||
14690 Opc == X86ISD::SMUL ||
14691 Opc == X86ISD::UMUL ||
14692 Opc == X86ISD::INC ||
14693 Opc == X86ISD::DEC ||
14694 Opc == X86ISD::OR ||
14695 Opc == X86ISD::XOR ||
14696 Opc == X86ISD::AND))
14699 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14705 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14706 if (V.getOpcode() != ISD::TRUNCATE)
14709 SDValue VOp0 = V.getOperand(0);
14710 unsigned InBits = VOp0.getValueSizeInBits();
14711 unsigned Bits = V.getValueSizeInBits();
14712 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14715 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14716 bool addTest = true;
14717 SDValue Cond = Op.getOperand(0);
14718 SDValue Op1 = Op.getOperand(1);
14719 SDValue Op2 = Op.getOperand(2);
14721 MVT VT = Op1.getSimpleValueType();
14724 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14725 // are available or VBLENDV if AVX is available.
14726 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14727 if (Cond.getOpcode() == ISD::SETCC &&
14728 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14729 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14730 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14731 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14732 int SSECC = translateX86FSETCC(
14733 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14736 if (Subtarget->hasAVX512()) {
14737 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14738 DAG.getConstant(SSECC, DL, MVT::i8));
14739 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14742 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14743 DAG.getConstant(SSECC, DL, MVT::i8));
14745 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14746 // of 3 logic instructions for size savings and potentially speed.
14747 // Unfortunately, there is no scalar form of VBLENDV.
14749 // If either operand is a constant, don't try this. We can expect to
14750 // optimize away at least one of the logic instructions later in that
14751 // case, so that sequence would be faster than a variable blend.
14753 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14754 // uses XMM0 as the selection register. That may need just as many
14755 // instructions as the AND/ANDN/OR sequence due to register moves, so
14758 if (Subtarget->hasAVX() &&
14759 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14761 // Convert to vectors, do a VSELECT, and convert back to scalar.
14762 // All of the conversions should be optimized away.
14764 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14765 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14766 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14767 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14769 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14770 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14772 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14774 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14775 VSel, DAG.getIntPtrConstant(0, DL));
14777 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14778 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14779 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14783 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14785 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14786 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14787 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14788 Op1Scalar = Op1.getOperand(0);
14790 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14791 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14792 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14793 Op2Scalar = Op2.getOperand(0);
14794 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14795 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14796 Op1Scalar.getValueType(),
14797 Cond, Op1Scalar, Op2Scalar);
14798 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14799 return DAG.getBitcast(VT, newSelect);
14800 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14801 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14802 DAG.getIntPtrConstant(0, DL));
14806 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14807 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14808 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14809 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14810 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14811 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14812 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14814 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14817 if (Cond.getOpcode() == ISD::SETCC) {
14818 SDValue NewCond = LowerSETCC(Cond, DAG);
14819 if (NewCond.getNode())
14823 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14824 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14825 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14826 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14827 if (Cond.getOpcode() == X86ISD::SETCC &&
14828 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14829 isZero(Cond.getOperand(1).getOperand(1))) {
14830 SDValue Cmp = Cond.getOperand(1);
14832 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14834 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14835 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14836 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14838 SDValue CmpOp0 = Cmp.getOperand(0);
14839 // Apply further optimizations for special cases
14840 // (select (x != 0), -1, 0) -> neg & sbb
14841 // (select (x == 0), 0, -1) -> neg & sbb
14842 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14843 if (YC->isNullValue() &&
14844 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14845 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14846 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14847 DAG.getConstant(0, DL,
14848 CmpOp0.getValueType()),
14850 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14851 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14852 SDValue(Neg.getNode(), 1));
14856 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14857 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14858 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14860 SDValue Res = // Res = 0 or -1.
14861 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14862 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14864 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14865 Res = DAG.getNOT(DL, Res, Res.getValueType());
14867 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14868 if (!N2C || !N2C->isNullValue())
14869 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14874 // Look past (and (setcc_carry (cmp ...)), 1).
14875 if (Cond.getOpcode() == ISD::AND &&
14876 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14877 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14878 if (C && C->getAPIntValue() == 1)
14879 Cond = Cond.getOperand(0);
14882 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14883 // setting operand in place of the X86ISD::SETCC.
14884 unsigned CondOpcode = Cond.getOpcode();
14885 if (CondOpcode == X86ISD::SETCC ||
14886 CondOpcode == X86ISD::SETCC_CARRY) {
14887 CC = Cond.getOperand(0);
14889 SDValue Cmp = Cond.getOperand(1);
14890 unsigned Opc = Cmp.getOpcode();
14891 MVT VT = Op.getSimpleValueType();
14893 bool IllegalFPCMov = false;
14894 if (VT.isFloatingPoint() && !VT.isVector() &&
14895 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14896 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14898 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14899 Opc == X86ISD::BT) { // FIXME
14903 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14904 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14905 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14906 Cond.getOperand(0).getValueType() != MVT::i8)) {
14907 SDValue LHS = Cond.getOperand(0);
14908 SDValue RHS = Cond.getOperand(1);
14909 unsigned X86Opcode;
14912 switch (CondOpcode) {
14913 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14914 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14915 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14916 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14917 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14918 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14919 default: llvm_unreachable("unexpected overflowing operator");
14921 if (CondOpcode == ISD::UMULO)
14922 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14925 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14927 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14929 if (CondOpcode == ISD::UMULO)
14930 Cond = X86Op.getValue(2);
14932 Cond = X86Op.getValue(1);
14934 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14939 // Look past the truncate if the high bits are known zero.
14940 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14941 Cond = Cond.getOperand(0);
14943 // We know the result of AND is compared against zero. Try to match
14945 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14946 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
14947 CC = NewSetCC.getOperand(0);
14948 Cond = NewSetCC.getOperand(1);
14955 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14956 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14959 // a < b ? -1 : 0 -> RES = ~setcc_carry
14960 // a < b ? 0 : -1 -> RES = setcc_carry
14961 // a >= b ? -1 : 0 -> RES = setcc_carry
14962 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14963 if (Cond.getOpcode() == X86ISD::SUB) {
14964 Cond = ConvertCmpIfNecessary(Cond, DAG);
14965 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14967 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14968 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14969 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14970 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14972 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14973 return DAG.getNOT(DL, Res, Res.getValueType());
14978 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14979 // widen the cmov and push the truncate through. This avoids introducing a new
14980 // branch during isel and doesn't add any extensions.
14981 if (Op.getValueType() == MVT::i8 &&
14982 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14983 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14984 if (T1.getValueType() == T2.getValueType() &&
14985 // Blacklist CopyFromReg to avoid partial register stalls.
14986 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14987 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14988 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14989 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14993 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14994 // condition is true.
14995 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14996 SDValue Ops[] = { Op2, Op1, CC, Cond };
14997 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15000 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15001 const X86Subtarget *Subtarget,
15002 SelectionDAG &DAG) {
15003 MVT VT = Op->getSimpleValueType(0);
15004 SDValue In = Op->getOperand(0);
15005 MVT InVT = In.getSimpleValueType();
15006 MVT VTElt = VT.getVectorElementType();
15007 MVT InVTElt = InVT.getVectorElementType();
15011 if ((InVTElt == MVT::i1) &&
15012 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15013 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15015 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15016 VTElt.getSizeInBits() <= 16)) ||
15018 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15019 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15021 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15022 VTElt.getSizeInBits() >= 32))))
15023 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15025 unsigned int NumElts = VT.getVectorNumElements();
15027 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15030 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15031 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15032 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15033 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15036 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15037 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15039 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15042 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15044 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15045 if (VT.is512BitVector())
15047 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15050 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15051 const X86Subtarget *Subtarget,
15052 SelectionDAG &DAG) {
15053 SDValue In = Op->getOperand(0);
15054 MVT VT = Op->getSimpleValueType(0);
15055 MVT InVT = In.getSimpleValueType();
15056 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15058 MVT InSVT = InVT.getVectorElementType();
15059 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15061 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15063 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15068 // SSE41 targets can use the pmovsx* instructions directly.
15069 if (Subtarget->hasSSE41())
15070 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15072 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15076 // As SRAI is only available on i16/i32 types, we expand only up to i32
15077 // and handle i64 separately.
15078 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15079 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15080 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15081 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15082 Curr = DAG.getBitcast(CurrVT, Curr);
15085 SDValue SignExt = Curr;
15086 if (CurrVT != InVT) {
15087 unsigned SignExtShift =
15088 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15089 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15090 DAG.getConstant(SignExtShift, dl, MVT::i8));
15096 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15097 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15098 DAG.getConstant(31, dl, MVT::i8));
15099 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15100 return DAG.getBitcast(VT, Ext);
15106 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15107 SelectionDAG &DAG) {
15108 MVT VT = Op->getSimpleValueType(0);
15109 SDValue In = Op->getOperand(0);
15110 MVT InVT = In.getSimpleValueType();
15113 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15114 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15116 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15117 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15118 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15121 if (Subtarget->hasInt256())
15122 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15124 // Optimize vectors in AVX mode
15125 // Sign extend v8i16 to v8i32 and
15128 // Divide input vector into two parts
15129 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15130 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15131 // concat the vectors to original VT
15133 unsigned NumElems = InVT.getVectorNumElements();
15134 SDValue Undef = DAG.getUNDEF(InVT);
15136 SmallVector<int,8> ShufMask1(NumElems, -1);
15137 for (unsigned i = 0; i != NumElems/2; ++i)
15140 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15142 SmallVector<int,8> ShufMask2(NumElems, -1);
15143 for (unsigned i = 0; i != NumElems/2; ++i)
15144 ShufMask2[i] = i + NumElems/2;
15146 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15148 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15149 VT.getVectorNumElements()/2);
15151 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15152 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15154 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15157 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15158 // may emit an illegal shuffle but the expansion is still better than scalar
15159 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15160 // we'll emit a shuffle and a arithmetic shift.
15161 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15162 // TODO: It is possible to support ZExt by zeroing the undef values during
15163 // the shuffle phase or after the shuffle.
15164 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15165 SelectionDAG &DAG) {
15166 MVT RegVT = Op.getSimpleValueType();
15167 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15168 assert(RegVT.isInteger() &&
15169 "We only custom lower integer vector sext loads.");
15171 // Nothing useful we can do without SSE2 shuffles.
15172 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15174 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15176 EVT MemVT = Ld->getMemoryVT();
15177 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15178 unsigned RegSz = RegVT.getSizeInBits();
15180 ISD::LoadExtType Ext = Ld->getExtensionType();
15182 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15183 && "Only anyext and sext are currently implemented.");
15184 assert(MemVT != RegVT && "Cannot extend to the same type");
15185 assert(MemVT.isVector() && "Must load a vector from memory");
15187 unsigned NumElems = RegVT.getVectorNumElements();
15188 unsigned MemSz = MemVT.getSizeInBits();
15189 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15191 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15192 // The only way in which we have a legal 256-bit vector result but not the
15193 // integer 256-bit operations needed to directly lower a sextload is if we
15194 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15195 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15196 // correctly legalized. We do this late to allow the canonical form of
15197 // sextload to persist throughout the rest of the DAG combiner -- it wants
15198 // to fold together any extensions it can, and so will fuse a sign_extend
15199 // of an sextload into a sextload targeting a wider value.
15201 if (MemSz == 128) {
15202 // Just switch this to a normal load.
15203 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15204 "it must be a legal 128-bit vector "
15206 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15207 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15208 Ld->isInvariant(), Ld->getAlignment());
15210 assert(MemSz < 128 &&
15211 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15212 // Do an sext load to a 128-bit vector type. We want to use the same
15213 // number of elements, but elements half as wide. This will end up being
15214 // recursively lowered by this routine, but will succeed as we definitely
15215 // have all the necessary features if we're using AVX1.
15217 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15218 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15220 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15221 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15222 Ld->isNonTemporal(), Ld->isInvariant(),
15223 Ld->getAlignment());
15226 // Replace chain users with the new chain.
15227 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15228 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15230 // Finally, do a normal sign-extend to the desired register.
15231 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15234 // All sizes must be a power of two.
15235 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15236 "Non-power-of-two elements are not custom lowered!");
15238 // Attempt to load the original value using scalar loads.
15239 // Find the largest scalar type that divides the total loaded size.
15240 MVT SclrLoadTy = MVT::i8;
15241 for (MVT Tp : MVT::integer_valuetypes()) {
15242 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15247 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15248 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15250 SclrLoadTy = MVT::f64;
15252 // Calculate the number of scalar loads that we need to perform
15253 // in order to load our vector from memory.
15254 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15256 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15257 "Can only lower sext loads with a single scalar load!");
15259 unsigned loadRegZize = RegSz;
15260 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15263 // Represent our vector as a sequence of elements which are the
15264 // largest scalar that we can load.
15265 EVT LoadUnitVecVT = EVT::getVectorVT(
15266 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15268 // Represent the data using the same element type that is stored in
15269 // memory. In practice, we ''widen'' MemVT.
15271 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15272 loadRegZize / MemVT.getScalarSizeInBits());
15274 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15275 "Invalid vector type");
15277 // We can't shuffle using an illegal type.
15278 assert(TLI.isTypeLegal(WideVecVT) &&
15279 "We only lower types that form legal widened vector types");
15281 SmallVector<SDValue, 8> Chains;
15282 SDValue Ptr = Ld->getBasePtr();
15283 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15284 TLI.getPointerTy(DAG.getDataLayout()));
15285 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15287 for (unsigned i = 0; i < NumLoads; ++i) {
15288 // Perform a single load.
15289 SDValue ScalarLoad =
15290 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15291 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15292 Ld->getAlignment());
15293 Chains.push_back(ScalarLoad.getValue(1));
15294 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15295 // another round of DAGCombining.
15297 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15299 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15300 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15302 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15305 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15307 // Bitcast the loaded value to a vector of the original element type, in
15308 // the size of the target vector type.
15309 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15310 unsigned SizeRatio = RegSz / MemSz;
15312 if (Ext == ISD::SEXTLOAD) {
15313 // If we have SSE4.1, we can directly emit a VSEXT node.
15314 if (Subtarget->hasSSE41()) {
15315 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15316 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15320 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15322 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15323 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15325 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15326 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15330 // Redistribute the loaded elements into the different locations.
15331 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15332 for (unsigned i = 0; i != NumElems; ++i)
15333 ShuffleVec[i * SizeRatio] = i;
15335 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15336 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15338 // Bitcast to the requested type.
15339 Shuff = DAG.getBitcast(RegVT, Shuff);
15340 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15344 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15345 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15346 // from the AND / OR.
15347 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15348 Opc = Op.getOpcode();
15349 if (Opc != ISD::OR && Opc != ISD::AND)
15351 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15352 Op.getOperand(0).hasOneUse() &&
15353 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15354 Op.getOperand(1).hasOneUse());
15357 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15358 // 1 and that the SETCC node has a single use.
15359 static bool isXor1OfSetCC(SDValue Op) {
15360 if (Op.getOpcode() != ISD::XOR)
15362 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15363 if (N1C && N1C->getAPIntValue() == 1) {
15364 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15365 Op.getOperand(0).hasOneUse();
15370 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15371 bool addTest = true;
15372 SDValue Chain = Op.getOperand(0);
15373 SDValue Cond = Op.getOperand(1);
15374 SDValue Dest = Op.getOperand(2);
15377 bool Inverted = false;
15379 if (Cond.getOpcode() == ISD::SETCC) {
15380 // Check for setcc([su]{add,sub,mul}o == 0).
15381 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15382 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15383 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15384 Cond.getOperand(0).getResNo() == 1 &&
15385 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15386 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15387 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15388 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15389 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15390 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15392 Cond = Cond.getOperand(0);
15394 SDValue NewCond = LowerSETCC(Cond, DAG);
15395 if (NewCond.getNode())
15400 // FIXME: LowerXALUO doesn't handle these!!
15401 else if (Cond.getOpcode() == X86ISD::ADD ||
15402 Cond.getOpcode() == X86ISD::SUB ||
15403 Cond.getOpcode() == X86ISD::SMUL ||
15404 Cond.getOpcode() == X86ISD::UMUL)
15405 Cond = LowerXALUO(Cond, DAG);
15408 // Look pass (and (setcc_carry (cmp ...)), 1).
15409 if (Cond.getOpcode() == ISD::AND &&
15410 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15411 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15412 if (C && C->getAPIntValue() == 1)
15413 Cond = Cond.getOperand(0);
15416 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15417 // setting operand in place of the X86ISD::SETCC.
15418 unsigned CondOpcode = Cond.getOpcode();
15419 if (CondOpcode == X86ISD::SETCC ||
15420 CondOpcode == X86ISD::SETCC_CARRY) {
15421 CC = Cond.getOperand(0);
15423 SDValue Cmp = Cond.getOperand(1);
15424 unsigned Opc = Cmp.getOpcode();
15425 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15426 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15430 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15434 // These can only come from an arithmetic instruction with overflow,
15435 // e.g. SADDO, UADDO.
15436 Cond = Cond.getNode()->getOperand(1);
15442 CondOpcode = Cond.getOpcode();
15443 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15444 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15445 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15446 Cond.getOperand(0).getValueType() != MVT::i8)) {
15447 SDValue LHS = Cond.getOperand(0);
15448 SDValue RHS = Cond.getOperand(1);
15449 unsigned X86Opcode;
15452 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15453 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15455 switch (CondOpcode) {
15456 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15458 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15460 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15463 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15464 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15468 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15471 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15472 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15473 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15474 default: llvm_unreachable("unexpected overflowing operator");
15477 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15478 if (CondOpcode == ISD::UMULO)
15479 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15482 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15484 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15486 if (CondOpcode == ISD::UMULO)
15487 Cond = X86Op.getValue(2);
15489 Cond = X86Op.getValue(1);
15491 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15495 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15496 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15497 if (CondOpc == ISD::OR) {
15498 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15499 // two branches instead of an explicit OR instruction with a
15501 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15502 isX86LogicalCmp(Cmp)) {
15503 CC = Cond.getOperand(0).getOperand(0);
15504 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15505 Chain, Dest, CC, Cmp);
15506 CC = Cond.getOperand(1).getOperand(0);
15510 } else { // ISD::AND
15511 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15512 // two branches instead of an explicit AND instruction with a
15513 // separate test. However, we only do this if this block doesn't
15514 // have a fall-through edge, because this requires an explicit
15515 // jmp when the condition is false.
15516 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15517 isX86LogicalCmp(Cmp) &&
15518 Op.getNode()->hasOneUse()) {
15519 X86::CondCode CCode =
15520 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15521 CCode = X86::GetOppositeBranchCondition(CCode);
15522 CC = DAG.getConstant(CCode, dl, MVT::i8);
15523 SDNode *User = *Op.getNode()->use_begin();
15524 // Look for an unconditional branch following this conditional branch.
15525 // We need this because we need to reverse the successors in order
15526 // to implement FCMP_OEQ.
15527 if (User->getOpcode() == ISD::BR) {
15528 SDValue FalseBB = User->getOperand(1);
15530 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15531 assert(NewBR == User);
15535 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15536 Chain, Dest, CC, Cmp);
15537 X86::CondCode CCode =
15538 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15539 CCode = X86::GetOppositeBranchCondition(CCode);
15540 CC = DAG.getConstant(CCode, dl, MVT::i8);
15546 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15547 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15548 // It should be transformed during dag combiner except when the condition
15549 // is set by a arithmetics with overflow node.
15550 X86::CondCode CCode =
15551 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15552 CCode = X86::GetOppositeBranchCondition(CCode);
15553 CC = DAG.getConstant(CCode, dl, MVT::i8);
15554 Cond = Cond.getOperand(0).getOperand(1);
15556 } else if (Cond.getOpcode() == ISD::SETCC &&
15557 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15558 // For FCMP_OEQ, we can emit
15559 // two branches instead of an explicit AND instruction with a
15560 // separate test. However, we only do this if this block doesn't
15561 // have a fall-through edge, because this requires an explicit
15562 // jmp when the condition is false.
15563 if (Op.getNode()->hasOneUse()) {
15564 SDNode *User = *Op.getNode()->use_begin();
15565 // Look for an unconditional branch following this conditional branch.
15566 // We need this because we need to reverse the successors in order
15567 // to implement FCMP_OEQ.
15568 if (User->getOpcode() == ISD::BR) {
15569 SDValue FalseBB = User->getOperand(1);
15571 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15572 assert(NewBR == User);
15576 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15577 Cond.getOperand(0), Cond.getOperand(1));
15578 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15579 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15580 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15581 Chain, Dest, CC, Cmp);
15582 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15587 } else if (Cond.getOpcode() == ISD::SETCC &&
15588 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15589 // For FCMP_UNE, we can emit
15590 // two branches instead of an explicit AND instruction with a
15591 // separate test. However, we only do this if this block doesn't
15592 // have a fall-through edge, because this requires an explicit
15593 // jmp when the condition is false.
15594 if (Op.getNode()->hasOneUse()) {
15595 SDNode *User = *Op.getNode()->use_begin();
15596 // Look for an unconditional branch following this conditional branch.
15597 // We need this because we need to reverse the successors in order
15598 // to implement FCMP_UNE.
15599 if (User->getOpcode() == ISD::BR) {
15600 SDValue FalseBB = User->getOperand(1);
15602 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15603 assert(NewBR == User);
15606 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15607 Cond.getOperand(0), Cond.getOperand(1));
15608 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15609 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15610 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15611 Chain, Dest, CC, Cmp);
15612 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15622 // Look pass the truncate if the high bits are known zero.
15623 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15624 Cond = Cond.getOperand(0);
15626 // We know the result of AND is compared against zero. Try to match
15628 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15629 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15630 CC = NewSetCC.getOperand(0);
15631 Cond = NewSetCC.getOperand(1);
15638 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15639 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15640 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15642 Cond = ConvertCmpIfNecessary(Cond, DAG);
15643 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15644 Chain, Dest, CC, Cond);
15647 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15648 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15649 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15650 // that the guard pages used by the OS virtual memory manager are allocated in
15651 // correct sequence.
15653 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15654 SelectionDAG &DAG) const {
15655 MachineFunction &MF = DAG.getMachineFunction();
15656 bool SplitStack = MF.shouldSplitStack();
15657 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15662 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15663 SDNode* Node = Op.getNode();
15665 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15666 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15667 " not tell us which reg is the stack pointer!");
15668 EVT VT = Node->getValueType(0);
15669 SDValue Tmp1 = SDValue(Node, 0);
15670 SDValue Tmp2 = SDValue(Node, 1);
15671 SDValue Tmp3 = Node->getOperand(2);
15672 SDValue Chain = Tmp1.getOperand(0);
15674 // Chain the dynamic stack allocation so that it doesn't modify the stack
15675 // pointer when other instructions are using the stack.
15676 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15679 SDValue Size = Tmp2.getOperand(1);
15680 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15681 Chain = SP.getValue(1);
15682 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15683 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15684 unsigned StackAlign = TFI.getStackAlignment();
15685 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15686 if (Align > StackAlign)
15687 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15688 DAG.getConstant(-(uint64_t)Align, dl, VT));
15689 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15691 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15692 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15695 SDValue Ops[2] = { Tmp1, Tmp2 };
15696 return DAG.getMergeValues(Ops, dl);
15700 SDValue Chain = Op.getOperand(0);
15701 SDValue Size = Op.getOperand(1);
15702 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15703 EVT VT = Op.getNode()->getValueType(0);
15705 bool Is64Bit = Subtarget->is64Bit();
15706 MVT SPTy = getPointerTy(DAG.getDataLayout());
15709 MachineRegisterInfo &MRI = MF.getRegInfo();
15712 // The 64 bit implementation of segmented stacks needs to clobber both r10
15713 // r11. This makes it impossible to use it along with nested parameters.
15714 const Function *F = MF.getFunction();
15716 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15718 if (I->hasNestAttr())
15719 report_fatal_error("Cannot use segmented stacks with functions that "
15720 "have nested arguments.");
15723 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15724 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15725 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15726 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15727 DAG.getRegister(Vreg, SPTy));
15728 SDValue Ops1[2] = { Value, Chain };
15729 return DAG.getMergeValues(Ops1, dl);
15732 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15734 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15735 Flag = Chain.getValue(1);
15736 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15738 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15740 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15741 unsigned SPReg = RegInfo->getStackRegister();
15742 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15743 Chain = SP.getValue(1);
15746 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15747 DAG.getConstant(-(uint64_t)Align, dl, VT));
15748 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15751 SDValue Ops1[2] = { SP, Chain };
15752 return DAG.getMergeValues(Ops1, dl);
15756 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15757 MachineFunction &MF = DAG.getMachineFunction();
15758 auto PtrVT = getPointerTy(MF.getDataLayout());
15759 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15761 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15764 if (!Subtarget->is64Bit() ||
15765 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15766 // vastart just stores the address of the VarArgsFrameIndex slot into the
15767 // memory location argument.
15768 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15769 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15770 MachinePointerInfo(SV), false, false, 0);
15774 // gp_offset (0 - 6 * 8)
15775 // fp_offset (48 - 48 + 8 * 16)
15776 // overflow_arg_area (point to parameters coming in memory).
15778 SmallVector<SDValue, 8> MemOps;
15779 SDValue FIN = Op.getOperand(1);
15781 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15782 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15784 FIN, MachinePointerInfo(SV), false, false, 0);
15785 MemOps.push_back(Store);
15788 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15789 Store = DAG.getStore(Op.getOperand(0), DL,
15790 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15792 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15793 MemOps.push_back(Store);
15795 // Store ptr to overflow_arg_area
15796 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15797 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15798 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15799 MachinePointerInfo(SV, 8),
15801 MemOps.push_back(Store);
15803 // Store ptr to reg_save_area.
15804 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15805 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15806 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15807 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15808 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15809 MemOps.push_back(Store);
15810 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15813 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15814 assert(Subtarget->is64Bit() &&
15815 "LowerVAARG only handles 64-bit va_arg!");
15816 assert(Op.getNode()->getNumOperands() == 4);
15818 MachineFunction &MF = DAG.getMachineFunction();
15819 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15820 // The Win64 ABI uses char* instead of a structure.
15821 return DAG.expandVAArg(Op.getNode());
15823 SDValue Chain = Op.getOperand(0);
15824 SDValue SrcPtr = Op.getOperand(1);
15825 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15826 unsigned Align = Op.getConstantOperandVal(3);
15829 EVT ArgVT = Op.getNode()->getValueType(0);
15830 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15831 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15834 // Decide which area this value should be read from.
15835 // TODO: Implement the AMD64 ABI in its entirety. This simple
15836 // selection mechanism works only for the basic types.
15837 if (ArgVT == MVT::f80) {
15838 llvm_unreachable("va_arg for f80 not yet implemented");
15839 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15840 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15841 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15842 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15844 llvm_unreachable("Unhandled argument type in LowerVAARG");
15847 if (ArgMode == 2) {
15848 // Sanity Check: Make sure using fp_offset makes sense.
15849 assert(!Subtarget->useSoftFloat() &&
15850 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15851 Subtarget->hasSSE1());
15854 // Insert VAARG_64 node into the DAG
15855 // VAARG_64 returns two values: Variable Argument Address, Chain
15856 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15857 DAG.getConstant(ArgMode, dl, MVT::i8),
15858 DAG.getConstant(Align, dl, MVT::i32)};
15859 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15860 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15861 VTs, InstOps, MVT::i64,
15862 MachinePointerInfo(SV),
15864 /*Volatile=*/false,
15866 /*WriteMem=*/true);
15867 Chain = VAARG.getValue(1);
15869 // Load the next argument and return it
15870 return DAG.getLoad(ArgVT, dl,
15873 MachinePointerInfo(),
15874 false, false, false, 0);
15877 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15878 SelectionDAG &DAG) {
15879 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15880 // where a va_list is still an i8*.
15881 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15882 if (Subtarget->isCallingConvWin64(
15883 DAG.getMachineFunction().getFunction()->getCallingConv()))
15884 // Probably a Win64 va_copy.
15885 return DAG.expandVACopy(Op.getNode());
15887 SDValue Chain = Op.getOperand(0);
15888 SDValue DstPtr = Op.getOperand(1);
15889 SDValue SrcPtr = Op.getOperand(2);
15890 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15891 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15894 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15895 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15897 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15900 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15901 // amount is a constant. Takes immediate version of shift as input.
15902 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15903 SDValue SrcOp, uint64_t ShiftAmt,
15904 SelectionDAG &DAG) {
15905 MVT ElementType = VT.getVectorElementType();
15907 // Fold this packed shift into its first operand if ShiftAmt is 0.
15911 // Check for ShiftAmt >= element width
15912 if (ShiftAmt >= ElementType.getSizeInBits()) {
15913 if (Opc == X86ISD::VSRAI)
15914 ShiftAmt = ElementType.getSizeInBits() - 1;
15916 return DAG.getConstant(0, dl, VT);
15919 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15920 && "Unknown target vector shift-by-constant node");
15922 // Fold this packed vector shift into a build vector if SrcOp is a
15923 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15924 if (VT == SrcOp.getSimpleValueType() &&
15925 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15926 SmallVector<SDValue, 8> Elts;
15927 unsigned NumElts = SrcOp->getNumOperands();
15928 ConstantSDNode *ND;
15931 default: llvm_unreachable(nullptr);
15932 case X86ISD::VSHLI:
15933 for (unsigned i=0; i!=NumElts; ++i) {
15934 SDValue CurrentOp = SrcOp->getOperand(i);
15935 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15936 Elts.push_back(CurrentOp);
15939 ND = cast<ConstantSDNode>(CurrentOp);
15940 const APInt &C = ND->getAPIntValue();
15941 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15944 case X86ISD::VSRLI:
15945 for (unsigned i=0; i!=NumElts; ++i) {
15946 SDValue CurrentOp = SrcOp->getOperand(i);
15947 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15948 Elts.push_back(CurrentOp);
15951 ND = cast<ConstantSDNode>(CurrentOp);
15952 const APInt &C = ND->getAPIntValue();
15953 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15956 case X86ISD::VSRAI:
15957 for (unsigned i=0; i!=NumElts; ++i) {
15958 SDValue CurrentOp = SrcOp->getOperand(i);
15959 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15960 Elts.push_back(CurrentOp);
15963 ND = cast<ConstantSDNode>(CurrentOp);
15964 const APInt &C = ND->getAPIntValue();
15965 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15970 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15973 return DAG.getNode(Opc, dl, VT, SrcOp,
15974 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15977 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15978 // may or may not be a constant. Takes immediate version of shift as input.
15979 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15980 SDValue SrcOp, SDValue ShAmt,
15981 SelectionDAG &DAG) {
15982 MVT SVT = ShAmt.getSimpleValueType();
15983 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15985 // Catch shift-by-constant.
15986 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15987 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15988 CShAmt->getZExtValue(), DAG);
15990 // Change opcode to non-immediate version
15992 default: llvm_unreachable("Unknown target vector shift node");
15993 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15994 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15995 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15998 const X86Subtarget &Subtarget =
15999 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16000 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16001 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16002 // Let the shuffle legalizer expand this shift amount node.
16003 SDValue Op0 = ShAmt.getOperand(0);
16004 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16005 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16007 // Need to build a vector containing shift amount.
16008 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16009 SmallVector<SDValue, 4> ShOps;
16010 ShOps.push_back(ShAmt);
16011 if (SVT == MVT::i32) {
16012 ShOps.push_back(DAG.getConstant(0, dl, SVT));
16013 ShOps.push_back(DAG.getUNDEF(SVT));
16015 ShOps.push_back(DAG.getUNDEF(SVT));
16017 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16018 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16021 // The return type has to be a 128-bit type with the same element
16022 // type as the input type.
16023 MVT EltVT = VT.getVectorElementType();
16024 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16026 ShAmt = DAG.getBitcast(ShVT, ShAmt);
16027 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16030 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16031 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16032 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16033 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16034 SDValue PreservedSrc,
16035 const X86Subtarget *Subtarget,
16036 SelectionDAG &DAG) {
16037 MVT VT = Op.getSimpleValueType();
16038 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16040 unsigned OpcodeSelect = ISD::VSELECT;
16043 if (isAllOnes(Mask))
16046 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16047 MVT newMaskVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16048 VMask = DAG.getBitcast(MaskVT,
16049 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
16051 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16052 Mask.getSimpleValueType().getSizeInBits());
16053 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16054 // are extracted by EXTRACT_SUBVECTOR.
16055 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16056 DAG.getBitcast(BitcastVT, Mask),
16057 DAG.getIntPtrConstant(0, dl));
16060 switch (Op.getOpcode()) {
16062 case X86ISD::PCMPEQM:
16063 case X86ISD::PCMPGTM:
16065 case X86ISD::CMPMU:
16066 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16067 case X86ISD::VFPCLASS:
16068 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16069 case X86ISD::VTRUNC:
16070 case X86ISD::VTRUNCS:
16071 case X86ISD::VTRUNCUS:
16072 // We can't use ISD::VSELECT here because it is not always "Legal"
16073 // for the destination type. For example vpmovqb require only AVX512
16074 // and vselect that can operate on byte element type require BWI
16075 OpcodeSelect = X86ISD::SELECT;
16078 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16079 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16080 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16083 /// \brief Creates an SDNode for a predicated scalar operation.
16084 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16085 /// The mask is coming as MVT::i8 and it should be truncated
16086 /// to MVT::i1 while lowering masking intrinsics.
16087 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16088 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16089 /// for a scalar instruction.
16090 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16091 SDValue PreservedSrc,
16092 const X86Subtarget *Subtarget,
16093 SelectionDAG &DAG) {
16094 if (isAllOnes(Mask))
16097 MVT VT = Op.getSimpleValueType();
16099 // The mask should be of type MVT::i1
16100 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16102 if (Op.getOpcode() == X86ISD::FSETCC)
16103 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16104 if (Op.getOpcode() == X86ISD::VFPCLASS)
16105 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16107 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16108 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16109 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16112 static int getSEHRegistrationNodeSize(const Function *Fn) {
16113 if (!Fn->hasPersonalityFn())
16114 report_fatal_error(
16115 "querying registration node size for function without personality");
16116 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16117 // WinEHStatePass for the full struct definition.
16118 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16119 case EHPersonality::MSVC_X86SEH: return 24;
16120 case EHPersonality::MSVC_CXX: return 16;
16123 report_fatal_error("can only recover FP for MSVC EH personality functions");
16126 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16127 /// function or when returning to a parent frame after catching an exception, we
16128 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16129 /// Here's the math:
16130 /// RegNodeBase = EntryEBP - RegNodeSize
16131 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16132 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16133 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16134 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16135 SDValue EntryEBP) {
16136 MachineFunction &MF = DAG.getMachineFunction();
16139 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16140 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16142 // It's possible that the parent function no longer has a personality function
16143 // if the exceptional code was optimized away, in which case we just return
16144 // the incoming EBP.
16145 if (!Fn->hasPersonalityFn())
16148 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16150 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16152 MCSymbol *OffsetSym =
16153 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16154 GlobalValue::getRealLinkageName(Fn->getName()));
16155 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16156 SDValue RegNodeFrameOffset =
16157 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16159 // RegNodeBase = EntryEBP - RegNodeSize
16160 // ParentFP = RegNodeBase - RegNodeFrameOffset
16161 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16162 DAG.getConstant(RegNodeSize, dl, PtrVT));
16163 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16166 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16167 SelectionDAG &DAG) {
16169 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16170 MVT VT = Op.getSimpleValueType();
16171 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16173 switch(IntrData->Type) {
16174 case INTR_TYPE_1OP:
16175 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16176 case INTR_TYPE_2OP:
16177 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16179 case INTR_TYPE_2OP_IMM8:
16180 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16181 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16182 case INTR_TYPE_3OP:
16183 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16184 Op.getOperand(2), Op.getOperand(3));
16185 case INTR_TYPE_4OP:
16186 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16187 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16188 case INTR_TYPE_1OP_MASK_RM: {
16189 SDValue Src = Op.getOperand(1);
16190 SDValue PassThru = Op.getOperand(2);
16191 SDValue Mask = Op.getOperand(3);
16192 SDValue RoundingMode;
16193 // We allways add rounding mode to the Node.
16194 // If the rounding mode is not specified, we add the
16195 // "current direction" mode.
16196 if (Op.getNumOperands() == 4)
16198 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16200 RoundingMode = Op.getOperand(4);
16201 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16202 if (IntrWithRoundingModeOpcode != 0)
16203 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16204 X86::STATIC_ROUNDING::CUR_DIRECTION)
16205 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16206 dl, Op.getValueType(), Src, RoundingMode),
16207 Mask, PassThru, Subtarget, DAG);
16208 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16210 Mask, PassThru, Subtarget, DAG);
16212 case INTR_TYPE_1OP_MASK: {
16213 SDValue Src = Op.getOperand(1);
16214 SDValue PassThru = Op.getOperand(2);
16215 SDValue Mask = Op.getOperand(3);
16216 // We add rounding mode to the Node when
16217 // - RM Opcode is specified and
16218 // - RM is not "current direction".
16219 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16220 if (IntrWithRoundingModeOpcode != 0) {
16221 SDValue Rnd = Op.getOperand(4);
16222 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16223 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16224 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16225 dl, Op.getValueType(),
16227 Mask, PassThru, Subtarget, DAG);
16230 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16231 Mask, PassThru, Subtarget, DAG);
16233 case INTR_TYPE_SCALAR_MASK: {
16234 SDValue Src1 = Op.getOperand(1);
16235 SDValue Src2 = Op.getOperand(2);
16236 SDValue passThru = Op.getOperand(3);
16237 SDValue Mask = Op.getOperand(4);
16238 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16239 Mask, passThru, Subtarget, DAG);
16241 case INTR_TYPE_SCALAR_MASK_RM: {
16242 SDValue Src1 = Op.getOperand(1);
16243 SDValue Src2 = Op.getOperand(2);
16244 SDValue Src0 = Op.getOperand(3);
16245 SDValue Mask = Op.getOperand(4);
16246 // There are 2 kinds of intrinsics in this group:
16247 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16248 // (2) With rounding mode and sae - 7 operands.
16249 if (Op.getNumOperands() == 6) {
16250 SDValue Sae = Op.getOperand(5);
16251 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16252 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16254 Mask, Src0, Subtarget, DAG);
16256 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16257 SDValue RoundingMode = Op.getOperand(5);
16258 SDValue Sae = Op.getOperand(6);
16259 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16260 RoundingMode, Sae),
16261 Mask, Src0, Subtarget, DAG);
16263 case INTR_TYPE_2OP_MASK:
16264 case INTR_TYPE_2OP_IMM8_MASK: {
16265 SDValue Src1 = Op.getOperand(1);
16266 SDValue Src2 = Op.getOperand(2);
16267 SDValue PassThru = Op.getOperand(3);
16268 SDValue Mask = Op.getOperand(4);
16270 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16271 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16273 // We specify 2 possible opcodes for intrinsics with rounding modes.
16274 // First, we check if the intrinsic may have non-default rounding mode,
16275 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16276 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16277 if (IntrWithRoundingModeOpcode != 0) {
16278 SDValue Rnd = Op.getOperand(5);
16279 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16280 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16281 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16282 dl, Op.getValueType(),
16284 Mask, PassThru, Subtarget, DAG);
16287 // TODO: Intrinsics should have fast-math-flags to propagate.
16288 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16289 Mask, PassThru, Subtarget, DAG);
16291 case INTR_TYPE_2OP_MASK_RM: {
16292 SDValue Src1 = Op.getOperand(1);
16293 SDValue Src2 = Op.getOperand(2);
16294 SDValue PassThru = Op.getOperand(3);
16295 SDValue Mask = Op.getOperand(4);
16296 // We specify 2 possible modes for intrinsics, with/without rounding
16298 // First, we check if the intrinsic have rounding mode (6 operands),
16299 // if not, we set rounding mode to "current".
16301 if (Op.getNumOperands() == 6)
16302 Rnd = Op.getOperand(5);
16304 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16305 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16307 Mask, PassThru, Subtarget, DAG);
16309 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16310 SDValue Src1 = Op.getOperand(1);
16311 SDValue Src2 = Op.getOperand(2);
16312 SDValue Src3 = Op.getOperand(3);
16313 SDValue PassThru = Op.getOperand(4);
16314 SDValue Mask = Op.getOperand(5);
16315 SDValue Sae = Op.getOperand(6);
16317 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16319 Mask, PassThru, Subtarget, DAG);
16321 case INTR_TYPE_3OP_MASK_RM: {
16322 SDValue Src1 = Op.getOperand(1);
16323 SDValue Src2 = Op.getOperand(2);
16324 SDValue Imm = Op.getOperand(3);
16325 SDValue PassThru = Op.getOperand(4);
16326 SDValue Mask = Op.getOperand(5);
16327 // We specify 2 possible modes for intrinsics, with/without rounding
16329 // First, we check if the intrinsic have rounding mode (7 operands),
16330 // if not, we set rounding mode to "current".
16332 if (Op.getNumOperands() == 7)
16333 Rnd = Op.getOperand(6);
16335 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16336 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16337 Src1, Src2, Imm, Rnd),
16338 Mask, PassThru, Subtarget, DAG);
16340 case INTR_TYPE_3OP_IMM8_MASK:
16341 case INTR_TYPE_3OP_MASK:
16342 case INSERT_SUBVEC: {
16343 SDValue Src1 = Op.getOperand(1);
16344 SDValue Src2 = Op.getOperand(2);
16345 SDValue Src3 = Op.getOperand(3);
16346 SDValue PassThru = Op.getOperand(4);
16347 SDValue Mask = Op.getOperand(5);
16349 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16350 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16351 else if (IntrData->Type == INSERT_SUBVEC) {
16352 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16353 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16354 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16355 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16356 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16359 // We specify 2 possible opcodes for intrinsics with rounding modes.
16360 // First, we check if the intrinsic may have non-default rounding mode,
16361 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16362 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16363 if (IntrWithRoundingModeOpcode != 0) {
16364 SDValue Rnd = Op.getOperand(6);
16365 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16366 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16367 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16368 dl, Op.getValueType(),
16369 Src1, Src2, Src3, Rnd),
16370 Mask, PassThru, Subtarget, DAG);
16373 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16375 Mask, PassThru, Subtarget, DAG);
16377 case VPERM_3OP_MASKZ:
16378 case VPERM_3OP_MASK:
16381 case FMA_OP_MASK: {
16382 SDValue Src1 = Op.getOperand(1);
16383 SDValue Src2 = Op.getOperand(2);
16384 SDValue Src3 = Op.getOperand(3);
16385 SDValue Mask = Op.getOperand(4);
16386 MVT VT = Op.getSimpleValueType();
16387 SDValue PassThru = SDValue();
16389 // set PassThru element
16390 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16391 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16392 else if (IntrData->Type == FMA_OP_MASK3)
16397 // We specify 2 possible opcodes for intrinsics with rounding modes.
16398 // First, we check if the intrinsic may have non-default rounding mode,
16399 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16400 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16401 if (IntrWithRoundingModeOpcode != 0) {
16402 SDValue Rnd = Op.getOperand(5);
16403 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16404 X86::STATIC_ROUNDING::CUR_DIRECTION)
16405 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16406 dl, Op.getValueType(),
16407 Src1, Src2, Src3, Rnd),
16408 Mask, PassThru, Subtarget, DAG);
16410 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16411 dl, Op.getValueType(),
16413 Mask, PassThru, Subtarget, DAG);
16415 case TERLOG_OP_MASK:
16416 case TERLOG_OP_MASKZ: {
16417 SDValue Src1 = Op.getOperand(1);
16418 SDValue Src2 = Op.getOperand(2);
16419 SDValue Src3 = Op.getOperand(3);
16420 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16421 SDValue Mask = Op.getOperand(5);
16422 MVT VT = Op.getSimpleValueType();
16423 SDValue PassThru = Src1;
16424 // Set PassThru element.
16425 if (IntrData->Type == TERLOG_OP_MASKZ)
16426 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16428 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16429 Src1, Src2, Src3, Src4),
16430 Mask, PassThru, Subtarget, DAG);
16433 // FPclass intrinsics with mask
16434 SDValue Src1 = Op.getOperand(1);
16435 MVT VT = Src1.getSimpleValueType();
16436 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16437 SDValue Imm = Op.getOperand(2);
16438 SDValue Mask = Op.getOperand(3);
16439 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16440 Mask.getSimpleValueType().getSizeInBits());
16441 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16442 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16443 DAG.getTargetConstant(0, dl, MaskVT),
16445 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16446 DAG.getUNDEF(BitcastVT), FPclassMask,
16447 DAG.getIntPtrConstant(0, dl));
16448 return DAG.getBitcast(Op.getValueType(), Res);
16451 SDValue Src1 = Op.getOperand(1);
16452 SDValue Imm = Op.getOperand(2);
16453 SDValue Mask = Op.getOperand(3);
16454 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16455 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16456 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16457 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16460 case CMP_MASK_CC: {
16461 // Comparison intrinsics with masks.
16462 // Example of transformation:
16463 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16464 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16466 // (v8i1 (insert_subvector undef,
16467 // (v2i1 (and (PCMPEQM %a, %b),
16468 // (extract_subvector
16469 // (v8i1 (bitcast %mask)), 0))), 0))))
16470 MVT VT = Op.getOperand(1).getSimpleValueType();
16471 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16472 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16473 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16474 Mask.getSimpleValueType().getSizeInBits());
16476 if (IntrData->Type == CMP_MASK_CC) {
16477 SDValue CC = Op.getOperand(3);
16478 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16479 // We specify 2 possible opcodes for intrinsics with rounding modes.
16480 // First, we check if the intrinsic may have non-default rounding mode,
16481 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16482 if (IntrData->Opc1 != 0) {
16483 SDValue Rnd = Op.getOperand(5);
16484 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16485 X86::STATIC_ROUNDING::CUR_DIRECTION)
16486 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16487 Op.getOperand(2), CC, Rnd);
16489 //default rounding mode
16491 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16492 Op.getOperand(2), CC);
16495 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16496 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16499 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16500 DAG.getTargetConstant(0, dl,
16503 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16504 DAG.getUNDEF(BitcastVT), CmpMask,
16505 DAG.getIntPtrConstant(0, dl));
16506 return DAG.getBitcast(Op.getValueType(), Res);
16508 case CMP_MASK_SCALAR_CC: {
16509 SDValue Src1 = Op.getOperand(1);
16510 SDValue Src2 = Op.getOperand(2);
16511 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16512 SDValue Mask = Op.getOperand(4);
16515 if (IntrData->Opc1 != 0) {
16516 SDValue Rnd = Op.getOperand(5);
16517 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16518 X86::STATIC_ROUNDING::CUR_DIRECTION)
16519 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16521 //default rounding mode
16523 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16525 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16526 DAG.getTargetConstant(0, dl,
16530 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16531 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16532 DAG.getValueType(MVT::i1));
16534 case COMI: { // Comparison intrinsics
16535 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16536 SDValue LHS = Op.getOperand(1);
16537 SDValue RHS = Op.getOperand(2);
16538 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16539 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16540 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16541 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16542 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16543 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16546 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16547 Op.getOperand(1), Op.getOperand(2), DAG);
16549 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16550 Op.getSimpleValueType(),
16552 Op.getOperand(2), DAG),
16553 Op.getOperand(4), Op.getOperand(3), Subtarget,
16555 case COMPRESS_EXPAND_IN_REG: {
16556 SDValue Mask = Op.getOperand(3);
16557 SDValue DataToCompress = Op.getOperand(1);
16558 SDValue PassThru = Op.getOperand(2);
16559 if (isAllOnes(Mask)) // return data as is
16560 return Op.getOperand(1);
16562 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16564 Mask, PassThru, Subtarget, DAG);
16567 SDValue Mask = Op.getOperand(1);
16568 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16569 Mask = DAG.getBitcast(MaskVT, Mask);
16570 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16573 SDValue Mask = Op.getOperand(3);
16574 MVT VT = Op.getSimpleValueType();
16575 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16576 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16577 Mask.getSimpleValueType().getSizeInBits());
16579 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16580 DAG.getBitcast(BitcastVT, Mask),
16581 DAG.getIntPtrConstant(0, dl));
16582 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16591 default: return SDValue(); // Don't custom lower most intrinsics.
16593 case Intrinsic::x86_avx2_permd:
16594 case Intrinsic::x86_avx2_permps:
16595 // Operands intentionally swapped. Mask is last operand to intrinsic,
16596 // but second operand for node/instruction.
16597 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16598 Op.getOperand(2), Op.getOperand(1));
16600 // ptest and testp intrinsics. The intrinsic these come from are designed to
16601 // return an integer value, not just an instruction so lower it to the ptest
16602 // or testp pattern and a setcc for the result.
16603 case Intrinsic::x86_sse41_ptestz:
16604 case Intrinsic::x86_sse41_ptestc:
16605 case Intrinsic::x86_sse41_ptestnzc:
16606 case Intrinsic::x86_avx_ptestz_256:
16607 case Intrinsic::x86_avx_ptestc_256:
16608 case Intrinsic::x86_avx_ptestnzc_256:
16609 case Intrinsic::x86_avx_vtestz_ps:
16610 case Intrinsic::x86_avx_vtestc_ps:
16611 case Intrinsic::x86_avx_vtestnzc_ps:
16612 case Intrinsic::x86_avx_vtestz_pd:
16613 case Intrinsic::x86_avx_vtestc_pd:
16614 case Intrinsic::x86_avx_vtestnzc_pd:
16615 case Intrinsic::x86_avx_vtestz_ps_256:
16616 case Intrinsic::x86_avx_vtestc_ps_256:
16617 case Intrinsic::x86_avx_vtestnzc_ps_256:
16618 case Intrinsic::x86_avx_vtestz_pd_256:
16619 case Intrinsic::x86_avx_vtestc_pd_256:
16620 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16621 bool IsTestPacked = false;
16624 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16625 case Intrinsic::x86_avx_vtestz_ps:
16626 case Intrinsic::x86_avx_vtestz_pd:
16627 case Intrinsic::x86_avx_vtestz_ps_256:
16628 case Intrinsic::x86_avx_vtestz_pd_256:
16629 IsTestPacked = true; // Fallthrough
16630 case Intrinsic::x86_sse41_ptestz:
16631 case Intrinsic::x86_avx_ptestz_256:
16633 X86CC = X86::COND_E;
16635 case Intrinsic::x86_avx_vtestc_ps:
16636 case Intrinsic::x86_avx_vtestc_pd:
16637 case Intrinsic::x86_avx_vtestc_ps_256:
16638 case Intrinsic::x86_avx_vtestc_pd_256:
16639 IsTestPacked = true; // Fallthrough
16640 case Intrinsic::x86_sse41_ptestc:
16641 case Intrinsic::x86_avx_ptestc_256:
16643 X86CC = X86::COND_B;
16645 case Intrinsic::x86_avx_vtestnzc_ps:
16646 case Intrinsic::x86_avx_vtestnzc_pd:
16647 case Intrinsic::x86_avx_vtestnzc_ps_256:
16648 case Intrinsic::x86_avx_vtestnzc_pd_256:
16649 IsTestPacked = true; // Fallthrough
16650 case Intrinsic::x86_sse41_ptestnzc:
16651 case Intrinsic::x86_avx_ptestnzc_256:
16653 X86CC = X86::COND_A;
16657 SDValue LHS = Op.getOperand(1);
16658 SDValue RHS = Op.getOperand(2);
16659 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16660 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16661 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16662 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16663 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16665 case Intrinsic::x86_avx512_kortestz_w:
16666 case Intrinsic::x86_avx512_kortestc_w: {
16667 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16668 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16669 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16670 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16671 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16672 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16673 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16676 case Intrinsic::x86_sse42_pcmpistria128:
16677 case Intrinsic::x86_sse42_pcmpestria128:
16678 case Intrinsic::x86_sse42_pcmpistric128:
16679 case Intrinsic::x86_sse42_pcmpestric128:
16680 case Intrinsic::x86_sse42_pcmpistrio128:
16681 case Intrinsic::x86_sse42_pcmpestrio128:
16682 case Intrinsic::x86_sse42_pcmpistris128:
16683 case Intrinsic::x86_sse42_pcmpestris128:
16684 case Intrinsic::x86_sse42_pcmpistriz128:
16685 case Intrinsic::x86_sse42_pcmpestriz128: {
16689 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16690 case Intrinsic::x86_sse42_pcmpistria128:
16691 Opcode = X86ISD::PCMPISTRI;
16692 X86CC = X86::COND_A;
16694 case Intrinsic::x86_sse42_pcmpestria128:
16695 Opcode = X86ISD::PCMPESTRI;
16696 X86CC = X86::COND_A;
16698 case Intrinsic::x86_sse42_pcmpistric128:
16699 Opcode = X86ISD::PCMPISTRI;
16700 X86CC = X86::COND_B;
16702 case Intrinsic::x86_sse42_pcmpestric128:
16703 Opcode = X86ISD::PCMPESTRI;
16704 X86CC = X86::COND_B;
16706 case Intrinsic::x86_sse42_pcmpistrio128:
16707 Opcode = X86ISD::PCMPISTRI;
16708 X86CC = X86::COND_O;
16710 case Intrinsic::x86_sse42_pcmpestrio128:
16711 Opcode = X86ISD::PCMPESTRI;
16712 X86CC = X86::COND_O;
16714 case Intrinsic::x86_sse42_pcmpistris128:
16715 Opcode = X86ISD::PCMPISTRI;
16716 X86CC = X86::COND_S;
16718 case Intrinsic::x86_sse42_pcmpestris128:
16719 Opcode = X86ISD::PCMPESTRI;
16720 X86CC = X86::COND_S;
16722 case Intrinsic::x86_sse42_pcmpistriz128:
16723 Opcode = X86ISD::PCMPISTRI;
16724 X86CC = X86::COND_E;
16726 case Intrinsic::x86_sse42_pcmpestriz128:
16727 Opcode = X86ISD::PCMPESTRI;
16728 X86CC = X86::COND_E;
16731 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16732 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16733 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16734 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16735 DAG.getConstant(X86CC, dl, MVT::i8),
16736 SDValue(PCMP.getNode(), 1));
16737 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16740 case Intrinsic::x86_sse42_pcmpistri128:
16741 case Intrinsic::x86_sse42_pcmpestri128: {
16743 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16744 Opcode = X86ISD::PCMPISTRI;
16746 Opcode = X86ISD::PCMPESTRI;
16748 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16749 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16750 return DAG.getNode(Opcode, dl, VTs, NewOps);
16753 case Intrinsic::x86_seh_lsda: {
16754 // Compute the symbol for the LSDA. We know it'll get emitted later.
16755 MachineFunction &MF = DAG.getMachineFunction();
16756 SDValue Op1 = Op.getOperand(1);
16757 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16758 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16759 GlobalValue::getRealLinkageName(Fn->getName()));
16761 // Generate a simple absolute symbol reference. This intrinsic is only
16762 // supported on 32-bit Windows, which isn't PIC.
16763 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16764 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16767 case Intrinsic::x86_seh_recoverfp: {
16768 SDValue FnOp = Op.getOperand(1);
16769 SDValue IncomingFPOp = Op.getOperand(2);
16770 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16771 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16773 report_fatal_error(
16774 "llvm.x86.seh.recoverfp must take a function as the first argument");
16775 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16778 case Intrinsic::localaddress: {
16779 // Returns one of the stack, base, or frame pointer registers, depending on
16780 // which is used to reference local variables.
16781 MachineFunction &MF = DAG.getMachineFunction();
16782 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16784 if (RegInfo->hasBasePointer(MF))
16785 Reg = RegInfo->getBaseRegister();
16786 else // This function handles the SP or FP case.
16787 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16788 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16793 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16794 SDValue Src, SDValue Mask, SDValue Base,
16795 SDValue Index, SDValue ScaleOp, SDValue Chain,
16796 const X86Subtarget * Subtarget) {
16798 auto *C = cast<ConstantSDNode>(ScaleOp);
16799 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16800 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16801 Index.getSimpleValueType().getVectorNumElements());
16803 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16805 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16807 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16808 Mask.getSimpleValueType().getSizeInBits());
16810 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16811 // are extracted by EXTRACT_SUBVECTOR.
16812 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16813 DAG.getBitcast(BitcastVT, Mask),
16814 DAG.getIntPtrConstant(0, dl));
16816 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16817 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16818 SDValue Segment = DAG.getRegister(0, MVT::i32);
16819 if (Src.getOpcode() == ISD::UNDEF)
16820 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16821 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16822 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16823 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16824 return DAG.getMergeValues(RetOps, dl);
16827 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16828 SDValue Src, SDValue Mask, SDValue Base,
16829 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16831 auto *C = cast<ConstantSDNode>(ScaleOp);
16832 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16833 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16834 SDValue Segment = DAG.getRegister(0, MVT::i32);
16835 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16836 Index.getSimpleValueType().getVectorNumElements());
16838 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16840 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16842 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16843 Mask.getSimpleValueType().getSizeInBits());
16845 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16846 // are extracted by EXTRACT_SUBVECTOR.
16847 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16848 DAG.getBitcast(BitcastVT, Mask),
16849 DAG.getIntPtrConstant(0, dl));
16851 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16852 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16853 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16854 return SDValue(Res, 1);
16857 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16858 SDValue Mask, SDValue Base, SDValue Index,
16859 SDValue ScaleOp, SDValue Chain) {
16861 auto *C = cast<ConstantSDNode>(ScaleOp);
16862 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16863 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16864 SDValue Segment = DAG.getRegister(0, MVT::i32);
16866 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16868 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16870 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16872 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16873 //SDVTList VTs = DAG.getVTList(MVT::Other);
16874 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16875 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16876 return SDValue(Res, 0);
16879 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16880 // read performance monitor counters (x86_rdpmc).
16881 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16882 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16883 SmallVectorImpl<SDValue> &Results) {
16884 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16885 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16888 // The ECX register is used to select the index of the performance counter
16890 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16892 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16894 // Reads the content of a 64-bit performance counter and returns it in the
16895 // registers EDX:EAX.
16896 if (Subtarget->is64Bit()) {
16897 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16898 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16901 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16902 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16905 Chain = HI.getValue(1);
16907 if (Subtarget->is64Bit()) {
16908 // The EAX register is loaded with the low-order 32 bits. The EDX register
16909 // is loaded with the supported high-order bits of the counter.
16910 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16911 DAG.getConstant(32, DL, MVT::i8));
16912 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16913 Results.push_back(Chain);
16917 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16918 SDValue Ops[] = { LO, HI };
16919 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16920 Results.push_back(Pair);
16921 Results.push_back(Chain);
16924 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16925 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16926 // also used to custom lower READCYCLECOUNTER nodes.
16927 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16928 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16929 SmallVectorImpl<SDValue> &Results) {
16930 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16931 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16934 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16935 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16936 // and the EAX register is loaded with the low-order 32 bits.
16937 if (Subtarget->is64Bit()) {
16938 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16939 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16942 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16943 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16946 SDValue Chain = HI.getValue(1);
16948 if (Opcode == X86ISD::RDTSCP_DAG) {
16949 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16951 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16952 // the ECX register. Add 'ecx' explicitly to the chain.
16953 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16955 // Explicitly store the content of ECX at the location passed in input
16956 // to the 'rdtscp' intrinsic.
16957 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16958 MachinePointerInfo(), false, false, 0);
16961 if (Subtarget->is64Bit()) {
16962 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16963 // the EAX register is loaded with the low-order 32 bits.
16964 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16965 DAG.getConstant(32, DL, MVT::i8));
16966 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16967 Results.push_back(Chain);
16971 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16972 SDValue Ops[] = { LO, HI };
16973 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16974 Results.push_back(Pair);
16975 Results.push_back(Chain);
16978 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16979 SelectionDAG &DAG) {
16980 SmallVector<SDValue, 2> Results;
16982 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16984 return DAG.getMergeValues(Results, DL);
16987 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16988 SelectionDAG &DAG) {
16989 MachineFunction &MF = DAG.getMachineFunction();
16990 const Function *Fn = MF.getFunction();
16992 SDValue Chain = Op.getOperand(0);
16994 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16995 "using llvm.x86.seh.restoreframe requires a frame pointer");
16997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16998 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
17000 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17001 unsigned FrameReg =
17002 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17003 unsigned SPReg = RegInfo->getStackRegister();
17004 unsigned SlotSize = RegInfo->getSlotSize();
17006 // Get incoming EBP.
17007 SDValue IncomingEBP =
17008 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
17010 // SP is saved in the first field of every registration node, so load
17011 // [EBP-RegNodeSize] into SP.
17012 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
17013 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
17014 DAG.getConstant(-RegNodeSize, dl, VT));
17016 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
17017 false, VT.getScalarSizeInBits() / 8);
17018 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
17020 if (!RegInfo->needsStackRealignment(MF)) {
17021 // Adjust EBP to point back to the original frame position.
17022 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
17023 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
17025 assert(RegInfo->hasBasePointer(MF) &&
17026 "functions with Win32 EH must use frame or base pointer register");
17028 // Reload the base pointer (ESI) with the adjusted incoming EBP.
17029 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
17030 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
17032 // Reload the spilled EBP value, now that the stack and base pointers are
17034 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
17035 X86FI->setHasSEHFramePtrSave(true);
17036 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
17037 X86FI->setSEHFramePtrSaveIndex(FI);
17038 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
17039 MachinePointerInfo(), false, false, false,
17040 VT.getScalarSizeInBits() / 8);
17041 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
17047 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17048 MachineFunction &MF = DAG.getMachineFunction();
17049 SDValue Chain = Op.getOperand(0);
17050 SDValue RegNode = Op.getOperand(2);
17051 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17053 report_fatal_error("EH registrations only live in functions using WinEH");
17055 // Cast the operand to an alloca, and remember the frame index.
17056 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17058 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17059 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17061 // Return the chain operand without making any DAG nodes.
17065 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17066 /// return truncate Store/MaskedStore Node
17067 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17071 SDValue Mask = Op.getOperand(4);
17072 SDValue DataToTruncate = Op.getOperand(3);
17073 SDValue Addr = Op.getOperand(2);
17074 SDValue Chain = Op.getOperand(0);
17076 MVT VT = DataToTruncate.getSimpleValueType();
17077 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17079 if (isAllOnes(Mask)) // return just a truncate store
17080 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17081 MachinePointerInfo(), SVT, false, false,
17082 SVT.getScalarSizeInBits()/8);
17084 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17085 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17086 Mask.getSimpleValueType().getSizeInBits());
17087 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17088 // are extracted by EXTRACT_SUBVECTOR.
17089 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17090 DAG.getBitcast(BitcastVT, Mask),
17091 DAG.getIntPtrConstant(0, dl));
17093 MachineMemOperand *MMO = DAG.getMachineFunction().
17094 getMachineMemOperand(MachinePointerInfo(),
17095 MachineMemOperand::MOStore, SVT.getStoreSize(),
17096 SVT.getScalarSizeInBits()/8);
17098 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17099 VMask, SVT, MMO, true);
17102 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17103 SelectionDAG &DAG) {
17104 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17106 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17108 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17109 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17110 else if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17111 return MarkEHRegistrationNode(Op, DAG);
17116 switch(IntrData->Type) {
17117 default: llvm_unreachable("Unknown Intrinsic Type");
17120 // Emit the node with the right value type.
17121 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17122 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17124 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17125 // Otherwise return the value from Rand, which is always 0, casted to i32.
17126 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17127 DAG.getConstant(1, dl, Op->getValueType(1)),
17128 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17129 SDValue(Result.getNode(), 1) };
17130 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17131 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17134 // Return { result, isValid, chain }.
17135 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17136 SDValue(Result.getNode(), 2));
17139 //gather(v1, mask, index, base, scale);
17140 SDValue Chain = Op.getOperand(0);
17141 SDValue Src = Op.getOperand(2);
17142 SDValue Base = Op.getOperand(3);
17143 SDValue Index = Op.getOperand(4);
17144 SDValue Mask = Op.getOperand(5);
17145 SDValue Scale = Op.getOperand(6);
17146 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17150 //scatter(base, mask, index, v1, scale);
17151 SDValue Chain = Op.getOperand(0);
17152 SDValue Base = Op.getOperand(2);
17153 SDValue Mask = Op.getOperand(3);
17154 SDValue Index = Op.getOperand(4);
17155 SDValue Src = Op.getOperand(5);
17156 SDValue Scale = Op.getOperand(6);
17157 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17161 SDValue Hint = Op.getOperand(6);
17162 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17163 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17164 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17165 SDValue Chain = Op.getOperand(0);
17166 SDValue Mask = Op.getOperand(2);
17167 SDValue Index = Op.getOperand(3);
17168 SDValue Base = Op.getOperand(4);
17169 SDValue Scale = Op.getOperand(5);
17170 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17172 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17174 SmallVector<SDValue, 2> Results;
17175 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17177 return DAG.getMergeValues(Results, dl);
17179 // Read Performance Monitoring Counters.
17181 SmallVector<SDValue, 2> Results;
17182 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17183 return DAG.getMergeValues(Results, dl);
17185 // XTEST intrinsics.
17187 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17188 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17189 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17190 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17192 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17193 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17194 Ret, SDValue(InTrans.getNode(), 1));
17198 SmallVector<SDValue, 2> Results;
17199 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17200 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17201 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17202 DAG.getConstant(-1, dl, MVT::i8));
17203 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17204 Op.getOperand(4), GenCF.getValue(1));
17205 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17206 Op.getOperand(5), MachinePointerInfo(),
17208 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17209 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17211 Results.push_back(SetCC);
17212 Results.push_back(Store);
17213 return DAG.getMergeValues(Results, dl);
17215 case COMPRESS_TO_MEM: {
17217 SDValue Mask = Op.getOperand(4);
17218 SDValue DataToCompress = Op.getOperand(3);
17219 SDValue Addr = Op.getOperand(2);
17220 SDValue Chain = Op.getOperand(0);
17222 MVT VT = DataToCompress.getSimpleValueType();
17223 if (isAllOnes(Mask)) // return just a store
17224 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17225 MachinePointerInfo(), false, false,
17226 VT.getScalarSizeInBits()/8);
17228 SDValue Compressed =
17229 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17230 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17231 return DAG.getStore(Chain, dl, Compressed, Addr,
17232 MachinePointerInfo(), false, false,
17233 VT.getScalarSizeInBits()/8);
17235 case TRUNCATE_TO_MEM_VI8:
17236 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17237 case TRUNCATE_TO_MEM_VI16:
17238 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17239 case TRUNCATE_TO_MEM_VI32:
17240 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17241 case EXPAND_FROM_MEM: {
17243 SDValue Mask = Op.getOperand(4);
17244 SDValue PassThru = Op.getOperand(3);
17245 SDValue Addr = Op.getOperand(2);
17246 SDValue Chain = Op.getOperand(0);
17247 MVT VT = Op.getSimpleValueType();
17249 if (isAllOnes(Mask)) // return just a load
17250 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17251 false, VT.getScalarSizeInBits()/8);
17253 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17254 false, false, false,
17255 VT.getScalarSizeInBits()/8);
17257 SDValue Results[] = {
17258 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17259 Mask, PassThru, Subtarget, DAG), Chain};
17260 return DAG.getMergeValues(Results, dl);
17265 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17266 SelectionDAG &DAG) const {
17267 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17268 MFI->setReturnAddressIsTaken(true);
17270 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17273 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17275 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17278 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17279 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17280 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17281 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17282 DAG.getNode(ISD::ADD, dl, PtrVT,
17283 FrameAddr, Offset),
17284 MachinePointerInfo(), false, false, false, 0);
17287 // Just load the return address.
17288 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17289 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17290 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17293 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17294 MachineFunction &MF = DAG.getMachineFunction();
17295 MachineFrameInfo *MFI = MF.getFrameInfo();
17296 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17297 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17298 EVT VT = Op.getValueType();
17300 MFI->setFrameAddressIsTaken(true);
17302 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17303 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17304 // is not possible to crawl up the stack without looking at the unwind codes
17306 int FrameAddrIndex = FuncInfo->getFAIndex();
17307 if (!FrameAddrIndex) {
17308 // Set up a frame object for the return address.
17309 unsigned SlotSize = RegInfo->getSlotSize();
17310 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17311 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17312 FuncInfo->setFAIndex(FrameAddrIndex);
17314 return DAG.getFrameIndex(FrameAddrIndex, VT);
17317 unsigned FrameReg =
17318 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17319 SDLoc dl(Op); // FIXME probably not meaningful
17320 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17321 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17322 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17323 "Invalid Frame Register!");
17324 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17326 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17327 MachinePointerInfo(),
17328 false, false, false, 0);
17332 // FIXME? Maybe this could be a TableGen attribute on some registers and
17333 // this table could be generated automatically from RegInfo.
17334 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17335 SelectionDAG &DAG) const {
17336 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17337 const MachineFunction &MF = DAG.getMachineFunction();
17339 unsigned Reg = StringSwitch<unsigned>(RegName)
17340 .Case("esp", X86::ESP)
17341 .Case("rsp", X86::RSP)
17342 .Case("ebp", X86::EBP)
17343 .Case("rbp", X86::RBP)
17346 if (Reg == X86::EBP || Reg == X86::RBP) {
17347 if (!TFI.hasFP(MF))
17348 report_fatal_error("register " + StringRef(RegName) +
17349 " is allocatable: function has no frame pointer");
17352 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17353 unsigned FrameReg =
17354 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17355 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17356 "Invalid Frame Register!");
17364 report_fatal_error("Invalid register name global variable");
17367 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17368 SelectionDAG &DAG) const {
17369 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17370 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17373 unsigned X86TargetLowering::getExceptionPointerRegister(
17374 const Constant *PersonalityFn) const {
17375 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17376 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17378 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17381 unsigned X86TargetLowering::getExceptionSelectorRegister(
17382 const Constant *PersonalityFn) const {
17383 // Funclet personalities don't use selectors (the runtime does the selection).
17384 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17385 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17388 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17389 SDValue Chain = Op.getOperand(0);
17390 SDValue Offset = Op.getOperand(1);
17391 SDValue Handler = Op.getOperand(2);
17394 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17395 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17396 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17397 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17398 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17399 "Invalid Frame Register!");
17400 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17401 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17403 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17404 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17406 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17407 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17409 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17411 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17412 DAG.getRegister(StoreAddrReg, PtrVT));
17415 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17416 SelectionDAG &DAG) const {
17418 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17419 DAG.getVTList(MVT::i32, MVT::Other),
17420 Op.getOperand(0), Op.getOperand(1));
17423 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17424 SelectionDAG &DAG) const {
17426 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17427 Op.getOperand(0), Op.getOperand(1));
17430 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17431 return Op.getOperand(0);
17434 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17435 SelectionDAG &DAG) const {
17436 SDValue Root = Op.getOperand(0);
17437 SDValue Trmp = Op.getOperand(1); // trampoline
17438 SDValue FPtr = Op.getOperand(2); // nested function
17439 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17442 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17443 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17445 if (Subtarget->is64Bit()) {
17446 SDValue OutChains[6];
17448 // Large code-model.
17449 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17450 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17452 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17453 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17455 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17457 // Load the pointer to the nested function into R11.
17458 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17459 SDValue Addr = Trmp;
17460 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17461 Addr, MachinePointerInfo(TrmpAddr),
17464 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17465 DAG.getConstant(2, dl, MVT::i64));
17466 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17467 MachinePointerInfo(TrmpAddr, 2),
17470 // Load the 'nest' parameter value into R10.
17471 // R10 is specified in X86CallingConv.td
17472 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17473 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17474 DAG.getConstant(10, dl, MVT::i64));
17475 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17476 Addr, MachinePointerInfo(TrmpAddr, 10),
17479 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17480 DAG.getConstant(12, dl, MVT::i64));
17481 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17482 MachinePointerInfo(TrmpAddr, 12),
17485 // Jump to the nested function.
17486 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17487 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17488 DAG.getConstant(20, dl, MVT::i64));
17489 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17490 Addr, MachinePointerInfo(TrmpAddr, 20),
17493 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17494 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17495 DAG.getConstant(22, dl, MVT::i64));
17496 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17497 Addr, MachinePointerInfo(TrmpAddr, 22),
17500 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17502 const Function *Func =
17503 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17504 CallingConv::ID CC = Func->getCallingConv();
17509 llvm_unreachable("Unsupported calling convention");
17510 case CallingConv::C:
17511 case CallingConv::X86_StdCall: {
17512 // Pass 'nest' parameter in ECX.
17513 // Must be kept in sync with X86CallingConv.td
17514 NestReg = X86::ECX;
17516 // Check that ECX wasn't needed by an 'inreg' parameter.
17517 FunctionType *FTy = Func->getFunctionType();
17518 const AttributeSet &Attrs = Func->getAttributes();
17520 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17521 unsigned InRegCount = 0;
17524 for (FunctionType::param_iterator I = FTy->param_begin(),
17525 E = FTy->param_end(); I != E; ++I, ++Idx)
17526 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17527 auto &DL = DAG.getDataLayout();
17528 // FIXME: should only count parameters that are lowered to integers.
17529 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17532 if (InRegCount > 2) {
17533 report_fatal_error("Nest register in use - reduce number of inreg"
17539 case CallingConv::X86_FastCall:
17540 case CallingConv::X86_ThisCall:
17541 case CallingConv::Fast:
17542 // Pass 'nest' parameter in EAX.
17543 // Must be kept in sync with X86CallingConv.td
17544 NestReg = X86::EAX;
17548 SDValue OutChains[4];
17549 SDValue Addr, Disp;
17551 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17552 DAG.getConstant(10, dl, MVT::i32));
17553 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17555 // This is storing the opcode for MOV32ri.
17556 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17557 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17558 OutChains[0] = DAG.getStore(Root, dl,
17559 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17560 Trmp, MachinePointerInfo(TrmpAddr),
17563 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17564 DAG.getConstant(1, dl, MVT::i32));
17565 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17566 MachinePointerInfo(TrmpAddr, 1),
17569 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17570 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17571 DAG.getConstant(5, dl, MVT::i32));
17572 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17573 Addr, MachinePointerInfo(TrmpAddr, 5),
17576 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17577 DAG.getConstant(6, dl, MVT::i32));
17578 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17579 MachinePointerInfo(TrmpAddr, 6),
17582 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17586 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17587 SelectionDAG &DAG) const {
17589 The rounding mode is in bits 11:10 of FPSR, and has the following
17591 00 Round to nearest
17596 FLT_ROUNDS, on the other hand, expects the following:
17603 To perform the conversion, we do:
17604 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17607 MachineFunction &MF = DAG.getMachineFunction();
17608 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17609 unsigned StackAlignment = TFI.getStackAlignment();
17610 MVT VT = Op.getSimpleValueType();
17613 // Save FP Control Word to stack slot
17614 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17615 SDValue StackSlot =
17616 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17618 MachineMemOperand *MMO =
17619 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17620 MachineMemOperand::MOStore, 2, 2);
17622 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17623 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17624 DAG.getVTList(MVT::Other),
17625 Ops, MVT::i16, MMO);
17627 // Load FP Control Word from stack slot
17628 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17629 MachinePointerInfo(), false, false, false, 0);
17631 // Transform as necessary
17633 DAG.getNode(ISD::SRL, DL, MVT::i16,
17634 DAG.getNode(ISD::AND, DL, MVT::i16,
17635 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17636 DAG.getConstant(11, DL, MVT::i8));
17638 DAG.getNode(ISD::SRL, DL, MVT::i16,
17639 DAG.getNode(ISD::AND, DL, MVT::i16,
17640 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17641 DAG.getConstant(9, DL, MVT::i8));
17644 DAG.getNode(ISD::AND, DL, MVT::i16,
17645 DAG.getNode(ISD::ADD, DL, MVT::i16,
17646 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17647 DAG.getConstant(1, DL, MVT::i16)),
17648 DAG.getConstant(3, DL, MVT::i16));
17650 return DAG.getNode((VT.getSizeInBits() < 16 ?
17651 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17654 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17656 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17657 // to 512-bit vector.
17658 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17659 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17660 // split the vector, perform operation on it's Lo a Hi part and
17661 // concatenate the results.
17662 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17664 MVT VT = Op.getSimpleValueType();
17665 MVT EltVT = VT.getVectorElementType();
17666 unsigned NumElems = VT.getVectorNumElements();
17668 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17669 // Extend to 512 bit vector.
17670 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17671 "Unsupported value type for operation");
17673 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17674 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17675 DAG.getUNDEF(NewVT),
17677 DAG.getIntPtrConstant(0, dl));
17678 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17680 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17681 DAG.getIntPtrConstant(0, dl));
17684 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17685 "Unsupported element type");
17687 if (16 < NumElems) {
17688 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17690 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17691 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17693 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17694 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17696 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17699 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17701 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17702 "Unsupported value type for operation");
17704 // Use native supported vector instruction vplzcntd.
17705 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17706 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17707 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17708 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17710 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17713 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17714 SelectionDAG &DAG) {
17715 MVT VT = Op.getSimpleValueType();
17717 unsigned NumBits = VT.getSizeInBits();
17720 if (VT.isVector() && Subtarget->hasAVX512())
17721 return LowerVectorCTLZ_AVX512(Op, DAG);
17723 Op = Op.getOperand(0);
17724 if (VT == MVT::i8) {
17725 // Zero extend to i32 since there is not an i8 bsr.
17727 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17730 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17731 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17732 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17734 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17737 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17738 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17741 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17743 // Finally xor with NumBits-1.
17744 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17745 DAG.getConstant(NumBits - 1, dl, OpVT));
17748 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17752 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17753 SelectionDAG &DAG) {
17754 MVT VT = Op.getSimpleValueType();
17756 unsigned NumBits = VT.getSizeInBits();
17759 if (VT.isVector() && Subtarget->hasAVX512())
17760 return LowerVectorCTLZ_AVX512(Op, DAG);
17762 Op = Op.getOperand(0);
17763 if (VT == MVT::i8) {
17764 // Zero extend to i32 since there is not an i8 bsr.
17766 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17769 // Issue a bsr (scan bits in reverse).
17770 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17771 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17773 // And xor with NumBits-1.
17774 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17775 DAG.getConstant(NumBits - 1, dl, OpVT));
17778 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17782 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17783 MVT VT = Op.getSimpleValueType();
17784 unsigned NumBits = VT.getScalarSizeInBits();
17787 if (VT.isVector()) {
17788 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17790 SDValue N0 = Op.getOperand(0);
17791 SDValue Zero = DAG.getConstant(0, dl, VT);
17793 // lsb(x) = (x & -x)
17794 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17795 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17797 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17798 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17799 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17800 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17801 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17802 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17805 // cttz(x) = ctpop(lsb - 1)
17806 SDValue One = DAG.getConstant(1, dl, VT);
17807 return DAG.getNode(ISD::CTPOP, dl, VT,
17808 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17811 assert(Op.getOpcode() == ISD::CTTZ &&
17812 "Only scalar CTTZ requires custom lowering");
17814 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17815 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17816 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17818 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17821 DAG.getConstant(NumBits, dl, VT),
17822 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17825 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17828 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17829 // ones, and then concatenate the result back.
17830 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17831 MVT VT = Op.getSimpleValueType();
17833 assert(VT.is256BitVector() && VT.isInteger() &&
17834 "Unsupported value type for operation");
17836 unsigned NumElems = VT.getVectorNumElements();
17839 // Extract the LHS vectors
17840 SDValue LHS = Op.getOperand(0);
17841 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17842 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17844 // Extract the RHS vectors
17845 SDValue RHS = Op.getOperand(1);
17846 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17847 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17849 MVT EltVT = VT.getVectorElementType();
17850 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17852 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17853 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17854 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17857 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17858 if (Op.getValueType() == MVT::i1)
17859 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17860 Op.getOperand(0), Op.getOperand(1));
17861 assert(Op.getSimpleValueType().is256BitVector() &&
17862 Op.getSimpleValueType().isInteger() &&
17863 "Only handle AVX 256-bit vector integer operation");
17864 return Lower256IntArith(Op, DAG);
17867 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17868 if (Op.getValueType() == MVT::i1)
17869 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17870 Op.getOperand(0), Op.getOperand(1));
17871 assert(Op.getSimpleValueType().is256BitVector() &&
17872 Op.getSimpleValueType().isInteger() &&
17873 "Only handle AVX 256-bit vector integer operation");
17874 return Lower256IntArith(Op, DAG);
17877 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17878 assert(Op.getSimpleValueType().is256BitVector() &&
17879 Op.getSimpleValueType().isInteger() &&
17880 "Only handle AVX 256-bit vector integer operation");
17881 return Lower256IntArith(Op, DAG);
17884 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17885 SelectionDAG &DAG) {
17887 MVT VT = Op.getSimpleValueType();
17890 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17892 // Decompose 256-bit ops into smaller 128-bit ops.
17893 if (VT.is256BitVector() && !Subtarget->hasInt256())
17894 return Lower256IntArith(Op, DAG);
17896 SDValue A = Op.getOperand(0);
17897 SDValue B = Op.getOperand(1);
17899 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17900 // pairs, multiply and truncate.
17901 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17902 if (Subtarget->hasInt256()) {
17903 if (VT == MVT::v32i8) {
17904 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17905 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17906 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17907 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17908 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17909 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17910 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17911 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17912 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17913 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17916 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17917 return DAG.getNode(
17918 ISD::TRUNCATE, dl, VT,
17919 DAG.getNode(ISD::MUL, dl, ExVT,
17920 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17921 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17924 assert(VT == MVT::v16i8 &&
17925 "Pre-AVX2 support only supports v16i8 multiplication");
17926 MVT ExVT = MVT::v8i16;
17928 // Extract the lo parts and sign extend to i16
17930 if (Subtarget->hasSSE41()) {
17931 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17932 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17934 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17935 -1, 4, -1, 5, -1, 6, -1, 7};
17936 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17937 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17938 ALo = DAG.getBitcast(ExVT, ALo);
17939 BLo = DAG.getBitcast(ExVT, BLo);
17940 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17941 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17944 // Extract the hi parts and sign extend to i16
17946 if (Subtarget->hasSSE41()) {
17947 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17948 -1, -1, -1, -1, -1, -1, -1, -1};
17949 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17950 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17951 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17952 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17954 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17955 -1, 12, -1, 13, -1, 14, -1, 15};
17956 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17957 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17958 AHi = DAG.getBitcast(ExVT, AHi);
17959 BHi = DAG.getBitcast(ExVT, BHi);
17960 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17961 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17964 // Multiply, mask the lower 8bits of the lo/hi results and pack
17965 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17966 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17967 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17968 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17969 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17972 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17973 if (VT == MVT::v4i32) {
17974 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17975 "Should not custom lower when pmuldq is available!");
17977 // Extract the odd parts.
17978 static const int UnpackMask[] = { 1, -1, 3, -1 };
17979 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17980 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17982 // Multiply the even parts.
17983 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17984 // Now multiply odd parts.
17985 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17987 Evens = DAG.getBitcast(VT, Evens);
17988 Odds = DAG.getBitcast(VT, Odds);
17990 // Merge the two vectors back together with a shuffle. This expands into 2
17992 static const int ShufMask[] = { 0, 4, 2, 6 };
17993 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17996 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17997 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17999 // Ahi = psrlqi(a, 32);
18000 // Bhi = psrlqi(b, 32);
18002 // AloBlo = pmuludq(a, b);
18003 // AloBhi = pmuludq(a, Bhi);
18004 // AhiBlo = pmuludq(Ahi, b);
18006 // AloBhi = psllqi(AloBhi, 32);
18007 // AhiBlo = psllqi(AhiBlo, 32);
18008 // return AloBlo + AloBhi + AhiBlo;
18010 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18011 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18013 SDValue AhiBlo = Ahi;
18014 SDValue AloBhi = Bhi;
18015 // Bit cast to 32-bit vectors for MULUDQ
18016 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18017 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18018 A = DAG.getBitcast(MulVT, A);
18019 B = DAG.getBitcast(MulVT, B);
18020 Ahi = DAG.getBitcast(MulVT, Ahi);
18021 Bhi = DAG.getBitcast(MulVT, Bhi);
18023 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18024 // After shifting right const values the result may be all-zero.
18025 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18026 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18027 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18029 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18030 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18031 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18034 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18035 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18038 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18039 assert(Subtarget->isTargetWin64() && "Unexpected target");
18040 EVT VT = Op.getValueType();
18041 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18042 "Unexpected return type for lowering");
18046 switch (Op->getOpcode()) {
18047 default: llvm_unreachable("Unexpected request for libcall!");
18048 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18049 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18050 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18051 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18052 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18053 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18057 SDValue InChain = DAG.getEntryNode();
18059 TargetLowering::ArgListTy Args;
18060 TargetLowering::ArgListEntry Entry;
18061 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18062 EVT ArgVT = Op->getOperand(i).getValueType();
18063 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18064 "Unexpected argument type for lowering");
18065 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18066 Entry.Node = StackPtr;
18067 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18069 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18070 Entry.Ty = PointerType::get(ArgTy,0);
18071 Entry.isSExt = false;
18072 Entry.isZExt = false;
18073 Args.push_back(Entry);
18076 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18077 getPointerTy(DAG.getDataLayout()));
18079 TargetLowering::CallLoweringInfo CLI(DAG);
18080 CLI.setDebugLoc(dl).setChain(InChain)
18081 .setCallee(getLibcallCallingConv(LC),
18082 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18083 Callee, std::move(Args), 0)
18084 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18086 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18087 return DAG.getBitcast(VT, CallInfo.first);
18090 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18091 SelectionDAG &DAG) {
18092 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18093 MVT VT = Op0.getSimpleValueType();
18096 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18097 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18099 // PMULxD operations multiply each even value (starting at 0) of LHS with
18100 // the related value of RHS and produce a widen result.
18101 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18102 // => <2 x i64> <ae|cg>
18104 // In other word, to have all the results, we need to perform two PMULxD:
18105 // 1. one with the even values.
18106 // 2. one with the odd values.
18107 // To achieve #2, with need to place the odd values at an even position.
18109 // Place the odd value at an even position (basically, shift all values 1
18110 // step to the left):
18111 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18112 // <a|b|c|d> => <b|undef|d|undef>
18113 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18114 // <e|f|g|h> => <f|undef|h|undef>
18115 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18117 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18119 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18120 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18122 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18123 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18124 // => <2 x i64> <ae|cg>
18125 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18126 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18127 // => <2 x i64> <bf|dh>
18128 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18130 // Shuffle it back into the right order.
18131 SDValue Highs, Lows;
18132 if (VT == MVT::v8i32) {
18133 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18134 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18135 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18136 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18138 const int HighMask[] = {1, 5, 3, 7};
18139 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18140 const int LowMask[] = {0, 4, 2, 6};
18141 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18144 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18145 // unsigned multiply.
18146 if (IsSigned && !Subtarget->hasSSE41()) {
18147 SDValue ShAmt = DAG.getConstant(
18149 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18150 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18151 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18152 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18153 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18155 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18156 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18159 // The first result of MUL_LOHI is actually the low value, followed by the
18161 SDValue Ops[] = {Lows, Highs};
18162 return DAG.getMergeValues(Ops, dl);
18165 // Return true if the required (according to Opcode) shift-imm form is natively
18166 // supported by the Subtarget
18167 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18169 if (VT.getScalarSizeInBits() < 16)
18172 if (VT.is512BitVector() &&
18173 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18176 bool LShift = VT.is128BitVector() ||
18177 (VT.is256BitVector() && Subtarget->hasInt256());
18179 bool AShift = LShift && (Subtarget->hasVLX() ||
18180 (VT != MVT::v2i64 && VT != MVT::v4i64));
18181 return (Opcode == ISD::SRA) ? AShift : LShift;
18184 // The shift amount is a variable, but it is the same for all vector lanes.
18185 // These instructions are defined together with shift-immediate.
18187 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18189 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18192 // Return true if the required (according to Opcode) variable-shift form is
18193 // natively supported by the Subtarget
18194 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18197 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18200 // vXi16 supported only on AVX-512, BWI
18201 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18204 if (VT.is512BitVector() || Subtarget->hasVLX())
18207 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18208 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18209 return (Opcode == ISD::SRA) ? AShift : LShift;
18212 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18213 const X86Subtarget *Subtarget) {
18214 MVT VT = Op.getSimpleValueType();
18216 SDValue R = Op.getOperand(0);
18217 SDValue Amt = Op.getOperand(1);
18219 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18220 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18222 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18223 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18224 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18225 SDValue Ex = DAG.getBitcast(ExVT, R);
18227 if (ShiftAmt >= 32) {
18228 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18230 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18231 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18232 ShiftAmt - 32, DAG);
18233 if (VT == MVT::v2i64)
18234 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18235 if (VT == MVT::v4i64)
18236 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18237 {9, 1, 11, 3, 13, 5, 15, 7});
18239 // SRA upper i32, SHL whole i64 and select lower i32.
18240 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18243 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18244 Lower = DAG.getBitcast(ExVT, Lower);
18245 if (VT == MVT::v2i64)
18246 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18247 if (VT == MVT::v4i64)
18248 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18249 {8, 1, 10, 3, 12, 5, 14, 7});
18251 return DAG.getBitcast(VT, Ex);
18254 // Optimize shl/srl/sra with constant shift amount.
18255 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18256 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18257 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18259 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18260 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18262 // i64 SRA needs to be performed as partial shifts.
18263 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18264 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18265 return ArithmeticShiftRight64(ShiftAmt);
18267 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18268 unsigned NumElts = VT.getVectorNumElements();
18269 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18271 // Simple i8 add case
18272 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18273 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18275 // ashr(R, 7) === cmp_slt(R, 0)
18276 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18277 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18278 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18281 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18282 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18285 if (Op.getOpcode() == ISD::SHL) {
18286 // Make a large shift.
18287 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18289 SHL = DAG.getBitcast(VT, SHL);
18290 // Zero out the rightmost bits.
18291 SmallVector<SDValue, 32> V(
18292 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18293 return DAG.getNode(ISD::AND, dl, VT, SHL,
18294 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18296 if (Op.getOpcode() == ISD::SRL) {
18297 // Make a large shift.
18298 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18300 SRL = DAG.getBitcast(VT, SRL);
18301 // Zero out the leftmost bits.
18302 SmallVector<SDValue, 32> V(
18303 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18304 return DAG.getNode(ISD::AND, dl, VT, SRL,
18305 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18307 if (Op.getOpcode() == ISD::SRA) {
18308 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18309 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18310 SmallVector<SDValue, 32> V(NumElts,
18311 DAG.getConstant(128 >> ShiftAmt, dl,
18313 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18314 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18315 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18318 llvm_unreachable("Unknown shift opcode.");
18323 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18324 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18325 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18327 // Peek through any splat that was introduced for i64 shift vectorization.
18328 int SplatIndex = -1;
18329 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18330 if (SVN->isSplat()) {
18331 SplatIndex = SVN->getSplatIndex();
18332 Amt = Amt.getOperand(0);
18333 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18334 "Splat shuffle referencing second operand");
18337 if (Amt.getOpcode() != ISD::BITCAST ||
18338 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18341 Amt = Amt.getOperand(0);
18342 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18343 VT.getVectorNumElements();
18344 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18345 uint64_t ShiftAmt = 0;
18346 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18347 for (unsigned i = 0; i != Ratio; ++i) {
18348 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18352 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18355 // Check remaining shift amounts (if not a splat).
18356 if (SplatIndex < 0) {
18357 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18358 uint64_t ShAmt = 0;
18359 for (unsigned j = 0; j != Ratio; ++j) {
18360 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18364 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18366 if (ShAmt != ShiftAmt)
18371 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18372 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18374 if (Op.getOpcode() == ISD::SRA)
18375 return ArithmeticShiftRight64(ShiftAmt);
18381 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18382 const X86Subtarget* Subtarget) {
18383 MVT VT = Op.getSimpleValueType();
18385 SDValue R = Op.getOperand(0);
18386 SDValue Amt = Op.getOperand(1);
18388 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18389 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18391 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18392 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18394 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18396 MVT EltVT = VT.getVectorElementType();
18398 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18399 // Check if this build_vector node is doing a splat.
18400 // If so, then set BaseShAmt equal to the splat value.
18401 BaseShAmt = BV->getSplatValue();
18402 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18403 BaseShAmt = SDValue();
18405 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18406 Amt = Amt.getOperand(0);
18408 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18409 if (SVN && SVN->isSplat()) {
18410 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18411 SDValue InVec = Amt.getOperand(0);
18412 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18413 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18414 "Unexpected shuffle index found!");
18415 BaseShAmt = InVec.getOperand(SplatIdx);
18416 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18417 if (ConstantSDNode *C =
18418 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18419 if (C->getZExtValue() == SplatIdx)
18420 BaseShAmt = InVec.getOperand(1);
18425 // Avoid introducing an extract element from a shuffle.
18426 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18427 DAG.getIntPtrConstant(SplatIdx, dl));
18431 if (BaseShAmt.getNode()) {
18432 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18433 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18434 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18435 else if (EltVT.bitsLT(MVT::i32))
18436 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18438 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18442 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18443 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18444 Amt.getOpcode() == ISD::BITCAST &&
18445 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18446 Amt = Amt.getOperand(0);
18447 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18448 VT.getVectorNumElements();
18449 std::vector<SDValue> Vals(Ratio);
18450 for (unsigned i = 0; i != Ratio; ++i)
18451 Vals[i] = Amt.getOperand(i);
18452 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18453 for (unsigned j = 0; j != Ratio; ++j)
18454 if (Vals[j] != Amt.getOperand(i + j))
18458 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18459 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18464 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18465 SelectionDAG &DAG) {
18466 MVT VT = Op.getSimpleValueType();
18468 SDValue R = Op.getOperand(0);
18469 SDValue Amt = Op.getOperand(1);
18471 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18472 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18474 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18477 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18480 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18483 // XOP has 128-bit variable logical/arithmetic shifts.
18484 // +ve/-ve Amt = shift left/right.
18485 if (Subtarget->hasXOP() &&
18486 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18487 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18488 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18489 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18490 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18492 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18493 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18494 if (Op.getOpcode() == ISD::SRA)
18495 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18498 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18499 // shifts per-lane and then shuffle the partial results back together.
18500 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18501 // Splat the shift amounts so the scalar shifts above will catch it.
18502 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18503 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18504 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18505 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18506 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18509 // i64 vector arithmetic shift can be emulated with the transform:
18510 // M = lshr(SIGN_BIT, Amt)
18511 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18512 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18513 Op.getOpcode() == ISD::SRA) {
18514 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18515 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18516 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18517 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18518 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18522 // If possible, lower this packed shift into a vector multiply instead of
18523 // expanding it into a sequence of scalar shifts.
18524 // Do this only if the vector shift count is a constant build_vector.
18525 if (Op.getOpcode() == ISD::SHL &&
18526 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18527 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18528 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18529 SmallVector<SDValue, 8> Elts;
18530 MVT SVT = VT.getVectorElementType();
18531 unsigned SVTBits = SVT.getSizeInBits();
18532 APInt One(SVTBits, 1);
18533 unsigned NumElems = VT.getVectorNumElements();
18535 for (unsigned i=0; i !=NumElems; ++i) {
18536 SDValue Op = Amt->getOperand(i);
18537 if (Op->getOpcode() == ISD::UNDEF) {
18538 Elts.push_back(Op);
18542 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18543 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18544 uint64_t ShAmt = C.getZExtValue();
18545 if (ShAmt >= SVTBits) {
18546 Elts.push_back(DAG.getUNDEF(SVT));
18549 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18551 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18552 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18555 // Lower SHL with variable shift amount.
18556 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18557 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18559 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18560 DAG.getConstant(0x3f800000U, dl, VT));
18561 Op = DAG.getBitcast(MVT::v4f32, Op);
18562 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18563 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18566 // If possible, lower this shift as a sequence of two shifts by
18567 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18569 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18571 // Could be rewritten as:
18572 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18574 // The advantage is that the two shifts from the example would be
18575 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18576 // the vector shift into four scalar shifts plus four pairs of vector
18578 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18579 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18580 unsigned TargetOpcode = X86ISD::MOVSS;
18581 bool CanBeSimplified;
18582 // The splat value for the first packed shift (the 'X' from the example).
18583 SDValue Amt1 = Amt->getOperand(0);
18584 // The splat value for the second packed shift (the 'Y' from the example).
18585 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18586 Amt->getOperand(2);
18588 // See if it is possible to replace this node with a sequence of
18589 // two shifts followed by a MOVSS/MOVSD
18590 if (VT == MVT::v4i32) {
18591 // Check if it is legal to use a MOVSS.
18592 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18593 Amt2 == Amt->getOperand(3);
18594 if (!CanBeSimplified) {
18595 // Otherwise, check if we can still simplify this node using a MOVSD.
18596 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18597 Amt->getOperand(2) == Amt->getOperand(3);
18598 TargetOpcode = X86ISD::MOVSD;
18599 Amt2 = Amt->getOperand(2);
18602 // Do similar checks for the case where the machine value type
18604 CanBeSimplified = Amt1 == Amt->getOperand(1);
18605 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18606 CanBeSimplified = Amt2 == Amt->getOperand(i);
18608 if (!CanBeSimplified) {
18609 TargetOpcode = X86ISD::MOVSD;
18610 CanBeSimplified = true;
18611 Amt2 = Amt->getOperand(4);
18612 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18613 CanBeSimplified = Amt1 == Amt->getOperand(i);
18614 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18615 CanBeSimplified = Amt2 == Amt->getOperand(j);
18619 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18620 isa<ConstantSDNode>(Amt2)) {
18621 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18622 MVT CastVT = MVT::v4i32;
18624 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18625 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18627 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18628 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18629 if (TargetOpcode == X86ISD::MOVSD)
18630 CastVT = MVT::v2i64;
18631 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18632 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18633 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18635 return DAG.getBitcast(VT, Result);
18639 // v4i32 Non Uniform Shifts.
18640 // If the shift amount is constant we can shift each lane using the SSE2
18641 // immediate shifts, else we need to zero-extend each lane to the lower i64
18642 // and shift using the SSE2 variable shifts.
18643 // The separate results can then be blended together.
18644 if (VT == MVT::v4i32) {
18645 unsigned Opc = Op.getOpcode();
18646 SDValue Amt0, Amt1, Amt2, Amt3;
18647 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18648 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18649 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18650 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18651 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18653 // ISD::SHL is handled above but we include it here for completeness.
18656 llvm_unreachable("Unknown target vector shift node");
18658 Opc = X86ISD::VSHL;
18661 Opc = X86ISD::VSRL;
18664 Opc = X86ISD::VSRA;
18667 // The SSE2 shifts use the lower i64 as the same shift amount for
18668 // all lanes and the upper i64 is ignored. These shuffle masks
18669 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18670 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18671 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18672 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18673 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18674 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18677 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18678 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18679 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18680 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18681 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18682 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18683 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18686 if (VT == MVT::v16i8 ||
18687 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18688 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18689 unsigned ShiftOpcode = Op->getOpcode();
18691 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18692 // On SSE41 targets we make use of the fact that VSELECT lowers
18693 // to PBLENDVB which selects bytes based just on the sign bit.
18694 if (Subtarget->hasSSE41()) {
18695 V0 = DAG.getBitcast(VT, V0);
18696 V1 = DAG.getBitcast(VT, V1);
18697 Sel = DAG.getBitcast(VT, Sel);
18698 return DAG.getBitcast(SelVT,
18699 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18701 // On pre-SSE41 targets we test for the sign bit by comparing to
18702 // zero - a negative value will set all bits of the lanes to true
18703 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18704 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18705 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18706 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18709 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18710 // We can safely do this using i16 shifts as we're only interested in
18711 // the 3 lower bits of each byte.
18712 Amt = DAG.getBitcast(ExtVT, Amt);
18713 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18714 Amt = DAG.getBitcast(VT, Amt);
18716 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18717 // r = VSELECT(r, shift(r, 4), a);
18719 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18720 R = SignBitSelect(VT, Amt, M, R);
18723 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18725 // r = VSELECT(r, shift(r, 2), a);
18726 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18727 R = SignBitSelect(VT, Amt, M, R);
18730 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18732 // return VSELECT(r, shift(r, 1), a);
18733 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18734 R = SignBitSelect(VT, Amt, M, R);
18738 if (Op->getOpcode() == ISD::SRA) {
18739 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18740 // so we can correctly sign extend. We don't care what happens to the
18742 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18743 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18744 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18745 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18746 ALo = DAG.getBitcast(ExtVT, ALo);
18747 AHi = DAG.getBitcast(ExtVT, AHi);
18748 RLo = DAG.getBitcast(ExtVT, RLo);
18749 RHi = DAG.getBitcast(ExtVT, RHi);
18751 // r = VSELECT(r, shift(r, 4), a);
18752 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18753 DAG.getConstant(4, dl, ExtVT));
18754 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18755 DAG.getConstant(4, dl, ExtVT));
18756 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18757 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18760 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18761 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18763 // r = VSELECT(r, shift(r, 2), a);
18764 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18765 DAG.getConstant(2, dl, ExtVT));
18766 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18767 DAG.getConstant(2, dl, ExtVT));
18768 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18769 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18772 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18773 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18775 // r = VSELECT(r, shift(r, 1), a);
18776 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18777 DAG.getConstant(1, dl, ExtVT));
18778 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18779 DAG.getConstant(1, dl, ExtVT));
18780 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18781 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18783 // Logical shift the result back to the lower byte, leaving a zero upper
18785 // meaning that we can safely pack with PACKUSWB.
18787 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18789 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18790 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18794 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18795 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18796 // solution better.
18797 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18798 MVT ExtVT = MVT::v8i32;
18800 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18801 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18802 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18803 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18804 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18807 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18808 MVT ExtVT = MVT::v8i32;
18809 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18810 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18811 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18812 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18813 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18814 ALo = DAG.getBitcast(ExtVT, ALo);
18815 AHi = DAG.getBitcast(ExtVT, AHi);
18816 RLo = DAG.getBitcast(ExtVT, RLo);
18817 RHi = DAG.getBitcast(ExtVT, RHi);
18818 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18819 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18820 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18821 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18822 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18825 if (VT == MVT::v8i16) {
18826 unsigned ShiftOpcode = Op->getOpcode();
18828 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18829 // On SSE41 targets we make use of the fact that VSELECT lowers
18830 // to PBLENDVB which selects bytes based just on the sign bit.
18831 if (Subtarget->hasSSE41()) {
18832 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18833 V0 = DAG.getBitcast(ExtVT, V0);
18834 V1 = DAG.getBitcast(ExtVT, V1);
18835 Sel = DAG.getBitcast(ExtVT, Sel);
18836 return DAG.getBitcast(
18837 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18839 // On pre-SSE41 targets we splat the sign bit - a negative value will
18840 // set all bits of the lanes to true and VSELECT uses that in
18841 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18843 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18844 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18847 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18848 if (Subtarget->hasSSE41()) {
18849 // On SSE41 targets we need to replicate the shift mask in both
18850 // bytes for PBLENDVB.
18853 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18854 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18856 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18859 // r = VSELECT(r, shift(r, 8), a);
18860 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18861 R = SignBitSelect(Amt, M, R);
18864 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18866 // r = VSELECT(r, shift(r, 4), a);
18867 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18868 R = SignBitSelect(Amt, M, R);
18871 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18873 // r = VSELECT(r, shift(r, 2), a);
18874 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18875 R = SignBitSelect(Amt, M, R);
18878 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18880 // return VSELECT(r, shift(r, 1), a);
18881 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18882 R = SignBitSelect(Amt, M, R);
18886 // Decompose 256-bit shifts into smaller 128-bit shifts.
18887 if (VT.is256BitVector()) {
18888 unsigned NumElems = VT.getVectorNumElements();
18889 MVT EltVT = VT.getVectorElementType();
18890 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18892 // Extract the two vectors
18893 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18894 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18896 // Recreate the shift amount vectors
18897 SDValue Amt1, Amt2;
18898 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18899 // Constant shift amount
18900 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18901 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18902 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18904 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18905 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18907 // Variable shift amount
18908 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18909 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18912 // Issue new vector shifts for the smaller types
18913 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18914 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18916 // Concatenate the result back
18917 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18923 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18924 SelectionDAG &DAG) {
18925 MVT VT = Op.getSimpleValueType();
18927 SDValue R = Op.getOperand(0);
18928 SDValue Amt = Op.getOperand(1);
18930 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18931 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18932 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18934 // XOP has 128-bit vector variable + immediate rotates.
18935 // +ve/-ve Amt = rotate left/right.
18937 // Split 256-bit integers.
18938 if (VT.is256BitVector())
18939 return Lower256IntArith(Op, DAG);
18941 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18943 // Attempt to rotate by immediate.
18944 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18945 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18946 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18947 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18948 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18949 DAG.getConstant(RotateAmt, DL, MVT::i8));
18953 // Use general rotate by variable (per-element).
18954 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18957 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18958 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18959 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18960 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18961 // has only one use.
18962 SDNode *N = Op.getNode();
18963 SDValue LHS = N->getOperand(0);
18964 SDValue RHS = N->getOperand(1);
18965 unsigned BaseOp = 0;
18968 switch (Op.getOpcode()) {
18969 default: llvm_unreachable("Unknown ovf instruction!");
18971 // A subtract of one will be selected as a INC. Note that INC doesn't
18972 // set CF, so we can't do this for UADDO.
18973 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18975 BaseOp = X86ISD::INC;
18976 Cond = X86::COND_O;
18979 BaseOp = X86ISD::ADD;
18980 Cond = X86::COND_O;
18983 BaseOp = X86ISD::ADD;
18984 Cond = X86::COND_B;
18987 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18988 // set CF, so we can't do this for USUBO.
18989 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18991 BaseOp = X86ISD::DEC;
18992 Cond = X86::COND_O;
18995 BaseOp = X86ISD::SUB;
18996 Cond = X86::COND_O;
18999 BaseOp = X86ISD::SUB;
19000 Cond = X86::COND_B;
19003 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19004 Cond = X86::COND_O;
19006 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19007 if (N->getValueType(0) == MVT::i8) {
19008 BaseOp = X86ISD::UMUL8;
19009 Cond = X86::COND_O;
19012 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19014 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19017 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19018 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19019 SDValue(Sum.getNode(), 2));
19021 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19025 // Also sets EFLAGS.
19026 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19027 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19030 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19031 DAG.getConstant(Cond, DL, MVT::i32),
19032 SDValue(Sum.getNode(), 1));
19034 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19037 /// Returns true if the operand type is exactly twice the native width, and
19038 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19039 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19040 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19041 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19042 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19045 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19046 else if (OpWidth == 128)
19047 return Subtarget->hasCmpxchg16b();
19052 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19053 return needsCmpXchgNb(SI->getValueOperand()->getType());
19056 // Note: this turns large loads into lock cmpxchg8b/16b.
19057 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19058 TargetLowering::AtomicExpansionKind
19059 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19060 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19061 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19062 : AtomicExpansionKind::None;
19065 TargetLowering::AtomicExpansionKind
19066 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19067 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19068 Type *MemType = AI->getType();
19070 // If the operand is too big, we must see if cmpxchg8/16b is available
19071 // and default to library calls otherwise.
19072 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19073 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19074 : AtomicExpansionKind::None;
19077 AtomicRMWInst::BinOp Op = AI->getOperation();
19080 llvm_unreachable("Unknown atomic operation");
19081 case AtomicRMWInst::Xchg:
19082 case AtomicRMWInst::Add:
19083 case AtomicRMWInst::Sub:
19084 // It's better to use xadd, xsub or xchg for these in all cases.
19085 return AtomicExpansionKind::None;
19086 case AtomicRMWInst::Or:
19087 case AtomicRMWInst::And:
19088 case AtomicRMWInst::Xor:
19089 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19090 // prefix to a normal instruction for these operations.
19091 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19092 : AtomicExpansionKind::None;
19093 case AtomicRMWInst::Nand:
19094 case AtomicRMWInst::Max:
19095 case AtomicRMWInst::Min:
19096 case AtomicRMWInst::UMax:
19097 case AtomicRMWInst::UMin:
19098 // These always require a non-trivial set of data operations on x86. We must
19099 // use a cmpxchg loop.
19100 return AtomicExpansionKind::CmpXChg;
19104 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19105 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19106 // no-sse2). There isn't any reason to disable it if the target processor
19108 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19112 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19113 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19114 Type *MemType = AI->getType();
19115 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19116 // there is no benefit in turning such RMWs into loads, and it is actually
19117 // harmful as it introduces a mfence.
19118 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19121 auto Builder = IRBuilder<>(AI);
19122 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19123 auto SynchScope = AI->getSynchScope();
19124 // We must restrict the ordering to avoid generating loads with Release or
19125 // ReleaseAcquire orderings.
19126 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19127 auto Ptr = AI->getPointerOperand();
19129 // Before the load we need a fence. Here is an example lifted from
19130 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19133 // x.store(1, relaxed);
19134 // r1 = y.fetch_add(0, release);
19136 // y.fetch_add(42, acquire);
19137 // r2 = x.load(relaxed);
19138 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19139 // lowered to just a load without a fence. A mfence flushes the store buffer,
19140 // making the optimization clearly correct.
19141 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19142 // otherwise, we might be able to be more aggressive on relaxed idempotent
19143 // rmw. In practice, they do not look useful, so we don't try to be
19144 // especially clever.
19145 if (SynchScope == SingleThread)
19146 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19147 // the IR level, so we must wrap it in an intrinsic.
19150 if (!hasMFENCE(*Subtarget))
19151 // FIXME: it might make sense to use a locked operation here but on a
19152 // different cache-line to prevent cache-line bouncing. In practice it
19153 // is probably a small win, and x86 processors without mfence are rare
19154 // enough that we do not bother.
19158 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19159 Builder.CreateCall(MFence, {});
19161 // Finally we can emit the atomic load.
19162 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19163 AI->getType()->getPrimitiveSizeInBits());
19164 Loaded->setAtomic(Order, SynchScope);
19165 AI->replaceAllUsesWith(Loaded);
19166 AI->eraseFromParent();
19170 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19171 SelectionDAG &DAG) {
19173 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19174 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19175 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19176 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19178 // The only fence that needs an instruction is a sequentially-consistent
19179 // cross-thread fence.
19180 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19181 if (hasMFENCE(*Subtarget))
19182 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19184 SDValue Chain = Op.getOperand(0);
19185 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19187 DAG.getRegister(X86::ESP, MVT::i32), // Base
19188 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19189 DAG.getRegister(0, MVT::i32), // Index
19190 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19191 DAG.getRegister(0, MVT::i32), // Segment.
19195 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19196 return SDValue(Res, 0);
19199 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19200 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19203 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19204 SelectionDAG &DAG) {
19205 MVT T = Op.getSimpleValueType();
19209 switch(T.SimpleTy) {
19210 default: llvm_unreachable("Invalid value type!");
19211 case MVT::i8: Reg = X86::AL; size = 1; break;
19212 case MVT::i16: Reg = X86::AX; size = 2; break;
19213 case MVT::i32: Reg = X86::EAX; size = 4; break;
19215 assert(Subtarget->is64Bit() && "Node not type legal!");
19216 Reg = X86::RAX; size = 8;
19219 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19220 Op.getOperand(2), SDValue());
19221 SDValue Ops[] = { cpIn.getValue(0),
19224 DAG.getTargetConstant(size, DL, MVT::i8),
19225 cpIn.getValue(1) };
19226 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19227 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19228 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19232 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19233 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19234 MVT::i32, cpOut.getValue(2));
19235 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19236 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19239 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19240 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19241 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19245 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19246 SelectionDAG &DAG) {
19247 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19248 MVT DstVT = Op.getSimpleValueType();
19250 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19251 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19252 if (DstVT != MVT::f64)
19253 // This conversion needs to be expanded.
19256 SDValue InVec = Op->getOperand(0);
19258 unsigned NumElts = SrcVT.getVectorNumElements();
19259 MVT SVT = SrcVT.getVectorElementType();
19261 // Widen the vector in input in the case of MVT::v2i32.
19262 // Example: from MVT::v2i32 to MVT::v4i32.
19263 SmallVector<SDValue, 16> Elts;
19264 for (unsigned i = 0, e = NumElts; i != e; ++i)
19265 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19266 DAG.getIntPtrConstant(i, dl)));
19268 // Explicitly mark the extra elements as Undef.
19269 Elts.append(NumElts, DAG.getUNDEF(SVT));
19271 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19272 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19273 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19274 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19275 DAG.getIntPtrConstant(0, dl));
19278 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19279 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19280 assert((DstVT == MVT::i64 ||
19281 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19282 "Unexpected custom BITCAST");
19283 // i64 <=> MMX conversions are Legal.
19284 if (SrcVT==MVT::i64 && DstVT.isVector())
19286 if (DstVT==MVT::i64 && SrcVT.isVector())
19288 // MMX <=> MMX conversions are Legal.
19289 if (SrcVT.isVector() && DstVT.isVector())
19291 // All other conversions need to be expanded.
19295 /// Compute the horizontal sum of bytes in V for the elements of VT.
19297 /// Requires V to be a byte vector and VT to be an integer vector type with
19298 /// wider elements than V's type. The width of the elements of VT determines
19299 /// how many bytes of V are summed horizontally to produce each element of the
19301 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19302 const X86Subtarget *Subtarget,
19303 SelectionDAG &DAG) {
19305 MVT ByteVecVT = V.getSimpleValueType();
19306 MVT EltVT = VT.getVectorElementType();
19307 int NumElts = VT.getVectorNumElements();
19308 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19309 "Expected value to have byte element type.");
19310 assert(EltVT != MVT::i8 &&
19311 "Horizontal byte sum only makes sense for wider elements!");
19312 unsigned VecSize = VT.getSizeInBits();
19313 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19315 // PSADBW instruction horizontally add all bytes and leave the result in i64
19316 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19317 if (EltVT == MVT::i64) {
19318 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19319 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19320 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19321 return DAG.getBitcast(VT, V);
19324 if (EltVT == MVT::i32) {
19325 // We unpack the low half and high half into i32s interleaved with zeros so
19326 // that we can use PSADBW to horizontally sum them. The most useful part of
19327 // this is that it lines up the results of two PSADBW instructions to be
19328 // two v2i64 vectors which concatenated are the 4 population counts. We can
19329 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19330 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19331 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19332 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19334 // Do the horizontal sums into two v2i64s.
19335 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19336 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19337 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19338 DAG.getBitcast(ByteVecVT, Low), Zeros);
19339 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19340 DAG.getBitcast(ByteVecVT, High), Zeros);
19342 // Merge them together.
19343 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19344 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19345 DAG.getBitcast(ShortVecVT, Low),
19346 DAG.getBitcast(ShortVecVT, High));
19348 return DAG.getBitcast(VT, V);
19351 // The only element type left is i16.
19352 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19354 // To obtain pop count for each i16 element starting from the pop count for
19355 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19356 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19357 // directly supported.
19358 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19359 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19360 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19361 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19362 DAG.getBitcast(ByteVecVT, V));
19363 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19366 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19367 const X86Subtarget *Subtarget,
19368 SelectionDAG &DAG) {
19369 MVT VT = Op.getSimpleValueType();
19370 MVT EltVT = VT.getVectorElementType();
19371 unsigned VecSize = VT.getSizeInBits();
19373 // Implement a lookup table in register by using an algorithm based on:
19374 // http://wm.ite.pl/articles/sse-popcount.html
19376 // The general idea is that every lower byte nibble in the input vector is an
19377 // index into a in-register pre-computed pop count table. We then split up the
19378 // input vector in two new ones: (1) a vector with only the shifted-right
19379 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19380 // masked out higher ones) for each byte. PSHUB is used separately with both
19381 // to index the in-register table. Next, both are added and the result is a
19382 // i8 vector where each element contains the pop count for input byte.
19384 // To obtain the pop count for elements != i8, we follow up with the same
19385 // approach and use additional tricks as described below.
19387 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19388 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19389 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19390 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19392 int NumByteElts = VecSize / 8;
19393 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19394 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19395 SmallVector<SDValue, 16> LUTVec;
19396 for (int i = 0; i < NumByteElts; ++i)
19397 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19398 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19399 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19400 DAG.getConstant(0x0F, DL, MVT::i8));
19401 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19404 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19405 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19406 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19409 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19411 // The input vector is used as the shuffle mask that index elements into the
19412 // LUT. After counting low and high nibbles, add the vector to obtain the
19413 // final pop count per i8 element.
19414 SDValue HighPopCnt =
19415 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19416 SDValue LowPopCnt =
19417 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19418 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19420 if (EltVT == MVT::i8)
19423 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19426 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19427 const X86Subtarget *Subtarget,
19428 SelectionDAG &DAG) {
19429 MVT VT = Op.getSimpleValueType();
19430 assert(VT.is128BitVector() &&
19431 "Only 128-bit vector bitmath lowering supported.");
19433 int VecSize = VT.getSizeInBits();
19434 MVT EltVT = VT.getVectorElementType();
19435 int Len = EltVT.getSizeInBits();
19437 // This is the vectorized version of the "best" algorithm from
19438 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19439 // with a minor tweak to use a series of adds + shifts instead of vector
19440 // multiplications. Implemented for all integer vector types. We only use
19441 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19442 // much faster, even faster than using native popcnt instructions.
19444 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19445 MVT VT = V.getSimpleValueType();
19446 SmallVector<SDValue, 32> Shifters(
19447 VT.getVectorNumElements(),
19448 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19449 return DAG.getNode(OpCode, DL, VT, V,
19450 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19452 auto GetMask = [&](SDValue V, APInt Mask) {
19453 MVT VT = V.getSimpleValueType();
19454 SmallVector<SDValue, 32> Masks(
19455 VT.getVectorNumElements(),
19456 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19457 return DAG.getNode(ISD::AND, DL, VT, V,
19458 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19461 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19462 // x86, so set the SRL type to have elements at least i16 wide. This is
19463 // correct because all of our SRLs are followed immediately by a mask anyways
19464 // that handles any bits that sneak into the high bits of the byte elements.
19465 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19469 // v = v - ((v >> 1) & 0x55555555...)
19471 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19472 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19473 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19475 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19476 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19477 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19478 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19479 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19481 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19482 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19483 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19484 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19486 // At this point, V contains the byte-wise population count, and we are
19487 // merely doing a horizontal sum if necessary to get the wider element
19489 if (EltVT == MVT::i8)
19492 return LowerHorizontalByteSum(
19493 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19497 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19498 SelectionDAG &DAG) {
19499 MVT VT = Op.getSimpleValueType();
19500 // FIXME: Need to add AVX-512 support here!
19501 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19502 "Unknown CTPOP type to handle");
19503 SDLoc DL(Op.getNode());
19504 SDValue Op0 = Op.getOperand(0);
19506 if (!Subtarget->hasSSSE3()) {
19507 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19508 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19509 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19512 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19513 unsigned NumElems = VT.getVectorNumElements();
19515 // Extract each 128-bit vector, compute pop count and concat the result.
19516 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19517 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19519 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19520 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19521 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19524 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19527 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19528 SelectionDAG &DAG) {
19529 assert(Op.getSimpleValueType().isVector() &&
19530 "We only do custom lowering for vector population count.");
19531 return LowerVectorCTPOP(Op, Subtarget, DAG);
19534 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19535 SDNode *Node = Op.getNode();
19537 EVT T = Node->getValueType(0);
19538 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19539 DAG.getConstant(0, dl, T), Node->getOperand(2));
19540 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19541 cast<AtomicSDNode>(Node)->getMemoryVT(),
19542 Node->getOperand(0),
19543 Node->getOperand(1), negOp,
19544 cast<AtomicSDNode>(Node)->getMemOperand(),
19545 cast<AtomicSDNode>(Node)->getOrdering(),
19546 cast<AtomicSDNode>(Node)->getSynchScope());
19549 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19550 SDNode *Node = Op.getNode();
19552 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19554 // Convert seq_cst store -> xchg
19555 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19556 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19557 // (The only way to get a 16-byte store is cmpxchg16b)
19558 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19559 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19560 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19561 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19562 cast<AtomicSDNode>(Node)->getMemoryVT(),
19563 Node->getOperand(0),
19564 Node->getOperand(1), Node->getOperand(2),
19565 cast<AtomicSDNode>(Node)->getMemOperand(),
19566 cast<AtomicSDNode>(Node)->getOrdering(),
19567 cast<AtomicSDNode>(Node)->getSynchScope());
19568 return Swap.getValue(1);
19570 // Other atomic stores have a simple pattern.
19574 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19575 MVT VT = Op.getNode()->getSimpleValueType(0);
19577 // Let legalize expand this if it isn't a legal type yet.
19578 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19581 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19584 bool ExtraOp = false;
19585 switch (Op.getOpcode()) {
19586 default: llvm_unreachable("Invalid code");
19587 case ISD::ADDC: Opc = X86ISD::ADD; break;
19588 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19589 case ISD::SUBC: Opc = X86ISD::SUB; break;
19590 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19594 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19596 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19597 Op.getOperand(1), Op.getOperand(2));
19600 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19601 SelectionDAG &DAG) {
19602 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19604 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19605 // which returns the values as { float, float } (in XMM0) or
19606 // { double, double } (which is returned in XMM0, XMM1).
19608 SDValue Arg = Op.getOperand(0);
19609 EVT ArgVT = Arg.getValueType();
19610 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19612 TargetLowering::ArgListTy Args;
19613 TargetLowering::ArgListEntry Entry;
19617 Entry.isSExt = false;
19618 Entry.isZExt = false;
19619 Args.push_back(Entry);
19621 bool isF64 = ArgVT == MVT::f64;
19622 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19623 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19624 // the results are returned via SRet in memory.
19625 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19626 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19628 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19630 Type *RetTy = isF64
19631 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19632 : (Type*)VectorType::get(ArgTy, 4);
19634 TargetLowering::CallLoweringInfo CLI(DAG);
19635 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19636 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19638 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19641 // Returned in xmm0 and xmm1.
19642 return CallResult.first;
19644 // Returned in bits 0:31 and 32:64 xmm0.
19645 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19646 CallResult.first, DAG.getIntPtrConstant(0, dl));
19647 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19648 CallResult.first, DAG.getIntPtrConstant(1, dl));
19649 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19650 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19653 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19654 SelectionDAG &DAG) {
19655 assert(Subtarget->hasAVX512() &&
19656 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19658 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19659 MVT VT = N->getValue().getSimpleValueType();
19660 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19663 // X86 scatter kills mask register, so its type should be added to
19664 // the list of return values
19665 if (N->getNumValues() == 1) {
19666 SDValue Index = N->getIndex();
19667 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19668 !Index.getSimpleValueType().is512BitVector())
19669 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19671 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19672 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19673 N->getOperand(3), Index };
19675 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19676 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19677 return SDValue(NewScatter.getNode(), 0);
19682 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19683 SelectionDAG &DAG) {
19684 assert(Subtarget->hasAVX512() &&
19685 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19687 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19688 MVT VT = Op.getSimpleValueType();
19689 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19692 SDValue Index = N->getIndex();
19693 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19694 !Index.getSimpleValueType().is512BitVector()) {
19695 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19696 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19697 N->getOperand(3), Index };
19698 DAG.UpdateNodeOperands(N, Ops);
19703 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19704 SelectionDAG &DAG) const {
19705 // TODO: Eventually, the lowering of these nodes should be informed by or
19706 // deferred to the GC strategy for the function in which they appear. For
19707 // now, however, they must be lowered to something. Since they are logically
19708 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19709 // require special handling for these nodes), lower them as literal NOOPs for
19711 SmallVector<SDValue, 2> Ops;
19713 Ops.push_back(Op.getOperand(0));
19714 if (Op->getGluedNode())
19715 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19718 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19719 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19724 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19725 SelectionDAG &DAG) const {
19726 // TODO: Eventually, the lowering of these nodes should be informed by or
19727 // deferred to the GC strategy for the function in which they appear. For
19728 // now, however, they must be lowered to something. Since they are logically
19729 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19730 // require special handling for these nodes), lower them as literal NOOPs for
19732 SmallVector<SDValue, 2> Ops;
19734 Ops.push_back(Op.getOperand(0));
19735 if (Op->getGluedNode())
19736 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19739 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19740 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19745 /// LowerOperation - Provide custom lowering hooks for some operations.
19747 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19748 switch (Op.getOpcode()) {
19749 default: llvm_unreachable("Should not custom lower this!");
19750 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19751 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19752 return LowerCMP_SWAP(Op, Subtarget, DAG);
19753 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19754 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19755 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19756 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19757 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19758 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19759 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19760 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19761 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19762 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19763 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19764 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19765 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19766 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19767 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19768 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19769 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19770 case ISD::SHL_PARTS:
19771 case ISD::SRA_PARTS:
19772 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19773 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19774 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19775 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19776 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19777 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19778 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19779 case ISD::SIGN_EXTEND_VECTOR_INREG:
19780 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19781 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19782 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19783 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19784 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19786 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19787 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19788 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19789 case ISD::SETCC: return LowerSETCC(Op, DAG);
19790 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
19791 case ISD::SELECT: return LowerSELECT(Op, DAG);
19792 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19793 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19794 case ISD::VASTART: return LowerVASTART(Op, DAG);
19795 case ISD::VAARG: return LowerVAARG(Op, DAG);
19796 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19797 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19798 case ISD::INTRINSIC_VOID:
19799 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19800 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19801 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19802 case ISD::FRAME_TO_ARGS_OFFSET:
19803 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19804 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19805 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19806 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19807 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19808 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19809 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19810 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19811 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19812 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19814 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19815 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19816 case ISD::UMUL_LOHI:
19817 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19818 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19821 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19827 case ISD::UMULO: return LowerXALUO(Op, DAG);
19828 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19829 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19833 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19834 case ISD::ADD: return LowerADD(Op, DAG);
19835 case ISD::SUB: return LowerSUB(Op, DAG);
19839 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19840 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19841 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19842 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19843 case ISD::GC_TRANSITION_START:
19844 return LowerGC_TRANSITION_START(Op, DAG);
19845 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19849 /// ReplaceNodeResults - Replace a node with an illegal result type
19850 /// with a new node built out of custom code.
19851 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19852 SmallVectorImpl<SDValue>&Results,
19853 SelectionDAG &DAG) const {
19855 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19856 switch (N->getOpcode()) {
19858 llvm_unreachable("Do not know how to custom type legalize this operation!");
19859 case X86ISD::AVG: {
19860 // Legalize types for X86ISD::AVG by expanding vectors.
19861 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19863 auto InVT = N->getValueType(0);
19864 auto InVTSize = InVT.getSizeInBits();
19865 const unsigned RegSize =
19866 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
19867 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
19868 "512-bit vector requires AVX512");
19869 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
19870 "256-bit vector requires AVX2");
19872 auto ElemVT = InVT.getVectorElementType();
19873 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
19874 RegSize / ElemVT.getSizeInBits());
19875 assert(RegSize % InVT.getSizeInBits() == 0);
19876 unsigned NumConcat = RegSize / InVT.getSizeInBits();
19878 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
19879 Ops[0] = N->getOperand(0);
19880 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
19881 Ops[0] = N->getOperand(1);
19882 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
19884 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
19885 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
19886 DAG.getIntPtrConstant(0, dl)));
19889 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19890 case X86ISD::FMINC:
19892 case X86ISD::FMAXC:
19893 case X86ISD::FMAX: {
19894 EVT VT = N->getValueType(0);
19895 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
19896 SDValue UNDEF = DAG.getUNDEF(VT);
19897 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19898 N->getOperand(0), UNDEF);
19899 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19900 N->getOperand(1), UNDEF);
19901 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19904 case ISD::SIGN_EXTEND_INREG:
19909 // We don't want to expand or promote these.
19916 case ISD::UDIVREM: {
19917 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19918 Results.push_back(V);
19921 case ISD::FP_TO_SINT:
19922 case ISD::FP_TO_UINT: {
19923 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19925 std::pair<SDValue,SDValue> Vals =
19926 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19927 SDValue FIST = Vals.first, StackSlot = Vals.second;
19928 if (FIST.getNode()) {
19929 EVT VT = N->getValueType(0);
19930 // Return a load from the stack slot.
19931 if (StackSlot.getNode())
19932 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19933 MachinePointerInfo(),
19934 false, false, false, 0));
19936 Results.push_back(FIST);
19940 case ISD::UINT_TO_FP: {
19941 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19942 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19943 N->getValueType(0) != MVT::v2f32)
19945 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19947 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19949 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19950 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19951 DAG.getBitcast(MVT::v2i64, VBias));
19952 Or = DAG.getBitcast(MVT::v2f64, Or);
19953 // TODO: Are there any fast-math-flags to propagate here?
19954 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19955 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19958 case ISD::FP_ROUND: {
19959 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19961 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19962 Results.push_back(V);
19965 case ISD::FP_EXTEND: {
19966 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19967 // No other ValueType for FP_EXTEND should reach this point.
19968 assert(N->getValueType(0) == MVT::v2f32 &&
19969 "Do not know how to legalize this Node");
19972 case ISD::INTRINSIC_W_CHAIN: {
19973 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19975 default : llvm_unreachable("Do not know how to custom type "
19976 "legalize this intrinsic operation!");
19977 case Intrinsic::x86_rdtsc:
19978 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19980 case Intrinsic::x86_rdtscp:
19981 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19983 case Intrinsic::x86_rdpmc:
19984 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19987 case ISD::READCYCLECOUNTER: {
19988 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19991 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19992 EVT T = N->getValueType(0);
19993 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19994 bool Regs64bit = T == MVT::i128;
19995 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19996 SDValue cpInL, cpInH;
19997 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19998 DAG.getConstant(0, dl, HalfT));
19999 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20000 DAG.getConstant(1, dl, HalfT));
20001 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20002 Regs64bit ? X86::RAX : X86::EAX,
20004 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20005 Regs64bit ? X86::RDX : X86::EDX,
20006 cpInH, cpInL.getValue(1));
20007 SDValue swapInL, swapInH;
20008 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20009 DAG.getConstant(0, dl, HalfT));
20010 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20011 DAG.getConstant(1, dl, HalfT));
20012 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20013 Regs64bit ? X86::RBX : X86::EBX,
20014 swapInL, cpInH.getValue(1));
20015 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20016 Regs64bit ? X86::RCX : X86::ECX,
20017 swapInH, swapInL.getValue(1));
20018 SDValue Ops[] = { swapInH.getValue(0),
20020 swapInH.getValue(1) };
20021 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20022 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20023 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20024 X86ISD::LCMPXCHG8_DAG;
20025 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20026 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20027 Regs64bit ? X86::RAX : X86::EAX,
20028 HalfT, Result.getValue(1));
20029 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20030 Regs64bit ? X86::RDX : X86::EDX,
20031 HalfT, cpOutL.getValue(2));
20032 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20034 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20035 MVT::i32, cpOutH.getValue(2));
20037 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20038 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20039 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20041 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20042 Results.push_back(Success);
20043 Results.push_back(EFLAGS.getValue(1));
20046 case ISD::ATOMIC_SWAP:
20047 case ISD::ATOMIC_LOAD_ADD:
20048 case ISD::ATOMIC_LOAD_SUB:
20049 case ISD::ATOMIC_LOAD_AND:
20050 case ISD::ATOMIC_LOAD_OR:
20051 case ISD::ATOMIC_LOAD_XOR:
20052 case ISD::ATOMIC_LOAD_NAND:
20053 case ISD::ATOMIC_LOAD_MIN:
20054 case ISD::ATOMIC_LOAD_MAX:
20055 case ISD::ATOMIC_LOAD_UMIN:
20056 case ISD::ATOMIC_LOAD_UMAX:
20057 case ISD::ATOMIC_LOAD: {
20058 // Delegate to generic TypeLegalization. Situations we can really handle
20059 // should have already been dealt with by AtomicExpandPass.cpp.
20062 case ISD::BITCAST: {
20063 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20064 EVT DstVT = N->getValueType(0);
20065 EVT SrcVT = N->getOperand(0)->getValueType(0);
20067 if (SrcVT != MVT::f64 ||
20068 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20071 unsigned NumElts = DstVT.getVectorNumElements();
20072 EVT SVT = DstVT.getVectorElementType();
20073 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20074 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20075 MVT::v2f64, N->getOperand(0));
20076 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20078 if (ExperimentalVectorWideningLegalization) {
20079 // If we are legalizing vectors by widening, we already have the desired
20080 // legal vector type, just return it.
20081 Results.push_back(ToVecInt);
20085 SmallVector<SDValue, 8> Elts;
20086 for (unsigned i = 0, e = NumElts; i != e; ++i)
20087 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20088 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20090 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20095 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20096 switch ((X86ISD::NodeType)Opcode) {
20097 case X86ISD::FIRST_NUMBER: break;
20098 case X86ISD::BSF: return "X86ISD::BSF";
20099 case X86ISD::BSR: return "X86ISD::BSR";
20100 case X86ISD::SHLD: return "X86ISD::SHLD";
20101 case X86ISD::SHRD: return "X86ISD::SHRD";
20102 case X86ISD::FAND: return "X86ISD::FAND";
20103 case X86ISD::FANDN: return "X86ISD::FANDN";
20104 case X86ISD::FOR: return "X86ISD::FOR";
20105 case X86ISD::FXOR: return "X86ISD::FXOR";
20106 case X86ISD::FILD: return "X86ISD::FILD";
20107 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20108 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20109 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20110 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20111 case X86ISD::FLD: return "X86ISD::FLD";
20112 case X86ISD::FST: return "X86ISD::FST";
20113 case X86ISD::CALL: return "X86ISD::CALL";
20114 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20115 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20116 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20117 case X86ISD::BT: return "X86ISD::BT";
20118 case X86ISD::CMP: return "X86ISD::CMP";
20119 case X86ISD::COMI: return "X86ISD::COMI";
20120 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20121 case X86ISD::CMPM: return "X86ISD::CMPM";
20122 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20123 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20124 case X86ISD::SETCC: return "X86ISD::SETCC";
20125 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20126 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20127 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20128 case X86ISD::CMOV: return "X86ISD::CMOV";
20129 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20130 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20131 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20132 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20133 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20134 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20135 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20136 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20137 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20138 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20139 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20140 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20141 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20142 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20143 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20144 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20145 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20146 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20147 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20148 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20149 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20150 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20151 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20152 case X86ISD::HADD: return "X86ISD::HADD";
20153 case X86ISD::HSUB: return "X86ISD::HSUB";
20154 case X86ISD::FHADD: return "X86ISD::FHADD";
20155 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20156 case X86ISD::ABS: return "X86ISD::ABS";
20157 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20158 case X86ISD::FMAX: return "X86ISD::FMAX";
20159 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20160 case X86ISD::FMIN: return "X86ISD::FMIN";
20161 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20162 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20163 case X86ISD::FMINC: return "X86ISD::FMINC";
20164 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20165 case X86ISD::FRCP: return "X86ISD::FRCP";
20166 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20167 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20168 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20169 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20170 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20171 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20172 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20173 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20174 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20175 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20176 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20177 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20178 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20179 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20180 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20181 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20182 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20183 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20184 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20185 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20186 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20187 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20188 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20189 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20190 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20191 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20192 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20193 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20194 case X86ISD::VSHL: return "X86ISD::VSHL";
20195 case X86ISD::VSRL: return "X86ISD::VSRL";
20196 case X86ISD::VSRA: return "X86ISD::VSRA";
20197 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20198 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20199 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20200 case X86ISD::CMPP: return "X86ISD::CMPP";
20201 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20202 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20203 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20204 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20205 case X86ISD::ADD: return "X86ISD::ADD";
20206 case X86ISD::SUB: return "X86ISD::SUB";
20207 case X86ISD::ADC: return "X86ISD::ADC";
20208 case X86ISD::SBB: return "X86ISD::SBB";
20209 case X86ISD::SMUL: return "X86ISD::SMUL";
20210 case X86ISD::UMUL: return "X86ISD::UMUL";
20211 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20212 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20213 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20214 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20215 case X86ISD::INC: return "X86ISD::INC";
20216 case X86ISD::DEC: return "X86ISD::DEC";
20217 case X86ISD::OR: return "X86ISD::OR";
20218 case X86ISD::XOR: return "X86ISD::XOR";
20219 case X86ISD::AND: return "X86ISD::AND";
20220 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20221 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20222 case X86ISD::PTEST: return "X86ISD::PTEST";
20223 case X86ISD::TESTP: return "X86ISD::TESTP";
20224 case X86ISD::TESTM: return "X86ISD::TESTM";
20225 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20226 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20227 case X86ISD::KTEST: return "X86ISD::KTEST";
20228 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20229 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20230 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20231 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20232 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20233 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20234 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20235 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20236 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20237 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20238 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20239 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20240 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20241 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20242 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20243 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20244 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20245 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20246 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20247 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20248 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20249 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20250 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20251 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20252 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20253 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20254 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20255 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20256 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20257 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20258 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20259 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20260 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20261 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20262 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20263 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20264 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20265 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20266 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20267 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20268 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20269 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20270 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20271 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20272 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20273 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20274 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20275 case X86ISD::SAHF: return "X86ISD::SAHF";
20276 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20277 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20278 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20279 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20280 case X86ISD::VPROT: return "X86ISD::VPROT";
20281 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20282 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20283 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20284 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20285 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20286 case X86ISD::FMADD: return "X86ISD::FMADD";
20287 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20288 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20289 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20290 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20291 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20292 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20293 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20294 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20295 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20296 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20297 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20298 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20299 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20300 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20301 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20302 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20303 case X86ISD::XTEST: return "X86ISD::XTEST";
20304 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20305 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20306 case X86ISD::SELECT: return "X86ISD::SELECT";
20307 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20308 case X86ISD::RCP28: return "X86ISD::RCP28";
20309 case X86ISD::EXP2: return "X86ISD::EXP2";
20310 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20311 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20312 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20313 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20314 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20315 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20316 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20317 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20318 case X86ISD::ADDS: return "X86ISD::ADDS";
20319 case X86ISD::SUBS: return "X86ISD::SUBS";
20320 case X86ISD::AVG: return "X86ISD::AVG";
20321 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20322 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20323 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20324 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20325 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20326 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20331 // isLegalAddressingMode - Return true if the addressing mode represented
20332 // by AM is legal for this target, for a load/store of the specified type.
20333 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20334 const AddrMode &AM, Type *Ty,
20335 unsigned AS) const {
20336 // X86 supports extremely general addressing modes.
20337 CodeModel::Model M = getTargetMachine().getCodeModel();
20338 Reloc::Model R = getTargetMachine().getRelocationModel();
20340 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20341 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20346 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20348 // If a reference to this global requires an extra load, we can't fold it.
20349 if (isGlobalStubReference(GVFlags))
20352 // If BaseGV requires a register for the PIC base, we cannot also have a
20353 // BaseReg specified.
20354 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20357 // If lower 4G is not available, then we must use rip-relative addressing.
20358 if ((M != CodeModel::Small || R != Reloc::Static) &&
20359 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20363 switch (AM.Scale) {
20369 // These scales always work.
20374 // These scales are formed with basereg+scalereg. Only accept if there is
20379 default: // Other stuff never works.
20386 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20387 unsigned Bits = Ty->getScalarSizeInBits();
20389 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20390 // particularly cheaper than those without.
20394 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20395 // variable shifts just as cheap as scalar ones.
20396 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20399 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20400 // fully general vector.
20404 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20405 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20407 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20408 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20409 return NumBits1 > NumBits2;
20412 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20413 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20416 if (!isTypeLegal(EVT::getEVT(Ty1)))
20419 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20421 // Assuming the caller doesn't have a zeroext or signext return parameter,
20422 // truncation all the way down to i1 is valid.
20426 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20427 return isInt<32>(Imm);
20430 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20431 // Can also use sub to handle negated immediates.
20432 return isInt<32>(Imm);
20435 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20436 if (!VT1.isInteger() || !VT2.isInteger())
20438 unsigned NumBits1 = VT1.getSizeInBits();
20439 unsigned NumBits2 = VT2.getSizeInBits();
20440 return NumBits1 > NumBits2;
20443 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20444 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20445 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20448 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20449 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20450 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20453 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20454 EVT VT1 = Val.getValueType();
20455 if (isZExtFree(VT1, VT2))
20458 if (Val.getOpcode() != ISD::LOAD)
20461 if (!VT1.isSimple() || !VT1.isInteger() ||
20462 !VT2.isSimple() || !VT2.isInteger())
20465 switch (VT1.getSimpleVT().SimpleTy) {
20470 // X86 has 8, 16, and 32-bit zero-extending loads.
20477 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20480 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20481 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20484 VT = VT.getScalarType();
20486 if (!VT.isSimple())
20489 switch (VT.getSimpleVT().SimpleTy) {
20500 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20501 // i16 instructions are longer (0x66 prefix) and potentially slower.
20502 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20505 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20506 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20507 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20508 /// are assumed to be legal.
20510 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20512 if (!VT.isSimple())
20515 // Not for i1 vectors
20516 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20519 // Very little shuffling can be done for 64-bit vectors right now.
20520 if (VT.getSimpleVT().getSizeInBits() == 64)
20523 // We only care that the types being shuffled are legal. The lowering can
20524 // handle any possible shuffle mask that results.
20525 return isTypeLegal(VT.getSimpleVT());
20529 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20531 // Just delegate to the generic legality, clear masks aren't special.
20532 return isShuffleMaskLegal(Mask, VT);
20535 //===----------------------------------------------------------------------===//
20536 // X86 Scheduler Hooks
20537 //===----------------------------------------------------------------------===//
20539 /// Utility function to emit xbegin specifying the start of an RTM region.
20540 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20541 const TargetInstrInfo *TII) {
20542 DebugLoc DL = MI->getDebugLoc();
20544 const BasicBlock *BB = MBB->getBasicBlock();
20545 MachineFunction::iterator I = ++MBB->getIterator();
20547 // For the v = xbegin(), we generate
20558 MachineBasicBlock *thisMBB = MBB;
20559 MachineFunction *MF = MBB->getParent();
20560 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20561 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20562 MF->insert(I, mainMBB);
20563 MF->insert(I, sinkMBB);
20565 // Transfer the remainder of BB and its successor edges to sinkMBB.
20566 sinkMBB->splice(sinkMBB->begin(), MBB,
20567 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20568 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20572 // # fallthrough to mainMBB
20573 // # abortion to sinkMBB
20574 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20575 thisMBB->addSuccessor(mainMBB);
20576 thisMBB->addSuccessor(sinkMBB);
20580 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20581 mainMBB->addSuccessor(sinkMBB);
20584 // EAX is live into the sinkMBB
20585 sinkMBB->addLiveIn(X86::EAX);
20586 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20587 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20590 MI->eraseFromParent();
20594 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20595 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20596 // in the .td file.
20597 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20598 const TargetInstrInfo *TII) {
20600 switch (MI->getOpcode()) {
20601 default: llvm_unreachable("illegal opcode!");
20602 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20603 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20604 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20605 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20606 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20607 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20608 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20609 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20612 DebugLoc dl = MI->getDebugLoc();
20613 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20615 unsigned NumArgs = MI->getNumOperands();
20616 for (unsigned i = 1; i < NumArgs; ++i) {
20617 MachineOperand &Op = MI->getOperand(i);
20618 if (!(Op.isReg() && Op.isImplicit()))
20619 MIB.addOperand(Op);
20621 if (MI->hasOneMemOperand())
20622 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20624 BuildMI(*BB, MI, dl,
20625 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20626 .addReg(X86::XMM0);
20628 MI->eraseFromParent();
20632 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20633 // defs in an instruction pattern
20634 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20635 const TargetInstrInfo *TII) {
20637 switch (MI->getOpcode()) {
20638 default: llvm_unreachable("illegal opcode!");
20639 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20640 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20641 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20642 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20643 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20644 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20645 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20646 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20649 DebugLoc dl = MI->getDebugLoc();
20650 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20652 unsigned NumArgs = MI->getNumOperands(); // remove the results
20653 for (unsigned i = 1; i < NumArgs; ++i) {
20654 MachineOperand &Op = MI->getOperand(i);
20655 if (!(Op.isReg() && Op.isImplicit()))
20656 MIB.addOperand(Op);
20658 if (MI->hasOneMemOperand())
20659 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20661 BuildMI(*BB, MI, dl,
20662 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20665 MI->eraseFromParent();
20669 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20670 const X86Subtarget *Subtarget) {
20671 DebugLoc dl = MI->getDebugLoc();
20672 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20673 // Address into RAX/EAX, other two args into ECX, EDX.
20674 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20675 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20676 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20677 for (int i = 0; i < X86::AddrNumOperands; ++i)
20678 MIB.addOperand(MI->getOperand(i));
20680 unsigned ValOps = X86::AddrNumOperands;
20681 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20682 .addReg(MI->getOperand(ValOps).getReg());
20683 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20684 .addReg(MI->getOperand(ValOps+1).getReg());
20686 // The instruction doesn't actually take any operands though.
20687 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20689 MI->eraseFromParent(); // The pseudo is gone now.
20693 MachineBasicBlock *
20694 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20695 MachineBasicBlock *MBB) const {
20696 // Emit va_arg instruction on X86-64.
20698 // Operands to this pseudo-instruction:
20699 // 0 ) Output : destination address (reg)
20700 // 1-5) Input : va_list address (addr, i64mem)
20701 // 6 ) ArgSize : Size (in bytes) of vararg type
20702 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20703 // 8 ) Align : Alignment of type
20704 // 9 ) EFLAGS (implicit-def)
20706 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20707 static_assert(X86::AddrNumOperands == 5,
20708 "VAARG_64 assumes 5 address operands");
20710 unsigned DestReg = MI->getOperand(0).getReg();
20711 MachineOperand &Base = MI->getOperand(1);
20712 MachineOperand &Scale = MI->getOperand(2);
20713 MachineOperand &Index = MI->getOperand(3);
20714 MachineOperand &Disp = MI->getOperand(4);
20715 MachineOperand &Segment = MI->getOperand(5);
20716 unsigned ArgSize = MI->getOperand(6).getImm();
20717 unsigned ArgMode = MI->getOperand(7).getImm();
20718 unsigned Align = MI->getOperand(8).getImm();
20720 // Memory Reference
20721 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20722 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20723 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20725 // Machine Information
20726 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20727 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20728 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20729 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20730 DebugLoc DL = MI->getDebugLoc();
20732 // struct va_list {
20735 // i64 overflow_area (address)
20736 // i64 reg_save_area (address)
20738 // sizeof(va_list) = 24
20739 // alignment(va_list) = 8
20741 unsigned TotalNumIntRegs = 6;
20742 unsigned TotalNumXMMRegs = 8;
20743 bool UseGPOffset = (ArgMode == 1);
20744 bool UseFPOffset = (ArgMode == 2);
20745 unsigned MaxOffset = TotalNumIntRegs * 8 +
20746 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20748 /* Align ArgSize to a multiple of 8 */
20749 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20750 bool NeedsAlign = (Align > 8);
20752 MachineBasicBlock *thisMBB = MBB;
20753 MachineBasicBlock *overflowMBB;
20754 MachineBasicBlock *offsetMBB;
20755 MachineBasicBlock *endMBB;
20757 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20758 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20759 unsigned OffsetReg = 0;
20761 if (!UseGPOffset && !UseFPOffset) {
20762 // If we only pull from the overflow region, we don't create a branch.
20763 // We don't need to alter control flow.
20764 OffsetDestReg = 0; // unused
20765 OverflowDestReg = DestReg;
20767 offsetMBB = nullptr;
20768 overflowMBB = thisMBB;
20771 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20772 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20773 // If not, pull from overflow_area. (branch to overflowMBB)
20778 // offsetMBB overflowMBB
20783 // Registers for the PHI in endMBB
20784 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20785 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20787 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20788 MachineFunction *MF = MBB->getParent();
20789 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20790 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20791 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20793 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20795 // Insert the new basic blocks
20796 MF->insert(MBBIter, offsetMBB);
20797 MF->insert(MBBIter, overflowMBB);
20798 MF->insert(MBBIter, endMBB);
20800 // Transfer the remainder of MBB and its successor edges to endMBB.
20801 endMBB->splice(endMBB->begin(), thisMBB,
20802 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20803 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20805 // Make offsetMBB and overflowMBB successors of thisMBB
20806 thisMBB->addSuccessor(offsetMBB);
20807 thisMBB->addSuccessor(overflowMBB);
20809 // endMBB is a successor of both offsetMBB and overflowMBB
20810 offsetMBB->addSuccessor(endMBB);
20811 overflowMBB->addSuccessor(endMBB);
20813 // Load the offset value into a register
20814 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20815 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20819 .addDisp(Disp, UseFPOffset ? 4 : 0)
20820 .addOperand(Segment)
20821 .setMemRefs(MMOBegin, MMOEnd);
20823 // Check if there is enough room left to pull this argument.
20824 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20826 .addImm(MaxOffset + 8 - ArgSizeA8);
20828 // Branch to "overflowMBB" if offset >= max
20829 // Fall through to "offsetMBB" otherwise
20830 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20831 .addMBB(overflowMBB);
20834 // In offsetMBB, emit code to use the reg_save_area.
20836 assert(OffsetReg != 0);
20838 // Read the reg_save_area address.
20839 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20840 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20845 .addOperand(Segment)
20846 .setMemRefs(MMOBegin, MMOEnd);
20848 // Zero-extend the offset
20849 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20850 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20853 .addImm(X86::sub_32bit);
20855 // Add the offset to the reg_save_area to get the final address.
20856 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20857 .addReg(OffsetReg64)
20858 .addReg(RegSaveReg);
20860 // Compute the offset for the next argument
20861 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20862 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20864 .addImm(UseFPOffset ? 16 : 8);
20866 // Store it back into the va_list.
20867 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20871 .addDisp(Disp, UseFPOffset ? 4 : 0)
20872 .addOperand(Segment)
20873 .addReg(NextOffsetReg)
20874 .setMemRefs(MMOBegin, MMOEnd);
20877 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20882 // Emit code to use overflow area
20885 // Load the overflow_area address into a register.
20886 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20887 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20892 .addOperand(Segment)
20893 .setMemRefs(MMOBegin, MMOEnd);
20895 // If we need to align it, do so. Otherwise, just copy the address
20896 // to OverflowDestReg.
20898 // Align the overflow address
20899 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20900 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20902 // aligned_addr = (addr + (align-1)) & ~(align-1)
20903 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20904 .addReg(OverflowAddrReg)
20907 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20909 .addImm(~(uint64_t)(Align-1));
20911 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20912 .addReg(OverflowAddrReg);
20915 // Compute the next overflow address after this argument.
20916 // (the overflow address should be kept 8-byte aligned)
20917 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20918 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20919 .addReg(OverflowDestReg)
20920 .addImm(ArgSizeA8);
20922 // Store the new overflow address.
20923 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20928 .addOperand(Segment)
20929 .addReg(NextAddrReg)
20930 .setMemRefs(MMOBegin, MMOEnd);
20932 // If we branched, emit the PHI to the front of endMBB.
20934 BuildMI(*endMBB, endMBB->begin(), DL,
20935 TII->get(X86::PHI), DestReg)
20936 .addReg(OffsetDestReg).addMBB(offsetMBB)
20937 .addReg(OverflowDestReg).addMBB(overflowMBB);
20940 // Erase the pseudo instruction
20941 MI->eraseFromParent();
20946 MachineBasicBlock *
20947 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20949 MachineBasicBlock *MBB) const {
20950 // Emit code to save XMM registers to the stack. The ABI says that the
20951 // number of registers to save is given in %al, so it's theoretically
20952 // possible to do an indirect jump trick to avoid saving all of them,
20953 // however this code takes a simpler approach and just executes all
20954 // of the stores if %al is non-zero. It's less code, and it's probably
20955 // easier on the hardware branch predictor, and stores aren't all that
20956 // expensive anyway.
20958 // Create the new basic blocks. One block contains all the XMM stores,
20959 // and one block is the final destination regardless of whether any
20960 // stores were performed.
20961 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20962 MachineFunction *F = MBB->getParent();
20963 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20964 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20965 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20966 F->insert(MBBIter, XMMSaveMBB);
20967 F->insert(MBBIter, EndMBB);
20969 // Transfer the remainder of MBB and its successor edges to EndMBB.
20970 EndMBB->splice(EndMBB->begin(), MBB,
20971 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20972 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20974 // The original block will now fall through to the XMM save block.
20975 MBB->addSuccessor(XMMSaveMBB);
20976 // The XMMSaveMBB will fall through to the end block.
20977 XMMSaveMBB->addSuccessor(EndMBB);
20979 // Now add the instructions.
20980 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20981 DebugLoc DL = MI->getDebugLoc();
20983 unsigned CountReg = MI->getOperand(0).getReg();
20984 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20985 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20987 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20988 // If %al is 0, branch around the XMM save block.
20989 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20990 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20991 MBB->addSuccessor(EndMBB);
20994 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20995 // that was just emitted, but clearly shouldn't be "saved".
20996 assert((MI->getNumOperands() <= 3 ||
20997 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20998 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20999 && "Expected last argument to be EFLAGS");
21000 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21001 // In the XMM save block, save all the XMM argument registers.
21002 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21003 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21004 MachineMemOperand *MMO = F->getMachineMemOperand(
21005 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21006 MachineMemOperand::MOStore,
21007 /*Size=*/16, /*Align=*/16);
21008 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21009 .addFrameIndex(RegSaveFrameIndex)
21010 .addImm(/*Scale=*/1)
21011 .addReg(/*IndexReg=*/0)
21012 .addImm(/*Disp=*/Offset)
21013 .addReg(/*Segment=*/0)
21014 .addReg(MI->getOperand(i).getReg())
21015 .addMemOperand(MMO);
21018 MI->eraseFromParent(); // The pseudo instruction is gone now.
21023 // The EFLAGS operand of SelectItr might be missing a kill marker
21024 // because there were multiple uses of EFLAGS, and ISel didn't know
21025 // which to mark. Figure out whether SelectItr should have had a
21026 // kill marker, and set it if it should. Returns the correct kill
21028 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21029 MachineBasicBlock* BB,
21030 const TargetRegisterInfo* TRI) {
21031 // Scan forward through BB for a use/def of EFLAGS.
21032 MachineBasicBlock::iterator miI(std::next(SelectItr));
21033 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21034 const MachineInstr& mi = *miI;
21035 if (mi.readsRegister(X86::EFLAGS))
21037 if (mi.definesRegister(X86::EFLAGS))
21038 break; // Should have kill-flag - update below.
21041 // If we hit the end of the block, check whether EFLAGS is live into a
21043 if (miI == BB->end()) {
21044 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21045 sEnd = BB->succ_end();
21046 sItr != sEnd; ++sItr) {
21047 MachineBasicBlock* succ = *sItr;
21048 if (succ->isLiveIn(X86::EFLAGS))
21053 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21054 // out. SelectMI should have a kill flag on EFLAGS.
21055 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21059 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21060 // together with other CMOV pseudo-opcodes into a single basic-block with
21061 // conditional jump around it.
21062 static bool isCMOVPseudo(MachineInstr *MI) {
21063 switch (MI->getOpcode()) {
21064 case X86::CMOV_FR32:
21065 case X86::CMOV_FR64:
21066 case X86::CMOV_GR8:
21067 case X86::CMOV_GR16:
21068 case X86::CMOV_GR32:
21069 case X86::CMOV_RFP32:
21070 case X86::CMOV_RFP64:
21071 case X86::CMOV_RFP80:
21072 case X86::CMOV_V2F64:
21073 case X86::CMOV_V2I64:
21074 case X86::CMOV_V4F32:
21075 case X86::CMOV_V4F64:
21076 case X86::CMOV_V4I64:
21077 case X86::CMOV_V16F32:
21078 case X86::CMOV_V8F32:
21079 case X86::CMOV_V8F64:
21080 case X86::CMOV_V8I64:
21081 case X86::CMOV_V8I1:
21082 case X86::CMOV_V16I1:
21083 case X86::CMOV_V32I1:
21084 case X86::CMOV_V64I1:
21092 MachineBasicBlock *
21093 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21094 MachineBasicBlock *BB) const {
21095 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21096 DebugLoc DL = MI->getDebugLoc();
21098 // To "insert" a SELECT_CC instruction, we actually have to insert the
21099 // diamond control-flow pattern. The incoming instruction knows the
21100 // destination vreg to set, the condition code register to branch on, the
21101 // true/false values to select between, and a branch opcode to use.
21102 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21103 MachineFunction::iterator It = ++BB->getIterator();
21108 // cmpTY ccX, r1, r2
21110 // fallthrough --> copy0MBB
21111 MachineBasicBlock *thisMBB = BB;
21112 MachineFunction *F = BB->getParent();
21114 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21115 // as described above, by inserting a BB, and then making a PHI at the join
21116 // point to select the true and false operands of the CMOV in the PHI.
21118 // The code also handles two different cases of multiple CMOV opcodes
21122 // In this case, there are multiple CMOVs in a row, all which are based on
21123 // the same condition setting (or the exact opposite condition setting).
21124 // In this case we can lower all the CMOVs using a single inserted BB, and
21125 // then make a number of PHIs at the join point to model the CMOVs. The only
21126 // trickiness here, is that in a case like:
21128 // t2 = CMOV cond1 t1, f1
21129 // t3 = CMOV cond1 t2, f2
21131 // when rewriting this into PHIs, we have to perform some renaming on the
21132 // temps since you cannot have a PHI operand refer to a PHI result earlier
21133 // in the same block. The "simple" but wrong lowering would be:
21135 // t2 = PHI t1(BB1), f1(BB2)
21136 // t3 = PHI t2(BB1), f2(BB2)
21138 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21139 // renaming is to note that on the path through BB1, t2 is really just a
21140 // copy of t1, and do that renaming, properly generating:
21142 // t2 = PHI t1(BB1), f1(BB2)
21143 // t3 = PHI t1(BB1), f2(BB2)
21145 // Case 2, we lower cascaded CMOVs such as
21147 // (CMOV (CMOV F, T, cc1), T, cc2)
21149 // to two successives branches. For that, we look for another CMOV as the
21150 // following instruction.
21152 // Without this, we would add a PHI between the two jumps, which ends up
21153 // creating a few copies all around. For instance, for
21155 // (sitofp (zext (fcmp une)))
21157 // we would generate:
21159 // ucomiss %xmm1, %xmm0
21160 // movss <1.0f>, %xmm0
21161 // movaps %xmm0, %xmm1
21163 // xorps %xmm1, %xmm1
21166 // movaps %xmm1, %xmm0
21170 // because this custom-inserter would have generated:
21182 // A: X = ...; Y = ...
21184 // C: Z = PHI [X, A], [Y, B]
21186 // E: PHI [X, C], [Z, D]
21188 // If we lower both CMOVs in a single step, we can instead generate:
21200 // A: X = ...; Y = ...
21202 // E: PHI [X, A], [X, C], [Y, D]
21204 // Which, in our sitofp/fcmp example, gives us something like:
21206 // ucomiss %xmm1, %xmm0
21207 // movss <1.0f>, %xmm0
21210 // xorps %xmm0, %xmm0
21214 MachineInstr *CascadedCMOV = nullptr;
21215 MachineInstr *LastCMOV = MI;
21216 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21217 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21218 MachineBasicBlock::iterator NextMIIt =
21219 std::next(MachineBasicBlock::iterator(MI));
21221 // Check for case 1, where there are multiple CMOVs with the same condition
21222 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21223 // number of jumps the most.
21225 if (isCMOVPseudo(MI)) {
21226 // See if we have a string of CMOVS with the same condition.
21227 while (NextMIIt != BB->end() &&
21228 isCMOVPseudo(NextMIIt) &&
21229 (NextMIIt->getOperand(3).getImm() == CC ||
21230 NextMIIt->getOperand(3).getImm() == OppCC)) {
21231 LastCMOV = &*NextMIIt;
21236 // This checks for case 2, but only do this if we didn't already find
21237 // case 1, as indicated by LastCMOV == MI.
21238 if (LastCMOV == MI &&
21239 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21240 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21241 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21242 CascadedCMOV = &*NextMIIt;
21245 MachineBasicBlock *jcc1MBB = nullptr;
21247 // If we have a cascaded CMOV, we lower it to two successive branches to
21248 // the same block. EFLAGS is used by both, so mark it as live in the second.
21249 if (CascadedCMOV) {
21250 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21251 F->insert(It, jcc1MBB);
21252 jcc1MBB->addLiveIn(X86::EFLAGS);
21255 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21256 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21257 F->insert(It, copy0MBB);
21258 F->insert(It, sinkMBB);
21260 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21261 // live into the sink and copy blocks.
21262 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21264 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21265 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21266 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21267 copy0MBB->addLiveIn(X86::EFLAGS);
21268 sinkMBB->addLiveIn(X86::EFLAGS);
21271 // Transfer the remainder of BB and its successor edges to sinkMBB.
21272 sinkMBB->splice(sinkMBB->begin(), BB,
21273 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21274 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21276 // Add the true and fallthrough blocks as its successors.
21277 if (CascadedCMOV) {
21278 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21279 BB->addSuccessor(jcc1MBB);
21281 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21282 // jump to the sinkMBB.
21283 jcc1MBB->addSuccessor(copy0MBB);
21284 jcc1MBB->addSuccessor(sinkMBB);
21286 BB->addSuccessor(copy0MBB);
21289 // The true block target of the first (or only) branch is always sinkMBB.
21290 BB->addSuccessor(sinkMBB);
21292 // Create the conditional branch instruction.
21293 unsigned Opc = X86::GetCondBranchFromCond(CC);
21294 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21296 if (CascadedCMOV) {
21297 unsigned Opc2 = X86::GetCondBranchFromCond(
21298 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21299 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21303 // %FalseValue = ...
21304 // # fallthrough to sinkMBB
21305 copy0MBB->addSuccessor(sinkMBB);
21308 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21310 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21311 MachineBasicBlock::iterator MIItEnd =
21312 std::next(MachineBasicBlock::iterator(LastCMOV));
21313 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21314 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21315 MachineInstrBuilder MIB;
21317 // As we are creating the PHIs, we have to be careful if there is more than
21318 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21319 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21320 // That also means that PHI construction must work forward from earlier to
21321 // later, and that the code must maintain a mapping from earlier PHI's
21322 // destination registers, and the registers that went into the PHI.
21324 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21325 unsigned DestReg = MIIt->getOperand(0).getReg();
21326 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21327 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21329 // If this CMOV we are generating is the opposite condition from
21330 // the jump we generated, then we have to swap the operands for the
21331 // PHI that is going to be generated.
21332 if (MIIt->getOperand(3).getImm() == OppCC)
21333 std::swap(Op1Reg, Op2Reg);
21335 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21336 Op1Reg = RegRewriteTable[Op1Reg].first;
21338 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21339 Op2Reg = RegRewriteTable[Op2Reg].second;
21341 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21342 TII->get(X86::PHI), DestReg)
21343 .addReg(Op1Reg).addMBB(copy0MBB)
21344 .addReg(Op2Reg).addMBB(thisMBB);
21346 // Add this PHI to the rewrite table.
21347 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21350 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21351 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21352 if (CascadedCMOV) {
21353 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21354 // Copy the PHI result to the register defined by the second CMOV.
21355 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21356 DL, TII->get(TargetOpcode::COPY),
21357 CascadedCMOV->getOperand(0).getReg())
21358 .addReg(MI->getOperand(0).getReg());
21359 CascadedCMOV->eraseFromParent();
21362 // Now remove the CMOV(s).
21363 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21364 (MIIt++)->eraseFromParent();
21369 MachineBasicBlock *
21370 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21371 MachineBasicBlock *BB) const {
21372 // Combine the following atomic floating-point modification pattern:
21373 // a.store(reg OP a.load(acquire), release)
21374 // Transform them into:
21375 // OPss (%gpr), %xmm
21376 // movss %xmm, (%gpr)
21377 // Or sd equivalent for 64-bit operations.
21379 switch (MI->getOpcode()) {
21380 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21381 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21382 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21384 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21385 DebugLoc DL = MI->getDebugLoc();
21386 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21387 MachineOperand MSrc = MI->getOperand(0);
21388 unsigned VSrc = MI->getOperand(5).getReg();
21389 const MachineOperand &Disp = MI->getOperand(3);
21390 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21391 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21392 if (hasDisp && MSrc.isReg())
21393 MSrc.setIsKill(false);
21394 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21395 .addOperand(/*Base=*/MSrc)
21396 .addImm(/*Scale=*/1)
21397 .addReg(/*Index=*/0)
21398 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21400 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21401 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21403 .addOperand(/*Base=*/MSrc)
21404 .addImm(/*Scale=*/1)
21405 .addReg(/*Index=*/0)
21406 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21407 .addReg(/*Segment=*/0);
21408 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21409 MI->eraseFromParent(); // The pseudo instruction is gone now.
21413 MachineBasicBlock *
21414 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21415 MachineBasicBlock *BB) const {
21416 MachineFunction *MF = BB->getParent();
21417 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21418 DebugLoc DL = MI->getDebugLoc();
21419 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21421 assert(MF->shouldSplitStack());
21423 const bool Is64Bit = Subtarget->is64Bit();
21424 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21426 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21427 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21430 // ... [Till the alloca]
21431 // If stacklet is not large enough, jump to mallocMBB
21434 // Allocate by subtracting from RSP
21435 // Jump to continueMBB
21438 // Allocate by call to runtime
21442 // [rest of original BB]
21445 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21446 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21447 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21449 MachineRegisterInfo &MRI = MF->getRegInfo();
21450 const TargetRegisterClass *AddrRegClass =
21451 getRegClassFor(getPointerTy(MF->getDataLayout()));
21453 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21454 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21455 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21456 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21457 sizeVReg = MI->getOperand(1).getReg(),
21458 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21460 MachineFunction::iterator MBBIter = ++BB->getIterator();
21462 MF->insert(MBBIter, bumpMBB);
21463 MF->insert(MBBIter, mallocMBB);
21464 MF->insert(MBBIter, continueMBB);
21466 continueMBB->splice(continueMBB->begin(), BB,
21467 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21468 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21470 // Add code to the main basic block to check if the stack limit has been hit,
21471 // and if so, jump to mallocMBB otherwise to bumpMBB.
21472 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21473 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21474 .addReg(tmpSPVReg).addReg(sizeVReg);
21475 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21476 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21477 .addReg(SPLimitVReg);
21478 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21480 // bumpMBB simply decreases the stack pointer, since we know the current
21481 // stacklet has enough space.
21482 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21483 .addReg(SPLimitVReg);
21484 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21485 .addReg(SPLimitVReg);
21486 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21488 // Calls into a routine in libgcc to allocate more space from the heap.
21489 const uint32_t *RegMask =
21490 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21492 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21494 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21495 .addExternalSymbol("__morestack_allocate_stack_space")
21496 .addRegMask(RegMask)
21497 .addReg(X86::RDI, RegState::Implicit)
21498 .addReg(X86::RAX, RegState::ImplicitDefine);
21499 } else if (Is64Bit) {
21500 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21502 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21503 .addExternalSymbol("__morestack_allocate_stack_space")
21504 .addRegMask(RegMask)
21505 .addReg(X86::EDI, RegState::Implicit)
21506 .addReg(X86::EAX, RegState::ImplicitDefine);
21508 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21510 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21511 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21512 .addExternalSymbol("__morestack_allocate_stack_space")
21513 .addRegMask(RegMask)
21514 .addReg(X86::EAX, RegState::ImplicitDefine);
21518 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21521 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21522 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21523 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21525 // Set up the CFG correctly.
21526 BB->addSuccessor(bumpMBB);
21527 BB->addSuccessor(mallocMBB);
21528 mallocMBB->addSuccessor(continueMBB);
21529 bumpMBB->addSuccessor(continueMBB);
21531 // Take care of the PHI nodes.
21532 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21533 MI->getOperand(0).getReg())
21534 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21535 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21537 // Delete the original pseudo instruction.
21538 MI->eraseFromParent();
21541 return continueMBB;
21544 MachineBasicBlock *
21545 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21546 MachineBasicBlock *BB) const {
21547 assert(!Subtarget->isTargetMachO());
21548 DebugLoc DL = MI->getDebugLoc();
21549 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21550 *BB->getParent(), *BB, MI, DL, false);
21551 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21552 MI->eraseFromParent(); // The pseudo instruction is gone now.
21556 MachineBasicBlock *
21557 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21558 MachineBasicBlock *BB) const {
21559 MachineFunction *MF = BB->getParent();
21560 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21561 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21562 DebugLoc DL = MI->getDebugLoc();
21564 assert(!isAsynchronousEHPersonality(
21565 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21566 "SEH does not use catchret!");
21568 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21569 if (!Subtarget->is32Bit())
21572 // C++ EH creates a new target block to hold the restore code, and wires up
21573 // the new block to the return destination with a normal JMP_4.
21574 MachineBasicBlock *RestoreMBB =
21575 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21576 assert(BB->succ_size() == 1);
21577 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21578 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21579 BB->addSuccessor(RestoreMBB);
21580 MI->getOperand(0).setMBB(RestoreMBB);
21582 auto RestoreMBBI = RestoreMBB->begin();
21583 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21584 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21588 MachineBasicBlock *
21589 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21590 MachineBasicBlock *BB) const {
21591 MachineFunction *MF = BB->getParent();
21592 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21593 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21594 // Only 32-bit SEH requires special handling for catchpad.
21595 if (IsSEH && Subtarget->is32Bit()) {
21596 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21597 DebugLoc DL = MI->getDebugLoc();
21598 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21600 MI->eraseFromParent();
21604 MachineBasicBlock *
21605 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21606 MachineBasicBlock *BB) const {
21607 // This is pretty easy. We're taking the value that we received from
21608 // our load from the relocation, sticking it in either RDI (x86-64)
21609 // or EAX and doing an indirect call. The return value will then
21610 // be in the normal return register.
21611 MachineFunction *F = BB->getParent();
21612 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21613 DebugLoc DL = MI->getDebugLoc();
21615 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21616 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21618 // Get a register mask for the lowered call.
21619 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21620 // proper register mask.
21621 const uint32_t *RegMask =
21622 Subtarget->is64Bit() ?
21623 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21624 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21625 if (Subtarget->is64Bit()) {
21626 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21627 TII->get(X86::MOV64rm), X86::RDI)
21629 .addImm(0).addReg(0)
21630 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21631 MI->getOperand(3).getTargetFlags())
21633 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21634 addDirectMem(MIB, X86::RDI);
21635 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21636 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21637 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21638 TII->get(X86::MOV32rm), X86::EAX)
21640 .addImm(0).addReg(0)
21641 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21642 MI->getOperand(3).getTargetFlags())
21644 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21645 addDirectMem(MIB, X86::EAX);
21646 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21648 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21649 TII->get(X86::MOV32rm), X86::EAX)
21650 .addReg(TII->getGlobalBaseReg(F))
21651 .addImm(0).addReg(0)
21652 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21653 MI->getOperand(3).getTargetFlags())
21655 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21656 addDirectMem(MIB, X86::EAX);
21657 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21660 MI->eraseFromParent(); // The pseudo instruction is gone now.
21664 MachineBasicBlock *
21665 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21666 MachineBasicBlock *MBB) const {
21667 DebugLoc DL = MI->getDebugLoc();
21668 MachineFunction *MF = MBB->getParent();
21669 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21670 MachineRegisterInfo &MRI = MF->getRegInfo();
21672 const BasicBlock *BB = MBB->getBasicBlock();
21673 MachineFunction::iterator I = ++MBB->getIterator();
21675 // Memory Reference
21676 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21677 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21680 unsigned MemOpndSlot = 0;
21682 unsigned CurOp = 0;
21684 DstReg = MI->getOperand(CurOp++).getReg();
21685 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21686 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21687 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21688 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21690 MemOpndSlot = CurOp;
21692 MVT PVT = getPointerTy(MF->getDataLayout());
21693 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21694 "Invalid Pointer Size!");
21696 // For v = setjmp(buf), we generate
21699 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21700 // SjLjSetup restoreMBB
21706 // v = phi(main, restore)
21709 // if base pointer being used, load it from frame
21712 MachineBasicBlock *thisMBB = MBB;
21713 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21714 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21715 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21716 MF->insert(I, mainMBB);
21717 MF->insert(I, sinkMBB);
21718 MF->push_back(restoreMBB);
21719 restoreMBB->setHasAddressTaken();
21721 MachineInstrBuilder MIB;
21723 // Transfer the remainder of BB and its successor edges to sinkMBB.
21724 sinkMBB->splice(sinkMBB->begin(), MBB,
21725 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21726 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21729 unsigned PtrStoreOpc = 0;
21730 unsigned LabelReg = 0;
21731 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21732 Reloc::Model RM = MF->getTarget().getRelocationModel();
21733 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21734 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21736 // Prepare IP either in reg or imm.
21737 if (!UseImmLabel) {
21738 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21739 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21740 LabelReg = MRI.createVirtualRegister(PtrRC);
21741 if (Subtarget->is64Bit()) {
21742 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21746 .addMBB(restoreMBB)
21749 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21750 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21751 .addReg(XII->getGlobalBaseReg(MF))
21754 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21758 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21760 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21761 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21762 if (i == X86::AddrDisp)
21763 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21765 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21768 MIB.addReg(LabelReg);
21770 MIB.addMBB(restoreMBB);
21771 MIB.setMemRefs(MMOBegin, MMOEnd);
21773 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21774 .addMBB(restoreMBB);
21776 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21777 MIB.addRegMask(RegInfo->getNoPreservedMask());
21778 thisMBB->addSuccessor(mainMBB);
21779 thisMBB->addSuccessor(restoreMBB);
21783 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21784 mainMBB->addSuccessor(sinkMBB);
21787 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21788 TII->get(X86::PHI), DstReg)
21789 .addReg(mainDstReg).addMBB(mainMBB)
21790 .addReg(restoreDstReg).addMBB(restoreMBB);
21793 if (RegInfo->hasBasePointer(*MF)) {
21794 const bool Uses64BitFramePtr =
21795 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21796 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21797 X86FI->setRestoreBasePointer(MF);
21798 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21799 unsigned BasePtr = RegInfo->getBaseRegister();
21800 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21801 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21802 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21803 .setMIFlag(MachineInstr::FrameSetup);
21805 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21806 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21807 restoreMBB->addSuccessor(sinkMBB);
21809 MI->eraseFromParent();
21813 MachineBasicBlock *
21814 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21815 MachineBasicBlock *MBB) const {
21816 DebugLoc DL = MI->getDebugLoc();
21817 MachineFunction *MF = MBB->getParent();
21818 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21819 MachineRegisterInfo &MRI = MF->getRegInfo();
21821 // Memory Reference
21822 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21823 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21825 MVT PVT = getPointerTy(MF->getDataLayout());
21826 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21827 "Invalid Pointer Size!");
21829 const TargetRegisterClass *RC =
21830 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21831 unsigned Tmp = MRI.createVirtualRegister(RC);
21832 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21833 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21834 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21835 unsigned SP = RegInfo->getStackRegister();
21837 MachineInstrBuilder MIB;
21839 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21840 const int64_t SPOffset = 2 * PVT.getStoreSize();
21842 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21843 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21846 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21847 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21848 MIB.addOperand(MI->getOperand(i));
21849 MIB.setMemRefs(MMOBegin, MMOEnd);
21851 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21852 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21853 if (i == X86::AddrDisp)
21854 MIB.addDisp(MI->getOperand(i), LabelOffset);
21856 MIB.addOperand(MI->getOperand(i));
21858 MIB.setMemRefs(MMOBegin, MMOEnd);
21860 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21861 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21862 if (i == X86::AddrDisp)
21863 MIB.addDisp(MI->getOperand(i), SPOffset);
21865 MIB.addOperand(MI->getOperand(i));
21867 MIB.setMemRefs(MMOBegin, MMOEnd);
21869 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21871 MI->eraseFromParent();
21875 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21876 // accumulator loops. Writing back to the accumulator allows the coalescer
21877 // to remove extra copies in the loop.
21878 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21879 MachineBasicBlock *
21880 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21881 MachineBasicBlock *MBB) const {
21882 MachineOperand &AddendOp = MI->getOperand(3);
21884 // Bail out early if the addend isn't a register - we can't switch these.
21885 if (!AddendOp.isReg())
21888 MachineFunction &MF = *MBB->getParent();
21889 MachineRegisterInfo &MRI = MF.getRegInfo();
21891 // Check whether the addend is defined by a PHI:
21892 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21893 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21894 if (!AddendDef.isPHI())
21897 // Look for the following pattern:
21899 // %addend = phi [%entry, 0], [%loop, %result]
21901 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21905 // %addend = phi [%entry, 0], [%loop, %result]
21907 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21909 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21910 assert(AddendDef.getOperand(i).isReg());
21911 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21912 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21913 if (&PHISrcInst == MI) {
21914 // Found a matching instruction.
21915 unsigned NewFMAOpc = 0;
21916 switch (MI->getOpcode()) {
21917 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21918 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21919 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21920 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21921 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21922 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21923 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21924 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21925 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21926 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21927 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21928 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21929 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21930 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21931 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21932 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21933 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21934 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21935 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21936 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21938 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21939 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21940 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21941 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21942 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21943 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21944 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21945 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21946 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21947 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21948 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21949 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21950 default: llvm_unreachable("Unrecognized FMA variant.");
21953 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21954 MachineInstrBuilder MIB =
21955 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21956 .addOperand(MI->getOperand(0))
21957 .addOperand(MI->getOperand(3))
21958 .addOperand(MI->getOperand(2))
21959 .addOperand(MI->getOperand(1));
21960 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21961 MI->eraseFromParent();
21968 MachineBasicBlock *
21969 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21970 MachineBasicBlock *BB) const {
21971 switch (MI->getOpcode()) {
21972 default: llvm_unreachable("Unexpected instr type to insert");
21973 case X86::TAILJMPd64:
21974 case X86::TAILJMPr64:
21975 case X86::TAILJMPm64:
21976 case X86::TAILJMPd64_REX:
21977 case X86::TAILJMPr64_REX:
21978 case X86::TAILJMPm64_REX:
21979 llvm_unreachable("TAILJMP64 would not be touched here.");
21980 case X86::TCRETURNdi64:
21981 case X86::TCRETURNri64:
21982 case X86::TCRETURNmi64:
21984 case X86::WIN_ALLOCA:
21985 return EmitLoweredWinAlloca(MI, BB);
21986 case X86::CATCHRET:
21987 return EmitLoweredCatchRet(MI, BB);
21988 case X86::CATCHPAD:
21989 return EmitLoweredCatchPad(MI, BB);
21990 case X86::SEG_ALLOCA_32:
21991 case X86::SEG_ALLOCA_64:
21992 return EmitLoweredSegAlloca(MI, BB);
21993 case X86::TLSCall_32:
21994 case X86::TLSCall_64:
21995 return EmitLoweredTLSCall(MI, BB);
21996 case X86::CMOV_FR32:
21997 case X86::CMOV_FR64:
21998 case X86::CMOV_GR8:
21999 case X86::CMOV_GR16:
22000 case X86::CMOV_GR32:
22001 case X86::CMOV_RFP32:
22002 case X86::CMOV_RFP64:
22003 case X86::CMOV_RFP80:
22004 case X86::CMOV_V2F64:
22005 case X86::CMOV_V2I64:
22006 case X86::CMOV_V4F32:
22007 case X86::CMOV_V4F64:
22008 case X86::CMOV_V4I64:
22009 case X86::CMOV_V16F32:
22010 case X86::CMOV_V8F32:
22011 case X86::CMOV_V8F64:
22012 case X86::CMOV_V8I64:
22013 case X86::CMOV_V8I1:
22014 case X86::CMOV_V16I1:
22015 case X86::CMOV_V32I1:
22016 case X86::CMOV_V64I1:
22017 return EmitLoweredSelect(MI, BB);
22019 case X86::RELEASE_FADD32mr:
22020 case X86::RELEASE_FADD64mr:
22021 return EmitLoweredAtomicFP(MI, BB);
22023 case X86::FP32_TO_INT16_IN_MEM:
22024 case X86::FP32_TO_INT32_IN_MEM:
22025 case X86::FP32_TO_INT64_IN_MEM:
22026 case X86::FP64_TO_INT16_IN_MEM:
22027 case X86::FP64_TO_INT32_IN_MEM:
22028 case X86::FP64_TO_INT64_IN_MEM:
22029 case X86::FP80_TO_INT16_IN_MEM:
22030 case X86::FP80_TO_INT32_IN_MEM:
22031 case X86::FP80_TO_INT64_IN_MEM: {
22032 MachineFunction *F = BB->getParent();
22033 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22034 DebugLoc DL = MI->getDebugLoc();
22036 // Change the floating point control register to use "round towards zero"
22037 // mode when truncating to an integer value.
22038 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22039 addFrameReference(BuildMI(*BB, MI, DL,
22040 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22042 // Load the old value of the high byte of the control word...
22044 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22045 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22048 // Set the high part to be round to zero...
22049 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22052 // Reload the modified control word now...
22053 addFrameReference(BuildMI(*BB, MI, DL,
22054 TII->get(X86::FLDCW16m)), CWFrameIdx);
22056 // Restore the memory image of control word to original value
22057 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22060 // Get the X86 opcode to use.
22062 switch (MI->getOpcode()) {
22063 default: llvm_unreachable("illegal opcode!");
22064 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22065 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22066 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22067 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22068 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22069 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22070 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22071 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22072 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22076 MachineOperand &Op = MI->getOperand(0);
22078 AM.BaseType = X86AddressMode::RegBase;
22079 AM.Base.Reg = Op.getReg();
22081 AM.BaseType = X86AddressMode::FrameIndexBase;
22082 AM.Base.FrameIndex = Op.getIndex();
22084 Op = MI->getOperand(1);
22086 AM.Scale = Op.getImm();
22087 Op = MI->getOperand(2);
22089 AM.IndexReg = Op.getImm();
22090 Op = MI->getOperand(3);
22091 if (Op.isGlobal()) {
22092 AM.GV = Op.getGlobal();
22094 AM.Disp = Op.getImm();
22096 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22097 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22099 // Reload the original control word now.
22100 addFrameReference(BuildMI(*BB, MI, DL,
22101 TII->get(X86::FLDCW16m)), CWFrameIdx);
22103 MI->eraseFromParent(); // The pseudo instruction is gone now.
22106 // String/text processing lowering.
22107 case X86::PCMPISTRM128REG:
22108 case X86::VPCMPISTRM128REG:
22109 case X86::PCMPISTRM128MEM:
22110 case X86::VPCMPISTRM128MEM:
22111 case X86::PCMPESTRM128REG:
22112 case X86::VPCMPESTRM128REG:
22113 case X86::PCMPESTRM128MEM:
22114 case X86::VPCMPESTRM128MEM:
22115 assert(Subtarget->hasSSE42() &&
22116 "Target must have SSE4.2 or AVX features enabled");
22117 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22119 // String/text processing lowering.
22120 case X86::PCMPISTRIREG:
22121 case X86::VPCMPISTRIREG:
22122 case X86::PCMPISTRIMEM:
22123 case X86::VPCMPISTRIMEM:
22124 case X86::PCMPESTRIREG:
22125 case X86::VPCMPESTRIREG:
22126 case X86::PCMPESTRIMEM:
22127 case X86::VPCMPESTRIMEM:
22128 assert(Subtarget->hasSSE42() &&
22129 "Target must have SSE4.2 or AVX features enabled");
22130 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22132 // Thread synchronization.
22134 return EmitMonitor(MI, BB, Subtarget);
22138 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22140 case X86::VASTART_SAVE_XMM_REGS:
22141 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22143 case X86::VAARG_64:
22144 return EmitVAARG64WithCustomInserter(MI, BB);
22146 case X86::EH_SjLj_SetJmp32:
22147 case X86::EH_SjLj_SetJmp64:
22148 return emitEHSjLjSetJmp(MI, BB);
22150 case X86::EH_SjLj_LongJmp32:
22151 case X86::EH_SjLj_LongJmp64:
22152 return emitEHSjLjLongJmp(MI, BB);
22154 case TargetOpcode::STATEPOINT:
22155 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22156 // this point in the process. We diverge later.
22157 return emitPatchPoint(MI, BB);
22159 case TargetOpcode::STACKMAP:
22160 case TargetOpcode::PATCHPOINT:
22161 return emitPatchPoint(MI, BB);
22163 case X86::VFMADDPDr213r:
22164 case X86::VFMADDPSr213r:
22165 case X86::VFMADDSDr213r:
22166 case X86::VFMADDSSr213r:
22167 case X86::VFMSUBPDr213r:
22168 case X86::VFMSUBPSr213r:
22169 case X86::VFMSUBSDr213r:
22170 case X86::VFMSUBSSr213r:
22171 case X86::VFNMADDPDr213r:
22172 case X86::VFNMADDPSr213r:
22173 case X86::VFNMADDSDr213r:
22174 case X86::VFNMADDSSr213r:
22175 case X86::VFNMSUBPDr213r:
22176 case X86::VFNMSUBPSr213r:
22177 case X86::VFNMSUBSDr213r:
22178 case X86::VFNMSUBSSr213r:
22179 case X86::VFMADDSUBPDr213r:
22180 case X86::VFMADDSUBPSr213r:
22181 case X86::VFMSUBADDPDr213r:
22182 case X86::VFMSUBADDPSr213r:
22183 case X86::VFMADDPDr213rY:
22184 case X86::VFMADDPSr213rY:
22185 case X86::VFMSUBPDr213rY:
22186 case X86::VFMSUBPSr213rY:
22187 case X86::VFNMADDPDr213rY:
22188 case X86::VFNMADDPSr213rY:
22189 case X86::VFNMSUBPDr213rY:
22190 case X86::VFNMSUBPSr213rY:
22191 case X86::VFMADDSUBPDr213rY:
22192 case X86::VFMADDSUBPSr213rY:
22193 case X86::VFMSUBADDPDr213rY:
22194 case X86::VFMSUBADDPSr213rY:
22195 return emitFMA3Instr(MI, BB);
22199 //===----------------------------------------------------------------------===//
22200 // X86 Optimization Hooks
22201 //===----------------------------------------------------------------------===//
22203 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22206 const SelectionDAG &DAG,
22207 unsigned Depth) const {
22208 unsigned BitWidth = KnownZero.getBitWidth();
22209 unsigned Opc = Op.getOpcode();
22210 assert((Opc >= ISD::BUILTIN_OP_END ||
22211 Opc == ISD::INTRINSIC_WO_CHAIN ||
22212 Opc == ISD::INTRINSIC_W_CHAIN ||
22213 Opc == ISD::INTRINSIC_VOID) &&
22214 "Should use MaskedValueIsZero if you don't know whether Op"
22215 " is a target node!");
22217 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22231 // These nodes' second result is a boolean.
22232 if (Op.getResNo() == 0)
22235 case X86ISD::SETCC:
22236 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22238 case ISD::INTRINSIC_WO_CHAIN: {
22239 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22240 unsigned NumLoBits = 0;
22243 case Intrinsic::x86_sse_movmsk_ps:
22244 case Intrinsic::x86_avx_movmsk_ps_256:
22245 case Intrinsic::x86_sse2_movmsk_pd:
22246 case Intrinsic::x86_avx_movmsk_pd_256:
22247 case Intrinsic::x86_mmx_pmovmskb:
22248 case Intrinsic::x86_sse2_pmovmskb_128:
22249 case Intrinsic::x86_avx2_pmovmskb: {
22250 // High bits of movmskp{s|d}, pmovmskb are known zero.
22252 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22253 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22254 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22255 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22256 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22257 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22258 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22259 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22261 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22270 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22272 const SelectionDAG &,
22273 unsigned Depth) const {
22274 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22275 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22276 return Op.getValueType().getScalarSizeInBits();
22282 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22283 /// node is a GlobalAddress + offset.
22284 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22285 const GlobalValue* &GA,
22286 int64_t &Offset) const {
22287 if (N->getOpcode() == X86ISD::Wrapper) {
22288 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22289 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22290 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22294 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22297 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22298 /// same as extracting the high 128-bit part of 256-bit vector and then
22299 /// inserting the result into the low part of a new 256-bit vector
22300 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22301 EVT VT = SVOp->getValueType(0);
22302 unsigned NumElems = VT.getVectorNumElements();
22304 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22305 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22306 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22307 SVOp->getMaskElt(j) >= 0)
22313 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22314 /// same as extracting the low 128-bit part of 256-bit vector and then
22315 /// inserting the result into the high part of a new 256-bit vector
22316 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22317 EVT VT = SVOp->getValueType(0);
22318 unsigned NumElems = VT.getVectorNumElements();
22320 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22321 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22322 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22323 SVOp->getMaskElt(j) >= 0)
22329 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22330 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22331 TargetLowering::DAGCombinerInfo &DCI,
22332 const X86Subtarget* Subtarget) {
22334 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22335 SDValue V1 = SVOp->getOperand(0);
22336 SDValue V2 = SVOp->getOperand(1);
22337 EVT VT = SVOp->getValueType(0);
22338 unsigned NumElems = VT.getVectorNumElements();
22340 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22341 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22345 // V UNDEF BUILD_VECTOR UNDEF
22347 // CONCAT_VECTOR CONCAT_VECTOR
22350 // RESULT: V + zero extended
22352 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22353 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22354 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22357 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22360 // To match the shuffle mask, the first half of the mask should
22361 // be exactly the first vector, and all the rest a splat with the
22362 // first element of the second one.
22363 for (unsigned i = 0; i != NumElems/2; ++i)
22364 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22365 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22368 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22369 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22370 if (Ld->hasNUsesOfValue(1, 0)) {
22371 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22372 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22374 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22376 Ld->getPointerInfo(),
22377 Ld->getAlignment(),
22378 false/*isVolatile*/, true/*ReadMem*/,
22379 false/*WriteMem*/);
22381 // Make sure the newly-created LOAD is in the same position as Ld in
22382 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22383 // and update uses of Ld's output chain to use the TokenFactor.
22384 if (Ld->hasAnyUseOfValue(1)) {
22385 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22386 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22387 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22388 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22389 SDValue(ResNode.getNode(), 1));
22392 return DAG.getBitcast(VT, ResNode);
22396 // Emit a zeroed vector and insert the desired subvector on its
22398 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22399 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22400 return DCI.CombineTo(N, InsV);
22403 //===--------------------------------------------------------------------===//
22404 // Combine some shuffles into subvector extracts and inserts:
22407 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22408 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22409 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22410 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22411 return DCI.CombineTo(N, InsV);
22414 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22415 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22416 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22417 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22418 return DCI.CombineTo(N, InsV);
22424 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22427 /// This is the leaf of the recursive combinine below. When we have found some
22428 /// chain of single-use x86 shuffle instructions and accumulated the combined
22429 /// shuffle mask represented by them, this will try to pattern match that mask
22430 /// into either a single instruction if there is a special purpose instruction
22431 /// for this operation, or into a PSHUFB instruction which is a fully general
22432 /// instruction but should only be used to replace chains over a certain depth.
22433 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22434 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22435 TargetLowering::DAGCombinerInfo &DCI,
22436 const X86Subtarget *Subtarget) {
22437 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22439 // Find the operand that enters the chain. Note that multiple uses are OK
22440 // here, we're not going to remove the operand we find.
22441 SDValue Input = Op.getOperand(0);
22442 while (Input.getOpcode() == ISD::BITCAST)
22443 Input = Input.getOperand(0);
22445 MVT VT = Input.getSimpleValueType();
22446 MVT RootVT = Root.getSimpleValueType();
22449 if (Mask.size() == 1) {
22450 int Index = Mask[0];
22451 assert((Index >= 0 || Index == SM_SentinelUndef ||
22452 Index == SM_SentinelZero) &&
22453 "Invalid shuffle index found!");
22455 // We may end up with an accumulated mask of size 1 as a result of
22456 // widening of shuffle operands (see function canWidenShuffleElements).
22457 // If the only shuffle index is equal to SM_SentinelZero then propagate
22458 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22459 // mask, and therefore the entire chain of shuffles can be folded away.
22460 if (Index == SM_SentinelZero)
22461 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22463 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22468 // Use the float domain if the operand type is a floating point type.
22469 bool FloatDomain = VT.isFloatingPoint();
22471 // For floating point shuffles, we don't have free copies in the shuffle
22472 // instructions or the ability to load as part of the instruction, so
22473 // canonicalize their shuffles to UNPCK or MOV variants.
22475 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22476 // vectors because it can have a load folded into it that UNPCK cannot. This
22477 // doesn't preclude something switching to the shorter encoding post-RA.
22479 // FIXME: Should teach these routines about AVX vector widths.
22480 if (FloatDomain && VT.is128BitVector()) {
22481 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22482 bool Lo = Mask.equals({0, 0});
22485 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22486 // is no slower than UNPCKLPD but has the option to fold the input operand
22487 // into even an unaligned memory load.
22488 if (Lo && Subtarget->hasSSE3()) {
22489 Shuffle = X86ISD::MOVDDUP;
22490 ShuffleVT = MVT::v2f64;
22492 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22493 // than the UNPCK variants.
22494 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22495 ShuffleVT = MVT::v4f32;
22497 if (Depth == 1 && Root->getOpcode() == Shuffle)
22498 return false; // Nothing to do!
22499 Op = DAG.getBitcast(ShuffleVT, Input);
22500 DCI.AddToWorklist(Op.getNode());
22501 if (Shuffle == X86ISD::MOVDDUP)
22502 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22504 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22505 DCI.AddToWorklist(Op.getNode());
22506 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22510 if (Subtarget->hasSSE3() &&
22511 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22512 bool Lo = Mask.equals({0, 0, 2, 2});
22513 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22514 MVT ShuffleVT = MVT::v4f32;
22515 if (Depth == 1 && Root->getOpcode() == Shuffle)
22516 return false; // Nothing to do!
22517 Op = DAG.getBitcast(ShuffleVT, Input);
22518 DCI.AddToWorklist(Op.getNode());
22519 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22520 DCI.AddToWorklist(Op.getNode());
22521 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22525 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22526 bool Lo = Mask.equals({0, 0, 1, 1});
22527 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22528 MVT ShuffleVT = MVT::v4f32;
22529 if (Depth == 1 && Root->getOpcode() == Shuffle)
22530 return false; // Nothing to do!
22531 Op = DAG.getBitcast(ShuffleVT, Input);
22532 DCI.AddToWorklist(Op.getNode());
22533 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22534 DCI.AddToWorklist(Op.getNode());
22535 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22541 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22542 // variants as none of these have single-instruction variants that are
22543 // superior to the UNPCK formulation.
22544 if (!FloatDomain && VT.is128BitVector() &&
22545 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22546 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22547 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22549 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22550 bool Lo = Mask[0] == 0;
22551 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22552 if (Depth == 1 && Root->getOpcode() == Shuffle)
22553 return false; // Nothing to do!
22555 switch (Mask.size()) {
22557 ShuffleVT = MVT::v8i16;
22560 ShuffleVT = MVT::v16i8;
22563 llvm_unreachable("Impossible mask size!");
22565 Op = DAG.getBitcast(ShuffleVT, Input);
22566 DCI.AddToWorklist(Op.getNode());
22567 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22568 DCI.AddToWorklist(Op.getNode());
22569 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22574 // Don't try to re-form single instruction chains under any circumstances now
22575 // that we've done encoding canonicalization for them.
22579 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22580 // can replace them with a single PSHUFB instruction profitably. Intel's
22581 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22582 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22583 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22584 SmallVector<SDValue, 16> PSHUFBMask;
22585 int NumBytes = VT.getSizeInBits() / 8;
22586 int Ratio = NumBytes / Mask.size();
22587 for (int i = 0; i < NumBytes; ++i) {
22588 if (Mask[i / Ratio] == SM_SentinelUndef) {
22589 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22592 int M = Mask[i / Ratio] != SM_SentinelZero
22593 ? Ratio * Mask[i / Ratio] + i % Ratio
22595 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22597 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22598 Op = DAG.getBitcast(ByteVT, Input);
22599 DCI.AddToWorklist(Op.getNode());
22600 SDValue PSHUFBMaskOp =
22601 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22602 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22603 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22604 DCI.AddToWorklist(Op.getNode());
22605 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22610 // Failed to find any combines.
22614 /// \brief Fully generic combining of x86 shuffle instructions.
22616 /// This should be the last combine run over the x86 shuffle instructions. Once
22617 /// they have been fully optimized, this will recursively consider all chains
22618 /// of single-use shuffle instructions, build a generic model of the cumulative
22619 /// shuffle operation, and check for simpler instructions which implement this
22620 /// operation. We use this primarily for two purposes:
22622 /// 1) Collapse generic shuffles to specialized single instructions when
22623 /// equivalent. In most cases, this is just an encoding size win, but
22624 /// sometimes we will collapse multiple generic shuffles into a single
22625 /// special-purpose shuffle.
22626 /// 2) Look for sequences of shuffle instructions with 3 or more total
22627 /// instructions, and replace them with the slightly more expensive SSSE3
22628 /// PSHUFB instruction if available. We do this as the last combining step
22629 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22630 /// a suitable short sequence of other instructions. The PHUFB will either
22631 /// use a register or have to read from memory and so is slightly (but only
22632 /// slightly) more expensive than the other shuffle instructions.
22634 /// Because this is inherently a quadratic operation (for each shuffle in
22635 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22636 /// This should never be an issue in practice as the shuffle lowering doesn't
22637 /// produce sequences of more than 8 instructions.
22639 /// FIXME: We will currently miss some cases where the redundant shuffling
22640 /// would simplify under the threshold for PSHUFB formation because of
22641 /// combine-ordering. To fix this, we should do the redundant instruction
22642 /// combining in this recursive walk.
22643 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22644 ArrayRef<int> RootMask,
22645 int Depth, bool HasPSHUFB,
22647 TargetLowering::DAGCombinerInfo &DCI,
22648 const X86Subtarget *Subtarget) {
22649 // Bound the depth of our recursive combine because this is ultimately
22650 // quadratic in nature.
22654 // Directly rip through bitcasts to find the underlying operand.
22655 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22656 Op = Op.getOperand(0);
22658 MVT VT = Op.getSimpleValueType();
22659 if (!VT.isVector())
22660 return false; // Bail if we hit a non-vector.
22662 assert(Root.getSimpleValueType().isVector() &&
22663 "Shuffles operate on vector types!");
22664 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22665 "Can only combine shuffles of the same vector register size.");
22667 if (!isTargetShuffle(Op.getOpcode()))
22669 SmallVector<int, 16> OpMask;
22671 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22672 // We only can combine unary shuffles which we can decode the mask for.
22673 if (!HaveMask || !IsUnary)
22676 assert(VT.getVectorNumElements() == OpMask.size() &&
22677 "Different mask size from vector size!");
22678 assert(((RootMask.size() > OpMask.size() &&
22679 RootMask.size() % OpMask.size() == 0) ||
22680 (OpMask.size() > RootMask.size() &&
22681 OpMask.size() % RootMask.size() == 0) ||
22682 OpMask.size() == RootMask.size()) &&
22683 "The smaller number of elements must divide the larger.");
22684 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22685 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22686 assert(((RootRatio == 1 && OpRatio == 1) ||
22687 (RootRatio == 1) != (OpRatio == 1)) &&
22688 "Must not have a ratio for both incoming and op masks!");
22690 SmallVector<int, 16> Mask;
22691 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22693 // Merge this shuffle operation's mask into our accumulated mask. Note that
22694 // this shuffle's mask will be the first applied to the input, followed by the
22695 // root mask to get us all the way to the root value arrangement. The reason
22696 // for this order is that we are recursing up the operation chain.
22697 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22698 int RootIdx = i / RootRatio;
22699 if (RootMask[RootIdx] < 0) {
22700 // This is a zero or undef lane, we're done.
22701 Mask.push_back(RootMask[RootIdx]);
22705 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22706 int OpIdx = RootMaskedIdx / OpRatio;
22707 if (OpMask[OpIdx] < 0) {
22708 // The incoming lanes are zero or undef, it doesn't matter which ones we
22710 Mask.push_back(OpMask[OpIdx]);
22714 // Ok, we have non-zero lanes, map them through.
22715 Mask.push_back(OpMask[OpIdx] * OpRatio +
22716 RootMaskedIdx % OpRatio);
22719 // See if we can recurse into the operand to combine more things.
22720 switch (Op.getOpcode()) {
22721 case X86ISD::PSHUFB:
22723 case X86ISD::PSHUFD:
22724 case X86ISD::PSHUFHW:
22725 case X86ISD::PSHUFLW:
22726 if (Op.getOperand(0).hasOneUse() &&
22727 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22728 HasPSHUFB, DAG, DCI, Subtarget))
22732 case X86ISD::UNPCKL:
22733 case X86ISD::UNPCKH:
22734 assert(Op.getOperand(0) == Op.getOperand(1) &&
22735 "We only combine unary shuffles!");
22736 // We can't check for single use, we have to check that this shuffle is the
22738 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22739 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22740 HasPSHUFB, DAG, DCI, Subtarget))
22745 // Minor canonicalization of the accumulated shuffle mask to make it easier
22746 // to match below. All this does is detect masks with squential pairs of
22747 // elements, and shrink them to the half-width mask. It does this in a loop
22748 // so it will reduce the size of the mask to the minimal width mask which
22749 // performs an equivalent shuffle.
22750 SmallVector<int, 16> WidenedMask;
22751 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22752 Mask = std::move(WidenedMask);
22753 WidenedMask.clear();
22756 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22760 /// \brief Get the PSHUF-style mask from PSHUF node.
22762 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22763 /// PSHUF-style masks that can be reused with such instructions.
22764 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22765 MVT VT = N.getSimpleValueType();
22766 SmallVector<int, 4> Mask;
22768 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22772 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22773 // matter. Check that the upper masks are repeats and remove them.
22774 if (VT.getSizeInBits() > 128) {
22775 int LaneElts = 128 / VT.getScalarSizeInBits();
22777 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22778 for (int j = 0; j < LaneElts; ++j)
22779 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22780 "Mask doesn't repeat in high 128-bit lanes!");
22782 Mask.resize(LaneElts);
22785 switch (N.getOpcode()) {
22786 case X86ISD::PSHUFD:
22788 case X86ISD::PSHUFLW:
22791 case X86ISD::PSHUFHW:
22792 Mask.erase(Mask.begin(), Mask.begin() + 4);
22793 for (int &M : Mask)
22797 llvm_unreachable("No valid shuffle instruction found!");
22801 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22803 /// We walk up the chain and look for a combinable shuffle, skipping over
22804 /// shuffles that we could hoist this shuffle's transformation past without
22805 /// altering anything.
22807 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22809 TargetLowering::DAGCombinerInfo &DCI) {
22810 assert(N.getOpcode() == X86ISD::PSHUFD &&
22811 "Called with something other than an x86 128-bit half shuffle!");
22814 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22815 // of the shuffles in the chain so that we can form a fresh chain to replace
22817 SmallVector<SDValue, 8> Chain;
22818 SDValue V = N.getOperand(0);
22819 for (; V.hasOneUse(); V = V.getOperand(0)) {
22820 switch (V.getOpcode()) {
22822 return SDValue(); // Nothing combined!
22825 // Skip bitcasts as we always know the type for the target specific
22829 case X86ISD::PSHUFD:
22830 // Found another dword shuffle.
22833 case X86ISD::PSHUFLW:
22834 // Check that the low words (being shuffled) are the identity in the
22835 // dword shuffle, and the high words are self-contained.
22836 if (Mask[0] != 0 || Mask[1] != 1 ||
22837 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22840 Chain.push_back(V);
22843 case X86ISD::PSHUFHW:
22844 // Check that the high words (being shuffled) are the identity in the
22845 // dword shuffle, and the low words are self-contained.
22846 if (Mask[2] != 2 || Mask[3] != 3 ||
22847 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22850 Chain.push_back(V);
22853 case X86ISD::UNPCKL:
22854 case X86ISD::UNPCKH:
22855 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22856 // shuffle into a preceding word shuffle.
22857 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
22858 V.getSimpleValueType().getVectorElementType() != MVT::i16)
22861 // Search for a half-shuffle which we can combine with.
22862 unsigned CombineOp =
22863 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22864 if (V.getOperand(0) != V.getOperand(1) ||
22865 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22867 Chain.push_back(V);
22868 V = V.getOperand(0);
22870 switch (V.getOpcode()) {
22872 return SDValue(); // Nothing to combine.
22874 case X86ISD::PSHUFLW:
22875 case X86ISD::PSHUFHW:
22876 if (V.getOpcode() == CombineOp)
22879 Chain.push_back(V);
22883 V = V.getOperand(0);
22887 } while (V.hasOneUse());
22890 // Break out of the loop if we break out of the switch.
22894 if (!V.hasOneUse())
22895 // We fell out of the loop without finding a viable combining instruction.
22898 // Merge this node's mask and our incoming mask.
22899 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22900 for (int &M : Mask)
22902 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22903 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22905 // Rebuild the chain around this new shuffle.
22906 while (!Chain.empty()) {
22907 SDValue W = Chain.pop_back_val();
22909 if (V.getValueType() != W.getOperand(0).getValueType())
22910 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22912 switch (W.getOpcode()) {
22914 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22916 case X86ISD::UNPCKL:
22917 case X86ISD::UNPCKH:
22918 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22921 case X86ISD::PSHUFD:
22922 case X86ISD::PSHUFLW:
22923 case X86ISD::PSHUFHW:
22924 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22928 if (V.getValueType() != N.getValueType())
22929 V = DAG.getBitcast(N.getValueType(), V);
22931 // Return the new chain to replace N.
22935 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22938 /// We walk up the chain, skipping shuffles of the other half and looking
22939 /// through shuffles which switch halves trying to find a shuffle of the same
22940 /// pair of dwords.
22941 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22943 TargetLowering::DAGCombinerInfo &DCI) {
22945 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22946 "Called with something other than an x86 128-bit half shuffle!");
22948 unsigned CombineOpcode = N.getOpcode();
22950 // Walk up a single-use chain looking for a combinable shuffle.
22951 SDValue V = N.getOperand(0);
22952 for (; V.hasOneUse(); V = V.getOperand(0)) {
22953 switch (V.getOpcode()) {
22955 return false; // Nothing combined!
22958 // Skip bitcasts as we always know the type for the target specific
22962 case X86ISD::PSHUFLW:
22963 case X86ISD::PSHUFHW:
22964 if (V.getOpcode() == CombineOpcode)
22967 // Other-half shuffles are no-ops.
22970 // Break out of the loop if we break out of the switch.
22974 if (!V.hasOneUse())
22975 // We fell out of the loop without finding a viable combining instruction.
22978 // Combine away the bottom node as its shuffle will be accumulated into
22979 // a preceding shuffle.
22980 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22982 // Record the old value.
22985 // Merge this node's mask and our incoming mask (adjusted to account for all
22986 // the pshufd instructions encountered).
22987 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22988 for (int &M : Mask)
22990 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22991 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22993 // Check that the shuffles didn't cancel each other out. If not, we need to
22994 // combine to the new one.
22996 // Replace the combinable shuffle with the combined one, updating all users
22997 // so that we re-evaluate the chain here.
22998 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23003 /// \brief Try to combine x86 target specific shuffles.
23004 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23005 TargetLowering::DAGCombinerInfo &DCI,
23006 const X86Subtarget *Subtarget) {
23008 MVT VT = N.getSimpleValueType();
23009 SmallVector<int, 4> Mask;
23011 switch (N.getOpcode()) {
23012 case X86ISD::PSHUFD:
23013 case X86ISD::PSHUFLW:
23014 case X86ISD::PSHUFHW:
23015 Mask = getPSHUFShuffleMask(N);
23016 assert(Mask.size() == 4);
23018 case X86ISD::UNPCKL: {
23019 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23020 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23021 // moves upper half elements into the lower half part. For example:
23023 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23025 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23027 // will be combined to:
23029 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23031 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23032 // happen due to advanced instructions.
23033 if (!VT.is128BitVector())
23036 auto Op0 = N.getOperand(0);
23037 auto Op1 = N.getOperand(1);
23038 if (Op0.getOpcode() == ISD::UNDEF &&
23039 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23040 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23042 unsigned NumElts = VT.getVectorNumElements();
23043 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23044 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23047 auto ShufOp = Op1.getOperand(0);
23048 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23049 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23057 // Nuke no-op shuffles that show up after combining.
23058 if (isNoopShuffleMask(Mask))
23059 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23061 // Look for simplifications involving one or two shuffle instructions.
23062 SDValue V = N.getOperand(0);
23063 switch (N.getOpcode()) {
23066 case X86ISD::PSHUFLW:
23067 case X86ISD::PSHUFHW:
23068 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23070 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23071 return SDValue(); // We combined away this shuffle, so we're done.
23073 // See if this reduces to a PSHUFD which is no more expensive and can
23074 // combine with more operations. Note that it has to at least flip the
23075 // dwords as otherwise it would have been removed as a no-op.
23076 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23077 int DMask[] = {0, 1, 2, 3};
23078 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23079 DMask[DOffset + 0] = DOffset + 1;
23080 DMask[DOffset + 1] = DOffset + 0;
23081 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23082 V = DAG.getBitcast(DVT, V);
23083 DCI.AddToWorklist(V.getNode());
23084 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23085 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23086 DCI.AddToWorklist(V.getNode());
23087 return DAG.getBitcast(VT, V);
23090 // Look for shuffle patterns which can be implemented as a single unpack.
23091 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23092 // only works when we have a PSHUFD followed by two half-shuffles.
23093 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23094 (V.getOpcode() == X86ISD::PSHUFLW ||
23095 V.getOpcode() == X86ISD::PSHUFHW) &&
23096 V.getOpcode() != N.getOpcode() &&
23098 SDValue D = V.getOperand(0);
23099 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23100 D = D.getOperand(0);
23101 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23102 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23103 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23104 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23105 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23107 for (int i = 0; i < 4; ++i) {
23108 WordMask[i + NOffset] = Mask[i] + NOffset;
23109 WordMask[i + VOffset] = VMask[i] + VOffset;
23111 // Map the word mask through the DWord mask.
23113 for (int i = 0; i < 8; ++i)
23114 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23115 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23116 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23117 // We can replace all three shuffles with an unpack.
23118 V = DAG.getBitcast(VT, D.getOperand(0));
23119 DCI.AddToWorklist(V.getNode());
23120 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23129 case X86ISD::PSHUFD:
23130 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23139 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23141 /// We combine this directly on the abstract vector shuffle nodes so it is
23142 /// easier to generically match. We also insert dummy vector shuffle nodes for
23143 /// the operands which explicitly discard the lanes which are unused by this
23144 /// operation to try to flow through the rest of the combiner the fact that
23145 /// they're unused.
23146 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23148 EVT VT = N->getValueType(0);
23150 // We only handle target-independent shuffles.
23151 // FIXME: It would be easy and harmless to use the target shuffle mask
23152 // extraction tool to support more.
23153 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23156 auto *SVN = cast<ShuffleVectorSDNode>(N);
23157 ArrayRef<int> Mask = SVN->getMask();
23158 SDValue V1 = N->getOperand(0);
23159 SDValue V2 = N->getOperand(1);
23161 // We require the first shuffle operand to be the SUB node, and the second to
23162 // be the ADD node.
23163 // FIXME: We should support the commuted patterns.
23164 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
23167 // If there are other uses of these operations we can't fold them.
23168 if (!V1->hasOneUse() || !V2->hasOneUse())
23171 // Ensure that both operations have the same operands. Note that we can
23172 // commute the FADD operands.
23173 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23174 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23175 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23178 // We're looking for blends between FADD and FSUB nodes. We insist on these
23179 // nodes being lined up in a specific expected pattern.
23180 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23181 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23182 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23185 // Only specific types are legal at this point, assert so we notice if and
23186 // when these change.
23187 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23188 VT == MVT::v4f64) &&
23189 "Unknown vector type encountered!");
23191 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23194 /// PerformShuffleCombine - Performs several different shuffle combines.
23195 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23196 TargetLowering::DAGCombinerInfo &DCI,
23197 const X86Subtarget *Subtarget) {
23199 SDValue N0 = N->getOperand(0);
23200 SDValue N1 = N->getOperand(1);
23201 EVT VT = N->getValueType(0);
23203 // Don't create instructions with illegal types after legalize types has run.
23204 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23205 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23208 // If we have legalized the vector types, look for blends of FADD and FSUB
23209 // nodes that we can fuse into an ADDSUB node.
23210 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23211 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23214 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23215 if (Subtarget->hasFp256() && VT.is256BitVector() &&
23216 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23217 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23219 // During Type Legalization, when promoting illegal vector types,
23220 // the backend might introduce new shuffle dag nodes and bitcasts.
23222 // This code performs the following transformation:
23223 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23224 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23226 // We do this only if both the bitcast and the BINOP dag nodes have
23227 // one use. Also, perform this transformation only if the new binary
23228 // operation is legal. This is to avoid introducing dag nodes that
23229 // potentially need to be further expanded (or custom lowered) into a
23230 // less optimal sequence of dag nodes.
23231 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23232 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23233 N0.getOpcode() == ISD::BITCAST) {
23234 SDValue BC0 = N0.getOperand(0);
23235 EVT SVT = BC0.getValueType();
23236 unsigned Opcode = BC0.getOpcode();
23237 unsigned NumElts = VT.getVectorNumElements();
23239 if (BC0.hasOneUse() && SVT.isVector() &&
23240 SVT.getVectorNumElements() * 2 == NumElts &&
23241 TLI.isOperationLegal(Opcode, VT)) {
23242 bool CanFold = false;
23254 unsigned SVTNumElts = SVT.getVectorNumElements();
23255 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23256 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23257 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23258 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23259 CanFold = SVOp->getMaskElt(i) < 0;
23262 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23263 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23264 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23265 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23270 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23271 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23272 // consecutive, non-overlapping, and in the right order.
23273 SmallVector<SDValue, 16> Elts;
23274 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23275 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23277 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23280 if (isTargetShuffle(N->getOpcode())) {
23282 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23283 if (Shuffle.getNode())
23286 // Try recursively combining arbitrary sequences of x86 shuffle
23287 // instructions into higher-order shuffles. We do this after combining
23288 // specific PSHUF instruction sequences into their minimal form so that we
23289 // can evaluate how many specialized shuffle instructions are involved in
23290 // a particular chain.
23291 SmallVector<int, 1> NonceMask; // Just a placeholder.
23292 NonceMask.push_back(0);
23293 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23294 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23296 return SDValue(); // This routine will use CombineTo to replace N.
23302 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23303 /// specific shuffle of a load can be folded into a single element load.
23304 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23305 /// shuffles have been custom lowered so we need to handle those here.
23306 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23307 TargetLowering::DAGCombinerInfo &DCI) {
23308 if (DCI.isBeforeLegalizeOps())
23311 SDValue InVec = N->getOperand(0);
23312 SDValue EltNo = N->getOperand(1);
23314 if (!isa<ConstantSDNode>(EltNo))
23317 EVT OriginalVT = InVec.getValueType();
23319 if (InVec.getOpcode() == ISD::BITCAST) {
23320 // Don't duplicate a load with other uses.
23321 if (!InVec.hasOneUse())
23323 EVT BCVT = InVec.getOperand(0).getValueType();
23324 if (!BCVT.isVector() ||
23325 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23327 InVec = InVec.getOperand(0);
23330 EVT CurrentVT = InVec.getValueType();
23332 if (!isTargetShuffle(InVec.getOpcode()))
23335 // Don't duplicate a load with other uses.
23336 if (!InVec.hasOneUse())
23339 SmallVector<int, 16> ShuffleMask;
23341 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23342 ShuffleMask, UnaryShuffle))
23345 // Select the input vector, guarding against out of range extract vector.
23346 unsigned NumElems = CurrentVT.getVectorNumElements();
23347 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23348 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23349 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23350 : InVec.getOperand(1);
23352 // If inputs to shuffle are the same for both ops, then allow 2 uses
23353 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23354 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23356 if (LdNode.getOpcode() == ISD::BITCAST) {
23357 // Don't duplicate a load with other uses.
23358 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23361 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23362 LdNode = LdNode.getOperand(0);
23365 if (!ISD::isNormalLoad(LdNode.getNode()))
23368 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23370 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23373 EVT EltVT = N->getValueType(0);
23374 // If there's a bitcast before the shuffle, check if the load type and
23375 // alignment is valid.
23376 unsigned Align = LN0->getAlignment();
23377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23378 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23379 EltVT.getTypeForEVT(*DAG.getContext()));
23381 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23384 // All checks match so transform back to vector_shuffle so that DAG combiner
23385 // can finish the job
23388 // Create shuffle node taking into account the case that its a unary shuffle
23389 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23390 : InVec.getOperand(1);
23391 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23392 InVec.getOperand(0), Shuffle,
23394 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23395 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23399 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23400 const X86Subtarget *Subtarget) {
23401 SDValue N0 = N->getOperand(0);
23402 EVT VT = N->getValueType(0);
23404 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23405 // special and don't usually play with other vector types, it's better to
23406 // handle them early to be sure we emit efficient code by avoiding
23407 // store-load conversions.
23408 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23409 N0.getValueType() == MVT::v2i32 &&
23410 isa<ConstantSDNode>(N0.getOperand(1))) {
23411 SDValue N00 = N0->getOperand(0);
23412 if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
23413 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23416 // Convert a bitcasted integer logic operation that has one bitcasted
23417 // floating-point operand and one constant operand into a floating-point
23418 // logic operation. This may create a load of the constant, but that is
23419 // cheaper than materializing the constant in an integer register and
23420 // transferring it to an SSE register or transferring the SSE operand to
23421 // integer register and back.
23423 switch (N0.getOpcode()) {
23424 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23425 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23426 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23427 default: return SDValue();
23429 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23430 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23431 isa<ConstantSDNode>(N0.getOperand(1)) &&
23432 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23433 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23434 SDValue N000 = N0.getOperand(0).getOperand(0);
23435 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23436 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23442 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23443 /// generation and convert it from being a bunch of shuffles and extracts
23444 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23445 /// storing the value and loading scalars back, while for x64 we should
23446 /// use 64-bit extracts and shifts.
23447 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23448 TargetLowering::DAGCombinerInfo &DCI) {
23449 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23452 SDValue InputVector = N->getOperand(0);
23453 SDLoc dl(InputVector);
23454 // Detect mmx to i32 conversion through a v2i32 elt extract.
23455 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23456 N->getValueType(0) == MVT::i32 &&
23457 InputVector.getValueType() == MVT::v2i32) {
23459 // The bitcast source is a direct mmx result.
23460 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23461 if (MMXSrc.getValueType() == MVT::x86mmx)
23462 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23463 N->getValueType(0),
23464 InputVector.getNode()->getOperand(0));
23466 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23467 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23468 MMXSrc.getValueType() == MVT::i64) {
23469 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23470 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23471 MMXSrcOp.getValueType() == MVT::v1i64 &&
23472 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23473 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23474 N->getValueType(0), MMXSrcOp.getOperand(0));
23478 EVT VT = N->getValueType(0);
23480 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23481 InputVector.getOpcode() == ISD::BITCAST &&
23482 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23483 uint64_t ExtractedElt =
23484 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23485 uint64_t InputValue =
23486 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23487 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23488 return DAG.getConstant(Res, dl, MVT::i1);
23490 // Only operate on vectors of 4 elements, where the alternative shuffling
23491 // gets to be more expensive.
23492 if (InputVector.getValueType() != MVT::v4i32)
23495 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23496 // single use which is a sign-extend or zero-extend, and all elements are
23498 SmallVector<SDNode *, 4> Uses;
23499 unsigned ExtractedElements = 0;
23500 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23501 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23502 if (UI.getUse().getResNo() != InputVector.getResNo())
23505 SDNode *Extract = *UI;
23506 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23509 if (Extract->getValueType(0) != MVT::i32)
23511 if (!Extract->hasOneUse())
23513 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23514 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23516 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23519 // Record which element was extracted.
23520 ExtractedElements |=
23521 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23523 Uses.push_back(Extract);
23526 // If not all the elements were used, this may not be worthwhile.
23527 if (ExtractedElements != 15)
23530 // Ok, we've now decided to do the transformation.
23531 // If 64-bit shifts are legal, use the extract-shift sequence,
23532 // otherwise bounce the vector off the cache.
23533 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23536 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23537 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23538 auto &DL = DAG.getDataLayout();
23539 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23540 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23541 DAG.getConstant(0, dl, VecIdxTy));
23542 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23543 DAG.getConstant(1, dl, VecIdxTy));
23545 SDValue ShAmt = DAG.getConstant(
23546 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23547 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23548 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23549 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23550 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23551 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23552 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23554 // Store the value to a temporary stack slot.
23555 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23556 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23557 MachinePointerInfo(), false, false, 0);
23559 EVT ElementType = InputVector.getValueType().getVectorElementType();
23560 unsigned EltSize = ElementType.getSizeInBits() / 8;
23562 // Replace each use (extract) with a load of the appropriate element.
23563 for (unsigned i = 0; i < 4; ++i) {
23564 uint64_t Offset = EltSize * i;
23565 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23566 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23568 SDValue ScalarAddr =
23569 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23571 // Load the scalar.
23572 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23573 ScalarAddr, MachinePointerInfo(),
23574 false, false, false, 0);
23579 // Replace the extracts
23580 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23581 UE = Uses.end(); UI != UE; ++UI) {
23582 SDNode *Extract = *UI;
23584 SDValue Idx = Extract->getOperand(1);
23585 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23586 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23589 // The replacement was made in place; don't return anything.
23594 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23595 const X86Subtarget *Subtarget) {
23597 SDValue Cond = N->getOperand(0);
23598 SDValue LHS = N->getOperand(1);
23599 SDValue RHS = N->getOperand(2);
23601 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23602 SDValue CondSrc = Cond->getOperand(0);
23603 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23604 Cond = CondSrc->getOperand(0);
23607 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23610 // A vselect where all conditions and data are constants can be optimized into
23611 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23612 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23613 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23616 unsigned MaskValue = 0;
23617 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23620 MVT VT = N->getSimpleValueType(0);
23621 unsigned NumElems = VT.getVectorNumElements();
23622 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23623 for (unsigned i = 0; i < NumElems; ++i) {
23624 // Be sure we emit undef where we can.
23625 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23626 ShuffleMask[i] = -1;
23628 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23631 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23632 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23634 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23637 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23639 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23640 TargetLowering::DAGCombinerInfo &DCI,
23641 const X86Subtarget *Subtarget) {
23643 SDValue Cond = N->getOperand(0);
23644 // Get the LHS/RHS of the select.
23645 SDValue LHS = N->getOperand(1);
23646 SDValue RHS = N->getOperand(2);
23647 EVT VT = LHS.getValueType();
23648 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23650 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23651 // instructions match the semantics of the common C idiom x<y?x:y but not
23652 // x<=y?x:y, because of how they handle negative zero (which can be
23653 // ignored in unsafe-math mode).
23654 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23655 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23656 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23657 (Subtarget->hasSSE2() ||
23658 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23659 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23661 unsigned Opcode = 0;
23662 // Check for x CC y ? x : y.
23663 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23664 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23668 // Converting this to a min would handle NaNs incorrectly, and swapping
23669 // the operands would cause it to handle comparisons between positive
23670 // and negative zero incorrectly.
23671 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23672 if (!DAG.getTarget().Options.UnsafeFPMath &&
23673 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23675 std::swap(LHS, RHS);
23677 Opcode = X86ISD::FMIN;
23680 // Converting this to a min would handle comparisons between positive
23681 // and negative zero incorrectly.
23682 if (!DAG.getTarget().Options.UnsafeFPMath &&
23683 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23685 Opcode = X86ISD::FMIN;
23688 // Converting this to a min would handle both negative zeros and NaNs
23689 // incorrectly, but we can swap the operands to fix both.
23690 std::swap(LHS, RHS);
23694 Opcode = X86ISD::FMIN;
23698 // Converting this to a max would handle comparisons between positive
23699 // and negative zero incorrectly.
23700 if (!DAG.getTarget().Options.UnsafeFPMath &&
23701 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23703 Opcode = X86ISD::FMAX;
23706 // Converting this to a max would handle NaNs incorrectly, and swapping
23707 // the operands would cause it to handle comparisons between positive
23708 // and negative zero incorrectly.
23709 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23710 if (!DAG.getTarget().Options.UnsafeFPMath &&
23711 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23713 std::swap(LHS, RHS);
23715 Opcode = X86ISD::FMAX;
23718 // Converting this to a max would handle both negative zeros and NaNs
23719 // incorrectly, but we can swap the operands to fix both.
23720 std::swap(LHS, RHS);
23724 Opcode = X86ISD::FMAX;
23727 // Check for x CC y ? y : x -- a min/max with reversed arms.
23728 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23729 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23733 // Converting this to a min would handle comparisons between positive
23734 // and negative zero incorrectly, and swapping the operands would
23735 // cause it to handle NaNs incorrectly.
23736 if (!DAG.getTarget().Options.UnsafeFPMath &&
23737 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23738 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23740 std::swap(LHS, RHS);
23742 Opcode = X86ISD::FMIN;
23745 // Converting this to a min would handle NaNs incorrectly.
23746 if (!DAG.getTarget().Options.UnsafeFPMath &&
23747 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23749 Opcode = X86ISD::FMIN;
23752 // Converting this to a min would handle both negative zeros and NaNs
23753 // incorrectly, but we can swap the operands to fix both.
23754 std::swap(LHS, RHS);
23758 Opcode = X86ISD::FMIN;
23762 // Converting this to a max would handle NaNs incorrectly.
23763 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23765 Opcode = X86ISD::FMAX;
23768 // Converting this to a max would handle comparisons between positive
23769 // and negative zero incorrectly, and swapping the operands would
23770 // cause it to handle NaNs incorrectly.
23771 if (!DAG.getTarget().Options.UnsafeFPMath &&
23772 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23773 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23775 std::swap(LHS, RHS);
23777 Opcode = X86ISD::FMAX;
23780 // Converting this to a max would handle both negative zeros and NaNs
23781 // incorrectly, but we can swap the operands to fix both.
23782 std::swap(LHS, RHS);
23786 Opcode = X86ISD::FMAX;
23792 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23795 EVT CondVT = Cond.getValueType();
23796 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23797 CondVT.getVectorElementType() == MVT::i1) {
23798 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23799 // lowering on KNL. In this case we convert it to
23800 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23801 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23802 // Since SKX these selects have a proper lowering.
23803 EVT OpVT = LHS.getValueType();
23804 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23805 (OpVT.getVectorElementType() == MVT::i8 ||
23806 OpVT.getVectorElementType() == MVT::i16) &&
23807 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23808 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23809 DCI.AddToWorklist(Cond.getNode());
23810 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23813 // If this is a select between two integer constants, try to do some
23815 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23816 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23817 // Don't do this for crazy integer types.
23818 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23819 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23820 // so that TrueC (the true value) is larger than FalseC.
23821 bool NeedsCondInvert = false;
23823 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23824 // Efficiently invertible.
23825 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23826 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23827 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23828 NeedsCondInvert = true;
23829 std::swap(TrueC, FalseC);
23832 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23833 if (FalseC->getAPIntValue() == 0 &&
23834 TrueC->getAPIntValue().isPowerOf2()) {
23835 if (NeedsCondInvert) // Invert the condition if needed.
23836 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23837 DAG.getConstant(1, DL, Cond.getValueType()));
23839 // Zero extend the condition if needed.
23840 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23842 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23843 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23844 DAG.getConstant(ShAmt, DL, MVT::i8));
23847 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23848 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23849 if (NeedsCondInvert) // Invert the condition if needed.
23850 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23851 DAG.getConstant(1, DL, Cond.getValueType()));
23853 // Zero extend the condition if needed.
23854 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23855 FalseC->getValueType(0), Cond);
23856 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23857 SDValue(FalseC, 0));
23860 // Optimize cases that will turn into an LEA instruction. This requires
23861 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23862 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23863 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23864 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23866 bool isFastMultiplier = false;
23868 switch ((unsigned char)Diff) {
23870 case 1: // result = add base, cond
23871 case 2: // result = lea base( , cond*2)
23872 case 3: // result = lea base(cond, cond*2)
23873 case 4: // result = lea base( , cond*4)
23874 case 5: // result = lea base(cond, cond*4)
23875 case 8: // result = lea base( , cond*8)
23876 case 9: // result = lea base(cond, cond*8)
23877 isFastMultiplier = true;
23882 if (isFastMultiplier) {
23883 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23884 if (NeedsCondInvert) // Invert the condition if needed.
23885 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23886 DAG.getConstant(1, DL, Cond.getValueType()));
23888 // Zero extend the condition if needed.
23889 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23891 // Scale the condition by the difference.
23893 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23894 DAG.getConstant(Diff, DL,
23895 Cond.getValueType()));
23897 // Add the base if non-zero.
23898 if (FalseC->getAPIntValue() != 0)
23899 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23900 SDValue(FalseC, 0));
23907 // Canonicalize max and min:
23908 // (x > y) ? x : y -> (x >= y) ? x : y
23909 // (x < y) ? x : y -> (x <= y) ? x : y
23910 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23911 // the need for an extra compare
23912 // against zero. e.g.
23913 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23915 // testl %edi, %edi
23917 // cmovgl %edi, %eax
23921 // cmovsl %eax, %edi
23922 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23923 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23924 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23925 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23930 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23931 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23932 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23933 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23938 // Early exit check
23939 if (!TLI.isTypeLegal(VT))
23942 // Match VSELECTs into subs with unsigned saturation.
23943 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23944 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23945 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23946 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23947 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23949 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23950 // left side invert the predicate to simplify logic below.
23952 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23954 CC = ISD::getSetCCInverse(CC, true);
23955 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23959 if (Other.getNode() && Other->getNumOperands() == 2 &&
23960 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23961 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23962 SDValue CondRHS = Cond->getOperand(1);
23964 // Look for a general sub with unsigned saturation first.
23965 // x >= y ? x-y : 0 --> subus x, y
23966 // x > y ? x-y : 0 --> subus x, y
23967 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23968 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23969 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23971 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23972 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23973 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23974 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23975 // If the RHS is a constant we have to reverse the const
23976 // canonicalization.
23977 // x > C-1 ? x+-C : 0 --> subus x, C
23978 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23979 CondRHSConst->getAPIntValue() ==
23980 (-OpRHSConst->getAPIntValue() - 1))
23981 return DAG.getNode(
23982 X86ISD::SUBUS, DL, VT, OpLHS,
23983 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23985 // Another special case: If C was a sign bit, the sub has been
23986 // canonicalized into a xor.
23987 // FIXME: Would it be better to use computeKnownBits to determine
23988 // whether it's safe to decanonicalize the xor?
23989 // x s< 0 ? x^C : 0 --> subus x, C
23990 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23991 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23992 OpRHSConst->getAPIntValue().isSignBit())
23993 // Note that we have to rebuild the RHS constant here to ensure we
23994 // don't rely on particular values of undef lanes.
23995 return DAG.getNode(
23996 X86ISD::SUBUS, DL, VT, OpLHS,
23997 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24002 // Simplify vector selection if condition value type matches vselect
24004 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24005 assert(Cond.getValueType().isVector() &&
24006 "vector select expects a vector selector!");
24008 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24009 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24011 // Try invert the condition if true value is not all 1s and false value
24013 if (!TValIsAllOnes && !FValIsAllZeros &&
24014 // Check if the selector will be produced by CMPP*/PCMP*
24015 Cond.getOpcode() == ISD::SETCC &&
24016 // Check if SETCC has already been promoted
24017 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24019 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24020 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24022 if (TValIsAllZeros || FValIsAllOnes) {
24023 SDValue CC = Cond.getOperand(2);
24024 ISD::CondCode NewCC =
24025 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24026 Cond.getOperand(0).getValueType().isInteger());
24027 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24028 std::swap(LHS, RHS);
24029 TValIsAllOnes = FValIsAllOnes;
24030 FValIsAllZeros = TValIsAllZeros;
24034 if (TValIsAllOnes || FValIsAllZeros) {
24037 if (TValIsAllOnes && FValIsAllZeros)
24039 else if (TValIsAllOnes)
24041 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24042 else if (FValIsAllZeros)
24043 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24044 DAG.getBitcast(CondVT, LHS));
24046 return DAG.getBitcast(VT, Ret);
24050 // We should generate an X86ISD::BLENDI from a vselect if its argument
24051 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24052 // constants. This specific pattern gets generated when we split a
24053 // selector for a 512 bit vector in a machine without AVX512 (but with
24054 // 256-bit vectors), during legalization:
24056 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24058 // Iff we find this pattern and the build_vectors are built from
24059 // constants, we translate the vselect into a shuffle_vector that we
24060 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24061 if ((N->getOpcode() == ISD::VSELECT ||
24062 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24063 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24064 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24065 if (Shuffle.getNode())
24069 // If this is a *dynamic* select (non-constant condition) and we can match
24070 // this node with one of the variable blend instructions, restructure the
24071 // condition so that the blends can use the high bit of each element and use
24072 // SimplifyDemandedBits to simplify the condition operand.
24073 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24074 !DCI.isBeforeLegalize() &&
24075 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24076 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24078 // Don't optimize vector selects that map to mask-registers.
24082 // We can only handle the cases where VSELECT is directly legal on the
24083 // subtarget. We custom lower VSELECT nodes with constant conditions and
24084 // this makes it hard to see whether a dynamic VSELECT will correctly
24085 // lower, so we both check the operation's status and explicitly handle the
24086 // cases where a *dynamic* blend will fail even though a constant-condition
24087 // blend could be custom lowered.
24088 // FIXME: We should find a better way to handle this class of problems.
24089 // Potentially, we should combine constant-condition vselect nodes
24090 // pre-legalization into shuffles and not mark as many types as custom
24092 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24094 // FIXME: We don't support i16-element blends currently. We could and
24095 // should support them by making *all* the bits in the condition be set
24096 // rather than just the high bit and using an i8-element blend.
24097 if (VT.getVectorElementType() == MVT::i16)
24099 // Dynamic blending was only available from SSE4.1 onward.
24100 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24102 // Byte blends are only available in AVX2
24103 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24106 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24107 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24109 APInt KnownZero, KnownOne;
24110 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24111 DCI.isBeforeLegalizeOps());
24112 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24113 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24115 // If we changed the computation somewhere in the DAG, this change
24116 // will affect all users of Cond.
24117 // Make sure it is fine and update all the nodes so that we do not
24118 // use the generic VSELECT anymore. Otherwise, we may perform
24119 // wrong optimizations as we messed up with the actual expectation
24120 // for the vector boolean values.
24121 if (Cond != TLO.Old) {
24122 // Check all uses of that condition operand to check whether it will be
24123 // consumed by non-BLEND instructions, which may depend on all bits are
24125 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24127 if (I->getOpcode() != ISD::VSELECT)
24128 // TODO: Add other opcodes eventually lowered into BLEND.
24131 // Update all the users of the condition, before committing the change,
24132 // so that the VSELECT optimizations that expect the correct vector
24133 // boolean value will not be triggered.
24134 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24136 DAG.ReplaceAllUsesOfValueWith(
24138 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24139 Cond, I->getOperand(1), I->getOperand(2)));
24140 DCI.CommitTargetLoweringOpt(TLO);
24143 // At this point, only Cond is changed. Change the condition
24144 // just for N to keep the opportunity to optimize all other
24145 // users their own way.
24146 DAG.ReplaceAllUsesOfValueWith(
24148 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24149 TLO.New, N->getOperand(1), N->getOperand(2)));
24157 // Check whether a boolean test is testing a boolean value generated by
24158 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24161 // Simplify the following patterns:
24162 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24163 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24164 // to (Op EFLAGS Cond)
24166 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24167 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24168 // to (Op EFLAGS !Cond)
24170 // where Op could be BRCOND or CMOV.
24172 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24173 // Quit if not CMP and SUB with its value result used.
24174 if (Cmp.getOpcode() != X86ISD::CMP &&
24175 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24178 // Quit if not used as a boolean value.
24179 if (CC != X86::COND_E && CC != X86::COND_NE)
24182 // Check CMP operands. One of them should be 0 or 1 and the other should be
24183 // an SetCC or extended from it.
24184 SDValue Op1 = Cmp.getOperand(0);
24185 SDValue Op2 = Cmp.getOperand(1);
24188 const ConstantSDNode* C = nullptr;
24189 bool needOppositeCond = (CC == X86::COND_E);
24190 bool checkAgainstTrue = false; // Is it a comparison against 1?
24192 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24194 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24196 else // Quit if all operands are not constants.
24199 if (C->getZExtValue() == 1) {
24200 needOppositeCond = !needOppositeCond;
24201 checkAgainstTrue = true;
24202 } else if (C->getZExtValue() != 0)
24203 // Quit if the constant is neither 0 or 1.
24206 bool truncatedToBoolWithAnd = false;
24207 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24208 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24209 SetCC.getOpcode() == ISD::TRUNCATE ||
24210 SetCC.getOpcode() == ISD::AND) {
24211 if (SetCC.getOpcode() == ISD::AND) {
24213 ConstantSDNode *CS;
24214 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
24215 CS->getZExtValue() == 1)
24217 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
24218 CS->getZExtValue() == 1)
24222 SetCC = SetCC.getOperand(OpIdx);
24223 truncatedToBoolWithAnd = true;
24225 SetCC = SetCC.getOperand(0);
24228 switch (SetCC.getOpcode()) {
24229 case X86ISD::SETCC_CARRY:
24230 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24231 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24232 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24233 // truncated to i1 using 'and'.
24234 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24236 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24237 "Invalid use of SETCC_CARRY!");
24239 case X86ISD::SETCC:
24240 // Set the condition code or opposite one if necessary.
24241 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24242 if (needOppositeCond)
24243 CC = X86::GetOppositeBranchCondition(CC);
24244 return SetCC.getOperand(1);
24245 case X86ISD::CMOV: {
24246 // Check whether false/true value has canonical one, i.e. 0 or 1.
24247 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24248 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24249 // Quit if true value is not a constant.
24252 // Quit if false value is not a constant.
24254 SDValue Op = SetCC.getOperand(0);
24255 // Skip 'zext' or 'trunc' node.
24256 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24257 Op.getOpcode() == ISD::TRUNCATE)
24258 Op = Op.getOperand(0);
24259 // A special case for rdrand/rdseed, where 0 is set if false cond is
24261 if ((Op.getOpcode() != X86ISD::RDRAND &&
24262 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24265 // Quit if false value is not the constant 0 or 1.
24266 bool FValIsFalse = true;
24267 if (FVal && FVal->getZExtValue() != 0) {
24268 if (FVal->getZExtValue() != 1)
24270 // If FVal is 1, opposite cond is needed.
24271 needOppositeCond = !needOppositeCond;
24272 FValIsFalse = false;
24274 // Quit if TVal is not the constant opposite of FVal.
24275 if (FValIsFalse && TVal->getZExtValue() != 1)
24277 if (!FValIsFalse && TVal->getZExtValue() != 0)
24279 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24280 if (needOppositeCond)
24281 CC = X86::GetOppositeBranchCondition(CC);
24282 return SetCC.getOperand(3);
24289 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24291 /// (X86or (X86setcc) (X86setcc))
24292 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24293 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24294 X86::CondCode &CC1, SDValue &Flags,
24296 if (Cond->getOpcode() == X86ISD::CMP) {
24297 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24298 if (!CondOp1C || !CondOp1C->isNullValue())
24301 Cond = Cond->getOperand(0);
24306 SDValue SetCC0, SetCC1;
24307 switch (Cond->getOpcode()) {
24308 default: return false;
24315 SetCC0 = Cond->getOperand(0);
24316 SetCC1 = Cond->getOperand(1);
24320 // Make sure we have SETCC nodes, using the same flags value.
24321 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24322 SetCC1.getOpcode() != X86ISD::SETCC ||
24323 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24326 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24327 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24328 Flags = SetCC0->getOperand(1);
24332 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24333 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24334 TargetLowering::DAGCombinerInfo &DCI,
24335 const X86Subtarget *Subtarget) {
24338 // If the flag operand isn't dead, don't touch this CMOV.
24339 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24342 SDValue FalseOp = N->getOperand(0);
24343 SDValue TrueOp = N->getOperand(1);
24344 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24345 SDValue Cond = N->getOperand(3);
24347 if (CC == X86::COND_E || CC == X86::COND_NE) {
24348 switch (Cond.getOpcode()) {
24352 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24353 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24354 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24360 Flags = checkBoolTestSetCCCombine(Cond, CC);
24361 if (Flags.getNode() &&
24362 // Extra check as FCMOV only supports a subset of X86 cond.
24363 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24364 SDValue Ops[] = { FalseOp, TrueOp,
24365 DAG.getConstant(CC, DL, MVT::i8), Flags };
24366 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24369 // If this is a select between two integer constants, try to do some
24370 // optimizations. Note that the operands are ordered the opposite of SELECT
24372 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24373 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24374 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24375 // larger than FalseC (the false value).
24376 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24377 CC = X86::GetOppositeBranchCondition(CC);
24378 std::swap(TrueC, FalseC);
24379 std::swap(TrueOp, FalseOp);
24382 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24383 // This is efficient for any integer data type (including i8/i16) and
24385 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24386 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24387 DAG.getConstant(CC, DL, MVT::i8), Cond);
24389 // Zero extend the condition if needed.
24390 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24392 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24393 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24394 DAG.getConstant(ShAmt, DL, MVT::i8));
24395 if (N->getNumValues() == 2) // Dead flag value?
24396 return DCI.CombineTo(N, Cond, SDValue());
24400 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24401 // for any integer data type, including i8/i16.
24402 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24403 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24404 DAG.getConstant(CC, DL, MVT::i8), Cond);
24406 // Zero extend the condition if needed.
24407 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24408 FalseC->getValueType(0), Cond);
24409 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24410 SDValue(FalseC, 0));
24412 if (N->getNumValues() == 2) // Dead flag value?
24413 return DCI.CombineTo(N, Cond, SDValue());
24417 // Optimize cases that will turn into an LEA instruction. This requires
24418 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24419 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24420 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24421 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24423 bool isFastMultiplier = false;
24425 switch ((unsigned char)Diff) {
24427 case 1: // result = add base, cond
24428 case 2: // result = lea base( , cond*2)
24429 case 3: // result = lea base(cond, cond*2)
24430 case 4: // result = lea base( , cond*4)
24431 case 5: // result = lea base(cond, cond*4)
24432 case 8: // result = lea base( , cond*8)
24433 case 9: // result = lea base(cond, cond*8)
24434 isFastMultiplier = true;
24439 if (isFastMultiplier) {
24440 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24441 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24442 DAG.getConstant(CC, DL, MVT::i8), Cond);
24443 // Zero extend the condition if needed.
24444 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24446 // Scale the condition by the difference.
24448 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24449 DAG.getConstant(Diff, DL, Cond.getValueType()));
24451 // Add the base if non-zero.
24452 if (FalseC->getAPIntValue() != 0)
24453 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24454 SDValue(FalseC, 0));
24455 if (N->getNumValues() == 2) // Dead flag value?
24456 return DCI.CombineTo(N, Cond, SDValue());
24463 // Handle these cases:
24464 // (select (x != c), e, c) -> select (x != c), e, x),
24465 // (select (x == c), c, e) -> select (x == c), x, e)
24466 // where the c is an integer constant, and the "select" is the combination
24467 // of CMOV and CMP.
24469 // The rationale for this change is that the conditional-move from a constant
24470 // needs two instructions, however, conditional-move from a register needs
24471 // only one instruction.
24473 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24474 // some instruction-combining opportunities. This opt needs to be
24475 // postponed as late as possible.
24477 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24478 // the DCI.xxxx conditions are provided to postpone the optimization as
24479 // late as possible.
24481 ConstantSDNode *CmpAgainst = nullptr;
24482 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24483 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24484 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24486 if (CC == X86::COND_NE &&
24487 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24488 CC = X86::GetOppositeBranchCondition(CC);
24489 std::swap(TrueOp, FalseOp);
24492 if (CC == X86::COND_E &&
24493 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24494 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24495 DAG.getConstant(CC, DL, MVT::i8), Cond };
24496 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24501 // Fold and/or of setcc's to double CMOV:
24502 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24503 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24505 // This combine lets us generate:
24506 // cmovcc1 (jcc1 if we don't have CMOV)
24512 // cmovne (jne if we don't have CMOV)
24513 // When we can't use the CMOV instruction, it might increase branch
24515 // When we can use CMOV, or when there is no mispredict, this improves
24516 // throughput and reduces register pressure.
24518 if (CC == X86::COND_NE) {
24520 X86::CondCode CC0, CC1;
24522 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24524 std::swap(FalseOp, TrueOp);
24525 CC0 = X86::GetOppositeBranchCondition(CC0);
24526 CC1 = X86::GetOppositeBranchCondition(CC1);
24529 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24531 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24532 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24533 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24534 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24542 /// PerformMulCombine - Optimize a single multiply with constant into two
24543 /// in order to implement it with two cheaper instructions, e.g.
24544 /// LEA + SHL, LEA + LEA.
24545 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24546 TargetLowering::DAGCombinerInfo &DCI) {
24547 // An imul is usually smaller than the alternative sequence.
24548 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24551 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24554 EVT VT = N->getValueType(0);
24555 if (VT != MVT::i64 && VT != MVT::i32)
24558 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24561 uint64_t MulAmt = C->getZExtValue();
24562 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24565 uint64_t MulAmt1 = 0;
24566 uint64_t MulAmt2 = 0;
24567 if ((MulAmt % 9) == 0) {
24569 MulAmt2 = MulAmt / 9;
24570 } else if ((MulAmt % 5) == 0) {
24572 MulAmt2 = MulAmt / 5;
24573 } else if ((MulAmt % 3) == 0) {
24575 MulAmt2 = MulAmt / 3;
24578 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24581 if (isPowerOf2_64(MulAmt2) &&
24582 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24583 // If second multiplifer is pow2, issue it first. We want the multiply by
24584 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24586 std::swap(MulAmt1, MulAmt2);
24589 if (isPowerOf2_64(MulAmt1))
24590 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24591 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24593 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24594 DAG.getConstant(MulAmt1, DL, VT));
24596 if (isPowerOf2_64(MulAmt2))
24597 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24598 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24600 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24601 DAG.getConstant(MulAmt2, DL, VT));
24603 // Do not add new nodes to DAG combiner worklist.
24604 DCI.CombineTo(N, NewMul, false);
24609 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24610 SDValue N0 = N->getOperand(0);
24611 SDValue N1 = N->getOperand(1);
24612 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24613 EVT VT = N0.getValueType();
24615 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24616 // since the result of setcc_c is all zero's or all ones.
24617 if (VT.isInteger() && !VT.isVector() &&
24618 N1C && N0.getOpcode() == ISD::AND &&
24619 N0.getOperand(1).getOpcode() == ISD::Constant) {
24620 SDValue N00 = N0.getOperand(0);
24621 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24622 APInt ShAmt = N1C->getAPIntValue();
24623 Mask = Mask.shl(ShAmt);
24624 bool MaskOK = false;
24625 // We can handle cases concerning bit-widening nodes containing setcc_c if
24626 // we carefully interrogate the mask to make sure we are semantics
24628 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24629 // of the underlying setcc_c operation if the setcc_c was zero extended.
24630 // Consider the following example:
24631 // zext(setcc_c) -> i32 0x0000FFFF
24632 // c1 -> i32 0x0000FFFF
24633 // c2 -> i32 0x00000001
24634 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24635 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24636 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24638 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24639 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24641 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24642 N00.getOpcode() == ISD::ANY_EXTEND) &&
24643 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24644 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24646 if (MaskOK && Mask != 0) {
24648 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24652 // Hardware support for vector shifts is sparse which makes us scalarize the
24653 // vector operations in many cases. Also, on sandybridge ADD is faster than
24655 // (shl V, 1) -> add V,V
24656 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24657 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24658 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24659 // We shift all of the values by one. In many cases we do not have
24660 // hardware support for this operation. This is better expressed as an ADD
24662 if (N1SplatC->getAPIntValue() == 1)
24663 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24669 /// \brief Returns a vector of 0s if the node in input is a vector logical
24670 /// shift by a constant amount which is known to be bigger than or equal
24671 /// to the vector element size in bits.
24672 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24673 const X86Subtarget *Subtarget) {
24674 EVT VT = N->getValueType(0);
24676 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24677 (!Subtarget->hasInt256() ||
24678 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24681 SDValue Amt = N->getOperand(1);
24683 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24684 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24685 APInt ShiftAmt = AmtSplat->getAPIntValue();
24686 unsigned MaxAmount =
24687 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24689 // SSE2/AVX2 logical shifts always return a vector of 0s
24690 // if the shift amount is bigger than or equal to
24691 // the element size. The constant shift amount will be
24692 // encoded as a 8-bit immediate.
24693 if (ShiftAmt.trunc(8).uge(MaxAmount))
24694 return getZeroVector(VT, Subtarget, DAG, DL);
24700 /// PerformShiftCombine - Combine shifts.
24701 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24702 TargetLowering::DAGCombinerInfo &DCI,
24703 const X86Subtarget *Subtarget) {
24704 if (N->getOpcode() == ISD::SHL)
24705 if (SDValue V = PerformSHLCombine(N, DAG))
24708 // Try to fold this logical shift into a zero vector.
24709 if (N->getOpcode() != ISD::SRA)
24710 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24716 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24717 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24718 // and friends. Likewise for OR -> CMPNEQSS.
24719 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24720 TargetLowering::DAGCombinerInfo &DCI,
24721 const X86Subtarget *Subtarget) {
24724 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24725 // we're requiring SSE2 for both.
24726 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24727 SDValue N0 = N->getOperand(0);
24728 SDValue N1 = N->getOperand(1);
24729 SDValue CMP0 = N0->getOperand(1);
24730 SDValue CMP1 = N1->getOperand(1);
24733 // The SETCCs should both refer to the same CMP.
24734 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24737 SDValue CMP00 = CMP0->getOperand(0);
24738 SDValue CMP01 = CMP0->getOperand(1);
24739 EVT VT = CMP00.getValueType();
24741 if (VT == MVT::f32 || VT == MVT::f64) {
24742 bool ExpectingFlags = false;
24743 // Check for any users that want flags:
24744 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24745 !ExpectingFlags && UI != UE; ++UI)
24746 switch (UI->getOpcode()) {
24751 ExpectingFlags = true;
24753 case ISD::CopyToReg:
24754 case ISD::SIGN_EXTEND:
24755 case ISD::ZERO_EXTEND:
24756 case ISD::ANY_EXTEND:
24760 if (!ExpectingFlags) {
24761 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24762 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24764 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24765 X86::CondCode tmp = cc0;
24770 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24771 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24772 // FIXME: need symbolic constants for these magic numbers.
24773 // See X86ATTInstPrinter.cpp:printSSECC().
24774 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24775 if (Subtarget->hasAVX512()) {
24776 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24778 DAG.getConstant(x86cc, DL, MVT::i8));
24779 if (N->getValueType(0) != MVT::i1)
24780 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24784 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24785 CMP00.getValueType(), CMP00, CMP01,
24786 DAG.getConstant(x86cc, DL,
24789 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24790 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24792 if (is64BitFP && !Subtarget->is64Bit()) {
24793 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24794 // 64-bit integer, since that's not a legal type. Since
24795 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24796 // bits, but can do this little dance to extract the lowest 32 bits
24797 // and work with those going forward.
24798 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24800 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24801 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24802 Vector32, DAG.getIntPtrConstant(0, DL));
24806 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24807 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24808 DAG.getConstant(1, DL, IntVT));
24809 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24811 return OneBitOfTruth;
24819 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24820 /// so it can be folded inside ANDNP.
24821 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24822 EVT VT = N->getValueType(0);
24824 // Match direct AllOnes for 128 and 256-bit vectors
24825 if (ISD::isBuildVectorAllOnes(N))
24828 // Look through a bit convert.
24829 if (N->getOpcode() == ISD::BITCAST)
24830 N = N->getOperand(0).getNode();
24832 // Sometimes the operand may come from a insert_subvector building a 256-bit
24834 if (VT.is256BitVector() &&
24835 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24836 SDValue V1 = N->getOperand(0);
24837 SDValue V2 = N->getOperand(1);
24839 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24840 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24841 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24842 ISD::isBuildVectorAllOnes(V2.getNode()))
24849 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24850 // register. In most cases we actually compare or select YMM-sized registers
24851 // and mixing the two types creates horrible code. This method optimizes
24852 // some of the transition sequences.
24853 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24854 TargetLowering::DAGCombinerInfo &DCI,
24855 const X86Subtarget *Subtarget) {
24856 EVT VT = N->getValueType(0);
24857 if (!VT.is256BitVector())
24860 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24861 N->getOpcode() == ISD::ZERO_EXTEND ||
24862 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24864 SDValue Narrow = N->getOperand(0);
24865 EVT NarrowVT = Narrow->getValueType(0);
24866 if (!NarrowVT.is128BitVector())
24869 if (Narrow->getOpcode() != ISD::XOR &&
24870 Narrow->getOpcode() != ISD::AND &&
24871 Narrow->getOpcode() != ISD::OR)
24874 SDValue N0 = Narrow->getOperand(0);
24875 SDValue N1 = Narrow->getOperand(1);
24878 // The Left side has to be a trunc.
24879 if (N0.getOpcode() != ISD::TRUNCATE)
24882 // The type of the truncated inputs.
24883 EVT WideVT = N0->getOperand(0)->getValueType(0);
24887 // The right side has to be a 'trunc' or a constant vector.
24888 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24889 ConstantSDNode *RHSConstSplat = nullptr;
24890 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24891 RHSConstSplat = RHSBV->getConstantSplatNode();
24892 if (!RHSTrunc && !RHSConstSplat)
24895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24897 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24900 // Set N0 and N1 to hold the inputs to the new wide operation.
24901 N0 = N0->getOperand(0);
24902 if (RHSConstSplat) {
24903 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
24904 SDValue(RHSConstSplat, 0));
24905 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24906 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24907 } else if (RHSTrunc) {
24908 N1 = N1->getOperand(0);
24911 // Generate the wide operation.
24912 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24913 unsigned Opcode = N->getOpcode();
24915 case ISD::ANY_EXTEND:
24917 case ISD::ZERO_EXTEND: {
24918 unsigned InBits = NarrowVT.getScalarSizeInBits();
24919 APInt Mask = APInt::getAllOnesValue(InBits);
24920 Mask = Mask.zext(VT.getScalarSizeInBits());
24921 return DAG.getNode(ISD::AND, DL, VT,
24922 Op, DAG.getConstant(Mask, DL, VT));
24924 case ISD::SIGN_EXTEND:
24925 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24926 Op, DAG.getValueType(NarrowVT));
24928 llvm_unreachable("Unexpected opcode");
24932 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24933 TargetLowering::DAGCombinerInfo &DCI,
24934 const X86Subtarget *Subtarget) {
24935 SDValue N0 = N->getOperand(0);
24936 SDValue N1 = N->getOperand(1);
24939 // A vector zext_in_reg may be represented as a shuffle,
24940 // feeding into a bitcast (this represents anyext) feeding into
24941 // an and with a mask.
24942 // We'd like to try to combine that into a shuffle with zero
24943 // plus a bitcast, removing the and.
24944 if (N0.getOpcode() != ISD::BITCAST ||
24945 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24948 // The other side of the AND should be a splat of 2^C, where C
24949 // is the number of bits in the source type.
24950 if (N1.getOpcode() == ISD::BITCAST)
24951 N1 = N1.getOperand(0);
24952 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24954 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24956 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24957 EVT SrcType = Shuffle->getValueType(0);
24959 // We expect a single-source shuffle
24960 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24963 unsigned SrcSize = SrcType.getScalarSizeInBits();
24965 APInt SplatValue, SplatUndef;
24966 unsigned SplatBitSize;
24968 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24969 SplatBitSize, HasAnyUndefs))
24972 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24973 // Make sure the splat matches the mask we expect
24974 if (SplatBitSize > ResSize ||
24975 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24978 // Make sure the input and output size make sense
24979 if (SrcSize >= ResSize || ResSize % SrcSize)
24982 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24983 // The number of u's between each two values depends on the ratio between
24984 // the source and dest type.
24985 unsigned ZextRatio = ResSize / SrcSize;
24986 bool IsZext = true;
24987 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24988 if (i % ZextRatio) {
24989 if (Shuffle->getMaskElt(i) > 0) {
24995 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24996 // Expected element number
25006 // Ok, perform the transformation - replace the shuffle with
25007 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25008 // (instead of undef) where the k elements come from the zero vector.
25009 SmallVector<int, 8> Mask;
25010 unsigned NumElems = SrcType.getVectorNumElements();
25011 for (unsigned i = 0; i < NumElems; ++i)
25013 Mask.push_back(NumElems);
25015 Mask.push_back(i / ZextRatio);
25017 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25018 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25019 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25022 /// If both input operands of a logic op are being cast from floating point
25023 /// types, try to convert this into a floating point logic node to avoid
25024 /// unnecessary moves from SSE to integer registers.
25025 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25026 const X86Subtarget *Subtarget) {
25027 unsigned FPOpcode = ISD::DELETED_NODE;
25028 if (N->getOpcode() == ISD::AND)
25029 FPOpcode = X86ISD::FAND;
25030 else if (N->getOpcode() == ISD::OR)
25031 FPOpcode = X86ISD::FOR;
25032 else if (N->getOpcode() == ISD::XOR)
25033 FPOpcode = X86ISD::FXOR;
25035 assert(FPOpcode != ISD::DELETED_NODE &&
25036 "Unexpected input node for FP logic conversion");
25038 EVT VT = N->getValueType(0);
25039 SDValue N0 = N->getOperand(0);
25040 SDValue N1 = N->getOperand(1);
25042 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25043 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25044 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25045 SDValue N00 = N0.getOperand(0);
25046 SDValue N10 = N1.getOperand(0);
25047 EVT N00Type = N00.getValueType();
25048 EVT N10Type = N10.getValueType();
25049 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25050 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25051 return DAG.getBitcast(VT, FPLogic);
25057 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25058 TargetLowering::DAGCombinerInfo &DCI,
25059 const X86Subtarget *Subtarget) {
25060 if (DCI.isBeforeLegalizeOps())
25063 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25066 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25069 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25072 EVT VT = N->getValueType(0);
25073 SDValue N0 = N->getOperand(0);
25074 SDValue N1 = N->getOperand(1);
25077 // Create BEXTR instructions
25078 // BEXTR is ((X >> imm) & (2**size-1))
25079 if (VT == MVT::i32 || VT == MVT::i64) {
25080 // Check for BEXTR.
25081 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25082 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25083 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25084 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25085 if (MaskNode && ShiftNode) {
25086 uint64_t Mask = MaskNode->getZExtValue();
25087 uint64_t Shift = ShiftNode->getZExtValue();
25088 if (isMask_64(Mask)) {
25089 uint64_t MaskSize = countPopulation(Mask);
25090 if (Shift + MaskSize <= VT.getSizeInBits())
25091 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25092 DAG.getConstant(Shift | (MaskSize << 8), DL,
25101 // Want to form ANDNP nodes:
25102 // 1) In the hopes of then easily combining them with OR and AND nodes
25103 // to form PBLEND/PSIGN.
25104 // 2) To match ANDN packed intrinsics
25105 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25108 // Check LHS for vnot
25109 if (N0.getOpcode() == ISD::XOR &&
25110 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25111 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25112 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25114 // Check RHS for vnot
25115 if (N1.getOpcode() == ISD::XOR &&
25116 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25117 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25118 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25123 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25124 TargetLowering::DAGCombinerInfo &DCI,
25125 const X86Subtarget *Subtarget) {
25126 if (DCI.isBeforeLegalizeOps())
25129 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25132 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25135 SDValue N0 = N->getOperand(0);
25136 SDValue N1 = N->getOperand(1);
25137 EVT VT = N->getValueType(0);
25139 // look for psign/blend
25140 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25141 if (!Subtarget->hasSSSE3() ||
25142 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25145 // Canonicalize pandn to RHS
25146 if (N0.getOpcode() == X86ISD::ANDNP)
25148 // or (and (m, y), (pandn m, x))
25149 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25150 SDValue Mask = N1.getOperand(0);
25151 SDValue X = N1.getOperand(1);
25153 if (N0.getOperand(0) == Mask)
25154 Y = N0.getOperand(1);
25155 if (N0.getOperand(1) == Mask)
25156 Y = N0.getOperand(0);
25158 // Check to see if the mask appeared in both the AND and ANDNP and
25162 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25163 // Look through mask bitcast.
25164 if (Mask.getOpcode() == ISD::BITCAST)
25165 Mask = Mask.getOperand(0);
25166 if (X.getOpcode() == ISD::BITCAST)
25167 X = X.getOperand(0);
25168 if (Y.getOpcode() == ISD::BITCAST)
25169 Y = Y.getOperand(0);
25171 EVT MaskVT = Mask.getValueType();
25173 // Validate that the Mask operand is a vector sra node.
25174 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25175 // there is no psrai.b
25176 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25177 unsigned SraAmt = ~0;
25178 if (Mask.getOpcode() == ISD::SRA) {
25179 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25180 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25181 SraAmt = AmtConst->getZExtValue();
25182 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25183 SDValue SraC = Mask.getOperand(1);
25184 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25186 if ((SraAmt + 1) != EltBits)
25191 // Now we know we at least have a plendvb with the mask val. See if
25192 // we can form a psignb/w/d.
25193 // psign = x.type == y.type == mask.type && y = sub(0, x);
25194 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25195 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25196 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25197 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25198 "Unsupported VT for PSIGN");
25199 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25200 return DAG.getBitcast(VT, Mask);
25202 // PBLENDVB only available on SSE 4.1
25203 if (!Subtarget->hasSSE41())
25206 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25208 X = DAG.getBitcast(BlendVT, X);
25209 Y = DAG.getBitcast(BlendVT, Y);
25210 Mask = DAG.getBitcast(BlendVT, Mask);
25211 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25212 return DAG.getBitcast(VT, Mask);
25216 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25219 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25220 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25222 // SHLD/SHRD instructions have lower register pressure, but on some
25223 // platforms they have higher latency than the equivalent
25224 // series of shifts/or that would otherwise be generated.
25225 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25226 // have higher latencies and we are not optimizing for size.
25227 if (!OptForSize && Subtarget->isSHLDSlow())
25230 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25232 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25234 if (!N0.hasOneUse() || !N1.hasOneUse())
25237 SDValue ShAmt0 = N0.getOperand(1);
25238 if (ShAmt0.getValueType() != MVT::i8)
25240 SDValue ShAmt1 = N1.getOperand(1);
25241 if (ShAmt1.getValueType() != MVT::i8)
25243 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25244 ShAmt0 = ShAmt0.getOperand(0);
25245 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25246 ShAmt1 = ShAmt1.getOperand(0);
25249 unsigned Opc = X86ISD::SHLD;
25250 SDValue Op0 = N0.getOperand(0);
25251 SDValue Op1 = N1.getOperand(0);
25252 if (ShAmt0.getOpcode() == ISD::SUB) {
25253 Opc = X86ISD::SHRD;
25254 std::swap(Op0, Op1);
25255 std::swap(ShAmt0, ShAmt1);
25258 unsigned Bits = VT.getSizeInBits();
25259 if (ShAmt1.getOpcode() == ISD::SUB) {
25260 SDValue Sum = ShAmt1.getOperand(0);
25261 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25262 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25263 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25264 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25265 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25266 return DAG.getNode(Opc, DL, VT,
25268 DAG.getNode(ISD::TRUNCATE, DL,
25271 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25272 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25274 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25275 return DAG.getNode(Opc, DL, VT,
25276 N0.getOperand(0), N1.getOperand(0),
25277 DAG.getNode(ISD::TRUNCATE, DL,
25284 // Generate NEG and CMOV for integer abs.
25285 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25286 EVT VT = N->getValueType(0);
25288 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25289 // 8-bit integer abs to NEG and CMOV.
25290 if (VT.isInteger() && VT.getSizeInBits() == 8)
25293 SDValue N0 = N->getOperand(0);
25294 SDValue N1 = N->getOperand(1);
25297 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25298 // and change it to SUB and CMOV.
25299 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25300 N0.getOpcode() == ISD::ADD &&
25301 N0.getOperand(1) == N1 &&
25302 N1.getOpcode() == ISD::SRA &&
25303 N1.getOperand(0) == N0.getOperand(0))
25304 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25305 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25306 // Generate SUB & CMOV.
25307 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25308 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25310 SDValue Ops[] = { N0.getOperand(0), Neg,
25311 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25312 SDValue(Neg.getNode(), 1) };
25313 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25318 // Try to turn tests against the signbit in the form of:
25319 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25322 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25323 // This is only worth doing if the output type is i8.
25324 if (N->getValueType(0) != MVT::i8)
25327 SDValue N0 = N->getOperand(0);
25328 SDValue N1 = N->getOperand(1);
25330 // We should be performing an xor against a truncated shift.
25331 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25334 // Make sure we are performing an xor against one.
25335 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25338 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25339 SDValue Shift = N0.getOperand(0);
25340 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25343 // Make sure we are truncating from one of i16, i32 or i64.
25344 EVT ShiftTy = Shift.getValueType();
25345 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25348 // Make sure the shift amount extracts the sign bit.
25349 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25350 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25353 // Create a greater-than comparison against -1.
25354 // N.B. Using SETGE against 0 works but we want a canonical looking
25355 // comparison, using SETGT matches up with what TranslateX86CC.
25357 SDValue ShiftOp = Shift.getOperand(0);
25358 EVT ShiftOpTy = ShiftOp.getValueType();
25359 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25360 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25364 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25365 TargetLowering::DAGCombinerInfo &DCI,
25366 const X86Subtarget *Subtarget) {
25367 if (DCI.isBeforeLegalizeOps())
25370 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25373 if (Subtarget->hasCMov())
25374 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25377 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25383 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25384 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25385 /// X86ISD::AVG instruction.
25386 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25387 const X86Subtarget *Subtarget, SDLoc DL) {
25388 if (!VT.isVector() || !VT.isSimple())
25390 EVT InVT = In.getValueType();
25391 unsigned NumElems = VT.getVectorNumElements();
25393 EVT ScalarVT = VT.getVectorElementType();
25394 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25395 isPowerOf2_32(NumElems)))
25398 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25399 // than the original input type (i8/i16).
25400 EVT InScalarVT = InVT.getVectorElementType();
25401 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25404 if (Subtarget->hasAVX512()) {
25405 if (VT.getSizeInBits() > 512)
25407 } else if (Subtarget->hasAVX2()) {
25408 if (VT.getSizeInBits() > 256)
25411 if (VT.getSizeInBits() > 128)
25415 // Detect the following pattern:
25417 // %1 = zext <N x i8> %a to <N x i32>
25418 // %2 = zext <N x i8> %b to <N x i32>
25419 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25420 // %4 = add nuw nsw <N x i32> %3, %2
25421 // %5 = lshr <N x i32> %N, <i32 1 x N>
25422 // %6 = trunc <N x i32> %5 to <N x i8>
25424 // In AVX512, the last instruction can also be a trunc store.
25426 if (In.getOpcode() != ISD::SRL)
25429 // A lambda checking the given SDValue is a constant vector and each element
25430 // is in the range [Min, Max].
25431 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25432 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25433 if (!BV || !BV->isConstant())
25435 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25436 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25439 uint64_t Val = C->getZExtValue();
25440 if (Val < Min || Val > Max)
25446 // Check if each element of the vector is left-shifted by one.
25447 auto LHS = In.getOperand(0);
25448 auto RHS = In.getOperand(1);
25449 if (!IsConstVectorInRange(RHS, 1, 1))
25451 if (LHS.getOpcode() != ISD::ADD)
25454 // Detect a pattern of a + b + 1 where the order doesn't matter.
25455 SDValue Operands[3];
25456 Operands[0] = LHS.getOperand(0);
25457 Operands[1] = LHS.getOperand(1);
25459 // Take care of the case when one of the operands is a constant vector whose
25460 // element is in the range [1, 256].
25461 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25462 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25463 Operands[0].getOperand(0).getValueType() == VT) {
25464 // The pattern is detected. Subtract one from the constant vector, then
25465 // demote it and emit X86ISD::AVG instruction.
25466 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25467 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25468 SmallVector<SDValue, 8>(NumElems, One));
25469 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25470 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25471 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25475 if (Operands[0].getOpcode() == ISD::ADD)
25476 std::swap(Operands[0], Operands[1]);
25477 else if (Operands[1].getOpcode() != ISD::ADD)
25479 Operands[2] = Operands[1].getOperand(0);
25480 Operands[1] = Operands[1].getOperand(1);
25482 // Now we have three operands of two additions. Check that one of them is a
25483 // constant vector with ones, and the other two are promoted from i8/i16.
25484 for (int i = 0; i < 3; ++i) {
25485 if (!IsConstVectorInRange(Operands[i], 1, 1))
25487 std::swap(Operands[i], Operands[2]);
25489 // Check if Operands[0] and Operands[1] are results of type promotion.
25490 for (int j = 0; j < 2; ++j)
25491 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25492 Operands[j].getOperand(0).getValueType() != VT)
25495 // The pattern is detected, emit X86ISD::AVG instruction.
25496 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25497 Operands[1].getOperand(0));
25503 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
25504 const X86Subtarget *Subtarget) {
25505 return detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG, Subtarget,
25509 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25510 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25511 TargetLowering::DAGCombinerInfo &DCI,
25512 const X86Subtarget *Subtarget) {
25513 LoadSDNode *Ld = cast<LoadSDNode>(N);
25514 EVT RegVT = Ld->getValueType(0);
25515 EVT MemVT = Ld->getMemoryVT();
25517 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25519 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25520 // into two 16-byte operations.
25521 ISD::LoadExtType Ext = Ld->getExtensionType();
25523 unsigned AddressSpace = Ld->getAddressSpace();
25524 unsigned Alignment = Ld->getAlignment();
25525 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25526 Ext == ISD::NON_EXTLOAD &&
25527 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25528 AddressSpace, Alignment, &Fast) && !Fast) {
25529 unsigned NumElems = RegVT.getVectorNumElements();
25533 SDValue Ptr = Ld->getBasePtr();
25534 SDValue Increment =
25535 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25537 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25539 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25540 Ld->getPointerInfo(), Ld->isVolatile(),
25541 Ld->isNonTemporal(), Ld->isInvariant(),
25543 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25544 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25545 Ld->getPointerInfo(), Ld->isVolatile(),
25546 Ld->isNonTemporal(), Ld->isInvariant(),
25547 std::min(16U, Alignment));
25548 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25550 Load2.getValue(1));
25552 SDValue NewVec = DAG.getUNDEF(RegVT);
25553 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25554 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25555 return DCI.CombineTo(N, NewVec, TF, true);
25561 /// PerformMLOADCombine - Resolve extending loads
25562 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25563 TargetLowering::DAGCombinerInfo &DCI,
25564 const X86Subtarget *Subtarget) {
25565 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25566 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25569 EVT VT = Mld->getValueType(0);
25570 unsigned NumElems = VT.getVectorNumElements();
25571 EVT LdVT = Mld->getMemoryVT();
25574 assert(LdVT != VT && "Cannot extend to the same type");
25575 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25576 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25577 // From, To sizes and ElemCount must be pow of two
25578 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25579 "Unexpected size for extending masked load");
25581 unsigned SizeRatio = ToSz / FromSz;
25582 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25584 // Create a type on which we perform the shuffle
25585 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25586 LdVT.getScalarType(), NumElems*SizeRatio);
25587 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25589 // Convert Src0 value
25590 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25591 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25592 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25593 for (unsigned i = 0; i != NumElems; ++i)
25594 ShuffleVec[i] = i * SizeRatio;
25596 // Can't shuffle using an illegal type.
25597 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25598 "WideVecVT should be legal");
25599 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25600 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25602 // Prepare the new mask
25604 SDValue Mask = Mld->getMask();
25605 if (Mask.getValueType() == VT) {
25606 // Mask and original value have the same type
25607 NewMask = DAG.getBitcast(WideVecVT, Mask);
25608 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25609 for (unsigned i = 0; i != NumElems; ++i)
25610 ShuffleVec[i] = i * SizeRatio;
25611 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25612 ShuffleVec[i] = NumElems*SizeRatio;
25613 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25614 DAG.getConstant(0, dl, WideVecVT),
25618 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25619 unsigned WidenNumElts = NumElems*SizeRatio;
25620 unsigned MaskNumElts = VT.getVectorNumElements();
25621 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25624 unsigned NumConcat = WidenNumElts / MaskNumElts;
25625 SmallVector<SDValue, 16> Ops(NumConcat);
25626 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25628 for (unsigned i = 1; i != NumConcat; ++i)
25631 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25634 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25635 Mld->getBasePtr(), NewMask, WideSrc0,
25636 Mld->getMemoryVT(), Mld->getMemOperand(),
25638 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25639 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25641 /// PerformMSTORECombine - Resolve truncating stores
25642 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25643 const X86Subtarget *Subtarget) {
25644 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25645 if (!Mst->isTruncatingStore())
25648 EVT VT = Mst->getValue().getValueType();
25649 unsigned NumElems = VT.getVectorNumElements();
25650 EVT StVT = Mst->getMemoryVT();
25653 assert(StVT != VT && "Cannot truncate to the same type");
25654 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25655 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25657 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25659 // The truncating store is legal in some cases. For example
25660 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25661 // are designated for truncate store.
25662 // In this case we don't need any further transformations.
25663 if (TLI.isTruncStoreLegal(VT, StVT))
25666 // From, To sizes and ElemCount must be pow of two
25667 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25668 "Unexpected size for truncating masked store");
25669 // We are going to use the original vector elt for storing.
25670 // Accumulated smaller vector elements must be a multiple of the store size.
25671 assert (((NumElems * FromSz) % ToSz) == 0 &&
25672 "Unexpected ratio for truncating masked store");
25674 unsigned SizeRatio = FromSz / ToSz;
25675 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25677 // Create a type on which we perform the shuffle
25678 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25679 StVT.getScalarType(), NumElems*SizeRatio);
25681 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25683 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25684 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25685 for (unsigned i = 0; i != NumElems; ++i)
25686 ShuffleVec[i] = i * SizeRatio;
25688 // Can't shuffle using an illegal type.
25689 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25690 "WideVecVT should be legal");
25692 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25693 DAG.getUNDEF(WideVecVT),
25697 SDValue Mask = Mst->getMask();
25698 if (Mask.getValueType() == VT) {
25699 // Mask and original value have the same type
25700 NewMask = DAG.getBitcast(WideVecVT, Mask);
25701 for (unsigned i = 0; i != NumElems; ++i)
25702 ShuffleVec[i] = i * SizeRatio;
25703 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25704 ShuffleVec[i] = NumElems*SizeRatio;
25705 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25706 DAG.getConstant(0, dl, WideVecVT),
25710 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25711 unsigned WidenNumElts = NumElems*SizeRatio;
25712 unsigned MaskNumElts = VT.getVectorNumElements();
25713 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25716 unsigned NumConcat = WidenNumElts / MaskNumElts;
25717 SmallVector<SDValue, 16> Ops(NumConcat);
25718 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25720 for (unsigned i = 1; i != NumConcat; ++i)
25723 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25726 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25727 NewMask, StVT, Mst->getMemOperand(), false);
25729 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25730 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25731 const X86Subtarget *Subtarget) {
25732 StoreSDNode *St = cast<StoreSDNode>(N);
25733 EVT VT = St->getValue().getValueType();
25734 EVT StVT = St->getMemoryVT();
25736 SDValue StoredVal = St->getOperand(1);
25737 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25739 // If we are saving a concatenation of two XMM registers and 32-byte stores
25740 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25742 unsigned AddressSpace = St->getAddressSpace();
25743 unsigned Alignment = St->getAlignment();
25744 if (VT.is256BitVector() && StVT == VT &&
25745 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25746 AddressSpace, Alignment, &Fast) && !Fast) {
25747 unsigned NumElems = VT.getVectorNumElements();
25751 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25752 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25755 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25756 SDValue Ptr0 = St->getBasePtr();
25757 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25759 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25760 St->getPointerInfo(), St->isVolatile(),
25761 St->isNonTemporal(), Alignment);
25762 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25763 St->getPointerInfo(), St->isVolatile(),
25764 St->isNonTemporal(),
25765 std::min(16U, Alignment));
25766 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25769 // Optimize trunc store (of multiple scalars) to shuffle and store.
25770 // First, pack all of the elements in one place. Next, store to memory
25771 // in fewer chunks.
25772 if (St->isTruncatingStore() && VT.isVector()) {
25773 // Check if we can detect an AVG pattern from the truncation. If yes,
25774 // replace the trunc store by a normal store with the result of X86ISD::AVG
25777 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
25779 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
25780 St->getPointerInfo(), St->isVolatile(),
25781 St->isNonTemporal(), St->getAlignment());
25783 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25784 unsigned NumElems = VT.getVectorNumElements();
25785 assert(StVT != VT && "Cannot truncate to the same type");
25786 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25787 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25789 // The truncating store is legal in some cases. For example
25790 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25791 // are designated for truncate store.
25792 // In this case we don't need any further transformations.
25793 if (TLI.isTruncStoreLegal(VT, StVT))
25796 // From, To sizes and ElemCount must be pow of two
25797 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25798 // We are going to use the original vector elt for storing.
25799 // Accumulated smaller vector elements must be a multiple of the store size.
25800 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25802 unsigned SizeRatio = FromSz / ToSz;
25804 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25806 // Create a type on which we perform the shuffle
25807 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25808 StVT.getScalarType(), NumElems*SizeRatio);
25810 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25812 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25813 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25814 for (unsigned i = 0; i != NumElems; ++i)
25815 ShuffleVec[i] = i * SizeRatio;
25817 // Can't shuffle using an illegal type.
25818 if (!TLI.isTypeLegal(WideVecVT))
25821 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25822 DAG.getUNDEF(WideVecVT),
25824 // At this point all of the data is stored at the bottom of the
25825 // register. We now need to save it to mem.
25827 // Find the largest store unit
25828 MVT StoreType = MVT::i8;
25829 for (MVT Tp : MVT::integer_valuetypes()) {
25830 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25834 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25835 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25836 (64 <= NumElems * ToSz))
25837 StoreType = MVT::f64;
25839 // Bitcast the original vector into a vector of store-size units
25840 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25841 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25842 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25843 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25844 SmallVector<SDValue, 8> Chains;
25845 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25846 TLI.getPointerTy(DAG.getDataLayout()));
25847 SDValue Ptr = St->getBasePtr();
25849 // Perform one or more big stores into memory.
25850 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25851 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25852 StoreType, ShuffWide,
25853 DAG.getIntPtrConstant(i, dl));
25854 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25855 St->getPointerInfo(), St->isVolatile(),
25856 St->isNonTemporal(), St->getAlignment());
25857 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25858 Chains.push_back(Ch);
25861 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25864 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25865 // the FP state in cases where an emms may be missing.
25866 // A preferable solution to the general problem is to figure out the right
25867 // places to insert EMMS. This qualifies as a quick hack.
25869 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25870 if (VT.getSizeInBits() != 64)
25873 const Function *F = DAG.getMachineFunction().getFunction();
25874 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25876 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25877 if ((VT.isVector() ||
25878 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25879 isa<LoadSDNode>(St->getValue()) &&
25880 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25881 St->getChain().hasOneUse() && !St->isVolatile()) {
25882 SDNode* LdVal = St->getValue().getNode();
25883 LoadSDNode *Ld = nullptr;
25884 int TokenFactorIndex = -1;
25885 SmallVector<SDValue, 8> Ops;
25886 SDNode* ChainVal = St->getChain().getNode();
25887 // Must be a store of a load. We currently handle two cases: the load
25888 // is a direct child, and it's under an intervening TokenFactor. It is
25889 // possible to dig deeper under nested TokenFactors.
25890 if (ChainVal == LdVal)
25891 Ld = cast<LoadSDNode>(St->getChain());
25892 else if (St->getValue().hasOneUse() &&
25893 ChainVal->getOpcode() == ISD::TokenFactor) {
25894 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25895 if (ChainVal->getOperand(i).getNode() == LdVal) {
25896 TokenFactorIndex = i;
25897 Ld = cast<LoadSDNode>(St->getValue());
25899 Ops.push_back(ChainVal->getOperand(i));
25903 if (!Ld || !ISD::isNormalLoad(Ld))
25906 // If this is not the MMX case, i.e. we are just turning i64 load/store
25907 // into f64 load/store, avoid the transformation if there are multiple
25908 // uses of the loaded value.
25909 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25914 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25915 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25917 if (Subtarget->is64Bit() || F64IsLegal) {
25918 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25919 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25920 Ld->getPointerInfo(), Ld->isVolatile(),
25921 Ld->isNonTemporal(), Ld->isInvariant(),
25922 Ld->getAlignment());
25923 SDValue NewChain = NewLd.getValue(1);
25924 if (TokenFactorIndex != -1) {
25925 Ops.push_back(NewChain);
25926 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25928 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25929 St->getPointerInfo(),
25930 St->isVolatile(), St->isNonTemporal(),
25931 St->getAlignment());
25934 // Otherwise, lower to two pairs of 32-bit loads / stores.
25935 SDValue LoAddr = Ld->getBasePtr();
25936 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25937 DAG.getConstant(4, LdDL, MVT::i32));
25939 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25940 Ld->getPointerInfo(),
25941 Ld->isVolatile(), Ld->isNonTemporal(),
25942 Ld->isInvariant(), Ld->getAlignment());
25943 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25944 Ld->getPointerInfo().getWithOffset(4),
25945 Ld->isVolatile(), Ld->isNonTemporal(),
25947 MinAlign(Ld->getAlignment(), 4));
25949 SDValue NewChain = LoLd.getValue(1);
25950 if (TokenFactorIndex != -1) {
25951 Ops.push_back(LoLd);
25952 Ops.push_back(HiLd);
25953 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25956 LoAddr = St->getBasePtr();
25957 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25958 DAG.getConstant(4, StDL, MVT::i32));
25960 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25961 St->getPointerInfo(),
25962 St->isVolatile(), St->isNonTemporal(),
25963 St->getAlignment());
25964 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25965 St->getPointerInfo().getWithOffset(4),
25967 St->isNonTemporal(),
25968 MinAlign(St->getAlignment(), 4));
25969 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25972 // This is similar to the above case, but here we handle a scalar 64-bit
25973 // integer store that is extracted from a vector on a 32-bit target.
25974 // If we have SSE2, then we can treat it like a floating-point double
25975 // to get past legalization. The execution dependencies fixup pass will
25976 // choose the optimal machine instruction for the store if this really is
25977 // an integer or v2f32 rather than an f64.
25978 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25979 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25980 SDValue OldExtract = St->getOperand(1);
25981 SDValue ExtOp0 = OldExtract.getOperand(0);
25982 unsigned VecSize = ExtOp0.getValueSizeInBits();
25983 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25984 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25985 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25986 BitCast, OldExtract.getOperand(1));
25987 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25988 St->getPointerInfo(), St->isVolatile(),
25989 St->isNonTemporal(), St->getAlignment());
25995 /// Return 'true' if this vector operation is "horizontal"
25996 /// and return the operands for the horizontal operation in LHS and RHS. A
25997 /// horizontal operation performs the binary operation on successive elements
25998 /// of its first operand, then on successive elements of its second operand,
25999 /// returning the resulting values in a vector. For example, if
26000 /// A = < float a0, float a1, float a2, float a3 >
26002 /// B = < float b0, float b1, float b2, float b3 >
26003 /// then the result of doing a horizontal operation on A and B is
26004 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26005 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26006 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26007 /// set to A, RHS to B, and the routine returns 'true'.
26008 /// Note that the binary operation should have the property that if one of the
26009 /// operands is UNDEF then the result is UNDEF.
26010 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26011 // Look for the following pattern: if
26012 // A = < float a0, float a1, float a2, float a3 >
26013 // B = < float b0, float b1, float b2, float b3 >
26015 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26016 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26017 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26018 // which is A horizontal-op B.
26020 // At least one of the operands should be a vector shuffle.
26021 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26022 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26025 MVT VT = LHS.getSimpleValueType();
26027 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26028 "Unsupported vector type for horizontal add/sub");
26030 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26031 // operate independently on 128-bit lanes.
26032 unsigned NumElts = VT.getVectorNumElements();
26033 unsigned NumLanes = VT.getSizeInBits()/128;
26034 unsigned NumLaneElts = NumElts / NumLanes;
26035 assert((NumLaneElts % 2 == 0) &&
26036 "Vector type should have an even number of elements in each lane");
26037 unsigned HalfLaneElts = NumLaneElts/2;
26039 // View LHS in the form
26040 // LHS = VECTOR_SHUFFLE A, B, LMask
26041 // If LHS is not a shuffle then pretend it is the shuffle
26042 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26043 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26046 SmallVector<int, 16> LMask(NumElts);
26047 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26048 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26049 A = LHS.getOperand(0);
26050 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26051 B = LHS.getOperand(1);
26052 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26053 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26055 if (LHS.getOpcode() != ISD::UNDEF)
26057 for (unsigned i = 0; i != NumElts; ++i)
26061 // Likewise, view RHS in the form
26062 // RHS = VECTOR_SHUFFLE C, D, RMask
26064 SmallVector<int, 16> RMask(NumElts);
26065 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26066 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26067 C = RHS.getOperand(0);
26068 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26069 D = RHS.getOperand(1);
26070 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26071 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26073 if (RHS.getOpcode() != ISD::UNDEF)
26075 for (unsigned i = 0; i != NumElts; ++i)
26079 // Check that the shuffles are both shuffling the same vectors.
26080 if (!(A == C && B == D) && !(A == D && B == C))
26083 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26084 if (!A.getNode() && !B.getNode())
26087 // If A and B occur in reverse order in RHS, then "swap" them (which means
26088 // rewriting the mask).
26090 ShuffleVectorSDNode::commuteMask(RMask);
26092 // At this point LHS and RHS are equivalent to
26093 // LHS = VECTOR_SHUFFLE A, B, LMask
26094 // RHS = VECTOR_SHUFFLE A, B, RMask
26095 // Check that the masks correspond to performing a horizontal operation.
26096 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26097 for (unsigned i = 0; i != NumLaneElts; ++i) {
26098 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26100 // Ignore any UNDEF components.
26101 if (LIdx < 0 || RIdx < 0 ||
26102 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26103 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26106 // Check that successive elements are being operated on. If not, this is
26107 // not a horizontal operation.
26108 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26109 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26110 if (!(LIdx == Index && RIdx == Index + 1) &&
26111 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26116 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26117 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26121 /// Do target-specific dag combines on floating point adds.
26122 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26123 const X86Subtarget *Subtarget) {
26124 EVT VT = N->getValueType(0);
26125 SDValue LHS = N->getOperand(0);
26126 SDValue RHS = N->getOperand(1);
26128 // Try to synthesize horizontal adds from adds of shuffles.
26129 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26130 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26131 isHorizontalBinOp(LHS, RHS, true))
26132 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26136 /// Do target-specific dag combines on floating point subs.
26137 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26138 const X86Subtarget *Subtarget) {
26139 EVT VT = N->getValueType(0);
26140 SDValue LHS = N->getOperand(0);
26141 SDValue RHS = N->getOperand(1);
26143 // Try to synthesize horizontal subs from subs of shuffles.
26144 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26145 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26146 isHorizontalBinOp(LHS, RHS, false))
26147 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26151 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26152 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26153 const X86Subtarget *Subtarget) {
26154 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26156 // F[X]OR(0.0, x) -> x
26157 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26158 if (C->getValueAPF().isPosZero())
26159 return N->getOperand(1);
26161 // F[X]OR(x, 0.0) -> x
26162 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26163 if (C->getValueAPF().isPosZero())
26164 return N->getOperand(0);
26166 EVT VT = N->getValueType(0);
26167 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26169 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26170 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26172 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26173 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26174 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
26175 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26176 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26181 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26182 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26183 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26185 // Only perform optimizations if UnsafeMath is used.
26186 if (!DAG.getTarget().Options.UnsafeFPMath)
26189 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26190 // into FMINC and FMAXC, which are Commutative operations.
26191 unsigned NewOp = 0;
26192 switch (N->getOpcode()) {
26193 default: llvm_unreachable("unknown opcode");
26194 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26195 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26198 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26199 N->getOperand(0), N->getOperand(1));
26202 /// Do target-specific dag combines on X86ISD::FAND nodes.
26203 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
26204 // FAND(0.0, x) -> 0.0
26205 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26206 if (C->getValueAPF().isPosZero())
26207 return N->getOperand(0);
26209 // FAND(x, 0.0) -> 0.0
26210 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26211 if (C->getValueAPF().isPosZero())
26212 return N->getOperand(1);
26217 /// Do target-specific dag combines on X86ISD::FANDN nodes
26218 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
26219 // FANDN(0.0, x) -> x
26220 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26221 if (C->getValueAPF().isPosZero())
26222 return N->getOperand(1);
26224 // FANDN(x, 0.0) -> 0.0
26225 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26226 if (C->getValueAPF().isPosZero())
26227 return N->getOperand(1);
26232 static SDValue PerformBTCombine(SDNode *N,
26234 TargetLowering::DAGCombinerInfo &DCI) {
26235 // BT ignores high bits in the bit index operand.
26236 SDValue Op1 = N->getOperand(1);
26237 if (Op1.hasOneUse()) {
26238 unsigned BitWidth = Op1.getValueSizeInBits();
26239 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26240 APInt KnownZero, KnownOne;
26241 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26242 !DCI.isBeforeLegalizeOps());
26243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26244 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26245 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26246 DCI.CommitTargetLoweringOpt(TLO);
26251 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26252 SDValue Op = N->getOperand(0);
26253 if (Op.getOpcode() == ISD::BITCAST)
26254 Op = Op.getOperand(0);
26255 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26256 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26257 VT.getVectorElementType().getSizeInBits() ==
26258 OpVT.getVectorElementType().getSizeInBits()) {
26259 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26264 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26265 const X86Subtarget *Subtarget) {
26266 EVT VT = N->getValueType(0);
26267 if (!VT.isVector())
26270 SDValue N0 = N->getOperand(0);
26271 SDValue N1 = N->getOperand(1);
26272 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26275 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26276 // both SSE and AVX2 since there is no sign-extended shift right
26277 // operation on a vector with 64-bit elements.
26278 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26279 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26280 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26281 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26282 SDValue N00 = N0.getOperand(0);
26284 // EXTLOAD has a better solution on AVX2,
26285 // it may be replaced with X86ISD::VSEXT node.
26286 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26287 if (!ISD::isNormalLoad(N00.getNode()))
26290 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26291 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26293 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26299 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26300 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26301 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26302 /// eliminate extend, add, and shift instructions.
26303 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26304 const X86Subtarget *Subtarget) {
26305 // TODO: This should be valid for other integer types.
26306 EVT VT = Sext->getValueType(0);
26307 if (VT != MVT::i64)
26310 // We need an 'add nsw' feeding into the 'sext'.
26311 SDValue Add = Sext->getOperand(0);
26312 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26315 // Having a constant operand to the 'add' ensures that we are not increasing
26316 // the instruction count because the constant is extended for free below.
26317 // A constant operand can also become the displacement field of an LEA.
26318 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26322 // Don't make the 'add' bigger if there's no hope of combining it with some
26323 // other 'add' or 'shl' instruction.
26324 // TODO: It may be profitable to generate simpler LEA instructions in place
26325 // of single 'add' instructions, but the cost model for selecting an LEA
26326 // currently has a high threshold.
26327 bool HasLEAPotential = false;
26328 for (auto *User : Sext->uses()) {
26329 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26330 HasLEAPotential = true;
26334 if (!HasLEAPotential)
26337 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26338 int64_t AddConstant = AddOp1->getSExtValue();
26339 SDValue AddOp0 = Add.getOperand(0);
26340 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26341 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26343 // The wider add is guaranteed to not wrap because both operands are
26346 Flags.setNoSignedWrap(true);
26347 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26350 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26351 TargetLowering::DAGCombinerInfo &DCI,
26352 const X86Subtarget *Subtarget) {
26353 SDValue N0 = N->getOperand(0);
26354 EVT VT = N->getValueType(0);
26355 EVT SVT = VT.getScalarType();
26356 EVT InVT = N0.getValueType();
26357 EVT InSVT = InVT.getScalarType();
26360 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26361 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26362 // This exposes the sext to the sdivrem lowering, so that it directly extends
26363 // from AH (which we otherwise need to do contortions to access).
26364 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26365 InVT == MVT::i8 && VT == MVT::i32) {
26366 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26367 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26368 N0.getOperand(0), N0.getOperand(1));
26369 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26370 return R.getValue(1);
26373 if (!DCI.isBeforeLegalizeOps()) {
26374 if (InVT == MVT::i1) {
26375 SDValue Zero = DAG.getConstant(0, DL, VT);
26377 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26378 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26383 if (VT.isVector() && Subtarget->hasSSE2()) {
26384 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26385 EVT InVT = N.getValueType();
26386 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26387 Size / InVT.getScalarSizeInBits());
26388 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26389 DAG.getUNDEF(InVT));
26391 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26394 // If target-size is less than 128-bits, extend to a type that would extend
26395 // to 128 bits, extend that and extract the original target vector.
26396 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26397 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26398 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26399 unsigned Scale = 128 / VT.getSizeInBits();
26401 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26402 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26403 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26404 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26405 DAG.getIntPtrConstant(0, DL));
26408 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26409 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26410 if (VT.getSizeInBits() == 128 &&
26411 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26412 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26413 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26414 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26417 // On pre-AVX2 targets, split into 128-bit nodes of
26418 // ISD::SIGN_EXTEND_VECTOR_INREG.
26419 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26420 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26421 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26422 unsigned NumVecs = VT.getSizeInBits() / 128;
26423 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26424 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26425 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26427 SmallVector<SDValue, 8> Opnds;
26428 for (unsigned i = 0, Offset = 0; i != NumVecs;
26429 ++i, Offset += NumSubElts) {
26430 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26431 DAG.getIntPtrConstant(Offset, DL));
26432 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26433 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26434 Opnds.push_back(SrcVec);
26436 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26440 if (Subtarget->hasAVX() && VT.is256BitVector())
26441 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26444 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26450 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26451 const X86Subtarget* Subtarget) {
26453 EVT VT = N->getValueType(0);
26455 // Let legalize expand this if it isn't a legal type yet.
26456 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26459 EVT ScalarVT = VT.getScalarType();
26460 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26461 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26462 !Subtarget->hasAVX512()))
26465 SDValue A = N->getOperand(0);
26466 SDValue B = N->getOperand(1);
26467 SDValue C = N->getOperand(2);
26469 bool NegA = (A.getOpcode() == ISD::FNEG);
26470 bool NegB = (B.getOpcode() == ISD::FNEG);
26471 bool NegC = (C.getOpcode() == ISD::FNEG);
26473 // Negative multiplication when NegA xor NegB
26474 bool NegMul = (NegA != NegB);
26476 A = A.getOperand(0);
26478 B = B.getOperand(0);
26480 C = C.getOperand(0);
26484 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26486 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26488 return DAG.getNode(Opcode, dl, VT, A, B, C);
26491 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26492 TargetLowering::DAGCombinerInfo &DCI,
26493 const X86Subtarget *Subtarget) {
26494 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26495 // (and (i32 x86isd::setcc_carry), 1)
26496 // This eliminates the zext. This transformation is necessary because
26497 // ISD::SETCC is always legalized to i8.
26499 SDValue N0 = N->getOperand(0);
26500 EVT VT = N->getValueType(0);
26502 if (N0.getOpcode() == ISD::AND &&
26504 N0.getOperand(0).hasOneUse()) {
26505 SDValue N00 = N0.getOperand(0);
26506 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26507 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26508 if (!C || C->getZExtValue() != 1)
26510 return DAG.getNode(ISD::AND, dl, VT,
26511 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26512 N00.getOperand(0), N00.getOperand(1)),
26513 DAG.getConstant(1, dl, VT));
26517 if (N0.getOpcode() == ISD::TRUNCATE &&
26519 N0.getOperand(0).hasOneUse()) {
26520 SDValue N00 = N0.getOperand(0);
26521 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26522 return DAG.getNode(ISD::AND, dl, VT,
26523 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26524 N00.getOperand(0), N00.getOperand(1)),
26525 DAG.getConstant(1, dl, VT));
26529 if (VT.is256BitVector())
26530 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26533 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26534 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26535 // This exposes the zext to the udivrem lowering, so that it directly extends
26536 // from AH (which we otherwise need to do contortions to access).
26537 if (N0.getOpcode() == ISD::UDIVREM &&
26538 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26539 (VT == MVT::i32 || VT == MVT::i64)) {
26540 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26541 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26542 N0.getOperand(0), N0.getOperand(1));
26543 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26544 return R.getValue(1);
26550 // Optimize x == -y --> x+y == 0
26551 // x != -y --> x+y != 0
26552 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26553 const X86Subtarget* Subtarget) {
26554 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26555 SDValue LHS = N->getOperand(0);
26556 SDValue RHS = N->getOperand(1);
26557 EVT VT = N->getValueType(0);
26560 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26561 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26562 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26563 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26564 LHS.getOperand(1));
26565 return DAG.getSetCC(DL, N->getValueType(0), addV,
26566 DAG.getConstant(0, DL, addV.getValueType()), CC);
26568 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26569 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26570 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26571 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26572 RHS.getOperand(1));
26573 return DAG.getSetCC(DL, N->getValueType(0), addV,
26574 DAG.getConstant(0, DL, addV.getValueType()), CC);
26577 if (VT.getScalarType() == MVT::i1 &&
26578 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26580 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26581 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26582 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26584 if (!IsSEXT0 || !IsVZero1) {
26585 // Swap the operands and update the condition code.
26586 std::swap(LHS, RHS);
26587 CC = ISD::getSetCCSwappedOperands(CC);
26589 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26590 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26591 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26594 if (IsSEXT0 && IsVZero1) {
26595 assert(VT == LHS.getOperand(0).getValueType() &&
26596 "Uexpected operand type");
26597 if (CC == ISD::SETGT)
26598 return DAG.getConstant(0, DL, VT);
26599 if (CC == ISD::SETLE)
26600 return DAG.getConstant(1, DL, VT);
26601 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26602 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26604 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26605 "Unexpected condition code!");
26606 return LHS.getOperand(0);
26613 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26614 SDValue V0 = N->getOperand(0);
26615 SDValue V1 = N->getOperand(1);
26617 EVT VT = N->getValueType(0);
26619 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26620 // operands and changing the mask to 1. This saves us a bunch of
26621 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26622 // x86InstrInfo knows how to commute this back after instruction selection
26623 // if it would help register allocation.
26625 // TODO: If optimizing for size or a processor that doesn't suffer from
26626 // partial register update stalls, this should be transformed into a MOVSD
26627 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26629 if (VT == MVT::v2f64)
26630 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26631 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26632 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26633 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26639 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26640 // as "sbb reg,reg", since it can be extended without zext and produces
26641 // an all-ones bit which is more useful than 0/1 in some cases.
26642 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26645 return DAG.getNode(ISD::AND, DL, VT,
26646 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26647 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26649 DAG.getConstant(1, DL, VT));
26650 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26651 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26652 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26653 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26657 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26658 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26659 TargetLowering::DAGCombinerInfo &DCI,
26660 const X86Subtarget *Subtarget) {
26662 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26663 SDValue EFLAGS = N->getOperand(1);
26665 if (CC == X86::COND_A) {
26666 // Try to convert COND_A into COND_B in an attempt to facilitate
26667 // materializing "setb reg".
26669 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26670 // cannot take an immediate as its first operand.
26672 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26673 EFLAGS.getValueType().isInteger() &&
26674 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26675 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26676 EFLAGS.getNode()->getVTList(),
26677 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26678 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26679 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26683 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26684 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26686 if (CC == X86::COND_B)
26687 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26689 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26690 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26691 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26697 // Optimize branch condition evaluation.
26699 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26700 TargetLowering::DAGCombinerInfo &DCI,
26701 const X86Subtarget *Subtarget) {
26703 SDValue Chain = N->getOperand(0);
26704 SDValue Dest = N->getOperand(1);
26705 SDValue EFLAGS = N->getOperand(3);
26706 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26708 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26709 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26710 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26717 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26718 SelectionDAG &DAG) {
26719 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26720 // optimize away operation when it's from a constant.
26722 // The general transformation is:
26723 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26724 // AND(VECTOR_CMP(x,y), constant2)
26725 // constant2 = UNARYOP(constant)
26727 // Early exit if this isn't a vector operation, the operand of the
26728 // unary operation isn't a bitwise AND, or if the sizes of the operations
26729 // aren't the same.
26730 EVT VT = N->getValueType(0);
26731 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26732 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26733 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26736 // Now check that the other operand of the AND is a constant. We could
26737 // make the transformation for non-constant splats as well, but it's unclear
26738 // that would be a benefit as it would not eliminate any operations, just
26739 // perform one more step in scalar code before moving to the vector unit.
26740 if (BuildVectorSDNode *BV =
26741 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26742 // Bail out if the vector isn't a constant.
26743 if (!BV->isConstant())
26746 // Everything checks out. Build up the new and improved node.
26748 EVT IntVT = BV->getValueType(0);
26749 // Create a new constant of the appropriate type for the transformed
26751 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26752 // The AND node needs bitcasts to/from an integer vector type around it.
26753 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26754 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26755 N->getOperand(0)->getOperand(0), MaskConst);
26756 SDValue Res = DAG.getBitcast(VT, NewAnd);
26763 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26764 const X86Subtarget *Subtarget) {
26765 SDValue Op0 = N->getOperand(0);
26766 EVT VT = N->getValueType(0);
26767 EVT InVT = Op0.getValueType();
26768 EVT InSVT = InVT.getScalarType();
26769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26771 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26772 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26773 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26775 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26776 InVT.getVectorNumElements());
26777 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26779 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26780 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26782 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26788 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26789 const X86Subtarget *Subtarget) {
26790 // First try to optimize away the conversion entirely when it's
26791 // conditionally from a constant. Vectors only.
26792 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26795 // Now move on to more general possibilities.
26796 SDValue Op0 = N->getOperand(0);
26797 EVT VT = N->getValueType(0);
26798 EVT InVT = Op0.getValueType();
26799 EVT InSVT = InVT.getScalarType();
26801 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26802 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26803 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26805 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26806 InVT.getVectorNumElements());
26807 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26808 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26811 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26812 // a 32-bit target where SSE doesn't support i64->FP operations.
26813 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
26814 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26815 EVT LdVT = Ld->getValueType(0);
26817 // This transformation is not supported if the result type is f16
26818 if (VT == MVT::f16)
26821 if (!Ld->isVolatile() && !VT.isVector() &&
26822 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26823 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26824 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26825 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26826 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26833 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26834 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26835 X86TargetLowering::DAGCombinerInfo &DCI) {
26836 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26837 // the result is either zero or one (depending on the input carry bit).
26838 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26839 if (X86::isZeroNode(N->getOperand(0)) &&
26840 X86::isZeroNode(N->getOperand(1)) &&
26841 // We don't have a good way to replace an EFLAGS use, so only do this when
26843 SDValue(N, 1).use_empty()) {
26845 EVT VT = N->getValueType(0);
26846 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26847 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26848 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26849 DAG.getConstant(X86::COND_B, DL,
26852 DAG.getConstant(1, DL, VT));
26853 return DCI.CombineTo(N, Res1, CarryOut);
26859 // fold (add Y, (sete X, 0)) -> adc 0, Y
26860 // (add Y, (setne X, 0)) -> sbb -1, Y
26861 // (sub (sete X, 0), Y) -> sbb 0, Y
26862 // (sub (setne X, 0), Y) -> adc -1, Y
26863 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26866 // Look through ZExts.
26867 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26868 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26871 SDValue SetCC = Ext.getOperand(0);
26872 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26875 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26876 if (CC != X86::COND_E && CC != X86::COND_NE)
26879 SDValue Cmp = SetCC.getOperand(1);
26880 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26881 !X86::isZeroNode(Cmp.getOperand(1)) ||
26882 !Cmp.getOperand(0).getValueType().isInteger())
26885 SDValue CmpOp0 = Cmp.getOperand(0);
26886 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26887 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26889 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26890 if (CC == X86::COND_NE)
26891 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26892 DL, OtherVal.getValueType(), OtherVal,
26893 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26895 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26896 DL, OtherVal.getValueType(), OtherVal,
26897 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26900 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26901 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26902 const X86Subtarget *Subtarget) {
26903 EVT VT = N->getValueType(0);
26904 SDValue Op0 = N->getOperand(0);
26905 SDValue Op1 = N->getOperand(1);
26907 // Try to synthesize horizontal adds from adds of shuffles.
26908 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26909 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26910 isHorizontalBinOp(Op0, Op1, true))
26911 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26913 return OptimizeConditionalInDecrement(N, DAG);
26916 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26917 const X86Subtarget *Subtarget) {
26918 SDValue Op0 = N->getOperand(0);
26919 SDValue Op1 = N->getOperand(1);
26921 // X86 can't encode an immediate LHS of a sub. See if we can push the
26922 // negation into a preceding instruction.
26923 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26924 // If the RHS of the sub is a XOR with one use and a constant, invert the
26925 // immediate. Then add one to the LHS of the sub so we can turn
26926 // X-Y -> X+~Y+1, saving one register.
26927 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26928 isa<ConstantSDNode>(Op1.getOperand(1))) {
26929 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26930 EVT VT = Op0.getValueType();
26931 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26933 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26934 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26935 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26939 // Try to synthesize horizontal adds from adds of shuffles.
26940 EVT VT = N->getValueType(0);
26941 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26942 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26943 isHorizontalBinOp(Op0, Op1, true))
26944 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26946 return OptimizeConditionalInDecrement(N, DAG);
26949 /// performVZEXTCombine - Performs build vector combines
26950 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26951 TargetLowering::DAGCombinerInfo &DCI,
26952 const X86Subtarget *Subtarget) {
26954 MVT VT = N->getSimpleValueType(0);
26955 SDValue Op = N->getOperand(0);
26956 MVT OpVT = Op.getSimpleValueType();
26957 MVT OpEltVT = OpVT.getVectorElementType();
26958 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26960 // (vzext (bitcast (vzext (x)) -> (vzext x)
26962 while (V.getOpcode() == ISD::BITCAST)
26963 V = V.getOperand(0);
26965 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26966 MVT InnerVT = V.getSimpleValueType();
26967 MVT InnerEltVT = InnerVT.getVectorElementType();
26969 // If the element sizes match exactly, we can just do one larger vzext. This
26970 // is always an exact type match as vzext operates on integer types.
26971 if (OpEltVT == InnerEltVT) {
26972 assert(OpVT == InnerVT && "Types must match for vzext!");
26973 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26976 // The only other way we can combine them is if only a single element of the
26977 // inner vzext is used in the input to the outer vzext.
26978 if (InnerEltVT.getSizeInBits() < InputBits)
26981 // In this case, the inner vzext is completely dead because we're going to
26982 // only look at bits inside of the low element. Just do the outer vzext on
26983 // a bitcast of the input to the inner.
26984 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26987 // Check if we can bypass extracting and re-inserting an element of an input
26988 // vector. Essentially:
26989 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26990 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26991 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26992 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26993 SDValue ExtractedV = V.getOperand(0);
26994 SDValue OrigV = ExtractedV.getOperand(0);
26995 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26996 if (ExtractIdx->getZExtValue() == 0) {
26997 MVT OrigVT = OrigV.getSimpleValueType();
26998 // Extract a subvector if necessary...
26999 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27000 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27001 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27002 OrigVT.getVectorNumElements() / Ratio);
27003 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27004 DAG.getIntPtrConstant(0, DL));
27006 Op = DAG.getBitcast(OpVT, OrigV);
27007 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27014 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27015 DAGCombinerInfo &DCI) const {
27016 SelectionDAG &DAG = DCI.DAG;
27017 switch (N->getOpcode()) {
27019 case ISD::EXTRACT_VECTOR_ELT:
27020 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27023 case X86ISD::SHRUNKBLEND:
27024 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27025 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27026 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27027 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27028 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27029 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27030 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27033 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27034 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27035 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27036 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27037 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27038 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27039 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27040 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27041 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27042 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27043 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27044 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27045 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27047 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27049 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27050 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
27051 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
27052 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27053 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27054 case ISD::ANY_EXTEND:
27055 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27056 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27057 case ISD::SIGN_EXTEND_INREG:
27058 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27059 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27060 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27061 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27062 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27063 case X86ISD::SHUFP: // Handle all target specific shuffles
27064 case X86ISD::PALIGNR:
27065 case X86ISD::UNPCKH:
27066 case X86ISD::UNPCKL:
27067 case X86ISD::MOVHLPS:
27068 case X86ISD::MOVLHPS:
27069 case X86ISD::PSHUFB:
27070 case X86ISD::PSHUFD:
27071 case X86ISD::PSHUFHW:
27072 case X86ISD::PSHUFLW:
27073 case X86ISD::MOVSS:
27074 case X86ISD::MOVSD:
27075 case X86ISD::VPERMILPI:
27076 case X86ISD::VPERM2X128:
27077 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27078 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27079 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27085 /// isTypeDesirableForOp - Return true if the target has native support for
27086 /// the specified value type and it is 'desirable' to use the type for the
27087 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27088 /// instruction encodings are longer and some i16 instructions are slow.
27089 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27090 if (!isTypeLegal(VT))
27092 if (VT != MVT::i16)
27099 case ISD::SIGN_EXTEND:
27100 case ISD::ZERO_EXTEND:
27101 case ISD::ANY_EXTEND:
27114 /// IsDesirableToPromoteOp - This method query the target whether it is
27115 /// beneficial for dag combiner to promote the specified node. If true, it
27116 /// should return the desired promotion type by reference.
27117 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27118 EVT VT = Op.getValueType();
27119 if (VT != MVT::i16)
27122 bool Promote = false;
27123 bool Commute = false;
27124 switch (Op.getOpcode()) {
27127 LoadSDNode *LD = cast<LoadSDNode>(Op);
27128 // If the non-extending load has a single use and it's not live out, then it
27129 // might be folded.
27130 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27131 Op.hasOneUse()*/) {
27132 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27133 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27134 // The only case where we'd want to promote LOAD (rather then it being
27135 // promoted as an operand is when it's only use is liveout.
27136 if (UI->getOpcode() != ISD::CopyToReg)
27143 case ISD::SIGN_EXTEND:
27144 case ISD::ZERO_EXTEND:
27145 case ISD::ANY_EXTEND:
27150 SDValue N0 = Op.getOperand(0);
27151 // Look out for (store (shl (load), x)).
27152 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27165 SDValue N0 = Op.getOperand(0);
27166 SDValue N1 = Op.getOperand(1);
27167 if (!Commute && MayFoldLoad(N1))
27169 // Avoid disabling potential load folding opportunities.
27170 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27172 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27182 //===----------------------------------------------------------------------===//
27183 // X86 Inline Assembly Support
27184 //===----------------------------------------------------------------------===//
27186 // Helper to match a string separated by whitespace.
27187 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27188 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27190 for (StringRef Piece : Pieces) {
27191 if (!S.startswith(Piece)) // Check if the piece matches.
27194 S = S.substr(Piece.size());
27195 StringRef::size_type Pos = S.find_first_not_of(" \t");
27196 if (Pos == 0) // We matched a prefix.
27205 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27207 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27208 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27209 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27210 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27212 if (AsmPieces.size() == 3)
27214 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27221 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27222 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27224 std::string AsmStr = IA->getAsmString();
27226 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27227 if (!Ty || Ty->getBitWidth() % 16 != 0)
27230 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27231 SmallVector<StringRef, 4> AsmPieces;
27232 SplitString(AsmStr, AsmPieces, ";\n");
27234 switch (AsmPieces.size()) {
27235 default: return false;
27237 // FIXME: this should verify that we are targeting a 486 or better. If not,
27238 // we will turn this bswap into something that will be lowered to logical
27239 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27240 // lower so don't worry about this.
27242 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27243 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27244 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27245 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27246 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27247 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27248 // No need to check constraints, nothing other than the equivalent of
27249 // "=r,0" would be valid here.
27250 return IntrinsicLowering::LowerToByteSwap(CI);
27253 // rorw $$8, ${0:w} --> llvm.bswap.i16
27254 if (CI->getType()->isIntegerTy(16) &&
27255 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27256 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27257 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27259 StringRef ConstraintsStr = IA->getConstraintString();
27260 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27261 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27262 if (clobbersFlagRegisters(AsmPieces))
27263 return IntrinsicLowering::LowerToByteSwap(CI);
27267 if (CI->getType()->isIntegerTy(32) &&
27268 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27269 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27270 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27271 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27273 StringRef ConstraintsStr = IA->getConstraintString();
27274 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27275 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27276 if (clobbersFlagRegisters(AsmPieces))
27277 return IntrinsicLowering::LowerToByteSwap(CI);
27280 if (CI->getType()->isIntegerTy(64)) {
27281 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27282 if (Constraints.size() >= 2 &&
27283 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27284 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27285 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27286 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27287 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27288 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27289 return IntrinsicLowering::LowerToByteSwap(CI);
27297 /// getConstraintType - Given a constraint letter, return the type of
27298 /// constraint it is for this target.
27299 X86TargetLowering::ConstraintType
27300 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27301 if (Constraint.size() == 1) {
27302 switch (Constraint[0]) {
27313 return C_RegisterClass;
27337 return TargetLowering::getConstraintType(Constraint);
27340 /// Examine constraint type and operand type and determine a weight value.
27341 /// This object must already have been set up with the operand type
27342 /// and the current alternative constraint selected.
27343 TargetLowering::ConstraintWeight
27344 X86TargetLowering::getSingleConstraintMatchWeight(
27345 AsmOperandInfo &info, const char *constraint) const {
27346 ConstraintWeight weight = CW_Invalid;
27347 Value *CallOperandVal = info.CallOperandVal;
27348 // If we don't have a value, we can't do a match,
27349 // but allow it at the lowest weight.
27350 if (!CallOperandVal)
27352 Type *type = CallOperandVal->getType();
27353 // Look at the constraint type.
27354 switch (*constraint) {
27356 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27367 if (CallOperandVal->getType()->isIntegerTy())
27368 weight = CW_SpecificReg;
27373 if (type->isFloatingPointTy())
27374 weight = CW_SpecificReg;
27377 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27378 weight = CW_SpecificReg;
27382 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27383 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27384 weight = CW_Register;
27387 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27388 if (C->getZExtValue() <= 31)
27389 weight = CW_Constant;
27393 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27394 if (C->getZExtValue() <= 63)
27395 weight = CW_Constant;
27399 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27400 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27401 weight = CW_Constant;
27405 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27406 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27407 weight = CW_Constant;
27411 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27412 if (C->getZExtValue() <= 3)
27413 weight = CW_Constant;
27417 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27418 if (C->getZExtValue() <= 0xff)
27419 weight = CW_Constant;
27424 if (isa<ConstantFP>(CallOperandVal)) {
27425 weight = CW_Constant;
27429 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27430 if ((C->getSExtValue() >= -0x80000000LL) &&
27431 (C->getSExtValue() <= 0x7fffffffLL))
27432 weight = CW_Constant;
27436 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27437 if (C->getZExtValue() <= 0xffffffff)
27438 weight = CW_Constant;
27445 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27446 /// with another that has more specific requirements based on the type of the
27447 /// corresponding operand.
27448 const char *X86TargetLowering::
27449 LowerXConstraint(EVT ConstraintVT) const {
27450 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27451 // 'f' like normal targets.
27452 if (ConstraintVT.isFloatingPoint()) {
27453 if (Subtarget->hasSSE2())
27455 if (Subtarget->hasSSE1())
27459 return TargetLowering::LowerXConstraint(ConstraintVT);
27462 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27463 /// vector. If it is invalid, don't add anything to Ops.
27464 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27465 std::string &Constraint,
27466 std::vector<SDValue>&Ops,
27467 SelectionDAG &DAG) const {
27470 // Only support length 1 constraints for now.
27471 if (Constraint.length() > 1) return;
27473 char ConstraintLetter = Constraint[0];
27474 switch (ConstraintLetter) {
27477 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27478 if (C->getZExtValue() <= 31) {
27479 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27480 Op.getValueType());
27486 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27487 if (C->getZExtValue() <= 63) {
27488 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27489 Op.getValueType());
27495 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27496 if (isInt<8>(C->getSExtValue())) {
27497 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27498 Op.getValueType());
27504 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27505 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27506 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27507 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27508 Op.getValueType());
27514 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27515 if (C->getZExtValue() <= 3) {
27516 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27517 Op.getValueType());
27523 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27524 if (C->getZExtValue() <= 255) {
27525 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27526 Op.getValueType());
27532 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27533 if (C->getZExtValue() <= 127) {
27534 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27535 Op.getValueType());
27541 // 32-bit signed value
27542 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27543 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27544 C->getSExtValue())) {
27545 // Widen to 64 bits here to get it sign extended.
27546 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27549 // FIXME gcc accepts some relocatable values here too, but only in certain
27550 // memory models; it's complicated.
27555 // 32-bit unsigned value
27556 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27557 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27558 C->getZExtValue())) {
27559 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27560 Op.getValueType());
27564 // FIXME gcc accepts some relocatable values here too, but only in certain
27565 // memory models; it's complicated.
27569 // Literal immediates are always ok.
27570 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27571 // Widen to 64 bits here to get it sign extended.
27572 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27576 // In any sort of PIC mode addresses need to be computed at runtime by
27577 // adding in a register or some sort of table lookup. These can't
27578 // be used as immediates.
27579 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27582 // If we are in non-pic codegen mode, we allow the address of a global (with
27583 // an optional displacement) to be used with 'i'.
27584 GlobalAddressSDNode *GA = nullptr;
27585 int64_t Offset = 0;
27587 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27589 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27590 Offset += GA->getOffset();
27592 } else if (Op.getOpcode() == ISD::ADD) {
27593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27594 Offset += C->getZExtValue();
27595 Op = Op.getOperand(0);
27598 } else if (Op.getOpcode() == ISD::SUB) {
27599 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27600 Offset += -C->getZExtValue();
27601 Op = Op.getOperand(0);
27606 // Otherwise, this isn't something we can handle, reject it.
27610 const GlobalValue *GV = GA->getGlobal();
27611 // If we require an extra load to get this address, as in PIC mode, we
27612 // can't accept it.
27613 if (isGlobalStubReference(
27614 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27617 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27618 GA->getValueType(0), Offset);
27623 if (Result.getNode()) {
27624 Ops.push_back(Result);
27627 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27630 std::pair<unsigned, const TargetRegisterClass *>
27631 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27632 StringRef Constraint,
27634 // First, see if this is a constraint that directly corresponds to an LLVM
27636 if (Constraint.size() == 1) {
27637 // GCC Constraint Letters
27638 switch (Constraint[0]) {
27640 // TODO: Slight differences here in allocation order and leaving
27641 // RIP in the class. Do they matter any more here than they do
27642 // in the normal allocation?
27643 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27644 if (Subtarget->is64Bit()) {
27645 if (VT == MVT::i32 || VT == MVT::f32)
27646 return std::make_pair(0U, &X86::GR32RegClass);
27647 if (VT == MVT::i16)
27648 return std::make_pair(0U, &X86::GR16RegClass);
27649 if (VT == MVT::i8 || VT == MVT::i1)
27650 return std::make_pair(0U, &X86::GR8RegClass);
27651 if (VT == MVT::i64 || VT == MVT::f64)
27652 return std::make_pair(0U, &X86::GR64RegClass);
27655 // 32-bit fallthrough
27656 case 'Q': // Q_REGS
27657 if (VT == MVT::i32 || VT == MVT::f32)
27658 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27659 if (VT == MVT::i16)
27660 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27661 if (VT == MVT::i8 || VT == MVT::i1)
27662 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27663 if (VT == MVT::i64)
27664 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27666 case 'r': // GENERAL_REGS
27667 case 'l': // INDEX_REGS
27668 if (VT == MVT::i8 || VT == MVT::i1)
27669 return std::make_pair(0U, &X86::GR8RegClass);
27670 if (VT == MVT::i16)
27671 return std::make_pair(0U, &X86::GR16RegClass);
27672 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27673 return std::make_pair(0U, &X86::GR32RegClass);
27674 return std::make_pair(0U, &X86::GR64RegClass);
27675 case 'R': // LEGACY_REGS
27676 if (VT == MVT::i8 || VT == MVT::i1)
27677 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27678 if (VT == MVT::i16)
27679 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27680 if (VT == MVT::i32 || !Subtarget->is64Bit())
27681 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27682 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27683 case 'f': // FP Stack registers.
27684 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27685 // value to the correct fpstack register class.
27686 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27687 return std::make_pair(0U, &X86::RFP32RegClass);
27688 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27689 return std::make_pair(0U, &X86::RFP64RegClass);
27690 return std::make_pair(0U, &X86::RFP80RegClass);
27691 case 'y': // MMX_REGS if MMX allowed.
27692 if (!Subtarget->hasMMX()) break;
27693 return std::make_pair(0U, &X86::VR64RegClass);
27694 case 'Y': // SSE_REGS if SSE2 allowed
27695 if (!Subtarget->hasSSE2()) break;
27697 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27698 if (!Subtarget->hasSSE1()) break;
27700 switch (VT.SimpleTy) {
27702 // Scalar SSE types.
27705 return std::make_pair(0U, &X86::FR32RegClass);
27708 return std::make_pair(0U, &X86::FR64RegClass);
27716 return std::make_pair(0U, &X86::VR128RegClass);
27724 return std::make_pair(0U, &X86::VR256RegClass);
27729 return std::make_pair(0U, &X86::VR512RegClass);
27735 // Use the default implementation in TargetLowering to convert the register
27736 // constraint into a member of a register class.
27737 std::pair<unsigned, const TargetRegisterClass*> Res;
27738 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27740 // Not found as a standard register?
27742 // Map st(0) -> st(7) -> ST0
27743 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27744 tolower(Constraint[1]) == 's' &&
27745 tolower(Constraint[2]) == 't' &&
27746 Constraint[3] == '(' &&
27747 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27748 Constraint[5] == ')' &&
27749 Constraint[6] == '}') {
27751 Res.first = X86::FP0+Constraint[4]-'0';
27752 Res.second = &X86::RFP80RegClass;
27756 // GCC allows "st(0)" to be called just plain "st".
27757 if (StringRef("{st}").equals_lower(Constraint)) {
27758 Res.first = X86::FP0;
27759 Res.second = &X86::RFP80RegClass;
27764 if (StringRef("{flags}").equals_lower(Constraint)) {
27765 Res.first = X86::EFLAGS;
27766 Res.second = &X86::CCRRegClass;
27770 // 'A' means EAX + EDX.
27771 if (Constraint == "A") {
27772 Res.first = X86::EAX;
27773 Res.second = &X86::GR32_ADRegClass;
27779 // Otherwise, check to see if this is a register class of the wrong value
27780 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27781 // turn into {ax},{dx}.
27782 // MVT::Other is used to specify clobber names.
27783 if (Res.second->hasType(VT) || VT == MVT::Other)
27784 return Res; // Correct type already, nothing to do.
27786 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27787 // return "eax". This should even work for things like getting 64bit integer
27788 // registers when given an f64 type.
27789 const TargetRegisterClass *Class = Res.second;
27790 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27791 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27792 unsigned Size = VT.getSizeInBits();
27793 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27794 : Size == 16 ? MVT::i16
27795 : Size == 32 ? MVT::i32
27796 : Size == 64 ? MVT::i64
27798 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27800 Res.first = DestReg;
27801 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27802 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27803 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27804 : &X86::GR64RegClass;
27805 assert(Res.second->contains(Res.first) && "Register in register class");
27807 // No register found/type mismatch.
27809 Res.second = nullptr;
27811 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27812 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27813 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27814 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27815 Class == &X86::VR512RegClass) {
27816 // Handle references to XMM physical registers that got mapped into the
27817 // wrong class. This can happen with constraints like {xmm0} where the
27818 // target independent register mapper will just pick the first match it can
27819 // find, ignoring the required type.
27821 if (VT == MVT::f32 || VT == MVT::i32)
27822 Res.second = &X86::FR32RegClass;
27823 else if (VT == MVT::f64 || VT == MVT::i64)
27824 Res.second = &X86::FR64RegClass;
27825 else if (X86::VR128RegClass.hasType(VT))
27826 Res.second = &X86::VR128RegClass;
27827 else if (X86::VR256RegClass.hasType(VT))
27828 Res.second = &X86::VR256RegClass;
27829 else if (X86::VR512RegClass.hasType(VT))
27830 Res.second = &X86::VR512RegClass;
27832 // Type mismatch and not a clobber: Return an error;
27834 Res.second = nullptr;
27841 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27842 const AddrMode &AM, Type *Ty,
27843 unsigned AS) const {
27844 // Scaling factors are not free at all.
27845 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27846 // will take 2 allocations in the out of order engine instead of 1
27847 // for plain addressing mode, i.e. inst (reg1).
27849 // vaddps (%rsi,%drx), %ymm0, %ymm1
27850 // Requires two allocations (one for the load, one for the computation)
27852 // vaddps (%rsi), %ymm0, %ymm1
27853 // Requires just 1 allocation, i.e., freeing allocations for other operations
27854 // and having less micro operations to execute.
27856 // For some X86 architectures, this is even worse because for instance for
27857 // stores, the complex addressing mode forces the instruction to use the
27858 // "load" ports instead of the dedicated "store" port.
27859 // E.g., on Haswell:
27860 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27861 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27862 if (isLegalAddressingMode(DL, AM, Ty, AS))
27863 // Scale represents reg2 * scale, thus account for 1
27864 // as soon as we use a second register.
27865 return AM.Scale != 0;
27869 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27870 // Integer division on x86 is expensive. However, when aggressively optimizing
27871 // for code size, we prefer to use a div instruction, as it is usually smaller
27872 // than the alternative sequence.
27873 // The exception to this is vector division. Since x86 doesn't have vector
27874 // integer division, leaving the division as-is is a loss even in terms of
27875 // size, because it will have to be scalarized, while the alternative code
27876 // sequence can be performed in vector form.
27877 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27878 Attribute::MinSize);
27879 return OptSize && !VT.isVector();
27882 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27883 TargetLowering::ArgListTy& Args) const {
27884 // The MCU psABI requires some arguments to be passed in-register.
27885 // For regular calls, the inreg arguments are marked by the front-end.
27886 // However, for compiler generated library calls, we have to patch this
27888 if (!Subtarget->isTargetMCU() || !Args.size())
27891 unsigned FreeRegs = 3;
27892 for (auto &Arg : Args) {
27893 // For library functions, we do not expect any fancy types.
27894 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27895 unsigned SizeInRegs = (Size + 31) / 32;
27896 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27899 Arg.isInReg = true;
27900 FreeRegs -= SizeInRegs;