1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
162 RegInfo = TM.getRegisterInfo();
163 TD = getDataLayout();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
184 // Bypass i32 with i8 on Atom when compiling with O2
185 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default)
186 addBypassSlowDiv(32, 8);
188 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
189 // Setup Windows compiler runtime calls.
190 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
191 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
192 setLibcallName(RTLIB::SREM_I64, "_allrem");
193 setLibcallName(RTLIB::UREM_I64, "_aullrem");
194 setLibcallName(RTLIB::MUL_I64, "_allmul");
195 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
197 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
198 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
199 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
201 // The _ftol2 runtime function has an unusual calling conv, which
202 // is modeled by a special pseudo-instruction.
203 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
204 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
205 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
206 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
209 if (Subtarget->isTargetDarwin()) {
210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
211 setUseUnderscoreSetJmp(false);
212 setUseUnderscoreLongJmp(false);
213 } else if (Subtarget->isTargetMingw()) {
214 // MS runtime is weird: it exports _setjmp, but longjmp!
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(false);
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(true);
222 // Set up the register classes.
223 addRegisterClass(MVT::i8, &X86::GR8RegClass);
224 addRegisterClass(MVT::i16, &X86::GR16RegClass);
225 addRegisterClass(MVT::i32, &X86::GR32RegClass);
226 if (Subtarget->is64Bit())
227 addRegisterClass(MVT::i64, &X86::GR64RegClass);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 // We don't accept any truncstore of integer registers.
232 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
233 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
235 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
239 // SETOEQ and SETUNE require checking two conditions.
240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 } else if (!TM.Options.UseSoftFloat) {
257 // We have an algorithm for SSE2->double, and we turn this into a
258 // 64-bit FILD followed by conditional FADD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
260 // We have an algorithm for SSE2, and we turn this into a 64-bit
261 // FILD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
270 if (!TM.Options.UseSoftFloat) {
271 // SSE has no i16 to fp conversion, only i32
272 if (X86ScalarSSEf32) {
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 // f32 and f64 cases are Legal, f80 case is not
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
286 // are Legal, f80 is custom lowered.
287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
295 if (X86ScalarSSEf32) {
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
297 // f32 and f64 cases are Legal, f80 case is not
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 // Handle FP_TO_UINT by promoting the destination to a larger signed
306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
310 if (Subtarget->is64Bit()) {
311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
313 } else if (!TM.Options.UseSoftFloat) {
314 // Since AVX is a superset of SSE3, only check for SSE here.
315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 if (isTargetFTOL()) {
327 // Use the _ftol2 runtime function, which has a pseudo-instruction
328 // to handle its weird calling convention.
329 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
332 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
333 if (!X86ScalarSSEf64) {
334 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
335 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
338 // Without SSE, i64->f64 goes through memory.
339 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
343 // Scalar integer divide and remainder are lowered to use operations that
344 // produce two results, to match the available instructions. This exposes
345 // the two-result form to trivial CSE, which is able to combine x/y and x%y
346 // into a single instruction.
348 // Scalar integer multiply-high is also lowered to use two-result
349 // operations, to match the available instructions. However, plain multiply
350 // (low) operations are left as Legal, as there are single-result
351 // instructions for this in x86. Using the two-result multiply instructions
352 // when both high and low results are needed must be arranged by dagcombine.
353 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
355 setOperationAction(ISD::MULHS, VT, Expand);
356 setOperationAction(ISD::MULHU, VT, Expand);
357 setOperationAction(ISD::SDIV, VT, Expand);
358 setOperationAction(ISD::UDIV, VT, Expand);
359 setOperationAction(ISD::SREM, VT, Expand);
360 setOperationAction(ISD::UREM, VT, Expand);
362 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
363 setOperationAction(ISD::ADDC, VT, Custom);
364 setOperationAction(ISD::ADDE, VT, Custom);
365 setOperationAction(ISD::SUBC, VT, Custom);
366 setOperationAction(ISD::SUBE, VT, Custom);
369 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
370 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
371 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
372 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
373 if (Subtarget->is64Bit())
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
378 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
379 setOperationAction(ISD::FREM , MVT::f32 , Expand);
380 setOperationAction(ISD::FREM , MVT::f64 , Expand);
381 setOperationAction(ISD::FREM , MVT::f80 , Expand);
382 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
384 // Promote the i8 variants and force them on up to i32 which has a shorter
386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
387 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
389 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
390 if (Subtarget->hasBMI()) {
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
396 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
397 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
402 if (Subtarget->hasLZCNT()) {
403 // When promoting the i8 variants, force them to i32 for a shorter
405 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
406 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
408 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
411 if (Subtarget->is64Bit())
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
414 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
426 if (Subtarget->hasPOPCNT()) {
427 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
429 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
430 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
431 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
436 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
437 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
439 // These should be promoted to a larger select which is supported.
440 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
441 // X86 wants to expand cmov itself.
442 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
443 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
444 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
445 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
447 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
448 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
451 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
454 if (Subtarget->is64Bit()) {
455 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
456 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
458 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
459 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support
460 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
461 // support continuation, user-level threading, and etc.. As a result, no
462 // other SjLj exception interfaces are implemented and please don't build
463 // your own exception handling based on them.
464 // LLVM/Clang supports zero-cost DWARF exception handling.
465 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
466 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
469 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
470 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
471 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
472 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
475 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
476 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
479 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
480 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
481 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
482 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
484 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
485 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
486 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
487 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
488 if (Subtarget->is64Bit()) {
489 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
490 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
491 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
494 if (Subtarget->hasSSE1())
495 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
497 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
498 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
500 // On X86 and X86-64, atomic operations are lowered to locked instructions.
501 // Locked instructions, in turn, have implicit fence semantics (all memory
502 // operations are flushed before issuing the locked instruction, and they
503 // are not buffered), so we can fold away the common pattern of
504 // fence-atomic-fence.
505 setShouldFoldAtomicFences(true);
507 // Expand certain atomics
508 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
512 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
515 if (!Subtarget->is64Bit()) {
516 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
517 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
518 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
519 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
520 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
521 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
522 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
523 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
524 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
525 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
526 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
527 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
530 if (Subtarget->hasCmpxchg16b()) {
531 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
534 // FIXME - use subtarget debug flags
535 if (!Subtarget->isTargetDarwin() &&
536 !Subtarget->isTargetELF() &&
537 !Subtarget->isTargetCygMing()) {
538 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
541 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
542 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
543 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
544 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
545 if (Subtarget->is64Bit()) {
546 setExceptionPointerRegister(X86::RAX);
547 setExceptionSelectorRegister(X86::RDX);
549 setExceptionPointerRegister(X86::EAX);
550 setExceptionSelectorRegister(X86::EDX);
552 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
553 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
555 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
556 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
558 setOperationAction(ISD::TRAP, MVT::Other, Legal);
559 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
561 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
562 setOperationAction(ISD::VASTART , MVT::Other, Custom);
563 setOperationAction(ISD::VAEND , MVT::Other, Expand);
564 if (Subtarget->is64Bit()) {
565 setOperationAction(ISD::VAARG , MVT::Other, Custom);
566 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
568 setOperationAction(ISD::VAARG , MVT::Other, Expand);
569 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
572 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
573 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
575 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
576 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
577 MVT::i64 : MVT::i32, Custom);
578 else if (TM.Options.EnableSegmentedStacks)
579 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
580 MVT::i64 : MVT::i32, Custom);
582 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
583 MVT::i64 : MVT::i32, Expand);
585 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
586 // f32 and f64 use SSE.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f32, &X86::FR32RegClass);
589 addRegisterClass(MVT::f64, &X86::FR64RegClass);
591 // Use ANDPD to simulate FABS.
592 setOperationAction(ISD::FABS , MVT::f64, Custom);
593 setOperationAction(ISD::FABS , MVT::f32, Custom);
595 // Use XORP to simulate FNEG.
596 setOperationAction(ISD::FNEG , MVT::f64, Custom);
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 // Use ANDPD and ORPD to simulate FCOPYSIGN.
600 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
601 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
603 // Lower this to FGETSIGNx86 plus an AND.
604 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
605 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
607 // We don't support sin/cos/fmod
608 setOperationAction(ISD::FSIN , MVT::f64, Expand);
609 setOperationAction(ISD::FCOS , MVT::f64, Expand);
610 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
611 setOperationAction(ISD::FSIN , MVT::f32, Expand);
612 setOperationAction(ISD::FCOS , MVT::f32, Expand);
613 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
615 // Expand FP immediates into loads from the stack, except for the special
617 addLegalFPImmediate(APFloat(+0.0)); // xorpd
618 addLegalFPImmediate(APFloat(+0.0f)); // xorps
619 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
620 // Use SSE for f32, x87 for f64.
621 // Set up the FP register classes.
622 addRegisterClass(MVT::f32, &X86::FR32RegClass);
623 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
625 // Use ANDPS to simulate FABS.
626 setOperationAction(ISD::FABS , MVT::f32, Custom);
628 // Use XORP to simulate FNEG.
629 setOperationAction(ISD::FNEG , MVT::f32, Custom);
631 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
633 // Use ANDPS and ORPS to simulate FCOPYSIGN.
634 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
635 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
637 // We don't support sin/cos/fmod
638 setOperationAction(ISD::FSIN , MVT::f32, Expand);
639 setOperationAction(ISD::FCOS , MVT::f32, Expand);
640 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
642 // Special cases we handle for FP constants.
643 addLegalFPImmediate(APFloat(+0.0f)); // xorps
644 addLegalFPImmediate(APFloat(+0.0)); // FLD0
645 addLegalFPImmediate(APFloat(+1.0)); // FLD1
646 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
647 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
649 if (!TM.Options.UnsafeFPMath) {
650 setOperationAction(ISD::FSIN , MVT::f64, Expand);
651 setOperationAction(ISD::FCOS , MVT::f64, Expand);
652 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
654 } else if (!TM.Options.UseSoftFloat) {
655 // f32 and f64 in x87.
656 // Set up the FP register classes.
657 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
658 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
660 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
661 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
662 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
663 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
665 if (!TM.Options.UnsafeFPMath) {
666 setOperationAction(ISD::FSIN , MVT::f64, Expand);
667 setOperationAction(ISD::FSIN , MVT::f32, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FCOS , MVT::f32, Expand);
670 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
671 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
673 addLegalFPImmediate(APFloat(+0.0)); // FLD0
674 addLegalFPImmediate(APFloat(+1.0)); // FLD1
675 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
676 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
677 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
678 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
679 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
680 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
683 // We don't support FMA.
684 setOperationAction(ISD::FMA, MVT::f64, Expand);
685 setOperationAction(ISD::FMA, MVT::f32, Expand);
687 // Long double always uses X87.
688 if (!TM.Options.UseSoftFloat) {
689 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
690 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
691 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
693 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
694 addLegalFPImmediate(TmpFlt); // FLD0
696 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
699 APFloat TmpFlt2(+1.0);
700 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
702 addLegalFPImmediate(TmpFlt2); // FLD1
703 TmpFlt2.changeSign();
704 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
707 if (!TM.Options.UnsafeFPMath) {
708 setOperationAction(ISD::FSIN , MVT::f80, Expand);
709 setOperationAction(ISD::FCOS , MVT::f80, Expand);
710 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
713 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
714 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
715 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
716 setOperationAction(ISD::FRINT, MVT::f80, Expand);
717 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
718 setOperationAction(ISD::FMA, MVT::f80, Expand);
721 // Always use a library call for pow.
722 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
723 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
724 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
726 setOperationAction(ISD::FLOG, MVT::f80, Expand);
727 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
728 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
729 setOperationAction(ISD::FEXP, MVT::f80, Expand);
730 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
732 // First set operation action for all vector types to either promote
733 // (for widening) or expand (for scalarization). Then we will selectively
734 // turn on ones that can be effectively codegen'd.
735 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
736 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
737 MVT VT = (MVT::SimpleValueType)i;
738 setOperationAction(ISD::ADD , VT, Expand);
739 setOperationAction(ISD::SUB , VT, Expand);
740 setOperationAction(ISD::FADD, VT, Expand);
741 setOperationAction(ISD::FNEG, VT, Expand);
742 setOperationAction(ISD::FSUB, VT, Expand);
743 setOperationAction(ISD::MUL , VT, Expand);
744 setOperationAction(ISD::FMUL, VT, Expand);
745 setOperationAction(ISD::SDIV, VT, Expand);
746 setOperationAction(ISD::UDIV, VT, Expand);
747 setOperationAction(ISD::FDIV, VT, Expand);
748 setOperationAction(ISD::SREM, VT, Expand);
749 setOperationAction(ISD::UREM, VT, Expand);
750 setOperationAction(ISD::LOAD, VT, Expand);
751 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
752 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
753 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
754 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
755 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
756 setOperationAction(ISD::FABS, VT, Expand);
757 setOperationAction(ISD::FSIN, VT, Expand);
758 setOperationAction(ISD::FSINCOS, VT, Expand);
759 setOperationAction(ISD::FCOS, VT, Expand);
760 setOperationAction(ISD::FSINCOS, VT, Expand);
761 setOperationAction(ISD::FREM, VT, Expand);
762 setOperationAction(ISD::FMA, VT, Expand);
763 setOperationAction(ISD::FPOWI, VT, Expand);
764 setOperationAction(ISD::FSQRT, VT, Expand);
765 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
766 setOperationAction(ISD::FFLOOR, VT, Expand);
767 setOperationAction(ISD::FCEIL, VT, Expand);
768 setOperationAction(ISD::FTRUNC, VT, Expand);
769 setOperationAction(ISD::FRINT, VT, Expand);
770 setOperationAction(ISD::FNEARBYINT, VT, Expand);
771 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
772 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
773 setOperationAction(ISD::SDIVREM, VT, Expand);
774 setOperationAction(ISD::UDIVREM, VT, Expand);
775 setOperationAction(ISD::FPOW, VT, Expand);
776 setOperationAction(ISD::CTPOP, VT, Expand);
777 setOperationAction(ISD::CTTZ, VT, Expand);
778 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
779 setOperationAction(ISD::CTLZ, VT, Expand);
780 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
781 setOperationAction(ISD::SHL, VT, Expand);
782 setOperationAction(ISD::SRA, VT, Expand);
783 setOperationAction(ISD::SRL, VT, Expand);
784 setOperationAction(ISD::ROTL, VT, Expand);
785 setOperationAction(ISD::ROTR, VT, Expand);
786 setOperationAction(ISD::BSWAP, VT, Expand);
787 setOperationAction(ISD::SETCC, VT, Expand);
788 setOperationAction(ISD::FLOG, VT, Expand);
789 setOperationAction(ISD::FLOG2, VT, Expand);
790 setOperationAction(ISD::FLOG10, VT, Expand);
791 setOperationAction(ISD::FEXP, VT, Expand);
792 setOperationAction(ISD::FEXP2, VT, Expand);
793 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
794 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
795 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
796 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
797 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
798 setOperationAction(ISD::TRUNCATE, VT, Expand);
799 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
800 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
801 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
802 setOperationAction(ISD::VSELECT, VT, Expand);
803 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
804 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
805 setTruncStoreAction(VT,
806 (MVT::SimpleValueType)InnerVT, Expand);
807 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
808 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
809 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
812 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
813 // with -msoft-float, disable use of MMX as well.
814 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
815 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
816 // No operations on x86mmx supported, everything uses intrinsics.
819 // MMX-sized vectors (other than x86mmx) are expected to be expanded
820 // into smaller operations.
821 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
822 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
823 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
824 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
825 setOperationAction(ISD::AND, MVT::v8i8, Expand);
826 setOperationAction(ISD::AND, MVT::v4i16, Expand);
827 setOperationAction(ISD::AND, MVT::v2i32, Expand);
828 setOperationAction(ISD::AND, MVT::v1i64, Expand);
829 setOperationAction(ISD::OR, MVT::v8i8, Expand);
830 setOperationAction(ISD::OR, MVT::v4i16, Expand);
831 setOperationAction(ISD::OR, MVT::v2i32, Expand);
832 setOperationAction(ISD::OR, MVT::v1i64, Expand);
833 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
834 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
835 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
836 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
837 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
840 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
842 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
843 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
844 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
845 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
846 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
847 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
848 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
849 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
851 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
852 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
854 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
855 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
856 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
857 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
858 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
859 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
860 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
861 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
862 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
863 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
864 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
865 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
868 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
869 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
871 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
872 // registers cannot be used even for integer operations.
873 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
874 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
875 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
876 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
878 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
879 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
880 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
881 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
882 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
883 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
884 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
885 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
886 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
887 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
888 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
889 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
890 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
891 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
892 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
893 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
894 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
895 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
897 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
898 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
899 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
900 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
902 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
903 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
905 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
906 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
908 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
911 // Do not attempt to custom lower non-power-of-2 vectors
912 if (!isPowerOf2_32(VT.getVectorNumElements()))
914 // Do not attempt to custom lower non-128-bit vectors
915 if (!VT.is128BitVector())
917 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
918 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
919 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
922 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
923 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
924 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
925 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
926 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
927 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
929 if (Subtarget->is64Bit()) {
930 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
931 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
934 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
935 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
936 MVT VT = (MVT::SimpleValueType)i;
938 // Do not attempt to promote non-128-bit vectors
939 if (!VT.is128BitVector())
942 setOperationAction(ISD::AND, VT, Promote);
943 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
944 setOperationAction(ISD::OR, VT, Promote);
945 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
946 setOperationAction(ISD::XOR, VT, Promote);
947 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
948 setOperationAction(ISD::LOAD, VT, Promote);
949 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
950 setOperationAction(ISD::SELECT, VT, Promote);
951 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
954 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
956 // Custom lower v2i64 and v2f64 selects.
957 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
958 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
959 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
960 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
962 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
963 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
965 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
966 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
967 // As there is no 64-bit GPR available, we need build a special custom
968 // sequence to convert from v2i32 to v2f32.
969 if (!Subtarget->is64Bit())
970 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
972 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
973 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
975 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
978 if (Subtarget->hasSSE41()) {
979 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
980 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
981 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
982 setOperationAction(ISD::FRINT, MVT::f32, Legal);
983 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
984 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
985 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
986 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
987 setOperationAction(ISD::FRINT, MVT::f64, Legal);
988 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
990 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
991 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
992 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
993 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
994 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
995 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
996 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
997 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
998 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
999 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1001 // FIXME: Do we need to handle scalar-to-vector here?
1002 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1004 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1005 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1006 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1007 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1008 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1010 // i8 and i16 vectors are custom , because the source register and source
1011 // source memory operand types are not the same width. f32 vectors are
1012 // custom since the immediate controlling the insert encodes additional
1014 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1019 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1020 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1021 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1022 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1024 // FIXME: these should be Legal but thats only for the case where
1025 // the index is constant. For now custom expand to deal with that.
1026 if (Subtarget->is64Bit()) {
1027 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1028 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1032 if (Subtarget->hasSSE2()) {
1033 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1034 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1036 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1037 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1039 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1040 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1042 if (Subtarget->hasInt256()) {
1043 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1049 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1051 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1052 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1054 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1055 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1057 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1059 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1060 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1063 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1064 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1065 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1066 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1067 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1068 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1069 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1071 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1072 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1073 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1075 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1076 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1077 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1078 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1079 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1080 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1081 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1082 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1083 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1084 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1085 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1086 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1088 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1089 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1090 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1091 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1092 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1098 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1099 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1101 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1102 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1104 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1106 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1107 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1108 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1110 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1111 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1112 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1114 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1116 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1119 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1120 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1122 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1123 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1125 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1127 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1128 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1129 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1130 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1132 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1133 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1134 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1136 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1137 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1138 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1139 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1141 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1142 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1143 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1144 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1145 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1146 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1148 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1149 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1150 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1151 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1152 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1153 setOperationAction(ISD::FMA, MVT::f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::f64, Legal);
1157 if (Subtarget->hasInt256()) {
1158 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1159 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1160 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1161 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1163 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1164 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1165 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1166 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1168 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1169 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1170 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1171 // Don't lower v32i8 because there is no 128-bit byte mul
1173 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1175 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1176 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1178 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1179 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1181 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1183 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1185 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1186 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1187 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1188 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1190 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1191 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1192 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1193 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1195 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1196 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1197 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1198 // Don't lower v32i8 because there is no 128-bit byte mul
1200 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1201 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1203 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1204 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1206 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1209 // Custom lower several nodes for 256-bit types.
1210 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1211 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1212 MVT VT = (MVT::SimpleValueType)i;
1214 // Extract subvector is special because the value type
1215 // (result) is 128-bit but the source is 256-bit wide.
1216 if (VT.is128BitVector())
1217 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1219 // Do not attempt to custom lower other non-256-bit vectors
1220 if (!VT.is256BitVector())
1223 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1224 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1225 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1226 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1227 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1228 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1229 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1232 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1233 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1234 MVT VT = (MVT::SimpleValueType)i;
1236 // Do not attempt to promote non-256-bit vectors
1237 if (!VT.is256BitVector())
1240 setOperationAction(ISD::AND, VT, Promote);
1241 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1242 setOperationAction(ISD::OR, VT, Promote);
1243 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1244 setOperationAction(ISD::XOR, VT, Promote);
1245 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1246 setOperationAction(ISD::LOAD, VT, Promote);
1247 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1248 setOperationAction(ISD::SELECT, VT, Promote);
1249 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1253 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1254 // of this type with custom code.
1255 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1256 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1257 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1261 // We want to custom lower some of our intrinsics.
1262 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1263 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1265 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1266 // handle type legalization for these operations here.
1268 // FIXME: We really should do custom legalization for addition and
1269 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1270 // than generic legalization for 64-bit multiplication-with-overflow, though.
1271 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1272 // Add/Sub/Mul with overflow operations are custom lowered.
1274 setOperationAction(ISD::SADDO, VT, Custom);
1275 setOperationAction(ISD::UADDO, VT, Custom);
1276 setOperationAction(ISD::SSUBO, VT, Custom);
1277 setOperationAction(ISD::USUBO, VT, Custom);
1278 setOperationAction(ISD::SMULO, VT, Custom);
1279 setOperationAction(ISD::UMULO, VT, Custom);
1282 // There are no 8-bit 3-address imul/mul instructions
1283 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1284 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1286 if (!Subtarget->is64Bit()) {
1287 // These libcalls are not available in 32-bit.
1288 setLibcallName(RTLIB::SHL_I128, 0);
1289 setLibcallName(RTLIB::SRL_I128, 0);
1290 setLibcallName(RTLIB::SRA_I128, 0);
1293 // Combine sin / cos into one node or libcall if possible.
1294 if (Subtarget->hasSinCos()) {
1295 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1296 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1297 if (Subtarget->isTargetDarwin()) {
1298 // For MacOSX, we don't want to the normal expansion of a libcall to
1299 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1301 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1302 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1306 // We have target-specific dag combine patterns for the following nodes:
1307 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1308 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1309 setTargetDAGCombine(ISD::VSELECT);
1310 setTargetDAGCombine(ISD::SELECT);
1311 setTargetDAGCombine(ISD::SHL);
1312 setTargetDAGCombine(ISD::SRA);
1313 setTargetDAGCombine(ISD::SRL);
1314 setTargetDAGCombine(ISD::OR);
1315 setTargetDAGCombine(ISD::AND);
1316 setTargetDAGCombine(ISD::ADD);
1317 setTargetDAGCombine(ISD::FADD);
1318 setTargetDAGCombine(ISD::FSUB);
1319 setTargetDAGCombine(ISD::FMA);
1320 setTargetDAGCombine(ISD::SUB);
1321 setTargetDAGCombine(ISD::LOAD);
1322 setTargetDAGCombine(ISD::STORE);
1323 setTargetDAGCombine(ISD::ZERO_EXTEND);
1324 setTargetDAGCombine(ISD::ANY_EXTEND);
1325 setTargetDAGCombine(ISD::SIGN_EXTEND);
1326 setTargetDAGCombine(ISD::TRUNCATE);
1327 setTargetDAGCombine(ISD::SINT_TO_FP);
1328 setTargetDAGCombine(ISD::SETCC);
1329 if (Subtarget->is64Bit())
1330 setTargetDAGCombine(ISD::MUL);
1331 setTargetDAGCombine(ISD::XOR);
1333 computeRegisterProperties();
1335 // On Darwin, -Os means optimize for size without hurting performance,
1336 // do not reduce the limit.
1337 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1338 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1339 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1340 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1341 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1342 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1343 setPrefLoopAlignment(4); // 2^4 bytes.
1344 benefitFromCodePlacementOpt = true;
1346 // Predictable cmov don't hurt on atom because it's in-order.
1347 predictableSelectIsExpensive = !Subtarget->isAtom();
1349 setPrefFunctionAlignment(4); // 2^4 bytes.
1352 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1353 if (!VT.isVector()) return MVT::i8;
1354 return VT.changeVectorElementTypeToInteger();
1357 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1358 /// the desired ByVal argument alignment.
1359 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1362 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1363 if (VTy->getBitWidth() == 128)
1365 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1366 unsigned EltAlign = 0;
1367 getMaxByValAlign(ATy->getElementType(), EltAlign);
1368 if (EltAlign > MaxAlign)
1369 MaxAlign = EltAlign;
1370 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1371 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1372 unsigned EltAlign = 0;
1373 getMaxByValAlign(STy->getElementType(i), EltAlign);
1374 if (EltAlign > MaxAlign)
1375 MaxAlign = EltAlign;
1382 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1383 /// function arguments in the caller parameter area. For X86, aggregates
1384 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1385 /// are at 4-byte boundaries.
1386 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1387 if (Subtarget->is64Bit()) {
1388 // Max of 8 and alignment of type.
1389 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1396 if (Subtarget->hasSSE1())
1397 getMaxByValAlign(Ty, Align);
1401 /// getOptimalMemOpType - Returns the target specific optimal type for load
1402 /// and store operations as a result of memset, memcpy, and memmove
1403 /// lowering. If DstAlign is zero that means it's safe to destination
1404 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1405 /// means there isn't a need to check it against alignment requirement,
1406 /// probably because the source does not need to be loaded. If 'IsMemset' is
1407 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1408 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1409 /// source is constant so it does not need to be loaded.
1410 /// It returns EVT::Other if the type should be determined using generic
1411 /// target-independent logic.
1413 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1414 unsigned DstAlign, unsigned SrcAlign,
1415 bool IsMemset, bool ZeroMemset,
1417 MachineFunction &MF) const {
1418 const Function *F = MF.getFunction();
1419 if ((!IsMemset || ZeroMemset) &&
1420 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1421 Attribute::NoImplicitFloat)) {
1423 (Subtarget->isUnalignedMemAccessFast() ||
1424 ((DstAlign == 0 || DstAlign >= 16) &&
1425 (SrcAlign == 0 || SrcAlign >= 16)))) {
1427 if (Subtarget->hasInt256())
1429 if (Subtarget->hasFp256())
1432 if (Subtarget->hasSSE2())
1434 if (Subtarget->hasSSE1())
1436 } else if (!MemcpyStrSrc && Size >= 8 &&
1437 !Subtarget->is64Bit() &&
1438 Subtarget->hasSSE2()) {
1439 // Do not use f64 to lower memcpy if source is string constant. It's
1440 // better to use i32 to avoid the loads.
1444 if (Subtarget->is64Bit() && Size >= 8)
1449 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1451 return X86ScalarSSEf32;
1452 else if (VT == MVT::f64)
1453 return X86ScalarSSEf64;
1458 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1460 *Fast = Subtarget->isUnalignedMemAccessFast();
1464 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1465 /// current function. The returned value is a member of the
1466 /// MachineJumpTableInfo::JTEntryKind enum.
1467 unsigned X86TargetLowering::getJumpTableEncoding() const {
1468 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1470 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1471 Subtarget->isPICStyleGOT())
1472 return MachineJumpTableInfo::EK_Custom32;
1474 // Otherwise, use the normal jump table encoding heuristics.
1475 return TargetLowering::getJumpTableEncoding();
1479 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1480 const MachineBasicBlock *MBB,
1481 unsigned uid,MCContext &Ctx) const{
1482 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1483 Subtarget->isPICStyleGOT());
1484 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1486 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1487 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1490 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1492 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1493 SelectionDAG &DAG) const {
1494 if (!Subtarget->is64Bit())
1495 // This doesn't have DebugLoc associated with it, but is not really the
1496 // same as a Register.
1497 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1501 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1502 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1504 const MCExpr *X86TargetLowering::
1505 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1506 MCContext &Ctx) const {
1507 // X86-64 uses RIP relative addressing based on the jump table label.
1508 if (Subtarget->isPICStyleRIPRel())
1509 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1511 // Otherwise, the reference is relative to the PIC base.
1512 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1515 // FIXME: Why this routine is here? Move to RegInfo!
1516 std::pair<const TargetRegisterClass*, uint8_t>
1517 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1518 const TargetRegisterClass *RRC = 0;
1520 switch (VT.SimpleTy) {
1522 return TargetLowering::findRepresentativeClass(VT);
1523 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1524 RRC = Subtarget->is64Bit() ?
1525 (const TargetRegisterClass*)&X86::GR64RegClass :
1526 (const TargetRegisterClass*)&X86::GR32RegClass;
1529 RRC = &X86::VR64RegClass;
1531 case MVT::f32: case MVT::f64:
1532 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1533 case MVT::v4f32: case MVT::v2f64:
1534 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1536 RRC = &X86::VR128RegClass;
1539 return std::make_pair(RRC, Cost);
1542 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1543 unsigned &Offset) const {
1544 if (!Subtarget->isTargetLinux())
1547 if (Subtarget->is64Bit()) {
1548 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1550 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1562 //===----------------------------------------------------------------------===//
1563 // Return Value Calling Convention Implementation
1564 //===----------------------------------------------------------------------===//
1566 #include "X86GenCallingConv.inc"
1569 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1570 MachineFunction &MF, bool isVarArg,
1571 const SmallVectorImpl<ISD::OutputArg> &Outs,
1572 LLVMContext &Context) const {
1573 SmallVector<CCValAssign, 16> RVLocs;
1574 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1576 return CCInfo.CheckReturn(Outs, RetCC_X86);
1580 X86TargetLowering::LowerReturn(SDValue Chain,
1581 CallingConv::ID CallConv, bool isVarArg,
1582 const SmallVectorImpl<ISD::OutputArg> &Outs,
1583 const SmallVectorImpl<SDValue> &OutVals,
1584 DebugLoc dl, SelectionDAG &DAG) const {
1585 MachineFunction &MF = DAG.getMachineFunction();
1586 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1588 SmallVector<CCValAssign, 16> RVLocs;
1589 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1590 RVLocs, *DAG.getContext());
1591 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1594 SmallVector<SDValue, 6> RetOps;
1595 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1596 // Operand #1 = Bytes To Pop
1597 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1600 // Copy the result values into the output registers.
1601 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1602 CCValAssign &VA = RVLocs[i];
1603 assert(VA.isRegLoc() && "Can only return in registers!");
1604 SDValue ValToCopy = OutVals[i];
1605 EVT ValVT = ValToCopy.getValueType();
1607 // Promote values to the appropriate types
1608 if (VA.getLocInfo() == CCValAssign::SExt)
1609 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1610 else if (VA.getLocInfo() == CCValAssign::ZExt)
1611 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1612 else if (VA.getLocInfo() == CCValAssign::AExt)
1613 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1614 else if (VA.getLocInfo() == CCValAssign::BCvt)
1615 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1617 // If this is x86-64, and we disabled SSE, we can't return FP values,
1618 // or SSE or MMX vectors.
1619 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1620 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1621 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1622 report_fatal_error("SSE register return with SSE disabled");
1624 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1625 // llvm-gcc has never done it right and no one has noticed, so this
1626 // should be OK for now.
1627 if (ValVT == MVT::f64 &&
1628 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1629 report_fatal_error("SSE2 register return with SSE2 disabled");
1631 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1632 // the RET instruction and handled by the FP Stackifier.
1633 if (VA.getLocReg() == X86::ST0 ||
1634 VA.getLocReg() == X86::ST1) {
1635 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1636 // change the value to the FP stack register class.
1637 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1638 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1639 RetOps.push_back(ValToCopy);
1640 // Don't emit a copytoreg.
1644 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1645 // which is returned in RAX / RDX.
1646 if (Subtarget->is64Bit()) {
1647 if (ValVT == MVT::x86mmx) {
1648 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1649 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1650 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1652 // If we don't have SSE2 available, convert to v4f32 so the generated
1653 // register is legal.
1654 if (!Subtarget->hasSSE2())
1655 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1660 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1661 Flag = Chain.getValue(1);
1662 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1665 // The x86-64 ABIs require that for returning structs by value we copy
1666 // the sret argument into %rax/%eax (depending on ABI) for the return.
1667 // We saved the argument into a virtual register in the entry block,
1668 // so now we copy the value out and into %rax/%eax.
1669 if (Subtarget->is64Bit() &&
1670 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1671 MachineFunction &MF = DAG.getMachineFunction();
1672 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1673 unsigned Reg = FuncInfo->getSRetReturnReg();
1675 "SRetReturnReg should have been set in LowerFormalArguments().");
1676 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1678 unsigned RetValReg = Subtarget->isTarget64BitILP32() ? X86::EAX : X86::RAX;
1679 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1680 Flag = Chain.getValue(1);
1682 // RAX/EAX now acts like a return value.
1683 RetOps.push_back(DAG.getRegister(RetValReg, MVT::i64));
1686 RetOps[0] = Chain; // Update chain.
1688 // Add the flag if we have it.
1690 RetOps.push_back(Flag);
1692 return DAG.getNode(X86ISD::RET_FLAG, dl,
1693 MVT::Other, &RetOps[0], RetOps.size());
1696 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1697 if (N->getNumValues() != 1)
1699 if (!N->hasNUsesOfValue(1, 0))
1702 SDValue TCChain = Chain;
1703 SDNode *Copy = *N->use_begin();
1704 if (Copy->getOpcode() == ISD::CopyToReg) {
1705 // If the copy has a glue operand, we conservatively assume it isn't safe to
1706 // perform a tail call.
1707 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1709 TCChain = Copy->getOperand(0);
1710 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1713 bool HasRet = false;
1714 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1716 if (UI->getOpcode() != X86ISD::RET_FLAG)
1729 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1730 ISD::NodeType ExtendKind) const {
1732 // TODO: Is this also valid on 32-bit?
1733 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1734 ReturnMVT = MVT::i8;
1736 ReturnMVT = MVT::i32;
1738 MVT MinVT = getRegisterType(ReturnMVT);
1739 return VT.bitsLT(MinVT) ? MinVT : VT;
1742 /// LowerCallResult - Lower the result values of a call into the
1743 /// appropriate copies out of appropriate physical registers.
1746 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1747 CallingConv::ID CallConv, bool isVarArg,
1748 const SmallVectorImpl<ISD::InputArg> &Ins,
1749 DebugLoc dl, SelectionDAG &DAG,
1750 SmallVectorImpl<SDValue> &InVals) const {
1752 // Assign locations to each value returned by this call.
1753 SmallVector<CCValAssign, 16> RVLocs;
1754 bool Is64Bit = Subtarget->is64Bit();
1755 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1756 getTargetMachine(), RVLocs, *DAG.getContext());
1757 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1759 // Copy all of the result registers out of their specified physreg.
1760 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1761 CCValAssign &VA = RVLocs[i];
1762 EVT CopyVT = VA.getValVT();
1764 // If this is x86-64, and we disabled SSE, we can't return FP values
1765 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1766 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1767 report_fatal_error("SSE register return with SSE disabled");
1772 // If this is a call to a function that returns an fp value on the floating
1773 // point stack, we must guarantee the value is popped from the stack, so
1774 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1775 // if the return value is not used. We use the FpPOP_RETVAL instruction
1777 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1778 // If we prefer to use the value in xmm registers, copy it out as f80 and
1779 // use a truncate to move it from fp stack reg to xmm reg.
1780 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1781 SDValue Ops[] = { Chain, InFlag };
1782 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1783 MVT::Other, MVT::Glue, Ops, 2), 1);
1784 Val = Chain.getValue(0);
1786 // Round the f80 to the right size, which also moves it to the appropriate
1788 if (CopyVT != VA.getValVT())
1789 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1790 // This truncation won't change the value.
1791 DAG.getIntPtrConstant(1));
1793 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1794 CopyVT, InFlag).getValue(1);
1795 Val = Chain.getValue(0);
1797 InFlag = Chain.getValue(2);
1798 InVals.push_back(Val);
1804 //===----------------------------------------------------------------------===//
1805 // C & StdCall & Fast Calling Convention implementation
1806 //===----------------------------------------------------------------------===//
1807 // StdCall calling convention seems to be standard for many Windows' API
1808 // routines and around. It differs from C calling convention just a little:
1809 // callee should clean up the stack, not caller. Symbols should be also
1810 // decorated in some fancy way :) It doesn't support any vector arguments.
1811 // For info on fast calling convention see Fast Calling Convention (tail call)
1812 // implementation LowerX86_32FastCCCallTo.
1814 /// CallIsStructReturn - Determines whether a call uses struct return
1816 enum StructReturnType {
1821 static StructReturnType
1822 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1824 return NotStructReturn;
1826 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1827 if (!Flags.isSRet())
1828 return NotStructReturn;
1829 if (Flags.isInReg())
1830 return RegStructReturn;
1831 return StackStructReturn;
1834 /// ArgsAreStructReturn - Determines whether a function uses struct
1835 /// return semantics.
1836 static StructReturnType
1837 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1839 return NotStructReturn;
1841 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1842 if (!Flags.isSRet())
1843 return NotStructReturn;
1844 if (Flags.isInReg())
1845 return RegStructReturn;
1846 return StackStructReturn;
1849 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1850 /// by "Src" to address "Dst" with size and alignment information specified by
1851 /// the specific parameter attribute. The copy will be passed as a byval
1852 /// function parameter.
1854 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1855 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1857 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1859 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1860 /*isVolatile*/false, /*AlwaysInline=*/true,
1861 MachinePointerInfo(), MachinePointerInfo());
1864 /// IsTailCallConvention - Return true if the calling convention is one that
1865 /// supports tail call optimization.
1866 static bool IsTailCallConvention(CallingConv::ID CC) {
1867 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1868 CC == CallingConv::HiPE);
1871 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1872 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1876 CallingConv::ID CalleeCC = CS.getCallingConv();
1877 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1883 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1884 /// a tailcall target by changing its ABI.
1885 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1886 bool GuaranteedTailCallOpt) {
1887 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1891 X86TargetLowering::LowerMemArgument(SDValue Chain,
1892 CallingConv::ID CallConv,
1893 const SmallVectorImpl<ISD::InputArg> &Ins,
1894 DebugLoc dl, SelectionDAG &DAG,
1895 const CCValAssign &VA,
1896 MachineFrameInfo *MFI,
1898 // Create the nodes corresponding to a load from this parameter slot.
1899 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1900 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1901 getTargetMachine().Options.GuaranteedTailCallOpt);
1902 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1905 // If value is passed by pointer we have address passed instead of the value
1907 if (VA.getLocInfo() == CCValAssign::Indirect)
1908 ValVT = VA.getLocVT();
1910 ValVT = VA.getValVT();
1912 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1913 // changed with more analysis.
1914 // In case of tail call optimization mark all arguments mutable. Since they
1915 // could be overwritten by lowering of arguments in case of a tail call.
1916 if (Flags.isByVal()) {
1917 unsigned Bytes = Flags.getByValSize();
1918 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1919 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1920 return DAG.getFrameIndex(FI, getPointerTy());
1922 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1923 VA.getLocMemOffset(), isImmutable);
1924 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1925 return DAG.getLoad(ValVT, dl, Chain, FIN,
1926 MachinePointerInfo::getFixedStack(FI),
1927 false, false, false, 0);
1932 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1933 CallingConv::ID CallConv,
1935 const SmallVectorImpl<ISD::InputArg> &Ins,
1938 SmallVectorImpl<SDValue> &InVals)
1940 MachineFunction &MF = DAG.getMachineFunction();
1941 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1943 const Function* Fn = MF.getFunction();
1944 if (Fn->hasExternalLinkage() &&
1945 Subtarget->isTargetCygMing() &&
1946 Fn->getName() == "main")
1947 FuncInfo->setForceFramePointer(true);
1949 MachineFrameInfo *MFI = MF.getFrameInfo();
1950 bool Is64Bit = Subtarget->is64Bit();
1951 bool IsWindows = Subtarget->isTargetWindows();
1952 bool IsWin64 = Subtarget->isTargetWin64();
1954 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1955 "Var args not supported with calling convention fastcc, ghc or hipe");
1957 // Assign locations to all of the incoming arguments.
1958 SmallVector<CCValAssign, 16> ArgLocs;
1959 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1960 ArgLocs, *DAG.getContext());
1962 // Allocate shadow area for Win64
1964 CCInfo.AllocateStack(32, 8);
1967 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1969 unsigned LastVal = ~0U;
1971 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1972 CCValAssign &VA = ArgLocs[i];
1973 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1975 assert(VA.getValNo() != LastVal &&
1976 "Don't support value assigned to multiple locs yet");
1978 LastVal = VA.getValNo();
1980 if (VA.isRegLoc()) {
1981 EVT RegVT = VA.getLocVT();
1982 const TargetRegisterClass *RC;
1983 if (RegVT == MVT::i32)
1984 RC = &X86::GR32RegClass;
1985 else if (Is64Bit && RegVT == MVT::i64)
1986 RC = &X86::GR64RegClass;
1987 else if (RegVT == MVT::f32)
1988 RC = &X86::FR32RegClass;
1989 else if (RegVT == MVT::f64)
1990 RC = &X86::FR64RegClass;
1991 else if (RegVT.is256BitVector())
1992 RC = &X86::VR256RegClass;
1993 else if (RegVT.is128BitVector())
1994 RC = &X86::VR128RegClass;
1995 else if (RegVT == MVT::x86mmx)
1996 RC = &X86::VR64RegClass;
1998 llvm_unreachable("Unknown argument type!");
2000 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2001 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2003 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2004 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2006 if (VA.getLocInfo() == CCValAssign::SExt)
2007 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2008 DAG.getValueType(VA.getValVT()));
2009 else if (VA.getLocInfo() == CCValAssign::ZExt)
2010 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2011 DAG.getValueType(VA.getValVT()));
2012 else if (VA.getLocInfo() == CCValAssign::BCvt)
2013 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2015 if (VA.isExtInLoc()) {
2016 // Handle MMX values passed in XMM regs.
2017 if (RegVT.isVector())
2018 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2020 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2023 assert(VA.isMemLoc());
2024 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2027 // If value is passed via pointer - do a load.
2028 if (VA.getLocInfo() == CCValAssign::Indirect)
2029 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2030 MachinePointerInfo(), false, false, false, 0);
2032 InVals.push_back(ArgValue);
2035 // The x86-64 ABIs require that for returning structs by value we copy
2036 // the sret argument into %rax/%eax (depending on ABI) for the return.
2037 // Save the argument into a virtual register so that we can access it
2038 // from the return points.
2039 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
2040 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2041 unsigned Reg = FuncInfo->getSRetReturnReg();
2043 MVT PtrTy = getPointerTy();
2044 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2045 FuncInfo->setSRetReturnReg(Reg);
2047 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2048 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2051 unsigned StackSize = CCInfo.getNextStackOffset();
2052 // Align stack specially for tail calls.
2053 if (FuncIsMadeTailCallSafe(CallConv,
2054 MF.getTarget().Options.GuaranteedTailCallOpt))
2055 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2057 // If the function takes variable number of arguments, make a frame index for
2058 // the start of the first vararg value... for expansion of llvm.va_start.
2060 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2061 CallConv != CallingConv::X86_ThisCall)) {
2062 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2065 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2067 // FIXME: We should really autogenerate these arrays
2068 static const uint16_t GPR64ArgRegsWin64[] = {
2069 X86::RCX, X86::RDX, X86::R8, X86::R9
2071 static const uint16_t GPR64ArgRegs64Bit[] = {
2072 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2074 static const uint16_t XMMArgRegs64Bit[] = {
2075 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2076 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2078 const uint16_t *GPR64ArgRegs;
2079 unsigned NumXMMRegs = 0;
2082 // The XMM registers which might contain var arg parameters are shadowed
2083 // in their paired GPR. So we only need to save the GPR to their home
2085 TotalNumIntRegs = 4;
2086 GPR64ArgRegs = GPR64ArgRegsWin64;
2088 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2089 GPR64ArgRegs = GPR64ArgRegs64Bit;
2091 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2094 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2097 bool NoImplicitFloatOps = Fn->getAttributes().
2098 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2099 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2100 "SSE register cannot be used when SSE is disabled!");
2101 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2102 NoImplicitFloatOps) &&
2103 "SSE register cannot be used when SSE is disabled!");
2104 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2105 !Subtarget->hasSSE1())
2106 // Kernel mode asks for SSE to be disabled, so don't push them
2108 TotalNumXMMRegs = 0;
2111 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2112 // Get to the caller-allocated home save location. Add 8 to account
2113 // for the return address.
2114 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2115 FuncInfo->setRegSaveFrameIndex(
2116 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2117 // Fixup to set vararg frame on shadow area (4 x i64).
2119 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2121 // For X86-64, if there are vararg parameters that are passed via
2122 // registers, then we must store them to their spots on the stack so
2123 // they may be loaded by deferencing the result of va_next.
2124 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2125 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2126 FuncInfo->setRegSaveFrameIndex(
2127 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2131 // Store the integer parameter registers.
2132 SmallVector<SDValue, 8> MemOps;
2133 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2135 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2136 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2137 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2138 DAG.getIntPtrConstant(Offset));
2139 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2140 &X86::GR64RegClass);
2141 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2143 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2144 MachinePointerInfo::getFixedStack(
2145 FuncInfo->getRegSaveFrameIndex(), Offset),
2147 MemOps.push_back(Store);
2151 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2152 // Now store the XMM (fp + vector) parameter registers.
2153 SmallVector<SDValue, 11> SaveXMMOps;
2154 SaveXMMOps.push_back(Chain);
2156 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2157 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2158 SaveXMMOps.push_back(ALVal);
2160 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2161 FuncInfo->getRegSaveFrameIndex()));
2162 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2163 FuncInfo->getVarArgsFPOffset()));
2165 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2166 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2167 &X86::VR128RegClass);
2168 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2169 SaveXMMOps.push_back(Val);
2171 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2173 &SaveXMMOps[0], SaveXMMOps.size()));
2176 if (!MemOps.empty())
2177 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2178 &MemOps[0], MemOps.size());
2182 // Some CCs need callee pop.
2183 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2184 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2185 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2187 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2188 // If this is an sret function, the return should pop the hidden pointer.
2189 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2190 argsAreStructReturn(Ins) == StackStructReturn)
2191 FuncInfo->setBytesToPopOnReturn(4);
2195 // RegSaveFrameIndex is X86-64 only.
2196 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2197 if (CallConv == CallingConv::X86_FastCall ||
2198 CallConv == CallingConv::X86_ThisCall)
2199 // fastcc functions can't have varargs.
2200 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2203 FuncInfo->setArgumentStackSize(StackSize);
2209 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2210 SDValue StackPtr, SDValue Arg,
2211 DebugLoc dl, SelectionDAG &DAG,
2212 const CCValAssign &VA,
2213 ISD::ArgFlagsTy Flags) const {
2214 unsigned LocMemOffset = VA.getLocMemOffset();
2215 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2216 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2217 if (Flags.isByVal())
2218 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2220 return DAG.getStore(Chain, dl, Arg, PtrOff,
2221 MachinePointerInfo::getStack(LocMemOffset),
2225 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2226 /// optimization is performed and it is required.
2228 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2229 SDValue &OutRetAddr, SDValue Chain,
2230 bool IsTailCall, bool Is64Bit,
2231 int FPDiff, DebugLoc dl) const {
2232 // Adjust the Return address stack slot.
2233 EVT VT = getPointerTy();
2234 OutRetAddr = getReturnAddressFrameIndex(DAG);
2236 // Load the "old" Return address.
2237 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2238 false, false, false, 0);
2239 return SDValue(OutRetAddr.getNode(), 1);
2242 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2243 /// optimization is performed and it is required (FPDiff!=0).
2245 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2246 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2247 unsigned SlotSize, int FPDiff, DebugLoc dl) {
2248 // Store the return address to the appropriate stack slot.
2249 if (!FPDiff) return Chain;
2250 // Calculate the new stack slot for the return address.
2251 int NewReturnAddrFI =
2252 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2253 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2254 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2255 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2261 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2262 SmallVectorImpl<SDValue> &InVals) const {
2263 SelectionDAG &DAG = CLI.DAG;
2264 DebugLoc &dl = CLI.DL;
2265 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2266 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2267 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2268 SDValue Chain = CLI.Chain;
2269 SDValue Callee = CLI.Callee;
2270 CallingConv::ID CallConv = CLI.CallConv;
2271 bool &isTailCall = CLI.IsTailCall;
2272 bool isVarArg = CLI.IsVarArg;
2274 MachineFunction &MF = DAG.getMachineFunction();
2275 bool Is64Bit = Subtarget->is64Bit();
2276 bool IsWin64 = Subtarget->isTargetWin64();
2277 bool IsWindows = Subtarget->isTargetWindows();
2278 StructReturnType SR = callIsStructReturn(Outs);
2279 bool IsSibcall = false;
2281 if (MF.getTarget().Options.DisableTailCalls)
2285 // Check if it's really possible to do a tail call.
2286 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2287 isVarArg, SR != NotStructReturn,
2288 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2289 Outs, OutVals, Ins, DAG);
2291 // Sibcalls are automatically detected tailcalls which do not require
2293 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2300 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2301 "Var args not supported with calling convention fastcc, ghc or hipe");
2303 // Analyze operands of the call, assigning locations to each operand.
2304 SmallVector<CCValAssign, 16> ArgLocs;
2305 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2306 ArgLocs, *DAG.getContext());
2308 // Allocate shadow area for Win64
2310 CCInfo.AllocateStack(32, 8);
2313 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2315 // Get a count of how many bytes are to be pushed on the stack.
2316 unsigned NumBytes = CCInfo.getNextStackOffset();
2318 // This is a sibcall. The memory operands are available in caller's
2319 // own caller's stack.
2321 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2322 IsTailCallConvention(CallConv))
2323 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2326 if (isTailCall && !IsSibcall) {
2327 // Lower arguments at fp - stackoffset + fpdiff.
2328 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2329 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2331 FPDiff = NumBytesCallerPushed - NumBytes;
2333 // Set the delta of movement of the returnaddr stackslot.
2334 // But only set if delta is greater than previous delta.
2335 if (FPDiff < X86Info->getTCReturnAddrDelta())
2336 X86Info->setTCReturnAddrDelta(FPDiff);
2340 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2342 SDValue RetAddrFrIdx;
2343 // Load return address for tail calls.
2344 if (isTailCall && FPDiff)
2345 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2346 Is64Bit, FPDiff, dl);
2348 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2349 SmallVector<SDValue, 8> MemOpChains;
2352 // Walk the register/memloc assignments, inserting copies/loads. In the case
2353 // of tail call optimization arguments are handle later.
2354 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2355 CCValAssign &VA = ArgLocs[i];
2356 EVT RegVT = VA.getLocVT();
2357 SDValue Arg = OutVals[i];
2358 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2359 bool isByVal = Flags.isByVal();
2361 // Promote the value if needed.
2362 switch (VA.getLocInfo()) {
2363 default: llvm_unreachable("Unknown loc info!");
2364 case CCValAssign::Full: break;
2365 case CCValAssign::SExt:
2366 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2368 case CCValAssign::ZExt:
2369 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2371 case CCValAssign::AExt:
2372 if (RegVT.is128BitVector()) {
2373 // Special case: passing MMX values in XMM registers.
2374 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2375 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2376 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2378 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2380 case CCValAssign::BCvt:
2381 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2383 case CCValAssign::Indirect: {
2384 // Store the argument.
2385 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2386 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2387 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2388 MachinePointerInfo::getFixedStack(FI),
2395 if (VA.isRegLoc()) {
2396 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2397 if (isVarArg && IsWin64) {
2398 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2399 // shadow reg if callee is a varargs function.
2400 unsigned ShadowReg = 0;
2401 switch (VA.getLocReg()) {
2402 case X86::XMM0: ShadowReg = X86::RCX; break;
2403 case X86::XMM1: ShadowReg = X86::RDX; break;
2404 case X86::XMM2: ShadowReg = X86::R8; break;
2405 case X86::XMM3: ShadowReg = X86::R9; break;
2408 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2410 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2411 assert(VA.isMemLoc());
2412 if (StackPtr.getNode() == 0)
2413 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2415 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2416 dl, DAG, VA, Flags));
2420 if (!MemOpChains.empty())
2421 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2422 &MemOpChains[0], MemOpChains.size());
2424 if (Subtarget->isPICStyleGOT()) {
2425 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2428 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2429 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2431 // If we are tail calling and generating PIC/GOT style code load the
2432 // address of the callee into ECX. The value in ecx is used as target of
2433 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2434 // for tail calls on PIC/GOT architectures. Normally we would just put the
2435 // address of GOT into ebx and then call target@PLT. But for tail calls
2436 // ebx would be restored (since ebx is callee saved) before jumping to the
2439 // Note: The actual moving to ECX is done further down.
2440 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2441 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2442 !G->getGlobal()->hasProtectedVisibility())
2443 Callee = LowerGlobalAddress(Callee, DAG);
2444 else if (isa<ExternalSymbolSDNode>(Callee))
2445 Callee = LowerExternalSymbol(Callee, DAG);
2449 if (Is64Bit && isVarArg && !IsWin64) {
2450 // From AMD64 ABI document:
2451 // For calls that may call functions that use varargs or stdargs
2452 // (prototype-less calls or calls to functions containing ellipsis (...) in
2453 // the declaration) %al is used as hidden argument to specify the number
2454 // of SSE registers used. The contents of %al do not need to match exactly
2455 // the number of registers, but must be an ubound on the number of SSE
2456 // registers used and is in the range 0 - 8 inclusive.
2458 // Count the number of XMM registers allocated.
2459 static const uint16_t XMMArgRegs[] = {
2460 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2461 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2463 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2464 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2465 && "SSE registers cannot be used when SSE is disabled");
2467 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2468 DAG.getConstant(NumXMMRegs, MVT::i8)));
2471 // For tail calls lower the arguments to the 'real' stack slot.
2473 // Force all the incoming stack arguments to be loaded from the stack
2474 // before any new outgoing arguments are stored to the stack, because the
2475 // outgoing stack slots may alias the incoming argument stack slots, and
2476 // the alias isn't otherwise explicit. This is slightly more conservative
2477 // than necessary, because it means that each store effectively depends
2478 // on every argument instead of just those arguments it would clobber.
2479 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2481 SmallVector<SDValue, 8> MemOpChains2;
2484 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2485 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2486 CCValAssign &VA = ArgLocs[i];
2489 assert(VA.isMemLoc());
2490 SDValue Arg = OutVals[i];
2491 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2492 // Create frame index.
2493 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2494 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2495 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2496 FIN = DAG.getFrameIndex(FI, getPointerTy());
2498 if (Flags.isByVal()) {
2499 // Copy relative to framepointer.
2500 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2501 if (StackPtr.getNode() == 0)
2502 StackPtr = DAG.getCopyFromReg(Chain, dl,
2503 RegInfo->getStackRegister(),
2505 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2507 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2511 // Store relative to framepointer.
2512 MemOpChains2.push_back(
2513 DAG.getStore(ArgChain, dl, Arg, FIN,
2514 MachinePointerInfo::getFixedStack(FI),
2520 if (!MemOpChains2.empty())
2521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2522 &MemOpChains2[0], MemOpChains2.size());
2524 // Store the return address to the appropriate stack slot.
2525 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2526 getPointerTy(), RegInfo->getSlotSize(),
2530 // Build a sequence of copy-to-reg nodes chained together with token chain
2531 // and flag operands which copy the outgoing args into registers.
2533 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2534 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2535 RegsToPass[i].second, InFlag);
2536 InFlag = Chain.getValue(1);
2539 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2540 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2541 // In the 64-bit large code model, we have to make all calls
2542 // through a register, since the call instruction's 32-bit
2543 // pc-relative offset may not be large enough to hold the whole
2545 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2546 // If the callee is a GlobalAddress node (quite common, every direct call
2547 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2550 // We should use extra load for direct calls to dllimported functions in
2552 const GlobalValue *GV = G->getGlobal();
2553 if (!GV->hasDLLImportLinkage()) {
2554 unsigned char OpFlags = 0;
2555 bool ExtraLoad = false;
2556 unsigned WrapperKind = ISD::DELETED_NODE;
2558 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2559 // external symbols most go through the PLT in PIC mode. If the symbol
2560 // has hidden or protected visibility, or if it is static or local, then
2561 // we don't need to use the PLT - we can directly call it.
2562 if (Subtarget->isTargetELF() &&
2563 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2564 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2565 OpFlags = X86II::MO_PLT;
2566 } else if (Subtarget->isPICStyleStubAny() &&
2567 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2568 (!Subtarget->getTargetTriple().isMacOSX() ||
2569 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2570 // PC-relative references to external symbols should go through $stub,
2571 // unless we're building with the leopard linker or later, which
2572 // automatically synthesizes these stubs.
2573 OpFlags = X86II::MO_DARWIN_STUB;
2574 } else if (Subtarget->isPICStyleRIPRel() &&
2575 isa<Function>(GV) &&
2576 cast<Function>(GV)->getAttributes().
2577 hasAttribute(AttributeSet::FunctionIndex,
2578 Attribute::NonLazyBind)) {
2579 // If the function is marked as non-lazy, generate an indirect call
2580 // which loads from the GOT directly. This avoids runtime overhead
2581 // at the cost of eager binding (and one extra byte of encoding).
2582 OpFlags = X86II::MO_GOTPCREL;
2583 WrapperKind = X86ISD::WrapperRIP;
2587 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2588 G->getOffset(), OpFlags);
2590 // Add a wrapper if needed.
2591 if (WrapperKind != ISD::DELETED_NODE)
2592 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2593 // Add extra indirection if needed.
2595 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2596 MachinePointerInfo::getGOT(),
2597 false, false, false, 0);
2599 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2600 unsigned char OpFlags = 0;
2602 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2603 // external symbols should go through the PLT.
2604 if (Subtarget->isTargetELF() &&
2605 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2606 OpFlags = X86II::MO_PLT;
2607 } else if (Subtarget->isPICStyleStubAny() &&
2608 (!Subtarget->getTargetTriple().isMacOSX() ||
2609 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2610 // PC-relative references to external symbols should go through $stub,
2611 // unless we're building with the leopard linker or later, which
2612 // automatically synthesizes these stubs.
2613 OpFlags = X86II::MO_DARWIN_STUB;
2616 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2620 // Returns a chain & a flag for retval copy to use.
2621 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2622 SmallVector<SDValue, 8> Ops;
2624 if (!IsSibcall && isTailCall) {
2625 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2626 DAG.getIntPtrConstant(0, true), InFlag);
2627 InFlag = Chain.getValue(1);
2630 Ops.push_back(Chain);
2631 Ops.push_back(Callee);
2634 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2636 // Add argument registers to the end of the list so that they are known live
2638 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2639 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2640 RegsToPass[i].second.getValueType()));
2642 // Add a register mask operand representing the call-preserved registers.
2643 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2644 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2645 assert(Mask && "Missing call preserved mask for calling convention");
2646 Ops.push_back(DAG.getRegisterMask(Mask));
2648 if (InFlag.getNode())
2649 Ops.push_back(InFlag);
2653 //// If this is the first return lowered for this function, add the regs
2654 //// to the liveout set for the function.
2655 // This isn't right, although it's probably harmless on x86; liveouts
2656 // should be computed from returns not tail calls. Consider a void
2657 // function making a tail call to a function returning int.
2658 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2661 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2662 InFlag = Chain.getValue(1);
2664 // Create the CALLSEQ_END node.
2665 unsigned NumBytesForCalleeToPush;
2666 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2667 getTargetMachine().Options.GuaranteedTailCallOpt))
2668 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2669 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2670 SR == StackStructReturn)
2671 // If this is a call to a struct-return function, the callee
2672 // pops the hidden struct pointer, so we have to push it back.
2673 // This is common for Darwin/X86, Linux & Mingw32 targets.
2674 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2675 NumBytesForCalleeToPush = 4;
2677 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2679 // Returns a flag for retval copy to use.
2681 Chain = DAG.getCALLSEQ_END(Chain,
2682 DAG.getIntPtrConstant(NumBytes, true),
2683 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2686 InFlag = Chain.getValue(1);
2689 // Handle result values, copying them out of physregs into vregs that we
2691 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2692 Ins, dl, DAG, InVals);
2695 //===----------------------------------------------------------------------===//
2696 // Fast Calling Convention (tail call) implementation
2697 //===----------------------------------------------------------------------===//
2699 // Like std call, callee cleans arguments, convention except that ECX is
2700 // reserved for storing the tail called function address. Only 2 registers are
2701 // free for argument passing (inreg). Tail call optimization is performed
2703 // * tailcallopt is enabled
2704 // * caller/callee are fastcc
2705 // On X86_64 architecture with GOT-style position independent code only local
2706 // (within module) calls are supported at the moment.
2707 // To keep the stack aligned according to platform abi the function
2708 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2709 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2710 // If a tail called function callee has more arguments than the caller the
2711 // caller needs to make sure that there is room to move the RETADDR to. This is
2712 // achieved by reserving an area the size of the argument delta right after the
2713 // original REtADDR, but before the saved framepointer or the spilled registers
2714 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2726 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2727 /// for a 16 byte align requirement.
2729 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2730 SelectionDAG& DAG) const {
2731 MachineFunction &MF = DAG.getMachineFunction();
2732 const TargetMachine &TM = MF.getTarget();
2733 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2734 unsigned StackAlignment = TFI.getStackAlignment();
2735 uint64_t AlignMask = StackAlignment - 1;
2736 int64_t Offset = StackSize;
2737 unsigned SlotSize = RegInfo->getSlotSize();
2738 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2739 // Number smaller than 12 so just add the difference.
2740 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2742 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2743 Offset = ((~AlignMask) & Offset) + StackAlignment +
2744 (StackAlignment-SlotSize);
2749 /// MatchingStackOffset - Return true if the given stack call argument is
2750 /// already available in the same position (relatively) of the caller's
2751 /// incoming argument stack.
2753 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2754 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2755 const X86InstrInfo *TII) {
2756 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2758 if (Arg.getOpcode() == ISD::CopyFromReg) {
2759 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2760 if (!TargetRegisterInfo::isVirtualRegister(VR))
2762 MachineInstr *Def = MRI->getVRegDef(VR);
2765 if (!Flags.isByVal()) {
2766 if (!TII->isLoadFromStackSlot(Def, FI))
2769 unsigned Opcode = Def->getOpcode();
2770 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2771 Def->getOperand(1).isFI()) {
2772 FI = Def->getOperand(1).getIndex();
2773 Bytes = Flags.getByValSize();
2777 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2778 if (Flags.isByVal())
2779 // ByVal argument is passed in as a pointer but it's now being
2780 // dereferenced. e.g.
2781 // define @foo(%struct.X* %A) {
2782 // tail call @bar(%struct.X* byval %A)
2785 SDValue Ptr = Ld->getBasePtr();
2786 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2789 FI = FINode->getIndex();
2790 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2791 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2792 FI = FINode->getIndex();
2793 Bytes = Flags.getByValSize();
2797 assert(FI != INT_MAX);
2798 if (!MFI->isFixedObjectIndex(FI))
2800 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2803 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2804 /// for tail call optimization. Targets which want to do tail call
2805 /// optimization should implement this function.
2807 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2808 CallingConv::ID CalleeCC,
2810 bool isCalleeStructRet,
2811 bool isCallerStructRet,
2813 const SmallVectorImpl<ISD::OutputArg> &Outs,
2814 const SmallVectorImpl<SDValue> &OutVals,
2815 const SmallVectorImpl<ISD::InputArg> &Ins,
2816 SelectionDAG &DAG) const {
2817 if (!IsTailCallConvention(CalleeCC) &&
2818 CalleeCC != CallingConv::C)
2821 // If -tailcallopt is specified, make fastcc functions tail-callable.
2822 const MachineFunction &MF = DAG.getMachineFunction();
2823 const Function *CallerF = DAG.getMachineFunction().getFunction();
2825 // If the function return type is x86_fp80 and the callee return type is not,
2826 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2827 // perform a tailcall optimization here.
2828 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
2831 CallingConv::ID CallerCC = CallerF->getCallingConv();
2832 bool CCMatch = CallerCC == CalleeCC;
2834 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2835 if (IsTailCallConvention(CalleeCC) && CCMatch)
2840 // Look for obvious safe cases to perform tail call optimization that do not
2841 // require ABI changes. This is what gcc calls sibcall.
2843 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2844 // emit a special epilogue.
2845 if (RegInfo->needsStackRealignment(MF))
2848 // Also avoid sibcall optimization if either caller or callee uses struct
2849 // return semantics.
2850 if (isCalleeStructRet || isCallerStructRet)
2853 // An stdcall caller is expected to clean up its arguments; the callee
2854 // isn't going to do that.
2855 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
2858 // Do not sibcall optimize vararg calls unless all arguments are passed via
2860 if (isVarArg && !Outs.empty()) {
2862 // Optimizing for varargs on Win64 is unlikely to be safe without
2863 // additional testing.
2864 if (Subtarget->isTargetWin64())
2867 SmallVector<CCValAssign, 16> ArgLocs;
2868 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2869 getTargetMachine(), ArgLocs, *DAG.getContext());
2871 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2872 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2873 if (!ArgLocs[i].isRegLoc())
2877 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2878 // stack. Therefore, if it's not used by the call it is not safe to optimize
2879 // this into a sibcall.
2880 bool Unused = false;
2881 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2888 SmallVector<CCValAssign, 16> RVLocs;
2889 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2890 getTargetMachine(), RVLocs, *DAG.getContext());
2891 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2892 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2893 CCValAssign &VA = RVLocs[i];
2894 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2899 // If the calling conventions do not match, then we'd better make sure the
2900 // results are returned in the same way as what the caller expects.
2902 SmallVector<CCValAssign, 16> RVLocs1;
2903 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2904 getTargetMachine(), RVLocs1, *DAG.getContext());
2905 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2907 SmallVector<CCValAssign, 16> RVLocs2;
2908 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2909 getTargetMachine(), RVLocs2, *DAG.getContext());
2910 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2912 if (RVLocs1.size() != RVLocs2.size())
2914 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2915 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2917 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2919 if (RVLocs1[i].isRegLoc()) {
2920 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2923 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2929 // If the callee takes no arguments then go on to check the results of the
2931 if (!Outs.empty()) {
2932 // Check if stack adjustment is needed. For now, do not do this if any
2933 // argument is passed on the stack.
2934 SmallVector<CCValAssign, 16> ArgLocs;
2935 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2936 getTargetMachine(), ArgLocs, *DAG.getContext());
2938 // Allocate shadow area for Win64
2939 if (Subtarget->isTargetWin64()) {
2940 CCInfo.AllocateStack(32, 8);
2943 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2944 if (CCInfo.getNextStackOffset()) {
2945 MachineFunction &MF = DAG.getMachineFunction();
2946 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2949 // Check if the arguments are already laid out in the right way as
2950 // the caller's fixed stack objects.
2951 MachineFrameInfo *MFI = MF.getFrameInfo();
2952 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2953 const X86InstrInfo *TII =
2954 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
2955 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2956 CCValAssign &VA = ArgLocs[i];
2957 SDValue Arg = OutVals[i];
2958 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2959 if (VA.getLocInfo() == CCValAssign::Indirect)
2961 if (!VA.isRegLoc()) {
2962 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2969 // If the tailcall address may be in a register, then make sure it's
2970 // possible to register allocate for it. In 32-bit, the call address can
2971 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2972 // callee-saved registers are restored. These happen to be the same
2973 // registers used to pass 'inreg' arguments so watch out for those.
2974 if (!Subtarget->is64Bit() &&
2975 ((!isa<GlobalAddressSDNode>(Callee) &&
2976 !isa<ExternalSymbolSDNode>(Callee)) ||
2977 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
2978 unsigned NumInRegs = 0;
2979 // In PIC we need an extra register to formulate the address computation
2981 unsigned MaxInRegs =
2982 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
2984 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2985 CCValAssign &VA = ArgLocs[i];
2988 unsigned Reg = VA.getLocReg();
2991 case X86::EAX: case X86::EDX: case X86::ECX:
2992 if (++NumInRegs == MaxInRegs)
3004 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3005 const TargetLibraryInfo *libInfo) const {
3006 return X86::createFastISel(funcInfo, libInfo);
3009 //===----------------------------------------------------------------------===//
3010 // Other Lowering Hooks
3011 //===----------------------------------------------------------------------===//
3013 static bool MayFoldLoad(SDValue Op) {
3014 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3017 static bool MayFoldIntoStore(SDValue Op) {
3018 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3021 static bool isTargetShuffle(unsigned Opcode) {
3023 default: return false;
3024 case X86ISD::PSHUFD:
3025 case X86ISD::PSHUFHW:
3026 case X86ISD::PSHUFLW:
3028 case X86ISD::PALIGNR:
3029 case X86ISD::MOVLHPS:
3030 case X86ISD::MOVLHPD:
3031 case X86ISD::MOVHLPS:
3032 case X86ISD::MOVLPS:
3033 case X86ISD::MOVLPD:
3034 case X86ISD::MOVSHDUP:
3035 case X86ISD::MOVSLDUP:
3036 case X86ISD::MOVDDUP:
3039 case X86ISD::UNPCKL:
3040 case X86ISD::UNPCKH:
3041 case X86ISD::VPERMILP:
3042 case X86ISD::VPERM2X128:
3043 case X86ISD::VPERMI:
3048 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3049 SDValue V1, SelectionDAG &DAG) {
3051 default: llvm_unreachable("Unknown x86 shuffle node");
3052 case X86ISD::MOVSHDUP:
3053 case X86ISD::MOVSLDUP:
3054 case X86ISD::MOVDDUP:
3055 return DAG.getNode(Opc, dl, VT, V1);
3059 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3060 SDValue V1, unsigned TargetMask,
3061 SelectionDAG &DAG) {
3063 default: llvm_unreachable("Unknown x86 shuffle node");
3064 case X86ISD::PSHUFD:
3065 case X86ISD::PSHUFHW:
3066 case X86ISD::PSHUFLW:
3067 case X86ISD::VPERMILP:
3068 case X86ISD::VPERMI:
3069 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3073 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3074 SDValue V1, SDValue V2, unsigned TargetMask,
3075 SelectionDAG &DAG) {
3077 default: llvm_unreachable("Unknown x86 shuffle node");
3078 case X86ISD::PALIGNR:
3080 case X86ISD::VPERM2X128:
3081 return DAG.getNode(Opc, dl, VT, V1, V2,
3082 DAG.getConstant(TargetMask, MVT::i8));
3086 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3087 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3089 default: llvm_unreachable("Unknown x86 shuffle node");
3090 case X86ISD::MOVLHPS:
3091 case X86ISD::MOVLHPD:
3092 case X86ISD::MOVHLPS:
3093 case X86ISD::MOVLPS:
3094 case X86ISD::MOVLPD:
3097 case X86ISD::UNPCKL:
3098 case X86ISD::UNPCKH:
3099 return DAG.getNode(Opc, dl, VT, V1, V2);
3103 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3104 MachineFunction &MF = DAG.getMachineFunction();
3105 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3106 int ReturnAddrIndex = FuncInfo->getRAIndex();
3108 if (ReturnAddrIndex == 0) {
3109 // Set up a frame object for the return address.
3110 unsigned SlotSize = RegInfo->getSlotSize();
3111 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3113 FuncInfo->setRAIndex(ReturnAddrIndex);
3116 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3119 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3120 bool hasSymbolicDisplacement) {
3121 // Offset should fit into 32 bit immediate field.
3122 if (!isInt<32>(Offset))
3125 // If we don't have a symbolic displacement - we don't have any extra
3127 if (!hasSymbolicDisplacement)
3130 // FIXME: Some tweaks might be needed for medium code model.
3131 if (M != CodeModel::Small && M != CodeModel::Kernel)
3134 // For small code model we assume that latest object is 16MB before end of 31
3135 // bits boundary. We may also accept pretty large negative constants knowing
3136 // that all objects are in the positive half of address space.
3137 if (M == CodeModel::Small && Offset < 16*1024*1024)
3140 // For kernel code model we know that all object resist in the negative half
3141 // of 32bits address space. We may not accept negative offsets, since they may
3142 // be just off and we may accept pretty large positive ones.
3143 if (M == CodeModel::Kernel && Offset > 0)
3149 /// isCalleePop - Determines whether the callee is required to pop its
3150 /// own arguments. Callee pop is necessary to support tail calls.
3151 bool X86::isCalleePop(CallingConv::ID CallingConv,
3152 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3156 switch (CallingConv) {
3159 case CallingConv::X86_StdCall:
3161 case CallingConv::X86_FastCall:
3163 case CallingConv::X86_ThisCall:
3165 case CallingConv::Fast:
3167 case CallingConv::GHC:
3169 case CallingConv::HiPE:
3174 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3175 /// specific condition code, returning the condition code and the LHS/RHS of the
3176 /// comparison to make.
3177 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3178 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3180 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3181 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3182 // X > -1 -> X == 0, jump !sign.
3183 RHS = DAG.getConstant(0, RHS.getValueType());
3184 return X86::COND_NS;
3186 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3187 // X < 0 -> X == 0, jump on sign.
3190 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3192 RHS = DAG.getConstant(0, RHS.getValueType());
3193 return X86::COND_LE;
3197 switch (SetCCOpcode) {
3198 default: llvm_unreachable("Invalid integer condition!");
3199 case ISD::SETEQ: return X86::COND_E;
3200 case ISD::SETGT: return X86::COND_G;
3201 case ISD::SETGE: return X86::COND_GE;
3202 case ISD::SETLT: return X86::COND_L;
3203 case ISD::SETLE: return X86::COND_LE;
3204 case ISD::SETNE: return X86::COND_NE;
3205 case ISD::SETULT: return X86::COND_B;
3206 case ISD::SETUGT: return X86::COND_A;
3207 case ISD::SETULE: return X86::COND_BE;
3208 case ISD::SETUGE: return X86::COND_AE;
3212 // First determine if it is required or is profitable to flip the operands.
3214 // If LHS is a foldable load, but RHS is not, flip the condition.
3215 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3216 !ISD::isNON_EXTLoad(RHS.getNode())) {
3217 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3218 std::swap(LHS, RHS);
3221 switch (SetCCOpcode) {
3227 std::swap(LHS, RHS);
3231 // On a floating point condition, the flags are set as follows:
3233 // 0 | 0 | 0 | X > Y
3234 // 0 | 0 | 1 | X < Y
3235 // 1 | 0 | 0 | X == Y
3236 // 1 | 1 | 1 | unordered
3237 switch (SetCCOpcode) {
3238 default: llvm_unreachable("Condcode should be pre-legalized away");
3240 case ISD::SETEQ: return X86::COND_E;
3241 case ISD::SETOLT: // flipped
3243 case ISD::SETGT: return X86::COND_A;
3244 case ISD::SETOLE: // flipped
3246 case ISD::SETGE: return X86::COND_AE;
3247 case ISD::SETUGT: // flipped
3249 case ISD::SETLT: return X86::COND_B;
3250 case ISD::SETUGE: // flipped
3252 case ISD::SETLE: return X86::COND_BE;
3254 case ISD::SETNE: return X86::COND_NE;
3255 case ISD::SETUO: return X86::COND_P;
3256 case ISD::SETO: return X86::COND_NP;
3258 case ISD::SETUNE: return X86::COND_INVALID;
3262 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3263 /// code. Current x86 isa includes the following FP cmov instructions:
3264 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3265 static bool hasFPCMov(unsigned X86CC) {
3281 /// isFPImmLegal - Returns true if the target can instruction select the
3282 /// specified FP immediate natively. If false, the legalizer will
3283 /// materialize the FP immediate as a load from a constant pool.
3284 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3285 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3286 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3292 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3293 /// the specified range (L, H].
3294 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3295 return (Val < 0) || (Val >= Low && Val < Hi);
3298 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3299 /// specified value.
3300 static bool isUndefOrEqual(int Val, int CmpVal) {
3301 return (Val < 0 || Val == CmpVal);
3304 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3305 /// from position Pos and ending in Pos+Size, falls within the specified
3306 /// sequential range (L, L+Pos]. or is undef.
3307 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3308 unsigned Pos, unsigned Size, int Low) {
3309 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3310 if (!isUndefOrEqual(Mask[i], Low))
3315 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3316 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3317 /// the second operand.
3318 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3319 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3320 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3321 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3322 return (Mask[0] < 2 && Mask[1] < 2);
3326 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3327 /// is suitable for input to PSHUFHW.
3328 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3329 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3332 // Lower quadword copied in order or undef.
3333 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3336 // Upper quadword shuffled.
3337 for (unsigned i = 4; i != 8; ++i)
3338 if (!isUndefOrInRange(Mask[i], 4, 8))
3341 if (VT == MVT::v16i16) {
3342 // Lower quadword copied in order or undef.
3343 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3346 // Upper quadword shuffled.
3347 for (unsigned i = 12; i != 16; ++i)
3348 if (!isUndefOrInRange(Mask[i], 12, 16))
3355 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3356 /// is suitable for input to PSHUFLW.
3357 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3358 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3361 // Upper quadword copied in order.
3362 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3365 // Lower quadword shuffled.
3366 for (unsigned i = 0; i != 4; ++i)
3367 if (!isUndefOrInRange(Mask[i], 0, 4))
3370 if (VT == MVT::v16i16) {
3371 // Upper quadword copied in order.
3372 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3375 // Lower quadword shuffled.
3376 for (unsigned i = 8; i != 12; ++i)
3377 if (!isUndefOrInRange(Mask[i], 8, 12))
3384 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3385 /// is suitable for input to PALIGNR.
3386 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3387 const X86Subtarget *Subtarget) {
3388 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3389 (VT.is256BitVector() && !Subtarget->hasInt256()))
3392 unsigned NumElts = VT.getVectorNumElements();
3393 unsigned NumLanes = VT.getSizeInBits()/128;
3394 unsigned NumLaneElts = NumElts/NumLanes;
3396 // Do not handle 64-bit element shuffles with palignr.
3397 if (NumLaneElts == 2)
3400 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3402 for (i = 0; i != NumLaneElts; ++i) {
3407 // Lane is all undef, go to next lane
3408 if (i == NumLaneElts)
3411 int Start = Mask[i+l];
3413 // Make sure its in this lane in one of the sources
3414 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3415 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3418 // If not lane 0, then we must match lane 0
3419 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3422 // Correct second source to be contiguous with first source
3423 if (Start >= (int)NumElts)
3424 Start -= NumElts - NumLaneElts;
3426 // Make sure we're shifting in the right direction.
3427 if (Start <= (int)(i+l))
3432 // Check the rest of the elements to see if they are consecutive.
3433 for (++i; i != NumLaneElts; ++i) {
3434 int Idx = Mask[i+l];
3436 // Make sure its in this lane
3437 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3438 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3441 // If not lane 0, then we must match lane 0
3442 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3445 if (Idx >= (int)NumElts)
3446 Idx -= NumElts - NumLaneElts;
3448 if (!isUndefOrEqual(Idx, Start+i))
3457 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3458 /// the two vector operands have swapped position.
3459 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3460 unsigned NumElems) {
3461 for (unsigned i = 0; i != NumElems; ++i) {
3465 else if (idx < (int)NumElems)
3466 Mask[i] = idx + NumElems;
3468 Mask[i] = idx - NumElems;
3472 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3473 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3474 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3475 /// reverse of what x86 shuffles want.
3476 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3477 bool Commuted = false) {
3478 if (!HasFp256 && VT.is256BitVector())
3481 unsigned NumElems = VT.getVectorNumElements();
3482 unsigned NumLanes = VT.getSizeInBits()/128;
3483 unsigned NumLaneElems = NumElems/NumLanes;
3485 if (NumLaneElems != 2 && NumLaneElems != 4)
3488 // VSHUFPSY divides the resulting vector into 4 chunks.
3489 // The sources are also splitted into 4 chunks, and each destination
3490 // chunk must come from a different source chunk.
3492 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3493 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3495 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3496 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3498 // VSHUFPDY divides the resulting vector into 4 chunks.
3499 // The sources are also splitted into 4 chunks, and each destination
3500 // chunk must come from a different source chunk.
3502 // SRC1 => X3 X2 X1 X0
3503 // SRC2 => Y3 Y2 Y1 Y0
3505 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3507 unsigned HalfLaneElems = NumLaneElems/2;
3508 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3509 for (unsigned i = 0; i != NumLaneElems; ++i) {
3510 int Idx = Mask[i+l];
3511 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3512 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3514 // For VSHUFPSY, the mask of the second half must be the same as the
3515 // first but with the appropriate offsets. This works in the same way as
3516 // VPERMILPS works with masks.
3517 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3519 if (!isUndefOrEqual(Idx, Mask[i]+l))
3527 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3528 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3529 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3530 if (!VT.is128BitVector())
3533 unsigned NumElems = VT.getVectorNumElements();
3538 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3539 return isUndefOrEqual(Mask[0], 6) &&
3540 isUndefOrEqual(Mask[1], 7) &&
3541 isUndefOrEqual(Mask[2], 2) &&
3542 isUndefOrEqual(Mask[3], 3);
3545 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3546 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3548 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3549 if (!VT.is128BitVector())
3552 unsigned NumElems = VT.getVectorNumElements();
3557 return isUndefOrEqual(Mask[0], 2) &&
3558 isUndefOrEqual(Mask[1], 3) &&
3559 isUndefOrEqual(Mask[2], 2) &&
3560 isUndefOrEqual(Mask[3], 3);
3563 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3564 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3565 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3566 if (!VT.is128BitVector())
3569 unsigned NumElems = VT.getVectorNumElements();
3571 if (NumElems != 2 && NumElems != 4)
3574 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3575 if (!isUndefOrEqual(Mask[i], i + NumElems))
3578 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3579 if (!isUndefOrEqual(Mask[i], i))
3585 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3586 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3587 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3588 if (!VT.is128BitVector())
3591 unsigned NumElems = VT.getVectorNumElements();
3593 if (NumElems != 2 && NumElems != 4)
3596 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3597 if (!isUndefOrEqual(Mask[i], i))
3600 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3601 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3608 // Some special combinations that can be optimized.
3611 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3612 SelectionDAG &DAG) {
3613 MVT VT = SVOp->getValueType(0).getSimpleVT();
3614 DebugLoc dl = SVOp->getDebugLoc();
3616 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3619 ArrayRef<int> Mask = SVOp->getMask();
3621 // These are the special masks that may be optimized.
3622 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3623 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3624 bool MatchEvenMask = true;
3625 bool MatchOddMask = true;
3626 for (int i=0; i<8; ++i) {
3627 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3628 MatchEvenMask = false;
3629 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3630 MatchOddMask = false;
3633 if (!MatchEvenMask && !MatchOddMask)
3636 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3638 SDValue Op0 = SVOp->getOperand(0);
3639 SDValue Op1 = SVOp->getOperand(1);
3641 if (MatchEvenMask) {
3642 // Shift the second operand right to 32 bits.
3643 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3644 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3646 // Shift the first operand left to 32 bits.
3647 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3648 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3650 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3651 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3654 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3655 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3656 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3657 bool HasInt256, bool V2IsSplat = false) {
3658 unsigned NumElts = VT.getVectorNumElements();
3660 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3661 "Unsupported vector type for unpckh");
3663 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3664 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3667 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3668 // independently on 128-bit lanes.
3669 unsigned NumLanes = VT.getSizeInBits()/128;
3670 unsigned NumLaneElts = NumElts/NumLanes;
3672 for (unsigned l = 0; l != NumLanes; ++l) {
3673 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3674 i != (l+1)*NumLaneElts;
3677 int BitI1 = Mask[i+1];
3678 if (!isUndefOrEqual(BitI, j))
3681 if (!isUndefOrEqual(BitI1, NumElts))
3684 if (!isUndefOrEqual(BitI1, j + NumElts))
3693 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3694 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3695 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3696 bool HasInt256, bool V2IsSplat = false) {
3697 unsigned NumElts = VT.getVectorNumElements();
3699 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3700 "Unsupported vector type for unpckh");
3702 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3703 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3706 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3707 // independently on 128-bit lanes.
3708 unsigned NumLanes = VT.getSizeInBits()/128;
3709 unsigned NumLaneElts = NumElts/NumLanes;
3711 for (unsigned l = 0; l != NumLanes; ++l) {
3712 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3713 i != (l+1)*NumLaneElts; i += 2, ++j) {
3715 int BitI1 = Mask[i+1];
3716 if (!isUndefOrEqual(BitI, j))
3719 if (isUndefOrEqual(BitI1, NumElts))
3722 if (!isUndefOrEqual(BitI1, j+NumElts))
3730 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3731 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3733 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3734 unsigned NumElts = VT.getVectorNumElements();
3735 bool Is256BitVec = VT.is256BitVector();
3737 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3738 "Unsupported vector type for unpckh");
3740 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3741 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3744 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3745 // FIXME: Need a better way to get rid of this, there's no latency difference
3746 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3747 // the former later. We should also remove the "_undef" special mask.
3748 if (NumElts == 4 && Is256BitVec)
3751 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3752 // independently on 128-bit lanes.
3753 unsigned NumLanes = VT.getSizeInBits()/128;
3754 unsigned NumLaneElts = NumElts/NumLanes;
3756 for (unsigned l = 0; l != NumLanes; ++l) {
3757 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3758 i != (l+1)*NumLaneElts;
3761 int BitI1 = Mask[i+1];
3763 if (!isUndefOrEqual(BitI, j))
3765 if (!isUndefOrEqual(BitI1, j))
3773 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3774 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3776 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3777 unsigned NumElts = VT.getVectorNumElements();
3779 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3780 "Unsupported vector type for unpckh");
3782 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3783 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3786 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3787 // independently on 128-bit lanes.
3788 unsigned NumLanes = VT.getSizeInBits()/128;
3789 unsigned NumLaneElts = NumElts/NumLanes;
3791 for (unsigned l = 0; l != NumLanes; ++l) {
3792 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3793 i != (l+1)*NumLaneElts; i += 2, ++j) {
3795 int BitI1 = Mask[i+1];
3796 if (!isUndefOrEqual(BitI, j))
3798 if (!isUndefOrEqual(BitI1, j))
3805 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3806 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3807 /// MOVSD, and MOVD, i.e. setting the lowest element.
3808 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3809 if (VT.getVectorElementType().getSizeInBits() < 32)
3811 if (!VT.is128BitVector())
3814 unsigned NumElts = VT.getVectorNumElements();
3816 if (!isUndefOrEqual(Mask[0], NumElts))
3819 for (unsigned i = 1; i != NumElts; ++i)
3820 if (!isUndefOrEqual(Mask[i], i))
3826 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3827 /// as permutations between 128-bit chunks or halves. As an example: this
3829 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3830 /// The first half comes from the second half of V1 and the second half from the
3831 /// the second half of V2.
3832 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3833 if (!HasFp256 || !VT.is256BitVector())
3836 // The shuffle result is divided into half A and half B. In total the two
3837 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3838 // B must come from C, D, E or F.
3839 unsigned HalfSize = VT.getVectorNumElements()/2;
3840 bool MatchA = false, MatchB = false;
3842 // Check if A comes from one of C, D, E, F.
3843 for (unsigned Half = 0; Half != 4; ++Half) {
3844 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3850 // Check if B comes from one of C, D, E, F.
3851 for (unsigned Half = 0; Half != 4; ++Half) {
3852 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3858 return MatchA && MatchB;
3861 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3862 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3863 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3864 MVT VT = SVOp->getValueType(0).getSimpleVT();
3866 unsigned HalfSize = VT.getVectorNumElements()/2;
3868 unsigned FstHalf = 0, SndHalf = 0;
3869 for (unsigned i = 0; i < HalfSize; ++i) {
3870 if (SVOp->getMaskElt(i) > 0) {
3871 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3875 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3876 if (SVOp->getMaskElt(i) > 0) {
3877 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3882 return (FstHalf | (SndHalf << 4));
3885 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3886 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3887 /// Note that VPERMIL mask matching is different depending whether theunderlying
3888 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3889 /// to the same elements of the low, but to the higher half of the source.
3890 /// In VPERMILPD the two lanes could be shuffled independently of each other
3891 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3892 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3896 unsigned NumElts = VT.getVectorNumElements();
3897 // Only match 256-bit with 32/64-bit types
3898 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
3901 unsigned NumLanes = VT.getSizeInBits()/128;
3902 unsigned LaneSize = NumElts/NumLanes;
3903 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3904 for (unsigned i = 0; i != LaneSize; ++i) {
3905 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3907 if (NumElts != 8 || l == 0)
3909 // VPERMILPS handling
3912 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3920 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3921 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3922 /// element of vector 2 and the other elements to come from vector 1 in order.
3923 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3924 bool V2IsSplat = false, bool V2IsUndef = false) {
3925 if (!VT.is128BitVector())
3928 unsigned NumOps = VT.getVectorNumElements();
3929 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3932 if (!isUndefOrEqual(Mask[0], 0))
3935 for (unsigned i = 1; i != NumOps; ++i)
3936 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3937 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3938 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3944 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3945 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3946 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3947 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3948 const X86Subtarget *Subtarget) {
3949 if (!Subtarget->hasSSE3())
3952 unsigned NumElems = VT.getVectorNumElements();
3954 if ((VT.is128BitVector() && NumElems != 4) ||
3955 (VT.is256BitVector() && NumElems != 8))
3958 // "i+1" is the value the indexed mask element must have
3959 for (unsigned i = 0; i != NumElems; i += 2)
3960 if (!isUndefOrEqual(Mask[i], i+1) ||
3961 !isUndefOrEqual(Mask[i+1], i+1))
3967 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3968 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3969 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3970 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3971 const X86Subtarget *Subtarget) {
3972 if (!Subtarget->hasSSE3())
3975 unsigned NumElems = VT.getVectorNumElements();
3977 if ((VT.is128BitVector() && NumElems != 4) ||
3978 (VT.is256BitVector() && NumElems != 8))
3981 // "i" is the value the indexed mask element must have
3982 for (unsigned i = 0; i != NumElems; i += 2)
3983 if (!isUndefOrEqual(Mask[i], i) ||
3984 !isUndefOrEqual(Mask[i+1], i))
3990 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3991 /// specifies a shuffle of elements that is suitable for input to 256-bit
3992 /// version of MOVDDUP.
3993 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3994 if (!HasFp256 || !VT.is256BitVector())
3997 unsigned NumElts = VT.getVectorNumElements();
4001 for (unsigned i = 0; i != NumElts/2; ++i)
4002 if (!isUndefOrEqual(Mask[i], 0))
4004 for (unsigned i = NumElts/2; i != NumElts; ++i)
4005 if (!isUndefOrEqual(Mask[i], NumElts/2))
4010 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4011 /// specifies a shuffle of elements that is suitable for input to 128-bit
4012 /// version of MOVDDUP.
4013 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
4014 if (!VT.is128BitVector())
4017 unsigned e = VT.getVectorNumElements() / 2;
4018 for (unsigned i = 0; i != e; ++i)
4019 if (!isUndefOrEqual(Mask[i], i))
4021 for (unsigned i = 0; i != e; ++i)
4022 if (!isUndefOrEqual(Mask[e+i], i))
4027 /// isVEXTRACTF128Index - Return true if the specified
4028 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4029 /// suitable for input to VEXTRACTF128.
4030 bool X86::isVEXTRACTF128Index(SDNode *N) {
4031 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4034 // The index should be aligned on a 128-bit boundary.
4036 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4038 MVT VT = N->getValueType(0).getSimpleVT();
4039 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4040 bool Result = (Index * ElSize) % 128 == 0;
4045 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4046 /// operand specifies a subvector insert that is suitable for input to
4048 bool X86::isVINSERTF128Index(SDNode *N) {
4049 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4052 // The index should be aligned on a 128-bit boundary.
4054 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4056 MVT VT = N->getValueType(0).getSimpleVT();
4057 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4058 bool Result = (Index * ElSize) % 128 == 0;
4063 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4064 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4065 /// Handles 128-bit and 256-bit.
4066 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4067 MVT VT = N->getValueType(0).getSimpleVT();
4069 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4070 "Unsupported vector type for PSHUF/SHUFP");
4072 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4073 // independently on 128-bit lanes.
4074 unsigned NumElts = VT.getVectorNumElements();
4075 unsigned NumLanes = VT.getSizeInBits()/128;
4076 unsigned NumLaneElts = NumElts/NumLanes;
4078 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4079 "Only supports 2 or 4 elements per lane");
4081 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4083 for (unsigned i = 0; i != NumElts; ++i) {
4084 int Elt = N->getMaskElt(i);
4085 if (Elt < 0) continue;
4086 Elt &= NumLaneElts - 1;
4087 unsigned ShAmt = (i << Shift) % 8;
4088 Mask |= Elt << ShAmt;
4094 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4095 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4096 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4097 MVT VT = N->getValueType(0).getSimpleVT();
4099 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4100 "Unsupported vector type for PSHUFHW");
4102 unsigned NumElts = VT.getVectorNumElements();
4105 for (unsigned l = 0; l != NumElts; l += 8) {
4106 // 8 nodes per lane, but we only care about the last 4.
4107 for (unsigned i = 0; i < 4; ++i) {
4108 int Elt = N->getMaskElt(l+i+4);
4109 if (Elt < 0) continue;
4110 Elt &= 0x3; // only 2-bits.
4111 Mask |= Elt << (i * 2);
4118 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4119 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4120 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4121 MVT VT = N->getValueType(0).getSimpleVT();
4123 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4124 "Unsupported vector type for PSHUFHW");
4126 unsigned NumElts = VT.getVectorNumElements();
4129 for (unsigned l = 0; l != NumElts; l += 8) {
4130 // 8 nodes per lane, but we only care about the first 4.
4131 for (unsigned i = 0; i < 4; ++i) {
4132 int Elt = N->getMaskElt(l+i);
4133 if (Elt < 0) continue;
4134 Elt &= 0x3; // only 2-bits
4135 Mask |= Elt << (i * 2);
4142 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4143 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4144 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4145 MVT VT = SVOp->getValueType(0).getSimpleVT();
4146 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4148 unsigned NumElts = VT.getVectorNumElements();
4149 unsigned NumLanes = VT.getSizeInBits()/128;
4150 unsigned NumLaneElts = NumElts/NumLanes;
4154 for (i = 0; i != NumElts; ++i) {
4155 Val = SVOp->getMaskElt(i);
4159 if (Val >= (int)NumElts)
4160 Val -= NumElts - NumLaneElts;
4162 assert(Val - i > 0 && "PALIGNR imm should be positive");
4163 return (Val - i) * EltSize;
4166 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4167 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4169 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4170 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4171 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4174 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4176 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT();
4177 MVT ElVT = VecVT.getVectorElementType();
4179 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4180 return Index / NumElemsPerChunk;
4183 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4184 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4186 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4187 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4188 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4191 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4193 MVT VecVT = N->getValueType(0).getSimpleVT();
4194 MVT ElVT = VecVT.getVectorElementType();
4196 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4197 return Index / NumElemsPerChunk;
4200 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4201 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4202 /// Handles 256-bit.
4203 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4204 MVT VT = N->getValueType(0).getSimpleVT();
4206 unsigned NumElts = VT.getVectorNumElements();
4208 assert((VT.is256BitVector() && NumElts == 4) &&
4209 "Unsupported vector type for VPERMQ/VPERMPD");
4212 for (unsigned i = 0; i != NumElts; ++i) {
4213 int Elt = N->getMaskElt(i);
4216 Mask |= Elt << (i*2);
4221 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4223 bool X86::isZeroNode(SDValue Elt) {
4224 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4225 return CN->isNullValue();
4226 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4227 return CFP->getValueAPF().isPosZero();
4231 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4232 /// their permute mask.
4233 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4234 SelectionDAG &DAG) {
4235 MVT VT = SVOp->getValueType(0).getSimpleVT();
4236 unsigned NumElems = VT.getVectorNumElements();
4237 SmallVector<int, 8> MaskVec;
4239 for (unsigned i = 0; i != NumElems; ++i) {
4240 int Idx = SVOp->getMaskElt(i);
4242 if (Idx < (int)NumElems)
4247 MaskVec.push_back(Idx);
4249 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4250 SVOp->getOperand(0), &MaskVec[0]);
4253 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4254 /// match movhlps. The lower half elements should come from upper half of
4255 /// V1 (and in order), and the upper half elements should come from the upper
4256 /// half of V2 (and in order).
4257 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4258 if (!VT.is128BitVector())
4260 if (VT.getVectorNumElements() != 4)
4262 for (unsigned i = 0, e = 2; i != e; ++i)
4263 if (!isUndefOrEqual(Mask[i], i+2))
4265 for (unsigned i = 2; i != 4; ++i)
4266 if (!isUndefOrEqual(Mask[i], i+4))
4271 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4272 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4274 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4275 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4277 N = N->getOperand(0).getNode();
4278 if (!ISD::isNON_EXTLoad(N))
4281 *LD = cast<LoadSDNode>(N);
4285 // Test whether the given value is a vector value which will be legalized
4287 static bool WillBeConstantPoolLoad(SDNode *N) {
4288 if (N->getOpcode() != ISD::BUILD_VECTOR)
4291 // Check for any non-constant elements.
4292 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4293 switch (N->getOperand(i).getNode()->getOpcode()) {
4295 case ISD::ConstantFP:
4302 // Vectors of all-zeros and all-ones are materialized with special
4303 // instructions rather than being loaded.
4304 return !ISD::isBuildVectorAllZeros(N) &&
4305 !ISD::isBuildVectorAllOnes(N);
4308 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4309 /// match movlp{s|d}. The lower half elements should come from lower half of
4310 /// V1 (and in order), and the upper half elements should come from the upper
4311 /// half of V2 (and in order). And since V1 will become the source of the
4312 /// MOVLP, it must be either a vector load or a scalar load to vector.
4313 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4314 ArrayRef<int> Mask, EVT VT) {
4315 if (!VT.is128BitVector())
4318 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4320 // Is V2 is a vector load, don't do this transformation. We will try to use
4321 // load folding shufps op.
4322 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4325 unsigned NumElems = VT.getVectorNumElements();
4327 if (NumElems != 2 && NumElems != 4)
4329 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4330 if (!isUndefOrEqual(Mask[i], i))
4332 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4333 if (!isUndefOrEqual(Mask[i], i+NumElems))
4338 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4340 static bool isSplatVector(SDNode *N) {
4341 if (N->getOpcode() != ISD::BUILD_VECTOR)
4344 SDValue SplatValue = N->getOperand(0);
4345 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4346 if (N->getOperand(i) != SplatValue)
4351 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4352 /// to an zero vector.
4353 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4354 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4355 SDValue V1 = N->getOperand(0);
4356 SDValue V2 = N->getOperand(1);
4357 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4358 for (unsigned i = 0; i != NumElems; ++i) {
4359 int Idx = N->getMaskElt(i);
4360 if (Idx >= (int)NumElems) {
4361 unsigned Opc = V2.getOpcode();
4362 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4364 if (Opc != ISD::BUILD_VECTOR ||
4365 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4367 } else if (Idx >= 0) {
4368 unsigned Opc = V1.getOpcode();
4369 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4371 if (Opc != ISD::BUILD_VECTOR ||
4372 !X86::isZeroNode(V1.getOperand(Idx)))
4379 /// getZeroVector - Returns a vector of specified type with all zero elements.
4381 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4382 SelectionDAG &DAG, DebugLoc dl) {
4383 assert(VT.isVector() && "Expected a vector type");
4385 // Always build SSE zero vectors as <4 x i32> bitcasted
4386 // to their dest type. This ensures they get CSE'd.
4388 if (VT.is128BitVector()) { // SSE
4389 if (Subtarget->hasSSE2()) { // SSE2
4390 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4391 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4393 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4394 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4396 } else if (VT.is256BitVector()) { // AVX
4397 if (Subtarget->hasInt256()) { // AVX2
4398 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4399 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4400 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4402 // 256-bit logic and arithmetic instructions in AVX are all
4403 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4404 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4405 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4406 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4409 llvm_unreachable("Unexpected vector type");
4411 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4414 /// getOnesVector - Returns a vector of specified type with all bits set.
4415 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4416 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4417 /// Then bitcast to their original type, ensuring they get CSE'd.
4418 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4420 assert(VT.isVector() && "Expected a vector type");
4422 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4424 if (VT.is256BitVector()) {
4425 if (HasInt256) { // AVX2
4426 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4427 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4429 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4430 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4432 } else if (VT.is128BitVector()) {
4433 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4435 llvm_unreachable("Unexpected vector type");
4437 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4440 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4441 /// that point to V2 points to its first element.
4442 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4443 for (unsigned i = 0; i != NumElems; ++i) {
4444 if (Mask[i] > (int)NumElems) {
4450 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4451 /// operation of specified width.
4452 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4454 unsigned NumElems = VT.getVectorNumElements();
4455 SmallVector<int, 8> Mask;
4456 Mask.push_back(NumElems);
4457 for (unsigned i = 1; i != NumElems; ++i)
4459 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4462 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4463 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4465 unsigned NumElems = VT.getVectorNumElements();
4466 SmallVector<int, 8> Mask;
4467 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4469 Mask.push_back(i + NumElems);
4471 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4474 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4475 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4477 unsigned NumElems = VT.getVectorNumElements();
4478 SmallVector<int, 8> Mask;
4479 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4480 Mask.push_back(i + Half);
4481 Mask.push_back(i + NumElems + Half);
4483 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4486 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4487 // a generic shuffle instruction because the target has no such instructions.
4488 // Generate shuffles which repeat i16 and i8 several times until they can be
4489 // represented by v4f32 and then be manipulated by target suported shuffles.
4490 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4491 EVT VT = V.getValueType();
4492 int NumElems = VT.getVectorNumElements();
4493 DebugLoc dl = V.getDebugLoc();
4495 while (NumElems > 4) {
4496 if (EltNo < NumElems/2) {
4497 V = getUnpackl(DAG, dl, VT, V, V);
4499 V = getUnpackh(DAG, dl, VT, V, V);
4500 EltNo -= NumElems/2;
4507 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4508 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4509 EVT VT = V.getValueType();
4510 DebugLoc dl = V.getDebugLoc();
4512 if (VT.is128BitVector()) {
4513 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4514 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4515 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4517 } else if (VT.is256BitVector()) {
4518 // To use VPERMILPS to splat scalars, the second half of indicies must
4519 // refer to the higher part, which is a duplication of the lower one,
4520 // because VPERMILPS can only handle in-lane permutations.
4521 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4522 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4524 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4525 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4528 llvm_unreachable("Vector size not supported");
4530 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4533 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4534 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4535 EVT SrcVT = SV->getValueType(0);
4536 SDValue V1 = SV->getOperand(0);
4537 DebugLoc dl = SV->getDebugLoc();
4539 int EltNo = SV->getSplatIndex();
4540 int NumElems = SrcVT.getVectorNumElements();
4541 bool Is256BitVec = SrcVT.is256BitVector();
4543 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4544 "Unknown how to promote splat for type");
4546 // Extract the 128-bit part containing the splat element and update
4547 // the splat element index when it refers to the higher register.
4549 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4550 if (EltNo >= NumElems/2)
4551 EltNo -= NumElems/2;
4554 // All i16 and i8 vector types can't be used directly by a generic shuffle
4555 // instruction because the target has no such instruction. Generate shuffles
4556 // which repeat i16 and i8 several times until they fit in i32, and then can
4557 // be manipulated by target suported shuffles.
4558 EVT EltVT = SrcVT.getVectorElementType();
4559 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4560 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4562 // Recreate the 256-bit vector and place the same 128-bit vector
4563 // into the low and high part. This is necessary because we want
4564 // to use VPERM* to shuffle the vectors
4566 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4569 return getLegalSplat(DAG, V1, EltNo);
4572 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4573 /// vector of zero or undef vector. This produces a shuffle where the low
4574 /// element of V2 is swizzled into the zero/undef vector, landing at element
4575 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4576 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4578 const X86Subtarget *Subtarget,
4579 SelectionDAG &DAG) {
4580 EVT VT = V2.getValueType();
4582 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4583 unsigned NumElems = VT.getVectorNumElements();
4584 SmallVector<int, 16> MaskVec;
4585 for (unsigned i = 0; i != NumElems; ++i)
4586 // If this is the insertion idx, put the low elt of V2 here.
4587 MaskVec.push_back(i == Idx ? NumElems : i);
4588 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4591 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4592 /// target specific opcode. Returns true if the Mask could be calculated.
4593 /// Sets IsUnary to true if only uses one source.
4594 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4595 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4596 unsigned NumElems = VT.getVectorNumElements();
4600 switch(N->getOpcode()) {
4602 ImmN = N->getOperand(N->getNumOperands()-1);
4603 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4605 case X86ISD::UNPCKH:
4606 DecodeUNPCKHMask(VT, Mask);
4608 case X86ISD::UNPCKL:
4609 DecodeUNPCKLMask(VT, Mask);
4611 case X86ISD::MOVHLPS:
4612 DecodeMOVHLPSMask(NumElems, Mask);
4614 case X86ISD::MOVLHPS:
4615 DecodeMOVLHPSMask(NumElems, Mask);
4617 case X86ISD::PALIGNR:
4618 ImmN = N->getOperand(N->getNumOperands()-1);
4619 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4621 case X86ISD::PSHUFD:
4622 case X86ISD::VPERMILP:
4623 ImmN = N->getOperand(N->getNumOperands()-1);
4624 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4627 case X86ISD::PSHUFHW:
4628 ImmN = N->getOperand(N->getNumOperands()-1);
4629 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4632 case X86ISD::PSHUFLW:
4633 ImmN = N->getOperand(N->getNumOperands()-1);
4634 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4637 case X86ISD::VPERMI:
4638 ImmN = N->getOperand(N->getNumOperands()-1);
4639 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4643 case X86ISD::MOVSD: {
4644 // The index 0 always comes from the first element of the second source,
4645 // this is why MOVSS and MOVSD are used in the first place. The other
4646 // elements come from the other positions of the first source vector
4647 Mask.push_back(NumElems);
4648 for (unsigned i = 1; i != NumElems; ++i) {
4653 case X86ISD::VPERM2X128:
4654 ImmN = N->getOperand(N->getNumOperands()-1);
4655 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4656 if (Mask.empty()) return false;
4658 case X86ISD::MOVDDUP:
4659 case X86ISD::MOVLHPD:
4660 case X86ISD::MOVLPD:
4661 case X86ISD::MOVLPS:
4662 case X86ISD::MOVSHDUP:
4663 case X86ISD::MOVSLDUP:
4664 // Not yet implemented
4666 default: llvm_unreachable("unknown target shuffle node");
4672 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4673 /// element of the result of the vector shuffle.
4674 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4677 return SDValue(); // Limit search depth.
4679 SDValue V = SDValue(N, 0);
4680 EVT VT = V.getValueType();
4681 unsigned Opcode = V.getOpcode();
4683 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4684 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4685 int Elt = SV->getMaskElt(Index);
4688 return DAG.getUNDEF(VT.getVectorElementType());
4690 unsigned NumElems = VT.getVectorNumElements();
4691 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4692 : SV->getOperand(1);
4693 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4696 // Recurse into target specific vector shuffles to find scalars.
4697 if (isTargetShuffle(Opcode)) {
4698 MVT ShufVT = V.getValueType().getSimpleVT();
4699 unsigned NumElems = ShufVT.getVectorNumElements();
4700 SmallVector<int, 16> ShuffleMask;
4703 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4706 int Elt = ShuffleMask[Index];
4708 return DAG.getUNDEF(ShufVT.getVectorElementType());
4710 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4712 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4716 // Actual nodes that may contain scalar elements
4717 if (Opcode == ISD::BITCAST) {
4718 V = V.getOperand(0);
4719 EVT SrcVT = V.getValueType();
4720 unsigned NumElems = VT.getVectorNumElements();
4722 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4726 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4727 return (Index == 0) ? V.getOperand(0)
4728 : DAG.getUNDEF(VT.getVectorElementType());
4730 if (V.getOpcode() == ISD::BUILD_VECTOR)
4731 return V.getOperand(Index);
4736 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4737 /// shuffle operation which come from a consecutively from a zero. The
4738 /// search can start in two different directions, from left or right.
4740 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4741 bool ZerosFromLeft, SelectionDAG &DAG) {
4743 for (i = 0; i != NumElems; ++i) {
4744 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4745 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4746 if (!(Elt.getNode() &&
4747 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4754 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4755 /// correspond consecutively to elements from one of the vector operands,
4756 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4758 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4759 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4760 unsigned NumElems, unsigned &OpNum) {
4761 bool SeenV1 = false;
4762 bool SeenV2 = false;
4764 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4765 int Idx = SVOp->getMaskElt(i);
4766 // Ignore undef indicies
4770 if (Idx < (int)NumElems)
4775 // Only accept consecutive elements from the same vector
4776 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4780 OpNum = SeenV1 ? 0 : 1;
4784 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4785 /// logical left shift of a vector.
4786 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4787 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4788 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4789 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4790 false /* check zeros from right */, DAG);
4796 // Considering the elements in the mask that are not consecutive zeros,
4797 // check if they consecutively come from only one of the source vectors.
4799 // V1 = {X, A, B, C} 0
4801 // vector_shuffle V1, V2 <1, 2, 3, X>
4803 if (!isShuffleMaskConsecutive(SVOp,
4804 0, // Mask Start Index
4805 NumElems-NumZeros, // Mask End Index(exclusive)
4806 NumZeros, // Where to start looking in the src vector
4807 NumElems, // Number of elements in vector
4808 OpSrc)) // Which source operand ?
4813 ShVal = SVOp->getOperand(OpSrc);
4817 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4818 /// logical left shift of a vector.
4819 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4820 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4821 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4822 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4823 true /* check zeros from left */, DAG);
4829 // Considering the elements in the mask that are not consecutive zeros,
4830 // check if they consecutively come from only one of the source vectors.
4832 // 0 { A, B, X, X } = V2
4834 // vector_shuffle V1, V2 <X, X, 4, 5>
4836 if (!isShuffleMaskConsecutive(SVOp,
4837 NumZeros, // Mask Start Index
4838 NumElems, // Mask End Index(exclusive)
4839 0, // Where to start looking in the src vector
4840 NumElems, // Number of elements in vector
4841 OpSrc)) // Which source operand ?
4846 ShVal = SVOp->getOperand(OpSrc);
4850 /// isVectorShift - Returns true if the shuffle can be implemented as a
4851 /// logical left or right shift of a vector.
4852 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4853 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4854 // Although the logic below support any bitwidth size, there are no
4855 // shift instructions which handle more than 128-bit vectors.
4856 if (!SVOp->getValueType(0).is128BitVector())
4859 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4860 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4866 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4868 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4869 unsigned NumNonZero, unsigned NumZero,
4871 const X86Subtarget* Subtarget,
4872 const TargetLowering &TLI) {
4876 DebugLoc dl = Op.getDebugLoc();
4879 for (unsigned i = 0; i < 16; ++i) {
4880 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4881 if (ThisIsNonZero && First) {
4883 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4885 V = DAG.getUNDEF(MVT::v8i16);
4890 SDValue ThisElt(0, 0), LastElt(0, 0);
4891 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4892 if (LastIsNonZero) {
4893 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4894 MVT::i16, Op.getOperand(i-1));
4896 if (ThisIsNonZero) {
4897 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4898 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4899 ThisElt, DAG.getConstant(8, MVT::i8));
4901 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4905 if (ThisElt.getNode())
4906 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4907 DAG.getIntPtrConstant(i/2));
4911 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4914 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4916 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4917 unsigned NumNonZero, unsigned NumZero,
4919 const X86Subtarget* Subtarget,
4920 const TargetLowering &TLI) {
4924 DebugLoc dl = Op.getDebugLoc();
4927 for (unsigned i = 0; i < 8; ++i) {
4928 bool isNonZero = (NonZeros & (1 << i)) != 0;
4932 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4934 V = DAG.getUNDEF(MVT::v8i16);
4937 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4938 MVT::v8i16, V, Op.getOperand(i),
4939 DAG.getIntPtrConstant(i));
4946 /// getVShift - Return a vector logical shift node.
4948 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4949 unsigned NumBits, SelectionDAG &DAG,
4950 const TargetLowering &TLI, DebugLoc dl) {
4951 assert(VT.is128BitVector() && "Unknown type for VShift");
4952 EVT ShVT = MVT::v2i64;
4953 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4954 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4955 return DAG.getNode(ISD::BITCAST, dl, VT,
4956 DAG.getNode(Opc, dl, ShVT, SrcOp,
4957 DAG.getConstant(NumBits,
4958 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4962 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4963 SelectionDAG &DAG) const {
4965 // Check if the scalar load can be widened into a vector load. And if
4966 // the address is "base + cst" see if the cst can be "absorbed" into
4967 // the shuffle mask.
4968 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4969 SDValue Ptr = LD->getBasePtr();
4970 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4972 EVT PVT = LD->getValueType(0);
4973 if (PVT != MVT::i32 && PVT != MVT::f32)
4978 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4979 FI = FINode->getIndex();
4981 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4982 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4983 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4984 Offset = Ptr.getConstantOperandVal(1);
4985 Ptr = Ptr.getOperand(0);
4990 // FIXME: 256-bit vector instructions don't require a strict alignment,
4991 // improve this code to support it better.
4992 unsigned RequiredAlign = VT.getSizeInBits()/8;
4993 SDValue Chain = LD->getChain();
4994 // Make sure the stack object alignment is at least 16 or 32.
4995 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4996 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4997 if (MFI->isFixedObjectIndex(FI)) {
4998 // Can't change the alignment. FIXME: It's possible to compute
4999 // the exact stack offset and reference FI + adjust offset instead.
5000 // If someone *really* cares about this. That's the way to implement it.
5003 MFI->setObjectAlignment(FI, RequiredAlign);
5007 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5008 // Ptr + (Offset & ~15).
5011 if ((Offset % RequiredAlign) & 3)
5013 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5015 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
5016 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5018 int EltNo = (Offset - StartOffset) >> 2;
5019 unsigned NumElems = VT.getVectorNumElements();
5021 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5022 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5023 LD->getPointerInfo().getWithOffset(StartOffset),
5024 false, false, false, 0);
5026 SmallVector<int, 8> Mask;
5027 for (unsigned i = 0; i != NumElems; ++i)
5028 Mask.push_back(EltNo);
5030 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5036 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5037 /// vector of type 'VT', see if the elements can be replaced by a single large
5038 /// load which has the same value as a build_vector whose operands are 'elts'.
5040 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5042 /// FIXME: we'd also like to handle the case where the last elements are zero
5043 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5044 /// There's even a handy isZeroNode for that purpose.
5045 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5046 DebugLoc &DL, SelectionDAG &DAG) {
5047 EVT EltVT = VT.getVectorElementType();
5048 unsigned NumElems = Elts.size();
5050 LoadSDNode *LDBase = NULL;
5051 unsigned LastLoadedElt = -1U;
5053 // For each element in the initializer, see if we've found a load or an undef.
5054 // If we don't find an initial load element, or later load elements are
5055 // non-consecutive, bail out.
5056 for (unsigned i = 0; i < NumElems; ++i) {
5057 SDValue Elt = Elts[i];
5059 if (!Elt.getNode() ||
5060 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5063 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5065 LDBase = cast<LoadSDNode>(Elt.getNode());
5069 if (Elt.getOpcode() == ISD::UNDEF)
5072 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5073 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5078 // If we have found an entire vector of loads and undefs, then return a large
5079 // load of the entire vector width starting at the base pointer. If we found
5080 // consecutive loads for the low half, generate a vzext_load node.
5081 if (LastLoadedElt == NumElems - 1) {
5082 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5083 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5084 LDBase->getPointerInfo(),
5085 LDBase->isVolatile(), LDBase->isNonTemporal(),
5086 LDBase->isInvariant(), 0);
5087 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5088 LDBase->getPointerInfo(),
5089 LDBase->isVolatile(), LDBase->isNonTemporal(),
5090 LDBase->isInvariant(), LDBase->getAlignment());
5092 if (NumElems == 4 && LastLoadedElt == 1 &&
5093 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5094 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5095 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5097 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5098 LDBase->getPointerInfo(),
5099 LDBase->getAlignment(),
5100 false/*isVolatile*/, true/*ReadMem*/,
5103 // Make sure the newly-created LOAD is in the same position as LDBase in
5104 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5105 // update uses of LDBase's output chain to use the TokenFactor.
5106 if (LDBase->hasAnyUseOfValue(1)) {
5107 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5108 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5109 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5110 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5111 SDValue(ResNode.getNode(), 1));
5114 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5119 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5120 /// to generate a splat value for the following cases:
5121 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5122 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5123 /// a scalar load, or a constant.
5124 /// The VBROADCAST node is returned when a pattern is found,
5125 /// or SDValue() otherwise.
5127 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5128 if (!Subtarget->hasFp256())
5131 MVT VT = Op.getValueType().getSimpleVT();
5132 DebugLoc dl = Op.getDebugLoc();
5134 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5135 "Unsupported vector type for broadcast.");
5140 switch (Op.getOpcode()) {
5142 // Unknown pattern found.
5145 case ISD::BUILD_VECTOR: {
5146 // The BUILD_VECTOR node must be a splat.
5147 if (!isSplatVector(Op.getNode()))
5150 Ld = Op.getOperand(0);
5151 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5152 Ld.getOpcode() == ISD::ConstantFP);
5154 // The suspected load node has several users. Make sure that all
5155 // of its users are from the BUILD_VECTOR node.
5156 // Constants may have multiple users.
5157 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5162 case ISD::VECTOR_SHUFFLE: {
5163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5165 // Shuffles must have a splat mask where the first element is
5167 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5170 SDValue Sc = Op.getOperand(0);
5171 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5172 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5174 if (!Subtarget->hasInt256())
5177 // Use the register form of the broadcast instruction available on AVX2.
5178 if (VT.is256BitVector())
5179 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5180 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5183 Ld = Sc.getOperand(0);
5184 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5185 Ld.getOpcode() == ISD::ConstantFP);
5187 // The scalar_to_vector node and the suspected
5188 // load node must have exactly one user.
5189 // Constants may have multiple users.
5190 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5196 bool Is256 = VT.is256BitVector();
5198 // Handle the broadcasting a single constant scalar from the constant pool
5199 // into a vector. On Sandybridge it is still better to load a constant vector
5200 // from the constant pool and not to broadcast it from a scalar.
5201 if (ConstSplatVal && Subtarget->hasInt256()) {
5202 EVT CVT = Ld.getValueType();
5203 assert(!CVT.isVector() && "Must not broadcast a vector type");
5204 unsigned ScalarSize = CVT.getSizeInBits();
5206 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5207 const Constant *C = 0;
5208 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5209 C = CI->getConstantIntValue();
5210 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5211 C = CF->getConstantFPValue();
5213 assert(C && "Invalid constant type");
5215 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5216 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5217 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5218 MachinePointerInfo::getConstantPool(),
5219 false, false, false, Alignment);
5221 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5225 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5226 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5228 // Handle AVX2 in-register broadcasts.
5229 if (!IsLoad && Subtarget->hasInt256() &&
5230 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5231 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5233 // The scalar source must be a normal load.
5237 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5238 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5240 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5241 // double since there is no vbroadcastsd xmm
5242 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5243 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5244 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5247 // Unsupported broadcast.
5252 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5253 EVT VT = Op.getValueType();
5255 // Skip if insert_vec_elt is not supported.
5256 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5259 DebugLoc DL = Op.getDebugLoc();
5260 unsigned NumElems = Op.getNumOperands();
5264 SmallVector<unsigned, 4> InsertIndices;
5265 SmallVector<int, 8> Mask(NumElems, -1);
5267 for (unsigned i = 0; i != NumElems; ++i) {
5268 unsigned Opc = Op.getOperand(i).getOpcode();
5270 if (Opc == ISD::UNDEF)
5273 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5274 // Quit if more than 1 elements need inserting.
5275 if (InsertIndices.size() > 1)
5278 InsertIndices.push_back(i);
5282 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5283 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5285 // Quit if extracted from vector of different type.
5286 if (ExtractedFromVec.getValueType() != VT)
5289 // Quit if non-constant index.
5290 if (!isa<ConstantSDNode>(ExtIdx))
5293 if (VecIn1.getNode() == 0)
5294 VecIn1 = ExtractedFromVec;
5295 else if (VecIn1 != ExtractedFromVec) {
5296 if (VecIn2.getNode() == 0)
5297 VecIn2 = ExtractedFromVec;
5298 else if (VecIn2 != ExtractedFromVec)
5299 // Quit if more than 2 vectors to shuffle
5303 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5305 if (ExtractedFromVec == VecIn1)
5307 else if (ExtractedFromVec == VecIn2)
5308 Mask[i] = Idx + NumElems;
5311 if (VecIn1.getNode() == 0)
5314 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5315 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5316 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5317 unsigned Idx = InsertIndices[i];
5318 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5319 DAG.getIntPtrConstant(Idx));
5326 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5327 DebugLoc dl = Op.getDebugLoc();
5329 MVT VT = Op.getValueType().getSimpleVT();
5330 MVT ExtVT = VT.getVectorElementType();
5331 unsigned NumElems = Op.getNumOperands();
5333 // Vectors containing all zeros can be matched by pxor and xorps later
5334 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5335 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5336 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5337 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5340 return getZeroVector(VT, Subtarget, DAG, dl);
5343 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5344 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5345 // vpcmpeqd on 256-bit vectors.
5346 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5347 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5350 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5353 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5354 if (Broadcast.getNode())
5357 unsigned EVTBits = ExtVT.getSizeInBits();
5359 unsigned NumZero = 0;
5360 unsigned NumNonZero = 0;
5361 unsigned NonZeros = 0;
5362 bool IsAllConstants = true;
5363 SmallSet<SDValue, 8> Values;
5364 for (unsigned i = 0; i < NumElems; ++i) {
5365 SDValue Elt = Op.getOperand(i);
5366 if (Elt.getOpcode() == ISD::UNDEF)
5369 if (Elt.getOpcode() != ISD::Constant &&
5370 Elt.getOpcode() != ISD::ConstantFP)
5371 IsAllConstants = false;
5372 if (X86::isZeroNode(Elt))
5375 NonZeros |= (1 << i);
5380 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5381 if (NumNonZero == 0)
5382 return DAG.getUNDEF(VT);
5384 // Special case for single non-zero, non-undef, element.
5385 if (NumNonZero == 1) {
5386 unsigned Idx = CountTrailingZeros_32(NonZeros);
5387 SDValue Item = Op.getOperand(Idx);
5389 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5390 // the value are obviously zero, truncate the value to i32 and do the
5391 // insertion that way. Only do this if the value is non-constant or if the
5392 // value is a constant being inserted into element 0. It is cheaper to do
5393 // a constant pool load than it is to do a movd + shuffle.
5394 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5395 (!IsAllConstants || Idx == 0)) {
5396 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5398 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5399 EVT VecVT = MVT::v4i32;
5400 unsigned VecElts = 4;
5402 // Truncate the value (which may itself be a constant) to i32, and
5403 // convert it to a vector with movd (S2V+shuffle to zero extend).
5404 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5405 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5406 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5408 // Now we have our 32-bit value zero extended in the low element of
5409 // a vector. If Idx != 0, swizzle it into place.
5411 SmallVector<int, 4> Mask;
5412 Mask.push_back(Idx);
5413 for (unsigned i = 1; i != VecElts; ++i)
5415 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5418 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5422 // If we have a constant or non-constant insertion into the low element of
5423 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5424 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5425 // depending on what the source datatype is.
5428 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5430 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5431 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5432 if (VT.is256BitVector()) {
5433 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5434 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5435 Item, DAG.getIntPtrConstant(0));
5437 assert(VT.is128BitVector() && "Expected an SSE value type!");
5438 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5439 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5440 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5443 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5444 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5445 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5446 if (VT.is256BitVector()) {
5447 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5448 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5450 assert(VT.is128BitVector() && "Expected an SSE value type!");
5451 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5453 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5457 // Is it a vector logical left shift?
5458 if (NumElems == 2 && Idx == 1 &&
5459 X86::isZeroNode(Op.getOperand(0)) &&
5460 !X86::isZeroNode(Op.getOperand(1))) {
5461 unsigned NumBits = VT.getSizeInBits();
5462 return getVShift(true, VT,
5463 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5464 VT, Op.getOperand(1)),
5465 NumBits/2, DAG, *this, dl);
5468 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5471 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5472 // is a non-constant being inserted into an element other than the low one,
5473 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5474 // movd/movss) to move this into the low element, then shuffle it into
5476 if (EVTBits == 32) {
5477 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5479 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5480 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5481 SmallVector<int, 8> MaskVec;
5482 for (unsigned i = 0; i != NumElems; ++i)
5483 MaskVec.push_back(i == Idx ? 0 : 1);
5484 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5488 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5489 if (Values.size() == 1) {
5490 if (EVTBits == 32) {
5491 // Instead of a shuffle like this:
5492 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5493 // Check if it's possible to issue this instead.
5494 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5495 unsigned Idx = CountTrailingZeros_32(NonZeros);
5496 SDValue Item = Op.getOperand(Idx);
5497 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5498 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5503 // A vector full of immediates; various special cases are already
5504 // handled, so this is best done with a single constant-pool load.
5508 // For AVX-length vectors, build the individual 128-bit pieces and use
5509 // shuffles to put them in place.
5510 if (VT.is256BitVector()) {
5511 SmallVector<SDValue, 32> V;
5512 for (unsigned i = 0; i != NumElems; ++i)
5513 V.push_back(Op.getOperand(i));
5515 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5517 // Build both the lower and upper subvector.
5518 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5519 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5522 // Recreate the wider vector with the lower and upper part.
5523 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5526 // Let legalizer expand 2-wide build_vectors.
5527 if (EVTBits == 64) {
5528 if (NumNonZero == 1) {
5529 // One half is zero or undef.
5530 unsigned Idx = CountTrailingZeros_32(NonZeros);
5531 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5532 Op.getOperand(Idx));
5533 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5538 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5539 if (EVTBits == 8 && NumElems == 16) {
5540 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5542 if (V.getNode()) return V;
5545 if (EVTBits == 16 && NumElems == 8) {
5546 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5548 if (V.getNode()) return V;
5551 // If element VT is == 32 bits, turn it into a number of shuffles.
5552 SmallVector<SDValue, 8> V(NumElems);
5553 if (NumElems == 4 && NumZero > 0) {
5554 for (unsigned i = 0; i < 4; ++i) {
5555 bool isZero = !(NonZeros & (1 << i));
5557 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5559 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5562 for (unsigned i = 0; i < 2; ++i) {
5563 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5566 V[i] = V[i*2]; // Must be a zero vector.
5569 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5572 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5575 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5580 bool Reverse1 = (NonZeros & 0x3) == 2;
5581 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5585 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5586 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5588 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5591 if (Values.size() > 1 && VT.is128BitVector()) {
5592 // Check for a build vector of consecutive loads.
5593 for (unsigned i = 0; i < NumElems; ++i)
5594 V[i] = Op.getOperand(i);
5596 // Check for elements which are consecutive loads.
5597 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5601 // Check for a build vector from mostly shuffle plus few inserting.
5602 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5606 // For SSE 4.1, use insertps to put the high elements into the low element.
5607 if (getSubtarget()->hasSSE41()) {
5609 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5610 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5612 Result = DAG.getUNDEF(VT);
5614 for (unsigned i = 1; i < NumElems; ++i) {
5615 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5616 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5617 Op.getOperand(i), DAG.getIntPtrConstant(i));
5622 // Otherwise, expand into a number of unpckl*, start by extending each of
5623 // our (non-undef) elements to the full vector width with the element in the
5624 // bottom slot of the vector (which generates no code for SSE).
5625 for (unsigned i = 0; i < NumElems; ++i) {
5626 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5627 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5629 V[i] = DAG.getUNDEF(VT);
5632 // Next, we iteratively mix elements, e.g. for v4f32:
5633 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5634 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5635 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5636 unsigned EltStride = NumElems >> 1;
5637 while (EltStride != 0) {
5638 for (unsigned i = 0; i < EltStride; ++i) {
5639 // If V[i+EltStride] is undef and this is the first round of mixing,
5640 // then it is safe to just drop this shuffle: V[i] is already in the
5641 // right place, the one element (since it's the first round) being
5642 // inserted as undef can be dropped. This isn't safe for successive
5643 // rounds because they will permute elements within both vectors.
5644 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5645 EltStride == NumElems/2)
5648 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5657 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5658 // to create 256-bit vectors from two other 128-bit ones.
5659 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5660 DebugLoc dl = Op.getDebugLoc();
5661 MVT ResVT = Op.getValueType().getSimpleVT();
5663 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5665 SDValue V1 = Op.getOperand(0);
5666 SDValue V2 = Op.getOperand(1);
5667 unsigned NumElems = ResVT.getVectorNumElements();
5669 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5672 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5673 assert(Op.getNumOperands() == 2);
5675 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5676 // from two other 128-bit ones.
5677 return LowerAVXCONCAT_VECTORS(Op, DAG);
5680 // Try to lower a shuffle node into a simple blend instruction.
5682 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5683 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5684 SDValue V1 = SVOp->getOperand(0);
5685 SDValue V2 = SVOp->getOperand(1);
5686 DebugLoc dl = SVOp->getDebugLoc();
5687 MVT VT = SVOp->getValueType(0).getSimpleVT();
5688 MVT EltVT = VT.getVectorElementType();
5689 unsigned NumElems = VT.getVectorNumElements();
5691 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5693 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5696 // Check the mask for BLEND and build the value.
5697 unsigned MaskValue = 0;
5698 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5699 unsigned NumLanes = (NumElems-1)/8 + 1;
5700 unsigned NumElemsInLane = NumElems / NumLanes;
5702 // Blend for v16i16 should be symetric for the both lanes.
5703 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5705 int SndLaneEltIdx = (NumLanes == 2) ?
5706 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5707 int EltIdx = SVOp->getMaskElt(i);
5709 if ((EltIdx < 0 || EltIdx == (int)i) &&
5710 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5713 if (((unsigned)EltIdx == (i + NumElems)) &&
5714 (SndLaneEltIdx < 0 ||
5715 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
5716 MaskValue |= (1<<i);
5721 // Convert i32 vectors to floating point if it is not AVX2.
5722 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
5724 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
5725 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
5727 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5728 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5731 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
5732 DAG.getConstant(MaskValue, MVT::i32));
5733 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5736 // v8i16 shuffles - Prefer shuffles in the following order:
5737 // 1. [all] pshuflw, pshufhw, optional move
5738 // 2. [ssse3] 1 x pshufb
5739 // 3. [ssse3] 2 x pshufb + 1 x por
5740 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5742 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
5743 SelectionDAG &DAG) {
5744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5745 SDValue V1 = SVOp->getOperand(0);
5746 SDValue V2 = SVOp->getOperand(1);
5747 DebugLoc dl = SVOp->getDebugLoc();
5748 SmallVector<int, 8> MaskVals;
5750 // Determine if more than 1 of the words in each of the low and high quadwords
5751 // of the result come from the same quadword of one of the two inputs. Undef
5752 // mask values count as coming from any quadword, for better codegen.
5753 unsigned LoQuad[] = { 0, 0, 0, 0 };
5754 unsigned HiQuad[] = { 0, 0, 0, 0 };
5755 std::bitset<4> InputQuads;
5756 for (unsigned i = 0; i < 8; ++i) {
5757 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5758 int EltIdx = SVOp->getMaskElt(i);
5759 MaskVals.push_back(EltIdx);
5768 InputQuads.set(EltIdx / 4);
5771 int BestLoQuad = -1;
5772 unsigned MaxQuad = 1;
5773 for (unsigned i = 0; i < 4; ++i) {
5774 if (LoQuad[i] > MaxQuad) {
5776 MaxQuad = LoQuad[i];
5780 int BestHiQuad = -1;
5782 for (unsigned i = 0; i < 4; ++i) {
5783 if (HiQuad[i] > MaxQuad) {
5785 MaxQuad = HiQuad[i];
5789 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5790 // of the two input vectors, shuffle them into one input vector so only a
5791 // single pshufb instruction is necessary. If There are more than 2 input
5792 // quads, disable the next transformation since it does not help SSSE3.
5793 bool V1Used = InputQuads[0] || InputQuads[1];
5794 bool V2Used = InputQuads[2] || InputQuads[3];
5795 if (Subtarget->hasSSSE3()) {
5796 if (InputQuads.count() == 2 && V1Used && V2Used) {
5797 BestLoQuad = InputQuads[0] ? 0 : 1;
5798 BestHiQuad = InputQuads[2] ? 2 : 3;
5800 if (InputQuads.count() > 2) {
5806 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5807 // the shuffle mask. If a quad is scored as -1, that means that it contains
5808 // words from all 4 input quadwords.
5810 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5812 BestLoQuad < 0 ? 0 : BestLoQuad,
5813 BestHiQuad < 0 ? 1 : BestHiQuad
5815 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5816 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5817 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5818 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5820 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5821 // source words for the shuffle, to aid later transformations.
5822 bool AllWordsInNewV = true;
5823 bool InOrder[2] = { true, true };
5824 for (unsigned i = 0; i != 8; ++i) {
5825 int idx = MaskVals[i];
5827 InOrder[i/4] = false;
5828 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5830 AllWordsInNewV = false;
5834 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5835 if (AllWordsInNewV) {
5836 for (int i = 0; i != 8; ++i) {
5837 int idx = MaskVals[i];
5840 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5841 if ((idx != i) && idx < 4)
5843 if ((idx != i) && idx > 3)
5852 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5853 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5854 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5855 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5856 unsigned TargetMask = 0;
5857 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5858 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5859 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5860 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5861 getShufflePSHUFLWImmediate(SVOp);
5862 V1 = NewV.getOperand(0);
5863 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5867 // Promote splats to a larger type which usually leads to more efficient code.
5868 // FIXME: Is this true if pshufb is available?
5869 if (SVOp->isSplat())
5870 return PromoteSplat(SVOp, DAG);
5872 // If we have SSSE3, and all words of the result are from 1 input vector,
5873 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5874 // is present, fall back to case 4.
5875 if (Subtarget->hasSSSE3()) {
5876 SmallVector<SDValue,16> pshufbMask;
5878 // If we have elements from both input vectors, set the high bit of the
5879 // shuffle mask element to zero out elements that come from V2 in the V1
5880 // mask, and elements that come from V1 in the V2 mask, so that the two
5881 // results can be OR'd together.
5882 bool TwoInputs = V1Used && V2Used;
5883 for (unsigned i = 0; i != 8; ++i) {
5884 int EltIdx = MaskVals[i] * 2;
5885 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5886 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5887 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5888 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5890 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5891 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5892 DAG.getNode(ISD::BUILD_VECTOR, dl,
5893 MVT::v16i8, &pshufbMask[0], 16));
5895 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5897 // Calculate the shuffle mask for the second input, shuffle it, and
5898 // OR it with the first shuffled input.
5900 for (unsigned i = 0; i != 8; ++i) {
5901 int EltIdx = MaskVals[i] * 2;
5902 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5903 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5904 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5905 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5907 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5908 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5909 DAG.getNode(ISD::BUILD_VECTOR, dl,
5910 MVT::v16i8, &pshufbMask[0], 16));
5911 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5912 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5915 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5916 // and update MaskVals with new element order.
5917 std::bitset<8> InOrder;
5918 if (BestLoQuad >= 0) {
5919 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5920 for (int i = 0; i != 4; ++i) {
5921 int idx = MaskVals[i];
5924 } else if ((idx / 4) == BestLoQuad) {
5929 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5932 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5933 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5934 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5936 getShufflePSHUFLWImmediate(SVOp), DAG);
5940 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5941 // and update MaskVals with the new element order.
5942 if (BestHiQuad >= 0) {
5943 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5944 for (unsigned i = 4; i != 8; ++i) {
5945 int idx = MaskVals[i];
5948 } else if ((idx / 4) == BestHiQuad) {
5949 MaskV[i] = (idx & 3) + 4;
5953 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5956 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5958 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5960 getShufflePSHUFHWImmediate(SVOp), DAG);
5964 // In case BestHi & BestLo were both -1, which means each quadword has a word
5965 // from each of the four input quadwords, calculate the InOrder bitvector now
5966 // before falling through to the insert/extract cleanup.
5967 if (BestLoQuad == -1 && BestHiQuad == -1) {
5969 for (int i = 0; i != 8; ++i)
5970 if (MaskVals[i] < 0 || MaskVals[i] == i)
5974 // The other elements are put in the right place using pextrw and pinsrw.
5975 for (unsigned i = 0; i != 8; ++i) {
5978 int EltIdx = MaskVals[i];
5981 SDValue ExtOp = (EltIdx < 8) ?
5982 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5983 DAG.getIntPtrConstant(EltIdx)) :
5984 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5985 DAG.getIntPtrConstant(EltIdx - 8));
5986 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5987 DAG.getIntPtrConstant(i));
5992 // v16i8 shuffles - Prefer shuffles in the following order:
5993 // 1. [ssse3] 1 x pshufb
5994 // 2. [ssse3] 2 x pshufb + 1 x por
5995 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5997 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5999 const X86TargetLowering &TLI) {
6000 SDValue V1 = SVOp->getOperand(0);
6001 SDValue V2 = SVOp->getOperand(1);
6002 DebugLoc dl = SVOp->getDebugLoc();
6003 ArrayRef<int> MaskVals = SVOp->getMask();
6005 // Promote splats to a larger type which usually leads to more efficient code.
6006 // FIXME: Is this true if pshufb is available?
6007 if (SVOp->isSplat())
6008 return PromoteSplat(SVOp, DAG);
6010 // If we have SSSE3, case 1 is generated when all result bytes come from
6011 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6012 // present, fall back to case 3.
6014 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6015 if (TLI.getSubtarget()->hasSSSE3()) {
6016 SmallVector<SDValue,16> pshufbMask;
6018 // If all result elements are from one input vector, then only translate
6019 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6021 // Otherwise, we have elements from both input vectors, and must zero out
6022 // elements that come from V2 in the first mask, and V1 in the second mask
6023 // so that we can OR them together.
6024 for (unsigned i = 0; i != 16; ++i) {
6025 int EltIdx = MaskVals[i];
6026 if (EltIdx < 0 || EltIdx >= 16)
6028 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6030 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6031 DAG.getNode(ISD::BUILD_VECTOR, dl,
6032 MVT::v16i8, &pshufbMask[0], 16));
6034 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6035 // the 2nd operand if it's undefined or zero.
6036 if (V2.getOpcode() == ISD::UNDEF ||
6037 ISD::isBuildVectorAllZeros(V2.getNode()))
6040 // Calculate the shuffle mask for the second input, shuffle it, and
6041 // OR it with the first shuffled input.
6043 for (unsigned i = 0; i != 16; ++i) {
6044 int EltIdx = MaskVals[i];
6045 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6046 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6048 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6049 DAG.getNode(ISD::BUILD_VECTOR, dl,
6050 MVT::v16i8, &pshufbMask[0], 16));
6051 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6054 // No SSSE3 - Calculate in place words and then fix all out of place words
6055 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6056 // the 16 different words that comprise the two doublequadword input vectors.
6057 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6058 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6060 for (int i = 0; i != 8; ++i) {
6061 int Elt0 = MaskVals[i*2];
6062 int Elt1 = MaskVals[i*2+1];
6064 // This word of the result is all undef, skip it.
6065 if (Elt0 < 0 && Elt1 < 0)
6068 // This word of the result is already in the correct place, skip it.
6069 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6072 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6073 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6076 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6077 // using a single extract together, load it and store it.
6078 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6079 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6080 DAG.getIntPtrConstant(Elt1 / 2));
6081 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6082 DAG.getIntPtrConstant(i));
6086 // If Elt1 is defined, extract it from the appropriate source. If the
6087 // source byte is not also odd, shift the extracted word left 8 bits
6088 // otherwise clear the bottom 8 bits if we need to do an or.
6090 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6091 DAG.getIntPtrConstant(Elt1 / 2));
6092 if ((Elt1 & 1) == 0)
6093 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6095 TLI.getShiftAmountTy(InsElt.getValueType())));
6097 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6098 DAG.getConstant(0xFF00, MVT::i16));
6100 // If Elt0 is defined, extract it from the appropriate source. If the
6101 // source byte is not also even, shift the extracted word right 8 bits. If
6102 // Elt1 was also defined, OR the extracted values together before
6103 // inserting them in the result.
6105 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6106 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6107 if ((Elt0 & 1) != 0)
6108 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6110 TLI.getShiftAmountTy(InsElt0.getValueType())));
6112 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6113 DAG.getConstant(0x00FF, MVT::i16));
6114 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6117 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6118 DAG.getIntPtrConstant(i));
6120 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6123 // v32i8 shuffles - Translate to VPSHUFB if possible.
6125 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6126 const X86Subtarget *Subtarget,
6127 SelectionDAG &DAG) {
6128 MVT VT = SVOp->getValueType(0).getSimpleVT();
6129 SDValue V1 = SVOp->getOperand(0);
6130 SDValue V2 = SVOp->getOperand(1);
6131 DebugLoc dl = SVOp->getDebugLoc();
6132 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6134 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6135 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6136 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6138 // VPSHUFB may be generated if
6139 // (1) one of input vector is undefined or zeroinitializer.
6140 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6141 // And (2) the mask indexes don't cross the 128-bit lane.
6142 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6143 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6146 if (V1IsAllZero && !V2IsAllZero) {
6147 CommuteVectorShuffleMask(MaskVals, 32);
6150 SmallVector<SDValue, 32> pshufbMask;
6151 for (unsigned i = 0; i != 32; i++) {
6152 int EltIdx = MaskVals[i];
6153 if (EltIdx < 0 || EltIdx >= 32)
6156 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6157 // Cross lane is not allowed.
6161 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6163 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6164 DAG.getNode(ISD::BUILD_VECTOR, dl,
6165 MVT::v32i8, &pshufbMask[0], 32));
6168 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6169 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6170 /// done when every pair / quad of shuffle mask elements point to elements in
6171 /// the right sequence. e.g.
6172 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6174 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6175 SelectionDAG &DAG) {
6176 MVT VT = SVOp->getValueType(0).getSimpleVT();
6177 DebugLoc dl = SVOp->getDebugLoc();
6178 unsigned NumElems = VT.getVectorNumElements();
6181 switch (VT.SimpleTy) {
6182 default: llvm_unreachable("Unexpected!");
6183 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6184 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6185 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6186 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6187 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6188 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6191 SmallVector<int, 8> MaskVec;
6192 for (unsigned i = 0; i != NumElems; i += Scale) {
6194 for (unsigned j = 0; j != Scale; ++j) {
6195 int EltIdx = SVOp->getMaskElt(i+j);
6199 StartIdx = (EltIdx / Scale);
6200 if (EltIdx != (int)(StartIdx*Scale + j))
6203 MaskVec.push_back(StartIdx);
6206 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6207 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6208 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6211 /// getVZextMovL - Return a zero-extending vector move low node.
6213 static SDValue getVZextMovL(MVT VT, EVT OpVT,
6214 SDValue SrcOp, SelectionDAG &DAG,
6215 const X86Subtarget *Subtarget, DebugLoc dl) {
6216 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6217 LoadSDNode *LD = NULL;
6218 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6219 LD = dyn_cast<LoadSDNode>(SrcOp);
6221 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6223 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6224 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6225 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6226 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6227 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6229 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6230 return DAG.getNode(ISD::BITCAST, dl, VT,
6231 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6232 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6240 return DAG.getNode(ISD::BITCAST, dl, VT,
6241 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6242 DAG.getNode(ISD::BITCAST, dl,
6246 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6247 /// which could not be matched by any known target speficic shuffle
6249 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6251 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6252 if (NewOp.getNode())
6255 MVT VT = SVOp->getValueType(0).getSimpleVT();
6257 unsigned NumElems = VT.getVectorNumElements();
6258 unsigned NumLaneElems = NumElems / 2;
6260 DebugLoc dl = SVOp->getDebugLoc();
6261 MVT EltVT = VT.getVectorElementType();
6262 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6265 SmallVector<int, 16> Mask;
6266 for (unsigned l = 0; l < 2; ++l) {
6267 // Build a shuffle mask for the output, discovering on the fly which
6268 // input vectors to use as shuffle operands (recorded in InputUsed).
6269 // If building a suitable shuffle vector proves too hard, then bail
6270 // out with UseBuildVector set.
6271 bool UseBuildVector = false;
6272 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6273 unsigned LaneStart = l * NumLaneElems;
6274 for (unsigned i = 0; i != NumLaneElems; ++i) {
6275 // The mask element. This indexes into the input.
6276 int Idx = SVOp->getMaskElt(i+LaneStart);
6278 // the mask element does not index into any input vector.
6283 // The input vector this mask element indexes into.
6284 int Input = Idx / NumLaneElems;
6286 // Turn the index into an offset from the start of the input vector.
6287 Idx -= Input * NumLaneElems;
6289 // Find or create a shuffle vector operand to hold this input.
6291 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6292 if (InputUsed[OpNo] == Input)
6293 // This input vector is already an operand.
6295 if (InputUsed[OpNo] < 0) {
6296 // Create a new operand for this input vector.
6297 InputUsed[OpNo] = Input;
6302 if (OpNo >= array_lengthof(InputUsed)) {
6303 // More than two input vectors used! Give up on trying to create a
6304 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6305 UseBuildVector = true;
6309 // Add the mask index for the new shuffle vector.
6310 Mask.push_back(Idx + OpNo * NumLaneElems);
6313 if (UseBuildVector) {
6314 SmallVector<SDValue, 16> SVOps;
6315 for (unsigned i = 0; i != NumLaneElems; ++i) {
6316 // The mask element. This indexes into the input.
6317 int Idx = SVOp->getMaskElt(i+LaneStart);
6319 SVOps.push_back(DAG.getUNDEF(EltVT));
6323 // The input vector this mask element indexes into.
6324 int Input = Idx / NumElems;
6326 // Turn the index into an offset from the start of the input vector.
6327 Idx -= Input * NumElems;
6329 // Extract the vector element by hand.
6330 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6331 SVOp->getOperand(Input),
6332 DAG.getIntPtrConstant(Idx)));
6335 // Construct the output using a BUILD_VECTOR.
6336 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6338 } else if (InputUsed[0] < 0) {
6339 // No input vectors were used! The result is undefined.
6340 Output[l] = DAG.getUNDEF(NVT);
6342 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6343 (InputUsed[0] % 2) * NumLaneElems,
6345 // If only one input was used, use an undefined vector for the other.
6346 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6347 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6348 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6349 // At least one input vector was used. Create a new shuffle vector.
6350 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6356 // Concatenate the result back
6357 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6360 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6361 /// 4 elements, and match them with several different shuffle types.
6363 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6364 SDValue V1 = SVOp->getOperand(0);
6365 SDValue V2 = SVOp->getOperand(1);
6366 DebugLoc dl = SVOp->getDebugLoc();
6367 MVT VT = SVOp->getValueType(0).getSimpleVT();
6369 assert(VT.is128BitVector() && "Unsupported vector size");
6371 std::pair<int, int> Locs[4];
6372 int Mask1[] = { -1, -1, -1, -1 };
6373 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6377 for (unsigned i = 0; i != 4; ++i) {
6378 int Idx = PermMask[i];
6380 Locs[i] = std::make_pair(-1, -1);
6382 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6384 Locs[i] = std::make_pair(0, NumLo);
6388 Locs[i] = std::make_pair(1, NumHi);
6390 Mask1[2+NumHi] = Idx;
6396 if (NumLo <= 2 && NumHi <= 2) {
6397 // If no more than two elements come from either vector. This can be
6398 // implemented with two shuffles. First shuffle gather the elements.
6399 // The second shuffle, which takes the first shuffle as both of its
6400 // vector operands, put the elements into the right order.
6401 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6403 int Mask2[] = { -1, -1, -1, -1 };
6405 for (unsigned i = 0; i != 4; ++i)
6406 if (Locs[i].first != -1) {
6407 unsigned Idx = (i < 2) ? 0 : 4;
6408 Idx += Locs[i].first * 2 + Locs[i].second;
6412 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6415 if (NumLo == 3 || NumHi == 3) {
6416 // Otherwise, we must have three elements from one vector, call it X, and
6417 // one element from the other, call it Y. First, use a shufps to build an
6418 // intermediate vector with the one element from Y and the element from X
6419 // that will be in the same half in the final destination (the indexes don't
6420 // matter). Then, use a shufps to build the final vector, taking the half
6421 // containing the element from Y from the intermediate, and the other half
6424 // Normalize it so the 3 elements come from V1.
6425 CommuteVectorShuffleMask(PermMask, 4);
6429 // Find the element from V2.
6431 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6432 int Val = PermMask[HiIndex];
6439 Mask1[0] = PermMask[HiIndex];
6441 Mask1[2] = PermMask[HiIndex^1];
6443 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6446 Mask1[0] = PermMask[0];
6447 Mask1[1] = PermMask[1];
6448 Mask1[2] = HiIndex & 1 ? 6 : 4;
6449 Mask1[3] = HiIndex & 1 ? 4 : 6;
6450 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6453 Mask1[0] = HiIndex & 1 ? 2 : 0;
6454 Mask1[1] = HiIndex & 1 ? 0 : 2;
6455 Mask1[2] = PermMask[2];
6456 Mask1[3] = PermMask[3];
6461 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6464 // Break it into (shuffle shuffle_hi, shuffle_lo).
6465 int LoMask[] = { -1, -1, -1, -1 };
6466 int HiMask[] = { -1, -1, -1, -1 };
6468 int *MaskPtr = LoMask;
6469 unsigned MaskIdx = 0;
6472 for (unsigned i = 0; i != 4; ++i) {
6479 int Idx = PermMask[i];
6481 Locs[i] = std::make_pair(-1, -1);
6482 } else if (Idx < 4) {
6483 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6484 MaskPtr[LoIdx] = Idx;
6487 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6488 MaskPtr[HiIdx] = Idx;
6493 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6494 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6495 int MaskOps[] = { -1, -1, -1, -1 };
6496 for (unsigned i = 0; i != 4; ++i)
6497 if (Locs[i].first != -1)
6498 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6499 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6502 static bool MayFoldVectorLoad(SDValue V) {
6503 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6504 V = V.getOperand(0);
6506 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6507 V = V.getOperand(0);
6508 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6509 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6510 // BUILD_VECTOR (load), undef
6511 V = V.getOperand(0);
6513 return MayFoldLoad(V);
6517 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6518 EVT VT = Op.getValueType();
6520 // Canonizalize to v2f64.
6521 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6522 return DAG.getNode(ISD::BITCAST, dl, VT,
6523 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6528 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6530 SDValue V1 = Op.getOperand(0);
6531 SDValue V2 = Op.getOperand(1);
6532 EVT VT = Op.getValueType();
6534 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6536 if (HasSSE2 && VT == MVT::v2f64)
6537 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6539 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6540 return DAG.getNode(ISD::BITCAST, dl, VT,
6541 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6542 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6543 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6547 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6548 SDValue V1 = Op.getOperand(0);
6549 SDValue V2 = Op.getOperand(1);
6550 EVT VT = Op.getValueType();
6552 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6553 "unsupported shuffle type");
6555 if (V2.getOpcode() == ISD::UNDEF)
6559 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6563 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6564 SDValue V1 = Op.getOperand(0);
6565 SDValue V2 = Op.getOperand(1);
6566 EVT VT = Op.getValueType();
6567 unsigned NumElems = VT.getVectorNumElements();
6569 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6570 // operand of these instructions is only memory, so check if there's a
6571 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6573 bool CanFoldLoad = false;
6575 // Trivial case, when V2 comes from a load.
6576 if (MayFoldVectorLoad(V2))
6579 // When V1 is a load, it can be folded later into a store in isel, example:
6580 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6582 // (MOVLPSmr addr:$src1, VR128:$src2)
6583 // So, recognize this potential and also use MOVLPS or MOVLPD
6584 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6587 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6589 if (HasSSE2 && NumElems == 2)
6590 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6593 // If we don't care about the second element, proceed to use movss.
6594 if (SVOp->getMaskElt(1) != -1)
6595 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6598 // movl and movlp will both match v2i64, but v2i64 is never matched by
6599 // movl earlier because we make it strict to avoid messing with the movlp load
6600 // folding logic (see the code above getMOVLP call). Match it here then,
6601 // this is horrible, but will stay like this until we move all shuffle
6602 // matching to x86 specific nodes. Note that for the 1st condition all
6603 // types are matched with movsd.
6605 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6606 // as to remove this logic from here, as much as possible
6607 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6608 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6609 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6612 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6614 // Invert the operand order and use SHUFPS to match it.
6615 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6616 getShuffleSHUFImmediate(SVOp), DAG);
6619 // Reduce a vector shuffle to zext.
6621 X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6622 // PMOVZX is only available from SSE41.
6623 if (!Subtarget->hasSSE41())
6626 EVT VT = Op.getValueType();
6628 // Only AVX2 support 256-bit vector integer extending.
6629 if (!Subtarget->hasInt256() && VT.is256BitVector())
6632 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6633 DebugLoc DL = Op.getDebugLoc();
6634 SDValue V1 = Op.getOperand(0);
6635 SDValue V2 = Op.getOperand(1);
6636 unsigned NumElems = VT.getVectorNumElements();
6638 // Extending is an unary operation and the element type of the source vector
6639 // won't be equal to or larger than i64.
6640 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6641 VT.getVectorElementType() == MVT::i64)
6644 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6645 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6646 while ((1U << Shift) < NumElems) {
6647 if (SVOp->getMaskElt(1U << Shift) == 1)
6650 // The maximal ratio is 8, i.e. from i8 to i64.
6655 // Check the shuffle mask.
6656 unsigned Mask = (1U << Shift) - 1;
6657 for (unsigned i = 0; i != NumElems; ++i) {
6658 int EltIdx = SVOp->getMaskElt(i);
6659 if ((i & Mask) != 0 && EltIdx != -1)
6661 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6665 LLVMContext *Context = DAG.getContext();
6666 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6667 EVT NeVT = EVT::getIntegerVT(*Context, NBits);
6668 EVT NVT = EVT::getVectorVT(*Context, NeVT, NumElems >> Shift);
6670 if (!isTypeLegal(NVT))
6673 // Simplify the operand as it's prepared to be fed into shuffle.
6674 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6675 if (V1.getOpcode() == ISD::BITCAST &&
6676 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6677 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6679 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6680 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6681 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6682 ConstantSDNode *CIdx =
6683 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6684 // If it's foldable, i.e. normal load with single use, we will let code
6685 // selection to fold it. Otherwise, we will short the conversion sequence.
6686 if (CIdx && CIdx->getZExtValue() == 0 &&
6687 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
6688 if (V.getValueSizeInBits() > V1.getValueSizeInBits()) {
6689 // The "ext_vec_elt" node is wider than the result node.
6690 // In this case we should extract subvector from V.
6691 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
6692 unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits();
6693 EVT FullVT = V.getValueType();
6694 EVT SubVecVT = EVT::getVectorVT(*Context,
6695 FullVT.getVectorElementType(),
6696 FullVT.getVectorNumElements()/Ratio);
6697 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
6698 DAG.getIntPtrConstant(0));
6700 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6704 return DAG.getNode(ISD::BITCAST, DL, VT,
6705 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6709 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6710 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6711 MVT VT = Op.getValueType().getSimpleVT();
6712 DebugLoc dl = Op.getDebugLoc();
6713 SDValue V1 = Op.getOperand(0);
6714 SDValue V2 = Op.getOperand(1);
6716 if (isZeroShuffle(SVOp))
6717 return getZeroVector(VT, Subtarget, DAG, dl);
6719 // Handle splat operations
6720 if (SVOp->isSplat()) {
6721 // Use vbroadcast whenever the splat comes from a foldable load
6722 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6723 if (Broadcast.getNode())
6727 // Check integer expanding shuffles.
6728 SDValue NewOp = LowerVectorIntExtend(Op, DAG);
6729 if (NewOp.getNode())
6732 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6734 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6735 VT == MVT::v16i16 || VT == MVT::v32i8) {
6736 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6737 if (NewOp.getNode())
6738 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6739 } else if ((VT == MVT::v4i32 ||
6740 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6741 // FIXME: Figure out a cleaner way to do this.
6742 // Try to make use of movq to zero out the top part.
6743 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6744 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6745 if (NewOp.getNode()) {
6746 MVT NewVT = NewOp.getValueType().getSimpleVT();
6747 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6748 NewVT, true, false))
6749 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6750 DAG, Subtarget, dl);
6752 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6753 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6754 if (NewOp.getNode()) {
6755 MVT NewVT = NewOp.getValueType().getSimpleVT();
6756 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6757 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6758 DAG, Subtarget, dl);
6766 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6767 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6768 SDValue V1 = Op.getOperand(0);
6769 SDValue V2 = Op.getOperand(1);
6770 MVT VT = Op.getValueType().getSimpleVT();
6771 DebugLoc dl = Op.getDebugLoc();
6772 unsigned NumElems = VT.getVectorNumElements();
6773 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6774 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6775 bool V1IsSplat = false;
6776 bool V2IsSplat = false;
6777 bool HasSSE2 = Subtarget->hasSSE2();
6778 bool HasFp256 = Subtarget->hasFp256();
6779 bool HasInt256 = Subtarget->hasInt256();
6780 MachineFunction &MF = DAG.getMachineFunction();
6781 bool OptForSize = MF.getFunction()->getAttributes().
6782 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6784 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6786 if (V1IsUndef && V2IsUndef)
6787 return DAG.getUNDEF(VT);
6789 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6791 // Vector shuffle lowering takes 3 steps:
6793 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6794 // narrowing and commutation of operands should be handled.
6795 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6797 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6798 // so the shuffle can be broken into other shuffles and the legalizer can
6799 // try the lowering again.
6801 // The general idea is that no vector_shuffle operation should be left to
6802 // be matched during isel, all of them must be converted to a target specific
6805 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6806 // narrowing and commutation of operands should be handled. The actual code
6807 // doesn't include all of those, work in progress...
6808 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6809 if (NewOp.getNode())
6812 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6814 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6815 // unpckh_undef). Only use pshufd if speed is more important than size.
6816 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6817 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6818 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6819 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6821 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6822 V2IsUndef && MayFoldVectorLoad(V1))
6823 return getMOVDDup(Op, dl, V1, DAG);
6825 if (isMOVHLPS_v_undef_Mask(M, VT))
6826 return getMOVHighToLow(Op, dl, DAG);
6828 // Use to match splats
6829 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
6830 (VT == MVT::v2f64 || VT == MVT::v2i64))
6831 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6833 if (isPSHUFDMask(M, VT)) {
6834 // The actual implementation will match the mask in the if above and then
6835 // during isel it can match several different instructions, not only pshufd
6836 // as its name says, sad but true, emulate the behavior for now...
6837 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6838 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6840 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6842 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6843 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6845 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6846 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
6849 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6853 // Check if this can be converted into a logical shift.
6854 bool isLeft = false;
6857 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6858 if (isShift && ShVal.hasOneUse()) {
6859 // If the shifted value has multiple uses, it may be cheaper to use
6860 // v_set0 + movlhps or movhlps, etc.
6861 MVT EltVT = VT.getVectorElementType();
6862 ShAmt *= EltVT.getSizeInBits();
6863 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6866 if (isMOVLMask(M, VT)) {
6867 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6868 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6869 if (!isMOVLPMask(M, VT)) {
6870 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6871 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6873 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6874 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6878 // FIXME: fold these into legal mask.
6879 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
6880 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6882 if (isMOVHLPSMask(M, VT))
6883 return getMOVHighToLow(Op, dl, DAG);
6885 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6886 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6888 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6889 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6891 if (isMOVLPMask(M, VT))
6892 return getMOVLP(Op, dl, DAG, HasSSE2);
6894 if (ShouldXformToMOVHLPS(M, VT) ||
6895 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6896 return CommuteVectorShuffle(SVOp, DAG);
6899 // No better options. Use a vshldq / vsrldq.
6900 MVT EltVT = VT.getVectorElementType();
6901 ShAmt *= EltVT.getSizeInBits();
6902 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6905 bool Commuted = false;
6906 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6907 // 1,1,1,1 -> v8i16 though.
6908 V1IsSplat = isSplatVector(V1.getNode());
6909 V2IsSplat = isSplatVector(V2.getNode());
6911 // Canonicalize the splat or undef, if present, to be on the RHS.
6912 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6913 CommuteVectorShuffleMask(M, NumElems);
6915 std::swap(V1IsSplat, V2IsSplat);
6919 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6920 // Shuffling low element of v1 into undef, just return v1.
6923 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6924 // the instruction selector will not match, so get a canonical MOVL with
6925 // swapped operands to undo the commute.
6926 return getMOVL(DAG, dl, VT, V2, V1);
6929 if (isUNPCKLMask(M, VT, HasInt256))
6930 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6932 if (isUNPCKHMask(M, VT, HasInt256))
6933 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6936 // Normalize mask so all entries that point to V2 points to its first
6937 // element then try to match unpck{h|l} again. If match, return a
6938 // new vector_shuffle with the corrected mask.p
6939 SmallVector<int, 8> NewMask(M.begin(), M.end());
6940 NormalizeMask(NewMask, NumElems);
6941 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
6942 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6943 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
6944 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6948 // Commute is back and try unpck* again.
6949 // FIXME: this seems wrong.
6950 CommuteVectorShuffleMask(M, NumElems);
6952 std::swap(V1IsSplat, V2IsSplat);
6955 if (isUNPCKLMask(M, VT, HasInt256))
6956 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6958 if (isUNPCKHMask(M, VT, HasInt256))
6959 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6962 // Normalize the node to match x86 shuffle ops if needed
6963 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
6964 return CommuteVectorShuffle(SVOp, DAG);
6966 // The checks below are all present in isShuffleMaskLegal, but they are
6967 // inlined here right now to enable us to directly emit target specific
6968 // nodes, and remove one by one until they don't return Op anymore.
6970 if (isPALIGNRMask(M, VT, Subtarget))
6971 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
6972 getShufflePALIGNRImmediate(SVOp),
6975 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6976 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6977 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6978 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6981 if (isPSHUFHWMask(M, VT, HasInt256))
6982 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6983 getShufflePSHUFHWImmediate(SVOp),
6986 if (isPSHUFLWMask(M, VT, HasInt256))
6987 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6988 getShufflePSHUFLWImmediate(SVOp),
6991 if (isSHUFPMask(M, VT, HasFp256))
6992 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6993 getShuffleSHUFImmediate(SVOp), DAG);
6995 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6996 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6997 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6998 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7000 //===--------------------------------------------------------------------===//
7001 // Generate target specific nodes for 128 or 256-bit shuffles only
7002 // supported in the AVX instruction set.
7005 // Handle VMOVDDUPY permutations
7006 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7007 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7009 // Handle VPERMILPS/D* permutations
7010 if (isVPERMILPMask(M, VT, HasFp256)) {
7011 if (HasInt256 && VT == MVT::v8i32)
7012 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7013 getShuffleSHUFImmediate(SVOp), DAG);
7014 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7015 getShuffleSHUFImmediate(SVOp), DAG);
7018 // Handle VPERM2F128/VPERM2I128 permutations
7019 if (isVPERM2X128Mask(M, VT, HasFp256))
7020 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7021 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7023 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7024 if (BlendOp.getNode())
7027 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
7028 SmallVector<SDValue, 8> permclMask;
7029 for (unsigned i = 0; i != 8; ++i) {
7030 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
7032 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
7034 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7035 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7036 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7039 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
7040 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
7041 getShuffleCLImmediate(SVOp), DAG);
7043 //===--------------------------------------------------------------------===//
7044 // Since no target specific shuffle was selected for this generic one,
7045 // lower it into other known shuffles. FIXME: this isn't true yet, but
7046 // this is the plan.
7049 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7050 if (VT == MVT::v8i16) {
7051 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7052 if (NewOp.getNode())
7056 if (VT == MVT::v16i8) {
7057 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7058 if (NewOp.getNode())
7062 if (VT == MVT::v32i8) {
7063 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7064 if (NewOp.getNode())
7068 // Handle all 128-bit wide vectors with 4 elements, and match them with
7069 // several different shuffle types.
7070 if (NumElems == 4 && VT.is128BitVector())
7071 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7073 // Handle general 256-bit shuffles
7074 if (VT.is256BitVector())
7075 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7080 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7081 MVT VT = Op.getValueType().getSimpleVT();
7082 DebugLoc dl = Op.getDebugLoc();
7084 if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector())
7087 if (VT.getSizeInBits() == 8) {
7088 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7089 Op.getOperand(0), Op.getOperand(1));
7090 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7091 DAG.getValueType(VT));
7092 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7095 if (VT.getSizeInBits() == 16) {
7096 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7097 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7099 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7100 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7101 DAG.getNode(ISD::BITCAST, dl,
7105 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7106 Op.getOperand(0), Op.getOperand(1));
7107 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7108 DAG.getValueType(VT));
7109 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7112 if (VT == MVT::f32) {
7113 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7114 // the result back to FR32 register. It's only worth matching if the
7115 // result has a single use which is a store or a bitcast to i32. And in
7116 // the case of a store, it's not worth it if the index is a constant 0,
7117 // because a MOVSSmr can be used instead, which is smaller and faster.
7118 if (!Op.hasOneUse())
7120 SDNode *User = *Op.getNode()->use_begin();
7121 if ((User->getOpcode() != ISD::STORE ||
7122 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7123 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7124 (User->getOpcode() != ISD::BITCAST ||
7125 User->getValueType(0) != MVT::i32))
7127 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7128 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7131 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7134 if (VT == MVT::i32 || VT == MVT::i64) {
7135 // ExtractPS/pextrq works with constant index.
7136 if (isa<ConstantSDNode>(Op.getOperand(1)))
7143 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7144 SelectionDAG &DAG) const {
7145 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7148 SDValue Vec = Op.getOperand(0);
7149 MVT VecVT = Vec.getValueType().getSimpleVT();
7151 // If this is a 256-bit vector result, first extract the 128-bit vector and
7152 // then extract the element from the 128-bit vector.
7153 if (VecVT.is256BitVector()) {
7154 DebugLoc dl = Op.getNode()->getDebugLoc();
7155 unsigned NumElems = VecVT.getVectorNumElements();
7156 SDValue Idx = Op.getOperand(1);
7157 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7159 // Get the 128-bit vector.
7160 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7162 if (IdxVal >= NumElems/2)
7163 IdxVal -= NumElems/2;
7164 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7165 DAG.getConstant(IdxVal, MVT::i32));
7168 assert(VecVT.is128BitVector() && "Unexpected vector length");
7170 if (Subtarget->hasSSE41()) {
7171 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7176 MVT VT = Op.getValueType().getSimpleVT();
7177 DebugLoc dl = Op.getDebugLoc();
7178 // TODO: handle v16i8.
7179 if (VT.getSizeInBits() == 16) {
7180 SDValue Vec = Op.getOperand(0);
7181 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7183 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7184 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7185 DAG.getNode(ISD::BITCAST, dl,
7188 // Transform it so it match pextrw which produces a 32-bit result.
7189 MVT EltVT = MVT::i32;
7190 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7191 Op.getOperand(0), Op.getOperand(1));
7192 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7193 DAG.getValueType(VT));
7194 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7197 if (VT.getSizeInBits() == 32) {
7198 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7202 // SHUFPS the element to the lowest double word, then movss.
7203 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7204 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7205 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7206 DAG.getUNDEF(VVT), Mask);
7207 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7208 DAG.getIntPtrConstant(0));
7211 if (VT.getSizeInBits() == 64) {
7212 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7213 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7214 // to match extract_elt for f64.
7215 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7219 // UNPCKHPD the element to the lowest double word, then movsd.
7220 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7221 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7222 int Mask[2] = { 1, -1 };
7223 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7224 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7225 DAG.getUNDEF(VVT), Mask);
7226 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7227 DAG.getIntPtrConstant(0));
7233 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7234 MVT VT = Op.getValueType().getSimpleVT();
7235 MVT EltVT = VT.getVectorElementType();
7236 DebugLoc dl = Op.getDebugLoc();
7238 SDValue N0 = Op.getOperand(0);
7239 SDValue N1 = Op.getOperand(1);
7240 SDValue N2 = Op.getOperand(2);
7242 if (!VT.is128BitVector())
7245 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7246 isa<ConstantSDNode>(N2)) {
7248 if (VT == MVT::v8i16)
7249 Opc = X86ISD::PINSRW;
7250 else if (VT == MVT::v16i8)
7251 Opc = X86ISD::PINSRB;
7253 Opc = X86ISD::PINSRB;
7255 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7257 if (N1.getValueType() != MVT::i32)
7258 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7259 if (N2.getValueType() != MVT::i32)
7260 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7261 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7264 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7265 // Bits [7:6] of the constant are the source select. This will always be
7266 // zero here. The DAG Combiner may combine an extract_elt index into these
7267 // bits. For example (insert (extract, 3), 2) could be matched by putting
7268 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7269 // Bits [5:4] of the constant are the destination select. This is the
7270 // value of the incoming immediate.
7271 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7272 // combine either bitwise AND or insert of float 0.0 to set these bits.
7273 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7274 // Create this as a scalar to vector..
7275 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7276 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7279 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7280 // PINSR* works with constant index.
7287 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7288 MVT VT = Op.getValueType().getSimpleVT();
7289 MVT EltVT = VT.getVectorElementType();
7291 DebugLoc dl = Op.getDebugLoc();
7292 SDValue N0 = Op.getOperand(0);
7293 SDValue N1 = Op.getOperand(1);
7294 SDValue N2 = Op.getOperand(2);
7296 // If this is a 256-bit vector result, first extract the 128-bit vector,
7297 // insert the element into the extracted half and then place it back.
7298 if (VT.is256BitVector()) {
7299 if (!isa<ConstantSDNode>(N2))
7302 // Get the desired 128-bit vector half.
7303 unsigned NumElems = VT.getVectorNumElements();
7304 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7305 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7307 // Insert the element into the desired half.
7308 bool Upper = IdxVal >= NumElems/2;
7309 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7310 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7312 // Insert the changed part back to the 256-bit vector
7313 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7316 if (Subtarget->hasSSE41())
7317 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7319 if (EltVT == MVT::i8)
7322 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7323 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7324 // as its second argument.
7325 if (N1.getValueType() != MVT::i32)
7326 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7327 if (N2.getValueType() != MVT::i32)
7328 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7329 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7334 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7335 LLVMContext *Context = DAG.getContext();
7336 DebugLoc dl = Op.getDebugLoc();
7337 MVT OpVT = Op.getValueType().getSimpleVT();
7339 // If this is a 256-bit vector result, first insert into a 128-bit
7340 // vector and then insert into the 256-bit vector.
7341 if (!OpVT.is128BitVector()) {
7342 // Insert into a 128-bit vector.
7343 EVT VT128 = EVT::getVectorVT(*Context,
7344 OpVT.getVectorElementType(),
7345 OpVT.getVectorNumElements() / 2);
7347 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7349 // Insert the 128-bit vector.
7350 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7353 if (OpVT == MVT::v1i64 &&
7354 Op.getOperand(0).getValueType() == MVT::i64)
7355 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7357 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7358 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7359 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7360 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7363 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7364 // a simple subregister reference or explicit instructions to grab
7365 // upper bits of a vector.
7366 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7367 SelectionDAG &DAG) {
7368 if (Subtarget->hasFp256()) {
7369 DebugLoc dl = Op.getNode()->getDebugLoc();
7370 SDValue Vec = Op.getNode()->getOperand(0);
7371 SDValue Idx = Op.getNode()->getOperand(1);
7373 if (Op.getNode()->getValueType(0).is128BitVector() &&
7374 Vec.getNode()->getValueType(0).is256BitVector() &&
7375 isa<ConstantSDNode>(Idx)) {
7376 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7377 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7383 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7384 // simple superregister reference or explicit instructions to insert
7385 // the upper bits of a vector.
7386 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7387 SelectionDAG &DAG) {
7388 if (Subtarget->hasFp256()) {
7389 DebugLoc dl = Op.getNode()->getDebugLoc();
7390 SDValue Vec = Op.getNode()->getOperand(0);
7391 SDValue SubVec = Op.getNode()->getOperand(1);
7392 SDValue Idx = Op.getNode()->getOperand(2);
7394 if (Op.getNode()->getValueType(0).is256BitVector() &&
7395 SubVec.getNode()->getValueType(0).is128BitVector() &&
7396 isa<ConstantSDNode>(Idx)) {
7397 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7398 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7404 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7405 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7406 // one of the above mentioned nodes. It has to be wrapped because otherwise
7407 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7408 // be used to form addressing mode. These wrapped nodes will be selected
7411 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7412 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7414 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7416 unsigned char OpFlag = 0;
7417 unsigned WrapperKind = X86ISD::Wrapper;
7418 CodeModel::Model M = getTargetMachine().getCodeModel();
7420 if (Subtarget->isPICStyleRIPRel() &&
7421 (M == CodeModel::Small || M == CodeModel::Kernel))
7422 WrapperKind = X86ISD::WrapperRIP;
7423 else if (Subtarget->isPICStyleGOT())
7424 OpFlag = X86II::MO_GOTOFF;
7425 else if (Subtarget->isPICStyleStubPIC())
7426 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7428 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7430 CP->getOffset(), OpFlag);
7431 DebugLoc DL = CP->getDebugLoc();
7432 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7433 // With PIC, the address is actually $g + Offset.
7435 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7436 DAG.getNode(X86ISD::GlobalBaseReg,
7437 DebugLoc(), getPointerTy()),
7444 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7445 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7447 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7449 unsigned char OpFlag = 0;
7450 unsigned WrapperKind = X86ISD::Wrapper;
7451 CodeModel::Model M = getTargetMachine().getCodeModel();
7453 if (Subtarget->isPICStyleRIPRel() &&
7454 (M == CodeModel::Small || M == CodeModel::Kernel))
7455 WrapperKind = X86ISD::WrapperRIP;
7456 else if (Subtarget->isPICStyleGOT())
7457 OpFlag = X86II::MO_GOTOFF;
7458 else if (Subtarget->isPICStyleStubPIC())
7459 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7461 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7463 DebugLoc DL = JT->getDebugLoc();
7464 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7466 // With PIC, the address is actually $g + Offset.
7468 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7469 DAG.getNode(X86ISD::GlobalBaseReg,
7470 DebugLoc(), getPointerTy()),
7477 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7478 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7480 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7482 unsigned char OpFlag = 0;
7483 unsigned WrapperKind = X86ISD::Wrapper;
7484 CodeModel::Model M = getTargetMachine().getCodeModel();
7486 if (Subtarget->isPICStyleRIPRel() &&
7487 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7488 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7489 OpFlag = X86II::MO_GOTPCREL;
7490 WrapperKind = X86ISD::WrapperRIP;
7491 } else if (Subtarget->isPICStyleGOT()) {
7492 OpFlag = X86II::MO_GOT;
7493 } else if (Subtarget->isPICStyleStubPIC()) {
7494 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7495 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7496 OpFlag = X86II::MO_DARWIN_NONLAZY;
7499 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7501 DebugLoc DL = Op.getDebugLoc();
7502 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7504 // With PIC, the address is actually $g + Offset.
7505 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7506 !Subtarget->is64Bit()) {
7507 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7508 DAG.getNode(X86ISD::GlobalBaseReg,
7509 DebugLoc(), getPointerTy()),
7513 // For symbols that require a load from a stub to get the address, emit the
7515 if (isGlobalStubReference(OpFlag))
7516 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7517 MachinePointerInfo::getGOT(), false, false, false, 0);
7523 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7524 // Create the TargetBlockAddressAddress node.
7525 unsigned char OpFlags =
7526 Subtarget->ClassifyBlockAddressReference();
7527 CodeModel::Model M = getTargetMachine().getCodeModel();
7528 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7529 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7530 DebugLoc dl = Op.getDebugLoc();
7531 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7534 if (Subtarget->isPICStyleRIPRel() &&
7535 (M == CodeModel::Small || M == CodeModel::Kernel))
7536 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7538 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7540 // With PIC, the address is actually $g + Offset.
7541 if (isGlobalRelativeToPICBase(OpFlags)) {
7542 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7543 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7551 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7552 int64_t Offset, SelectionDAG &DAG) const {
7553 // Create the TargetGlobalAddress node, folding in the constant
7554 // offset if it is legal.
7555 unsigned char OpFlags =
7556 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7557 CodeModel::Model M = getTargetMachine().getCodeModel();
7559 if (OpFlags == X86II::MO_NO_FLAG &&
7560 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7561 // A direct static reference to a global.
7562 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7565 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7568 if (Subtarget->isPICStyleRIPRel() &&
7569 (M == CodeModel::Small || M == CodeModel::Kernel))
7570 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7572 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7574 // With PIC, the address is actually $g + Offset.
7575 if (isGlobalRelativeToPICBase(OpFlags)) {
7576 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7577 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7581 // For globals that require a load from a stub to get the address, emit the
7583 if (isGlobalStubReference(OpFlags))
7584 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7585 MachinePointerInfo::getGOT(), false, false, false, 0);
7587 // If there was a non-zero offset that we didn't fold, create an explicit
7590 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7591 DAG.getConstant(Offset, getPointerTy()));
7597 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7598 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7599 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7600 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7604 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7605 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7606 unsigned char OperandFlags, bool LocalDynamic = false) {
7607 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7608 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7609 DebugLoc dl = GA->getDebugLoc();
7610 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7611 GA->getValueType(0),
7615 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7619 SDValue Ops[] = { Chain, TGA, *InFlag };
7620 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7622 SDValue Ops[] = { Chain, TGA };
7623 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7626 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7627 MFI->setAdjustsStack(true);
7629 SDValue Flag = Chain.getValue(1);
7630 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7633 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7635 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7638 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7639 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7640 DAG.getNode(X86ISD::GlobalBaseReg,
7641 DebugLoc(), PtrVT), InFlag);
7642 InFlag = Chain.getValue(1);
7644 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7647 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7649 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7651 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7652 X86::RAX, X86II::MO_TLSGD);
7655 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7659 DebugLoc dl = GA->getDebugLoc();
7661 // Get the start address of the TLS block for this module.
7662 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7663 .getInfo<X86MachineFunctionInfo>();
7664 MFI->incNumLocalDynamicTLSAccesses();
7668 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7669 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7672 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7673 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7674 InFlag = Chain.getValue(1);
7675 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7676 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7679 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7683 unsigned char OperandFlags = X86II::MO_DTPOFF;
7684 unsigned WrapperKind = X86ISD::Wrapper;
7685 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7686 GA->getValueType(0),
7687 GA->getOffset(), OperandFlags);
7688 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7690 // Add x@dtpoff with the base.
7691 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7694 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7695 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7696 const EVT PtrVT, TLSModel::Model model,
7697 bool is64Bit, bool isPIC) {
7698 DebugLoc dl = GA->getDebugLoc();
7700 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7701 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7702 is64Bit ? 257 : 256));
7704 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7705 DAG.getIntPtrConstant(0),
7706 MachinePointerInfo(Ptr),
7707 false, false, false, 0);
7709 unsigned char OperandFlags = 0;
7710 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7712 unsigned WrapperKind = X86ISD::Wrapper;
7713 if (model == TLSModel::LocalExec) {
7714 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7715 } else if (model == TLSModel::InitialExec) {
7717 OperandFlags = X86II::MO_GOTTPOFF;
7718 WrapperKind = X86ISD::WrapperRIP;
7720 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7723 llvm_unreachable("Unexpected model");
7726 // emit "addl x@ntpoff,%eax" (local exec)
7727 // or "addl x@indntpoff,%eax" (initial exec)
7728 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7729 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7730 GA->getValueType(0),
7731 GA->getOffset(), OperandFlags);
7732 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7734 if (model == TLSModel::InitialExec) {
7735 if (isPIC && !is64Bit) {
7736 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7737 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7741 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7742 MachinePointerInfo::getGOT(), false, false, false,
7746 // The address of the thread local variable is the add of the thread
7747 // pointer with the offset of the variable.
7748 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7752 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7754 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7755 const GlobalValue *GV = GA->getGlobal();
7757 if (Subtarget->isTargetELF()) {
7758 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7761 case TLSModel::GeneralDynamic:
7762 if (Subtarget->is64Bit())
7763 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7764 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7765 case TLSModel::LocalDynamic:
7766 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7767 Subtarget->is64Bit());
7768 case TLSModel::InitialExec:
7769 case TLSModel::LocalExec:
7770 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7771 Subtarget->is64Bit(),
7772 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7774 llvm_unreachable("Unknown TLS model.");
7777 if (Subtarget->isTargetDarwin()) {
7778 // Darwin only has one model of TLS. Lower to that.
7779 unsigned char OpFlag = 0;
7780 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7781 X86ISD::WrapperRIP : X86ISD::Wrapper;
7783 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7785 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7786 !Subtarget->is64Bit();
7788 OpFlag = X86II::MO_TLVP_PIC_BASE;
7790 OpFlag = X86II::MO_TLVP;
7791 DebugLoc DL = Op.getDebugLoc();
7792 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7793 GA->getValueType(0),
7794 GA->getOffset(), OpFlag);
7795 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7797 // With PIC32, the address is actually $g + Offset.
7799 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7800 DAG.getNode(X86ISD::GlobalBaseReg,
7801 DebugLoc(), getPointerTy()),
7804 // Lowering the machine isd will make sure everything is in the right
7806 SDValue Chain = DAG.getEntryNode();
7807 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7808 SDValue Args[] = { Chain, Offset };
7809 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7811 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7812 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7813 MFI->setAdjustsStack(true);
7815 // And our return value (tls address) is in the standard call return value
7817 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7818 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7822 if (Subtarget->isTargetWindows()) {
7823 // Just use the implicit TLS architecture
7824 // Need to generate someting similar to:
7825 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7827 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7828 // mov rcx, qword [rdx+rcx*8]
7829 // mov eax, .tls$:tlsvar
7830 // [rax+rcx] contains the address
7831 // Windows 64bit: gs:0x58
7832 // Windows 32bit: fs:__tls_array
7834 // If GV is an alias then use the aliasee for determining
7835 // thread-localness.
7836 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7837 GV = GA->resolveAliasedGlobal(false);
7838 DebugLoc dl = GA->getDebugLoc();
7839 SDValue Chain = DAG.getEntryNode();
7841 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7842 // %gs:0x58 (64-bit).
7843 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7844 ? Type::getInt8PtrTy(*DAG.getContext(),
7846 : Type::getInt32PtrTy(*DAG.getContext(),
7849 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7850 Subtarget->is64Bit()
7851 ? DAG.getIntPtrConstant(0x58)
7852 : DAG.getExternalSymbol("_tls_array",
7854 MachinePointerInfo(Ptr),
7855 false, false, false, 0);
7857 // Load the _tls_index variable
7858 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7859 if (Subtarget->is64Bit())
7860 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7861 IDX, MachinePointerInfo(), MVT::i32,
7864 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7865 false, false, false, 0);
7867 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7869 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7871 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7872 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7873 false, false, false, 0);
7875 // Get the offset of start of .tls section
7876 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7877 GA->getValueType(0),
7878 GA->getOffset(), X86II::MO_SECREL);
7879 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7881 // The address of the thread local variable is the add of the thread
7882 // pointer with the offset of the variable.
7883 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7886 llvm_unreachable("TLS not implemented for this target.");
7889 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7890 /// and take a 2 x i32 value to shift plus a shift amount.
7891 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7892 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7893 EVT VT = Op.getValueType();
7894 unsigned VTBits = VT.getSizeInBits();
7895 DebugLoc dl = Op.getDebugLoc();
7896 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7897 SDValue ShOpLo = Op.getOperand(0);
7898 SDValue ShOpHi = Op.getOperand(1);
7899 SDValue ShAmt = Op.getOperand(2);
7900 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7901 DAG.getConstant(VTBits - 1, MVT::i8))
7902 : DAG.getConstant(0, VT);
7905 if (Op.getOpcode() == ISD::SHL_PARTS) {
7906 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7907 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7909 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7910 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7913 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7914 DAG.getConstant(VTBits, MVT::i8));
7915 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7916 AndNode, DAG.getConstant(0, MVT::i8));
7919 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7920 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7921 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7923 if (Op.getOpcode() == ISD::SHL_PARTS) {
7924 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7925 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7927 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7928 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7931 SDValue Ops[2] = { Lo, Hi };
7932 return DAG.getMergeValues(Ops, 2, dl);
7935 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7936 SelectionDAG &DAG) const {
7937 EVT SrcVT = Op.getOperand(0).getValueType();
7939 if (SrcVT.isVector())
7942 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7943 "Unknown SINT_TO_FP to lower!");
7945 // These are really Legal; return the operand so the caller accepts it as
7947 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7949 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7950 Subtarget->is64Bit()) {
7954 DebugLoc dl = Op.getDebugLoc();
7955 unsigned Size = SrcVT.getSizeInBits()/8;
7956 MachineFunction &MF = DAG.getMachineFunction();
7957 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7958 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7959 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7961 MachinePointerInfo::getFixedStack(SSFI),
7963 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7966 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7968 SelectionDAG &DAG) const {
7970 DebugLoc DL = Op.getDebugLoc();
7972 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7974 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7976 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7978 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7980 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7981 MachineMemOperand *MMO;
7983 int SSFI = FI->getIndex();
7985 DAG.getMachineFunction()
7986 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7987 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7989 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7990 StackSlot = StackSlot.getOperand(1);
7992 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7993 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7995 Tys, Ops, array_lengthof(Ops),
7999 Chain = Result.getValue(1);
8000 SDValue InFlag = Result.getValue(2);
8002 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8003 // shouldn't be necessary except that RFP cannot be live across
8004 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8005 MachineFunction &MF = DAG.getMachineFunction();
8006 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8007 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8008 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8009 Tys = DAG.getVTList(MVT::Other);
8011 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8013 MachineMemOperand *MMO =
8014 DAG.getMachineFunction()
8015 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8016 MachineMemOperand::MOStore, SSFISize, SSFISize);
8018 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8019 Ops, array_lengthof(Ops),
8020 Op.getValueType(), MMO);
8021 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8022 MachinePointerInfo::getFixedStack(SSFI),
8023 false, false, false, 0);
8029 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8030 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8031 SelectionDAG &DAG) const {
8032 // This algorithm is not obvious. Here it is what we're trying to output:
8035 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8036 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8040 pshufd $0x4e, %xmm0, %xmm1
8045 DebugLoc dl = Op.getDebugLoc();
8046 LLVMContext *Context = DAG.getContext();
8048 // Build some magic constants.
8049 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8050 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8051 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8053 SmallVector<Constant*,2> CV1;
8055 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8056 APInt(64, 0x4330000000000000ULL))));
8058 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8059 APInt(64, 0x4530000000000000ULL))));
8060 Constant *C1 = ConstantVector::get(CV1);
8061 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8063 // Load the 64-bit value into an XMM register.
8064 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8066 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8067 MachinePointerInfo::getConstantPool(),
8068 false, false, false, 16);
8069 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8070 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8073 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8074 MachinePointerInfo::getConstantPool(),
8075 false, false, false, 16);
8076 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8077 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8080 if (Subtarget->hasSSE3()) {
8081 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8082 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8084 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8085 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8087 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8088 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8092 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8093 DAG.getIntPtrConstant(0));
8096 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8097 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8098 SelectionDAG &DAG) const {
8099 DebugLoc dl = Op.getDebugLoc();
8100 // FP constant to bias correct the final result.
8101 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8104 // Load the 32-bit value into an XMM register.
8105 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8108 // Zero out the upper parts of the register.
8109 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8111 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8112 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8113 DAG.getIntPtrConstant(0));
8115 // Or the load with the bias.
8116 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8117 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8118 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8120 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8121 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8122 MVT::v2f64, Bias)));
8123 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8124 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8125 DAG.getIntPtrConstant(0));
8127 // Subtract the bias.
8128 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8130 // Handle final rounding.
8131 EVT DestVT = Op.getValueType();
8133 if (DestVT.bitsLT(MVT::f64))
8134 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8135 DAG.getIntPtrConstant(0));
8136 if (DestVT.bitsGT(MVT::f64))
8137 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8139 // Handle final rounding.
8143 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8144 SelectionDAG &DAG) const {
8145 SDValue N0 = Op.getOperand(0);
8146 EVT SVT = N0.getValueType();
8147 DebugLoc dl = Op.getDebugLoc();
8149 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8150 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8151 "Custom UINT_TO_FP is not supported!");
8153 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8154 SVT.getVectorNumElements());
8155 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8156 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8159 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8160 SelectionDAG &DAG) const {
8161 SDValue N0 = Op.getOperand(0);
8162 DebugLoc dl = Op.getDebugLoc();
8164 if (Op.getValueType().isVector())
8165 return lowerUINT_TO_FP_vec(Op, DAG);
8167 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8168 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8169 // the optimization here.
8170 if (DAG.SignBitIsZero(N0))
8171 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8173 EVT SrcVT = N0.getValueType();
8174 EVT DstVT = Op.getValueType();
8175 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8176 return LowerUINT_TO_FP_i64(Op, DAG);
8177 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8178 return LowerUINT_TO_FP_i32(Op, DAG);
8179 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8182 // Make a 64-bit buffer, and use it to build an FILD.
8183 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8184 if (SrcVT == MVT::i32) {
8185 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8186 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8187 getPointerTy(), StackSlot, WordOff);
8188 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8189 StackSlot, MachinePointerInfo(),
8191 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8192 OffsetSlot, MachinePointerInfo(),
8194 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8198 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8199 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8200 StackSlot, MachinePointerInfo(),
8202 // For i64 source, we need to add the appropriate power of 2 if the input
8203 // was negative. This is the same as the optimization in
8204 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8205 // we must be careful to do the computation in x87 extended precision, not
8206 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8207 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8208 MachineMemOperand *MMO =
8209 DAG.getMachineFunction()
8210 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8211 MachineMemOperand::MOLoad, 8, 8);
8213 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8214 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8215 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
8218 APInt FF(32, 0x5F800000ULL);
8220 // Check whether the sign bit is set.
8221 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
8222 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8225 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8226 SDValue FudgePtr = DAG.getConstantPool(
8227 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8230 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8231 SDValue Zero = DAG.getIntPtrConstant(0);
8232 SDValue Four = DAG.getIntPtrConstant(4);
8233 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8235 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8237 // Load the value out, extending it from f32 to f80.
8238 // FIXME: Avoid the extend by constructing the right constant pool?
8239 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8240 FudgePtr, MachinePointerInfo::getConstantPool(),
8241 MVT::f32, false, false, 4);
8242 // Extend everything to 80 bits to force it to be done on x87.
8243 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8244 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8247 std::pair<SDValue,SDValue>
8248 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8249 bool IsSigned, bool IsReplace) const {
8250 DebugLoc DL = Op.getDebugLoc();
8252 EVT DstTy = Op.getValueType();
8254 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8255 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8259 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8260 DstTy.getSimpleVT() >= MVT::i16 &&
8261 "Unknown FP_TO_INT to lower!");
8263 // These are really Legal.
8264 if (DstTy == MVT::i32 &&
8265 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8266 return std::make_pair(SDValue(), SDValue());
8267 if (Subtarget->is64Bit() &&
8268 DstTy == MVT::i64 &&
8269 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8270 return std::make_pair(SDValue(), SDValue());
8272 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8273 // stack slot, or into the FTOL runtime function.
8274 MachineFunction &MF = DAG.getMachineFunction();
8275 unsigned MemSize = DstTy.getSizeInBits()/8;
8276 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8277 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8280 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8281 Opc = X86ISD::WIN_FTOL;
8283 switch (DstTy.getSimpleVT().SimpleTy) {
8284 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8285 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8286 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8287 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8290 SDValue Chain = DAG.getEntryNode();
8291 SDValue Value = Op.getOperand(0);
8292 EVT TheVT = Op.getOperand(0).getValueType();
8293 // FIXME This causes a redundant load/store if the SSE-class value is already
8294 // in memory, such as if it is on the callstack.
8295 if (isScalarFPTypeInSSEReg(TheVT)) {
8296 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8297 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8298 MachinePointerInfo::getFixedStack(SSFI),
8300 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8302 Chain, StackSlot, DAG.getValueType(TheVT)
8305 MachineMemOperand *MMO =
8306 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8307 MachineMemOperand::MOLoad, MemSize, MemSize);
8308 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8310 Chain = Value.getValue(1);
8311 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8312 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8315 MachineMemOperand *MMO =
8316 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8317 MachineMemOperand::MOStore, MemSize, MemSize);
8319 if (Opc != X86ISD::WIN_FTOL) {
8320 // Build the FP_TO_INT*_IN_MEM
8321 SDValue Ops[] = { Chain, Value, StackSlot };
8322 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8323 Ops, 3, DstTy, MMO);
8324 return std::make_pair(FIST, StackSlot);
8326 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8327 DAG.getVTList(MVT::Other, MVT::Glue),
8329 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8330 MVT::i32, ftol.getValue(1));
8331 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8332 MVT::i32, eax.getValue(2));
8333 SDValue Ops[] = { eax, edx };
8334 SDValue pair = IsReplace
8335 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8336 : DAG.getMergeValues(Ops, 2, DL);
8337 return std::make_pair(pair, SDValue());
8341 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8342 const X86Subtarget *Subtarget) {
8343 MVT VT = Op->getValueType(0).getSimpleVT();
8344 SDValue In = Op->getOperand(0);
8345 MVT InVT = In.getValueType().getSimpleVT();
8346 DebugLoc dl = Op->getDebugLoc();
8348 // Optimize vectors in AVX mode:
8351 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8352 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8353 // Concat upper and lower parts.
8356 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8357 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8358 // Concat upper and lower parts.
8361 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8362 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8365 if (Subtarget->hasInt256())
8366 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8368 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8369 SDValue Undef = DAG.getUNDEF(InVT);
8370 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8371 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8372 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8374 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8375 VT.getVectorNumElements()/2);
8377 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8378 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8380 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8383 SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
8384 SelectionDAG &DAG) const {
8385 if (Subtarget->hasFp256()) {
8386 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8393 SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
8394 SelectionDAG &DAG) const {
8395 DebugLoc DL = Op.getDebugLoc();
8396 MVT VT = Op.getValueType().getSimpleVT();
8397 SDValue In = Op.getOperand(0);
8398 MVT SVT = In.getValueType().getSimpleVT();
8400 if (Subtarget->hasFp256()) {
8401 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8406 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8407 VT.getVectorNumElements() != SVT.getVectorNumElements())
8410 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8412 // AVX2 has better support of integer extending.
8413 if (Subtarget->hasInt256())
8414 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8416 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8417 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8418 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8419 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8420 DAG.getUNDEF(MVT::v8i16),
8423 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8426 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8427 DebugLoc DL = Op.getDebugLoc();
8428 MVT VT = Op.getValueType().getSimpleVT();
8429 SDValue In = Op.getOperand(0);
8430 MVT SVT = In.getValueType().getSimpleVT();
8432 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8433 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8434 if (Subtarget->hasInt256()) {
8435 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8436 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8437 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8439 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8440 DAG.getIntPtrConstant(0));
8443 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8444 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8445 DAG.getIntPtrConstant(0));
8446 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8447 DAG.getIntPtrConstant(2));
8449 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8450 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8453 static const int ShufMask1[] = {0, 2, 0, 0};
8454 SDValue Undef = DAG.getUNDEF(VT);
8455 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8456 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8458 // The MOVLHPS mask:
8459 static const int ShufMask2[] = {0, 1, 4, 5};
8460 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8463 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8464 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8465 if (Subtarget->hasInt256()) {
8466 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8468 SmallVector<SDValue,32> pshufbMask;
8469 for (unsigned i = 0; i < 2; ++i) {
8470 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8471 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8472 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8473 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8474 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8475 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8476 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8477 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8478 for (unsigned j = 0; j < 8; ++j)
8479 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8481 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8482 &pshufbMask[0], 32);
8483 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8484 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8486 static const int ShufMask[] = {0, 2, -1, -1};
8487 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8489 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8490 DAG.getIntPtrConstant(0));
8491 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8494 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8495 DAG.getIntPtrConstant(0));
8497 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8498 DAG.getIntPtrConstant(4));
8500 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8501 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8504 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8505 -1, -1, -1, -1, -1, -1, -1, -1};
8507 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8508 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8509 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8511 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8512 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8514 // The MOVLHPS Mask:
8515 static const int ShufMask2[] = {0, 1, 4, 5};
8516 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8517 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8520 // Handle truncation of V256 to V128 using shuffles.
8521 if (!VT.is128BitVector() || !SVT.is256BitVector())
8524 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8526 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8528 unsigned NumElems = VT.getVectorNumElements();
8529 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8532 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8533 // Prepare truncation shuffle mask
8534 for (unsigned i = 0; i != NumElems; ++i)
8536 SDValue V = DAG.getVectorShuffle(NVT, DL,
8537 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8538 DAG.getUNDEF(NVT), &MaskVec[0]);
8539 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8540 DAG.getIntPtrConstant(0));
8543 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8544 SelectionDAG &DAG) const {
8545 MVT VT = Op.getValueType().getSimpleVT();
8546 if (VT.isVector()) {
8547 if (VT == MVT::v8i16)
8548 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), VT,
8549 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8550 MVT::v8i32, Op.getOperand(0)));
8554 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8555 /*IsSigned=*/ true, /*IsReplace=*/ false);
8556 SDValue FIST = Vals.first, StackSlot = Vals.second;
8557 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8558 if (FIST.getNode() == 0) return Op;
8560 if (StackSlot.getNode())
8562 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8563 FIST, StackSlot, MachinePointerInfo(),
8564 false, false, false, 0);
8566 // The node is the result.
8570 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8571 SelectionDAG &DAG) const {
8572 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8573 /*IsSigned=*/ false, /*IsReplace=*/ false);
8574 SDValue FIST = Vals.first, StackSlot = Vals.second;
8575 assert(FIST.getNode() && "Unexpected failure");
8577 if (StackSlot.getNode())
8579 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8580 FIST, StackSlot, MachinePointerInfo(),
8581 false, false, false, 0);
8583 // The node is the result.
8587 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
8588 DebugLoc DL = Op.getDebugLoc();
8589 MVT VT = Op.getValueType().getSimpleVT();
8590 SDValue In = Op.getOperand(0);
8591 MVT SVT = In.getValueType().getSimpleVT();
8593 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8595 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8596 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8597 In, DAG.getUNDEF(SVT)));
8600 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8601 LLVMContext *Context = DAG.getContext();
8602 DebugLoc dl = Op.getDebugLoc();
8603 MVT VT = Op.getValueType().getSimpleVT();
8605 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8606 if (VT.isVector()) {
8607 EltVT = VT.getVectorElementType();
8608 NumElts = VT.getVectorNumElements();
8611 if (EltVT == MVT::f64)
8612 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8613 APInt(64, ~(1ULL << 63))));
8615 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8616 APInt(32, ~(1U << 31))));
8617 C = ConstantVector::getSplat(NumElts, C);
8618 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8619 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8620 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8621 MachinePointerInfo::getConstantPool(),
8622 false, false, false, Alignment);
8623 if (VT.isVector()) {
8624 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8625 return DAG.getNode(ISD::BITCAST, dl, VT,
8626 DAG.getNode(ISD::AND, dl, ANDVT,
8627 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8629 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8631 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8634 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8635 LLVMContext *Context = DAG.getContext();
8636 DebugLoc dl = Op.getDebugLoc();
8637 MVT VT = Op.getValueType().getSimpleVT();
8639 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8640 if (VT.isVector()) {
8641 EltVT = VT.getVectorElementType();
8642 NumElts = VT.getVectorNumElements();
8645 if (EltVT == MVT::f64)
8646 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8647 APInt(64, 1ULL << 63)));
8649 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8650 APInt(32, 1U << 31)));
8651 C = ConstantVector::getSplat(NumElts, C);
8652 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8653 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8654 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8655 MachinePointerInfo::getConstantPool(),
8656 false, false, false, Alignment);
8657 if (VT.isVector()) {
8658 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8659 return DAG.getNode(ISD::BITCAST, dl, VT,
8660 DAG.getNode(ISD::XOR, dl, XORVT,
8661 DAG.getNode(ISD::BITCAST, dl, XORVT,
8663 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8666 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8669 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8670 LLVMContext *Context = DAG.getContext();
8671 SDValue Op0 = Op.getOperand(0);
8672 SDValue Op1 = Op.getOperand(1);
8673 DebugLoc dl = Op.getDebugLoc();
8674 MVT VT = Op.getValueType().getSimpleVT();
8675 MVT SrcVT = Op1.getValueType().getSimpleVT();
8677 // If second operand is smaller, extend it first.
8678 if (SrcVT.bitsLT(VT)) {
8679 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8682 // And if it is bigger, shrink it first.
8683 if (SrcVT.bitsGT(VT)) {
8684 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8688 // At this point the operands and the result should have the same
8689 // type, and that won't be f80 since that is not custom lowered.
8691 // First get the sign bit of second operand.
8692 SmallVector<Constant*,4> CV;
8693 if (SrcVT == MVT::f64) {
8694 const fltSemantics &Sem = APFloat::IEEEdouble;
8695 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
8696 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
8698 const fltSemantics &Sem = APFloat::IEEEsingle;
8699 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
8700 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8701 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8702 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8704 Constant *C = ConstantVector::get(CV);
8705 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8706 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8707 MachinePointerInfo::getConstantPool(),
8708 false, false, false, 16);
8709 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8711 // Shift sign bit right or left if the two operands have different types.
8712 if (SrcVT.bitsGT(VT)) {
8713 // Op0 is MVT::f32, Op1 is MVT::f64.
8714 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8715 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8716 DAG.getConstant(32, MVT::i32));
8717 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8718 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8719 DAG.getIntPtrConstant(0));
8722 // Clear first operand sign bit.
8724 if (VT == MVT::f64) {
8725 const fltSemantics &Sem = APFloat::IEEEdouble;
8726 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
8727 APInt(64, ~(1ULL << 63)))));
8728 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
8730 const fltSemantics &Sem = APFloat::IEEEsingle;
8731 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
8732 APInt(32, ~(1U << 31)))));
8733 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8734 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8735 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8737 C = ConstantVector::get(CV);
8738 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8739 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8740 MachinePointerInfo::getConstantPool(),
8741 false, false, false, 16);
8742 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8744 // Or the value with the sign bit.
8745 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8748 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
8749 SDValue N0 = Op.getOperand(0);
8750 DebugLoc dl = Op.getDebugLoc();
8751 MVT VT = Op.getValueType().getSimpleVT();
8753 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8754 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8755 DAG.getConstant(1, VT));
8756 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8759 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
8761 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op,
8762 SelectionDAG &DAG) const {
8763 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8765 if (!Subtarget->hasSSE41())
8768 if (!Op->hasOneUse())
8771 SDNode *N = Op.getNode();
8772 DebugLoc DL = N->getDebugLoc();
8774 SmallVector<SDValue, 8> Opnds;
8775 DenseMap<SDValue, unsigned> VecInMap;
8776 EVT VT = MVT::Other;
8778 // Recognize a special case where a vector is casted into wide integer to
8780 Opnds.push_back(N->getOperand(0));
8781 Opnds.push_back(N->getOperand(1));
8783 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
8784 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot;
8785 // BFS traverse all OR'd operands.
8786 if (I->getOpcode() == ISD::OR) {
8787 Opnds.push_back(I->getOperand(0));
8788 Opnds.push_back(I->getOperand(1));
8789 // Re-evaluate the number of nodes to be traversed.
8790 e += 2; // 2 more nodes (LHS and RHS) are pushed.
8794 // Quit if a non-EXTRACT_VECTOR_ELT
8795 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8798 // Quit if without a constant index.
8799 SDValue Idx = I->getOperand(1);
8800 if (!isa<ConstantSDNode>(Idx))
8803 SDValue ExtractedFromVec = I->getOperand(0);
8804 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
8805 if (M == VecInMap.end()) {
8806 VT = ExtractedFromVec.getValueType();
8807 // Quit if not 128/256-bit vector.
8808 if (!VT.is128BitVector() && !VT.is256BitVector())
8810 // Quit if not the same type.
8811 if (VecInMap.begin() != VecInMap.end() &&
8812 VT != VecInMap.begin()->first.getValueType())
8814 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
8816 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
8819 assert((VT.is128BitVector() || VT.is256BitVector()) &&
8820 "Not extracted from 128-/256-bit vector.");
8822 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
8823 SmallVector<SDValue, 8> VecIns;
8825 for (DenseMap<SDValue, unsigned>::const_iterator
8826 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
8827 // Quit if not all elements are used.
8828 if (I->second != FullMask)
8830 VecIns.push_back(I->first);
8833 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8835 // Cast all vectors into TestVT for PTEST.
8836 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
8837 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8839 // If more than one full vectors are evaluated, OR them first before PTEST.
8840 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
8841 // Each iteration will OR 2 nodes and append the result until there is only
8842 // 1 node left, i.e. the final OR'd value of all vectors.
8843 SDValue LHS = VecIns[Slot];
8844 SDValue RHS = VecIns[Slot + 1];
8845 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8848 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
8849 VecIns.back(), VecIns.back());
8852 /// Emit nodes that will be selected as "test Op0,Op0", or something
8854 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8855 SelectionDAG &DAG) const {
8856 DebugLoc dl = Op.getDebugLoc();
8858 // CF and OF aren't always set the way we want. Determine which
8859 // of these we need.
8860 bool NeedCF = false;
8861 bool NeedOF = false;
8864 case X86::COND_A: case X86::COND_AE:
8865 case X86::COND_B: case X86::COND_BE:
8868 case X86::COND_G: case X86::COND_GE:
8869 case X86::COND_L: case X86::COND_LE:
8870 case X86::COND_O: case X86::COND_NO:
8875 // See if we can use the EFLAGS value from the operand instead of
8876 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8877 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8878 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8879 // Emit a CMP with 0, which is the TEST pattern.
8880 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8881 DAG.getConstant(0, Op.getValueType()));
8883 unsigned Opcode = 0;
8884 unsigned NumOperands = 0;
8886 // Truncate operations may prevent the merge of the SETCC instruction
8887 // and the arithmetic intruction before it. Attempt to truncate the operands
8888 // of the arithmetic instruction and use a reduced bit-width instruction.
8889 bool NeedTruncation = false;
8890 SDValue ArithOp = Op;
8891 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8892 SDValue Arith = Op->getOperand(0);
8893 // Both the trunc and the arithmetic op need to have one user each.
8894 if (Arith->hasOneUse())
8895 switch (Arith.getOpcode()) {
8902 NeedTruncation = true;
8908 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8909 // which may be the result of a CAST. We use the variable 'Op', which is the
8910 // non-casted variable when we check for possible users.
8911 switch (ArithOp.getOpcode()) {
8913 // Due to an isel shortcoming, be conservative if this add is likely to be
8914 // selected as part of a load-modify-store instruction. When the root node
8915 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8916 // uses of other nodes in the match, such as the ADD in this case. This
8917 // leads to the ADD being left around and reselected, with the result being
8918 // two adds in the output. Alas, even if none our users are stores, that
8919 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8920 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8921 // climbing the DAG back to the root, and it doesn't seem to be worth the
8923 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8924 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8925 if (UI->getOpcode() != ISD::CopyToReg &&
8926 UI->getOpcode() != ISD::SETCC &&
8927 UI->getOpcode() != ISD::STORE)
8930 if (ConstantSDNode *C =
8931 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8932 // An add of one will be selected as an INC.
8933 if (C->getAPIntValue() == 1) {
8934 Opcode = X86ISD::INC;
8939 // An add of negative one (subtract of one) will be selected as a DEC.
8940 if (C->getAPIntValue().isAllOnesValue()) {
8941 Opcode = X86ISD::DEC;
8947 // Otherwise use a regular EFLAGS-setting add.
8948 Opcode = X86ISD::ADD;
8952 // If the primary and result isn't used, don't bother using X86ISD::AND,
8953 // because a TEST instruction will be better.
8954 bool NonFlagUse = false;
8955 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8956 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8958 unsigned UOpNo = UI.getOperandNo();
8959 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8960 // Look pass truncate.
8961 UOpNo = User->use_begin().getOperandNo();
8962 User = *User->use_begin();
8965 if (User->getOpcode() != ISD::BRCOND &&
8966 User->getOpcode() != ISD::SETCC &&
8967 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8980 // Due to the ISEL shortcoming noted above, be conservative if this op is
8981 // likely to be selected as part of a load-modify-store instruction.
8982 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8983 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8984 if (UI->getOpcode() == ISD::STORE)
8987 // Otherwise use a regular EFLAGS-setting instruction.
8988 switch (ArithOp.getOpcode()) {
8989 default: llvm_unreachable("unexpected operator!");
8990 case ISD::SUB: Opcode = X86ISD::SUB; break;
8991 case ISD::XOR: Opcode = X86ISD::XOR; break;
8992 case ISD::AND: Opcode = X86ISD::AND; break;
8994 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
8995 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
8996 if (EFLAGS.getNode())
8999 Opcode = X86ISD::OR;
9013 return SDValue(Op.getNode(), 1);
9019 // If we found that truncation is beneficial, perform the truncation and
9021 if (NeedTruncation) {
9022 EVT VT = Op.getValueType();
9023 SDValue WideVal = Op->getOperand(0);
9024 EVT WideVT = WideVal.getValueType();
9025 unsigned ConvertedOp = 0;
9026 // Use a target machine opcode to prevent further DAGCombine
9027 // optimizations that may separate the arithmetic operations
9028 // from the setcc node.
9029 switch (WideVal.getOpcode()) {
9031 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9032 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9033 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9034 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9035 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9040 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9041 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9042 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9043 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9049 // Emit a CMP with 0, which is the TEST pattern.
9050 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9051 DAG.getConstant(0, Op.getValueType()));
9053 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9054 SmallVector<SDValue, 4> Ops;
9055 for (unsigned i = 0; i != NumOperands; ++i)
9056 Ops.push_back(Op.getOperand(i));
9058 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9059 DAG.ReplaceAllUsesWith(Op, New);
9060 return SDValue(New.getNode(), 1);
9063 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9065 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9066 SelectionDAG &DAG) const {
9067 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9068 if (C->getAPIntValue() == 0)
9069 return EmitTest(Op0, X86CC, DAG);
9071 DebugLoc dl = Op0.getDebugLoc();
9072 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9073 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9074 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9075 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9076 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9078 return SDValue(Sub.getNode(), 1);
9080 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9083 /// Convert a comparison if required by the subtarget.
9084 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9085 SelectionDAG &DAG) const {
9086 // If the subtarget does not support the FUCOMI instruction, floating-point
9087 // comparisons have to be converted.
9088 if (Subtarget->hasCMov() ||
9089 Cmp.getOpcode() != X86ISD::CMP ||
9090 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9091 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9094 // The instruction selector will select an FUCOM instruction instead of
9095 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9096 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9097 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9098 DebugLoc dl = Cmp.getDebugLoc();
9099 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9100 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9101 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9102 DAG.getConstant(8, MVT::i8));
9103 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9104 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9107 static bool isAllOnes(SDValue V) {
9108 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9109 return C && C->isAllOnesValue();
9112 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9113 /// if it's possible.
9114 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9115 DebugLoc dl, SelectionDAG &DAG) const {
9116 SDValue Op0 = And.getOperand(0);
9117 SDValue Op1 = And.getOperand(1);
9118 if (Op0.getOpcode() == ISD::TRUNCATE)
9119 Op0 = Op0.getOperand(0);
9120 if (Op1.getOpcode() == ISD::TRUNCATE)
9121 Op1 = Op1.getOperand(0);
9124 if (Op1.getOpcode() == ISD::SHL)
9125 std::swap(Op0, Op1);
9126 if (Op0.getOpcode() == ISD::SHL) {
9127 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9128 if (And00C->getZExtValue() == 1) {
9129 // If we looked past a truncate, check that it's only truncating away
9131 unsigned BitWidth = Op0.getValueSizeInBits();
9132 unsigned AndBitWidth = And.getValueSizeInBits();
9133 if (BitWidth > AndBitWidth) {
9135 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9136 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9140 RHS = Op0.getOperand(1);
9142 } else if (Op1.getOpcode() == ISD::Constant) {
9143 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9144 uint64_t AndRHSVal = AndRHS->getZExtValue();
9145 SDValue AndLHS = Op0;
9147 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9148 LHS = AndLHS.getOperand(0);
9149 RHS = AndLHS.getOperand(1);
9152 // Use BT if the immediate can't be encoded in a TEST instruction.
9153 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9155 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9159 if (LHS.getNode()) {
9160 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip
9161 // the condition code later.
9162 bool Invert = false;
9163 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
9165 LHS = LHS.getOperand(0);
9168 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9169 // instruction. Since the shift amount is in-range-or-undefined, we know
9170 // that doing a bittest on the i32 value is ok. We extend to i32 because
9171 // the encoding for the i16 version is larger than the i32 version.
9172 // Also promote i16 to i32 for performance / code size reason.
9173 if (LHS.getValueType() == MVT::i8 ||
9174 LHS.getValueType() == MVT::i16)
9175 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9177 // If the operand types disagree, extend the shift amount to match. Since
9178 // BT ignores high bits (like shifts) we can use anyextend.
9179 if (LHS.getValueType() != RHS.getValueType())
9180 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9182 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9183 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9184 // Flip the condition if the LHS was a not instruction
9186 Cond = X86::GetOppositeBranchCondition(Cond);
9187 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9188 DAG.getConstant(Cond, MVT::i8), BT);
9194 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9195 // ones, and then concatenate the result back.
9196 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9197 MVT VT = Op.getValueType().getSimpleVT();
9199 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9200 "Unsupported value type for operation");
9202 unsigned NumElems = VT.getVectorNumElements();
9203 DebugLoc dl = Op.getDebugLoc();
9204 SDValue CC = Op.getOperand(2);
9206 // Extract the LHS vectors
9207 SDValue LHS = Op.getOperand(0);
9208 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9209 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9211 // Extract the RHS vectors
9212 SDValue RHS = Op.getOperand(1);
9213 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9214 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9216 // Issue the operation on the smaller types and concatenate the result back
9217 MVT EltVT = VT.getVectorElementType();
9218 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9219 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9220 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9221 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9224 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9225 SelectionDAG &DAG) {
9227 SDValue Op0 = Op.getOperand(0);
9228 SDValue Op1 = Op.getOperand(1);
9229 SDValue CC = Op.getOperand(2);
9230 MVT VT = Op.getValueType().getSimpleVT();
9231 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9232 bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint();
9233 DebugLoc dl = Op.getDebugLoc();
9237 MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
9238 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9244 // SSE Condition code mapping:
9253 switch (SetCCOpcode) {
9254 default: llvm_unreachable("Unexpected SETCC condition");
9256 case ISD::SETEQ: SSECC = 0; break;
9258 case ISD::SETGT: Swap = true; // Fallthrough
9260 case ISD::SETOLT: SSECC = 1; break;
9262 case ISD::SETGE: Swap = true; // Fallthrough
9264 case ISD::SETOLE: SSECC = 2; break;
9265 case ISD::SETUO: SSECC = 3; break;
9267 case ISD::SETNE: SSECC = 4; break;
9268 case ISD::SETULE: Swap = true; // Fallthrough
9269 case ISD::SETUGE: SSECC = 5; break;
9270 case ISD::SETULT: Swap = true; // Fallthrough
9271 case ISD::SETUGT: SSECC = 6; break;
9272 case ISD::SETO: SSECC = 7; break;
9274 case ISD::SETONE: SSECC = 8; break;
9277 std::swap(Op0, Op1);
9279 // In the two special cases we can't handle, emit two comparisons.
9282 unsigned CombineOpc;
9283 if (SetCCOpcode == ISD::SETUEQ) {
9284 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9286 assert(SetCCOpcode == ISD::SETONE);
9287 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9290 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9291 DAG.getConstant(CC0, MVT::i8));
9292 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9293 DAG.getConstant(CC1, MVT::i8));
9294 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9296 // Handle all other FP comparisons here.
9297 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9298 DAG.getConstant(SSECC, MVT::i8));
9301 // Break 256-bit integer vector compare into smaller ones.
9302 if (VT.is256BitVector() && !Subtarget->hasInt256())
9303 return Lower256IntVSETCC(Op, DAG);
9305 // We are handling one of the integer comparisons here. Since SSE only has
9306 // GT and EQ comparisons for integer, swapping operands and multiple
9307 // operations may be required for some comparisons.
9309 bool Swap = false, Invert = false, FlipSigns = false;
9311 switch (SetCCOpcode) {
9312 default: llvm_unreachable("Unexpected SETCC condition");
9313 case ISD::SETNE: Invert = true;
9314 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9315 case ISD::SETLT: Swap = true;
9316 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9317 case ISD::SETGE: Swap = true;
9318 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9319 case ISD::SETULT: Swap = true;
9320 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9321 case ISD::SETUGE: Swap = true;
9322 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9325 std::swap(Op0, Op1);
9327 // Check that the operation in question is available (most are plain SSE2,
9328 // but PCMPGTQ and PCMPEQQ have different requirements).
9329 if (VT == MVT::v2i64) {
9330 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
9332 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9333 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9334 // pcmpeqd + pshufd + pand.
9335 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9337 // First cast everything to the right type,
9338 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9339 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9342 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9344 // Make sure the lower and upper halves are both all-ones.
9345 const int Mask[] = { 1, 0, 3, 2 };
9346 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9347 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9350 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9352 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9356 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9357 // bits of the inputs before performing those operations.
9359 EVT EltVT = VT.getVectorElementType();
9360 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
9362 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
9363 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9365 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9366 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9369 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9371 // If the logical-not of the result is required, perform that now.
9373 Result = DAG.getNOT(dl, Result, VT);
9378 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9380 MVT VT = Op.getValueType().getSimpleVT();
9382 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9384 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9385 SDValue Op0 = Op.getOperand(0);
9386 SDValue Op1 = Op.getOperand(1);
9387 DebugLoc dl = Op.getDebugLoc();
9388 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9390 // Optimize to BT if possible.
9391 // Lower (X & (1 << N)) == 0 to BT(X, N).
9392 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9393 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9394 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9395 Op1.getOpcode() == ISD::Constant &&
9396 cast<ConstantSDNode>(Op1)->isNullValue() &&
9397 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9398 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9399 if (NewSetCC.getNode())
9403 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9405 if (Op1.getOpcode() == ISD::Constant &&
9406 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9407 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9408 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9410 // If the input is a setcc, then reuse the input setcc or use a new one with
9411 // the inverted condition.
9412 if (Op0.getOpcode() == X86ISD::SETCC) {
9413 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9414 bool Invert = (CC == ISD::SETNE) ^
9415 cast<ConstantSDNode>(Op1)->isNullValue();
9416 if (!Invert) return Op0;
9418 CCode = X86::GetOppositeBranchCondition(CCode);
9419 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9420 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9424 bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint();
9425 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9426 if (X86CC == X86::COND_INVALID)
9429 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9430 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9431 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9432 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9435 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9436 static bool isX86LogicalCmp(SDValue Op) {
9437 unsigned Opc = Op.getNode()->getOpcode();
9438 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9439 Opc == X86ISD::SAHF)
9441 if (Op.getResNo() == 1 &&
9442 (Opc == X86ISD::ADD ||
9443 Opc == X86ISD::SUB ||
9444 Opc == X86ISD::ADC ||
9445 Opc == X86ISD::SBB ||
9446 Opc == X86ISD::SMUL ||
9447 Opc == X86ISD::UMUL ||
9448 Opc == X86ISD::INC ||
9449 Opc == X86ISD::DEC ||
9450 Opc == X86ISD::OR ||
9451 Opc == X86ISD::XOR ||
9452 Opc == X86ISD::AND))
9455 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9461 static bool isZero(SDValue V) {
9462 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9463 return C && C->isNullValue();
9466 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9467 if (V.getOpcode() != ISD::TRUNCATE)
9470 SDValue VOp0 = V.getOperand(0);
9471 unsigned InBits = VOp0.getValueSizeInBits();
9472 unsigned Bits = V.getValueSizeInBits();
9473 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9476 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9477 bool addTest = true;
9478 SDValue Cond = Op.getOperand(0);
9479 SDValue Op1 = Op.getOperand(1);
9480 SDValue Op2 = Op.getOperand(2);
9481 DebugLoc DL = Op.getDebugLoc();
9484 if (Cond.getOpcode() == ISD::SETCC) {
9485 SDValue NewCond = LowerSETCC(Cond, DAG);
9486 if (NewCond.getNode())
9490 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9491 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9492 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9493 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9494 if (Cond.getOpcode() == X86ISD::SETCC &&
9495 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9496 isZero(Cond.getOperand(1).getOperand(1))) {
9497 SDValue Cmp = Cond.getOperand(1);
9499 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9501 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9502 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9503 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9505 SDValue CmpOp0 = Cmp.getOperand(0);
9506 // Apply further optimizations for special cases
9507 // (select (x != 0), -1, 0) -> neg & sbb
9508 // (select (x == 0), 0, -1) -> neg & sbb
9509 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9510 if (YC->isNullValue() &&
9511 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9512 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9513 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9514 DAG.getConstant(0, CmpOp0.getValueType()),
9516 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9517 DAG.getConstant(X86::COND_B, MVT::i8),
9518 SDValue(Neg.getNode(), 1));
9522 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9523 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9524 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9526 SDValue Res = // Res = 0 or -1.
9527 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9528 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9530 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9531 Res = DAG.getNOT(DL, Res, Res.getValueType());
9533 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9534 if (N2C == 0 || !N2C->isNullValue())
9535 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9540 // Look past (and (setcc_carry (cmp ...)), 1).
9541 if (Cond.getOpcode() == ISD::AND &&
9542 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9543 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9544 if (C && C->getAPIntValue() == 1)
9545 Cond = Cond.getOperand(0);
9548 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9549 // setting operand in place of the X86ISD::SETCC.
9550 unsigned CondOpcode = Cond.getOpcode();
9551 if (CondOpcode == X86ISD::SETCC ||
9552 CondOpcode == X86ISD::SETCC_CARRY) {
9553 CC = Cond.getOperand(0);
9555 SDValue Cmp = Cond.getOperand(1);
9556 unsigned Opc = Cmp.getOpcode();
9557 MVT VT = Op.getValueType().getSimpleVT();
9559 bool IllegalFPCMov = false;
9560 if (VT.isFloatingPoint() && !VT.isVector() &&
9561 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9562 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9564 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9565 Opc == X86ISD::BT) { // FIXME
9569 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9570 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9571 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9572 Cond.getOperand(0).getValueType() != MVT::i8)) {
9573 SDValue LHS = Cond.getOperand(0);
9574 SDValue RHS = Cond.getOperand(1);
9578 switch (CondOpcode) {
9579 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9580 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9581 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9582 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9583 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9584 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9585 default: llvm_unreachable("unexpected overflowing operator");
9587 if (CondOpcode == ISD::UMULO)
9588 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9591 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9593 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9595 if (CondOpcode == ISD::UMULO)
9596 Cond = X86Op.getValue(2);
9598 Cond = X86Op.getValue(1);
9600 CC = DAG.getConstant(X86Cond, MVT::i8);
9605 // Look pass the truncate if the high bits are known zero.
9606 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9607 Cond = Cond.getOperand(0);
9609 // We know the result of AND is compared against zero. Try to match
9611 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9612 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9613 if (NewSetCC.getNode()) {
9614 CC = NewSetCC.getOperand(0);
9615 Cond = NewSetCC.getOperand(1);
9622 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9623 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9626 // a < b ? -1 : 0 -> RES = ~setcc_carry
9627 // a < b ? 0 : -1 -> RES = setcc_carry
9628 // a >= b ? -1 : 0 -> RES = setcc_carry
9629 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9630 if (Cond.getOpcode() == X86ISD::SUB) {
9631 Cond = ConvertCmpIfNecessary(Cond, DAG);
9632 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9634 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9635 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9636 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9637 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9638 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9639 return DAG.getNOT(DL, Res, Res.getValueType());
9644 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9645 // widen the cmov and push the truncate through. This avoids introducing a new
9646 // branch during isel and doesn't add any extensions.
9647 if (Op.getValueType() == MVT::i8 &&
9648 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9649 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
9650 if (T1.getValueType() == T2.getValueType() &&
9651 // Blacklist CopyFromReg to avoid partial register stalls.
9652 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9653 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
9654 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
9655 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9659 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9660 // condition is true.
9661 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9662 SDValue Ops[] = { Op2, Op1, CC, Cond };
9663 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9666 SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
9667 SelectionDAG &DAG) const {
9668 MVT VT = Op->getValueType(0).getSimpleVT();
9669 SDValue In = Op->getOperand(0);
9670 MVT InVT = In.getValueType().getSimpleVT();
9671 DebugLoc dl = Op->getDebugLoc();
9673 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
9674 (VT != MVT::v8i32 || InVT != MVT::v8i16))
9677 if (Subtarget->hasInt256())
9678 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
9680 // Optimize vectors in AVX mode
9681 // Sign extend v8i16 to v8i32 and
9684 // Divide input vector into two parts
9685 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
9686 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
9687 // concat the vectors to original VT
9689 unsigned NumElems = InVT.getVectorNumElements();
9690 SDValue Undef = DAG.getUNDEF(InVT);
9692 SmallVector<int,8> ShufMask1(NumElems, -1);
9693 for (unsigned i = 0; i != NumElems/2; ++i)
9696 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
9698 SmallVector<int,8> ShufMask2(NumElems, -1);
9699 for (unsigned i = 0; i != NumElems/2; ++i)
9700 ShufMask2[i] = i + NumElems/2;
9702 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
9704 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
9705 VT.getVectorNumElements()/2);
9707 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
9708 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
9710 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9713 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9714 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9715 // from the AND / OR.
9716 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9717 Opc = Op.getOpcode();
9718 if (Opc != ISD::OR && Opc != ISD::AND)
9720 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9721 Op.getOperand(0).hasOneUse() &&
9722 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9723 Op.getOperand(1).hasOneUse());
9726 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9727 // 1 and that the SETCC node has a single use.
9728 static bool isXor1OfSetCC(SDValue Op) {
9729 if (Op.getOpcode() != ISD::XOR)
9731 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9732 if (N1C && N1C->getAPIntValue() == 1) {
9733 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9734 Op.getOperand(0).hasOneUse();
9739 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9740 bool addTest = true;
9741 SDValue Chain = Op.getOperand(0);
9742 SDValue Cond = Op.getOperand(1);
9743 SDValue Dest = Op.getOperand(2);
9744 DebugLoc dl = Op.getDebugLoc();
9746 bool Inverted = false;
9748 if (Cond.getOpcode() == ISD::SETCC) {
9749 // Check for setcc([su]{add,sub,mul}o == 0).
9750 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9751 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9752 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9753 Cond.getOperand(0).getResNo() == 1 &&
9754 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9755 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9756 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9757 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9758 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9759 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9761 Cond = Cond.getOperand(0);
9763 SDValue NewCond = LowerSETCC(Cond, DAG);
9764 if (NewCond.getNode())
9769 // FIXME: LowerXALUO doesn't handle these!!
9770 else if (Cond.getOpcode() == X86ISD::ADD ||
9771 Cond.getOpcode() == X86ISD::SUB ||
9772 Cond.getOpcode() == X86ISD::SMUL ||
9773 Cond.getOpcode() == X86ISD::UMUL)
9774 Cond = LowerXALUO(Cond, DAG);
9777 // Look pass (and (setcc_carry (cmp ...)), 1).
9778 if (Cond.getOpcode() == ISD::AND &&
9779 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9780 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9781 if (C && C->getAPIntValue() == 1)
9782 Cond = Cond.getOperand(0);
9785 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9786 // setting operand in place of the X86ISD::SETCC.
9787 unsigned CondOpcode = Cond.getOpcode();
9788 if (CondOpcode == X86ISD::SETCC ||
9789 CondOpcode == X86ISD::SETCC_CARRY) {
9790 CC = Cond.getOperand(0);
9792 SDValue Cmp = Cond.getOperand(1);
9793 unsigned Opc = Cmp.getOpcode();
9794 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9795 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9799 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9803 // These can only come from an arithmetic instruction with overflow,
9804 // e.g. SADDO, UADDO.
9805 Cond = Cond.getNode()->getOperand(1);
9811 CondOpcode = Cond.getOpcode();
9812 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9813 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9814 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9815 Cond.getOperand(0).getValueType() != MVT::i8)) {
9816 SDValue LHS = Cond.getOperand(0);
9817 SDValue RHS = Cond.getOperand(1);
9821 switch (CondOpcode) {
9822 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9823 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9824 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9825 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9826 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9827 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9828 default: llvm_unreachable("unexpected overflowing operator");
9831 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9832 if (CondOpcode == ISD::UMULO)
9833 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9836 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9838 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9840 if (CondOpcode == ISD::UMULO)
9841 Cond = X86Op.getValue(2);
9843 Cond = X86Op.getValue(1);
9845 CC = DAG.getConstant(X86Cond, MVT::i8);
9849 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9850 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9851 if (CondOpc == ISD::OR) {
9852 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9853 // two branches instead of an explicit OR instruction with a
9855 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9856 isX86LogicalCmp(Cmp)) {
9857 CC = Cond.getOperand(0).getOperand(0);
9858 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9859 Chain, Dest, CC, Cmp);
9860 CC = Cond.getOperand(1).getOperand(0);
9864 } else { // ISD::AND
9865 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9866 // two branches instead of an explicit AND instruction with a
9867 // separate test. However, we only do this if this block doesn't
9868 // have a fall-through edge, because this requires an explicit
9869 // jmp when the condition is false.
9870 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9871 isX86LogicalCmp(Cmp) &&
9872 Op.getNode()->hasOneUse()) {
9873 X86::CondCode CCode =
9874 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9875 CCode = X86::GetOppositeBranchCondition(CCode);
9876 CC = DAG.getConstant(CCode, MVT::i8);
9877 SDNode *User = *Op.getNode()->use_begin();
9878 // Look for an unconditional branch following this conditional branch.
9879 // We need this because we need to reverse the successors in order
9880 // to implement FCMP_OEQ.
9881 if (User->getOpcode() == ISD::BR) {
9882 SDValue FalseBB = User->getOperand(1);
9884 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9885 assert(NewBR == User);
9889 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9890 Chain, Dest, CC, Cmp);
9891 X86::CondCode CCode =
9892 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9893 CCode = X86::GetOppositeBranchCondition(CCode);
9894 CC = DAG.getConstant(CCode, MVT::i8);
9900 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9901 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9902 // It should be transformed during dag combiner except when the condition
9903 // is set by a arithmetics with overflow node.
9904 X86::CondCode CCode =
9905 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9906 CCode = X86::GetOppositeBranchCondition(CCode);
9907 CC = DAG.getConstant(CCode, MVT::i8);
9908 Cond = Cond.getOperand(0).getOperand(1);
9910 } else if (Cond.getOpcode() == ISD::SETCC &&
9911 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9912 // For FCMP_OEQ, we can emit
9913 // two branches instead of an explicit AND instruction with a
9914 // separate test. However, we only do this if this block doesn't
9915 // have a fall-through edge, because this requires an explicit
9916 // jmp when the condition is false.
9917 if (Op.getNode()->hasOneUse()) {
9918 SDNode *User = *Op.getNode()->use_begin();
9919 // Look for an unconditional branch following this conditional branch.
9920 // We need this because we need to reverse the successors in order
9921 // to implement FCMP_OEQ.
9922 if (User->getOpcode() == ISD::BR) {
9923 SDValue FalseBB = User->getOperand(1);
9925 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9926 assert(NewBR == User);
9930 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9931 Cond.getOperand(0), Cond.getOperand(1));
9932 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9933 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9934 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9935 Chain, Dest, CC, Cmp);
9936 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9941 } else if (Cond.getOpcode() == ISD::SETCC &&
9942 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9943 // For FCMP_UNE, we can emit
9944 // two branches instead of an explicit AND instruction with a
9945 // separate test. However, we only do this if this block doesn't
9946 // have a fall-through edge, because this requires an explicit
9947 // jmp when the condition is false.
9948 if (Op.getNode()->hasOneUse()) {
9949 SDNode *User = *Op.getNode()->use_begin();
9950 // Look for an unconditional branch following this conditional branch.
9951 // We need this because we need to reverse the successors in order
9952 // to implement FCMP_UNE.
9953 if (User->getOpcode() == ISD::BR) {
9954 SDValue FalseBB = User->getOperand(1);
9956 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9957 assert(NewBR == User);
9960 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9961 Cond.getOperand(0), Cond.getOperand(1));
9962 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9963 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9964 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9965 Chain, Dest, CC, Cmp);
9966 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9976 // Look pass the truncate if the high bits are known zero.
9977 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9978 Cond = Cond.getOperand(0);
9980 // We know the result of AND is compared against zero. Try to match
9982 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9983 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9984 if (NewSetCC.getNode()) {
9985 CC = NewSetCC.getOperand(0);
9986 Cond = NewSetCC.getOperand(1);
9993 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9994 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9996 Cond = ConvertCmpIfNecessary(Cond, DAG);
9997 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9998 Chain, Dest, CC, Cond);
10001 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10002 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10003 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10004 // that the guard pages used by the OS virtual memory manager are allocated in
10005 // correct sequence.
10007 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10008 SelectionDAG &DAG) const {
10009 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10010 getTargetMachine().Options.EnableSegmentedStacks) &&
10011 "This should be used only on Windows targets or when segmented stacks "
10013 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10014 DebugLoc dl = Op.getDebugLoc();
10017 SDValue Chain = Op.getOperand(0);
10018 SDValue Size = Op.getOperand(1);
10019 // FIXME: Ensure alignment here
10021 bool Is64Bit = Subtarget->is64Bit();
10022 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10024 if (getTargetMachine().Options.EnableSegmentedStacks) {
10025 MachineFunction &MF = DAG.getMachineFunction();
10026 MachineRegisterInfo &MRI = MF.getRegInfo();
10029 // The 64 bit implementation of segmented stacks needs to clobber both r10
10030 // r11. This makes it impossible to use it along with nested parameters.
10031 const Function *F = MF.getFunction();
10033 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10035 if (I->hasNestAttr())
10036 report_fatal_error("Cannot use segmented stacks with functions that "
10037 "have nested arguments.");
10040 const TargetRegisterClass *AddrRegClass =
10041 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10042 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10043 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10044 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10045 DAG.getRegister(Vreg, SPTy));
10046 SDValue Ops1[2] = { Value, Chain };
10047 return DAG.getMergeValues(Ops1, 2, dl);
10050 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10052 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10053 Flag = Chain.getValue(1);
10054 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10056 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10057 Flag = Chain.getValue(1);
10059 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10062 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10063 return DAG.getMergeValues(Ops1, 2, dl);
10067 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10068 MachineFunction &MF = DAG.getMachineFunction();
10069 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10071 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10072 DebugLoc DL = Op.getDebugLoc();
10074 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10075 // vastart just stores the address of the VarArgsFrameIndex slot into the
10076 // memory location argument.
10077 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10079 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10080 MachinePointerInfo(SV), false, false, 0);
10084 // gp_offset (0 - 6 * 8)
10085 // fp_offset (48 - 48 + 8 * 16)
10086 // overflow_arg_area (point to parameters coming in memory).
10088 SmallVector<SDValue, 8> MemOps;
10089 SDValue FIN = Op.getOperand(1);
10091 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10092 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10094 FIN, MachinePointerInfo(SV), false, false, 0);
10095 MemOps.push_back(Store);
10098 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10099 FIN, DAG.getIntPtrConstant(4));
10100 Store = DAG.getStore(Op.getOperand(0), DL,
10101 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10103 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10104 MemOps.push_back(Store);
10106 // Store ptr to overflow_arg_area
10107 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10108 FIN, DAG.getIntPtrConstant(4));
10109 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10111 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10112 MachinePointerInfo(SV, 8),
10114 MemOps.push_back(Store);
10116 // Store ptr to reg_save_area.
10117 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10118 FIN, DAG.getIntPtrConstant(8));
10119 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10121 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10122 MachinePointerInfo(SV, 16), false, false, 0);
10123 MemOps.push_back(Store);
10124 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10125 &MemOps[0], MemOps.size());
10128 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10129 assert(Subtarget->is64Bit() &&
10130 "LowerVAARG only handles 64-bit va_arg!");
10131 assert((Subtarget->isTargetLinux() ||
10132 Subtarget->isTargetDarwin()) &&
10133 "Unhandled target in LowerVAARG");
10134 assert(Op.getNode()->getNumOperands() == 4);
10135 SDValue Chain = Op.getOperand(0);
10136 SDValue SrcPtr = Op.getOperand(1);
10137 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10138 unsigned Align = Op.getConstantOperandVal(3);
10139 DebugLoc dl = Op.getDebugLoc();
10141 EVT ArgVT = Op.getNode()->getValueType(0);
10142 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10143 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10146 // Decide which area this value should be read from.
10147 // TODO: Implement the AMD64 ABI in its entirety. This simple
10148 // selection mechanism works only for the basic types.
10149 if (ArgVT == MVT::f80) {
10150 llvm_unreachable("va_arg for f80 not yet implemented");
10151 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10152 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10153 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10154 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10156 llvm_unreachable("Unhandled argument type in LowerVAARG");
10159 if (ArgMode == 2) {
10160 // Sanity Check: Make sure using fp_offset makes sense.
10161 assert(!getTargetMachine().Options.UseSoftFloat &&
10162 !(DAG.getMachineFunction()
10163 .getFunction()->getAttributes()
10164 .hasAttribute(AttributeSet::FunctionIndex,
10165 Attribute::NoImplicitFloat)) &&
10166 Subtarget->hasSSE1());
10169 // Insert VAARG_64 node into the DAG
10170 // VAARG_64 returns two values: Variable Argument Address, Chain
10171 SmallVector<SDValue, 11> InstOps;
10172 InstOps.push_back(Chain);
10173 InstOps.push_back(SrcPtr);
10174 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10175 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10176 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10177 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10178 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10179 VTs, &InstOps[0], InstOps.size(),
10181 MachinePointerInfo(SV),
10183 /*Volatile=*/false,
10185 /*WriteMem=*/true);
10186 Chain = VAARG.getValue(1);
10188 // Load the next argument and return it
10189 return DAG.getLoad(ArgVT, dl,
10192 MachinePointerInfo(),
10193 false, false, false, 0);
10196 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10197 SelectionDAG &DAG) {
10198 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10199 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10200 SDValue Chain = Op.getOperand(0);
10201 SDValue DstPtr = Op.getOperand(1);
10202 SDValue SrcPtr = Op.getOperand(2);
10203 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10204 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10205 DebugLoc DL = Op.getDebugLoc();
10207 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10208 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10210 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10213 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
10214 // may or may not be a constant. Takes immediate version of shift as input.
10215 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
10216 SDValue SrcOp, SDValue ShAmt,
10217 SelectionDAG &DAG) {
10218 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10220 if (isa<ConstantSDNode>(ShAmt)) {
10221 // Constant may be a TargetConstant. Use a regular constant.
10222 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10224 default: llvm_unreachable("Unknown target vector shift node");
10225 case X86ISD::VSHLI:
10226 case X86ISD::VSRLI:
10227 case X86ISD::VSRAI:
10228 return DAG.getNode(Opc, dl, VT, SrcOp,
10229 DAG.getConstant(ShiftAmt, MVT::i32));
10233 // Change opcode to non-immediate version
10235 default: llvm_unreachable("Unknown target vector shift node");
10236 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10237 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10238 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10241 // Need to build a vector containing shift amount
10242 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10245 ShOps[1] = DAG.getConstant(0, MVT::i32);
10246 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10247 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10249 // The return type has to be a 128-bit type with the same element
10250 // type as the input type.
10251 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10252 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10254 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10255 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10258 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10259 DebugLoc dl = Op.getDebugLoc();
10260 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10262 default: return SDValue(); // Don't custom lower most intrinsics.
10263 // Comparison intrinsics.
10264 case Intrinsic::x86_sse_comieq_ss:
10265 case Intrinsic::x86_sse_comilt_ss:
10266 case Intrinsic::x86_sse_comile_ss:
10267 case Intrinsic::x86_sse_comigt_ss:
10268 case Intrinsic::x86_sse_comige_ss:
10269 case Intrinsic::x86_sse_comineq_ss:
10270 case Intrinsic::x86_sse_ucomieq_ss:
10271 case Intrinsic::x86_sse_ucomilt_ss:
10272 case Intrinsic::x86_sse_ucomile_ss:
10273 case Intrinsic::x86_sse_ucomigt_ss:
10274 case Intrinsic::x86_sse_ucomige_ss:
10275 case Intrinsic::x86_sse_ucomineq_ss:
10276 case Intrinsic::x86_sse2_comieq_sd:
10277 case Intrinsic::x86_sse2_comilt_sd:
10278 case Intrinsic::x86_sse2_comile_sd:
10279 case Intrinsic::x86_sse2_comigt_sd:
10280 case Intrinsic::x86_sse2_comige_sd:
10281 case Intrinsic::x86_sse2_comineq_sd:
10282 case Intrinsic::x86_sse2_ucomieq_sd:
10283 case Intrinsic::x86_sse2_ucomilt_sd:
10284 case Intrinsic::x86_sse2_ucomile_sd:
10285 case Intrinsic::x86_sse2_ucomigt_sd:
10286 case Intrinsic::x86_sse2_ucomige_sd:
10287 case Intrinsic::x86_sse2_ucomineq_sd: {
10291 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10292 case Intrinsic::x86_sse_comieq_ss:
10293 case Intrinsic::x86_sse2_comieq_sd:
10294 Opc = X86ISD::COMI;
10297 case Intrinsic::x86_sse_comilt_ss:
10298 case Intrinsic::x86_sse2_comilt_sd:
10299 Opc = X86ISD::COMI;
10302 case Intrinsic::x86_sse_comile_ss:
10303 case Intrinsic::x86_sse2_comile_sd:
10304 Opc = X86ISD::COMI;
10307 case Intrinsic::x86_sse_comigt_ss:
10308 case Intrinsic::x86_sse2_comigt_sd:
10309 Opc = X86ISD::COMI;
10312 case Intrinsic::x86_sse_comige_ss:
10313 case Intrinsic::x86_sse2_comige_sd:
10314 Opc = X86ISD::COMI;
10317 case Intrinsic::x86_sse_comineq_ss:
10318 case Intrinsic::x86_sse2_comineq_sd:
10319 Opc = X86ISD::COMI;
10322 case Intrinsic::x86_sse_ucomieq_ss:
10323 case Intrinsic::x86_sse2_ucomieq_sd:
10324 Opc = X86ISD::UCOMI;
10327 case Intrinsic::x86_sse_ucomilt_ss:
10328 case Intrinsic::x86_sse2_ucomilt_sd:
10329 Opc = X86ISD::UCOMI;
10332 case Intrinsic::x86_sse_ucomile_ss:
10333 case Intrinsic::x86_sse2_ucomile_sd:
10334 Opc = X86ISD::UCOMI;
10337 case Intrinsic::x86_sse_ucomigt_ss:
10338 case Intrinsic::x86_sse2_ucomigt_sd:
10339 Opc = X86ISD::UCOMI;
10342 case Intrinsic::x86_sse_ucomige_ss:
10343 case Intrinsic::x86_sse2_ucomige_sd:
10344 Opc = X86ISD::UCOMI;
10347 case Intrinsic::x86_sse_ucomineq_ss:
10348 case Intrinsic::x86_sse2_ucomineq_sd:
10349 Opc = X86ISD::UCOMI;
10354 SDValue LHS = Op.getOperand(1);
10355 SDValue RHS = Op.getOperand(2);
10356 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10357 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10358 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10359 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10360 DAG.getConstant(X86CC, MVT::i8), Cond);
10361 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10364 // Arithmetic intrinsics.
10365 case Intrinsic::x86_sse2_pmulu_dq:
10366 case Intrinsic::x86_avx2_pmulu_dq:
10367 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10368 Op.getOperand(1), Op.getOperand(2));
10370 // SSE2/AVX2 sub with unsigned saturation intrinsics
10371 case Intrinsic::x86_sse2_psubus_b:
10372 case Intrinsic::x86_sse2_psubus_w:
10373 case Intrinsic::x86_avx2_psubus_b:
10374 case Intrinsic::x86_avx2_psubus_w:
10375 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10376 Op.getOperand(1), Op.getOperand(2));
10378 // SSE3/AVX horizontal add/sub intrinsics
10379 case Intrinsic::x86_sse3_hadd_ps:
10380 case Intrinsic::x86_sse3_hadd_pd:
10381 case Intrinsic::x86_avx_hadd_ps_256:
10382 case Intrinsic::x86_avx_hadd_pd_256:
10383 case Intrinsic::x86_sse3_hsub_ps:
10384 case Intrinsic::x86_sse3_hsub_pd:
10385 case Intrinsic::x86_avx_hsub_ps_256:
10386 case Intrinsic::x86_avx_hsub_pd_256:
10387 case Intrinsic::x86_ssse3_phadd_w_128:
10388 case Intrinsic::x86_ssse3_phadd_d_128:
10389 case Intrinsic::x86_avx2_phadd_w:
10390 case Intrinsic::x86_avx2_phadd_d:
10391 case Intrinsic::x86_ssse3_phsub_w_128:
10392 case Intrinsic::x86_ssse3_phsub_d_128:
10393 case Intrinsic::x86_avx2_phsub_w:
10394 case Intrinsic::x86_avx2_phsub_d: {
10397 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10398 case Intrinsic::x86_sse3_hadd_ps:
10399 case Intrinsic::x86_sse3_hadd_pd:
10400 case Intrinsic::x86_avx_hadd_ps_256:
10401 case Intrinsic::x86_avx_hadd_pd_256:
10402 Opcode = X86ISD::FHADD;
10404 case Intrinsic::x86_sse3_hsub_ps:
10405 case Intrinsic::x86_sse3_hsub_pd:
10406 case Intrinsic::x86_avx_hsub_ps_256:
10407 case Intrinsic::x86_avx_hsub_pd_256:
10408 Opcode = X86ISD::FHSUB;
10410 case Intrinsic::x86_ssse3_phadd_w_128:
10411 case Intrinsic::x86_ssse3_phadd_d_128:
10412 case Intrinsic::x86_avx2_phadd_w:
10413 case Intrinsic::x86_avx2_phadd_d:
10414 Opcode = X86ISD::HADD;
10416 case Intrinsic::x86_ssse3_phsub_w_128:
10417 case Intrinsic::x86_ssse3_phsub_d_128:
10418 case Intrinsic::x86_avx2_phsub_w:
10419 case Intrinsic::x86_avx2_phsub_d:
10420 Opcode = X86ISD::HSUB;
10423 return DAG.getNode(Opcode, dl, Op.getValueType(),
10424 Op.getOperand(1), Op.getOperand(2));
10427 // SSE2/SSE41/AVX2 integer max/min intrinsics.
10428 case Intrinsic::x86_sse2_pmaxu_b:
10429 case Intrinsic::x86_sse41_pmaxuw:
10430 case Intrinsic::x86_sse41_pmaxud:
10431 case Intrinsic::x86_avx2_pmaxu_b:
10432 case Intrinsic::x86_avx2_pmaxu_w:
10433 case Intrinsic::x86_avx2_pmaxu_d:
10434 case Intrinsic::x86_sse2_pminu_b:
10435 case Intrinsic::x86_sse41_pminuw:
10436 case Intrinsic::x86_sse41_pminud:
10437 case Intrinsic::x86_avx2_pminu_b:
10438 case Intrinsic::x86_avx2_pminu_w:
10439 case Intrinsic::x86_avx2_pminu_d:
10440 case Intrinsic::x86_sse41_pmaxsb:
10441 case Intrinsic::x86_sse2_pmaxs_w:
10442 case Intrinsic::x86_sse41_pmaxsd:
10443 case Intrinsic::x86_avx2_pmaxs_b:
10444 case Intrinsic::x86_avx2_pmaxs_w:
10445 case Intrinsic::x86_avx2_pmaxs_d:
10446 case Intrinsic::x86_sse41_pminsb:
10447 case Intrinsic::x86_sse2_pmins_w:
10448 case Intrinsic::x86_sse41_pminsd:
10449 case Intrinsic::x86_avx2_pmins_b:
10450 case Intrinsic::x86_avx2_pmins_w:
10451 case Intrinsic::x86_avx2_pmins_d: {
10454 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10455 case Intrinsic::x86_sse2_pmaxu_b:
10456 case Intrinsic::x86_sse41_pmaxuw:
10457 case Intrinsic::x86_sse41_pmaxud:
10458 case Intrinsic::x86_avx2_pmaxu_b:
10459 case Intrinsic::x86_avx2_pmaxu_w:
10460 case Intrinsic::x86_avx2_pmaxu_d:
10461 Opcode = X86ISD::UMAX;
10463 case Intrinsic::x86_sse2_pminu_b:
10464 case Intrinsic::x86_sse41_pminuw:
10465 case Intrinsic::x86_sse41_pminud:
10466 case Intrinsic::x86_avx2_pminu_b:
10467 case Intrinsic::x86_avx2_pminu_w:
10468 case Intrinsic::x86_avx2_pminu_d:
10469 Opcode = X86ISD::UMIN;
10471 case Intrinsic::x86_sse41_pmaxsb:
10472 case Intrinsic::x86_sse2_pmaxs_w:
10473 case Intrinsic::x86_sse41_pmaxsd:
10474 case Intrinsic::x86_avx2_pmaxs_b:
10475 case Intrinsic::x86_avx2_pmaxs_w:
10476 case Intrinsic::x86_avx2_pmaxs_d:
10477 Opcode = X86ISD::SMAX;
10479 case Intrinsic::x86_sse41_pminsb:
10480 case Intrinsic::x86_sse2_pmins_w:
10481 case Intrinsic::x86_sse41_pminsd:
10482 case Intrinsic::x86_avx2_pmins_b:
10483 case Intrinsic::x86_avx2_pmins_w:
10484 case Intrinsic::x86_avx2_pmins_d:
10485 Opcode = X86ISD::SMIN;
10488 return DAG.getNode(Opcode, dl, Op.getValueType(),
10489 Op.getOperand(1), Op.getOperand(2));
10492 // SSE/SSE2/AVX floating point max/min intrinsics.
10493 case Intrinsic::x86_sse_max_ps:
10494 case Intrinsic::x86_sse2_max_pd:
10495 case Intrinsic::x86_avx_max_ps_256:
10496 case Intrinsic::x86_avx_max_pd_256:
10497 case Intrinsic::x86_sse_min_ps:
10498 case Intrinsic::x86_sse2_min_pd:
10499 case Intrinsic::x86_avx_min_ps_256:
10500 case Intrinsic::x86_avx_min_pd_256: {
10503 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10504 case Intrinsic::x86_sse_max_ps:
10505 case Intrinsic::x86_sse2_max_pd:
10506 case Intrinsic::x86_avx_max_ps_256:
10507 case Intrinsic::x86_avx_max_pd_256:
10508 Opcode = X86ISD::FMAX;
10510 case Intrinsic::x86_sse_min_ps:
10511 case Intrinsic::x86_sse2_min_pd:
10512 case Intrinsic::x86_avx_min_ps_256:
10513 case Intrinsic::x86_avx_min_pd_256:
10514 Opcode = X86ISD::FMIN;
10517 return DAG.getNode(Opcode, dl, Op.getValueType(),
10518 Op.getOperand(1), Op.getOperand(2));
10521 // AVX2 variable shift intrinsics
10522 case Intrinsic::x86_avx2_psllv_d:
10523 case Intrinsic::x86_avx2_psllv_q:
10524 case Intrinsic::x86_avx2_psllv_d_256:
10525 case Intrinsic::x86_avx2_psllv_q_256:
10526 case Intrinsic::x86_avx2_psrlv_d:
10527 case Intrinsic::x86_avx2_psrlv_q:
10528 case Intrinsic::x86_avx2_psrlv_d_256:
10529 case Intrinsic::x86_avx2_psrlv_q_256:
10530 case Intrinsic::x86_avx2_psrav_d:
10531 case Intrinsic::x86_avx2_psrav_d_256: {
10534 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10535 case Intrinsic::x86_avx2_psllv_d:
10536 case Intrinsic::x86_avx2_psllv_q:
10537 case Intrinsic::x86_avx2_psllv_d_256:
10538 case Intrinsic::x86_avx2_psllv_q_256:
10541 case Intrinsic::x86_avx2_psrlv_d:
10542 case Intrinsic::x86_avx2_psrlv_q:
10543 case Intrinsic::x86_avx2_psrlv_d_256:
10544 case Intrinsic::x86_avx2_psrlv_q_256:
10547 case Intrinsic::x86_avx2_psrav_d:
10548 case Intrinsic::x86_avx2_psrav_d_256:
10552 return DAG.getNode(Opcode, dl, Op.getValueType(),
10553 Op.getOperand(1), Op.getOperand(2));
10556 case Intrinsic::x86_ssse3_pshuf_b_128:
10557 case Intrinsic::x86_avx2_pshuf_b:
10558 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10559 Op.getOperand(1), Op.getOperand(2));
10561 case Intrinsic::x86_ssse3_psign_b_128:
10562 case Intrinsic::x86_ssse3_psign_w_128:
10563 case Intrinsic::x86_ssse3_psign_d_128:
10564 case Intrinsic::x86_avx2_psign_b:
10565 case Intrinsic::x86_avx2_psign_w:
10566 case Intrinsic::x86_avx2_psign_d:
10567 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10568 Op.getOperand(1), Op.getOperand(2));
10570 case Intrinsic::x86_sse41_insertps:
10571 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10572 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10574 case Intrinsic::x86_avx_vperm2f128_ps_256:
10575 case Intrinsic::x86_avx_vperm2f128_pd_256:
10576 case Intrinsic::x86_avx_vperm2f128_si_256:
10577 case Intrinsic::x86_avx2_vperm2i128:
10578 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10579 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10581 case Intrinsic::x86_avx2_permd:
10582 case Intrinsic::x86_avx2_permps:
10583 // Operands intentionally swapped. Mask is last operand to intrinsic,
10584 // but second operand for node/intruction.
10585 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10586 Op.getOperand(2), Op.getOperand(1));
10588 case Intrinsic::x86_sse_sqrt_ps:
10589 case Intrinsic::x86_sse2_sqrt_pd:
10590 case Intrinsic::x86_avx_sqrt_ps_256:
10591 case Intrinsic::x86_avx_sqrt_pd_256:
10592 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
10594 // ptest and testp intrinsics. The intrinsic these come from are designed to
10595 // return an integer value, not just an instruction so lower it to the ptest
10596 // or testp pattern and a setcc for the result.
10597 case Intrinsic::x86_sse41_ptestz:
10598 case Intrinsic::x86_sse41_ptestc:
10599 case Intrinsic::x86_sse41_ptestnzc:
10600 case Intrinsic::x86_avx_ptestz_256:
10601 case Intrinsic::x86_avx_ptestc_256:
10602 case Intrinsic::x86_avx_ptestnzc_256:
10603 case Intrinsic::x86_avx_vtestz_ps:
10604 case Intrinsic::x86_avx_vtestc_ps:
10605 case Intrinsic::x86_avx_vtestnzc_ps:
10606 case Intrinsic::x86_avx_vtestz_pd:
10607 case Intrinsic::x86_avx_vtestc_pd:
10608 case Intrinsic::x86_avx_vtestnzc_pd:
10609 case Intrinsic::x86_avx_vtestz_ps_256:
10610 case Intrinsic::x86_avx_vtestc_ps_256:
10611 case Intrinsic::x86_avx_vtestnzc_ps_256:
10612 case Intrinsic::x86_avx_vtestz_pd_256:
10613 case Intrinsic::x86_avx_vtestc_pd_256:
10614 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10615 bool IsTestPacked = false;
10618 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10619 case Intrinsic::x86_avx_vtestz_ps:
10620 case Intrinsic::x86_avx_vtestz_pd:
10621 case Intrinsic::x86_avx_vtestz_ps_256:
10622 case Intrinsic::x86_avx_vtestz_pd_256:
10623 IsTestPacked = true; // Fallthrough
10624 case Intrinsic::x86_sse41_ptestz:
10625 case Intrinsic::x86_avx_ptestz_256:
10627 X86CC = X86::COND_E;
10629 case Intrinsic::x86_avx_vtestc_ps:
10630 case Intrinsic::x86_avx_vtestc_pd:
10631 case Intrinsic::x86_avx_vtestc_ps_256:
10632 case Intrinsic::x86_avx_vtestc_pd_256:
10633 IsTestPacked = true; // Fallthrough
10634 case Intrinsic::x86_sse41_ptestc:
10635 case Intrinsic::x86_avx_ptestc_256:
10637 X86CC = X86::COND_B;
10639 case Intrinsic::x86_avx_vtestnzc_ps:
10640 case Intrinsic::x86_avx_vtestnzc_pd:
10641 case Intrinsic::x86_avx_vtestnzc_ps_256:
10642 case Intrinsic::x86_avx_vtestnzc_pd_256:
10643 IsTestPacked = true; // Fallthrough
10644 case Intrinsic::x86_sse41_ptestnzc:
10645 case Intrinsic::x86_avx_ptestnzc_256:
10647 X86CC = X86::COND_A;
10651 SDValue LHS = Op.getOperand(1);
10652 SDValue RHS = Op.getOperand(2);
10653 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
10654 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
10655 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
10656 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10657 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10660 // SSE/AVX shift intrinsics
10661 case Intrinsic::x86_sse2_psll_w:
10662 case Intrinsic::x86_sse2_psll_d:
10663 case Intrinsic::x86_sse2_psll_q:
10664 case Intrinsic::x86_avx2_psll_w:
10665 case Intrinsic::x86_avx2_psll_d:
10666 case Intrinsic::x86_avx2_psll_q:
10667 case Intrinsic::x86_sse2_psrl_w:
10668 case Intrinsic::x86_sse2_psrl_d:
10669 case Intrinsic::x86_sse2_psrl_q:
10670 case Intrinsic::x86_avx2_psrl_w:
10671 case Intrinsic::x86_avx2_psrl_d:
10672 case Intrinsic::x86_avx2_psrl_q:
10673 case Intrinsic::x86_sse2_psra_w:
10674 case Intrinsic::x86_sse2_psra_d:
10675 case Intrinsic::x86_avx2_psra_w:
10676 case Intrinsic::x86_avx2_psra_d: {
10679 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10680 case Intrinsic::x86_sse2_psll_w:
10681 case Intrinsic::x86_sse2_psll_d:
10682 case Intrinsic::x86_sse2_psll_q:
10683 case Intrinsic::x86_avx2_psll_w:
10684 case Intrinsic::x86_avx2_psll_d:
10685 case Intrinsic::x86_avx2_psll_q:
10686 Opcode = X86ISD::VSHL;
10688 case Intrinsic::x86_sse2_psrl_w:
10689 case Intrinsic::x86_sse2_psrl_d:
10690 case Intrinsic::x86_sse2_psrl_q:
10691 case Intrinsic::x86_avx2_psrl_w:
10692 case Intrinsic::x86_avx2_psrl_d:
10693 case Intrinsic::x86_avx2_psrl_q:
10694 Opcode = X86ISD::VSRL;
10696 case Intrinsic::x86_sse2_psra_w:
10697 case Intrinsic::x86_sse2_psra_d:
10698 case Intrinsic::x86_avx2_psra_w:
10699 case Intrinsic::x86_avx2_psra_d:
10700 Opcode = X86ISD::VSRA;
10703 return DAG.getNode(Opcode, dl, Op.getValueType(),
10704 Op.getOperand(1), Op.getOperand(2));
10707 // SSE/AVX immediate shift intrinsics
10708 case Intrinsic::x86_sse2_pslli_w:
10709 case Intrinsic::x86_sse2_pslli_d:
10710 case Intrinsic::x86_sse2_pslli_q:
10711 case Intrinsic::x86_avx2_pslli_w:
10712 case Intrinsic::x86_avx2_pslli_d:
10713 case Intrinsic::x86_avx2_pslli_q:
10714 case Intrinsic::x86_sse2_psrli_w:
10715 case Intrinsic::x86_sse2_psrli_d:
10716 case Intrinsic::x86_sse2_psrli_q:
10717 case Intrinsic::x86_avx2_psrli_w:
10718 case Intrinsic::x86_avx2_psrli_d:
10719 case Intrinsic::x86_avx2_psrli_q:
10720 case Intrinsic::x86_sse2_psrai_w:
10721 case Intrinsic::x86_sse2_psrai_d:
10722 case Intrinsic::x86_avx2_psrai_w:
10723 case Intrinsic::x86_avx2_psrai_d: {
10726 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10727 case Intrinsic::x86_sse2_pslli_w:
10728 case Intrinsic::x86_sse2_pslli_d:
10729 case Intrinsic::x86_sse2_pslli_q:
10730 case Intrinsic::x86_avx2_pslli_w:
10731 case Intrinsic::x86_avx2_pslli_d:
10732 case Intrinsic::x86_avx2_pslli_q:
10733 Opcode = X86ISD::VSHLI;
10735 case Intrinsic::x86_sse2_psrli_w:
10736 case Intrinsic::x86_sse2_psrli_d:
10737 case Intrinsic::x86_sse2_psrli_q:
10738 case Intrinsic::x86_avx2_psrli_w:
10739 case Intrinsic::x86_avx2_psrli_d:
10740 case Intrinsic::x86_avx2_psrli_q:
10741 Opcode = X86ISD::VSRLI;
10743 case Intrinsic::x86_sse2_psrai_w:
10744 case Intrinsic::x86_sse2_psrai_d:
10745 case Intrinsic::x86_avx2_psrai_w:
10746 case Intrinsic::x86_avx2_psrai_d:
10747 Opcode = X86ISD::VSRAI;
10750 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
10751 Op.getOperand(1), Op.getOperand(2), DAG);
10754 case Intrinsic::x86_sse42_pcmpistria128:
10755 case Intrinsic::x86_sse42_pcmpestria128:
10756 case Intrinsic::x86_sse42_pcmpistric128:
10757 case Intrinsic::x86_sse42_pcmpestric128:
10758 case Intrinsic::x86_sse42_pcmpistrio128:
10759 case Intrinsic::x86_sse42_pcmpestrio128:
10760 case Intrinsic::x86_sse42_pcmpistris128:
10761 case Intrinsic::x86_sse42_pcmpestris128:
10762 case Intrinsic::x86_sse42_pcmpistriz128:
10763 case Intrinsic::x86_sse42_pcmpestriz128: {
10767 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10768 case Intrinsic::x86_sse42_pcmpistria128:
10769 Opcode = X86ISD::PCMPISTRI;
10770 X86CC = X86::COND_A;
10772 case Intrinsic::x86_sse42_pcmpestria128:
10773 Opcode = X86ISD::PCMPESTRI;
10774 X86CC = X86::COND_A;
10776 case Intrinsic::x86_sse42_pcmpistric128:
10777 Opcode = X86ISD::PCMPISTRI;
10778 X86CC = X86::COND_B;
10780 case Intrinsic::x86_sse42_pcmpestric128:
10781 Opcode = X86ISD::PCMPESTRI;
10782 X86CC = X86::COND_B;
10784 case Intrinsic::x86_sse42_pcmpistrio128:
10785 Opcode = X86ISD::PCMPISTRI;
10786 X86CC = X86::COND_O;
10788 case Intrinsic::x86_sse42_pcmpestrio128:
10789 Opcode = X86ISD::PCMPESTRI;
10790 X86CC = X86::COND_O;
10792 case Intrinsic::x86_sse42_pcmpistris128:
10793 Opcode = X86ISD::PCMPISTRI;
10794 X86CC = X86::COND_S;
10796 case Intrinsic::x86_sse42_pcmpestris128:
10797 Opcode = X86ISD::PCMPESTRI;
10798 X86CC = X86::COND_S;
10800 case Intrinsic::x86_sse42_pcmpistriz128:
10801 Opcode = X86ISD::PCMPISTRI;
10802 X86CC = X86::COND_E;
10804 case Intrinsic::x86_sse42_pcmpestriz128:
10805 Opcode = X86ISD::PCMPESTRI;
10806 X86CC = X86::COND_E;
10809 SmallVector<SDValue, 5> NewOps;
10810 NewOps.append(Op->op_begin()+1, Op->op_end());
10811 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10812 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10813 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10814 DAG.getConstant(X86CC, MVT::i8),
10815 SDValue(PCMP.getNode(), 1));
10816 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10819 case Intrinsic::x86_sse42_pcmpistri128:
10820 case Intrinsic::x86_sse42_pcmpestri128: {
10822 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10823 Opcode = X86ISD::PCMPISTRI;
10825 Opcode = X86ISD::PCMPESTRI;
10827 SmallVector<SDValue, 5> NewOps;
10828 NewOps.append(Op->op_begin()+1, Op->op_end());
10829 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10830 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10832 case Intrinsic::x86_fma_vfmadd_ps:
10833 case Intrinsic::x86_fma_vfmadd_pd:
10834 case Intrinsic::x86_fma_vfmsub_ps:
10835 case Intrinsic::x86_fma_vfmsub_pd:
10836 case Intrinsic::x86_fma_vfnmadd_ps:
10837 case Intrinsic::x86_fma_vfnmadd_pd:
10838 case Intrinsic::x86_fma_vfnmsub_ps:
10839 case Intrinsic::x86_fma_vfnmsub_pd:
10840 case Intrinsic::x86_fma_vfmaddsub_ps:
10841 case Intrinsic::x86_fma_vfmaddsub_pd:
10842 case Intrinsic::x86_fma_vfmsubadd_ps:
10843 case Intrinsic::x86_fma_vfmsubadd_pd:
10844 case Intrinsic::x86_fma_vfmadd_ps_256:
10845 case Intrinsic::x86_fma_vfmadd_pd_256:
10846 case Intrinsic::x86_fma_vfmsub_ps_256:
10847 case Intrinsic::x86_fma_vfmsub_pd_256:
10848 case Intrinsic::x86_fma_vfnmadd_ps_256:
10849 case Intrinsic::x86_fma_vfnmadd_pd_256:
10850 case Intrinsic::x86_fma_vfnmsub_ps_256:
10851 case Intrinsic::x86_fma_vfnmsub_pd_256:
10852 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10853 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10854 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10855 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10858 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10859 case Intrinsic::x86_fma_vfmadd_ps:
10860 case Intrinsic::x86_fma_vfmadd_pd:
10861 case Intrinsic::x86_fma_vfmadd_ps_256:
10862 case Intrinsic::x86_fma_vfmadd_pd_256:
10863 Opc = X86ISD::FMADD;
10865 case Intrinsic::x86_fma_vfmsub_ps:
10866 case Intrinsic::x86_fma_vfmsub_pd:
10867 case Intrinsic::x86_fma_vfmsub_ps_256:
10868 case Intrinsic::x86_fma_vfmsub_pd_256:
10869 Opc = X86ISD::FMSUB;
10871 case Intrinsic::x86_fma_vfnmadd_ps:
10872 case Intrinsic::x86_fma_vfnmadd_pd:
10873 case Intrinsic::x86_fma_vfnmadd_ps_256:
10874 case Intrinsic::x86_fma_vfnmadd_pd_256:
10875 Opc = X86ISD::FNMADD;
10877 case Intrinsic::x86_fma_vfnmsub_ps:
10878 case Intrinsic::x86_fma_vfnmsub_pd:
10879 case Intrinsic::x86_fma_vfnmsub_ps_256:
10880 case Intrinsic::x86_fma_vfnmsub_pd_256:
10881 Opc = X86ISD::FNMSUB;
10883 case Intrinsic::x86_fma_vfmaddsub_ps:
10884 case Intrinsic::x86_fma_vfmaddsub_pd:
10885 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10886 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10887 Opc = X86ISD::FMADDSUB;
10889 case Intrinsic::x86_fma_vfmsubadd_ps:
10890 case Intrinsic::x86_fma_vfmsubadd_pd:
10891 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10892 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10893 Opc = X86ISD::FMSUBADD;
10897 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10898 Op.getOperand(2), Op.getOperand(3));
10903 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
10904 DebugLoc dl = Op.getDebugLoc();
10905 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10907 default: return SDValue(); // Don't custom lower most intrinsics.
10909 // RDRAND intrinsics.
10910 case Intrinsic::x86_rdrand_16:
10911 case Intrinsic::x86_rdrand_32:
10912 case Intrinsic::x86_rdrand_64: {
10913 // Emit the node with the right value type.
10914 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10915 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10917 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
10918 // return the value from Rand, which is always 0, casted to i32.
10919 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10920 DAG.getConstant(1, Op->getValueType(1)),
10921 DAG.getConstant(X86::COND_B, MVT::i32),
10922 SDValue(Result.getNode(), 1) };
10923 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10924 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10927 // Return { result, isValid, chain }.
10928 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10929 SDValue(Result.getNode(), 2));
10934 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
10935 SelectionDAG &DAG) const {
10936 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10937 MFI->setReturnAddressIsTaken(true);
10939 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10940 DebugLoc dl = Op.getDebugLoc();
10941 EVT PtrVT = getPointerTy();
10944 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10946 DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
10947 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10948 DAG.getNode(ISD::ADD, dl, PtrVT,
10949 FrameAddr, Offset),
10950 MachinePointerInfo(), false, false, false, 0);
10953 // Just load the return address.
10954 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
10955 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10956 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10959 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
10960 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10961 MFI->setFrameAddressIsTaken(true);
10963 EVT VT = Op.getValueType();
10964 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
10965 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10966 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
10967 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
10969 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
10970 MachinePointerInfo(),
10971 false, false, false, 0);
10975 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
10976 SelectionDAG &DAG) const {
10977 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
10980 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
10981 SDValue Chain = Op.getOperand(0);
10982 SDValue Offset = Op.getOperand(1);
10983 SDValue Handler = Op.getOperand(2);
10984 DebugLoc dl = Op.getDebugLoc();
10986 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
10987 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
10989 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
10991 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
10992 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
10993 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
10994 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
10996 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
10998 return DAG.getNode(X86ISD::EH_RETURN, dl,
11000 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
11003 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
11004 SelectionDAG &DAG) const {
11005 DebugLoc DL = Op.getDebugLoc();
11006 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
11007 DAG.getVTList(MVT::i32, MVT::Other),
11008 Op.getOperand(0), Op.getOperand(1));
11011 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
11012 SelectionDAG &DAG) const {
11013 DebugLoc DL = Op.getDebugLoc();
11014 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
11015 Op.getOperand(0), Op.getOperand(1));
11018 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
11019 return Op.getOperand(0);
11022 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
11023 SelectionDAG &DAG) const {
11024 SDValue Root = Op.getOperand(0);
11025 SDValue Trmp = Op.getOperand(1); // trampoline
11026 SDValue FPtr = Op.getOperand(2); // nested function
11027 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
11028 DebugLoc dl = Op.getDebugLoc();
11030 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11031 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
11033 if (Subtarget->is64Bit()) {
11034 SDValue OutChains[6];
11036 // Large code-model.
11037 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11038 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11040 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
11041 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
11043 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
11045 // Load the pointer to the nested function into R11.
11046 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11047 SDValue Addr = Trmp;
11048 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11049 Addr, MachinePointerInfo(TrmpAddr),
11052 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11053 DAG.getConstant(2, MVT::i64));
11054 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11055 MachinePointerInfo(TrmpAddr, 2),
11058 // Load the 'nest' parameter value into R10.
11059 // R10 is specified in X86CallingConv.td
11060 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11061 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11062 DAG.getConstant(10, MVT::i64));
11063 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11064 Addr, MachinePointerInfo(TrmpAddr, 10),
11067 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11068 DAG.getConstant(12, MVT::i64));
11069 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11070 MachinePointerInfo(TrmpAddr, 12),
11073 // Jump to the nested function.
11074 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11075 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11076 DAG.getConstant(20, MVT::i64));
11077 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11078 Addr, MachinePointerInfo(TrmpAddr, 20),
11081 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11082 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11083 DAG.getConstant(22, MVT::i64));
11084 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11085 MachinePointerInfo(TrmpAddr, 22),
11088 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11090 const Function *Func =
11091 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11092 CallingConv::ID CC = Func->getCallingConv();
11097 llvm_unreachable("Unsupported calling convention");
11098 case CallingConv::C:
11099 case CallingConv::X86_StdCall: {
11100 // Pass 'nest' parameter in ECX.
11101 // Must be kept in sync with X86CallingConv.td
11102 NestReg = X86::ECX;
11104 // Check that ECX wasn't needed by an 'inreg' parameter.
11105 FunctionType *FTy = Func->getFunctionType();
11106 const AttributeSet &Attrs = Func->getAttributes();
11108 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11109 unsigned InRegCount = 0;
11112 for (FunctionType::param_iterator I = FTy->param_begin(),
11113 E = FTy->param_end(); I != E; ++I, ++Idx)
11114 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11115 // FIXME: should only count parameters that are lowered to integers.
11116 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11118 if (InRegCount > 2) {
11119 report_fatal_error("Nest register in use - reduce number of inreg"
11125 case CallingConv::X86_FastCall:
11126 case CallingConv::X86_ThisCall:
11127 case CallingConv::Fast:
11128 // Pass 'nest' parameter in EAX.
11129 // Must be kept in sync with X86CallingConv.td
11130 NestReg = X86::EAX;
11134 SDValue OutChains[4];
11135 SDValue Addr, Disp;
11137 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11138 DAG.getConstant(10, MVT::i32));
11139 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11141 // This is storing the opcode for MOV32ri.
11142 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11143 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11144 OutChains[0] = DAG.getStore(Root, dl,
11145 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11146 Trmp, MachinePointerInfo(TrmpAddr),
11149 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11150 DAG.getConstant(1, MVT::i32));
11151 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11152 MachinePointerInfo(TrmpAddr, 1),
11155 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11156 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11157 DAG.getConstant(5, MVT::i32));
11158 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11159 MachinePointerInfo(TrmpAddr, 5),
11162 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11163 DAG.getConstant(6, MVT::i32));
11164 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11165 MachinePointerInfo(TrmpAddr, 6),
11168 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11172 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11173 SelectionDAG &DAG) const {
11175 The rounding mode is in bits 11:10 of FPSR, and has the following
11177 00 Round to nearest
11182 FLT_ROUNDS, on the other hand, expects the following:
11189 To perform the conversion, we do:
11190 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11193 MachineFunction &MF = DAG.getMachineFunction();
11194 const TargetMachine &TM = MF.getTarget();
11195 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11196 unsigned StackAlignment = TFI.getStackAlignment();
11197 EVT VT = Op.getValueType();
11198 DebugLoc DL = Op.getDebugLoc();
11200 // Save FP Control Word to stack slot
11201 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11202 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11204 MachineMemOperand *MMO =
11205 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11206 MachineMemOperand::MOStore, 2, 2);
11208 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11209 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11210 DAG.getVTList(MVT::Other),
11211 Ops, 2, MVT::i16, MMO);
11213 // Load FP Control Word from stack slot
11214 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11215 MachinePointerInfo(), false, false, false, 0);
11217 // Transform as necessary
11219 DAG.getNode(ISD::SRL, DL, MVT::i16,
11220 DAG.getNode(ISD::AND, DL, MVT::i16,
11221 CWD, DAG.getConstant(0x800, MVT::i16)),
11222 DAG.getConstant(11, MVT::i8));
11224 DAG.getNode(ISD::SRL, DL, MVT::i16,
11225 DAG.getNode(ISD::AND, DL, MVT::i16,
11226 CWD, DAG.getConstant(0x400, MVT::i16)),
11227 DAG.getConstant(9, MVT::i8));
11230 DAG.getNode(ISD::AND, DL, MVT::i16,
11231 DAG.getNode(ISD::ADD, DL, MVT::i16,
11232 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11233 DAG.getConstant(1, MVT::i16)),
11234 DAG.getConstant(3, MVT::i16));
11236 return DAG.getNode((VT.getSizeInBits() < 16 ?
11237 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11240 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11241 EVT VT = Op.getValueType();
11243 unsigned NumBits = VT.getSizeInBits();
11244 DebugLoc dl = Op.getDebugLoc();
11246 Op = Op.getOperand(0);
11247 if (VT == MVT::i8) {
11248 // Zero extend to i32 since there is not an i8 bsr.
11250 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11253 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11254 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11255 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11257 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11260 DAG.getConstant(NumBits+NumBits-1, OpVT),
11261 DAG.getConstant(X86::COND_E, MVT::i8),
11264 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11266 // Finally xor with NumBits-1.
11267 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11270 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11274 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11275 EVT VT = Op.getValueType();
11277 unsigned NumBits = VT.getSizeInBits();
11278 DebugLoc dl = Op.getDebugLoc();
11280 Op = Op.getOperand(0);
11281 if (VT == MVT::i8) {
11282 // Zero extend to i32 since there is not an i8 bsr.
11284 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11287 // Issue a bsr (scan bits in reverse).
11288 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11289 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11291 // And xor with NumBits-1.
11292 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11295 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11299 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11300 EVT VT = Op.getValueType();
11301 unsigned NumBits = VT.getSizeInBits();
11302 DebugLoc dl = Op.getDebugLoc();
11303 Op = Op.getOperand(0);
11305 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11306 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11307 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11309 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11312 DAG.getConstant(NumBits, VT),
11313 DAG.getConstant(X86::COND_E, MVT::i8),
11316 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11319 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11320 // ones, and then concatenate the result back.
11321 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11322 EVT VT = Op.getValueType();
11324 assert(VT.is256BitVector() && VT.isInteger() &&
11325 "Unsupported value type for operation");
11327 unsigned NumElems = VT.getVectorNumElements();
11328 DebugLoc dl = Op.getDebugLoc();
11330 // Extract the LHS vectors
11331 SDValue LHS = Op.getOperand(0);
11332 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11333 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11335 // Extract the RHS vectors
11336 SDValue RHS = Op.getOperand(1);
11337 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11338 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11340 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11341 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11343 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11344 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11345 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11348 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
11349 assert(Op.getValueType().is256BitVector() &&
11350 Op.getValueType().isInteger() &&
11351 "Only handle AVX 256-bit vector integer operation");
11352 return Lower256IntArith(Op, DAG);
11355 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
11356 assert(Op.getValueType().is256BitVector() &&
11357 Op.getValueType().isInteger() &&
11358 "Only handle AVX 256-bit vector integer operation");
11359 return Lower256IntArith(Op, DAG);
11362 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
11363 SelectionDAG &DAG) {
11364 DebugLoc dl = Op.getDebugLoc();
11365 EVT VT = Op.getValueType();
11367 // Decompose 256-bit ops into smaller 128-bit ops.
11368 if (VT.is256BitVector() && !Subtarget->hasInt256())
11369 return Lower256IntArith(Op, DAG);
11371 SDValue A = Op.getOperand(0);
11372 SDValue B = Op.getOperand(1);
11374 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
11375 if (VT == MVT::v4i32) {
11376 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
11377 "Should not custom lower when pmuldq is available!");
11379 // Extract the odd parts.
11380 const int UnpackMask[] = { 1, -1, 3, -1 };
11381 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
11382 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
11384 // Multiply the even parts.
11385 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
11386 // Now multiply odd parts.
11387 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
11389 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
11390 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
11392 // Merge the two vectors back together with a shuffle. This expands into 2
11394 const int ShufMask[] = { 0, 4, 2, 6 };
11395 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
11398 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11399 "Only know how to lower V2I64/V4I64 multiply");
11401 // Ahi = psrlqi(a, 32);
11402 // Bhi = psrlqi(b, 32);
11404 // AloBlo = pmuludq(a, b);
11405 // AloBhi = pmuludq(a, Bhi);
11406 // AhiBlo = pmuludq(Ahi, b);
11408 // AloBhi = psllqi(AloBhi, 32);
11409 // AhiBlo = psllqi(AhiBlo, 32);
11410 // return AloBlo + AloBhi + AhiBlo;
11412 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11414 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11415 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11417 // Bit cast to 32-bit vectors for MULUDQ
11418 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11419 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11420 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11421 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11422 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11424 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11425 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11426 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11428 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11429 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11431 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11432 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11435 SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
11436 EVT VT = Op.getValueType();
11437 EVT EltTy = VT.getVectorElementType();
11438 unsigned NumElts = VT.getVectorNumElements();
11439 SDValue N0 = Op.getOperand(0);
11440 DebugLoc dl = Op.getDebugLoc();
11442 // Lower sdiv X, pow2-const.
11443 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
11447 APInt SplatValue, SplatUndef;
11448 unsigned MinSplatBits;
11450 if (!C->isConstantSplat(SplatValue, SplatUndef, MinSplatBits, HasAnyUndefs))
11453 if ((SplatValue != 0) &&
11454 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
11455 unsigned lg2 = SplatValue.countTrailingZeros();
11456 // Splat the sign bit.
11457 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
11458 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
11459 // Add (N0 < 0) ? abs2 - 1 : 0;
11460 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
11461 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
11462 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
11463 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
11464 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
11466 // If we're dividing by a positive value, we're done. Otherwise, we must
11467 // negate the result.
11468 if (SplatValue.isNonNegative())
11471 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
11472 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
11473 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
11478 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
11480 EVT VT = Op.getValueType();
11481 DebugLoc dl = Op.getDebugLoc();
11482 SDValue R = Op.getOperand(0);
11483 SDValue Amt = Op.getOperand(1);
11485 if (!Subtarget->hasSSE2())
11488 // Optimize shl/srl/sra with constant shift amount.
11489 if (isSplatVector(Amt.getNode())) {
11490 SDValue SclrAmt = Amt->getOperand(0);
11491 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11492 uint64_t ShiftAmt = C->getZExtValue();
11494 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11495 (Subtarget->hasInt256() &&
11496 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11497 if (Op.getOpcode() == ISD::SHL)
11498 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11499 DAG.getConstant(ShiftAmt, MVT::i32));
11500 if (Op.getOpcode() == ISD::SRL)
11501 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11502 DAG.getConstant(ShiftAmt, MVT::i32));
11503 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11504 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11505 DAG.getConstant(ShiftAmt, MVT::i32));
11508 if (VT == MVT::v16i8) {
11509 if (Op.getOpcode() == ISD::SHL) {
11510 // Make a large shift.
11511 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11512 DAG.getConstant(ShiftAmt, MVT::i32));
11513 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11514 // Zero out the rightmost bits.
11515 SmallVector<SDValue, 16> V(16,
11516 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11518 return DAG.getNode(ISD::AND, dl, VT, SHL,
11519 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11521 if (Op.getOpcode() == ISD::SRL) {
11522 // Make a large shift.
11523 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11524 DAG.getConstant(ShiftAmt, MVT::i32));
11525 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11526 // Zero out the leftmost bits.
11527 SmallVector<SDValue, 16> V(16,
11528 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11530 return DAG.getNode(ISD::AND, dl, VT, SRL,
11531 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11533 if (Op.getOpcode() == ISD::SRA) {
11534 if (ShiftAmt == 7) {
11535 // R s>> 7 === R s< 0
11536 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11537 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11540 // R s>> a === ((R u>> a) ^ m) - m
11541 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11542 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11544 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11545 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11546 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11549 llvm_unreachable("Unknown shift opcode.");
11552 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11553 if (Op.getOpcode() == ISD::SHL) {
11554 // Make a large shift.
11555 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11556 DAG.getConstant(ShiftAmt, MVT::i32));
11557 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11558 // Zero out the rightmost bits.
11559 SmallVector<SDValue, 32> V(32,
11560 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11562 return DAG.getNode(ISD::AND, dl, VT, SHL,
11563 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11565 if (Op.getOpcode() == ISD::SRL) {
11566 // Make a large shift.
11567 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11568 DAG.getConstant(ShiftAmt, MVT::i32));
11569 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11570 // Zero out the leftmost bits.
11571 SmallVector<SDValue, 32> V(32,
11572 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11574 return DAG.getNode(ISD::AND, dl, VT, SRL,
11575 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11577 if (Op.getOpcode() == ISD::SRA) {
11578 if (ShiftAmt == 7) {
11579 // R s>> 7 === R s< 0
11580 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11581 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11584 // R s>> a === ((R u>> a) ^ m) - m
11585 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11586 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11588 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11589 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11590 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11593 llvm_unreachable("Unknown shift opcode.");
11598 // Lower SHL with variable shift amount.
11599 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11600 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
11602 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
11603 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11604 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11605 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11607 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11608 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
11611 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
11612 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11614 // Turn 'a' into a mask suitable for VSELECT
11615 SDValue VSelM = DAG.getConstant(0x80, VT);
11616 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11617 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11619 SDValue CM1 = DAG.getConstant(0x0f, VT);
11620 SDValue CM2 = DAG.getConstant(0x3f, VT);
11622 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
11623 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11624 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11625 DAG.getConstant(4, MVT::i32), DAG);
11626 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11627 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11630 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11631 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11632 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11634 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
11635 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11636 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11637 DAG.getConstant(2, MVT::i32), DAG);
11638 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11639 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11642 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11643 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11644 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11646 // return VSELECT(r, r+r, a);
11647 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11648 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11652 // Decompose 256-bit shifts into smaller 128-bit shifts.
11653 if (VT.is256BitVector()) {
11654 unsigned NumElems = VT.getVectorNumElements();
11655 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11656 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11658 // Extract the two vectors
11659 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
11660 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
11662 // Recreate the shift amount vectors
11663 SDValue Amt1, Amt2;
11664 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11665 // Constant shift amount
11666 SmallVector<SDValue, 4> Amt1Csts;
11667 SmallVector<SDValue, 4> Amt2Csts;
11668 for (unsigned i = 0; i != NumElems/2; ++i)
11669 Amt1Csts.push_back(Amt->getOperand(i));
11670 for (unsigned i = NumElems/2; i != NumElems; ++i)
11671 Amt2Csts.push_back(Amt->getOperand(i));
11673 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11674 &Amt1Csts[0], NumElems/2);
11675 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11676 &Amt2Csts[0], NumElems/2);
11678 // Variable shift amount
11679 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11680 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
11683 // Issue new vector shifts for the smaller types
11684 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11685 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11687 // Concatenate the result back
11688 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11694 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
11695 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
11696 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
11697 // looks for this combo and may remove the "setcc" instruction if the "setcc"
11698 // has only one use.
11699 SDNode *N = Op.getNode();
11700 SDValue LHS = N->getOperand(0);
11701 SDValue RHS = N->getOperand(1);
11702 unsigned BaseOp = 0;
11704 DebugLoc DL = Op.getDebugLoc();
11705 switch (Op.getOpcode()) {
11706 default: llvm_unreachable("Unknown ovf instruction!");
11708 // A subtract of one will be selected as a INC. Note that INC doesn't
11709 // set CF, so we can't do this for UADDO.
11710 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11712 BaseOp = X86ISD::INC;
11713 Cond = X86::COND_O;
11716 BaseOp = X86ISD::ADD;
11717 Cond = X86::COND_O;
11720 BaseOp = X86ISD::ADD;
11721 Cond = X86::COND_B;
11724 // A subtract of one will be selected as a DEC. Note that DEC doesn't
11725 // set CF, so we can't do this for USUBO.
11726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11728 BaseOp = X86ISD::DEC;
11729 Cond = X86::COND_O;
11732 BaseOp = X86ISD::SUB;
11733 Cond = X86::COND_O;
11736 BaseOp = X86ISD::SUB;
11737 Cond = X86::COND_B;
11740 BaseOp = X86ISD::SMUL;
11741 Cond = X86::COND_O;
11743 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
11744 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
11746 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
11749 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11750 DAG.getConstant(X86::COND_O, MVT::i32),
11751 SDValue(Sum.getNode(), 2));
11753 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11757 // Also sets EFLAGS.
11758 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
11759 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
11762 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
11763 DAG.getConstant(Cond, MVT::i32),
11764 SDValue(Sum.getNode(), 1));
11766 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11769 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
11770 SelectionDAG &DAG) const {
11771 DebugLoc dl = Op.getDebugLoc();
11772 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
11773 EVT VT = Op.getValueType();
11775 if (!Subtarget->hasSSE2() || !VT.isVector())
11778 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
11779 ExtraVT.getScalarType().getSizeInBits();
11780 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
11782 switch (VT.getSimpleVT().SimpleTy) {
11783 default: return SDValue();
11786 if (!Subtarget->hasFp256())
11788 if (!Subtarget->hasInt256()) {
11789 // needs to be split
11790 unsigned NumElems = VT.getVectorNumElements();
11792 // Extract the LHS vectors
11793 SDValue LHS = Op.getOperand(0);
11794 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11795 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11797 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11798 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11800 EVT ExtraEltVT = ExtraVT.getVectorElementType();
11801 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
11802 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
11804 SDValue Extra = DAG.getValueType(ExtraVT);
11806 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
11807 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
11809 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
11814 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
11815 Op.getOperand(0), ShAmt, DAG);
11816 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
11821 static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
11822 SelectionDAG &DAG) {
11823 DebugLoc dl = Op.getDebugLoc();
11825 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
11826 // There isn't any reason to disable it if the target processor supports it.
11827 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
11828 SDValue Chain = Op.getOperand(0);
11829 SDValue Zero = DAG.getConstant(0, MVT::i32);
11831 DAG.getRegister(X86::ESP, MVT::i32), // Base
11832 DAG.getTargetConstant(1, MVT::i8), // Scale
11833 DAG.getRegister(0, MVT::i32), // Index
11834 DAG.getTargetConstant(0, MVT::i32), // Disp
11835 DAG.getRegister(0, MVT::i32), // Segment.
11840 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11841 array_lengthof(Ops));
11842 return SDValue(Res, 0);
11845 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
11847 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11849 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11850 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11851 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
11852 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
11854 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
11855 if (!Op1 && !Op2 && !Op3 && Op4)
11856 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
11858 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
11859 if (Op1 && !Op2 && !Op3 && !Op4)
11860 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
11862 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
11864 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11867 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
11868 SelectionDAG &DAG) {
11869 DebugLoc dl = Op.getDebugLoc();
11870 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
11871 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
11872 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
11873 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
11875 // The only fence that needs an instruction is a sequentially-consistent
11876 // cross-thread fence.
11877 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
11878 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
11879 // no-sse2). There isn't any reason to disable it if the target processor
11881 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
11882 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11884 SDValue Chain = Op.getOperand(0);
11885 SDValue Zero = DAG.getConstant(0, MVT::i32);
11887 DAG.getRegister(X86::ESP, MVT::i32), // Base
11888 DAG.getTargetConstant(1, MVT::i8), // Scale
11889 DAG.getRegister(0, MVT::i32), // Index
11890 DAG.getTargetConstant(0, MVT::i32), // Disp
11891 DAG.getRegister(0, MVT::i32), // Segment.
11896 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11897 array_lengthof(Ops));
11898 return SDValue(Res, 0);
11901 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
11902 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11905 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
11906 SelectionDAG &DAG) {
11907 EVT T = Op.getValueType();
11908 DebugLoc DL = Op.getDebugLoc();
11911 switch(T.getSimpleVT().SimpleTy) {
11912 default: llvm_unreachable("Invalid value type!");
11913 case MVT::i8: Reg = X86::AL; size = 1; break;
11914 case MVT::i16: Reg = X86::AX; size = 2; break;
11915 case MVT::i32: Reg = X86::EAX; size = 4; break;
11917 assert(Subtarget->is64Bit() && "Node not type legal!");
11918 Reg = X86::RAX; size = 8;
11921 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
11922 Op.getOperand(2), SDValue());
11923 SDValue Ops[] = { cpIn.getValue(0),
11926 DAG.getTargetConstant(size, MVT::i8),
11927 cpIn.getValue(1) };
11928 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11929 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
11930 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11933 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11937 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
11938 SelectionDAG &DAG) {
11939 assert(Subtarget->is64Bit() && "Result not type legalized?");
11940 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11941 SDValue TheChain = Op.getOperand(0);
11942 DebugLoc dl = Op.getDebugLoc();
11943 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11944 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
11945 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
11947 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11948 DAG.getConstant(32, MVT::i8));
11950 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11953 return DAG.getMergeValues(Ops, 2, dl);
11956 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
11957 EVT SrcVT = Op.getOperand(0).getValueType();
11958 EVT DstVT = Op.getValueType();
11959 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
11960 Subtarget->hasMMX() && "Unexpected custom BITCAST");
11961 assert((DstVT == MVT::i64 ||
11962 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
11963 "Unexpected custom BITCAST");
11964 // i64 <=> MMX conversions are Legal.
11965 if (SrcVT==MVT::i64 && DstVT.isVector())
11967 if (DstVT==MVT::i64 && SrcVT.isVector())
11969 // MMX <=> MMX conversions are Legal.
11970 if (SrcVT.isVector() && DstVT.isVector())
11972 // All other conversions need to be expanded.
11976 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
11977 SDNode *Node = Op.getNode();
11978 DebugLoc dl = Node->getDebugLoc();
11979 EVT T = Node->getValueType(0);
11980 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11981 DAG.getConstant(0, T), Node->getOperand(2));
11982 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
11983 cast<AtomicSDNode>(Node)->getMemoryVT(),
11984 Node->getOperand(0),
11985 Node->getOperand(1), negOp,
11986 cast<AtomicSDNode>(Node)->getSrcValue(),
11987 cast<AtomicSDNode>(Node)->getAlignment(),
11988 cast<AtomicSDNode>(Node)->getOrdering(),
11989 cast<AtomicSDNode>(Node)->getSynchScope());
11992 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
11993 SDNode *Node = Op.getNode();
11994 DebugLoc dl = Node->getDebugLoc();
11995 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11997 // Convert seq_cst store -> xchg
11998 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
11999 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12000 // (The only way to get a 16-byte store is cmpxchg16b)
12001 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
12002 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
12003 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12004 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
12005 cast<AtomicSDNode>(Node)->getMemoryVT(),
12006 Node->getOperand(0),
12007 Node->getOperand(1), Node->getOperand(2),
12008 cast<AtomicSDNode>(Node)->getMemOperand(),
12009 cast<AtomicSDNode>(Node)->getOrdering(),
12010 cast<AtomicSDNode>(Node)->getSynchScope());
12011 return Swap.getValue(1);
12013 // Other atomic stores have a simple pattern.
12017 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
12018 EVT VT = Op.getNode()->getValueType(0);
12020 // Let legalize expand this if it isn't a legal type yet.
12021 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
12024 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12027 bool ExtraOp = false;
12028 switch (Op.getOpcode()) {
12029 default: llvm_unreachable("Invalid code");
12030 case ISD::ADDC: Opc = X86ISD::ADD; break;
12031 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12032 case ISD::SUBC: Opc = X86ISD::SUB; break;
12033 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12037 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
12039 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
12040 Op.getOperand(1), Op.getOperand(2));
12043 SDValue X86TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
12044 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
12046 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
12047 // which returns the values in two XMM registers.
12048 DebugLoc dl = Op.getDebugLoc();
12049 SDValue Arg = Op.getOperand(0);
12050 EVT ArgVT = Arg.getValueType();
12051 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
12054 ArgListEntry Entry;
12058 Entry.isSExt = false;
12059 Entry.isZExt = false;
12060 Args.push_back(Entry);
12062 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
12063 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12064 // the results are returned via SRet in memory.
12065 const char *LibcallName = (ArgVT == MVT::f64)
12066 ? "__sincos_stret" : "__sincosf_stret";
12067 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
12069 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
12071 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
12072 false, false, false, false, 0,
12073 CallingConv::C, /*isTaillCall=*/false,
12074 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
12075 Callee, Args, DAG, dl);
12076 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
12077 return CallResult.first;
12080 /// LowerOperation - Provide custom lowering hooks for some operations.
12082 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12083 switch (Op.getOpcode()) {
12084 default: llvm_unreachable("Should not custom lower this!");
12085 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12086 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
12087 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12088 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12089 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12090 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12091 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12092 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12093 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12094 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12095 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12096 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12097 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12098 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12099 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12100 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12101 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12102 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12103 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12104 case ISD::SHL_PARTS:
12105 case ISD::SRA_PARTS:
12106 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12107 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12108 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12109 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
12110 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
12111 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
12112 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
12113 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12114 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12115 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
12116 case ISD::FABS: return LowerFABS(Op, DAG);
12117 case ISD::FNEG: return LowerFNEG(Op, DAG);
12118 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12119 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12120 case ISD::SETCC: return LowerSETCC(Op, DAG);
12121 case ISD::SELECT: return LowerSELECT(Op, DAG);
12122 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12123 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12124 case ISD::VASTART: return LowerVASTART(Op, DAG);
12125 case ISD::VAARG: return LowerVAARG(Op, DAG);
12126 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12127 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12128 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12129 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12130 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12131 case ISD::FRAME_TO_ARGS_OFFSET:
12132 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12133 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12134 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12135 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12136 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12137 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12138 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12139 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12140 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12141 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12142 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12143 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12146 case ISD::SHL: return LowerShift(Op, DAG);
12152 case ISD::UMULO: return LowerXALUO(Op, DAG);
12153 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12154 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
12158 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
12159 case ISD::ADD: return LowerADD(Op, DAG);
12160 case ISD::SUB: return LowerSUB(Op, DAG);
12161 case ISD::SDIV: return LowerSDIV(Op, DAG);
12162 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
12166 static void ReplaceATOMIC_LOAD(SDNode *Node,
12167 SmallVectorImpl<SDValue> &Results,
12168 SelectionDAG &DAG) {
12169 DebugLoc dl = Node->getDebugLoc();
12170 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12172 // Convert wide load -> cmpxchg8b/cmpxchg16b
12173 // FIXME: On 32-bit, load -> fild or movq would be more efficient
12174 // (The only way to get a 16-byte load is cmpxchg16b)
12175 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
12176 SDValue Zero = DAG.getConstant(0, VT);
12177 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
12178 Node->getOperand(0),
12179 Node->getOperand(1), Zero, Zero,
12180 cast<AtomicSDNode>(Node)->getMemOperand(),
12181 cast<AtomicSDNode>(Node)->getOrdering(),
12182 cast<AtomicSDNode>(Node)->getSynchScope());
12183 Results.push_back(Swap.getValue(0));
12184 Results.push_back(Swap.getValue(1));
12188 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
12189 SelectionDAG &DAG, unsigned NewOp) {
12190 DebugLoc dl = Node->getDebugLoc();
12191 assert (Node->getValueType(0) == MVT::i64 &&
12192 "Only know how to expand i64 atomics");
12194 SDValue Chain = Node->getOperand(0);
12195 SDValue In1 = Node->getOperand(1);
12196 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12197 Node->getOperand(2), DAG.getIntPtrConstant(0));
12198 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12199 Node->getOperand(2), DAG.getIntPtrConstant(1));
12200 SDValue Ops[] = { Chain, In1, In2L, In2H };
12201 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
12203 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
12204 cast<MemSDNode>(Node)->getMemOperand());
12205 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
12206 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12207 Results.push_back(Result.getValue(2));
12210 /// ReplaceNodeResults - Replace a node with an illegal result type
12211 /// with a new node built out of custom code.
12212 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
12213 SmallVectorImpl<SDValue>&Results,
12214 SelectionDAG &DAG) const {
12215 DebugLoc dl = N->getDebugLoc();
12216 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12217 switch (N->getOpcode()) {
12219 llvm_unreachable("Do not know how to custom type legalize this operation!");
12220 case ISD::SIGN_EXTEND_INREG:
12225 // We don't want to expand or promote these.
12227 case ISD::FP_TO_SINT:
12228 case ISD::FP_TO_UINT: {
12229 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12231 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
12234 std::pair<SDValue,SDValue> Vals =
12235 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
12236 SDValue FIST = Vals.first, StackSlot = Vals.second;
12237 if (FIST.getNode() != 0) {
12238 EVT VT = N->getValueType(0);
12239 // Return a load from the stack slot.
12240 if (StackSlot.getNode() != 0)
12241 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
12242 MachinePointerInfo(),
12243 false, false, false, 0));
12245 Results.push_back(FIST);
12249 case ISD::UINT_TO_FP: {
12250 if (N->getOperand(0).getValueType() != MVT::v2i32 &&
12251 N->getValueType(0) != MVT::v2f32)
12253 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12255 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12257 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12258 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12259 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12260 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12261 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12262 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12265 case ISD::FP_ROUND: {
12266 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
12268 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
12269 Results.push_back(V);
12272 case ISD::READCYCLECOUNTER: {
12273 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12274 SDValue TheChain = N->getOperand(0);
12275 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12276 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12278 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12280 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12281 SDValue Ops[] = { eax, edx };
12282 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
12283 Results.push_back(edx.getValue(1));
12286 case ISD::ATOMIC_CMP_SWAP: {
12287 EVT T = N->getValueType(0);
12288 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
12289 bool Regs64bit = T == MVT::i128;
12290 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
12291 SDValue cpInL, cpInH;
12292 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12293 DAG.getConstant(0, HalfT));
12294 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12295 DAG.getConstant(1, HalfT));
12296 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
12297 Regs64bit ? X86::RAX : X86::EAX,
12299 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
12300 Regs64bit ? X86::RDX : X86::EDX,
12301 cpInH, cpInL.getValue(1));
12302 SDValue swapInL, swapInH;
12303 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12304 DAG.getConstant(0, HalfT));
12305 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12306 DAG.getConstant(1, HalfT));
12307 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
12308 Regs64bit ? X86::RBX : X86::EBX,
12309 swapInL, cpInH.getValue(1));
12310 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
12311 Regs64bit ? X86::RCX : X86::ECX,
12312 swapInH, swapInL.getValue(1));
12313 SDValue Ops[] = { swapInH.getValue(0),
12315 swapInH.getValue(1) };
12316 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12317 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
12318 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
12319 X86ISD::LCMPXCHG8_DAG;
12320 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
12322 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
12323 Regs64bit ? X86::RAX : X86::EAX,
12324 HalfT, Result.getValue(1));
12325 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
12326 Regs64bit ? X86::RDX : X86::EDX,
12327 HalfT, cpOutL.getValue(2));
12328 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
12329 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
12330 Results.push_back(cpOutH.getValue(1));
12333 case ISD::ATOMIC_LOAD_ADD:
12334 case ISD::ATOMIC_LOAD_AND:
12335 case ISD::ATOMIC_LOAD_NAND:
12336 case ISD::ATOMIC_LOAD_OR:
12337 case ISD::ATOMIC_LOAD_SUB:
12338 case ISD::ATOMIC_LOAD_XOR:
12339 case ISD::ATOMIC_LOAD_MAX:
12340 case ISD::ATOMIC_LOAD_MIN:
12341 case ISD::ATOMIC_LOAD_UMAX:
12342 case ISD::ATOMIC_LOAD_UMIN:
12343 case ISD::ATOMIC_SWAP: {
12345 switch (N->getOpcode()) {
12346 default: llvm_unreachable("Unexpected opcode");
12347 case ISD::ATOMIC_LOAD_ADD:
12348 Opc = X86ISD::ATOMADD64_DAG;
12350 case ISD::ATOMIC_LOAD_AND:
12351 Opc = X86ISD::ATOMAND64_DAG;
12353 case ISD::ATOMIC_LOAD_NAND:
12354 Opc = X86ISD::ATOMNAND64_DAG;
12356 case ISD::ATOMIC_LOAD_OR:
12357 Opc = X86ISD::ATOMOR64_DAG;
12359 case ISD::ATOMIC_LOAD_SUB:
12360 Opc = X86ISD::ATOMSUB64_DAG;
12362 case ISD::ATOMIC_LOAD_XOR:
12363 Opc = X86ISD::ATOMXOR64_DAG;
12365 case ISD::ATOMIC_LOAD_MAX:
12366 Opc = X86ISD::ATOMMAX64_DAG;
12368 case ISD::ATOMIC_LOAD_MIN:
12369 Opc = X86ISD::ATOMMIN64_DAG;
12371 case ISD::ATOMIC_LOAD_UMAX:
12372 Opc = X86ISD::ATOMUMAX64_DAG;
12374 case ISD::ATOMIC_LOAD_UMIN:
12375 Opc = X86ISD::ATOMUMIN64_DAG;
12377 case ISD::ATOMIC_SWAP:
12378 Opc = X86ISD::ATOMSWAP64_DAG;
12381 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
12384 case ISD::ATOMIC_LOAD:
12385 ReplaceATOMIC_LOAD(N, Results, DAG);
12389 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
12391 default: return NULL;
12392 case X86ISD::BSF: return "X86ISD::BSF";
12393 case X86ISD::BSR: return "X86ISD::BSR";
12394 case X86ISD::SHLD: return "X86ISD::SHLD";
12395 case X86ISD::SHRD: return "X86ISD::SHRD";
12396 case X86ISD::FAND: return "X86ISD::FAND";
12397 case X86ISD::FOR: return "X86ISD::FOR";
12398 case X86ISD::FXOR: return "X86ISD::FXOR";
12399 case X86ISD::FSRL: return "X86ISD::FSRL";
12400 case X86ISD::FILD: return "X86ISD::FILD";
12401 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
12402 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
12403 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
12404 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
12405 case X86ISD::FLD: return "X86ISD::FLD";
12406 case X86ISD::FST: return "X86ISD::FST";
12407 case X86ISD::CALL: return "X86ISD::CALL";
12408 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
12409 case X86ISD::BT: return "X86ISD::BT";
12410 case X86ISD::CMP: return "X86ISD::CMP";
12411 case X86ISD::COMI: return "X86ISD::COMI";
12412 case X86ISD::UCOMI: return "X86ISD::UCOMI";
12413 case X86ISD::SETCC: return "X86ISD::SETCC";
12414 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
12415 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
12416 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
12417 case X86ISD::CMOV: return "X86ISD::CMOV";
12418 case X86ISD::BRCOND: return "X86ISD::BRCOND";
12419 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
12420 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
12421 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
12422 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
12423 case X86ISD::Wrapper: return "X86ISD::Wrapper";
12424 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
12425 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
12426 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
12427 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
12428 case X86ISD::PINSRB: return "X86ISD::PINSRB";
12429 case X86ISD::PINSRW: return "X86ISD::PINSRW";
12430 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
12431 case X86ISD::ANDNP: return "X86ISD::ANDNP";
12432 case X86ISD::PSIGN: return "X86ISD::PSIGN";
12433 case X86ISD::BLENDV: return "X86ISD::BLENDV";
12434 case X86ISD::BLENDI: return "X86ISD::BLENDI";
12435 case X86ISD::SUBUS: return "X86ISD::SUBUS";
12436 case X86ISD::HADD: return "X86ISD::HADD";
12437 case X86ISD::HSUB: return "X86ISD::HSUB";
12438 case X86ISD::FHADD: return "X86ISD::FHADD";
12439 case X86ISD::FHSUB: return "X86ISD::FHSUB";
12440 case X86ISD::UMAX: return "X86ISD::UMAX";
12441 case X86ISD::UMIN: return "X86ISD::UMIN";
12442 case X86ISD::SMAX: return "X86ISD::SMAX";
12443 case X86ISD::SMIN: return "X86ISD::SMIN";
12444 case X86ISD::FMAX: return "X86ISD::FMAX";
12445 case X86ISD::FMIN: return "X86ISD::FMIN";
12446 case X86ISD::FMAXC: return "X86ISD::FMAXC";
12447 case X86ISD::FMINC: return "X86ISD::FMINC";
12448 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
12449 case X86ISD::FRCP: return "X86ISD::FRCP";
12450 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
12451 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
12452 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
12453 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
12454 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
12455 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
12456 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
12457 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
12458 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
12459 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
12460 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
12461 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
12462 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
12463 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
12464 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
12465 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
12466 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
12467 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
12468 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
12469 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
12470 case X86ISD::VZEXT: return "X86ISD::VZEXT";
12471 case X86ISD::VSEXT: return "X86ISD::VSEXT";
12472 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
12473 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
12474 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
12475 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
12476 case X86ISD::VSHL: return "X86ISD::VSHL";
12477 case X86ISD::VSRL: return "X86ISD::VSRL";
12478 case X86ISD::VSRA: return "X86ISD::VSRA";
12479 case X86ISD::VSHLI: return "X86ISD::VSHLI";
12480 case X86ISD::VSRLI: return "X86ISD::VSRLI";
12481 case X86ISD::VSRAI: return "X86ISD::VSRAI";
12482 case X86ISD::CMPP: return "X86ISD::CMPP";
12483 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
12484 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
12485 case X86ISD::ADD: return "X86ISD::ADD";
12486 case X86ISD::SUB: return "X86ISD::SUB";
12487 case X86ISD::ADC: return "X86ISD::ADC";
12488 case X86ISD::SBB: return "X86ISD::SBB";
12489 case X86ISD::SMUL: return "X86ISD::SMUL";
12490 case X86ISD::UMUL: return "X86ISD::UMUL";
12491 case X86ISD::INC: return "X86ISD::INC";
12492 case X86ISD::DEC: return "X86ISD::DEC";
12493 case X86ISD::OR: return "X86ISD::OR";
12494 case X86ISD::XOR: return "X86ISD::XOR";
12495 case X86ISD::AND: return "X86ISD::AND";
12496 case X86ISD::BLSI: return "X86ISD::BLSI";
12497 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
12498 case X86ISD::BLSR: return "X86ISD::BLSR";
12499 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
12500 case X86ISD::PTEST: return "X86ISD::PTEST";
12501 case X86ISD::TESTP: return "X86ISD::TESTP";
12502 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
12503 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
12504 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
12505 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
12506 case X86ISD::SHUFP: return "X86ISD::SHUFP";
12507 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
12508 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
12509 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
12510 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
12511 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
12512 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
12513 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
12514 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
12515 case X86ISD::MOVSD: return "X86ISD::MOVSD";
12516 case X86ISD::MOVSS: return "X86ISD::MOVSS";
12517 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
12518 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
12519 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
12520 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
12521 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
12522 case X86ISD::VPERMV: return "X86ISD::VPERMV";
12523 case X86ISD::VPERMI: return "X86ISD::VPERMI";
12524 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
12525 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
12526 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
12527 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
12528 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
12529 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
12530 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
12531 case X86ISD::SAHF: return "X86ISD::SAHF";
12532 case X86ISD::RDRAND: return "X86ISD::RDRAND";
12533 case X86ISD::FMADD: return "X86ISD::FMADD";
12534 case X86ISD::FMSUB: return "X86ISD::FMSUB";
12535 case X86ISD::FNMADD: return "X86ISD::FNMADD";
12536 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
12537 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
12538 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
12539 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
12540 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12544 // isLegalAddressingMode - Return true if the addressing mode represented
12545 // by AM is legal for this target, for a load/store of the specified type.
12546 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
12548 // X86 supports extremely general addressing modes.
12549 CodeModel::Model M = getTargetMachine().getCodeModel();
12550 Reloc::Model R = getTargetMachine().getRelocationModel();
12552 // X86 allows a sign-extended 32-bit immediate field as a displacement.
12553 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
12558 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
12560 // If a reference to this global requires an extra load, we can't fold it.
12561 if (isGlobalStubReference(GVFlags))
12564 // If BaseGV requires a register for the PIC base, we cannot also have a
12565 // BaseReg specified.
12566 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
12569 // If lower 4G is not available, then we must use rip-relative addressing.
12570 if ((M != CodeModel::Small || R != Reloc::Static) &&
12571 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
12575 switch (AM.Scale) {
12581 // These scales always work.
12586 // These scales are formed with basereg+scalereg. Only accept if there is
12591 default: // Other stuff never works.
12598 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12599 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12601 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12602 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12603 return NumBits1 > NumBits2;
12606 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12607 return isInt<32>(Imm);
12610 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
12611 // Can also use sub to handle negated immediates.
12612 return isInt<32>(Imm);
12615 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12616 if (!VT1.isInteger() || !VT2.isInteger())
12618 unsigned NumBits1 = VT1.getSizeInBits();
12619 unsigned NumBits2 = VT2.getSizeInBits();
12620 return NumBits1 > NumBits2;
12623 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
12624 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12625 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
12628 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
12629 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12630 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
12633 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12634 EVT VT1 = Val.getValueType();
12635 if (isZExtFree(VT1, VT2))
12638 if (Val.getOpcode() != ISD::LOAD)
12641 if (!VT1.isSimple() || !VT1.isInteger() ||
12642 !VT2.isSimple() || !VT2.isInteger())
12645 switch (VT1.getSimpleVT().SimpleTy) {
12650 // X86 has 8, 16, and 32-bit zero-extending loads.
12657 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
12658 // i16 instructions are longer (0x66 prefix) and potentially slower.
12659 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
12662 /// isShuffleMaskLegal - Targets can use this to indicate that they only
12663 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
12664 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12665 /// are assumed to be legal.
12667 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
12669 // Very little shuffling can be done for 64-bit vectors right now.
12670 if (VT.getSizeInBits() == 64)
12673 // FIXME: pshufb, blends, shifts.
12674 return (VT.getVectorNumElements() == 2 ||
12675 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
12676 isMOVLMask(M, VT) ||
12677 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
12678 isPSHUFDMask(M, VT) ||
12679 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
12680 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
12681 isPALIGNRMask(M, VT, Subtarget) ||
12682 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
12683 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
12684 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
12685 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
12689 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
12691 unsigned NumElts = VT.getVectorNumElements();
12692 // FIXME: This collection of masks seems suspect.
12695 if (NumElts == 4 && VT.is128BitVector()) {
12696 return (isMOVLMask(Mask, VT) ||
12697 isCommutedMOVLMask(Mask, VT, true) ||
12698 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
12699 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
12704 //===----------------------------------------------------------------------===//
12705 // X86 Scheduler Hooks
12706 //===----------------------------------------------------------------------===//
12708 /// Utility function to emit xbegin specifying the start of an RTM region.
12709 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
12710 const TargetInstrInfo *TII) {
12711 DebugLoc DL = MI->getDebugLoc();
12713 const BasicBlock *BB = MBB->getBasicBlock();
12714 MachineFunction::iterator I = MBB;
12717 // For the v = xbegin(), we generate
12728 MachineBasicBlock *thisMBB = MBB;
12729 MachineFunction *MF = MBB->getParent();
12730 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12731 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12732 MF->insert(I, mainMBB);
12733 MF->insert(I, sinkMBB);
12735 // Transfer the remainder of BB and its successor edges to sinkMBB.
12736 sinkMBB->splice(sinkMBB->begin(), MBB,
12737 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12738 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12742 // # fallthrough to mainMBB
12743 // # abortion to sinkMBB
12744 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
12745 thisMBB->addSuccessor(mainMBB);
12746 thisMBB->addSuccessor(sinkMBB);
12750 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12751 mainMBB->addSuccessor(sinkMBB);
12754 // EAX is live into the sinkMBB
12755 sinkMBB->addLiveIn(X86::EAX);
12756 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12757 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12760 MI->eraseFromParent();
12764 // Get CMPXCHG opcode for the specified data type.
12765 static unsigned getCmpXChgOpcode(EVT VT) {
12766 switch (VT.getSimpleVT().SimpleTy) {
12767 case MVT::i8: return X86::LCMPXCHG8;
12768 case MVT::i16: return X86::LCMPXCHG16;
12769 case MVT::i32: return X86::LCMPXCHG32;
12770 case MVT::i64: return X86::LCMPXCHG64;
12774 llvm_unreachable("Invalid operand size!");
12777 // Get LOAD opcode for the specified data type.
12778 static unsigned getLoadOpcode(EVT VT) {
12779 switch (VT.getSimpleVT().SimpleTy) {
12780 case MVT::i8: return X86::MOV8rm;
12781 case MVT::i16: return X86::MOV16rm;
12782 case MVT::i32: return X86::MOV32rm;
12783 case MVT::i64: return X86::MOV64rm;
12787 llvm_unreachable("Invalid operand size!");
12790 // Get opcode of the non-atomic one from the specified atomic instruction.
12791 static unsigned getNonAtomicOpcode(unsigned Opc) {
12793 case X86::ATOMAND8: return X86::AND8rr;
12794 case X86::ATOMAND16: return X86::AND16rr;
12795 case X86::ATOMAND32: return X86::AND32rr;
12796 case X86::ATOMAND64: return X86::AND64rr;
12797 case X86::ATOMOR8: return X86::OR8rr;
12798 case X86::ATOMOR16: return X86::OR16rr;
12799 case X86::ATOMOR32: return X86::OR32rr;
12800 case X86::ATOMOR64: return X86::OR64rr;
12801 case X86::ATOMXOR8: return X86::XOR8rr;
12802 case X86::ATOMXOR16: return X86::XOR16rr;
12803 case X86::ATOMXOR32: return X86::XOR32rr;
12804 case X86::ATOMXOR64: return X86::XOR64rr;
12806 llvm_unreachable("Unhandled atomic-load-op opcode!");
12809 // Get opcode of the non-atomic one from the specified atomic instruction with
12811 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
12812 unsigned &ExtraOpc) {
12814 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
12815 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
12816 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
12817 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
12818 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
12819 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
12820 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
12821 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
12822 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
12823 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
12824 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
12825 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
12826 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
12827 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
12828 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
12829 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
12830 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
12831 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
12832 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
12833 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
12835 llvm_unreachable("Unhandled atomic-load-op opcode!");
12838 // Get opcode of the non-atomic one from the specified atomic instruction for
12839 // 64-bit data type on 32-bit target.
12840 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
12842 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
12843 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
12844 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
12845 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
12846 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
12847 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
12848 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
12849 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
12850 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
12851 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
12853 llvm_unreachable("Unhandled atomic-load-op opcode!");
12856 // Get opcode of the non-atomic one from the specified atomic instruction for
12857 // 64-bit data type on 32-bit target with extra opcode.
12858 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
12860 unsigned &ExtraOpc) {
12862 case X86::ATOMNAND6432:
12863 ExtraOpc = X86::NOT32r;
12864 HiOpc = X86::AND32rr;
12865 return X86::AND32rr;
12867 llvm_unreachable("Unhandled atomic-load-op opcode!");
12870 // Get pseudo CMOV opcode from the specified data type.
12871 static unsigned getPseudoCMOVOpc(EVT VT) {
12872 switch (VT.getSimpleVT().SimpleTy) {
12873 case MVT::i8: return X86::CMOV_GR8;
12874 case MVT::i16: return X86::CMOV_GR16;
12875 case MVT::i32: return X86::CMOV_GR32;
12879 llvm_unreachable("Unknown CMOV opcode!");
12882 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
12883 // They will be translated into a spin-loop or compare-exchange loop from
12886 // dst = atomic-fetch-op MI.addr, MI.val
12892 // EAX = LOAD MI.addr
12894 // t1 = OP MI.val, EAX
12895 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12900 MachineBasicBlock *
12901 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
12902 MachineBasicBlock *MBB) const {
12903 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12904 DebugLoc DL = MI->getDebugLoc();
12906 MachineFunction *MF = MBB->getParent();
12907 MachineRegisterInfo &MRI = MF->getRegInfo();
12909 const BasicBlock *BB = MBB->getBasicBlock();
12910 MachineFunction::iterator I = MBB;
12913 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
12914 "Unexpected number of operands");
12916 assert(MI->hasOneMemOperand() &&
12917 "Expected atomic-load-op to have one memoperand");
12919 // Memory Reference
12920 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12921 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12923 unsigned DstReg, SrcReg;
12924 unsigned MemOpndSlot;
12926 unsigned CurOp = 0;
12928 DstReg = MI->getOperand(CurOp++).getReg();
12929 MemOpndSlot = CurOp;
12930 CurOp += X86::AddrNumOperands;
12931 SrcReg = MI->getOperand(CurOp++).getReg();
12933 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
12934 MVT::SimpleValueType VT = *RC->vt_begin();
12935 unsigned AccPhyReg = getX86SubSuperRegister(X86::EAX, VT);
12937 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
12938 unsigned LOADOpc = getLoadOpcode(VT);
12940 // For the atomic load-arith operator, we generate
12943 // EAX = LOAD [MI.addr]
12945 // t1 = OP MI.val, EAX
12946 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12950 MachineBasicBlock *thisMBB = MBB;
12951 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12952 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12953 MF->insert(I, mainMBB);
12954 MF->insert(I, sinkMBB);
12956 MachineInstrBuilder MIB;
12958 // Transfer the remainder of BB and its successor edges to sinkMBB.
12959 sinkMBB->splice(sinkMBB->begin(), MBB,
12960 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12961 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12964 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), AccPhyReg);
12965 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12966 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12967 MIB.setMemRefs(MMOBegin, MMOEnd);
12969 thisMBB->addSuccessor(mainMBB);
12972 MachineBasicBlock *origMainMBB = mainMBB;
12973 mainMBB->addLiveIn(AccPhyReg);
12975 // Copy AccPhyReg as it is used more than once.
12976 unsigned AccReg = MRI.createVirtualRegister(RC);
12977 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccReg)
12978 .addReg(AccPhyReg);
12980 unsigned t1 = MRI.createVirtualRegister(RC);
12981 unsigned Opc = MI->getOpcode();
12984 llvm_unreachable("Unhandled atomic-load-op opcode!");
12985 case X86::ATOMAND8:
12986 case X86::ATOMAND16:
12987 case X86::ATOMAND32:
12988 case X86::ATOMAND64:
12990 case X86::ATOMOR16:
12991 case X86::ATOMOR32:
12992 case X86::ATOMOR64:
12993 case X86::ATOMXOR8:
12994 case X86::ATOMXOR16:
12995 case X86::ATOMXOR32:
12996 case X86::ATOMXOR64: {
12997 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
12998 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t1).addReg(SrcReg)
13002 case X86::ATOMNAND8:
13003 case X86::ATOMNAND16:
13004 case X86::ATOMNAND32:
13005 case X86::ATOMNAND64: {
13006 unsigned t2 = MRI.createVirtualRegister(RC);
13008 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
13009 BuildMI(mainMBB, DL, TII->get(ANDOpc), t2).addReg(SrcReg)
13011 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2);
13014 case X86::ATOMMAX8:
13015 case X86::ATOMMAX16:
13016 case X86::ATOMMAX32:
13017 case X86::ATOMMAX64:
13018 case X86::ATOMMIN8:
13019 case X86::ATOMMIN16:
13020 case X86::ATOMMIN32:
13021 case X86::ATOMMIN64:
13022 case X86::ATOMUMAX8:
13023 case X86::ATOMUMAX16:
13024 case X86::ATOMUMAX32:
13025 case X86::ATOMUMAX64:
13026 case X86::ATOMUMIN8:
13027 case X86::ATOMUMIN16:
13028 case X86::ATOMUMIN32:
13029 case X86::ATOMUMIN64: {
13031 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
13033 BuildMI(mainMBB, DL, TII->get(CMPOpc))
13037 if (Subtarget->hasCMov()) {
13038 if (VT != MVT::i8) {
13040 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t1)
13044 // Promote i8 to i32 to use CMOV32
13045 const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32);
13046 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
13047 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
13048 unsigned t2 = MRI.createVirtualRegister(RC32);
13050 unsigned Undef = MRI.createVirtualRegister(RC32);
13051 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
13053 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
13056 .addImm(X86::sub_8bit);
13057 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
13060 .addImm(X86::sub_8bit);
13062 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
13066 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t1)
13067 .addReg(t2, 0, X86::sub_8bit);
13070 // Use pseudo select and lower them.
13071 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
13072 "Invalid atomic-load-op transformation!");
13073 unsigned SelOpc = getPseudoCMOVOpc(VT);
13074 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
13075 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
13076 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t1)
13077 .addReg(SrcReg).addReg(AccReg)
13079 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13085 // Copy AccPhyReg back from virtual register.
13086 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccPhyReg)
13089 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13090 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13091 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13093 MIB.setMemRefs(MMOBegin, MMOEnd);
13095 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13097 mainMBB->addSuccessor(origMainMBB);
13098 mainMBB->addSuccessor(sinkMBB);
13101 sinkMBB->addLiveIn(AccPhyReg);
13103 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13104 TII->get(TargetOpcode::COPY), DstReg)
13105 .addReg(AccPhyReg);
13107 MI->eraseFromParent();
13111 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
13112 // instructions. They will be translated into a spin-loop or compare-exchange
13116 // dst = atomic-fetch-op MI.addr, MI.val
13122 // EAX = LOAD [MI.addr + 0]
13123 // EDX = LOAD [MI.addr + 4]
13125 // EBX = OP MI.val.lo, EAX
13126 // ECX = OP MI.val.hi, EDX
13127 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13132 MachineBasicBlock *
13133 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
13134 MachineBasicBlock *MBB) const {
13135 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13136 DebugLoc DL = MI->getDebugLoc();
13138 MachineFunction *MF = MBB->getParent();
13139 MachineRegisterInfo &MRI = MF->getRegInfo();
13141 const BasicBlock *BB = MBB->getBasicBlock();
13142 MachineFunction::iterator I = MBB;
13145 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
13146 "Unexpected number of operands");
13148 assert(MI->hasOneMemOperand() &&
13149 "Expected atomic-load-op32 to have one memoperand");
13151 // Memory Reference
13152 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13153 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13155 unsigned DstLoReg, DstHiReg;
13156 unsigned SrcLoReg, SrcHiReg;
13157 unsigned MemOpndSlot;
13159 unsigned CurOp = 0;
13161 DstLoReg = MI->getOperand(CurOp++).getReg();
13162 DstHiReg = MI->getOperand(CurOp++).getReg();
13163 MemOpndSlot = CurOp;
13164 CurOp += X86::AddrNumOperands;
13165 SrcLoReg = MI->getOperand(CurOp++).getReg();
13166 SrcHiReg = MI->getOperand(CurOp++).getReg();
13168 const TargetRegisterClass *RC = &X86::GR32RegClass;
13169 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
13171 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
13172 unsigned LOADOpc = X86::MOV32rm;
13174 // For the atomic load-arith operator, we generate
13177 // EAX = LOAD [MI.addr + 0]
13178 // EDX = LOAD [MI.addr + 4]
13180 // EBX = OP MI.vallo, EAX
13181 // ECX = OP MI.valhi, EDX
13182 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13186 MachineBasicBlock *thisMBB = MBB;
13187 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13188 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13189 MF->insert(I, mainMBB);
13190 MF->insert(I, sinkMBB);
13192 MachineInstrBuilder MIB;
13194 // Transfer the remainder of BB and its successor edges to sinkMBB.
13195 sinkMBB->splice(sinkMBB->begin(), MBB,
13196 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13197 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13201 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EAX);
13202 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13203 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13204 MIB.setMemRefs(MMOBegin, MMOEnd);
13206 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX);
13207 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13208 if (i == X86::AddrDisp)
13209 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
13211 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13213 MIB.setMemRefs(MMOBegin, MMOEnd);
13215 thisMBB->addSuccessor(mainMBB);
13218 MachineBasicBlock *origMainMBB = mainMBB;
13219 mainMBB->addLiveIn(X86::EAX);
13220 mainMBB->addLiveIn(X86::EDX);
13222 // Copy EDX:EAX as they are used more than once.
13223 unsigned LoReg = MRI.createVirtualRegister(RC);
13224 unsigned HiReg = MRI.createVirtualRegister(RC);
13225 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), LoReg).addReg(X86::EAX);
13226 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), HiReg).addReg(X86::EDX);
13228 unsigned t1L = MRI.createVirtualRegister(RC);
13229 unsigned t1H = MRI.createVirtualRegister(RC);
13231 unsigned Opc = MI->getOpcode();
13234 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
13235 case X86::ATOMAND6432:
13236 case X86::ATOMOR6432:
13237 case X86::ATOMXOR6432:
13238 case X86::ATOMADD6432:
13239 case X86::ATOMSUB6432: {
13241 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13242 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
13243 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
13246 case X86::ATOMNAND6432: {
13247 unsigned HiOpc, NOTOpc;
13248 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
13249 unsigned t2L = MRI.createVirtualRegister(RC);
13250 unsigned t2H = MRI.createVirtualRegister(RC);
13251 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg).addReg(LoReg);
13252 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg).addReg(HiReg);
13253 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1L).addReg(t2L);
13254 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1H).addReg(t2H);
13257 case X86::ATOMMAX6432:
13258 case X86::ATOMMIN6432:
13259 case X86::ATOMUMAX6432:
13260 case X86::ATOMUMIN6432: {
13262 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13263 unsigned cL = MRI.createVirtualRegister(RC8);
13264 unsigned cH = MRI.createVirtualRegister(RC8);
13265 unsigned cL32 = MRI.createVirtualRegister(RC);
13266 unsigned cH32 = MRI.createVirtualRegister(RC);
13267 unsigned cc = MRI.createVirtualRegister(RC);
13268 // cl := cmp src_lo, lo
13269 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13270 .addReg(SrcLoReg).addReg(LoReg);
13271 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
13272 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
13273 // ch := cmp src_hi, hi
13274 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13275 .addReg(SrcHiReg).addReg(HiReg);
13276 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
13277 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
13278 // cc := if (src_hi == hi) ? cl : ch;
13279 if (Subtarget->hasCMov()) {
13280 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
13281 .addReg(cH32).addReg(cL32);
13283 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
13284 .addReg(cH32).addReg(cL32)
13285 .addImm(X86::COND_E);
13286 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13288 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
13289 if (Subtarget->hasCMov()) {
13290 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1L)
13291 .addReg(SrcLoReg).addReg(LoReg);
13292 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1H)
13293 .addReg(SrcHiReg).addReg(HiReg);
13295 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1L)
13296 .addReg(SrcLoReg).addReg(LoReg)
13297 .addImm(X86::COND_NE);
13298 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13299 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1H)
13300 .addReg(SrcHiReg).addReg(HiReg)
13301 .addImm(X86::COND_NE);
13302 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13306 case X86::ATOMSWAP6432: {
13308 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13309 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg);
13310 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg);
13315 // Copy EDX:EAX back from HiReg:LoReg
13316 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(LoReg);
13317 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(HiReg);
13318 // Copy ECX:EBX from t1H:t1L
13319 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t1L);
13320 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t1H);
13322 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13323 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13324 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13325 MIB.setMemRefs(MMOBegin, MMOEnd);
13327 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13329 mainMBB->addSuccessor(origMainMBB);
13330 mainMBB->addSuccessor(sinkMBB);
13333 sinkMBB->addLiveIn(X86::EAX);
13334 sinkMBB->addLiveIn(X86::EDX);
13336 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13337 TII->get(TargetOpcode::COPY), DstLoReg)
13339 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13340 TII->get(TargetOpcode::COPY), DstHiReg)
13343 MI->eraseFromParent();
13347 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
13348 // or XMM0_V32I8 in AVX all of this code can be replaced with that
13349 // in the .td file.
13350 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
13351 const TargetInstrInfo *TII) {
13353 switch (MI->getOpcode()) {
13354 default: llvm_unreachable("illegal opcode!");
13355 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
13356 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
13357 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
13358 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
13359 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
13360 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
13361 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
13362 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
13365 DebugLoc dl = MI->getDebugLoc();
13366 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13368 unsigned NumArgs = MI->getNumOperands();
13369 for (unsigned i = 1; i < NumArgs; ++i) {
13370 MachineOperand &Op = MI->getOperand(i);
13371 if (!(Op.isReg() && Op.isImplicit()))
13372 MIB.addOperand(Op);
13374 if (MI->hasOneMemOperand())
13375 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13377 BuildMI(*BB, MI, dl,
13378 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13379 .addReg(X86::XMM0);
13381 MI->eraseFromParent();
13385 // FIXME: Custom handling because TableGen doesn't support multiple implicit
13386 // defs in an instruction pattern
13387 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
13388 const TargetInstrInfo *TII) {
13390 switch (MI->getOpcode()) {
13391 default: llvm_unreachable("illegal opcode!");
13392 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
13393 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
13394 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
13395 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
13396 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
13397 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
13398 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
13399 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
13402 DebugLoc dl = MI->getDebugLoc();
13403 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13405 unsigned NumArgs = MI->getNumOperands(); // remove the results
13406 for (unsigned i = 1; i < NumArgs; ++i) {
13407 MachineOperand &Op = MI->getOperand(i);
13408 if (!(Op.isReg() && Op.isImplicit()))
13409 MIB.addOperand(Op);
13411 if (MI->hasOneMemOperand())
13412 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13414 BuildMI(*BB, MI, dl,
13415 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13418 MI->eraseFromParent();
13422 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
13423 const TargetInstrInfo *TII,
13424 const X86Subtarget* Subtarget) {
13425 DebugLoc dl = MI->getDebugLoc();
13427 // Address into RAX/EAX, other two args into ECX, EDX.
13428 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
13429 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13430 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
13431 for (int i = 0; i < X86::AddrNumOperands; ++i)
13432 MIB.addOperand(MI->getOperand(i));
13434 unsigned ValOps = X86::AddrNumOperands;
13435 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
13436 .addReg(MI->getOperand(ValOps).getReg());
13437 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
13438 .addReg(MI->getOperand(ValOps+1).getReg());
13440 // The instruction doesn't actually take any operands though.
13441 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
13443 MI->eraseFromParent(); // The pseudo is gone now.
13447 MachineBasicBlock *
13448 X86TargetLowering::EmitVAARG64WithCustomInserter(
13450 MachineBasicBlock *MBB) const {
13451 // Emit va_arg instruction on X86-64.
13453 // Operands to this pseudo-instruction:
13454 // 0 ) Output : destination address (reg)
13455 // 1-5) Input : va_list address (addr, i64mem)
13456 // 6 ) ArgSize : Size (in bytes) of vararg type
13457 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
13458 // 8 ) Align : Alignment of type
13459 // 9 ) EFLAGS (implicit-def)
13461 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
13462 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
13464 unsigned DestReg = MI->getOperand(0).getReg();
13465 MachineOperand &Base = MI->getOperand(1);
13466 MachineOperand &Scale = MI->getOperand(2);
13467 MachineOperand &Index = MI->getOperand(3);
13468 MachineOperand &Disp = MI->getOperand(4);
13469 MachineOperand &Segment = MI->getOperand(5);
13470 unsigned ArgSize = MI->getOperand(6).getImm();
13471 unsigned ArgMode = MI->getOperand(7).getImm();
13472 unsigned Align = MI->getOperand(8).getImm();
13474 // Memory Reference
13475 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
13476 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13477 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13479 // Machine Information
13480 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13481 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
13482 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
13483 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
13484 DebugLoc DL = MI->getDebugLoc();
13486 // struct va_list {
13489 // i64 overflow_area (address)
13490 // i64 reg_save_area (address)
13492 // sizeof(va_list) = 24
13493 // alignment(va_list) = 8
13495 unsigned TotalNumIntRegs = 6;
13496 unsigned TotalNumXMMRegs = 8;
13497 bool UseGPOffset = (ArgMode == 1);
13498 bool UseFPOffset = (ArgMode == 2);
13499 unsigned MaxOffset = TotalNumIntRegs * 8 +
13500 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
13502 /* Align ArgSize to a multiple of 8 */
13503 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
13504 bool NeedsAlign = (Align > 8);
13506 MachineBasicBlock *thisMBB = MBB;
13507 MachineBasicBlock *overflowMBB;
13508 MachineBasicBlock *offsetMBB;
13509 MachineBasicBlock *endMBB;
13511 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
13512 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
13513 unsigned OffsetReg = 0;
13515 if (!UseGPOffset && !UseFPOffset) {
13516 // If we only pull from the overflow region, we don't create a branch.
13517 // We don't need to alter control flow.
13518 OffsetDestReg = 0; // unused
13519 OverflowDestReg = DestReg;
13522 overflowMBB = thisMBB;
13525 // First emit code to check if gp_offset (or fp_offset) is below the bound.
13526 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
13527 // If not, pull from overflow_area. (branch to overflowMBB)
13532 // offsetMBB overflowMBB
13537 // Registers for the PHI in endMBB
13538 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
13539 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
13541 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13542 MachineFunction *MF = MBB->getParent();
13543 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13544 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13545 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13547 MachineFunction::iterator MBBIter = MBB;
13550 // Insert the new basic blocks
13551 MF->insert(MBBIter, offsetMBB);
13552 MF->insert(MBBIter, overflowMBB);
13553 MF->insert(MBBIter, endMBB);
13555 // Transfer the remainder of MBB and its successor edges to endMBB.
13556 endMBB->splice(endMBB->begin(), thisMBB,
13557 llvm::next(MachineBasicBlock::iterator(MI)),
13559 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
13561 // Make offsetMBB and overflowMBB successors of thisMBB
13562 thisMBB->addSuccessor(offsetMBB);
13563 thisMBB->addSuccessor(overflowMBB);
13565 // endMBB is a successor of both offsetMBB and overflowMBB
13566 offsetMBB->addSuccessor(endMBB);
13567 overflowMBB->addSuccessor(endMBB);
13569 // Load the offset value into a register
13570 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13571 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13575 .addDisp(Disp, UseFPOffset ? 4 : 0)
13576 .addOperand(Segment)
13577 .setMemRefs(MMOBegin, MMOEnd);
13579 // Check if there is enough room left to pull this argument.
13580 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13582 .addImm(MaxOffset + 8 - ArgSizeA8);
13584 // Branch to "overflowMBB" if offset >= max
13585 // Fall through to "offsetMBB" otherwise
13586 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13587 .addMBB(overflowMBB);
13590 // In offsetMBB, emit code to use the reg_save_area.
13592 assert(OffsetReg != 0);
13594 // Read the reg_save_area address.
13595 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
13596 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13601 .addOperand(Segment)
13602 .setMemRefs(MMOBegin, MMOEnd);
13604 // Zero-extend the offset
13605 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
13606 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13609 .addImm(X86::sub_32bit);
13611 // Add the offset to the reg_save_area to get the final address.
13612 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13613 .addReg(OffsetReg64)
13614 .addReg(RegSaveReg);
13616 // Compute the offset for the next argument
13617 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13618 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13620 .addImm(UseFPOffset ? 16 : 8);
13622 // Store it back into the va_list.
13623 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13627 .addDisp(Disp, UseFPOffset ? 4 : 0)
13628 .addOperand(Segment)
13629 .addReg(NextOffsetReg)
13630 .setMemRefs(MMOBegin, MMOEnd);
13633 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
13638 // Emit code to use overflow area
13641 // Load the overflow_area address into a register.
13642 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
13643 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
13648 .addOperand(Segment)
13649 .setMemRefs(MMOBegin, MMOEnd);
13651 // If we need to align it, do so. Otherwise, just copy the address
13652 // to OverflowDestReg.
13654 // Align the overflow address
13655 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
13656 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
13658 // aligned_addr = (addr + (align-1)) & ~(align-1)
13659 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
13660 .addReg(OverflowAddrReg)
13663 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
13665 .addImm(~(uint64_t)(Align-1));
13667 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
13668 .addReg(OverflowAddrReg);
13671 // Compute the next overflow address after this argument.
13672 // (the overflow address should be kept 8-byte aligned)
13673 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
13674 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
13675 .addReg(OverflowDestReg)
13676 .addImm(ArgSizeA8);
13678 // Store the new overflow address.
13679 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
13684 .addOperand(Segment)
13685 .addReg(NextAddrReg)
13686 .setMemRefs(MMOBegin, MMOEnd);
13688 // If we branched, emit the PHI to the front of endMBB.
13690 BuildMI(*endMBB, endMBB->begin(), DL,
13691 TII->get(X86::PHI), DestReg)
13692 .addReg(OffsetDestReg).addMBB(offsetMBB)
13693 .addReg(OverflowDestReg).addMBB(overflowMBB);
13696 // Erase the pseudo instruction
13697 MI->eraseFromParent();
13702 MachineBasicBlock *
13703 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
13705 MachineBasicBlock *MBB) const {
13706 // Emit code to save XMM registers to the stack. The ABI says that the
13707 // number of registers to save is given in %al, so it's theoretically
13708 // possible to do an indirect jump trick to avoid saving all of them,
13709 // however this code takes a simpler approach and just executes all
13710 // of the stores if %al is non-zero. It's less code, and it's probably
13711 // easier on the hardware branch predictor, and stores aren't all that
13712 // expensive anyway.
13714 // Create the new basic blocks. One block contains all the XMM stores,
13715 // and one block is the final destination regardless of whether any
13716 // stores were performed.
13717 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13718 MachineFunction *F = MBB->getParent();
13719 MachineFunction::iterator MBBIter = MBB;
13721 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
13722 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
13723 F->insert(MBBIter, XMMSaveMBB);
13724 F->insert(MBBIter, EndMBB);
13726 // Transfer the remainder of MBB and its successor edges to EndMBB.
13727 EndMBB->splice(EndMBB->begin(), MBB,
13728 llvm::next(MachineBasicBlock::iterator(MI)),
13730 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
13732 // The original block will now fall through to the XMM save block.
13733 MBB->addSuccessor(XMMSaveMBB);
13734 // The XMMSaveMBB will fall through to the end block.
13735 XMMSaveMBB->addSuccessor(EndMBB);
13737 // Now add the instructions.
13738 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13739 DebugLoc DL = MI->getDebugLoc();
13741 unsigned CountReg = MI->getOperand(0).getReg();
13742 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
13743 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
13745 if (!Subtarget->isTargetWin64()) {
13746 // If %al is 0, branch around the XMM save block.
13747 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
13748 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
13749 MBB->addSuccessor(EndMBB);
13752 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
13753 // In the XMM save block, save all the XMM argument registers.
13754 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
13755 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
13756 MachineMemOperand *MMO =
13757 F->getMachineMemOperand(
13758 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
13759 MachineMemOperand::MOStore,
13760 /*Size=*/16, /*Align=*/16);
13761 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
13762 .addFrameIndex(RegSaveFrameIndex)
13763 .addImm(/*Scale=*/1)
13764 .addReg(/*IndexReg=*/0)
13765 .addImm(/*Disp=*/Offset)
13766 .addReg(/*Segment=*/0)
13767 .addReg(MI->getOperand(i).getReg())
13768 .addMemOperand(MMO);
13771 MI->eraseFromParent(); // The pseudo instruction is gone now.
13776 // The EFLAGS operand of SelectItr might be missing a kill marker
13777 // because there were multiple uses of EFLAGS, and ISel didn't know
13778 // which to mark. Figure out whether SelectItr should have had a
13779 // kill marker, and set it if it should. Returns the correct kill
13781 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
13782 MachineBasicBlock* BB,
13783 const TargetRegisterInfo* TRI) {
13784 // Scan forward through BB for a use/def of EFLAGS.
13785 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
13786 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
13787 const MachineInstr& mi = *miI;
13788 if (mi.readsRegister(X86::EFLAGS))
13790 if (mi.definesRegister(X86::EFLAGS))
13791 break; // Should have kill-flag - update below.
13794 // If we hit the end of the block, check whether EFLAGS is live into a
13796 if (miI == BB->end()) {
13797 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
13798 sEnd = BB->succ_end();
13799 sItr != sEnd; ++sItr) {
13800 MachineBasicBlock* succ = *sItr;
13801 if (succ->isLiveIn(X86::EFLAGS))
13806 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
13807 // out. SelectMI should have a kill flag on EFLAGS.
13808 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
13812 MachineBasicBlock *
13813 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
13814 MachineBasicBlock *BB) const {
13815 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13816 DebugLoc DL = MI->getDebugLoc();
13818 // To "insert" a SELECT_CC instruction, we actually have to insert the
13819 // diamond control-flow pattern. The incoming instruction knows the
13820 // destination vreg to set, the condition code register to branch on, the
13821 // true/false values to select between, and a branch opcode to use.
13822 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13823 MachineFunction::iterator It = BB;
13829 // cmpTY ccX, r1, r2
13831 // fallthrough --> copy0MBB
13832 MachineBasicBlock *thisMBB = BB;
13833 MachineFunction *F = BB->getParent();
13834 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
13835 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
13836 F->insert(It, copy0MBB);
13837 F->insert(It, sinkMBB);
13839 // If the EFLAGS register isn't dead in the terminator, then claim that it's
13840 // live into the sink and copy blocks.
13841 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13842 if (!MI->killsRegister(X86::EFLAGS) &&
13843 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
13844 copy0MBB->addLiveIn(X86::EFLAGS);
13845 sinkMBB->addLiveIn(X86::EFLAGS);
13848 // Transfer the remainder of BB and its successor edges to sinkMBB.
13849 sinkMBB->splice(sinkMBB->begin(), BB,
13850 llvm::next(MachineBasicBlock::iterator(MI)),
13852 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
13854 // Add the true and fallthrough blocks as its successors.
13855 BB->addSuccessor(copy0MBB);
13856 BB->addSuccessor(sinkMBB);
13858 // Create the conditional branch instruction.
13860 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
13861 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
13864 // %FalseValue = ...
13865 // # fallthrough to sinkMBB
13866 copy0MBB->addSuccessor(sinkMBB);
13869 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
13871 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13872 TII->get(X86::PHI), MI->getOperand(0).getReg())
13873 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
13874 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
13876 MI->eraseFromParent(); // The pseudo instruction is gone now.
13880 MachineBasicBlock *
13881 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
13882 bool Is64Bit) const {
13883 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13884 DebugLoc DL = MI->getDebugLoc();
13885 MachineFunction *MF = BB->getParent();
13886 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13888 assert(getTargetMachine().Options.EnableSegmentedStacks);
13890 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
13891 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
13894 // ... [Till the alloca]
13895 // If stacklet is not large enough, jump to mallocMBB
13898 // Allocate by subtracting from RSP
13899 // Jump to continueMBB
13902 // Allocate by call to runtime
13906 // [rest of original BB]
13909 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13910 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13911 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13913 MachineRegisterInfo &MRI = MF->getRegInfo();
13914 const TargetRegisterClass *AddrRegClass =
13915 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
13917 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13918 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13919 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
13920 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
13921 sizeVReg = MI->getOperand(1).getReg(),
13922 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
13924 MachineFunction::iterator MBBIter = BB;
13927 MF->insert(MBBIter, bumpMBB);
13928 MF->insert(MBBIter, mallocMBB);
13929 MF->insert(MBBIter, continueMBB);
13931 continueMBB->splice(continueMBB->begin(), BB, llvm::next
13932 (MachineBasicBlock::iterator(MI)), BB->end());
13933 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
13935 // Add code to the main basic block to check if the stack limit has been hit,
13936 // and if so, jump to mallocMBB otherwise to bumpMBB.
13937 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
13938 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
13939 .addReg(tmpSPVReg).addReg(sizeVReg);
13940 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
13941 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
13942 .addReg(SPLimitVReg);
13943 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
13945 // bumpMBB simply decreases the stack pointer, since we know the current
13946 // stacklet has enough space.
13947 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
13948 .addReg(SPLimitVReg);
13949 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
13950 .addReg(SPLimitVReg);
13951 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13953 // Calls into a routine in libgcc to allocate more space from the heap.
13954 const uint32_t *RegMask =
13955 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13957 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
13959 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
13960 .addExternalSymbol("__morestack_allocate_stack_space")
13961 .addRegMask(RegMask)
13962 .addReg(X86::RDI, RegState::Implicit)
13963 .addReg(X86::RAX, RegState::ImplicitDefine);
13965 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
13967 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
13968 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
13969 .addExternalSymbol("__morestack_allocate_stack_space")
13970 .addRegMask(RegMask)
13971 .addReg(X86::EAX, RegState::ImplicitDefine);
13975 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
13978 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
13979 .addReg(Is64Bit ? X86::RAX : X86::EAX);
13980 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13982 // Set up the CFG correctly.
13983 BB->addSuccessor(bumpMBB);
13984 BB->addSuccessor(mallocMBB);
13985 mallocMBB->addSuccessor(continueMBB);
13986 bumpMBB->addSuccessor(continueMBB);
13988 // Take care of the PHI nodes.
13989 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
13990 MI->getOperand(0).getReg())
13991 .addReg(mallocPtrVReg).addMBB(mallocMBB)
13992 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
13994 // Delete the original pseudo instruction.
13995 MI->eraseFromParent();
13998 return continueMBB;
14001 MachineBasicBlock *
14002 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
14003 MachineBasicBlock *BB) const {
14004 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14005 DebugLoc DL = MI->getDebugLoc();
14007 assert(!Subtarget->isTargetEnvMacho());
14009 // The lowering is pretty easy: we're just emitting the call to _alloca. The
14010 // non-trivial part is impdef of ESP.
14012 if (Subtarget->isTargetWin64()) {
14013 if (Subtarget->isTargetCygMing()) {
14014 // ___chkstk(Mingw64):
14015 // Clobbers R10, R11, RAX and EFLAGS.
14017 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14018 .addExternalSymbol("___chkstk")
14019 .addReg(X86::RAX, RegState::Implicit)
14020 .addReg(X86::RSP, RegState::Implicit)
14021 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
14022 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
14023 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14025 // __chkstk(MSVCRT): does not update stack pointer.
14026 // Clobbers R10, R11 and EFLAGS.
14027 // FIXME: RAX(allocated size) might be reused and not killed.
14028 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14029 .addExternalSymbol("__chkstk")
14030 .addReg(X86::RAX, RegState::Implicit)
14031 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14032 // RAX has the offset to subtracted from RSP.
14033 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
14038 const char *StackProbeSymbol =
14039 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
14041 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
14042 .addExternalSymbol(StackProbeSymbol)
14043 .addReg(X86::EAX, RegState::Implicit)
14044 .addReg(X86::ESP, RegState::Implicit)
14045 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
14046 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
14047 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14050 MI->eraseFromParent(); // The pseudo instruction is gone now.
14054 MachineBasicBlock *
14055 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
14056 MachineBasicBlock *BB) const {
14057 // This is pretty easy. We're taking the value that we received from
14058 // our load from the relocation, sticking it in either RDI (x86-64)
14059 // or EAX and doing an indirect call. The return value will then
14060 // be in the normal return register.
14061 const X86InstrInfo *TII
14062 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
14063 DebugLoc DL = MI->getDebugLoc();
14064 MachineFunction *F = BB->getParent();
14066 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
14067 assert(MI->getOperand(3).isGlobal() && "This should be a global");
14069 // Get a register mask for the lowered call.
14070 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
14071 // proper register mask.
14072 const uint32_t *RegMask =
14073 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14074 if (Subtarget->is64Bit()) {
14075 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14076 TII->get(X86::MOV64rm), X86::RDI)
14078 .addImm(0).addReg(0)
14079 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14080 MI->getOperand(3).getTargetFlags())
14082 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
14083 addDirectMem(MIB, X86::RDI);
14084 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
14085 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
14086 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14087 TII->get(X86::MOV32rm), X86::EAX)
14089 .addImm(0).addReg(0)
14090 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14091 MI->getOperand(3).getTargetFlags())
14093 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14094 addDirectMem(MIB, X86::EAX);
14095 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14097 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14098 TII->get(X86::MOV32rm), X86::EAX)
14099 .addReg(TII->getGlobalBaseReg(F))
14100 .addImm(0).addReg(0)
14101 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14102 MI->getOperand(3).getTargetFlags())
14104 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14105 addDirectMem(MIB, X86::EAX);
14106 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14109 MI->eraseFromParent(); // The pseudo instruction is gone now.
14113 MachineBasicBlock *
14114 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
14115 MachineBasicBlock *MBB) const {
14116 DebugLoc DL = MI->getDebugLoc();
14117 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14119 MachineFunction *MF = MBB->getParent();
14120 MachineRegisterInfo &MRI = MF->getRegInfo();
14122 const BasicBlock *BB = MBB->getBasicBlock();
14123 MachineFunction::iterator I = MBB;
14126 // Memory Reference
14127 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14128 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14131 unsigned MemOpndSlot = 0;
14133 unsigned CurOp = 0;
14135 DstReg = MI->getOperand(CurOp++).getReg();
14136 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14137 assert(RC->hasType(MVT::i32) && "Invalid destination!");
14138 unsigned mainDstReg = MRI.createVirtualRegister(RC);
14139 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
14141 MemOpndSlot = CurOp;
14143 MVT PVT = getPointerTy();
14144 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14145 "Invalid Pointer Size!");
14147 // For v = setjmp(buf), we generate
14150 // buf[LabelOffset] = restoreMBB
14151 // SjLjSetup restoreMBB
14157 // v = phi(main, restore)
14162 MachineBasicBlock *thisMBB = MBB;
14163 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14164 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14165 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
14166 MF->insert(I, mainMBB);
14167 MF->insert(I, sinkMBB);
14168 MF->push_back(restoreMBB);
14170 MachineInstrBuilder MIB;
14172 // Transfer the remainder of BB and its successor edges to sinkMBB.
14173 sinkMBB->splice(sinkMBB->begin(), MBB,
14174 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14175 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14178 unsigned PtrStoreOpc = 0;
14179 unsigned LabelReg = 0;
14180 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14181 Reloc::Model RM = getTargetMachine().getRelocationModel();
14182 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
14183 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
14185 // Prepare IP either in reg or imm.
14186 if (!UseImmLabel) {
14187 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
14188 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
14189 LabelReg = MRI.createVirtualRegister(PtrRC);
14190 if (Subtarget->is64Bit()) {
14191 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
14195 .addMBB(restoreMBB)
14198 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
14199 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
14200 .addReg(XII->getGlobalBaseReg(MF))
14203 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
14207 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
14209 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
14210 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14211 if (i == X86::AddrDisp)
14212 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
14214 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
14217 MIB.addReg(LabelReg);
14219 MIB.addMBB(restoreMBB);
14220 MIB.setMemRefs(MMOBegin, MMOEnd);
14222 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
14223 .addMBB(restoreMBB);
14224 MIB.addRegMask(RegInfo->getNoPreservedMask());
14225 thisMBB->addSuccessor(mainMBB);
14226 thisMBB->addSuccessor(restoreMBB);
14230 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
14231 mainMBB->addSuccessor(sinkMBB);
14234 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14235 TII->get(X86::PHI), DstReg)
14236 .addReg(mainDstReg).addMBB(mainMBB)
14237 .addReg(restoreDstReg).addMBB(restoreMBB);
14240 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
14241 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
14242 restoreMBB->addSuccessor(sinkMBB);
14244 MI->eraseFromParent();
14248 MachineBasicBlock *
14249 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
14250 MachineBasicBlock *MBB) const {
14251 DebugLoc DL = MI->getDebugLoc();
14252 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14254 MachineFunction *MF = MBB->getParent();
14255 MachineRegisterInfo &MRI = MF->getRegInfo();
14257 // Memory Reference
14258 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14259 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14261 MVT PVT = getPointerTy();
14262 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14263 "Invalid Pointer Size!");
14265 const TargetRegisterClass *RC =
14266 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
14267 unsigned Tmp = MRI.createVirtualRegister(RC);
14268 // Since FP is only updated here but NOT referenced, it's treated as GPR.
14269 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
14270 unsigned SP = RegInfo->getStackRegister();
14272 MachineInstrBuilder MIB;
14274 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14275 const int64_t SPOffset = 2 * PVT.getStoreSize();
14277 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
14278 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
14281 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
14282 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
14283 MIB.addOperand(MI->getOperand(i));
14284 MIB.setMemRefs(MMOBegin, MMOEnd);
14286 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
14287 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14288 if (i == X86::AddrDisp)
14289 MIB.addDisp(MI->getOperand(i), LabelOffset);
14291 MIB.addOperand(MI->getOperand(i));
14293 MIB.setMemRefs(MMOBegin, MMOEnd);
14295 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
14296 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14297 if (i == X86::AddrDisp)
14298 MIB.addDisp(MI->getOperand(i), SPOffset);
14300 MIB.addOperand(MI->getOperand(i));
14302 MIB.setMemRefs(MMOBegin, MMOEnd);
14304 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
14306 MI->eraseFromParent();
14310 MachineBasicBlock *
14311 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
14312 MachineBasicBlock *BB) const {
14313 switch (MI->getOpcode()) {
14314 default: llvm_unreachable("Unexpected instr type to insert");
14315 case X86::TAILJMPd64:
14316 case X86::TAILJMPr64:
14317 case X86::TAILJMPm64:
14318 llvm_unreachable("TAILJMP64 would not be touched here.");
14319 case X86::TCRETURNdi64:
14320 case X86::TCRETURNri64:
14321 case X86::TCRETURNmi64:
14323 case X86::WIN_ALLOCA:
14324 return EmitLoweredWinAlloca(MI, BB);
14325 case X86::SEG_ALLOCA_32:
14326 return EmitLoweredSegAlloca(MI, BB, false);
14327 case X86::SEG_ALLOCA_64:
14328 return EmitLoweredSegAlloca(MI, BB, true);
14329 case X86::TLSCall_32:
14330 case X86::TLSCall_64:
14331 return EmitLoweredTLSCall(MI, BB);
14332 case X86::CMOV_GR8:
14333 case X86::CMOV_FR32:
14334 case X86::CMOV_FR64:
14335 case X86::CMOV_V4F32:
14336 case X86::CMOV_V2F64:
14337 case X86::CMOV_V2I64:
14338 case X86::CMOV_V8F32:
14339 case X86::CMOV_V4F64:
14340 case X86::CMOV_V4I64:
14341 case X86::CMOV_GR16:
14342 case X86::CMOV_GR32:
14343 case X86::CMOV_RFP32:
14344 case X86::CMOV_RFP64:
14345 case X86::CMOV_RFP80:
14346 return EmitLoweredSelect(MI, BB);
14348 case X86::FP32_TO_INT16_IN_MEM:
14349 case X86::FP32_TO_INT32_IN_MEM:
14350 case X86::FP32_TO_INT64_IN_MEM:
14351 case X86::FP64_TO_INT16_IN_MEM:
14352 case X86::FP64_TO_INT32_IN_MEM:
14353 case X86::FP64_TO_INT64_IN_MEM:
14354 case X86::FP80_TO_INT16_IN_MEM:
14355 case X86::FP80_TO_INT32_IN_MEM:
14356 case X86::FP80_TO_INT64_IN_MEM: {
14357 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14358 DebugLoc DL = MI->getDebugLoc();
14360 // Change the floating point control register to use "round towards zero"
14361 // mode when truncating to an integer value.
14362 MachineFunction *F = BB->getParent();
14363 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
14364 addFrameReference(BuildMI(*BB, MI, DL,
14365 TII->get(X86::FNSTCW16m)), CWFrameIdx);
14367 // Load the old value of the high byte of the control word...
14369 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
14370 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
14373 // Set the high part to be round to zero...
14374 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
14377 // Reload the modified control word now...
14378 addFrameReference(BuildMI(*BB, MI, DL,
14379 TII->get(X86::FLDCW16m)), CWFrameIdx);
14381 // Restore the memory image of control word to original value
14382 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
14385 // Get the X86 opcode to use.
14387 switch (MI->getOpcode()) {
14388 default: llvm_unreachable("illegal opcode!");
14389 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
14390 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
14391 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
14392 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
14393 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
14394 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
14395 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
14396 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
14397 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
14401 MachineOperand &Op = MI->getOperand(0);
14403 AM.BaseType = X86AddressMode::RegBase;
14404 AM.Base.Reg = Op.getReg();
14406 AM.BaseType = X86AddressMode::FrameIndexBase;
14407 AM.Base.FrameIndex = Op.getIndex();
14409 Op = MI->getOperand(1);
14411 AM.Scale = Op.getImm();
14412 Op = MI->getOperand(2);
14414 AM.IndexReg = Op.getImm();
14415 Op = MI->getOperand(3);
14416 if (Op.isGlobal()) {
14417 AM.GV = Op.getGlobal();
14419 AM.Disp = Op.getImm();
14421 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
14422 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
14424 // Reload the original control word now.
14425 addFrameReference(BuildMI(*BB, MI, DL,
14426 TII->get(X86::FLDCW16m)), CWFrameIdx);
14428 MI->eraseFromParent(); // The pseudo instruction is gone now.
14431 // String/text processing lowering.
14432 case X86::PCMPISTRM128REG:
14433 case X86::VPCMPISTRM128REG:
14434 case X86::PCMPISTRM128MEM:
14435 case X86::VPCMPISTRM128MEM:
14436 case X86::PCMPESTRM128REG:
14437 case X86::VPCMPESTRM128REG:
14438 case X86::PCMPESTRM128MEM:
14439 case X86::VPCMPESTRM128MEM:
14440 assert(Subtarget->hasSSE42() &&
14441 "Target must have SSE4.2 or AVX features enabled");
14442 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
14444 // String/text processing lowering.
14445 case X86::PCMPISTRIREG:
14446 case X86::VPCMPISTRIREG:
14447 case X86::PCMPISTRIMEM:
14448 case X86::VPCMPISTRIMEM:
14449 case X86::PCMPESTRIREG:
14450 case X86::VPCMPESTRIREG:
14451 case X86::PCMPESTRIMEM:
14452 case X86::VPCMPESTRIMEM:
14453 assert(Subtarget->hasSSE42() &&
14454 "Target must have SSE4.2 or AVX features enabled");
14455 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
14457 // Thread synchronization.
14459 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
14463 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
14465 // Atomic Lowering.
14466 case X86::ATOMAND8:
14467 case X86::ATOMAND16:
14468 case X86::ATOMAND32:
14469 case X86::ATOMAND64:
14472 case X86::ATOMOR16:
14473 case X86::ATOMOR32:
14474 case X86::ATOMOR64:
14476 case X86::ATOMXOR16:
14477 case X86::ATOMXOR8:
14478 case X86::ATOMXOR32:
14479 case X86::ATOMXOR64:
14481 case X86::ATOMNAND8:
14482 case X86::ATOMNAND16:
14483 case X86::ATOMNAND32:
14484 case X86::ATOMNAND64:
14486 case X86::ATOMMAX8:
14487 case X86::ATOMMAX16:
14488 case X86::ATOMMAX32:
14489 case X86::ATOMMAX64:
14491 case X86::ATOMMIN8:
14492 case X86::ATOMMIN16:
14493 case X86::ATOMMIN32:
14494 case X86::ATOMMIN64:
14496 case X86::ATOMUMAX8:
14497 case X86::ATOMUMAX16:
14498 case X86::ATOMUMAX32:
14499 case X86::ATOMUMAX64:
14501 case X86::ATOMUMIN8:
14502 case X86::ATOMUMIN16:
14503 case X86::ATOMUMIN32:
14504 case X86::ATOMUMIN64:
14505 return EmitAtomicLoadArith(MI, BB);
14507 // This group does 64-bit operations on a 32-bit host.
14508 case X86::ATOMAND6432:
14509 case X86::ATOMOR6432:
14510 case X86::ATOMXOR6432:
14511 case X86::ATOMNAND6432:
14512 case X86::ATOMADD6432:
14513 case X86::ATOMSUB6432:
14514 case X86::ATOMMAX6432:
14515 case X86::ATOMMIN6432:
14516 case X86::ATOMUMAX6432:
14517 case X86::ATOMUMIN6432:
14518 case X86::ATOMSWAP6432:
14519 return EmitAtomicLoadArith6432(MI, BB);
14521 case X86::VASTART_SAVE_XMM_REGS:
14522 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
14524 case X86::VAARG_64:
14525 return EmitVAARG64WithCustomInserter(MI, BB);
14527 case X86::EH_SjLj_SetJmp32:
14528 case X86::EH_SjLj_SetJmp64:
14529 return emitEHSjLjSetJmp(MI, BB);
14531 case X86::EH_SjLj_LongJmp32:
14532 case X86::EH_SjLj_LongJmp64:
14533 return emitEHSjLjLongJmp(MI, BB);
14537 //===----------------------------------------------------------------------===//
14538 // X86 Optimization Hooks
14539 //===----------------------------------------------------------------------===//
14541 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
14544 const SelectionDAG &DAG,
14545 unsigned Depth) const {
14546 unsigned BitWidth = KnownZero.getBitWidth();
14547 unsigned Opc = Op.getOpcode();
14548 assert((Opc >= ISD::BUILTIN_OP_END ||
14549 Opc == ISD::INTRINSIC_WO_CHAIN ||
14550 Opc == ISD::INTRINSIC_W_CHAIN ||
14551 Opc == ISD::INTRINSIC_VOID) &&
14552 "Should use MaskedValueIsZero if you don't know whether Op"
14553 " is a target node!");
14555 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
14569 // These nodes' second result is a boolean.
14570 if (Op.getResNo() == 0)
14573 case X86ISD::SETCC:
14574 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
14576 case ISD::INTRINSIC_WO_CHAIN: {
14577 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14578 unsigned NumLoBits = 0;
14581 case Intrinsic::x86_sse_movmsk_ps:
14582 case Intrinsic::x86_avx_movmsk_ps_256:
14583 case Intrinsic::x86_sse2_movmsk_pd:
14584 case Intrinsic::x86_avx_movmsk_pd_256:
14585 case Intrinsic::x86_mmx_pmovmskb:
14586 case Intrinsic::x86_sse2_pmovmskb_128:
14587 case Intrinsic::x86_avx2_pmovmskb: {
14588 // High bits of movmskp{s|d}, pmovmskb are known zero.
14590 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14591 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
14592 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
14593 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
14594 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
14595 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
14596 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
14597 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
14599 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
14608 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
14609 unsigned Depth) const {
14610 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
14611 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14612 return Op.getValueType().getScalarType().getSizeInBits();
14618 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
14619 /// node is a GlobalAddress + offset.
14620 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
14621 const GlobalValue* &GA,
14622 int64_t &Offset) const {
14623 if (N->getOpcode() == X86ISD::Wrapper) {
14624 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
14625 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
14626 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
14630 return TargetLowering::isGAPlusOffset(N, GA, Offset);
14633 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
14634 /// same as extracting the high 128-bit part of 256-bit vector and then
14635 /// inserting the result into the low part of a new 256-bit vector
14636 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
14637 EVT VT = SVOp->getValueType(0);
14638 unsigned NumElems = VT.getVectorNumElements();
14640 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14641 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
14642 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14643 SVOp->getMaskElt(j) >= 0)
14649 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
14650 /// same as extracting the low 128-bit part of 256-bit vector and then
14651 /// inserting the result into the high part of a new 256-bit vector
14652 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
14653 EVT VT = SVOp->getValueType(0);
14654 unsigned NumElems = VT.getVectorNumElements();
14656 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14657 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
14658 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14659 SVOp->getMaskElt(j) >= 0)
14665 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
14666 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
14667 TargetLowering::DAGCombinerInfo &DCI,
14668 const X86Subtarget* Subtarget) {
14669 DebugLoc dl = N->getDebugLoc();
14670 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
14671 SDValue V1 = SVOp->getOperand(0);
14672 SDValue V2 = SVOp->getOperand(1);
14673 EVT VT = SVOp->getValueType(0);
14674 unsigned NumElems = VT.getVectorNumElements();
14676 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
14677 V2.getOpcode() == ISD::CONCAT_VECTORS) {
14681 // V UNDEF BUILD_VECTOR UNDEF
14683 // CONCAT_VECTOR CONCAT_VECTOR
14686 // RESULT: V + zero extended
14688 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
14689 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
14690 V1.getOperand(1).getOpcode() != ISD::UNDEF)
14693 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
14696 // To match the shuffle mask, the first half of the mask should
14697 // be exactly the first vector, and all the rest a splat with the
14698 // first element of the second one.
14699 for (unsigned i = 0; i != NumElems/2; ++i)
14700 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
14701 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
14704 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
14705 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
14706 if (Ld->hasNUsesOfValue(1, 0)) {
14707 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
14708 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
14710 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
14712 Ld->getPointerInfo(),
14713 Ld->getAlignment(),
14714 false/*isVolatile*/, true/*ReadMem*/,
14715 false/*WriteMem*/);
14717 // Make sure the newly-created LOAD is in the same position as Ld in
14718 // terms of dependency. We create a TokenFactor for Ld and ResNode,
14719 // and update uses of Ld's output chain to use the TokenFactor.
14720 if (Ld->hasAnyUseOfValue(1)) {
14721 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
14722 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
14723 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
14724 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
14725 SDValue(ResNode.getNode(), 1));
14728 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
14732 // Emit a zeroed vector and insert the desired subvector on its
14734 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
14735 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
14736 return DCI.CombineTo(N, InsV);
14739 //===--------------------------------------------------------------------===//
14740 // Combine some shuffles into subvector extracts and inserts:
14743 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14744 if (isShuffleHigh128VectorInsertLow(SVOp)) {
14745 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
14746 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
14747 return DCI.CombineTo(N, InsV);
14750 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14751 if (isShuffleLow128VectorInsertHigh(SVOp)) {
14752 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
14753 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
14754 return DCI.CombineTo(N, InsV);
14760 /// PerformShuffleCombine - Performs several different shuffle combines.
14761 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
14762 TargetLowering::DAGCombinerInfo &DCI,
14763 const X86Subtarget *Subtarget) {
14764 DebugLoc dl = N->getDebugLoc();
14765 EVT VT = N->getValueType(0);
14767 // Don't create instructions with illegal types after legalize types has run.
14768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14769 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
14772 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
14773 if (Subtarget->hasFp256() && VT.is256BitVector() &&
14774 N->getOpcode() == ISD::VECTOR_SHUFFLE)
14775 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
14777 // Only handle 128 wide vector from here on.
14778 if (!VT.is128BitVector())
14781 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
14782 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
14783 // consecutive, non-overlapping, and in the right order.
14784 SmallVector<SDValue, 16> Elts;
14785 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
14786 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
14788 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
14791 /// PerformTruncateCombine - Converts truncate operation to
14792 /// a sequence of vector shuffle operations.
14793 /// It is possible when we truncate 256-bit vector to 128-bit vector
14794 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
14795 TargetLowering::DAGCombinerInfo &DCI,
14796 const X86Subtarget *Subtarget) {
14800 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
14801 /// specific shuffle of a load can be folded into a single element load.
14802 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
14803 /// shuffles have been customed lowered so we need to handle those here.
14804 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
14805 TargetLowering::DAGCombinerInfo &DCI) {
14806 if (DCI.isBeforeLegalizeOps())
14809 SDValue InVec = N->getOperand(0);
14810 SDValue EltNo = N->getOperand(1);
14812 if (!isa<ConstantSDNode>(EltNo))
14815 EVT VT = InVec.getValueType();
14817 bool HasShuffleIntoBitcast = false;
14818 if (InVec.getOpcode() == ISD::BITCAST) {
14819 // Don't duplicate a load with other uses.
14820 if (!InVec.hasOneUse())
14822 EVT BCVT = InVec.getOperand(0).getValueType();
14823 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
14825 InVec = InVec.getOperand(0);
14826 HasShuffleIntoBitcast = true;
14829 if (!isTargetShuffle(InVec.getOpcode()))
14832 // Don't duplicate a load with other uses.
14833 if (!InVec.hasOneUse())
14836 SmallVector<int, 16> ShuffleMask;
14838 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
14842 // Select the input vector, guarding against out of range extract vector.
14843 unsigned NumElems = VT.getVectorNumElements();
14844 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
14845 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
14846 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
14847 : InVec.getOperand(1);
14849 // If inputs to shuffle are the same for both ops, then allow 2 uses
14850 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
14852 if (LdNode.getOpcode() == ISD::BITCAST) {
14853 // Don't duplicate a load with other uses.
14854 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
14857 AllowedUses = 1; // only allow 1 load use if we have a bitcast
14858 LdNode = LdNode.getOperand(0);
14861 if (!ISD::isNormalLoad(LdNode.getNode()))
14864 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
14866 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
14869 if (HasShuffleIntoBitcast) {
14870 // If there's a bitcast before the shuffle, check if the load type and
14871 // alignment is valid.
14872 unsigned Align = LN0->getAlignment();
14873 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14874 unsigned NewAlign = TLI.getDataLayout()->
14875 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
14877 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
14881 // All checks match so transform back to vector_shuffle so that DAG combiner
14882 // can finish the job
14883 DebugLoc dl = N->getDebugLoc();
14885 // Create shuffle node taking into account the case that its a unary shuffle
14886 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
14887 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
14888 InVec.getOperand(0), Shuffle,
14890 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
14891 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
14895 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
14896 /// generation and convert it from being a bunch of shuffles and extracts
14897 /// to a simple store and scalar loads to extract the elements.
14898 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
14899 TargetLowering::DAGCombinerInfo &DCI) {
14900 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
14901 if (NewOp.getNode())
14904 SDValue InputVector = N->getOperand(0);
14905 // Detect whether we are trying to convert from mmx to i32 and the bitcast
14906 // from mmx to v2i32 has a single usage.
14907 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
14908 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
14909 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
14910 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(),
14911 N->getValueType(0),
14912 InputVector.getNode()->getOperand(0));
14914 // Only operate on vectors of 4 elements, where the alternative shuffling
14915 // gets to be more expensive.
14916 if (InputVector.getValueType() != MVT::v4i32)
14919 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
14920 // single use which is a sign-extend or zero-extend, and all elements are
14922 SmallVector<SDNode *, 4> Uses;
14923 unsigned ExtractedElements = 0;
14924 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
14925 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
14926 if (UI.getUse().getResNo() != InputVector.getResNo())
14929 SDNode *Extract = *UI;
14930 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14933 if (Extract->getValueType(0) != MVT::i32)
14935 if (!Extract->hasOneUse())
14937 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
14938 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
14940 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
14943 // Record which element was extracted.
14944 ExtractedElements |=
14945 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
14947 Uses.push_back(Extract);
14950 // If not all the elements were used, this may not be worthwhile.
14951 if (ExtractedElements != 15)
14954 // Ok, we've now decided to do the transformation.
14955 DebugLoc dl = InputVector.getDebugLoc();
14957 // Store the value to a temporary stack slot.
14958 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
14959 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
14960 MachinePointerInfo(), false, false, 0);
14962 // Replace each use (extract) with a load of the appropriate element.
14963 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
14964 UE = Uses.end(); UI != UE; ++UI) {
14965 SDNode *Extract = *UI;
14967 // cOMpute the element's address.
14968 SDValue Idx = Extract->getOperand(1);
14970 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
14971 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
14972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14973 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
14975 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
14976 StackPtr, OffsetVal);
14978 // Load the scalar.
14979 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
14980 ScalarAddr, MachinePointerInfo(),
14981 false, false, false, 0);
14983 // Replace the exact with the load.
14984 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
14987 // The replacement was made in place; don't return anything.
14991 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
14992 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
14993 SDValue RHS, SelectionDAG &DAG,
14994 const X86Subtarget *Subtarget) {
14995 if (!VT.isVector())
14998 switch (VT.getSimpleVT().SimpleTy) {
15003 if (!Subtarget->hasAVX2())
15008 if (!Subtarget->hasSSE2())
15012 // SSE2 has only a small subset of the operations.
15013 bool hasUnsigned = Subtarget->hasSSE41() ||
15014 (Subtarget->hasSSE2() && VT == MVT::v16i8);
15015 bool hasSigned = Subtarget->hasSSE41() ||
15016 (Subtarget->hasSSE2() && VT == MVT::v8i16);
15018 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15020 // Check for x CC y ? x : y.
15021 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15022 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15027 return hasUnsigned ? X86ISD::UMIN : 0;
15030 return hasUnsigned ? X86ISD::UMAX : 0;
15033 return hasSigned ? X86ISD::SMIN : 0;
15036 return hasSigned ? X86ISD::SMAX : 0;
15038 // Check for x CC y ? y : x -- a min/max with reversed arms.
15039 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15040 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15045 return hasUnsigned ? X86ISD::UMAX : 0;
15048 return hasUnsigned ? X86ISD::UMIN : 0;
15051 return hasSigned ? X86ISD::SMAX : 0;
15054 return hasSigned ? X86ISD::SMIN : 0;
15061 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
15063 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
15064 TargetLowering::DAGCombinerInfo &DCI,
15065 const X86Subtarget *Subtarget) {
15066 DebugLoc DL = N->getDebugLoc();
15067 SDValue Cond = N->getOperand(0);
15068 // Get the LHS/RHS of the select.
15069 SDValue LHS = N->getOperand(1);
15070 SDValue RHS = N->getOperand(2);
15071 EVT VT = LHS.getValueType();
15073 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
15074 // instructions match the semantics of the common C idiom x<y?x:y but not
15075 // x<=y?x:y, because of how they handle negative zero (which can be
15076 // ignored in unsafe-math mode).
15077 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
15078 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
15079 (Subtarget->hasSSE2() ||
15080 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
15081 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15083 unsigned Opcode = 0;
15084 // Check for x CC y ? x : y.
15085 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15086 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15090 // Converting this to a min would handle NaNs incorrectly, and swapping
15091 // the operands would cause it to handle comparisons between positive
15092 // and negative zero incorrectly.
15093 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15094 if (!DAG.getTarget().Options.UnsafeFPMath &&
15095 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15097 std::swap(LHS, RHS);
15099 Opcode = X86ISD::FMIN;
15102 // Converting this to a min would handle comparisons between positive
15103 // and negative zero incorrectly.
15104 if (!DAG.getTarget().Options.UnsafeFPMath &&
15105 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15107 Opcode = X86ISD::FMIN;
15110 // Converting this to a min would handle both negative zeros and NaNs
15111 // incorrectly, but we can swap the operands to fix both.
15112 std::swap(LHS, RHS);
15116 Opcode = X86ISD::FMIN;
15120 // Converting this to a max would handle comparisons between positive
15121 // and negative zero incorrectly.
15122 if (!DAG.getTarget().Options.UnsafeFPMath &&
15123 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15125 Opcode = X86ISD::FMAX;
15128 // Converting this to a max would handle NaNs incorrectly, and swapping
15129 // the operands would cause it to handle comparisons between positive
15130 // and negative zero incorrectly.
15131 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15132 if (!DAG.getTarget().Options.UnsafeFPMath &&
15133 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15135 std::swap(LHS, RHS);
15137 Opcode = X86ISD::FMAX;
15140 // Converting this to a max would handle both negative zeros and NaNs
15141 // incorrectly, but we can swap the operands to fix both.
15142 std::swap(LHS, RHS);
15146 Opcode = X86ISD::FMAX;
15149 // Check for x CC y ? y : x -- a min/max with reversed arms.
15150 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15151 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15155 // Converting this to a min would handle comparisons between positive
15156 // and negative zero incorrectly, and swapping the operands would
15157 // cause it to handle NaNs incorrectly.
15158 if (!DAG.getTarget().Options.UnsafeFPMath &&
15159 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
15160 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15162 std::swap(LHS, RHS);
15164 Opcode = X86ISD::FMIN;
15167 // Converting this to a min would handle NaNs incorrectly.
15168 if (!DAG.getTarget().Options.UnsafeFPMath &&
15169 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
15171 Opcode = X86ISD::FMIN;
15174 // Converting this to a min would handle both negative zeros and NaNs
15175 // incorrectly, but we can swap the operands to fix both.
15176 std::swap(LHS, RHS);
15180 Opcode = X86ISD::FMIN;
15184 // Converting this to a max would handle NaNs incorrectly.
15185 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15187 Opcode = X86ISD::FMAX;
15190 // Converting this to a max would handle comparisons between positive
15191 // and negative zero incorrectly, and swapping the operands would
15192 // cause it to handle NaNs incorrectly.
15193 if (!DAG.getTarget().Options.UnsafeFPMath &&
15194 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
15195 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15197 std::swap(LHS, RHS);
15199 Opcode = X86ISD::FMAX;
15202 // Converting this to a max would handle both negative zeros and NaNs
15203 // incorrectly, but we can swap the operands to fix both.
15204 std::swap(LHS, RHS);
15208 Opcode = X86ISD::FMAX;
15214 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
15217 // If this is a select between two integer constants, try to do some
15219 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
15220 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
15221 // Don't do this for crazy integer types.
15222 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
15223 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
15224 // so that TrueC (the true value) is larger than FalseC.
15225 bool NeedsCondInvert = false;
15227 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
15228 // Efficiently invertible.
15229 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15230 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15231 isa<ConstantSDNode>(Cond.getOperand(1))))) {
15232 NeedsCondInvert = true;
15233 std::swap(TrueC, FalseC);
15236 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
15237 if (FalseC->getAPIntValue() == 0 &&
15238 TrueC->getAPIntValue().isPowerOf2()) {
15239 if (NeedsCondInvert) // Invert the condition if needed.
15240 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15241 DAG.getConstant(1, Cond.getValueType()));
15243 // Zero extend the condition if needed.
15244 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
15246 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15247 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15248 DAG.getConstant(ShAmt, MVT::i8));
15251 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
15252 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15253 if (NeedsCondInvert) // Invert the condition if needed.
15254 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15255 DAG.getConstant(1, Cond.getValueType()));
15257 // Zero extend the condition if needed.
15258 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15259 FalseC->getValueType(0), Cond);
15260 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15261 SDValue(FalseC, 0));
15264 // Optimize cases that will turn into an LEA instruction. This requires
15265 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15266 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15267 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15268 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15270 bool isFastMultiplier = false;
15272 switch ((unsigned char)Diff) {
15274 case 1: // result = add base, cond
15275 case 2: // result = lea base( , cond*2)
15276 case 3: // result = lea base(cond, cond*2)
15277 case 4: // result = lea base( , cond*4)
15278 case 5: // result = lea base(cond, cond*4)
15279 case 8: // result = lea base( , cond*8)
15280 case 9: // result = lea base(cond, cond*8)
15281 isFastMultiplier = true;
15286 if (isFastMultiplier) {
15287 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15288 if (NeedsCondInvert) // Invert the condition if needed.
15289 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15290 DAG.getConstant(1, Cond.getValueType()));
15292 // Zero extend the condition if needed.
15293 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15295 // Scale the condition by the difference.
15297 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15298 DAG.getConstant(Diff, Cond.getValueType()));
15300 // Add the base if non-zero.
15301 if (FalseC->getAPIntValue() != 0)
15302 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15303 SDValue(FalseC, 0));
15310 // Canonicalize max and min:
15311 // (x > y) ? x : y -> (x >= y) ? x : y
15312 // (x < y) ? x : y -> (x <= y) ? x : y
15313 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
15314 // the need for an extra compare
15315 // against zero. e.g.
15316 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
15318 // testl %edi, %edi
15320 // cmovgl %edi, %eax
15324 // cmovsl %eax, %edi
15325 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
15326 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15327 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15328 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15333 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
15334 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
15335 Cond.getOperand(0), Cond.getOperand(1), NewCC);
15336 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
15341 // Match VSELECTs into subs with unsigned saturation.
15342 if (!DCI.isBeforeLegalize() &&
15343 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
15344 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
15345 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
15346 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
15347 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15349 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
15350 // left side invert the predicate to simplify logic below.
15352 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
15354 CC = ISD::getSetCCInverse(CC, true);
15355 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
15359 if (Other.getNode() && Other->getNumOperands() == 2 &&
15360 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
15361 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
15362 SDValue CondRHS = Cond->getOperand(1);
15364 // Look for a general sub with unsigned saturation first.
15365 // x >= y ? x-y : 0 --> subus x, y
15366 // x > y ? x-y : 0 --> subus x, y
15367 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
15368 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
15369 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15371 // If the RHS is a constant we have to reverse the const canonicalization.
15372 // x > C-1 ? x+-C : 0 --> subus x, C
15373 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
15374 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
15375 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15376 if (CondRHS.getConstantOperandVal(0) == -A-1)
15377 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
15378 DAG.getConstant(-A, VT));
15381 // Another special case: If C was a sign bit, the sub has been
15382 // canonicalized into a xor.
15383 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
15384 // it's safe to decanonicalize the xor?
15385 // x s< 0 ? x^C : 0 --> subus x, C
15386 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
15387 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
15388 isSplatVector(OpRHS.getNode())) {
15389 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15391 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15396 // Try to match a min/max vector operation.
15397 if (!DCI.isBeforeLegalize() &&
15398 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
15399 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
15400 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
15402 // If we know that this node is legal then we know that it is going to be
15403 // matched by one of the SSE/AVX BLEND instructions. These instructions only
15404 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
15405 // to simplify previous instructions.
15406 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15407 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
15408 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
15409 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
15411 // Don't optimize vector selects that map to mask-registers.
15415 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
15416 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
15418 APInt KnownZero, KnownOne;
15419 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
15420 DCI.isBeforeLegalizeOps());
15421 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
15422 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
15423 DCI.CommitTargetLoweringOpt(TLO);
15429 // Check whether a boolean test is testing a boolean value generated by
15430 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
15433 // Simplify the following patterns:
15434 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
15435 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
15436 // to (Op EFLAGS Cond)
15438 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
15439 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
15440 // to (Op EFLAGS !Cond)
15442 // where Op could be BRCOND or CMOV.
15444 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
15445 // Quit if not CMP and SUB with its value result used.
15446 if (Cmp.getOpcode() != X86ISD::CMP &&
15447 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
15450 // Quit if not used as a boolean value.
15451 if (CC != X86::COND_E && CC != X86::COND_NE)
15454 // Check CMP operands. One of them should be 0 or 1 and the other should be
15455 // an SetCC or extended from it.
15456 SDValue Op1 = Cmp.getOperand(0);
15457 SDValue Op2 = Cmp.getOperand(1);
15460 const ConstantSDNode* C = 0;
15461 bool needOppositeCond = (CC == X86::COND_E);
15463 if ((C = dyn_cast<ConstantSDNode>(Op1)))
15465 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
15467 else // Quit if all operands are not constants.
15470 if (C->getZExtValue() == 1)
15471 needOppositeCond = !needOppositeCond;
15472 else if (C->getZExtValue() != 0)
15473 // Quit if the constant is neither 0 or 1.
15476 // Skip 'zext' node.
15477 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
15478 SetCC = SetCC.getOperand(0);
15480 switch (SetCC.getOpcode()) {
15481 case X86ISD::SETCC:
15482 // Set the condition code or opposite one if necessary.
15483 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
15484 if (needOppositeCond)
15485 CC = X86::GetOppositeBranchCondition(CC);
15486 return SetCC.getOperand(1);
15487 case X86ISD::CMOV: {
15488 // Check whether false/true value has canonical one, i.e. 0 or 1.
15489 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
15490 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
15491 // Quit if true value is not a constant.
15494 // Quit if false value is not a constant.
15496 // A special case for rdrand, where 0 is set if false cond is found.
15497 SDValue Op = SetCC.getOperand(0);
15498 if (Op.getOpcode() != X86ISD::RDRAND)
15501 // Quit if false value is not the constant 0 or 1.
15502 bool FValIsFalse = true;
15503 if (FVal && FVal->getZExtValue() != 0) {
15504 if (FVal->getZExtValue() != 1)
15506 // If FVal is 1, opposite cond is needed.
15507 needOppositeCond = !needOppositeCond;
15508 FValIsFalse = false;
15510 // Quit if TVal is not the constant opposite of FVal.
15511 if (FValIsFalse && TVal->getZExtValue() != 1)
15513 if (!FValIsFalse && TVal->getZExtValue() != 0)
15515 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
15516 if (needOppositeCond)
15517 CC = X86::GetOppositeBranchCondition(CC);
15518 return SetCC.getOperand(3);
15525 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
15526 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
15527 TargetLowering::DAGCombinerInfo &DCI,
15528 const X86Subtarget *Subtarget) {
15529 DebugLoc DL = N->getDebugLoc();
15531 // If the flag operand isn't dead, don't touch this CMOV.
15532 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
15535 SDValue FalseOp = N->getOperand(0);
15536 SDValue TrueOp = N->getOperand(1);
15537 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
15538 SDValue Cond = N->getOperand(3);
15540 if (CC == X86::COND_E || CC == X86::COND_NE) {
15541 switch (Cond.getOpcode()) {
15545 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
15546 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
15547 return (CC == X86::COND_E) ? FalseOp : TrueOp;
15553 Flags = checkBoolTestSetCCCombine(Cond, CC);
15554 if (Flags.getNode() &&
15555 // Extra check as FCMOV only supports a subset of X86 cond.
15556 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
15557 SDValue Ops[] = { FalseOp, TrueOp,
15558 DAG.getConstant(CC, MVT::i8), Flags };
15559 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
15560 Ops, array_lengthof(Ops));
15563 // If this is a select between two integer constants, try to do some
15564 // optimizations. Note that the operands are ordered the opposite of SELECT
15566 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
15567 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
15568 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
15569 // larger than FalseC (the false value).
15570 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
15571 CC = X86::GetOppositeBranchCondition(CC);
15572 std::swap(TrueC, FalseC);
15573 std::swap(TrueOp, FalseOp);
15576 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
15577 // This is efficient for any integer data type (including i8/i16) and
15579 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
15580 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15581 DAG.getConstant(CC, MVT::i8), Cond);
15583 // Zero extend the condition if needed.
15584 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
15586 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15587 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
15588 DAG.getConstant(ShAmt, MVT::i8));
15589 if (N->getNumValues() == 2) // Dead flag value?
15590 return DCI.CombineTo(N, Cond, SDValue());
15594 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
15595 // for any integer data type, including i8/i16.
15596 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15597 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15598 DAG.getConstant(CC, MVT::i8), Cond);
15600 // Zero extend the condition if needed.
15601 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15602 FalseC->getValueType(0), Cond);
15603 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15604 SDValue(FalseC, 0));
15606 if (N->getNumValues() == 2) // Dead flag value?
15607 return DCI.CombineTo(N, Cond, SDValue());
15611 // Optimize cases that will turn into an LEA instruction. This requires
15612 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15613 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15614 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15615 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15617 bool isFastMultiplier = false;
15619 switch ((unsigned char)Diff) {
15621 case 1: // result = add base, cond
15622 case 2: // result = lea base( , cond*2)
15623 case 3: // result = lea base(cond, cond*2)
15624 case 4: // result = lea base( , cond*4)
15625 case 5: // result = lea base(cond, cond*4)
15626 case 8: // result = lea base( , cond*8)
15627 case 9: // result = lea base(cond, cond*8)
15628 isFastMultiplier = true;
15633 if (isFastMultiplier) {
15634 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15635 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15636 DAG.getConstant(CC, MVT::i8), Cond);
15637 // Zero extend the condition if needed.
15638 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15640 // Scale the condition by the difference.
15642 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15643 DAG.getConstant(Diff, Cond.getValueType()));
15645 // Add the base if non-zero.
15646 if (FalseC->getAPIntValue() != 0)
15647 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15648 SDValue(FalseC, 0));
15649 if (N->getNumValues() == 2) // Dead flag value?
15650 return DCI.CombineTo(N, Cond, SDValue());
15657 // Handle these cases:
15658 // (select (x != c), e, c) -> select (x != c), e, x),
15659 // (select (x == c), c, e) -> select (x == c), x, e)
15660 // where the c is an integer constant, and the "select" is the combination
15661 // of CMOV and CMP.
15663 // The rationale for this change is that the conditional-move from a constant
15664 // needs two instructions, however, conditional-move from a register needs
15665 // only one instruction.
15667 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
15668 // some instruction-combining opportunities. This opt needs to be
15669 // postponed as late as possible.
15671 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
15672 // the DCI.xxxx conditions are provided to postpone the optimization as
15673 // late as possible.
15675 ConstantSDNode *CmpAgainst = 0;
15676 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
15677 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
15678 !isa<ConstantSDNode>(Cond.getOperand(0))) {
15680 if (CC == X86::COND_NE &&
15681 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
15682 CC = X86::GetOppositeBranchCondition(CC);
15683 std::swap(TrueOp, FalseOp);
15686 if (CC == X86::COND_E &&
15687 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
15688 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
15689 DAG.getConstant(CC, MVT::i8), Cond };
15690 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
15691 array_lengthof(Ops));
15699 /// PerformMulCombine - Optimize a single multiply with constant into two
15700 /// in order to implement it with two cheaper instructions, e.g.
15701 /// LEA + SHL, LEA + LEA.
15702 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
15703 TargetLowering::DAGCombinerInfo &DCI) {
15704 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15707 EVT VT = N->getValueType(0);
15708 if (VT != MVT::i64)
15711 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
15714 uint64_t MulAmt = C->getZExtValue();
15715 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
15718 uint64_t MulAmt1 = 0;
15719 uint64_t MulAmt2 = 0;
15720 if ((MulAmt % 9) == 0) {
15722 MulAmt2 = MulAmt / 9;
15723 } else if ((MulAmt % 5) == 0) {
15725 MulAmt2 = MulAmt / 5;
15726 } else if ((MulAmt % 3) == 0) {
15728 MulAmt2 = MulAmt / 3;
15731 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
15732 DebugLoc DL = N->getDebugLoc();
15734 if (isPowerOf2_64(MulAmt2) &&
15735 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
15736 // If second multiplifer is pow2, issue it first. We want the multiply by
15737 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
15739 std::swap(MulAmt1, MulAmt2);
15742 if (isPowerOf2_64(MulAmt1))
15743 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15744 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
15746 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
15747 DAG.getConstant(MulAmt1, VT));
15749 if (isPowerOf2_64(MulAmt2))
15750 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
15751 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
15753 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
15754 DAG.getConstant(MulAmt2, VT));
15756 // Do not add new nodes to DAG combiner worklist.
15757 DCI.CombineTo(N, NewMul, false);
15762 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
15763 SDValue N0 = N->getOperand(0);
15764 SDValue N1 = N->getOperand(1);
15765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
15766 EVT VT = N0.getValueType();
15768 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
15769 // since the result of setcc_c is all zero's or all ones.
15770 if (VT.isInteger() && !VT.isVector() &&
15771 N1C && N0.getOpcode() == ISD::AND &&
15772 N0.getOperand(1).getOpcode() == ISD::Constant) {
15773 SDValue N00 = N0.getOperand(0);
15774 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
15775 ((N00.getOpcode() == ISD::ANY_EXTEND ||
15776 N00.getOpcode() == ISD::ZERO_EXTEND) &&
15777 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
15778 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
15779 APInt ShAmt = N1C->getAPIntValue();
15780 Mask = Mask.shl(ShAmt);
15782 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
15783 N00, DAG.getConstant(Mask, VT));
15787 // Hardware support for vector shifts is sparse which makes us scalarize the
15788 // vector operations in many cases. Also, on sandybridge ADD is faster than
15790 // (shl V, 1) -> add V,V
15791 if (isSplatVector(N1.getNode())) {
15792 assert(N0.getValueType().isVector() && "Invalid vector shift type");
15793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
15794 // We shift all of the values by one. In many cases we do not have
15795 // hardware support for this operation. This is better expressed as an ADD
15797 if (N1C && (1 == N1C->getZExtValue())) {
15798 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
15805 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
15807 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
15808 TargetLowering::DAGCombinerInfo &DCI,
15809 const X86Subtarget *Subtarget) {
15810 EVT VT = N->getValueType(0);
15811 if (N->getOpcode() == ISD::SHL) {
15812 SDValue V = PerformSHLCombine(N, DAG);
15813 if (V.getNode()) return V;
15816 // On X86 with SSE2 support, we can transform this to a vector shift if
15817 // all elements are shifted by the same amount. We can't do this in legalize
15818 // because the a constant vector is typically transformed to a constant pool
15819 // so we have no knowledge of the shift amount.
15820 if (!Subtarget->hasSSE2())
15823 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
15824 (!Subtarget->hasInt256() ||
15825 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
15828 SDValue ShAmtOp = N->getOperand(1);
15829 EVT EltVT = VT.getVectorElementType();
15830 DebugLoc DL = N->getDebugLoc();
15831 SDValue BaseShAmt = SDValue();
15832 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
15833 unsigned NumElts = VT.getVectorNumElements();
15835 for (; i != NumElts; ++i) {
15836 SDValue Arg = ShAmtOp.getOperand(i);
15837 if (Arg.getOpcode() == ISD::UNDEF) continue;
15841 // Handle the case where the build_vector is all undef
15842 // FIXME: Should DAG allow this?
15846 for (; i != NumElts; ++i) {
15847 SDValue Arg = ShAmtOp.getOperand(i);
15848 if (Arg.getOpcode() == ISD::UNDEF) continue;
15849 if (Arg != BaseShAmt) {
15853 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
15854 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
15855 SDValue InVec = ShAmtOp.getOperand(0);
15856 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15857 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15859 for (; i != NumElts; ++i) {
15860 SDValue Arg = InVec.getOperand(i);
15861 if (Arg.getOpcode() == ISD::UNDEF) continue;
15865 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15866 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15867 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
15868 if (C->getZExtValue() == SplatIdx)
15869 BaseShAmt = InVec.getOperand(1);
15872 if (BaseShAmt.getNode() == 0) {
15873 // Don't create instructions with illegal types after legalize
15875 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
15876 !DCI.isBeforeLegalize())
15879 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
15880 DAG.getIntPtrConstant(0));
15885 // The shift amount is an i32.
15886 if (EltVT.bitsGT(MVT::i32))
15887 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
15888 else if (EltVT.bitsLT(MVT::i32))
15889 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
15891 // The shift amount is identical so we can do a vector shift.
15892 SDValue ValOp = N->getOperand(0);
15893 switch (N->getOpcode()) {
15895 llvm_unreachable("Unknown shift opcode!");
15897 switch (VT.getSimpleVT().SimpleTy) {
15898 default: return SDValue();
15905 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
15908 switch (VT.getSimpleVT().SimpleTy) {
15909 default: return SDValue();
15914 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
15917 switch (VT.getSimpleVT().SimpleTy) {
15918 default: return SDValue();
15925 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
15930 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
15931 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
15932 // and friends. Likewise for OR -> CMPNEQSS.
15933 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
15934 TargetLowering::DAGCombinerInfo &DCI,
15935 const X86Subtarget *Subtarget) {
15938 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
15939 // we're requiring SSE2 for both.
15940 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
15941 SDValue N0 = N->getOperand(0);
15942 SDValue N1 = N->getOperand(1);
15943 SDValue CMP0 = N0->getOperand(1);
15944 SDValue CMP1 = N1->getOperand(1);
15945 DebugLoc DL = N->getDebugLoc();
15947 // The SETCCs should both refer to the same CMP.
15948 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
15951 SDValue CMP00 = CMP0->getOperand(0);
15952 SDValue CMP01 = CMP0->getOperand(1);
15953 EVT VT = CMP00.getValueType();
15955 if (VT == MVT::f32 || VT == MVT::f64) {
15956 bool ExpectingFlags = false;
15957 // Check for any users that want flags:
15958 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
15959 !ExpectingFlags && UI != UE; ++UI)
15960 switch (UI->getOpcode()) {
15965 ExpectingFlags = true;
15967 case ISD::CopyToReg:
15968 case ISD::SIGN_EXTEND:
15969 case ISD::ZERO_EXTEND:
15970 case ISD::ANY_EXTEND:
15974 if (!ExpectingFlags) {
15975 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
15976 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
15978 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
15979 X86::CondCode tmp = cc0;
15984 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
15985 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
15986 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
15987 X86ISD::NodeType NTOperator = is64BitFP ?
15988 X86ISD::FSETCCsd : X86ISD::FSETCCss;
15989 // FIXME: need symbolic constants for these magic numbers.
15990 // See X86ATTInstPrinter.cpp:printSSECC().
15991 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
15992 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
15993 DAG.getConstant(x86cc, MVT::i8));
15994 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
15996 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
15997 DAG.getConstant(1, MVT::i32));
15998 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
15999 return OneBitOfTruth;
16007 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
16008 /// so it can be folded inside ANDNP.
16009 static bool CanFoldXORWithAllOnes(const SDNode *N) {
16010 EVT VT = N->getValueType(0);
16012 // Match direct AllOnes for 128 and 256-bit vectors
16013 if (ISD::isBuildVectorAllOnes(N))
16016 // Look through a bit convert.
16017 if (N->getOpcode() == ISD::BITCAST)
16018 N = N->getOperand(0).getNode();
16020 // Sometimes the operand may come from a insert_subvector building a 256-bit
16022 if (VT.is256BitVector() &&
16023 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
16024 SDValue V1 = N->getOperand(0);
16025 SDValue V2 = N->getOperand(1);
16027 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
16028 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
16029 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
16030 ISD::isBuildVectorAllOnes(V2.getNode()))
16037 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
16038 // register. In most cases we actually compare or select YMM-sized registers
16039 // and mixing the two types creates horrible code. This method optimizes
16040 // some of the transition sequences.
16041 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
16042 TargetLowering::DAGCombinerInfo &DCI,
16043 const X86Subtarget *Subtarget) {
16044 EVT VT = N->getValueType(0);
16045 if (!VT.is256BitVector())
16048 assert((N->getOpcode() == ISD::ANY_EXTEND ||
16049 N->getOpcode() == ISD::ZERO_EXTEND ||
16050 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
16052 SDValue Narrow = N->getOperand(0);
16053 EVT NarrowVT = Narrow->getValueType(0);
16054 if (!NarrowVT.is128BitVector())
16057 if (Narrow->getOpcode() != ISD::XOR &&
16058 Narrow->getOpcode() != ISD::AND &&
16059 Narrow->getOpcode() != ISD::OR)
16062 SDValue N0 = Narrow->getOperand(0);
16063 SDValue N1 = Narrow->getOperand(1);
16064 DebugLoc DL = Narrow->getDebugLoc();
16066 // The Left side has to be a trunc.
16067 if (N0.getOpcode() != ISD::TRUNCATE)
16070 // The type of the truncated inputs.
16071 EVT WideVT = N0->getOperand(0)->getValueType(0);
16075 // The right side has to be a 'trunc' or a constant vector.
16076 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
16077 bool RHSConst = (isSplatVector(N1.getNode()) &&
16078 isa<ConstantSDNode>(N1->getOperand(0)));
16079 if (!RHSTrunc && !RHSConst)
16082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16084 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
16087 // Set N0 and N1 to hold the inputs to the new wide operation.
16088 N0 = N0->getOperand(0);
16090 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
16091 N1->getOperand(0));
16092 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
16093 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
16094 } else if (RHSTrunc) {
16095 N1 = N1->getOperand(0);
16098 // Generate the wide operation.
16099 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
16100 unsigned Opcode = N->getOpcode();
16102 case ISD::ANY_EXTEND:
16104 case ISD::ZERO_EXTEND: {
16105 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
16106 APInt Mask = APInt::getAllOnesValue(InBits);
16107 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
16108 return DAG.getNode(ISD::AND, DL, VT,
16109 Op, DAG.getConstant(Mask, VT));
16111 case ISD::SIGN_EXTEND:
16112 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
16113 Op, DAG.getValueType(NarrowVT));
16115 llvm_unreachable("Unexpected opcode");
16119 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
16120 TargetLowering::DAGCombinerInfo &DCI,
16121 const X86Subtarget *Subtarget) {
16122 EVT VT = N->getValueType(0);
16123 if (DCI.isBeforeLegalizeOps())
16126 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16130 // Create BLSI, and BLSR instructions
16131 // BLSI is X & (-X)
16132 // BLSR is X & (X-1)
16133 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
16134 SDValue N0 = N->getOperand(0);
16135 SDValue N1 = N->getOperand(1);
16136 DebugLoc DL = N->getDebugLoc();
16138 // Check LHS for neg
16139 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16140 isZero(N0.getOperand(0)))
16141 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
16143 // Check RHS for neg
16144 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16145 isZero(N1.getOperand(0)))
16146 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
16148 // Check LHS for X-1
16149 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16150 isAllOnes(N0.getOperand(1)))
16151 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
16153 // Check RHS for X-1
16154 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16155 isAllOnes(N1.getOperand(1)))
16156 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
16161 // Want to form ANDNP nodes:
16162 // 1) In the hopes of then easily combining them with OR and AND nodes
16163 // to form PBLEND/PSIGN.
16164 // 2) To match ANDN packed intrinsics
16165 if (VT != MVT::v2i64 && VT != MVT::v4i64)
16168 SDValue N0 = N->getOperand(0);
16169 SDValue N1 = N->getOperand(1);
16170 DebugLoc DL = N->getDebugLoc();
16172 // Check LHS for vnot
16173 if (N0.getOpcode() == ISD::XOR &&
16174 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
16175 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
16176 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
16178 // Check RHS for vnot
16179 if (N1.getOpcode() == ISD::XOR &&
16180 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
16181 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
16182 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
16187 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
16188 TargetLowering::DAGCombinerInfo &DCI,
16189 const X86Subtarget *Subtarget) {
16190 EVT VT = N->getValueType(0);
16191 if (DCI.isBeforeLegalizeOps())
16194 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16198 SDValue N0 = N->getOperand(0);
16199 SDValue N1 = N->getOperand(1);
16201 // look for psign/blend
16202 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
16203 if (!Subtarget->hasSSSE3() ||
16204 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
16207 // Canonicalize pandn to RHS
16208 if (N0.getOpcode() == X86ISD::ANDNP)
16210 // or (and (m, y), (pandn m, x))
16211 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16212 SDValue Mask = N1.getOperand(0);
16213 SDValue X = N1.getOperand(1);
16215 if (N0.getOperand(0) == Mask)
16216 Y = N0.getOperand(1);
16217 if (N0.getOperand(1) == Mask)
16218 Y = N0.getOperand(0);
16220 // Check to see if the mask appeared in both the AND and ANDNP and
16224 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
16225 // Look through mask bitcast.
16226 if (Mask.getOpcode() == ISD::BITCAST)
16227 Mask = Mask.getOperand(0);
16228 if (X.getOpcode() == ISD::BITCAST)
16229 X = X.getOperand(0);
16230 if (Y.getOpcode() == ISD::BITCAST)
16231 Y = Y.getOperand(0);
16233 EVT MaskVT = Mask.getValueType();
16235 // Validate that the Mask operand is a vector sra node.
16236 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
16237 // there is no psrai.b
16238 if (Mask.getOpcode() != X86ISD::VSRAI)
16241 // Check that the SRA is all signbits.
16242 SDValue SraC = Mask.getOperand(1);
16243 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
16244 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
16245 if ((SraAmt + 1) != EltBits)
16248 DebugLoc DL = N->getDebugLoc();
16250 // We are going to replace the AND, OR, NAND with either BLEND
16251 // or PSIGN, which only look at the MSB. The VSRAI instruction
16252 // does not affect the highest bit, so we can get rid of it.
16253 Mask = Mask.getOperand(0);
16255 // Now we know we at least have a plendvb with the mask val. See if
16256 // we can form a psignb/w/d.
16257 // psign = x.type == y.type == mask.type && y = sub(0, x);
16258 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16259 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
16260 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
16261 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
16262 "Unsupported VT for PSIGN");
16263 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask);
16264 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16266 // PBLENDVB only available on SSE 4.1
16267 if (!Subtarget->hasSSE41())
16270 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
16272 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
16273 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
16274 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
16275 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
16276 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16280 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
16283 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
16284 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16286 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16288 if (!N0.hasOneUse() || !N1.hasOneUse())
16291 SDValue ShAmt0 = N0.getOperand(1);
16292 if (ShAmt0.getValueType() != MVT::i8)
16294 SDValue ShAmt1 = N1.getOperand(1);
16295 if (ShAmt1.getValueType() != MVT::i8)
16297 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
16298 ShAmt0 = ShAmt0.getOperand(0);
16299 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
16300 ShAmt1 = ShAmt1.getOperand(0);
16302 DebugLoc DL = N->getDebugLoc();
16303 unsigned Opc = X86ISD::SHLD;
16304 SDValue Op0 = N0.getOperand(0);
16305 SDValue Op1 = N1.getOperand(0);
16306 if (ShAmt0.getOpcode() == ISD::SUB) {
16307 Opc = X86ISD::SHRD;
16308 std::swap(Op0, Op1);
16309 std::swap(ShAmt0, ShAmt1);
16312 unsigned Bits = VT.getSizeInBits();
16313 if (ShAmt1.getOpcode() == ISD::SUB) {
16314 SDValue Sum = ShAmt1.getOperand(0);
16315 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
16316 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
16317 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
16318 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
16319 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
16320 return DAG.getNode(Opc, DL, VT,
16322 DAG.getNode(ISD::TRUNCATE, DL,
16325 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
16326 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
16328 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
16329 return DAG.getNode(Opc, DL, VT,
16330 N0.getOperand(0), N1.getOperand(0),
16331 DAG.getNode(ISD::TRUNCATE, DL,
16338 // Generate NEG and CMOV for integer abs.
16339 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
16340 EVT VT = N->getValueType(0);
16342 // Since X86 does not have CMOV for 8-bit integer, we don't convert
16343 // 8-bit integer abs to NEG and CMOV.
16344 if (VT.isInteger() && VT.getSizeInBits() == 8)
16347 SDValue N0 = N->getOperand(0);
16348 SDValue N1 = N->getOperand(1);
16349 DebugLoc DL = N->getDebugLoc();
16351 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
16352 // and change it to SUB and CMOV.
16353 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
16354 N0.getOpcode() == ISD::ADD &&
16355 N0.getOperand(1) == N1 &&
16356 N1.getOpcode() == ISD::SRA &&
16357 N1.getOperand(0) == N0.getOperand(0))
16358 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
16359 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
16360 // Generate SUB & CMOV.
16361 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
16362 DAG.getConstant(0, VT), N0.getOperand(0));
16364 SDValue Ops[] = { N0.getOperand(0), Neg,
16365 DAG.getConstant(X86::COND_GE, MVT::i8),
16366 SDValue(Neg.getNode(), 1) };
16367 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
16368 Ops, array_lengthof(Ops));
16373 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
16374 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
16375 TargetLowering::DAGCombinerInfo &DCI,
16376 const X86Subtarget *Subtarget) {
16377 EVT VT = N->getValueType(0);
16378 if (DCI.isBeforeLegalizeOps())
16381 if (Subtarget->hasCMov()) {
16382 SDValue RV = performIntegerAbsCombine(N, DAG);
16387 // Try forming BMI if it is available.
16388 if (!Subtarget->hasBMI())
16391 if (VT != MVT::i32 && VT != MVT::i64)
16394 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
16396 // Create BLSMSK instructions by finding X ^ (X-1)
16397 SDValue N0 = N->getOperand(0);
16398 SDValue N1 = N->getOperand(1);
16399 DebugLoc DL = N->getDebugLoc();
16401 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16402 isAllOnes(N0.getOperand(1)))
16403 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
16405 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16406 isAllOnes(N1.getOperand(1)))
16407 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
16412 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
16413 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
16414 TargetLowering::DAGCombinerInfo &DCI,
16415 const X86Subtarget *Subtarget) {
16416 LoadSDNode *Ld = cast<LoadSDNode>(N);
16417 EVT RegVT = Ld->getValueType(0);
16418 EVT MemVT = Ld->getMemoryVT();
16419 DebugLoc dl = Ld->getDebugLoc();
16420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16421 unsigned RegSz = RegVT.getSizeInBits();
16423 ISD::LoadExtType Ext = Ld->getExtensionType();
16424 unsigned Alignment = Ld->getAlignment();
16425 bool IsAligned = Alignment == 0 || Alignment == MemVT.getSizeInBits()/8;
16427 // On Sandybridge unaligned 256bit loads are inefficient.
16428 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
16429 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
16430 unsigned NumElems = RegVT.getVectorNumElements();
16434 SDValue Ptr = Ld->getBasePtr();
16435 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
16437 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16439 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
16440 Ld->getPointerInfo(), Ld->isVolatile(),
16441 Ld->isNonTemporal(), Ld->isInvariant(),
16443 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16444 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
16445 Ld->getPointerInfo(), Ld->isVolatile(),
16446 Ld->isNonTemporal(), Ld->isInvariant(),
16447 std::max(Alignment/2U, 1U));
16448 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16450 Load2.getValue(1));
16452 SDValue NewVec = DAG.getUNDEF(RegVT);
16453 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
16454 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
16455 return DCI.CombineTo(N, NewVec, TF, true);
16458 // If this is a vector EXT Load then attempt to optimize it using a
16459 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
16460 // expansion is still better than scalar code.
16461 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
16462 // emit a shuffle and a arithmetic shift.
16463 // TODO: It is possible to support ZExt by zeroing the undef values
16464 // during the shuffle phase or after the shuffle.
16465 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
16466 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
16467 assert(MemVT != RegVT && "Cannot extend to the same type");
16468 assert(MemVT.isVector() && "Must load a vector from memory");
16470 unsigned NumElems = RegVT.getVectorNumElements();
16471 unsigned MemSz = MemVT.getSizeInBits();
16472 assert(RegSz > MemSz && "Register size must be greater than the mem size");
16474 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
16477 // All sizes must be a power of two.
16478 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
16481 // Attempt to load the original value using scalar loads.
16482 // Find the largest scalar type that divides the total loaded size.
16483 MVT SclrLoadTy = MVT::i8;
16484 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16485 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16486 MVT Tp = (MVT::SimpleValueType)tp;
16487 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16492 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16493 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16495 SclrLoadTy = MVT::f64;
16497 // Calculate the number of scalar loads that we need to perform
16498 // in order to load our vector from memory.
16499 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16500 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
16503 unsigned loadRegZize = RegSz;
16504 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16507 // Represent our vector as a sequence of elements which are the
16508 // largest scalar that we can load.
16509 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
16510 loadRegZize/SclrLoadTy.getSizeInBits());
16512 // Represent the data using the same element type that is stored in
16513 // memory. In practice, we ''widen'' MemVT.
16515 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16516 loadRegZize/MemVT.getScalarType().getSizeInBits());
16518 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16519 "Invalid vector type");
16521 // We can't shuffle using an illegal type.
16522 if (!TLI.isTypeLegal(WideVecVT))
16525 SmallVector<SDValue, 8> Chains;
16526 SDValue Ptr = Ld->getBasePtr();
16527 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
16528 TLI.getPointerTy());
16529 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16531 for (unsigned i = 0; i < NumLoads; ++i) {
16532 // Perform a single load.
16533 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
16534 Ptr, Ld->getPointerInfo(),
16535 Ld->isVolatile(), Ld->isNonTemporal(),
16536 Ld->isInvariant(), Ld->getAlignment());
16537 Chains.push_back(ScalarLoad.getValue(1));
16538 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16539 // another round of DAGCombining.
16541 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16543 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16544 ScalarLoad, DAG.getIntPtrConstant(i));
16546 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16549 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16552 // Bitcast the loaded value to a vector of the original element type, in
16553 // the size of the target vector type.
16554 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16555 unsigned SizeRatio = RegSz/MemSz;
16557 if (Ext == ISD::SEXTLOAD) {
16558 // If we have SSE4.1 we can directly emit a VSEXT node.
16559 if (Subtarget->hasSSE41()) {
16560 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16561 return DCI.CombineTo(N, Sext, TF, true);
16564 // Otherwise we'll shuffle the small elements in the high bits of the
16565 // larger type and perform an arithmetic shift. If the shift is not legal
16566 // it's better to scalarize.
16567 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
16570 // Redistribute the loaded elements into the different locations.
16571 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16572 for (unsigned i = 0; i != NumElems; ++i)
16573 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
16575 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16576 DAG.getUNDEF(WideVecVT),
16579 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16581 // Build the arithmetic shift.
16582 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16583 MemVT.getVectorElementType().getSizeInBits();
16584 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
16585 DAG.getConstant(Amt, RegVT));
16587 return DCI.CombineTo(N, Shuff, TF, true);
16590 // Redistribute the loaded elements into the different locations.
16591 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16592 for (unsigned i = 0; i != NumElems; ++i)
16593 ShuffleVec[i*SizeRatio] = i;
16595 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16596 DAG.getUNDEF(WideVecVT),
16599 // Bitcast to the requested type.
16600 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16601 // Replace the original load with the new sequence
16602 // and return the new chain.
16603 return DCI.CombineTo(N, Shuff, TF, true);
16609 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
16610 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
16611 const X86Subtarget *Subtarget) {
16612 StoreSDNode *St = cast<StoreSDNode>(N);
16613 EVT VT = St->getValue().getValueType();
16614 EVT StVT = St->getMemoryVT();
16615 DebugLoc dl = St->getDebugLoc();
16616 SDValue StoredVal = St->getOperand(1);
16617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16618 unsigned Alignment = St->getAlignment();
16619 bool IsAligned = Alignment == 0 || Alignment == VT.getSizeInBits()/8;
16621 // If we are saving a concatenation of two XMM registers, perform two stores.
16622 // On Sandy Bridge, 256-bit memory operations are executed by two
16623 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
16624 // memory operation.
16625 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
16626 StVT == VT && !IsAligned) {
16627 unsigned NumElems = VT.getVectorNumElements();
16631 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
16632 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
16634 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
16635 SDValue Ptr0 = St->getBasePtr();
16636 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
16638 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
16639 St->getPointerInfo(), St->isVolatile(),
16640 St->isNonTemporal(), Alignment);
16641 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
16642 St->getPointerInfo(), St->isVolatile(),
16643 St->isNonTemporal(),
16644 std::max(Alignment/2U, 1U));
16645 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16648 // Optimize trunc store (of multiple scalars) to shuffle and store.
16649 // First, pack all of the elements in one place. Next, store to memory
16650 // in fewer chunks.
16651 if (St->isTruncatingStore() && VT.isVector()) {
16652 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16653 unsigned NumElems = VT.getVectorNumElements();
16654 assert(StVT != VT && "Cannot truncate to the same type");
16655 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
16656 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
16658 // From, To sizes and ElemCount must be pow of two
16659 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
16660 // We are going to use the original vector elt for storing.
16661 // Accumulated smaller vector elements must be a multiple of the store size.
16662 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
16664 unsigned SizeRatio = FromSz / ToSz;
16666 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
16668 // Create a type on which we perform the shuffle
16669 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
16670 StVT.getScalarType(), NumElems*SizeRatio);
16672 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
16674 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
16675 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16676 for (unsigned i = 0; i != NumElems; ++i)
16677 ShuffleVec[i] = i * SizeRatio;
16679 // Can't shuffle using an illegal type.
16680 if (!TLI.isTypeLegal(WideVecVT))
16683 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
16684 DAG.getUNDEF(WideVecVT),
16686 // At this point all of the data is stored at the bottom of the
16687 // register. We now need to save it to mem.
16689 // Find the largest store unit
16690 MVT StoreType = MVT::i8;
16691 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16692 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16693 MVT Tp = (MVT::SimpleValueType)tp;
16694 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
16698 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16699 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
16700 (64 <= NumElems * ToSz))
16701 StoreType = MVT::f64;
16703 // Bitcast the original vector into a vector of store-size units
16704 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
16705 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
16706 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
16707 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
16708 SmallVector<SDValue, 8> Chains;
16709 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
16710 TLI.getPointerTy());
16711 SDValue Ptr = St->getBasePtr();
16713 // Perform one or more big stores into memory.
16714 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
16715 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16716 StoreType, ShuffWide,
16717 DAG.getIntPtrConstant(i));
16718 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
16719 St->getPointerInfo(), St->isVolatile(),
16720 St->isNonTemporal(), St->getAlignment());
16721 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16722 Chains.push_back(Ch);
16725 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16729 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
16730 // the FP state in cases where an emms may be missing.
16731 // A preferable solution to the general problem is to figure out the right
16732 // places to insert EMMS. This qualifies as a quick hack.
16734 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
16735 if (VT.getSizeInBits() != 64)
16738 const Function *F = DAG.getMachineFunction().getFunction();
16739 bool NoImplicitFloatOps = F->getAttributes().
16740 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
16741 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
16742 && Subtarget->hasSSE2();
16743 if ((VT.isVector() ||
16744 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
16745 isa<LoadSDNode>(St->getValue()) &&
16746 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
16747 St->getChain().hasOneUse() && !St->isVolatile()) {
16748 SDNode* LdVal = St->getValue().getNode();
16749 LoadSDNode *Ld = 0;
16750 int TokenFactorIndex = -1;
16751 SmallVector<SDValue, 8> Ops;
16752 SDNode* ChainVal = St->getChain().getNode();
16753 // Must be a store of a load. We currently handle two cases: the load
16754 // is a direct child, and it's under an intervening TokenFactor. It is
16755 // possible to dig deeper under nested TokenFactors.
16756 if (ChainVal == LdVal)
16757 Ld = cast<LoadSDNode>(St->getChain());
16758 else if (St->getValue().hasOneUse() &&
16759 ChainVal->getOpcode() == ISD::TokenFactor) {
16760 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
16761 if (ChainVal->getOperand(i).getNode() == LdVal) {
16762 TokenFactorIndex = i;
16763 Ld = cast<LoadSDNode>(St->getValue());
16765 Ops.push_back(ChainVal->getOperand(i));
16769 if (!Ld || !ISD::isNormalLoad(Ld))
16772 // If this is not the MMX case, i.e. we are just turning i64 load/store
16773 // into f64 load/store, avoid the transformation if there are multiple
16774 // uses of the loaded value.
16775 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
16778 DebugLoc LdDL = Ld->getDebugLoc();
16779 DebugLoc StDL = N->getDebugLoc();
16780 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
16781 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
16783 if (Subtarget->is64Bit() || F64IsLegal) {
16784 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
16785 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
16786 Ld->getPointerInfo(), Ld->isVolatile(),
16787 Ld->isNonTemporal(), Ld->isInvariant(),
16788 Ld->getAlignment());
16789 SDValue NewChain = NewLd.getValue(1);
16790 if (TokenFactorIndex != -1) {
16791 Ops.push_back(NewChain);
16792 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16795 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
16796 St->getPointerInfo(),
16797 St->isVolatile(), St->isNonTemporal(),
16798 St->getAlignment());
16801 // Otherwise, lower to two pairs of 32-bit loads / stores.
16802 SDValue LoAddr = Ld->getBasePtr();
16803 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
16804 DAG.getConstant(4, MVT::i32));
16806 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
16807 Ld->getPointerInfo(),
16808 Ld->isVolatile(), Ld->isNonTemporal(),
16809 Ld->isInvariant(), Ld->getAlignment());
16810 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
16811 Ld->getPointerInfo().getWithOffset(4),
16812 Ld->isVolatile(), Ld->isNonTemporal(),
16814 MinAlign(Ld->getAlignment(), 4));
16816 SDValue NewChain = LoLd.getValue(1);
16817 if (TokenFactorIndex != -1) {
16818 Ops.push_back(LoLd);
16819 Ops.push_back(HiLd);
16820 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16824 LoAddr = St->getBasePtr();
16825 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
16826 DAG.getConstant(4, MVT::i32));
16828 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
16829 St->getPointerInfo(),
16830 St->isVolatile(), St->isNonTemporal(),
16831 St->getAlignment());
16832 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
16833 St->getPointerInfo().getWithOffset(4),
16835 St->isNonTemporal(),
16836 MinAlign(St->getAlignment(), 4));
16837 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
16842 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
16843 /// and return the operands for the horizontal operation in LHS and RHS. A
16844 /// horizontal operation performs the binary operation on successive elements
16845 /// of its first operand, then on successive elements of its second operand,
16846 /// returning the resulting values in a vector. For example, if
16847 /// A = < float a0, float a1, float a2, float a3 >
16849 /// B = < float b0, float b1, float b2, float b3 >
16850 /// then the result of doing a horizontal operation on A and B is
16851 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
16852 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
16853 /// A horizontal-op B, for some already available A and B, and if so then LHS is
16854 /// set to A, RHS to B, and the routine returns 'true'.
16855 /// Note that the binary operation should have the property that if one of the
16856 /// operands is UNDEF then the result is UNDEF.
16857 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
16858 // Look for the following pattern: if
16859 // A = < float a0, float a1, float a2, float a3 >
16860 // B = < float b0, float b1, float b2, float b3 >
16862 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
16863 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
16864 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
16865 // which is A horizontal-op B.
16867 // At least one of the operands should be a vector shuffle.
16868 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
16869 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
16872 EVT VT = LHS.getValueType();
16874 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16875 "Unsupported vector type for horizontal add/sub");
16877 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
16878 // operate independently on 128-bit lanes.
16879 unsigned NumElts = VT.getVectorNumElements();
16880 unsigned NumLanes = VT.getSizeInBits()/128;
16881 unsigned NumLaneElts = NumElts / NumLanes;
16882 assert((NumLaneElts % 2 == 0) &&
16883 "Vector type should have an even number of elements in each lane");
16884 unsigned HalfLaneElts = NumLaneElts/2;
16886 // View LHS in the form
16887 // LHS = VECTOR_SHUFFLE A, B, LMask
16888 // If LHS is not a shuffle then pretend it is the shuffle
16889 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
16890 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
16893 SmallVector<int, 16> LMask(NumElts);
16894 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16895 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
16896 A = LHS.getOperand(0);
16897 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
16898 B = LHS.getOperand(1);
16899 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
16900 std::copy(Mask.begin(), Mask.end(), LMask.begin());
16902 if (LHS.getOpcode() != ISD::UNDEF)
16904 for (unsigned i = 0; i != NumElts; ++i)
16908 // Likewise, view RHS in the form
16909 // RHS = VECTOR_SHUFFLE C, D, RMask
16911 SmallVector<int, 16> RMask(NumElts);
16912 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16913 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
16914 C = RHS.getOperand(0);
16915 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
16916 D = RHS.getOperand(1);
16917 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
16918 std::copy(Mask.begin(), Mask.end(), RMask.begin());
16920 if (RHS.getOpcode() != ISD::UNDEF)
16922 for (unsigned i = 0; i != NumElts; ++i)
16926 // Check that the shuffles are both shuffling the same vectors.
16927 if (!(A == C && B == D) && !(A == D && B == C))
16930 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
16931 if (!A.getNode() && !B.getNode())
16934 // If A and B occur in reverse order in RHS, then "swap" them (which means
16935 // rewriting the mask).
16937 CommuteVectorShuffleMask(RMask, NumElts);
16939 // At this point LHS and RHS are equivalent to
16940 // LHS = VECTOR_SHUFFLE A, B, LMask
16941 // RHS = VECTOR_SHUFFLE A, B, RMask
16942 // Check that the masks correspond to performing a horizontal operation.
16943 for (unsigned i = 0; i != NumElts; ++i) {
16944 int LIdx = LMask[i], RIdx = RMask[i];
16946 // Ignore any UNDEF components.
16947 if (LIdx < 0 || RIdx < 0 ||
16948 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
16949 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
16952 // Check that successive elements are being operated on. If not, this is
16953 // not a horizontal operation.
16954 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
16955 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
16956 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
16957 if (!(LIdx == Index && RIdx == Index + 1) &&
16958 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
16962 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
16963 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
16967 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
16968 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
16969 const X86Subtarget *Subtarget) {
16970 EVT VT = N->getValueType(0);
16971 SDValue LHS = N->getOperand(0);
16972 SDValue RHS = N->getOperand(1);
16974 // Try to synthesize horizontal adds from adds of shuffles.
16975 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16976 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16977 isHorizontalBinOp(LHS, RHS, true))
16978 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
16982 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
16983 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
16984 const X86Subtarget *Subtarget) {
16985 EVT VT = N->getValueType(0);
16986 SDValue LHS = N->getOperand(0);
16987 SDValue RHS = N->getOperand(1);
16989 // Try to synthesize horizontal subs from subs of shuffles.
16990 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16991 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16992 isHorizontalBinOp(LHS, RHS, false))
16993 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
16997 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
16998 /// X86ISD::FXOR nodes.
16999 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
17000 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
17001 // F[X]OR(0.0, x) -> x
17002 // F[X]OR(x, 0.0) -> x
17003 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17004 if (C->getValueAPF().isPosZero())
17005 return N->getOperand(1);
17006 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17007 if (C->getValueAPF().isPosZero())
17008 return N->getOperand(0);
17012 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
17013 /// X86ISD::FMAX nodes.
17014 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
17015 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
17017 // Only perform optimizations if UnsafeMath is used.
17018 if (!DAG.getTarget().Options.UnsafeFPMath)
17021 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
17022 // into FMINC and FMAXC, which are Commutative operations.
17023 unsigned NewOp = 0;
17024 switch (N->getOpcode()) {
17025 default: llvm_unreachable("unknown opcode");
17026 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
17027 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
17030 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
17031 N->getOperand(0), N->getOperand(1));
17034 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
17035 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
17036 // FAND(0.0, x) -> 0.0
17037 // FAND(x, 0.0) -> 0.0
17038 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17039 if (C->getValueAPF().isPosZero())
17040 return N->getOperand(0);
17041 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17042 if (C->getValueAPF().isPosZero())
17043 return N->getOperand(1);
17047 static SDValue PerformBTCombine(SDNode *N,
17049 TargetLowering::DAGCombinerInfo &DCI) {
17050 // BT ignores high bits in the bit index operand.
17051 SDValue Op1 = N->getOperand(1);
17052 if (Op1.hasOneUse()) {
17053 unsigned BitWidth = Op1.getValueSizeInBits();
17054 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
17055 APInt KnownZero, KnownOne;
17056 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
17057 !DCI.isBeforeLegalizeOps());
17058 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17059 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
17060 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
17061 DCI.CommitTargetLoweringOpt(TLO);
17066 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
17067 SDValue Op = N->getOperand(0);
17068 if (Op.getOpcode() == ISD::BITCAST)
17069 Op = Op.getOperand(0);
17070 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
17071 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
17072 VT.getVectorElementType().getSizeInBits() ==
17073 OpVT.getVectorElementType().getSizeInBits()) {
17074 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
17079 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
17080 TargetLowering::DAGCombinerInfo &DCI,
17081 const X86Subtarget *Subtarget) {
17082 if (!DCI.isBeforeLegalizeOps())
17085 if (!Subtarget->hasFp256())
17088 EVT VT = N->getValueType(0);
17089 if (VT.isVector() && VT.getSizeInBits() == 256) {
17090 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17098 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
17099 const X86Subtarget* Subtarget) {
17100 DebugLoc dl = N->getDebugLoc();
17101 EVT VT = N->getValueType(0);
17103 // Let legalize expand this if it isn't a legal type yet.
17104 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17107 EVT ScalarVT = VT.getScalarType();
17108 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
17109 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
17112 SDValue A = N->getOperand(0);
17113 SDValue B = N->getOperand(1);
17114 SDValue C = N->getOperand(2);
17116 bool NegA = (A.getOpcode() == ISD::FNEG);
17117 bool NegB = (B.getOpcode() == ISD::FNEG);
17118 bool NegC = (C.getOpcode() == ISD::FNEG);
17120 // Negative multiplication when NegA xor NegB
17121 bool NegMul = (NegA != NegB);
17123 A = A.getOperand(0);
17125 B = B.getOperand(0);
17127 C = C.getOperand(0);
17131 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
17133 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
17135 return DAG.getNode(Opcode, dl, VT, A, B, C);
17138 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
17139 TargetLowering::DAGCombinerInfo &DCI,
17140 const X86Subtarget *Subtarget) {
17141 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
17142 // (and (i32 x86isd::setcc_carry), 1)
17143 // This eliminates the zext. This transformation is necessary because
17144 // ISD::SETCC is always legalized to i8.
17145 DebugLoc dl = N->getDebugLoc();
17146 SDValue N0 = N->getOperand(0);
17147 EVT VT = N->getValueType(0);
17149 if (N0.getOpcode() == ISD::AND &&
17151 N0.getOperand(0).hasOneUse()) {
17152 SDValue N00 = N0.getOperand(0);
17153 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
17154 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17155 if (!C || C->getZExtValue() != 1)
17157 return DAG.getNode(ISD::AND, dl, VT,
17158 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
17159 N00.getOperand(0), N00.getOperand(1)),
17160 DAG.getConstant(1, VT));
17164 if (VT.is256BitVector()) {
17165 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17173 // Optimize x == -y --> x+y == 0
17174 // x != -y --> x+y != 0
17175 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
17176 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
17177 SDValue LHS = N->getOperand(0);
17178 SDValue RHS = N->getOperand(1);
17180 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17181 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
17182 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
17183 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17184 LHS.getValueType(), RHS, LHS.getOperand(1));
17185 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17186 addV, DAG.getConstant(0, addV.getValueType()), CC);
17188 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17189 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
17190 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
17191 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17192 RHS.getValueType(), LHS, RHS.getOperand(1));
17193 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17194 addV, DAG.getConstant(0, addV.getValueType()), CC);
17199 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
17200 // as "sbb reg,reg", since it can be extended without zext and produces
17201 // an all-ones bit which is more useful than 0/1 in some cases.
17202 static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
17203 return DAG.getNode(ISD::AND, DL, MVT::i8,
17204 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
17205 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
17206 DAG.getConstant(1, MVT::i8));
17209 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
17210 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
17211 TargetLowering::DAGCombinerInfo &DCI,
17212 const X86Subtarget *Subtarget) {
17213 DebugLoc DL = N->getDebugLoc();
17214 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
17215 SDValue EFLAGS = N->getOperand(1);
17217 if (CC == X86::COND_A) {
17218 // Try to convert COND_A into COND_B in an attempt to facilitate
17219 // materializing "setb reg".
17221 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
17222 // cannot take an immediate as its first operand.
17224 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
17225 EFLAGS.getValueType().isInteger() &&
17226 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
17227 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(),
17228 EFLAGS.getNode()->getVTList(),
17229 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
17230 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
17231 return MaterializeSETB(DL, NewEFLAGS, DAG);
17235 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
17236 // a zext and produces an all-ones bit which is more useful than 0/1 in some
17238 if (CC == X86::COND_B)
17239 return MaterializeSETB(DL, EFLAGS, DAG);
17243 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17244 if (Flags.getNode()) {
17245 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17246 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
17252 // Optimize branch condition evaluation.
17254 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
17255 TargetLowering::DAGCombinerInfo &DCI,
17256 const X86Subtarget *Subtarget) {
17257 DebugLoc DL = N->getDebugLoc();
17258 SDValue Chain = N->getOperand(0);
17259 SDValue Dest = N->getOperand(1);
17260 SDValue EFLAGS = N->getOperand(3);
17261 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
17265 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17266 if (Flags.getNode()) {
17267 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17268 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
17275 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
17276 const X86TargetLowering *XTLI) {
17277 SDValue Op0 = N->getOperand(0);
17278 EVT InVT = Op0->getValueType(0);
17280 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
17281 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
17282 DebugLoc dl = N->getDebugLoc();
17283 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
17284 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
17285 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
17288 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
17289 // a 32-bit target where SSE doesn't support i64->FP operations.
17290 if (Op0.getOpcode() == ISD::LOAD) {
17291 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
17292 EVT VT = Ld->getValueType(0);
17293 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
17294 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
17295 !XTLI->getSubtarget()->is64Bit() &&
17296 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17297 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
17298 Ld->getChain(), Op0, DAG);
17299 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
17306 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
17307 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
17308 X86TargetLowering::DAGCombinerInfo &DCI) {
17309 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
17310 // the result is either zero or one (depending on the input carry bit).
17311 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
17312 if (X86::isZeroNode(N->getOperand(0)) &&
17313 X86::isZeroNode(N->getOperand(1)) &&
17314 // We don't have a good way to replace an EFLAGS use, so only do this when
17316 SDValue(N, 1).use_empty()) {
17317 DebugLoc DL = N->getDebugLoc();
17318 EVT VT = N->getValueType(0);
17319 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
17320 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
17321 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
17322 DAG.getConstant(X86::COND_B,MVT::i8),
17324 DAG.getConstant(1, VT));
17325 return DCI.CombineTo(N, Res1, CarryOut);
17331 // fold (add Y, (sete X, 0)) -> adc 0, Y
17332 // (add Y, (setne X, 0)) -> sbb -1, Y
17333 // (sub (sete X, 0), Y) -> sbb 0, Y
17334 // (sub (setne X, 0), Y) -> adc -1, Y
17335 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
17336 DebugLoc DL = N->getDebugLoc();
17338 // Look through ZExts.
17339 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
17340 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
17343 SDValue SetCC = Ext.getOperand(0);
17344 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
17347 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
17348 if (CC != X86::COND_E && CC != X86::COND_NE)
17351 SDValue Cmp = SetCC.getOperand(1);
17352 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
17353 !X86::isZeroNode(Cmp.getOperand(1)) ||
17354 !Cmp.getOperand(0).getValueType().isInteger())
17357 SDValue CmpOp0 = Cmp.getOperand(0);
17358 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
17359 DAG.getConstant(1, CmpOp0.getValueType()));
17361 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
17362 if (CC == X86::COND_NE)
17363 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
17364 DL, OtherVal.getValueType(), OtherVal,
17365 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
17366 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
17367 DL, OtherVal.getValueType(), OtherVal,
17368 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
17371 /// PerformADDCombine - Do target-specific dag combines on integer adds.
17372 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
17373 const X86Subtarget *Subtarget) {
17374 EVT VT = N->getValueType(0);
17375 SDValue Op0 = N->getOperand(0);
17376 SDValue Op1 = N->getOperand(1);
17378 // Try to synthesize horizontal adds from adds of shuffles.
17379 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17380 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17381 isHorizontalBinOp(Op0, Op1, true))
17382 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
17384 return OptimizeConditionalInDecrement(N, DAG);
17387 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
17388 const X86Subtarget *Subtarget) {
17389 SDValue Op0 = N->getOperand(0);
17390 SDValue Op1 = N->getOperand(1);
17392 // X86 can't encode an immediate LHS of a sub. See if we can push the
17393 // negation into a preceding instruction.
17394 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
17395 // If the RHS of the sub is a XOR with one use and a constant, invert the
17396 // immediate. Then add one to the LHS of the sub so we can turn
17397 // X-Y -> X+~Y+1, saving one register.
17398 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
17399 isa<ConstantSDNode>(Op1.getOperand(1))) {
17400 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
17401 EVT VT = Op0.getValueType();
17402 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
17404 DAG.getConstant(~XorC, VT));
17405 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
17406 DAG.getConstant(C->getAPIntValue()+1, VT));
17410 // Try to synthesize horizontal adds from adds of shuffles.
17411 EVT VT = N->getValueType(0);
17412 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17413 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17414 isHorizontalBinOp(Op0, Op1, true))
17415 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
17417 return OptimizeConditionalInDecrement(N, DAG);
17420 /// performVZEXTCombine - Performs build vector combines
17421 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
17422 TargetLowering::DAGCombinerInfo &DCI,
17423 const X86Subtarget *Subtarget) {
17424 // (vzext (bitcast (vzext (x)) -> (vzext x)
17425 SDValue In = N->getOperand(0);
17426 while (In.getOpcode() == ISD::BITCAST)
17427 In = In.getOperand(0);
17429 if (In.getOpcode() != X86ISD::VZEXT)
17432 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0),
17436 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
17437 DAGCombinerInfo &DCI) const {
17438 SelectionDAG &DAG = DCI.DAG;
17439 switch (N->getOpcode()) {
17441 case ISD::EXTRACT_VECTOR_ELT:
17442 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
17444 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
17445 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
17446 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
17447 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
17448 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
17449 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
17452 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
17453 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
17454 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
17455 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
17456 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
17457 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
17458 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
17459 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
17460 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
17462 case X86ISD::FOR: return PerformFORCombine(N, DAG);
17464 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
17465 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
17466 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
17467 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
17468 case ISD::ANY_EXTEND:
17469 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
17470 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
17471 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
17472 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
17473 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
17474 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
17475 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
17476 case X86ISD::SHUFP: // Handle all target specific shuffles
17477 case X86ISD::PALIGNR:
17478 case X86ISD::UNPCKH:
17479 case X86ISD::UNPCKL:
17480 case X86ISD::MOVHLPS:
17481 case X86ISD::MOVLHPS:
17482 case X86ISD::PSHUFD:
17483 case X86ISD::PSHUFHW:
17484 case X86ISD::PSHUFLW:
17485 case X86ISD::MOVSS:
17486 case X86ISD::MOVSD:
17487 case X86ISD::VPERMILP:
17488 case X86ISD::VPERM2X128:
17489 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
17490 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
17496 /// isTypeDesirableForOp - Return true if the target has native support for
17497 /// the specified value type and it is 'desirable' to use the type for the
17498 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
17499 /// instruction encodings are longer and some i16 instructions are slow.
17500 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
17501 if (!isTypeLegal(VT))
17503 if (VT != MVT::i16)
17510 case ISD::SIGN_EXTEND:
17511 case ISD::ZERO_EXTEND:
17512 case ISD::ANY_EXTEND:
17525 /// IsDesirableToPromoteOp - This method query the target whether it is
17526 /// beneficial for dag combiner to promote the specified node. If true, it
17527 /// should return the desired promotion type by reference.
17528 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
17529 EVT VT = Op.getValueType();
17530 if (VT != MVT::i16)
17533 bool Promote = false;
17534 bool Commute = false;
17535 switch (Op.getOpcode()) {
17538 LoadSDNode *LD = cast<LoadSDNode>(Op);
17539 // If the non-extending load has a single use and it's not live out, then it
17540 // might be folded.
17541 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
17542 Op.hasOneUse()*/) {
17543 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
17544 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
17545 // The only case where we'd want to promote LOAD (rather then it being
17546 // promoted as an operand is when it's only use is liveout.
17547 if (UI->getOpcode() != ISD::CopyToReg)
17554 case ISD::SIGN_EXTEND:
17555 case ISD::ZERO_EXTEND:
17556 case ISD::ANY_EXTEND:
17561 SDValue N0 = Op.getOperand(0);
17562 // Look out for (store (shl (load), x)).
17563 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
17576 SDValue N0 = Op.getOperand(0);
17577 SDValue N1 = Op.getOperand(1);
17578 if (!Commute && MayFoldLoad(N1))
17580 // Avoid disabling potential load folding opportunities.
17581 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
17583 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
17593 //===----------------------------------------------------------------------===//
17594 // X86 Inline Assembly Support
17595 //===----------------------------------------------------------------------===//
17598 // Helper to match a string separated by whitespace.
17599 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
17600 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
17602 for (unsigned i = 0, e = args.size(); i != e; ++i) {
17603 StringRef piece(*args[i]);
17604 if (!s.startswith(piece)) // Check if the piece matches.
17607 s = s.substr(piece.size());
17608 StringRef::size_type pos = s.find_first_not_of(" \t");
17609 if (pos == 0) // We matched a prefix.
17617 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
17620 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
17621 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
17623 std::string AsmStr = IA->getAsmString();
17625 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
17626 if (!Ty || Ty->getBitWidth() % 16 != 0)
17629 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
17630 SmallVector<StringRef, 4> AsmPieces;
17631 SplitString(AsmStr, AsmPieces, ";\n");
17633 switch (AsmPieces.size()) {
17634 default: return false;
17636 // FIXME: this should verify that we are targeting a 486 or better. If not,
17637 // we will turn this bswap into something that will be lowered to logical
17638 // ops instead of emitting the bswap asm. For now, we don't support 486 or
17639 // lower so don't worry about this.
17641 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
17642 matchAsm(AsmPieces[0], "bswapl", "$0") ||
17643 matchAsm(AsmPieces[0], "bswapq", "$0") ||
17644 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
17645 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
17646 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
17647 // No need to check constraints, nothing other than the equivalent of
17648 // "=r,0" would be valid here.
17649 return IntrinsicLowering::LowerToByteSwap(CI);
17652 // rorw $$8, ${0:w} --> llvm.bswap.i16
17653 if (CI->getType()->isIntegerTy(16) &&
17654 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17655 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
17656 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
17658 const std::string &ConstraintsStr = IA->getConstraintString();
17659 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17660 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
17661 if (AsmPieces.size() == 4 &&
17662 AsmPieces[0] == "~{cc}" &&
17663 AsmPieces[1] == "~{dirflag}" &&
17664 AsmPieces[2] == "~{flags}" &&
17665 AsmPieces[3] == "~{fpsr}")
17666 return IntrinsicLowering::LowerToByteSwap(CI);
17670 if (CI->getType()->isIntegerTy(32) &&
17671 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17672 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
17673 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
17674 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
17676 const std::string &ConstraintsStr = IA->getConstraintString();
17677 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17678 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
17679 if (AsmPieces.size() == 4 &&
17680 AsmPieces[0] == "~{cc}" &&
17681 AsmPieces[1] == "~{dirflag}" &&
17682 AsmPieces[2] == "~{flags}" &&
17683 AsmPieces[3] == "~{fpsr}")
17684 return IntrinsicLowering::LowerToByteSwap(CI);
17687 if (CI->getType()->isIntegerTy(64)) {
17688 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
17689 if (Constraints.size() >= 2 &&
17690 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
17691 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
17692 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
17693 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
17694 matchAsm(AsmPieces[1], "bswap", "%edx") &&
17695 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
17696 return IntrinsicLowering::LowerToByteSwap(CI);
17704 /// getConstraintType - Given a constraint letter, return the type of
17705 /// constraint it is for this target.
17706 X86TargetLowering::ConstraintType
17707 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
17708 if (Constraint.size() == 1) {
17709 switch (Constraint[0]) {
17720 return C_RegisterClass;
17744 return TargetLowering::getConstraintType(Constraint);
17747 /// Examine constraint type and operand type and determine a weight value.
17748 /// This object must already have been set up with the operand type
17749 /// and the current alternative constraint selected.
17750 TargetLowering::ConstraintWeight
17751 X86TargetLowering::getSingleConstraintMatchWeight(
17752 AsmOperandInfo &info, const char *constraint) const {
17753 ConstraintWeight weight = CW_Invalid;
17754 Value *CallOperandVal = info.CallOperandVal;
17755 // If we don't have a value, we can't do a match,
17756 // but allow it at the lowest weight.
17757 if (CallOperandVal == NULL)
17759 Type *type = CallOperandVal->getType();
17760 // Look at the constraint type.
17761 switch (*constraint) {
17763 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
17774 if (CallOperandVal->getType()->isIntegerTy())
17775 weight = CW_SpecificReg;
17780 if (type->isFloatingPointTy())
17781 weight = CW_SpecificReg;
17784 if (type->isX86_MMXTy() && Subtarget->hasMMX())
17785 weight = CW_SpecificReg;
17789 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
17790 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
17791 weight = CW_Register;
17794 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
17795 if (C->getZExtValue() <= 31)
17796 weight = CW_Constant;
17800 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17801 if (C->getZExtValue() <= 63)
17802 weight = CW_Constant;
17806 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17807 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
17808 weight = CW_Constant;
17812 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17813 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
17814 weight = CW_Constant;
17818 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17819 if (C->getZExtValue() <= 3)
17820 weight = CW_Constant;
17824 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17825 if (C->getZExtValue() <= 0xff)
17826 weight = CW_Constant;
17831 if (dyn_cast<ConstantFP>(CallOperandVal)) {
17832 weight = CW_Constant;
17836 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17837 if ((C->getSExtValue() >= -0x80000000LL) &&
17838 (C->getSExtValue() <= 0x7fffffffLL))
17839 weight = CW_Constant;
17843 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17844 if (C->getZExtValue() <= 0xffffffff)
17845 weight = CW_Constant;
17852 /// LowerXConstraint - try to replace an X constraint, which matches anything,
17853 /// with another that has more specific requirements based on the type of the
17854 /// corresponding operand.
17855 const char *X86TargetLowering::
17856 LowerXConstraint(EVT ConstraintVT) const {
17857 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
17858 // 'f' like normal targets.
17859 if (ConstraintVT.isFloatingPoint()) {
17860 if (Subtarget->hasSSE2())
17862 if (Subtarget->hasSSE1())
17866 return TargetLowering::LowerXConstraint(ConstraintVT);
17869 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
17870 /// vector. If it is invalid, don't add anything to Ops.
17871 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
17872 std::string &Constraint,
17873 std::vector<SDValue>&Ops,
17874 SelectionDAG &DAG) const {
17875 SDValue Result(0, 0);
17877 // Only support length 1 constraints for now.
17878 if (Constraint.length() > 1) return;
17880 char ConstraintLetter = Constraint[0];
17881 switch (ConstraintLetter) {
17884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17885 if (C->getZExtValue() <= 31) {
17886 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17892 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17893 if (C->getZExtValue() <= 63) {
17894 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17901 if (isInt<8>(C->getSExtValue())) {
17902 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17908 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17909 if (C->getZExtValue() <= 255) {
17910 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17916 // 32-bit signed value
17917 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17918 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17919 C->getSExtValue())) {
17920 // Widen to 64 bits here to get it sign extended.
17921 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
17924 // FIXME gcc accepts some relocatable values here too, but only in certain
17925 // memory models; it's complicated.
17930 // 32-bit unsigned value
17931 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17932 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17933 C->getZExtValue())) {
17934 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17938 // FIXME gcc accepts some relocatable values here too, but only in certain
17939 // memory models; it's complicated.
17943 // Literal immediates are always ok.
17944 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
17945 // Widen to 64 bits here to get it sign extended.
17946 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
17950 // In any sort of PIC mode addresses need to be computed at runtime by
17951 // adding in a register or some sort of table lookup. These can't
17952 // be used as immediates.
17953 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
17956 // If we are in non-pic codegen mode, we allow the address of a global (with
17957 // an optional displacement) to be used with 'i'.
17958 GlobalAddressSDNode *GA = 0;
17959 int64_t Offset = 0;
17961 // Match either (GA), (GA+C), (GA+C1+C2), etc.
17963 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
17964 Offset += GA->getOffset();
17966 } else if (Op.getOpcode() == ISD::ADD) {
17967 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17968 Offset += C->getZExtValue();
17969 Op = Op.getOperand(0);
17972 } else if (Op.getOpcode() == ISD::SUB) {
17973 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17974 Offset += -C->getZExtValue();
17975 Op = Op.getOperand(0);
17980 // Otherwise, this isn't something we can handle, reject it.
17984 const GlobalValue *GV = GA->getGlobal();
17985 // If we require an extra load to get this address, as in PIC mode, we
17986 // can't accept it.
17987 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
17988 getTargetMachine())))
17991 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
17992 GA->getValueType(0), Offset);
17997 if (Result.getNode()) {
17998 Ops.push_back(Result);
18001 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
18004 std::pair<unsigned, const TargetRegisterClass*>
18005 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
18007 // First, see if this is a constraint that directly corresponds to an LLVM
18009 if (Constraint.size() == 1) {
18010 // GCC Constraint Letters
18011 switch (Constraint[0]) {
18013 // TODO: Slight differences here in allocation order and leaving
18014 // RIP in the class. Do they matter any more here than they do
18015 // in the normal allocation?
18016 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
18017 if (Subtarget->is64Bit()) {
18018 if (VT == MVT::i32 || VT == MVT::f32)
18019 return std::make_pair(0U, &X86::GR32RegClass);
18020 if (VT == MVT::i16)
18021 return std::make_pair(0U, &X86::GR16RegClass);
18022 if (VT == MVT::i8 || VT == MVT::i1)
18023 return std::make_pair(0U, &X86::GR8RegClass);
18024 if (VT == MVT::i64 || VT == MVT::f64)
18025 return std::make_pair(0U, &X86::GR64RegClass);
18028 // 32-bit fallthrough
18029 case 'Q': // Q_REGS
18030 if (VT == MVT::i32 || VT == MVT::f32)
18031 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
18032 if (VT == MVT::i16)
18033 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
18034 if (VT == MVT::i8 || VT == MVT::i1)
18035 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
18036 if (VT == MVT::i64)
18037 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
18039 case 'r': // GENERAL_REGS
18040 case 'l': // INDEX_REGS
18041 if (VT == MVT::i8 || VT == MVT::i1)
18042 return std::make_pair(0U, &X86::GR8RegClass);
18043 if (VT == MVT::i16)
18044 return std::make_pair(0U, &X86::GR16RegClass);
18045 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
18046 return std::make_pair(0U, &X86::GR32RegClass);
18047 return std::make_pair(0U, &X86::GR64RegClass);
18048 case 'R': // LEGACY_REGS
18049 if (VT == MVT::i8 || VT == MVT::i1)
18050 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
18051 if (VT == MVT::i16)
18052 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
18053 if (VT == MVT::i32 || !Subtarget->is64Bit())
18054 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
18055 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
18056 case 'f': // FP Stack registers.
18057 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
18058 // value to the correct fpstack register class.
18059 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
18060 return std::make_pair(0U, &X86::RFP32RegClass);
18061 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
18062 return std::make_pair(0U, &X86::RFP64RegClass);
18063 return std::make_pair(0U, &X86::RFP80RegClass);
18064 case 'y': // MMX_REGS if MMX allowed.
18065 if (!Subtarget->hasMMX()) break;
18066 return std::make_pair(0U, &X86::VR64RegClass);
18067 case 'Y': // SSE_REGS if SSE2 allowed
18068 if (!Subtarget->hasSSE2()) break;
18070 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
18071 if (!Subtarget->hasSSE1()) break;
18073 switch (VT.getSimpleVT().SimpleTy) {
18075 // Scalar SSE types.
18078 return std::make_pair(0U, &X86::FR32RegClass);
18081 return std::make_pair(0U, &X86::FR64RegClass);
18089 return std::make_pair(0U, &X86::VR128RegClass);
18097 return std::make_pair(0U, &X86::VR256RegClass);
18103 // Use the default implementation in TargetLowering to convert the register
18104 // constraint into a member of a register class.
18105 std::pair<unsigned, const TargetRegisterClass*> Res;
18106 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
18108 // Not found as a standard register?
18109 if (Res.second == 0) {
18110 // Map st(0) -> st(7) -> ST0
18111 if (Constraint.size() == 7 && Constraint[0] == '{' &&
18112 tolower(Constraint[1]) == 's' &&
18113 tolower(Constraint[2]) == 't' &&
18114 Constraint[3] == '(' &&
18115 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
18116 Constraint[5] == ')' &&
18117 Constraint[6] == '}') {
18119 Res.first = X86::ST0+Constraint[4]-'0';
18120 Res.second = &X86::RFP80RegClass;
18124 // GCC allows "st(0)" to be called just plain "st".
18125 if (StringRef("{st}").equals_lower(Constraint)) {
18126 Res.first = X86::ST0;
18127 Res.second = &X86::RFP80RegClass;
18132 if (StringRef("{flags}").equals_lower(Constraint)) {
18133 Res.first = X86::EFLAGS;
18134 Res.second = &X86::CCRRegClass;
18138 // 'A' means EAX + EDX.
18139 if (Constraint == "A") {
18140 Res.first = X86::EAX;
18141 Res.second = &X86::GR32_ADRegClass;
18147 // Otherwise, check to see if this is a register class of the wrong value
18148 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
18149 // turn into {ax},{dx}.
18150 if (Res.second->hasType(VT))
18151 return Res; // Correct type already, nothing to do.
18153 // All of the single-register GCC register classes map their values onto
18154 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
18155 // really want an 8-bit or 32-bit register, map to the appropriate register
18156 // class and return the appropriate register.
18157 if (Res.second == &X86::GR16RegClass) {
18158 if (VT == MVT::i8 || VT == MVT::i1) {
18159 unsigned DestReg = 0;
18160 switch (Res.first) {
18162 case X86::AX: DestReg = X86::AL; break;
18163 case X86::DX: DestReg = X86::DL; break;
18164 case X86::CX: DestReg = X86::CL; break;
18165 case X86::BX: DestReg = X86::BL; break;
18168 Res.first = DestReg;
18169 Res.second = &X86::GR8RegClass;
18171 } else if (VT == MVT::i32 || VT == MVT::f32) {
18172 unsigned DestReg = 0;
18173 switch (Res.first) {
18175 case X86::AX: DestReg = X86::EAX; break;
18176 case X86::DX: DestReg = X86::EDX; break;
18177 case X86::CX: DestReg = X86::ECX; break;
18178 case X86::BX: DestReg = X86::EBX; break;
18179 case X86::SI: DestReg = X86::ESI; break;
18180 case X86::DI: DestReg = X86::EDI; break;
18181 case X86::BP: DestReg = X86::EBP; break;
18182 case X86::SP: DestReg = X86::ESP; break;
18185 Res.first = DestReg;
18186 Res.second = &X86::GR32RegClass;
18188 } else if (VT == MVT::i64 || VT == MVT::f64) {
18189 unsigned DestReg = 0;
18190 switch (Res.first) {
18192 case X86::AX: DestReg = X86::RAX; break;
18193 case X86::DX: DestReg = X86::RDX; break;
18194 case X86::CX: DestReg = X86::RCX; break;
18195 case X86::BX: DestReg = X86::RBX; break;
18196 case X86::SI: DestReg = X86::RSI; break;
18197 case X86::DI: DestReg = X86::RDI; break;
18198 case X86::BP: DestReg = X86::RBP; break;
18199 case X86::SP: DestReg = X86::RSP; break;
18202 Res.first = DestReg;
18203 Res.second = &X86::GR64RegClass;
18206 } else if (Res.second == &X86::FR32RegClass ||
18207 Res.second == &X86::FR64RegClass ||
18208 Res.second == &X86::VR128RegClass) {
18209 // Handle references to XMM physical registers that got mapped into the
18210 // wrong class. This can happen with constraints like {xmm0} where the
18211 // target independent register mapper will just pick the first match it can
18212 // find, ignoring the required type.
18214 if (VT == MVT::f32 || VT == MVT::i32)
18215 Res.second = &X86::FR32RegClass;
18216 else if (VT == MVT::f64 || VT == MVT::i64)
18217 Res.second = &X86::FR64RegClass;
18218 else if (X86::VR128RegClass.hasType(VT))
18219 Res.second = &X86::VR128RegClass;
18220 else if (X86::VR256RegClass.hasType(VT))
18221 Res.second = &X86::VR256RegClass;