1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
18 #include "X86InstrBuilder.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/SmallSet.h"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/ADT/StringExtras.h"
45 #include "llvm/ADT/VariadicFunction.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // Forward declarations.
57 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
60 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
61 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
62 /// simple subregister reference. Idx is an index in the 128 bits we
63 /// want. It need not be aligned to a 128-bit bounday. That makes
64 /// lowering EXTRACT_VECTOR_ELT operations easier.
65 static SDValue Extract128BitVector(SDValue Vec,
69 EVT VT = Vec.getValueType();
70 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
71 EVT ElVT = VT.getVectorElementType();
72 int Factor = VT.getSizeInBits()/128;
73 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
74 VT.getVectorNumElements()/Factor);
76 // Extract from UNDEF is UNDEF.
77 if (Vec.getOpcode() == ISD::UNDEF)
78 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
80 if (isa<ConstantSDNode>(Idx)) {
81 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
83 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
84 // we can match to VEXTRACTF128.
85 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
87 // This is the index of the first element of the 128-bit chunk
89 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
92 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
93 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
102 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
103 /// sets things up to match to an AVX VINSERTF128 instruction or a
104 /// simple superregister reference. Idx is an index in the 128 bits
105 /// we want. It need not be aligned to a 128-bit bounday. That makes
106 /// lowering INSERT_VECTOR_ELT operations easier.
107 static SDValue Insert128BitVector(SDValue Result,
112 if (isa<ConstantSDNode>(Idx)) {
113 EVT VT = Vec.getValueType();
114 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
116 EVT ElVT = VT.getVectorElementType();
117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
118 EVT ResultVT = Result.getValueType();
120 // Insert the relevant 128 bits.
121 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
123 // This is the index of the first element of the 128-bit chunk
125 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
128 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
129 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X8664_MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetELF())
148 return new TargetLoweringObjectFileELF();
149 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
150 return new TargetLoweringObjectFileCOFF();
151 llvm_unreachable("unknown subtarget type");
154 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
155 : TargetLowering(TM, createTLOF(TM)) {
156 Subtarget = &TM.getSubtarget<X86Subtarget>();
157 X86ScalarSSEf64 = Subtarget->hasSSE2();
158 X86ScalarSSEf32 = Subtarget->hasSSE1();
159 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
161 RegInfo = TM.getRegisterInfo();
162 TD = getTargetData();
164 // Set up the TargetLowering object.
165 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
167 // X86 is weird, it always uses i8 for shift amounts and setcc results.
168 setBooleanContents(ZeroOrOneBooleanContent);
169 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
170 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
172 // For 64-bit since we have so many registers use the ILP scheduler, for
173 // 32-bit code use the register pressure specific scheduling.
174 // For 32 bit Atom, use Hybrid (register pressure + latency) scheduling.
175 if (Subtarget->is64Bit())
176 setSchedulingPreference(Sched::ILP);
177 else if (Subtarget->isAtom())
178 setSchedulingPreference(Sched::Hybrid);
180 setSchedulingPreference(Sched::RegPressure);
181 setStackPointerRegisterToSaveRestore(X86StackPtr);
183 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
184 // Setup Windows compiler runtime calls.
185 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
186 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
187 setLibcallName(RTLIB::SREM_I64, "_allrem");
188 setLibcallName(RTLIB::UREM_I64, "_aullrem");
189 setLibcallName(RTLIB::MUL_I64, "_allmul");
190 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
191 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
192 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
193 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
194 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
196 // The _ftol2 runtime function has an unusual calling conv, which
197 // is modeled by a special pseudo-instruction.
198 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
199 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
200 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
201 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
204 if (Subtarget->isTargetDarwin()) {
205 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
206 setUseUnderscoreSetJmp(false);
207 setUseUnderscoreLongJmp(false);
208 } else if (Subtarget->isTargetMingw()) {
209 // MS runtime is weird: it exports _setjmp, but longjmp!
210 setUseUnderscoreSetJmp(true);
211 setUseUnderscoreLongJmp(false);
213 setUseUnderscoreSetJmp(true);
214 setUseUnderscoreLongJmp(true);
217 // Set up the register classes.
218 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
219 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
220 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
221 if (Subtarget->is64Bit())
222 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
224 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
226 // We don't accept any truncstore of integer registers.
227 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
228 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
229 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
230 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
231 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
232 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
234 // SETOEQ and SETUNE require checking two conditions.
235 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
236 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
237 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
238 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
242 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
244 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
245 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
246 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
248 if (Subtarget->is64Bit()) {
249 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
251 } else if (!TM.Options.UseSoftFloat) {
252 // We have an algorithm for SSE2->double, and we turn this into a
253 // 64-bit FILD followed by conditional FADD for other targets.
254 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
255 // We have an algorithm for SSE2, and we turn this into a 64-bit
256 // FILD for other targets.
257 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
260 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
262 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
263 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
265 if (!TM.Options.UseSoftFloat) {
266 // SSE has no i16 to fp conversion, only i32
267 if (X86ScalarSSEf32) {
268 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
269 // f32 and f64 cases are Legal, f80 case is not
270 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
273 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
276 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
280 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
281 // are Legal, f80 is custom lowered.
282 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
283 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
285 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
287 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
288 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
290 if (X86ScalarSSEf32) {
291 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
292 // f32 and f64 cases are Legal, f80 case is not
293 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
295 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
296 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
299 // Handle FP_TO_UINT by promoting the destination to a larger signed
301 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
302 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
303 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
305 if (Subtarget->is64Bit()) {
306 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
308 } else if (!TM.Options.UseSoftFloat) {
309 // Since AVX is a superset of SSE3, only check for SSE here.
310 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
311 // Expand FP_TO_UINT into a select.
312 // FIXME: We would like to use a Custom expander here eventually to do
313 // the optimal thing for SSE vs. the default expansion in the legalizer.
314 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
316 // With SSE3 we can use fisttpll to convert to a signed i64; without
317 // SSE, we're stuck with a fistpll.
318 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
321 if (isTargetFTOL()) {
322 // Use the _ftol2 runtime function, which has a pseudo-instruction
323 // to handle its weird calling convention.
324 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
327 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
328 if (!X86ScalarSSEf64) {
329 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
330 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
331 if (Subtarget->is64Bit()) {
332 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
333 // Without SSE, i64->f64 goes through memory.
334 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
338 // Scalar integer divide and remainder are lowered to use operations that
339 // produce two results, to match the available instructions. This exposes
340 // the two-result form to trivial CSE, which is able to combine x/y and x%y
341 // into a single instruction.
343 // Scalar integer multiply-high is also lowered to use two-result
344 // operations, to match the available instructions. However, plain multiply
345 // (low) operations are left as Legal, as there are single-result
346 // instructions for this in x86. Using the two-result multiply instructions
347 // when both high and low results are needed must be arranged by dagcombine.
348 for (unsigned i = 0, e = 4; i != e; ++i) {
350 setOperationAction(ISD::MULHS, VT, Expand);
351 setOperationAction(ISD::MULHU, VT, Expand);
352 setOperationAction(ISD::SDIV, VT, Expand);
353 setOperationAction(ISD::UDIV, VT, Expand);
354 setOperationAction(ISD::SREM, VT, Expand);
355 setOperationAction(ISD::UREM, VT, Expand);
357 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
358 setOperationAction(ISD::ADDC, VT, Custom);
359 setOperationAction(ISD::ADDE, VT, Custom);
360 setOperationAction(ISD::SUBC, VT, Custom);
361 setOperationAction(ISD::SUBE, VT, Custom);
364 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
365 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
366 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
367 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
368 if (Subtarget->is64Bit())
369 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
370 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
373 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
374 setOperationAction(ISD::FREM , MVT::f32 , Expand);
375 setOperationAction(ISD::FREM , MVT::f64 , Expand);
376 setOperationAction(ISD::FREM , MVT::f80 , Expand);
377 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
379 // Promote the i8 variants and force them on up to i32 which has a shorter
381 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
382 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
383 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
384 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
385 if (Subtarget->hasBMI()) {
386 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
387 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
388 if (Subtarget->is64Bit())
389 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
391 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
392 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
397 if (Subtarget->hasLZCNT()) {
398 // When promoting the i8 variants, force them to i32 for a shorter
400 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
401 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
402 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
403 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
404 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
405 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
406 if (Subtarget->is64Bit())
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
409 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
410 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
411 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
413 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
414 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
415 if (Subtarget->is64Bit()) {
416 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
421 if (Subtarget->hasPOPCNT()) {
422 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
424 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
425 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
426 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
427 if (Subtarget->is64Bit())
428 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
431 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
432 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
434 // These should be promoted to a larger select which is supported.
435 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
436 // X86 wants to expand cmov itself.
437 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
438 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
439 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
440 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
441 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
442 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
443 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
444 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
445 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
446 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
447 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
448 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
449 if (Subtarget->is64Bit()) {
450 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
451 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
453 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
456 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
457 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
458 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
459 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
460 if (Subtarget->is64Bit())
461 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
462 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
463 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
464 if (Subtarget->is64Bit()) {
465 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
466 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
467 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
468 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
469 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
471 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
472 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
473 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
474 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
475 if (Subtarget->is64Bit()) {
476 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
477 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
478 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
481 if (Subtarget->hasSSE1())
482 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
484 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
485 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
487 // On X86 and X86-64, atomic operations are lowered to locked instructions.
488 // Locked instructions, in turn, have implicit fence semantics (all memory
489 // operations are flushed before issuing the locked instruction, and they
490 // are not buffered), so we can fold away the common pattern of
491 // fence-atomic-fence.
492 setShouldFoldAtomicFences(true);
494 // Expand certain atomics
495 for (unsigned i = 0, e = 4; i != e; ++i) {
497 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
498 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
499 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
502 if (!Subtarget->is64Bit()) {
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
504 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
505 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
506 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
507 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
508 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
509 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
510 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
513 if (Subtarget->hasCmpxchg16b()) {
514 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
517 // FIXME - use subtarget debug flags
518 if (!Subtarget->isTargetDarwin() &&
519 !Subtarget->isTargetELF() &&
520 !Subtarget->isTargetCygMing()) {
521 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
524 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
525 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
526 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
527 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
528 if (Subtarget->is64Bit()) {
529 setExceptionPointerRegister(X86::RAX);
530 setExceptionSelectorRegister(X86::RDX);
532 setExceptionPointerRegister(X86::EAX);
533 setExceptionSelectorRegister(X86::EDX);
535 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
536 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
538 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
539 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
541 setOperationAction(ISD::TRAP, MVT::Other, Legal);
543 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
544 setOperationAction(ISD::VASTART , MVT::Other, Custom);
545 setOperationAction(ISD::VAEND , MVT::Other, Expand);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::VAARG , MVT::Other, Custom);
548 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
550 setOperationAction(ISD::VAARG , MVT::Other, Expand);
551 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
554 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
555 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
557 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
558 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
559 MVT::i64 : MVT::i32, Custom);
560 else if (TM.Options.EnableSegmentedStacks)
561 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
562 MVT::i64 : MVT::i32, Custom);
564 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
565 MVT::i64 : MVT::i32, Expand);
567 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
568 // f32 and f64 use SSE.
569 // Set up the FP register classes.
570 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
571 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
573 // Use ANDPD to simulate FABS.
574 setOperationAction(ISD::FABS , MVT::f64, Custom);
575 setOperationAction(ISD::FABS , MVT::f32, Custom);
577 // Use XORP to simulate FNEG.
578 setOperationAction(ISD::FNEG , MVT::f64, Custom);
579 setOperationAction(ISD::FNEG , MVT::f32, Custom);
581 // Use ANDPD and ORPD to simulate FCOPYSIGN.
582 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
583 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
585 // Lower this to FGETSIGNx86 plus an AND.
586 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
587 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
589 // We don't support sin/cos/fmod
590 setOperationAction(ISD::FSIN , MVT::f64, Expand);
591 setOperationAction(ISD::FCOS , MVT::f64, Expand);
592 setOperationAction(ISD::FSIN , MVT::f32, Expand);
593 setOperationAction(ISD::FCOS , MVT::f32, Expand);
595 // Expand FP immediates into loads from the stack, except for the special
597 addLegalFPImmediate(APFloat(+0.0)); // xorpd
598 addLegalFPImmediate(APFloat(+0.0f)); // xorps
599 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
600 // Use SSE for f32, x87 for f64.
601 // Set up the FP register classes.
602 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
603 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
605 // Use ANDPS to simulate FABS.
606 setOperationAction(ISD::FABS , MVT::f32, Custom);
608 // Use XORP to simulate FNEG.
609 setOperationAction(ISD::FNEG , MVT::f32, Custom);
611 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
613 // Use ANDPS and ORPS to simulate FCOPYSIGN.
614 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
615 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
617 // We don't support sin/cos/fmod
618 setOperationAction(ISD::FSIN , MVT::f32, Expand);
619 setOperationAction(ISD::FCOS , MVT::f32, Expand);
621 // Special cases we handle for FP constants.
622 addLegalFPImmediate(APFloat(+0.0f)); // xorps
623 addLegalFPImmediate(APFloat(+0.0)); // FLD0
624 addLegalFPImmediate(APFloat(+1.0)); // FLD1
625 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
626 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
628 if (!TM.Options.UnsafeFPMath) {
629 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
630 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
632 } else if (!TM.Options.UseSoftFloat) {
633 // f32 and f64 in x87.
634 // Set up the FP register classes.
635 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
636 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
638 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
639 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
640 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
641 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
643 if (!TM.Options.UnsafeFPMath) {
644 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
645 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
647 addLegalFPImmediate(APFloat(+0.0)); // FLD0
648 addLegalFPImmediate(APFloat(+1.0)); // FLD1
649 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
650 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
651 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
652 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
653 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
654 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
657 // We don't support FMA.
658 setOperationAction(ISD::FMA, MVT::f64, Expand);
659 setOperationAction(ISD::FMA, MVT::f32, Expand);
661 // Long double always uses X87.
662 if (!TM.Options.UseSoftFloat) {
663 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
664 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
665 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
667 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
668 addLegalFPImmediate(TmpFlt); // FLD0
670 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
673 APFloat TmpFlt2(+1.0);
674 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
676 addLegalFPImmediate(TmpFlt2); // FLD1
677 TmpFlt2.changeSign();
678 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
681 if (!TM.Options.UnsafeFPMath) {
682 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
683 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
686 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
687 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
688 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
689 setOperationAction(ISD::FRINT, MVT::f80, Expand);
690 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
691 setOperationAction(ISD::FMA, MVT::f80, Expand);
694 // Always use a library call for pow.
695 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
696 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
697 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
699 setOperationAction(ISD::FLOG, MVT::f80, Expand);
700 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
701 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
702 setOperationAction(ISD::FEXP, MVT::f80, Expand);
703 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
705 // First set operation action for all vector types to either promote
706 // (for widening) or expand (for scalarization). Then we will selectively
707 // turn on ones that can be effectively codegen'd.
708 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
709 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
710 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
725 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
726 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
727 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
728 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
731 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
732 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
733 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
734 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
735 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
736 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
737 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
738 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
739 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
740 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
741 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
742 setOperationAction(ISD::CTTZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
743 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
744 setOperationAction(ISD::CTLZ_ZERO_UNDEF, (MVT::SimpleValueType)VT, Expand);
745 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
746 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
747 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
748 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
749 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
750 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
751 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
752 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
753 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
754 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
755 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
756 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
757 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
758 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
759 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
760 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
761 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
762 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
763 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
764 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
765 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
766 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
767 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
768 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
769 setTruncStoreAction((MVT::SimpleValueType)VT,
770 (MVT::SimpleValueType)InnerVT, Expand);
771 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
772 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
773 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
776 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
777 // with -msoft-float, disable use of MMX as well.
778 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
779 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
780 // No operations on x86mmx supported, everything uses intrinsics.
783 // MMX-sized vectors (other than x86mmx) are expected to be expanded
784 // into smaller operations.
785 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
786 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
787 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
788 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
789 setOperationAction(ISD::AND, MVT::v8i8, Expand);
790 setOperationAction(ISD::AND, MVT::v4i16, Expand);
791 setOperationAction(ISD::AND, MVT::v2i32, Expand);
792 setOperationAction(ISD::AND, MVT::v1i64, Expand);
793 setOperationAction(ISD::OR, MVT::v8i8, Expand);
794 setOperationAction(ISD::OR, MVT::v4i16, Expand);
795 setOperationAction(ISD::OR, MVT::v2i32, Expand);
796 setOperationAction(ISD::OR, MVT::v1i64, Expand);
797 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
798 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
799 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
800 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
801 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
802 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
803 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
804 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
806 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
807 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
808 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
809 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
810 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
811 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
812 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
813 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
815 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
816 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
818 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
819 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
820 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
821 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
822 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
823 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
824 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
825 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
826 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
827 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
828 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
829 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
832 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
833 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
835 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
836 // registers cannot be used even for integer operations.
837 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
838 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
839 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
840 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
842 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
843 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
844 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
845 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
846 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
847 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
848 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
849 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
850 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
851 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
852 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
853 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
854 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
855 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
856 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
857 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
859 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
860 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
861 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
862 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
866 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
870 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
871 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
872 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
876 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
877 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
878 EVT VT = (MVT::SimpleValueType)i;
879 // Do not attempt to custom lower non-power-of-2 vectors
880 if (!isPowerOf2_32(VT.getVectorNumElements()))
882 // Do not attempt to custom lower non-128-bit vectors
883 if (!VT.is128BitVector())
885 setOperationAction(ISD::BUILD_VECTOR,
886 VT.getSimpleVT().SimpleTy, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE,
888 VT.getSimpleVT().SimpleTy, Custom);
889 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
890 VT.getSimpleVT().SimpleTy, Custom);
893 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
895 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
900 if (Subtarget->is64Bit()) {
901 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
902 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
905 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
906 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
907 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
910 // Do not attempt to promote non-128-bit vectors
911 if (!VT.is128BitVector())
914 setOperationAction(ISD::AND, SVT, Promote);
915 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
916 setOperationAction(ISD::OR, SVT, Promote);
917 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
918 setOperationAction(ISD::XOR, SVT, Promote);
919 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
920 setOperationAction(ISD::LOAD, SVT, Promote);
921 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
922 setOperationAction(ISD::SELECT, SVT, Promote);
923 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
926 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
938 if (Subtarget->hasSSE41()) {
939 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
940 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
941 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
942 setOperationAction(ISD::FRINT, MVT::f32, Legal);
943 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
944 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
945 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
946 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
947 setOperationAction(ISD::FRINT, MVT::f64, Legal);
948 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
950 // FIXME: Do we need to handle scalar-to-vector here?
951 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
953 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
954 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
955 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
956 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
957 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
959 // i8 and i16 vectors are custom , because the source register and source
960 // source memory operand types are not the same width. f32 vectors are
961 // custom since the immediate controlling the insert encodes additional
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
966 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
968 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
969 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
970 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
971 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
973 // FIXME: these should be Legal but thats only for the case where
974 // the index is constant. For now custom expand to deal with that.
975 if (Subtarget->is64Bit()) {
976 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
977 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
981 if (Subtarget->hasSSE2()) {
982 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
983 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
985 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
986 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
988 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
989 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
991 if (Subtarget->hasAVX2()) {
992 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
993 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
995 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
996 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
998 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1000 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1001 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1003 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1004 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1006 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1010 if (Subtarget->hasSSE42())
1011 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
1013 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX()) {
1014 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
1015 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
1016 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
1017 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
1018 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
1019 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
1021 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1022 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1023 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1025 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1026 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1027 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1028 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1029 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1030 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1032 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1033 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1034 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1035 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1036 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1037 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1039 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1040 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1041 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1043 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
1044 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
1045 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
1046 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
1047 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
1048 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1050 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1051 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1053 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1054 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1056 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1057 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1059 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1060 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1061 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1062 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1064 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1065 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1066 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1068 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1070 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1071 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1073 if (Subtarget->hasAVX2()) {
1074 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1075 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1076 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1077 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1079 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1080 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1081 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1082 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1084 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1085 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1086 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1087 // Don't lower v32i8 because there is no 128-bit byte mul
1089 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1091 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1092 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1094 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1095 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1099 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1100 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1101 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1104 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1105 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1106 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1109 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1110 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1111 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1112 // Don't lower v32i8 because there is no 128-bit byte mul
1114 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1115 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1117 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1118 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1120 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1123 // Custom lower several nodes for 256-bit types.
1124 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1125 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1126 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1129 // Extract subvector is special because the value type
1130 // (result) is 128-bit but the source is 256-bit wide.
1131 if (VT.is128BitVector())
1132 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1134 // Do not attempt to custom lower other non-256-bit vectors
1135 if (!VT.is256BitVector())
1138 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1139 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1140 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1142 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1143 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1146 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1147 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1148 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1151 // Do not attempt to promote non-256-bit vectors
1152 if (!VT.is256BitVector())
1155 setOperationAction(ISD::AND, SVT, Promote);
1156 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1157 setOperationAction(ISD::OR, SVT, Promote);
1158 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1159 setOperationAction(ISD::XOR, SVT, Promote);
1160 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1161 setOperationAction(ISD::LOAD, SVT, Promote);
1162 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1163 setOperationAction(ISD::SELECT, SVT, Promote);
1164 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1168 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1169 // of this type with custom code.
1170 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1171 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1172 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1176 // We want to custom lower some of our intrinsics.
1177 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1180 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1181 // handle type legalization for these operations here.
1183 // FIXME: We really should do custom legalization for addition and
1184 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1185 // than generic legalization for 64-bit multiplication-with-overflow, though.
1186 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1187 // Add/Sub/Mul with overflow operations are custom lowered.
1189 setOperationAction(ISD::SADDO, VT, Custom);
1190 setOperationAction(ISD::UADDO, VT, Custom);
1191 setOperationAction(ISD::SSUBO, VT, Custom);
1192 setOperationAction(ISD::USUBO, VT, Custom);
1193 setOperationAction(ISD::SMULO, VT, Custom);
1194 setOperationAction(ISD::UMULO, VT, Custom);
1197 // There are no 8-bit 3-address imul/mul instructions
1198 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1199 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1201 if (!Subtarget->is64Bit()) {
1202 // These libcalls are not available in 32-bit.
1203 setLibcallName(RTLIB::SHL_I128, 0);
1204 setLibcallName(RTLIB::SRL_I128, 0);
1205 setLibcallName(RTLIB::SRA_I128, 0);
1208 // We have target-specific dag combine patterns for the following nodes:
1209 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1210 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1211 setTargetDAGCombine(ISD::VSELECT);
1212 setTargetDAGCombine(ISD::SELECT);
1213 setTargetDAGCombine(ISD::SHL);
1214 setTargetDAGCombine(ISD::SRA);
1215 setTargetDAGCombine(ISD::SRL);
1216 setTargetDAGCombine(ISD::OR);
1217 setTargetDAGCombine(ISD::AND);
1218 setTargetDAGCombine(ISD::ADD);
1219 setTargetDAGCombine(ISD::FADD);
1220 setTargetDAGCombine(ISD::FSUB);
1221 setTargetDAGCombine(ISD::SUB);
1222 setTargetDAGCombine(ISD::LOAD);
1223 setTargetDAGCombine(ISD::STORE);
1224 setTargetDAGCombine(ISD::ZERO_EXTEND);
1225 setTargetDAGCombine(ISD::SIGN_EXTEND);
1226 setTargetDAGCombine(ISD::TRUNCATE);
1227 setTargetDAGCombine(ISD::SINT_TO_FP);
1228 if (Subtarget->is64Bit())
1229 setTargetDAGCombine(ISD::MUL);
1230 if (Subtarget->hasBMI())
1231 setTargetDAGCombine(ISD::XOR);
1233 computeRegisterProperties();
1235 // On Darwin, -Os means optimize for size without hurting performance,
1236 // do not reduce the limit.
1237 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1238 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1239 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1240 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1241 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1242 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1243 setPrefLoopAlignment(4); // 2^4 bytes.
1244 benefitFromCodePlacementOpt = true;
1246 setPrefFunctionAlignment(4); // 2^4 bytes.
1250 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1251 if (!VT.isVector()) return MVT::i8;
1252 return VT.changeVectorElementTypeToInteger();
1256 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1257 /// the desired ByVal argument alignment.
1258 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1261 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1262 if (VTy->getBitWidth() == 128)
1264 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1265 unsigned EltAlign = 0;
1266 getMaxByValAlign(ATy->getElementType(), EltAlign);
1267 if (EltAlign > MaxAlign)
1268 MaxAlign = EltAlign;
1269 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1270 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1271 unsigned EltAlign = 0;
1272 getMaxByValAlign(STy->getElementType(i), EltAlign);
1273 if (EltAlign > MaxAlign)
1274 MaxAlign = EltAlign;
1282 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1283 /// function arguments in the caller parameter area. For X86, aggregates
1284 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1285 /// are at 4-byte boundaries.
1286 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1287 if (Subtarget->is64Bit()) {
1288 // Max of 8 and alignment of type.
1289 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1296 if (Subtarget->hasSSE1())
1297 getMaxByValAlign(Ty, Align);
1301 /// getOptimalMemOpType - Returns the target specific optimal type for load
1302 /// and store operations as a result of memset, memcpy, and memmove
1303 /// lowering. If DstAlign is zero that means it's safe to destination
1304 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1305 /// means there isn't a need to check it against alignment requirement,
1306 /// probably because the source does not need to be loaded. If
1307 /// 'IsZeroVal' is true, that means it's safe to return a
1308 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1309 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1310 /// constant so it does not need to be loaded.
1311 /// It returns EVT::Other if the type should be determined using generic
1312 /// target-independent logic.
1314 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1315 unsigned DstAlign, unsigned SrcAlign,
1318 MachineFunction &MF) const {
1319 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1320 // linux. This is because the stack realignment code can't handle certain
1321 // cases like PR2962. This should be removed when PR2962 is fixed.
1322 const Function *F = MF.getFunction();
1324 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1326 (Subtarget->isUnalignedMemAccessFast() ||
1327 ((DstAlign == 0 || DstAlign >= 16) &&
1328 (SrcAlign == 0 || SrcAlign >= 16))) &&
1329 Subtarget->getStackAlignment() >= 16) {
1330 if (Subtarget->getStackAlignment() >= 32) {
1331 if (Subtarget->hasAVX2())
1333 if (Subtarget->hasAVX())
1336 if (Subtarget->hasSSE2())
1338 if (Subtarget->hasSSE1())
1340 } else if (!MemcpyStrSrc && Size >= 8 &&
1341 !Subtarget->is64Bit() &&
1342 Subtarget->getStackAlignment() >= 8 &&
1343 Subtarget->hasSSE2()) {
1344 // Do not use f64 to lower memcpy if source is string constant. It's
1345 // better to use i32 to avoid the loads.
1349 if (Subtarget->is64Bit() && Size >= 8)
1354 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1355 /// current function. The returned value is a member of the
1356 /// MachineJumpTableInfo::JTEntryKind enum.
1357 unsigned X86TargetLowering::getJumpTableEncoding() const {
1358 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1360 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1361 Subtarget->isPICStyleGOT())
1362 return MachineJumpTableInfo::EK_Custom32;
1364 // Otherwise, use the normal jump table encoding heuristics.
1365 return TargetLowering::getJumpTableEncoding();
1369 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1370 const MachineBasicBlock *MBB,
1371 unsigned uid,MCContext &Ctx) const{
1372 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1373 Subtarget->isPICStyleGOT());
1374 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1376 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1377 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1380 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1382 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1383 SelectionDAG &DAG) const {
1384 if (!Subtarget->is64Bit())
1385 // This doesn't have DebugLoc associated with it, but is not really the
1386 // same as a Register.
1387 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1391 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1392 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1394 const MCExpr *X86TargetLowering::
1395 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1396 MCContext &Ctx) const {
1397 // X86-64 uses RIP relative addressing based on the jump table label.
1398 if (Subtarget->isPICStyleRIPRel())
1399 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1401 // Otherwise, the reference is relative to the PIC base.
1402 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1405 // FIXME: Why this routine is here? Move to RegInfo!
1406 std::pair<const TargetRegisterClass*, uint8_t>
1407 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1408 const TargetRegisterClass *RRC = 0;
1410 switch (VT.getSimpleVT().SimpleTy) {
1412 return TargetLowering::findRepresentativeClass(VT);
1413 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1414 RRC = (Subtarget->is64Bit()
1415 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1418 RRC = X86::VR64RegisterClass;
1420 case MVT::f32: case MVT::f64:
1421 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1422 case MVT::v4f32: case MVT::v2f64:
1423 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1425 RRC = X86::VR128RegisterClass;
1428 return std::make_pair(RRC, Cost);
1431 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1432 unsigned &Offset) const {
1433 if (!Subtarget->isTargetLinux())
1436 if (Subtarget->is64Bit()) {
1437 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1439 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1452 //===----------------------------------------------------------------------===//
1453 // Return Value Calling Convention Implementation
1454 //===----------------------------------------------------------------------===//
1456 #include "X86GenCallingConv.inc"
1459 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1460 MachineFunction &MF, bool isVarArg,
1461 const SmallVectorImpl<ISD::OutputArg> &Outs,
1462 LLVMContext &Context) const {
1463 SmallVector<CCValAssign, 16> RVLocs;
1464 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1466 return CCInfo.CheckReturn(Outs, RetCC_X86);
1470 X86TargetLowering::LowerReturn(SDValue Chain,
1471 CallingConv::ID CallConv, bool isVarArg,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 DebugLoc dl, SelectionDAG &DAG) const {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1478 SmallVector<CCValAssign, 16> RVLocs;
1479 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1480 RVLocs, *DAG.getContext());
1481 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1483 // Add the regs to the liveout set for the function.
1484 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1485 for (unsigned i = 0; i != RVLocs.size(); ++i)
1486 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1487 MRI.addLiveOut(RVLocs[i].getLocReg());
1491 SmallVector<SDValue, 6> RetOps;
1492 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1493 // Operand #1 = Bytes To Pop
1494 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1497 // Copy the result values into the output registers.
1498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1501 SDValue ValToCopy = OutVals[i];
1502 EVT ValVT = ValToCopy.getValueType();
1504 // If this is x86-64, and we disabled SSE, we can't return FP values,
1505 // or SSE or MMX vectors.
1506 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1507 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1508 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1509 report_fatal_error("SSE register return with SSE disabled");
1511 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1512 // llvm-gcc has never done it right and no one has noticed, so this
1513 // should be OK for now.
1514 if (ValVT == MVT::f64 &&
1515 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1516 report_fatal_error("SSE2 register return with SSE2 disabled");
1518 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1519 // the RET instruction and handled by the FP Stackifier.
1520 if (VA.getLocReg() == X86::ST0 ||
1521 VA.getLocReg() == X86::ST1) {
1522 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1523 // change the value to the FP stack register class.
1524 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1525 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1526 RetOps.push_back(ValToCopy);
1527 // Don't emit a copytoreg.
1531 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1532 // which is returned in RAX / RDX.
1533 if (Subtarget->is64Bit()) {
1534 if (ValVT == MVT::x86mmx) {
1535 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1536 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1537 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1539 // If we don't have SSE2 available, convert to v4f32 so the generated
1540 // register is legal.
1541 if (!Subtarget->hasSSE2())
1542 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1547 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1548 Flag = Chain.getValue(1);
1551 // The x86-64 ABI for returning structs by value requires that we copy
1552 // the sret argument into %rax for the return. We saved the argument into
1553 // a virtual register in the entry block, so now we copy the value out
1555 if (Subtarget->is64Bit() &&
1556 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1559 unsigned Reg = FuncInfo->getSRetReturnReg();
1561 "SRetReturnReg should have been set in LowerFormalArguments().");
1562 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1564 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1565 Flag = Chain.getValue(1);
1567 // RAX now acts like a return value.
1568 MRI.addLiveOut(X86::RAX);
1571 RetOps[0] = Chain; // Update chain.
1573 // Add the flag if we have it.
1575 RetOps.push_back(Flag);
1577 return DAG.getNode(X86ISD::RET_FLAG, dl,
1578 MVT::Other, &RetOps[0], RetOps.size());
1581 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1582 if (N->getNumValues() != 1)
1584 if (!N->hasNUsesOfValue(1, 0))
1587 SDNode *Copy = *N->use_begin();
1588 if (Copy->getOpcode() != ISD::CopyToReg &&
1589 Copy->getOpcode() != ISD::FP_EXTEND)
1592 bool HasRet = false;
1593 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1595 if (UI->getOpcode() != X86ISD::RET_FLAG)
1604 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1605 ISD::NodeType ExtendKind) const {
1607 // TODO: Is this also valid on 32-bit?
1608 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1609 ReturnMVT = MVT::i8;
1611 ReturnMVT = MVT::i32;
1613 EVT MinVT = getRegisterType(Context, ReturnMVT);
1614 return VT.bitsLT(MinVT) ? MinVT : VT;
1617 /// LowerCallResult - Lower the result values of a call into the
1618 /// appropriate copies out of appropriate physical registers.
1621 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1622 CallingConv::ID CallConv, bool isVarArg,
1623 const SmallVectorImpl<ISD::InputArg> &Ins,
1624 DebugLoc dl, SelectionDAG &DAG,
1625 SmallVectorImpl<SDValue> &InVals) const {
1627 // Assign locations to each value returned by this call.
1628 SmallVector<CCValAssign, 16> RVLocs;
1629 bool Is64Bit = Subtarget->is64Bit();
1630 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1631 getTargetMachine(), RVLocs, *DAG.getContext());
1632 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1634 // Copy all of the result registers out of their specified physreg.
1635 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1636 CCValAssign &VA = RVLocs[i];
1637 EVT CopyVT = VA.getValVT();
1639 // If this is x86-64, and we disabled SSE, we can't return FP values
1640 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1641 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1642 report_fatal_error("SSE register return with SSE disabled");
1647 // If this is a call to a function that returns an fp value on the floating
1648 // point stack, we must guarantee the the value is popped from the stack, so
1649 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1650 // if the return value is not used. We use the FpPOP_RETVAL instruction
1652 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1653 // If we prefer to use the value in xmm registers, copy it out as f80 and
1654 // use a truncate to move it from fp stack reg to xmm reg.
1655 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1656 SDValue Ops[] = { Chain, InFlag };
1657 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1658 MVT::Other, MVT::Glue, Ops, 2), 1);
1659 Val = Chain.getValue(0);
1661 // Round the f80 to the right size, which also moves it to the appropriate
1663 if (CopyVT != VA.getValVT())
1664 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1665 // This truncation won't change the value.
1666 DAG.getIntPtrConstant(1));
1668 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1669 CopyVT, InFlag).getValue(1);
1670 Val = Chain.getValue(0);
1672 InFlag = Chain.getValue(2);
1673 InVals.push_back(Val);
1680 //===----------------------------------------------------------------------===//
1681 // C & StdCall & Fast Calling Convention implementation
1682 //===----------------------------------------------------------------------===//
1683 // StdCall calling convention seems to be standard for many Windows' API
1684 // routines and around. It differs from C calling convention just a little:
1685 // callee should clean up the stack, not caller. Symbols should be also
1686 // decorated in some fancy way :) It doesn't support any vector arguments.
1687 // For info on fast calling convention see Fast Calling Convention (tail call)
1688 // implementation LowerX86_32FastCCCallTo.
1690 /// CallIsStructReturn - Determines whether a call uses struct return
1692 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1696 return Outs[0].Flags.isSRet();
1699 /// ArgsAreStructReturn - Determines whether a function uses struct
1700 /// return semantics.
1702 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1706 return Ins[0].Flags.isSRet();
1709 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1710 /// by "Src" to address "Dst" with size and alignment information specified by
1711 /// the specific parameter attribute. The copy will be passed as a byval
1712 /// function parameter.
1714 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1715 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1717 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1719 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1720 /*isVolatile*/false, /*AlwaysInline=*/true,
1721 MachinePointerInfo(), MachinePointerInfo());
1724 /// IsTailCallConvention - Return true if the calling convention is one that
1725 /// supports tail call optimization.
1726 static bool IsTailCallConvention(CallingConv::ID CC) {
1727 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1730 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1731 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1735 CallingConv::ID CalleeCC = CS.getCallingConv();
1736 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1742 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1743 /// a tailcall target by changing its ABI.
1744 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1745 bool GuaranteedTailCallOpt) {
1746 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1750 X86TargetLowering::LowerMemArgument(SDValue Chain,
1751 CallingConv::ID CallConv,
1752 const SmallVectorImpl<ISD::InputArg> &Ins,
1753 DebugLoc dl, SelectionDAG &DAG,
1754 const CCValAssign &VA,
1755 MachineFrameInfo *MFI,
1757 // Create the nodes corresponding to a load from this parameter slot.
1758 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1759 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1760 getTargetMachine().Options.GuaranteedTailCallOpt);
1761 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1764 // If value is passed by pointer we have address passed instead of the value
1766 if (VA.getLocInfo() == CCValAssign::Indirect)
1767 ValVT = VA.getLocVT();
1769 ValVT = VA.getValVT();
1771 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1772 // changed with more analysis.
1773 // In case of tail call optimization mark all arguments mutable. Since they
1774 // could be overwritten by lowering of arguments in case of a tail call.
1775 if (Flags.isByVal()) {
1776 unsigned Bytes = Flags.getByValSize();
1777 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1778 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1779 return DAG.getFrameIndex(FI, getPointerTy());
1781 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1782 VA.getLocMemOffset(), isImmutable);
1783 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1784 return DAG.getLoad(ValVT, dl, Chain, FIN,
1785 MachinePointerInfo::getFixedStack(FI),
1786 false, false, false, 0);
1791 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1792 CallingConv::ID CallConv,
1794 const SmallVectorImpl<ISD::InputArg> &Ins,
1797 SmallVectorImpl<SDValue> &InVals)
1799 MachineFunction &MF = DAG.getMachineFunction();
1800 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1802 const Function* Fn = MF.getFunction();
1803 if (Fn->hasExternalLinkage() &&
1804 Subtarget->isTargetCygMing() &&
1805 Fn->getName() == "main")
1806 FuncInfo->setForceFramePointer(true);
1808 MachineFrameInfo *MFI = MF.getFrameInfo();
1809 bool Is64Bit = Subtarget->is64Bit();
1810 bool IsWindows = Subtarget->isTargetWindows();
1811 bool IsWin64 = Subtarget->isTargetWin64();
1813 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1814 "Var args not supported with calling convention fastcc or ghc");
1816 // Assign locations to all of the incoming arguments.
1817 SmallVector<CCValAssign, 16> ArgLocs;
1818 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1819 ArgLocs, *DAG.getContext());
1821 // Allocate shadow area for Win64
1823 CCInfo.AllocateStack(32, 8);
1826 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1828 unsigned LastVal = ~0U;
1830 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1831 CCValAssign &VA = ArgLocs[i];
1832 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1834 assert(VA.getValNo() != LastVal &&
1835 "Don't support value assigned to multiple locs yet");
1837 LastVal = VA.getValNo();
1839 if (VA.isRegLoc()) {
1840 EVT RegVT = VA.getLocVT();
1841 const TargetRegisterClass *RC;
1842 if (RegVT == MVT::i32)
1843 RC = X86::GR32RegisterClass;
1844 else if (Is64Bit && RegVT == MVT::i64)
1845 RC = X86::GR64RegisterClass;
1846 else if (RegVT == MVT::f32)
1847 RC = X86::FR32RegisterClass;
1848 else if (RegVT == MVT::f64)
1849 RC = X86::FR64RegisterClass;
1850 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1851 RC = X86::VR256RegisterClass;
1852 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1853 RC = X86::VR128RegisterClass;
1854 else if (RegVT == MVT::x86mmx)
1855 RC = X86::VR64RegisterClass;
1857 llvm_unreachable("Unknown argument type!");
1859 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1860 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1862 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1863 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1865 if (VA.getLocInfo() == CCValAssign::SExt)
1866 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1867 DAG.getValueType(VA.getValVT()));
1868 else if (VA.getLocInfo() == CCValAssign::ZExt)
1869 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1870 DAG.getValueType(VA.getValVT()));
1871 else if (VA.getLocInfo() == CCValAssign::BCvt)
1872 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1874 if (VA.isExtInLoc()) {
1875 // Handle MMX values passed in XMM regs.
1876 if (RegVT.isVector()) {
1877 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1880 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1883 assert(VA.isMemLoc());
1884 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1887 // If value is passed via pointer - do a load.
1888 if (VA.getLocInfo() == CCValAssign::Indirect)
1889 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1890 MachinePointerInfo(), false, false, false, 0);
1892 InVals.push_back(ArgValue);
1895 // The x86-64 ABI for returning structs by value requires that we copy
1896 // the sret argument into %rax for the return. Save the argument into
1897 // a virtual register so that we can access it from the return points.
1898 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1899 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1900 unsigned Reg = FuncInfo->getSRetReturnReg();
1902 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1903 FuncInfo->setSRetReturnReg(Reg);
1905 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1906 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1909 unsigned StackSize = CCInfo.getNextStackOffset();
1910 // Align stack specially for tail calls.
1911 if (FuncIsMadeTailCallSafe(CallConv,
1912 MF.getTarget().Options.GuaranteedTailCallOpt))
1913 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1915 // If the function takes variable number of arguments, make a frame index for
1916 // the start of the first vararg value... for expansion of llvm.va_start.
1918 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1919 CallConv != CallingConv::X86_ThisCall)) {
1920 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1923 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1925 // FIXME: We should really autogenerate these arrays
1926 static const unsigned GPR64ArgRegsWin64[] = {
1927 X86::RCX, X86::RDX, X86::R8, X86::R9
1929 static const unsigned GPR64ArgRegs64Bit[] = {
1930 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1932 static const unsigned XMMArgRegs64Bit[] = {
1933 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1934 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1936 const unsigned *GPR64ArgRegs;
1937 unsigned NumXMMRegs = 0;
1940 // The XMM registers which might contain var arg parameters are shadowed
1941 // in their paired GPR. So we only need to save the GPR to their home
1943 TotalNumIntRegs = 4;
1944 GPR64ArgRegs = GPR64ArgRegsWin64;
1946 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1947 GPR64ArgRegs = GPR64ArgRegs64Bit;
1949 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
1952 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1955 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1956 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1957 "SSE register cannot be used when SSE is disabled!");
1958 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
1959 NoImplicitFloatOps) &&
1960 "SSE register cannot be used when SSE is disabled!");
1961 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
1962 !Subtarget->hasSSE1())
1963 // Kernel mode asks for SSE to be disabled, so don't push them
1965 TotalNumXMMRegs = 0;
1968 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1969 // Get to the caller-allocated home save location. Add 8 to account
1970 // for the return address.
1971 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1972 FuncInfo->setRegSaveFrameIndex(
1973 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1974 // Fixup to set vararg frame on shadow area (4 x i64).
1976 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1978 // For X86-64, if there are vararg parameters that are passed via
1979 // registers, then we must store them to their spots on the stack so
1980 // they may be loaded by deferencing the result of va_next.
1981 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1982 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1983 FuncInfo->setRegSaveFrameIndex(
1984 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1988 // Store the integer parameter registers.
1989 SmallVector<SDValue, 8> MemOps;
1990 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1992 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1993 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1994 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1995 DAG.getIntPtrConstant(Offset));
1996 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1997 X86::GR64RegisterClass);
1998 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2000 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2001 MachinePointerInfo::getFixedStack(
2002 FuncInfo->getRegSaveFrameIndex(), Offset),
2004 MemOps.push_back(Store);
2008 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2009 // Now store the XMM (fp + vector) parameter registers.
2010 SmallVector<SDValue, 11> SaveXMMOps;
2011 SaveXMMOps.push_back(Chain);
2013 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
2014 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2015 SaveXMMOps.push_back(ALVal);
2017 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2018 FuncInfo->getRegSaveFrameIndex()));
2019 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2020 FuncInfo->getVarArgsFPOffset()));
2022 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2023 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2024 X86::VR128RegisterClass);
2025 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2026 SaveXMMOps.push_back(Val);
2028 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2030 &SaveXMMOps[0], SaveXMMOps.size()));
2033 if (!MemOps.empty())
2034 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2035 &MemOps[0], MemOps.size());
2039 // Some CCs need callee pop.
2040 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2041 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2042 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2044 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2045 // If this is an sret function, the return should pop the hidden pointer.
2046 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2047 ArgsAreStructReturn(Ins))
2048 FuncInfo->setBytesToPopOnReturn(4);
2052 // RegSaveFrameIndex is X86-64 only.
2053 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2054 if (CallConv == CallingConv::X86_FastCall ||
2055 CallConv == CallingConv::X86_ThisCall)
2056 // fastcc functions can't have varargs.
2057 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2060 FuncInfo->setArgumentStackSize(StackSize);
2066 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2067 SDValue StackPtr, SDValue Arg,
2068 DebugLoc dl, SelectionDAG &DAG,
2069 const CCValAssign &VA,
2070 ISD::ArgFlagsTy Flags) const {
2071 unsigned LocMemOffset = VA.getLocMemOffset();
2072 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2073 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2074 if (Flags.isByVal())
2075 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2077 return DAG.getStore(Chain, dl, Arg, PtrOff,
2078 MachinePointerInfo::getStack(LocMemOffset),
2082 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2083 /// optimization is performed and it is required.
2085 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2086 SDValue &OutRetAddr, SDValue Chain,
2087 bool IsTailCall, bool Is64Bit,
2088 int FPDiff, DebugLoc dl) const {
2089 // Adjust the Return address stack slot.
2090 EVT VT = getPointerTy();
2091 OutRetAddr = getReturnAddressFrameIndex(DAG);
2093 // Load the "old" Return address.
2094 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2095 false, false, false, 0);
2096 return SDValue(OutRetAddr.getNode(), 1);
2099 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2100 /// optimization is performed and it is required (FPDiff!=0).
2102 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2103 SDValue Chain, SDValue RetAddrFrIdx,
2104 bool Is64Bit, int FPDiff, DebugLoc dl) {
2105 // Store the return address to the appropriate stack slot.
2106 if (!FPDiff) return Chain;
2107 // Calculate the new stack slot for the return address.
2108 int SlotSize = Is64Bit ? 8 : 4;
2109 int NewReturnAddrFI =
2110 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2111 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2112 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2113 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2114 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2120 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2121 CallingConv::ID CallConv, bool isVarArg,
2122 bool doesNotRet, bool &isTailCall,
2123 const SmallVectorImpl<ISD::OutputArg> &Outs,
2124 const SmallVectorImpl<SDValue> &OutVals,
2125 const SmallVectorImpl<ISD::InputArg> &Ins,
2126 DebugLoc dl, SelectionDAG &DAG,
2127 SmallVectorImpl<SDValue> &InVals) const {
2128 MachineFunction &MF = DAG.getMachineFunction();
2129 bool Is64Bit = Subtarget->is64Bit();
2130 bool IsWin64 = Subtarget->isTargetWin64();
2131 bool IsWindows = Subtarget->isTargetWindows();
2132 bool IsStructRet = CallIsStructReturn(Outs);
2133 bool IsSibcall = false;
2135 if (MF.getTarget().Options.DisableTailCalls)
2139 // Check if it's really possible to do a tail call.
2140 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2141 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2142 Outs, OutVals, Ins, DAG);
2144 // Sibcalls are automatically detected tailcalls which do not require
2146 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2153 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2154 "Var args not supported with calling convention fastcc or ghc");
2156 // Analyze operands of the call, assigning locations to each operand.
2157 SmallVector<CCValAssign, 16> ArgLocs;
2158 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2159 ArgLocs, *DAG.getContext());
2161 // Allocate shadow area for Win64
2163 CCInfo.AllocateStack(32, 8);
2166 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2168 // Get a count of how many bytes are to be pushed on the stack.
2169 unsigned NumBytes = CCInfo.getNextStackOffset();
2171 // This is a sibcall. The memory operands are available in caller's
2172 // own caller's stack.
2174 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2175 IsTailCallConvention(CallConv))
2176 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2179 if (isTailCall && !IsSibcall) {
2180 // Lower arguments at fp - stackoffset + fpdiff.
2181 unsigned NumBytesCallerPushed =
2182 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2183 FPDiff = NumBytesCallerPushed - NumBytes;
2185 // Set the delta of movement of the returnaddr stackslot.
2186 // But only set if delta is greater than previous delta.
2187 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2188 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2192 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2194 SDValue RetAddrFrIdx;
2195 // Load return address for tail calls.
2196 if (isTailCall && FPDiff)
2197 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2198 Is64Bit, FPDiff, dl);
2200 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2201 SmallVector<SDValue, 8> MemOpChains;
2204 // Walk the register/memloc assignments, inserting copies/loads. In the case
2205 // of tail call optimization arguments are handle later.
2206 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2207 CCValAssign &VA = ArgLocs[i];
2208 EVT RegVT = VA.getLocVT();
2209 SDValue Arg = OutVals[i];
2210 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2211 bool isByVal = Flags.isByVal();
2213 // Promote the value if needed.
2214 switch (VA.getLocInfo()) {
2215 default: llvm_unreachable("Unknown loc info!");
2216 case CCValAssign::Full: break;
2217 case CCValAssign::SExt:
2218 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2220 case CCValAssign::ZExt:
2221 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2223 case CCValAssign::AExt:
2224 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2225 // Special case: passing MMX values in XMM registers.
2226 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2227 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2228 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2230 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2232 case CCValAssign::BCvt:
2233 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2235 case CCValAssign::Indirect: {
2236 // Store the argument.
2237 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2238 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2239 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2240 MachinePointerInfo::getFixedStack(FI),
2247 if (VA.isRegLoc()) {
2248 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2249 if (isVarArg && IsWin64) {
2250 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2251 // shadow reg if callee is a varargs function.
2252 unsigned ShadowReg = 0;
2253 switch (VA.getLocReg()) {
2254 case X86::XMM0: ShadowReg = X86::RCX; break;
2255 case X86::XMM1: ShadowReg = X86::RDX; break;
2256 case X86::XMM2: ShadowReg = X86::R8; break;
2257 case X86::XMM3: ShadowReg = X86::R9; break;
2260 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2262 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2263 assert(VA.isMemLoc());
2264 if (StackPtr.getNode() == 0)
2265 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2266 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2267 dl, DAG, VA, Flags));
2271 if (!MemOpChains.empty())
2272 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2273 &MemOpChains[0], MemOpChains.size());
2275 // Build a sequence of copy-to-reg nodes chained together with token chain
2276 // and flag operands which copy the outgoing args into registers.
2278 // Tail call byval lowering might overwrite argument registers so in case of
2279 // tail call optimization the copies to registers are lowered later.
2281 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2282 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2283 RegsToPass[i].second, InFlag);
2284 InFlag = Chain.getValue(1);
2287 if (Subtarget->isPICStyleGOT()) {
2288 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2291 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2292 DAG.getNode(X86ISD::GlobalBaseReg,
2293 DebugLoc(), getPointerTy()),
2295 InFlag = Chain.getValue(1);
2297 // If we are tail calling and generating PIC/GOT style code load the
2298 // address of the callee into ECX. The value in ecx is used as target of
2299 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2300 // for tail calls on PIC/GOT architectures. Normally we would just put the
2301 // address of GOT into ebx and then call target@PLT. But for tail calls
2302 // ebx would be restored (since ebx is callee saved) before jumping to the
2305 // Note: The actual moving to ECX is done further down.
2306 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2307 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2308 !G->getGlobal()->hasProtectedVisibility())
2309 Callee = LowerGlobalAddress(Callee, DAG);
2310 else if (isa<ExternalSymbolSDNode>(Callee))
2311 Callee = LowerExternalSymbol(Callee, DAG);
2315 if (Is64Bit && isVarArg && !IsWin64) {
2316 // From AMD64 ABI document:
2317 // For calls that may call functions that use varargs or stdargs
2318 // (prototype-less calls or calls to functions containing ellipsis (...) in
2319 // the declaration) %al is used as hidden argument to specify the number
2320 // of SSE registers used. The contents of %al do not need to match exactly
2321 // the number of registers, but must be an ubound on the number of SSE
2322 // registers used and is in the range 0 - 8 inclusive.
2324 // Count the number of XMM registers allocated.
2325 static const unsigned XMMArgRegs[] = {
2326 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2327 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2329 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2330 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2331 && "SSE registers cannot be used when SSE is disabled");
2333 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2334 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2335 InFlag = Chain.getValue(1);
2339 // For tail calls lower the arguments to the 'real' stack slot.
2341 // Force all the incoming stack arguments to be loaded from the stack
2342 // before any new outgoing arguments are stored to the stack, because the
2343 // outgoing stack slots may alias the incoming argument stack slots, and
2344 // the alias isn't otherwise explicit. This is slightly more conservative
2345 // than necessary, because it means that each store effectively depends
2346 // on every argument instead of just those arguments it would clobber.
2347 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2349 SmallVector<SDValue, 8> MemOpChains2;
2352 // Do not flag preceding copytoreg stuff together with the following stuff.
2354 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2355 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2356 CCValAssign &VA = ArgLocs[i];
2359 assert(VA.isMemLoc());
2360 SDValue Arg = OutVals[i];
2361 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2362 // Create frame index.
2363 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2364 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2365 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2366 FIN = DAG.getFrameIndex(FI, getPointerTy());
2368 if (Flags.isByVal()) {
2369 // Copy relative to framepointer.
2370 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2371 if (StackPtr.getNode() == 0)
2372 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2374 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2376 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2380 // Store relative to framepointer.
2381 MemOpChains2.push_back(
2382 DAG.getStore(ArgChain, dl, Arg, FIN,
2383 MachinePointerInfo::getFixedStack(FI),
2389 if (!MemOpChains2.empty())
2390 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2391 &MemOpChains2[0], MemOpChains2.size());
2393 // Copy arguments to their registers.
2394 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2395 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2396 RegsToPass[i].second, InFlag);
2397 InFlag = Chain.getValue(1);
2401 // Store the return address to the appropriate stack slot.
2402 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2406 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2407 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2408 // In the 64-bit large code model, we have to make all calls
2409 // through a register, since the call instruction's 32-bit
2410 // pc-relative offset may not be large enough to hold the whole
2412 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2413 // If the callee is a GlobalAddress node (quite common, every direct call
2414 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2417 // We should use extra load for direct calls to dllimported functions in
2419 const GlobalValue *GV = G->getGlobal();
2420 if (!GV->hasDLLImportLinkage()) {
2421 unsigned char OpFlags = 0;
2422 bool ExtraLoad = false;
2423 unsigned WrapperKind = ISD::DELETED_NODE;
2425 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2426 // external symbols most go through the PLT in PIC mode. If the symbol
2427 // has hidden or protected visibility, or if it is static or local, then
2428 // we don't need to use the PLT - we can directly call it.
2429 if (Subtarget->isTargetELF() &&
2430 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2431 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2432 OpFlags = X86II::MO_PLT;
2433 } else if (Subtarget->isPICStyleStubAny() &&
2434 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2435 (!Subtarget->getTargetTriple().isMacOSX() ||
2436 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2437 // PC-relative references to external symbols should go through $stub,
2438 // unless we're building with the leopard linker or later, which
2439 // automatically synthesizes these stubs.
2440 OpFlags = X86II::MO_DARWIN_STUB;
2441 } else if (Subtarget->isPICStyleRIPRel() &&
2442 isa<Function>(GV) &&
2443 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2444 // If the function is marked as non-lazy, generate an indirect call
2445 // which loads from the GOT directly. This avoids runtime overhead
2446 // at the cost of eager binding (and one extra byte of encoding).
2447 OpFlags = X86II::MO_GOTPCREL;
2448 WrapperKind = X86ISD::WrapperRIP;
2452 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2453 G->getOffset(), OpFlags);
2455 // Add a wrapper if needed.
2456 if (WrapperKind != ISD::DELETED_NODE)
2457 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2458 // Add extra indirection if needed.
2460 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2461 MachinePointerInfo::getGOT(),
2462 false, false, false, 0);
2464 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2465 unsigned char OpFlags = 0;
2467 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2468 // external symbols should go through the PLT.
2469 if (Subtarget->isTargetELF() &&
2470 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2471 OpFlags = X86II::MO_PLT;
2472 } else if (Subtarget->isPICStyleStubAny() &&
2473 (!Subtarget->getTargetTriple().isMacOSX() ||
2474 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2475 // PC-relative references to external symbols should go through $stub,
2476 // unless we're building with the leopard linker or later, which
2477 // automatically synthesizes these stubs.
2478 OpFlags = X86II::MO_DARWIN_STUB;
2481 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2485 // Returns a chain & a flag for retval copy to use.
2486 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2487 SmallVector<SDValue, 8> Ops;
2489 if (!IsSibcall && isTailCall) {
2490 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2491 DAG.getIntPtrConstant(0, true), InFlag);
2492 InFlag = Chain.getValue(1);
2495 Ops.push_back(Chain);
2496 Ops.push_back(Callee);
2499 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2501 // Add argument registers to the end of the list so that they are known live
2503 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2504 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2505 RegsToPass[i].second.getValueType()));
2507 // Add an implicit use GOT pointer in EBX.
2508 if (!isTailCall && Subtarget->isPICStyleGOT())
2509 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2511 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2512 if (Is64Bit && isVarArg && !IsWin64)
2513 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2515 // Add a register mask operand representing the call-preserved registers.
2516 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2517 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2518 assert(Mask && "Missing call preserved mask for calling convention");
2519 Ops.push_back(DAG.getRegisterMask(Mask));
2521 if (InFlag.getNode())
2522 Ops.push_back(InFlag);
2526 //// If this is the first return lowered for this function, add the regs
2527 //// to the liveout set for the function.
2528 // This isn't right, although it's probably harmless on x86; liveouts
2529 // should be computed from returns not tail calls. Consider a void
2530 // function making a tail call to a function returning int.
2531 return DAG.getNode(X86ISD::TC_RETURN, dl,
2532 NodeTys, &Ops[0], Ops.size());
2535 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2536 InFlag = Chain.getValue(1);
2538 // Create the CALLSEQ_END node.
2539 unsigned NumBytesForCalleeToPush;
2540 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2541 getTargetMachine().Options.GuaranteedTailCallOpt))
2542 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2543 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2545 // If this is a call to a struct-return function, the callee
2546 // pops the hidden struct pointer, so we have to push it back.
2547 // This is common for Darwin/X86, Linux & Mingw32 targets.
2548 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2549 NumBytesForCalleeToPush = 4;
2551 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2553 // Returns a flag for retval copy to use.
2555 Chain = DAG.getCALLSEQ_END(Chain,
2556 DAG.getIntPtrConstant(NumBytes, true),
2557 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2560 InFlag = Chain.getValue(1);
2563 // Handle result values, copying them out of physregs into vregs that we
2565 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2566 Ins, dl, DAG, InVals);
2570 //===----------------------------------------------------------------------===//
2571 // Fast Calling Convention (tail call) implementation
2572 //===----------------------------------------------------------------------===//
2574 // Like std call, callee cleans arguments, convention except that ECX is
2575 // reserved for storing the tail called function address. Only 2 registers are
2576 // free for argument passing (inreg). Tail call optimization is performed
2578 // * tailcallopt is enabled
2579 // * caller/callee are fastcc
2580 // On X86_64 architecture with GOT-style position independent code only local
2581 // (within module) calls are supported at the moment.
2582 // To keep the stack aligned according to platform abi the function
2583 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2584 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2585 // If a tail called function callee has more arguments than the caller the
2586 // caller needs to make sure that there is room to move the RETADDR to. This is
2587 // achieved by reserving an area the size of the argument delta right after the
2588 // original REtADDR, but before the saved framepointer or the spilled registers
2589 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2601 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2602 /// for a 16 byte align requirement.
2604 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2605 SelectionDAG& DAG) const {
2606 MachineFunction &MF = DAG.getMachineFunction();
2607 const TargetMachine &TM = MF.getTarget();
2608 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2609 unsigned StackAlignment = TFI.getStackAlignment();
2610 uint64_t AlignMask = StackAlignment - 1;
2611 int64_t Offset = StackSize;
2612 uint64_t SlotSize = TD->getPointerSize();
2613 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2614 // Number smaller than 12 so just add the difference.
2615 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2617 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2618 Offset = ((~AlignMask) & Offset) + StackAlignment +
2619 (StackAlignment-SlotSize);
2624 /// MatchingStackOffset - Return true if the given stack call argument is
2625 /// already available in the same position (relatively) of the caller's
2626 /// incoming argument stack.
2628 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2629 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2630 const X86InstrInfo *TII) {
2631 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2633 if (Arg.getOpcode() == ISD::CopyFromReg) {
2634 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2635 if (!TargetRegisterInfo::isVirtualRegister(VR))
2637 MachineInstr *Def = MRI->getVRegDef(VR);
2640 if (!Flags.isByVal()) {
2641 if (!TII->isLoadFromStackSlot(Def, FI))
2644 unsigned Opcode = Def->getOpcode();
2645 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2646 Def->getOperand(1).isFI()) {
2647 FI = Def->getOperand(1).getIndex();
2648 Bytes = Flags.getByValSize();
2652 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2653 if (Flags.isByVal())
2654 // ByVal argument is passed in as a pointer but it's now being
2655 // dereferenced. e.g.
2656 // define @foo(%struct.X* %A) {
2657 // tail call @bar(%struct.X* byval %A)
2660 SDValue Ptr = Ld->getBasePtr();
2661 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2664 FI = FINode->getIndex();
2665 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2666 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2667 FI = FINode->getIndex();
2668 Bytes = Flags.getByValSize();
2672 assert(FI != INT_MAX);
2673 if (!MFI->isFixedObjectIndex(FI))
2675 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2678 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2679 /// for tail call optimization. Targets which want to do tail call
2680 /// optimization should implement this function.
2682 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2683 CallingConv::ID CalleeCC,
2685 bool isCalleeStructRet,
2686 bool isCallerStructRet,
2687 const SmallVectorImpl<ISD::OutputArg> &Outs,
2688 const SmallVectorImpl<SDValue> &OutVals,
2689 const SmallVectorImpl<ISD::InputArg> &Ins,
2690 SelectionDAG& DAG) const {
2691 if (!IsTailCallConvention(CalleeCC) &&
2692 CalleeCC != CallingConv::C)
2695 // If -tailcallopt is specified, make fastcc functions tail-callable.
2696 const MachineFunction &MF = DAG.getMachineFunction();
2697 const Function *CallerF = DAG.getMachineFunction().getFunction();
2698 CallingConv::ID CallerCC = CallerF->getCallingConv();
2699 bool CCMatch = CallerCC == CalleeCC;
2701 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2702 if (IsTailCallConvention(CalleeCC) && CCMatch)
2707 // Look for obvious safe cases to perform tail call optimization that do not
2708 // require ABI changes. This is what gcc calls sibcall.
2710 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2711 // emit a special epilogue.
2712 if (RegInfo->needsStackRealignment(MF))
2715 // Also avoid sibcall optimization if either caller or callee uses struct
2716 // return semantics.
2717 if (isCalleeStructRet || isCallerStructRet)
2720 // An stdcall caller is expected to clean up its arguments; the callee
2721 // isn't going to do that.
2722 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2725 // Do not sibcall optimize vararg calls unless all arguments are passed via
2727 if (isVarArg && !Outs.empty()) {
2729 // Optimizing for varargs on Win64 is unlikely to be safe without
2730 // additional testing.
2731 if (Subtarget->isTargetWin64())
2734 SmallVector<CCValAssign, 16> ArgLocs;
2735 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2736 getTargetMachine(), ArgLocs, *DAG.getContext());
2738 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2739 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2740 if (!ArgLocs[i].isRegLoc())
2744 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2745 // stack. Therefore, if it's not used by the call it is not safe to optimize
2746 // this into a sibcall.
2747 bool Unused = false;
2748 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2755 SmallVector<CCValAssign, 16> RVLocs;
2756 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2757 getTargetMachine(), RVLocs, *DAG.getContext());
2758 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2759 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2760 CCValAssign &VA = RVLocs[i];
2761 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2766 // If the calling conventions do not match, then we'd better make sure the
2767 // results are returned in the same way as what the caller expects.
2769 SmallVector<CCValAssign, 16> RVLocs1;
2770 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2771 getTargetMachine(), RVLocs1, *DAG.getContext());
2772 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2774 SmallVector<CCValAssign, 16> RVLocs2;
2775 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2776 getTargetMachine(), RVLocs2, *DAG.getContext());
2777 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2779 if (RVLocs1.size() != RVLocs2.size())
2781 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2782 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2784 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2786 if (RVLocs1[i].isRegLoc()) {
2787 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2790 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2796 // If the callee takes no arguments then go on to check the results of the
2798 if (!Outs.empty()) {
2799 // Check if stack adjustment is needed. For now, do not do this if any
2800 // argument is passed on the stack.
2801 SmallVector<CCValAssign, 16> ArgLocs;
2802 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2803 getTargetMachine(), ArgLocs, *DAG.getContext());
2805 // Allocate shadow area for Win64
2806 if (Subtarget->isTargetWin64()) {
2807 CCInfo.AllocateStack(32, 8);
2810 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2811 if (CCInfo.getNextStackOffset()) {
2812 MachineFunction &MF = DAG.getMachineFunction();
2813 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2816 // Check if the arguments are already laid out in the right way as
2817 // the caller's fixed stack objects.
2818 MachineFrameInfo *MFI = MF.getFrameInfo();
2819 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2820 const X86InstrInfo *TII =
2821 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2822 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2823 CCValAssign &VA = ArgLocs[i];
2824 SDValue Arg = OutVals[i];
2825 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2826 if (VA.getLocInfo() == CCValAssign::Indirect)
2828 if (!VA.isRegLoc()) {
2829 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2836 // If the tailcall address may be in a register, then make sure it's
2837 // possible to register allocate for it. In 32-bit, the call address can
2838 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2839 // callee-saved registers are restored. These happen to be the same
2840 // registers used to pass 'inreg' arguments so watch out for those.
2841 if (!Subtarget->is64Bit() &&
2842 !isa<GlobalAddressSDNode>(Callee) &&
2843 !isa<ExternalSymbolSDNode>(Callee)) {
2844 unsigned NumInRegs = 0;
2845 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2846 CCValAssign &VA = ArgLocs[i];
2849 unsigned Reg = VA.getLocReg();
2852 case X86::EAX: case X86::EDX: case X86::ECX:
2853 if (++NumInRegs == 3)
2865 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2866 return X86::createFastISel(funcInfo);
2870 //===----------------------------------------------------------------------===//
2871 // Other Lowering Hooks
2872 //===----------------------------------------------------------------------===//
2874 static bool MayFoldLoad(SDValue Op) {
2875 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2878 static bool MayFoldIntoStore(SDValue Op) {
2879 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2882 static bool isTargetShuffle(unsigned Opcode) {
2884 default: return false;
2885 case X86ISD::PSHUFD:
2886 case X86ISD::PSHUFHW:
2887 case X86ISD::PSHUFLW:
2889 case X86ISD::PALIGN:
2890 case X86ISD::MOVLHPS:
2891 case X86ISD::MOVLHPD:
2892 case X86ISD::MOVHLPS:
2893 case X86ISD::MOVLPS:
2894 case X86ISD::MOVLPD:
2895 case X86ISD::MOVSHDUP:
2896 case X86ISD::MOVSLDUP:
2897 case X86ISD::MOVDDUP:
2900 case X86ISD::UNPCKL:
2901 case X86ISD::UNPCKH:
2902 case X86ISD::VPERMILP:
2903 case X86ISD::VPERM2X128:
2908 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2909 SDValue V1, SelectionDAG &DAG) {
2911 default: llvm_unreachable("Unknown x86 shuffle node");
2912 case X86ISD::MOVSHDUP:
2913 case X86ISD::MOVSLDUP:
2914 case X86ISD::MOVDDUP:
2915 return DAG.getNode(Opc, dl, VT, V1);
2919 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2920 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2922 default: llvm_unreachable("Unknown x86 shuffle node");
2923 case X86ISD::PSHUFD:
2924 case X86ISD::PSHUFHW:
2925 case X86ISD::PSHUFLW:
2926 case X86ISD::VPERMILP:
2927 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2931 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2932 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2934 default: llvm_unreachable("Unknown x86 shuffle node");
2935 case X86ISD::PALIGN:
2937 case X86ISD::VPERM2X128:
2938 return DAG.getNode(Opc, dl, VT, V1, V2,
2939 DAG.getConstant(TargetMask, MVT::i8));
2943 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2944 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2946 default: llvm_unreachable("Unknown x86 shuffle node");
2947 case X86ISD::MOVLHPS:
2948 case X86ISD::MOVLHPD:
2949 case X86ISD::MOVHLPS:
2950 case X86ISD::MOVLPS:
2951 case X86ISD::MOVLPD:
2954 case X86ISD::UNPCKL:
2955 case X86ISD::UNPCKH:
2956 return DAG.getNode(Opc, dl, VT, V1, V2);
2960 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2961 MachineFunction &MF = DAG.getMachineFunction();
2962 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2963 int ReturnAddrIndex = FuncInfo->getRAIndex();
2965 if (ReturnAddrIndex == 0) {
2966 // Set up a frame object for the return address.
2967 uint64_t SlotSize = TD->getPointerSize();
2968 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2970 FuncInfo->setRAIndex(ReturnAddrIndex);
2973 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2977 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2978 bool hasSymbolicDisplacement) {
2979 // Offset should fit into 32 bit immediate field.
2980 if (!isInt<32>(Offset))
2983 // If we don't have a symbolic displacement - we don't have any extra
2985 if (!hasSymbolicDisplacement)
2988 // FIXME: Some tweaks might be needed for medium code model.
2989 if (M != CodeModel::Small && M != CodeModel::Kernel)
2992 // For small code model we assume that latest object is 16MB before end of 31
2993 // bits boundary. We may also accept pretty large negative constants knowing
2994 // that all objects are in the positive half of address space.
2995 if (M == CodeModel::Small && Offset < 16*1024*1024)
2998 // For kernel code model we know that all object resist in the negative half
2999 // of 32bits address space. We may not accept negative offsets, since they may
3000 // be just off and we may accept pretty large positive ones.
3001 if (M == CodeModel::Kernel && Offset > 0)
3007 /// isCalleePop - Determines whether the callee is required to pop its
3008 /// own arguments. Callee pop is necessary to support tail calls.
3009 bool X86::isCalleePop(CallingConv::ID CallingConv,
3010 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3014 switch (CallingConv) {
3017 case CallingConv::X86_StdCall:
3019 case CallingConv::X86_FastCall:
3021 case CallingConv::X86_ThisCall:
3023 case CallingConv::Fast:
3025 case CallingConv::GHC:
3030 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3031 /// specific condition code, returning the condition code and the LHS/RHS of the
3032 /// comparison to make.
3033 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3034 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3036 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3037 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3038 // X > -1 -> X == 0, jump !sign.
3039 RHS = DAG.getConstant(0, RHS.getValueType());
3040 return X86::COND_NS;
3041 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3042 // X < 0 -> X == 0, jump on sign.
3044 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3046 RHS = DAG.getConstant(0, RHS.getValueType());
3047 return X86::COND_LE;
3051 switch (SetCCOpcode) {
3052 default: llvm_unreachable("Invalid integer condition!");
3053 case ISD::SETEQ: return X86::COND_E;
3054 case ISD::SETGT: return X86::COND_G;
3055 case ISD::SETGE: return X86::COND_GE;
3056 case ISD::SETLT: return X86::COND_L;
3057 case ISD::SETLE: return X86::COND_LE;
3058 case ISD::SETNE: return X86::COND_NE;
3059 case ISD::SETULT: return X86::COND_B;
3060 case ISD::SETUGT: return X86::COND_A;
3061 case ISD::SETULE: return X86::COND_BE;
3062 case ISD::SETUGE: return X86::COND_AE;
3066 // First determine if it is required or is profitable to flip the operands.
3068 // If LHS is a foldable load, but RHS is not, flip the condition.
3069 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3070 !ISD::isNON_EXTLoad(RHS.getNode())) {
3071 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3072 std::swap(LHS, RHS);
3075 switch (SetCCOpcode) {
3081 std::swap(LHS, RHS);
3085 // On a floating point condition, the flags are set as follows:
3087 // 0 | 0 | 0 | X > Y
3088 // 0 | 0 | 1 | X < Y
3089 // 1 | 0 | 0 | X == Y
3090 // 1 | 1 | 1 | unordered
3091 switch (SetCCOpcode) {
3092 default: llvm_unreachable("Condcode should be pre-legalized away");
3094 case ISD::SETEQ: return X86::COND_E;
3095 case ISD::SETOLT: // flipped
3097 case ISD::SETGT: return X86::COND_A;
3098 case ISD::SETOLE: // flipped
3100 case ISD::SETGE: return X86::COND_AE;
3101 case ISD::SETUGT: // flipped
3103 case ISD::SETLT: return X86::COND_B;
3104 case ISD::SETUGE: // flipped
3106 case ISD::SETLE: return X86::COND_BE;
3108 case ISD::SETNE: return X86::COND_NE;
3109 case ISD::SETUO: return X86::COND_P;
3110 case ISD::SETO: return X86::COND_NP;
3112 case ISD::SETUNE: return X86::COND_INVALID;
3116 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3117 /// code. Current x86 isa includes the following FP cmov instructions:
3118 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3119 static bool hasFPCMov(unsigned X86CC) {
3135 /// isFPImmLegal - Returns true if the target can instruction select the
3136 /// specified FP immediate natively. If false, the legalizer will
3137 /// materialize the FP immediate as a load from a constant pool.
3138 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3139 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3140 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3146 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3147 /// the specified range (L, H].
3148 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3149 return (Val < 0) || (Val >= Low && Val < Hi);
3152 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3153 /// specified value.
3154 static bool isUndefOrEqual(int Val, int CmpVal) {
3155 if (Val < 0 || Val == CmpVal)
3160 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3161 /// from position Pos and ending in Pos+Size, falls within the specified
3162 /// sequential range (L, L+Pos]. or is undef.
3163 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3164 int Pos, int Size, int Low) {
3165 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3166 if (!isUndefOrEqual(Mask[i], Low))
3171 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3172 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3173 /// the second operand.
3174 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3175 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3176 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3177 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3178 return (Mask[0] < 2 && Mask[1] < 2);
3182 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3183 /// is suitable for input to PSHUFHW.
3184 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT) {
3185 if (VT != MVT::v8i16)
3188 // Lower quadword copied in order or undef.
3189 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3192 // Upper quadword shuffled.
3193 for (unsigned i = 4; i != 8; ++i)
3194 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3200 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3201 /// is suitable for input to PSHUFLW.
3202 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT) {
3203 if (VT != MVT::v8i16)
3206 // Upper quadword copied in order.
3207 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3210 // Lower quadword shuffled.
3211 for (unsigned i = 0; i != 4; ++i)
3218 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3219 /// is suitable for input to PALIGNR.
3220 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3221 const X86Subtarget *Subtarget) {
3222 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3223 (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
3226 unsigned NumElts = VT.getVectorNumElements();
3227 unsigned NumLanes = VT.getSizeInBits()/128;
3228 unsigned NumLaneElts = NumElts/NumLanes;
3230 // Do not handle 64-bit element shuffles with palignr.
3231 if (NumLaneElts == 2)
3234 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3236 for (i = 0; i != NumLaneElts; ++i) {
3241 // Lane is all undef, go to next lane
3242 if (i == NumLaneElts)
3245 int Start = Mask[i+l];
3247 // Make sure its in this lane in one of the sources
3248 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3249 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3252 // If not lane 0, then we must match lane 0
3253 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3256 // Correct second source to be contiguous with first source
3257 if (Start >= (int)NumElts)
3258 Start -= NumElts - NumLaneElts;
3260 // Make sure we're shifting in the right direction.
3261 if (Start <= (int)(i+l))
3266 // Check the rest of the elements to see if they are consecutive.
3267 for (++i; i != NumLaneElts; ++i) {
3268 int Idx = Mask[i+l];
3270 // Make sure its in this lane
3271 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3272 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3275 // If not lane 0, then we must match lane 0
3276 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3279 if (Idx >= (int)NumElts)
3280 Idx -= NumElts - NumLaneElts;
3282 if (!isUndefOrEqual(Idx, Start+i))
3291 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3292 /// the two vector operands have swapped position.
3293 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3294 unsigned NumElems) {
3295 for (unsigned i = 0; i != NumElems; ++i) {
3299 else if (idx < (int)NumElems)
3300 Mask[i] = idx + NumElems;
3302 Mask[i] = idx - NumElems;
3306 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3307 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3308 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3309 /// reverse of what x86 shuffles want.
3310 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX,
3311 bool Commuted = false) {
3312 if (!HasAVX && VT.getSizeInBits() == 256)
3315 unsigned NumElems = VT.getVectorNumElements();
3316 unsigned NumLanes = VT.getSizeInBits()/128;
3317 unsigned NumLaneElems = NumElems/NumLanes;
3319 if (NumLaneElems != 2 && NumLaneElems != 4)
3322 // VSHUFPSY divides the resulting vector into 4 chunks.
3323 // The sources are also splitted into 4 chunks, and each destination
3324 // chunk must come from a different source chunk.
3326 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3327 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3329 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3330 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3332 // VSHUFPDY divides the resulting vector into 4 chunks.
3333 // The sources are also splitted into 4 chunks, and each destination
3334 // chunk must come from a different source chunk.
3336 // SRC1 => X3 X2 X1 X0
3337 // SRC2 => Y3 Y2 Y1 Y0
3339 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3341 unsigned HalfLaneElems = NumLaneElems/2;
3342 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3343 for (unsigned i = 0; i != NumLaneElems; ++i) {
3344 int Idx = Mask[i+l];
3345 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3346 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3348 // For VSHUFPSY, the mask of the second half must be the same as the
3349 // first but with the appropriate offsets. This works in the same way as
3350 // VPERMILPS works with masks.
3351 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3353 if (!isUndefOrEqual(Idx, Mask[i]+l))
3361 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3362 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3363 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3364 unsigned NumElems = VT.getVectorNumElements();
3366 if (VT.getSizeInBits() != 128)
3372 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3373 return isUndefOrEqual(Mask[0], 6) &&
3374 isUndefOrEqual(Mask[1], 7) &&
3375 isUndefOrEqual(Mask[2], 2) &&
3376 isUndefOrEqual(Mask[3], 3);
3379 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3380 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3382 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3383 unsigned NumElems = VT.getVectorNumElements();
3385 if (VT.getSizeInBits() != 128)
3391 return isUndefOrEqual(Mask[0], 2) &&
3392 isUndefOrEqual(Mask[1], 3) &&
3393 isUndefOrEqual(Mask[2], 2) &&
3394 isUndefOrEqual(Mask[3], 3);
3397 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3398 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3399 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3400 if (VT.getSizeInBits() != 128)
3403 unsigned NumElems = VT.getVectorNumElements();
3405 if (NumElems != 2 && NumElems != 4)
3408 for (unsigned i = 0; i != NumElems/2; ++i)
3409 if (!isUndefOrEqual(Mask[i], i + NumElems))
3412 for (unsigned i = NumElems/2; i != NumElems; ++i)
3413 if (!isUndefOrEqual(Mask[i], i))
3419 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3420 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3421 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3422 unsigned NumElems = VT.getVectorNumElements();
3424 if ((NumElems != 2 && NumElems != 4)
3425 || VT.getSizeInBits() > 128)
3428 for (unsigned i = 0; i != NumElems/2; ++i)
3429 if (!isUndefOrEqual(Mask[i], i))
3432 for (unsigned i = 0; i != NumElems/2; ++i)
3433 if (!isUndefOrEqual(Mask[i + NumElems/2], i + NumElems))
3439 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3440 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3441 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3442 bool HasAVX2, bool V2IsSplat = false) {
3443 unsigned NumElts = VT.getVectorNumElements();
3445 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3446 "Unsupported vector type for unpckh");
3448 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3449 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3452 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3453 // independently on 128-bit lanes.
3454 unsigned NumLanes = VT.getSizeInBits()/128;
3455 unsigned NumLaneElts = NumElts/NumLanes;
3457 for (unsigned l = 0; l != NumLanes; ++l) {
3458 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3459 i != (l+1)*NumLaneElts;
3462 int BitI1 = Mask[i+1];
3463 if (!isUndefOrEqual(BitI, j))
3466 if (!isUndefOrEqual(BitI1, NumElts))
3469 if (!isUndefOrEqual(BitI1, j + NumElts))
3478 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3479 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3480 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3481 bool HasAVX2, bool V2IsSplat = false) {
3482 unsigned NumElts = VT.getVectorNumElements();
3484 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3485 "Unsupported vector type for unpckh");
3487 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3488 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3491 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3492 // independently on 128-bit lanes.
3493 unsigned NumLanes = VT.getSizeInBits()/128;
3494 unsigned NumLaneElts = NumElts/NumLanes;
3496 for (unsigned l = 0; l != NumLanes; ++l) {
3497 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3498 i != (l+1)*NumLaneElts; i += 2, ++j) {
3500 int BitI1 = Mask[i+1];
3501 if (!isUndefOrEqual(BitI, j))
3504 if (isUndefOrEqual(BitI1, NumElts))
3507 if (!isUndefOrEqual(BitI1, j+NumElts))
3515 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3516 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3518 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3520 unsigned NumElts = VT.getVectorNumElements();
3522 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3523 "Unsupported vector type for unpckh");
3525 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3526 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3529 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3530 // FIXME: Need a better way to get rid of this, there's no latency difference
3531 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3532 // the former later. We should also remove the "_undef" special mask.
3533 if (NumElts == 4 && VT.getSizeInBits() == 256)
3536 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3537 // independently on 128-bit lanes.
3538 unsigned NumLanes = VT.getSizeInBits()/128;
3539 unsigned NumLaneElts = NumElts/NumLanes;
3541 for (unsigned l = 0; l != NumLanes; ++l) {
3542 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3543 i != (l+1)*NumLaneElts;
3546 int BitI1 = Mask[i+1];
3548 if (!isUndefOrEqual(BitI, j))
3550 if (!isUndefOrEqual(BitI1, j))
3558 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3559 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3561 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX2) {
3562 unsigned NumElts = VT.getVectorNumElements();
3564 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3565 "Unsupported vector type for unpckh");
3567 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3568 (!HasAVX2 || (NumElts != 16 && NumElts != 32)))
3571 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3572 // independently on 128-bit lanes.
3573 unsigned NumLanes = VT.getSizeInBits()/128;
3574 unsigned NumLaneElts = NumElts/NumLanes;
3576 for (unsigned l = 0; l != NumLanes; ++l) {
3577 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3578 i != (l+1)*NumLaneElts; i += 2, ++j) {
3580 int BitI1 = Mask[i+1];
3581 if (!isUndefOrEqual(BitI, j))
3583 if (!isUndefOrEqual(BitI1, j))
3590 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3591 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3592 /// MOVSD, and MOVD, i.e. setting the lowest element.
3593 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3594 if (VT.getVectorElementType().getSizeInBits() < 32)
3596 if (VT.getSizeInBits() == 256)
3599 unsigned NumElts = VT.getVectorNumElements();
3601 if (!isUndefOrEqual(Mask[0], NumElts))
3604 for (unsigned i = 1; i != NumElts; ++i)
3605 if (!isUndefOrEqual(Mask[i], i))
3611 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3612 /// as permutations between 128-bit chunks or halves. As an example: this
3614 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3615 /// The first half comes from the second half of V1 and the second half from the
3616 /// the second half of V2.
3617 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3618 if (!HasAVX || VT.getSizeInBits() != 256)
3621 // The shuffle result is divided into half A and half B. In total the two
3622 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3623 // B must come from C, D, E or F.
3624 unsigned HalfSize = VT.getVectorNumElements()/2;
3625 bool MatchA = false, MatchB = false;
3627 // Check if A comes from one of C, D, E, F.
3628 for (unsigned Half = 0; Half != 4; ++Half) {
3629 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3635 // Check if B comes from one of C, D, E, F.
3636 for (unsigned Half = 0; Half != 4; ++Half) {
3637 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3643 return MatchA && MatchB;
3646 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3647 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3648 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3649 EVT VT = SVOp->getValueType(0);
3651 unsigned HalfSize = VT.getVectorNumElements()/2;
3653 unsigned FstHalf = 0, SndHalf = 0;
3654 for (unsigned i = 0; i < HalfSize; ++i) {
3655 if (SVOp->getMaskElt(i) > 0) {
3656 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3660 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3661 if (SVOp->getMaskElt(i) > 0) {
3662 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3667 return (FstHalf | (SndHalf << 4));
3670 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3671 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3672 /// Note that VPERMIL mask matching is different depending whether theunderlying
3673 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3674 /// to the same elements of the low, but to the higher half of the source.
3675 /// In VPERMILPD the two lanes could be shuffled independently of each other
3676 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3677 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3681 unsigned NumElts = VT.getVectorNumElements();
3682 // Only match 256-bit with 32/64-bit types
3683 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3686 unsigned NumLanes = VT.getSizeInBits()/128;
3687 unsigned LaneSize = NumElts/NumLanes;
3688 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3689 for (unsigned i = 0; i != LaneSize; ++i) {
3690 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3692 if (NumElts != 8 || l == 0)
3694 // VPERMILPS handling
3697 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3705 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3706 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3707 /// element of vector 2 and the other elements to come from vector 1 in order.
3708 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3709 bool V2IsSplat = false, bool V2IsUndef = false) {
3710 unsigned NumOps = VT.getVectorNumElements();
3711 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3714 if (!isUndefOrEqual(Mask[0], 0))
3717 for (unsigned i = 1; i != NumOps; ++i)
3718 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3719 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3720 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3726 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3727 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3728 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3729 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3730 const X86Subtarget *Subtarget) {
3731 if (!Subtarget->hasSSE3())
3734 unsigned NumElems = VT.getVectorNumElements();
3736 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3737 (VT.getSizeInBits() == 256 && NumElems != 8))
3740 // "i+1" is the value the indexed mask element must have
3741 for (unsigned i = 0; i != NumElems; i += 2)
3742 if (!isUndefOrEqual(Mask[i], i+1) ||
3743 !isUndefOrEqual(Mask[i+1], i+1))
3749 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3750 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3751 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3752 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3753 const X86Subtarget *Subtarget) {
3754 if (!Subtarget->hasSSE3())
3757 unsigned NumElems = VT.getVectorNumElements();
3759 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3760 (VT.getSizeInBits() == 256 && NumElems != 8))
3763 // "i" is the value the indexed mask element must have
3764 for (unsigned i = 0; i != NumElems; i += 2)
3765 if (!isUndefOrEqual(Mask[i], i) ||
3766 !isUndefOrEqual(Mask[i+1], i))
3772 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3773 /// specifies a shuffle of elements that is suitable for input to 256-bit
3774 /// version of MOVDDUP.
3775 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasAVX) {
3776 unsigned NumElts = VT.getVectorNumElements();
3778 if (!HasAVX || VT.getSizeInBits() != 256 || NumElts != 4)
3781 for (unsigned i = 0; i != NumElts/2; ++i)
3782 if (!isUndefOrEqual(Mask[i], 0))
3784 for (unsigned i = NumElts/2; i != NumElts; ++i)
3785 if (!isUndefOrEqual(Mask[i], NumElts/2))
3790 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3791 /// specifies a shuffle of elements that is suitable for input to 128-bit
3792 /// version of MOVDDUP.
3793 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3794 if (VT.getSizeInBits() != 128)
3797 unsigned e = VT.getVectorNumElements() / 2;
3798 for (unsigned i = 0; i != e; ++i)
3799 if (!isUndefOrEqual(Mask[i], i))
3801 for (unsigned i = 0; i != e; ++i)
3802 if (!isUndefOrEqual(Mask[e+i], i))
3807 /// isVEXTRACTF128Index - Return true if the specified
3808 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3809 /// suitable for input to VEXTRACTF128.
3810 bool X86::isVEXTRACTF128Index(SDNode *N) {
3811 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3814 // The index should be aligned on a 128-bit boundary.
3816 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3818 unsigned VL = N->getValueType(0).getVectorNumElements();
3819 unsigned VBits = N->getValueType(0).getSizeInBits();
3820 unsigned ElSize = VBits / VL;
3821 bool Result = (Index * ElSize) % 128 == 0;
3826 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
3827 /// operand specifies a subvector insert that is suitable for input to
3829 bool X86::isVINSERTF128Index(SDNode *N) {
3830 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3833 // The index should be aligned on a 128-bit boundary.
3835 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3837 unsigned VL = N->getValueType(0).getVectorNumElements();
3838 unsigned VBits = N->getValueType(0).getSizeInBits();
3839 unsigned ElSize = VBits / VL;
3840 bool Result = (Index * ElSize) % 128 == 0;
3845 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3846 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3847 /// Handles 128-bit and 256-bit.
3848 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
3849 EVT VT = N->getValueType(0);
3851 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3852 "Unsupported vector type for PSHUF/SHUFP");
3854 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
3855 // independently on 128-bit lanes.
3856 unsigned NumElts = VT.getVectorNumElements();
3857 unsigned NumLanes = VT.getSizeInBits()/128;
3858 unsigned NumLaneElts = NumElts/NumLanes;
3860 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
3861 "Only supports 2 or 4 elements per lane");
3863 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
3865 for (unsigned i = 0; i != NumElts; ++i) {
3866 int Elt = N->getMaskElt(i);
3867 if (Elt < 0) continue;
3869 unsigned ShAmt = i << Shift;
3870 if (ShAmt >= 8) ShAmt -= 8;
3871 Mask |= Elt << ShAmt;
3877 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3878 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3879 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
3881 // 8 nodes, but we only care about the last 4.
3882 for (unsigned i = 7; i >= 4; --i) {
3883 int Val = N->getMaskElt(i);
3892 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3893 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3894 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
3896 // 8 nodes, but we only care about the first 4.
3897 for (int i = 3; i >= 0; --i) {
3898 int Val = N->getMaskElt(i);
3907 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3908 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3909 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
3910 EVT VT = SVOp->getValueType(0);
3911 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
3913 unsigned NumElts = VT.getVectorNumElements();
3914 unsigned NumLanes = VT.getSizeInBits()/128;
3915 unsigned NumLaneElts = NumElts/NumLanes;
3919 for (i = 0; i != NumElts; ++i) {
3920 Val = SVOp->getMaskElt(i);
3924 if (Val >= (int)NumElts)
3925 Val -= NumElts - NumLaneElts;
3927 assert(Val - i > 0 && "PALIGNR imm should be positive");
3928 return (Val - i) * EltSize;
3931 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
3932 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3934 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
3935 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3936 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
3939 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3941 EVT VecVT = N->getOperand(0).getValueType();
3942 EVT ElVT = VecVT.getVectorElementType();
3944 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3945 return Index / NumElemsPerChunk;
3948 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
3949 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
3951 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
3952 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3953 llvm_unreachable("Illegal insert subvector for VINSERTF128");
3956 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3958 EVT VecVT = N->getValueType(0);
3959 EVT ElVT = VecVT.getVectorElementType();
3961 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
3962 return Index / NumElemsPerChunk;
3965 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3967 bool X86::isZeroNode(SDValue Elt) {
3968 return ((isa<ConstantSDNode>(Elt) &&
3969 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3970 (isa<ConstantFPSDNode>(Elt) &&
3971 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3974 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3975 /// their permute mask.
3976 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3977 SelectionDAG &DAG) {
3978 EVT VT = SVOp->getValueType(0);
3979 unsigned NumElems = VT.getVectorNumElements();
3980 SmallVector<int, 8> MaskVec;
3982 for (unsigned i = 0; i != NumElems; ++i) {
3983 int idx = SVOp->getMaskElt(i);
3985 MaskVec.push_back(idx);
3986 else if (idx < (int)NumElems)
3987 MaskVec.push_back(idx + NumElems);
3989 MaskVec.push_back(idx - NumElems);
3991 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3992 SVOp->getOperand(0), &MaskVec[0]);
3995 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3996 /// match movhlps. The lower half elements should come from upper half of
3997 /// V1 (and in order), and the upper half elements should come from the upper
3998 /// half of V2 (and in order).
3999 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4000 if (VT.getSizeInBits() != 128)
4002 if (VT.getVectorNumElements() != 4)
4004 for (unsigned i = 0, e = 2; i != e; ++i)
4005 if (!isUndefOrEqual(Mask[i], i+2))
4007 for (unsigned i = 2; i != 4; ++i)
4008 if (!isUndefOrEqual(Mask[i], i+4))
4013 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4014 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4016 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4017 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4019 N = N->getOperand(0).getNode();
4020 if (!ISD::isNON_EXTLoad(N))
4023 *LD = cast<LoadSDNode>(N);
4027 // Test whether the given value is a vector value which will be legalized
4029 static bool WillBeConstantPoolLoad(SDNode *N) {
4030 if (N->getOpcode() != ISD::BUILD_VECTOR)
4033 // Check for any non-constant elements.
4034 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4035 switch (N->getOperand(i).getNode()->getOpcode()) {
4037 case ISD::ConstantFP:
4044 // Vectors of all-zeros and all-ones are materialized with special
4045 // instructions rather than being loaded.
4046 return !ISD::isBuildVectorAllZeros(N) &&
4047 !ISD::isBuildVectorAllOnes(N);
4050 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4051 /// match movlp{s|d}. The lower half elements should come from lower half of
4052 /// V1 (and in order), and the upper half elements should come from the upper
4053 /// half of V2 (and in order). And since V1 will become the source of the
4054 /// MOVLP, it must be either a vector load or a scalar load to vector.
4055 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4056 ArrayRef<int> Mask, EVT VT) {
4057 if (VT.getSizeInBits() != 128)
4060 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4062 // Is V2 is a vector load, don't do this transformation. We will try to use
4063 // load folding shufps op.
4064 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4067 unsigned NumElems = VT.getVectorNumElements();
4069 if (NumElems != 2 && NumElems != 4)
4071 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4072 if (!isUndefOrEqual(Mask[i], i))
4074 for (unsigned i = NumElems/2; i != NumElems; ++i)
4075 if (!isUndefOrEqual(Mask[i], i+NumElems))
4080 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4082 static bool isSplatVector(SDNode *N) {
4083 if (N->getOpcode() != ISD::BUILD_VECTOR)
4086 SDValue SplatValue = N->getOperand(0);
4087 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4088 if (N->getOperand(i) != SplatValue)
4093 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4094 /// to an zero vector.
4095 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4096 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4097 SDValue V1 = N->getOperand(0);
4098 SDValue V2 = N->getOperand(1);
4099 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4100 for (unsigned i = 0; i != NumElems; ++i) {
4101 int Idx = N->getMaskElt(i);
4102 if (Idx >= (int)NumElems) {
4103 unsigned Opc = V2.getOpcode();
4104 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4106 if (Opc != ISD::BUILD_VECTOR ||
4107 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4109 } else if (Idx >= 0) {
4110 unsigned Opc = V1.getOpcode();
4111 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4113 if (Opc != ISD::BUILD_VECTOR ||
4114 !X86::isZeroNode(V1.getOperand(Idx)))
4121 /// getZeroVector - Returns a vector of specified type with all zero elements.
4123 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4124 SelectionDAG &DAG, DebugLoc dl) {
4125 assert(VT.isVector() && "Expected a vector type");
4127 // Always build SSE zero vectors as <4 x i32> bitcasted
4128 // to their dest type. This ensures they get CSE'd.
4130 if (VT.getSizeInBits() == 128) { // SSE
4131 if (Subtarget->hasSSE2()) { // SSE2
4132 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4133 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4135 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4136 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4138 } else if (VT.getSizeInBits() == 256) { // AVX
4139 if (Subtarget->hasAVX2()) { // AVX2
4140 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4141 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4142 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4144 // 256-bit logic and arithmetic instructions in AVX are all
4145 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4146 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4147 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4148 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4151 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4154 /// getOnesVector - Returns a vector of specified type with all bits set.
4155 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4156 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4157 /// Then bitcast to their original type, ensuring they get CSE'd.
4158 static SDValue getOnesVector(EVT VT, bool HasAVX2, SelectionDAG &DAG,
4160 assert(VT.isVector() && "Expected a vector type");
4161 assert((VT.is128BitVector() || VT.is256BitVector())
4162 && "Expected a 128-bit or 256-bit vector type");
4164 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4166 if (VT.getSizeInBits() == 256) {
4167 if (HasAVX2) { // AVX2
4168 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4169 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4171 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4172 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4173 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4174 Vec = Insert128BitVector(InsV, Vec,
4175 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4178 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4181 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4184 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4185 /// that point to V2 points to its first element.
4186 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4187 for (unsigned i = 0; i != NumElems; ++i) {
4188 if (Mask[i] > (int)NumElems) {
4194 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4195 /// operation of specified width.
4196 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4198 unsigned NumElems = VT.getVectorNumElements();
4199 SmallVector<int, 8> Mask;
4200 Mask.push_back(NumElems);
4201 for (unsigned i = 1; i != NumElems; ++i)
4203 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4206 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4207 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4209 unsigned NumElems = VT.getVectorNumElements();
4210 SmallVector<int, 8> Mask;
4211 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4213 Mask.push_back(i + NumElems);
4215 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4218 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4219 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4221 unsigned NumElems = VT.getVectorNumElements();
4222 unsigned Half = NumElems/2;
4223 SmallVector<int, 8> Mask;
4224 for (unsigned i = 0; i != Half; ++i) {
4225 Mask.push_back(i + Half);
4226 Mask.push_back(i + NumElems + Half);
4228 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4231 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4232 // a generic shuffle instruction because the target has no such instructions.
4233 // Generate shuffles which repeat i16 and i8 several times until they can be
4234 // represented by v4f32 and then be manipulated by target suported shuffles.
4235 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4236 EVT VT = V.getValueType();
4237 int NumElems = VT.getVectorNumElements();
4238 DebugLoc dl = V.getDebugLoc();
4240 while (NumElems > 4) {
4241 if (EltNo < NumElems/2) {
4242 V = getUnpackl(DAG, dl, VT, V, V);
4244 V = getUnpackh(DAG, dl, VT, V, V);
4245 EltNo -= NumElems/2;
4252 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4253 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4254 EVT VT = V.getValueType();
4255 DebugLoc dl = V.getDebugLoc();
4256 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4257 && "Vector size not supported");
4259 if (VT.getSizeInBits() == 128) {
4260 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4261 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4262 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4265 // To use VPERMILPS to splat scalars, the second half of indicies must
4266 // refer to the higher part, which is a duplication of the lower one,
4267 // because VPERMILPS can only handle in-lane permutations.
4268 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4269 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4271 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4272 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4276 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4279 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4280 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4281 EVT SrcVT = SV->getValueType(0);
4282 SDValue V1 = SV->getOperand(0);
4283 DebugLoc dl = SV->getDebugLoc();
4285 int EltNo = SV->getSplatIndex();
4286 int NumElems = SrcVT.getVectorNumElements();
4287 unsigned Size = SrcVT.getSizeInBits();
4289 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4290 "Unknown how to promote splat for type");
4292 // Extract the 128-bit part containing the splat element and update
4293 // the splat element index when it refers to the higher register.
4295 unsigned Idx = (EltNo >= NumElems/2) ? NumElems/2 : 0;
4296 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4298 EltNo -= NumElems/2;
4301 // All i16 and i8 vector types can't be used directly by a generic shuffle
4302 // instruction because the target has no such instruction. Generate shuffles
4303 // which repeat i16 and i8 several times until they fit in i32, and then can
4304 // be manipulated by target suported shuffles.
4305 EVT EltVT = SrcVT.getVectorElementType();
4306 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4307 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4309 // Recreate the 256-bit vector and place the same 128-bit vector
4310 // into the low and high part. This is necessary because we want
4311 // to use VPERM* to shuffle the vectors
4313 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4314 DAG.getConstant(0, MVT::i32), DAG, dl);
4315 V1 = Insert128BitVector(InsV, V1,
4316 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4319 return getLegalSplat(DAG, V1, EltNo);
4322 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4323 /// vector of zero or undef vector. This produces a shuffle where the low
4324 /// element of V2 is swizzled into the zero/undef vector, landing at element
4325 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4326 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4328 const X86Subtarget *Subtarget,
4329 SelectionDAG &DAG) {
4330 EVT VT = V2.getValueType();
4332 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4333 unsigned NumElems = VT.getVectorNumElements();
4334 SmallVector<int, 16> MaskVec;
4335 for (unsigned i = 0; i != NumElems; ++i)
4336 // If this is the insertion idx, put the low elt of V2 here.
4337 MaskVec.push_back(i == Idx ? NumElems : i);
4338 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4341 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4342 /// element of the result of the vector shuffle.
4343 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4346 return SDValue(); // Limit search depth.
4348 SDValue V = SDValue(N, 0);
4349 EVT VT = V.getValueType();
4350 unsigned Opcode = V.getOpcode();
4352 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4353 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4354 Index = SV->getMaskElt(Index);
4357 return DAG.getUNDEF(VT.getVectorElementType());
4359 unsigned NumElems = VT.getVectorNumElements();
4360 SDValue NewV = (Index < (int)NumElems) ? SV->getOperand(0)
4361 : SV->getOperand(1);
4362 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4365 // Recurse into target specific vector shuffles to find scalars.
4366 if (isTargetShuffle(Opcode)) {
4367 unsigned NumElems = VT.getVectorNumElements();
4368 SmallVector<unsigned, 16> ShuffleMask;
4373 ImmN = N->getOperand(N->getNumOperands()-1);
4374 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4377 case X86ISD::UNPCKH:
4378 DecodeUNPCKHMask(VT, ShuffleMask);
4380 case X86ISD::UNPCKL:
4381 DecodeUNPCKLMask(VT, ShuffleMask);
4383 case X86ISD::MOVHLPS:
4384 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4386 case X86ISD::MOVLHPS:
4387 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4389 case X86ISD::PSHUFD:
4390 case X86ISD::VPERMILP:
4391 ImmN = N->getOperand(N->getNumOperands()-1);
4392 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4395 case X86ISD::PSHUFHW:
4396 ImmN = N->getOperand(N->getNumOperands()-1);
4397 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4400 case X86ISD::PSHUFLW:
4401 ImmN = N->getOperand(N->getNumOperands()-1);
4402 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4406 case X86ISD::MOVSD: {
4407 // The index 0 always comes from the first element of the second source,
4408 // this is why MOVSS and MOVSD are used in the first place. The other
4409 // elements come from the other positions of the first source vector.
4410 unsigned OpNum = (Index == 0) ? 1 : 0;
4411 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4414 case X86ISD::VPERM2X128:
4415 ImmN = N->getOperand(N->getNumOperands()-1);
4416 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4419 case X86ISD::MOVDDUP:
4420 case X86ISD::MOVLHPD:
4421 case X86ISD::MOVLPD:
4422 case X86ISD::MOVLPS:
4423 case X86ISD::MOVSHDUP:
4424 case X86ISD::MOVSLDUP:
4425 case X86ISD::PALIGN:
4426 return SDValue(); // Not yet implemented.
4427 default: llvm_unreachable("unknown target shuffle node");
4430 Index = ShuffleMask[Index];
4432 return DAG.getUNDEF(VT.getVectorElementType());
4434 SDValue NewV = (Index < (int)NumElems) ? N->getOperand(0)
4436 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4440 // Actual nodes that may contain scalar elements
4441 if (Opcode == ISD::BITCAST) {
4442 V = V.getOperand(0);
4443 EVT SrcVT = V.getValueType();
4444 unsigned NumElems = VT.getVectorNumElements();
4446 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4450 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4451 return (Index == 0) ? V.getOperand(0)
4452 : DAG.getUNDEF(VT.getVectorElementType());
4454 if (V.getOpcode() == ISD::BUILD_VECTOR)
4455 return V.getOperand(Index);
4460 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4461 /// shuffle operation which come from a consecutively from a zero. The
4462 /// search can start in two different directions, from left or right.
4464 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4465 bool ZerosFromLeft, SelectionDAG &DAG) {
4468 while (i < NumElems) {
4469 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4470 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4471 if (!(Elt.getNode() &&
4472 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4480 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4481 /// MaskE correspond consecutively to elements from one of the vector operands,
4482 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4484 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4485 int OpIdx, int NumElems, unsigned &OpNum) {
4486 bool SeenV1 = false;
4487 bool SeenV2 = false;
4489 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4490 int Idx = SVOp->getMaskElt(i);
4491 // Ignore undef indicies
4500 // Only accept consecutive elements from the same vector
4501 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4505 OpNum = SeenV1 ? 0 : 1;
4509 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4510 /// logical left shift of a vector.
4511 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4512 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4513 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4514 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4515 false /* check zeros from right */, DAG);
4521 // Considering the elements in the mask that are not consecutive zeros,
4522 // check if they consecutively come from only one of the source vectors.
4524 // V1 = {X, A, B, C} 0
4526 // vector_shuffle V1, V2 <1, 2, 3, X>
4528 if (!isShuffleMaskConsecutive(SVOp,
4529 0, // Mask Start Index
4530 NumElems-NumZeros-1, // Mask End Index
4531 NumZeros, // Where to start looking in the src vector
4532 NumElems, // Number of elements in vector
4533 OpSrc)) // Which source operand ?
4538 ShVal = SVOp->getOperand(OpSrc);
4542 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4543 /// logical left shift of a vector.
4544 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4545 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4546 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4547 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4548 true /* check zeros from left */, DAG);
4554 // Considering the elements in the mask that are not consecutive zeros,
4555 // check if they consecutively come from only one of the source vectors.
4557 // 0 { A, B, X, X } = V2
4559 // vector_shuffle V1, V2 <X, X, 4, 5>
4561 if (!isShuffleMaskConsecutive(SVOp,
4562 NumZeros, // Mask Start Index
4563 NumElems-1, // Mask End Index
4564 0, // Where to start looking in the src vector
4565 NumElems, // Number of elements in vector
4566 OpSrc)) // Which source operand ?
4571 ShVal = SVOp->getOperand(OpSrc);
4575 /// isVectorShift - Returns true if the shuffle can be implemented as a
4576 /// logical left or right shift of a vector.
4577 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4578 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4579 // Although the logic below support any bitwidth size, there are no
4580 // shift instructions which handle more than 128-bit vectors.
4581 if (SVOp->getValueType(0).getSizeInBits() > 128)
4584 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4585 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4591 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4593 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4594 unsigned NumNonZero, unsigned NumZero,
4596 const X86Subtarget* Subtarget,
4597 const TargetLowering &TLI) {
4601 DebugLoc dl = Op.getDebugLoc();
4604 for (unsigned i = 0; i < 16; ++i) {
4605 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4606 if (ThisIsNonZero && First) {
4608 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4610 V = DAG.getUNDEF(MVT::v8i16);
4615 SDValue ThisElt(0, 0), LastElt(0, 0);
4616 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4617 if (LastIsNonZero) {
4618 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4619 MVT::i16, Op.getOperand(i-1));
4621 if (ThisIsNonZero) {
4622 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4623 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4624 ThisElt, DAG.getConstant(8, MVT::i8));
4626 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4630 if (ThisElt.getNode())
4631 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4632 DAG.getIntPtrConstant(i/2));
4636 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4639 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4641 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4642 unsigned NumNonZero, unsigned NumZero,
4644 const X86Subtarget* Subtarget,
4645 const TargetLowering &TLI) {
4649 DebugLoc dl = Op.getDebugLoc();
4652 for (unsigned i = 0; i < 8; ++i) {
4653 bool isNonZero = (NonZeros & (1 << i)) != 0;
4657 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4659 V = DAG.getUNDEF(MVT::v8i16);
4662 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4663 MVT::v8i16, V, Op.getOperand(i),
4664 DAG.getIntPtrConstant(i));
4671 /// getVShift - Return a vector logical shift node.
4673 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4674 unsigned NumBits, SelectionDAG &DAG,
4675 const TargetLowering &TLI, DebugLoc dl) {
4676 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift");
4677 EVT ShVT = MVT::v2i64;
4678 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4679 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4680 return DAG.getNode(ISD::BITCAST, dl, VT,
4681 DAG.getNode(Opc, dl, ShVT, SrcOp,
4682 DAG.getConstant(NumBits,
4683 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4687 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4688 SelectionDAG &DAG) const {
4690 // Check if the scalar load can be widened into a vector load. And if
4691 // the address is "base + cst" see if the cst can be "absorbed" into
4692 // the shuffle mask.
4693 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4694 SDValue Ptr = LD->getBasePtr();
4695 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4697 EVT PVT = LD->getValueType(0);
4698 if (PVT != MVT::i32 && PVT != MVT::f32)
4703 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4704 FI = FINode->getIndex();
4706 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4707 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4708 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4709 Offset = Ptr.getConstantOperandVal(1);
4710 Ptr = Ptr.getOperand(0);
4715 // FIXME: 256-bit vector instructions don't require a strict alignment,
4716 // improve this code to support it better.
4717 unsigned RequiredAlign = VT.getSizeInBits()/8;
4718 SDValue Chain = LD->getChain();
4719 // Make sure the stack object alignment is at least 16 or 32.
4720 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4721 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4722 if (MFI->isFixedObjectIndex(FI)) {
4723 // Can't change the alignment. FIXME: It's possible to compute
4724 // the exact stack offset and reference FI + adjust offset instead.
4725 // If someone *really* cares about this. That's the way to implement it.
4728 MFI->setObjectAlignment(FI, RequiredAlign);
4732 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4733 // Ptr + (Offset & ~15).
4736 if ((Offset % RequiredAlign) & 3)
4738 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4740 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4741 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4743 int EltNo = (Offset - StartOffset) >> 2;
4744 int NumElems = VT.getVectorNumElements();
4746 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4747 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4748 LD->getPointerInfo().getWithOffset(StartOffset),
4749 false, false, false, 0);
4751 SmallVector<int, 8> Mask;
4752 for (int i = 0; i < NumElems; ++i)
4753 Mask.push_back(EltNo);
4755 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4761 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4762 /// vector of type 'VT', see if the elements can be replaced by a single large
4763 /// load which has the same value as a build_vector whose operands are 'elts'.
4765 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4767 /// FIXME: we'd also like to handle the case where the last elements are zero
4768 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4769 /// There's even a handy isZeroNode for that purpose.
4770 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4771 DebugLoc &DL, SelectionDAG &DAG) {
4772 EVT EltVT = VT.getVectorElementType();
4773 unsigned NumElems = Elts.size();
4775 LoadSDNode *LDBase = NULL;
4776 unsigned LastLoadedElt = -1U;
4778 // For each element in the initializer, see if we've found a load or an undef.
4779 // If we don't find an initial load element, or later load elements are
4780 // non-consecutive, bail out.
4781 for (unsigned i = 0; i < NumElems; ++i) {
4782 SDValue Elt = Elts[i];
4784 if (!Elt.getNode() ||
4785 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4788 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4790 LDBase = cast<LoadSDNode>(Elt.getNode());
4794 if (Elt.getOpcode() == ISD::UNDEF)
4797 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4798 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4803 // If we have found an entire vector of loads and undefs, then return a large
4804 // load of the entire vector width starting at the base pointer. If we found
4805 // consecutive loads for the low half, generate a vzext_load node.
4806 if (LastLoadedElt == NumElems - 1) {
4807 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4808 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4809 LDBase->getPointerInfo(),
4810 LDBase->isVolatile(), LDBase->isNonTemporal(),
4811 LDBase->isInvariant(), 0);
4812 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4813 LDBase->getPointerInfo(),
4814 LDBase->isVolatile(), LDBase->isNonTemporal(),
4815 LDBase->isInvariant(), LDBase->getAlignment());
4816 } else if (NumElems == 4 && LastLoadedElt == 1 &&
4817 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4818 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4819 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4821 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
4822 LDBase->getPointerInfo(),
4823 LDBase->getAlignment(),
4824 false/*isVolatile*/, true/*ReadMem*/,
4826 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4831 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
4832 /// a vbroadcast node. We support two patterns:
4833 /// 1. A splat BUILD_VECTOR which uses a single scalar load.
4834 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4836 /// The scalar load node is returned when a pattern is found,
4837 /// or SDValue() otherwise.
4838 static SDValue isVectorBroadcast(SDValue &Op, const X86Subtarget *Subtarget) {
4839 if (!Subtarget->hasAVX())
4842 EVT VT = Op.getValueType();
4845 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
4846 V = V.getOperand(0);
4848 //A suspected load to be broadcasted.
4851 switch (V.getOpcode()) {
4853 // Unknown pattern found.
4856 case ISD::BUILD_VECTOR: {
4857 // The BUILD_VECTOR node must be a splat.
4858 if (!isSplatVector(V.getNode()))
4861 Ld = V.getOperand(0);
4863 // The suspected load node has several users. Make sure that all
4864 // of its users are from the BUILD_VECTOR node.
4865 if (!Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
4870 case ISD::VECTOR_SHUFFLE: {
4871 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4873 // Shuffles must have a splat mask where the first element is
4875 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
4878 SDValue Sc = Op.getOperand(0);
4879 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR)
4882 Ld = Sc.getOperand(0);
4884 // The scalar_to_vector node and the suspected
4885 // load node must have exactly one user.
4886 if (!Sc.hasOneUse() || !Ld.hasOneUse())
4892 // The scalar source must be a normal load.
4893 if (!ISD::isNormalLoad(Ld.getNode()))
4896 // Reject loads that have uses of the chain result
4897 if (Ld->hasAnyUseOfValue(1))
4900 bool Is256 = VT.getSizeInBits() == 256;
4901 bool Is128 = VT.getSizeInBits() == 128;
4902 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
4904 // VBroadcast to YMM
4905 if (Is256 && (ScalarSize == 32 || ScalarSize == 64))
4908 // VBroadcast to XMM
4909 if (Is128 && (ScalarSize == 32))
4912 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
4913 // double since there is vbroadcastsd xmm
4914 if (Subtarget->hasAVX2() && Ld.getValueType().isInteger()) {
4915 // VBroadcast to YMM
4916 if (Is256 && (ScalarSize == 8 || ScalarSize == 16))
4919 // VBroadcast to XMM
4920 if (Is128 && (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64))
4924 // Unsupported broadcast.
4929 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4930 DebugLoc dl = Op.getDebugLoc();
4932 EVT VT = Op.getValueType();
4933 EVT ExtVT = VT.getVectorElementType();
4934 unsigned NumElems = Op.getNumOperands();
4936 // Vectors containing all zeros can be matched by pxor and xorps later
4937 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
4938 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
4939 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
4940 if (VT == MVT::v4i32 || VT == MVT::v8i32)
4943 return getZeroVector(VT, Subtarget, DAG, dl);
4946 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
4947 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
4948 // vpcmpeqd on 256-bit vectors.
4949 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
4950 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasAVX2()))
4953 return getOnesVector(VT, Subtarget->hasAVX2(), DAG, dl);
4956 SDValue LD = isVectorBroadcast(Op, Subtarget);
4958 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
4960 unsigned EVTBits = ExtVT.getSizeInBits();
4962 unsigned NumZero = 0;
4963 unsigned NumNonZero = 0;
4964 unsigned NonZeros = 0;
4965 bool IsAllConstants = true;
4966 SmallSet<SDValue, 8> Values;
4967 for (unsigned i = 0; i < NumElems; ++i) {
4968 SDValue Elt = Op.getOperand(i);
4969 if (Elt.getOpcode() == ISD::UNDEF)
4972 if (Elt.getOpcode() != ISD::Constant &&
4973 Elt.getOpcode() != ISD::ConstantFP)
4974 IsAllConstants = false;
4975 if (X86::isZeroNode(Elt))
4978 NonZeros |= (1 << i);
4983 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4984 if (NumNonZero == 0)
4985 return DAG.getUNDEF(VT);
4987 // Special case for single non-zero, non-undef, element.
4988 if (NumNonZero == 1) {
4989 unsigned Idx = CountTrailingZeros_32(NonZeros);
4990 SDValue Item = Op.getOperand(Idx);
4992 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4993 // the value are obviously zero, truncate the value to i32 and do the
4994 // insertion that way. Only do this if the value is non-constant or if the
4995 // value is a constant being inserted into element 0. It is cheaper to do
4996 // a constant pool load than it is to do a movd + shuffle.
4997 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4998 (!IsAllConstants || Idx == 0)) {
4999 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5001 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5002 EVT VecVT = MVT::v4i32;
5003 unsigned VecElts = 4;
5005 // Truncate the value (which may itself be a constant) to i32, and
5006 // convert it to a vector with movd (S2V+shuffle to zero extend).
5007 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5008 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5009 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5011 // Now we have our 32-bit value zero extended in the low element of
5012 // a vector. If Idx != 0, swizzle it into place.
5014 SmallVector<int, 4> Mask;
5015 Mask.push_back(Idx);
5016 for (unsigned i = 1; i != VecElts; ++i)
5018 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5019 DAG.getUNDEF(Item.getValueType()),
5022 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5026 // If we have a constant or non-constant insertion into the low element of
5027 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5028 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5029 // depending on what the source datatype is.
5032 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5034 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5035 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5036 if (VT.getSizeInBits() == 256) {
5037 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5038 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5039 Item, DAG.getIntPtrConstant(0));
5041 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5042 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5043 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5044 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5047 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5048 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5049 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5050 if (VT.getSizeInBits() == 256) {
5051 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5052 Item = Insert128BitVector(ZeroVec, Item, DAG.getConstant(0, MVT::i32),
5055 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5056 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5058 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5062 // Is it a vector logical left shift?
5063 if (NumElems == 2 && Idx == 1 &&
5064 X86::isZeroNode(Op.getOperand(0)) &&
5065 !X86::isZeroNode(Op.getOperand(1))) {
5066 unsigned NumBits = VT.getSizeInBits();
5067 return getVShift(true, VT,
5068 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5069 VT, Op.getOperand(1)),
5070 NumBits/2, DAG, *this, dl);
5073 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5076 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5077 // is a non-constant being inserted into an element other than the low one,
5078 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5079 // movd/movss) to move this into the low element, then shuffle it into
5081 if (EVTBits == 32) {
5082 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5084 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5085 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5086 SmallVector<int, 8> MaskVec;
5087 for (unsigned i = 0; i < NumElems; i++)
5088 MaskVec.push_back(i == Idx ? 0 : 1);
5089 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5093 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5094 if (Values.size() == 1) {
5095 if (EVTBits == 32) {
5096 // Instead of a shuffle like this:
5097 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5098 // Check if it's possible to issue this instead.
5099 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5100 unsigned Idx = CountTrailingZeros_32(NonZeros);
5101 SDValue Item = Op.getOperand(Idx);
5102 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5103 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5108 // A vector full of immediates; various special cases are already
5109 // handled, so this is best done with a single constant-pool load.
5113 // For AVX-length vectors, build the individual 128-bit pieces and use
5114 // shuffles to put them in place.
5115 if (VT.getSizeInBits() == 256) {
5116 SmallVector<SDValue, 32> V;
5117 for (unsigned i = 0; i != NumElems; ++i)
5118 V.push_back(Op.getOperand(i));
5120 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5122 // Build both the lower and upper subvector.
5123 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5124 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5127 // Recreate the wider vector with the lower and upper part.
5128 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5129 DAG.getConstant(0, MVT::i32), DAG, dl);
5130 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5134 // Let legalizer expand 2-wide build_vectors.
5135 if (EVTBits == 64) {
5136 if (NumNonZero == 1) {
5137 // One half is zero or undef.
5138 unsigned Idx = CountTrailingZeros_32(NonZeros);
5139 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5140 Op.getOperand(Idx));
5141 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5146 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5147 if (EVTBits == 8 && NumElems == 16) {
5148 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5150 if (V.getNode()) return V;
5153 if (EVTBits == 16 && NumElems == 8) {
5154 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5156 if (V.getNode()) return V;
5159 // If element VT is == 32 bits, turn it into a number of shuffles.
5160 SmallVector<SDValue, 8> V(NumElems);
5161 if (NumElems == 4 && NumZero > 0) {
5162 for (unsigned i = 0; i < 4; ++i) {
5163 bool isZero = !(NonZeros & (1 << i));
5165 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5167 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5170 for (unsigned i = 0; i < 2; ++i) {
5171 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5174 V[i] = V[i*2]; // Must be a zero vector.
5177 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5180 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5183 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5188 bool Reverse1 = (NonZeros & 0x3) == 2;
5189 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5193 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5194 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5196 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5199 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5200 // Check for a build vector of consecutive loads.
5201 for (unsigned i = 0; i < NumElems; ++i)
5202 V[i] = Op.getOperand(i);
5204 // Check for elements which are consecutive loads.
5205 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5209 // For SSE 4.1, use insertps to put the high elements into the low element.
5210 if (getSubtarget()->hasSSE41()) {
5212 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5213 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5215 Result = DAG.getUNDEF(VT);
5217 for (unsigned i = 1; i < NumElems; ++i) {
5218 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5219 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5220 Op.getOperand(i), DAG.getIntPtrConstant(i));
5225 // Otherwise, expand into a number of unpckl*, start by extending each of
5226 // our (non-undef) elements to the full vector width with the element in the
5227 // bottom slot of the vector (which generates no code for SSE).
5228 for (unsigned i = 0; i < NumElems; ++i) {
5229 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5230 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5232 V[i] = DAG.getUNDEF(VT);
5235 // Next, we iteratively mix elements, e.g. for v4f32:
5236 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5237 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5238 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5239 unsigned EltStride = NumElems >> 1;
5240 while (EltStride != 0) {
5241 for (unsigned i = 0; i < EltStride; ++i) {
5242 // If V[i+EltStride] is undef and this is the first round of mixing,
5243 // then it is safe to just drop this shuffle: V[i] is already in the
5244 // right place, the one element (since it's the first round) being
5245 // inserted as undef can be dropped. This isn't safe for successive
5246 // rounds because they will permute elements within both vectors.
5247 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5248 EltStride == NumElems/2)
5251 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5260 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5261 // them in a MMX register. This is better than doing a stack convert.
5262 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5263 DebugLoc dl = Op.getDebugLoc();
5264 EVT ResVT = Op.getValueType();
5266 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5267 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5269 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5270 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5271 InVec = Op.getOperand(1);
5272 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5273 unsigned NumElts = ResVT.getVectorNumElements();
5274 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5275 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5276 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5278 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5279 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5280 Mask[0] = 0; Mask[1] = 2;
5281 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5283 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5286 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5287 // to create 256-bit vectors from two other 128-bit ones.
5288 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5289 DebugLoc dl = Op.getDebugLoc();
5290 EVT ResVT = Op.getValueType();
5292 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5294 SDValue V1 = Op.getOperand(0);
5295 SDValue V2 = Op.getOperand(1);
5296 unsigned NumElems = ResVT.getVectorNumElements();
5298 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5299 DAG.getConstant(0, MVT::i32), DAG, dl);
5300 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5305 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5306 EVT ResVT = Op.getValueType();
5308 assert(Op.getNumOperands() == 2);
5309 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5310 "Unsupported CONCAT_VECTORS for value type");
5312 // We support concatenate two MMX registers and place them in a MMX register.
5313 // This is better than doing a stack convert.
5314 if (ResVT.is128BitVector())
5315 return LowerMMXCONCAT_VECTORS(Op, DAG);
5317 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5318 // from two other 128-bit ones.
5319 return LowerAVXCONCAT_VECTORS(Op, DAG);
5322 // v8i16 shuffles - Prefer shuffles in the following order:
5323 // 1. [all] pshuflw, pshufhw, optional move
5324 // 2. [ssse3] 1 x pshufb
5325 // 3. [ssse3] 2 x pshufb + 1 x por
5326 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5328 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5329 SelectionDAG &DAG) const {
5330 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5331 SDValue V1 = SVOp->getOperand(0);
5332 SDValue V2 = SVOp->getOperand(1);
5333 DebugLoc dl = SVOp->getDebugLoc();
5334 SmallVector<int, 8> MaskVals;
5336 // Determine if more than 1 of the words in each of the low and high quadwords
5337 // of the result come from the same quadword of one of the two inputs. Undef
5338 // mask values count as coming from any quadword, for better codegen.
5339 unsigned LoQuad[] = { 0, 0, 0, 0 };
5340 unsigned HiQuad[] = { 0, 0, 0, 0 };
5341 std::bitset<4> InputQuads;
5342 for (unsigned i = 0; i < 8; ++i) {
5343 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5344 int EltIdx = SVOp->getMaskElt(i);
5345 MaskVals.push_back(EltIdx);
5354 InputQuads.set(EltIdx / 4);
5357 int BestLoQuad = -1;
5358 unsigned MaxQuad = 1;
5359 for (unsigned i = 0; i < 4; ++i) {
5360 if (LoQuad[i] > MaxQuad) {
5362 MaxQuad = LoQuad[i];
5366 int BestHiQuad = -1;
5368 for (unsigned i = 0; i < 4; ++i) {
5369 if (HiQuad[i] > MaxQuad) {
5371 MaxQuad = HiQuad[i];
5375 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5376 // of the two input vectors, shuffle them into one input vector so only a
5377 // single pshufb instruction is necessary. If There are more than 2 input
5378 // quads, disable the next transformation since it does not help SSSE3.
5379 bool V1Used = InputQuads[0] || InputQuads[1];
5380 bool V2Used = InputQuads[2] || InputQuads[3];
5381 if (Subtarget->hasSSSE3()) {
5382 if (InputQuads.count() == 2 && V1Used && V2Used) {
5383 BestLoQuad = InputQuads[0] ? 0 : 1;
5384 BestHiQuad = InputQuads[2] ? 2 : 3;
5386 if (InputQuads.count() > 2) {
5392 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5393 // the shuffle mask. If a quad is scored as -1, that means that it contains
5394 // words from all 4 input quadwords.
5396 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5398 BestLoQuad < 0 ? 0 : BestLoQuad,
5399 BestHiQuad < 0 ? 1 : BestHiQuad
5401 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5402 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5403 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5404 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5406 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5407 // source words for the shuffle, to aid later transformations.
5408 bool AllWordsInNewV = true;
5409 bool InOrder[2] = { true, true };
5410 for (unsigned i = 0; i != 8; ++i) {
5411 int idx = MaskVals[i];
5413 InOrder[i/4] = false;
5414 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5416 AllWordsInNewV = false;
5420 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5421 if (AllWordsInNewV) {
5422 for (int i = 0; i != 8; ++i) {
5423 int idx = MaskVals[i];
5426 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5427 if ((idx != i) && idx < 4)
5429 if ((idx != i) && idx > 3)
5438 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5439 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5440 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5441 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5442 unsigned TargetMask = 0;
5443 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5444 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5445 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5446 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5447 getShufflePSHUFLWImmediate(SVOp);
5448 V1 = NewV.getOperand(0);
5449 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5453 // If we have SSSE3, and all words of the result are from 1 input vector,
5454 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5455 // is present, fall back to case 4.
5456 if (Subtarget->hasSSSE3()) {
5457 SmallVector<SDValue,16> pshufbMask;
5459 // If we have elements from both input vectors, set the high bit of the
5460 // shuffle mask element to zero out elements that come from V2 in the V1
5461 // mask, and elements that come from V1 in the V2 mask, so that the two
5462 // results can be OR'd together.
5463 bool TwoInputs = V1Used && V2Used;
5464 for (unsigned i = 0; i != 8; ++i) {
5465 int EltIdx = MaskVals[i] * 2;
5466 if (TwoInputs && (EltIdx >= 16)) {
5467 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5468 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5471 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5472 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5474 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5475 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5476 DAG.getNode(ISD::BUILD_VECTOR, dl,
5477 MVT::v16i8, &pshufbMask[0], 16));
5479 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5481 // Calculate the shuffle mask for the second input, shuffle it, and
5482 // OR it with the first shuffled input.
5484 for (unsigned i = 0; i != 8; ++i) {
5485 int EltIdx = MaskVals[i] * 2;
5487 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5488 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5491 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5492 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5494 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5495 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5496 DAG.getNode(ISD::BUILD_VECTOR, dl,
5497 MVT::v16i8, &pshufbMask[0], 16));
5498 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5499 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5502 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5503 // and update MaskVals with new element order.
5504 std::bitset<8> InOrder;
5505 if (BestLoQuad >= 0) {
5506 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5507 for (int i = 0; i != 4; ++i) {
5508 int idx = MaskVals[i];
5511 } else if ((idx / 4) == BestLoQuad) {
5516 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5519 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5520 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5521 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5523 getShufflePSHUFLWImmediate(SVOp), DAG);
5527 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5528 // and update MaskVals with the new element order.
5529 if (BestHiQuad >= 0) {
5530 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5531 for (unsigned i = 4; i != 8; ++i) {
5532 int idx = MaskVals[i];
5535 } else if ((idx / 4) == BestHiQuad) {
5536 MaskV[i] = (idx & 3) + 4;
5540 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5543 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5544 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5545 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5547 getShufflePSHUFHWImmediate(SVOp), DAG);
5551 // In case BestHi & BestLo were both -1, which means each quadword has a word
5552 // from each of the four input quadwords, calculate the InOrder bitvector now
5553 // before falling through to the insert/extract cleanup.
5554 if (BestLoQuad == -1 && BestHiQuad == -1) {
5556 for (int i = 0; i != 8; ++i)
5557 if (MaskVals[i] < 0 || MaskVals[i] == i)
5561 // The other elements are put in the right place using pextrw and pinsrw.
5562 for (unsigned i = 0; i != 8; ++i) {
5565 int EltIdx = MaskVals[i];
5568 SDValue ExtOp = (EltIdx < 8)
5569 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5570 DAG.getIntPtrConstant(EltIdx))
5571 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5572 DAG.getIntPtrConstant(EltIdx - 8));
5573 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5574 DAG.getIntPtrConstant(i));
5579 // v16i8 shuffles - Prefer shuffles in the following order:
5580 // 1. [ssse3] 1 x pshufb
5581 // 2. [ssse3] 2 x pshufb + 1 x por
5582 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5584 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5586 const X86TargetLowering &TLI) {
5587 SDValue V1 = SVOp->getOperand(0);
5588 SDValue V2 = SVOp->getOperand(1);
5589 DebugLoc dl = SVOp->getDebugLoc();
5590 ArrayRef<int> MaskVals = SVOp->getMask();
5592 // If we have SSSE3, case 1 is generated when all result bytes come from
5593 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5594 // present, fall back to case 3.
5595 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5598 for (unsigned i = 0; i < 16; ++i) {
5599 int EltIdx = MaskVals[i];
5608 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5609 if (TLI.getSubtarget()->hasSSSE3()) {
5610 SmallVector<SDValue,16> pshufbMask;
5612 // If all result elements are from one input vector, then only translate
5613 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5615 // Otherwise, we have elements from both input vectors, and must zero out
5616 // elements that come from V2 in the first mask, and V1 in the second mask
5617 // so that we can OR them together.
5618 bool TwoInputs = !(V1Only || V2Only);
5619 for (unsigned i = 0; i != 16; ++i) {
5620 int EltIdx = MaskVals[i];
5621 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5622 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5625 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5627 // If all the elements are from V2, assign it to V1 and return after
5628 // building the first pshufb.
5631 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5632 DAG.getNode(ISD::BUILD_VECTOR, dl,
5633 MVT::v16i8, &pshufbMask[0], 16));
5637 // Calculate the shuffle mask for the second input, shuffle it, and
5638 // OR it with the first shuffled input.
5640 for (unsigned i = 0; i != 16; ++i) {
5641 int EltIdx = MaskVals[i];
5643 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5646 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5648 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5649 DAG.getNode(ISD::BUILD_VECTOR, dl,
5650 MVT::v16i8, &pshufbMask[0], 16));
5651 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5654 // No SSSE3 - Calculate in place words and then fix all out of place words
5655 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5656 // the 16 different words that comprise the two doublequadword input vectors.
5657 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5658 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5659 SDValue NewV = V2Only ? V2 : V1;
5660 for (int i = 0; i != 8; ++i) {
5661 int Elt0 = MaskVals[i*2];
5662 int Elt1 = MaskVals[i*2+1];
5664 // This word of the result is all undef, skip it.
5665 if (Elt0 < 0 && Elt1 < 0)
5668 // This word of the result is already in the correct place, skip it.
5669 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5671 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5674 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5675 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5678 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5679 // using a single extract together, load it and store it.
5680 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5681 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5682 DAG.getIntPtrConstant(Elt1 / 2));
5683 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5684 DAG.getIntPtrConstant(i));
5688 // If Elt1 is defined, extract it from the appropriate source. If the
5689 // source byte is not also odd, shift the extracted word left 8 bits
5690 // otherwise clear the bottom 8 bits if we need to do an or.
5692 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5693 DAG.getIntPtrConstant(Elt1 / 2));
5694 if ((Elt1 & 1) == 0)
5695 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5697 TLI.getShiftAmountTy(InsElt.getValueType())));
5699 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5700 DAG.getConstant(0xFF00, MVT::i16));
5702 // If Elt0 is defined, extract it from the appropriate source. If the
5703 // source byte is not also even, shift the extracted word right 8 bits. If
5704 // Elt1 was also defined, OR the extracted values together before
5705 // inserting them in the result.
5707 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5708 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5709 if ((Elt0 & 1) != 0)
5710 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5712 TLI.getShiftAmountTy(InsElt0.getValueType())));
5714 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5715 DAG.getConstant(0x00FF, MVT::i16));
5716 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5719 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5720 DAG.getIntPtrConstant(i));
5722 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5725 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5726 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5727 /// done when every pair / quad of shuffle mask elements point to elements in
5728 /// the right sequence. e.g.
5729 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5731 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5732 SelectionDAG &DAG, DebugLoc dl) {
5733 EVT VT = SVOp->getValueType(0);
5734 SDValue V1 = SVOp->getOperand(0);
5735 SDValue V2 = SVOp->getOperand(1);
5736 unsigned NumElems = VT.getVectorNumElements();
5737 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5739 switch (VT.getSimpleVT().SimpleTy) {
5740 default: llvm_unreachable("Unexpected!");
5741 case MVT::v4f32: NewVT = MVT::v2f64; break;
5742 case MVT::v4i32: NewVT = MVT::v2i64; break;
5743 case MVT::v8i16: NewVT = MVT::v4i32; break;
5744 case MVT::v16i8: NewVT = MVT::v4i32; break;
5747 int Scale = NumElems / NewWidth;
5748 SmallVector<int, 8> MaskVec;
5749 for (unsigned i = 0; i < NumElems; i += Scale) {
5751 for (int j = 0; j < Scale; ++j) {
5752 int EltIdx = SVOp->getMaskElt(i+j);
5756 StartIdx = EltIdx - (EltIdx % Scale);
5757 if (EltIdx != StartIdx + j)
5761 MaskVec.push_back(-1);
5763 MaskVec.push_back(StartIdx / Scale);
5766 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5767 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5768 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5771 /// getVZextMovL - Return a zero-extending vector move low node.
5773 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5774 SDValue SrcOp, SelectionDAG &DAG,
5775 const X86Subtarget *Subtarget, DebugLoc dl) {
5776 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5777 LoadSDNode *LD = NULL;
5778 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5779 LD = dyn_cast<LoadSDNode>(SrcOp);
5781 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5783 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5784 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5785 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5786 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5787 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5789 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5790 return DAG.getNode(ISD::BITCAST, dl, VT,
5791 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5792 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5800 return DAG.getNode(ISD::BITCAST, dl, VT,
5801 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5802 DAG.getNode(ISD::BITCAST, dl,
5806 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5807 /// which could not be matched by any known target speficic shuffle
5809 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5810 EVT VT = SVOp->getValueType(0);
5812 unsigned NumElems = VT.getVectorNumElements();
5813 unsigned NumLaneElems = NumElems / 2;
5815 int MinRange[2][2] = { { static_cast<int>(NumElems),
5816 static_cast<int>(NumElems) },
5817 { static_cast<int>(NumElems),
5818 static_cast<int>(NumElems) } };
5819 int MaxRange[2][2] = { { -1, -1 }, { -1, -1 } };
5821 // Collect used ranges for each source in each lane
5822 for (unsigned l = 0; l < 2; ++l) {
5823 unsigned LaneStart = l*NumLaneElems;
5824 for (unsigned i = 0; i != NumLaneElems; ++i) {
5825 int Idx = SVOp->getMaskElt(i+LaneStart);
5830 if (Idx >= (int)NumElems) {
5835 if (Idx > MaxRange[l][Input])
5836 MaxRange[l][Input] = Idx;
5837 if (Idx < MinRange[l][Input])
5838 MinRange[l][Input] = Idx;
5842 // Make sure each range is 128-bits
5843 int ExtractIdx[2][2] = { { -1, -1 }, { -1, -1 } };
5844 for (unsigned l = 0; l < 2; ++l) {
5845 for (unsigned Input = 0; Input < 2; ++Input) {
5846 if (MinRange[l][Input] == (int)NumElems && MaxRange[l][Input] < 0)
5849 if (MinRange[l][Input] >= 0 && MaxRange[l][Input] < (int)NumLaneElems)
5850 ExtractIdx[l][Input] = 0;
5851 else if (MinRange[l][Input] >= (int)NumLaneElems &&
5852 MaxRange[l][Input] < (int)NumElems)
5853 ExtractIdx[l][Input] = NumLaneElems;
5859 DebugLoc dl = SVOp->getDebugLoc();
5860 MVT EltVT = VT.getVectorElementType().getSimpleVT();
5861 EVT NVT = MVT::getVectorVT(EltVT, NumElems/2);
5864 for (unsigned l = 0; l < 2; ++l) {
5865 for (unsigned Input = 0; Input < 2; ++Input) {
5866 if (ExtractIdx[l][Input] >= 0)
5867 Ops[l][Input] = Extract128BitVector(SVOp->getOperand(Input),
5868 DAG.getConstant(ExtractIdx[l][Input], MVT::i32),
5871 Ops[l][Input] = DAG.getUNDEF(NVT);
5875 // Generate 128-bit shuffles
5876 SmallVector<int, 16> Mask1, Mask2;
5877 for (unsigned i = 0; i != NumLaneElems; ++i) {
5878 int Elt = SVOp->getMaskElt(i);
5879 if (Elt >= (int)NumElems) {
5880 Elt %= NumLaneElems;
5881 Elt += NumLaneElems;
5882 } else if (Elt >= 0) {
5883 Elt %= NumLaneElems;
5885 Mask1.push_back(Elt);
5887 for (unsigned i = NumLaneElems; i != NumElems; ++i) {
5888 int Elt = SVOp->getMaskElt(i);
5889 if (Elt >= (int)NumElems) {
5890 Elt %= NumLaneElems;
5891 Elt += NumLaneElems;
5892 } else if (Elt >= 0) {
5893 Elt %= NumLaneElems;
5895 Mask2.push_back(Elt);
5898 SDValue Shuf1 = DAG.getVectorShuffle(NVT, dl, Ops[0][0], Ops[0][1], &Mask1[0]);
5899 SDValue Shuf2 = DAG.getVectorShuffle(NVT, dl, Ops[1][0], Ops[1][1], &Mask2[0]);
5901 // Concatenate the result back
5902 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Shuf1,
5903 DAG.getConstant(0, MVT::i32), DAG, dl);
5904 return Insert128BitVector(V, Shuf2, DAG.getConstant(NumElems/2, MVT::i32),
5908 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5909 /// 4 elements, and match them with several different shuffle types.
5911 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5912 SDValue V1 = SVOp->getOperand(0);
5913 SDValue V2 = SVOp->getOperand(1);
5914 DebugLoc dl = SVOp->getDebugLoc();
5915 EVT VT = SVOp->getValueType(0);
5917 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
5919 std::pair<int, int> Locs[4];
5920 int Mask1[] = { -1, -1, -1, -1 };
5921 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
5925 for (unsigned i = 0; i != 4; ++i) {
5926 int Idx = PermMask[i];
5928 Locs[i] = std::make_pair(-1, -1);
5930 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
5932 Locs[i] = std::make_pair(0, NumLo);
5936 Locs[i] = std::make_pair(1, NumHi);
5938 Mask1[2+NumHi] = Idx;
5944 if (NumLo <= 2 && NumHi <= 2) {
5945 // If no more than two elements come from either vector. This can be
5946 // implemented with two shuffles. First shuffle gather the elements.
5947 // The second shuffle, which takes the first shuffle as both of its
5948 // vector operands, put the elements into the right order.
5949 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5951 int Mask2[] = { -1, -1, -1, -1 };
5953 for (unsigned i = 0; i != 4; ++i)
5954 if (Locs[i].first != -1) {
5955 unsigned Idx = (i < 2) ? 0 : 4;
5956 Idx += Locs[i].first * 2 + Locs[i].second;
5960 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
5961 } else if (NumLo == 3 || NumHi == 3) {
5962 // Otherwise, we must have three elements from one vector, call it X, and
5963 // one element from the other, call it Y. First, use a shufps to build an
5964 // intermediate vector with the one element from Y and the element from X
5965 // that will be in the same half in the final destination (the indexes don't
5966 // matter). Then, use a shufps to build the final vector, taking the half
5967 // containing the element from Y from the intermediate, and the other half
5970 // Normalize it so the 3 elements come from V1.
5971 CommuteVectorShuffleMask(PermMask, 4);
5975 // Find the element from V2.
5977 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5978 int Val = PermMask[HiIndex];
5985 Mask1[0] = PermMask[HiIndex];
5987 Mask1[2] = PermMask[HiIndex^1];
5989 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5992 Mask1[0] = PermMask[0];
5993 Mask1[1] = PermMask[1];
5994 Mask1[2] = HiIndex & 1 ? 6 : 4;
5995 Mask1[3] = HiIndex & 1 ? 4 : 6;
5996 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5998 Mask1[0] = HiIndex & 1 ? 2 : 0;
5999 Mask1[1] = HiIndex & 1 ? 0 : 2;
6000 Mask1[2] = PermMask[2];
6001 Mask1[3] = PermMask[3];
6006 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6010 // Break it into (shuffle shuffle_hi, shuffle_lo).
6011 int LoMask[] = { -1, -1, -1, -1 };
6012 int HiMask[] = { -1, -1, -1, -1 };
6014 int *MaskPtr = LoMask;
6015 unsigned MaskIdx = 0;
6018 for (unsigned i = 0; i != 4; ++i) {
6025 int Idx = PermMask[i];
6027 Locs[i] = std::make_pair(-1, -1);
6028 } else if (Idx < 4) {
6029 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6030 MaskPtr[LoIdx] = Idx;
6033 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6034 MaskPtr[HiIdx] = Idx;
6039 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6040 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6041 int MaskOps[] = { -1, -1, -1, -1 };
6042 for (unsigned i = 0; i != 4; ++i)
6043 if (Locs[i].first != -1)
6044 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6045 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6048 static bool MayFoldVectorLoad(SDValue V) {
6049 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6050 V = V.getOperand(0);
6051 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6052 V = V.getOperand(0);
6053 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6054 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6055 // BUILD_VECTOR (load), undef
6056 V = V.getOperand(0);
6062 // FIXME: the version above should always be used. Since there's
6063 // a bug where several vector shuffles can't be folded because the
6064 // DAG is not updated during lowering and a node claims to have two
6065 // uses while it only has one, use this version, and let isel match
6066 // another instruction if the load really happens to have more than
6067 // one use. Remove this version after this bug get fixed.
6068 // rdar://8434668, PR8156
6069 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6070 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6071 V = V.getOperand(0);
6072 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6073 V = V.getOperand(0);
6074 if (ISD::isNormalLoad(V.getNode()))
6079 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6080 /// a vector extract, and if both can be later optimized into a single load.
6081 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6082 /// here because otherwise a target specific shuffle node is going to be
6083 /// emitted for this shuffle, and the optimization not done.
6084 /// FIXME: This is probably not the best approach, but fix the problem
6085 /// until the right path is decided.
6087 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6088 const TargetLowering &TLI) {
6089 EVT VT = V.getValueType();
6090 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6092 // Be sure that the vector shuffle is present in a pattern like this:
6093 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6097 SDNode *N = *V.getNode()->use_begin();
6098 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6101 SDValue EltNo = N->getOperand(1);
6102 if (!isa<ConstantSDNode>(EltNo))
6105 // If the bit convert changed the number of elements, it is unsafe
6106 // to examine the mask.
6107 bool HasShuffleIntoBitcast = false;
6108 if (V.getOpcode() == ISD::BITCAST) {
6109 EVT SrcVT = V.getOperand(0).getValueType();
6110 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6112 V = V.getOperand(0);
6113 HasShuffleIntoBitcast = true;
6116 // Select the input vector, guarding against out of range extract vector.
6117 unsigned NumElems = VT.getVectorNumElements();
6118 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6119 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6120 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6122 // If we are accessing the upper part of a YMM register
6123 // then the EXTRACT_VECTOR_ELT is likely to be legalized to a sequence of
6124 // EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which are not detected at this point
6125 // because the legalization of N did not happen yet.
6126 if (Idx >= (int)NumElems/2 && VT.getSizeInBits() == 256)
6129 // Skip one more bit_convert if necessary
6130 if (V.getOpcode() == ISD::BITCAST) {
6133 V = V.getOperand(0);
6136 if (!ISD::isNormalLoad(V.getNode()))
6139 // Is the original load suitable?
6140 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6142 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6145 if (!HasShuffleIntoBitcast)
6148 // If there's a bitcast before the shuffle, check if the load type and
6149 // alignment is valid.
6150 unsigned Align = LN0->getAlignment();
6152 TLI.getTargetData()->getABITypeAlignment(
6153 VT.getTypeForEVT(*DAG.getContext()));
6155 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6162 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6163 EVT VT = Op.getValueType();
6165 // Canonizalize to v2f64.
6166 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6167 return DAG.getNode(ISD::BITCAST, dl, VT,
6168 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6173 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6175 SDValue V1 = Op.getOperand(0);
6176 SDValue V2 = Op.getOperand(1);
6177 EVT VT = Op.getValueType();
6179 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6181 if (HasSSE2 && VT == MVT::v2f64)
6182 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6184 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6185 return DAG.getNode(ISD::BITCAST, dl, VT,
6186 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6187 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6188 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6192 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6193 SDValue V1 = Op.getOperand(0);
6194 SDValue V2 = Op.getOperand(1);
6195 EVT VT = Op.getValueType();
6197 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6198 "unsupported shuffle type");
6200 if (V2.getOpcode() == ISD::UNDEF)
6204 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6208 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6209 SDValue V1 = Op.getOperand(0);
6210 SDValue V2 = Op.getOperand(1);
6211 EVT VT = Op.getValueType();
6212 unsigned NumElems = VT.getVectorNumElements();
6214 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6215 // operand of these instructions is only memory, so check if there's a
6216 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6218 bool CanFoldLoad = false;
6220 // Trivial case, when V2 comes from a load.
6221 if (MayFoldVectorLoad(V2))
6224 // When V1 is a load, it can be folded later into a store in isel, example:
6225 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6227 // (MOVLPSmr addr:$src1, VR128:$src2)
6228 // So, recognize this potential and also use MOVLPS or MOVLPD
6229 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6232 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6234 if (HasSSE2 && NumElems == 2)
6235 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6238 // If we don't care about the second element, procede to use movss.
6239 if (SVOp->getMaskElt(1) != -1)
6240 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6243 // movl and movlp will both match v2i64, but v2i64 is never matched by
6244 // movl earlier because we make it strict to avoid messing with the movlp load
6245 // folding logic (see the code above getMOVLP call). Match it here then,
6246 // this is horrible, but will stay like this until we move all shuffle
6247 // matching to x86 specific nodes. Note that for the 1st condition all
6248 // types are matched with movsd.
6250 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6251 // as to remove this logic from here, as much as possible
6252 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6253 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6254 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6257 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6259 // Invert the operand order and use SHUFPS to match it.
6260 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6261 getShuffleSHUFImmediate(SVOp), DAG);
6265 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6266 const TargetLowering &TLI,
6267 const X86Subtarget *Subtarget) {
6268 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6269 EVT VT = Op.getValueType();
6270 DebugLoc dl = Op.getDebugLoc();
6271 SDValue V1 = Op.getOperand(0);
6272 SDValue V2 = Op.getOperand(1);
6274 if (isZeroShuffle(SVOp))
6275 return getZeroVector(VT, Subtarget, DAG, dl);
6277 // Handle splat operations
6278 if (SVOp->isSplat()) {
6279 unsigned NumElem = VT.getVectorNumElements();
6280 int Size = VT.getSizeInBits();
6281 // Special case, this is the only place now where it's allowed to return
6282 // a vector_shuffle operation without using a target specific node, because
6283 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6284 // this be moved to DAGCombine instead?
6285 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6288 // Use vbroadcast whenever the splat comes from a foldable load
6289 SDValue LD = isVectorBroadcast(Op, Subtarget);
6291 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, LD);
6293 // Handle splats by matching through known shuffle masks
6294 if ((Size == 128 && NumElem <= 4) ||
6295 (Size == 256 && NumElem < 8))
6298 // All remaning splats are promoted to target supported vector shuffles.
6299 return PromoteSplat(SVOp, DAG);
6302 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6304 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6305 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6306 if (NewOp.getNode())
6307 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6308 } else if ((VT == MVT::v4i32 ||
6309 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6310 // FIXME: Figure out a cleaner way to do this.
6311 // Try to make use of movq to zero out the top part.
6312 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6313 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6314 if (NewOp.getNode()) {
6315 EVT NewVT = NewOp.getValueType();
6316 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6317 NewVT, true, false))
6318 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6319 DAG, Subtarget, dl);
6321 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6322 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6323 if (NewOp.getNode()) {
6324 EVT NewVT = NewOp.getValueType();
6325 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6326 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6327 DAG, Subtarget, dl);
6335 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6336 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6337 SDValue V1 = Op.getOperand(0);
6338 SDValue V2 = Op.getOperand(1);
6339 EVT VT = Op.getValueType();
6340 DebugLoc dl = Op.getDebugLoc();
6341 unsigned NumElems = VT.getVectorNumElements();
6342 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6343 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6344 bool V1IsSplat = false;
6345 bool V2IsSplat = false;
6346 bool HasSSE2 = Subtarget->hasSSE2();
6347 bool HasAVX = Subtarget->hasAVX();
6348 bool HasAVX2 = Subtarget->hasAVX2();
6349 MachineFunction &MF = DAG.getMachineFunction();
6350 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6352 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6354 if (V1IsUndef && V2IsUndef)
6355 return DAG.getUNDEF(VT);
6357 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6359 // Vector shuffle lowering takes 3 steps:
6361 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6362 // narrowing and commutation of operands should be handled.
6363 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6365 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6366 // so the shuffle can be broken into other shuffles and the legalizer can
6367 // try the lowering again.
6369 // The general idea is that no vector_shuffle operation should be left to
6370 // be matched during isel, all of them must be converted to a target specific
6373 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6374 // narrowing and commutation of operands should be handled. The actual code
6375 // doesn't include all of those, work in progress...
6376 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6377 if (NewOp.getNode())
6380 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6382 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6383 // unpckh_undef). Only use pshufd if speed is more important than size.
6384 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6385 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6386 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6387 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6389 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6390 V2IsUndef && RelaxedMayFoldVectorLoad(V1))
6391 return getMOVDDup(Op, dl, V1, DAG);
6393 if (isMOVHLPS_v_undef_Mask(M, VT))
6394 return getMOVHighToLow(Op, dl, DAG);
6396 // Use to match splats
6397 if (HasSSE2 && isUNPCKHMask(M, VT, HasAVX2) && V2IsUndef &&
6398 (VT == MVT::v2f64 || VT == MVT::v2i64))
6399 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6401 if (isPSHUFDMask(M, VT)) {
6402 // The actual implementation will match the mask in the if above and then
6403 // during isel it can match several different instructions, not only pshufd
6404 // as its name says, sad but true, emulate the behavior for now...
6405 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6406 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6408 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6410 if (HasAVX && (VT == MVT::v4f32 || VT == MVT::v2f64))
6411 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask, DAG);
6413 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6414 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6416 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6420 // Check if this can be converted into a logical shift.
6421 bool isLeft = false;
6424 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6425 if (isShift && ShVal.hasOneUse()) {
6426 // If the shifted value has multiple uses, it may be cheaper to use
6427 // v_set0 + movlhps or movhlps, etc.
6428 EVT EltVT = VT.getVectorElementType();
6429 ShAmt *= EltVT.getSizeInBits();
6430 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6433 if (isMOVLMask(M, VT)) {
6434 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6435 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6436 if (!isMOVLPMask(M, VT)) {
6437 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6438 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6440 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6441 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6445 // FIXME: fold these into legal mask.
6446 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasAVX2))
6447 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6449 if (isMOVHLPSMask(M, VT))
6450 return getMOVHighToLow(Op, dl, DAG);
6452 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6453 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6455 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6456 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6458 if (isMOVLPMask(M, VT))
6459 return getMOVLP(Op, dl, DAG, HasSSE2);
6461 if (ShouldXformToMOVHLPS(M, VT) ||
6462 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6463 return CommuteVectorShuffle(SVOp, DAG);
6466 // No better options. Use a vshldq / vsrldq.
6467 EVT EltVT = VT.getVectorElementType();
6468 ShAmt *= EltVT.getSizeInBits();
6469 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6472 bool Commuted = false;
6473 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6474 // 1,1,1,1 -> v8i16 though.
6475 V1IsSplat = isSplatVector(V1.getNode());
6476 V2IsSplat = isSplatVector(V2.getNode());
6478 // Canonicalize the splat or undef, if present, to be on the RHS.
6479 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6480 CommuteVectorShuffleMask(M, NumElems);
6482 std::swap(V1IsSplat, V2IsSplat);
6486 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6487 // Shuffling low element of v1 into undef, just return v1.
6490 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6491 // the instruction selector will not match, so get a canonical MOVL with
6492 // swapped operands to undo the commute.
6493 return getMOVL(DAG, dl, VT, V2, V1);
6496 if (isUNPCKLMask(M, VT, HasAVX2))
6497 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6499 if (isUNPCKHMask(M, VT, HasAVX2))
6500 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6503 // Normalize mask so all entries that point to V2 points to its first
6504 // element then try to match unpck{h|l} again. If match, return a
6505 // new vector_shuffle with the corrected mask.p
6506 SmallVector<int, 8> NewMask(M.begin(), M.end());
6507 NormalizeMask(NewMask, NumElems);
6508 if (isUNPCKLMask(NewMask, VT, HasAVX2, true)) {
6509 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6510 } else if (isUNPCKHMask(NewMask, VT, HasAVX2, true)) {
6511 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6516 // Commute is back and try unpck* again.
6517 // FIXME: this seems wrong.
6518 CommuteVectorShuffleMask(M, NumElems);
6520 std::swap(V1IsSplat, V2IsSplat);
6523 if (isUNPCKLMask(M, VT, HasAVX2))
6524 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6526 if (isUNPCKHMask(M, VT, HasAVX2))
6527 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6530 // Normalize the node to match x86 shuffle ops if needed
6531 if (!V2IsUndef && (isSHUFPMask(M, VT, HasAVX, /* Commuted */ true)))
6532 return CommuteVectorShuffle(SVOp, DAG);
6534 // The checks below are all present in isShuffleMaskLegal, but they are
6535 // inlined here right now to enable us to directly emit target specific
6536 // nodes, and remove one by one until they don't return Op anymore.
6538 if (isPALIGNRMask(M, VT, Subtarget))
6539 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6540 getShufflePALIGNRImmediate(SVOp),
6543 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6544 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6545 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6546 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6549 if (isPSHUFHWMask(M, VT))
6550 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6551 getShufflePSHUFHWImmediate(SVOp),
6554 if (isPSHUFLWMask(M, VT))
6555 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6556 getShufflePSHUFLWImmediate(SVOp),
6559 if (isSHUFPMask(M, VT, HasAVX))
6560 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6561 getShuffleSHUFImmediate(SVOp), DAG);
6563 if (isUNPCKL_v_undef_Mask(M, VT, HasAVX2))
6564 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6565 if (isUNPCKH_v_undef_Mask(M, VT, HasAVX2))
6566 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6568 //===--------------------------------------------------------------------===//
6569 // Generate target specific nodes for 128 or 256-bit shuffles only
6570 // supported in the AVX instruction set.
6573 // Handle VMOVDDUPY permutations
6574 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasAVX))
6575 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6577 // Handle VPERMILPS/D* permutations
6578 if (isVPERMILPMask(M, VT, HasAVX)) {
6579 if (HasAVX2 && VT == MVT::v8i32)
6580 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6581 getShuffleSHUFImmediate(SVOp), DAG);
6582 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6583 getShuffleSHUFImmediate(SVOp), DAG);
6586 // Handle VPERM2F128/VPERM2I128 permutations
6587 if (isVPERM2X128Mask(M, VT, HasAVX))
6588 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6589 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6591 //===--------------------------------------------------------------------===//
6592 // Since no target specific shuffle was selected for this generic one,
6593 // lower it into other known shuffles. FIXME: this isn't true yet, but
6594 // this is the plan.
6597 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6598 if (VT == MVT::v8i16) {
6599 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6600 if (NewOp.getNode())
6604 if (VT == MVT::v16i8) {
6605 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6606 if (NewOp.getNode())
6610 // Handle all 128-bit wide vectors with 4 elements, and match them with
6611 // several different shuffle types.
6612 if (NumElems == 4 && VT.getSizeInBits() == 128)
6613 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6615 // Handle general 256-bit shuffles
6616 if (VT.is256BitVector())
6617 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6623 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6624 SelectionDAG &DAG) const {
6625 EVT VT = Op.getValueType();
6626 DebugLoc dl = Op.getDebugLoc();
6628 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6631 if (VT.getSizeInBits() == 8) {
6632 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6633 Op.getOperand(0), Op.getOperand(1));
6634 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6635 DAG.getValueType(VT));
6636 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6637 } else if (VT.getSizeInBits() == 16) {
6638 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6639 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6641 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6642 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6643 DAG.getNode(ISD::BITCAST, dl,
6647 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6648 Op.getOperand(0), Op.getOperand(1));
6649 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6650 DAG.getValueType(VT));
6651 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6652 } else if (VT == MVT::f32) {
6653 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6654 // the result back to FR32 register. It's only worth matching if the
6655 // result has a single use which is a store or a bitcast to i32. And in
6656 // the case of a store, it's not worth it if the index is a constant 0,
6657 // because a MOVSSmr can be used instead, which is smaller and faster.
6658 if (!Op.hasOneUse())
6660 SDNode *User = *Op.getNode()->use_begin();
6661 if ((User->getOpcode() != ISD::STORE ||
6662 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6663 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6664 (User->getOpcode() != ISD::BITCAST ||
6665 User->getValueType(0) != MVT::i32))
6667 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6668 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6671 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6672 } else if (VT == MVT::i32 || VT == MVT::i64) {
6673 // ExtractPS/pextrq works with constant index.
6674 if (isa<ConstantSDNode>(Op.getOperand(1)))
6682 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6683 SelectionDAG &DAG) const {
6684 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6687 SDValue Vec = Op.getOperand(0);
6688 EVT VecVT = Vec.getValueType();
6690 // If this is a 256-bit vector result, first extract the 128-bit vector and
6691 // then extract the element from the 128-bit vector.
6692 if (VecVT.getSizeInBits() == 256) {
6693 DebugLoc dl = Op.getNode()->getDebugLoc();
6694 unsigned NumElems = VecVT.getVectorNumElements();
6695 SDValue Idx = Op.getOperand(1);
6696 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6698 // Get the 128-bit vector.
6699 bool Upper = IdxVal >= NumElems/2;
6700 Vec = Extract128BitVector(Vec,
6701 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6703 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6704 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6707 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6709 if (Subtarget->hasSSE41()) {
6710 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6715 EVT VT = Op.getValueType();
6716 DebugLoc dl = Op.getDebugLoc();
6717 // TODO: handle v16i8.
6718 if (VT.getSizeInBits() == 16) {
6719 SDValue Vec = Op.getOperand(0);
6720 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6722 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6723 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6724 DAG.getNode(ISD::BITCAST, dl,
6727 // Transform it so it match pextrw which produces a 32-bit result.
6728 EVT EltVT = MVT::i32;
6729 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6730 Op.getOperand(0), Op.getOperand(1));
6731 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6732 DAG.getValueType(VT));
6733 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6734 } else if (VT.getSizeInBits() == 32) {
6735 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6739 // SHUFPS the element to the lowest double word, then movss.
6740 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6741 EVT VVT = Op.getOperand(0).getValueType();
6742 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6743 DAG.getUNDEF(VVT), Mask);
6744 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6745 DAG.getIntPtrConstant(0));
6746 } else if (VT.getSizeInBits() == 64) {
6747 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6748 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6749 // to match extract_elt for f64.
6750 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6754 // UNPCKHPD the element to the lowest double word, then movsd.
6755 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6756 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6757 int Mask[2] = { 1, -1 };
6758 EVT VVT = Op.getOperand(0).getValueType();
6759 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6760 DAG.getUNDEF(VVT), Mask);
6761 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6762 DAG.getIntPtrConstant(0));
6769 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6770 SelectionDAG &DAG) const {
6771 EVT VT = Op.getValueType();
6772 EVT EltVT = VT.getVectorElementType();
6773 DebugLoc dl = Op.getDebugLoc();
6775 SDValue N0 = Op.getOperand(0);
6776 SDValue N1 = Op.getOperand(1);
6777 SDValue N2 = Op.getOperand(2);
6779 if (VT.getSizeInBits() == 256)
6782 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6783 isa<ConstantSDNode>(N2)) {
6785 if (VT == MVT::v8i16)
6786 Opc = X86ISD::PINSRW;
6787 else if (VT == MVT::v16i8)
6788 Opc = X86ISD::PINSRB;
6790 Opc = X86ISD::PINSRB;
6792 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
6794 if (N1.getValueType() != MVT::i32)
6795 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6796 if (N2.getValueType() != MVT::i32)
6797 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6798 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
6799 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
6800 // Bits [7:6] of the constant are the source select. This will always be
6801 // zero here. The DAG Combiner may combine an extract_elt index into these
6802 // bits. For example (insert (extract, 3), 2) could be matched by putting
6803 // the '3' into bits [7:6] of X86ISD::INSERTPS.
6804 // Bits [5:4] of the constant are the destination select. This is the
6805 // value of the incoming immediate.
6806 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
6807 // combine either bitwise AND or insert of float 0.0 to set these bits.
6808 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
6809 // Create this as a scalar to vector..
6810 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
6811 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
6812 } else if ((EltVT == MVT::i32 || EltVT == MVT::i64) &&
6813 isa<ConstantSDNode>(N2)) {
6814 // PINSR* works with constant index.
6821 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
6822 EVT VT = Op.getValueType();
6823 EVT EltVT = VT.getVectorElementType();
6825 DebugLoc dl = Op.getDebugLoc();
6826 SDValue N0 = Op.getOperand(0);
6827 SDValue N1 = Op.getOperand(1);
6828 SDValue N2 = Op.getOperand(2);
6830 // If this is a 256-bit vector result, first extract the 128-bit vector,
6831 // insert the element into the extracted half and then place it back.
6832 if (VT.getSizeInBits() == 256) {
6833 if (!isa<ConstantSDNode>(N2))
6836 // Get the desired 128-bit vector half.
6837 unsigned NumElems = VT.getVectorNumElements();
6838 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
6839 bool Upper = IdxVal >= NumElems/2;
6840 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
6841 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
6843 // Insert the element into the desired half.
6844 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
6845 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
6847 // Insert the changed part back to the 256-bit vector
6848 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
6851 if (Subtarget->hasSSE41())
6852 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
6854 if (EltVT == MVT::i8)
6857 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
6858 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
6859 // as its second argument.
6860 if (N1.getValueType() != MVT::i32)
6861 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
6862 if (N2.getValueType() != MVT::i32)
6863 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
6864 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
6870 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6871 LLVMContext *Context = DAG.getContext();
6872 DebugLoc dl = Op.getDebugLoc();
6873 EVT OpVT = Op.getValueType();
6875 // If this is a 256-bit vector result, first insert into a 128-bit
6876 // vector and then insert into the 256-bit vector.
6877 if (OpVT.getSizeInBits() > 128) {
6878 // Insert into a 128-bit vector.
6879 EVT VT128 = EVT::getVectorVT(*Context,
6880 OpVT.getVectorElementType(),
6881 OpVT.getVectorNumElements() / 2);
6883 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
6885 // Insert the 128-bit vector.
6886 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
6887 DAG.getConstant(0, MVT::i32),
6891 if (Op.getValueType() == MVT::v1i64 &&
6892 Op.getOperand(0).getValueType() == MVT::i64)
6893 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
6895 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
6896 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
6897 "Expected an SSE type!");
6898 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
6899 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
6902 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
6903 // a simple subregister reference or explicit instructions to grab
6904 // upper bits of a vector.
6906 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6907 if (Subtarget->hasAVX()) {
6908 DebugLoc dl = Op.getNode()->getDebugLoc();
6909 SDValue Vec = Op.getNode()->getOperand(0);
6910 SDValue Idx = Op.getNode()->getOperand(1);
6912 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
6913 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
6914 return Extract128BitVector(Vec, Idx, DAG, dl);
6920 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
6921 // simple superregister reference or explicit instructions to insert
6922 // the upper bits of a vector.
6924 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
6925 if (Subtarget->hasAVX()) {
6926 DebugLoc dl = Op.getNode()->getDebugLoc();
6927 SDValue Vec = Op.getNode()->getOperand(0);
6928 SDValue SubVec = Op.getNode()->getOperand(1);
6929 SDValue Idx = Op.getNode()->getOperand(2);
6931 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
6932 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
6933 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
6939 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
6940 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
6941 // one of the above mentioned nodes. It has to be wrapped because otherwise
6942 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
6943 // be used to form addressing mode. These wrapped nodes will be selected
6946 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
6947 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
6949 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6951 unsigned char OpFlag = 0;
6952 unsigned WrapperKind = X86ISD::Wrapper;
6953 CodeModel::Model M = getTargetMachine().getCodeModel();
6955 if (Subtarget->isPICStyleRIPRel() &&
6956 (M == CodeModel::Small || M == CodeModel::Kernel))
6957 WrapperKind = X86ISD::WrapperRIP;
6958 else if (Subtarget->isPICStyleGOT())
6959 OpFlag = X86II::MO_GOTOFF;
6960 else if (Subtarget->isPICStyleStubPIC())
6961 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6963 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
6965 CP->getOffset(), OpFlag);
6966 DebugLoc DL = CP->getDebugLoc();
6967 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6968 // With PIC, the address is actually $g + Offset.
6970 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6971 DAG.getNode(X86ISD::GlobalBaseReg,
6972 DebugLoc(), getPointerTy()),
6979 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
6980 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
6982 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6984 unsigned char OpFlag = 0;
6985 unsigned WrapperKind = X86ISD::Wrapper;
6986 CodeModel::Model M = getTargetMachine().getCodeModel();
6988 if (Subtarget->isPICStyleRIPRel() &&
6989 (M == CodeModel::Small || M == CodeModel::Kernel))
6990 WrapperKind = X86ISD::WrapperRIP;
6991 else if (Subtarget->isPICStyleGOT())
6992 OpFlag = X86II::MO_GOTOFF;
6993 else if (Subtarget->isPICStyleStubPIC())
6994 OpFlag = X86II::MO_PIC_BASE_OFFSET;
6996 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
6998 DebugLoc DL = JT->getDebugLoc();
6999 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7001 // With PIC, the address is actually $g + Offset.
7003 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7004 DAG.getNode(X86ISD::GlobalBaseReg,
7005 DebugLoc(), getPointerTy()),
7012 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7013 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7015 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7017 unsigned char OpFlag = 0;
7018 unsigned WrapperKind = X86ISD::Wrapper;
7019 CodeModel::Model M = getTargetMachine().getCodeModel();
7021 if (Subtarget->isPICStyleRIPRel() &&
7022 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7023 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7024 OpFlag = X86II::MO_GOTPCREL;
7025 WrapperKind = X86ISD::WrapperRIP;
7026 } else if (Subtarget->isPICStyleGOT()) {
7027 OpFlag = X86II::MO_GOT;
7028 } else if (Subtarget->isPICStyleStubPIC()) {
7029 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7030 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7031 OpFlag = X86II::MO_DARWIN_NONLAZY;
7034 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7036 DebugLoc DL = Op.getDebugLoc();
7037 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7040 // With PIC, the address is actually $g + Offset.
7041 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7042 !Subtarget->is64Bit()) {
7043 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7044 DAG.getNode(X86ISD::GlobalBaseReg,
7045 DebugLoc(), getPointerTy()),
7049 // For symbols that require a load from a stub to get the address, emit the
7051 if (isGlobalStubReference(OpFlag))
7052 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7053 MachinePointerInfo::getGOT(), false, false, false, 0);
7059 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7060 // Create the TargetBlockAddressAddress node.
7061 unsigned char OpFlags =
7062 Subtarget->ClassifyBlockAddressReference();
7063 CodeModel::Model M = getTargetMachine().getCodeModel();
7064 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7065 DebugLoc dl = Op.getDebugLoc();
7066 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7067 /*isTarget=*/true, OpFlags);
7069 if (Subtarget->isPICStyleRIPRel() &&
7070 (M == CodeModel::Small || M == CodeModel::Kernel))
7071 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7073 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7075 // With PIC, the address is actually $g + Offset.
7076 if (isGlobalRelativeToPICBase(OpFlags)) {
7077 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7078 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7086 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7088 SelectionDAG &DAG) const {
7089 // Create the TargetGlobalAddress node, folding in the constant
7090 // offset if it is legal.
7091 unsigned char OpFlags =
7092 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7093 CodeModel::Model M = getTargetMachine().getCodeModel();
7095 if (OpFlags == X86II::MO_NO_FLAG &&
7096 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7097 // A direct static reference to a global.
7098 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7101 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7104 if (Subtarget->isPICStyleRIPRel() &&
7105 (M == CodeModel::Small || M == CodeModel::Kernel))
7106 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7108 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7110 // With PIC, the address is actually $g + Offset.
7111 if (isGlobalRelativeToPICBase(OpFlags)) {
7112 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7113 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7117 // For globals that require a load from a stub to get the address, emit the
7119 if (isGlobalStubReference(OpFlags))
7120 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7121 MachinePointerInfo::getGOT(), false, false, false, 0);
7123 // If there was a non-zero offset that we didn't fold, create an explicit
7126 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7127 DAG.getConstant(Offset, getPointerTy()));
7133 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7134 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7135 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7136 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7140 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7141 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7142 unsigned char OperandFlags) {
7143 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7144 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7145 DebugLoc dl = GA->getDebugLoc();
7146 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7147 GA->getValueType(0),
7151 SDValue Ops[] = { Chain, TGA, *InFlag };
7152 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7154 SDValue Ops[] = { Chain, TGA };
7155 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7158 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7159 MFI->setAdjustsStack(true);
7161 SDValue Flag = Chain.getValue(1);
7162 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7165 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7167 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7170 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7171 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7172 DAG.getNode(X86ISD::GlobalBaseReg,
7173 DebugLoc(), PtrVT), InFlag);
7174 InFlag = Chain.getValue(1);
7176 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7179 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7181 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7183 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7184 X86::RAX, X86II::MO_TLSGD);
7187 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7188 // "local exec" model.
7189 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7190 const EVT PtrVT, TLSModel::Model model,
7192 DebugLoc dl = GA->getDebugLoc();
7194 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7195 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7196 is64Bit ? 257 : 256));
7198 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7199 DAG.getIntPtrConstant(0),
7200 MachinePointerInfo(Ptr),
7201 false, false, false, 0);
7203 unsigned char OperandFlags = 0;
7204 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7206 unsigned WrapperKind = X86ISD::Wrapper;
7207 if (model == TLSModel::LocalExec) {
7208 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7209 } else if (is64Bit) {
7210 assert(model == TLSModel::InitialExec);
7211 OperandFlags = X86II::MO_GOTTPOFF;
7212 WrapperKind = X86ISD::WrapperRIP;
7214 assert(model == TLSModel::InitialExec);
7215 OperandFlags = X86II::MO_INDNTPOFF;
7218 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7220 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7221 GA->getValueType(0),
7222 GA->getOffset(), OperandFlags);
7223 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7225 if (model == TLSModel::InitialExec)
7226 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7227 MachinePointerInfo::getGOT(), false, false, false, 0);
7229 // The address of the thread local variable is the add of the thread
7230 // pointer with the offset of the variable.
7231 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7235 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7237 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7238 const GlobalValue *GV = GA->getGlobal();
7240 if (Subtarget->isTargetELF()) {
7241 // TODO: implement the "local dynamic" model
7242 // TODO: implement the "initial exec"model for pic executables
7244 // If GV is an alias then use the aliasee for determining
7245 // thread-localness.
7246 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7247 GV = GA->resolveAliasedGlobal(false);
7249 TLSModel::Model model
7250 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7253 case TLSModel::GeneralDynamic:
7254 case TLSModel::LocalDynamic: // not implemented
7255 if (Subtarget->is64Bit())
7256 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7257 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7259 case TLSModel::InitialExec:
7260 case TLSModel::LocalExec:
7261 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7262 Subtarget->is64Bit());
7264 } else if (Subtarget->isTargetDarwin()) {
7265 // Darwin only has one model of TLS. Lower to that.
7266 unsigned char OpFlag = 0;
7267 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7268 X86ISD::WrapperRIP : X86ISD::Wrapper;
7270 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7272 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7273 !Subtarget->is64Bit();
7275 OpFlag = X86II::MO_TLVP_PIC_BASE;
7277 OpFlag = X86II::MO_TLVP;
7278 DebugLoc DL = Op.getDebugLoc();
7279 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7280 GA->getValueType(0),
7281 GA->getOffset(), OpFlag);
7282 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7284 // With PIC32, the address is actually $g + Offset.
7286 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7287 DAG.getNode(X86ISD::GlobalBaseReg,
7288 DebugLoc(), getPointerTy()),
7291 // Lowering the machine isd will make sure everything is in the right
7293 SDValue Chain = DAG.getEntryNode();
7294 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7295 SDValue Args[] = { Chain, Offset };
7296 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7298 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7299 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7300 MFI->setAdjustsStack(true);
7302 // And our return value (tls address) is in the standard call return value
7304 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7305 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7307 } else if (Subtarget->isTargetWindows()) {
7308 // Just use the implicit TLS architecture
7309 // Need to generate someting similar to:
7310 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7312 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7313 // mov rcx, qword [rdx+rcx*8]
7314 // mov eax, .tls$:tlsvar
7315 // [rax+rcx] contains the address
7316 // Windows 64bit: gs:0x58
7317 // Windows 32bit: fs:__tls_array
7319 // If GV is an alias then use the aliasee for determining
7320 // thread-localness.
7321 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7322 GV = GA->resolveAliasedGlobal(false);
7323 DebugLoc dl = GA->getDebugLoc();
7324 SDValue Chain = DAG.getEntryNode();
7326 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7327 // %gs:0x58 (64-bit).
7328 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7329 ? Type::getInt8PtrTy(*DAG.getContext(),
7331 : Type::getInt32PtrTy(*DAG.getContext(),
7334 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7335 Subtarget->is64Bit()
7336 ? DAG.getIntPtrConstant(0x58)
7337 : DAG.getExternalSymbol("_tls_array",
7339 MachinePointerInfo(Ptr),
7340 false, false, false, 0);
7342 // Load the _tls_index variable
7343 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7344 if (Subtarget->is64Bit())
7345 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7346 IDX, MachinePointerInfo(), MVT::i32,
7349 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7350 false, false, false, 0);
7352 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7354 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7356 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7357 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7358 false, false, false, 0);
7360 // Get the offset of start of .tls section
7361 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7362 GA->getValueType(0),
7363 GA->getOffset(), X86II::MO_SECREL);
7364 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7366 // The address of the thread local variable is the add of the thread
7367 // pointer with the offset of the variable.
7368 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7371 llvm_unreachable("TLS not implemented for this target.");
7375 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7376 /// and take a 2 x i32 value to shift plus a shift amount.
7377 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7378 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7379 EVT VT = Op.getValueType();
7380 unsigned VTBits = VT.getSizeInBits();
7381 DebugLoc dl = Op.getDebugLoc();
7382 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7383 SDValue ShOpLo = Op.getOperand(0);
7384 SDValue ShOpHi = Op.getOperand(1);
7385 SDValue ShAmt = Op.getOperand(2);
7386 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7387 DAG.getConstant(VTBits - 1, MVT::i8))
7388 : DAG.getConstant(0, VT);
7391 if (Op.getOpcode() == ISD::SHL_PARTS) {
7392 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7393 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7395 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7396 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7399 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7400 DAG.getConstant(VTBits, MVT::i8));
7401 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7402 AndNode, DAG.getConstant(0, MVT::i8));
7405 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7406 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7407 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7409 if (Op.getOpcode() == ISD::SHL_PARTS) {
7410 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7411 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7413 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7414 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7417 SDValue Ops[2] = { Lo, Hi };
7418 return DAG.getMergeValues(Ops, 2, dl);
7421 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7422 SelectionDAG &DAG) const {
7423 EVT SrcVT = Op.getOperand(0).getValueType();
7425 if (SrcVT.isVector())
7428 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7429 "Unknown SINT_TO_FP to lower!");
7431 // These are really Legal; return the operand so the caller accepts it as
7433 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7435 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7436 Subtarget->is64Bit()) {
7440 DebugLoc dl = Op.getDebugLoc();
7441 unsigned Size = SrcVT.getSizeInBits()/8;
7442 MachineFunction &MF = DAG.getMachineFunction();
7443 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7444 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7445 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7447 MachinePointerInfo::getFixedStack(SSFI),
7449 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7452 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7454 SelectionDAG &DAG) const {
7456 DebugLoc DL = Op.getDebugLoc();
7458 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7460 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7462 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7464 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7466 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7467 MachineMemOperand *MMO;
7469 int SSFI = FI->getIndex();
7471 DAG.getMachineFunction()
7472 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7473 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7475 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7476 StackSlot = StackSlot.getOperand(1);
7478 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7479 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7481 Tys, Ops, array_lengthof(Ops),
7485 Chain = Result.getValue(1);
7486 SDValue InFlag = Result.getValue(2);
7488 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7489 // shouldn't be necessary except that RFP cannot be live across
7490 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7491 MachineFunction &MF = DAG.getMachineFunction();
7492 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7493 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7494 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7495 Tys = DAG.getVTList(MVT::Other);
7497 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7499 MachineMemOperand *MMO =
7500 DAG.getMachineFunction()
7501 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7502 MachineMemOperand::MOStore, SSFISize, SSFISize);
7504 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7505 Ops, array_lengthof(Ops),
7506 Op.getValueType(), MMO);
7507 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7508 MachinePointerInfo::getFixedStack(SSFI),
7509 false, false, false, 0);
7515 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7516 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7517 SelectionDAG &DAG) const {
7518 // This algorithm is not obvious. Here it is what we're trying to output:
7521 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7522 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
7526 pshufd $0x4e, %xmm0, %xmm1
7531 DebugLoc dl = Op.getDebugLoc();
7532 LLVMContext *Context = DAG.getContext();
7534 // Build some magic constants.
7535 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
7536 Constant *C0 = ConstantDataVector::get(*Context, CV0);
7537 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7539 SmallVector<Constant*,2> CV1;
7541 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7543 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7544 Constant *C1 = ConstantVector::get(CV1);
7545 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7547 // Load the 64-bit value into an XMM register.
7548 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
7550 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7551 MachinePointerInfo::getConstantPool(),
7552 false, false, false, 16);
7553 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
7554 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
7557 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7558 MachinePointerInfo::getConstantPool(),
7559 false, false, false, 16);
7560 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
7561 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7564 if (Subtarget->hasSSE3()) {
7565 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
7566 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
7568 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
7569 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
7571 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
7572 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
7576 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
7577 DAG.getIntPtrConstant(0));
7580 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7581 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7582 SelectionDAG &DAG) const {
7583 DebugLoc dl = Op.getDebugLoc();
7584 // FP constant to bias correct the final result.
7585 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7588 // Load the 32-bit value into an XMM register.
7589 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7592 // Zero out the upper parts of the register.
7593 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
7595 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7596 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7597 DAG.getIntPtrConstant(0));
7599 // Or the load with the bias.
7600 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7601 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7602 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7604 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7605 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7606 MVT::v2f64, Bias)));
7607 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7608 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7609 DAG.getIntPtrConstant(0));
7611 // Subtract the bias.
7612 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7614 // Handle final rounding.
7615 EVT DestVT = Op.getValueType();
7617 if (DestVT.bitsLT(MVT::f64)) {
7618 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7619 DAG.getIntPtrConstant(0));
7620 } else if (DestVT.bitsGT(MVT::f64)) {
7621 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7624 // Handle final rounding.
7628 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7629 SelectionDAG &DAG) const {
7630 SDValue N0 = Op.getOperand(0);
7631 DebugLoc dl = Op.getDebugLoc();
7633 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7634 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7635 // the optimization here.
7636 if (DAG.SignBitIsZero(N0))
7637 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7639 EVT SrcVT = N0.getValueType();
7640 EVT DstVT = Op.getValueType();
7641 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7642 return LowerUINT_TO_FP_i64(Op, DAG);
7643 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7644 return LowerUINT_TO_FP_i32(Op, DAG);
7645 else if (Subtarget->is64Bit() &&
7646 SrcVT == MVT::i64 && DstVT == MVT::f32)
7649 // Make a 64-bit buffer, and use it to build an FILD.
7650 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7651 if (SrcVT == MVT::i32) {
7652 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7653 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7654 getPointerTy(), StackSlot, WordOff);
7655 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7656 StackSlot, MachinePointerInfo(),
7658 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7659 OffsetSlot, MachinePointerInfo(),
7661 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7665 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7667 StackSlot, MachinePointerInfo(),
7669 // For i64 source, we need to add the appropriate power of 2 if the input
7670 // was negative. This is the same as the optimization in
7671 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7672 // we must be careful to do the computation in x87 extended precision, not
7673 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7674 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7675 MachineMemOperand *MMO =
7676 DAG.getMachineFunction()
7677 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7678 MachineMemOperand::MOLoad, 8, 8);
7680 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7681 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7682 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7685 APInt FF(32, 0x5F800000ULL);
7687 // Check whether the sign bit is set.
7688 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7689 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7692 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7693 SDValue FudgePtr = DAG.getConstantPool(
7694 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7697 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7698 SDValue Zero = DAG.getIntPtrConstant(0);
7699 SDValue Four = DAG.getIntPtrConstant(4);
7700 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7702 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7704 // Load the value out, extending it from f32 to f80.
7705 // FIXME: Avoid the extend by constructing the right constant pool?
7706 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7707 FudgePtr, MachinePointerInfo::getConstantPool(),
7708 MVT::f32, false, false, 4);
7709 // Extend everything to 80 bits to force it to be done on x87.
7710 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7711 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7714 std::pair<SDValue,SDValue> X86TargetLowering::
7715 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
7716 DebugLoc DL = Op.getDebugLoc();
7718 EVT DstTy = Op.getValueType();
7720 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
7721 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7725 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7726 DstTy.getSimpleVT() >= MVT::i16 &&
7727 "Unknown FP_TO_INT to lower!");
7729 // These are really Legal.
7730 if (DstTy == MVT::i32 &&
7731 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7732 return std::make_pair(SDValue(), SDValue());
7733 if (Subtarget->is64Bit() &&
7734 DstTy == MVT::i64 &&
7735 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7736 return std::make_pair(SDValue(), SDValue());
7738 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
7739 // stack slot, or into the FTOL runtime function.
7740 MachineFunction &MF = DAG.getMachineFunction();
7741 unsigned MemSize = DstTy.getSizeInBits()/8;
7742 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7743 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7746 if (!IsSigned && isIntegerTypeFTOL(DstTy))
7747 Opc = X86ISD::WIN_FTOL;
7749 switch (DstTy.getSimpleVT().SimpleTy) {
7750 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7751 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7752 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7753 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7756 SDValue Chain = DAG.getEntryNode();
7757 SDValue Value = Op.getOperand(0);
7758 EVT TheVT = Op.getOperand(0).getValueType();
7759 // FIXME This causes a redundant load/store if the SSE-class value is already
7760 // in memory, such as if it is on the callstack.
7761 if (isScalarFPTypeInSSEReg(TheVT)) {
7762 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7763 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7764 MachinePointerInfo::getFixedStack(SSFI),
7766 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7768 Chain, StackSlot, DAG.getValueType(TheVT)
7771 MachineMemOperand *MMO =
7772 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7773 MachineMemOperand::MOLoad, MemSize, MemSize);
7774 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7776 Chain = Value.getValue(1);
7777 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7778 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7781 MachineMemOperand *MMO =
7782 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7783 MachineMemOperand::MOStore, MemSize, MemSize);
7785 if (Opc != X86ISD::WIN_FTOL) {
7786 // Build the FP_TO_INT*_IN_MEM
7787 SDValue Ops[] = { Chain, Value, StackSlot };
7788 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7789 Ops, 3, DstTy, MMO);
7790 return std::make_pair(FIST, StackSlot);
7792 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
7793 DAG.getVTList(MVT::Other, MVT::Glue),
7795 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
7796 MVT::i32, ftol.getValue(1));
7797 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
7798 MVT::i32, eax.getValue(2));
7799 SDValue Ops[] = { eax, edx };
7800 SDValue pair = IsReplace
7801 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
7802 : DAG.getMergeValues(Ops, 2, DL);
7803 return std::make_pair(pair, SDValue());
7807 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7808 SelectionDAG &DAG) const {
7809 if (Op.getValueType().isVector())
7812 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7813 /*IsSigned=*/ true, /*IsReplace=*/ false);
7814 SDValue FIST = Vals.first, StackSlot = Vals.second;
7815 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7816 if (FIST.getNode() == 0) return Op;
7818 if (StackSlot.getNode())
7820 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7821 FIST, StackSlot, MachinePointerInfo(),
7822 false, false, false, 0);
7824 // The node is the result.
7828 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7829 SelectionDAG &DAG) const {
7830 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
7831 /*IsSigned=*/ false, /*IsReplace=*/ false);
7832 SDValue FIST = Vals.first, StackSlot = Vals.second;
7833 assert(FIST.getNode() && "Unexpected failure");
7835 if (StackSlot.getNode())
7837 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7838 FIST, StackSlot, MachinePointerInfo(),
7839 false, false, false, 0);
7841 // The node is the result.
7845 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7846 SelectionDAG &DAG) const {
7847 LLVMContext *Context = DAG.getContext();
7848 DebugLoc dl = Op.getDebugLoc();
7849 EVT VT = Op.getValueType();
7852 EltVT = VT.getVectorElementType();
7854 if (EltVT == MVT::f64) {
7855 C = ConstantVector::getSplat(2,
7856 ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7858 C = ConstantVector::getSplat(4,
7859 ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7861 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7862 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7863 MachinePointerInfo::getConstantPool(),
7864 false, false, false, 16);
7865 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
7868 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
7869 LLVMContext *Context = DAG.getContext();
7870 DebugLoc dl = Op.getDebugLoc();
7871 EVT VT = Op.getValueType();
7873 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
7874 if (VT.isVector()) {
7875 EltVT = VT.getVectorElementType();
7876 NumElts = VT.getVectorNumElements();
7879 if (EltVT == MVT::f64)
7880 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
7882 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
7883 C = ConstantVector::getSplat(NumElts, C);
7884 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7885 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7886 MachinePointerInfo::getConstantPool(),
7887 false, false, false, 16);
7888 if (VT.isVector()) {
7889 MVT XORVT = VT.getSizeInBits() == 128 ? MVT::v2i64 : MVT::v4i64;
7890 return DAG.getNode(ISD::BITCAST, dl, VT,
7891 DAG.getNode(ISD::XOR, dl, XORVT,
7892 DAG.getNode(ISD::BITCAST, dl, XORVT,
7894 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
7896 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
7900 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
7901 LLVMContext *Context = DAG.getContext();
7902 SDValue Op0 = Op.getOperand(0);
7903 SDValue Op1 = Op.getOperand(1);
7904 DebugLoc dl = Op.getDebugLoc();
7905 EVT VT = Op.getValueType();
7906 EVT SrcVT = Op1.getValueType();
7908 // If second operand is smaller, extend it first.
7909 if (SrcVT.bitsLT(VT)) {
7910 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
7913 // And if it is bigger, shrink it first.
7914 if (SrcVT.bitsGT(VT)) {
7915 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
7919 // At this point the operands and the result should have the same
7920 // type, and that won't be f80 since that is not custom lowered.
7922 // First get the sign bit of second operand.
7923 SmallVector<Constant*,4> CV;
7924 if (SrcVT == MVT::f64) {
7925 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
7926 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7928 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
7929 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7930 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7931 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7933 Constant *C = ConstantVector::get(CV);
7934 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7935 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
7936 MachinePointerInfo::getConstantPool(),
7937 false, false, false, 16);
7938 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
7940 // Shift sign bit right or left if the two operands have different types.
7941 if (SrcVT.bitsGT(VT)) {
7942 // Op0 is MVT::f32, Op1 is MVT::f64.
7943 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
7944 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
7945 DAG.getConstant(32, MVT::i32));
7946 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
7947 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
7948 DAG.getIntPtrConstant(0));
7951 // Clear first operand sign bit.
7953 if (VT == MVT::f64) {
7954 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
7955 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
7957 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
7958 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7959 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7960 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
7962 C = ConstantVector::get(CV);
7963 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
7964 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
7965 MachinePointerInfo::getConstantPool(),
7966 false, false, false, 16);
7967 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
7969 // Or the value with the sign bit.
7970 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
7973 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
7974 SDValue N0 = Op.getOperand(0);
7975 DebugLoc dl = Op.getDebugLoc();
7976 EVT VT = Op.getValueType();
7978 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
7979 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
7980 DAG.getConstant(1, VT));
7981 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
7984 /// Emit nodes that will be selected as "test Op0,Op0", or something
7986 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
7987 SelectionDAG &DAG) const {
7988 DebugLoc dl = Op.getDebugLoc();
7990 // CF and OF aren't always set the way we want. Determine which
7991 // of these we need.
7992 bool NeedCF = false;
7993 bool NeedOF = false;
7996 case X86::COND_A: case X86::COND_AE:
7997 case X86::COND_B: case X86::COND_BE:
8000 case X86::COND_G: case X86::COND_GE:
8001 case X86::COND_L: case X86::COND_LE:
8002 case X86::COND_O: case X86::COND_NO:
8007 // See if we can use the EFLAGS value from the operand instead of
8008 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8009 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8010 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8011 // Emit a CMP with 0, which is the TEST pattern.
8012 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8013 DAG.getConstant(0, Op.getValueType()));
8015 unsigned Opcode = 0;
8016 unsigned NumOperands = 0;
8017 switch (Op.getNode()->getOpcode()) {
8019 // Due to an isel shortcoming, be conservative if this add is likely to be
8020 // selected as part of a load-modify-store instruction. When the root node
8021 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8022 // uses of other nodes in the match, such as the ADD in this case. This
8023 // leads to the ADD being left around and reselected, with the result being
8024 // two adds in the output. Alas, even if none our users are stores, that
8025 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8026 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8027 // climbing the DAG back to the root, and it doesn't seem to be worth the
8029 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8030 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8031 if (UI->getOpcode() != ISD::CopyToReg &&
8032 UI->getOpcode() != ISD::SETCC &&
8033 UI->getOpcode() != ISD::STORE)
8036 if (ConstantSDNode *C =
8037 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8038 // An add of one will be selected as an INC.
8039 if (C->getAPIntValue() == 1) {
8040 Opcode = X86ISD::INC;
8045 // An add of negative one (subtract of one) will be selected as a DEC.
8046 if (C->getAPIntValue().isAllOnesValue()) {
8047 Opcode = X86ISD::DEC;
8053 // Otherwise use a regular EFLAGS-setting add.
8054 Opcode = X86ISD::ADD;
8058 // If the primary and result isn't used, don't bother using X86ISD::AND,
8059 // because a TEST instruction will be better.
8060 bool NonFlagUse = false;
8061 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8062 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8064 unsigned UOpNo = UI.getOperandNo();
8065 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8066 // Look pass truncate.
8067 UOpNo = User->use_begin().getOperandNo();
8068 User = *User->use_begin();
8071 if (User->getOpcode() != ISD::BRCOND &&
8072 User->getOpcode() != ISD::SETCC &&
8073 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8086 // Due to the ISEL shortcoming noted above, be conservative if this op is
8087 // likely to be selected as part of a load-modify-store instruction.
8088 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8089 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8090 if (UI->getOpcode() == ISD::STORE)
8093 // Otherwise use a regular EFLAGS-setting instruction.
8094 switch (Op.getNode()->getOpcode()) {
8095 default: llvm_unreachable("unexpected operator!");
8096 case ISD::SUB: Opcode = X86ISD::SUB; break;
8097 case ISD::OR: Opcode = X86ISD::OR; break;
8098 case ISD::XOR: Opcode = X86ISD::XOR; break;
8099 case ISD::AND: Opcode = X86ISD::AND; break;
8111 return SDValue(Op.getNode(), 1);
8118 // Emit a CMP with 0, which is the TEST pattern.
8119 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8120 DAG.getConstant(0, Op.getValueType()));
8122 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8123 SmallVector<SDValue, 4> Ops;
8124 for (unsigned i = 0; i != NumOperands; ++i)
8125 Ops.push_back(Op.getOperand(i));
8127 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8128 DAG.ReplaceAllUsesWith(Op, New);
8129 return SDValue(New.getNode(), 1);
8132 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8134 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8135 SelectionDAG &DAG) const {
8136 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8137 if (C->getAPIntValue() == 0)
8138 return EmitTest(Op0, X86CC, DAG);
8140 DebugLoc dl = Op0.getDebugLoc();
8141 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8144 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8145 /// if it's possible.
8146 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8147 DebugLoc dl, SelectionDAG &DAG) const {
8148 SDValue Op0 = And.getOperand(0);
8149 SDValue Op1 = And.getOperand(1);
8150 if (Op0.getOpcode() == ISD::TRUNCATE)
8151 Op0 = Op0.getOperand(0);
8152 if (Op1.getOpcode() == ISD::TRUNCATE)
8153 Op1 = Op1.getOperand(0);
8156 if (Op1.getOpcode() == ISD::SHL)
8157 std::swap(Op0, Op1);
8158 if (Op0.getOpcode() == ISD::SHL) {
8159 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8160 if (And00C->getZExtValue() == 1) {
8161 // If we looked past a truncate, check that it's only truncating away
8163 unsigned BitWidth = Op0.getValueSizeInBits();
8164 unsigned AndBitWidth = And.getValueSizeInBits();
8165 if (BitWidth > AndBitWidth) {
8166 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8167 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8168 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8172 RHS = Op0.getOperand(1);
8174 } else if (Op1.getOpcode() == ISD::Constant) {
8175 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8176 uint64_t AndRHSVal = AndRHS->getZExtValue();
8177 SDValue AndLHS = Op0;
8179 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
8180 LHS = AndLHS.getOperand(0);
8181 RHS = AndLHS.getOperand(1);
8184 // Use BT if the immediate can't be encoded in a TEST instruction.
8185 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
8187 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
8191 if (LHS.getNode()) {
8192 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8193 // instruction. Since the shift amount is in-range-or-undefined, we know
8194 // that doing a bittest on the i32 value is ok. We extend to i32 because
8195 // the encoding for the i16 version is larger than the i32 version.
8196 // Also promote i16 to i32 for performance / code size reason.
8197 if (LHS.getValueType() == MVT::i8 ||
8198 LHS.getValueType() == MVT::i16)
8199 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8201 // If the operand types disagree, extend the shift amount to match. Since
8202 // BT ignores high bits (like shifts) we can use anyextend.
8203 if (LHS.getValueType() != RHS.getValueType())
8204 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8206 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8207 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8208 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8209 DAG.getConstant(Cond, MVT::i8), BT);
8215 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8217 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8219 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8220 SDValue Op0 = Op.getOperand(0);
8221 SDValue Op1 = Op.getOperand(1);
8222 DebugLoc dl = Op.getDebugLoc();
8223 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8225 // Optimize to BT if possible.
8226 // Lower (X & (1 << N)) == 0 to BT(X, N).
8227 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8228 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8229 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8230 Op1.getOpcode() == ISD::Constant &&
8231 cast<ConstantSDNode>(Op1)->isNullValue() &&
8232 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8233 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8234 if (NewSetCC.getNode())
8238 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8240 if (Op1.getOpcode() == ISD::Constant &&
8241 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8242 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8243 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8245 // If the input is a setcc, then reuse the input setcc or use a new one with
8246 // the inverted condition.
8247 if (Op0.getOpcode() == X86ISD::SETCC) {
8248 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8249 bool Invert = (CC == ISD::SETNE) ^
8250 cast<ConstantSDNode>(Op1)->isNullValue();
8251 if (!Invert) return Op0;
8253 CCode = X86::GetOppositeBranchCondition(CCode);
8254 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8255 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8259 bool isFP = Op1.getValueType().isFloatingPoint();
8260 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8261 if (X86CC == X86::COND_INVALID)
8264 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8265 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8266 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8269 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8270 // ones, and then concatenate the result back.
8271 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
8272 EVT VT = Op.getValueType();
8274 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8275 "Unsupported value type for operation");
8277 int NumElems = VT.getVectorNumElements();
8278 DebugLoc dl = Op.getDebugLoc();
8279 SDValue CC = Op.getOperand(2);
8280 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8281 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8283 // Extract the LHS vectors
8284 SDValue LHS = Op.getOperand(0);
8285 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8286 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8288 // Extract the RHS vectors
8289 SDValue RHS = Op.getOperand(1);
8290 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8291 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8293 // Issue the operation on the smaller types and concatenate the result back
8294 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8295 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8296 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8297 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8298 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8302 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8304 SDValue Op0 = Op.getOperand(0);
8305 SDValue Op1 = Op.getOperand(1);
8306 SDValue CC = Op.getOperand(2);
8307 EVT VT = Op.getValueType();
8308 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8309 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8310 DebugLoc dl = Op.getDebugLoc();
8314 EVT EltVT = Op0.getValueType().getVectorElementType();
8315 assert(EltVT == MVT::f32 || EltVT == MVT::f64); (void)EltVT;
8319 // SSE Condition code mapping:
8328 switch (SetCCOpcode) {
8331 case ISD::SETEQ: SSECC = 0; break;
8333 case ISD::SETGT: Swap = true; // Fallthrough
8335 case ISD::SETOLT: SSECC = 1; break;
8337 case ISD::SETGE: Swap = true; // Fallthrough
8339 case ISD::SETOLE: SSECC = 2; break;
8340 case ISD::SETUO: SSECC = 3; break;
8342 case ISD::SETNE: SSECC = 4; break;
8343 case ISD::SETULE: Swap = true;
8344 case ISD::SETUGE: SSECC = 5; break;
8345 case ISD::SETULT: Swap = true;
8346 case ISD::SETUGT: SSECC = 6; break;
8347 case ISD::SETO: SSECC = 7; break;
8350 std::swap(Op0, Op1);
8352 // In the two special cases we can't handle, emit two comparisons.
8354 if (SetCCOpcode == ISD::SETUEQ) {
8356 UNORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8357 DAG.getConstant(3, MVT::i8));
8358 EQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8359 DAG.getConstant(0, MVT::i8));
8360 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8361 } else if (SetCCOpcode == ISD::SETONE) {
8363 ORD = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8364 DAG.getConstant(7, MVT::i8));
8365 NEQ = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8366 DAG.getConstant(4, MVT::i8));
8367 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8369 llvm_unreachable("Illegal FP comparison");
8371 // Handle all other FP comparisons here.
8372 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
8373 DAG.getConstant(SSECC, MVT::i8));
8376 // Break 256-bit integer vector compare into smaller ones.
8377 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
8378 return Lower256IntVSETCC(Op, DAG);
8380 // We are handling one of the integer comparisons here. Since SSE only has
8381 // GT and EQ comparisons for integer, swapping operands and multiple
8382 // operations may be required for some comparisons.
8384 bool Swap = false, Invert = false, FlipSigns = false;
8386 switch (SetCCOpcode) {
8388 case ISD::SETNE: Invert = true;
8389 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
8390 case ISD::SETLT: Swap = true;
8391 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
8392 case ISD::SETGE: Swap = true;
8393 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
8394 case ISD::SETULT: Swap = true;
8395 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
8396 case ISD::SETUGE: Swap = true;
8397 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
8400 std::swap(Op0, Op1);
8402 // Check that the operation in question is available (most are plain SSE2,
8403 // but PCMPGTQ and PCMPEQQ have different requirements).
8404 if (Opc == X86ISD::PCMPGT && VT == MVT::v2i64 && !Subtarget->hasSSE42())
8406 if (Opc == X86ISD::PCMPEQ && VT == MVT::v2i64 && !Subtarget->hasSSE41())
8409 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8410 // bits of the inputs before performing those operations.
8412 EVT EltVT = VT.getVectorElementType();
8413 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8415 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8416 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8418 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8419 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8422 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8424 // If the logical-not of the result is required, perform that now.
8426 Result = DAG.getNOT(dl, Result, VT);
8431 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8432 static bool isX86LogicalCmp(SDValue Op) {
8433 unsigned Opc = Op.getNode()->getOpcode();
8434 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8436 if (Op.getResNo() == 1 &&
8437 (Opc == X86ISD::ADD ||
8438 Opc == X86ISD::SUB ||
8439 Opc == X86ISD::ADC ||
8440 Opc == X86ISD::SBB ||
8441 Opc == X86ISD::SMUL ||
8442 Opc == X86ISD::UMUL ||
8443 Opc == X86ISD::INC ||
8444 Opc == X86ISD::DEC ||
8445 Opc == X86ISD::OR ||
8446 Opc == X86ISD::XOR ||
8447 Opc == X86ISD::AND))
8450 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8456 static bool isZero(SDValue V) {
8457 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8458 return C && C->isNullValue();
8461 static bool isAllOnes(SDValue V) {
8462 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8463 return C && C->isAllOnesValue();
8466 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8467 bool addTest = true;
8468 SDValue Cond = Op.getOperand(0);
8469 SDValue Op1 = Op.getOperand(1);
8470 SDValue Op2 = Op.getOperand(2);
8471 DebugLoc DL = Op.getDebugLoc();
8474 if (Cond.getOpcode() == ISD::SETCC) {
8475 SDValue NewCond = LowerSETCC(Cond, DAG);
8476 if (NewCond.getNode())
8480 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8481 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8482 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8483 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8484 if (Cond.getOpcode() == X86ISD::SETCC &&
8485 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8486 isZero(Cond.getOperand(1).getOperand(1))) {
8487 SDValue Cmp = Cond.getOperand(1);
8489 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8491 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8492 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8493 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8495 SDValue CmpOp0 = Cmp.getOperand(0);
8496 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8497 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8499 SDValue Res = // Res = 0 or -1.
8500 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8501 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8503 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8504 Res = DAG.getNOT(DL, Res, Res.getValueType());
8506 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8507 if (N2C == 0 || !N2C->isNullValue())
8508 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8513 // Look past (and (setcc_carry (cmp ...)), 1).
8514 if (Cond.getOpcode() == ISD::AND &&
8515 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8516 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8517 if (C && C->getAPIntValue() == 1)
8518 Cond = Cond.getOperand(0);
8521 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8522 // setting operand in place of the X86ISD::SETCC.
8523 unsigned CondOpcode = Cond.getOpcode();
8524 if (CondOpcode == X86ISD::SETCC ||
8525 CondOpcode == X86ISD::SETCC_CARRY) {
8526 CC = Cond.getOperand(0);
8528 SDValue Cmp = Cond.getOperand(1);
8529 unsigned Opc = Cmp.getOpcode();
8530 EVT VT = Op.getValueType();
8532 bool IllegalFPCMov = false;
8533 if (VT.isFloatingPoint() && !VT.isVector() &&
8534 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8535 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8537 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8538 Opc == X86ISD::BT) { // FIXME
8542 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8543 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8544 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8545 Cond.getOperand(0).getValueType() != MVT::i8)) {
8546 SDValue LHS = Cond.getOperand(0);
8547 SDValue RHS = Cond.getOperand(1);
8551 switch (CondOpcode) {
8552 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8553 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8554 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8555 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8556 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8557 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8558 default: llvm_unreachable("unexpected overflowing operator");
8560 if (CondOpcode == ISD::UMULO)
8561 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8564 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8566 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
8568 if (CondOpcode == ISD::UMULO)
8569 Cond = X86Op.getValue(2);
8571 Cond = X86Op.getValue(1);
8573 CC = DAG.getConstant(X86Cond, MVT::i8);
8578 // Look pass the truncate.
8579 if (Cond.getOpcode() == ISD::TRUNCATE)
8580 Cond = Cond.getOperand(0);
8582 // We know the result of AND is compared against zero. Try to match
8584 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8585 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8586 if (NewSetCC.getNode()) {
8587 CC = NewSetCC.getOperand(0);
8588 Cond = NewSetCC.getOperand(1);
8595 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8596 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8599 // a < b ? -1 : 0 -> RES = ~setcc_carry
8600 // a < b ? 0 : -1 -> RES = setcc_carry
8601 // a >= b ? -1 : 0 -> RES = setcc_carry
8602 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8603 if (Cond.getOpcode() == X86ISD::CMP) {
8604 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8606 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8607 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8608 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8609 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8610 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8611 return DAG.getNOT(DL, Res, Res.getValueType());
8616 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8617 // condition is true.
8618 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8619 SDValue Ops[] = { Op2, Op1, CC, Cond };
8620 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8623 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8624 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8625 // from the AND / OR.
8626 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8627 Opc = Op.getOpcode();
8628 if (Opc != ISD::OR && Opc != ISD::AND)
8630 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8631 Op.getOperand(0).hasOneUse() &&
8632 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8633 Op.getOperand(1).hasOneUse());
8636 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8637 // 1 and that the SETCC node has a single use.
8638 static bool isXor1OfSetCC(SDValue Op) {
8639 if (Op.getOpcode() != ISD::XOR)
8641 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8642 if (N1C && N1C->getAPIntValue() == 1) {
8643 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8644 Op.getOperand(0).hasOneUse();
8649 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8650 bool addTest = true;
8651 SDValue Chain = Op.getOperand(0);
8652 SDValue Cond = Op.getOperand(1);
8653 SDValue Dest = Op.getOperand(2);
8654 DebugLoc dl = Op.getDebugLoc();
8656 bool Inverted = false;
8658 if (Cond.getOpcode() == ISD::SETCC) {
8659 // Check for setcc([su]{add,sub,mul}o == 0).
8660 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
8661 isa<ConstantSDNode>(Cond.getOperand(1)) &&
8662 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
8663 Cond.getOperand(0).getResNo() == 1 &&
8664 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
8665 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
8666 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
8667 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
8668 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
8669 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
8671 Cond = Cond.getOperand(0);
8673 SDValue NewCond = LowerSETCC(Cond, DAG);
8674 if (NewCond.getNode())
8679 // FIXME: LowerXALUO doesn't handle these!!
8680 else if (Cond.getOpcode() == X86ISD::ADD ||
8681 Cond.getOpcode() == X86ISD::SUB ||
8682 Cond.getOpcode() == X86ISD::SMUL ||
8683 Cond.getOpcode() == X86ISD::UMUL)
8684 Cond = LowerXALUO(Cond, DAG);
8687 // Look pass (and (setcc_carry (cmp ...)), 1).
8688 if (Cond.getOpcode() == ISD::AND &&
8689 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8690 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8691 if (C && C->getAPIntValue() == 1)
8692 Cond = Cond.getOperand(0);
8695 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8696 // setting operand in place of the X86ISD::SETCC.
8697 unsigned CondOpcode = Cond.getOpcode();
8698 if (CondOpcode == X86ISD::SETCC ||
8699 CondOpcode == X86ISD::SETCC_CARRY) {
8700 CC = Cond.getOperand(0);
8702 SDValue Cmp = Cond.getOperand(1);
8703 unsigned Opc = Cmp.getOpcode();
8704 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8705 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8709 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8713 // These can only come from an arithmetic instruction with overflow,
8714 // e.g. SADDO, UADDO.
8715 Cond = Cond.getNode()->getOperand(1);
8721 CondOpcode = Cond.getOpcode();
8722 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
8723 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
8724 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
8725 Cond.getOperand(0).getValueType() != MVT::i8)) {
8726 SDValue LHS = Cond.getOperand(0);
8727 SDValue RHS = Cond.getOperand(1);
8731 switch (CondOpcode) {
8732 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
8733 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
8734 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
8735 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
8736 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
8737 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
8738 default: llvm_unreachable("unexpected overflowing operator");
8741 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
8742 if (CondOpcode == ISD::UMULO)
8743 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
8746 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
8748 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
8750 if (CondOpcode == ISD::UMULO)
8751 Cond = X86Op.getValue(2);
8753 Cond = X86Op.getValue(1);
8755 CC = DAG.getConstant(X86Cond, MVT::i8);
8759 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8760 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8761 if (CondOpc == ISD::OR) {
8762 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8763 // two branches instead of an explicit OR instruction with a
8765 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8766 isX86LogicalCmp(Cmp)) {
8767 CC = Cond.getOperand(0).getOperand(0);
8768 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8769 Chain, Dest, CC, Cmp);
8770 CC = Cond.getOperand(1).getOperand(0);
8774 } else { // ISD::AND
8775 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8776 // two branches instead of an explicit AND instruction with a
8777 // separate test. However, we only do this if this block doesn't
8778 // have a fall-through edge, because this requires an explicit
8779 // jmp when the condition is false.
8780 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8781 isX86LogicalCmp(Cmp) &&
8782 Op.getNode()->hasOneUse()) {
8783 X86::CondCode CCode =
8784 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8785 CCode = X86::GetOppositeBranchCondition(CCode);
8786 CC = DAG.getConstant(CCode, MVT::i8);
8787 SDNode *User = *Op.getNode()->use_begin();
8788 // Look for an unconditional branch following this conditional branch.
8789 // We need this because we need to reverse the successors in order
8790 // to implement FCMP_OEQ.
8791 if (User->getOpcode() == ISD::BR) {
8792 SDValue FalseBB = User->getOperand(1);
8794 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8795 assert(NewBR == User);
8799 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8800 Chain, Dest, CC, Cmp);
8801 X86::CondCode CCode =
8802 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8803 CCode = X86::GetOppositeBranchCondition(CCode);
8804 CC = DAG.getConstant(CCode, MVT::i8);
8810 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8811 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8812 // It should be transformed during dag combiner except when the condition
8813 // is set by a arithmetics with overflow node.
8814 X86::CondCode CCode =
8815 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8816 CCode = X86::GetOppositeBranchCondition(CCode);
8817 CC = DAG.getConstant(CCode, MVT::i8);
8818 Cond = Cond.getOperand(0).getOperand(1);
8820 } else if (Cond.getOpcode() == ISD::SETCC &&
8821 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
8822 // For FCMP_OEQ, we can emit
8823 // two branches instead of an explicit AND instruction with a
8824 // separate test. However, we only do this if this block doesn't
8825 // have a fall-through edge, because this requires an explicit
8826 // jmp when the condition is false.
8827 if (Op.getNode()->hasOneUse()) {
8828 SDNode *User = *Op.getNode()->use_begin();
8829 // Look for an unconditional branch following this conditional branch.
8830 // We need this because we need to reverse the successors in order
8831 // to implement FCMP_OEQ.
8832 if (User->getOpcode() == ISD::BR) {
8833 SDValue FalseBB = User->getOperand(1);
8835 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8836 assert(NewBR == User);
8840 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8841 Cond.getOperand(0), Cond.getOperand(1));
8842 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8843 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8844 Chain, Dest, CC, Cmp);
8845 CC = DAG.getConstant(X86::COND_P, MVT::i8);
8850 } else if (Cond.getOpcode() == ISD::SETCC &&
8851 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
8852 // For FCMP_UNE, we can emit
8853 // two branches instead of an explicit AND instruction with a
8854 // separate test. However, we only do this if this block doesn't
8855 // have a fall-through edge, because this requires an explicit
8856 // jmp when the condition is false.
8857 if (Op.getNode()->hasOneUse()) {
8858 SDNode *User = *Op.getNode()->use_begin();
8859 // Look for an unconditional branch following this conditional branch.
8860 // We need this because we need to reverse the successors in order
8861 // to implement FCMP_UNE.
8862 if (User->getOpcode() == ISD::BR) {
8863 SDValue FalseBB = User->getOperand(1);
8865 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8866 assert(NewBR == User);
8869 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8870 Cond.getOperand(0), Cond.getOperand(1));
8871 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8872 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8873 Chain, Dest, CC, Cmp);
8874 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
8884 // Look pass the truncate.
8885 if (Cond.getOpcode() == ISD::TRUNCATE)
8886 Cond = Cond.getOperand(0);
8888 // We know the result of AND is compared against zero. Try to match
8890 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8891 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8892 if (NewSetCC.getNode()) {
8893 CC = NewSetCC.getOperand(0);
8894 Cond = NewSetCC.getOperand(1);
8901 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8902 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8904 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8905 Chain, Dest, CC, Cond);
8909 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8910 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8911 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8912 // that the guard pages used by the OS virtual memory manager are allocated in
8913 // correct sequence.
8915 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8916 SelectionDAG &DAG) const {
8917 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8918 getTargetMachine().Options.EnableSegmentedStacks) &&
8919 "This should be used only on Windows targets or when segmented stacks "
8921 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8922 DebugLoc dl = Op.getDebugLoc();
8925 SDValue Chain = Op.getOperand(0);
8926 SDValue Size = Op.getOperand(1);
8927 // FIXME: Ensure alignment here
8929 bool Is64Bit = Subtarget->is64Bit();
8930 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8932 if (getTargetMachine().Options.EnableSegmentedStacks) {
8933 MachineFunction &MF = DAG.getMachineFunction();
8934 MachineRegisterInfo &MRI = MF.getRegInfo();
8937 // The 64 bit implementation of segmented stacks needs to clobber both r10
8938 // r11. This makes it impossible to use it along with nested parameters.
8939 const Function *F = MF.getFunction();
8941 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8943 if (I->hasNestAttr())
8944 report_fatal_error("Cannot use segmented stacks with functions that "
8945 "have nested arguments.");
8948 const TargetRegisterClass *AddrRegClass =
8949 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8950 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8951 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8952 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8953 DAG.getRegister(Vreg, SPTy));
8954 SDValue Ops1[2] = { Value, Chain };
8955 return DAG.getMergeValues(Ops1, 2, dl);
8958 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8960 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8961 Flag = Chain.getValue(1);
8962 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8964 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8965 Flag = Chain.getValue(1);
8967 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8969 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8970 return DAG.getMergeValues(Ops1, 2, dl);
8974 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8975 MachineFunction &MF = DAG.getMachineFunction();
8976 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8978 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8979 DebugLoc DL = Op.getDebugLoc();
8981 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8982 // vastart just stores the address of the VarArgsFrameIndex slot into the
8983 // memory location argument.
8984 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8986 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8987 MachinePointerInfo(SV), false, false, 0);
8991 // gp_offset (0 - 6 * 8)
8992 // fp_offset (48 - 48 + 8 * 16)
8993 // overflow_arg_area (point to parameters coming in memory).
8995 SmallVector<SDValue, 8> MemOps;
8996 SDValue FIN = Op.getOperand(1);
8998 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8999 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
9001 FIN, MachinePointerInfo(SV), false, false, 0);
9002 MemOps.push_back(Store);
9005 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9006 FIN, DAG.getIntPtrConstant(4));
9007 Store = DAG.getStore(Op.getOperand(0), DL,
9008 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
9010 FIN, MachinePointerInfo(SV, 4), false, false, 0);
9011 MemOps.push_back(Store);
9013 // Store ptr to overflow_arg_area
9014 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9015 FIN, DAG.getIntPtrConstant(4));
9016 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
9018 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9019 MachinePointerInfo(SV, 8),
9021 MemOps.push_back(Store);
9023 // Store ptr to reg_save_area.
9024 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9025 FIN, DAG.getIntPtrConstant(8));
9026 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9028 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9029 MachinePointerInfo(SV, 16), false, false, 0);
9030 MemOps.push_back(Store);
9031 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9032 &MemOps[0], MemOps.size());
9035 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9036 assert(Subtarget->is64Bit() &&
9037 "LowerVAARG only handles 64-bit va_arg!");
9038 assert((Subtarget->isTargetLinux() ||
9039 Subtarget->isTargetDarwin()) &&
9040 "Unhandled target in LowerVAARG");
9041 assert(Op.getNode()->getNumOperands() == 4);
9042 SDValue Chain = Op.getOperand(0);
9043 SDValue SrcPtr = Op.getOperand(1);
9044 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9045 unsigned Align = Op.getConstantOperandVal(3);
9046 DebugLoc dl = Op.getDebugLoc();
9048 EVT ArgVT = Op.getNode()->getValueType(0);
9049 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9050 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9053 // Decide which area this value should be read from.
9054 // TODO: Implement the AMD64 ABI in its entirety. This simple
9055 // selection mechanism works only for the basic types.
9056 if (ArgVT == MVT::f80) {
9057 llvm_unreachable("va_arg for f80 not yet implemented");
9058 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9059 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9060 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9061 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9063 llvm_unreachable("Unhandled argument type in LowerVAARG");
9067 // Sanity Check: Make sure using fp_offset makes sense.
9068 assert(!getTargetMachine().Options.UseSoftFloat &&
9069 !(DAG.getMachineFunction()
9070 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9071 Subtarget->hasSSE1());
9074 // Insert VAARG_64 node into the DAG
9075 // VAARG_64 returns two values: Variable Argument Address, Chain
9076 SmallVector<SDValue, 11> InstOps;
9077 InstOps.push_back(Chain);
9078 InstOps.push_back(SrcPtr);
9079 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9080 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9081 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9082 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9083 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9084 VTs, &InstOps[0], InstOps.size(),
9086 MachinePointerInfo(SV),
9091 Chain = VAARG.getValue(1);
9093 // Load the next argument and return it
9094 return DAG.getLoad(ArgVT, dl,
9097 MachinePointerInfo(),
9098 false, false, false, 0);
9101 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9102 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9103 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9104 SDValue Chain = Op.getOperand(0);
9105 SDValue DstPtr = Op.getOperand(1);
9106 SDValue SrcPtr = Op.getOperand(2);
9107 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9108 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9109 DebugLoc DL = Op.getDebugLoc();
9111 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9112 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9114 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9117 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
9118 // may or may not be a constant. Takes immediate version of shift as input.
9119 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
9120 SDValue SrcOp, SDValue ShAmt,
9121 SelectionDAG &DAG) {
9122 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
9124 if (isa<ConstantSDNode>(ShAmt)) {
9126 default: llvm_unreachable("Unknown target vector shift node");
9130 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9134 // Change opcode to non-immediate version
9136 default: llvm_unreachable("Unknown target vector shift node");
9137 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
9138 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
9139 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
9142 // Need to build a vector containing shift amount
9143 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
9146 ShOps[1] = DAG.getConstant(0, MVT::i32);
9147 ShOps[2] = DAG.getUNDEF(MVT::i32);
9148 ShOps[3] = DAG.getUNDEF(MVT::i32);
9149 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
9150 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9151 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
9155 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9156 DebugLoc dl = Op.getDebugLoc();
9157 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9159 default: return SDValue(); // Don't custom lower most intrinsics.
9160 // Comparison intrinsics.
9161 case Intrinsic::x86_sse_comieq_ss:
9162 case Intrinsic::x86_sse_comilt_ss:
9163 case Intrinsic::x86_sse_comile_ss:
9164 case Intrinsic::x86_sse_comigt_ss:
9165 case Intrinsic::x86_sse_comige_ss:
9166 case Intrinsic::x86_sse_comineq_ss:
9167 case Intrinsic::x86_sse_ucomieq_ss:
9168 case Intrinsic::x86_sse_ucomilt_ss:
9169 case Intrinsic::x86_sse_ucomile_ss:
9170 case Intrinsic::x86_sse_ucomigt_ss:
9171 case Intrinsic::x86_sse_ucomige_ss:
9172 case Intrinsic::x86_sse_ucomineq_ss:
9173 case Intrinsic::x86_sse2_comieq_sd:
9174 case Intrinsic::x86_sse2_comilt_sd:
9175 case Intrinsic::x86_sse2_comile_sd:
9176 case Intrinsic::x86_sse2_comigt_sd:
9177 case Intrinsic::x86_sse2_comige_sd:
9178 case Intrinsic::x86_sse2_comineq_sd:
9179 case Intrinsic::x86_sse2_ucomieq_sd:
9180 case Intrinsic::x86_sse2_ucomilt_sd:
9181 case Intrinsic::x86_sse2_ucomile_sd:
9182 case Intrinsic::x86_sse2_ucomigt_sd:
9183 case Intrinsic::x86_sse2_ucomige_sd:
9184 case Intrinsic::x86_sse2_ucomineq_sd: {
9186 ISD::CondCode CC = ISD::SETCC_INVALID;
9188 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9189 case Intrinsic::x86_sse_comieq_ss:
9190 case Intrinsic::x86_sse2_comieq_sd:
9194 case Intrinsic::x86_sse_comilt_ss:
9195 case Intrinsic::x86_sse2_comilt_sd:
9199 case Intrinsic::x86_sse_comile_ss:
9200 case Intrinsic::x86_sse2_comile_sd:
9204 case Intrinsic::x86_sse_comigt_ss:
9205 case Intrinsic::x86_sse2_comigt_sd:
9209 case Intrinsic::x86_sse_comige_ss:
9210 case Intrinsic::x86_sse2_comige_sd:
9214 case Intrinsic::x86_sse_comineq_ss:
9215 case Intrinsic::x86_sse2_comineq_sd:
9219 case Intrinsic::x86_sse_ucomieq_ss:
9220 case Intrinsic::x86_sse2_ucomieq_sd:
9221 Opc = X86ISD::UCOMI;
9224 case Intrinsic::x86_sse_ucomilt_ss:
9225 case Intrinsic::x86_sse2_ucomilt_sd:
9226 Opc = X86ISD::UCOMI;
9229 case Intrinsic::x86_sse_ucomile_ss:
9230 case Intrinsic::x86_sse2_ucomile_sd:
9231 Opc = X86ISD::UCOMI;
9234 case Intrinsic::x86_sse_ucomigt_ss:
9235 case Intrinsic::x86_sse2_ucomigt_sd:
9236 Opc = X86ISD::UCOMI;
9239 case Intrinsic::x86_sse_ucomige_ss:
9240 case Intrinsic::x86_sse2_ucomige_sd:
9241 Opc = X86ISD::UCOMI;
9244 case Intrinsic::x86_sse_ucomineq_ss:
9245 case Intrinsic::x86_sse2_ucomineq_sd:
9246 Opc = X86ISD::UCOMI;
9251 SDValue LHS = Op.getOperand(1);
9252 SDValue RHS = Op.getOperand(2);
9253 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9254 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9255 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9256 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9257 DAG.getConstant(X86CC, MVT::i8), Cond);
9258 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9260 // XOP comparison intrinsics
9261 case Intrinsic::x86_xop_vpcomltb:
9262 case Intrinsic::x86_xop_vpcomltw:
9263 case Intrinsic::x86_xop_vpcomltd:
9264 case Intrinsic::x86_xop_vpcomltq:
9265 case Intrinsic::x86_xop_vpcomltub:
9266 case Intrinsic::x86_xop_vpcomltuw:
9267 case Intrinsic::x86_xop_vpcomltud:
9268 case Intrinsic::x86_xop_vpcomltuq:
9269 case Intrinsic::x86_xop_vpcomleb:
9270 case Intrinsic::x86_xop_vpcomlew:
9271 case Intrinsic::x86_xop_vpcomled:
9272 case Intrinsic::x86_xop_vpcomleq:
9273 case Intrinsic::x86_xop_vpcomleub:
9274 case Intrinsic::x86_xop_vpcomleuw:
9275 case Intrinsic::x86_xop_vpcomleud:
9276 case Intrinsic::x86_xop_vpcomleuq:
9277 case Intrinsic::x86_xop_vpcomgtb:
9278 case Intrinsic::x86_xop_vpcomgtw:
9279 case Intrinsic::x86_xop_vpcomgtd:
9280 case Intrinsic::x86_xop_vpcomgtq:
9281 case Intrinsic::x86_xop_vpcomgtub:
9282 case Intrinsic::x86_xop_vpcomgtuw:
9283 case Intrinsic::x86_xop_vpcomgtud:
9284 case Intrinsic::x86_xop_vpcomgtuq:
9285 case Intrinsic::x86_xop_vpcomgeb:
9286 case Intrinsic::x86_xop_vpcomgew:
9287 case Intrinsic::x86_xop_vpcomged:
9288 case Intrinsic::x86_xop_vpcomgeq:
9289 case Intrinsic::x86_xop_vpcomgeub:
9290 case Intrinsic::x86_xop_vpcomgeuw:
9291 case Intrinsic::x86_xop_vpcomgeud:
9292 case Intrinsic::x86_xop_vpcomgeuq:
9293 case Intrinsic::x86_xop_vpcomeqb:
9294 case Intrinsic::x86_xop_vpcomeqw:
9295 case Intrinsic::x86_xop_vpcomeqd:
9296 case Intrinsic::x86_xop_vpcomeqq:
9297 case Intrinsic::x86_xop_vpcomequb:
9298 case Intrinsic::x86_xop_vpcomequw:
9299 case Intrinsic::x86_xop_vpcomequd:
9300 case Intrinsic::x86_xop_vpcomequq:
9301 case Intrinsic::x86_xop_vpcomneb:
9302 case Intrinsic::x86_xop_vpcomnew:
9303 case Intrinsic::x86_xop_vpcomned:
9304 case Intrinsic::x86_xop_vpcomneq:
9305 case Intrinsic::x86_xop_vpcomneub:
9306 case Intrinsic::x86_xop_vpcomneuw:
9307 case Intrinsic::x86_xop_vpcomneud:
9308 case Intrinsic::x86_xop_vpcomneuq:
9309 case Intrinsic::x86_xop_vpcomfalseb:
9310 case Intrinsic::x86_xop_vpcomfalsew:
9311 case Intrinsic::x86_xop_vpcomfalsed:
9312 case Intrinsic::x86_xop_vpcomfalseq:
9313 case Intrinsic::x86_xop_vpcomfalseub:
9314 case Intrinsic::x86_xop_vpcomfalseuw:
9315 case Intrinsic::x86_xop_vpcomfalseud:
9316 case Intrinsic::x86_xop_vpcomfalseuq:
9317 case Intrinsic::x86_xop_vpcomtrueb:
9318 case Intrinsic::x86_xop_vpcomtruew:
9319 case Intrinsic::x86_xop_vpcomtrued:
9320 case Intrinsic::x86_xop_vpcomtrueq:
9321 case Intrinsic::x86_xop_vpcomtrueub:
9322 case Intrinsic::x86_xop_vpcomtrueuw:
9323 case Intrinsic::x86_xop_vpcomtrueud:
9324 case Intrinsic::x86_xop_vpcomtrueuq: {
9329 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9330 case Intrinsic::x86_xop_vpcomltb:
9331 case Intrinsic::x86_xop_vpcomltw:
9332 case Intrinsic::x86_xop_vpcomltd:
9333 case Intrinsic::x86_xop_vpcomltq:
9335 Opc = X86ISD::VPCOM;
9337 case Intrinsic::x86_xop_vpcomltub:
9338 case Intrinsic::x86_xop_vpcomltuw:
9339 case Intrinsic::x86_xop_vpcomltud:
9340 case Intrinsic::x86_xop_vpcomltuq:
9342 Opc = X86ISD::VPCOMU;
9344 case Intrinsic::x86_xop_vpcomleb:
9345 case Intrinsic::x86_xop_vpcomlew:
9346 case Intrinsic::x86_xop_vpcomled:
9347 case Intrinsic::x86_xop_vpcomleq:
9349 Opc = X86ISD::VPCOM;
9351 case Intrinsic::x86_xop_vpcomleub:
9352 case Intrinsic::x86_xop_vpcomleuw:
9353 case Intrinsic::x86_xop_vpcomleud:
9354 case Intrinsic::x86_xop_vpcomleuq:
9356 Opc = X86ISD::VPCOMU;
9358 case Intrinsic::x86_xop_vpcomgtb:
9359 case Intrinsic::x86_xop_vpcomgtw:
9360 case Intrinsic::x86_xop_vpcomgtd:
9361 case Intrinsic::x86_xop_vpcomgtq:
9363 Opc = X86ISD::VPCOM;
9365 case Intrinsic::x86_xop_vpcomgtub:
9366 case Intrinsic::x86_xop_vpcomgtuw:
9367 case Intrinsic::x86_xop_vpcomgtud:
9368 case Intrinsic::x86_xop_vpcomgtuq:
9370 Opc = X86ISD::VPCOMU;
9372 case Intrinsic::x86_xop_vpcomgeb:
9373 case Intrinsic::x86_xop_vpcomgew:
9374 case Intrinsic::x86_xop_vpcomged:
9375 case Intrinsic::x86_xop_vpcomgeq:
9377 Opc = X86ISD::VPCOM;
9379 case Intrinsic::x86_xop_vpcomgeub:
9380 case Intrinsic::x86_xop_vpcomgeuw:
9381 case Intrinsic::x86_xop_vpcomgeud:
9382 case Intrinsic::x86_xop_vpcomgeuq:
9384 Opc = X86ISD::VPCOMU;
9386 case Intrinsic::x86_xop_vpcomeqb:
9387 case Intrinsic::x86_xop_vpcomeqw:
9388 case Intrinsic::x86_xop_vpcomeqd:
9389 case Intrinsic::x86_xop_vpcomeqq:
9391 Opc = X86ISD::VPCOM;
9393 case Intrinsic::x86_xop_vpcomequb:
9394 case Intrinsic::x86_xop_vpcomequw:
9395 case Intrinsic::x86_xop_vpcomequd:
9396 case Intrinsic::x86_xop_vpcomequq:
9398 Opc = X86ISD::VPCOMU;
9400 case Intrinsic::x86_xop_vpcomneb:
9401 case Intrinsic::x86_xop_vpcomnew:
9402 case Intrinsic::x86_xop_vpcomned:
9403 case Intrinsic::x86_xop_vpcomneq:
9405 Opc = X86ISD::VPCOM;
9407 case Intrinsic::x86_xop_vpcomneub:
9408 case Intrinsic::x86_xop_vpcomneuw:
9409 case Intrinsic::x86_xop_vpcomneud:
9410 case Intrinsic::x86_xop_vpcomneuq:
9412 Opc = X86ISD::VPCOMU;
9414 case Intrinsic::x86_xop_vpcomfalseb:
9415 case Intrinsic::x86_xop_vpcomfalsew:
9416 case Intrinsic::x86_xop_vpcomfalsed:
9417 case Intrinsic::x86_xop_vpcomfalseq:
9419 Opc = X86ISD::VPCOM;
9421 case Intrinsic::x86_xop_vpcomfalseub:
9422 case Intrinsic::x86_xop_vpcomfalseuw:
9423 case Intrinsic::x86_xop_vpcomfalseud:
9424 case Intrinsic::x86_xop_vpcomfalseuq:
9426 Opc = X86ISD::VPCOMU;
9428 case Intrinsic::x86_xop_vpcomtrueb:
9429 case Intrinsic::x86_xop_vpcomtruew:
9430 case Intrinsic::x86_xop_vpcomtrued:
9431 case Intrinsic::x86_xop_vpcomtrueq:
9433 Opc = X86ISD::VPCOM;
9435 case Intrinsic::x86_xop_vpcomtrueub:
9436 case Intrinsic::x86_xop_vpcomtrueuw:
9437 case Intrinsic::x86_xop_vpcomtrueud:
9438 case Intrinsic::x86_xop_vpcomtrueuq:
9440 Opc = X86ISD::VPCOMU;
9444 SDValue LHS = Op.getOperand(1);
9445 SDValue RHS = Op.getOperand(2);
9446 return DAG.getNode(Opc, dl, Op.getValueType(), LHS, RHS,
9447 DAG.getConstant(CC, MVT::i8));
9450 // Arithmetic intrinsics.
9451 case Intrinsic::x86_sse2_pmulu_dq:
9452 case Intrinsic::x86_avx2_pmulu_dq:
9453 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
9454 Op.getOperand(1), Op.getOperand(2));
9455 case Intrinsic::x86_sse3_hadd_ps:
9456 case Intrinsic::x86_sse3_hadd_pd:
9457 case Intrinsic::x86_avx_hadd_ps_256:
9458 case Intrinsic::x86_avx_hadd_pd_256:
9459 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(),
9460 Op.getOperand(1), Op.getOperand(2));
9461 case Intrinsic::x86_sse3_hsub_ps:
9462 case Intrinsic::x86_sse3_hsub_pd:
9463 case Intrinsic::x86_avx_hsub_ps_256:
9464 case Intrinsic::x86_avx_hsub_pd_256:
9465 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(),
9466 Op.getOperand(1), Op.getOperand(2));
9467 case Intrinsic::x86_ssse3_phadd_w_128:
9468 case Intrinsic::x86_ssse3_phadd_d_128:
9469 case Intrinsic::x86_avx2_phadd_w:
9470 case Intrinsic::x86_avx2_phadd_d:
9471 return DAG.getNode(X86ISD::HADD, dl, Op.getValueType(),
9472 Op.getOperand(1), Op.getOperand(2));
9473 case Intrinsic::x86_ssse3_phsub_w_128:
9474 case Intrinsic::x86_ssse3_phsub_d_128:
9475 case Intrinsic::x86_avx2_phsub_w:
9476 case Intrinsic::x86_avx2_phsub_d:
9477 return DAG.getNode(X86ISD::HSUB, dl, Op.getValueType(),
9478 Op.getOperand(1), Op.getOperand(2));
9479 case Intrinsic::x86_avx2_psllv_d:
9480 case Intrinsic::x86_avx2_psllv_q:
9481 case Intrinsic::x86_avx2_psllv_d_256:
9482 case Intrinsic::x86_avx2_psllv_q_256:
9483 return DAG.getNode(ISD::SHL, dl, Op.getValueType(),
9484 Op.getOperand(1), Op.getOperand(2));
9485 case Intrinsic::x86_avx2_psrlv_d:
9486 case Intrinsic::x86_avx2_psrlv_q:
9487 case Intrinsic::x86_avx2_psrlv_d_256:
9488 case Intrinsic::x86_avx2_psrlv_q_256:
9489 return DAG.getNode(ISD::SRL, dl, Op.getValueType(),
9490 Op.getOperand(1), Op.getOperand(2));
9491 case Intrinsic::x86_avx2_psrav_d:
9492 case Intrinsic::x86_avx2_psrav_d_256:
9493 return DAG.getNode(ISD::SRA, dl, Op.getValueType(),
9494 Op.getOperand(1), Op.getOperand(2));
9495 case Intrinsic::x86_ssse3_pshuf_b_128:
9496 case Intrinsic::x86_avx2_pshuf_b:
9497 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
9498 Op.getOperand(1), Op.getOperand(2));
9499 case Intrinsic::x86_ssse3_psign_b_128:
9500 case Intrinsic::x86_ssse3_psign_w_128:
9501 case Intrinsic::x86_ssse3_psign_d_128:
9502 case Intrinsic::x86_avx2_psign_b:
9503 case Intrinsic::x86_avx2_psign_w:
9504 case Intrinsic::x86_avx2_psign_d:
9505 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
9506 Op.getOperand(1), Op.getOperand(2));
9507 case Intrinsic::x86_sse41_insertps:
9508 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
9509 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9510 case Intrinsic::x86_avx_vperm2f128_ps_256:
9511 case Intrinsic::x86_avx_vperm2f128_pd_256:
9512 case Intrinsic::x86_avx_vperm2f128_si_256:
9513 case Intrinsic::x86_avx2_vperm2i128:
9514 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
9515 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
9516 case Intrinsic::x86_avx_vpermil_ps:
9517 case Intrinsic::x86_avx_vpermil_pd:
9518 case Intrinsic::x86_avx_vpermil_ps_256:
9519 case Intrinsic::x86_avx_vpermil_pd_256:
9520 return DAG.getNode(X86ISD::VPERMILP, dl, Op.getValueType(),
9521 Op.getOperand(1), Op.getOperand(2));
9523 // ptest and testp intrinsics. The intrinsic these come from are designed to
9524 // return an integer value, not just an instruction so lower it to the ptest
9525 // or testp pattern and a setcc for the result.
9526 case Intrinsic::x86_sse41_ptestz:
9527 case Intrinsic::x86_sse41_ptestc:
9528 case Intrinsic::x86_sse41_ptestnzc:
9529 case Intrinsic::x86_avx_ptestz_256:
9530 case Intrinsic::x86_avx_ptestc_256:
9531 case Intrinsic::x86_avx_ptestnzc_256:
9532 case Intrinsic::x86_avx_vtestz_ps:
9533 case Intrinsic::x86_avx_vtestc_ps:
9534 case Intrinsic::x86_avx_vtestnzc_ps:
9535 case Intrinsic::x86_avx_vtestz_pd:
9536 case Intrinsic::x86_avx_vtestc_pd:
9537 case Intrinsic::x86_avx_vtestnzc_pd:
9538 case Intrinsic::x86_avx_vtestz_ps_256:
9539 case Intrinsic::x86_avx_vtestc_ps_256:
9540 case Intrinsic::x86_avx_vtestnzc_ps_256:
9541 case Intrinsic::x86_avx_vtestz_pd_256:
9542 case Intrinsic::x86_avx_vtestc_pd_256:
9543 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9544 bool IsTestPacked = false;
9547 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9548 case Intrinsic::x86_avx_vtestz_ps:
9549 case Intrinsic::x86_avx_vtestz_pd:
9550 case Intrinsic::x86_avx_vtestz_ps_256:
9551 case Intrinsic::x86_avx_vtestz_pd_256:
9552 IsTestPacked = true; // Fallthrough
9553 case Intrinsic::x86_sse41_ptestz:
9554 case Intrinsic::x86_avx_ptestz_256:
9556 X86CC = X86::COND_E;
9558 case Intrinsic::x86_avx_vtestc_ps:
9559 case Intrinsic::x86_avx_vtestc_pd:
9560 case Intrinsic::x86_avx_vtestc_ps_256:
9561 case Intrinsic::x86_avx_vtestc_pd_256:
9562 IsTestPacked = true; // Fallthrough
9563 case Intrinsic::x86_sse41_ptestc:
9564 case Intrinsic::x86_avx_ptestc_256:
9566 X86CC = X86::COND_B;
9568 case Intrinsic::x86_avx_vtestnzc_ps:
9569 case Intrinsic::x86_avx_vtestnzc_pd:
9570 case Intrinsic::x86_avx_vtestnzc_ps_256:
9571 case Intrinsic::x86_avx_vtestnzc_pd_256:
9572 IsTestPacked = true; // Fallthrough
9573 case Intrinsic::x86_sse41_ptestnzc:
9574 case Intrinsic::x86_avx_ptestnzc_256:
9576 X86CC = X86::COND_A;
9580 SDValue LHS = Op.getOperand(1);
9581 SDValue RHS = Op.getOperand(2);
9582 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9583 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9584 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9585 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9586 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9589 // SSE/AVX shift intrinsics
9590 case Intrinsic::x86_sse2_psll_w:
9591 case Intrinsic::x86_sse2_psll_d:
9592 case Intrinsic::x86_sse2_psll_q:
9593 case Intrinsic::x86_avx2_psll_w:
9594 case Intrinsic::x86_avx2_psll_d:
9595 case Intrinsic::x86_avx2_psll_q:
9596 return DAG.getNode(X86ISD::VSHL, dl, Op.getValueType(),
9597 Op.getOperand(1), Op.getOperand(2));
9598 case Intrinsic::x86_sse2_psrl_w:
9599 case Intrinsic::x86_sse2_psrl_d:
9600 case Intrinsic::x86_sse2_psrl_q:
9601 case Intrinsic::x86_avx2_psrl_w:
9602 case Intrinsic::x86_avx2_psrl_d:
9603 case Intrinsic::x86_avx2_psrl_q:
9604 return DAG.getNode(X86ISD::VSRL, dl, Op.getValueType(),
9605 Op.getOperand(1), Op.getOperand(2));
9606 case Intrinsic::x86_sse2_psra_w:
9607 case Intrinsic::x86_sse2_psra_d:
9608 case Intrinsic::x86_avx2_psra_w:
9609 case Intrinsic::x86_avx2_psra_d:
9610 return DAG.getNode(X86ISD::VSRA, dl, Op.getValueType(),
9611 Op.getOperand(1), Op.getOperand(2));
9612 case Intrinsic::x86_sse2_pslli_w:
9613 case Intrinsic::x86_sse2_pslli_d:
9614 case Intrinsic::x86_sse2_pslli_q:
9615 case Intrinsic::x86_avx2_pslli_w:
9616 case Intrinsic::x86_avx2_pslli_d:
9617 case Intrinsic::x86_avx2_pslli_q:
9618 return getTargetVShiftNode(X86ISD::VSHLI, dl, Op.getValueType(),
9619 Op.getOperand(1), Op.getOperand(2), DAG);
9620 case Intrinsic::x86_sse2_psrli_w:
9621 case Intrinsic::x86_sse2_psrli_d:
9622 case Intrinsic::x86_sse2_psrli_q:
9623 case Intrinsic::x86_avx2_psrli_w:
9624 case Intrinsic::x86_avx2_psrli_d:
9625 case Intrinsic::x86_avx2_psrli_q:
9626 return getTargetVShiftNode(X86ISD::VSRLI, dl, Op.getValueType(),
9627 Op.getOperand(1), Op.getOperand(2), DAG);
9628 case Intrinsic::x86_sse2_psrai_w:
9629 case Intrinsic::x86_sse2_psrai_d:
9630 case Intrinsic::x86_avx2_psrai_w:
9631 case Intrinsic::x86_avx2_psrai_d:
9632 return getTargetVShiftNode(X86ISD::VSRAI, dl, Op.getValueType(),
9633 Op.getOperand(1), Op.getOperand(2), DAG);
9634 // Fix vector shift instructions where the last operand is a non-immediate
9636 case Intrinsic::x86_mmx_pslli_w:
9637 case Intrinsic::x86_mmx_pslli_d:
9638 case Intrinsic::x86_mmx_pslli_q:
9639 case Intrinsic::x86_mmx_psrli_w:
9640 case Intrinsic::x86_mmx_psrli_d:
9641 case Intrinsic::x86_mmx_psrli_q:
9642 case Intrinsic::x86_mmx_psrai_w:
9643 case Intrinsic::x86_mmx_psrai_d: {
9644 SDValue ShAmt = Op.getOperand(2);
9645 if (isa<ConstantSDNode>(ShAmt))
9648 unsigned NewIntNo = 0;
9650 case Intrinsic::x86_mmx_pslli_w:
9651 NewIntNo = Intrinsic::x86_mmx_psll_w;
9653 case Intrinsic::x86_mmx_pslli_d:
9654 NewIntNo = Intrinsic::x86_mmx_psll_d;
9656 case Intrinsic::x86_mmx_pslli_q:
9657 NewIntNo = Intrinsic::x86_mmx_psll_q;
9659 case Intrinsic::x86_mmx_psrli_w:
9660 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9662 case Intrinsic::x86_mmx_psrli_d:
9663 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9665 case Intrinsic::x86_mmx_psrli_q:
9666 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9668 case Intrinsic::x86_mmx_psrai_w:
9669 NewIntNo = Intrinsic::x86_mmx_psra_w;
9671 case Intrinsic::x86_mmx_psrai_d:
9672 NewIntNo = Intrinsic::x86_mmx_psra_d;
9674 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9677 // The vector shift intrinsics with scalars uses 32b shift amounts but
9678 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9680 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, ShAmt,
9681 DAG.getConstant(0, MVT::i32));
9682 // FIXME this must be lowered to get rid of the invalid type.
9684 EVT VT = Op.getValueType();
9685 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9686 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9687 DAG.getConstant(NewIntNo, MVT::i32),
9688 Op.getOperand(1), ShAmt);
9693 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9694 SelectionDAG &DAG) const {
9695 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9696 MFI->setReturnAddressIsTaken(true);
9698 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9699 DebugLoc dl = Op.getDebugLoc();
9702 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9704 DAG.getConstant(TD->getPointerSize(),
9705 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9706 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9707 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9709 MachinePointerInfo(), false, false, false, 0);
9712 // Just load the return address.
9713 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9714 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9715 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9718 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9719 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9720 MFI->setFrameAddressIsTaken(true);
9722 EVT VT = Op.getValueType();
9723 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9724 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9725 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9726 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9728 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9729 MachinePointerInfo(),
9730 false, false, false, 0);
9734 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9735 SelectionDAG &DAG) const {
9736 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9739 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9740 MachineFunction &MF = DAG.getMachineFunction();
9741 SDValue Chain = Op.getOperand(0);
9742 SDValue Offset = Op.getOperand(1);
9743 SDValue Handler = Op.getOperand(2);
9744 DebugLoc dl = Op.getDebugLoc();
9746 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9747 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9749 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9751 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9752 DAG.getIntPtrConstant(TD->getPointerSize()));
9753 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9754 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9756 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9757 MF.getRegInfo().addLiveOut(StoreAddrReg);
9759 return DAG.getNode(X86ISD::EH_RETURN, dl,
9761 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9764 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9765 SelectionDAG &DAG) const {
9766 return Op.getOperand(0);
9769 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9770 SelectionDAG &DAG) const {
9771 SDValue Root = Op.getOperand(0);
9772 SDValue Trmp = Op.getOperand(1); // trampoline
9773 SDValue FPtr = Op.getOperand(2); // nested function
9774 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9775 DebugLoc dl = Op.getDebugLoc();
9777 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9779 if (Subtarget->is64Bit()) {
9780 SDValue OutChains[6];
9782 // Large code-model.
9783 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9784 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9786 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9787 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9789 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9791 // Load the pointer to the nested function into R11.
9792 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9793 SDValue Addr = Trmp;
9794 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9795 Addr, MachinePointerInfo(TrmpAddr),
9798 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9799 DAG.getConstant(2, MVT::i64));
9800 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9801 MachinePointerInfo(TrmpAddr, 2),
9804 // Load the 'nest' parameter value into R10.
9805 // R10 is specified in X86CallingConv.td
9806 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9807 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9808 DAG.getConstant(10, MVT::i64));
9809 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9810 Addr, MachinePointerInfo(TrmpAddr, 10),
9813 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9814 DAG.getConstant(12, MVT::i64));
9815 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9816 MachinePointerInfo(TrmpAddr, 12),
9819 // Jump to the nested function.
9820 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9821 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9822 DAG.getConstant(20, MVT::i64));
9823 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9824 Addr, MachinePointerInfo(TrmpAddr, 20),
9827 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9828 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9829 DAG.getConstant(22, MVT::i64));
9830 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9831 MachinePointerInfo(TrmpAddr, 22),
9834 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9836 const Function *Func =
9837 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9838 CallingConv::ID CC = Func->getCallingConv();
9843 llvm_unreachable("Unsupported calling convention");
9844 case CallingConv::C:
9845 case CallingConv::X86_StdCall: {
9846 // Pass 'nest' parameter in ECX.
9847 // Must be kept in sync with X86CallingConv.td
9850 // Check that ECX wasn't needed by an 'inreg' parameter.
9851 FunctionType *FTy = Func->getFunctionType();
9852 const AttrListPtr &Attrs = Func->getAttributes();
9854 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9855 unsigned InRegCount = 0;
9858 for (FunctionType::param_iterator I = FTy->param_begin(),
9859 E = FTy->param_end(); I != E; ++I, ++Idx)
9860 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9861 // FIXME: should only count parameters that are lowered to integers.
9862 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9864 if (InRegCount > 2) {
9865 report_fatal_error("Nest register in use - reduce number of inreg"
9871 case CallingConv::X86_FastCall:
9872 case CallingConv::X86_ThisCall:
9873 case CallingConv::Fast:
9874 // Pass 'nest' parameter in EAX.
9875 // Must be kept in sync with X86CallingConv.td
9880 SDValue OutChains[4];
9883 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9884 DAG.getConstant(10, MVT::i32));
9885 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9887 // This is storing the opcode for MOV32ri.
9888 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9889 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9890 OutChains[0] = DAG.getStore(Root, dl,
9891 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9892 Trmp, MachinePointerInfo(TrmpAddr),
9895 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9896 DAG.getConstant(1, MVT::i32));
9897 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9898 MachinePointerInfo(TrmpAddr, 1),
9901 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9902 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9903 DAG.getConstant(5, MVT::i32));
9904 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9905 MachinePointerInfo(TrmpAddr, 5),
9908 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9909 DAG.getConstant(6, MVT::i32));
9910 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9911 MachinePointerInfo(TrmpAddr, 6),
9914 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9918 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9919 SelectionDAG &DAG) const {
9921 The rounding mode is in bits 11:10 of FPSR, and has the following
9928 FLT_ROUNDS, on the other hand, expects the following:
9935 To perform the conversion, we do:
9936 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9939 MachineFunction &MF = DAG.getMachineFunction();
9940 const TargetMachine &TM = MF.getTarget();
9941 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9942 unsigned StackAlignment = TFI.getStackAlignment();
9943 EVT VT = Op.getValueType();
9944 DebugLoc DL = Op.getDebugLoc();
9946 // Save FP Control Word to stack slot
9947 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9948 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9951 MachineMemOperand *MMO =
9952 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9953 MachineMemOperand::MOStore, 2, 2);
9955 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9956 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9957 DAG.getVTList(MVT::Other),
9958 Ops, 2, MVT::i16, MMO);
9960 // Load FP Control Word from stack slot
9961 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9962 MachinePointerInfo(), false, false, false, 0);
9964 // Transform as necessary
9966 DAG.getNode(ISD::SRL, DL, MVT::i16,
9967 DAG.getNode(ISD::AND, DL, MVT::i16,
9968 CWD, DAG.getConstant(0x800, MVT::i16)),
9969 DAG.getConstant(11, MVT::i8));
9971 DAG.getNode(ISD::SRL, DL, MVT::i16,
9972 DAG.getNode(ISD::AND, DL, MVT::i16,
9973 CWD, DAG.getConstant(0x400, MVT::i16)),
9974 DAG.getConstant(9, MVT::i8));
9977 DAG.getNode(ISD::AND, DL, MVT::i16,
9978 DAG.getNode(ISD::ADD, DL, MVT::i16,
9979 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9980 DAG.getConstant(1, MVT::i16)),
9981 DAG.getConstant(3, MVT::i16));
9984 return DAG.getNode((VT.getSizeInBits() < 16 ?
9985 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9988 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9989 EVT VT = Op.getValueType();
9991 unsigned NumBits = VT.getSizeInBits();
9992 DebugLoc dl = Op.getDebugLoc();
9994 Op = Op.getOperand(0);
9995 if (VT == MVT::i8) {
9996 // Zero extend to i32 since there is not an i8 bsr.
9998 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10001 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
10002 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10003 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10005 // If src is zero (i.e. bsr sets ZF), returns NumBits.
10008 DAG.getConstant(NumBits+NumBits-1, OpVT),
10009 DAG.getConstant(X86::COND_E, MVT::i8),
10012 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
10014 // Finally xor with NumBits-1.
10015 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10018 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10022 SDValue X86TargetLowering::LowerCTLZ_ZERO_UNDEF(SDValue Op,
10023 SelectionDAG &DAG) const {
10024 EVT VT = Op.getValueType();
10026 unsigned NumBits = VT.getSizeInBits();
10027 DebugLoc dl = Op.getDebugLoc();
10029 Op = Op.getOperand(0);
10030 if (VT == MVT::i8) {
10031 // Zero extend to i32 since there is not an i8 bsr.
10033 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
10036 // Issue a bsr (scan bits in reverse).
10037 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
10038 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
10040 // And xor with NumBits-1.
10041 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
10044 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
10048 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
10049 EVT VT = Op.getValueType();
10050 unsigned NumBits = VT.getSizeInBits();
10051 DebugLoc dl = Op.getDebugLoc();
10052 Op = Op.getOperand(0);
10054 // Issue a bsf (scan bits forward) which also sets EFLAGS.
10055 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10056 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
10058 // If src is zero (i.e. bsf sets ZF), returns NumBits.
10061 DAG.getConstant(NumBits, VT),
10062 DAG.getConstant(X86::COND_E, MVT::i8),
10065 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
10068 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
10069 // ones, and then concatenate the result back.
10070 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
10071 EVT VT = Op.getValueType();
10073 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
10074 "Unsupported value type for operation");
10076 int NumElems = VT.getVectorNumElements();
10077 DebugLoc dl = Op.getDebugLoc();
10078 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10079 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10081 // Extract the LHS vectors
10082 SDValue LHS = Op.getOperand(0);
10083 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10084 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10086 // Extract the RHS vectors
10087 SDValue RHS = Op.getOperand(1);
10088 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
10089 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
10091 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10092 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10094 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10095 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
10096 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
10099 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
10100 assert(Op.getValueType().getSizeInBits() == 256 &&
10101 Op.getValueType().isInteger() &&
10102 "Only handle AVX 256-bit vector integer operation");
10103 return Lower256IntArith(Op, DAG);
10106 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
10107 assert(Op.getValueType().getSizeInBits() == 256 &&
10108 Op.getValueType().isInteger() &&
10109 "Only handle AVX 256-bit vector integer operation");
10110 return Lower256IntArith(Op, DAG);
10113 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
10114 EVT VT = Op.getValueType();
10116 // Decompose 256-bit ops into smaller 128-bit ops.
10117 if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2())
10118 return Lower256IntArith(Op, DAG);
10120 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
10121 "Only know how to lower V2I64/V4I64 multiply");
10123 DebugLoc dl = Op.getDebugLoc();
10125 // Ahi = psrlqi(a, 32);
10126 // Bhi = psrlqi(b, 32);
10128 // AloBlo = pmuludq(a, b);
10129 // AloBhi = pmuludq(a, Bhi);
10130 // AhiBlo = pmuludq(Ahi, b);
10132 // AloBhi = psllqi(AloBhi, 32);
10133 // AhiBlo = psllqi(AhiBlo, 32);
10134 // return AloBlo + AloBhi + AhiBlo;
10136 SDValue A = Op.getOperand(0);
10137 SDValue B = Op.getOperand(1);
10139 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
10141 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
10142 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
10144 // Bit cast to 32-bit vectors for MULUDQ
10145 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
10146 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
10147 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
10148 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
10149 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
10151 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
10152 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
10153 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
10155 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
10156 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
10158 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
10159 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
10162 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
10164 EVT VT = Op.getValueType();
10165 DebugLoc dl = Op.getDebugLoc();
10166 SDValue R = Op.getOperand(0);
10167 SDValue Amt = Op.getOperand(1);
10168 LLVMContext *Context = DAG.getContext();
10170 if (!Subtarget->hasSSE2())
10173 // Optimize shl/srl/sra with constant shift amount.
10174 if (isSplatVector(Amt.getNode())) {
10175 SDValue SclrAmt = Amt->getOperand(0);
10176 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
10177 uint64_t ShiftAmt = C->getZExtValue();
10179 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
10180 (Subtarget->hasAVX2() &&
10181 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
10182 if (Op.getOpcode() == ISD::SHL)
10183 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
10184 DAG.getConstant(ShiftAmt, MVT::i32));
10185 if (Op.getOpcode() == ISD::SRL)
10186 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
10187 DAG.getConstant(ShiftAmt, MVT::i32));
10188 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
10189 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
10190 DAG.getConstant(ShiftAmt, MVT::i32));
10193 if (VT == MVT::v16i8) {
10194 if (Op.getOpcode() == ISD::SHL) {
10195 // Make a large shift.
10196 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
10197 DAG.getConstant(ShiftAmt, MVT::i32));
10198 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10199 // Zero out the rightmost bits.
10200 SmallVector<SDValue, 16> V(16,
10201 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10203 return DAG.getNode(ISD::AND, dl, VT, SHL,
10204 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10206 if (Op.getOpcode() == ISD::SRL) {
10207 // Make a large shift.
10208 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
10209 DAG.getConstant(ShiftAmt, MVT::i32));
10210 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10211 // Zero out the leftmost bits.
10212 SmallVector<SDValue, 16> V(16,
10213 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10215 return DAG.getNode(ISD::AND, dl, VT, SRL,
10216 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
10218 if (Op.getOpcode() == ISD::SRA) {
10219 if (ShiftAmt == 7) {
10220 // R s>> 7 === R s< 0
10221 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10222 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10225 // R s>> a === ((R u>> a) ^ m) - m
10226 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10227 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
10229 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
10230 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10231 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10236 if (Subtarget->hasAVX2() && VT == MVT::v32i8) {
10237 if (Op.getOpcode() == ISD::SHL) {
10238 // Make a large shift.
10239 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
10240 DAG.getConstant(ShiftAmt, MVT::i32));
10241 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
10242 // Zero out the rightmost bits.
10243 SmallVector<SDValue, 32> V(32,
10244 DAG.getConstant(uint8_t(-1U << ShiftAmt),
10246 return DAG.getNode(ISD::AND, dl, VT, SHL,
10247 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10249 if (Op.getOpcode() == ISD::SRL) {
10250 // Make a large shift.
10251 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
10252 DAG.getConstant(ShiftAmt, MVT::i32));
10253 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
10254 // Zero out the leftmost bits.
10255 SmallVector<SDValue, 32> V(32,
10256 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
10258 return DAG.getNode(ISD::AND, dl, VT, SRL,
10259 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
10261 if (Op.getOpcode() == ISD::SRA) {
10262 if (ShiftAmt == 7) {
10263 // R s>> 7 === R s< 0
10264 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
10265 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
10268 // R s>> a === ((R u>> a) ^ m) - m
10269 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
10270 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
10272 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
10273 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
10274 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
10281 // Lower SHL with variable shift amount.
10282 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
10283 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
10284 DAG.getConstant(23, MVT::i32));
10286 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
10287 Constant *C = ConstantDataVector::get(*Context, CV);
10288 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
10289 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
10290 MachinePointerInfo::getConstantPool(),
10291 false, false, false, 16);
10293 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
10294 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
10295 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
10296 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
10298 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
10299 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
10302 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
10303 DAG.getConstant(5, MVT::i32));
10304 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
10306 // Turn 'a' into a mask suitable for VSELECT
10307 SDValue VSelM = DAG.getConstant(0x80, VT);
10308 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10309 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10311 SDValue CM1 = DAG.getConstant(0x0f, VT);
10312 SDValue CM2 = DAG.getConstant(0x3f, VT);
10314 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
10315 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
10316 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10317 DAG.getConstant(4, MVT::i32), DAG);
10318 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10319 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10322 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10323 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10324 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10326 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
10327 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
10328 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
10329 DAG.getConstant(2, MVT::i32), DAG);
10330 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
10331 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
10334 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
10335 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
10336 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
10338 // return VSELECT(r, r+r, a);
10339 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
10340 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
10344 // Decompose 256-bit shifts into smaller 128-bit shifts.
10345 if (VT.getSizeInBits() == 256) {
10346 unsigned NumElems = VT.getVectorNumElements();
10347 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10348 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10350 // Extract the two vectors
10351 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
10352 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
10355 // Recreate the shift amount vectors
10356 SDValue Amt1, Amt2;
10357 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
10358 // Constant shift amount
10359 SmallVector<SDValue, 4> Amt1Csts;
10360 SmallVector<SDValue, 4> Amt2Csts;
10361 for (unsigned i = 0; i != NumElems/2; ++i)
10362 Amt1Csts.push_back(Amt->getOperand(i));
10363 for (unsigned i = NumElems/2; i != NumElems; ++i)
10364 Amt2Csts.push_back(Amt->getOperand(i));
10366 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10367 &Amt1Csts[0], NumElems/2);
10368 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
10369 &Amt2Csts[0], NumElems/2);
10371 // Variable shift amount
10372 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
10373 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
10377 // Issue new vector shifts for the smaller types
10378 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
10379 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
10381 // Concatenate the result back
10382 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
10388 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
10389 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10390 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10391 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10392 // has only one use.
10393 SDNode *N = Op.getNode();
10394 SDValue LHS = N->getOperand(0);
10395 SDValue RHS = N->getOperand(1);
10396 unsigned BaseOp = 0;
10398 DebugLoc DL = Op.getDebugLoc();
10399 switch (Op.getOpcode()) {
10400 default: llvm_unreachable("Unknown ovf instruction!");
10402 // A subtract of one will be selected as a INC. Note that INC doesn't
10403 // set CF, so we can't do this for UADDO.
10404 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10406 BaseOp = X86ISD::INC;
10407 Cond = X86::COND_O;
10410 BaseOp = X86ISD::ADD;
10411 Cond = X86::COND_O;
10414 BaseOp = X86ISD::ADD;
10415 Cond = X86::COND_B;
10418 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10419 // set CF, so we can't do this for USUBO.
10420 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10422 BaseOp = X86ISD::DEC;
10423 Cond = X86::COND_O;
10426 BaseOp = X86ISD::SUB;
10427 Cond = X86::COND_O;
10430 BaseOp = X86ISD::SUB;
10431 Cond = X86::COND_B;
10434 BaseOp = X86ISD::SMUL;
10435 Cond = X86::COND_O;
10437 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10438 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10440 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10443 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10444 DAG.getConstant(X86::COND_O, MVT::i32),
10445 SDValue(Sum.getNode(), 2));
10447 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10451 // Also sets EFLAGS.
10452 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10453 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10456 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10457 DAG.getConstant(Cond, MVT::i32),
10458 SDValue(Sum.getNode(), 1));
10460 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10463 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
10464 SelectionDAG &DAG) const {
10465 DebugLoc dl = Op.getDebugLoc();
10466 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
10467 EVT VT = Op.getValueType();
10469 if (!Subtarget->hasSSE2() || !VT.isVector())
10472 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10473 ExtraVT.getScalarType().getSizeInBits();
10474 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10476 switch (VT.getSimpleVT().SimpleTy) {
10477 default: return SDValue();
10480 if (!Subtarget->hasAVX())
10482 if (!Subtarget->hasAVX2()) {
10483 // needs to be split
10484 int NumElems = VT.getVectorNumElements();
10485 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
10486 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
10488 // Extract the LHS vectors
10489 SDValue LHS = Op.getOperand(0);
10490 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
10491 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
10493 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10494 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
10496 EVT ExtraEltVT = ExtraVT.getVectorElementType();
10497 int ExtraNumElems = ExtraVT.getVectorNumElements();
10498 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
10500 SDValue Extra = DAG.getValueType(ExtraVT);
10502 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
10503 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
10505 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);;
10510 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
10511 Op.getOperand(0), ShAmt, DAG);
10512 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
10518 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10519 DebugLoc dl = Op.getDebugLoc();
10521 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10522 // There isn't any reason to disable it if the target processor supports it.
10523 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10524 SDValue Chain = Op.getOperand(0);
10525 SDValue Zero = DAG.getConstant(0, MVT::i32);
10527 DAG.getRegister(X86::ESP, MVT::i32), // Base
10528 DAG.getTargetConstant(1, MVT::i8), // Scale
10529 DAG.getRegister(0, MVT::i32), // Index
10530 DAG.getTargetConstant(0, MVT::i32), // Disp
10531 DAG.getRegister(0, MVT::i32), // Segment.
10536 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10537 array_lengthof(Ops));
10538 return SDValue(Res, 0);
10541 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10543 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10545 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10546 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10547 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10548 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10550 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10551 if (!Op1 && !Op2 && !Op3 && Op4)
10552 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10554 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10555 if (Op1 && !Op2 && !Op3 && !Op4)
10556 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10558 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10560 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10563 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10564 SelectionDAG &DAG) const {
10565 DebugLoc dl = Op.getDebugLoc();
10566 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10567 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10568 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10569 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10571 // The only fence that needs an instruction is a sequentially-consistent
10572 // cross-thread fence.
10573 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10574 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10575 // no-sse2). There isn't any reason to disable it if the target processor
10577 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10578 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10580 SDValue Chain = Op.getOperand(0);
10581 SDValue Zero = DAG.getConstant(0, MVT::i32);
10583 DAG.getRegister(X86::ESP, MVT::i32), // Base
10584 DAG.getTargetConstant(1, MVT::i8), // Scale
10585 DAG.getRegister(0, MVT::i32), // Index
10586 DAG.getTargetConstant(0, MVT::i32), // Disp
10587 DAG.getRegister(0, MVT::i32), // Segment.
10592 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10593 array_lengthof(Ops));
10594 return SDValue(Res, 0);
10597 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10598 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10602 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10603 EVT T = Op.getValueType();
10604 DebugLoc DL = Op.getDebugLoc();
10607 switch(T.getSimpleVT().SimpleTy) {
10608 default: llvm_unreachable("Invalid value type!");
10609 case MVT::i8: Reg = X86::AL; size = 1; break;
10610 case MVT::i16: Reg = X86::AX; size = 2; break;
10611 case MVT::i32: Reg = X86::EAX; size = 4; break;
10613 assert(Subtarget->is64Bit() && "Node not type legal!");
10614 Reg = X86::RAX; size = 8;
10617 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10618 Op.getOperand(2), SDValue());
10619 SDValue Ops[] = { cpIn.getValue(0),
10622 DAG.getTargetConstant(size, MVT::i8),
10623 cpIn.getValue(1) };
10624 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10625 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10626 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10629 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10633 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10634 SelectionDAG &DAG) const {
10635 assert(Subtarget->is64Bit() && "Result not type legalized?");
10636 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10637 SDValue TheChain = Op.getOperand(0);
10638 DebugLoc dl = Op.getDebugLoc();
10639 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10640 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10641 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10643 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10644 DAG.getConstant(32, MVT::i8));
10646 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10649 return DAG.getMergeValues(Ops, 2, dl);
10652 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10653 SelectionDAG &DAG) const {
10654 EVT SrcVT = Op.getOperand(0).getValueType();
10655 EVT DstVT = Op.getValueType();
10656 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10657 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10658 assert((DstVT == MVT::i64 ||
10659 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10660 "Unexpected custom BITCAST");
10661 // i64 <=> MMX conversions are Legal.
10662 if (SrcVT==MVT::i64 && DstVT.isVector())
10664 if (DstVT==MVT::i64 && SrcVT.isVector())
10666 // MMX <=> MMX conversions are Legal.
10667 if (SrcVT.isVector() && DstVT.isVector())
10669 // All other conversions need to be expanded.
10673 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10674 SDNode *Node = Op.getNode();
10675 DebugLoc dl = Node->getDebugLoc();
10676 EVT T = Node->getValueType(0);
10677 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10678 DAG.getConstant(0, T), Node->getOperand(2));
10679 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10680 cast<AtomicSDNode>(Node)->getMemoryVT(),
10681 Node->getOperand(0),
10682 Node->getOperand(1), negOp,
10683 cast<AtomicSDNode>(Node)->getSrcValue(),
10684 cast<AtomicSDNode>(Node)->getAlignment(),
10685 cast<AtomicSDNode>(Node)->getOrdering(),
10686 cast<AtomicSDNode>(Node)->getSynchScope());
10689 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10690 SDNode *Node = Op.getNode();
10691 DebugLoc dl = Node->getDebugLoc();
10692 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10694 // Convert seq_cst store -> xchg
10695 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10696 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10697 // (The only way to get a 16-byte store is cmpxchg16b)
10698 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10699 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10700 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10701 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10702 cast<AtomicSDNode>(Node)->getMemoryVT(),
10703 Node->getOperand(0),
10704 Node->getOperand(1), Node->getOperand(2),
10705 cast<AtomicSDNode>(Node)->getMemOperand(),
10706 cast<AtomicSDNode>(Node)->getOrdering(),
10707 cast<AtomicSDNode>(Node)->getSynchScope());
10708 return Swap.getValue(1);
10710 // Other atomic stores have a simple pattern.
10714 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10715 EVT VT = Op.getNode()->getValueType(0);
10717 // Let legalize expand this if it isn't a legal type yet.
10718 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10721 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10724 bool ExtraOp = false;
10725 switch (Op.getOpcode()) {
10726 default: llvm_unreachable("Invalid code");
10727 case ISD::ADDC: Opc = X86ISD::ADD; break;
10728 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10729 case ISD::SUBC: Opc = X86ISD::SUB; break;
10730 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10734 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10736 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10737 Op.getOperand(1), Op.getOperand(2));
10740 /// LowerOperation - Provide custom lowering hooks for some operations.
10742 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10743 switch (Op.getOpcode()) {
10744 default: llvm_unreachable("Should not custom lower this!");
10745 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10746 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10747 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10748 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10749 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10750 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10751 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10752 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10753 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10754 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10755 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10756 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10757 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10758 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10759 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10760 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10761 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10762 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10763 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10764 case ISD::SHL_PARTS:
10765 case ISD::SRA_PARTS:
10766 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10767 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10768 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10769 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10770 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10771 case ISD::FABS: return LowerFABS(Op, DAG);
10772 case ISD::FNEG: return LowerFNEG(Op, DAG);
10773 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10774 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10775 case ISD::SETCC: return LowerSETCC(Op, DAG);
10776 case ISD::SELECT: return LowerSELECT(Op, DAG);
10777 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10778 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10779 case ISD::VASTART: return LowerVASTART(Op, DAG);
10780 case ISD::VAARG: return LowerVAARG(Op, DAG);
10781 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10782 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10783 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10784 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10785 case ISD::FRAME_TO_ARGS_OFFSET:
10786 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10787 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10788 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10789 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10790 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10791 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10792 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10793 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
10794 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10795 case ISD::MUL: return LowerMUL(Op, DAG);
10798 case ISD::SHL: return LowerShift(Op, DAG);
10804 case ISD::UMULO: return LowerXALUO(Op, DAG);
10805 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10806 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10810 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10811 case ISD::ADD: return LowerADD(Op, DAG);
10812 case ISD::SUB: return LowerSUB(Op, DAG);
10816 static void ReplaceATOMIC_LOAD(SDNode *Node,
10817 SmallVectorImpl<SDValue> &Results,
10818 SelectionDAG &DAG) {
10819 DebugLoc dl = Node->getDebugLoc();
10820 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10822 // Convert wide load -> cmpxchg8b/cmpxchg16b
10823 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10824 // (The only way to get a 16-byte load is cmpxchg16b)
10825 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10826 SDValue Zero = DAG.getConstant(0, VT);
10827 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10828 Node->getOperand(0),
10829 Node->getOperand(1), Zero, Zero,
10830 cast<AtomicSDNode>(Node)->getMemOperand(),
10831 cast<AtomicSDNode>(Node)->getOrdering(),
10832 cast<AtomicSDNode>(Node)->getSynchScope());
10833 Results.push_back(Swap.getValue(0));
10834 Results.push_back(Swap.getValue(1));
10837 void X86TargetLowering::
10838 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10839 SelectionDAG &DAG, unsigned NewOp) const {
10840 DebugLoc dl = Node->getDebugLoc();
10841 assert (Node->getValueType(0) == MVT::i64 &&
10842 "Only know how to expand i64 atomics");
10844 SDValue Chain = Node->getOperand(0);
10845 SDValue In1 = Node->getOperand(1);
10846 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10847 Node->getOperand(2), DAG.getIntPtrConstant(0));
10848 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10849 Node->getOperand(2), DAG.getIntPtrConstant(1));
10850 SDValue Ops[] = { Chain, In1, In2L, In2H };
10851 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10853 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10854 cast<MemSDNode>(Node)->getMemOperand());
10855 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10856 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10857 Results.push_back(Result.getValue(2));
10860 /// ReplaceNodeResults - Replace a node with an illegal result type
10861 /// with a new node built out of custom code.
10862 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10863 SmallVectorImpl<SDValue>&Results,
10864 SelectionDAG &DAG) const {
10865 DebugLoc dl = N->getDebugLoc();
10866 switch (N->getOpcode()) {
10868 llvm_unreachable("Do not know how to custom type legalize this operation!");
10869 case ISD::SIGN_EXTEND_INREG:
10874 // We don't want to expand or promote these.
10876 case ISD::FP_TO_SINT:
10877 case ISD::FP_TO_UINT: {
10878 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
10880 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
10883 std::pair<SDValue,SDValue> Vals =
10884 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
10885 SDValue FIST = Vals.first, StackSlot = Vals.second;
10886 if (FIST.getNode() != 0) {
10887 EVT VT = N->getValueType(0);
10888 // Return a load from the stack slot.
10889 if (StackSlot.getNode() != 0)
10890 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10891 MachinePointerInfo(),
10892 false, false, false, 0));
10894 Results.push_back(FIST);
10898 case ISD::READCYCLECOUNTER: {
10899 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10900 SDValue TheChain = N->getOperand(0);
10901 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10902 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10904 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10906 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10907 SDValue Ops[] = { eax, edx };
10908 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10909 Results.push_back(edx.getValue(1));
10912 case ISD::ATOMIC_CMP_SWAP: {
10913 EVT T = N->getValueType(0);
10914 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10915 bool Regs64bit = T == MVT::i128;
10916 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10917 SDValue cpInL, cpInH;
10918 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10919 DAG.getConstant(0, HalfT));
10920 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10921 DAG.getConstant(1, HalfT));
10922 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10923 Regs64bit ? X86::RAX : X86::EAX,
10925 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10926 Regs64bit ? X86::RDX : X86::EDX,
10927 cpInH, cpInL.getValue(1));
10928 SDValue swapInL, swapInH;
10929 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10930 DAG.getConstant(0, HalfT));
10931 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10932 DAG.getConstant(1, HalfT));
10933 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10934 Regs64bit ? X86::RBX : X86::EBX,
10935 swapInL, cpInH.getValue(1));
10936 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10937 Regs64bit ? X86::RCX : X86::ECX,
10938 swapInH, swapInL.getValue(1));
10939 SDValue Ops[] = { swapInH.getValue(0),
10941 swapInH.getValue(1) };
10942 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10943 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10944 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10945 X86ISD::LCMPXCHG8_DAG;
10946 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10948 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10949 Regs64bit ? X86::RAX : X86::EAX,
10950 HalfT, Result.getValue(1));
10951 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10952 Regs64bit ? X86::RDX : X86::EDX,
10953 HalfT, cpOutL.getValue(2));
10954 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10955 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10956 Results.push_back(cpOutH.getValue(1));
10959 case ISD::ATOMIC_LOAD_ADD:
10960 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10962 case ISD::ATOMIC_LOAD_AND:
10963 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10965 case ISD::ATOMIC_LOAD_NAND:
10966 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10968 case ISD::ATOMIC_LOAD_OR:
10969 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10971 case ISD::ATOMIC_LOAD_SUB:
10972 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10974 case ISD::ATOMIC_LOAD_XOR:
10975 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10977 case ISD::ATOMIC_SWAP:
10978 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10980 case ISD::ATOMIC_LOAD:
10981 ReplaceATOMIC_LOAD(N, Results, DAG);
10985 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10987 default: return NULL;
10988 case X86ISD::BSF: return "X86ISD::BSF";
10989 case X86ISD::BSR: return "X86ISD::BSR";
10990 case X86ISD::SHLD: return "X86ISD::SHLD";
10991 case X86ISD::SHRD: return "X86ISD::SHRD";
10992 case X86ISD::FAND: return "X86ISD::FAND";
10993 case X86ISD::FOR: return "X86ISD::FOR";
10994 case X86ISD::FXOR: return "X86ISD::FXOR";
10995 case X86ISD::FSRL: return "X86ISD::FSRL";
10996 case X86ISD::FILD: return "X86ISD::FILD";
10997 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10998 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10999 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
11000 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
11001 case X86ISD::FLD: return "X86ISD::FLD";
11002 case X86ISD::FST: return "X86ISD::FST";
11003 case X86ISD::CALL: return "X86ISD::CALL";
11004 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
11005 case X86ISD::BT: return "X86ISD::BT";
11006 case X86ISD::CMP: return "X86ISD::CMP";
11007 case X86ISD::COMI: return "X86ISD::COMI";
11008 case X86ISD::UCOMI: return "X86ISD::UCOMI";
11009 case X86ISD::SETCC: return "X86ISD::SETCC";
11010 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
11011 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
11012 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
11013 case X86ISD::CMOV: return "X86ISD::CMOV";
11014 case X86ISD::BRCOND: return "X86ISD::BRCOND";
11015 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
11016 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
11017 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
11018 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
11019 case X86ISD::Wrapper: return "X86ISD::Wrapper";
11020 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
11021 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
11022 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
11023 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
11024 case X86ISD::PINSRB: return "X86ISD::PINSRB";
11025 case X86ISD::PINSRW: return "X86ISD::PINSRW";
11026 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
11027 case X86ISD::ANDNP: return "X86ISD::ANDNP";
11028 case X86ISD::PSIGN: return "X86ISD::PSIGN";
11029 case X86ISD::BLENDV: return "X86ISD::BLENDV";
11030 case X86ISD::HADD: return "X86ISD::HADD";
11031 case X86ISD::HSUB: return "X86ISD::HSUB";
11032 case X86ISD::FHADD: return "X86ISD::FHADD";
11033 case X86ISD::FHSUB: return "X86ISD::FHSUB";
11034 case X86ISD::FMAX: return "X86ISD::FMAX";
11035 case X86ISD::FMIN: return "X86ISD::FMIN";
11036 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
11037 case X86ISD::FRCP: return "X86ISD::FRCP";
11038 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
11039 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
11040 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
11041 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
11042 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
11043 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
11044 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
11045 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
11046 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
11047 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
11048 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
11049 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
11050 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
11051 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
11052 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
11053 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
11054 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
11055 case X86ISD::VSHL: return "X86ISD::VSHL";
11056 case X86ISD::VSRL: return "X86ISD::VSRL";
11057 case X86ISD::VSRA: return "X86ISD::VSRA";
11058 case X86ISD::VSHLI: return "X86ISD::VSHLI";
11059 case X86ISD::VSRLI: return "X86ISD::VSRLI";
11060 case X86ISD::VSRAI: return "X86ISD::VSRAI";
11061 case X86ISD::CMPP: return "X86ISD::CMPP";
11062 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
11063 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
11064 case X86ISD::ADD: return "X86ISD::ADD";
11065 case X86ISD::SUB: return "X86ISD::SUB";
11066 case X86ISD::ADC: return "X86ISD::ADC";
11067 case X86ISD::SBB: return "X86ISD::SBB";
11068 case X86ISD::SMUL: return "X86ISD::SMUL";
11069 case X86ISD::UMUL: return "X86ISD::UMUL";
11070 case X86ISD::INC: return "X86ISD::INC";
11071 case X86ISD::DEC: return "X86ISD::DEC";
11072 case X86ISD::OR: return "X86ISD::OR";
11073 case X86ISD::XOR: return "X86ISD::XOR";
11074 case X86ISD::AND: return "X86ISD::AND";
11075 case X86ISD::ANDN: return "X86ISD::ANDN";
11076 case X86ISD::BLSI: return "X86ISD::BLSI";
11077 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
11078 case X86ISD::BLSR: return "X86ISD::BLSR";
11079 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
11080 case X86ISD::PTEST: return "X86ISD::PTEST";
11081 case X86ISD::TESTP: return "X86ISD::TESTP";
11082 case X86ISD::PALIGN: return "X86ISD::PALIGN";
11083 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
11084 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
11085 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
11086 case X86ISD::SHUFP: return "X86ISD::SHUFP";
11087 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
11088 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
11089 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
11090 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
11091 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
11092 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
11093 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
11094 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
11095 case X86ISD::MOVSD: return "X86ISD::MOVSD";
11096 case X86ISD::MOVSS: return "X86ISD::MOVSS";
11097 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
11098 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
11099 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
11100 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
11101 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
11102 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
11103 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
11104 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
11105 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
11106 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
11107 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
11108 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
11112 // isLegalAddressingMode - Return true if the addressing mode represented
11113 // by AM is legal for this target, for a load/store of the specified type.
11114 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
11116 // X86 supports extremely general addressing modes.
11117 CodeModel::Model M = getTargetMachine().getCodeModel();
11118 Reloc::Model R = getTargetMachine().getRelocationModel();
11120 // X86 allows a sign-extended 32-bit immediate field as a displacement.
11121 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
11126 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
11128 // If a reference to this global requires an extra load, we can't fold it.
11129 if (isGlobalStubReference(GVFlags))
11132 // If BaseGV requires a register for the PIC base, we cannot also have a
11133 // BaseReg specified.
11134 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
11137 // If lower 4G is not available, then we must use rip-relative addressing.
11138 if ((M != CodeModel::Small || R != Reloc::Static) &&
11139 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
11143 switch (AM.Scale) {
11149 // These scales always work.
11154 // These scales are formed with basereg+scalereg. Only accept if there is
11159 default: // Other stuff never works.
11167 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11168 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11170 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11171 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11172 if (NumBits1 <= NumBits2)
11177 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11178 if (!VT1.isInteger() || !VT2.isInteger())
11180 unsigned NumBits1 = VT1.getSizeInBits();
11181 unsigned NumBits2 = VT2.getSizeInBits();
11182 if (NumBits1 <= NumBits2)
11187 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
11188 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11189 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
11192 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
11193 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
11194 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
11197 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
11198 // i16 instructions are longer (0x66 prefix) and potentially slower.
11199 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
11202 /// isShuffleMaskLegal - Targets can use this to indicate that they only
11203 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
11204 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
11205 /// are assumed to be legal.
11207 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
11209 // Very little shuffling can be done for 64-bit vectors right now.
11210 if (VT.getSizeInBits() == 64)
11213 // FIXME: pshufb, blends, shifts.
11214 return (VT.getVectorNumElements() == 2 ||
11215 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
11216 isMOVLMask(M, VT) ||
11217 isSHUFPMask(M, VT, Subtarget->hasAVX()) ||
11218 isPSHUFDMask(M, VT) ||
11219 isPSHUFHWMask(M, VT) ||
11220 isPSHUFLWMask(M, VT) ||
11221 isPALIGNRMask(M, VT, Subtarget) ||
11222 isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
11223 isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
11224 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||
11225 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasAVX2()));
11229 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
11231 unsigned NumElts = VT.getVectorNumElements();
11232 // FIXME: This collection of masks seems suspect.
11235 if (NumElts == 4 && VT.getSizeInBits() == 128) {
11236 return (isMOVLMask(Mask, VT) ||
11237 isCommutedMOVLMask(Mask, VT, true) ||
11238 isSHUFPMask(Mask, VT, Subtarget->hasAVX()) ||
11239 isSHUFPMask(Mask, VT, Subtarget->hasAVX(), /* Commuted */ true));
11244 //===----------------------------------------------------------------------===//
11245 // X86 Scheduler Hooks
11246 //===----------------------------------------------------------------------===//
11248 // private utility function
11249 MachineBasicBlock *
11250 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
11251 MachineBasicBlock *MBB,
11258 const TargetRegisterClass *RC,
11259 bool invSrc) const {
11260 // For the atomic bitwise operator, we generate
11263 // ld t1 = [bitinstr.addr]
11264 // op t2 = t1, [bitinstr.val]
11266 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11268 // fallthrough -->nextMBB
11269 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11270 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11271 MachineFunction::iterator MBBIter = MBB;
11274 /// First build the CFG
11275 MachineFunction *F = MBB->getParent();
11276 MachineBasicBlock *thisMBB = MBB;
11277 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11278 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11279 F->insert(MBBIter, newMBB);
11280 F->insert(MBBIter, nextMBB);
11282 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11283 nextMBB->splice(nextMBB->begin(), thisMBB,
11284 llvm::next(MachineBasicBlock::iterator(bInstr)),
11286 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11288 // Update thisMBB to fall through to newMBB
11289 thisMBB->addSuccessor(newMBB);
11291 // newMBB jumps to itself and fall through to nextMBB
11292 newMBB->addSuccessor(nextMBB);
11293 newMBB->addSuccessor(newMBB);
11295 // Insert instructions into newMBB based on incoming instruction
11296 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11297 "unexpected number of operands");
11298 DebugLoc dl = bInstr->getDebugLoc();
11299 MachineOperand& destOper = bInstr->getOperand(0);
11300 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11301 int numArgs = bInstr->getNumOperands() - 1;
11302 for (int i=0; i < numArgs; ++i)
11303 argOpers[i] = &bInstr->getOperand(i+1);
11305 // x86 address has 4 operands: base, index, scale, and displacement
11306 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11307 int valArgIndx = lastAddrIndx + 1;
11309 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11310 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
11311 for (int i=0; i <= lastAddrIndx; ++i)
11312 (*MIB).addOperand(*argOpers[i]);
11314 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
11316 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
11321 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11322 assert((argOpers[valArgIndx]->isReg() ||
11323 argOpers[valArgIndx]->isImm()) &&
11324 "invalid operand");
11325 if (argOpers[valArgIndx]->isReg())
11326 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
11328 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
11330 (*MIB).addOperand(*argOpers[valArgIndx]);
11332 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
11335 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
11336 for (int i=0; i <= lastAddrIndx; ++i)
11337 (*MIB).addOperand(*argOpers[i]);
11339 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11340 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11341 bInstr->memoperands_end());
11343 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11344 MIB.addReg(EAXreg);
11347 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11349 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11353 // private utility function: 64 bit atomics on 32 bit host.
11354 MachineBasicBlock *
11355 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
11356 MachineBasicBlock *MBB,
11361 bool invSrc) const {
11362 // For the atomic bitwise operator, we generate
11363 // thisMBB (instructions are in pairs, except cmpxchg8b)
11364 // ld t1,t2 = [bitinstr.addr]
11366 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
11367 // op t5, t6 <- out1, out2, [bitinstr.val]
11368 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
11369 // mov ECX, EBX <- t5, t6
11370 // mov EAX, EDX <- t1, t2
11371 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
11372 // mov t3, t4 <- EAX, EDX
11374 // result in out1, out2
11375 // fallthrough -->nextMBB
11377 const TargetRegisterClass *RC = X86::GR32RegisterClass;
11378 const unsigned LoadOpc = X86::MOV32rm;
11379 const unsigned NotOpc = X86::NOT32r;
11380 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11381 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11382 MachineFunction::iterator MBBIter = MBB;
11385 /// First build the CFG
11386 MachineFunction *F = MBB->getParent();
11387 MachineBasicBlock *thisMBB = MBB;
11388 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11389 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11390 F->insert(MBBIter, newMBB);
11391 F->insert(MBBIter, nextMBB);
11393 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11394 nextMBB->splice(nextMBB->begin(), thisMBB,
11395 llvm::next(MachineBasicBlock::iterator(bInstr)),
11397 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11399 // Update thisMBB to fall through to newMBB
11400 thisMBB->addSuccessor(newMBB);
11402 // newMBB jumps to itself and fall through to nextMBB
11403 newMBB->addSuccessor(nextMBB);
11404 newMBB->addSuccessor(newMBB);
11406 DebugLoc dl = bInstr->getDebugLoc();
11407 // Insert instructions into newMBB based on incoming instruction
11408 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11409 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11410 "unexpected number of operands");
11411 MachineOperand& dest1Oper = bInstr->getOperand(0);
11412 MachineOperand& dest2Oper = bInstr->getOperand(1);
11413 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11414 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11415 argOpers[i] = &bInstr->getOperand(i+2);
11417 // We use some of the operands multiple times, so conservatively just
11418 // clear any kill flags that might be present.
11419 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11420 argOpers[i]->setIsKill(false);
11423 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11424 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11426 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11427 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11428 for (int i=0; i <= lastAddrIndx; ++i)
11429 (*MIB).addOperand(*argOpers[i]);
11430 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11431 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11432 // add 4 to displacement.
11433 for (int i=0; i <= lastAddrIndx-2; ++i)
11434 (*MIB).addOperand(*argOpers[i]);
11435 MachineOperand newOp3 = *(argOpers[3]);
11436 if (newOp3.isImm())
11437 newOp3.setImm(newOp3.getImm()+4);
11439 newOp3.setOffset(newOp3.getOffset()+4);
11440 (*MIB).addOperand(newOp3);
11441 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11443 // t3/4 are defined later, at the bottom of the loop
11444 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11445 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11446 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11447 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11448 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11449 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11451 // The subsequent operations should be using the destination registers of
11452 //the PHI instructions.
11454 t1 = F->getRegInfo().createVirtualRegister(RC);
11455 t2 = F->getRegInfo().createVirtualRegister(RC);
11456 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11457 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11459 t1 = dest1Oper.getReg();
11460 t2 = dest2Oper.getReg();
11463 int valArgIndx = lastAddrIndx + 1;
11464 assert((argOpers[valArgIndx]->isReg() ||
11465 argOpers[valArgIndx]->isImm()) &&
11466 "invalid operand");
11467 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11468 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11469 if (argOpers[valArgIndx]->isReg())
11470 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11472 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11473 if (regOpcL != X86::MOV32rr)
11475 (*MIB).addOperand(*argOpers[valArgIndx]);
11476 assert(argOpers[valArgIndx + 1]->isReg() ==
11477 argOpers[valArgIndx]->isReg());
11478 assert(argOpers[valArgIndx + 1]->isImm() ==
11479 argOpers[valArgIndx]->isImm());
11480 if (argOpers[valArgIndx + 1]->isReg())
11481 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11483 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11484 if (regOpcH != X86::MOV32rr)
11486 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11488 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11490 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11493 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11495 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11498 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11499 for (int i=0; i <= lastAddrIndx; ++i)
11500 (*MIB).addOperand(*argOpers[i]);
11502 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11503 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11504 bInstr->memoperands_end());
11506 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11507 MIB.addReg(X86::EAX);
11508 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11509 MIB.addReg(X86::EDX);
11512 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11514 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11518 // private utility function
11519 MachineBasicBlock *
11520 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11521 MachineBasicBlock *MBB,
11522 unsigned cmovOpc) const {
11523 // For the atomic min/max operator, we generate
11526 // ld t1 = [min/max.addr]
11527 // mov t2 = [min/max.val]
11529 // cmov[cond] t2 = t1
11531 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11533 // fallthrough -->nextMBB
11535 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11536 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11537 MachineFunction::iterator MBBIter = MBB;
11540 /// First build the CFG
11541 MachineFunction *F = MBB->getParent();
11542 MachineBasicBlock *thisMBB = MBB;
11543 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11544 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11545 F->insert(MBBIter, newMBB);
11546 F->insert(MBBIter, nextMBB);
11548 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11549 nextMBB->splice(nextMBB->begin(), thisMBB,
11550 llvm::next(MachineBasicBlock::iterator(mInstr)),
11552 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11554 // Update thisMBB to fall through to newMBB
11555 thisMBB->addSuccessor(newMBB);
11557 // newMBB jumps to newMBB and fall through to nextMBB
11558 newMBB->addSuccessor(nextMBB);
11559 newMBB->addSuccessor(newMBB);
11561 DebugLoc dl = mInstr->getDebugLoc();
11562 // Insert instructions into newMBB based on incoming instruction
11563 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11564 "unexpected number of operands");
11565 MachineOperand& destOper = mInstr->getOperand(0);
11566 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11567 int numArgs = mInstr->getNumOperands() - 1;
11568 for (int i=0; i < numArgs; ++i)
11569 argOpers[i] = &mInstr->getOperand(i+1);
11571 // x86 address has 4 operands: base, index, scale, and displacement
11572 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11573 int valArgIndx = lastAddrIndx + 1;
11575 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11576 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11577 for (int i=0; i <= lastAddrIndx; ++i)
11578 (*MIB).addOperand(*argOpers[i]);
11580 // We only support register and immediate values
11581 assert((argOpers[valArgIndx]->isReg() ||
11582 argOpers[valArgIndx]->isImm()) &&
11583 "invalid operand");
11585 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11586 if (argOpers[valArgIndx]->isReg())
11587 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11589 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11590 (*MIB).addOperand(*argOpers[valArgIndx]);
11592 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11595 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11600 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11601 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11605 // Cmp and exchange if none has modified the memory location
11606 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11607 for (int i=0; i <= lastAddrIndx; ++i)
11608 (*MIB).addOperand(*argOpers[i]);
11610 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11611 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11612 mInstr->memoperands_end());
11614 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11615 MIB.addReg(X86::EAX);
11618 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11620 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11624 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11625 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11626 // in the .td file.
11627 MachineBasicBlock *
11628 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11629 unsigned numArgs, bool memArg) const {
11630 assert(Subtarget->hasSSE42() &&
11631 "Target must have SSE4.2 or AVX features enabled");
11633 DebugLoc dl = MI->getDebugLoc();
11634 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11636 if (!Subtarget->hasAVX()) {
11638 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11640 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11643 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11645 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11648 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11649 for (unsigned i = 0; i < numArgs; ++i) {
11650 MachineOperand &Op = MI->getOperand(i+1);
11651 if (!(Op.isReg() && Op.isImplicit()))
11652 MIB.addOperand(Op);
11654 BuildMI(*BB, MI, dl,
11655 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11656 MI->getOperand(0).getReg())
11657 .addReg(X86::XMM0);
11659 MI->eraseFromParent();
11663 MachineBasicBlock *
11664 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11665 DebugLoc dl = MI->getDebugLoc();
11666 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11668 // Address into RAX/EAX, other two args into ECX, EDX.
11669 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11670 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11671 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11672 for (int i = 0; i < X86::AddrNumOperands; ++i)
11673 MIB.addOperand(MI->getOperand(i));
11675 unsigned ValOps = X86::AddrNumOperands;
11676 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11677 .addReg(MI->getOperand(ValOps).getReg());
11678 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11679 .addReg(MI->getOperand(ValOps+1).getReg());
11681 // The instruction doesn't actually take any operands though.
11682 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11684 MI->eraseFromParent(); // The pseudo is gone now.
11688 MachineBasicBlock *
11689 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11690 DebugLoc dl = MI->getDebugLoc();
11691 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11693 // First arg in ECX, the second in EAX.
11694 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11695 .addReg(MI->getOperand(0).getReg());
11696 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11697 .addReg(MI->getOperand(1).getReg());
11699 // The instruction doesn't actually take any operands though.
11700 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11702 MI->eraseFromParent(); // The pseudo is gone now.
11706 MachineBasicBlock *
11707 X86TargetLowering::EmitVAARG64WithCustomInserter(
11709 MachineBasicBlock *MBB) const {
11710 // Emit va_arg instruction on X86-64.
11712 // Operands to this pseudo-instruction:
11713 // 0 ) Output : destination address (reg)
11714 // 1-5) Input : va_list address (addr, i64mem)
11715 // 6 ) ArgSize : Size (in bytes) of vararg type
11716 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11717 // 8 ) Align : Alignment of type
11718 // 9 ) EFLAGS (implicit-def)
11720 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11721 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11723 unsigned DestReg = MI->getOperand(0).getReg();
11724 MachineOperand &Base = MI->getOperand(1);
11725 MachineOperand &Scale = MI->getOperand(2);
11726 MachineOperand &Index = MI->getOperand(3);
11727 MachineOperand &Disp = MI->getOperand(4);
11728 MachineOperand &Segment = MI->getOperand(5);
11729 unsigned ArgSize = MI->getOperand(6).getImm();
11730 unsigned ArgMode = MI->getOperand(7).getImm();
11731 unsigned Align = MI->getOperand(8).getImm();
11733 // Memory Reference
11734 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11735 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11736 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11738 // Machine Information
11739 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11740 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11741 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11742 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11743 DebugLoc DL = MI->getDebugLoc();
11745 // struct va_list {
11748 // i64 overflow_area (address)
11749 // i64 reg_save_area (address)
11751 // sizeof(va_list) = 24
11752 // alignment(va_list) = 8
11754 unsigned TotalNumIntRegs = 6;
11755 unsigned TotalNumXMMRegs = 8;
11756 bool UseGPOffset = (ArgMode == 1);
11757 bool UseFPOffset = (ArgMode == 2);
11758 unsigned MaxOffset = TotalNumIntRegs * 8 +
11759 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11761 /* Align ArgSize to a multiple of 8 */
11762 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11763 bool NeedsAlign = (Align > 8);
11765 MachineBasicBlock *thisMBB = MBB;
11766 MachineBasicBlock *overflowMBB;
11767 MachineBasicBlock *offsetMBB;
11768 MachineBasicBlock *endMBB;
11770 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11771 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11772 unsigned OffsetReg = 0;
11774 if (!UseGPOffset && !UseFPOffset) {
11775 // If we only pull from the overflow region, we don't create a branch.
11776 // We don't need to alter control flow.
11777 OffsetDestReg = 0; // unused
11778 OverflowDestReg = DestReg;
11781 overflowMBB = thisMBB;
11784 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11785 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11786 // If not, pull from overflow_area. (branch to overflowMBB)
11791 // offsetMBB overflowMBB
11796 // Registers for the PHI in endMBB
11797 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11798 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11800 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11801 MachineFunction *MF = MBB->getParent();
11802 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11803 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11804 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11806 MachineFunction::iterator MBBIter = MBB;
11809 // Insert the new basic blocks
11810 MF->insert(MBBIter, offsetMBB);
11811 MF->insert(MBBIter, overflowMBB);
11812 MF->insert(MBBIter, endMBB);
11814 // Transfer the remainder of MBB and its successor edges to endMBB.
11815 endMBB->splice(endMBB->begin(), thisMBB,
11816 llvm::next(MachineBasicBlock::iterator(MI)),
11818 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11820 // Make offsetMBB and overflowMBB successors of thisMBB
11821 thisMBB->addSuccessor(offsetMBB);
11822 thisMBB->addSuccessor(overflowMBB);
11824 // endMBB is a successor of both offsetMBB and overflowMBB
11825 offsetMBB->addSuccessor(endMBB);
11826 overflowMBB->addSuccessor(endMBB);
11828 // Load the offset value into a register
11829 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11830 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11834 .addDisp(Disp, UseFPOffset ? 4 : 0)
11835 .addOperand(Segment)
11836 .setMemRefs(MMOBegin, MMOEnd);
11838 // Check if there is enough room left to pull this argument.
11839 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11841 .addImm(MaxOffset + 8 - ArgSizeA8);
11843 // Branch to "overflowMBB" if offset >= max
11844 // Fall through to "offsetMBB" otherwise
11845 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11846 .addMBB(overflowMBB);
11849 // In offsetMBB, emit code to use the reg_save_area.
11851 assert(OffsetReg != 0);
11853 // Read the reg_save_area address.
11854 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11855 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11860 .addOperand(Segment)
11861 .setMemRefs(MMOBegin, MMOEnd);
11863 // Zero-extend the offset
11864 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11865 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11868 .addImm(X86::sub_32bit);
11870 // Add the offset to the reg_save_area to get the final address.
11871 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11872 .addReg(OffsetReg64)
11873 .addReg(RegSaveReg);
11875 // Compute the offset for the next argument
11876 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11877 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11879 .addImm(UseFPOffset ? 16 : 8);
11881 // Store it back into the va_list.
11882 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11886 .addDisp(Disp, UseFPOffset ? 4 : 0)
11887 .addOperand(Segment)
11888 .addReg(NextOffsetReg)
11889 .setMemRefs(MMOBegin, MMOEnd);
11892 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11897 // Emit code to use overflow area
11900 // Load the overflow_area address into a register.
11901 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11902 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11907 .addOperand(Segment)
11908 .setMemRefs(MMOBegin, MMOEnd);
11910 // If we need to align it, do so. Otherwise, just copy the address
11911 // to OverflowDestReg.
11913 // Align the overflow address
11914 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11915 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11917 // aligned_addr = (addr + (align-1)) & ~(align-1)
11918 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11919 .addReg(OverflowAddrReg)
11922 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11924 .addImm(~(uint64_t)(Align-1));
11926 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11927 .addReg(OverflowAddrReg);
11930 // Compute the next overflow address after this argument.
11931 // (the overflow address should be kept 8-byte aligned)
11932 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11933 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11934 .addReg(OverflowDestReg)
11935 .addImm(ArgSizeA8);
11937 // Store the new overflow address.
11938 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11943 .addOperand(Segment)
11944 .addReg(NextAddrReg)
11945 .setMemRefs(MMOBegin, MMOEnd);
11947 // If we branched, emit the PHI to the front of endMBB.
11949 BuildMI(*endMBB, endMBB->begin(), DL,
11950 TII->get(X86::PHI), DestReg)
11951 .addReg(OffsetDestReg).addMBB(offsetMBB)
11952 .addReg(OverflowDestReg).addMBB(overflowMBB);
11955 // Erase the pseudo instruction
11956 MI->eraseFromParent();
11961 MachineBasicBlock *
11962 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11964 MachineBasicBlock *MBB) const {
11965 // Emit code to save XMM registers to the stack. The ABI says that the
11966 // number of registers to save is given in %al, so it's theoretically
11967 // possible to do an indirect jump trick to avoid saving all of them,
11968 // however this code takes a simpler approach and just executes all
11969 // of the stores if %al is non-zero. It's less code, and it's probably
11970 // easier on the hardware branch predictor, and stores aren't all that
11971 // expensive anyway.
11973 // Create the new basic blocks. One block contains all the XMM stores,
11974 // and one block is the final destination regardless of whether any
11975 // stores were performed.
11976 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11977 MachineFunction *F = MBB->getParent();
11978 MachineFunction::iterator MBBIter = MBB;
11980 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11981 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11982 F->insert(MBBIter, XMMSaveMBB);
11983 F->insert(MBBIter, EndMBB);
11985 // Transfer the remainder of MBB and its successor edges to EndMBB.
11986 EndMBB->splice(EndMBB->begin(), MBB,
11987 llvm::next(MachineBasicBlock::iterator(MI)),
11989 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11991 // The original block will now fall through to the XMM save block.
11992 MBB->addSuccessor(XMMSaveMBB);
11993 // The XMMSaveMBB will fall through to the end block.
11994 XMMSaveMBB->addSuccessor(EndMBB);
11996 // Now add the instructions.
11997 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11998 DebugLoc DL = MI->getDebugLoc();
12000 unsigned CountReg = MI->getOperand(0).getReg();
12001 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
12002 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
12004 if (!Subtarget->isTargetWin64()) {
12005 // If %al is 0, branch around the XMM save block.
12006 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
12007 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
12008 MBB->addSuccessor(EndMBB);
12011 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
12012 // In the XMM save block, save all the XMM argument registers.
12013 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
12014 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
12015 MachineMemOperand *MMO =
12016 F->getMachineMemOperand(
12017 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
12018 MachineMemOperand::MOStore,
12019 /*Size=*/16, /*Align=*/16);
12020 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
12021 .addFrameIndex(RegSaveFrameIndex)
12022 .addImm(/*Scale=*/1)
12023 .addReg(/*IndexReg=*/0)
12024 .addImm(/*Disp=*/Offset)
12025 .addReg(/*Segment=*/0)
12026 .addReg(MI->getOperand(i).getReg())
12027 .addMemOperand(MMO);
12030 MI->eraseFromParent(); // The pseudo instruction is gone now.
12035 // The EFLAGS operand of SelectItr might be missing a kill marker
12036 // because there were multiple uses of EFLAGS, and ISel didn't know
12037 // which to mark. Figure out whether SelectItr should have had a
12038 // kill marker, and set it if it should. Returns the correct kill
12040 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
12041 MachineBasicBlock* BB,
12042 const TargetRegisterInfo* TRI) {
12043 // Scan forward through BB for a use/def of EFLAGS.
12044 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
12045 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
12046 const MachineInstr& mi = *miI;
12047 if (mi.readsRegister(X86::EFLAGS))
12049 if (mi.definesRegister(X86::EFLAGS))
12050 break; // Should have kill-flag - update below.
12053 // If we hit the end of the block, check whether EFLAGS is live into a
12055 if (miI == BB->end()) {
12056 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
12057 sEnd = BB->succ_end();
12058 sItr != sEnd; ++sItr) {
12059 MachineBasicBlock* succ = *sItr;
12060 if (succ->isLiveIn(X86::EFLAGS))
12065 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
12066 // out. SelectMI should have a kill flag on EFLAGS.
12067 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
12071 MachineBasicBlock *
12072 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
12073 MachineBasicBlock *BB) const {
12074 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12075 DebugLoc DL = MI->getDebugLoc();
12077 // To "insert" a SELECT_CC instruction, we actually have to insert the
12078 // diamond control-flow pattern. The incoming instruction knows the
12079 // destination vreg to set, the condition code register to branch on, the
12080 // true/false values to select between, and a branch opcode to use.
12081 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12082 MachineFunction::iterator It = BB;
12088 // cmpTY ccX, r1, r2
12090 // fallthrough --> copy0MBB
12091 MachineBasicBlock *thisMBB = BB;
12092 MachineFunction *F = BB->getParent();
12093 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
12094 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
12095 F->insert(It, copy0MBB);
12096 F->insert(It, sinkMBB);
12098 // If the EFLAGS register isn't dead in the terminator, then claim that it's
12099 // live into the sink and copy blocks.
12100 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
12101 if (!MI->killsRegister(X86::EFLAGS) &&
12102 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
12103 copy0MBB->addLiveIn(X86::EFLAGS);
12104 sinkMBB->addLiveIn(X86::EFLAGS);
12107 // Transfer the remainder of BB and its successor edges to sinkMBB.
12108 sinkMBB->splice(sinkMBB->begin(), BB,
12109 llvm::next(MachineBasicBlock::iterator(MI)),
12111 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
12113 // Add the true and fallthrough blocks as its successors.
12114 BB->addSuccessor(copy0MBB);
12115 BB->addSuccessor(sinkMBB);
12117 // Create the conditional branch instruction.
12119 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
12120 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
12123 // %FalseValue = ...
12124 // # fallthrough to sinkMBB
12125 copy0MBB->addSuccessor(sinkMBB);
12128 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
12130 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12131 TII->get(X86::PHI), MI->getOperand(0).getReg())
12132 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
12133 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
12135 MI->eraseFromParent(); // The pseudo instruction is gone now.
12139 MachineBasicBlock *
12140 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
12141 bool Is64Bit) const {
12142 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12143 DebugLoc DL = MI->getDebugLoc();
12144 MachineFunction *MF = BB->getParent();
12145 const BasicBlock *LLVM_BB = BB->getBasicBlock();
12147 assert(getTargetMachine().Options.EnableSegmentedStacks);
12149 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
12150 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
12153 // ... [Till the alloca]
12154 // If stacklet is not large enough, jump to mallocMBB
12157 // Allocate by subtracting from RSP
12158 // Jump to continueMBB
12161 // Allocate by call to runtime
12165 // [rest of original BB]
12168 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12169 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12170 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
12172 MachineRegisterInfo &MRI = MF->getRegInfo();
12173 const TargetRegisterClass *AddrRegClass =
12174 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
12176 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12177 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
12178 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
12179 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
12180 sizeVReg = MI->getOperand(1).getReg(),
12181 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
12183 MachineFunction::iterator MBBIter = BB;
12186 MF->insert(MBBIter, bumpMBB);
12187 MF->insert(MBBIter, mallocMBB);
12188 MF->insert(MBBIter, continueMBB);
12190 continueMBB->splice(continueMBB->begin(), BB, llvm::next
12191 (MachineBasicBlock::iterator(MI)), BB->end());
12192 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
12194 // Add code to the main basic block to check if the stack limit has been hit,
12195 // and if so, jump to mallocMBB otherwise to bumpMBB.
12196 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
12197 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
12198 .addReg(tmpSPVReg).addReg(sizeVReg);
12199 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
12200 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
12201 .addReg(SPLimitVReg);
12202 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
12204 // bumpMBB simply decreases the stack pointer, since we know the current
12205 // stacklet has enough space.
12206 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
12207 .addReg(SPLimitVReg);
12208 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
12209 .addReg(SPLimitVReg);
12210 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12212 // Calls into a routine in libgcc to allocate more space from the heap.
12213 const uint32_t *RegMask =
12214 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12216 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
12218 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
12219 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI)
12220 .addRegMask(RegMask)
12221 .addReg(X86::RAX, RegState::ImplicitDefine);
12223 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
12225 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
12226 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
12227 .addExternalSymbol("__morestack_allocate_stack_space")
12228 .addRegMask(RegMask)
12229 .addReg(X86::EAX, RegState::ImplicitDefine);
12233 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
12236 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
12237 .addReg(Is64Bit ? X86::RAX : X86::EAX);
12238 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
12240 // Set up the CFG correctly.
12241 BB->addSuccessor(bumpMBB);
12242 BB->addSuccessor(mallocMBB);
12243 mallocMBB->addSuccessor(continueMBB);
12244 bumpMBB->addSuccessor(continueMBB);
12246 // Take care of the PHI nodes.
12247 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
12248 MI->getOperand(0).getReg())
12249 .addReg(mallocPtrVReg).addMBB(mallocMBB)
12250 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
12252 // Delete the original pseudo instruction.
12253 MI->eraseFromParent();
12256 return continueMBB;
12259 MachineBasicBlock *
12260 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
12261 MachineBasicBlock *BB) const {
12262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12263 DebugLoc DL = MI->getDebugLoc();
12265 assert(!Subtarget->isTargetEnvMacho());
12267 // The lowering is pretty easy: we're just emitting the call to _alloca. The
12268 // non-trivial part is impdef of ESP.
12270 if (Subtarget->isTargetWin64()) {
12271 if (Subtarget->isTargetCygMing()) {
12272 // ___chkstk(Mingw64):
12273 // Clobbers R10, R11, RAX and EFLAGS.
12275 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12276 .addExternalSymbol("___chkstk")
12277 .addReg(X86::RAX, RegState::Implicit)
12278 .addReg(X86::RSP, RegState::Implicit)
12279 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
12280 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
12281 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12283 // __chkstk(MSVCRT): does not update stack pointer.
12284 // Clobbers R10, R11 and EFLAGS.
12285 // FIXME: RAX(allocated size) might be reused and not killed.
12286 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
12287 .addExternalSymbol("__chkstk")
12288 .addReg(X86::RAX, RegState::Implicit)
12289 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12290 // RAX has the offset to subtracted from RSP.
12291 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
12296 const char *StackProbeSymbol =
12297 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
12299 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
12300 .addExternalSymbol(StackProbeSymbol)
12301 .addReg(X86::EAX, RegState::Implicit)
12302 .addReg(X86::ESP, RegState::Implicit)
12303 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
12304 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
12305 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
12308 MI->eraseFromParent(); // The pseudo instruction is gone now.
12312 MachineBasicBlock *
12313 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
12314 MachineBasicBlock *BB) const {
12315 // This is pretty easy. We're taking the value that we received from
12316 // our load from the relocation, sticking it in either RDI (x86-64)
12317 // or EAX and doing an indirect call. The return value will then
12318 // be in the normal return register.
12319 const X86InstrInfo *TII
12320 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
12321 DebugLoc DL = MI->getDebugLoc();
12322 MachineFunction *F = BB->getParent();
12324 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
12325 assert(MI->getOperand(3).isGlobal() && "This should be a global");
12327 // Get a register mask for the lowered call.
12328 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
12329 // proper register mask.
12330 const uint32_t *RegMask =
12331 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
12332 if (Subtarget->is64Bit()) {
12333 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12334 TII->get(X86::MOV64rm), X86::RDI)
12336 .addImm(0).addReg(0)
12337 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12338 MI->getOperand(3).getTargetFlags())
12340 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
12341 addDirectMem(MIB, X86::RDI);
12342 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
12343 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
12344 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12345 TII->get(X86::MOV32rm), X86::EAX)
12347 .addImm(0).addReg(0)
12348 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12349 MI->getOperand(3).getTargetFlags())
12351 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12352 addDirectMem(MIB, X86::EAX);
12353 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12355 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
12356 TII->get(X86::MOV32rm), X86::EAX)
12357 .addReg(TII->getGlobalBaseReg(F))
12358 .addImm(0).addReg(0)
12359 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
12360 MI->getOperand(3).getTargetFlags())
12362 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
12363 addDirectMem(MIB, X86::EAX);
12364 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
12367 MI->eraseFromParent(); // The pseudo instruction is gone now.
12371 MachineBasicBlock *
12372 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
12373 MachineBasicBlock *BB) const {
12374 switch (MI->getOpcode()) {
12375 default: llvm_unreachable("Unexpected instr type to insert");
12376 case X86::TAILJMPd64:
12377 case X86::TAILJMPr64:
12378 case X86::TAILJMPm64:
12379 llvm_unreachable("TAILJMP64 would not be touched here.");
12380 case X86::TCRETURNdi64:
12381 case X86::TCRETURNri64:
12382 case X86::TCRETURNmi64:
12384 case X86::WIN_ALLOCA:
12385 return EmitLoweredWinAlloca(MI, BB);
12386 case X86::SEG_ALLOCA_32:
12387 return EmitLoweredSegAlloca(MI, BB, false);
12388 case X86::SEG_ALLOCA_64:
12389 return EmitLoweredSegAlloca(MI, BB, true);
12390 case X86::TLSCall_32:
12391 case X86::TLSCall_64:
12392 return EmitLoweredTLSCall(MI, BB);
12393 case X86::CMOV_GR8:
12394 case X86::CMOV_FR32:
12395 case X86::CMOV_FR64:
12396 case X86::CMOV_V4F32:
12397 case X86::CMOV_V2F64:
12398 case X86::CMOV_V2I64:
12399 case X86::CMOV_V8F32:
12400 case X86::CMOV_V4F64:
12401 case X86::CMOV_V4I64:
12402 case X86::CMOV_GR16:
12403 case X86::CMOV_GR32:
12404 case X86::CMOV_RFP32:
12405 case X86::CMOV_RFP64:
12406 case X86::CMOV_RFP80:
12407 return EmitLoweredSelect(MI, BB);
12409 case X86::FP32_TO_INT16_IN_MEM:
12410 case X86::FP32_TO_INT32_IN_MEM:
12411 case X86::FP32_TO_INT64_IN_MEM:
12412 case X86::FP64_TO_INT16_IN_MEM:
12413 case X86::FP64_TO_INT32_IN_MEM:
12414 case X86::FP64_TO_INT64_IN_MEM:
12415 case X86::FP80_TO_INT16_IN_MEM:
12416 case X86::FP80_TO_INT32_IN_MEM:
12417 case X86::FP80_TO_INT64_IN_MEM: {
12418 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12419 DebugLoc DL = MI->getDebugLoc();
12421 // Change the floating point control register to use "round towards zero"
12422 // mode when truncating to an integer value.
12423 MachineFunction *F = BB->getParent();
12424 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
12425 addFrameReference(BuildMI(*BB, MI, DL,
12426 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12428 // Load the old value of the high byte of the control word...
12430 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12431 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12434 // Set the high part to be round to zero...
12435 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12438 // Reload the modified control word now...
12439 addFrameReference(BuildMI(*BB, MI, DL,
12440 TII->get(X86::FLDCW16m)), CWFrameIdx);
12442 // Restore the memory image of control word to original value
12443 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12446 // Get the X86 opcode to use.
12448 switch (MI->getOpcode()) {
12449 default: llvm_unreachable("illegal opcode!");
12450 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12451 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12452 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12453 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12454 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12455 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12456 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12457 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12458 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12462 MachineOperand &Op = MI->getOperand(0);
12464 AM.BaseType = X86AddressMode::RegBase;
12465 AM.Base.Reg = Op.getReg();
12467 AM.BaseType = X86AddressMode::FrameIndexBase;
12468 AM.Base.FrameIndex = Op.getIndex();
12470 Op = MI->getOperand(1);
12472 AM.Scale = Op.getImm();
12473 Op = MI->getOperand(2);
12475 AM.IndexReg = Op.getImm();
12476 Op = MI->getOperand(3);
12477 if (Op.isGlobal()) {
12478 AM.GV = Op.getGlobal();
12480 AM.Disp = Op.getImm();
12482 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12483 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12485 // Reload the original control word now.
12486 addFrameReference(BuildMI(*BB, MI, DL,
12487 TII->get(X86::FLDCW16m)), CWFrameIdx);
12489 MI->eraseFromParent(); // The pseudo instruction is gone now.
12492 // String/text processing lowering.
12493 case X86::PCMPISTRM128REG:
12494 case X86::VPCMPISTRM128REG:
12495 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12496 case X86::PCMPISTRM128MEM:
12497 case X86::VPCMPISTRM128MEM:
12498 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12499 case X86::PCMPESTRM128REG:
12500 case X86::VPCMPESTRM128REG:
12501 return EmitPCMP(MI, BB, 5, false /* in mem */);
12502 case X86::PCMPESTRM128MEM:
12503 case X86::VPCMPESTRM128MEM:
12504 return EmitPCMP(MI, BB, 5, true /* in mem */);
12506 // Thread synchronization.
12508 return EmitMonitor(MI, BB);
12510 return EmitMwait(MI, BB);
12512 // Atomic Lowering.
12513 case X86::ATOMAND32:
12514 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12515 X86::AND32ri, X86::MOV32rm,
12517 X86::NOT32r, X86::EAX,
12518 X86::GR32RegisterClass);
12519 case X86::ATOMOR32:
12520 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12521 X86::OR32ri, X86::MOV32rm,
12523 X86::NOT32r, X86::EAX,
12524 X86::GR32RegisterClass);
12525 case X86::ATOMXOR32:
12526 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12527 X86::XOR32ri, X86::MOV32rm,
12529 X86::NOT32r, X86::EAX,
12530 X86::GR32RegisterClass);
12531 case X86::ATOMNAND32:
12532 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12533 X86::AND32ri, X86::MOV32rm,
12535 X86::NOT32r, X86::EAX,
12536 X86::GR32RegisterClass, true);
12537 case X86::ATOMMIN32:
12538 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12539 case X86::ATOMMAX32:
12540 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12541 case X86::ATOMUMIN32:
12542 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12543 case X86::ATOMUMAX32:
12544 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12546 case X86::ATOMAND16:
12547 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12548 X86::AND16ri, X86::MOV16rm,
12550 X86::NOT16r, X86::AX,
12551 X86::GR16RegisterClass);
12552 case X86::ATOMOR16:
12553 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12554 X86::OR16ri, X86::MOV16rm,
12556 X86::NOT16r, X86::AX,
12557 X86::GR16RegisterClass);
12558 case X86::ATOMXOR16:
12559 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12560 X86::XOR16ri, X86::MOV16rm,
12562 X86::NOT16r, X86::AX,
12563 X86::GR16RegisterClass);
12564 case X86::ATOMNAND16:
12565 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12566 X86::AND16ri, X86::MOV16rm,
12568 X86::NOT16r, X86::AX,
12569 X86::GR16RegisterClass, true);
12570 case X86::ATOMMIN16:
12571 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12572 case X86::ATOMMAX16:
12573 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12574 case X86::ATOMUMIN16:
12575 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12576 case X86::ATOMUMAX16:
12577 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12579 case X86::ATOMAND8:
12580 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12581 X86::AND8ri, X86::MOV8rm,
12583 X86::NOT8r, X86::AL,
12584 X86::GR8RegisterClass);
12586 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12587 X86::OR8ri, X86::MOV8rm,
12589 X86::NOT8r, X86::AL,
12590 X86::GR8RegisterClass);
12591 case X86::ATOMXOR8:
12592 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12593 X86::XOR8ri, X86::MOV8rm,
12595 X86::NOT8r, X86::AL,
12596 X86::GR8RegisterClass);
12597 case X86::ATOMNAND8:
12598 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12599 X86::AND8ri, X86::MOV8rm,
12601 X86::NOT8r, X86::AL,
12602 X86::GR8RegisterClass, true);
12603 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12604 // This group is for 64-bit host.
12605 case X86::ATOMAND64:
12606 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12607 X86::AND64ri32, X86::MOV64rm,
12609 X86::NOT64r, X86::RAX,
12610 X86::GR64RegisterClass);
12611 case X86::ATOMOR64:
12612 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12613 X86::OR64ri32, X86::MOV64rm,
12615 X86::NOT64r, X86::RAX,
12616 X86::GR64RegisterClass);
12617 case X86::ATOMXOR64:
12618 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12619 X86::XOR64ri32, X86::MOV64rm,
12621 X86::NOT64r, X86::RAX,
12622 X86::GR64RegisterClass);
12623 case X86::ATOMNAND64:
12624 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12625 X86::AND64ri32, X86::MOV64rm,
12627 X86::NOT64r, X86::RAX,
12628 X86::GR64RegisterClass, true);
12629 case X86::ATOMMIN64:
12630 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12631 case X86::ATOMMAX64:
12632 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12633 case X86::ATOMUMIN64:
12634 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12635 case X86::ATOMUMAX64:
12636 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12638 // This group does 64-bit operations on a 32-bit host.
12639 case X86::ATOMAND6432:
12640 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12641 X86::AND32rr, X86::AND32rr,
12642 X86::AND32ri, X86::AND32ri,
12644 case X86::ATOMOR6432:
12645 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12646 X86::OR32rr, X86::OR32rr,
12647 X86::OR32ri, X86::OR32ri,
12649 case X86::ATOMXOR6432:
12650 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12651 X86::XOR32rr, X86::XOR32rr,
12652 X86::XOR32ri, X86::XOR32ri,
12654 case X86::ATOMNAND6432:
12655 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12656 X86::AND32rr, X86::AND32rr,
12657 X86::AND32ri, X86::AND32ri,
12659 case X86::ATOMADD6432:
12660 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12661 X86::ADD32rr, X86::ADC32rr,
12662 X86::ADD32ri, X86::ADC32ri,
12664 case X86::ATOMSUB6432:
12665 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12666 X86::SUB32rr, X86::SBB32rr,
12667 X86::SUB32ri, X86::SBB32ri,
12669 case X86::ATOMSWAP6432:
12670 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12671 X86::MOV32rr, X86::MOV32rr,
12672 X86::MOV32ri, X86::MOV32ri,
12674 case X86::VASTART_SAVE_XMM_REGS:
12675 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12677 case X86::VAARG_64:
12678 return EmitVAARG64WithCustomInserter(MI, BB);
12682 //===----------------------------------------------------------------------===//
12683 // X86 Optimization Hooks
12684 //===----------------------------------------------------------------------===//
12686 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12690 const SelectionDAG &DAG,
12691 unsigned Depth) const {
12692 unsigned Opc = Op.getOpcode();
12693 assert((Opc >= ISD::BUILTIN_OP_END ||
12694 Opc == ISD::INTRINSIC_WO_CHAIN ||
12695 Opc == ISD::INTRINSIC_W_CHAIN ||
12696 Opc == ISD::INTRINSIC_VOID) &&
12697 "Should use MaskedValueIsZero if you don't know whether Op"
12698 " is a target node!");
12700 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12714 // These nodes' second result is a boolean.
12715 if (Op.getResNo() == 0)
12718 case X86ISD::SETCC:
12719 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12720 Mask.getBitWidth() - 1);
12722 case ISD::INTRINSIC_WO_CHAIN: {
12723 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
12724 unsigned NumLoBits = 0;
12727 case Intrinsic::x86_sse_movmsk_ps:
12728 case Intrinsic::x86_avx_movmsk_ps_256:
12729 case Intrinsic::x86_sse2_movmsk_pd:
12730 case Intrinsic::x86_avx_movmsk_pd_256:
12731 case Intrinsic::x86_mmx_pmovmskb:
12732 case Intrinsic::x86_sse2_pmovmskb_128:
12733 case Intrinsic::x86_avx2_pmovmskb: {
12734 // High bits of movmskp{s|d}, pmovmskb are known zero.
12736 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
12737 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
12738 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
12739 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
12740 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
12741 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
12742 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
12743 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
12745 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
12746 Mask.getBitWidth() - NumLoBits);
12755 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12756 unsigned Depth) const {
12757 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12758 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12759 return Op.getValueType().getScalarType().getSizeInBits();
12765 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12766 /// node is a GlobalAddress + offset.
12767 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12768 const GlobalValue* &GA,
12769 int64_t &Offset) const {
12770 if (N->getOpcode() == X86ISD::Wrapper) {
12771 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12772 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12773 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12777 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12780 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12781 /// same as extracting the high 128-bit part of 256-bit vector and then
12782 /// inserting the result into the low part of a new 256-bit vector
12783 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12784 EVT VT = SVOp->getValueType(0);
12785 int NumElems = VT.getVectorNumElements();
12787 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12788 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12789 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12790 SVOp->getMaskElt(j) >= 0)
12796 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12797 /// same as extracting the low 128-bit part of 256-bit vector and then
12798 /// inserting the result into the high part of a new 256-bit vector
12799 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12800 EVT VT = SVOp->getValueType(0);
12801 int NumElems = VT.getVectorNumElements();
12803 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12804 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12805 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12806 SVOp->getMaskElt(j) >= 0)
12812 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12813 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12814 TargetLowering::DAGCombinerInfo &DCI,
12815 const X86Subtarget* Subtarget) {
12816 DebugLoc dl = N->getDebugLoc();
12817 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12818 SDValue V1 = SVOp->getOperand(0);
12819 SDValue V2 = SVOp->getOperand(1);
12820 EVT VT = SVOp->getValueType(0);
12821 int NumElems = VT.getVectorNumElements();
12823 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12824 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12828 // V UNDEF BUILD_VECTOR UNDEF
12830 // CONCAT_VECTOR CONCAT_VECTOR
12833 // RESULT: V + zero extended
12835 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12836 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12837 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12840 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12843 // To match the shuffle mask, the first half of the mask should
12844 // be exactly the first vector, and all the rest a splat with the
12845 // first element of the second one.
12846 for (int i = 0; i < NumElems/2; ++i)
12847 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12848 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12851 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
12852 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
12853 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
12854 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
12856 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
12858 Ld->getPointerInfo(),
12859 Ld->getAlignment(),
12860 false/*isVolatile*/, true/*ReadMem*/,
12861 false/*WriteMem*/);
12862 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
12865 // Emit a zeroed vector and insert the desired subvector on its
12867 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
12868 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12869 DAG.getConstant(0, MVT::i32), DAG, dl);
12870 return DCI.CombineTo(N, InsV);
12873 //===--------------------------------------------------------------------===//
12874 // Combine some shuffles into subvector extracts and inserts:
12877 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12878 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12879 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12881 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12882 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12883 return DCI.CombineTo(N, InsV);
12886 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12887 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12888 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12889 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12890 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12891 return DCI.CombineTo(N, InsV);
12897 /// PerformShuffleCombine - Performs several different shuffle combines.
12898 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12899 TargetLowering::DAGCombinerInfo &DCI,
12900 const X86Subtarget *Subtarget) {
12901 DebugLoc dl = N->getDebugLoc();
12902 EVT VT = N->getValueType(0);
12904 // Don't create instructions with illegal types after legalize types has run.
12905 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12906 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12909 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12910 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12911 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12912 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
12914 // Only handle 128 wide vector from here on.
12915 if (VT.getSizeInBits() != 128)
12918 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12919 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12920 // consecutive, non-overlapping, and in the right order.
12921 SmallVector<SDValue, 16> Elts;
12922 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12923 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12925 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12929 /// PerformTruncateCombine - Converts truncate operation to
12930 /// a sequence of vector shuffle operations.
12931 /// It is possible when we truncate 256-bit vector to 128-bit vector
12933 SDValue X86TargetLowering::PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
12934 DAGCombinerInfo &DCI) const {
12935 if (!DCI.isBeforeLegalizeOps())
12938 if (!Subtarget->hasAVX()) return SDValue();
12940 EVT VT = N->getValueType(0);
12941 SDValue Op = N->getOperand(0);
12942 EVT OpVT = Op.getValueType();
12943 DebugLoc dl = N->getDebugLoc();
12945 if ((VT == MVT::v4i32) && (OpVT == MVT::v4i64)) {
12947 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12948 DAG.getIntPtrConstant(0));
12950 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i64, Op,
12951 DAG.getIntPtrConstant(2));
12953 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12954 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12957 int ShufMask1[] = {0, 2, 0, 0};
12959 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, DAG.getUNDEF(VT),
12961 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, DAG.getUNDEF(VT),
12965 int ShufMask2[] = {0, 1, 4, 5};
12967 return DAG.getVectorShuffle(VT, dl, OpLo, OpHi, ShufMask2);
12969 if ((VT == MVT::v8i16) && (OpVT == MVT::v8i32)) {
12971 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12972 DAG.getIntPtrConstant(0));
12974 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i32, Op,
12975 DAG.getIntPtrConstant(4));
12977 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLo);
12978 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpHi);
12981 int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12982 -1, -1, -1, -1, -1, -1, -1, -1};
12984 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo,
12985 DAG.getUNDEF(MVT::v16i8),
12987 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi,
12988 DAG.getUNDEF(MVT::v16i8),
12991 OpLo = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpLo);
12992 OpHi = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, OpHi);
12995 int ShufMask2[] = {0, 1, 4, 5};
12997 SDValue res = DAG.getVectorShuffle(MVT::v4i32, dl, OpLo, OpHi, ShufMask2);
12998 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, res);
13004 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
13005 /// generation and convert it from being a bunch of shuffles and extracts
13006 /// to a simple store and scalar loads to extract the elements.
13007 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
13008 const TargetLowering &TLI) {
13009 SDValue InputVector = N->getOperand(0);
13011 // Only operate on vectors of 4 elements, where the alternative shuffling
13012 // gets to be more expensive.
13013 if (InputVector.getValueType() != MVT::v4i32)
13016 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
13017 // single use which is a sign-extend or zero-extend, and all elements are
13019 SmallVector<SDNode *, 4> Uses;
13020 unsigned ExtractedElements = 0;
13021 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
13022 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
13023 if (UI.getUse().getResNo() != InputVector.getResNo())
13026 SDNode *Extract = *UI;
13027 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13030 if (Extract->getValueType(0) != MVT::i32)
13032 if (!Extract->hasOneUse())
13034 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
13035 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
13037 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
13040 // Record which element was extracted.
13041 ExtractedElements |=
13042 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
13044 Uses.push_back(Extract);
13047 // If not all the elements were used, this may not be worthwhile.
13048 if (ExtractedElements != 15)
13051 // Ok, we've now decided to do the transformation.
13052 DebugLoc dl = InputVector.getDebugLoc();
13054 // Store the value to a temporary stack slot.
13055 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
13056 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
13057 MachinePointerInfo(), false, false, 0);
13059 // Replace each use (extract) with a load of the appropriate element.
13060 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
13061 UE = Uses.end(); UI != UE; ++UI) {
13062 SDNode *Extract = *UI;
13064 // cOMpute the element's address.
13065 SDValue Idx = Extract->getOperand(1);
13067 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
13068 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
13069 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
13071 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
13072 StackPtr, OffsetVal);
13074 // Load the scalar.
13075 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
13076 ScalarAddr, MachinePointerInfo(),
13077 false, false, false, 0);
13079 // Replace the exact with the load.
13080 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
13083 // The replacement was made in place; don't return anything.
13087 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
13089 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
13090 TargetLowering::DAGCombinerInfo &DCI,
13091 const X86Subtarget *Subtarget) {
13092 DebugLoc DL = N->getDebugLoc();
13093 SDValue Cond = N->getOperand(0);
13094 // Get the LHS/RHS of the select.
13095 SDValue LHS = N->getOperand(1);
13096 SDValue RHS = N->getOperand(2);
13097 EVT VT = LHS.getValueType();
13099 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
13100 // instructions match the semantics of the common C idiom x<y?x:y but not
13101 // x<=y?x:y, because of how they handle negative zero (which can be
13102 // ignored in unsafe-math mode).
13103 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
13104 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
13105 (Subtarget->hasSSE2() ||
13106 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
13107 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13109 unsigned Opcode = 0;
13110 // Check for x CC y ? x : y.
13111 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13112 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13116 // Converting this to a min would handle NaNs incorrectly, and swapping
13117 // the operands would cause it to handle comparisons between positive
13118 // and negative zero incorrectly.
13119 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13120 if (!DAG.getTarget().Options.UnsafeFPMath &&
13121 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13123 std::swap(LHS, RHS);
13125 Opcode = X86ISD::FMIN;
13128 // Converting this to a min would handle comparisons between positive
13129 // and negative zero incorrectly.
13130 if (!DAG.getTarget().Options.UnsafeFPMath &&
13131 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13133 Opcode = X86ISD::FMIN;
13136 // Converting this to a min would handle both negative zeros and NaNs
13137 // incorrectly, but we can swap the operands to fix both.
13138 std::swap(LHS, RHS);
13142 Opcode = X86ISD::FMIN;
13146 // Converting this to a max would handle comparisons between positive
13147 // and negative zero incorrectly.
13148 if (!DAG.getTarget().Options.UnsafeFPMath &&
13149 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
13151 Opcode = X86ISD::FMAX;
13154 // Converting this to a max would handle NaNs incorrectly, and swapping
13155 // the operands would cause it to handle comparisons between positive
13156 // and negative zero incorrectly.
13157 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
13158 if (!DAG.getTarget().Options.UnsafeFPMath &&
13159 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
13161 std::swap(LHS, RHS);
13163 Opcode = X86ISD::FMAX;
13166 // Converting this to a max would handle both negative zeros and NaNs
13167 // incorrectly, but we can swap the operands to fix both.
13168 std::swap(LHS, RHS);
13172 Opcode = X86ISD::FMAX;
13175 // Check for x CC y ? y : x -- a min/max with reversed arms.
13176 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
13177 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
13181 // Converting this to a min would handle comparisons between positive
13182 // and negative zero incorrectly, and swapping the operands would
13183 // cause it to handle NaNs incorrectly.
13184 if (!DAG.getTarget().Options.UnsafeFPMath &&
13185 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
13186 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13188 std::swap(LHS, RHS);
13190 Opcode = X86ISD::FMIN;
13193 // Converting this to a min would handle NaNs incorrectly.
13194 if (!DAG.getTarget().Options.UnsafeFPMath &&
13195 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
13197 Opcode = X86ISD::FMIN;
13200 // Converting this to a min would handle both negative zeros and NaNs
13201 // incorrectly, but we can swap the operands to fix both.
13202 std::swap(LHS, RHS);
13206 Opcode = X86ISD::FMIN;
13210 // Converting this to a max would handle NaNs incorrectly.
13211 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13213 Opcode = X86ISD::FMAX;
13216 // Converting this to a max would handle comparisons between positive
13217 // and negative zero incorrectly, and swapping the operands would
13218 // cause it to handle NaNs incorrectly.
13219 if (!DAG.getTarget().Options.UnsafeFPMath &&
13220 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
13221 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
13223 std::swap(LHS, RHS);
13225 Opcode = X86ISD::FMAX;
13228 // Converting this to a max would handle both negative zeros and NaNs
13229 // incorrectly, but we can swap the operands to fix both.
13230 std::swap(LHS, RHS);
13234 Opcode = X86ISD::FMAX;
13240 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
13243 // If this is a select between two integer constants, try to do some
13245 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
13246 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
13247 // Don't do this for crazy integer types.
13248 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
13249 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
13250 // so that TrueC (the true value) is larger than FalseC.
13251 bool NeedsCondInvert = false;
13253 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
13254 // Efficiently invertible.
13255 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
13256 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
13257 isa<ConstantSDNode>(Cond.getOperand(1))))) {
13258 NeedsCondInvert = true;
13259 std::swap(TrueC, FalseC);
13262 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
13263 if (FalseC->getAPIntValue() == 0 &&
13264 TrueC->getAPIntValue().isPowerOf2()) {
13265 if (NeedsCondInvert) // Invert the condition if needed.
13266 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13267 DAG.getConstant(1, Cond.getValueType()));
13269 // Zero extend the condition if needed.
13270 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
13272 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13273 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
13274 DAG.getConstant(ShAmt, MVT::i8));
13277 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
13278 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13279 if (NeedsCondInvert) // Invert the condition if needed.
13280 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13281 DAG.getConstant(1, Cond.getValueType()));
13283 // Zero extend the condition if needed.
13284 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13285 FalseC->getValueType(0), Cond);
13286 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13287 SDValue(FalseC, 0));
13290 // Optimize cases that will turn into an LEA instruction. This requires
13291 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13292 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13293 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13294 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13296 bool isFastMultiplier = false;
13298 switch ((unsigned char)Diff) {
13300 case 1: // result = add base, cond
13301 case 2: // result = lea base( , cond*2)
13302 case 3: // result = lea base(cond, cond*2)
13303 case 4: // result = lea base( , cond*4)
13304 case 5: // result = lea base(cond, cond*4)
13305 case 8: // result = lea base( , cond*8)
13306 case 9: // result = lea base(cond, cond*8)
13307 isFastMultiplier = true;
13312 if (isFastMultiplier) {
13313 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13314 if (NeedsCondInvert) // Invert the condition if needed.
13315 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
13316 DAG.getConstant(1, Cond.getValueType()));
13318 // Zero extend the condition if needed.
13319 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13321 // Scale the condition by the difference.
13323 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13324 DAG.getConstant(Diff, Cond.getValueType()));
13326 // Add the base if non-zero.
13327 if (FalseC->getAPIntValue() != 0)
13328 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13329 SDValue(FalseC, 0));
13336 // Canonicalize max and min:
13337 // (x > y) ? x : y -> (x >= y) ? x : y
13338 // (x < y) ? x : y -> (x <= y) ? x : y
13339 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
13340 // the need for an extra compare
13341 // against zero. e.g.
13342 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
13344 // testl %edi, %edi
13346 // cmovgl %edi, %eax
13350 // cmovsl %eax, %edi
13351 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
13352 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
13353 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
13354 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
13359 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
13360 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
13361 Cond.getOperand(0), Cond.getOperand(1), NewCC);
13362 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
13367 // If we know that this node is legal then we know that it is going to be
13368 // matched by one of the SSE/AVX BLEND instructions. These instructions only
13369 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
13370 // to simplify previous instructions.
13371 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13372 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
13373 !DCI.isBeforeLegalize() &&
13374 TLI.isOperationLegal(ISD::VSELECT, VT)) {
13375 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
13376 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
13377 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
13379 APInt KnownZero, KnownOne;
13380 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
13381 DCI.isBeforeLegalizeOps());
13382 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
13383 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
13384 DCI.CommitTargetLoweringOpt(TLO);
13390 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
13391 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
13392 TargetLowering::DAGCombinerInfo &DCI) {
13393 DebugLoc DL = N->getDebugLoc();
13395 // If the flag operand isn't dead, don't touch this CMOV.
13396 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
13399 SDValue FalseOp = N->getOperand(0);
13400 SDValue TrueOp = N->getOperand(1);
13401 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
13402 SDValue Cond = N->getOperand(3);
13403 if (CC == X86::COND_E || CC == X86::COND_NE) {
13404 switch (Cond.getOpcode()) {
13408 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
13409 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
13410 return (CC == X86::COND_E) ? FalseOp : TrueOp;
13414 // If this is a select between two integer constants, try to do some
13415 // optimizations. Note that the operands are ordered the opposite of SELECT
13417 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
13418 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
13419 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
13420 // larger than FalseC (the false value).
13421 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
13422 CC = X86::GetOppositeBranchCondition(CC);
13423 std::swap(TrueC, FalseC);
13426 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
13427 // This is efficient for any integer data type (including i8/i16) and
13429 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
13430 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13431 DAG.getConstant(CC, MVT::i8), Cond);
13433 // Zero extend the condition if needed.
13434 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
13436 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
13437 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
13438 DAG.getConstant(ShAmt, MVT::i8));
13439 if (N->getNumValues() == 2) // Dead flag value?
13440 return DCI.CombineTo(N, Cond, SDValue());
13444 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
13445 // for any integer data type, including i8/i16.
13446 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
13447 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13448 DAG.getConstant(CC, MVT::i8), Cond);
13450 // Zero extend the condition if needed.
13451 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
13452 FalseC->getValueType(0), Cond);
13453 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13454 SDValue(FalseC, 0));
13456 if (N->getNumValues() == 2) // Dead flag value?
13457 return DCI.CombineTo(N, Cond, SDValue());
13461 // Optimize cases that will turn into an LEA instruction. This requires
13462 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
13463 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
13464 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
13465 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
13467 bool isFastMultiplier = false;
13469 switch ((unsigned char)Diff) {
13471 case 1: // result = add base, cond
13472 case 2: // result = lea base( , cond*2)
13473 case 3: // result = lea base(cond, cond*2)
13474 case 4: // result = lea base( , cond*4)
13475 case 5: // result = lea base(cond, cond*4)
13476 case 8: // result = lea base( , cond*8)
13477 case 9: // result = lea base(cond, cond*8)
13478 isFastMultiplier = true;
13483 if (isFastMultiplier) {
13484 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
13485 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
13486 DAG.getConstant(CC, MVT::i8), Cond);
13487 // Zero extend the condition if needed.
13488 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
13490 // Scale the condition by the difference.
13492 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
13493 DAG.getConstant(Diff, Cond.getValueType()));
13495 // Add the base if non-zero.
13496 if (FalseC->getAPIntValue() != 0)
13497 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
13498 SDValue(FalseC, 0));
13499 if (N->getNumValues() == 2) // Dead flag value?
13500 return DCI.CombineTo(N, Cond, SDValue());
13510 /// PerformMulCombine - Optimize a single multiply with constant into two
13511 /// in order to implement it with two cheaper instructions, e.g.
13512 /// LEA + SHL, LEA + LEA.
13513 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
13514 TargetLowering::DAGCombinerInfo &DCI) {
13515 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
13518 EVT VT = N->getValueType(0);
13519 if (VT != MVT::i64)
13522 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
13525 uint64_t MulAmt = C->getZExtValue();
13526 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
13529 uint64_t MulAmt1 = 0;
13530 uint64_t MulAmt2 = 0;
13531 if ((MulAmt % 9) == 0) {
13533 MulAmt2 = MulAmt / 9;
13534 } else if ((MulAmt % 5) == 0) {
13536 MulAmt2 = MulAmt / 5;
13537 } else if ((MulAmt % 3) == 0) {
13539 MulAmt2 = MulAmt / 3;
13542 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
13543 DebugLoc DL = N->getDebugLoc();
13545 if (isPowerOf2_64(MulAmt2) &&
13546 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
13547 // If second multiplifer is pow2, issue it first. We want the multiply by
13548 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
13550 std::swap(MulAmt1, MulAmt2);
13553 if (isPowerOf2_64(MulAmt1))
13554 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
13555 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
13557 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
13558 DAG.getConstant(MulAmt1, VT));
13560 if (isPowerOf2_64(MulAmt2))
13561 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
13562 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
13564 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
13565 DAG.getConstant(MulAmt2, VT));
13567 // Do not add new nodes to DAG combiner worklist.
13568 DCI.CombineTo(N, NewMul, false);
13573 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
13574 SDValue N0 = N->getOperand(0);
13575 SDValue N1 = N->getOperand(1);
13576 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
13577 EVT VT = N0.getValueType();
13579 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
13580 // since the result of setcc_c is all zero's or all ones.
13581 if (VT.isInteger() && !VT.isVector() &&
13582 N1C && N0.getOpcode() == ISD::AND &&
13583 N0.getOperand(1).getOpcode() == ISD::Constant) {
13584 SDValue N00 = N0.getOperand(0);
13585 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
13586 ((N00.getOpcode() == ISD::ANY_EXTEND ||
13587 N00.getOpcode() == ISD::ZERO_EXTEND) &&
13588 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
13589 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
13590 APInt ShAmt = N1C->getAPIntValue();
13591 Mask = Mask.shl(ShAmt);
13593 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
13594 N00, DAG.getConstant(Mask, VT));
13599 // Hardware support for vector shifts is sparse which makes us scalarize the
13600 // vector operations in many cases. Also, on sandybridge ADD is faster than
13602 // (shl V, 1) -> add V,V
13603 if (isSplatVector(N1.getNode())) {
13604 assert(N0.getValueType().isVector() && "Invalid vector shift type");
13605 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
13606 // We shift all of the values by one. In many cases we do not have
13607 // hardware support for this operation. This is better expressed as an ADD
13609 if (N1C && (1 == N1C->getZExtValue())) {
13610 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
13617 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
13619 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13620 TargetLowering::DAGCombinerInfo &DCI,
13621 const X86Subtarget *Subtarget) {
13622 EVT VT = N->getValueType(0);
13623 if (N->getOpcode() == ISD::SHL) {
13624 SDValue V = PerformSHLCombine(N, DAG);
13625 if (V.getNode()) return V;
13628 // On X86 with SSE2 support, we can transform this to a vector shift if
13629 // all elements are shifted by the same amount. We can't do this in legalize
13630 // because the a constant vector is typically transformed to a constant pool
13631 // so we have no knowledge of the shift amount.
13632 if (!Subtarget->hasSSE2())
13635 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
13636 (!Subtarget->hasAVX2() ||
13637 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
13640 SDValue ShAmtOp = N->getOperand(1);
13641 EVT EltVT = VT.getVectorElementType();
13642 DebugLoc DL = N->getDebugLoc();
13643 SDValue BaseShAmt = SDValue();
13644 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13645 unsigned NumElts = VT.getVectorNumElements();
13647 for (; i != NumElts; ++i) {
13648 SDValue Arg = ShAmtOp.getOperand(i);
13649 if (Arg.getOpcode() == ISD::UNDEF) continue;
13653 // Handle the case where the build_vector is all undef
13654 // FIXME: Should DAG allow this?
13658 for (; i != NumElts; ++i) {
13659 SDValue Arg = ShAmtOp.getOperand(i);
13660 if (Arg.getOpcode() == ISD::UNDEF) continue;
13661 if (Arg != BaseShAmt) {
13665 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13666 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13667 SDValue InVec = ShAmtOp.getOperand(0);
13668 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13669 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13671 for (; i != NumElts; ++i) {
13672 SDValue Arg = InVec.getOperand(i);
13673 if (Arg.getOpcode() == ISD::UNDEF) continue;
13677 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13678 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13679 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13680 if (C->getZExtValue() == SplatIdx)
13681 BaseShAmt = InVec.getOperand(1);
13684 if (BaseShAmt.getNode() == 0) {
13685 // Don't create instructions with illegal types after legalize
13687 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13688 !DCI.isBeforeLegalize())
13691 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13692 DAG.getIntPtrConstant(0));
13697 // The shift amount is an i32.
13698 if (EltVT.bitsGT(MVT::i32))
13699 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13700 else if (EltVT.bitsLT(MVT::i32))
13701 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13703 // The shift amount is identical so we can do a vector shift.
13704 SDValue ValOp = N->getOperand(0);
13705 switch (N->getOpcode()) {
13707 llvm_unreachable("Unknown shift opcode!");
13709 switch (VT.getSimpleVT().SimpleTy) {
13710 default: return SDValue();
13717 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
13720 switch (VT.getSimpleVT().SimpleTy) {
13721 default: return SDValue();
13726 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
13729 switch (VT.getSimpleVT().SimpleTy) {
13730 default: return SDValue();
13737 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
13743 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13744 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13745 // and friends. Likewise for OR -> CMPNEQSS.
13746 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13747 TargetLowering::DAGCombinerInfo &DCI,
13748 const X86Subtarget *Subtarget) {
13751 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13752 // we're requiring SSE2 for both.
13753 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13754 SDValue N0 = N->getOperand(0);
13755 SDValue N1 = N->getOperand(1);
13756 SDValue CMP0 = N0->getOperand(1);
13757 SDValue CMP1 = N1->getOperand(1);
13758 DebugLoc DL = N->getDebugLoc();
13760 // The SETCCs should both refer to the same CMP.
13761 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13764 SDValue CMP00 = CMP0->getOperand(0);
13765 SDValue CMP01 = CMP0->getOperand(1);
13766 EVT VT = CMP00.getValueType();
13768 if (VT == MVT::f32 || VT == MVT::f64) {
13769 bool ExpectingFlags = false;
13770 // Check for any users that want flags:
13771 for (SDNode::use_iterator UI = N->use_begin(),
13773 !ExpectingFlags && UI != UE; ++UI)
13774 switch (UI->getOpcode()) {
13779 ExpectingFlags = true;
13781 case ISD::CopyToReg:
13782 case ISD::SIGN_EXTEND:
13783 case ISD::ZERO_EXTEND:
13784 case ISD::ANY_EXTEND:
13788 if (!ExpectingFlags) {
13789 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13790 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13792 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13793 X86::CondCode tmp = cc0;
13798 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13799 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13800 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13801 X86ISD::NodeType NTOperator = is64BitFP ?
13802 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13803 // FIXME: need symbolic constants for these magic numbers.
13804 // See X86ATTInstPrinter.cpp:printSSECC().
13805 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13806 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13807 DAG.getConstant(x86cc, MVT::i8));
13808 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13810 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13811 DAG.getConstant(1, MVT::i32));
13812 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13813 return OneBitOfTruth;
13821 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13822 /// so it can be folded inside ANDNP.
13823 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13824 EVT VT = N->getValueType(0);
13826 // Match direct AllOnes for 128 and 256-bit vectors
13827 if (ISD::isBuildVectorAllOnes(N))
13830 // Look through a bit convert.
13831 if (N->getOpcode() == ISD::BITCAST)
13832 N = N->getOperand(0).getNode();
13834 // Sometimes the operand may come from a insert_subvector building a 256-bit
13836 if (VT.getSizeInBits() == 256 &&
13837 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13838 SDValue V1 = N->getOperand(0);
13839 SDValue V2 = N->getOperand(1);
13841 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13842 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13843 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13844 ISD::isBuildVectorAllOnes(V2.getNode()))
13851 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13852 TargetLowering::DAGCombinerInfo &DCI,
13853 const X86Subtarget *Subtarget) {
13854 if (DCI.isBeforeLegalizeOps())
13857 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13861 EVT VT = N->getValueType(0);
13863 // Create ANDN, BLSI, and BLSR instructions
13864 // BLSI is X & (-X)
13865 // BLSR is X & (X-1)
13866 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
13867 SDValue N0 = N->getOperand(0);
13868 SDValue N1 = N->getOperand(1);
13869 DebugLoc DL = N->getDebugLoc();
13871 // Check LHS for not
13872 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1)))
13873 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1);
13874 // Check RHS for not
13875 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1)))
13876 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0);
13878 // Check LHS for neg
13879 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
13880 isZero(N0.getOperand(0)))
13881 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
13883 // Check RHS for neg
13884 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
13885 isZero(N1.getOperand(0)))
13886 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
13888 // Check LHS for X-1
13889 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
13890 isAllOnes(N0.getOperand(1)))
13891 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
13893 // Check RHS for X-1
13894 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
13895 isAllOnes(N1.getOperand(1)))
13896 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
13901 // Want to form ANDNP nodes:
13902 // 1) In the hopes of then easily combining them with OR and AND nodes
13903 // to form PBLEND/PSIGN.
13904 // 2) To match ANDN packed intrinsics
13905 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13908 SDValue N0 = N->getOperand(0);
13909 SDValue N1 = N->getOperand(1);
13910 DebugLoc DL = N->getDebugLoc();
13912 // Check LHS for vnot
13913 if (N0.getOpcode() == ISD::XOR &&
13914 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13915 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13916 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13918 // Check RHS for vnot
13919 if (N1.getOpcode() == ISD::XOR &&
13920 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13921 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13922 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13927 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13928 TargetLowering::DAGCombinerInfo &DCI,
13929 const X86Subtarget *Subtarget) {
13930 if (DCI.isBeforeLegalizeOps())
13933 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13937 EVT VT = N->getValueType(0);
13939 SDValue N0 = N->getOperand(0);
13940 SDValue N1 = N->getOperand(1);
13942 // look for psign/blend
13943 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
13944 if (!Subtarget->hasSSSE3() ||
13945 (VT == MVT::v4i64 && !Subtarget->hasAVX2()))
13948 // Canonicalize pandn to RHS
13949 if (N0.getOpcode() == X86ISD::ANDNP)
13951 // or (and (m, y), (pandn m, x))
13952 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13953 SDValue Mask = N1.getOperand(0);
13954 SDValue X = N1.getOperand(1);
13956 if (N0.getOperand(0) == Mask)
13957 Y = N0.getOperand(1);
13958 if (N0.getOperand(1) == Mask)
13959 Y = N0.getOperand(0);
13961 // Check to see if the mask appeared in both the AND and ANDNP and
13965 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13966 if (Mask.getOpcode() != ISD::BITCAST ||
13967 X.getOpcode() != ISD::BITCAST ||
13968 Y.getOpcode() != ISD::BITCAST)
13971 // Look through mask bitcast.
13972 Mask = Mask.getOperand(0);
13973 EVT MaskVT = Mask.getValueType();
13975 // Validate that the Mask operand is a vector sra node.
13976 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13977 // there is no psrai.b
13978 if (Mask.getOpcode() != X86ISD::VSRAI)
13981 // Check that the SRA is all signbits.
13982 SDValue SraC = Mask.getOperand(1);
13983 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13984 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13985 if ((SraAmt + 1) != EltBits)
13988 DebugLoc DL = N->getDebugLoc();
13990 // Now we know we at least have a plendvb with the mask val. See if
13991 // we can form a psignb/w/d.
13992 // psign = x.type == y.type == mask.type && y = sub(0, x);
13993 X = X.getOperand(0);
13994 Y = Y.getOperand(0);
13995 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13996 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13997 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
13998 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
13999 "Unsupported VT for PSIGN");
14000 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
14001 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14003 // PBLENDVB only available on SSE 4.1
14004 if (!Subtarget->hasSSE41())
14007 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
14009 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
14010 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
14011 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
14012 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
14013 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
14017 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
14020 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
14021 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
14023 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
14025 if (!N0.hasOneUse() || !N1.hasOneUse())
14028 SDValue ShAmt0 = N0.getOperand(1);
14029 if (ShAmt0.getValueType() != MVT::i8)
14031 SDValue ShAmt1 = N1.getOperand(1);
14032 if (ShAmt1.getValueType() != MVT::i8)
14034 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
14035 ShAmt0 = ShAmt0.getOperand(0);
14036 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
14037 ShAmt1 = ShAmt1.getOperand(0);
14039 DebugLoc DL = N->getDebugLoc();
14040 unsigned Opc = X86ISD::SHLD;
14041 SDValue Op0 = N0.getOperand(0);
14042 SDValue Op1 = N1.getOperand(0);
14043 if (ShAmt0.getOpcode() == ISD::SUB) {
14044 Opc = X86ISD::SHRD;
14045 std::swap(Op0, Op1);
14046 std::swap(ShAmt0, ShAmt1);
14049 unsigned Bits = VT.getSizeInBits();
14050 if (ShAmt1.getOpcode() == ISD::SUB) {
14051 SDValue Sum = ShAmt1.getOperand(0);
14052 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
14053 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
14054 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
14055 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
14056 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
14057 return DAG.getNode(Opc, DL, VT,
14059 DAG.getNode(ISD::TRUNCATE, DL,
14062 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
14063 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
14065 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
14066 return DAG.getNode(Opc, DL, VT,
14067 N0.getOperand(0), N1.getOperand(0),
14068 DAG.getNode(ISD::TRUNCATE, DL,
14075 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
14076 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
14077 TargetLowering::DAGCombinerInfo &DCI,
14078 const X86Subtarget *Subtarget) {
14079 if (DCI.isBeforeLegalizeOps())
14082 EVT VT = N->getValueType(0);
14084 if (VT != MVT::i32 && VT != MVT::i64)
14087 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
14089 // Create BLSMSK instructions by finding X ^ (X-1)
14090 SDValue N0 = N->getOperand(0);
14091 SDValue N1 = N->getOperand(1);
14092 DebugLoc DL = N->getDebugLoc();
14094 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
14095 isAllOnes(N0.getOperand(1)))
14096 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
14098 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
14099 isAllOnes(N1.getOperand(1)))
14100 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
14105 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
14106 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
14107 const X86Subtarget *Subtarget) {
14108 LoadSDNode *Ld = cast<LoadSDNode>(N);
14109 EVT RegVT = Ld->getValueType(0);
14110 EVT MemVT = Ld->getMemoryVT();
14111 DebugLoc dl = Ld->getDebugLoc();
14112 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14114 ISD::LoadExtType Ext = Ld->getExtensionType();
14116 // If this is a vector EXT Load then attempt to optimize it using a
14117 // shuffle. We need SSE4 for the shuffles.
14118 // TODO: It is possible to support ZExt by zeroing the undef values
14119 // during the shuffle phase or after the shuffle.
14120 if (RegVT.isVector() && RegVT.isInteger() &&
14121 Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) {
14122 assert(MemVT != RegVT && "Cannot extend to the same type");
14123 assert(MemVT.isVector() && "Must load a vector from memory");
14125 unsigned NumElems = RegVT.getVectorNumElements();
14126 unsigned RegSz = RegVT.getSizeInBits();
14127 unsigned MemSz = MemVT.getSizeInBits();
14128 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14129 // All sizes must be a power of two
14130 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
14132 // Attempt to load the original value using a single load op.
14133 // Find a scalar type which is equal to the loaded word size.
14134 MVT SclrLoadTy = MVT::i8;
14135 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14136 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14137 MVT Tp = (MVT::SimpleValueType)tp;
14138 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) {
14144 // Proceed if a load word is found.
14145 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue();
14147 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
14148 RegSz/SclrLoadTy.getSizeInBits());
14150 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14151 RegSz/MemVT.getScalarType().getSizeInBits());
14152 // Can't shuffle using an illegal type.
14153 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14155 // Perform a single load.
14156 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
14158 Ld->getPointerInfo(), Ld->isVolatile(),
14159 Ld->isNonTemporal(), Ld->isInvariant(),
14160 Ld->getAlignment());
14162 // Insert the word loaded into a vector.
14163 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
14164 LoadUnitVecVT, ScalarLoad);
14166 // Bitcast the loaded value to a vector of the original element type, in
14167 // the size of the target vector type.
14168 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT,
14170 unsigned SizeRatio = RegSz/MemSz;
14172 // Redistribute the loaded elements into the different locations.
14173 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14174 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i;
14176 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14177 DAG.getUNDEF(SlicedVec.getValueType()),
14178 ShuffleVec.data());
14180 // Bitcast to the requested type.
14181 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
14182 // Replace the original load with the new sequence
14183 // and return the new chain.
14184 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff);
14185 return SDValue(ScalarLoad.getNode(), 1);
14191 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
14192 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
14193 const X86Subtarget *Subtarget) {
14194 StoreSDNode *St = cast<StoreSDNode>(N);
14195 EVT VT = St->getValue().getValueType();
14196 EVT StVT = St->getMemoryVT();
14197 DebugLoc dl = St->getDebugLoc();
14198 SDValue StoredVal = St->getOperand(1);
14199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14201 // If we are saving a concatenation of two XMM registers, perform two stores.
14202 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
14203 // 128-bit ones. If in the future the cost becomes only one memory access the
14204 // first version would be better.
14205 if (VT.getSizeInBits() == 256 &&
14206 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
14207 StoredVal.getNumOperands() == 2) {
14209 SDValue Value0 = StoredVal.getOperand(0);
14210 SDValue Value1 = StoredVal.getOperand(1);
14212 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
14213 SDValue Ptr0 = St->getBasePtr();
14214 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
14216 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
14217 St->getPointerInfo(), St->isVolatile(),
14218 St->isNonTemporal(), St->getAlignment());
14219 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
14220 St->getPointerInfo(), St->isVolatile(),
14221 St->isNonTemporal(), St->getAlignment());
14222 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
14225 // Optimize trunc store (of multiple scalars) to shuffle and store.
14226 // First, pack all of the elements in one place. Next, store to memory
14227 // in fewer chunks.
14228 if (St->isTruncatingStore() && VT.isVector()) {
14229 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14230 unsigned NumElems = VT.getVectorNumElements();
14231 assert(StVT != VT && "Cannot truncate to the same type");
14232 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
14233 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
14235 // From, To sizes and ElemCount must be pow of two
14236 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
14237 // We are going to use the original vector elt for storing.
14238 // Accumulated smaller vector elements must be a multiple of the store size.
14239 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
14241 unsigned SizeRatio = FromSz / ToSz;
14243 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
14245 // Create a type on which we perform the shuffle
14246 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
14247 StVT.getScalarType(), NumElems*SizeRatio);
14249 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
14251 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
14252 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
14253 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
14255 // Can't shuffle using an illegal type
14256 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
14258 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
14259 DAG.getUNDEF(WideVec.getValueType()),
14260 ShuffleVec.data());
14261 // At this point all of the data is stored at the bottom of the
14262 // register. We now need to save it to mem.
14264 // Find the largest store unit
14265 MVT StoreType = MVT::i8;
14266 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
14267 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
14268 MVT Tp = (MVT::SimpleValueType)tp;
14269 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
14273 // Bitcast the original vector into a vector of store-size units
14274 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
14275 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
14276 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
14277 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
14278 SmallVector<SDValue, 8> Chains;
14279 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
14280 TLI.getPointerTy());
14281 SDValue Ptr = St->getBasePtr();
14283 // Perform one or more big stores into memory.
14284 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
14285 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
14286 StoreType, ShuffWide,
14287 DAG.getIntPtrConstant(i));
14288 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
14289 St->getPointerInfo(), St->isVolatile(),
14290 St->isNonTemporal(), St->getAlignment());
14291 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14292 Chains.push_back(Ch);
14295 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
14300 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
14301 // the FP state in cases where an emms may be missing.
14302 // A preferable solution to the general problem is to figure out the right
14303 // places to insert EMMS. This qualifies as a quick hack.
14305 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
14306 if (VT.getSizeInBits() != 64)
14309 const Function *F = DAG.getMachineFunction().getFunction();
14310 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
14311 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
14312 && Subtarget->hasSSE2();
14313 if ((VT.isVector() ||
14314 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
14315 isa<LoadSDNode>(St->getValue()) &&
14316 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
14317 St->getChain().hasOneUse() && !St->isVolatile()) {
14318 SDNode* LdVal = St->getValue().getNode();
14319 LoadSDNode *Ld = 0;
14320 int TokenFactorIndex = -1;
14321 SmallVector<SDValue, 8> Ops;
14322 SDNode* ChainVal = St->getChain().getNode();
14323 // Must be a store of a load. We currently handle two cases: the load
14324 // is a direct child, and it's under an intervening TokenFactor. It is
14325 // possible to dig deeper under nested TokenFactors.
14326 if (ChainVal == LdVal)
14327 Ld = cast<LoadSDNode>(St->getChain());
14328 else if (St->getValue().hasOneUse() &&
14329 ChainVal->getOpcode() == ISD::TokenFactor) {
14330 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
14331 if (ChainVal->getOperand(i).getNode() == LdVal) {
14332 TokenFactorIndex = i;
14333 Ld = cast<LoadSDNode>(St->getValue());
14335 Ops.push_back(ChainVal->getOperand(i));
14339 if (!Ld || !ISD::isNormalLoad(Ld))
14342 // If this is not the MMX case, i.e. we are just turning i64 load/store
14343 // into f64 load/store, avoid the transformation if there are multiple
14344 // uses of the loaded value.
14345 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
14348 DebugLoc LdDL = Ld->getDebugLoc();
14349 DebugLoc StDL = N->getDebugLoc();
14350 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
14351 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
14353 if (Subtarget->is64Bit() || F64IsLegal) {
14354 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
14355 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
14356 Ld->getPointerInfo(), Ld->isVolatile(),
14357 Ld->isNonTemporal(), Ld->isInvariant(),
14358 Ld->getAlignment());
14359 SDValue NewChain = NewLd.getValue(1);
14360 if (TokenFactorIndex != -1) {
14361 Ops.push_back(NewChain);
14362 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14365 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
14366 St->getPointerInfo(),
14367 St->isVolatile(), St->isNonTemporal(),
14368 St->getAlignment());
14371 // Otherwise, lower to two pairs of 32-bit loads / stores.
14372 SDValue LoAddr = Ld->getBasePtr();
14373 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
14374 DAG.getConstant(4, MVT::i32));
14376 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
14377 Ld->getPointerInfo(),
14378 Ld->isVolatile(), Ld->isNonTemporal(),
14379 Ld->isInvariant(), Ld->getAlignment());
14380 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
14381 Ld->getPointerInfo().getWithOffset(4),
14382 Ld->isVolatile(), Ld->isNonTemporal(),
14384 MinAlign(Ld->getAlignment(), 4));
14386 SDValue NewChain = LoLd.getValue(1);
14387 if (TokenFactorIndex != -1) {
14388 Ops.push_back(LoLd);
14389 Ops.push_back(HiLd);
14390 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
14394 LoAddr = St->getBasePtr();
14395 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
14396 DAG.getConstant(4, MVT::i32));
14398 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
14399 St->getPointerInfo(),
14400 St->isVolatile(), St->isNonTemporal(),
14401 St->getAlignment());
14402 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
14403 St->getPointerInfo().getWithOffset(4),
14405 St->isNonTemporal(),
14406 MinAlign(St->getAlignment(), 4));
14407 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
14412 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
14413 /// and return the operands for the horizontal operation in LHS and RHS. A
14414 /// horizontal operation performs the binary operation on successive elements
14415 /// of its first operand, then on successive elements of its second operand,
14416 /// returning the resulting values in a vector. For example, if
14417 /// A = < float a0, float a1, float a2, float a3 >
14419 /// B = < float b0, float b1, float b2, float b3 >
14420 /// then the result of doing a horizontal operation on A and B is
14421 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
14422 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
14423 /// A horizontal-op B, for some already available A and B, and if so then LHS is
14424 /// set to A, RHS to B, and the routine returns 'true'.
14425 /// Note that the binary operation should have the property that if one of the
14426 /// operands is UNDEF then the result is UNDEF.
14427 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
14428 // Look for the following pattern: if
14429 // A = < float a0, float a1, float a2, float a3 >
14430 // B = < float b0, float b1, float b2, float b3 >
14432 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
14433 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
14434 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
14435 // which is A horizontal-op B.
14437 // At least one of the operands should be a vector shuffle.
14438 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
14439 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
14442 EVT VT = LHS.getValueType();
14444 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14445 "Unsupported vector type for horizontal add/sub");
14447 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
14448 // operate independently on 128-bit lanes.
14449 unsigned NumElts = VT.getVectorNumElements();
14450 unsigned NumLanes = VT.getSizeInBits()/128;
14451 unsigned NumLaneElts = NumElts / NumLanes;
14452 assert((NumLaneElts % 2 == 0) &&
14453 "Vector type should have an even number of elements in each lane");
14454 unsigned HalfLaneElts = NumLaneElts/2;
14456 // View LHS in the form
14457 // LHS = VECTOR_SHUFFLE A, B, LMask
14458 // If LHS is not a shuffle then pretend it is the shuffle
14459 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
14460 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
14463 SmallVector<int, 16> LMask(NumElts);
14464 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14465 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
14466 A = LHS.getOperand(0);
14467 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
14468 B = LHS.getOperand(1);
14469 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
14470 std::copy(Mask.begin(), Mask.end(), LMask.begin());
14472 if (LHS.getOpcode() != ISD::UNDEF)
14474 for (unsigned i = 0; i != NumElts; ++i)
14478 // Likewise, view RHS in the form
14479 // RHS = VECTOR_SHUFFLE C, D, RMask
14481 SmallVector<int, 16> RMask(NumElts);
14482 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
14483 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
14484 C = RHS.getOperand(0);
14485 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
14486 D = RHS.getOperand(1);
14487 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
14488 std::copy(Mask.begin(), Mask.end(), RMask.begin());
14490 if (RHS.getOpcode() != ISD::UNDEF)
14492 for (unsigned i = 0; i != NumElts; ++i)
14496 // Check that the shuffles are both shuffling the same vectors.
14497 if (!(A == C && B == D) && !(A == D && B == C))
14500 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
14501 if (!A.getNode() && !B.getNode())
14504 // If A and B occur in reverse order in RHS, then "swap" them (which means
14505 // rewriting the mask).
14507 CommuteVectorShuffleMask(RMask, NumElts);
14509 // At this point LHS and RHS are equivalent to
14510 // LHS = VECTOR_SHUFFLE A, B, LMask
14511 // RHS = VECTOR_SHUFFLE A, B, RMask
14512 // Check that the masks correspond to performing a horizontal operation.
14513 for (unsigned i = 0; i != NumElts; ++i) {
14514 int LIdx = LMask[i], RIdx = RMask[i];
14516 // Ignore any UNDEF components.
14517 if (LIdx < 0 || RIdx < 0 ||
14518 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
14519 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
14522 // Check that successive elements are being operated on. If not, this is
14523 // not a horizontal operation.
14524 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
14525 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
14526 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
14527 if (!(LIdx == Index && RIdx == Index + 1) &&
14528 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
14532 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
14533 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
14537 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
14538 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
14539 const X86Subtarget *Subtarget) {
14540 EVT VT = N->getValueType(0);
14541 SDValue LHS = N->getOperand(0);
14542 SDValue RHS = N->getOperand(1);
14544 // Try to synthesize horizontal adds from adds of shuffles.
14545 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14546 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14547 isHorizontalBinOp(LHS, RHS, true))
14548 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
14552 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
14553 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
14554 const X86Subtarget *Subtarget) {
14555 EVT VT = N->getValueType(0);
14556 SDValue LHS = N->getOperand(0);
14557 SDValue RHS = N->getOperand(1);
14559 // Try to synthesize horizontal subs from subs of shuffles.
14560 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
14561 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
14562 isHorizontalBinOp(LHS, RHS, false))
14563 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
14567 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
14568 /// X86ISD::FXOR nodes.
14569 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
14570 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
14571 // F[X]OR(0.0, x) -> x
14572 // F[X]OR(x, 0.0) -> x
14573 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14574 if (C->getValueAPF().isPosZero())
14575 return N->getOperand(1);
14576 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14577 if (C->getValueAPF().isPosZero())
14578 return N->getOperand(0);
14582 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
14583 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
14584 // FAND(0.0, x) -> 0.0
14585 // FAND(x, 0.0) -> 0.0
14586 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
14587 if (C->getValueAPF().isPosZero())
14588 return N->getOperand(0);
14589 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
14590 if (C->getValueAPF().isPosZero())
14591 return N->getOperand(1);
14595 static SDValue PerformBTCombine(SDNode *N,
14597 TargetLowering::DAGCombinerInfo &DCI) {
14598 // BT ignores high bits in the bit index operand.
14599 SDValue Op1 = N->getOperand(1);
14600 if (Op1.hasOneUse()) {
14601 unsigned BitWidth = Op1.getValueSizeInBits();
14602 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
14603 APInt KnownZero, KnownOne;
14604 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
14605 !DCI.isBeforeLegalizeOps());
14606 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14607 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
14608 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
14609 DCI.CommitTargetLoweringOpt(TLO);
14614 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
14615 SDValue Op = N->getOperand(0);
14616 if (Op.getOpcode() == ISD::BITCAST)
14617 Op = Op.getOperand(0);
14618 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
14619 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
14620 VT.getVectorElementType().getSizeInBits() ==
14621 OpVT.getVectorElementType().getSizeInBits()) {
14622 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
14627 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
14628 TargetLowering::DAGCombinerInfo &DCI,
14629 const X86Subtarget *Subtarget) {
14630 if (!DCI.isBeforeLegalizeOps())
14633 if (!Subtarget->hasAVX())
14636 // Optimize vectors in AVX mode
14637 // Sign extend v8i16 to v8i32 and
14640 // Divide input vector into two parts
14641 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14642 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14643 // concat the vectors to original VT
14645 EVT VT = N->getValueType(0);
14646 SDValue Op = N->getOperand(0);
14647 EVT OpVT = Op.getValueType();
14648 DebugLoc dl = N->getDebugLoc();
14650 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14651 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
14653 unsigned NumElems = OpVT.getVectorNumElements();
14654 SmallVector<int,8> ShufMask1(NumElems, -1);
14655 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
14657 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14660 SmallVector<int,8> ShufMask2(NumElems, -1);
14661 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
14663 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14666 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14667 VT.getVectorNumElements()/2);
14669 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
14670 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
14672 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14677 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
14678 const X86Subtarget *Subtarget) {
14679 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
14680 // (and (i32 x86isd::setcc_carry), 1)
14681 // This eliminates the zext. This transformation is necessary because
14682 // ISD::SETCC is always legalized to i8.
14683 DebugLoc dl = N->getDebugLoc();
14684 SDValue N0 = N->getOperand(0);
14685 EVT VT = N->getValueType(0);
14686 EVT OpVT = N0.getValueType();
14688 if (N0.getOpcode() == ISD::AND &&
14690 N0.getOperand(0).hasOneUse()) {
14691 SDValue N00 = N0.getOperand(0);
14692 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
14694 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
14695 if (!C || C->getZExtValue() != 1)
14697 return DAG.getNode(ISD::AND, dl, VT,
14698 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
14699 N00.getOperand(0), N00.getOperand(1)),
14700 DAG.getConstant(1, VT));
14702 // Optimize vectors in AVX mode:
14705 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14706 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14707 // Concat upper and lower parts.
14710 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14711 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14712 // Concat upper and lower parts.
14714 if (Subtarget->hasAVX()) {
14716 if (((VT == MVT::v8i32) && (OpVT == MVT::v8i16)) ||
14717 ((VT == MVT::v4i64) && (OpVT == MVT::v4i32))) {
14719 SDValue ZeroVec = getZeroVector(OpVT, Subtarget, DAG, dl);
14720 SDValue OpLo = getTargetShuffleNode(X86ISD::UNPCKL, dl, OpVT, N0, ZeroVec, DAG);
14721 SDValue OpHi = getTargetShuffleNode(X86ISD::UNPCKH, dl, OpVT, N0, ZeroVec, DAG);
14723 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
14724 VT.getVectorNumElements()/2);
14726 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14727 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14729 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14737 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
14738 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
14739 unsigned X86CC = N->getConstantOperandVal(0);
14740 SDValue EFLAG = N->getOperand(1);
14741 DebugLoc DL = N->getDebugLoc();
14743 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
14744 // a zext and produces an all-ones bit which is more useful than 0/1 in some
14746 if (X86CC == X86::COND_B)
14747 return DAG.getNode(ISD::AND, DL, MVT::i8,
14748 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
14749 DAG.getConstant(X86CC, MVT::i8), EFLAG),
14750 DAG.getConstant(1, MVT::i8));
14755 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
14756 const X86TargetLowering *XTLI) {
14757 SDValue Op0 = N->getOperand(0);
14758 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
14759 // a 32-bit target where SSE doesn't support i64->FP operations.
14760 if (Op0.getOpcode() == ISD::LOAD) {
14761 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
14762 EVT VT = Ld->getValueType(0);
14763 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
14764 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
14765 !XTLI->getSubtarget()->is64Bit() &&
14766 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
14767 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
14768 Ld->getChain(), Op0, DAG);
14769 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
14776 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
14777 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
14778 X86TargetLowering::DAGCombinerInfo &DCI) {
14779 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
14780 // the result is either zero or one (depending on the input carry bit).
14781 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
14782 if (X86::isZeroNode(N->getOperand(0)) &&
14783 X86::isZeroNode(N->getOperand(1)) &&
14784 // We don't have a good way to replace an EFLAGS use, so only do this when
14786 SDValue(N, 1).use_empty()) {
14787 DebugLoc DL = N->getDebugLoc();
14788 EVT VT = N->getValueType(0);
14789 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
14790 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
14791 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
14792 DAG.getConstant(X86::COND_B,MVT::i8),
14794 DAG.getConstant(1, VT));
14795 return DCI.CombineTo(N, Res1, CarryOut);
14801 // fold (add Y, (sete X, 0)) -> adc 0, Y
14802 // (add Y, (setne X, 0)) -> sbb -1, Y
14803 // (sub (sete X, 0), Y) -> sbb 0, Y
14804 // (sub (setne X, 0), Y) -> adc -1, Y
14805 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
14806 DebugLoc DL = N->getDebugLoc();
14808 // Look through ZExts.
14809 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
14810 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
14813 SDValue SetCC = Ext.getOperand(0);
14814 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
14817 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
14818 if (CC != X86::COND_E && CC != X86::COND_NE)
14821 SDValue Cmp = SetCC.getOperand(1);
14822 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
14823 !X86::isZeroNode(Cmp.getOperand(1)) ||
14824 !Cmp.getOperand(0).getValueType().isInteger())
14827 SDValue CmpOp0 = Cmp.getOperand(0);
14828 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
14829 DAG.getConstant(1, CmpOp0.getValueType()));
14831 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
14832 if (CC == X86::COND_NE)
14833 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
14834 DL, OtherVal.getValueType(), OtherVal,
14835 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
14836 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
14837 DL, OtherVal.getValueType(), OtherVal,
14838 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
14841 /// PerformADDCombine - Do target-specific dag combines on integer adds.
14842 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
14843 const X86Subtarget *Subtarget) {
14844 EVT VT = N->getValueType(0);
14845 SDValue Op0 = N->getOperand(0);
14846 SDValue Op1 = N->getOperand(1);
14848 // Try to synthesize horizontal adds from adds of shuffles.
14849 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14850 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14851 isHorizontalBinOp(Op0, Op1, true))
14852 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
14854 return OptimizeConditionalInDecrement(N, DAG);
14857 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
14858 const X86Subtarget *Subtarget) {
14859 SDValue Op0 = N->getOperand(0);
14860 SDValue Op1 = N->getOperand(1);
14862 // X86 can't encode an immediate LHS of a sub. See if we can push the
14863 // negation into a preceding instruction.
14864 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
14865 // If the RHS of the sub is a XOR with one use and a constant, invert the
14866 // immediate. Then add one to the LHS of the sub so we can turn
14867 // X-Y -> X+~Y+1, saving one register.
14868 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
14869 isa<ConstantSDNode>(Op1.getOperand(1))) {
14870 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
14871 EVT VT = Op0.getValueType();
14872 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
14874 DAG.getConstant(~XorC, VT));
14875 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
14876 DAG.getConstant(C->getAPIntValue()+1, VT));
14880 // Try to synthesize horizontal adds from adds of shuffles.
14881 EVT VT = N->getValueType(0);
14882 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
14883 (Subtarget->hasAVX2() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
14884 isHorizontalBinOp(Op0, Op1, true))
14885 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
14887 return OptimizeConditionalInDecrement(N, DAG);
14890 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
14891 DAGCombinerInfo &DCI) const {
14892 SelectionDAG &DAG = DCI.DAG;
14893 switch (N->getOpcode()) {
14895 case ISD::EXTRACT_VECTOR_ELT:
14896 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
14898 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
14899 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
14900 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
14901 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
14902 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
14903 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
14906 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
14907 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
14908 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
14909 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
14910 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
14911 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
14912 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
14913 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
14914 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
14916 case X86ISD::FOR: return PerformFORCombine(N, DAG);
14917 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
14918 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
14919 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
14920 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, Subtarget);
14921 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
14922 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG, DCI);
14923 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
14924 case X86ISD::SHUFP: // Handle all target specific shuffles
14925 case X86ISD::PALIGN:
14926 case X86ISD::UNPCKH:
14927 case X86ISD::UNPCKL:
14928 case X86ISD::MOVHLPS:
14929 case X86ISD::MOVLHPS:
14930 case X86ISD::PSHUFD:
14931 case X86ISD::PSHUFHW:
14932 case X86ISD::PSHUFLW:
14933 case X86ISD::MOVSS:
14934 case X86ISD::MOVSD:
14935 case X86ISD::VPERMILP:
14936 case X86ISD::VPERM2X128:
14937 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
14943 /// isTypeDesirableForOp - Return true if the target has native support for
14944 /// the specified value type and it is 'desirable' to use the type for the
14945 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
14946 /// instruction encodings are longer and some i16 instructions are slow.
14947 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
14948 if (!isTypeLegal(VT))
14950 if (VT != MVT::i16)
14957 case ISD::SIGN_EXTEND:
14958 case ISD::ZERO_EXTEND:
14959 case ISD::ANY_EXTEND:
14972 /// IsDesirableToPromoteOp - This method query the target whether it is
14973 /// beneficial for dag combiner to promote the specified node. If true, it
14974 /// should return the desired promotion type by reference.
14975 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
14976 EVT VT = Op.getValueType();
14977 if (VT != MVT::i16)
14980 bool Promote = false;
14981 bool Commute = false;
14982 switch (Op.getOpcode()) {
14985 LoadSDNode *LD = cast<LoadSDNode>(Op);
14986 // If the non-extending load has a single use and it's not live out, then it
14987 // might be folded.
14988 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
14989 Op.hasOneUse()*/) {
14990 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14991 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
14992 // The only case where we'd want to promote LOAD (rather then it being
14993 // promoted as an operand is when it's only use is liveout.
14994 if (UI->getOpcode() != ISD::CopyToReg)
15001 case ISD::SIGN_EXTEND:
15002 case ISD::ZERO_EXTEND:
15003 case ISD::ANY_EXTEND:
15008 SDValue N0 = Op.getOperand(0);
15009 // Look out for (store (shl (load), x)).
15010 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
15023 SDValue N0 = Op.getOperand(0);
15024 SDValue N1 = Op.getOperand(1);
15025 if (!Commute && MayFoldLoad(N1))
15027 // Avoid disabling potential load folding opportunities.
15028 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
15030 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
15040 //===----------------------------------------------------------------------===//
15041 // X86 Inline Assembly Support
15042 //===----------------------------------------------------------------------===//
15045 // Helper to match a string separated by whitespace.
15046 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
15047 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
15049 for (unsigned i = 0, e = args.size(); i != e; ++i) {
15050 StringRef piece(*args[i]);
15051 if (!s.startswith(piece)) // Check if the piece matches.
15054 s = s.substr(piece.size());
15055 StringRef::size_type pos = s.find_first_not_of(" \t");
15056 if (pos == 0) // We matched a prefix.
15064 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
15067 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
15068 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
15070 std::string AsmStr = IA->getAsmString();
15072 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
15073 if (!Ty || Ty->getBitWidth() % 16 != 0)
15076 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
15077 SmallVector<StringRef, 4> AsmPieces;
15078 SplitString(AsmStr, AsmPieces, ";\n");
15080 switch (AsmPieces.size()) {
15081 default: return false;
15083 // FIXME: this should verify that we are targeting a 486 or better. If not,
15084 // we will turn this bswap into something that will be lowered to logical
15085 // ops instead of emitting the bswap asm. For now, we don't support 486 or
15086 // lower so don't worry about this.
15088 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
15089 matchAsm(AsmPieces[0], "bswapl", "$0") ||
15090 matchAsm(AsmPieces[0], "bswapq", "$0") ||
15091 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
15092 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
15093 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
15094 // No need to check constraints, nothing other than the equivalent of
15095 // "=r,0" would be valid here.
15096 return IntrinsicLowering::LowerToByteSwap(CI);
15099 // rorw $$8, ${0:w} --> llvm.bswap.i16
15100 if (CI->getType()->isIntegerTy(16) &&
15101 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15102 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
15103 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
15105 const std::string &ConstraintsStr = IA->getConstraintString();
15106 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15107 std::sort(AsmPieces.begin(), AsmPieces.end());
15108 if (AsmPieces.size() == 4 &&
15109 AsmPieces[0] == "~{cc}" &&
15110 AsmPieces[1] == "~{dirflag}" &&
15111 AsmPieces[2] == "~{flags}" &&
15112 AsmPieces[3] == "~{fpsr}")
15113 return IntrinsicLowering::LowerToByteSwap(CI);
15117 if (CI->getType()->isIntegerTy(32) &&
15118 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
15119 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
15120 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
15121 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
15123 const std::string &ConstraintsStr = IA->getConstraintString();
15124 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
15125 std::sort(AsmPieces.begin(), AsmPieces.end());
15126 if (AsmPieces.size() == 4 &&
15127 AsmPieces[0] == "~{cc}" &&
15128 AsmPieces[1] == "~{dirflag}" &&
15129 AsmPieces[2] == "~{flags}" &&
15130 AsmPieces[3] == "~{fpsr}")
15131 return IntrinsicLowering::LowerToByteSwap(CI);
15134 if (CI->getType()->isIntegerTy(64)) {
15135 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
15136 if (Constraints.size() >= 2 &&
15137 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
15138 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
15139 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
15140 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
15141 matchAsm(AsmPieces[1], "bswap", "%edx") &&
15142 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
15143 return IntrinsicLowering::LowerToByteSwap(CI);
15153 /// getConstraintType - Given a constraint letter, return the type of
15154 /// constraint it is for this target.
15155 X86TargetLowering::ConstraintType
15156 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
15157 if (Constraint.size() == 1) {
15158 switch (Constraint[0]) {
15169 return C_RegisterClass;
15193 return TargetLowering::getConstraintType(Constraint);
15196 /// Examine constraint type and operand type and determine a weight value.
15197 /// This object must already have been set up with the operand type
15198 /// and the current alternative constraint selected.
15199 TargetLowering::ConstraintWeight
15200 X86TargetLowering::getSingleConstraintMatchWeight(
15201 AsmOperandInfo &info, const char *constraint) const {
15202 ConstraintWeight weight = CW_Invalid;
15203 Value *CallOperandVal = info.CallOperandVal;
15204 // If we don't have a value, we can't do a match,
15205 // but allow it at the lowest weight.
15206 if (CallOperandVal == NULL)
15208 Type *type = CallOperandVal->getType();
15209 // Look at the constraint type.
15210 switch (*constraint) {
15212 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
15223 if (CallOperandVal->getType()->isIntegerTy())
15224 weight = CW_SpecificReg;
15229 if (type->isFloatingPointTy())
15230 weight = CW_SpecificReg;
15233 if (type->isX86_MMXTy() && Subtarget->hasMMX())
15234 weight = CW_SpecificReg;
15238 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
15239 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasAVX()))
15240 weight = CW_Register;
15243 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
15244 if (C->getZExtValue() <= 31)
15245 weight = CW_Constant;
15249 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15250 if (C->getZExtValue() <= 63)
15251 weight = CW_Constant;
15255 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15256 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
15257 weight = CW_Constant;
15261 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15262 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
15263 weight = CW_Constant;
15267 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15268 if (C->getZExtValue() <= 3)
15269 weight = CW_Constant;
15273 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15274 if (C->getZExtValue() <= 0xff)
15275 weight = CW_Constant;
15280 if (dyn_cast<ConstantFP>(CallOperandVal)) {
15281 weight = CW_Constant;
15285 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15286 if ((C->getSExtValue() >= -0x80000000LL) &&
15287 (C->getSExtValue() <= 0x7fffffffLL))
15288 weight = CW_Constant;
15292 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
15293 if (C->getZExtValue() <= 0xffffffff)
15294 weight = CW_Constant;
15301 /// LowerXConstraint - try to replace an X constraint, which matches anything,
15302 /// with another that has more specific requirements based on the type of the
15303 /// corresponding operand.
15304 const char *X86TargetLowering::
15305 LowerXConstraint(EVT ConstraintVT) const {
15306 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
15307 // 'f' like normal targets.
15308 if (ConstraintVT.isFloatingPoint()) {
15309 if (Subtarget->hasSSE2())
15311 if (Subtarget->hasSSE1())
15315 return TargetLowering::LowerXConstraint(ConstraintVT);
15318 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
15319 /// vector. If it is invalid, don't add anything to Ops.
15320 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
15321 std::string &Constraint,
15322 std::vector<SDValue>&Ops,
15323 SelectionDAG &DAG) const {
15324 SDValue Result(0, 0);
15326 // Only support length 1 constraints for now.
15327 if (Constraint.length() > 1) return;
15329 char ConstraintLetter = Constraint[0];
15330 switch (ConstraintLetter) {
15333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15334 if (C->getZExtValue() <= 31) {
15335 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15341 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15342 if (C->getZExtValue() <= 63) {
15343 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15349 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15350 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
15351 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15357 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15358 if (C->getZExtValue() <= 255) {
15359 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15365 // 32-bit signed value
15366 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15367 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15368 C->getSExtValue())) {
15369 // Widen to 64 bits here to get it sign extended.
15370 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
15373 // FIXME gcc accepts some relocatable values here too, but only in certain
15374 // memory models; it's complicated.
15379 // 32-bit unsigned value
15380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
15381 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
15382 C->getZExtValue())) {
15383 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
15387 // FIXME gcc accepts some relocatable values here too, but only in certain
15388 // memory models; it's complicated.
15392 // Literal immediates are always ok.
15393 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
15394 // Widen to 64 bits here to get it sign extended.
15395 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
15399 // In any sort of PIC mode addresses need to be computed at runtime by
15400 // adding in a register or some sort of table lookup. These can't
15401 // be used as immediates.
15402 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
15405 // If we are in non-pic codegen mode, we allow the address of a global (with
15406 // an optional displacement) to be used with 'i'.
15407 GlobalAddressSDNode *GA = 0;
15408 int64_t Offset = 0;
15410 // Match either (GA), (GA+C), (GA+C1+C2), etc.
15412 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
15413 Offset += GA->getOffset();
15415 } else if (Op.getOpcode() == ISD::ADD) {
15416 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15417 Offset += C->getZExtValue();
15418 Op = Op.getOperand(0);
15421 } else if (Op.getOpcode() == ISD::SUB) {
15422 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
15423 Offset += -C->getZExtValue();
15424 Op = Op.getOperand(0);
15429 // Otherwise, this isn't something we can handle, reject it.
15433 const GlobalValue *GV = GA->getGlobal();
15434 // If we require an extra load to get this address, as in PIC mode, we
15435 // can't accept it.
15436 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
15437 getTargetMachine())))
15440 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
15441 GA->getValueType(0), Offset);
15446 if (Result.getNode()) {
15447 Ops.push_back(Result);
15450 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
15453 std::pair<unsigned, const TargetRegisterClass*>
15454 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
15456 // First, see if this is a constraint that directly corresponds to an LLVM
15458 if (Constraint.size() == 1) {
15459 // GCC Constraint Letters
15460 switch (Constraint[0]) {
15462 // TODO: Slight differences here in allocation order and leaving
15463 // RIP in the class. Do they matter any more here than they do
15464 // in the normal allocation?
15465 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
15466 if (Subtarget->is64Bit()) {
15467 if (VT == MVT::i32 || VT == MVT::f32)
15468 return std::make_pair(0U, X86::GR32RegisterClass);
15469 else if (VT == MVT::i16)
15470 return std::make_pair(0U, X86::GR16RegisterClass);
15471 else if (VT == MVT::i8 || VT == MVT::i1)
15472 return std::make_pair(0U, X86::GR8RegisterClass);
15473 else if (VT == MVT::i64 || VT == MVT::f64)
15474 return std::make_pair(0U, X86::GR64RegisterClass);
15477 // 32-bit fallthrough
15478 case 'Q': // Q_REGS
15479 if (VT == MVT::i32 || VT == MVT::f32)
15480 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
15481 else if (VT == MVT::i16)
15482 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
15483 else if (VT == MVT::i8 || VT == MVT::i1)
15484 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
15485 else if (VT == MVT::i64)
15486 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
15488 case 'r': // GENERAL_REGS
15489 case 'l': // INDEX_REGS
15490 if (VT == MVT::i8 || VT == MVT::i1)
15491 return std::make_pair(0U, X86::GR8RegisterClass);
15492 if (VT == MVT::i16)
15493 return std::make_pair(0U, X86::GR16RegisterClass);
15494 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
15495 return std::make_pair(0U, X86::GR32RegisterClass);
15496 return std::make_pair(0U, X86::GR64RegisterClass);
15497 case 'R': // LEGACY_REGS
15498 if (VT == MVT::i8 || VT == MVT::i1)
15499 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
15500 if (VT == MVT::i16)
15501 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
15502 if (VT == MVT::i32 || !Subtarget->is64Bit())
15503 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
15504 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
15505 case 'f': // FP Stack registers.
15506 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
15507 // value to the correct fpstack register class.
15508 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
15509 return std::make_pair(0U, X86::RFP32RegisterClass);
15510 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
15511 return std::make_pair(0U, X86::RFP64RegisterClass);
15512 return std::make_pair(0U, X86::RFP80RegisterClass);
15513 case 'y': // MMX_REGS if MMX allowed.
15514 if (!Subtarget->hasMMX()) break;
15515 return std::make_pair(0U, X86::VR64RegisterClass);
15516 case 'Y': // SSE_REGS if SSE2 allowed
15517 if (!Subtarget->hasSSE2()) break;
15519 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
15520 if (!Subtarget->hasSSE1()) break;
15522 switch (VT.getSimpleVT().SimpleTy) {
15524 // Scalar SSE types.
15527 return std::make_pair(0U, X86::FR32RegisterClass);
15530 return std::make_pair(0U, X86::FR64RegisterClass);
15538 return std::make_pair(0U, X86::VR128RegisterClass);
15546 return std::make_pair(0U, X86::VR256RegisterClass);
15553 // Use the default implementation in TargetLowering to convert the register
15554 // constraint into a member of a register class.
15555 std::pair<unsigned, const TargetRegisterClass*> Res;
15556 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
15558 // Not found as a standard register?
15559 if (Res.second == 0) {
15560 // Map st(0) -> st(7) -> ST0
15561 if (Constraint.size() == 7 && Constraint[0] == '{' &&
15562 tolower(Constraint[1]) == 's' &&
15563 tolower(Constraint[2]) == 't' &&
15564 Constraint[3] == '(' &&
15565 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
15566 Constraint[5] == ')' &&
15567 Constraint[6] == '}') {
15569 Res.first = X86::ST0+Constraint[4]-'0';
15570 Res.second = X86::RFP80RegisterClass;
15574 // GCC allows "st(0)" to be called just plain "st".
15575 if (StringRef("{st}").equals_lower(Constraint)) {
15576 Res.first = X86::ST0;
15577 Res.second = X86::RFP80RegisterClass;
15582 if (StringRef("{flags}").equals_lower(Constraint)) {
15583 Res.first = X86::EFLAGS;
15584 Res.second = X86::CCRRegisterClass;
15588 // 'A' means EAX + EDX.
15589 if (Constraint == "A") {
15590 Res.first = X86::EAX;
15591 Res.second = X86::GR32_ADRegisterClass;
15597 // Otherwise, check to see if this is a register class of the wrong value
15598 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
15599 // turn into {ax},{dx}.
15600 if (Res.second->hasType(VT))
15601 return Res; // Correct type already, nothing to do.
15603 // All of the single-register GCC register classes map their values onto
15604 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
15605 // really want an 8-bit or 32-bit register, map to the appropriate register
15606 // class and return the appropriate register.
15607 if (Res.second == X86::GR16RegisterClass) {
15608 if (VT == MVT::i8) {
15609 unsigned DestReg = 0;
15610 switch (Res.first) {
15612 case X86::AX: DestReg = X86::AL; break;
15613 case X86::DX: DestReg = X86::DL; break;
15614 case X86::CX: DestReg = X86::CL; break;
15615 case X86::BX: DestReg = X86::BL; break;
15618 Res.first = DestReg;
15619 Res.second = X86::GR8RegisterClass;
15621 } else if (VT == MVT::i32) {
15622 unsigned DestReg = 0;
15623 switch (Res.first) {
15625 case X86::AX: DestReg = X86::EAX; break;
15626 case X86::DX: DestReg = X86::EDX; break;
15627 case X86::CX: DestReg = X86::ECX; break;
15628 case X86::BX: DestReg = X86::EBX; break;
15629 case X86::SI: DestReg = X86::ESI; break;
15630 case X86::DI: DestReg = X86::EDI; break;
15631 case X86::BP: DestReg = X86::EBP; break;
15632 case X86::SP: DestReg = X86::ESP; break;
15635 Res.first = DestReg;
15636 Res.second = X86::GR32RegisterClass;
15638 } else if (VT == MVT::i64) {
15639 unsigned DestReg = 0;
15640 switch (Res.first) {
15642 case X86::AX: DestReg = X86::RAX; break;
15643 case X86::DX: DestReg = X86::RDX; break;
15644 case X86::CX: DestReg = X86::RCX; break;
15645 case X86::BX: DestReg = X86::RBX; break;
15646 case X86::SI: DestReg = X86::RSI; break;
15647 case X86::DI: DestReg = X86::RDI; break;
15648 case X86::BP: DestReg = X86::RBP; break;
15649 case X86::SP: DestReg = X86::RSP; break;
15652 Res.first = DestReg;
15653 Res.second = X86::GR64RegisterClass;
15656 } else if (Res.second == X86::FR32RegisterClass ||
15657 Res.second == X86::FR64RegisterClass ||
15658 Res.second == X86::VR128RegisterClass) {
15659 // Handle references to XMM physical registers that got mapped into the
15660 // wrong class. This can happen with constraints like {xmm0} where the
15661 // target independent register mapper will just pick the first match it can
15662 // find, ignoring the required type.
15663 if (VT == MVT::f32)
15664 Res.second = X86::FR32RegisterClass;
15665 else if (VT == MVT::f64)
15666 Res.second = X86::FR64RegisterClass;
15667 else if (X86::VR128RegisterClass->hasType(VT))
15668 Res.second = X86::VR128RegisterClass;