1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/VectorExtras.h"
27 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/StringExtras.h"
37 #include "llvm/ParameterAttributes.h"
40 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
41 : TargetLowering(TM) {
42 Subtarget = &TM.getSubtarget<X86Subtarget>();
43 X86ScalarSSE = Subtarget->hasSSE2();
44 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
46 RegInfo = TM.getRegisterInfo();
48 // Set up the TargetLowering object.
50 // X86 is weird, it always uses i8 for shift amounts and setcc results.
51 setShiftAmountType(MVT::i8);
52 setSetCCResultType(MVT::i8);
53 setSetCCResultContents(ZeroOrOneSetCCResult);
54 setSchedulingPreference(SchedulingForRegPressure);
55 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
56 setStackPointerRegisterToSaveRestore(X86StackPtr);
58 if (Subtarget->isTargetDarwin()) {
59 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
60 setUseUnderscoreSetJmp(false);
61 setUseUnderscoreLongJmp(false);
62 } else if (Subtarget->isTargetMingw()) {
63 // MS runtime is weird: it exports _setjmp, but longjmp!
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(false);
67 setUseUnderscoreSetJmp(true);
68 setUseUnderscoreLongJmp(true);
71 // Set up the register classes.
72 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
73 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
74 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
75 if (Subtarget->is64Bit())
76 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
78 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
80 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
82 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
83 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
84 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
86 if (Subtarget->is64Bit()) {
87 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
88 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
91 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
92 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
94 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
97 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
99 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
101 // SSE has no i16 to fp conversion, only i32
103 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
105 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
106 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
109 if (!Subtarget->is64Bit()) {
110 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
111 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
112 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
115 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
117 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
118 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
123 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
124 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
127 // Handle FP_TO_UINT by promoting the destination to a larger signed
129 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
130 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
131 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
133 if (Subtarget->is64Bit()) {
134 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
135 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
137 if (X86ScalarSSE && !Subtarget->hasSSE3())
138 // Expand FP_TO_UINT into a select.
139 // FIXME: We would like to use a Custom expander here eventually to do
140 // the optimal thing for SSE vs. the default expansion in the legalizer.
141 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
143 // With SSE3 we can use fisttpll to convert to a signed i64.
144 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
147 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
149 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
150 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
153 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
154 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
155 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
156 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
157 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
158 if (Subtarget->is64Bit())
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
163 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
164 setOperationAction(ISD::FREM , MVT::f64 , Expand);
166 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
167 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
168 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
169 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
170 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
171 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
172 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
173 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
174 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
175 if (Subtarget->is64Bit()) {
176 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
177 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
178 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
181 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
182 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
184 // These should be promoted to a larger select which is supported.
185 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
186 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
187 // X86 wants to expand cmov itself.
188 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
189 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
190 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
191 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
192 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
193 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
194 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
195 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
196 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
197 if (Subtarget->is64Bit()) {
198 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
199 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
201 // X86 ret instruction may pop stack.
202 setOperationAction(ISD::RET , MVT::Other, Custom);
203 if (!Subtarget->is64Bit())
204 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
207 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
208 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
209 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
210 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
211 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
212 if (Subtarget->is64Bit()) {
213 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
214 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
215 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
216 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
218 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
219 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
220 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
221 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
222 // X86 wants to expand memset / memcpy itself.
223 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
224 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
226 // We don't have line number support yet.
227 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
228 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
229 // FIXME - use subtarget debug flags
230 if (!Subtarget->isTargetDarwin() &&
231 !Subtarget->isTargetELF() &&
232 !Subtarget->isTargetCygMing())
233 setOperationAction(ISD::LABEL, MVT::Other, Expand);
235 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
236 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
237 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
238 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
239 if (Subtarget->is64Bit()) {
241 setExceptionPointerRegister(X86::RAX);
242 setExceptionSelectorRegister(X86::RDX);
244 setExceptionPointerRegister(X86::EAX);
245 setExceptionSelectorRegister(X86::EDX);
247 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
249 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Expand);
250 setOperationAction(ISD::ADJUST_TRAMP, MVT::i64, Expand);
251 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
253 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
254 setOperationAction(ISD::VASTART , MVT::Other, Custom);
255 setOperationAction(ISD::VAARG , MVT::Other, Expand);
256 setOperationAction(ISD::VAEND , MVT::Other, Expand);
257 if (Subtarget->is64Bit())
258 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
260 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
262 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
263 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
264 if (Subtarget->is64Bit())
265 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
266 if (Subtarget->isTargetCygMing())
267 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
269 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
272 // Set up the FP register classes.
273 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
274 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
276 // Use ANDPD to simulate FABS.
277 setOperationAction(ISD::FABS , MVT::f64, Custom);
278 setOperationAction(ISD::FABS , MVT::f32, Custom);
280 // Use XORP to simulate FNEG.
281 setOperationAction(ISD::FNEG , MVT::f64, Custom);
282 setOperationAction(ISD::FNEG , MVT::f32, Custom);
284 // Use ANDPD and ORPD to simulate FCOPYSIGN.
285 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
286 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
288 // We don't support sin/cos/fmod
289 setOperationAction(ISD::FSIN , MVT::f64, Expand);
290 setOperationAction(ISD::FCOS , MVT::f64, Expand);
291 setOperationAction(ISD::FREM , MVT::f64, Expand);
292 setOperationAction(ISD::FSIN , MVT::f32, Expand);
293 setOperationAction(ISD::FCOS , MVT::f32, Expand);
294 setOperationAction(ISD::FREM , MVT::f32, Expand);
296 // Expand FP immediates into loads from the stack, except for the special
298 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
299 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
300 addLegalFPImmediate(APFloat(+0.0)); // xorps / xorpd
302 // Conversions to long double (in X87) go through memory.
303 setConvertAction(MVT::f32, MVT::f80, Expand);
304 setConvertAction(MVT::f64, MVT::f80, Expand);
306 // Conversions from long double (in X87) go through memory.
307 setConvertAction(MVT::f80, MVT::f32, Expand);
308 setConvertAction(MVT::f80, MVT::f64, Expand);
310 // Set up the FP register classes.
311 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
312 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
314 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
315 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
316 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
317 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
319 // Floating truncations need to go through memory.
320 setConvertAction(MVT::f80, MVT::f32, Expand);
321 setConvertAction(MVT::f64, MVT::f32, Expand);
322 setConvertAction(MVT::f80, MVT::f64, Expand);
325 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
326 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
329 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
330 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
331 addLegalFPImmediate(APFloat(+0.0)); // FLD0
332 addLegalFPImmediate(APFloat(+1.0)); // FLD1
333 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
334 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
337 // Long double always uses X87.
338 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
340 // First set operation action for all vector types to expand. Then we
341 // will selectively turn on ones that can be effectively codegen'd.
342 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
343 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
344 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
345 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
346 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
347 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
348 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
349 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
350 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
351 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
352 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
353 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
354 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
355 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
356 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
357 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
358 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
359 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
360 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
361 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
362 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
363 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
364 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
365 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
366 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
369 if (Subtarget->hasMMX()) {
370 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
371 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
372 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
373 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
375 // FIXME: add MMX packed arithmetics
377 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
378 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
379 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
380 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
382 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
383 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
384 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
386 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
387 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
389 setOperationAction(ISD::AND, MVT::v8i8, Promote);
390 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
391 setOperationAction(ISD::AND, MVT::v4i16, Promote);
392 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
393 setOperationAction(ISD::AND, MVT::v2i32, Promote);
394 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
395 setOperationAction(ISD::AND, MVT::v1i64, Legal);
397 setOperationAction(ISD::OR, MVT::v8i8, Promote);
398 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
399 setOperationAction(ISD::OR, MVT::v4i16, Promote);
400 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
401 setOperationAction(ISD::OR, MVT::v2i32, Promote);
402 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
403 setOperationAction(ISD::OR, MVT::v1i64, Legal);
405 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
406 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
407 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
408 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
409 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
410 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
411 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
413 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
414 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
415 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
416 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
417 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
418 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
419 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
421 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
422 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
423 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
424 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
426 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
427 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
428 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
429 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
431 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
432 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
433 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
434 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
437 if (Subtarget->hasSSE1()) {
438 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
440 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
441 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
442 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
443 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
444 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
445 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
446 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
447 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
448 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
449 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
450 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
453 if (Subtarget->hasSSE2()) {
454 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
455 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
456 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
457 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
458 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
460 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
461 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
462 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
463 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
464 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
465 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
466 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
467 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
468 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
469 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
470 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
471 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
472 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
473 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
474 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
477 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
478 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
479 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
480 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
481 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
483 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
484 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
485 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
486 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
487 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
489 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
490 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
491 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
492 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
493 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
494 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
496 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
497 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
498 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
499 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
500 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
501 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
502 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
503 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
504 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
505 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
506 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
507 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
510 // Custom lower v2i64 and v2f64 selects.
511 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
512 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
513 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
514 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
517 // We want to custom lower some of our intrinsics.
518 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
520 // We have target-specific dag combine patterns for the following nodes:
521 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
522 setTargetDAGCombine(ISD::SELECT);
524 computeRegisterProperties();
526 // FIXME: These should be based on subtarget info. Plus, the values should
527 // be smaller when we are in optimizing for size mode.
528 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
529 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
530 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
531 allowUnalignedMemoryAccesses = true; // x86 supports it!
535 //===----------------------------------------------------------------------===//
536 // Return Value Calling Convention Implementation
537 //===----------------------------------------------------------------------===//
539 #include "X86GenCallingConv.inc"
541 /// LowerRET - Lower an ISD::RET node.
542 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
543 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
545 SmallVector<CCValAssign, 16> RVLocs;
546 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
547 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
548 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
549 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
552 // If this is the first return lowered for this function, add the regs to the
553 // liveout set for the function.
554 if (DAG.getMachineFunction().liveout_empty()) {
555 for (unsigned i = 0; i != RVLocs.size(); ++i)
556 if (RVLocs[i].isRegLoc())
557 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
560 SDOperand Chain = Op.getOperand(0);
563 // Copy the result values into the output registers.
564 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
565 RVLocs[0].getLocReg() != X86::ST0) {
566 for (unsigned i = 0; i != RVLocs.size(); ++i) {
567 CCValAssign &VA = RVLocs[i];
568 assert(VA.isRegLoc() && "Can only return in registers!");
569 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
571 Flag = Chain.getValue(1);
574 // We need to handle a destination of ST0 specially, because it isn't really
576 SDOperand Value = Op.getOperand(1);
578 // If this is an FP return with ScalarSSE, we need to move the value from
579 // an XMM register onto the fp-stack.
583 // If this is a load into a scalarsse value, don't store the loaded value
584 // back to the stack, only to reload it: just replace the scalar-sse load.
585 if (ISD::isNON_EXTLoad(Value.Val) &&
586 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
587 Chain = Value.getOperand(0);
588 MemLoc = Value.getOperand(1);
590 // Spill the value to memory and reload it into top of stack.
591 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
592 MachineFunction &MF = DAG.getMachineFunction();
593 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
594 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
595 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
597 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other);
598 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
599 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
600 Chain = Value.getValue(1);
603 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
604 SDOperand Ops[] = { Chain, Value };
605 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
606 Flag = Chain.getValue(1);
609 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
611 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
613 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
617 /// LowerCallResult - Lower the result values of an ISD::CALL into the
618 /// appropriate copies out of appropriate physical registers. This assumes that
619 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
620 /// being lowered. The returns a SDNode with the same number of values as the
622 SDNode *X86TargetLowering::
623 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
624 unsigned CallingConv, SelectionDAG &DAG) {
626 // Assign locations to each value returned by this call.
627 SmallVector<CCValAssign, 16> RVLocs;
628 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
629 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
630 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
633 SmallVector<SDOperand, 8> ResultVals;
635 // Copy all of the result registers out of their specified physreg.
636 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
637 for (unsigned i = 0; i != RVLocs.size(); ++i) {
638 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
639 RVLocs[i].getValVT(), InFlag).getValue(1);
640 InFlag = Chain.getValue(2);
641 ResultVals.push_back(Chain.getValue(0));
644 // Copies from the FP stack are special, as ST0 isn't a valid register
645 // before the fp stackifier runs.
647 // Copy ST0 into an RFP register with FP_GET_RESULT.
648 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other, MVT::Flag);
649 SDOperand GROps[] = { Chain, InFlag };
650 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
651 Chain = RetVal.getValue(1);
652 InFlag = RetVal.getValue(2);
654 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
657 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
658 // shouldn't be necessary except that RFP cannot be live across
659 // multiple blocks. When stackifier is fixed, they can be uncoupled.
660 MachineFunction &MF = DAG.getMachineFunction();
661 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
662 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
664 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag
666 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
667 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0);
668 Chain = RetVal.getValue(1);
670 ResultVals.push_back(RetVal);
673 // Merge everything together with a MERGE_VALUES node.
674 ResultVals.push_back(Chain);
675 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
676 &ResultVals[0], ResultVals.size()).Val;
680 //===----------------------------------------------------------------------===//
681 // C & StdCall Calling Convention implementation
682 //===----------------------------------------------------------------------===//
683 // StdCall calling convention seems to be standard for many Windows' API
684 // routines and around. It differs from C calling convention just a little:
685 // callee should clean up the stack, not caller. Symbols should be also
686 // decorated in some fancy way :) It doesn't support any vector arguments.
688 /// AddLiveIn - This helper function adds the specified physical register to the
689 /// MachineFunction as a live in value. It also creates a corresponding virtual
691 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
692 const TargetRegisterClass *RC) {
693 assert(RC->contains(PReg) && "Not the correct regclass!");
694 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
695 MF.addLiveIn(PReg, VReg);
699 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
701 unsigned NumArgs = Op.Val->getNumValues() - 1;
702 MachineFunction &MF = DAG.getMachineFunction();
703 MachineFrameInfo *MFI = MF.getFrameInfo();
704 SDOperand Root = Op.getOperand(0);
705 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
707 // Assign locations to all of the incoming arguments.
708 SmallVector<CCValAssign, 16> ArgLocs;
709 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
710 getTargetMachine(), ArgLocs);
711 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
713 SmallVector<SDOperand, 8> ArgValues;
714 unsigned LastVal = ~0U;
715 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
716 CCValAssign &VA = ArgLocs[i];
717 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
719 assert(VA.getValNo() != LastVal &&
720 "Don't support value assigned to multiple locs yet");
721 LastVal = VA.getValNo();
724 MVT::ValueType RegVT = VA.getLocVT();
725 TargetRegisterClass *RC;
726 if (RegVT == MVT::i32)
727 RC = X86::GR32RegisterClass;
729 assert(MVT::isVector(RegVT));
730 RC = X86::VR128RegisterClass;
733 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
734 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
736 // If this is an 8 or 16-bit value, it is really passed promoted to 32
737 // bits. Insert an assert[sz]ext to capture this, then truncate to the
739 if (VA.getLocInfo() == CCValAssign::SExt)
740 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
741 DAG.getValueType(VA.getValVT()));
742 else if (VA.getLocInfo() == CCValAssign::ZExt)
743 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
744 DAG.getValueType(VA.getValVT()));
746 if (VA.getLocInfo() != CCValAssign::Full)
747 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
749 ArgValues.push_back(ArgValue);
751 assert(VA.isMemLoc());
753 // Create the nodes corresponding to a load from this parameter slot.
754 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
755 VA.getLocMemOffset());
756 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
757 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
761 unsigned StackSize = CCInfo.getNextStackOffset();
763 ArgValues.push_back(Root);
765 // If the function takes variable number of arguments, make a frame index for
766 // the start of the first vararg value... for expansion of llvm.va_start.
768 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
770 if (isStdCall && !isVarArg) {
771 BytesToPopOnReturn = StackSize; // Callee pops everything..
772 BytesCallerReserves = 0;
774 BytesToPopOnReturn = 0; // Callee pops nothing.
776 // If this is an sret function, the return should pop the hidden pointer.
778 (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
779 ISD::ParamFlags::StructReturn))
780 BytesToPopOnReturn = 4;
782 BytesCallerReserves = StackSize;
785 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
787 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
788 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
790 // Return the new list of results.
791 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
792 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
795 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
797 SDOperand Chain = Op.getOperand(0);
798 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
799 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
800 SDOperand Callee = Op.getOperand(4);
801 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
803 // Analyze operands of the call, assigning locations to each operand.
804 SmallVector<CCValAssign, 16> ArgLocs;
805 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
806 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
808 // Get a count of how many bytes are to be pushed on the stack.
809 unsigned NumBytes = CCInfo.getNextStackOffset();
811 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
813 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
814 SmallVector<SDOperand, 8> MemOpChains;
818 // Walk the register/memloc assignments, inserting copies/loads.
819 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
820 CCValAssign &VA = ArgLocs[i];
821 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
823 // Promote the value if needed.
824 switch (VA.getLocInfo()) {
825 default: assert(0 && "Unknown loc info!");
826 case CCValAssign::Full: break;
827 case CCValAssign::SExt:
828 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
830 case CCValAssign::ZExt:
831 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
833 case CCValAssign::AExt:
834 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
839 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
841 assert(VA.isMemLoc());
842 if (StackPtr.Val == 0)
843 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
844 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
845 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
846 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
850 // If the first argument is an sret pointer, remember it.
851 bool isSRet = NumOps &&
852 (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
853 ISD::ParamFlags::StructReturn);
855 if (!MemOpChains.empty())
856 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
857 &MemOpChains[0], MemOpChains.size());
859 // Build a sequence of copy-to-reg nodes chained together with token chain
860 // and flag operands which copy the outgoing args into registers.
862 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
863 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
865 InFlag = Chain.getValue(1);
868 // ELF / PIC requires GOT in the EBX register before function calls via PLT
870 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
871 Subtarget->isPICStyleGOT()) {
872 Chain = DAG.getCopyToReg(Chain, X86::EBX,
873 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
875 InFlag = Chain.getValue(1);
878 // If the callee is a GlobalAddress node (quite common, every direct call is)
879 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
880 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
881 // We should use extra load for direct calls to dllimported functions in
883 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
884 getTargetMachine(), true))
885 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
886 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
887 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
889 // Returns a chain & a flag for retval copy to use.
890 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
891 SmallVector<SDOperand, 8> Ops;
892 Ops.push_back(Chain);
893 Ops.push_back(Callee);
895 // Add argument registers to the end of the list so that they are known live
897 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
898 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
899 RegsToPass[i].second.getValueType()));
901 // Add an implicit use GOT pointer in EBX.
902 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
903 Subtarget->isPICStyleGOT())
904 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
907 Ops.push_back(InFlag);
909 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
910 NodeTys, &Ops[0], Ops.size());
911 InFlag = Chain.getValue(1);
913 // Create the CALLSEQ_END node.
914 unsigned NumBytesForCalleeToPush = 0;
916 if (CC == CallingConv::X86_StdCall) {
918 NumBytesForCalleeToPush = isSRet ? 4 : 0;
920 NumBytesForCalleeToPush = NumBytes;
922 // If this is is a call to a struct-return function, the callee
923 // pops the hidden struct pointer, so we have to push it back.
924 // This is common for Darwin/X86, Linux & Mingw32 targets.
925 NumBytesForCalleeToPush = isSRet ? 4 : 0;
928 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
930 Ops.push_back(Chain);
931 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
932 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
933 Ops.push_back(InFlag);
934 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
935 InFlag = Chain.getValue(1);
937 // Handle result values, copying them out of physregs into vregs that we
939 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
943 //===----------------------------------------------------------------------===//
944 // FastCall Calling Convention implementation
945 //===----------------------------------------------------------------------===//
947 // The X86 'fastcall' calling convention passes up to two integer arguments in
948 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
949 // and requires that the callee pop its arguments off the stack (allowing proper
950 // tail calls), and has the same return value conventions as C calling convs.
952 // This calling convention always arranges for the callee pop value to be 8n+4
953 // bytes, which is needed for tail recursion elimination and stack alignment
956 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
957 MachineFunction &MF = DAG.getMachineFunction();
958 MachineFrameInfo *MFI = MF.getFrameInfo();
959 SDOperand Root = Op.getOperand(0);
960 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
962 // Assign locations to all of the incoming arguments.
963 SmallVector<CCValAssign, 16> ArgLocs;
964 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
965 getTargetMachine(), ArgLocs);
966 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
968 SmallVector<SDOperand, 8> ArgValues;
969 unsigned LastVal = ~0U;
970 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
971 CCValAssign &VA = ArgLocs[i];
972 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
974 assert(VA.getValNo() != LastVal &&
975 "Don't support value assigned to multiple locs yet");
976 LastVal = VA.getValNo();
979 MVT::ValueType RegVT = VA.getLocVT();
980 TargetRegisterClass *RC;
981 if (RegVT == MVT::i32)
982 RC = X86::GR32RegisterClass;
984 assert(MVT::isVector(RegVT));
985 RC = X86::VR128RegisterClass;
988 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
989 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
991 // If this is an 8 or 16-bit value, it is really passed promoted to 32
992 // bits. Insert an assert[sz]ext to capture this, then truncate to the
994 if (VA.getLocInfo() == CCValAssign::SExt)
995 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
996 DAG.getValueType(VA.getValVT()));
997 else if (VA.getLocInfo() == CCValAssign::ZExt)
998 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
999 DAG.getValueType(VA.getValVT()));
1001 if (VA.getLocInfo() != CCValAssign::Full)
1002 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1004 ArgValues.push_back(ArgValue);
1006 assert(VA.isMemLoc());
1008 // Create the nodes corresponding to a load from this parameter slot.
1009 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1010 VA.getLocMemOffset());
1011 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1012 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1016 ArgValues.push_back(Root);
1018 unsigned StackSize = CCInfo.getNextStackOffset();
1020 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1021 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1022 // arguments and the arguments after the retaddr has been pushed are aligned.
1023 if ((StackSize & 7) == 0)
1027 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1028 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
1029 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
1030 BytesCallerReserves = 0;
1032 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1033 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1035 // Return the new list of results.
1036 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1037 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1041 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1042 const SDOperand &StackPtr,
1043 const CCValAssign &VA,
1046 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1047 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1048 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1049 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1050 if (Flags & ISD::ParamFlags::ByVal) {
1051 unsigned Align = 1 << ((Flags & ISD::ParamFlags::ByValAlign) >>
1052 ISD::ParamFlags::ByValAlignOffs);
1054 assert (Align >= 8);
1055 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1056 ISD::ParamFlags::ByValSizeOffs;
1058 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1059 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1061 return DAG.getNode(ISD::MEMCPY, MVT::Other, Chain, PtrOff, Arg, SizeNode,
1064 return DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1068 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1070 SDOperand Chain = Op.getOperand(0);
1071 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1072 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1073 SDOperand Callee = Op.getOperand(4);
1075 // Analyze operands of the call, assigning locations to each operand.
1076 SmallVector<CCValAssign, 16> ArgLocs;
1077 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1078 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
1080 // Get a count of how many bytes are to be pushed on the stack.
1081 unsigned NumBytes = CCInfo.getNextStackOffset();
1083 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1084 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1085 // arguments and the arguments after the retaddr has been pushed are aligned.
1086 if ((NumBytes & 7) == 0)
1090 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1092 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1093 SmallVector<SDOperand, 8> MemOpChains;
1097 // Walk the register/memloc assignments, inserting copies/loads.
1098 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1099 CCValAssign &VA = ArgLocs[i];
1100 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1102 // Promote the value if needed.
1103 switch (VA.getLocInfo()) {
1104 default: assert(0 && "Unknown loc info!");
1105 case CCValAssign::Full: break;
1106 case CCValAssign::SExt:
1107 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1109 case CCValAssign::ZExt:
1110 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1112 case CCValAssign::AExt:
1113 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1117 if (VA.isRegLoc()) {
1118 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1120 assert(VA.isMemLoc());
1121 if (StackPtr.Val == 0)
1122 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1123 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1124 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1125 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1129 if (!MemOpChains.empty())
1130 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1131 &MemOpChains[0], MemOpChains.size());
1133 // Build a sequence of copy-to-reg nodes chained together with token chain
1134 // and flag operands which copy the outgoing args into registers.
1136 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1137 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1139 InFlag = Chain.getValue(1);
1142 // If the callee is a GlobalAddress node (quite common, every direct call is)
1143 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1144 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1145 // We should use extra load for direct calls to dllimported functions in
1147 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1148 getTargetMachine(), true))
1149 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1150 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1151 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1153 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1155 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1156 Subtarget->isPICStyleGOT()) {
1157 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1158 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1160 InFlag = Chain.getValue(1);
1163 // Returns a chain & a flag for retval copy to use.
1164 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1165 SmallVector<SDOperand, 8> Ops;
1166 Ops.push_back(Chain);
1167 Ops.push_back(Callee);
1169 // Add argument registers to the end of the list so that they are known live
1171 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1172 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1173 RegsToPass[i].second.getValueType()));
1175 // Add an implicit use GOT pointer in EBX.
1176 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1177 Subtarget->isPICStyleGOT())
1178 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1181 Ops.push_back(InFlag);
1183 // FIXME: Do not generate X86ISD::TAILCALL for now.
1184 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1185 NodeTys, &Ops[0], Ops.size());
1186 InFlag = Chain.getValue(1);
1188 // Returns a flag for retval copy to use.
1189 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1191 Ops.push_back(Chain);
1192 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1193 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1194 Ops.push_back(InFlag);
1195 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1196 InFlag = Chain.getValue(1);
1198 // Handle result values, copying them out of physregs into vregs that we
1200 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1204 //===----------------------------------------------------------------------===//
1205 // X86-64 C Calling Convention implementation
1206 //===----------------------------------------------------------------------===//
1209 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1210 MachineFunction &MF = DAG.getMachineFunction();
1211 MachineFrameInfo *MFI = MF.getFrameInfo();
1212 SDOperand Root = Op.getOperand(0);
1213 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1215 static const unsigned GPR64ArgRegs[] = {
1216 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1218 static const unsigned XMMArgRegs[] = {
1219 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1220 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1224 // Assign locations to all of the incoming arguments.
1225 SmallVector<CCValAssign, 16> ArgLocs;
1226 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
1227 getTargetMachine(), ArgLocs);
1228 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
1230 SmallVector<SDOperand, 8> ArgValues;
1231 unsigned LastVal = ~0U;
1232 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1233 CCValAssign &VA = ArgLocs[i];
1234 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1236 assert(VA.getValNo() != LastVal &&
1237 "Don't support value assigned to multiple locs yet");
1238 LastVal = VA.getValNo();
1240 if (VA.isRegLoc()) {
1241 MVT::ValueType RegVT = VA.getLocVT();
1242 TargetRegisterClass *RC;
1243 if (RegVT == MVT::i32)
1244 RC = X86::GR32RegisterClass;
1245 else if (RegVT == MVT::i64)
1246 RC = X86::GR64RegisterClass;
1247 else if (RegVT == MVT::f32)
1248 RC = X86::FR32RegisterClass;
1249 else if (RegVT == MVT::f64)
1250 RC = X86::FR64RegisterClass;
1252 assert(MVT::isVector(RegVT));
1253 if (MVT::getSizeInBits(RegVT) == 64) {
1254 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1257 RC = X86::VR128RegisterClass;
1260 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1261 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1263 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1264 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1266 if (VA.getLocInfo() == CCValAssign::SExt)
1267 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1268 DAG.getValueType(VA.getValVT()));
1269 else if (VA.getLocInfo() == CCValAssign::ZExt)
1270 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1271 DAG.getValueType(VA.getValVT()));
1273 if (VA.getLocInfo() != CCValAssign::Full)
1274 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1276 // Handle MMX values passed in GPRs.
1277 if (RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1278 MVT::getSizeInBits(RegVT) == 64)
1279 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1281 ArgValues.push_back(ArgValue);
1283 assert(VA.isMemLoc());
1285 // Create the nodes corresponding to a load from this parameter slot.
1286 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1287 VA.getLocMemOffset());
1288 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1290 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
1291 if (Flags & ISD::ParamFlags::ByVal)
1292 ArgValues.push_back(FIN);
1294 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1298 unsigned StackSize = CCInfo.getNextStackOffset();
1300 // If the function takes variable number of arguments, make a frame index for
1301 // the start of the first vararg value... for expansion of llvm.va_start.
1303 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1304 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1306 // For X86-64, if there are vararg parameters that are passed via
1307 // registers, then we must store them to their spots on the stack so they
1308 // may be loaded by deferencing the result of va_next.
1309 VarArgsGPOffset = NumIntRegs * 8;
1310 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1311 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1312 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1314 // Store the integer parameter registers.
1315 SmallVector<SDOperand, 8> MemOps;
1316 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1317 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1318 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1319 for (; NumIntRegs != 6; ++NumIntRegs) {
1320 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1321 X86::GR64RegisterClass);
1322 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1323 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1324 MemOps.push_back(Store);
1325 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1326 DAG.getConstant(8, getPointerTy()));
1329 // Now store the XMM (fp + vector) parameter registers.
1330 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1331 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1332 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1333 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1334 X86::VR128RegisterClass);
1335 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1336 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1337 MemOps.push_back(Store);
1338 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1339 DAG.getConstant(16, getPointerTy()));
1341 if (!MemOps.empty())
1342 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1343 &MemOps[0], MemOps.size());
1346 ArgValues.push_back(Root);
1348 BytesToPopOnReturn = 0; // Callee pops nothing.
1349 BytesCallerReserves = StackSize;
1351 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1352 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1354 // Return the new list of results.
1355 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1356 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1360 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1362 SDOperand Chain = Op.getOperand(0);
1363 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1364 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1365 SDOperand Callee = Op.getOperand(4);
1367 // Analyze operands of the call, assigning locations to each operand.
1368 SmallVector<CCValAssign, 16> ArgLocs;
1369 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1370 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_64_C);
1372 // Get a count of how many bytes are to be pushed on the stack.
1373 unsigned NumBytes = CCInfo.getNextStackOffset();
1374 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1376 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1377 SmallVector<SDOperand, 8> MemOpChains;
1381 // Walk the register/memloc assignments, inserting copies/loads.
1382 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1383 CCValAssign &VA = ArgLocs[i];
1384 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1386 // Promote the value if needed.
1387 switch (VA.getLocInfo()) {
1388 default: assert(0 && "Unknown loc info!");
1389 case CCValAssign::Full: break;
1390 case CCValAssign::SExt:
1391 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1393 case CCValAssign::ZExt:
1394 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1396 case CCValAssign::AExt:
1397 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1401 if (VA.isRegLoc()) {
1402 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1404 assert(VA.isMemLoc());
1405 if (StackPtr.Val == 0)
1406 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1408 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1413 if (!MemOpChains.empty())
1414 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1415 &MemOpChains[0], MemOpChains.size());
1417 // Build a sequence of copy-to-reg nodes chained together with token chain
1418 // and flag operands which copy the outgoing args into registers.
1420 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1421 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1423 InFlag = Chain.getValue(1);
1427 // From AMD64 ABI document:
1428 // For calls that may call functions that use varargs or stdargs
1429 // (prototype-less calls or calls to functions containing ellipsis (...) in
1430 // the declaration) %al is used as hidden argument to specify the number
1431 // of SSE registers used. The contents of %al do not need to match exactly
1432 // the number of registers, but must be an ubound on the number of SSE
1433 // registers used and is in the range 0 - 8 inclusive.
1435 // Count the number of XMM registers allocated.
1436 static const unsigned XMMArgRegs[] = {
1437 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1438 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1440 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1442 Chain = DAG.getCopyToReg(Chain, X86::AL,
1443 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1444 InFlag = Chain.getValue(1);
1447 // If the callee is a GlobalAddress node (quite common, every direct call is)
1448 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1449 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1450 // We should use extra load for direct calls to dllimported functions in
1452 if (getTargetMachine().getCodeModel() != CodeModel::Large
1453 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1454 getTargetMachine(), true))
1455 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1456 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1457 if (getTargetMachine().getCodeModel() != CodeModel::Large)
1458 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1460 // Returns a chain & a flag for retval copy to use.
1461 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1462 SmallVector<SDOperand, 8> Ops;
1463 Ops.push_back(Chain);
1464 Ops.push_back(Callee);
1466 // Add argument registers to the end of the list so that they are known live
1468 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1469 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1470 RegsToPass[i].second.getValueType()));
1473 Ops.push_back(InFlag);
1475 // FIXME: Do not generate X86ISD::TAILCALL for now.
1476 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1477 NodeTys, &Ops[0], Ops.size());
1478 InFlag = Chain.getValue(1);
1480 // Returns a flag for retval copy to use.
1481 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1483 Ops.push_back(Chain);
1484 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1485 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1486 Ops.push_back(InFlag);
1487 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1488 InFlag = Chain.getValue(1);
1490 // Handle result values, copying them out of physregs into vregs that we
1492 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1496 //===----------------------------------------------------------------------===//
1497 // Other Lowering Hooks
1498 //===----------------------------------------------------------------------===//
1501 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1502 MachineFunction &MF = DAG.getMachineFunction();
1503 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1504 int ReturnAddrIndex = FuncInfo->getRAIndex();
1506 if (ReturnAddrIndex == 0) {
1507 // Set up a frame object for the return address.
1508 if (Subtarget->is64Bit())
1509 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1511 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1513 FuncInfo->setRAIndex(ReturnAddrIndex);
1516 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1521 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1522 /// specific condition code. It returns a false if it cannot do a direct
1523 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1525 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1526 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1527 SelectionDAG &DAG) {
1528 X86CC = X86::COND_INVALID;
1530 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1531 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1532 // X > -1 -> X == 0, jump !sign.
1533 RHS = DAG.getConstant(0, RHS.getValueType());
1534 X86CC = X86::COND_NS;
1536 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1537 // X < 0 -> X == 0, jump on sign.
1538 X86CC = X86::COND_S;
1543 switch (SetCCOpcode) {
1545 case ISD::SETEQ: X86CC = X86::COND_E; break;
1546 case ISD::SETGT: X86CC = X86::COND_G; break;
1547 case ISD::SETGE: X86CC = X86::COND_GE; break;
1548 case ISD::SETLT: X86CC = X86::COND_L; break;
1549 case ISD::SETLE: X86CC = X86::COND_LE; break;
1550 case ISD::SETNE: X86CC = X86::COND_NE; break;
1551 case ISD::SETULT: X86CC = X86::COND_B; break;
1552 case ISD::SETUGT: X86CC = X86::COND_A; break;
1553 case ISD::SETULE: X86CC = X86::COND_BE; break;
1554 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1557 // On a floating point condition, the flags are set as follows:
1559 // 0 | 0 | 0 | X > Y
1560 // 0 | 0 | 1 | X < Y
1561 // 1 | 0 | 0 | X == Y
1562 // 1 | 1 | 1 | unordered
1564 switch (SetCCOpcode) {
1567 case ISD::SETEQ: X86CC = X86::COND_E; break;
1568 case ISD::SETOLT: Flip = true; // Fallthrough
1570 case ISD::SETGT: X86CC = X86::COND_A; break;
1571 case ISD::SETOLE: Flip = true; // Fallthrough
1573 case ISD::SETGE: X86CC = X86::COND_AE; break;
1574 case ISD::SETUGT: Flip = true; // Fallthrough
1576 case ISD::SETLT: X86CC = X86::COND_B; break;
1577 case ISD::SETUGE: Flip = true; // Fallthrough
1579 case ISD::SETLE: X86CC = X86::COND_BE; break;
1581 case ISD::SETNE: X86CC = X86::COND_NE; break;
1582 case ISD::SETUO: X86CC = X86::COND_P; break;
1583 case ISD::SETO: X86CC = X86::COND_NP; break;
1586 std::swap(LHS, RHS);
1589 return X86CC != X86::COND_INVALID;
1592 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1593 /// code. Current x86 isa includes the following FP cmov instructions:
1594 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1595 static bool hasFPCMov(unsigned X86CC) {
1611 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1612 /// true if Op is undef or if its value falls within the specified range (L, H].
1613 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1614 if (Op.getOpcode() == ISD::UNDEF)
1617 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1618 return (Val >= Low && Val < Hi);
1621 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1622 /// true if Op is undef or if its value equal to the specified value.
1623 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1624 if (Op.getOpcode() == ISD::UNDEF)
1626 return cast<ConstantSDNode>(Op)->getValue() == Val;
1629 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1630 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1631 bool X86::isPSHUFDMask(SDNode *N) {
1632 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1634 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
1637 // Check if the value doesn't reference the second vector.
1638 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1639 SDOperand Arg = N->getOperand(i);
1640 if (Arg.getOpcode() == ISD::UNDEF) continue;
1641 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1642 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
1649 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1650 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1651 bool X86::isPSHUFHWMask(SDNode *N) {
1652 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1654 if (N->getNumOperands() != 8)
1657 // Lower quadword copied in order.
1658 for (unsigned i = 0; i != 4; ++i) {
1659 SDOperand Arg = N->getOperand(i);
1660 if (Arg.getOpcode() == ISD::UNDEF) continue;
1661 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1662 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1666 // Upper quadword shuffled.
1667 for (unsigned i = 4; i != 8; ++i) {
1668 SDOperand Arg = N->getOperand(i);
1669 if (Arg.getOpcode() == ISD::UNDEF) continue;
1670 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1671 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1672 if (Val < 4 || Val > 7)
1679 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1680 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1681 bool X86::isPSHUFLWMask(SDNode *N) {
1682 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1684 if (N->getNumOperands() != 8)
1687 // Upper quadword copied in order.
1688 for (unsigned i = 4; i != 8; ++i)
1689 if (!isUndefOrEqual(N->getOperand(i), i))
1692 // Lower quadword shuffled.
1693 for (unsigned i = 0; i != 4; ++i)
1694 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1700 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1701 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1702 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1703 if (NumElems != 2 && NumElems != 4) return false;
1705 unsigned Half = NumElems / 2;
1706 for (unsigned i = 0; i < Half; ++i)
1707 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1709 for (unsigned i = Half; i < NumElems; ++i)
1710 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1716 bool X86::isSHUFPMask(SDNode *N) {
1717 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1718 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1721 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
1722 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1723 /// half elements to come from vector 1 (which would equal the dest.) and
1724 /// the upper half to come from vector 2.
1725 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1726 if (NumOps != 2 && NumOps != 4) return false;
1728 unsigned Half = NumOps / 2;
1729 for (unsigned i = 0; i < Half; ++i)
1730 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1732 for (unsigned i = Half; i < NumOps; ++i)
1733 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1738 static bool isCommutedSHUFP(SDNode *N) {
1739 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1740 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1743 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1744 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1745 bool X86::isMOVHLPSMask(SDNode *N) {
1746 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1748 if (N->getNumOperands() != 4)
1751 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1752 return isUndefOrEqual(N->getOperand(0), 6) &&
1753 isUndefOrEqual(N->getOperand(1), 7) &&
1754 isUndefOrEqual(N->getOperand(2), 2) &&
1755 isUndefOrEqual(N->getOperand(3), 3);
1758 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1759 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1761 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1762 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1764 if (N->getNumOperands() != 4)
1767 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1768 return isUndefOrEqual(N->getOperand(0), 2) &&
1769 isUndefOrEqual(N->getOperand(1), 3) &&
1770 isUndefOrEqual(N->getOperand(2), 2) &&
1771 isUndefOrEqual(N->getOperand(3), 3);
1774 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1775 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1776 bool X86::isMOVLPMask(SDNode *N) {
1777 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1779 unsigned NumElems = N->getNumOperands();
1780 if (NumElems != 2 && NumElems != 4)
1783 for (unsigned i = 0; i < NumElems/2; ++i)
1784 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1787 for (unsigned i = NumElems/2; i < NumElems; ++i)
1788 if (!isUndefOrEqual(N->getOperand(i), i))
1794 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1795 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1797 bool X86::isMOVHPMask(SDNode *N) {
1798 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1800 unsigned NumElems = N->getNumOperands();
1801 if (NumElems != 2 && NumElems != 4)
1804 for (unsigned i = 0; i < NumElems/2; ++i)
1805 if (!isUndefOrEqual(N->getOperand(i), i))
1808 for (unsigned i = 0; i < NumElems/2; ++i) {
1809 SDOperand Arg = N->getOperand(i + NumElems/2);
1810 if (!isUndefOrEqual(Arg, i + NumElems))
1817 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1818 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1819 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1820 bool V2IsSplat = false) {
1821 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1824 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1825 SDOperand BitI = Elts[i];
1826 SDOperand BitI1 = Elts[i+1];
1827 if (!isUndefOrEqual(BitI, j))
1830 if (isUndefOrEqual(BitI1, NumElts))
1833 if (!isUndefOrEqual(BitI1, j + NumElts))
1841 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1842 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1843 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1846 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1847 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1848 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
1849 bool V2IsSplat = false) {
1850 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1853 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1854 SDOperand BitI = Elts[i];
1855 SDOperand BitI1 = Elts[i+1];
1856 if (!isUndefOrEqual(BitI, j + NumElts/2))
1859 if (isUndefOrEqual(BitI1, NumElts))
1862 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
1870 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1871 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1872 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1875 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1876 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1878 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1879 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1881 unsigned NumElems = N->getNumOperands();
1882 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1885 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1886 SDOperand BitI = N->getOperand(i);
1887 SDOperand BitI1 = N->getOperand(i+1);
1889 if (!isUndefOrEqual(BitI, j))
1891 if (!isUndefOrEqual(BitI1, j))
1898 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
1899 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
1901 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
1902 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1904 unsigned NumElems = N->getNumOperands();
1905 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1908 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
1909 SDOperand BitI = N->getOperand(i);
1910 SDOperand BitI1 = N->getOperand(i + 1);
1912 if (!isUndefOrEqual(BitI, j))
1914 if (!isUndefOrEqual(BitI1, j))
1921 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
1922 /// specifies a shuffle of elements that is suitable for input to MOVSS,
1923 /// MOVSD, and MOVD, i.e. setting the lowest element.
1924 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
1925 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1928 if (!isUndefOrEqual(Elts[0], NumElts))
1931 for (unsigned i = 1; i < NumElts; ++i) {
1932 if (!isUndefOrEqual(Elts[i], i))
1939 bool X86::isMOVLMask(SDNode *N) {
1940 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1941 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
1944 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
1945 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
1946 /// element of vector 2 and the other elements to come from vector 1 in order.
1947 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
1948 bool V2IsSplat = false,
1949 bool V2IsUndef = false) {
1950 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
1953 if (!isUndefOrEqual(Ops[0], 0))
1956 for (unsigned i = 1; i < NumOps; ++i) {
1957 SDOperand Arg = Ops[i];
1958 if (!(isUndefOrEqual(Arg, i+NumOps) ||
1959 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
1960 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
1967 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
1968 bool V2IsUndef = false) {
1969 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1970 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
1971 V2IsSplat, V2IsUndef);
1974 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1975 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
1976 bool X86::isMOVSHDUPMask(SDNode *N) {
1977 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1979 if (N->getNumOperands() != 4)
1982 // Expect 1, 1, 3, 3
1983 for (unsigned i = 0; i < 2; ++i) {
1984 SDOperand Arg = N->getOperand(i);
1985 if (Arg.getOpcode() == ISD::UNDEF) continue;
1986 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1987 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1988 if (Val != 1) return false;
1992 for (unsigned i = 2; i < 4; ++i) {
1993 SDOperand Arg = N->getOperand(i);
1994 if (Arg.getOpcode() == ISD::UNDEF) continue;
1995 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1996 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1997 if (Val != 3) return false;
2001 // Don't use movshdup if it can be done with a shufps.
2005 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2006 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2007 bool X86::isMOVSLDUPMask(SDNode *N) {
2008 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2010 if (N->getNumOperands() != 4)
2013 // Expect 0, 0, 2, 2
2014 for (unsigned i = 0; i < 2; ++i) {
2015 SDOperand Arg = N->getOperand(i);
2016 if (Arg.getOpcode() == ISD::UNDEF) continue;
2017 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2018 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2019 if (Val != 0) return false;
2023 for (unsigned i = 2; i < 4; ++i) {
2024 SDOperand Arg = N->getOperand(i);
2025 if (Arg.getOpcode() == ISD::UNDEF) continue;
2026 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2027 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2028 if (Val != 2) return false;
2032 // Don't use movshdup if it can be done with a shufps.
2036 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2037 /// specifies a identity operation on the LHS or RHS.
2038 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2039 unsigned NumElems = N->getNumOperands();
2040 for (unsigned i = 0; i < NumElems; ++i)
2041 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2046 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2047 /// a splat of a single element.
2048 static bool isSplatMask(SDNode *N) {
2049 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2051 // This is a splat operation if each element of the permute is the same, and
2052 // if the value doesn't reference the second vector.
2053 unsigned NumElems = N->getNumOperands();
2054 SDOperand ElementBase;
2056 for (; i != NumElems; ++i) {
2057 SDOperand Elt = N->getOperand(i);
2058 if (isa<ConstantSDNode>(Elt)) {
2064 if (!ElementBase.Val)
2067 for (; i != NumElems; ++i) {
2068 SDOperand Arg = N->getOperand(i);
2069 if (Arg.getOpcode() == ISD::UNDEF) continue;
2070 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2071 if (Arg != ElementBase) return false;
2074 // Make sure it is a splat of the first vector operand.
2075 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2078 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2079 /// a splat of a single element and it's a 2 or 4 element mask.
2080 bool X86::isSplatMask(SDNode *N) {
2081 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2083 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2084 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2086 return ::isSplatMask(N);
2089 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2090 /// specifies a splat of zero element.
2091 bool X86::isSplatLoMask(SDNode *N) {
2092 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2094 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2095 if (!isUndefOrEqual(N->getOperand(i), 0))
2100 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2101 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2103 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2104 unsigned NumOperands = N->getNumOperands();
2105 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2107 for (unsigned i = 0; i < NumOperands; ++i) {
2109 SDOperand Arg = N->getOperand(NumOperands-i-1);
2110 if (Arg.getOpcode() != ISD::UNDEF)
2111 Val = cast<ConstantSDNode>(Arg)->getValue();
2112 if (Val >= NumOperands) Val -= NumOperands;
2114 if (i != NumOperands - 1)
2121 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2122 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2124 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2126 // 8 nodes, but we only care about the last 4.
2127 for (unsigned i = 7; i >= 4; --i) {
2129 SDOperand Arg = N->getOperand(i);
2130 if (Arg.getOpcode() != ISD::UNDEF)
2131 Val = cast<ConstantSDNode>(Arg)->getValue();
2140 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2141 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2143 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2145 // 8 nodes, but we only care about the first 4.
2146 for (int i = 3; i >= 0; --i) {
2148 SDOperand Arg = N->getOperand(i);
2149 if (Arg.getOpcode() != ISD::UNDEF)
2150 Val = cast<ConstantSDNode>(Arg)->getValue();
2159 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2160 /// specifies a 8 element shuffle that can be broken into a pair of
2161 /// PSHUFHW and PSHUFLW.
2162 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2163 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2165 if (N->getNumOperands() != 8)
2168 // Lower quadword shuffled.
2169 for (unsigned i = 0; i != 4; ++i) {
2170 SDOperand Arg = N->getOperand(i);
2171 if (Arg.getOpcode() == ISD::UNDEF) continue;
2172 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2173 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2178 // Upper quadword shuffled.
2179 for (unsigned i = 4; i != 8; ++i) {
2180 SDOperand Arg = N->getOperand(i);
2181 if (Arg.getOpcode() == ISD::UNDEF) continue;
2182 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2183 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2184 if (Val < 4 || Val > 7)
2191 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2192 /// values in ther permute mask.
2193 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2194 SDOperand &V2, SDOperand &Mask,
2195 SelectionDAG &DAG) {
2196 MVT::ValueType VT = Op.getValueType();
2197 MVT::ValueType MaskVT = Mask.getValueType();
2198 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2199 unsigned NumElems = Mask.getNumOperands();
2200 SmallVector<SDOperand, 8> MaskVec;
2202 for (unsigned i = 0; i != NumElems; ++i) {
2203 SDOperand Arg = Mask.getOperand(i);
2204 if (Arg.getOpcode() == ISD::UNDEF) {
2205 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2208 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2209 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2211 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2213 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2217 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2218 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2221 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2222 /// match movhlps. The lower half elements should come from upper half of
2223 /// V1 (and in order), and the upper half elements should come from the upper
2224 /// half of V2 (and in order).
2225 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2226 unsigned NumElems = Mask->getNumOperands();
2229 for (unsigned i = 0, e = 2; i != e; ++i)
2230 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2232 for (unsigned i = 2; i != 4; ++i)
2233 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2238 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2239 /// is promoted to a vector.
2240 static inline bool isScalarLoadToVector(SDNode *N) {
2241 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2242 N = N->getOperand(0).Val;
2243 return ISD::isNON_EXTLoad(N);
2248 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2249 /// match movlp{s|d}. The lower half elements should come from lower half of
2250 /// V1 (and in order), and the upper half elements should come from the upper
2251 /// half of V2 (and in order). And since V1 will become the source of the
2252 /// MOVLP, it must be either a vector load or a scalar load to vector.
2253 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2254 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2256 // Is V2 is a vector load, don't do this transformation. We will try to use
2257 // load folding shufps op.
2258 if (ISD::isNON_EXTLoad(V2))
2261 unsigned NumElems = Mask->getNumOperands();
2262 if (NumElems != 2 && NumElems != 4)
2264 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2265 if (!isUndefOrEqual(Mask->getOperand(i), i))
2267 for (unsigned i = NumElems/2; i != NumElems; ++i)
2268 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2273 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2275 static bool isSplatVector(SDNode *N) {
2276 if (N->getOpcode() != ISD::BUILD_VECTOR)
2279 SDOperand SplatValue = N->getOperand(0);
2280 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2281 if (N->getOperand(i) != SplatValue)
2286 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2288 static bool isUndefShuffle(SDNode *N) {
2289 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2292 SDOperand V1 = N->getOperand(0);
2293 SDOperand V2 = N->getOperand(1);
2294 SDOperand Mask = N->getOperand(2);
2295 unsigned NumElems = Mask.getNumOperands();
2296 for (unsigned i = 0; i != NumElems; ++i) {
2297 SDOperand Arg = Mask.getOperand(i);
2298 if (Arg.getOpcode() != ISD::UNDEF) {
2299 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2300 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2302 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2309 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2311 static inline bool isZeroNode(SDOperand Elt) {
2312 return ((isa<ConstantSDNode>(Elt) &&
2313 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2314 (isa<ConstantFPSDNode>(Elt) &&
2315 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2318 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2319 /// to an zero vector.
2320 static bool isZeroShuffle(SDNode *N) {
2321 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2324 SDOperand V1 = N->getOperand(0);
2325 SDOperand V2 = N->getOperand(1);
2326 SDOperand Mask = N->getOperand(2);
2327 unsigned NumElems = Mask.getNumOperands();
2328 for (unsigned i = 0; i != NumElems; ++i) {
2329 SDOperand Arg = Mask.getOperand(i);
2330 if (Arg.getOpcode() != ISD::UNDEF) {
2331 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2332 if (Idx < NumElems) {
2333 unsigned Opc = V1.Val->getOpcode();
2334 if (Opc == ISD::UNDEF)
2336 if (Opc != ISD::BUILD_VECTOR ||
2337 !isZeroNode(V1.Val->getOperand(Idx)))
2339 } else if (Idx >= NumElems) {
2340 unsigned Opc = V2.Val->getOpcode();
2341 if (Opc == ISD::UNDEF)
2343 if (Opc != ISD::BUILD_VECTOR ||
2344 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2352 /// getZeroVector - Returns a vector of specified type with all zero elements.
2354 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2355 assert(MVT::isVector(VT) && "Expected a vector type");
2356 unsigned NumElems = MVT::getVectorNumElements(VT);
2357 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2358 bool isFP = MVT::isFloatingPoint(EVT);
2359 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2360 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2361 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2364 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2365 /// that point to V2 points to its first element.
2366 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2367 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2369 bool Changed = false;
2370 SmallVector<SDOperand, 8> MaskVec;
2371 unsigned NumElems = Mask.getNumOperands();
2372 for (unsigned i = 0; i != NumElems; ++i) {
2373 SDOperand Arg = Mask.getOperand(i);
2374 if (Arg.getOpcode() != ISD::UNDEF) {
2375 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2376 if (Val > NumElems) {
2377 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2381 MaskVec.push_back(Arg);
2385 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2386 &MaskVec[0], MaskVec.size());
2390 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2391 /// operation of specified width.
2392 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2393 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2394 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2396 SmallVector<SDOperand, 8> MaskVec;
2397 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2398 for (unsigned i = 1; i != NumElems; ++i)
2399 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2400 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2403 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2404 /// of specified width.
2405 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2406 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2407 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2408 SmallVector<SDOperand, 8> MaskVec;
2409 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2410 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2411 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2413 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2416 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2417 /// of specified width.
2418 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2419 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2420 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2421 unsigned Half = NumElems/2;
2422 SmallVector<SDOperand, 8> MaskVec;
2423 for (unsigned i = 0; i != Half; ++i) {
2424 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2425 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2427 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2430 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2432 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2433 SDOperand V1 = Op.getOperand(0);
2434 SDOperand Mask = Op.getOperand(2);
2435 MVT::ValueType VT = Op.getValueType();
2436 unsigned NumElems = Mask.getNumOperands();
2437 Mask = getUnpacklMask(NumElems, DAG);
2438 while (NumElems != 4) {
2439 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2442 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2444 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2445 Mask = getZeroVector(MaskVT, DAG);
2446 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2447 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2448 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2451 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2452 /// vector of zero or undef vector.
2453 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2454 unsigned NumElems, unsigned Idx,
2455 bool isZero, SelectionDAG &DAG) {
2456 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2457 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2458 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2459 SDOperand Zero = DAG.getConstant(0, EVT);
2460 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2461 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2462 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2463 &MaskVec[0], MaskVec.size());
2464 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2467 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2469 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2470 unsigned NumNonZero, unsigned NumZero,
2471 SelectionDAG &DAG, TargetLowering &TLI) {
2477 for (unsigned i = 0; i < 16; ++i) {
2478 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2479 if (ThisIsNonZero && First) {
2481 V = getZeroVector(MVT::v8i16, DAG);
2483 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2488 SDOperand ThisElt(0, 0), LastElt(0, 0);
2489 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2490 if (LastIsNonZero) {
2491 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2493 if (ThisIsNonZero) {
2494 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2495 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2496 ThisElt, DAG.getConstant(8, MVT::i8));
2498 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2503 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2504 DAG.getConstant(i/2, TLI.getPointerTy()));
2508 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2511 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2513 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2514 unsigned NumNonZero, unsigned NumZero,
2515 SelectionDAG &DAG, TargetLowering &TLI) {
2521 for (unsigned i = 0; i < 8; ++i) {
2522 bool isNonZero = (NonZeros & (1 << i)) != 0;
2526 V = getZeroVector(MVT::v8i16, DAG);
2528 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2531 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2532 DAG.getConstant(i, TLI.getPointerTy()));
2540 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2541 // All zero's are handled with pxor.
2542 if (ISD::isBuildVectorAllZeros(Op.Val))
2545 // All one's are handled with pcmpeqd.
2546 if (ISD::isBuildVectorAllOnes(Op.Val))
2549 MVT::ValueType VT = Op.getValueType();
2550 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2551 unsigned EVTBits = MVT::getSizeInBits(EVT);
2553 unsigned NumElems = Op.getNumOperands();
2554 unsigned NumZero = 0;
2555 unsigned NumNonZero = 0;
2556 unsigned NonZeros = 0;
2557 unsigned NumNonZeroImms = 0;
2558 std::set<SDOperand> Values;
2559 for (unsigned i = 0; i < NumElems; ++i) {
2560 SDOperand Elt = Op.getOperand(i);
2561 if (Elt.getOpcode() != ISD::UNDEF) {
2563 if (isZeroNode(Elt))
2566 NonZeros |= (1 << i);
2568 if (Elt.getOpcode() == ISD::Constant ||
2569 Elt.getOpcode() == ISD::ConstantFP)
2575 if (NumNonZero == 0) {
2577 // All undef vector. Return an UNDEF.
2578 return DAG.getNode(ISD::UNDEF, VT);
2580 // A mix of zero and undef. Return a zero vector.
2581 return getZeroVector(VT, DAG);
2584 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2585 if (Values.size() == 1)
2588 // Special case for single non-zero element.
2589 if (NumNonZero == 1) {
2590 unsigned Idx = CountTrailingZeros_32(NonZeros);
2591 SDOperand Item = Op.getOperand(Idx);
2592 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2594 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2595 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2598 if (EVTBits == 32) {
2599 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2600 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2602 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2603 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2604 SmallVector<SDOperand, 8> MaskVec;
2605 for (unsigned i = 0; i < NumElems; i++)
2606 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2607 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2608 &MaskVec[0], MaskVec.size());
2609 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2610 DAG.getNode(ISD::UNDEF, VT), Mask);
2614 // A vector full of immediates; various special cases are already
2615 // handled, so this is best done with a single constant-pool load.
2616 if (NumNonZero == NumNonZeroImms)
2619 // Let legalizer expand 2-wide build_vectors.
2623 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2624 if (EVTBits == 8 && NumElems == 16) {
2625 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2627 if (V.Val) return V;
2630 if (EVTBits == 16 && NumElems == 8) {
2631 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2633 if (V.Val) return V;
2636 // If element VT is == 32 bits, turn it into a number of shuffles.
2637 SmallVector<SDOperand, 8> V;
2639 if (NumElems == 4 && NumZero > 0) {
2640 for (unsigned i = 0; i < 4; ++i) {
2641 bool isZero = !(NonZeros & (1 << i));
2643 V[i] = getZeroVector(VT, DAG);
2645 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2648 for (unsigned i = 0; i < 2; ++i) {
2649 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2652 V[i] = V[i*2]; // Must be a zero vector.
2655 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2656 getMOVLMask(NumElems, DAG));
2659 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2660 getMOVLMask(NumElems, DAG));
2663 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2664 getUnpacklMask(NumElems, DAG));
2669 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2670 // clears the upper bits.
2671 // FIXME: we can do the same for v4f32 case when we know both parts of
2672 // the lower half come from scalar_to_vector (loadf32). We should do
2673 // that in post legalizer dag combiner with target specific hooks.
2674 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2676 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2677 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2678 SmallVector<SDOperand, 8> MaskVec;
2679 bool Reverse = (NonZeros & 0x3) == 2;
2680 for (unsigned i = 0; i < 2; ++i)
2682 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2684 MaskVec.push_back(DAG.getConstant(i, EVT));
2685 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2686 for (unsigned i = 0; i < 2; ++i)
2688 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2690 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2691 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2692 &MaskVec[0], MaskVec.size());
2693 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2696 if (Values.size() > 2) {
2697 // Expand into a number of unpckl*.
2699 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2700 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2701 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2702 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2703 for (unsigned i = 0; i < NumElems; ++i)
2704 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2706 while (NumElems != 0) {
2707 for (unsigned i = 0; i < NumElems; ++i)
2708 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2719 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2720 SDOperand V1 = Op.getOperand(0);
2721 SDOperand V2 = Op.getOperand(1);
2722 SDOperand PermMask = Op.getOperand(2);
2723 MVT::ValueType VT = Op.getValueType();
2724 unsigned NumElems = PermMask.getNumOperands();
2725 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2726 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2727 bool V1IsSplat = false;
2728 bool V2IsSplat = false;
2730 if (isUndefShuffle(Op.Val))
2731 return DAG.getNode(ISD::UNDEF, VT);
2733 if (isZeroShuffle(Op.Val))
2734 return getZeroVector(VT, DAG);
2736 if (isIdentityMask(PermMask.Val))
2738 else if (isIdentityMask(PermMask.Val, true))
2741 if (isSplatMask(PermMask.Val)) {
2742 if (NumElems <= 4) return Op;
2743 // Promote it to a v4i32 splat.
2744 return PromoteSplat(Op, DAG);
2747 if (X86::isMOVLMask(PermMask.Val))
2748 return (V1IsUndef) ? V2 : Op;
2750 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2751 X86::isMOVSLDUPMask(PermMask.Val) ||
2752 X86::isMOVHLPSMask(PermMask.Val) ||
2753 X86::isMOVHPMask(PermMask.Val) ||
2754 X86::isMOVLPMask(PermMask.Val))
2757 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2758 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
2759 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2761 bool Commuted = false;
2762 V1IsSplat = isSplatVector(V1.Val);
2763 V2IsSplat = isSplatVector(V2.Val);
2764 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
2765 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2766 std::swap(V1IsSplat, V2IsSplat);
2767 std::swap(V1IsUndef, V2IsUndef);
2771 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
2772 if (V2IsUndef) return V1;
2773 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2775 // V2 is a splat, so the mask may be malformed. That is, it may point
2776 // to any V2 element. The instruction selectior won't like this. Get
2777 // a corrected mask and commute to form a proper MOVS{S|D}.
2778 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2779 if (NewMask.Val != PermMask.Val)
2780 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2785 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2786 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2787 X86::isUNPCKLMask(PermMask.Val) ||
2788 X86::isUNPCKHMask(PermMask.Val))
2792 // Normalize mask so all entries that point to V2 points to its first
2793 // element then try to match unpck{h|l} again. If match, return a
2794 // new vector_shuffle with the corrected mask.
2795 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2796 if (NewMask.Val != PermMask.Val) {
2797 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2798 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2799 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2800 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2801 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2802 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2807 // Normalize the node to match x86 shuffle ops if needed
2808 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
2809 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2812 // Commute is back and try unpck* again.
2813 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2814 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2815 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2816 X86::isUNPCKLMask(PermMask.Val) ||
2817 X86::isUNPCKHMask(PermMask.Val))
2821 // If VT is integer, try PSHUF* first, then SHUFP*.
2822 if (MVT::isInteger(VT)) {
2823 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
2824 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
2825 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
2826 X86::isPSHUFDMask(PermMask.Val)) ||
2827 X86::isPSHUFHWMask(PermMask.Val) ||
2828 X86::isPSHUFLWMask(PermMask.Val)) {
2829 if (V2.getOpcode() != ISD::UNDEF)
2830 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2831 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2835 if (X86::isSHUFPMask(PermMask.Val) &&
2836 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
2839 // Handle v8i16 shuffle high / low shuffle node pair.
2840 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2841 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2842 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2843 SmallVector<SDOperand, 8> MaskVec;
2844 for (unsigned i = 0; i != 4; ++i)
2845 MaskVec.push_back(PermMask.getOperand(i));
2846 for (unsigned i = 4; i != 8; ++i)
2847 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2848 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2849 &MaskVec[0], MaskVec.size());
2850 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2852 for (unsigned i = 0; i != 4; ++i)
2853 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2854 for (unsigned i = 4; i != 8; ++i)
2855 MaskVec.push_back(PermMask.getOperand(i));
2856 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
2857 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2860 // Floating point cases in the other order.
2861 if (X86::isSHUFPMask(PermMask.Val))
2863 if (X86::isPSHUFDMask(PermMask.Val) ||
2864 X86::isPSHUFHWMask(PermMask.Val) ||
2865 X86::isPSHUFLWMask(PermMask.Val)) {
2866 if (V2.getOpcode() != ISD::UNDEF)
2867 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2868 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2873 if (NumElems == 4 &&
2874 // Don't do this for MMX.
2875 MVT::getSizeInBits(VT) != 64) {
2876 MVT::ValueType MaskVT = PermMask.getValueType();
2877 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2878 SmallVector<std::pair<int, int>, 8> Locs;
2879 Locs.reserve(NumElems);
2880 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2881 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2884 // If no more than two elements come from either vector. This can be
2885 // implemented with two shuffles. First shuffle gather the elements.
2886 // The second shuffle, which takes the first shuffle as both of its
2887 // vector operands, put the elements into the right order.
2888 for (unsigned i = 0; i != NumElems; ++i) {
2889 SDOperand Elt = PermMask.getOperand(i);
2890 if (Elt.getOpcode() == ISD::UNDEF) {
2891 Locs[i] = std::make_pair(-1, -1);
2893 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2894 if (Val < NumElems) {
2895 Locs[i] = std::make_pair(0, NumLo);
2899 Locs[i] = std::make_pair(1, NumHi);
2900 if (2+NumHi < NumElems)
2901 Mask1[2+NumHi] = Elt;
2906 if (NumLo <= 2 && NumHi <= 2) {
2907 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2908 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2909 &Mask1[0], Mask1.size()));
2910 for (unsigned i = 0; i != NumElems; ++i) {
2911 if (Locs[i].first == -1)
2914 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
2915 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
2916 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
2920 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
2921 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2922 &Mask2[0], Mask2.size()));
2925 // Break it into (shuffle shuffle_hi, shuffle_lo).
2927 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2928 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2929 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
2930 unsigned MaskIdx = 0;
2932 unsigned HiIdx = NumElems/2;
2933 for (unsigned i = 0; i != NumElems; ++i) {
2934 if (i == NumElems/2) {
2940 SDOperand Elt = PermMask.getOperand(i);
2941 if (Elt.getOpcode() == ISD::UNDEF) {
2942 Locs[i] = std::make_pair(-1, -1);
2943 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
2944 Locs[i] = std::make_pair(MaskIdx, LoIdx);
2945 (*MaskPtr)[LoIdx] = Elt;
2948 Locs[i] = std::make_pair(MaskIdx, HiIdx);
2949 (*MaskPtr)[HiIdx] = Elt;
2954 SDOperand LoShuffle =
2955 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2956 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2957 &LoMask[0], LoMask.size()));
2958 SDOperand HiShuffle =
2959 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2960 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2961 &HiMask[0], HiMask.size()));
2962 SmallVector<SDOperand, 8> MaskOps;
2963 for (unsigned i = 0; i != NumElems; ++i) {
2964 if (Locs[i].first == -1) {
2965 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
2967 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
2968 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
2971 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
2972 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2973 &MaskOps[0], MaskOps.size()));
2980 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2981 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2984 MVT::ValueType VT = Op.getValueType();
2985 // TODO: handle v16i8.
2986 if (MVT::getSizeInBits(VT) == 16) {
2987 // Transform it so it match pextrw which produces a 32-bit result.
2988 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
2989 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
2990 Op.getOperand(0), Op.getOperand(1));
2991 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
2992 DAG.getValueType(VT));
2993 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
2994 } else if (MVT::getSizeInBits(VT) == 32) {
2995 SDOperand Vec = Op.getOperand(0);
2996 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2999 // SHUFPS the element to the lowest double word, then movss.
3000 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3001 SmallVector<SDOperand, 8> IdxVec;
3002 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3003 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3004 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3005 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3006 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3007 &IdxVec[0], IdxVec.size());
3008 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3009 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3010 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3011 DAG.getConstant(0, getPointerTy()));
3012 } else if (MVT::getSizeInBits(VT) == 64) {
3013 SDOperand Vec = Op.getOperand(0);
3014 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3018 // UNPCKHPD the element to the lowest double word, then movsd.
3019 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3020 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3021 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3022 SmallVector<SDOperand, 8> IdxVec;
3023 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
3024 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3025 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3026 &IdxVec[0], IdxVec.size());
3027 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3028 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3029 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3030 DAG.getConstant(0, getPointerTy()));
3037 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3038 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3039 // as its second argument.
3040 MVT::ValueType VT = Op.getValueType();
3041 MVT::ValueType BaseVT = MVT::getVectorElementType(VT);
3042 SDOperand N0 = Op.getOperand(0);
3043 SDOperand N1 = Op.getOperand(1);
3044 SDOperand N2 = Op.getOperand(2);
3045 if (MVT::getSizeInBits(BaseVT) == 16) {
3046 if (N1.getValueType() != MVT::i32)
3047 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3048 if (N2.getValueType() != MVT::i32)
3049 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy());
3050 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3051 } else if (MVT::getSizeInBits(BaseVT) == 32) {
3052 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
3055 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
3056 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3057 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
3058 SmallVector<SDOperand, 8> MaskVec;
3059 MaskVec.push_back(DAG.getConstant(4, BaseVT));
3060 for (unsigned i = 1; i <= 3; ++i)
3061 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3062 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
3063 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3064 &MaskVec[0], MaskVec.size()));
3066 // Use two pinsrw instructions to insert a 32 bit value.
3068 if (MVT::isFloatingPoint(N1.getValueType())) {
3069 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
3070 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
3071 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
3072 DAG.getConstant(0, getPointerTy()));
3074 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
3075 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3076 DAG.getConstant(Idx, getPointerTy()));
3077 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
3078 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3079 DAG.getConstant(Idx+1, getPointerTy()));
3080 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3088 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3089 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3090 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3093 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3094 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3095 // one of the above mentioned nodes. It has to be wrapped because otherwise
3096 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3097 // be used to form addressing mode. These wrapped nodes will be selected
3100 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3101 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3102 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3104 CP->getAlignment());
3105 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3106 // With PIC, the address is actually $g + Offset.
3107 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3108 !Subtarget->isPICStyleRIPRel()) {
3109 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3110 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3118 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3119 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3120 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3121 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3122 // With PIC, the address is actually $g + Offset.
3123 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3124 !Subtarget->isPICStyleRIPRel()) {
3125 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3126 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3130 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3131 // load the value at address GV, not the value of GV itself. This means that
3132 // the GlobalAddress must be in the base or index register of the address, not
3133 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3134 // The same applies for external symbols during PIC codegen
3135 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3136 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3141 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3143 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3144 const MVT::ValueType PtrVT) {
3146 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3147 DAG.getNode(X86ISD::GlobalBaseReg,
3149 InFlag = Chain.getValue(1);
3151 // emit leal symbol@TLSGD(,%ebx,1), %eax
3152 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3153 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3154 GA->getValueType(0),
3156 SDOperand Ops[] = { Chain, TGA, InFlag };
3157 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3158 InFlag = Result.getValue(2);
3159 Chain = Result.getValue(1);
3161 // call ___tls_get_addr. This function receives its argument in
3162 // the register EAX.
3163 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3164 InFlag = Chain.getValue(1);
3166 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3167 SDOperand Ops1[] = { Chain,
3168 DAG.getTargetExternalSymbol("___tls_get_addr",
3170 DAG.getRegister(X86::EAX, PtrVT),
3171 DAG.getRegister(X86::EBX, PtrVT),
3173 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3174 InFlag = Chain.getValue(1);
3176 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3179 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3180 // "local exec" model.
3182 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3183 const MVT::ValueType PtrVT) {
3184 // Get the Thread Pointer
3185 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3186 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3188 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3189 GA->getValueType(0),
3191 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3193 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3194 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3196 // The address of the thread local variable is the add of the thread
3197 // pointer with the offset of the variable.
3198 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3202 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3203 // TODO: implement the "local dynamic" model
3204 // TODO: implement the "initial exec"model for pic executables
3205 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3206 "TLS not implemented for non-ELF and 64-bit targets");
3207 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3208 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3209 // otherwise use the "Local Exec"TLS Model
3210 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3211 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3213 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3217 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3218 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3219 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3220 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3221 // With PIC, the address is actually $g + Offset.
3222 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3223 !Subtarget->isPICStyleRIPRel()) {
3224 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3225 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3232 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3233 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3234 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3235 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3236 // With PIC, the address is actually $g + Offset.
3237 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3238 !Subtarget->isPICStyleRIPRel()) {
3239 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3240 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3247 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3248 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3249 "Not an i64 shift!");
3250 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3251 SDOperand ShOpLo = Op.getOperand(0);
3252 SDOperand ShOpHi = Op.getOperand(1);
3253 SDOperand ShAmt = Op.getOperand(2);
3254 SDOperand Tmp1 = isSRA ?
3255 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3256 DAG.getConstant(0, MVT::i32);
3258 SDOperand Tmp2, Tmp3;
3259 if (Op.getOpcode() == ISD::SHL_PARTS) {
3260 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3261 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3263 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3264 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3267 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3268 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3269 DAG.getConstant(32, MVT::i8));
3270 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3271 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3274 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3276 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3277 SmallVector<SDOperand, 4> Ops;
3278 if (Op.getOpcode() == ISD::SHL_PARTS) {
3279 Ops.push_back(Tmp2);
3280 Ops.push_back(Tmp3);
3282 Ops.push_back(InFlag);
3283 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3284 InFlag = Hi.getValue(1);
3287 Ops.push_back(Tmp3);
3288 Ops.push_back(Tmp1);
3290 Ops.push_back(InFlag);
3291 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3293 Ops.push_back(Tmp2);
3294 Ops.push_back(Tmp3);
3296 Ops.push_back(InFlag);
3297 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3298 InFlag = Lo.getValue(1);
3301 Ops.push_back(Tmp3);
3302 Ops.push_back(Tmp1);
3304 Ops.push_back(InFlag);
3305 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3308 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3312 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3315 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3316 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3317 Op.getOperand(0).getValueType() >= MVT::i16 &&
3318 "Unknown SINT_TO_FP to lower!");
3321 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3322 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3323 MachineFunction &MF = DAG.getMachineFunction();
3324 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3325 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3326 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3327 StackSlot, NULL, 0);
3332 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3334 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
3335 SmallVector<SDOperand, 8> Ops;
3336 Ops.push_back(Chain);
3337 Ops.push_back(StackSlot);
3338 Ops.push_back(DAG.getValueType(SrcVT));
3339 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3340 Tys, &Ops[0], Ops.size());
3343 Chain = Result.getValue(1);
3344 SDOperand InFlag = Result.getValue(2);
3346 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3347 // shouldn't be necessary except that RFP cannot be live across
3348 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3349 MachineFunction &MF = DAG.getMachineFunction();
3350 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3351 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3352 Tys = DAG.getVTList(MVT::Other);
3353 SmallVector<SDOperand, 8> Ops;
3354 Ops.push_back(Chain);
3355 Ops.push_back(Result);
3356 Ops.push_back(StackSlot);
3357 Ops.push_back(DAG.getValueType(Op.getValueType()));
3358 Ops.push_back(InFlag);
3359 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3360 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3366 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3367 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3368 "Unknown FP_TO_SINT to lower!");
3369 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3371 MachineFunction &MF = DAG.getMachineFunction();
3372 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3373 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3374 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3377 switch (Op.getValueType()) {
3378 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3379 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3380 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3381 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3384 SDOperand Chain = DAG.getEntryNode();
3385 SDOperand Value = Op.getOperand(0);
3387 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3388 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3389 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
3391 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3393 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3394 Chain = Value.getValue(1);
3395 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3396 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3399 // Build the FP_TO_INT*_IN_MEM
3400 SDOperand Ops[] = { Chain, Value, StackSlot };
3401 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3404 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3407 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3408 MVT::ValueType VT = Op.getValueType();
3409 MVT::ValueType EltVT = VT;
3410 if (MVT::isVector(VT))
3411 EltVT = MVT::getVectorElementType(VT);
3412 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3413 std::vector<Constant*> CV;
3414 if (EltVT == MVT::f64) {
3415 Constant *C = ConstantFP::get(OpNTy, APFloat(BitsToDouble(~(1ULL << 63))));
3419 Constant *C = ConstantFP::get(OpNTy, APFloat(BitsToFloat(~(1U << 31))));
3425 Constant *C = ConstantVector::get(CV);
3426 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3427 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3429 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3432 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3433 MVT::ValueType VT = Op.getValueType();
3434 MVT::ValueType EltVT = VT;
3435 unsigned EltNum = 1;
3436 if (MVT::isVector(VT)) {
3437 EltVT = MVT::getVectorElementType(VT);
3438 EltNum = MVT::getVectorNumElements(VT);
3440 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3441 std::vector<Constant*> CV;
3442 if (EltVT == MVT::f64) {
3443 Constant *C = ConstantFP::get(OpNTy, APFloat(BitsToDouble(1ULL << 63)));
3447 Constant *C = ConstantFP::get(OpNTy, APFloat(BitsToFloat(1U << 31)));
3453 Constant *C = ConstantVector::get(CV);
3454 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3455 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3457 if (MVT::isVector(VT)) {
3458 return DAG.getNode(ISD::BIT_CONVERT, VT,
3459 DAG.getNode(ISD::XOR, MVT::v2i64,
3460 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
3461 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
3463 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3467 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3468 SDOperand Op0 = Op.getOperand(0);
3469 SDOperand Op1 = Op.getOperand(1);
3470 MVT::ValueType VT = Op.getValueType();
3471 MVT::ValueType SrcVT = Op1.getValueType();
3472 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3474 // If second operand is smaller, extend it first.
3475 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3476 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3478 SrcTy = MVT::getTypeForValueType(SrcVT);
3481 // First get the sign bit of second operand.
3482 std::vector<Constant*> CV;
3483 if (SrcVT == MVT::f64) {
3484 CV.push_back(ConstantFP::get(SrcTy, APFloat(BitsToDouble(1ULL << 63))));
3485 CV.push_back(ConstantFP::get(SrcTy, APFloat(0.0)));
3487 CV.push_back(ConstantFP::get(SrcTy, APFloat(BitsToFloat(1U << 31))));
3488 CV.push_back(ConstantFP::get(SrcTy, APFloat(0.0f)));
3489 CV.push_back(ConstantFP::get(SrcTy, APFloat(0.0f)));
3490 CV.push_back(ConstantFP::get(SrcTy, APFloat(0.0f)));
3492 Constant *C = ConstantVector::get(CV);
3493 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3494 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
3496 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3498 // Shift sign bit right or left if the two operands have different types.
3499 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3500 // Op0 is MVT::f32, Op1 is MVT::f64.
3501 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3502 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3503 DAG.getConstant(32, MVT::i32));
3504 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3505 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3506 DAG.getConstant(0, getPointerTy()));
3509 // Clear first operand sign bit.
3511 if (VT == MVT::f64) {
3512 CV.push_back(ConstantFP::get(SrcTy, APFloat(BitsToDouble(~(1ULL << 63)))));
3513 CV.push_back(ConstantFP::get(SrcTy, APFloat(0.0)));
3515 CV.push_back(ConstantFP::get(SrcTy, APFloat(BitsToFloat(~(1U << 31)))));
3516 CV.push_back(ConstantFP::get(SrcTy, APFloat(0.0f)));
3517 CV.push_back(ConstantFP::get(SrcTy, APFloat(0.0f)));
3518 CV.push_back(ConstantFP::get(SrcTy, APFloat(0.0f)));
3520 C = ConstantVector::get(CV);
3521 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3522 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3524 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3526 // Or the value with the sign bit.
3527 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3530 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3532 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3534 SDOperand Op0 = Op.getOperand(0);
3535 SDOperand Op1 = Op.getOperand(1);
3536 SDOperand CC = Op.getOperand(2);
3537 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3538 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3539 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3540 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3543 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3545 SDOperand Ops1[] = { Chain, Op0, Op1 };
3546 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3547 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3548 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3551 assert(isFP && "Illegal integer SetCC!");
3553 SDOperand COps[] = { Chain, Op0, Op1 };
3554 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3556 switch (SetCCOpcode) {
3557 default: assert(false && "Illegal floating point SetCC!");
3558 case ISD::SETOEQ: { // !PF & ZF
3559 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3560 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3561 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3563 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3564 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3566 case ISD::SETUNE: { // PF | !ZF
3567 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3568 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3569 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3571 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3572 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3577 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3578 bool addTest = true;
3579 SDOperand Chain = DAG.getEntryNode();
3580 SDOperand Cond = Op.getOperand(0);
3582 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3584 if (Cond.getOpcode() == ISD::SETCC)
3585 Cond = LowerSETCC(Cond, DAG, Chain);
3587 if (Cond.getOpcode() == X86ISD::SETCC) {
3588 CC = Cond.getOperand(0);
3590 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3591 // (since flag operand cannot be shared). Use it as the condition setting
3592 // operand in place of the X86ISD::SETCC.
3593 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3594 // to use a test instead of duplicating the X86ISD::CMP (for register
3595 // pressure reason)?
3596 SDOperand Cmp = Cond.getOperand(1);
3597 unsigned Opc = Cmp.getOpcode();
3598 bool IllegalFPCMov = !X86ScalarSSE &&
3599 MVT::isFloatingPoint(Op.getValueType()) &&
3600 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3601 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3603 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3604 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3610 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3611 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3612 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3615 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3616 SmallVector<SDOperand, 4> Ops;
3617 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3618 // condition is true.
3619 Ops.push_back(Op.getOperand(2));
3620 Ops.push_back(Op.getOperand(1));
3622 Ops.push_back(Cond.getValue(1));
3623 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3626 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3627 bool addTest = true;
3628 SDOperand Chain = Op.getOperand(0);
3629 SDOperand Cond = Op.getOperand(1);
3630 SDOperand Dest = Op.getOperand(2);
3632 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3634 if (Cond.getOpcode() == ISD::SETCC)
3635 Cond = LowerSETCC(Cond, DAG, Chain);
3637 if (Cond.getOpcode() == X86ISD::SETCC) {
3638 CC = Cond.getOperand(0);
3640 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3641 // (since flag operand cannot be shared). Use it as the condition setting
3642 // operand in place of the X86ISD::SETCC.
3643 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3644 // to use a test instead of duplicating the X86ISD::CMP (for register
3645 // pressure reason)?
3646 SDOperand Cmp = Cond.getOperand(1);
3647 unsigned Opc = Cmp.getOpcode();
3648 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3649 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3650 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3656 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3657 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3658 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3660 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3661 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3664 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3665 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3667 if (Subtarget->is64Bit())
3668 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3670 switch (CallingConv) {
3672 assert(0 && "Unsupported calling convention");
3673 case CallingConv::Fast:
3674 // TODO: Implement fastcc
3676 case CallingConv::C:
3677 case CallingConv::X86_StdCall:
3678 return LowerCCCCallTo(Op, DAG, CallingConv);
3679 case CallingConv::X86_FastCall:
3680 return LowerFastCCCallTo(Op, DAG, CallingConv);
3685 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3686 // Calls to _alloca is needed to probe the stack when allocating more than 4k
3687 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3688 // that the guard pages used by the OS virtual memory manager are allocated in
3689 // correct sequence.
3691 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
3692 SelectionDAG &DAG) {
3693 assert(Subtarget->isTargetCygMing() &&
3694 "This should be used only on Cygwin/Mingw targets");
3697 SDOperand Chain = Op.getOperand(0);
3698 SDOperand Size = Op.getOperand(1);
3699 // FIXME: Ensure alignment here
3703 MVT::ValueType IntPtr = getPointerTy();
3704 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
3706 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
3707 Flag = Chain.getValue(1);
3709 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3710 SDOperand Ops[] = { Chain,
3711 DAG.getTargetExternalSymbol("_alloca", IntPtr),
3712 DAG.getRegister(X86::EAX, IntPtr),
3714 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
3715 Flag = Chain.getValue(1);
3717 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
3719 std::vector<MVT::ValueType> Tys;
3720 Tys.push_back(SPTy);
3721 Tys.push_back(MVT::Other);
3722 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
3723 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
3727 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3728 MachineFunction &MF = DAG.getMachineFunction();
3729 const Function* Fn = MF.getFunction();
3730 if (Fn->hasExternalLinkage() &&
3731 Subtarget->isTargetCygMing() &&
3732 Fn->getName() == "main")
3733 MF.getInfo<X86MachineFunctionInfo>()->setForceFramePointer(true);
3735 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3736 if (Subtarget->is64Bit())
3737 return LowerX86_64CCCArguments(Op, DAG);
3741 assert(0 && "Unsupported calling convention");
3742 case CallingConv::Fast:
3743 // TODO: implement fastcc.
3746 case CallingConv::C:
3747 return LowerCCCArguments(Op, DAG);
3748 case CallingConv::X86_StdCall:
3749 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(StdCall);
3750 return LowerCCCArguments(Op, DAG, true);
3751 case CallingConv::X86_FastCall:
3752 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(FastCall);
3753 return LowerFastCCArguments(Op, DAG);
3757 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3758 SDOperand InFlag(0, 0);
3759 SDOperand Chain = Op.getOperand(0);
3761 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3762 if (Align == 0) Align = 1;
3764 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3765 // If not DWORD aligned or size is more than the threshold, call memset.
3766 // The libc version is likely to be faster for these cases. It can use the
3767 // address value and run time information about the CPU.
3768 if ((Align & 3) != 0 ||
3769 (I && I->getValue() > Subtarget->getMinRepStrSizeThreshold())) {
3770 MVT::ValueType IntPtr = getPointerTy();
3771 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3772 TargetLowering::ArgListTy Args;
3773 TargetLowering::ArgListEntry Entry;
3774 Entry.Node = Op.getOperand(1);
3775 Entry.Ty = IntPtrTy;
3776 Args.push_back(Entry);
3777 // Extend the unsigned i8 argument to be an int value for the call.
3778 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3779 Entry.Ty = IntPtrTy;
3780 Args.push_back(Entry);
3781 Entry.Node = Op.getOperand(3);
3782 Args.push_back(Entry);
3783 std::pair<SDOperand,SDOperand> CallResult =
3784 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3785 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3786 return CallResult.second;
3791 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3792 unsigned BytesLeft = 0;
3793 bool TwoRepStos = false;
3796 uint64_t Val = ValC->getValue() & 255;
3798 // If the value is a constant, then we can potentially use larger sets.
3799 switch (Align & 3) {
3800 case 2: // WORD aligned
3803 Val = (Val << 8) | Val;
3805 case 0: // DWORD aligned
3808 Val = (Val << 8) | Val;
3809 Val = (Val << 16) | Val;
3810 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3813 Val = (Val << 32) | Val;
3816 default: // Byte aligned
3819 Count = Op.getOperand(3);
3823 if (AVT > MVT::i8) {
3825 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3826 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3827 BytesLeft = I->getValue() % UBytes;
3829 assert(AVT >= MVT::i32 &&
3830 "Do not use rep;stos if not at least DWORD aligned");
3831 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3832 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3837 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3839 InFlag = Chain.getValue(1);
3842 Count = Op.getOperand(3);
3843 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
3844 InFlag = Chain.getValue(1);
3847 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3849 InFlag = Chain.getValue(1);
3850 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3851 Op.getOperand(1), InFlag);
3852 InFlag = Chain.getValue(1);
3854 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3855 SmallVector<SDOperand, 8> Ops;
3856 Ops.push_back(Chain);
3857 Ops.push_back(DAG.getValueType(AVT));
3858 Ops.push_back(InFlag);
3859 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3862 InFlag = Chain.getValue(1);
3863 Count = Op.getOperand(3);
3864 MVT::ValueType CVT = Count.getValueType();
3865 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3866 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3867 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3869 InFlag = Chain.getValue(1);
3870 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3872 Ops.push_back(Chain);
3873 Ops.push_back(DAG.getValueType(MVT::i8));
3874 Ops.push_back(InFlag);
3875 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3876 } else if (BytesLeft) {
3877 // Issue stores for the last 1 - 7 bytes.
3879 unsigned Val = ValC->getValue() & 255;
3880 unsigned Offset = I->getValue() - BytesLeft;
3881 SDOperand DstAddr = Op.getOperand(1);
3882 MVT::ValueType AddrVT = DstAddr.getValueType();
3883 if (BytesLeft >= 4) {
3884 Val = (Val << 8) | Val;
3885 Val = (Val << 16) | Val;
3886 Value = DAG.getConstant(Val, MVT::i32);
3887 Chain = DAG.getStore(Chain, Value,
3888 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3889 DAG.getConstant(Offset, AddrVT)),
3894 if (BytesLeft >= 2) {
3895 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
3896 Chain = DAG.getStore(Chain, Value,
3897 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3898 DAG.getConstant(Offset, AddrVT)),
3903 if (BytesLeft == 1) {
3904 Value = DAG.getConstant(Val, MVT::i8);
3905 Chain = DAG.getStore(Chain, Value,
3906 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3907 DAG.getConstant(Offset, AddrVT)),
3915 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
3916 SDOperand Chain = Op.getOperand(0);
3918 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3919 if (Align == 0) Align = 1;
3921 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3922 // If not DWORD aligned or size is more than the threshold, call memcpy.
3923 // The libc version is likely to be faster for these cases. It can use the
3924 // address value and run time information about the CPU.
3925 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster
3926 if ((Align & 3) != 0 ||
3927 (I && I->getValue() > Subtarget->getMinRepStrSizeThreshold())) {
3928 MVT::ValueType IntPtr = getPointerTy();
3929 TargetLowering::ArgListTy Args;
3930 TargetLowering::ArgListEntry Entry;
3931 Entry.Ty = getTargetData()->getIntPtrType();
3932 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
3933 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
3934 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
3935 std::pair<SDOperand,SDOperand> CallResult =
3936 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3937 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
3938 return CallResult.second;
3943 unsigned BytesLeft = 0;
3944 bool TwoRepMovs = false;
3945 switch (Align & 3) {
3946 case 2: // WORD aligned
3949 case 0: // DWORD aligned
3951 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
3954 default: // Byte aligned
3956 Count = Op.getOperand(3);
3960 if (AVT > MVT::i8) {
3962 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3963 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3964 BytesLeft = I->getValue() % UBytes;
3966 assert(AVT >= MVT::i32 &&
3967 "Do not use rep;movs if not at least DWORD aligned");
3968 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3969 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3974 SDOperand InFlag(0, 0);
3975 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3977 InFlag = Chain.getValue(1);
3978 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3979 Op.getOperand(1), InFlag);
3980 InFlag = Chain.getValue(1);
3981 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
3982 Op.getOperand(2), InFlag);
3983 InFlag = Chain.getValue(1);
3985 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3986 SmallVector<SDOperand, 8> Ops;
3987 Ops.push_back(Chain);
3988 Ops.push_back(DAG.getValueType(AVT));
3989 Ops.push_back(InFlag);
3990 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3993 InFlag = Chain.getValue(1);
3994 Count = Op.getOperand(3);
3995 MVT::ValueType CVT = Count.getValueType();
3996 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3997 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3998 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4000 InFlag = Chain.getValue(1);
4001 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4003 Ops.push_back(Chain);
4004 Ops.push_back(DAG.getValueType(MVT::i8));
4005 Ops.push_back(InFlag);
4006 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4007 } else if (BytesLeft) {
4008 // Issue loads and stores for the last 1 - 7 bytes.
4009 unsigned Offset = I->getValue() - BytesLeft;
4010 SDOperand DstAddr = Op.getOperand(1);
4011 MVT::ValueType DstVT = DstAddr.getValueType();
4012 SDOperand SrcAddr = Op.getOperand(2);
4013 MVT::ValueType SrcVT = SrcAddr.getValueType();
4015 if (BytesLeft >= 4) {
4016 Value = DAG.getLoad(MVT::i32, Chain,
4017 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4018 DAG.getConstant(Offset, SrcVT)),
4020 Chain = Value.getValue(1);
4021 Chain = DAG.getStore(Chain, Value,
4022 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4023 DAG.getConstant(Offset, DstVT)),
4028 if (BytesLeft >= 2) {
4029 Value = DAG.getLoad(MVT::i16, Chain,
4030 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4031 DAG.getConstant(Offset, SrcVT)),
4033 Chain = Value.getValue(1);
4034 Chain = DAG.getStore(Chain, Value,
4035 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4036 DAG.getConstant(Offset, DstVT)),
4042 if (BytesLeft == 1) {
4043 Value = DAG.getLoad(MVT::i8, Chain,
4044 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4045 DAG.getConstant(Offset, SrcVT)),
4047 Chain = Value.getValue(1);
4048 Chain = DAG.getStore(Chain, Value,
4049 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4050 DAG.getConstant(Offset, DstVT)),
4059 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
4060 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4061 SDOperand TheOp = Op.getOperand(0);
4062 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
4063 if (Subtarget->is64Bit()) {
4064 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4065 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
4066 MVT::i64, Copy1.getValue(2));
4067 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
4068 DAG.getConstant(32, MVT::i8));
4070 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
4073 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4074 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
4077 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4078 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
4079 MVT::i32, Copy1.getValue(2));
4080 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
4081 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
4082 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
4085 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4086 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4088 if (!Subtarget->is64Bit()) {
4089 // vastart just stores the address of the VarArgsFrameIndex slot into the
4090 // memory location argument.
4091 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4092 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4097 // gp_offset (0 - 6 * 8)
4098 // fp_offset (48 - 48 + 8 * 16)
4099 // overflow_arg_area (point to parameters coming in memory).
4101 SmallVector<SDOperand, 8> MemOps;
4102 SDOperand FIN = Op.getOperand(1);
4104 SDOperand Store = DAG.getStore(Op.getOperand(0),
4105 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4106 FIN, SV->getValue(), SV->getOffset());
4107 MemOps.push_back(Store);
4110 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4111 DAG.getConstant(4, getPointerTy()));
4112 Store = DAG.getStore(Op.getOperand(0),
4113 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4114 FIN, SV->getValue(), SV->getOffset());
4115 MemOps.push_back(Store);
4117 // Store ptr to overflow_arg_area
4118 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4119 DAG.getConstant(4, getPointerTy()));
4120 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4121 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4123 MemOps.push_back(Store);
4125 // Store ptr to reg_save_area.
4126 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4127 DAG.getConstant(8, getPointerTy()));
4128 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4129 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4131 MemOps.push_back(Store);
4132 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4135 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4136 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4137 SDOperand Chain = Op.getOperand(0);
4138 SDOperand DstPtr = Op.getOperand(1);
4139 SDOperand SrcPtr = Op.getOperand(2);
4140 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4141 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4143 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4144 SrcSV->getValue(), SrcSV->getOffset());
4145 Chain = SrcPtr.getValue(1);
4146 for (unsigned i = 0; i < 3; ++i) {
4147 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4148 SrcSV->getValue(), SrcSV->getOffset());
4149 Chain = Val.getValue(1);
4150 Chain = DAG.getStore(Chain, Val, DstPtr,
4151 DstSV->getValue(), DstSV->getOffset());
4154 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4155 DAG.getConstant(8, getPointerTy()));
4156 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4157 DAG.getConstant(8, getPointerTy()));
4163 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4164 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4166 default: return SDOperand(); // Don't custom lower most intrinsics.
4167 // Comparison intrinsics.
4168 case Intrinsic::x86_sse_comieq_ss:
4169 case Intrinsic::x86_sse_comilt_ss:
4170 case Intrinsic::x86_sse_comile_ss:
4171 case Intrinsic::x86_sse_comigt_ss:
4172 case Intrinsic::x86_sse_comige_ss:
4173 case Intrinsic::x86_sse_comineq_ss:
4174 case Intrinsic::x86_sse_ucomieq_ss:
4175 case Intrinsic::x86_sse_ucomilt_ss:
4176 case Intrinsic::x86_sse_ucomile_ss:
4177 case Intrinsic::x86_sse_ucomigt_ss:
4178 case Intrinsic::x86_sse_ucomige_ss:
4179 case Intrinsic::x86_sse_ucomineq_ss:
4180 case Intrinsic::x86_sse2_comieq_sd:
4181 case Intrinsic::x86_sse2_comilt_sd:
4182 case Intrinsic::x86_sse2_comile_sd:
4183 case Intrinsic::x86_sse2_comigt_sd:
4184 case Intrinsic::x86_sse2_comige_sd:
4185 case Intrinsic::x86_sse2_comineq_sd:
4186 case Intrinsic::x86_sse2_ucomieq_sd:
4187 case Intrinsic::x86_sse2_ucomilt_sd:
4188 case Intrinsic::x86_sse2_ucomile_sd:
4189 case Intrinsic::x86_sse2_ucomigt_sd:
4190 case Intrinsic::x86_sse2_ucomige_sd:
4191 case Intrinsic::x86_sse2_ucomineq_sd: {
4193 ISD::CondCode CC = ISD::SETCC_INVALID;
4196 case Intrinsic::x86_sse_comieq_ss:
4197 case Intrinsic::x86_sse2_comieq_sd:
4201 case Intrinsic::x86_sse_comilt_ss:
4202 case Intrinsic::x86_sse2_comilt_sd:
4206 case Intrinsic::x86_sse_comile_ss:
4207 case Intrinsic::x86_sse2_comile_sd:
4211 case Intrinsic::x86_sse_comigt_ss:
4212 case Intrinsic::x86_sse2_comigt_sd:
4216 case Intrinsic::x86_sse_comige_ss:
4217 case Intrinsic::x86_sse2_comige_sd:
4221 case Intrinsic::x86_sse_comineq_ss:
4222 case Intrinsic::x86_sse2_comineq_sd:
4226 case Intrinsic::x86_sse_ucomieq_ss:
4227 case Intrinsic::x86_sse2_ucomieq_sd:
4228 Opc = X86ISD::UCOMI;
4231 case Intrinsic::x86_sse_ucomilt_ss:
4232 case Intrinsic::x86_sse2_ucomilt_sd:
4233 Opc = X86ISD::UCOMI;
4236 case Intrinsic::x86_sse_ucomile_ss:
4237 case Intrinsic::x86_sse2_ucomile_sd:
4238 Opc = X86ISD::UCOMI;
4241 case Intrinsic::x86_sse_ucomigt_ss:
4242 case Intrinsic::x86_sse2_ucomigt_sd:
4243 Opc = X86ISD::UCOMI;
4246 case Intrinsic::x86_sse_ucomige_ss:
4247 case Intrinsic::x86_sse2_ucomige_sd:
4248 Opc = X86ISD::UCOMI;
4251 case Intrinsic::x86_sse_ucomineq_ss:
4252 case Intrinsic::x86_sse2_ucomineq_sd:
4253 Opc = X86ISD::UCOMI;
4259 SDOperand LHS = Op.getOperand(1);
4260 SDOperand RHS = Op.getOperand(2);
4261 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4263 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4264 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4265 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4266 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4267 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4268 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4269 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4274 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4275 // Depths > 0 not supported yet!
4276 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4279 // Just load the return address
4280 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4281 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4284 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4285 // Depths > 0 not supported yet!
4286 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4289 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4290 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4291 DAG.getConstant(4, getPointerTy()));
4294 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
4295 SelectionDAG &DAG) {
4296 // Is not yet supported on x86-64
4297 if (Subtarget->is64Bit())
4300 return DAG.getConstant(8, getPointerTy());
4303 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
4305 assert(!Subtarget->is64Bit() &&
4306 "Lowering of eh_return builtin is not supported yet on x86-64");
4308 MachineFunction &MF = DAG.getMachineFunction();
4309 SDOperand Chain = Op.getOperand(0);
4310 SDOperand Offset = Op.getOperand(1);
4311 SDOperand Handler = Op.getOperand(2);
4313 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
4316 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
4317 DAG.getConstant(-4UL, getPointerTy()));
4318 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
4319 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
4320 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
4321 MF.addLiveOut(X86::ECX);
4323 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
4324 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
4327 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
4328 SelectionDAG &DAG) {
4329 SDOperand Root = Op.getOperand(0);
4330 SDOperand Trmp = Op.getOperand(1); // trampoline
4331 SDOperand FPtr = Op.getOperand(2); // nested function
4332 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
4334 SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4));
4336 if (Subtarget->is64Bit()) {
4337 return SDOperand(); // not yet supported
4339 Function *Func = (Function *)
4340 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
4341 unsigned CC = Func->getCallingConv();
4346 assert(0 && "Unsupported calling convention");
4347 case CallingConv::C:
4348 case CallingConv::Fast:
4349 case CallingConv::X86_StdCall: {
4350 // Pass 'nest' parameter in ECX.
4351 // Must be kept in sync with X86CallingConv.td
4354 // Check that ECX wasn't needed by an 'inreg' parameter.
4355 const FunctionType *FTy = Func->getFunctionType();
4356 const ParamAttrsList *Attrs = FTy->getParamAttrs();
4358 if (Attrs && !Func->isVarArg()) {
4359 unsigned InRegCount = 0;
4362 for (FunctionType::param_iterator I = FTy->param_begin(),
4363 E = FTy->param_end(); I != E; ++I, ++Idx)
4364 if (Attrs->paramHasAttr(Idx, ParamAttr::InReg))
4365 // FIXME: should only count parameters that are lowered to integers.
4366 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
4368 if (InRegCount > 2) {
4369 cerr << "Nest register in use - reduce number of inreg parameters!\n";
4375 case CallingConv::X86_FastCall:
4376 // Pass 'nest' parameter in EAX.
4377 // Must be kept in sync with X86CallingConv.td
4382 const X86InstrInfo *TII =
4383 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
4385 SDOperand OutChains[4];
4386 SDOperand Addr, Disp;
4388 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
4389 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
4391 unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
4392 unsigned char N86Reg = ((X86RegisterInfo&)RegInfo).getX86RegNum(NestReg);
4393 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
4394 Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
4396 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
4397 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4398 TrmpSV->getOffset() + 1, false, 1);
4400 unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
4401 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
4402 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
4403 TrmpSV->getValue() + 5, TrmpSV->getOffset());
4405 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
4406 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(),
4407 TrmpSV->getOffset() + 6, false, 1);
4409 return DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4);
4413 /// LowerOperation - Provide custom lowering hooks for some operations.
4415 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4416 switch (Op.getOpcode()) {
4417 default: assert(0 && "Should not custom lower this!");
4418 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4419 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4420 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4421 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4422 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4423 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4424 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4425 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4426 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4427 case ISD::SHL_PARTS:
4428 case ISD::SRA_PARTS:
4429 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4430 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4431 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4432 case ISD::FABS: return LowerFABS(Op, DAG);
4433 case ISD::FNEG: return LowerFNEG(Op, DAG);
4434 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4435 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4436 case ISD::SELECT: return LowerSELECT(Op, DAG);
4437 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4438 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4439 case ISD::CALL: return LowerCALL(Op, DAG);
4440 case ISD::RET: return LowerRET(Op, DAG);
4441 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4442 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4443 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4444 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4445 case ISD::VASTART: return LowerVASTART(Op, DAG);
4446 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
4447 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4448 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4449 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4450 case ISD::FRAME_TO_ARGS_OFFSET:
4451 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
4452 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
4453 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
4454 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4459 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4461 default: return NULL;
4462 case X86ISD::SHLD: return "X86ISD::SHLD";
4463 case X86ISD::SHRD: return "X86ISD::SHRD";
4464 case X86ISD::FAND: return "X86ISD::FAND";
4465 case X86ISD::FOR: return "X86ISD::FOR";
4466 case X86ISD::FXOR: return "X86ISD::FXOR";
4467 case X86ISD::FSRL: return "X86ISD::FSRL";
4468 case X86ISD::FILD: return "X86ISD::FILD";
4469 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4470 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4471 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4472 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4473 case X86ISD::FLD: return "X86ISD::FLD";
4474 case X86ISD::FST: return "X86ISD::FST";
4475 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4476 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4477 case X86ISD::CALL: return "X86ISD::CALL";
4478 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4479 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4480 case X86ISD::CMP: return "X86ISD::CMP";
4481 case X86ISD::COMI: return "X86ISD::COMI";
4482 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4483 case X86ISD::SETCC: return "X86ISD::SETCC";
4484 case X86ISD::CMOV: return "X86ISD::CMOV";
4485 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4486 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4487 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4488 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4489 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4490 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4491 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4492 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4493 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4494 case X86ISD::FMAX: return "X86ISD::FMAX";
4495 case X86ISD::FMIN: return "X86ISD::FMIN";
4496 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
4497 case X86ISD::FRCP: return "X86ISD::FRCP";
4498 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
4499 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
4500 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
4504 // isLegalAddressingMode - Return true if the addressing mode represented
4505 // by AM is legal for this target, for a load/store of the specified type.
4506 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
4507 const Type *Ty) const {
4508 // X86 supports extremely general addressing modes.
4510 // X86 allows a sign-extended 32-bit immediate field as a displacement.
4511 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
4515 // We can only fold this if we don't need an extra load.
4516 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
4519 // X86-64 only supports addr of globals in small code model.
4520 if (Subtarget->is64Bit()) {
4521 if (getTargetMachine().getCodeModel() != CodeModel::Small)
4523 // If lower 4G is not available, then we must use rip-relative addressing.
4524 if (AM.BaseOffs || AM.Scale > 1)
4535 // These scales always work.
4540 // These scales are formed with basereg+scalereg. Only accept if there is
4545 default: // Other stuff never works.
4553 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4554 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4555 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4556 /// are assumed to be legal.
4558 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4559 // Only do shuffles on 128-bit vector types for now.
4560 if (MVT::getSizeInBits(VT) == 64) return false;
4561 return (Mask.Val->getNumOperands() <= 4 ||
4562 isIdentityMask(Mask.Val) ||
4563 isIdentityMask(Mask.Val, true) ||
4564 isSplatMask(Mask.Val) ||
4565 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4566 X86::isUNPCKLMask(Mask.Val) ||
4567 X86::isUNPCKHMask(Mask.Val) ||
4568 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4569 X86::isUNPCKH_v_undef_Mask(Mask.Val));
4572 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4574 SelectionDAG &DAG) const {
4575 unsigned NumElts = BVOps.size();
4576 // Only do shuffles on 128-bit vector types for now.
4577 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4578 if (NumElts == 2) return true;
4580 return (isMOVLMask(&BVOps[0], 4) ||
4581 isCommutedMOVL(&BVOps[0], 4, true) ||
4582 isSHUFPMask(&BVOps[0], 4) ||
4583 isCommutedSHUFP(&BVOps[0], 4));
4588 //===----------------------------------------------------------------------===//
4589 // X86 Scheduler Hooks
4590 //===----------------------------------------------------------------------===//
4593 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4594 MachineBasicBlock *BB) {
4595 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4596 switch (MI->getOpcode()) {
4597 default: assert(false && "Unexpected instr type to insert");
4598 case X86::CMOV_FR32:
4599 case X86::CMOV_FR64:
4600 case X86::CMOV_V4F32:
4601 case X86::CMOV_V2F64:
4602 case X86::CMOV_V2I64: {
4603 // To "insert" a SELECT_CC instruction, we actually have to insert the
4604 // diamond control-flow pattern. The incoming instruction knows the
4605 // destination vreg to set, the condition code register to branch on, the
4606 // true/false values to select between, and a branch opcode to use.
4607 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4608 ilist<MachineBasicBlock>::iterator It = BB;
4614 // cmpTY ccX, r1, r2
4616 // fallthrough --> copy0MBB
4617 MachineBasicBlock *thisMBB = BB;
4618 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4619 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4621 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4622 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4623 MachineFunction *F = BB->getParent();
4624 F->getBasicBlockList().insert(It, copy0MBB);
4625 F->getBasicBlockList().insert(It, sinkMBB);
4626 // Update machine-CFG edges by first adding all successors of the current
4627 // block to the new block which will contain the Phi node for the select.
4628 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4629 e = BB->succ_end(); i != e; ++i)
4630 sinkMBB->addSuccessor(*i);
4631 // Next, remove all successors of the current block, and add the true
4632 // and fallthrough blocks as its successors.
4633 while(!BB->succ_empty())
4634 BB->removeSuccessor(BB->succ_begin());
4635 BB->addSuccessor(copy0MBB);
4636 BB->addSuccessor(sinkMBB);
4639 // %FalseValue = ...
4640 // # fallthrough to sinkMBB
4643 // Update machine-CFG edges
4644 BB->addSuccessor(sinkMBB);
4647 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4650 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4651 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4652 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4654 delete MI; // The pseudo instruction is gone now.
4658 case X86::FP32_TO_INT16_IN_MEM:
4659 case X86::FP32_TO_INT32_IN_MEM:
4660 case X86::FP32_TO_INT64_IN_MEM:
4661 case X86::FP64_TO_INT16_IN_MEM:
4662 case X86::FP64_TO_INT32_IN_MEM:
4663 case X86::FP64_TO_INT64_IN_MEM:
4664 case X86::FP80_TO_INT16_IN_MEM:
4665 case X86::FP80_TO_INT32_IN_MEM:
4666 case X86::FP80_TO_INT64_IN_MEM: {
4667 // Change the floating point control register to use "round towards zero"
4668 // mode when truncating to an integer value.
4669 MachineFunction *F = BB->getParent();
4670 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4671 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4673 // Load the old value of the high byte of the control word...
4675 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4676 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4678 // Set the high part to be round to zero...
4679 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4682 // Reload the modified control word now...
4683 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4685 // Restore the memory image of control word to original value
4686 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4689 // Get the X86 opcode to use.
4691 switch (MI->getOpcode()) {
4692 default: assert(0 && "illegal opcode!");
4693 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
4694 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
4695 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
4696 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
4697 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
4698 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
4699 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
4700 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
4701 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
4705 MachineOperand &Op = MI->getOperand(0);
4706 if (Op.isRegister()) {
4707 AM.BaseType = X86AddressMode::RegBase;
4708 AM.Base.Reg = Op.getReg();
4710 AM.BaseType = X86AddressMode::FrameIndexBase;
4711 AM.Base.FrameIndex = Op.getFrameIndex();
4713 Op = MI->getOperand(1);
4714 if (Op.isImmediate())
4715 AM.Scale = Op.getImm();
4716 Op = MI->getOperand(2);
4717 if (Op.isImmediate())
4718 AM.IndexReg = Op.getImm();
4719 Op = MI->getOperand(3);
4720 if (Op.isGlobalAddress()) {
4721 AM.GV = Op.getGlobal();
4723 AM.Disp = Op.getImm();
4725 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4726 .addReg(MI->getOperand(4).getReg());
4728 // Reload the original control word now.
4729 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4731 delete MI; // The pseudo instruction is gone now.
4737 //===----------------------------------------------------------------------===//
4738 // X86 Optimization Hooks
4739 //===----------------------------------------------------------------------===//
4741 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4743 uint64_t &KnownZero,
4745 const SelectionDAG &DAG,
4746 unsigned Depth) const {
4747 unsigned Opc = Op.getOpcode();
4748 assert((Opc >= ISD::BUILTIN_OP_END ||
4749 Opc == ISD::INTRINSIC_WO_CHAIN ||
4750 Opc == ISD::INTRINSIC_W_CHAIN ||
4751 Opc == ISD::INTRINSIC_VOID) &&
4752 "Should use MaskedValueIsZero if you don't know whether Op"
4753 " is a target node!");
4755 KnownZero = KnownOne = 0; // Don't know anything.
4759 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4764 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4765 /// element of the result of the vector shuffle.
4766 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4767 MVT::ValueType VT = N->getValueType(0);
4768 SDOperand PermMask = N->getOperand(2);
4769 unsigned NumElems = PermMask.getNumOperands();
4770 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4772 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4774 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
4775 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4776 SDOperand Idx = PermMask.getOperand(i);
4777 if (Idx.getOpcode() == ISD::UNDEF)
4778 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
4779 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4784 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4785 /// node is a GlobalAddress + an offset.
4786 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4787 unsigned Opc = N->getOpcode();
4788 if (Opc == X86ISD::Wrapper) {
4789 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4790 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4793 } else if (Opc == ISD::ADD) {
4794 SDOperand N1 = N->getOperand(0);
4795 SDOperand N2 = N->getOperand(1);
4796 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4797 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4799 Offset += V->getSignExtended();
4802 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4803 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4805 Offset += V->getSignExtended();
4813 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4815 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4816 MachineFrameInfo *MFI) {
4817 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4820 SDOperand Loc = N->getOperand(1);
4821 SDOperand BaseLoc = Base->getOperand(1);
4822 if (Loc.getOpcode() == ISD::FrameIndex) {
4823 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4825 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
4826 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4827 int FS = MFI->getObjectSize(FI);
4828 int BFS = MFI->getObjectSize(BFI);
4829 if (FS != BFS || FS != Size) return false;
4830 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4832 GlobalValue *GV1 = NULL;
4833 GlobalValue *GV2 = NULL;
4834 int64_t Offset1 = 0;
4835 int64_t Offset2 = 0;
4836 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4837 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4838 if (isGA1 && isGA2 && GV1 == GV2)
4839 return Offset1 == (Offset2 + Dist*Size);
4845 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4846 const X86Subtarget *Subtarget) {
4849 if (isGAPlusOffset(Base, GV, Offset))
4850 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4852 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4853 int BFI = cast<FrameIndexSDNode>(Base)->getIndex();
4855 // Fixed objects do not specify alignment, however the offsets are known.
4856 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4857 (MFI->getObjectOffset(BFI) % 16) == 0);
4859 return MFI->getObjectAlignment(BFI) >= 16;
4865 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4866 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4867 /// if the load addresses are consecutive, non-overlapping, and in the right
4869 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4870 const X86Subtarget *Subtarget) {
4871 MachineFunction &MF = DAG.getMachineFunction();
4872 MachineFrameInfo *MFI = MF.getFrameInfo();
4873 MVT::ValueType VT = N->getValueType(0);
4874 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4875 SDOperand PermMask = N->getOperand(2);
4876 int NumElems = (int)PermMask.getNumOperands();
4877 SDNode *Base = NULL;
4878 for (int i = 0; i < NumElems; ++i) {
4879 SDOperand Idx = PermMask.getOperand(i);
4880 if (Idx.getOpcode() == ISD::UNDEF) {
4881 if (!Base) return SDOperand();
4884 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4885 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4889 else if (!isConsecutiveLoad(Arg.Val, Base,
4890 i, MVT::getSizeInBits(EVT)/8,MFI))
4895 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4896 LoadSDNode *LD = cast<LoadSDNode>(Base);
4898 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4899 LD->getSrcValueOffset(), LD->isVolatile());
4901 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4902 LD->getSrcValueOffset(), LD->isVolatile(),
4903 LD->getAlignment());
4907 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4908 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4909 const X86Subtarget *Subtarget) {
4910 SDOperand Cond = N->getOperand(0);
4912 // If we have SSE[12] support, try to form min/max nodes.
4913 if (Subtarget->hasSSE2() &&
4914 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4915 if (Cond.getOpcode() == ISD::SETCC) {
4916 // Get the LHS/RHS of the select.
4917 SDOperand LHS = N->getOperand(1);
4918 SDOperand RHS = N->getOperand(2);
4919 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4921 unsigned Opcode = 0;
4922 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4925 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4928 if (!UnsafeFPMath) break;
4930 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4932 Opcode = X86ISD::FMIN;
4935 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4938 if (!UnsafeFPMath) break;
4940 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4942 Opcode = X86ISD::FMAX;
4945 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4948 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4951 if (!UnsafeFPMath) break;
4953 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4955 Opcode = X86ISD::FMIN;
4958 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4961 if (!UnsafeFPMath) break;
4963 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4965 Opcode = X86ISD::FMAX;
4971 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4980 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4981 DAGCombinerInfo &DCI) const {
4982 SelectionDAG &DAG = DCI.DAG;
4983 switch (N->getOpcode()) {
4985 case ISD::VECTOR_SHUFFLE:
4986 return PerformShuffleCombine(N, DAG, Subtarget);
4988 return PerformSELECTCombine(N, DAG, Subtarget);
4994 //===----------------------------------------------------------------------===//
4995 // X86 Inline Assembly Support
4996 //===----------------------------------------------------------------------===//
4998 /// getConstraintType - Given a constraint letter, return the type of
4999 /// constraint it is for this target.
5000 X86TargetLowering::ConstraintType
5001 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
5002 if (Constraint.size() == 1) {
5003 switch (Constraint[0]) {
5012 return C_RegisterClass;
5017 return TargetLowering::getConstraintType(Constraint);
5020 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5021 /// vector. If it is invalid, don't add anything to Ops.
5022 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
5024 std::vector<SDOperand>&Ops,
5025 SelectionDAG &DAG) {
5026 SDOperand Result(0, 0);
5028 switch (Constraint) {
5031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5032 if (C->getValue() <= 31) {
5033 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5039 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5040 if (C->getValue() <= 255) {
5041 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5047 // Literal immediates are always ok.
5048 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
5049 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
5053 // If we are in non-pic codegen mode, we allow the address of a global (with
5054 // an optional displacement) to be used with 'i'.
5055 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
5058 // Match either (GA) or (GA+C)
5060 Offset = GA->getOffset();
5061 } else if (Op.getOpcode() == ISD::ADD) {
5062 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5063 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5065 Offset = GA->getOffset()+C->getValue();
5067 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5068 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5070 Offset = GA->getOffset()+C->getValue();
5077 // If addressing this global requires a load (e.g. in PIC mode), we can't
5079 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
5083 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5089 // Otherwise, not valid for this mode.
5095 Ops.push_back(Result);
5098 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5101 std::vector<unsigned> X86TargetLowering::
5102 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5103 MVT::ValueType VT) const {
5104 if (Constraint.size() == 1) {
5105 // FIXME: not handling fp-stack yet!
5106 switch (Constraint[0]) { // GCC X86 Constraint Letters
5107 default: break; // Unknown constraint letter
5108 case 'A': // EAX/EDX
5109 if (VT == MVT::i32 || VT == MVT::i64)
5110 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5112 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5115 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5116 else if (VT == MVT::i16)
5117 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5118 else if (VT == MVT::i8)
5119 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5124 return std::vector<unsigned>();
5127 std::pair<unsigned, const TargetRegisterClass*>
5128 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5129 MVT::ValueType VT) const {
5130 // First, see if this is a constraint that directly corresponds to an LLVM
5132 if (Constraint.size() == 1) {
5133 // GCC Constraint Letters
5134 switch (Constraint[0]) {
5136 case 'r': // GENERAL_REGS
5137 case 'R': // LEGACY_REGS
5138 case 'l': // INDEX_REGS
5139 if (VT == MVT::i64 && Subtarget->is64Bit())
5140 return std::make_pair(0U, X86::GR64RegisterClass);
5142 return std::make_pair(0U, X86::GR32RegisterClass);
5143 else if (VT == MVT::i16)
5144 return std::make_pair(0U, X86::GR16RegisterClass);
5145 else if (VT == MVT::i8)
5146 return std::make_pair(0U, X86::GR8RegisterClass);
5148 case 'y': // MMX_REGS if MMX allowed.
5149 if (!Subtarget->hasMMX()) break;
5150 return std::make_pair(0U, X86::VR64RegisterClass);
5152 case 'Y': // SSE_REGS if SSE2 allowed
5153 if (!Subtarget->hasSSE2()) break;
5155 case 'x': // SSE_REGS if SSE1 allowed
5156 if (!Subtarget->hasSSE1()) break;
5160 // Scalar SSE types.
5163 return std::make_pair(0U, X86::FR32RegisterClass);
5166 return std::make_pair(0U, X86::FR64RegisterClass);
5174 return std::make_pair(0U, X86::VR128RegisterClass);
5180 // Use the default implementation in TargetLowering to convert the register
5181 // constraint into a member of a register class.
5182 std::pair<unsigned, const TargetRegisterClass*> Res;
5183 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5185 // Not found as a standard register?
5186 if (Res.second == 0) {
5187 // GCC calls "st(0)" just plain "st".
5188 if (StringsEqualNoCase("{st}", Constraint)) {
5189 Res.first = X86::ST0;
5190 Res.second = X86::RSTRegisterClass;
5196 // Otherwise, check to see if this is a register class of the wrong value
5197 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5198 // turn into {ax},{dx}.
5199 if (Res.second->hasType(VT))
5200 return Res; // Correct type already, nothing to do.
5202 // All of the single-register GCC register classes map their values onto
5203 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5204 // really want an 8-bit or 32-bit register, map to the appropriate register
5205 // class and return the appropriate register.
5206 if (Res.second != X86::GR16RegisterClass)
5209 if (VT == MVT::i8) {
5210 unsigned DestReg = 0;
5211 switch (Res.first) {
5213 case X86::AX: DestReg = X86::AL; break;
5214 case X86::DX: DestReg = X86::DL; break;
5215 case X86::CX: DestReg = X86::CL; break;
5216 case X86::BX: DestReg = X86::BL; break;
5219 Res.first = DestReg;
5220 Res.second = Res.second = X86::GR8RegisterClass;
5222 } else if (VT == MVT::i32) {
5223 unsigned DestReg = 0;
5224 switch (Res.first) {
5226 case X86::AX: DestReg = X86::EAX; break;
5227 case X86::DX: DestReg = X86::EDX; break;
5228 case X86::CX: DestReg = X86::ECX; break;
5229 case X86::BX: DestReg = X86::EBX; break;
5230 case X86::SI: DestReg = X86::ESI; break;
5231 case X86::DI: DestReg = X86::EDI; break;
5232 case X86::BP: DestReg = X86::EBP; break;
5233 case X86::SP: DestReg = X86::ESP; break;
5236 Res.first = DestReg;
5237 Res.second = Res.second = X86::GR32RegisterClass;
5239 } else if (VT == MVT::i64) {
5240 unsigned DestReg = 0;
5241 switch (Res.first) {
5243 case X86::AX: DestReg = X86::RAX; break;
5244 case X86::DX: DestReg = X86::RDX; break;
5245 case X86::CX: DestReg = X86::RCX; break;
5246 case X86::BX: DestReg = X86::RBX; break;
5247 case X86::SI: DestReg = X86::RSI; break;
5248 case X86::DI: DestReg = X86::RDI; break;
5249 case X86::BP: DestReg = X86::RBP; break;
5250 case X86::SP: DestReg = X86::RSP; break;
5253 Res.first = DestReg;
5254 Res.second = Res.second = X86::GR64RegisterClass;