1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/VectorExtras.h"
27 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/StringExtras.h"
37 #include "llvm/ParameterAttributes.h"
40 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
41 : TargetLowering(TM) {
42 Subtarget = &TM.getSubtarget<X86Subtarget>();
43 X86ScalarSSE = Subtarget->hasSSE2();
44 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
46 RegInfo = TM.getRegisterInfo();
48 // Set up the TargetLowering object.
50 // X86 is weird, it always uses i8 for shift amounts and setcc results.
51 setShiftAmountType(MVT::i8);
52 setSetCCResultType(MVT::i8);
53 setSetCCResultContents(ZeroOrOneSetCCResult);
54 setSchedulingPreference(SchedulingForRegPressure);
55 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
56 setStackPointerRegisterToSaveRestore(X86StackPtr);
58 if (Subtarget->isTargetDarwin()) {
59 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
60 setUseUnderscoreSetJmp(false);
61 setUseUnderscoreLongJmp(false);
62 } else if (Subtarget->isTargetMingw()) {
63 // MS runtime is weird: it exports _setjmp, but longjmp!
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(false);
67 setUseUnderscoreSetJmp(true);
68 setUseUnderscoreLongJmp(true);
71 // Set up the register classes.
72 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
73 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
74 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
75 if (Subtarget->is64Bit())
76 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
78 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
80 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
82 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
83 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
84 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
86 if (Subtarget->is64Bit()) {
87 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
88 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
91 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
92 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
94 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
97 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
99 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
100 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
101 // SSE has no i16 to fp conversion, only i32
103 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
105 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
106 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
109 if (!Subtarget->is64Bit()) {
110 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
111 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
112 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
115 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
117 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
118 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
123 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
124 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
127 // Handle FP_TO_UINT by promoting the destination to a larger signed
129 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
130 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
131 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
133 if (Subtarget->is64Bit()) {
134 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
135 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
137 if (X86ScalarSSE && !Subtarget->hasSSE3())
138 // Expand FP_TO_UINT into a select.
139 // FIXME: We would like to use a Custom expander here eventually to do
140 // the optimal thing for SSE vs. the default expansion in the legalizer.
141 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
143 // With SSE3 we can use fisttpll to convert to a signed i64.
144 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
147 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
149 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
150 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
153 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
154 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
155 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
156 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
157 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
158 if (Subtarget->is64Bit())
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
163 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
164 setOperationAction(ISD::FREM , MVT::f64 , Expand);
166 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
167 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
168 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
169 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
170 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
171 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
172 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
173 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
174 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
175 if (Subtarget->is64Bit()) {
176 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
177 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
178 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
181 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
182 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
184 // These should be promoted to a larger select which is supported.
185 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
186 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
187 // X86 wants to expand cmov itself.
188 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
189 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
190 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
191 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
192 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
193 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
194 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
195 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
196 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
197 if (Subtarget->is64Bit()) {
198 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
199 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
201 // X86 ret instruction may pop stack.
202 setOperationAction(ISD::RET , MVT::Other, Custom);
203 if (!Subtarget->is64Bit())
204 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
207 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
208 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
209 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
210 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
211 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
212 if (Subtarget->is64Bit()) {
213 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
214 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
215 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
216 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
218 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
219 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
220 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
221 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
222 // X86 wants to expand memset / memcpy itself.
223 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
224 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
226 // We don't have line number support yet.
227 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
228 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
229 // FIXME - use subtarget debug flags
230 if (!Subtarget->isTargetDarwin() &&
231 !Subtarget->isTargetELF() &&
232 !Subtarget->isTargetCygMing())
233 setOperationAction(ISD::LABEL, MVT::Other, Expand);
235 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
236 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
237 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
238 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
239 if (Subtarget->is64Bit()) {
241 setExceptionPointerRegister(X86::RAX);
242 setExceptionSelectorRegister(X86::RDX);
244 setExceptionPointerRegister(X86::EAX);
245 setExceptionSelectorRegister(X86::EDX);
247 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
249 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
251 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
252 setOperationAction(ISD::VASTART , MVT::Other, Custom);
253 setOperationAction(ISD::VAARG , MVT::Other, Expand);
254 setOperationAction(ISD::VAEND , MVT::Other, Expand);
255 if (Subtarget->is64Bit())
256 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
258 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
260 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
261 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
262 if (Subtarget->is64Bit())
263 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
264 if (Subtarget->isTargetCygMing())
265 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
267 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
270 // Set up the FP register classes.
271 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
272 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
274 // Use ANDPD to simulate FABS.
275 setOperationAction(ISD::FABS , MVT::f64, Custom);
276 setOperationAction(ISD::FABS , MVT::f32, Custom);
278 // Use XORP to simulate FNEG.
279 setOperationAction(ISD::FNEG , MVT::f64, Custom);
280 setOperationAction(ISD::FNEG , MVT::f32, Custom);
282 // Use ANDPD and ORPD to simulate FCOPYSIGN.
283 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
284 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
286 // We don't support sin/cos/fmod
287 setOperationAction(ISD::FSIN , MVT::f64, Expand);
288 setOperationAction(ISD::FCOS , MVT::f64, Expand);
289 setOperationAction(ISD::FREM , MVT::f64, Expand);
290 setOperationAction(ISD::FSIN , MVT::f32, Expand);
291 setOperationAction(ISD::FCOS , MVT::f32, Expand);
292 setOperationAction(ISD::FREM , MVT::f32, Expand);
294 // Expand FP immediates into loads from the stack, except for the special
296 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
297 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
298 addLegalFPImmediate(APFloat(+0.0)); // xorps / xorpd
300 // Conversions to long double (in X87) go through memory.
301 setConvertAction(MVT::f32, MVT::f80, Expand);
302 setConvertAction(MVT::f64, MVT::f80, Expand);
304 // Conversions from long double (in X87) go through memory.
305 setConvertAction(MVT::f80, MVT::f32, Expand);
306 setConvertAction(MVT::f80, MVT::f64, Expand);
308 // Set up the FP register classes.
309 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
310 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
312 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
313 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
314 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
315 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
317 // Floating truncations need to go through memory.
318 setConvertAction(MVT::f80, MVT::f32, Expand);
319 setConvertAction(MVT::f64, MVT::f32, Expand);
320 setConvertAction(MVT::f80, MVT::f64, Expand);
323 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
324 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
327 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
328 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
329 addLegalFPImmediate(APFloat(+0.0)); // FLD0
330 addLegalFPImmediate(APFloat(+1.0)); // FLD1
331 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
332 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
335 // Long double always uses X87.
336 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
338 // First set operation action for all vector types to expand. Then we
339 // will selectively turn on ones that can be effectively codegen'd.
340 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
341 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
342 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
343 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
344 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
345 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
346 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
347 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
348 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
349 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
350 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
351 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
352 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
353 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
354 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
355 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
356 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
357 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
358 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
359 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
360 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
361 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
362 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
363 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
364 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
367 if (Subtarget->hasMMX()) {
368 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
369 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
370 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
371 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
373 // FIXME: add MMX packed arithmetics
375 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
376 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
377 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
378 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
380 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
381 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
382 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
384 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
385 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
387 setOperationAction(ISD::AND, MVT::v8i8, Promote);
388 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
389 setOperationAction(ISD::AND, MVT::v4i16, Promote);
390 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
391 setOperationAction(ISD::AND, MVT::v2i32, Promote);
392 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
393 setOperationAction(ISD::AND, MVT::v1i64, Legal);
395 setOperationAction(ISD::OR, MVT::v8i8, Promote);
396 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
397 setOperationAction(ISD::OR, MVT::v4i16, Promote);
398 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
399 setOperationAction(ISD::OR, MVT::v2i32, Promote);
400 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
401 setOperationAction(ISD::OR, MVT::v1i64, Legal);
403 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
404 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
405 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
406 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
407 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
408 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
409 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
411 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
412 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
413 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
414 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
415 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
416 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
417 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
419 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
420 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
421 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
422 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
424 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
425 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
426 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
427 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
429 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
430 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
431 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
432 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
435 if (Subtarget->hasSSE1()) {
436 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
438 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
439 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
440 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
441 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
442 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
443 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
444 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
445 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
446 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
447 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
448 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
451 if (Subtarget->hasSSE2()) {
452 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
453 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
454 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
455 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
456 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
458 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
459 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
460 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
461 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
462 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
463 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
464 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
465 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
466 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
467 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
468 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
469 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
470 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
471 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
472 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
474 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
475 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
476 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
477 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
478 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
479 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
481 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
482 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
483 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
484 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
485 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
487 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
488 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
489 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
490 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
491 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
492 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
494 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
495 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
496 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
497 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
498 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
499 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
500 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
501 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
502 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
503 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
504 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
505 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
508 // Custom lower v2i64 and v2f64 selects.
509 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
510 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
511 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
512 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
515 // We want to custom lower some of our intrinsics.
516 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
518 // We have target-specific dag combine patterns for the following nodes:
519 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
520 setTargetDAGCombine(ISD::SELECT);
522 computeRegisterProperties();
524 // FIXME: These should be based on subtarget info. Plus, the values should
525 // be smaller when we are in optimizing for size mode.
526 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
527 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
528 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
529 allowUnalignedMemoryAccesses = true; // x86 supports it!
533 //===----------------------------------------------------------------------===//
534 // Return Value Calling Convention Implementation
535 //===----------------------------------------------------------------------===//
537 #include "X86GenCallingConv.inc"
539 /// LowerRET - Lower an ISD::RET node.
540 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
541 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
543 SmallVector<CCValAssign, 16> RVLocs;
544 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
545 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
546 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
547 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
550 // If this is the first return lowered for this function, add the regs to the
551 // liveout set for the function.
552 if (DAG.getMachineFunction().liveout_empty()) {
553 for (unsigned i = 0; i != RVLocs.size(); ++i)
554 if (RVLocs[i].isRegLoc())
555 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
558 SDOperand Chain = Op.getOperand(0);
561 // Copy the result values into the output registers.
562 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
563 RVLocs[0].getLocReg() != X86::ST0) {
564 for (unsigned i = 0; i != RVLocs.size(); ++i) {
565 CCValAssign &VA = RVLocs[i];
566 assert(VA.isRegLoc() && "Can only return in registers!");
567 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
569 Flag = Chain.getValue(1);
572 // We need to handle a destination of ST0 specially, because it isn't really
574 SDOperand Value = Op.getOperand(1);
576 // If this is an FP return with ScalarSSE, we need to move the value from
577 // an XMM register onto the fp-stack.
581 // If this is a load into a scalarsse value, don't store the loaded value
582 // back to the stack, only to reload it: just replace the scalar-sse load.
583 if (ISD::isNON_EXTLoad(Value.Val) &&
584 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
585 Chain = Value.getOperand(0);
586 MemLoc = Value.getOperand(1);
588 // Spill the value to memory and reload it into top of stack.
589 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
590 MachineFunction &MF = DAG.getMachineFunction();
591 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
592 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
593 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
595 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other);
596 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
597 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
598 Chain = Value.getValue(1);
601 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
602 SDOperand Ops[] = { Chain, Value };
603 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
604 Flag = Chain.getValue(1);
607 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
609 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
611 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
615 /// LowerCallResult - Lower the result values of an ISD::CALL into the
616 /// appropriate copies out of appropriate physical registers. This assumes that
617 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
618 /// being lowered. The returns a SDNode with the same number of values as the
620 SDNode *X86TargetLowering::
621 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
622 unsigned CallingConv, SelectionDAG &DAG) {
624 // Assign locations to each value returned by this call.
625 SmallVector<CCValAssign, 16> RVLocs;
626 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
627 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
628 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
631 SmallVector<SDOperand, 8> ResultVals;
633 // Copy all of the result registers out of their specified physreg.
634 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
635 for (unsigned i = 0; i != RVLocs.size(); ++i) {
636 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
637 RVLocs[i].getValVT(), InFlag).getValue(1);
638 InFlag = Chain.getValue(2);
639 ResultVals.push_back(Chain.getValue(0));
642 // Copies from the FP stack are special, as ST0 isn't a valid register
643 // before the fp stackifier runs.
645 // Copy ST0 into an RFP register with FP_GET_RESULT.
646 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other, MVT::Flag);
647 SDOperand GROps[] = { Chain, InFlag };
648 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
649 Chain = RetVal.getValue(1);
650 InFlag = RetVal.getValue(2);
652 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
655 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
656 // shouldn't be necessary except that RFP cannot be live across
657 // multiple blocks. When stackifier is fixed, they can be uncoupled.
658 MachineFunction &MF = DAG.getMachineFunction();
659 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
660 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
662 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag
664 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
665 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0);
666 Chain = RetVal.getValue(1);
668 ResultVals.push_back(RetVal);
671 // Merge everything together with a MERGE_VALUES node.
672 ResultVals.push_back(Chain);
673 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
674 &ResultVals[0], ResultVals.size()).Val;
678 //===----------------------------------------------------------------------===//
679 // C & StdCall Calling Convention implementation
680 //===----------------------------------------------------------------------===//
681 // StdCall calling convention seems to be standard for many Windows' API
682 // routines and around. It differs from C calling convention just a little:
683 // callee should clean up the stack, not caller. Symbols should be also
684 // decorated in some fancy way :) It doesn't support any vector arguments.
686 /// AddLiveIn - This helper function adds the specified physical register to the
687 /// MachineFunction as a live in value. It also creates a corresponding virtual
689 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
690 const TargetRegisterClass *RC) {
691 assert(RC->contains(PReg) && "Not the correct regclass!");
692 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
693 MF.addLiveIn(PReg, VReg);
697 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
699 unsigned NumArgs = Op.Val->getNumValues() - 1;
700 MachineFunction &MF = DAG.getMachineFunction();
701 MachineFrameInfo *MFI = MF.getFrameInfo();
702 SDOperand Root = Op.getOperand(0);
703 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
705 // Assign locations to all of the incoming arguments.
706 SmallVector<CCValAssign, 16> ArgLocs;
707 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
708 getTargetMachine(), ArgLocs);
709 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
711 SmallVector<SDOperand, 8> ArgValues;
712 unsigned LastVal = ~0U;
713 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
714 CCValAssign &VA = ArgLocs[i];
715 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
717 assert(VA.getValNo() != LastVal &&
718 "Don't support value assigned to multiple locs yet");
719 LastVal = VA.getValNo();
722 MVT::ValueType RegVT = VA.getLocVT();
723 TargetRegisterClass *RC;
724 if (RegVT == MVT::i32)
725 RC = X86::GR32RegisterClass;
727 assert(MVT::isVector(RegVT));
728 RC = X86::VR128RegisterClass;
731 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
732 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
734 // If this is an 8 or 16-bit value, it is really passed promoted to 32
735 // bits. Insert an assert[sz]ext to capture this, then truncate to the
737 if (VA.getLocInfo() == CCValAssign::SExt)
738 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
739 DAG.getValueType(VA.getValVT()));
740 else if (VA.getLocInfo() == CCValAssign::ZExt)
741 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
742 DAG.getValueType(VA.getValVT()));
744 if (VA.getLocInfo() != CCValAssign::Full)
745 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
747 ArgValues.push_back(ArgValue);
749 assert(VA.isMemLoc());
751 // Create the nodes corresponding to a load from this parameter slot.
752 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
753 VA.getLocMemOffset());
754 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
755 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
759 unsigned StackSize = CCInfo.getNextStackOffset();
761 ArgValues.push_back(Root);
763 // If the function takes variable number of arguments, make a frame index for
764 // the start of the first vararg value... for expansion of llvm.va_start.
766 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
768 if (isStdCall && !isVarArg) {
769 BytesToPopOnReturn = StackSize; // Callee pops everything..
770 BytesCallerReserves = 0;
772 BytesToPopOnReturn = 0; // Callee pops nothing.
774 // If this is an sret function, the return should pop the hidden pointer.
776 (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
777 ISD::ParamFlags::StructReturn))
778 BytesToPopOnReturn = 4;
780 BytesCallerReserves = StackSize;
783 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
785 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
786 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
788 // Return the new list of results.
789 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
790 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
793 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
795 SDOperand Chain = Op.getOperand(0);
796 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
797 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
798 SDOperand Callee = Op.getOperand(4);
799 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
801 // Analyze operands of the call, assigning locations to each operand.
802 SmallVector<CCValAssign, 16> ArgLocs;
803 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
804 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
806 // Get a count of how many bytes are to be pushed on the stack.
807 unsigned NumBytes = CCInfo.getNextStackOffset();
809 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
811 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
812 SmallVector<SDOperand, 8> MemOpChains;
816 // Walk the register/memloc assignments, inserting copies/loads.
817 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
818 CCValAssign &VA = ArgLocs[i];
819 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
821 // Promote the value if needed.
822 switch (VA.getLocInfo()) {
823 default: assert(0 && "Unknown loc info!");
824 case CCValAssign::Full: break;
825 case CCValAssign::SExt:
826 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
828 case CCValAssign::ZExt:
829 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
831 case CCValAssign::AExt:
832 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
837 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
839 assert(VA.isMemLoc());
840 if (StackPtr.Val == 0)
841 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
842 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
843 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
844 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
848 // If the first argument is an sret pointer, remember it.
849 bool isSRet = NumOps &&
850 (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
851 ISD::ParamFlags::StructReturn);
853 if (!MemOpChains.empty())
854 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
855 &MemOpChains[0], MemOpChains.size());
857 // Build a sequence of copy-to-reg nodes chained together with token chain
858 // and flag operands which copy the outgoing args into registers.
860 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
861 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
863 InFlag = Chain.getValue(1);
866 // ELF / PIC requires GOT in the EBX register before function calls via PLT
868 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
869 Subtarget->isPICStyleGOT()) {
870 Chain = DAG.getCopyToReg(Chain, X86::EBX,
871 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
873 InFlag = Chain.getValue(1);
876 // If the callee is a GlobalAddress node (quite common, every direct call is)
877 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
878 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
879 // We should use extra load for direct calls to dllimported functions in
881 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
882 getTargetMachine(), true))
883 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
884 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
885 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
887 // Returns a chain & a flag for retval copy to use.
888 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
889 SmallVector<SDOperand, 8> Ops;
890 Ops.push_back(Chain);
891 Ops.push_back(Callee);
893 // Add argument registers to the end of the list so that they are known live
895 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
896 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
897 RegsToPass[i].second.getValueType()));
899 // Add an implicit use GOT pointer in EBX.
900 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
901 Subtarget->isPICStyleGOT())
902 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
905 Ops.push_back(InFlag);
907 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
908 NodeTys, &Ops[0], Ops.size());
909 InFlag = Chain.getValue(1);
911 // Create the CALLSEQ_END node.
912 unsigned NumBytesForCalleeToPush = 0;
914 if (CC == CallingConv::X86_StdCall) {
916 NumBytesForCalleeToPush = isSRet ? 4 : 0;
918 NumBytesForCalleeToPush = NumBytes;
920 // If this is is a call to a struct-return function, the callee
921 // pops the hidden struct pointer, so we have to push it back.
922 // This is common for Darwin/X86, Linux & Mingw32 targets.
923 NumBytesForCalleeToPush = isSRet ? 4 : 0;
926 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
928 Ops.push_back(Chain);
929 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
930 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
931 Ops.push_back(InFlag);
932 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
933 InFlag = Chain.getValue(1);
935 // Handle result values, copying them out of physregs into vregs that we
937 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
941 //===----------------------------------------------------------------------===//
942 // FastCall Calling Convention implementation
943 //===----------------------------------------------------------------------===//
945 // The X86 'fastcall' calling convention passes up to two integer arguments in
946 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
947 // and requires that the callee pop its arguments off the stack (allowing proper
948 // tail calls), and has the same return value conventions as C calling convs.
950 // This calling convention always arranges for the callee pop value to be 8n+4
951 // bytes, which is needed for tail recursion elimination and stack alignment
954 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
955 MachineFunction &MF = DAG.getMachineFunction();
956 MachineFrameInfo *MFI = MF.getFrameInfo();
957 SDOperand Root = Op.getOperand(0);
958 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
960 // Assign locations to all of the incoming arguments.
961 SmallVector<CCValAssign, 16> ArgLocs;
962 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
963 getTargetMachine(), ArgLocs);
964 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
966 SmallVector<SDOperand, 8> ArgValues;
967 unsigned LastVal = ~0U;
968 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
969 CCValAssign &VA = ArgLocs[i];
970 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
972 assert(VA.getValNo() != LastVal &&
973 "Don't support value assigned to multiple locs yet");
974 LastVal = VA.getValNo();
977 MVT::ValueType RegVT = VA.getLocVT();
978 TargetRegisterClass *RC;
979 if (RegVT == MVT::i32)
980 RC = X86::GR32RegisterClass;
982 assert(MVT::isVector(RegVT));
983 RC = X86::VR128RegisterClass;
986 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
987 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
989 // If this is an 8 or 16-bit value, it is really passed promoted to 32
990 // bits. Insert an assert[sz]ext to capture this, then truncate to the
992 if (VA.getLocInfo() == CCValAssign::SExt)
993 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
994 DAG.getValueType(VA.getValVT()));
995 else if (VA.getLocInfo() == CCValAssign::ZExt)
996 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
997 DAG.getValueType(VA.getValVT()));
999 if (VA.getLocInfo() != CCValAssign::Full)
1000 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1002 ArgValues.push_back(ArgValue);
1004 assert(VA.isMemLoc());
1006 // Create the nodes corresponding to a load from this parameter slot.
1007 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1008 VA.getLocMemOffset());
1009 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1010 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1014 ArgValues.push_back(Root);
1016 unsigned StackSize = CCInfo.getNextStackOffset();
1018 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1019 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1020 // arguments and the arguments after the retaddr has been pushed are aligned.
1021 if ((StackSize & 7) == 0)
1025 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1026 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
1027 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
1028 BytesCallerReserves = 0;
1030 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1031 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1033 // Return the new list of results.
1034 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1035 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1039 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1040 const SDOperand &StackPtr,
1041 const CCValAssign &VA,
1044 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1045 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1046 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1047 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1048 if (Flags & ISD::ParamFlags::ByVal) {
1049 unsigned Align = 1 << ((Flags & ISD::ParamFlags::ByValAlign) >>
1050 ISD::ParamFlags::ByValAlignOffs);
1052 assert (Align >= 8);
1053 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1054 ISD::ParamFlags::ByValSizeOffs;
1056 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1057 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1059 return DAG.getNode(ISD::MEMCPY, MVT::Other, Chain, PtrOff, Arg, SizeNode,
1062 return DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1066 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
1068 SDOperand Chain = Op.getOperand(0);
1069 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1070 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1071 SDOperand Callee = Op.getOperand(4);
1073 // Analyze operands of the call, assigning locations to each operand.
1074 SmallVector<CCValAssign, 16> ArgLocs;
1075 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1076 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
1078 // Get a count of how many bytes are to be pushed on the stack.
1079 unsigned NumBytes = CCInfo.getNextStackOffset();
1081 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1082 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1083 // arguments and the arguments after the retaddr has been pushed are aligned.
1084 if ((NumBytes & 7) == 0)
1088 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1090 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1091 SmallVector<SDOperand, 8> MemOpChains;
1095 // Walk the register/memloc assignments, inserting copies/loads.
1096 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1097 CCValAssign &VA = ArgLocs[i];
1098 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1100 // Promote the value if needed.
1101 switch (VA.getLocInfo()) {
1102 default: assert(0 && "Unknown loc info!");
1103 case CCValAssign::Full: break;
1104 case CCValAssign::SExt:
1105 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1107 case CCValAssign::ZExt:
1108 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1110 case CCValAssign::AExt:
1111 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1115 if (VA.isRegLoc()) {
1116 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1118 assert(VA.isMemLoc());
1119 if (StackPtr.Val == 0)
1120 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1121 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1122 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1123 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1127 if (!MemOpChains.empty())
1128 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1129 &MemOpChains[0], MemOpChains.size());
1131 // Build a sequence of copy-to-reg nodes chained together with token chain
1132 // and flag operands which copy the outgoing args into registers.
1134 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1135 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1137 InFlag = Chain.getValue(1);
1140 // If the callee is a GlobalAddress node (quite common, every direct call is)
1141 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1142 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1143 // We should use extra load for direct calls to dllimported functions in
1145 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1146 getTargetMachine(), true))
1147 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1148 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1149 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1151 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1153 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1154 Subtarget->isPICStyleGOT()) {
1155 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1156 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1158 InFlag = Chain.getValue(1);
1161 // Returns a chain & a flag for retval copy to use.
1162 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1163 SmallVector<SDOperand, 8> Ops;
1164 Ops.push_back(Chain);
1165 Ops.push_back(Callee);
1167 // Add argument registers to the end of the list so that they are known live
1169 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1170 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1171 RegsToPass[i].second.getValueType()));
1173 // Add an implicit use GOT pointer in EBX.
1174 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1175 Subtarget->isPICStyleGOT())
1176 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1179 Ops.push_back(InFlag);
1181 // FIXME: Do not generate X86ISD::TAILCALL for now.
1182 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1183 NodeTys, &Ops[0], Ops.size());
1184 InFlag = Chain.getValue(1);
1186 // Returns a flag for retval copy to use.
1187 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1189 Ops.push_back(Chain);
1190 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1191 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1192 Ops.push_back(InFlag);
1193 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1194 InFlag = Chain.getValue(1);
1196 // Handle result values, copying them out of physregs into vregs that we
1198 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1202 //===----------------------------------------------------------------------===//
1203 // X86-64 C Calling Convention implementation
1204 //===----------------------------------------------------------------------===//
1207 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1208 MachineFunction &MF = DAG.getMachineFunction();
1209 MachineFrameInfo *MFI = MF.getFrameInfo();
1210 SDOperand Root = Op.getOperand(0);
1211 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1213 static const unsigned GPR64ArgRegs[] = {
1214 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1216 static const unsigned XMMArgRegs[] = {
1217 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1218 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1222 // Assign locations to all of the incoming arguments.
1223 SmallVector<CCValAssign, 16> ArgLocs;
1224 CCState CCInfo(MF.getFunction()->getCallingConv(), isVarArg,
1225 getTargetMachine(), ArgLocs);
1226 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
1228 SmallVector<SDOperand, 8> ArgValues;
1229 unsigned LastVal = ~0U;
1230 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1231 CCValAssign &VA = ArgLocs[i];
1232 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1234 assert(VA.getValNo() != LastVal &&
1235 "Don't support value assigned to multiple locs yet");
1236 LastVal = VA.getValNo();
1238 if (VA.isRegLoc()) {
1239 MVT::ValueType RegVT = VA.getLocVT();
1240 TargetRegisterClass *RC;
1241 if (RegVT == MVT::i32)
1242 RC = X86::GR32RegisterClass;
1243 else if (RegVT == MVT::i64)
1244 RC = X86::GR64RegisterClass;
1245 else if (RegVT == MVT::f32)
1246 RC = X86::FR32RegisterClass;
1247 else if (RegVT == MVT::f64)
1248 RC = X86::FR64RegisterClass;
1250 assert(MVT::isVector(RegVT));
1251 if (MVT::getSizeInBits(RegVT) == 64) {
1252 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1255 RC = X86::VR128RegisterClass;
1258 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1259 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1261 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1262 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1264 if (VA.getLocInfo() == CCValAssign::SExt)
1265 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1266 DAG.getValueType(VA.getValVT()));
1267 else if (VA.getLocInfo() == CCValAssign::ZExt)
1268 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1269 DAG.getValueType(VA.getValVT()));
1271 if (VA.getLocInfo() != CCValAssign::Full)
1272 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1274 // Handle MMX values passed in GPRs.
1275 if (RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1276 MVT::getSizeInBits(RegVT) == 64)
1277 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1279 ArgValues.push_back(ArgValue);
1281 assert(VA.isMemLoc());
1283 // Create the nodes corresponding to a load from this parameter slot.
1284 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1285 VA.getLocMemOffset());
1286 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1288 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
1289 if (Flags & ISD::ParamFlags::ByVal)
1290 ArgValues.push_back(FIN);
1292 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1296 unsigned StackSize = CCInfo.getNextStackOffset();
1298 // If the function takes variable number of arguments, make a frame index for
1299 // the start of the first vararg value... for expansion of llvm.va_start.
1301 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1302 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1304 // For X86-64, if there are vararg parameters that are passed via
1305 // registers, then we must store them to their spots on the stack so they
1306 // may be loaded by deferencing the result of va_next.
1307 VarArgsGPOffset = NumIntRegs * 8;
1308 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1309 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1310 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1312 // Store the integer parameter registers.
1313 SmallVector<SDOperand, 8> MemOps;
1314 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1315 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1316 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1317 for (; NumIntRegs != 6; ++NumIntRegs) {
1318 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1319 X86::GR64RegisterClass);
1320 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1321 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1322 MemOps.push_back(Store);
1323 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1324 DAG.getConstant(8, getPointerTy()));
1327 // Now store the XMM (fp + vector) parameter registers.
1328 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1329 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1330 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1331 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1332 X86::VR128RegisterClass);
1333 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1334 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1335 MemOps.push_back(Store);
1336 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1337 DAG.getConstant(16, getPointerTy()));
1339 if (!MemOps.empty())
1340 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1341 &MemOps[0], MemOps.size());
1344 ArgValues.push_back(Root);
1346 BytesToPopOnReturn = 0; // Callee pops nothing.
1347 BytesCallerReserves = StackSize;
1349 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1350 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1352 // Return the new list of results.
1353 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1354 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1358 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1360 SDOperand Chain = Op.getOperand(0);
1361 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1362 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1363 SDOperand Callee = Op.getOperand(4);
1365 // Analyze operands of the call, assigning locations to each operand.
1366 SmallVector<CCValAssign, 16> ArgLocs;
1367 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1368 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_64_C);
1370 // Get a count of how many bytes are to be pushed on the stack.
1371 unsigned NumBytes = CCInfo.getNextStackOffset();
1372 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1374 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1375 SmallVector<SDOperand, 8> MemOpChains;
1379 // Walk the register/memloc assignments, inserting copies/loads.
1380 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1381 CCValAssign &VA = ArgLocs[i];
1382 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1384 // Promote the value if needed.
1385 switch (VA.getLocInfo()) {
1386 default: assert(0 && "Unknown loc info!");
1387 case CCValAssign::Full: break;
1388 case CCValAssign::SExt:
1389 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1391 case CCValAssign::ZExt:
1392 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1394 case CCValAssign::AExt:
1395 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1399 if (VA.isRegLoc()) {
1400 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1402 assert(VA.isMemLoc());
1403 if (StackPtr.Val == 0)
1404 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1406 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1411 if (!MemOpChains.empty())
1412 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1413 &MemOpChains[0], MemOpChains.size());
1415 // Build a sequence of copy-to-reg nodes chained together with token chain
1416 // and flag operands which copy the outgoing args into registers.
1418 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1419 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1421 InFlag = Chain.getValue(1);
1425 // From AMD64 ABI document:
1426 // For calls that may call functions that use varargs or stdargs
1427 // (prototype-less calls or calls to functions containing ellipsis (...) in
1428 // the declaration) %al is used as hidden argument to specify the number
1429 // of SSE registers used. The contents of %al do not need to match exactly
1430 // the number of registers, but must be an ubound on the number of SSE
1431 // registers used and is in the range 0 - 8 inclusive.
1433 // Count the number of XMM registers allocated.
1434 static const unsigned XMMArgRegs[] = {
1435 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1436 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1438 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1440 Chain = DAG.getCopyToReg(Chain, X86::AL,
1441 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1442 InFlag = Chain.getValue(1);
1445 // If the callee is a GlobalAddress node (quite common, every direct call is)
1446 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1447 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1448 // We should use extra load for direct calls to dllimported functions in
1450 if (getTargetMachine().getCodeModel() != CodeModel::Large
1451 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1452 getTargetMachine(), true))
1453 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1454 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1455 if (getTargetMachine().getCodeModel() != CodeModel::Large)
1456 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1458 // Returns a chain & a flag for retval copy to use.
1459 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1460 SmallVector<SDOperand, 8> Ops;
1461 Ops.push_back(Chain);
1462 Ops.push_back(Callee);
1464 // Add argument registers to the end of the list so that they are known live
1466 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1467 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1468 RegsToPass[i].second.getValueType()));
1471 Ops.push_back(InFlag);
1473 // FIXME: Do not generate X86ISD::TAILCALL for now.
1474 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1475 NodeTys, &Ops[0], Ops.size());
1476 InFlag = Chain.getValue(1);
1478 // Returns a flag for retval copy to use.
1479 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1481 Ops.push_back(Chain);
1482 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1483 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1484 Ops.push_back(InFlag);
1485 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1486 InFlag = Chain.getValue(1);
1488 // Handle result values, copying them out of physregs into vregs that we
1490 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1494 //===----------------------------------------------------------------------===//
1495 // Other Lowering Hooks
1496 //===----------------------------------------------------------------------===//
1499 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1500 MachineFunction &MF = DAG.getMachineFunction();
1501 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1502 int ReturnAddrIndex = FuncInfo->getRAIndex();
1504 if (ReturnAddrIndex == 0) {
1505 // Set up a frame object for the return address.
1506 if (Subtarget->is64Bit())
1507 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1509 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1511 FuncInfo->setRAIndex(ReturnAddrIndex);
1514 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1519 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1520 /// specific condition code. It returns a false if it cannot do a direct
1521 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1523 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1524 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1525 SelectionDAG &DAG) {
1526 X86CC = X86::COND_INVALID;
1528 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1529 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1530 // X > -1 -> X == 0, jump !sign.
1531 RHS = DAG.getConstant(0, RHS.getValueType());
1532 X86CC = X86::COND_NS;
1534 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1535 // X < 0 -> X == 0, jump on sign.
1536 X86CC = X86::COND_S;
1541 switch (SetCCOpcode) {
1543 case ISD::SETEQ: X86CC = X86::COND_E; break;
1544 case ISD::SETGT: X86CC = X86::COND_G; break;
1545 case ISD::SETGE: X86CC = X86::COND_GE; break;
1546 case ISD::SETLT: X86CC = X86::COND_L; break;
1547 case ISD::SETLE: X86CC = X86::COND_LE; break;
1548 case ISD::SETNE: X86CC = X86::COND_NE; break;
1549 case ISD::SETULT: X86CC = X86::COND_B; break;
1550 case ISD::SETUGT: X86CC = X86::COND_A; break;
1551 case ISD::SETULE: X86CC = X86::COND_BE; break;
1552 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1555 // On a floating point condition, the flags are set as follows:
1557 // 0 | 0 | 0 | X > Y
1558 // 0 | 0 | 1 | X < Y
1559 // 1 | 0 | 0 | X == Y
1560 // 1 | 1 | 1 | unordered
1562 switch (SetCCOpcode) {
1565 case ISD::SETEQ: X86CC = X86::COND_E; break;
1566 case ISD::SETOLT: Flip = true; // Fallthrough
1568 case ISD::SETGT: X86CC = X86::COND_A; break;
1569 case ISD::SETOLE: Flip = true; // Fallthrough
1571 case ISD::SETGE: X86CC = X86::COND_AE; break;
1572 case ISD::SETUGT: Flip = true; // Fallthrough
1574 case ISD::SETLT: X86CC = X86::COND_B; break;
1575 case ISD::SETUGE: Flip = true; // Fallthrough
1577 case ISD::SETLE: X86CC = X86::COND_BE; break;
1579 case ISD::SETNE: X86CC = X86::COND_NE; break;
1580 case ISD::SETUO: X86CC = X86::COND_P; break;
1581 case ISD::SETO: X86CC = X86::COND_NP; break;
1584 std::swap(LHS, RHS);
1587 return X86CC != X86::COND_INVALID;
1590 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1591 /// code. Current x86 isa includes the following FP cmov instructions:
1592 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1593 static bool hasFPCMov(unsigned X86CC) {
1609 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1610 /// true if Op is undef or if its value falls within the specified range (L, H].
1611 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1612 if (Op.getOpcode() == ISD::UNDEF)
1615 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1616 return (Val >= Low && Val < Hi);
1619 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1620 /// true if Op is undef or if its value equal to the specified value.
1621 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1622 if (Op.getOpcode() == ISD::UNDEF)
1624 return cast<ConstantSDNode>(Op)->getValue() == Val;
1627 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1628 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1629 bool X86::isPSHUFDMask(SDNode *N) {
1630 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1632 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
1635 // Check if the value doesn't reference the second vector.
1636 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1637 SDOperand Arg = N->getOperand(i);
1638 if (Arg.getOpcode() == ISD::UNDEF) continue;
1639 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1640 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
1647 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1648 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1649 bool X86::isPSHUFHWMask(SDNode *N) {
1650 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1652 if (N->getNumOperands() != 8)
1655 // Lower quadword copied in order.
1656 for (unsigned i = 0; i != 4; ++i) {
1657 SDOperand Arg = N->getOperand(i);
1658 if (Arg.getOpcode() == ISD::UNDEF) continue;
1659 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1660 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1664 // Upper quadword shuffled.
1665 for (unsigned i = 4; i != 8; ++i) {
1666 SDOperand Arg = N->getOperand(i);
1667 if (Arg.getOpcode() == ISD::UNDEF) continue;
1668 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1669 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1670 if (Val < 4 || Val > 7)
1677 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1678 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1679 bool X86::isPSHUFLWMask(SDNode *N) {
1680 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1682 if (N->getNumOperands() != 8)
1685 // Upper quadword copied in order.
1686 for (unsigned i = 4; i != 8; ++i)
1687 if (!isUndefOrEqual(N->getOperand(i), i))
1690 // Lower quadword shuffled.
1691 for (unsigned i = 0; i != 4; ++i)
1692 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1698 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1699 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1700 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1701 if (NumElems != 2 && NumElems != 4) return false;
1703 unsigned Half = NumElems / 2;
1704 for (unsigned i = 0; i < Half; ++i)
1705 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1707 for (unsigned i = Half; i < NumElems; ++i)
1708 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1714 bool X86::isSHUFPMask(SDNode *N) {
1715 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1716 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1719 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
1720 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1721 /// half elements to come from vector 1 (which would equal the dest.) and
1722 /// the upper half to come from vector 2.
1723 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1724 if (NumOps != 2 && NumOps != 4) return false;
1726 unsigned Half = NumOps / 2;
1727 for (unsigned i = 0; i < Half; ++i)
1728 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1730 for (unsigned i = Half; i < NumOps; ++i)
1731 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1736 static bool isCommutedSHUFP(SDNode *N) {
1737 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1738 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1741 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1742 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1743 bool X86::isMOVHLPSMask(SDNode *N) {
1744 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1746 if (N->getNumOperands() != 4)
1749 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1750 return isUndefOrEqual(N->getOperand(0), 6) &&
1751 isUndefOrEqual(N->getOperand(1), 7) &&
1752 isUndefOrEqual(N->getOperand(2), 2) &&
1753 isUndefOrEqual(N->getOperand(3), 3);
1756 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1757 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1759 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1760 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1762 if (N->getNumOperands() != 4)
1765 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1766 return isUndefOrEqual(N->getOperand(0), 2) &&
1767 isUndefOrEqual(N->getOperand(1), 3) &&
1768 isUndefOrEqual(N->getOperand(2), 2) &&
1769 isUndefOrEqual(N->getOperand(3), 3);
1772 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1773 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1774 bool X86::isMOVLPMask(SDNode *N) {
1775 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1777 unsigned NumElems = N->getNumOperands();
1778 if (NumElems != 2 && NumElems != 4)
1781 for (unsigned i = 0; i < NumElems/2; ++i)
1782 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1785 for (unsigned i = NumElems/2; i < NumElems; ++i)
1786 if (!isUndefOrEqual(N->getOperand(i), i))
1792 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1793 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1795 bool X86::isMOVHPMask(SDNode *N) {
1796 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1798 unsigned NumElems = N->getNumOperands();
1799 if (NumElems != 2 && NumElems != 4)
1802 for (unsigned i = 0; i < NumElems/2; ++i)
1803 if (!isUndefOrEqual(N->getOperand(i), i))
1806 for (unsigned i = 0; i < NumElems/2; ++i) {
1807 SDOperand Arg = N->getOperand(i + NumElems/2);
1808 if (!isUndefOrEqual(Arg, i + NumElems))
1815 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1816 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1817 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1818 bool V2IsSplat = false) {
1819 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1822 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1823 SDOperand BitI = Elts[i];
1824 SDOperand BitI1 = Elts[i+1];
1825 if (!isUndefOrEqual(BitI, j))
1828 if (isUndefOrEqual(BitI1, NumElts))
1831 if (!isUndefOrEqual(BitI1, j + NumElts))
1839 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1840 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1841 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1844 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1845 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1846 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
1847 bool V2IsSplat = false) {
1848 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1851 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1852 SDOperand BitI = Elts[i];
1853 SDOperand BitI1 = Elts[i+1];
1854 if (!isUndefOrEqual(BitI, j + NumElts/2))
1857 if (isUndefOrEqual(BitI1, NumElts))
1860 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
1868 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1869 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1870 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1873 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1874 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1876 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1877 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1879 unsigned NumElems = N->getNumOperands();
1880 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1883 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1884 SDOperand BitI = N->getOperand(i);
1885 SDOperand BitI1 = N->getOperand(i+1);
1887 if (!isUndefOrEqual(BitI, j))
1889 if (!isUndefOrEqual(BitI1, j))
1896 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
1897 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
1899 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
1900 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1902 unsigned NumElems = N->getNumOperands();
1903 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
1906 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
1907 SDOperand BitI = N->getOperand(i);
1908 SDOperand BitI1 = N->getOperand(i + 1);
1910 if (!isUndefOrEqual(BitI, j))
1912 if (!isUndefOrEqual(BitI1, j))
1919 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
1920 /// specifies a shuffle of elements that is suitable for input to MOVSS,
1921 /// MOVSD, and MOVD, i.e. setting the lowest element.
1922 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
1923 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1926 if (!isUndefOrEqual(Elts[0], NumElts))
1929 for (unsigned i = 1; i < NumElts; ++i) {
1930 if (!isUndefOrEqual(Elts[i], i))
1937 bool X86::isMOVLMask(SDNode *N) {
1938 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1939 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
1942 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
1943 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
1944 /// element of vector 2 and the other elements to come from vector 1 in order.
1945 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
1946 bool V2IsSplat = false,
1947 bool V2IsUndef = false) {
1948 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
1951 if (!isUndefOrEqual(Ops[0], 0))
1954 for (unsigned i = 1; i < NumOps; ++i) {
1955 SDOperand Arg = Ops[i];
1956 if (!(isUndefOrEqual(Arg, i+NumOps) ||
1957 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
1958 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
1965 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
1966 bool V2IsUndef = false) {
1967 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1968 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
1969 V2IsSplat, V2IsUndef);
1972 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1973 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
1974 bool X86::isMOVSHDUPMask(SDNode *N) {
1975 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1977 if (N->getNumOperands() != 4)
1980 // Expect 1, 1, 3, 3
1981 for (unsigned i = 0; i < 2; ++i) {
1982 SDOperand Arg = N->getOperand(i);
1983 if (Arg.getOpcode() == ISD::UNDEF) continue;
1984 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1985 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1986 if (Val != 1) return false;
1990 for (unsigned i = 2; i < 4; ++i) {
1991 SDOperand Arg = N->getOperand(i);
1992 if (Arg.getOpcode() == ISD::UNDEF) continue;
1993 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1994 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1995 if (Val != 3) return false;
1999 // Don't use movshdup if it can be done with a shufps.
2003 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2004 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2005 bool X86::isMOVSLDUPMask(SDNode *N) {
2006 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2008 if (N->getNumOperands() != 4)
2011 // Expect 0, 0, 2, 2
2012 for (unsigned i = 0; i < 2; ++i) {
2013 SDOperand Arg = N->getOperand(i);
2014 if (Arg.getOpcode() == ISD::UNDEF) continue;
2015 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2016 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2017 if (Val != 0) return false;
2021 for (unsigned i = 2; i < 4; ++i) {
2022 SDOperand Arg = N->getOperand(i);
2023 if (Arg.getOpcode() == ISD::UNDEF) continue;
2024 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2025 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2026 if (Val != 2) return false;
2030 // Don't use movshdup if it can be done with a shufps.
2034 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2035 /// specifies a identity operation on the LHS or RHS.
2036 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2037 unsigned NumElems = N->getNumOperands();
2038 for (unsigned i = 0; i < NumElems; ++i)
2039 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2044 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2045 /// a splat of a single element.
2046 static bool isSplatMask(SDNode *N) {
2047 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2049 // This is a splat operation if each element of the permute is the same, and
2050 // if the value doesn't reference the second vector.
2051 unsigned NumElems = N->getNumOperands();
2052 SDOperand ElementBase;
2054 for (; i != NumElems; ++i) {
2055 SDOperand Elt = N->getOperand(i);
2056 if (isa<ConstantSDNode>(Elt)) {
2062 if (!ElementBase.Val)
2065 for (; i != NumElems; ++i) {
2066 SDOperand Arg = N->getOperand(i);
2067 if (Arg.getOpcode() == ISD::UNDEF) continue;
2068 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2069 if (Arg != ElementBase) return false;
2072 // Make sure it is a splat of the first vector operand.
2073 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2076 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2077 /// a splat of a single element and it's a 2 or 4 element mask.
2078 bool X86::isSplatMask(SDNode *N) {
2079 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2081 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2082 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2084 return ::isSplatMask(N);
2087 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2088 /// specifies a splat of zero element.
2089 bool X86::isSplatLoMask(SDNode *N) {
2090 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2092 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2093 if (!isUndefOrEqual(N->getOperand(i), 0))
2098 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2099 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2101 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2102 unsigned NumOperands = N->getNumOperands();
2103 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2105 for (unsigned i = 0; i < NumOperands; ++i) {
2107 SDOperand Arg = N->getOperand(NumOperands-i-1);
2108 if (Arg.getOpcode() != ISD::UNDEF)
2109 Val = cast<ConstantSDNode>(Arg)->getValue();
2110 if (Val >= NumOperands) Val -= NumOperands;
2112 if (i != NumOperands - 1)
2119 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2120 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2122 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2124 // 8 nodes, but we only care about the last 4.
2125 for (unsigned i = 7; i >= 4; --i) {
2127 SDOperand Arg = N->getOperand(i);
2128 if (Arg.getOpcode() != ISD::UNDEF)
2129 Val = cast<ConstantSDNode>(Arg)->getValue();
2138 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2139 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2141 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2143 // 8 nodes, but we only care about the first 4.
2144 for (int i = 3; i >= 0; --i) {
2146 SDOperand Arg = N->getOperand(i);
2147 if (Arg.getOpcode() != ISD::UNDEF)
2148 Val = cast<ConstantSDNode>(Arg)->getValue();
2157 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2158 /// specifies a 8 element shuffle that can be broken into a pair of
2159 /// PSHUFHW and PSHUFLW.
2160 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2161 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2163 if (N->getNumOperands() != 8)
2166 // Lower quadword shuffled.
2167 for (unsigned i = 0; i != 4; ++i) {
2168 SDOperand Arg = N->getOperand(i);
2169 if (Arg.getOpcode() == ISD::UNDEF) continue;
2170 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2171 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2176 // Upper quadword shuffled.
2177 for (unsigned i = 4; i != 8; ++i) {
2178 SDOperand Arg = N->getOperand(i);
2179 if (Arg.getOpcode() == ISD::UNDEF) continue;
2180 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2181 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2182 if (Val < 4 || Val > 7)
2189 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2190 /// values in ther permute mask.
2191 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2192 SDOperand &V2, SDOperand &Mask,
2193 SelectionDAG &DAG) {
2194 MVT::ValueType VT = Op.getValueType();
2195 MVT::ValueType MaskVT = Mask.getValueType();
2196 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2197 unsigned NumElems = Mask.getNumOperands();
2198 SmallVector<SDOperand, 8> MaskVec;
2200 for (unsigned i = 0; i != NumElems; ++i) {
2201 SDOperand Arg = Mask.getOperand(i);
2202 if (Arg.getOpcode() == ISD::UNDEF) {
2203 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2206 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2207 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2209 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2211 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2215 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2216 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2219 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2220 /// match movhlps. The lower half elements should come from upper half of
2221 /// V1 (and in order), and the upper half elements should come from the upper
2222 /// half of V2 (and in order).
2223 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2224 unsigned NumElems = Mask->getNumOperands();
2227 for (unsigned i = 0, e = 2; i != e; ++i)
2228 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2230 for (unsigned i = 2; i != 4; ++i)
2231 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2236 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2237 /// is promoted to a vector.
2238 static inline bool isScalarLoadToVector(SDNode *N) {
2239 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2240 N = N->getOperand(0).Val;
2241 return ISD::isNON_EXTLoad(N);
2246 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2247 /// match movlp{s|d}. The lower half elements should come from lower half of
2248 /// V1 (and in order), and the upper half elements should come from the upper
2249 /// half of V2 (and in order). And since V1 will become the source of the
2250 /// MOVLP, it must be either a vector load or a scalar load to vector.
2251 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2252 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2254 // Is V2 is a vector load, don't do this transformation. We will try to use
2255 // load folding shufps op.
2256 if (ISD::isNON_EXTLoad(V2))
2259 unsigned NumElems = Mask->getNumOperands();
2260 if (NumElems != 2 && NumElems != 4)
2262 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2263 if (!isUndefOrEqual(Mask->getOperand(i), i))
2265 for (unsigned i = NumElems/2; i != NumElems; ++i)
2266 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2271 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2273 static bool isSplatVector(SDNode *N) {
2274 if (N->getOpcode() != ISD::BUILD_VECTOR)
2277 SDOperand SplatValue = N->getOperand(0);
2278 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2279 if (N->getOperand(i) != SplatValue)
2284 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2286 static bool isUndefShuffle(SDNode *N) {
2287 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2290 SDOperand V1 = N->getOperand(0);
2291 SDOperand V2 = N->getOperand(1);
2292 SDOperand Mask = N->getOperand(2);
2293 unsigned NumElems = Mask.getNumOperands();
2294 for (unsigned i = 0; i != NumElems; ++i) {
2295 SDOperand Arg = Mask.getOperand(i);
2296 if (Arg.getOpcode() != ISD::UNDEF) {
2297 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2298 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2300 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2307 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2309 static inline bool isZeroNode(SDOperand Elt) {
2310 return ((isa<ConstantSDNode>(Elt) &&
2311 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2312 (isa<ConstantFPSDNode>(Elt) &&
2313 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2316 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2317 /// to an zero vector.
2318 static bool isZeroShuffle(SDNode *N) {
2319 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2322 SDOperand V1 = N->getOperand(0);
2323 SDOperand V2 = N->getOperand(1);
2324 SDOperand Mask = N->getOperand(2);
2325 unsigned NumElems = Mask.getNumOperands();
2326 for (unsigned i = 0; i != NumElems; ++i) {
2327 SDOperand Arg = Mask.getOperand(i);
2328 if (Arg.getOpcode() != ISD::UNDEF) {
2329 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2330 if (Idx < NumElems) {
2331 unsigned Opc = V1.Val->getOpcode();
2332 if (Opc == ISD::UNDEF)
2334 if (Opc != ISD::BUILD_VECTOR ||
2335 !isZeroNode(V1.Val->getOperand(Idx)))
2337 } else if (Idx >= NumElems) {
2338 unsigned Opc = V2.Val->getOpcode();
2339 if (Opc == ISD::UNDEF)
2341 if (Opc != ISD::BUILD_VECTOR ||
2342 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2350 /// getZeroVector - Returns a vector of specified type with all zero elements.
2352 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2353 assert(MVT::isVector(VT) && "Expected a vector type");
2354 unsigned NumElems = MVT::getVectorNumElements(VT);
2355 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2356 bool isFP = MVT::isFloatingPoint(EVT);
2357 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2358 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2359 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2362 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2363 /// that point to V2 points to its first element.
2364 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2365 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2367 bool Changed = false;
2368 SmallVector<SDOperand, 8> MaskVec;
2369 unsigned NumElems = Mask.getNumOperands();
2370 for (unsigned i = 0; i != NumElems; ++i) {
2371 SDOperand Arg = Mask.getOperand(i);
2372 if (Arg.getOpcode() != ISD::UNDEF) {
2373 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2374 if (Val > NumElems) {
2375 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2379 MaskVec.push_back(Arg);
2383 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2384 &MaskVec[0], MaskVec.size());
2388 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2389 /// operation of specified width.
2390 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2391 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2392 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2394 SmallVector<SDOperand, 8> MaskVec;
2395 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2396 for (unsigned i = 1; i != NumElems; ++i)
2397 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2398 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2401 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2402 /// of specified width.
2403 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2404 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2405 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2406 SmallVector<SDOperand, 8> MaskVec;
2407 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2408 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2409 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2411 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2414 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2415 /// of specified width.
2416 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2417 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2418 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2419 unsigned Half = NumElems/2;
2420 SmallVector<SDOperand, 8> MaskVec;
2421 for (unsigned i = 0; i != Half; ++i) {
2422 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2423 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2425 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2428 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2430 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2431 SDOperand V1 = Op.getOperand(0);
2432 SDOperand Mask = Op.getOperand(2);
2433 MVT::ValueType VT = Op.getValueType();
2434 unsigned NumElems = Mask.getNumOperands();
2435 Mask = getUnpacklMask(NumElems, DAG);
2436 while (NumElems != 4) {
2437 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2440 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2442 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2443 Mask = getZeroVector(MaskVT, DAG);
2444 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2445 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2446 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2449 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2450 /// vector of zero or undef vector.
2451 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2452 unsigned NumElems, unsigned Idx,
2453 bool isZero, SelectionDAG &DAG) {
2454 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2455 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2456 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2457 SDOperand Zero = DAG.getConstant(0, EVT);
2458 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2459 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2460 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2461 &MaskVec[0], MaskVec.size());
2462 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2465 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2467 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2468 unsigned NumNonZero, unsigned NumZero,
2469 SelectionDAG &DAG, TargetLowering &TLI) {
2475 for (unsigned i = 0; i < 16; ++i) {
2476 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2477 if (ThisIsNonZero && First) {
2479 V = getZeroVector(MVT::v8i16, DAG);
2481 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2486 SDOperand ThisElt(0, 0), LastElt(0, 0);
2487 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2488 if (LastIsNonZero) {
2489 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2491 if (ThisIsNonZero) {
2492 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2493 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2494 ThisElt, DAG.getConstant(8, MVT::i8));
2496 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2501 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2502 DAG.getConstant(i/2, TLI.getPointerTy()));
2506 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2509 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2511 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2512 unsigned NumNonZero, unsigned NumZero,
2513 SelectionDAG &DAG, TargetLowering &TLI) {
2519 for (unsigned i = 0; i < 8; ++i) {
2520 bool isNonZero = (NonZeros & (1 << i)) != 0;
2524 V = getZeroVector(MVT::v8i16, DAG);
2526 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2529 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2530 DAG.getConstant(i, TLI.getPointerTy()));
2538 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2539 // All zero's are handled with pxor.
2540 if (ISD::isBuildVectorAllZeros(Op.Val))
2543 // All one's are handled with pcmpeqd.
2544 if (ISD::isBuildVectorAllOnes(Op.Val))
2547 MVT::ValueType VT = Op.getValueType();
2548 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2549 unsigned EVTBits = MVT::getSizeInBits(EVT);
2551 unsigned NumElems = Op.getNumOperands();
2552 unsigned NumZero = 0;
2553 unsigned NumNonZero = 0;
2554 unsigned NonZeros = 0;
2555 unsigned NumNonZeroImms = 0;
2556 std::set<SDOperand> Values;
2557 for (unsigned i = 0; i < NumElems; ++i) {
2558 SDOperand Elt = Op.getOperand(i);
2559 if (Elt.getOpcode() != ISD::UNDEF) {
2561 if (isZeroNode(Elt))
2564 NonZeros |= (1 << i);
2566 if (Elt.getOpcode() == ISD::Constant ||
2567 Elt.getOpcode() == ISD::ConstantFP)
2573 if (NumNonZero == 0) {
2575 // All undef vector. Return an UNDEF.
2576 return DAG.getNode(ISD::UNDEF, VT);
2578 // A mix of zero and undef. Return a zero vector.
2579 return getZeroVector(VT, DAG);
2582 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2583 if (Values.size() == 1)
2586 // Special case for single non-zero element.
2587 if (NumNonZero == 1) {
2588 unsigned Idx = CountTrailingZeros_32(NonZeros);
2589 SDOperand Item = Op.getOperand(Idx);
2590 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2592 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2593 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2596 if (EVTBits == 32) {
2597 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2598 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2600 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2601 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2602 SmallVector<SDOperand, 8> MaskVec;
2603 for (unsigned i = 0; i < NumElems; i++)
2604 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2605 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2606 &MaskVec[0], MaskVec.size());
2607 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2608 DAG.getNode(ISD::UNDEF, VT), Mask);
2612 // A vector full of immediates; various special cases are already
2613 // handled, so this is best done with a single constant-pool load.
2614 if (NumNonZero == NumNonZeroImms)
2617 // Let legalizer expand 2-wide build_vectors.
2621 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2622 if (EVTBits == 8 && NumElems == 16) {
2623 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2625 if (V.Val) return V;
2628 if (EVTBits == 16 && NumElems == 8) {
2629 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2631 if (V.Val) return V;
2634 // If element VT is == 32 bits, turn it into a number of shuffles.
2635 SmallVector<SDOperand, 8> V;
2637 if (NumElems == 4 && NumZero > 0) {
2638 for (unsigned i = 0; i < 4; ++i) {
2639 bool isZero = !(NonZeros & (1 << i));
2641 V[i] = getZeroVector(VT, DAG);
2643 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2646 for (unsigned i = 0; i < 2; ++i) {
2647 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2650 V[i] = V[i*2]; // Must be a zero vector.
2653 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2654 getMOVLMask(NumElems, DAG));
2657 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2658 getMOVLMask(NumElems, DAG));
2661 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2662 getUnpacklMask(NumElems, DAG));
2667 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2668 // clears the upper bits.
2669 // FIXME: we can do the same for v4f32 case when we know both parts of
2670 // the lower half come from scalar_to_vector (loadf32). We should do
2671 // that in post legalizer dag combiner with target specific hooks.
2672 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2674 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2675 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2676 SmallVector<SDOperand, 8> MaskVec;
2677 bool Reverse = (NonZeros & 0x3) == 2;
2678 for (unsigned i = 0; i < 2; ++i)
2680 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2682 MaskVec.push_back(DAG.getConstant(i, EVT));
2683 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2684 for (unsigned i = 0; i < 2; ++i)
2686 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2688 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2689 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2690 &MaskVec[0], MaskVec.size());
2691 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2694 if (Values.size() > 2) {
2695 // Expand into a number of unpckl*.
2697 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2698 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2699 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2700 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2701 for (unsigned i = 0; i < NumElems; ++i)
2702 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2704 while (NumElems != 0) {
2705 for (unsigned i = 0; i < NumElems; ++i)
2706 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2717 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2718 SDOperand V1 = Op.getOperand(0);
2719 SDOperand V2 = Op.getOperand(1);
2720 SDOperand PermMask = Op.getOperand(2);
2721 MVT::ValueType VT = Op.getValueType();
2722 unsigned NumElems = PermMask.getNumOperands();
2723 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2724 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2725 bool V1IsSplat = false;
2726 bool V2IsSplat = false;
2728 if (isUndefShuffle(Op.Val))
2729 return DAG.getNode(ISD::UNDEF, VT);
2731 if (isZeroShuffle(Op.Val))
2732 return getZeroVector(VT, DAG);
2734 if (isIdentityMask(PermMask.Val))
2736 else if (isIdentityMask(PermMask.Val, true))
2739 if (isSplatMask(PermMask.Val)) {
2740 if (NumElems <= 4) return Op;
2741 // Promote it to a v4i32 splat.
2742 return PromoteSplat(Op, DAG);
2745 if (X86::isMOVLMask(PermMask.Val))
2746 return (V1IsUndef) ? V2 : Op;
2748 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2749 X86::isMOVSLDUPMask(PermMask.Val) ||
2750 X86::isMOVHLPSMask(PermMask.Val) ||
2751 X86::isMOVHPMask(PermMask.Val) ||
2752 X86::isMOVLPMask(PermMask.Val))
2755 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2756 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
2757 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2759 bool Commuted = false;
2760 V1IsSplat = isSplatVector(V1.Val);
2761 V2IsSplat = isSplatVector(V2.Val);
2762 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
2763 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2764 std::swap(V1IsSplat, V2IsSplat);
2765 std::swap(V1IsUndef, V2IsUndef);
2769 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
2770 if (V2IsUndef) return V1;
2771 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2773 // V2 is a splat, so the mask may be malformed. That is, it may point
2774 // to any V2 element. The instruction selectior won't like this. Get
2775 // a corrected mask and commute to form a proper MOVS{S|D}.
2776 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2777 if (NewMask.Val != PermMask.Val)
2778 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2783 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2784 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2785 X86::isUNPCKLMask(PermMask.Val) ||
2786 X86::isUNPCKHMask(PermMask.Val))
2790 // Normalize mask so all entries that point to V2 points to its first
2791 // element then try to match unpck{h|l} again. If match, return a
2792 // new vector_shuffle with the corrected mask.
2793 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2794 if (NewMask.Val != PermMask.Val) {
2795 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2796 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2797 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2798 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2799 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2800 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2805 // Normalize the node to match x86 shuffle ops if needed
2806 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
2807 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2810 // Commute is back and try unpck* again.
2811 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2812 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2813 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
2814 X86::isUNPCKLMask(PermMask.Val) ||
2815 X86::isUNPCKHMask(PermMask.Val))
2819 // If VT is integer, try PSHUF* first, then SHUFP*.
2820 if (MVT::isInteger(VT)) {
2821 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
2822 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
2823 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
2824 X86::isPSHUFDMask(PermMask.Val)) ||
2825 X86::isPSHUFHWMask(PermMask.Val) ||
2826 X86::isPSHUFLWMask(PermMask.Val)) {
2827 if (V2.getOpcode() != ISD::UNDEF)
2828 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2829 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2833 if (X86::isSHUFPMask(PermMask.Val) &&
2834 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
2837 // Handle v8i16 shuffle high / low shuffle node pair.
2838 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2839 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2840 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2841 SmallVector<SDOperand, 8> MaskVec;
2842 for (unsigned i = 0; i != 4; ++i)
2843 MaskVec.push_back(PermMask.getOperand(i));
2844 for (unsigned i = 4; i != 8; ++i)
2845 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2846 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2847 &MaskVec[0], MaskVec.size());
2848 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2850 for (unsigned i = 0; i != 4; ++i)
2851 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2852 for (unsigned i = 4; i != 8; ++i)
2853 MaskVec.push_back(PermMask.getOperand(i));
2854 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
2855 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2858 // Floating point cases in the other order.
2859 if (X86::isSHUFPMask(PermMask.Val))
2861 if (X86::isPSHUFDMask(PermMask.Val) ||
2862 X86::isPSHUFHWMask(PermMask.Val) ||
2863 X86::isPSHUFLWMask(PermMask.Val)) {
2864 if (V2.getOpcode() != ISD::UNDEF)
2865 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2866 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2871 if (NumElems == 4 &&
2872 // Don't do this for MMX.
2873 MVT::getSizeInBits(VT) != 64) {
2874 MVT::ValueType MaskVT = PermMask.getValueType();
2875 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2876 SmallVector<std::pair<int, int>, 8> Locs;
2877 Locs.reserve(NumElems);
2878 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2879 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2882 // If no more than two elements come from either vector. This can be
2883 // implemented with two shuffles. First shuffle gather the elements.
2884 // The second shuffle, which takes the first shuffle as both of its
2885 // vector operands, put the elements into the right order.
2886 for (unsigned i = 0; i != NumElems; ++i) {
2887 SDOperand Elt = PermMask.getOperand(i);
2888 if (Elt.getOpcode() == ISD::UNDEF) {
2889 Locs[i] = std::make_pair(-1, -1);
2891 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2892 if (Val < NumElems) {
2893 Locs[i] = std::make_pair(0, NumLo);
2897 Locs[i] = std::make_pair(1, NumHi);
2898 if (2+NumHi < NumElems)
2899 Mask1[2+NumHi] = Elt;
2904 if (NumLo <= 2 && NumHi <= 2) {
2905 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2906 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2907 &Mask1[0], Mask1.size()));
2908 for (unsigned i = 0; i != NumElems; ++i) {
2909 if (Locs[i].first == -1)
2912 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
2913 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
2914 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
2918 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
2919 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2920 &Mask2[0], Mask2.size()));
2923 // Break it into (shuffle shuffle_hi, shuffle_lo).
2925 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2926 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2927 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
2928 unsigned MaskIdx = 0;
2930 unsigned HiIdx = NumElems/2;
2931 for (unsigned i = 0; i != NumElems; ++i) {
2932 if (i == NumElems/2) {
2938 SDOperand Elt = PermMask.getOperand(i);
2939 if (Elt.getOpcode() == ISD::UNDEF) {
2940 Locs[i] = std::make_pair(-1, -1);
2941 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
2942 Locs[i] = std::make_pair(MaskIdx, LoIdx);
2943 (*MaskPtr)[LoIdx] = Elt;
2946 Locs[i] = std::make_pair(MaskIdx, HiIdx);
2947 (*MaskPtr)[HiIdx] = Elt;
2952 SDOperand LoShuffle =
2953 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2954 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2955 &LoMask[0], LoMask.size()));
2956 SDOperand HiShuffle =
2957 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2958 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2959 &HiMask[0], HiMask.size()));
2960 SmallVector<SDOperand, 8> MaskOps;
2961 for (unsigned i = 0; i != NumElems; ++i) {
2962 if (Locs[i].first == -1) {
2963 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
2965 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
2966 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
2969 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
2970 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2971 &MaskOps[0], MaskOps.size()));
2978 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2979 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2982 MVT::ValueType VT = Op.getValueType();
2983 // TODO: handle v16i8.
2984 if (MVT::getSizeInBits(VT) == 16) {
2985 // Transform it so it match pextrw which produces a 32-bit result.
2986 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
2987 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
2988 Op.getOperand(0), Op.getOperand(1));
2989 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
2990 DAG.getValueType(VT));
2991 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
2992 } else if (MVT::getSizeInBits(VT) == 32) {
2993 SDOperand Vec = Op.getOperand(0);
2994 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2997 // SHUFPS the element to the lowest double word, then movss.
2998 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2999 SmallVector<SDOperand, 8> IdxVec;
3000 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3001 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3002 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3003 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3004 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3005 &IdxVec[0], IdxVec.size());
3006 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3007 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3008 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3009 DAG.getConstant(0, getPointerTy()));
3010 } else if (MVT::getSizeInBits(VT) == 64) {
3011 SDOperand Vec = Op.getOperand(0);
3012 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3016 // UNPCKHPD the element to the lowest double word, then movsd.
3017 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3018 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3019 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3020 SmallVector<SDOperand, 8> IdxVec;
3021 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
3022 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3023 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3024 &IdxVec[0], IdxVec.size());
3025 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3026 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3027 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3028 DAG.getConstant(0, getPointerTy()));
3035 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3036 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3037 // as its second argument.
3038 MVT::ValueType VT = Op.getValueType();
3039 MVT::ValueType BaseVT = MVT::getVectorElementType(VT);
3040 SDOperand N0 = Op.getOperand(0);
3041 SDOperand N1 = Op.getOperand(1);
3042 SDOperand N2 = Op.getOperand(2);
3043 if (MVT::getSizeInBits(BaseVT) == 16) {
3044 if (N1.getValueType() != MVT::i32)
3045 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3046 if (N2.getValueType() != MVT::i32)
3047 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(),getPointerTy());
3048 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3049 } else if (MVT::getSizeInBits(BaseVT) == 32) {
3050 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
3053 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
3054 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3055 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
3056 SmallVector<SDOperand, 8> MaskVec;
3057 MaskVec.push_back(DAG.getConstant(4, BaseVT));
3058 for (unsigned i = 1; i <= 3; ++i)
3059 MaskVec.push_back(DAG.getConstant(i, BaseVT));
3060 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
3061 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3062 &MaskVec[0], MaskVec.size()));
3064 // Use two pinsrw instructions to insert a 32 bit value.
3066 if (MVT::isFloatingPoint(N1.getValueType())) {
3067 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
3068 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
3069 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
3070 DAG.getConstant(0, getPointerTy()));
3072 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
3073 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3074 DAG.getConstant(Idx, getPointerTy()));
3075 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
3076 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
3077 DAG.getConstant(Idx+1, getPointerTy()));
3078 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3086 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3087 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3088 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3091 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3092 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3093 // one of the above mentioned nodes. It has to be wrapped because otherwise
3094 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3095 // be used to form addressing mode. These wrapped nodes will be selected
3098 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3099 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3100 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3102 CP->getAlignment());
3103 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3104 // With PIC, the address is actually $g + Offset.
3105 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3106 !Subtarget->isPICStyleRIPRel()) {
3107 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3108 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3116 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3117 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3118 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3119 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3120 // With PIC, the address is actually $g + Offset.
3121 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3122 !Subtarget->isPICStyleRIPRel()) {
3123 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3124 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3128 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3129 // load the value at address GV, not the value of GV itself. This means that
3130 // the GlobalAddress must be in the base or index register of the address, not
3131 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3132 // The same applies for external symbols during PIC codegen
3133 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3134 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3139 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3141 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3142 const MVT::ValueType PtrVT) {
3144 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3145 DAG.getNode(X86ISD::GlobalBaseReg,
3147 InFlag = Chain.getValue(1);
3149 // emit leal symbol@TLSGD(,%ebx,1), %eax
3150 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3151 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3152 GA->getValueType(0),
3154 SDOperand Ops[] = { Chain, TGA, InFlag };
3155 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3156 InFlag = Result.getValue(2);
3157 Chain = Result.getValue(1);
3159 // call ___tls_get_addr. This function receives its argument in
3160 // the register EAX.
3161 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3162 InFlag = Chain.getValue(1);
3164 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3165 SDOperand Ops1[] = { Chain,
3166 DAG.getTargetExternalSymbol("___tls_get_addr",
3168 DAG.getRegister(X86::EAX, PtrVT),
3169 DAG.getRegister(X86::EBX, PtrVT),
3171 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3172 InFlag = Chain.getValue(1);
3174 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3177 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3178 // "local exec" model.
3180 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3181 const MVT::ValueType PtrVT) {
3182 // Get the Thread Pointer
3183 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3184 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3186 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3187 GA->getValueType(0),
3189 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3191 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3192 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3194 // The address of the thread local variable is the add of the thread
3195 // pointer with the offset of the variable.
3196 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3200 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3201 // TODO: implement the "local dynamic" model
3202 // TODO: implement the "initial exec"model for pic executables
3203 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3204 "TLS not implemented for non-ELF and 64-bit targets");
3205 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3206 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3207 // otherwise use the "Local Exec"TLS Model
3208 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3209 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3211 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3215 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3216 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3217 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3218 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3219 // With PIC, the address is actually $g + Offset.
3220 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3221 !Subtarget->isPICStyleRIPRel()) {
3222 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3223 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3230 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3231 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3232 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3233 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3234 // With PIC, the address is actually $g + Offset.
3235 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3236 !Subtarget->isPICStyleRIPRel()) {
3237 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3238 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3245 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3246 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3247 "Not an i64 shift!");
3248 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3249 SDOperand ShOpLo = Op.getOperand(0);
3250 SDOperand ShOpHi = Op.getOperand(1);
3251 SDOperand ShAmt = Op.getOperand(2);
3252 SDOperand Tmp1 = isSRA ?
3253 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3254 DAG.getConstant(0, MVT::i32);
3256 SDOperand Tmp2, Tmp3;
3257 if (Op.getOpcode() == ISD::SHL_PARTS) {
3258 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3259 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3261 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3262 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3265 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3266 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3267 DAG.getConstant(32, MVT::i8));
3268 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3269 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3272 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3274 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3275 SmallVector<SDOperand, 4> Ops;
3276 if (Op.getOpcode() == ISD::SHL_PARTS) {
3277 Ops.push_back(Tmp2);
3278 Ops.push_back(Tmp3);
3280 Ops.push_back(InFlag);
3281 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3282 InFlag = Hi.getValue(1);
3285 Ops.push_back(Tmp3);
3286 Ops.push_back(Tmp1);
3288 Ops.push_back(InFlag);
3289 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3291 Ops.push_back(Tmp2);
3292 Ops.push_back(Tmp3);
3294 Ops.push_back(InFlag);
3295 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3296 InFlag = Lo.getValue(1);
3299 Ops.push_back(Tmp3);
3300 Ops.push_back(Tmp1);
3302 Ops.push_back(InFlag);
3303 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3306 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3310 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3313 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3314 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3315 Op.getOperand(0).getValueType() >= MVT::i16 &&
3316 "Unknown SINT_TO_FP to lower!");
3319 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3320 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3321 MachineFunction &MF = DAG.getMachineFunction();
3322 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3323 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3324 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3325 StackSlot, NULL, 0);
3330 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3332 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
3333 SmallVector<SDOperand, 8> Ops;
3334 Ops.push_back(Chain);
3335 Ops.push_back(StackSlot);
3336 Ops.push_back(DAG.getValueType(SrcVT));
3337 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3338 Tys, &Ops[0], Ops.size());
3341 Chain = Result.getValue(1);
3342 SDOperand InFlag = Result.getValue(2);
3344 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3345 // shouldn't be necessary except that RFP cannot be live across
3346 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3347 MachineFunction &MF = DAG.getMachineFunction();
3348 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3349 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3350 Tys = DAG.getVTList(MVT::Other);
3351 SmallVector<SDOperand, 8> Ops;
3352 Ops.push_back(Chain);
3353 Ops.push_back(Result);
3354 Ops.push_back(StackSlot);
3355 Ops.push_back(DAG.getValueType(Op.getValueType()));
3356 Ops.push_back(InFlag);
3357 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3358 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3364 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3365 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3366 "Unknown FP_TO_SINT to lower!");
3367 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3369 MachineFunction &MF = DAG.getMachineFunction();
3370 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3371 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3372 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3375 switch (Op.getValueType()) {
3376 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3377 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3378 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3379 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3382 SDOperand Chain = DAG.getEntryNode();
3383 SDOperand Value = Op.getOperand(0);
3385 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3386 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3387 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
3389 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3391 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3392 Chain = Value.getValue(1);
3393 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3394 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3397 // Build the FP_TO_INT*_IN_MEM
3398 SDOperand Ops[] = { Chain, Value, StackSlot };
3399 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3402 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3405 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3406 MVT::ValueType VT = Op.getValueType();
3407 MVT::ValueType EltVT = VT;
3408 if (MVT::isVector(VT))
3409 EltVT = MVT::getVectorElementType(VT);
3410 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3411 std::vector<Constant*> CV;
3412 if (EltVT == MVT::f64) {
3413 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63))));
3417 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31))));
3423 Constant *C = ConstantVector::get(CV);
3424 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3425 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3427 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3430 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3431 MVT::ValueType VT = Op.getValueType();
3432 MVT::ValueType EltVT = VT;
3433 unsigned EltNum = 1;
3434 if (MVT::isVector(VT)) {
3435 EltVT = MVT::getVectorElementType(VT);
3436 EltNum = MVT::getVectorNumElements(VT);
3438 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3439 std::vector<Constant*> CV;
3440 if (EltVT == MVT::f64) {
3441 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63)));
3445 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31)));
3451 Constant *C = ConstantVector::get(CV);
3452 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3453 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3455 if (MVT::isVector(VT)) {
3456 return DAG.getNode(ISD::BIT_CONVERT, VT,
3457 DAG.getNode(ISD::XOR, MVT::v2i64,
3458 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
3459 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
3461 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3465 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3466 SDOperand Op0 = Op.getOperand(0);
3467 SDOperand Op1 = Op.getOperand(1);
3468 MVT::ValueType VT = Op.getValueType();
3469 MVT::ValueType SrcVT = Op1.getValueType();
3470 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3472 // If second operand is smaller, extend it first.
3473 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3474 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3476 SrcTy = MVT::getTypeForValueType(SrcVT);
3479 // First get the sign bit of second operand.
3480 std::vector<Constant*> CV;
3481 if (SrcVT == MVT::f64) {
3482 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63))));
3483 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
3485 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31))));
3486 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3487 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3488 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3490 Constant *C = ConstantVector::get(CV);
3491 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3492 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
3494 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3496 // Shift sign bit right or left if the two operands have different types.
3497 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3498 // Op0 is MVT::f32, Op1 is MVT::f64.
3499 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3500 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3501 DAG.getConstant(32, MVT::i32));
3502 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3503 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3504 DAG.getConstant(0, getPointerTy()));
3507 // Clear first operand sign bit.
3509 if (VT == MVT::f64) {
3510 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63)))));
3511 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
3513 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31)))));
3514 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3515 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3516 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
3518 C = ConstantVector::get(CV);
3519 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3520 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3522 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3524 // Or the value with the sign bit.
3525 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3528 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3530 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3532 SDOperand Op0 = Op.getOperand(0);
3533 SDOperand Op1 = Op.getOperand(1);
3534 SDOperand CC = Op.getOperand(2);
3535 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3536 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3537 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3538 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3541 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3543 SDOperand Ops1[] = { Chain, Op0, Op1 };
3544 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3545 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3546 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3549 assert(isFP && "Illegal integer SetCC!");
3551 SDOperand COps[] = { Chain, Op0, Op1 };
3552 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3554 switch (SetCCOpcode) {
3555 default: assert(false && "Illegal floating point SetCC!");
3556 case ISD::SETOEQ: { // !PF & ZF
3557 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3558 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3559 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3561 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3562 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3564 case ISD::SETUNE: { // PF | !ZF
3565 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3566 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3567 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3569 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3570 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3575 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3576 bool addTest = true;
3577 SDOperand Chain = DAG.getEntryNode();
3578 SDOperand Cond = Op.getOperand(0);
3580 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3582 if (Cond.getOpcode() == ISD::SETCC)
3583 Cond = LowerSETCC(Cond, DAG, Chain);
3585 if (Cond.getOpcode() == X86ISD::SETCC) {
3586 CC = Cond.getOperand(0);
3588 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3589 // (since flag operand cannot be shared). Use it as the condition setting
3590 // operand in place of the X86ISD::SETCC.
3591 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3592 // to use a test instead of duplicating the X86ISD::CMP (for register
3593 // pressure reason)?
3594 SDOperand Cmp = Cond.getOperand(1);
3595 unsigned Opc = Cmp.getOpcode();
3596 bool IllegalFPCMov = !X86ScalarSSE &&
3597 MVT::isFloatingPoint(Op.getValueType()) &&
3598 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3599 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3601 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3602 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3608 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3609 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3610 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3613 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3614 SmallVector<SDOperand, 4> Ops;
3615 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3616 // condition is true.
3617 Ops.push_back(Op.getOperand(2));
3618 Ops.push_back(Op.getOperand(1));
3620 Ops.push_back(Cond.getValue(1));
3621 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3624 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3625 bool addTest = true;
3626 SDOperand Chain = Op.getOperand(0);
3627 SDOperand Cond = Op.getOperand(1);
3628 SDOperand Dest = Op.getOperand(2);
3630 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3632 if (Cond.getOpcode() == ISD::SETCC)
3633 Cond = LowerSETCC(Cond, DAG, Chain);
3635 if (Cond.getOpcode() == X86ISD::SETCC) {
3636 CC = Cond.getOperand(0);
3638 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3639 // (since flag operand cannot be shared). Use it as the condition setting
3640 // operand in place of the X86ISD::SETCC.
3641 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3642 // to use a test instead of duplicating the X86ISD::CMP (for register
3643 // pressure reason)?
3644 SDOperand Cmp = Cond.getOperand(1);
3645 unsigned Opc = Cmp.getOpcode();
3646 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3647 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3648 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3654 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3655 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3656 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3658 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3659 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3662 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3663 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3665 if (Subtarget->is64Bit())
3666 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3668 switch (CallingConv) {
3670 assert(0 && "Unsupported calling convention");
3671 case CallingConv::Fast:
3672 // TODO: Implement fastcc
3674 case CallingConv::C:
3675 case CallingConv::X86_StdCall:
3676 return LowerCCCCallTo(Op, DAG, CallingConv);
3677 case CallingConv::X86_FastCall:
3678 return LowerFastCCCallTo(Op, DAG, CallingConv);
3683 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3684 // Calls to _alloca is needed to probe the stack when allocating more than 4k
3685 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3686 // that the guard pages used by the OS virtual memory manager are allocated in
3687 // correct sequence.
3689 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
3690 SelectionDAG &DAG) {
3691 assert(Subtarget->isTargetCygMing() &&
3692 "This should be used only on Cygwin/Mingw targets");
3695 SDOperand Chain = Op.getOperand(0);
3696 SDOperand Size = Op.getOperand(1);
3697 // FIXME: Ensure alignment here
3701 MVT::ValueType IntPtr = getPointerTy();
3702 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
3704 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
3705 Flag = Chain.getValue(1);
3707 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3708 SDOperand Ops[] = { Chain,
3709 DAG.getTargetExternalSymbol("_alloca", IntPtr),
3710 DAG.getRegister(X86::EAX, IntPtr),
3712 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
3713 Flag = Chain.getValue(1);
3715 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
3717 std::vector<MVT::ValueType> Tys;
3718 Tys.push_back(SPTy);
3719 Tys.push_back(MVT::Other);
3720 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
3721 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
3725 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3726 MachineFunction &MF = DAG.getMachineFunction();
3727 const Function* Fn = MF.getFunction();
3728 if (Fn->hasExternalLinkage() &&
3729 Subtarget->isTargetCygMing() &&
3730 Fn->getName() == "main")
3731 MF.getInfo<X86MachineFunctionInfo>()->setForceFramePointer(true);
3733 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3734 if (Subtarget->is64Bit())
3735 return LowerX86_64CCCArguments(Op, DAG);
3739 assert(0 && "Unsupported calling convention");
3740 case CallingConv::Fast:
3741 // TODO: implement fastcc.
3744 case CallingConv::C:
3745 return LowerCCCArguments(Op, DAG);
3746 case CallingConv::X86_StdCall:
3747 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(StdCall);
3748 return LowerCCCArguments(Op, DAG, true);
3749 case CallingConv::X86_FastCall:
3750 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(FastCall);
3751 return LowerFastCCArguments(Op, DAG);
3755 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3756 SDOperand InFlag(0, 0);
3757 SDOperand Chain = Op.getOperand(0);
3759 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3760 if (Align == 0) Align = 1;
3762 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3763 // If not DWORD aligned or size is more than the threshold, call memset.
3764 // The libc version is likely to be faster for these cases. It can use the
3765 // address value and run time information about the CPU.
3766 if ((Align & 3) != 0 ||
3767 (I && I->getValue() > Subtarget->getMinRepStrSizeThreshold())) {
3768 MVT::ValueType IntPtr = getPointerTy();
3769 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3770 TargetLowering::ArgListTy Args;
3771 TargetLowering::ArgListEntry Entry;
3772 Entry.Node = Op.getOperand(1);
3773 Entry.Ty = IntPtrTy;
3774 Args.push_back(Entry);
3775 // Extend the unsigned i8 argument to be an int value for the call.
3776 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3777 Entry.Ty = IntPtrTy;
3778 Args.push_back(Entry);
3779 Entry.Node = Op.getOperand(3);
3780 Args.push_back(Entry);
3781 std::pair<SDOperand,SDOperand> CallResult =
3782 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3783 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3784 return CallResult.second;
3789 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3790 unsigned BytesLeft = 0;
3791 bool TwoRepStos = false;
3794 uint64_t Val = ValC->getValue() & 255;
3796 // If the value is a constant, then we can potentially use larger sets.
3797 switch (Align & 3) {
3798 case 2: // WORD aligned
3801 Val = (Val << 8) | Val;
3803 case 0: // DWORD aligned
3806 Val = (Val << 8) | Val;
3807 Val = (Val << 16) | Val;
3808 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3811 Val = (Val << 32) | Val;
3814 default: // Byte aligned
3817 Count = Op.getOperand(3);
3821 if (AVT > MVT::i8) {
3823 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3824 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3825 BytesLeft = I->getValue() % UBytes;
3827 assert(AVT >= MVT::i32 &&
3828 "Do not use rep;stos if not at least DWORD aligned");
3829 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3830 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3835 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3837 InFlag = Chain.getValue(1);
3840 Count = Op.getOperand(3);
3841 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
3842 InFlag = Chain.getValue(1);
3845 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3847 InFlag = Chain.getValue(1);
3848 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3849 Op.getOperand(1), InFlag);
3850 InFlag = Chain.getValue(1);
3852 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3853 SmallVector<SDOperand, 8> Ops;
3854 Ops.push_back(Chain);
3855 Ops.push_back(DAG.getValueType(AVT));
3856 Ops.push_back(InFlag);
3857 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3860 InFlag = Chain.getValue(1);
3861 Count = Op.getOperand(3);
3862 MVT::ValueType CVT = Count.getValueType();
3863 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3864 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3865 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3867 InFlag = Chain.getValue(1);
3868 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3870 Ops.push_back(Chain);
3871 Ops.push_back(DAG.getValueType(MVT::i8));
3872 Ops.push_back(InFlag);
3873 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3874 } else if (BytesLeft) {
3875 // Issue stores for the last 1 - 7 bytes.
3877 unsigned Val = ValC->getValue() & 255;
3878 unsigned Offset = I->getValue() - BytesLeft;
3879 SDOperand DstAddr = Op.getOperand(1);
3880 MVT::ValueType AddrVT = DstAddr.getValueType();
3881 if (BytesLeft >= 4) {
3882 Val = (Val << 8) | Val;
3883 Val = (Val << 16) | Val;
3884 Value = DAG.getConstant(Val, MVT::i32);
3885 Chain = DAG.getStore(Chain, Value,
3886 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3887 DAG.getConstant(Offset, AddrVT)),
3892 if (BytesLeft >= 2) {
3893 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
3894 Chain = DAG.getStore(Chain, Value,
3895 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3896 DAG.getConstant(Offset, AddrVT)),
3901 if (BytesLeft == 1) {
3902 Value = DAG.getConstant(Val, MVT::i8);
3903 Chain = DAG.getStore(Chain, Value,
3904 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3905 DAG.getConstant(Offset, AddrVT)),
3913 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
3914 SDOperand Chain = Op.getOperand(0);
3916 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3917 if (Align == 0) Align = 1;
3919 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3920 // If not DWORD aligned or size is more than the threshold, call memcpy.
3921 // The libc version is likely to be faster for these cases. It can use the
3922 // address value and run time information about the CPU.
3923 // With glibc 2.6.1 on a core 2, coping an array of 100M longs was 30% faster
3924 if ((Align & 3) != 0 ||
3925 (I && I->getValue() > Subtarget->getMinRepStrSizeThreshold())) {
3926 MVT::ValueType IntPtr = getPointerTy();
3927 TargetLowering::ArgListTy Args;
3928 TargetLowering::ArgListEntry Entry;
3929 Entry.Ty = getTargetData()->getIntPtrType();
3930 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
3931 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
3932 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
3933 std::pair<SDOperand,SDOperand> CallResult =
3934 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3935 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
3936 return CallResult.second;
3941 unsigned BytesLeft = 0;
3942 bool TwoRepMovs = false;
3943 switch (Align & 3) {
3944 case 2: // WORD aligned
3947 case 0: // DWORD aligned
3949 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
3952 default: // Byte aligned
3954 Count = Op.getOperand(3);
3958 if (AVT > MVT::i8) {
3960 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3961 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3962 BytesLeft = I->getValue() % UBytes;
3964 assert(AVT >= MVT::i32 &&
3965 "Do not use rep;movs if not at least DWORD aligned");
3966 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3967 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3972 SDOperand InFlag(0, 0);
3973 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3975 InFlag = Chain.getValue(1);
3976 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3977 Op.getOperand(1), InFlag);
3978 InFlag = Chain.getValue(1);
3979 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
3980 Op.getOperand(2), InFlag);
3981 InFlag = Chain.getValue(1);
3983 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3984 SmallVector<SDOperand, 8> Ops;
3985 Ops.push_back(Chain);
3986 Ops.push_back(DAG.getValueType(AVT));
3987 Ops.push_back(InFlag);
3988 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3991 InFlag = Chain.getValue(1);
3992 Count = Op.getOperand(3);
3993 MVT::ValueType CVT = Count.getValueType();
3994 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3995 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3996 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3998 InFlag = Chain.getValue(1);
3999 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4001 Ops.push_back(Chain);
4002 Ops.push_back(DAG.getValueType(MVT::i8));
4003 Ops.push_back(InFlag);
4004 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4005 } else if (BytesLeft) {
4006 // Issue loads and stores for the last 1 - 7 bytes.
4007 unsigned Offset = I->getValue() - BytesLeft;
4008 SDOperand DstAddr = Op.getOperand(1);
4009 MVT::ValueType DstVT = DstAddr.getValueType();
4010 SDOperand SrcAddr = Op.getOperand(2);
4011 MVT::ValueType SrcVT = SrcAddr.getValueType();
4013 if (BytesLeft >= 4) {
4014 Value = DAG.getLoad(MVT::i32, Chain,
4015 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4016 DAG.getConstant(Offset, SrcVT)),
4018 Chain = Value.getValue(1);
4019 Chain = DAG.getStore(Chain, Value,
4020 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4021 DAG.getConstant(Offset, DstVT)),
4026 if (BytesLeft >= 2) {
4027 Value = DAG.getLoad(MVT::i16, Chain,
4028 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4029 DAG.getConstant(Offset, SrcVT)),
4031 Chain = Value.getValue(1);
4032 Chain = DAG.getStore(Chain, Value,
4033 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4034 DAG.getConstant(Offset, DstVT)),
4040 if (BytesLeft == 1) {
4041 Value = DAG.getLoad(MVT::i8, Chain,
4042 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4043 DAG.getConstant(Offset, SrcVT)),
4045 Chain = Value.getValue(1);
4046 Chain = DAG.getStore(Chain, Value,
4047 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4048 DAG.getConstant(Offset, DstVT)),
4057 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
4058 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4059 SDOperand TheOp = Op.getOperand(0);
4060 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
4061 if (Subtarget->is64Bit()) {
4062 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4063 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
4064 MVT::i64, Copy1.getValue(2));
4065 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
4066 DAG.getConstant(32, MVT::i8));
4068 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
4071 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4072 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
4075 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4076 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
4077 MVT::i32, Copy1.getValue(2));
4078 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
4079 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
4080 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
4083 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4084 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4086 if (!Subtarget->is64Bit()) {
4087 // vastart just stores the address of the VarArgsFrameIndex slot into the
4088 // memory location argument.
4089 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4090 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4095 // gp_offset (0 - 6 * 8)
4096 // fp_offset (48 - 48 + 8 * 16)
4097 // overflow_arg_area (point to parameters coming in memory).
4099 SmallVector<SDOperand, 8> MemOps;
4100 SDOperand FIN = Op.getOperand(1);
4102 SDOperand Store = DAG.getStore(Op.getOperand(0),
4103 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4104 FIN, SV->getValue(), SV->getOffset());
4105 MemOps.push_back(Store);
4108 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4109 DAG.getConstant(4, getPointerTy()));
4110 Store = DAG.getStore(Op.getOperand(0),
4111 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4112 FIN, SV->getValue(), SV->getOffset());
4113 MemOps.push_back(Store);
4115 // Store ptr to overflow_arg_area
4116 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4117 DAG.getConstant(4, getPointerTy()));
4118 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4119 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4121 MemOps.push_back(Store);
4123 // Store ptr to reg_save_area.
4124 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
4125 DAG.getConstant(8, getPointerTy()));
4126 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4127 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4129 MemOps.push_back(Store);
4130 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4133 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4134 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4135 SDOperand Chain = Op.getOperand(0);
4136 SDOperand DstPtr = Op.getOperand(1);
4137 SDOperand SrcPtr = Op.getOperand(2);
4138 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4139 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4141 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4142 SrcSV->getValue(), SrcSV->getOffset());
4143 Chain = SrcPtr.getValue(1);
4144 for (unsigned i = 0; i < 3; ++i) {
4145 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4146 SrcSV->getValue(), SrcSV->getOffset());
4147 Chain = Val.getValue(1);
4148 Chain = DAG.getStore(Chain, Val, DstPtr,
4149 DstSV->getValue(), DstSV->getOffset());
4152 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4153 DAG.getConstant(8, getPointerTy()));
4154 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4155 DAG.getConstant(8, getPointerTy()));
4161 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4162 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4164 default: return SDOperand(); // Don't custom lower most intrinsics.
4165 // Comparison intrinsics.
4166 case Intrinsic::x86_sse_comieq_ss:
4167 case Intrinsic::x86_sse_comilt_ss:
4168 case Intrinsic::x86_sse_comile_ss:
4169 case Intrinsic::x86_sse_comigt_ss:
4170 case Intrinsic::x86_sse_comige_ss:
4171 case Intrinsic::x86_sse_comineq_ss:
4172 case Intrinsic::x86_sse_ucomieq_ss:
4173 case Intrinsic::x86_sse_ucomilt_ss:
4174 case Intrinsic::x86_sse_ucomile_ss:
4175 case Intrinsic::x86_sse_ucomigt_ss:
4176 case Intrinsic::x86_sse_ucomige_ss:
4177 case Intrinsic::x86_sse_ucomineq_ss:
4178 case Intrinsic::x86_sse2_comieq_sd:
4179 case Intrinsic::x86_sse2_comilt_sd:
4180 case Intrinsic::x86_sse2_comile_sd:
4181 case Intrinsic::x86_sse2_comigt_sd:
4182 case Intrinsic::x86_sse2_comige_sd:
4183 case Intrinsic::x86_sse2_comineq_sd:
4184 case Intrinsic::x86_sse2_ucomieq_sd:
4185 case Intrinsic::x86_sse2_ucomilt_sd:
4186 case Intrinsic::x86_sse2_ucomile_sd:
4187 case Intrinsic::x86_sse2_ucomigt_sd:
4188 case Intrinsic::x86_sse2_ucomige_sd:
4189 case Intrinsic::x86_sse2_ucomineq_sd: {
4191 ISD::CondCode CC = ISD::SETCC_INVALID;
4194 case Intrinsic::x86_sse_comieq_ss:
4195 case Intrinsic::x86_sse2_comieq_sd:
4199 case Intrinsic::x86_sse_comilt_ss:
4200 case Intrinsic::x86_sse2_comilt_sd:
4204 case Intrinsic::x86_sse_comile_ss:
4205 case Intrinsic::x86_sse2_comile_sd:
4209 case Intrinsic::x86_sse_comigt_ss:
4210 case Intrinsic::x86_sse2_comigt_sd:
4214 case Intrinsic::x86_sse_comige_ss:
4215 case Intrinsic::x86_sse2_comige_sd:
4219 case Intrinsic::x86_sse_comineq_ss:
4220 case Intrinsic::x86_sse2_comineq_sd:
4224 case Intrinsic::x86_sse_ucomieq_ss:
4225 case Intrinsic::x86_sse2_ucomieq_sd:
4226 Opc = X86ISD::UCOMI;
4229 case Intrinsic::x86_sse_ucomilt_ss:
4230 case Intrinsic::x86_sse2_ucomilt_sd:
4231 Opc = X86ISD::UCOMI;
4234 case Intrinsic::x86_sse_ucomile_ss:
4235 case Intrinsic::x86_sse2_ucomile_sd:
4236 Opc = X86ISD::UCOMI;
4239 case Intrinsic::x86_sse_ucomigt_ss:
4240 case Intrinsic::x86_sse2_ucomigt_sd:
4241 Opc = X86ISD::UCOMI;
4244 case Intrinsic::x86_sse_ucomige_ss:
4245 case Intrinsic::x86_sse2_ucomige_sd:
4246 Opc = X86ISD::UCOMI;
4249 case Intrinsic::x86_sse_ucomineq_ss:
4250 case Intrinsic::x86_sse2_ucomineq_sd:
4251 Opc = X86ISD::UCOMI;
4257 SDOperand LHS = Op.getOperand(1);
4258 SDOperand RHS = Op.getOperand(2);
4259 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4261 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4262 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4263 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4264 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4265 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4266 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4267 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4272 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4273 // Depths > 0 not supported yet!
4274 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4277 // Just load the return address
4278 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4279 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4282 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4283 // Depths > 0 not supported yet!
4284 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4287 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4288 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4289 DAG.getConstant(4, getPointerTy()));
4292 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
4293 SelectionDAG &DAG) {
4294 // Is not yet supported on x86-64
4295 if (Subtarget->is64Bit())
4298 return DAG.getConstant(8, getPointerTy());
4301 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
4303 assert(!Subtarget->is64Bit() &&
4304 "Lowering of eh_return builtin is not supported yet on x86-64");
4306 MachineFunction &MF = DAG.getMachineFunction();
4307 SDOperand Chain = Op.getOperand(0);
4308 SDOperand Offset = Op.getOperand(1);
4309 SDOperand Handler = Op.getOperand(2);
4311 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
4314 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
4315 DAG.getConstant(-4UL, getPointerTy()));
4316 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
4317 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
4318 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
4319 MF.addLiveOut(X86::ECX);
4321 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
4322 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
4325 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
4326 SelectionDAG &DAG) {
4327 SDOperand Root = Op.getOperand(0);
4328 SDOperand Trmp = Op.getOperand(1); // trampoline
4329 SDOperand FPtr = Op.getOperand(2); // nested function
4330 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
4332 SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4));
4334 if (Subtarget->is64Bit()) {
4335 return SDOperand(); // not yet supported
4337 Function *Func = (Function *)
4338 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
4339 unsigned CC = Func->getCallingConv();
4344 assert(0 && "Unsupported calling convention");
4345 case CallingConv::C:
4346 case CallingConv::Fast:
4347 case CallingConv::X86_StdCall: {
4348 // Pass 'nest' parameter in ECX.
4349 // Must be kept in sync with X86CallingConv.td
4352 // Check that ECX wasn't needed by an 'inreg' parameter.
4353 const FunctionType *FTy = Func->getFunctionType();
4354 const ParamAttrsList *Attrs = FTy->getParamAttrs();
4356 if (Attrs && !Func->isVarArg()) {
4357 unsigned InRegCount = 0;
4360 for (FunctionType::param_iterator I = FTy->param_begin(),
4361 E = FTy->param_end(); I != E; ++I, ++Idx)
4362 if (Attrs->paramHasAttr(Idx, ParamAttr::InReg))
4363 // FIXME: should only count parameters that are lowered to integers.
4364 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
4366 if (InRegCount > 2) {
4367 cerr << "Nest register in use - reduce number of inreg parameters!\n";
4373 case CallingConv::X86_FastCall:
4374 // Pass 'nest' parameter in EAX.
4375 // Must be kept in sync with X86CallingConv.td
4380 const X86InstrInfo *TII =
4381 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
4383 SDOperand OutChains[4];
4384 SDOperand Addr, Disp;
4386 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
4387 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
4389 unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
4390 unsigned char N86Reg = ((X86RegisterInfo&)RegInfo).getX86RegNum(NestReg);
4391 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
4392 Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
4394 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
4395 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4396 TrmpSV->getOffset() + 1, false, 1);
4398 unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
4399 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
4400 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
4401 TrmpSV->getValue() + 5, TrmpSV->getOffset());
4403 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
4404 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(),
4405 TrmpSV->getOffset() + 6, false, 1);
4408 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
4409 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
4413 /// LowerOperation - Provide custom lowering hooks for some operations.
4415 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4416 switch (Op.getOpcode()) {
4417 default: assert(0 && "Should not custom lower this!");
4418 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4419 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4420 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4421 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4422 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4423 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4424 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4425 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4426 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4427 case ISD::SHL_PARTS:
4428 case ISD::SRA_PARTS:
4429 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4430 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4431 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4432 case ISD::FABS: return LowerFABS(Op, DAG);
4433 case ISD::FNEG: return LowerFNEG(Op, DAG);
4434 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4435 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4436 case ISD::SELECT: return LowerSELECT(Op, DAG);
4437 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4438 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4439 case ISD::CALL: return LowerCALL(Op, DAG);
4440 case ISD::RET: return LowerRET(Op, DAG);
4441 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4442 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4443 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4444 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4445 case ISD::VASTART: return LowerVASTART(Op, DAG);
4446 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
4447 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4448 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4449 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4450 case ISD::FRAME_TO_ARGS_OFFSET:
4451 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
4452 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
4453 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
4454 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4459 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4461 default: return NULL;
4462 case X86ISD::SHLD: return "X86ISD::SHLD";
4463 case X86ISD::SHRD: return "X86ISD::SHRD";
4464 case X86ISD::FAND: return "X86ISD::FAND";
4465 case X86ISD::FOR: return "X86ISD::FOR";
4466 case X86ISD::FXOR: return "X86ISD::FXOR";
4467 case X86ISD::FSRL: return "X86ISD::FSRL";
4468 case X86ISD::FILD: return "X86ISD::FILD";
4469 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4470 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4471 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4472 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4473 case X86ISD::FLD: return "X86ISD::FLD";
4474 case X86ISD::FST: return "X86ISD::FST";
4475 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4476 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4477 case X86ISD::CALL: return "X86ISD::CALL";
4478 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4479 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4480 case X86ISD::CMP: return "X86ISD::CMP";
4481 case X86ISD::COMI: return "X86ISD::COMI";
4482 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4483 case X86ISD::SETCC: return "X86ISD::SETCC";
4484 case X86ISD::CMOV: return "X86ISD::CMOV";
4485 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4486 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4487 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4488 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4489 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4490 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4491 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4492 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4493 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4494 case X86ISD::FMAX: return "X86ISD::FMAX";
4495 case X86ISD::FMIN: return "X86ISD::FMIN";
4496 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
4497 case X86ISD::FRCP: return "X86ISD::FRCP";
4498 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
4499 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
4500 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
4504 // isLegalAddressingMode - Return true if the addressing mode represented
4505 // by AM is legal for this target, for a load/store of the specified type.
4506 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
4507 const Type *Ty) const {
4508 // X86 supports extremely general addressing modes.
4510 // X86 allows a sign-extended 32-bit immediate field as a displacement.
4511 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
4515 // We can only fold this if we don't need an extra load.
4516 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
4519 // X86-64 only supports addr of globals in small code model.
4520 if (Subtarget->is64Bit()) {
4521 if (getTargetMachine().getCodeModel() != CodeModel::Small)
4523 // If lower 4G is not available, then we must use rip-relative addressing.
4524 if (AM.BaseOffs || AM.Scale > 1)
4535 // These scales always work.
4540 // These scales are formed with basereg+scalereg. Only accept if there is
4545 default: // Other stuff never works.
4553 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4554 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4555 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4556 /// are assumed to be legal.
4558 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4559 // Only do shuffles on 128-bit vector types for now.
4560 if (MVT::getSizeInBits(VT) == 64) return false;
4561 return (Mask.Val->getNumOperands() <= 4 ||
4562 isIdentityMask(Mask.Val) ||
4563 isIdentityMask(Mask.Val, true) ||
4564 isSplatMask(Mask.Val) ||
4565 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4566 X86::isUNPCKLMask(Mask.Val) ||
4567 X86::isUNPCKHMask(Mask.Val) ||
4568 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4569 X86::isUNPCKH_v_undef_Mask(Mask.Val));
4572 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4574 SelectionDAG &DAG) const {
4575 unsigned NumElts = BVOps.size();
4576 // Only do shuffles on 128-bit vector types for now.
4577 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4578 if (NumElts == 2) return true;
4580 return (isMOVLMask(&BVOps[0], 4) ||
4581 isCommutedMOVL(&BVOps[0], 4, true) ||
4582 isSHUFPMask(&BVOps[0], 4) ||
4583 isCommutedSHUFP(&BVOps[0], 4));
4588 //===----------------------------------------------------------------------===//
4589 // X86 Scheduler Hooks
4590 //===----------------------------------------------------------------------===//
4593 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4594 MachineBasicBlock *BB) {
4595 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4596 switch (MI->getOpcode()) {
4597 default: assert(false && "Unexpected instr type to insert");
4598 case X86::CMOV_FR32:
4599 case X86::CMOV_FR64:
4600 case X86::CMOV_V4F32:
4601 case X86::CMOV_V2F64:
4602 case X86::CMOV_V2I64: {
4603 // To "insert" a SELECT_CC instruction, we actually have to insert the
4604 // diamond control-flow pattern. The incoming instruction knows the
4605 // destination vreg to set, the condition code register to branch on, the
4606 // true/false values to select between, and a branch opcode to use.
4607 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4608 ilist<MachineBasicBlock>::iterator It = BB;
4614 // cmpTY ccX, r1, r2
4616 // fallthrough --> copy0MBB
4617 MachineBasicBlock *thisMBB = BB;
4618 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4619 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4621 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4622 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4623 MachineFunction *F = BB->getParent();
4624 F->getBasicBlockList().insert(It, copy0MBB);
4625 F->getBasicBlockList().insert(It, sinkMBB);
4626 // Update machine-CFG edges by first adding all successors of the current
4627 // block to the new block which will contain the Phi node for the select.
4628 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4629 e = BB->succ_end(); i != e; ++i)
4630 sinkMBB->addSuccessor(*i);
4631 // Next, remove all successors of the current block, and add the true
4632 // and fallthrough blocks as its successors.
4633 while(!BB->succ_empty())
4634 BB->removeSuccessor(BB->succ_begin());
4635 BB->addSuccessor(copy0MBB);
4636 BB->addSuccessor(sinkMBB);
4639 // %FalseValue = ...
4640 // # fallthrough to sinkMBB
4643 // Update machine-CFG edges
4644 BB->addSuccessor(sinkMBB);
4647 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4650 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4651 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4652 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4654 delete MI; // The pseudo instruction is gone now.
4658 case X86::FP32_TO_INT16_IN_MEM:
4659 case X86::FP32_TO_INT32_IN_MEM:
4660 case X86::FP32_TO_INT64_IN_MEM:
4661 case X86::FP64_TO_INT16_IN_MEM:
4662 case X86::FP64_TO_INT32_IN_MEM:
4663 case X86::FP64_TO_INT64_IN_MEM:
4664 case X86::FP80_TO_INT16_IN_MEM:
4665 case X86::FP80_TO_INT32_IN_MEM:
4666 case X86::FP80_TO_INT64_IN_MEM: {
4667 // Change the floating point control register to use "round towards zero"
4668 // mode when truncating to an integer value.
4669 MachineFunction *F = BB->getParent();
4670 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4671 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4673 // Load the old value of the high byte of the control word...
4675 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4676 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4678 // Set the high part to be round to zero...
4679 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4682 // Reload the modified control word now...
4683 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4685 // Restore the memory image of control word to original value
4686 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4689 // Get the X86 opcode to use.
4691 switch (MI->getOpcode()) {
4692 default: assert(0 && "illegal opcode!");
4693 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
4694 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
4695 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
4696 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
4697 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
4698 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
4699 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
4700 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
4701 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
4705 MachineOperand &Op = MI->getOperand(0);
4706 if (Op.isRegister()) {
4707 AM.BaseType = X86AddressMode::RegBase;
4708 AM.Base.Reg = Op.getReg();
4710 AM.BaseType = X86AddressMode::FrameIndexBase;
4711 AM.Base.FrameIndex = Op.getFrameIndex();
4713 Op = MI->getOperand(1);
4714 if (Op.isImmediate())
4715 AM.Scale = Op.getImm();
4716 Op = MI->getOperand(2);
4717 if (Op.isImmediate())
4718 AM.IndexReg = Op.getImm();
4719 Op = MI->getOperand(3);
4720 if (Op.isGlobalAddress()) {
4721 AM.GV = Op.getGlobal();
4723 AM.Disp = Op.getImm();
4725 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4726 .addReg(MI->getOperand(4).getReg());
4728 // Reload the original control word now.
4729 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4731 delete MI; // The pseudo instruction is gone now.
4737 //===----------------------------------------------------------------------===//
4738 // X86 Optimization Hooks
4739 //===----------------------------------------------------------------------===//
4741 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4743 uint64_t &KnownZero,
4745 const SelectionDAG &DAG,
4746 unsigned Depth) const {
4747 unsigned Opc = Op.getOpcode();
4748 assert((Opc >= ISD::BUILTIN_OP_END ||
4749 Opc == ISD::INTRINSIC_WO_CHAIN ||
4750 Opc == ISD::INTRINSIC_W_CHAIN ||
4751 Opc == ISD::INTRINSIC_VOID) &&
4752 "Should use MaskedValueIsZero if you don't know whether Op"
4753 " is a target node!");
4755 KnownZero = KnownOne = 0; // Don't know anything.
4759 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4764 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4765 /// element of the result of the vector shuffle.
4766 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4767 MVT::ValueType VT = N->getValueType(0);
4768 SDOperand PermMask = N->getOperand(2);
4769 unsigned NumElems = PermMask.getNumOperands();
4770 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4772 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4774 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
4775 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4776 SDOperand Idx = PermMask.getOperand(i);
4777 if (Idx.getOpcode() == ISD::UNDEF)
4778 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
4779 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4784 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4785 /// node is a GlobalAddress + an offset.
4786 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4787 unsigned Opc = N->getOpcode();
4788 if (Opc == X86ISD::Wrapper) {
4789 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4790 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4793 } else if (Opc == ISD::ADD) {
4794 SDOperand N1 = N->getOperand(0);
4795 SDOperand N2 = N->getOperand(1);
4796 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4797 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4799 Offset += V->getSignExtended();
4802 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4803 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4805 Offset += V->getSignExtended();
4813 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4815 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4816 MachineFrameInfo *MFI) {
4817 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4820 SDOperand Loc = N->getOperand(1);
4821 SDOperand BaseLoc = Base->getOperand(1);
4822 if (Loc.getOpcode() == ISD::FrameIndex) {
4823 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4825 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
4826 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4827 int FS = MFI->getObjectSize(FI);
4828 int BFS = MFI->getObjectSize(BFI);
4829 if (FS != BFS || FS != Size) return false;
4830 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4832 GlobalValue *GV1 = NULL;
4833 GlobalValue *GV2 = NULL;
4834 int64_t Offset1 = 0;
4835 int64_t Offset2 = 0;
4836 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4837 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4838 if (isGA1 && isGA2 && GV1 == GV2)
4839 return Offset1 == (Offset2 + Dist*Size);
4845 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4846 const X86Subtarget *Subtarget) {
4849 if (isGAPlusOffset(Base, GV, Offset))
4850 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4852 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4853 int BFI = cast<FrameIndexSDNode>(Base)->getIndex();
4855 // Fixed objects do not specify alignment, however the offsets are known.
4856 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4857 (MFI->getObjectOffset(BFI) % 16) == 0);
4859 return MFI->getObjectAlignment(BFI) >= 16;
4865 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4866 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4867 /// if the load addresses are consecutive, non-overlapping, and in the right
4869 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4870 const X86Subtarget *Subtarget) {
4871 MachineFunction &MF = DAG.getMachineFunction();
4872 MachineFrameInfo *MFI = MF.getFrameInfo();
4873 MVT::ValueType VT = N->getValueType(0);
4874 MVT::ValueType EVT = MVT::getVectorElementType(VT);
4875 SDOperand PermMask = N->getOperand(2);
4876 int NumElems = (int)PermMask.getNumOperands();
4877 SDNode *Base = NULL;
4878 for (int i = 0; i < NumElems; ++i) {
4879 SDOperand Idx = PermMask.getOperand(i);
4880 if (Idx.getOpcode() == ISD::UNDEF) {
4881 if (!Base) return SDOperand();
4884 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4885 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4889 else if (!isConsecutiveLoad(Arg.Val, Base,
4890 i, MVT::getSizeInBits(EVT)/8,MFI))
4895 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4896 LoadSDNode *LD = cast<LoadSDNode>(Base);
4898 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4899 LD->getSrcValueOffset(), LD->isVolatile());
4901 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4902 LD->getSrcValueOffset(), LD->isVolatile(),
4903 LD->getAlignment());
4907 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4908 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4909 const X86Subtarget *Subtarget) {
4910 SDOperand Cond = N->getOperand(0);
4912 // If we have SSE[12] support, try to form min/max nodes.
4913 if (Subtarget->hasSSE2() &&
4914 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4915 if (Cond.getOpcode() == ISD::SETCC) {
4916 // Get the LHS/RHS of the select.
4917 SDOperand LHS = N->getOperand(1);
4918 SDOperand RHS = N->getOperand(2);
4919 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4921 unsigned Opcode = 0;
4922 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4925 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4928 if (!UnsafeFPMath) break;
4930 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4932 Opcode = X86ISD::FMIN;
4935 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4938 if (!UnsafeFPMath) break;
4940 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4942 Opcode = X86ISD::FMAX;
4945 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4948 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4951 if (!UnsafeFPMath) break;
4953 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4955 Opcode = X86ISD::FMIN;
4958 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4961 if (!UnsafeFPMath) break;
4963 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4965 Opcode = X86ISD::FMAX;
4971 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4980 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4981 DAGCombinerInfo &DCI) const {
4982 SelectionDAG &DAG = DCI.DAG;
4983 switch (N->getOpcode()) {
4985 case ISD::VECTOR_SHUFFLE:
4986 return PerformShuffleCombine(N, DAG, Subtarget);
4988 return PerformSELECTCombine(N, DAG, Subtarget);
4994 //===----------------------------------------------------------------------===//
4995 // X86 Inline Assembly Support
4996 //===----------------------------------------------------------------------===//
4998 /// getConstraintType - Given a constraint letter, return the type of
4999 /// constraint it is for this target.
5000 X86TargetLowering::ConstraintType
5001 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
5002 if (Constraint.size() == 1) {
5003 switch (Constraint[0]) {
5012 return C_RegisterClass;
5017 return TargetLowering::getConstraintType(Constraint);
5020 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5021 /// vector. If it is invalid, don't add anything to Ops.
5022 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
5024 std::vector<SDOperand>&Ops,
5025 SelectionDAG &DAG) {
5026 SDOperand Result(0, 0);
5028 switch (Constraint) {
5031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5032 if (C->getValue() <= 31) {
5033 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5039 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5040 if (C->getValue() <= 255) {
5041 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5047 // Literal immediates are always ok.
5048 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
5049 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
5053 // If we are in non-pic codegen mode, we allow the address of a global (with
5054 // an optional displacement) to be used with 'i'.
5055 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
5058 // Match either (GA) or (GA+C)
5060 Offset = GA->getOffset();
5061 } else if (Op.getOpcode() == ISD::ADD) {
5062 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5063 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5065 Offset = GA->getOffset()+C->getValue();
5067 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5068 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5070 Offset = GA->getOffset()+C->getValue();
5077 // If addressing this global requires a load (e.g. in PIC mode), we can't
5079 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
5083 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5089 // Otherwise, not valid for this mode.
5095 Ops.push_back(Result);
5098 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5101 std::vector<unsigned> X86TargetLowering::
5102 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5103 MVT::ValueType VT) const {
5104 if (Constraint.size() == 1) {
5105 // FIXME: not handling fp-stack yet!
5106 switch (Constraint[0]) { // GCC X86 Constraint Letters
5107 default: break; // Unknown constraint letter
5108 case 'A': // EAX/EDX
5109 if (VT == MVT::i32 || VT == MVT::i64)
5110 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5112 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5115 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5116 else if (VT == MVT::i16)
5117 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5118 else if (VT == MVT::i8)
5119 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5124 return std::vector<unsigned>();
5127 std::pair<unsigned, const TargetRegisterClass*>
5128 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5129 MVT::ValueType VT) const {
5130 // First, see if this is a constraint that directly corresponds to an LLVM
5132 if (Constraint.size() == 1) {
5133 // GCC Constraint Letters
5134 switch (Constraint[0]) {
5136 case 'r': // GENERAL_REGS
5137 case 'R': // LEGACY_REGS
5138 case 'l': // INDEX_REGS
5139 if (VT == MVT::i64 && Subtarget->is64Bit())
5140 return std::make_pair(0U, X86::GR64RegisterClass);
5142 return std::make_pair(0U, X86::GR32RegisterClass);
5143 else if (VT == MVT::i16)
5144 return std::make_pair(0U, X86::GR16RegisterClass);
5145 else if (VT == MVT::i8)
5146 return std::make_pair(0U, X86::GR8RegisterClass);
5148 case 'y': // MMX_REGS if MMX allowed.
5149 if (!Subtarget->hasMMX()) break;
5150 return std::make_pair(0U, X86::VR64RegisterClass);
5152 case 'Y': // SSE_REGS if SSE2 allowed
5153 if (!Subtarget->hasSSE2()) break;
5155 case 'x': // SSE_REGS if SSE1 allowed
5156 if (!Subtarget->hasSSE1()) break;
5160 // Scalar SSE types.
5163 return std::make_pair(0U, X86::FR32RegisterClass);
5166 return std::make_pair(0U, X86::FR64RegisterClass);
5174 return std::make_pair(0U, X86::VR128RegisterClass);
5180 // Use the default implementation in TargetLowering to convert the register
5181 // constraint into a member of a register class.
5182 std::pair<unsigned, const TargetRegisterClass*> Res;
5183 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5185 // Not found as a standard register?
5186 if (Res.second == 0) {
5187 // GCC calls "st(0)" just plain "st".
5188 if (StringsEqualNoCase("{st}", Constraint)) {
5189 Res.first = X86::ST0;
5190 Res.second = X86::RSTRegisterClass;
5196 // Otherwise, check to see if this is a register class of the wrong value
5197 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5198 // turn into {ax},{dx}.
5199 if (Res.second->hasType(VT))
5200 return Res; // Correct type already, nothing to do.
5202 // All of the single-register GCC register classes map their values onto
5203 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5204 // really want an 8-bit or 32-bit register, map to the appropriate register
5205 // class and return the appropriate register.
5206 if (Res.second != X86::GR16RegisterClass)
5209 if (VT == MVT::i8) {
5210 unsigned DestReg = 0;
5211 switch (Res.first) {
5213 case X86::AX: DestReg = X86::AL; break;
5214 case X86::DX: DestReg = X86::DL; break;
5215 case X86::CX: DestReg = X86::CL; break;
5216 case X86::BX: DestReg = X86::BL; break;
5219 Res.first = DestReg;
5220 Res.second = Res.second = X86::GR8RegisterClass;
5222 } else if (VT == MVT::i32) {
5223 unsigned DestReg = 0;
5224 switch (Res.first) {
5226 case X86::AX: DestReg = X86::EAX; break;
5227 case X86::DX: DestReg = X86::EDX; break;
5228 case X86::CX: DestReg = X86::ECX; break;
5229 case X86::BX: DestReg = X86::EBX; break;
5230 case X86::SI: DestReg = X86::ESI; break;
5231 case X86::DI: DestReg = X86::EDI; break;
5232 case X86::BP: DestReg = X86::EBP; break;
5233 case X86::SP: DestReg = X86::ESP; break;
5236 Res.first = DestReg;
5237 Res.second = Res.second = X86::GR32RegisterClass;
5239 } else if (VT == MVT::i64) {
5240 unsigned DestReg = 0;
5241 switch (Res.first) {
5243 case X86::AX: DestReg = X86::RAX; break;
5244 case X86::DX: DestReg = X86::RDX; break;
5245 case X86::CX: DestReg = X86::RCX; break;
5246 case X86::BX: DestReg = X86::RBX; break;
5247 case X86::SI: DestReg = X86::RSI; break;
5248 case X86::DI: DestReg = X86::RDI; break;
5249 case X86::BP: DestReg = X86::RBP; break;
5250 case X86::SP: DestReg = X86::RSP; break;
5253 Res.first = DestReg;
5254 Res.second = Res.second = X86::GR64RegisterClass;