1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/EHPersonalities.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
427 if (Subtarget->is64Bit()) {
428 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
432 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
433 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
434 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
435 // support continuation, user-level threading, and etc.. As a result, no
436 // other SjLj exception interfaces are implemented and please don't build
437 // your own exception handling based on them.
438 // LLVM/Clang supports zero-cost DWARF exception handling.
439 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
440 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
443 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
449 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
455 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
456 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
458 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
459 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
468 if (Subtarget->hasSSE1())
469 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
471 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
473 // Expand certain atomics
474 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
475 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
480 if (Subtarget->hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
484 // FIXME - use subtarget debug flags
485 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
486 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
487 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
494 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
497 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
500 setOperationAction(ISD::VASTART , MVT::Other, Custom);
501 setOperationAction(ISD::VAEND , MVT::Other, Expand);
502 if (Subtarget->is64Bit()) {
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
835 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
836 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
837 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
839 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
840 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
841 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
845 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
853 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
858 // ISD::CTTZ v2i64 - scalarization is faster.
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
861 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
862 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
866 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
867 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
868 setOperationAction(ISD::VSELECT, VT, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
872 // We support custom legalizing of sext and anyext loads for specific
873 // memory vector types which we can load as a scalar (or sequence of
874 // scalars) and extend in-register to a legal 128-bit vector type. For sext
875 // loads these must work with a single scalar load.
876 for (MVT VT : MVT::integer_vector_valuetypes()) {
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
902 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (Subtarget->hasXOP()) {
1042 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1048 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1049 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1052 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1091 // even though v8i16 is a legal type.
1092 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1093 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1098 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 for (MVT VT : MVT::fp_vector_valuetypes())
1104 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1124 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1127 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1130 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1133 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1137 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1146 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1151 if (Subtarget->hasAnyFMA()) {
1152 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1155 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1156 setOperationAction(ISD::FMA, MVT::f32, Legal);
1157 setOperationAction(ISD::FMA, MVT::f64, Legal);
1160 if (Subtarget->hasInt256()) {
1161 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1179 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1184 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1187 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1190 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1194 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1195 // when we have a 256bit-wide blend with immediate.
1196 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1198 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1231 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1234 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1237 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1242 // In the customized shift lowering, the legal cases in AVX2 will be
1244 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1248 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1253 // Custom lower several nodes for 256-bit types.
1254 for (MVT VT : MVT::vector_valuetypes()) {
1255 if (VT.getScalarSizeInBits() >= 32) {
1256 setOperationAction(ISD::MLOAD, VT, Legal);
1257 setOperationAction(ISD::MSTORE, VT, Legal);
1259 // Extract subvector is special because the value type
1260 // (result) is 128-bit but the source is 256-bit wide.
1261 if (VT.is128BitVector()) {
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1264 // Do not attempt to custom lower other non-256-bit vectors
1265 if (!VT.is256BitVector())
1268 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1270 setOperationAction(ISD::VSELECT, VT, Custom);
1271 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1272 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1274 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1275 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1278 if (Subtarget->hasInt256())
1279 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1283 setOperationAction(ISD::AND, VT, Promote);
1284 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1285 setOperationAction(ISD::OR, VT, Promote);
1286 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1287 setOperationAction(ISD::XOR, VT, Promote);
1288 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1289 setOperationAction(ISD::LOAD, VT, Promote);
1290 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1291 setOperationAction(ISD::SELECT, VT, Promote);
1292 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1296 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1297 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1298 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1299 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1300 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1302 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1303 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1304 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1306 for (MVT VT : MVT::fp_vector_valuetypes())
1307 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1317 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1319 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1320 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1322 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1323 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1325 setOperationAction(ISD::XOR, MVT::i1, Legal);
1326 setOperationAction(ISD::OR, MVT::i1, Legal);
1327 setOperationAction(ISD::AND, MVT::i1, Legal);
1328 setOperationAction(ISD::SUB, MVT::i1, Custom);
1329 setOperationAction(ISD::ADD, MVT::i1, Custom);
1330 setOperationAction(ISD::MUL, MVT::i1, Custom);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1343 setOperationAction(ISD::FABS, MVT::v16f32, Custom);
1345 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1350 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1351 setOperationAction(ISD::FABS, MVT::v8f64, Custom);
1352 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1357 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1358 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1359 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1361 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1362 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1363 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1365 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1366 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1367 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1368 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1369 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1370 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1372 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1373 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1374 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1375 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1376 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1377 if (Subtarget->hasVLX()){
1378 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1379 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1380 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1381 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1382 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1384 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1385 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1386 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1387 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1388 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1390 setOperationAction(ISD::MLOAD, MVT::v8i32, Custom);
1391 setOperationAction(ISD::MLOAD, MVT::v8f32, Custom);
1392 setOperationAction(ISD::MSTORE, MVT::v8i32, Custom);
1393 setOperationAction(ISD::MSTORE, MVT::v8f32, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1397 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1399 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1400 if (Subtarget->hasDQI()) {
1401 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1402 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1407 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1408 if (Subtarget->hasVLX()) {
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1412 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1414 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1419 if (Subtarget->hasVLX()) {
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1429 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1435 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1441 if (Subtarget->hasDQI()) {
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1443 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1445 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1446 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1448 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1450 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1452 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1454 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1462 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1465 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1470 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1471 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1473 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1477 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1478 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1480 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1481 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1482 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1483 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1484 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1485 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1486 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1487 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1489 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1490 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1492 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1493 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1495 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1497 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1498 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1500 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1501 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1503 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1504 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1506 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1507 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1508 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1509 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1510 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1511 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1513 if (Subtarget->hasCDI()) {
1514 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1515 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1516 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1517 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1519 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1520 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1521 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1522 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1523 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1526 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1528 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1529 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1531 if (Subtarget->hasVLX()) {
1532 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1533 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1534 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1535 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1539 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1542 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1543 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1544 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1546 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1547 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1548 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1549 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1552 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1553 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1555 } // Subtarget->hasCDI()
1557 if (Subtarget->hasDQI()) {
1558 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1559 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1560 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1562 // Custom lower several nodes.
1563 for (MVT VT : MVT::vector_valuetypes()) {
1564 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1566 setOperationAction(ISD::AND, VT, Legal);
1567 setOperationAction(ISD::OR, VT, Legal);
1568 setOperationAction(ISD::XOR, VT, Legal);
1570 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1571 setOperationAction(ISD::MGATHER, VT, Custom);
1572 setOperationAction(ISD::MSCATTER, VT, Custom);
1574 // Extract subvector is special because the value type
1575 // (result) is 256/128-bit but the source is 512-bit wide.
1576 if (VT.is128BitVector() || VT.is256BitVector()) {
1577 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1579 if (VT.getVectorElementType() == MVT::i1)
1580 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1582 // Do not attempt to custom lower other non-512-bit vectors
1583 if (!VT.is512BitVector())
1586 if (EltSize >= 32) {
1587 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1588 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1589 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1590 setOperationAction(ISD::VSELECT, VT, Legal);
1591 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1592 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1593 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1594 setOperationAction(ISD::MLOAD, VT, Legal);
1595 setOperationAction(ISD::MSTORE, VT, Legal);
1598 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1599 setOperationAction(ISD::SELECT, VT, Promote);
1600 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1604 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1605 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1606 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1608 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1609 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1611 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1612 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1613 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1614 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1615 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1616 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1617 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1618 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1619 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1620 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1621 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1622 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1623 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1624 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1625 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1626 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1627 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1628 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1629 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1630 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1631 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1632 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1633 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1634 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1635 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1636 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1637 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1638 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1640 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1641 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1642 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1643 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1644 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1645 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1646 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1647 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1648 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1649 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1650 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1651 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1652 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1654 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1655 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1656 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1657 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1658 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1659 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1660 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1661 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1663 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1664 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1665 if (Subtarget->hasVLX())
1666 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1668 if (Subtarget->hasCDI()) {
1669 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1670 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1671 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1672 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1675 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1676 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1677 setOperationAction(ISD::VSELECT, VT, Legal);
1681 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1682 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1683 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1685 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1686 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1687 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1688 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1689 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1690 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1691 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1692 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1693 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1694 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1695 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1696 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1698 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1699 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1700 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1701 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1702 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1703 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1704 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1705 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1707 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1708 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1709 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1710 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1711 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1712 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1713 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1714 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1717 // We want to custom lower some of our intrinsics.
1718 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1719 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1720 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1721 if (!Subtarget->is64Bit()) {
1722 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1723 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1726 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1727 // handle type legalization for these operations here.
1729 // FIXME: We really should do custom legalization for addition and
1730 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1731 // than generic legalization for 64-bit multiplication-with-overflow, though.
1732 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1733 if (VT == MVT::i64 && !Subtarget->is64Bit())
1735 // Add/Sub/Mul with overflow operations are custom lowered.
1736 setOperationAction(ISD::SADDO, VT, Custom);
1737 setOperationAction(ISD::UADDO, VT, Custom);
1738 setOperationAction(ISD::SSUBO, VT, Custom);
1739 setOperationAction(ISD::USUBO, VT, Custom);
1740 setOperationAction(ISD::SMULO, VT, Custom);
1741 setOperationAction(ISD::UMULO, VT, Custom);
1744 if (!Subtarget->is64Bit()) {
1745 // These libcalls are not available in 32-bit.
1746 setLibcallName(RTLIB::SHL_I128, nullptr);
1747 setLibcallName(RTLIB::SRL_I128, nullptr);
1748 setLibcallName(RTLIB::SRA_I128, nullptr);
1751 // Combine sin / cos into one node or libcall if possible.
1752 if (Subtarget->hasSinCos()) {
1753 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1754 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1755 if (Subtarget->isTargetDarwin()) {
1756 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1757 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1758 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1759 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1763 if (Subtarget->isTargetWin64()) {
1764 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1765 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1766 setOperationAction(ISD::SREM, MVT::i128, Custom);
1767 setOperationAction(ISD::UREM, MVT::i128, Custom);
1768 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1769 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1772 // We have target-specific dag combine patterns for the following nodes:
1773 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1774 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1775 setTargetDAGCombine(ISD::BITCAST);
1776 setTargetDAGCombine(ISD::VSELECT);
1777 setTargetDAGCombine(ISD::SELECT);
1778 setTargetDAGCombine(ISD::SHL);
1779 setTargetDAGCombine(ISD::SRA);
1780 setTargetDAGCombine(ISD::SRL);
1781 setTargetDAGCombine(ISD::OR);
1782 setTargetDAGCombine(ISD::AND);
1783 setTargetDAGCombine(ISD::ADD);
1784 setTargetDAGCombine(ISD::FADD);
1785 setTargetDAGCombine(ISD::FSUB);
1786 setTargetDAGCombine(ISD::FNEG);
1787 setTargetDAGCombine(ISD::FMA);
1788 setTargetDAGCombine(ISD::SUB);
1789 setTargetDAGCombine(ISD::LOAD);
1790 setTargetDAGCombine(ISD::MLOAD);
1791 setTargetDAGCombine(ISD::STORE);
1792 setTargetDAGCombine(ISD::MSTORE);
1793 setTargetDAGCombine(ISD::TRUNCATE);
1794 setTargetDAGCombine(ISD::ZERO_EXTEND);
1795 setTargetDAGCombine(ISD::ANY_EXTEND);
1796 setTargetDAGCombine(ISD::SIGN_EXTEND);
1797 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1798 setTargetDAGCombine(ISD::SINT_TO_FP);
1799 setTargetDAGCombine(ISD::UINT_TO_FP);
1800 setTargetDAGCombine(ISD::SETCC);
1801 setTargetDAGCombine(ISD::BUILD_VECTOR);
1802 setTargetDAGCombine(ISD::MUL);
1803 setTargetDAGCombine(ISD::XOR);
1805 computeRegisterProperties(Subtarget->getRegisterInfo());
1807 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1808 MaxStoresPerMemsetOptSize = 8;
1809 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1810 MaxStoresPerMemcpyOptSize = 4;
1811 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1812 MaxStoresPerMemmoveOptSize = 4;
1813 setPrefLoopAlignment(4); // 2^4 bytes.
1815 // A predictable cmov does not hurt on an in-order CPU.
1816 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1817 PredictableSelectIsExpensive = !Subtarget->isAtom();
1818 EnableExtLdPromotion = true;
1819 setPrefFunctionAlignment(4); // 2^4 bytes.
1821 verifyIntrinsicTables();
1824 // This has so far only been implemented for 64-bit MachO.
1825 bool X86TargetLowering::useLoadStackGuardNode() const {
1826 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1829 TargetLoweringBase::LegalizeTypeAction
1830 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1831 if (ExperimentalVectorWideningLegalization &&
1832 VT.getVectorNumElements() != 1 &&
1833 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1834 return TypeWidenVector;
1836 return TargetLoweringBase::getPreferredVectorAction(VT);
1839 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1842 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1844 if (VT.isSimple()) {
1845 MVT VVT = VT.getSimpleVT();
1846 const unsigned NumElts = VVT.getVectorNumElements();
1847 const MVT EltVT = VVT.getVectorElementType();
1848 if (VVT.is512BitVector()) {
1849 if (Subtarget->hasAVX512())
1850 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1851 EltVT == MVT::f32 || EltVT == MVT::f64)
1853 case 8: return MVT::v8i1;
1854 case 16: return MVT::v16i1;
1856 if (Subtarget->hasBWI())
1857 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1859 case 32: return MVT::v32i1;
1860 case 64: return MVT::v64i1;
1864 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1865 if (Subtarget->hasVLX())
1866 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1867 EltVT == MVT::f32 || EltVT == MVT::f64)
1869 case 2: return MVT::v2i1;
1870 case 4: return MVT::v4i1;
1871 case 8: return MVT::v8i1;
1873 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1874 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1876 case 8: return MVT::v8i1;
1877 case 16: return MVT::v16i1;
1878 case 32: return MVT::v32i1;
1883 return VT.changeVectorElementTypeToInteger();
1886 /// Helper for getByValTypeAlignment to determine
1887 /// the desired ByVal argument alignment.
1888 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1891 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1892 if (VTy->getBitWidth() == 128)
1894 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1895 unsigned EltAlign = 0;
1896 getMaxByValAlign(ATy->getElementType(), EltAlign);
1897 if (EltAlign > MaxAlign)
1898 MaxAlign = EltAlign;
1899 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1900 for (auto *EltTy : STy->elements()) {
1901 unsigned EltAlign = 0;
1902 getMaxByValAlign(EltTy, EltAlign);
1903 if (EltAlign > MaxAlign)
1904 MaxAlign = EltAlign;
1911 /// Return the desired alignment for ByVal aggregate
1912 /// function arguments in the caller parameter area. For X86, aggregates
1913 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1914 /// are at 4-byte boundaries.
1915 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1916 const DataLayout &DL) const {
1917 if (Subtarget->is64Bit()) {
1918 // Max of 8 and alignment of type.
1919 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1926 if (Subtarget->hasSSE1())
1927 getMaxByValAlign(Ty, Align);
1931 /// Returns the target specific optimal type for load
1932 /// and store operations as a result of memset, memcpy, and memmove
1933 /// lowering. If DstAlign is zero that means it's safe to destination
1934 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1935 /// means there isn't a need to check it against alignment requirement,
1936 /// probably because the source does not need to be loaded. If 'IsMemset' is
1937 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1938 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1939 /// source is constant so it does not need to be loaded.
1940 /// It returns EVT::Other if the type should be determined using generic
1941 /// target-independent logic.
1943 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1944 unsigned DstAlign, unsigned SrcAlign,
1945 bool IsMemset, bool ZeroMemset,
1947 MachineFunction &MF) const {
1948 const Function *F = MF.getFunction();
1949 if ((!IsMemset || ZeroMemset) &&
1950 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1952 (!Subtarget->isUnalignedMem16Slow() ||
1953 ((DstAlign == 0 || DstAlign >= 16) &&
1954 (SrcAlign == 0 || SrcAlign >= 16)))) {
1956 // FIXME: Check if unaligned 32-byte accesses are slow.
1957 if (Subtarget->hasInt256())
1959 if (Subtarget->hasFp256())
1962 if (Subtarget->hasSSE2())
1964 if (Subtarget->hasSSE1())
1966 } else if (!MemcpyStrSrc && Size >= 8 &&
1967 !Subtarget->is64Bit() &&
1968 Subtarget->hasSSE2()) {
1969 // Do not use f64 to lower memcpy if source is string constant. It's
1970 // better to use i32 to avoid the loads.
1974 // This is a compromise. If we reach here, unaligned accesses may be slow on
1975 // this target. However, creating smaller, aligned accesses could be even
1976 // slower and would certainly be a lot more code.
1977 if (Subtarget->is64Bit() && Size >= 8)
1982 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1984 return X86ScalarSSEf32;
1985 else if (VT == MVT::f64)
1986 return X86ScalarSSEf64;
1991 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1996 switch (VT.getSizeInBits()) {
1998 // 8-byte and under are always assumed to be fast.
2002 *Fast = !Subtarget->isUnalignedMem16Slow();
2005 *Fast = !Subtarget->isUnalignedMem32Slow();
2007 // TODO: What about AVX-512 (512-bit) accesses?
2010 // Misaligned accesses of any size are always allowed.
2014 /// Return the entry encoding for a jump table in the
2015 /// current function. The returned value is a member of the
2016 /// MachineJumpTableInfo::JTEntryKind enum.
2017 unsigned X86TargetLowering::getJumpTableEncoding() const {
2018 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2020 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2021 Subtarget->isPICStyleGOT())
2022 return MachineJumpTableInfo::EK_Custom32;
2024 // Otherwise, use the normal jump table encoding heuristics.
2025 return TargetLowering::getJumpTableEncoding();
2028 bool X86TargetLowering::useSoftFloat() const {
2029 return Subtarget->useSoftFloat();
2033 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2034 const MachineBasicBlock *MBB,
2035 unsigned uid,MCContext &Ctx) const{
2036 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2037 Subtarget->isPICStyleGOT());
2038 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2040 return MCSymbolRefExpr::create(MBB->getSymbol(),
2041 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2044 /// Returns relocation base for the given PIC jumptable.
2045 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2046 SelectionDAG &DAG) const {
2047 if (!Subtarget->is64Bit())
2048 // This doesn't have SDLoc associated with it, but is not really the
2049 // same as a Register.
2050 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2051 getPointerTy(DAG.getDataLayout()));
2055 /// This returns the relocation base for the given PIC jumptable,
2056 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2057 const MCExpr *X86TargetLowering::
2058 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2059 MCContext &Ctx) const {
2060 // X86-64 uses RIP relative addressing based on the jump table label.
2061 if (Subtarget->isPICStyleRIPRel())
2062 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2064 // Otherwise, the reference is relative to the PIC base.
2065 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2068 std::pair<const TargetRegisterClass *, uint8_t>
2069 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2071 const TargetRegisterClass *RRC = nullptr;
2073 switch (VT.SimpleTy) {
2075 return TargetLowering::findRepresentativeClass(TRI, VT);
2076 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2077 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2080 RRC = &X86::VR64RegClass;
2082 case MVT::f32: case MVT::f64:
2083 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2084 case MVT::v4f32: case MVT::v2f64:
2085 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2087 RRC = &X86::VR128RegClass;
2090 return std::make_pair(RRC, Cost);
2093 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2094 unsigned &Offset) const {
2095 if (!Subtarget->isTargetLinux())
2098 if (Subtarget->is64Bit()) {
2099 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2101 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2113 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2114 if (!Subtarget->isTargetAndroid())
2115 return TargetLowering::getSafeStackPointerLocation(IRB);
2117 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2118 // definition of TLS_SLOT_SAFESTACK in
2119 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2120 unsigned AddressSpace, Offset;
2121 if (Subtarget->is64Bit()) {
2122 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2124 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2134 return ConstantExpr::getIntToPtr(
2135 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2136 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2139 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2140 unsigned DestAS) const {
2141 assert(SrcAS != DestAS && "Expected different address spaces!");
2143 return SrcAS < 256 && DestAS < 256;
2146 //===----------------------------------------------------------------------===//
2147 // Return Value Calling Convention Implementation
2148 //===----------------------------------------------------------------------===//
2150 #include "X86GenCallingConv.inc"
2152 bool X86TargetLowering::CanLowerReturn(
2153 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2154 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2155 SmallVector<CCValAssign, 16> RVLocs;
2156 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2157 return CCInfo.CheckReturn(Outs, RetCC_X86);
2160 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2161 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2166 X86TargetLowering::LowerReturn(SDValue Chain,
2167 CallingConv::ID CallConv, bool isVarArg,
2168 const SmallVectorImpl<ISD::OutputArg> &Outs,
2169 const SmallVectorImpl<SDValue> &OutVals,
2170 SDLoc dl, SelectionDAG &DAG) const {
2171 MachineFunction &MF = DAG.getMachineFunction();
2172 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2174 SmallVector<CCValAssign, 16> RVLocs;
2175 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2176 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2179 SmallVector<SDValue, 6> RetOps;
2180 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2181 // Operand #1 = Bytes To Pop
2182 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2185 // Copy the result values into the output registers.
2186 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2187 CCValAssign &VA = RVLocs[i];
2188 assert(VA.isRegLoc() && "Can only return in registers!");
2189 SDValue ValToCopy = OutVals[i];
2190 EVT ValVT = ValToCopy.getValueType();
2192 // Promote values to the appropriate types.
2193 if (VA.getLocInfo() == CCValAssign::SExt)
2194 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2195 else if (VA.getLocInfo() == CCValAssign::ZExt)
2196 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2197 else if (VA.getLocInfo() == CCValAssign::AExt) {
2198 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2199 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2201 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2203 else if (VA.getLocInfo() == CCValAssign::BCvt)
2204 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2206 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2207 "Unexpected FP-extend for return value.");
2209 // If this is x86-64, and we disabled SSE, we can't return FP values,
2210 // or SSE or MMX vectors.
2211 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2212 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2213 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2214 report_fatal_error("SSE register return with SSE disabled");
2216 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2217 // llvm-gcc has never done it right and no one has noticed, so this
2218 // should be OK for now.
2219 if (ValVT == MVT::f64 &&
2220 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2221 report_fatal_error("SSE2 register return with SSE2 disabled");
2223 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2224 // the RET instruction and handled by the FP Stackifier.
2225 if (VA.getLocReg() == X86::FP0 ||
2226 VA.getLocReg() == X86::FP1) {
2227 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2228 // change the value to the FP stack register class.
2229 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2230 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2231 RetOps.push_back(ValToCopy);
2232 // Don't emit a copytoreg.
2236 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2237 // which is returned in RAX / RDX.
2238 if (Subtarget->is64Bit()) {
2239 if (ValVT == MVT::x86mmx) {
2240 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2241 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2242 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2244 // If we don't have SSE2 available, convert to v4f32 so the generated
2245 // register is legal.
2246 if (!Subtarget->hasSSE2())
2247 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2252 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2253 Flag = Chain.getValue(1);
2254 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2257 // All x86 ABIs require that for returning structs by value we copy
2258 // the sret argument into %rax/%eax (depending on ABI) for the return.
2259 // We saved the argument into a virtual register in the entry block,
2260 // so now we copy the value out and into %rax/%eax.
2262 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2263 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2264 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2265 // either case FuncInfo->setSRetReturnReg() will have been called.
2266 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2267 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2268 getPointerTy(MF.getDataLayout()));
2271 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2272 X86::RAX : X86::EAX;
2273 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2274 Flag = Chain.getValue(1);
2276 // RAX/EAX now acts like a return value.
2278 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2281 RetOps[0] = Chain; // Update chain.
2283 // Add the flag if we have it.
2285 RetOps.push_back(Flag);
2287 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2290 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2291 if (N->getNumValues() != 1)
2293 if (!N->hasNUsesOfValue(1, 0))
2296 SDValue TCChain = Chain;
2297 SDNode *Copy = *N->use_begin();
2298 if (Copy->getOpcode() == ISD::CopyToReg) {
2299 // If the copy has a glue operand, we conservatively assume it isn't safe to
2300 // perform a tail call.
2301 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2303 TCChain = Copy->getOperand(0);
2304 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2307 bool HasRet = false;
2308 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2310 if (UI->getOpcode() != X86ISD::RET_FLAG)
2312 // If we are returning more than one value, we can definitely
2313 // not make a tail call see PR19530
2314 if (UI->getNumOperands() > 4)
2316 if (UI->getNumOperands() == 4 &&
2317 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2330 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2331 ISD::NodeType ExtendKind) const {
2333 // TODO: Is this also valid on 32-bit?
2334 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2335 ReturnMVT = MVT::i8;
2337 ReturnMVT = MVT::i32;
2339 EVT MinVT = getRegisterType(Context, ReturnMVT);
2340 return VT.bitsLT(MinVT) ? MinVT : VT;
2343 /// Lower the result values of a call into the
2344 /// appropriate copies out of appropriate physical registers.
2347 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2348 CallingConv::ID CallConv, bool isVarArg,
2349 const SmallVectorImpl<ISD::InputArg> &Ins,
2350 SDLoc dl, SelectionDAG &DAG,
2351 SmallVectorImpl<SDValue> &InVals) const {
2353 // Assign locations to each value returned by this call.
2354 SmallVector<CCValAssign, 16> RVLocs;
2355 bool Is64Bit = Subtarget->is64Bit();
2356 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2358 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2360 // Copy all of the result registers out of their specified physreg.
2361 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2362 CCValAssign &VA = RVLocs[i];
2363 EVT CopyVT = VA.getLocVT();
2365 // If this is x86-64, and we disabled SSE, we can't return FP values
2366 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2367 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2368 report_fatal_error("SSE register return with SSE disabled");
2371 // If we prefer to use the value in xmm registers, copy it out as f80 and
2372 // use a truncate to move it from fp stack reg to xmm reg.
2373 bool RoundAfterCopy = false;
2374 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2375 isScalarFPTypeInSSEReg(VA.getValVT())) {
2377 RoundAfterCopy = (CopyVT != VA.getLocVT());
2380 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2381 CopyVT, InFlag).getValue(1);
2382 SDValue Val = Chain.getValue(0);
2385 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2386 // This truncation won't change the value.
2387 DAG.getIntPtrConstant(1, dl));
2389 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2390 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2392 InFlag = Chain.getValue(2);
2393 InVals.push_back(Val);
2399 //===----------------------------------------------------------------------===//
2400 // C & StdCall & Fast Calling Convention implementation
2401 //===----------------------------------------------------------------------===//
2402 // StdCall calling convention seems to be standard for many Windows' API
2403 // routines and around. It differs from C calling convention just a little:
2404 // callee should clean up the stack, not caller. Symbols should be also
2405 // decorated in some fancy way :) It doesn't support any vector arguments.
2406 // For info on fast calling convention see Fast Calling Convention (tail call)
2407 // implementation LowerX86_32FastCCCallTo.
2409 /// CallIsStructReturn - Determines whether a call uses struct return
2411 enum StructReturnType {
2416 static StructReturnType
2417 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2419 return NotStructReturn;
2421 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2422 if (!Flags.isSRet())
2423 return NotStructReturn;
2424 if (Flags.isInReg())
2425 return RegStructReturn;
2426 return StackStructReturn;
2429 /// Determines whether a function uses struct return semantics.
2430 static StructReturnType
2431 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2433 return NotStructReturn;
2435 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2436 if (!Flags.isSRet())
2437 return NotStructReturn;
2438 if (Flags.isInReg())
2439 return RegStructReturn;
2440 return StackStructReturn;
2443 /// Make a copy of an aggregate at address specified by "Src" to address
2444 /// "Dst" with size and alignment information specified by the specific
2445 /// parameter attribute. The copy will be passed as a byval function parameter.
2447 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2448 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2450 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2452 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2453 /*isVolatile*/false, /*AlwaysInline=*/true,
2454 /*isTailCall*/false,
2455 MachinePointerInfo(), MachinePointerInfo());
2458 /// Return true if the calling convention is one that we can guarantee TCO for.
2459 static bool canGuaranteeTCO(CallingConv::ID CC) {
2460 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2461 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2464 /// Return true if we might ever do TCO for calls with this calling convention.
2465 static bool mayTailCallThisCC(CallingConv::ID CC) {
2467 // C calling conventions:
2468 case CallingConv::C:
2469 case CallingConv::X86_64_Win64:
2470 case CallingConv::X86_64_SysV:
2471 // Callee pop conventions:
2472 case CallingConv::X86_ThisCall:
2473 case CallingConv::X86_StdCall:
2474 case CallingConv::X86_VectorCall:
2475 case CallingConv::X86_FastCall:
2478 return canGuaranteeTCO(CC);
2482 /// Return true if the function is being made into a tailcall target by
2483 /// changing its ABI.
2484 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2485 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2488 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2490 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2491 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2495 CallingConv::ID CalleeCC = CS.getCallingConv();
2496 if (!mayTailCallThisCC(CalleeCC))
2503 X86TargetLowering::LowerMemArgument(SDValue Chain,
2504 CallingConv::ID CallConv,
2505 const SmallVectorImpl<ISD::InputArg> &Ins,
2506 SDLoc dl, SelectionDAG &DAG,
2507 const CCValAssign &VA,
2508 MachineFrameInfo *MFI,
2510 // Create the nodes corresponding to a load from this parameter slot.
2511 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2512 bool AlwaysUseMutable = shouldGuaranteeTCO(
2513 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2514 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2517 // If value is passed by pointer we have address passed instead of the value
2519 bool ExtendedInMem = VA.isExtInLoc() &&
2520 VA.getValVT().getScalarType() == MVT::i1;
2522 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2523 ValVT = VA.getLocVT();
2525 ValVT = VA.getValVT();
2527 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2528 // changed with more analysis.
2529 // In case of tail call optimization mark all arguments mutable. Since they
2530 // could be overwritten by lowering of arguments in case of a tail call.
2531 if (Flags.isByVal()) {
2532 unsigned Bytes = Flags.getByValSize();
2533 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2534 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2535 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2537 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2538 VA.getLocMemOffset(), isImmutable);
2539 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2540 SDValue Val = DAG.getLoad(
2541 ValVT, dl, Chain, FIN,
2542 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2544 return ExtendedInMem ?
2545 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2549 // FIXME: Get this from tablegen.
2550 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2551 const X86Subtarget *Subtarget) {
2552 assert(Subtarget->is64Bit());
2554 if (Subtarget->isCallingConvWin64(CallConv)) {
2555 static const MCPhysReg GPR64ArgRegsWin64[] = {
2556 X86::RCX, X86::RDX, X86::R8, X86::R9
2558 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2561 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2562 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2564 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2567 // FIXME: Get this from tablegen.
2568 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2569 CallingConv::ID CallConv,
2570 const X86Subtarget *Subtarget) {
2571 assert(Subtarget->is64Bit());
2572 if (Subtarget->isCallingConvWin64(CallConv)) {
2573 // The XMM registers which might contain var arg parameters are shadowed
2574 // in their paired GPR. So we only need to save the GPR to their home
2576 // TODO: __vectorcall will change this.
2580 const Function *Fn = MF.getFunction();
2581 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2582 bool isSoftFloat = Subtarget->useSoftFloat();
2583 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2584 "SSE register cannot be used when SSE is disabled!");
2585 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2586 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2590 static const MCPhysReg XMMArgRegs64Bit[] = {
2591 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2592 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2594 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2597 SDValue X86TargetLowering::LowerFormalArguments(
2598 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2599 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2600 SmallVectorImpl<SDValue> &InVals) const {
2601 MachineFunction &MF = DAG.getMachineFunction();
2602 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2603 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2605 const Function* Fn = MF.getFunction();
2606 if (Fn->hasExternalLinkage() &&
2607 Subtarget->isTargetCygMing() &&
2608 Fn->getName() == "main")
2609 FuncInfo->setForceFramePointer(true);
2611 MachineFrameInfo *MFI = MF.getFrameInfo();
2612 bool Is64Bit = Subtarget->is64Bit();
2613 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2615 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2616 "Var args not supported with calling convention fastcc, ghc or hipe");
2618 // Assign locations to all of the incoming arguments.
2619 SmallVector<CCValAssign, 16> ArgLocs;
2620 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2622 // Allocate shadow area for Win64
2624 CCInfo.AllocateStack(32, 8);
2626 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2628 unsigned LastVal = ~0U;
2630 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2631 CCValAssign &VA = ArgLocs[i];
2632 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2634 assert(VA.getValNo() != LastVal &&
2635 "Don't support value assigned to multiple locs yet");
2637 LastVal = VA.getValNo();
2639 if (VA.isRegLoc()) {
2640 EVT RegVT = VA.getLocVT();
2641 const TargetRegisterClass *RC;
2642 if (RegVT == MVT::i32)
2643 RC = &X86::GR32RegClass;
2644 else if (Is64Bit && RegVT == MVT::i64)
2645 RC = &X86::GR64RegClass;
2646 else if (RegVT == MVT::f32)
2647 RC = &X86::FR32RegClass;
2648 else if (RegVT == MVT::f64)
2649 RC = &X86::FR64RegClass;
2650 else if (RegVT.is512BitVector())
2651 RC = &X86::VR512RegClass;
2652 else if (RegVT.is256BitVector())
2653 RC = &X86::VR256RegClass;
2654 else if (RegVT.is128BitVector())
2655 RC = &X86::VR128RegClass;
2656 else if (RegVT == MVT::x86mmx)
2657 RC = &X86::VR64RegClass;
2658 else if (RegVT == MVT::i1)
2659 RC = &X86::VK1RegClass;
2660 else if (RegVT == MVT::v8i1)
2661 RC = &X86::VK8RegClass;
2662 else if (RegVT == MVT::v16i1)
2663 RC = &X86::VK16RegClass;
2664 else if (RegVT == MVT::v32i1)
2665 RC = &X86::VK32RegClass;
2666 else if (RegVT == MVT::v64i1)
2667 RC = &X86::VK64RegClass;
2669 llvm_unreachable("Unknown argument type!");
2671 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2672 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2674 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2675 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2677 if (VA.getLocInfo() == CCValAssign::SExt)
2678 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2679 DAG.getValueType(VA.getValVT()));
2680 else if (VA.getLocInfo() == CCValAssign::ZExt)
2681 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2682 DAG.getValueType(VA.getValVT()));
2683 else if (VA.getLocInfo() == CCValAssign::BCvt)
2684 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2686 if (VA.isExtInLoc()) {
2687 // Handle MMX values passed in XMM regs.
2688 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2689 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2691 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2694 assert(VA.isMemLoc());
2695 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2698 // If value is passed via pointer - do a load.
2699 if (VA.getLocInfo() == CCValAssign::Indirect)
2700 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2701 MachinePointerInfo(), false, false, false, 0);
2703 InVals.push_back(ArgValue);
2706 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2707 // All x86 ABIs require that for returning structs by value we copy the
2708 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2709 // the argument into a virtual register so that we can access it from the
2711 if (Ins[i].Flags.isSRet()) {
2712 unsigned Reg = FuncInfo->getSRetReturnReg();
2714 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2715 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2716 FuncInfo->setSRetReturnReg(Reg);
2718 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2719 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2724 unsigned StackSize = CCInfo.getNextStackOffset();
2725 // Align stack specially for tail calls.
2726 if (shouldGuaranteeTCO(CallConv,
2727 MF.getTarget().Options.GuaranteedTailCallOpt))
2728 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2730 // If the function takes variable number of arguments, make a frame index for
2731 // the start of the first vararg value... for expansion of llvm.va_start. We
2732 // can skip this if there are no va_start calls.
2733 if (MFI->hasVAStart() &&
2734 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2735 CallConv != CallingConv::X86_ThisCall))) {
2736 FuncInfo->setVarArgsFrameIndex(
2737 MFI->CreateFixedObject(1, StackSize, true));
2740 // Figure out if XMM registers are in use.
2741 assert(!(Subtarget->useSoftFloat() &&
2742 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2743 "SSE register cannot be used when SSE is disabled!");
2745 // 64-bit calling conventions support varargs and register parameters, so we
2746 // have to do extra work to spill them in the prologue.
2747 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2748 // Find the first unallocated argument registers.
2749 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2750 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2751 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2752 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2753 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2754 "SSE register cannot be used when SSE is disabled!");
2756 // Gather all the live in physical registers.
2757 SmallVector<SDValue, 6> LiveGPRs;
2758 SmallVector<SDValue, 8> LiveXMMRegs;
2760 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2761 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2763 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2765 if (!ArgXMMs.empty()) {
2766 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2767 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2768 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2769 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2770 LiveXMMRegs.push_back(
2771 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2776 // Get to the caller-allocated home save location. Add 8 to account
2777 // for the return address.
2778 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2779 FuncInfo->setRegSaveFrameIndex(
2780 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2781 // Fixup to set vararg frame on shadow area (4 x i64).
2783 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2785 // For X86-64, if there are vararg parameters that are passed via
2786 // registers, then we must store them to their spots on the stack so
2787 // they may be loaded by deferencing the result of va_next.
2788 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2789 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2790 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2791 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2794 // Store the integer parameter registers.
2795 SmallVector<SDValue, 8> MemOps;
2796 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2797 getPointerTy(DAG.getDataLayout()));
2798 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2799 for (SDValue Val : LiveGPRs) {
2800 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2801 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2803 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2804 MachinePointerInfo::getFixedStack(
2805 DAG.getMachineFunction(),
2806 FuncInfo->getRegSaveFrameIndex(), Offset),
2808 MemOps.push_back(Store);
2812 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2813 // Now store the XMM (fp + vector) parameter registers.
2814 SmallVector<SDValue, 12> SaveXMMOps;
2815 SaveXMMOps.push_back(Chain);
2816 SaveXMMOps.push_back(ALVal);
2817 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2818 FuncInfo->getRegSaveFrameIndex(), dl));
2819 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2820 FuncInfo->getVarArgsFPOffset(), dl));
2821 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2823 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2824 MVT::Other, SaveXMMOps));
2827 if (!MemOps.empty())
2828 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2831 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2832 // Find the largest legal vector type.
2833 MVT VecVT = MVT::Other;
2834 // FIXME: Only some x86_32 calling conventions support AVX512.
2835 if (Subtarget->hasAVX512() &&
2836 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2837 CallConv == CallingConv::Intel_OCL_BI)))
2838 VecVT = MVT::v16f32;
2839 else if (Subtarget->hasAVX())
2841 else if (Subtarget->hasSSE2())
2844 // We forward some GPRs and some vector types.
2845 SmallVector<MVT, 2> RegParmTypes;
2846 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2847 RegParmTypes.push_back(IntVT);
2848 if (VecVT != MVT::Other)
2849 RegParmTypes.push_back(VecVT);
2851 // Compute the set of forwarded registers. The rest are scratch.
2852 SmallVectorImpl<ForwardedRegister> &Forwards =
2853 FuncInfo->getForwardedMustTailRegParms();
2854 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2856 // Conservatively forward AL on x86_64, since it might be used for varargs.
2857 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2858 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2859 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2862 // Copy all forwards from physical to virtual registers.
2863 for (ForwardedRegister &F : Forwards) {
2864 // FIXME: Can we use a less constrained schedule?
2865 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2866 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2867 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2871 // Some CCs need callee pop.
2872 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2873 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2874 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2876 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2877 // If this is an sret function, the return should pop the hidden pointer.
2878 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2879 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2880 argsAreStructReturn(Ins) == StackStructReturn)
2881 FuncInfo->setBytesToPopOnReturn(4);
2885 // RegSaveFrameIndex is X86-64 only.
2886 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2887 if (CallConv == CallingConv::X86_FastCall ||
2888 CallConv == CallingConv::X86_ThisCall)
2889 // fastcc functions can't have varargs.
2890 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2893 FuncInfo->setArgumentStackSize(StackSize);
2895 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2896 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2897 if (Personality == EHPersonality::CoreCLR) {
2899 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2900 // that we'd prefer this slot be allocated towards the bottom of the frame
2901 // (i.e. near the stack pointer after allocating the frame). Every
2902 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2903 // offset from the bottom of this and each funclet's frame must be the
2904 // same, so the size of funclets' (mostly empty) frames is dictated by
2905 // how far this slot is from the bottom (since they allocate just enough
2906 // space to accomodate holding this slot at the correct offset).
2907 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2908 EHInfo->PSPSymFrameIdx = PSPSymFI;
2916 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2917 SDValue StackPtr, SDValue Arg,
2918 SDLoc dl, SelectionDAG &DAG,
2919 const CCValAssign &VA,
2920 ISD::ArgFlagsTy Flags) const {
2921 unsigned LocMemOffset = VA.getLocMemOffset();
2922 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2923 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2925 if (Flags.isByVal())
2926 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2928 return DAG.getStore(
2929 Chain, dl, Arg, PtrOff,
2930 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2934 /// Emit a load of return address if tail call
2935 /// optimization is performed and it is required.
2937 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2938 SDValue &OutRetAddr, SDValue Chain,
2939 bool IsTailCall, bool Is64Bit,
2940 int FPDiff, SDLoc dl) const {
2941 // Adjust the Return address stack slot.
2942 EVT VT = getPointerTy(DAG.getDataLayout());
2943 OutRetAddr = getReturnAddressFrameIndex(DAG);
2945 // Load the "old" Return address.
2946 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2947 false, false, false, 0);
2948 return SDValue(OutRetAddr.getNode(), 1);
2951 /// Emit a store of the return address if tail call
2952 /// optimization is performed and it is required (FPDiff!=0).
2953 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2954 SDValue Chain, SDValue RetAddrFrIdx,
2955 EVT PtrVT, unsigned SlotSize,
2956 int FPDiff, SDLoc dl) {
2957 // Store the return address to the appropriate stack slot.
2958 if (!FPDiff) return Chain;
2959 // Calculate the new stack slot for the return address.
2960 int NewReturnAddrFI =
2961 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2963 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2964 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2965 MachinePointerInfo::getFixedStack(
2966 DAG.getMachineFunction(), NewReturnAddrFI),
2971 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2972 /// operation of specified width.
2973 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2975 unsigned NumElems = VT.getVectorNumElements();
2976 SmallVector<int, 8> Mask;
2977 Mask.push_back(NumElems);
2978 for (unsigned i = 1; i != NumElems; ++i)
2980 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2984 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2985 SmallVectorImpl<SDValue> &InVals) const {
2986 SelectionDAG &DAG = CLI.DAG;
2988 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2989 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2990 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2991 SDValue Chain = CLI.Chain;
2992 SDValue Callee = CLI.Callee;
2993 CallingConv::ID CallConv = CLI.CallConv;
2994 bool &isTailCall = CLI.IsTailCall;
2995 bool isVarArg = CLI.IsVarArg;
2997 MachineFunction &MF = DAG.getMachineFunction();
2998 bool Is64Bit = Subtarget->is64Bit();
2999 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
3000 StructReturnType SR = callIsStructReturn(Outs);
3001 bool IsSibcall = false;
3002 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3003 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3005 if (Attr.getValueAsString() == "true")
3008 if (Subtarget->isPICStyleGOT() &&
3009 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3010 // If we are using a GOT, disable tail calls to external symbols with
3011 // default visibility. Tail calling such a symbol requires using a GOT
3012 // relocation, which forces early binding of the symbol. This breaks code
3013 // that require lazy function symbol resolution. Using musttail or
3014 // GuaranteedTailCallOpt will override this.
3015 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3016 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3017 G->getGlobal()->hasDefaultVisibility()))
3021 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3023 // Force this to be a tail call. The verifier rules are enough to ensure
3024 // that we can lower this successfully without moving the return address
3027 } else if (isTailCall) {
3028 // Check if it's really possible to do a tail call.
3029 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3030 isVarArg, SR != NotStructReturn,
3031 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3032 Outs, OutVals, Ins, DAG);
3034 // Sibcalls are automatically detected tailcalls which do not require
3036 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3043 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3044 "Var args not supported with calling convention fastcc, ghc or hipe");
3046 // Analyze operands of the call, assigning locations to each operand.
3047 SmallVector<CCValAssign, 16> ArgLocs;
3048 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3050 // Allocate shadow area for Win64
3052 CCInfo.AllocateStack(32, 8);
3054 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3056 // Get a count of how many bytes are to be pushed on the stack.
3057 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3059 // This is a sibcall. The memory operands are available in caller's
3060 // own caller's stack.
3062 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3063 canGuaranteeTCO(CallConv))
3064 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3067 if (isTailCall && !IsSibcall && !IsMustTail) {
3068 // Lower arguments at fp - stackoffset + fpdiff.
3069 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3071 FPDiff = NumBytesCallerPushed - NumBytes;
3073 // Set the delta of movement of the returnaddr stackslot.
3074 // But only set if delta is greater than previous delta.
3075 if (FPDiff < X86Info->getTCReturnAddrDelta())
3076 X86Info->setTCReturnAddrDelta(FPDiff);
3079 unsigned NumBytesToPush = NumBytes;
3080 unsigned NumBytesToPop = NumBytes;
3082 // If we have an inalloca argument, all stack space has already been allocated
3083 // for us and be right at the top of the stack. We don't support multiple
3084 // arguments passed in memory when using inalloca.
3085 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3087 if (!ArgLocs.back().isMemLoc())
3088 report_fatal_error("cannot use inalloca attribute on a register "
3090 if (ArgLocs.back().getLocMemOffset() != 0)
3091 report_fatal_error("any parameter with the inalloca attribute must be "
3092 "the only memory argument");
3096 Chain = DAG.getCALLSEQ_START(
3097 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3099 SDValue RetAddrFrIdx;
3100 // Load return address for tail calls.
3101 if (isTailCall && FPDiff)
3102 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3103 Is64Bit, FPDiff, dl);
3105 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3106 SmallVector<SDValue, 8> MemOpChains;
3109 // Walk the register/memloc assignments, inserting copies/loads. In the case
3110 // of tail call optimization arguments are handle later.
3111 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3112 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3113 // Skip inalloca arguments, they have already been written.
3114 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3115 if (Flags.isInAlloca())
3118 CCValAssign &VA = ArgLocs[i];
3119 EVT RegVT = VA.getLocVT();
3120 SDValue Arg = OutVals[i];
3121 bool isByVal = Flags.isByVal();
3123 // Promote the value if needed.
3124 switch (VA.getLocInfo()) {
3125 default: llvm_unreachable("Unknown loc info!");
3126 case CCValAssign::Full: break;
3127 case CCValAssign::SExt:
3128 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3130 case CCValAssign::ZExt:
3131 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3133 case CCValAssign::AExt:
3134 if (Arg.getValueType().isVector() &&
3135 Arg.getValueType().getVectorElementType() == MVT::i1)
3136 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3137 else if (RegVT.is128BitVector()) {
3138 // Special case: passing MMX values in XMM registers.
3139 Arg = DAG.getBitcast(MVT::i64, Arg);
3140 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3141 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3143 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3145 case CCValAssign::BCvt:
3146 Arg = DAG.getBitcast(RegVT, Arg);
3148 case CCValAssign::Indirect: {
3149 // Store the argument.
3150 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3151 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3152 Chain = DAG.getStore(
3153 Chain, dl, Arg, SpillSlot,
3154 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3161 if (VA.isRegLoc()) {
3162 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3163 if (isVarArg && IsWin64) {
3164 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3165 // shadow reg if callee is a varargs function.
3166 unsigned ShadowReg = 0;
3167 switch (VA.getLocReg()) {
3168 case X86::XMM0: ShadowReg = X86::RCX; break;
3169 case X86::XMM1: ShadowReg = X86::RDX; break;
3170 case X86::XMM2: ShadowReg = X86::R8; break;
3171 case X86::XMM3: ShadowReg = X86::R9; break;
3174 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3176 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3177 assert(VA.isMemLoc());
3178 if (!StackPtr.getNode())
3179 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3180 getPointerTy(DAG.getDataLayout()));
3181 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3182 dl, DAG, VA, Flags));
3186 if (!MemOpChains.empty())
3187 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3189 if (Subtarget->isPICStyleGOT()) {
3190 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3193 RegsToPass.push_back(std::make_pair(
3194 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3195 getPointerTy(DAG.getDataLayout()))));
3197 // If we are tail calling and generating PIC/GOT style code load the
3198 // address of the callee into ECX. The value in ecx is used as target of
3199 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3200 // for tail calls on PIC/GOT architectures. Normally we would just put the
3201 // address of GOT into ebx and then call target@PLT. But for tail calls
3202 // ebx would be restored (since ebx is callee saved) before jumping to the
3205 // Note: The actual moving to ECX is done further down.
3206 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3207 if (G && !G->getGlobal()->hasLocalLinkage() &&
3208 G->getGlobal()->hasDefaultVisibility())
3209 Callee = LowerGlobalAddress(Callee, DAG);
3210 else if (isa<ExternalSymbolSDNode>(Callee))
3211 Callee = LowerExternalSymbol(Callee, DAG);
3215 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3216 // From AMD64 ABI document:
3217 // For calls that may call functions that use varargs or stdargs
3218 // (prototype-less calls or calls to functions containing ellipsis (...) in
3219 // the declaration) %al is used as hidden argument to specify the number
3220 // of SSE registers used. The contents of %al do not need to match exactly
3221 // the number of registers, but must be an ubound on the number of SSE
3222 // registers used and is in the range 0 - 8 inclusive.
3224 // Count the number of XMM registers allocated.
3225 static const MCPhysReg XMMArgRegs[] = {
3226 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3227 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3229 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3230 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3231 && "SSE registers cannot be used when SSE is disabled");
3233 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3234 DAG.getConstant(NumXMMRegs, dl,
3238 if (isVarArg && IsMustTail) {
3239 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3240 for (const auto &F : Forwards) {
3241 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3242 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3246 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3247 // don't need this because the eligibility check rejects calls that require
3248 // shuffling arguments passed in memory.
3249 if (!IsSibcall && isTailCall) {
3250 // Force all the incoming stack arguments to be loaded from the stack
3251 // before any new outgoing arguments are stored to the stack, because the
3252 // outgoing stack slots may alias the incoming argument stack slots, and
3253 // the alias isn't otherwise explicit. This is slightly more conservative
3254 // than necessary, because it means that each store effectively depends
3255 // on every argument instead of just those arguments it would clobber.
3256 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3258 SmallVector<SDValue, 8> MemOpChains2;
3261 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3262 CCValAssign &VA = ArgLocs[i];
3265 assert(VA.isMemLoc());
3266 SDValue Arg = OutVals[i];
3267 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3268 // Skip inalloca arguments. They don't require any work.
3269 if (Flags.isInAlloca())
3271 // Create frame index.
3272 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3273 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3274 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3275 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3277 if (Flags.isByVal()) {
3278 // Copy relative to framepointer.
3279 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3280 if (!StackPtr.getNode())
3281 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3282 getPointerTy(DAG.getDataLayout()));
3283 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3286 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3290 // Store relative to framepointer.
3291 MemOpChains2.push_back(DAG.getStore(
3292 ArgChain, dl, Arg, FIN,
3293 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3298 if (!MemOpChains2.empty())
3299 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3301 // Store the return address to the appropriate stack slot.
3302 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3303 getPointerTy(DAG.getDataLayout()),
3304 RegInfo->getSlotSize(), FPDiff, dl);
3307 // Build a sequence of copy-to-reg nodes chained together with token chain
3308 // and flag operands which copy the outgoing args into registers.
3310 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3311 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3312 RegsToPass[i].second, InFlag);
3313 InFlag = Chain.getValue(1);
3316 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3317 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3318 // In the 64-bit large code model, we have to make all calls
3319 // through a register, since the call instruction's 32-bit
3320 // pc-relative offset may not be large enough to hold the whole
3322 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3323 // If the callee is a GlobalAddress node (quite common, every direct call
3324 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3326 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3328 // We should use extra load for direct calls to dllimported functions in
3330 const GlobalValue *GV = G->getGlobal();
3331 if (!GV->hasDLLImportStorageClass()) {
3332 unsigned char OpFlags = 0;
3333 bool ExtraLoad = false;
3334 unsigned WrapperKind = ISD::DELETED_NODE;
3336 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3337 // external symbols most go through the PLT in PIC mode. If the symbol
3338 // has hidden or protected visibility, or if it is static or local, then
3339 // we don't need to use the PLT - we can directly call it.
3340 if (Subtarget->isTargetELF() &&
3341 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3342 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3343 OpFlags = X86II::MO_PLT;
3344 } else if (Subtarget->isPICStyleStubAny() &&
3345 !GV->isStrongDefinitionForLinker() &&
3346 (!Subtarget->getTargetTriple().isMacOSX() ||
3347 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3348 // PC-relative references to external symbols should go through $stub,
3349 // unless we're building with the leopard linker or later, which
3350 // automatically synthesizes these stubs.
3351 OpFlags = X86II::MO_DARWIN_STUB;
3352 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3353 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3354 // If the function is marked as non-lazy, generate an indirect call
3355 // which loads from the GOT directly. This avoids runtime overhead
3356 // at the cost of eager binding (and one extra byte of encoding).
3357 OpFlags = X86II::MO_GOTPCREL;
3358 WrapperKind = X86ISD::WrapperRIP;
3362 Callee = DAG.getTargetGlobalAddress(
3363 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3365 // Add a wrapper if needed.
3366 if (WrapperKind != ISD::DELETED_NODE)
3367 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3368 getPointerTy(DAG.getDataLayout()), Callee);
3369 // Add extra indirection if needed.
3371 Callee = DAG.getLoad(
3372 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3373 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3376 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3377 unsigned char OpFlags = 0;
3379 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3380 // external symbols should go through the PLT.
3381 if (Subtarget->isTargetELF() &&
3382 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3383 OpFlags = X86II::MO_PLT;
3384 } else if (Subtarget->isPICStyleStubAny() &&
3385 (!Subtarget->getTargetTriple().isMacOSX() ||
3386 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3387 // PC-relative references to external symbols should go through $stub,
3388 // unless we're building with the leopard linker or later, which
3389 // automatically synthesizes these stubs.
3390 OpFlags = X86II::MO_DARWIN_STUB;
3393 Callee = DAG.getTargetExternalSymbol(
3394 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3395 } else if (Subtarget->isTarget64BitILP32() &&
3396 Callee->getValueType(0) == MVT::i32) {
3397 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3398 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3401 // Returns a chain & a flag for retval copy to use.
3402 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3403 SmallVector<SDValue, 8> Ops;
3405 if (!IsSibcall && isTailCall) {
3406 Chain = DAG.getCALLSEQ_END(Chain,
3407 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3408 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3409 InFlag = Chain.getValue(1);
3412 Ops.push_back(Chain);
3413 Ops.push_back(Callee);
3416 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3418 // Add argument registers to the end of the list so that they are known live
3420 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3421 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3422 RegsToPass[i].second.getValueType()));
3424 // Add a register mask operand representing the call-preserved registers.
3425 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3426 assert(Mask && "Missing call preserved mask for calling convention");
3428 // If this is an invoke in a 32-bit function using a funclet-based
3429 // personality, assume the function clobbers all registers. If an exception
3430 // is thrown, the runtime will not restore CSRs.
3431 // FIXME: Model this more precisely so that we can register allocate across
3432 // the normal edge and spill and fill across the exceptional edge.
3433 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3434 const Function *CallerFn = MF.getFunction();
3435 EHPersonality Pers =
3436 CallerFn->hasPersonalityFn()
3437 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3438 : EHPersonality::Unknown;
3439 if (isFuncletEHPersonality(Pers))
3440 Mask = RegInfo->getNoPreservedMask();
3443 Ops.push_back(DAG.getRegisterMask(Mask));
3445 if (InFlag.getNode())
3446 Ops.push_back(InFlag);
3450 //// If this is the first return lowered for this function, add the regs
3451 //// to the liveout set for the function.
3452 // This isn't right, although it's probably harmless on x86; liveouts
3453 // should be computed from returns not tail calls. Consider a void
3454 // function making a tail call to a function returning int.
3455 MF.getFrameInfo()->setHasTailCall();
3456 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3459 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3460 InFlag = Chain.getValue(1);
3462 // Create the CALLSEQ_END node.
3463 unsigned NumBytesForCalleeToPop;
3464 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3465 DAG.getTarget().Options.GuaranteedTailCallOpt))
3466 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3467 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3468 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3469 SR == StackStructReturn)
3470 // If this is a call to a struct-return function, the callee
3471 // pops the hidden struct pointer, so we have to push it back.
3472 // This is common for Darwin/X86, Linux & Mingw32 targets.
3473 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3474 NumBytesForCalleeToPop = 4;
3476 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3478 // Returns a flag for retval copy to use.
3480 Chain = DAG.getCALLSEQ_END(Chain,
3481 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3482 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3485 InFlag = Chain.getValue(1);
3488 // Handle result values, copying them out of physregs into vregs that we
3490 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3491 Ins, dl, DAG, InVals);
3494 //===----------------------------------------------------------------------===//
3495 // Fast Calling Convention (tail call) implementation
3496 //===----------------------------------------------------------------------===//
3498 // Like std call, callee cleans arguments, convention except that ECX is
3499 // reserved for storing the tail called function address. Only 2 registers are
3500 // free for argument passing (inreg). Tail call optimization is performed
3502 // * tailcallopt is enabled
3503 // * caller/callee are fastcc
3504 // On X86_64 architecture with GOT-style position independent code only local
3505 // (within module) calls are supported at the moment.
3506 // To keep the stack aligned according to platform abi the function
3507 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3508 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3509 // If a tail called function callee has more arguments than the caller the
3510 // caller needs to make sure that there is room to move the RETADDR to. This is
3511 // achieved by reserving an area the size of the argument delta right after the
3512 // original RETADDR, but before the saved framepointer or the spilled registers
3513 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3525 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3528 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3529 SelectionDAG& DAG) const {
3530 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3531 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3532 unsigned StackAlignment = TFI.getStackAlignment();
3533 uint64_t AlignMask = StackAlignment - 1;
3534 int64_t Offset = StackSize;
3535 unsigned SlotSize = RegInfo->getSlotSize();
3536 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3537 // Number smaller than 12 so just add the difference.
3538 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3540 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3541 Offset = ((~AlignMask) & Offset) + StackAlignment +
3542 (StackAlignment-SlotSize);
3547 /// Return true if the given stack call argument is already available in the
3548 /// same position (relatively) of the caller's incoming argument stack.
3550 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3551 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3552 const X86InstrInfo *TII) {
3553 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3555 if (Arg.getOpcode() == ISD::CopyFromReg) {
3556 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3557 if (!TargetRegisterInfo::isVirtualRegister(VR))
3559 MachineInstr *Def = MRI->getVRegDef(VR);
3562 if (!Flags.isByVal()) {
3563 if (!TII->isLoadFromStackSlot(Def, FI))
3566 unsigned Opcode = Def->getOpcode();
3567 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3568 Opcode == X86::LEA64_32r) &&
3569 Def->getOperand(1).isFI()) {
3570 FI = Def->getOperand(1).getIndex();
3571 Bytes = Flags.getByValSize();
3575 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3576 if (Flags.isByVal())
3577 // ByVal argument is passed in as a pointer but it's now being
3578 // dereferenced. e.g.
3579 // define @foo(%struct.X* %A) {
3580 // tail call @bar(%struct.X* byval %A)
3583 SDValue Ptr = Ld->getBasePtr();
3584 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3587 FI = FINode->getIndex();
3588 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3589 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3590 FI = FINode->getIndex();
3591 Bytes = Flags.getByValSize();
3595 assert(FI != INT_MAX);
3596 if (!MFI->isFixedObjectIndex(FI))
3598 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3601 /// Check whether the call is eligible for tail call optimization. Targets
3602 /// that want to do tail call optimization should implement this function.
3603 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3604 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3605 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3606 const SmallVectorImpl<ISD::OutputArg> &Outs,
3607 const SmallVectorImpl<SDValue> &OutVals,
3608 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3609 if (!mayTailCallThisCC(CalleeCC))
3612 // If -tailcallopt is specified, make fastcc functions tail-callable.
3613 MachineFunction &MF = DAG.getMachineFunction();
3614 const Function *CallerF = MF.getFunction();
3616 // If the function return type is x86_fp80 and the callee return type is not,
3617 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3618 // perform a tailcall optimization here.
3619 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3622 CallingConv::ID CallerCC = CallerF->getCallingConv();
3623 bool CCMatch = CallerCC == CalleeCC;
3624 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3625 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3627 // Win64 functions have extra shadow space for argument homing. Don't do the
3628 // sibcall if the caller and callee have mismatched expectations for this
3630 if (IsCalleeWin64 != IsCallerWin64)
3633 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3634 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3639 // Look for obvious safe cases to perform tail call optimization that do not
3640 // require ABI changes. This is what gcc calls sibcall.
3642 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3643 // emit a special epilogue.
3644 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3645 if (RegInfo->needsStackRealignment(MF))
3648 // Also avoid sibcall optimization if either caller or callee uses struct
3649 // return semantics.
3650 if (isCalleeStructRet || isCallerStructRet)
3653 // Do not sibcall optimize vararg calls unless all arguments are passed via
3655 if (isVarArg && !Outs.empty()) {
3656 // Optimizing for varargs on Win64 is unlikely to be safe without
3657 // additional testing.
3658 if (IsCalleeWin64 || IsCallerWin64)
3661 SmallVector<CCValAssign, 16> ArgLocs;
3662 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3665 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3666 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3667 if (!ArgLocs[i].isRegLoc())
3671 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3672 // stack. Therefore, if it's not used by the call it is not safe to optimize
3673 // this into a sibcall.
3674 bool Unused = false;
3675 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3682 SmallVector<CCValAssign, 16> RVLocs;
3683 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3685 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3686 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3687 CCValAssign &VA = RVLocs[i];
3688 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3693 // If the calling conventions do not match, then we'd better make sure the
3694 // results are returned in the same way as what the caller expects.
3696 SmallVector<CCValAssign, 16> RVLocs1;
3697 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3699 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3701 SmallVector<CCValAssign, 16> RVLocs2;
3702 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3704 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3706 if (RVLocs1.size() != RVLocs2.size())
3708 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3709 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3711 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3713 if (RVLocs1[i].isRegLoc()) {
3714 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3717 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3723 unsigned StackArgsSize = 0;
3725 // If the callee takes no arguments then go on to check the results of the
3727 if (!Outs.empty()) {
3728 // Check if stack adjustment is needed. For now, do not do this if any
3729 // argument is passed on the stack.
3730 SmallVector<CCValAssign, 16> ArgLocs;
3731 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3734 // Allocate shadow area for Win64
3736 CCInfo.AllocateStack(32, 8);
3738 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3739 StackArgsSize = CCInfo.getNextStackOffset();
3741 if (CCInfo.getNextStackOffset()) {
3742 // Check if the arguments are already laid out in the right way as
3743 // the caller's fixed stack objects.
3744 MachineFrameInfo *MFI = MF.getFrameInfo();
3745 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3746 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3747 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3748 CCValAssign &VA = ArgLocs[i];
3749 SDValue Arg = OutVals[i];
3750 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3751 if (VA.getLocInfo() == CCValAssign::Indirect)
3753 if (!VA.isRegLoc()) {
3754 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3761 // If the tailcall address may be in a register, then make sure it's
3762 // possible to register allocate for it. In 32-bit, the call address can
3763 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3764 // callee-saved registers are restored. These happen to be the same
3765 // registers used to pass 'inreg' arguments so watch out for those.
3766 if (!Subtarget->is64Bit() &&
3767 ((!isa<GlobalAddressSDNode>(Callee) &&
3768 !isa<ExternalSymbolSDNode>(Callee)) ||
3769 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3770 unsigned NumInRegs = 0;
3771 // In PIC we need an extra register to formulate the address computation
3773 unsigned MaxInRegs =
3774 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3776 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3777 CCValAssign &VA = ArgLocs[i];
3780 unsigned Reg = VA.getLocReg();
3783 case X86::EAX: case X86::EDX: case X86::ECX:
3784 if (++NumInRegs == MaxInRegs)
3792 bool CalleeWillPop =
3793 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3794 MF.getTarget().Options.GuaranteedTailCallOpt);
3796 if (unsigned BytesToPop =
3797 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3798 // If we have bytes to pop, the callee must pop them.
3799 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3800 if (!CalleePopMatches)
3802 } else if (CalleeWillPop && StackArgsSize > 0) {
3803 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3811 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3812 const TargetLibraryInfo *libInfo) const {
3813 return X86::createFastISel(funcInfo, libInfo);
3816 //===----------------------------------------------------------------------===//
3817 // Other Lowering Hooks
3818 //===----------------------------------------------------------------------===//
3820 static bool MayFoldLoad(SDValue Op) {
3821 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3824 static bool MayFoldIntoStore(SDValue Op) {
3825 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3828 static bool isTargetShuffle(unsigned Opcode) {
3830 default: return false;
3831 case X86ISD::BLENDI:
3832 case X86ISD::PSHUFB:
3833 case X86ISD::PSHUFD:
3834 case X86ISD::PSHUFHW:
3835 case X86ISD::PSHUFLW:
3837 case X86ISD::PALIGNR:
3838 case X86ISD::MOVLHPS:
3839 case X86ISD::MOVLHPD:
3840 case X86ISD::MOVHLPS:
3841 case X86ISD::MOVLPS:
3842 case X86ISD::MOVLPD:
3843 case X86ISD::MOVSHDUP:
3844 case X86ISD::MOVSLDUP:
3845 case X86ISD::MOVDDUP:
3848 case X86ISD::UNPCKL:
3849 case X86ISD::UNPCKH:
3850 case X86ISD::VPERMILPI:
3851 case X86ISD::VPERM2X128:
3852 case X86ISD::VPERMI:
3853 case X86ISD::VPERMV:
3854 case X86ISD::VPERMV3:
3859 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3860 SDValue V1, unsigned TargetMask,
3861 SelectionDAG &DAG) {
3863 default: llvm_unreachable("Unknown x86 shuffle node");
3864 case X86ISD::PSHUFD:
3865 case X86ISD::PSHUFHW:
3866 case X86ISD::PSHUFLW:
3867 case X86ISD::VPERMILPI:
3868 case X86ISD::VPERMI:
3869 return DAG.getNode(Opc, dl, VT, V1,
3870 DAG.getConstant(TargetMask, dl, MVT::i8));
3874 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3875 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3877 default: llvm_unreachable("Unknown x86 shuffle node");
3878 case X86ISD::MOVLHPS:
3879 case X86ISD::MOVLHPD:
3880 case X86ISD::MOVHLPS:
3881 case X86ISD::MOVLPS:
3882 case X86ISD::MOVLPD:
3885 case X86ISD::UNPCKL:
3886 case X86ISD::UNPCKH:
3887 return DAG.getNode(Opc, dl, VT, V1, V2);
3891 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3892 MachineFunction &MF = DAG.getMachineFunction();
3893 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3894 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3895 int ReturnAddrIndex = FuncInfo->getRAIndex();
3897 if (ReturnAddrIndex == 0) {
3898 // Set up a frame object for the return address.
3899 unsigned SlotSize = RegInfo->getSlotSize();
3900 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3903 FuncInfo->setRAIndex(ReturnAddrIndex);
3906 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3909 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3910 bool hasSymbolicDisplacement) {
3911 // Offset should fit into 32 bit immediate field.
3912 if (!isInt<32>(Offset))
3915 // If we don't have a symbolic displacement - we don't have any extra
3917 if (!hasSymbolicDisplacement)
3920 // FIXME: Some tweaks might be needed for medium code model.
3921 if (M != CodeModel::Small && M != CodeModel::Kernel)
3924 // For small code model we assume that latest object is 16MB before end of 31
3925 // bits boundary. We may also accept pretty large negative constants knowing
3926 // that all objects are in the positive half of address space.
3927 if (M == CodeModel::Small && Offset < 16*1024*1024)
3930 // For kernel code model we know that all object resist in the negative half
3931 // of 32bits address space. We may not accept negative offsets, since they may
3932 // be just off and we may accept pretty large positive ones.
3933 if (M == CodeModel::Kernel && Offset >= 0)
3939 /// Determines whether the callee is required to pop its own arguments.
3940 /// Callee pop is necessary to support tail calls.
3941 bool X86::isCalleePop(CallingConv::ID CallingConv,
3942 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3943 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3944 // can guarantee TCO.
3945 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3948 switch (CallingConv) {
3951 case CallingConv::X86_StdCall:
3952 case CallingConv::X86_FastCall:
3953 case CallingConv::X86_ThisCall:
3954 case CallingConv::X86_VectorCall:
3959 /// \brief Return true if the condition is an unsigned comparison operation.
3960 static bool isX86CCUnsigned(unsigned X86CC) {
3962 default: llvm_unreachable("Invalid integer condition!");
3963 case X86::COND_E: return true;
3964 case X86::COND_G: return false;
3965 case X86::COND_GE: return false;
3966 case X86::COND_L: return false;
3967 case X86::COND_LE: return false;
3968 case X86::COND_NE: return true;
3969 case X86::COND_B: return true;
3970 case X86::COND_A: return true;
3971 case X86::COND_BE: return true;
3972 case X86::COND_AE: return true;
3976 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
3977 switch (SetCCOpcode) {
3978 default: llvm_unreachable("Invalid integer condition!");
3979 case ISD::SETEQ: return X86::COND_E;
3980 case ISD::SETGT: return X86::COND_G;
3981 case ISD::SETGE: return X86::COND_GE;
3982 case ISD::SETLT: return X86::COND_L;
3983 case ISD::SETLE: return X86::COND_LE;
3984 case ISD::SETNE: return X86::COND_NE;
3985 case ISD::SETULT: return X86::COND_B;
3986 case ISD::SETUGT: return X86::COND_A;
3987 case ISD::SETULE: return X86::COND_BE;
3988 case ISD::SETUGE: return X86::COND_AE;
3992 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3993 /// condition code, returning the condition code and the LHS/RHS of the
3994 /// comparison to make.
3995 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3996 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3998 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3999 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4000 // X > -1 -> X == 0, jump !sign.
4001 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4002 return X86::COND_NS;
4004 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4005 // X < 0 -> X == 0, jump on sign.
4008 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4010 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4011 return X86::COND_LE;
4015 return TranslateIntegerX86CC(SetCCOpcode);
4018 // First determine if it is required or is profitable to flip the operands.
4020 // If LHS is a foldable load, but RHS is not, flip the condition.
4021 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4022 !ISD::isNON_EXTLoad(RHS.getNode())) {
4023 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4024 std::swap(LHS, RHS);
4027 switch (SetCCOpcode) {
4033 std::swap(LHS, RHS);
4037 // On a floating point condition, the flags are set as follows:
4039 // 0 | 0 | 0 | X > Y
4040 // 0 | 0 | 1 | X < Y
4041 // 1 | 0 | 0 | X == Y
4042 // 1 | 1 | 1 | unordered
4043 switch (SetCCOpcode) {
4044 default: llvm_unreachable("Condcode should be pre-legalized away");
4046 case ISD::SETEQ: return X86::COND_E;
4047 case ISD::SETOLT: // flipped
4049 case ISD::SETGT: return X86::COND_A;
4050 case ISD::SETOLE: // flipped
4052 case ISD::SETGE: return X86::COND_AE;
4053 case ISD::SETUGT: // flipped
4055 case ISD::SETLT: return X86::COND_B;
4056 case ISD::SETUGE: // flipped
4058 case ISD::SETLE: return X86::COND_BE;
4060 case ISD::SETNE: return X86::COND_NE;
4061 case ISD::SETUO: return X86::COND_P;
4062 case ISD::SETO: return X86::COND_NP;
4064 case ISD::SETUNE: return X86::COND_INVALID;
4068 /// Is there a floating point cmov for the specific X86 condition code?
4069 /// Current x86 isa includes the following FP cmov instructions:
4070 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4071 static bool hasFPCMov(unsigned X86CC) {
4087 /// Returns true if the target can instruction select the
4088 /// specified FP immediate natively. If false, the legalizer will
4089 /// materialize the FP immediate as a load from a constant pool.
4090 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4091 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4092 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4098 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4099 ISD::LoadExtType ExtTy,
4101 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4102 // relocation target a movq or addq instruction: don't let the load shrink.
4103 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4104 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4105 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4106 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4110 /// \brief Returns true if it is beneficial to convert a load of a constant
4111 /// to just the constant itself.
4112 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4114 assert(Ty->isIntegerTy());
4116 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4117 if (BitSize == 0 || BitSize > 64)
4122 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4123 unsigned Index) const {
4124 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4127 return (Index == 0 || Index == ResVT.getVectorNumElements());
4130 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4131 // Speculate cttz only if we can directly use TZCNT.
4132 return Subtarget->hasBMI();
4135 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4136 // Speculate ctlz only if we can directly use LZCNT.
4137 return Subtarget->hasLZCNT();
4140 /// Return true if every element in Mask, beginning
4141 /// from position Pos and ending in Pos+Size is undef.
4142 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4143 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4149 /// Return true if Val is undef or if its value falls within the
4150 /// specified range (L, H].
4151 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4152 return (Val < 0) || (Val >= Low && Val < Hi);
4155 /// Val is either less than zero (undef) or equal to the specified value.
4156 static bool isUndefOrEqual(int Val, int CmpVal) {
4157 return (Val < 0 || Val == CmpVal);
4160 /// Return true if every element in Mask, beginning
4161 /// from position Pos and ending in Pos+Size, falls within the specified
4162 /// sequential range (Low, Low+Size]. or is undef.
4163 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4164 unsigned Pos, unsigned Size, int Low) {
4165 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4166 if (!isUndefOrEqual(Mask[i], Low))
4171 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4172 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4173 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4174 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4175 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4178 // The index should be aligned on a vecWidth-bit boundary.
4180 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4182 MVT VT = N->getSimpleValueType(0);
4183 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4184 bool Result = (Index * ElSize) % vecWidth == 0;
4189 /// Return true if the specified INSERT_SUBVECTOR
4190 /// operand specifies a subvector insert that is suitable for input to
4191 /// insertion of 128 or 256-bit subvectors
4192 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4193 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4194 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4196 // The index should be aligned on a vecWidth-bit boundary.
4198 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4200 MVT VT = N->getSimpleValueType(0);
4201 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4202 bool Result = (Index * ElSize) % vecWidth == 0;
4207 bool X86::isVINSERT128Index(SDNode *N) {
4208 return isVINSERTIndex(N, 128);
4211 bool X86::isVINSERT256Index(SDNode *N) {
4212 return isVINSERTIndex(N, 256);
4215 bool X86::isVEXTRACT128Index(SDNode *N) {
4216 return isVEXTRACTIndex(N, 128);
4219 bool X86::isVEXTRACT256Index(SDNode *N) {
4220 return isVEXTRACTIndex(N, 256);
4223 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4224 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4225 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4226 "Illegal extract subvector for VEXTRACT");
4229 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4231 MVT VecVT = N->getOperand(0).getSimpleValueType();
4232 MVT ElVT = VecVT.getVectorElementType();
4234 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4235 return Index / NumElemsPerChunk;
4238 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4239 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4240 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4241 "Illegal insert subvector for VINSERT");
4244 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4246 MVT VecVT = N->getSimpleValueType(0);
4247 MVT ElVT = VecVT.getVectorElementType();
4249 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4250 return Index / NumElemsPerChunk;
4253 /// Return the appropriate immediate to extract the specified
4254 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4255 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4256 return getExtractVEXTRACTImmediate(N, 128);
4259 /// Return the appropriate immediate to extract the specified
4260 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4261 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4262 return getExtractVEXTRACTImmediate(N, 256);
4265 /// Return the appropriate immediate to insert at the specified
4266 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4267 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4268 return getInsertVINSERTImmediate(N, 128);
4271 /// Return the appropriate immediate to insert at the specified
4272 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4273 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4274 return getInsertVINSERTImmediate(N, 256);
4277 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4278 bool X86::isZeroNode(SDValue Elt) {
4279 return isNullConstant(Elt) || isNullFPConstant(Elt);
4282 // Build a vector of constants
4283 // Use an UNDEF node if MaskElt == -1.
4284 // Spilt 64-bit constants in the 32-bit mode.
4285 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4287 SDLoc dl, bool IsMask = false) {
4289 SmallVector<SDValue, 32> Ops;
4292 MVT ConstVecVT = VT;
4293 unsigned NumElts = VT.getVectorNumElements();
4294 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4295 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4296 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4300 MVT EltVT = ConstVecVT.getVectorElementType();
4301 for (unsigned i = 0; i < NumElts; ++i) {
4302 bool IsUndef = Values[i] < 0 && IsMask;
4303 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4304 DAG.getConstant(Values[i], dl, EltVT);
4305 Ops.push_back(OpNode);
4307 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4308 DAG.getConstant(0, dl, EltVT));
4310 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4312 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4316 /// Returns a vector of specified type with all zero elements.
4317 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4318 SelectionDAG &DAG, SDLoc dl) {
4319 assert(VT.isVector() && "Expected a vector type");
4321 // Always build SSE zero vectors as <4 x i32> bitcasted
4322 // to their dest type. This ensures they get CSE'd.
4324 if (VT.is128BitVector()) { // SSE
4325 if (Subtarget->hasSSE2()) { // SSE2
4326 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4327 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4329 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4330 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4332 } else if (VT.is256BitVector()) { // AVX
4333 if (Subtarget->hasInt256()) { // AVX2
4334 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4335 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4336 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4338 // 256-bit logic and arithmetic instructions in AVX are all
4339 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4340 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4341 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4342 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4344 } else if (VT.is512BitVector()) { // AVX-512
4345 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4346 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4347 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4348 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4349 } else if (VT.getVectorElementType() == MVT::i1) {
4351 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4352 && "Unexpected vector type");
4353 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4354 && "Unexpected vector type");
4355 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4356 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4357 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4359 llvm_unreachable("Unexpected vector type");
4361 return DAG.getBitcast(VT, Vec);
4364 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4365 SelectionDAG &DAG, SDLoc dl,
4366 unsigned vectorWidth) {
4367 assert((vectorWidth == 128 || vectorWidth == 256) &&
4368 "Unsupported vector width");
4369 EVT VT = Vec.getValueType();
4370 EVT ElVT = VT.getVectorElementType();
4371 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4372 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4373 VT.getVectorNumElements()/Factor);
4375 // Extract from UNDEF is UNDEF.
4376 if (Vec.getOpcode() == ISD::UNDEF)
4377 return DAG.getUNDEF(ResultVT);
4379 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4380 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4381 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4383 // This is the index of the first element of the vectorWidth-bit chunk
4384 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4385 IdxVal &= ~(ElemsPerChunk - 1);
4387 // If the input is a buildvector just emit a smaller one.
4388 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4389 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4390 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4392 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4393 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4396 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4397 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4398 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4399 /// instructions or a simple subregister reference. Idx is an index in the
4400 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4401 /// lowering EXTRACT_VECTOR_ELT operations easier.
4402 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4403 SelectionDAG &DAG, SDLoc dl) {
4404 assert((Vec.getValueType().is256BitVector() ||
4405 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4406 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4409 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4410 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4411 SelectionDAG &DAG, SDLoc dl) {
4412 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4413 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4416 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4417 unsigned IdxVal, SelectionDAG &DAG,
4418 SDLoc dl, unsigned vectorWidth) {
4419 assert((vectorWidth == 128 || vectorWidth == 256) &&
4420 "Unsupported vector width");
4421 // Inserting UNDEF is Result
4422 if (Vec.getOpcode() == ISD::UNDEF)
4424 EVT VT = Vec.getValueType();
4425 EVT ElVT = VT.getVectorElementType();
4426 EVT ResultVT = Result.getValueType();
4428 // Insert the relevant vectorWidth bits.
4429 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4430 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4432 // This is the index of the first element of the vectorWidth-bit chunk
4433 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4434 IdxVal &= ~(ElemsPerChunk - 1);
4436 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4437 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4440 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4441 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4442 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4443 /// simple superregister reference. Idx is an index in the 128 bits
4444 /// we want. It need not be aligned to a 128-bit boundary. That makes
4445 /// lowering INSERT_VECTOR_ELT operations easier.
4446 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4447 SelectionDAG &DAG, SDLoc dl) {
4448 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4450 // For insertion into the zero index (low half) of a 256-bit vector, it is
4451 // more efficient to generate a blend with immediate instead of an insert*128.
4452 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4453 // extend the subvector to the size of the result vector. Make sure that
4454 // we are not recursing on that node by checking for undef here.
4455 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4456 Result.getOpcode() != ISD::UNDEF) {
4457 EVT ResultVT = Result.getValueType();
4458 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4459 SDValue Undef = DAG.getUNDEF(ResultVT);
4460 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4463 // The blend instruction, and therefore its mask, depend on the data type.
4464 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4465 if (ScalarType.isFloatingPoint()) {
4466 // Choose either vblendps (float) or vblendpd (double).
4467 unsigned ScalarSize = ScalarType.getSizeInBits();
4468 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4469 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4470 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4471 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4474 const X86Subtarget &Subtarget =
4475 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4477 // AVX2 is needed for 256-bit integer blend support.
4478 // Integers must be cast to 32-bit because there is only vpblendd;
4479 // vpblendw can't be used for this because it has a handicapped mask.
4481 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4482 // is still more efficient than using the wrong domain vinsertf128 that
4483 // will be created by InsertSubVector().
4484 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4486 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4487 Vec256 = DAG.getBitcast(CastVT, Vec256);
4488 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4489 return DAG.getBitcast(ResultVT, Vec256);
4492 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4495 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4496 SelectionDAG &DAG, SDLoc dl) {
4497 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4498 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4501 /// Insert i1-subvector to i1-vector.
4502 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4505 SDValue Vec = Op.getOperand(0);
4506 SDValue SubVec = Op.getOperand(1);
4507 SDValue Idx = Op.getOperand(2);
4509 if (!isa<ConstantSDNode>(Idx))
4512 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4513 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4516 MVT OpVT = Op.getSimpleValueType();
4517 MVT SubVecVT = SubVec.getSimpleValueType();
4518 unsigned NumElems = OpVT.getVectorNumElements();
4519 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4521 assert(IdxVal + SubVecNumElems <= NumElems &&
4522 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4523 "Unexpected index value in INSERT_SUBVECTOR");
4525 // There are 3 possible cases:
4526 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4527 // 2. Subvector should be inserted in the upper part
4528 // (IdxVal + SubVecNumElems == NumElems)
4529 // 3. Subvector should be inserted in the middle (for example v2i1
4530 // to v16i1, index 2)
4532 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4533 SDValue Undef = DAG.getUNDEF(OpVT);
4534 SDValue WideSubVec =
4535 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4537 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4538 DAG.getConstant(IdxVal, dl, MVT::i8));
4540 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4541 unsigned ShiftLeft = NumElems - SubVecNumElems;
4542 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4543 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4544 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4545 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4546 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4550 // Zero lower bits of the Vec
4551 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4552 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4553 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4554 // Merge them together
4555 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4558 // Simple case when we put subvector in the upper part
4559 if (IdxVal + SubVecNumElems == NumElems) {
4560 // Zero upper bits of the Vec
4561 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4562 DAG.getConstant(IdxVal, dl, MVT::i8));
4563 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4564 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4565 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4566 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4568 // Subvector should be inserted in the middle - use shuffle
4569 SmallVector<int, 64> Mask;
4570 for (unsigned i = 0; i < NumElems; ++i)
4571 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4573 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4576 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4577 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4578 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4579 /// large BUILD_VECTORS.
4580 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4581 unsigned NumElems, SelectionDAG &DAG,
4583 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4584 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4587 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4588 unsigned NumElems, SelectionDAG &DAG,
4590 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4591 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4594 /// Returns a vector of specified type with all bits set.
4595 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4596 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4597 /// Then bitcast to their original type, ensuring they get CSE'd.
4598 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4599 SelectionDAG &DAG, SDLoc dl) {
4600 assert(VT.isVector() && "Expected a vector type");
4602 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4604 if (VT.is512BitVector()) {
4605 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4606 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4607 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4608 } else if (VT.is256BitVector()) {
4609 if (Subtarget->hasInt256()) { // AVX2
4610 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4611 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4613 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4614 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4616 } else if (VT.is128BitVector()) {
4617 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4619 llvm_unreachable("Unexpected vector type");
4621 return DAG.getBitcast(VT, Vec);
4624 /// Returns a vector_shuffle node for an unpackl operation.
4625 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4627 unsigned NumElems = VT.getVectorNumElements();
4628 SmallVector<int, 8> Mask;
4629 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4631 Mask.push_back(i + NumElems);
4633 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4636 /// Returns a vector_shuffle node for an unpackh operation.
4637 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4639 unsigned NumElems = VT.getVectorNumElements();
4640 SmallVector<int, 8> Mask;
4641 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4642 Mask.push_back(i + Half);
4643 Mask.push_back(i + NumElems + Half);
4645 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4648 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4649 /// This produces a shuffle where the low element of V2 is swizzled into the
4650 /// zero/undef vector, landing at element Idx.
4651 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4652 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4654 const X86Subtarget *Subtarget,
4655 SelectionDAG &DAG) {
4656 MVT VT = V2.getSimpleValueType();
4658 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4659 unsigned NumElems = VT.getVectorNumElements();
4660 SmallVector<int, 16> MaskVec;
4661 for (unsigned i = 0; i != NumElems; ++i)
4662 // If this is the insertion idx, put the low elt of V2 here.
4663 MaskVec.push_back(i == Idx ? NumElems : i);
4664 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4667 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4668 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4669 /// uses one source. Note that this will set IsUnary for shuffles which use a
4670 /// single input multiple times, and in those cases it will
4671 /// adjust the mask to only have indices within that single input.
4672 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4673 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4674 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4675 unsigned NumElems = VT.getVectorNumElements();
4679 bool IsFakeUnary = false;
4680 switch(N->getOpcode()) {
4681 case X86ISD::BLENDI:
4682 ImmN = N->getOperand(N->getNumOperands()-1);
4683 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4686 ImmN = N->getOperand(N->getNumOperands()-1);
4687 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4688 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4690 case X86ISD::UNPCKH:
4691 DecodeUNPCKHMask(VT, Mask);
4692 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4694 case X86ISD::UNPCKL:
4695 DecodeUNPCKLMask(VT, Mask);
4696 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4698 case X86ISD::MOVHLPS:
4699 DecodeMOVHLPSMask(NumElems, Mask);
4700 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4702 case X86ISD::MOVLHPS:
4703 DecodeMOVLHPSMask(NumElems, Mask);
4704 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4706 case X86ISD::PALIGNR:
4707 ImmN = N->getOperand(N->getNumOperands()-1);
4708 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4710 case X86ISD::PSHUFD:
4711 case X86ISD::VPERMILPI:
4712 ImmN = N->getOperand(N->getNumOperands()-1);
4713 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4716 case X86ISD::PSHUFHW:
4717 ImmN = N->getOperand(N->getNumOperands()-1);
4718 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4721 case X86ISD::PSHUFLW:
4722 ImmN = N->getOperand(N->getNumOperands()-1);
4723 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4726 case X86ISD::PSHUFB: {
4728 SDValue MaskNode = N->getOperand(1);
4729 while (MaskNode->getOpcode() == ISD::BITCAST)
4730 MaskNode = MaskNode->getOperand(0);
4732 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4733 // If we have a build-vector, then things are easy.
4734 MVT VT = MaskNode.getSimpleValueType();
4735 assert(VT.isVector() &&
4736 "Can't produce a non-vector with a build_vector!");
4737 if (!VT.isInteger())
4740 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4742 SmallVector<uint64_t, 32> RawMask;
4743 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4744 SDValue Op = MaskNode->getOperand(i);
4745 if (Op->getOpcode() == ISD::UNDEF) {
4746 RawMask.push_back((uint64_t)SM_SentinelUndef);
4749 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4752 APInt MaskElement = CN->getAPIntValue();
4754 // We now have to decode the element which could be any integer size and
4755 // extract each byte of it.
4756 for (int j = 0; j < NumBytesPerElement; ++j) {
4757 // Note that this is x86 and so always little endian: the low byte is
4758 // the first byte of the mask.
4759 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4760 MaskElement = MaskElement.lshr(8);
4763 DecodePSHUFBMask(RawMask, Mask);
4767 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4771 SDValue Ptr = MaskLoad->getBasePtr();
4772 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4773 Ptr->getOpcode() == X86ISD::WrapperRIP)
4774 Ptr = Ptr->getOperand(0);
4776 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4777 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4780 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4781 DecodePSHUFBMask(C, Mask);
4789 case X86ISD::VPERMI:
4790 ImmN = N->getOperand(N->getNumOperands()-1);
4791 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4796 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4798 case X86ISD::VPERM2X128:
4799 ImmN = N->getOperand(N->getNumOperands()-1);
4800 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4801 if (Mask.empty()) return false;
4802 // Mask only contains negative index if an element is zero.
4803 if (std::any_of(Mask.begin(), Mask.end(),
4804 [](int M){ return M == SM_SentinelZero; }))
4807 case X86ISD::MOVSLDUP:
4808 DecodeMOVSLDUPMask(VT, Mask);
4811 case X86ISD::MOVSHDUP:
4812 DecodeMOVSHDUPMask(VT, Mask);
4815 case X86ISD::MOVDDUP:
4816 DecodeMOVDDUPMask(VT, Mask);
4819 case X86ISD::MOVLHPD:
4820 case X86ISD::MOVLPD:
4821 case X86ISD::MOVLPS:
4822 // Not yet implemented
4824 case X86ISD::VPERMV: {
4826 SDValue MaskNode = N->getOperand(0);
4827 while (MaskNode->getOpcode() == ISD::BITCAST)
4828 MaskNode = MaskNode->getOperand(0);
4830 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4831 SmallVector<uint64_t, 32> RawMask;
4832 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4833 // If we have a build-vector, then things are easy.
4834 assert(MaskNode.getSimpleValueType().isInteger() &&
4835 MaskNode.getSimpleValueType().getVectorNumElements() ==
4836 VT.getVectorNumElements());
4838 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4839 SDValue Op = MaskNode->getOperand(i);
4840 if (Op->getOpcode() == ISD::UNDEF)
4841 RawMask.push_back((uint64_t)SM_SentinelUndef);
4842 else if (isa<ConstantSDNode>(Op)) {
4843 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4844 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4848 DecodeVPERMVMask(RawMask, Mask);
4851 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4852 unsigned NumEltsInMask = MaskNode->getNumOperands();
4853 MaskNode = MaskNode->getOperand(0);
4854 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4856 APInt MaskEltValue = CN->getAPIntValue();
4857 for (unsigned i = 0; i < NumEltsInMask; ++i)
4858 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4859 DecodeVPERMVMask(RawMask, Mask);
4862 // It may be a scalar load
4865 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4869 SDValue Ptr = MaskLoad->getBasePtr();
4870 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4871 Ptr->getOpcode() == X86ISD::WrapperRIP)
4872 Ptr = Ptr->getOperand(0);
4874 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4875 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4878 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4880 DecodeVPERMVMask(C, VT, Mask);
4887 case X86ISD::VPERMV3: {
4889 SDValue MaskNode = N->getOperand(1);
4890 while (MaskNode->getOpcode() == ISD::BITCAST)
4891 MaskNode = MaskNode->getOperand(1);
4893 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4894 // If we have a build-vector, then things are easy.
4895 assert(MaskNode.getSimpleValueType().isInteger() &&
4896 MaskNode.getSimpleValueType().getVectorNumElements() ==
4897 VT.getVectorNumElements());
4899 SmallVector<uint64_t, 32> RawMask;
4900 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4902 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4903 SDValue Op = MaskNode->getOperand(i);
4904 if (Op->getOpcode() == ISD::UNDEF)
4905 RawMask.push_back((uint64_t)SM_SentinelUndef);
4907 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4910 APInt MaskElement = CN->getAPIntValue();
4911 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4914 DecodeVPERMV3Mask(RawMask, Mask);
4918 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4922 SDValue Ptr = MaskLoad->getBasePtr();
4923 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4924 Ptr->getOpcode() == X86ISD::WrapperRIP)
4925 Ptr = Ptr->getOperand(0);
4927 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4928 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4931 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4933 DecodeVPERMV3Mask(C, VT, Mask);
4940 default: llvm_unreachable("unknown target shuffle node");
4943 // If we have a fake unary shuffle, the shuffle mask is spread across two
4944 // inputs that are actually the same node. Re-map the mask to always point
4945 // into the first input.
4948 if (M >= (int)Mask.size())
4954 /// Returns the scalar element that will make up the ith
4955 /// element of the result of the vector shuffle.
4956 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4959 return SDValue(); // Limit search depth.
4961 SDValue V = SDValue(N, 0);
4962 EVT VT = V.getValueType();
4963 unsigned Opcode = V.getOpcode();
4965 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4966 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4967 int Elt = SV->getMaskElt(Index);
4970 return DAG.getUNDEF(VT.getVectorElementType());
4972 unsigned NumElems = VT.getVectorNumElements();
4973 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4974 : SV->getOperand(1);
4975 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4978 // Recurse into target specific vector shuffles to find scalars.
4979 if (isTargetShuffle(Opcode)) {
4980 MVT ShufVT = V.getSimpleValueType();
4981 unsigned NumElems = ShufVT.getVectorNumElements();
4982 SmallVector<int, 16> ShuffleMask;
4985 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4988 int Elt = ShuffleMask[Index];
4990 return DAG.getUNDEF(ShufVT.getVectorElementType());
4992 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4994 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4998 // Actual nodes that may contain scalar elements
4999 if (Opcode == ISD::BITCAST) {
5000 V = V.getOperand(0);
5001 EVT SrcVT = V.getValueType();
5002 unsigned NumElems = VT.getVectorNumElements();
5004 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5008 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5009 return (Index == 0) ? V.getOperand(0)
5010 : DAG.getUNDEF(VT.getVectorElementType());
5012 if (V.getOpcode() == ISD::BUILD_VECTOR)
5013 return V.getOperand(Index);
5018 /// Custom lower build_vector of v16i8.
5019 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5020 unsigned NumNonZero, unsigned NumZero,
5022 const X86Subtarget* Subtarget,
5023 const TargetLowering &TLI) {
5031 // SSE4.1 - use PINSRB to insert each byte directly.
5032 if (Subtarget->hasSSE41()) {
5033 for (unsigned i = 0; i < 16; ++i) {
5034 bool isNonZero = (NonZeros & (1 << i)) != 0;
5038 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5040 V = DAG.getUNDEF(MVT::v16i8);
5043 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5044 MVT::v16i8, V, Op.getOperand(i),
5045 DAG.getIntPtrConstant(i, dl));
5052 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5053 for (unsigned i = 0; i < 16; ++i) {
5054 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5055 if (ThisIsNonZero && First) {
5057 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5059 V = DAG.getUNDEF(MVT::v8i16);
5064 SDValue ThisElt, LastElt;
5065 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5066 if (LastIsNonZero) {
5067 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5068 MVT::i16, Op.getOperand(i-1));
5070 if (ThisIsNonZero) {
5071 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5072 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5073 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5075 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5079 if (ThisElt.getNode())
5080 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5081 DAG.getIntPtrConstant(i/2, dl));
5085 return DAG.getBitcast(MVT::v16i8, V);
5088 /// Custom lower build_vector of v8i16.
5089 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5090 unsigned NumNonZero, unsigned NumZero,
5092 const X86Subtarget* Subtarget,
5093 const TargetLowering &TLI) {
5100 for (unsigned i = 0; i < 8; ++i) {
5101 bool isNonZero = (NonZeros & (1 << i)) != 0;
5105 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5107 V = DAG.getUNDEF(MVT::v8i16);
5110 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5111 MVT::v8i16, V, Op.getOperand(i),
5112 DAG.getIntPtrConstant(i, dl));
5119 /// Custom lower build_vector of v4i32 or v4f32.
5120 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5121 const X86Subtarget *Subtarget,
5122 const TargetLowering &TLI) {
5123 // Find all zeroable elements.
5124 std::bitset<4> Zeroable;
5125 for (int i=0; i < 4; ++i) {
5126 SDValue Elt = Op->getOperand(i);
5127 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5129 assert(Zeroable.size() - Zeroable.count() > 1 &&
5130 "We expect at least two non-zero elements!");
5132 // We only know how to deal with build_vector nodes where elements are either
5133 // zeroable or extract_vector_elt with constant index.
5134 SDValue FirstNonZero;
5135 unsigned FirstNonZeroIdx;
5136 for (unsigned i=0; i < 4; ++i) {
5139 SDValue Elt = Op->getOperand(i);
5140 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5141 !isa<ConstantSDNode>(Elt.getOperand(1)))
5143 // Make sure that this node is extracting from a 128-bit vector.
5144 MVT VT = Elt.getOperand(0).getSimpleValueType();
5145 if (!VT.is128BitVector())
5147 if (!FirstNonZero.getNode()) {
5149 FirstNonZeroIdx = i;
5153 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5154 SDValue V1 = FirstNonZero.getOperand(0);
5155 MVT VT = V1.getSimpleValueType();
5157 // See if this build_vector can be lowered as a blend with zero.
5159 unsigned EltMaskIdx, EltIdx;
5161 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5162 if (Zeroable[EltIdx]) {
5163 // The zero vector will be on the right hand side.
5164 Mask[EltIdx] = EltIdx+4;
5168 Elt = Op->getOperand(EltIdx);
5169 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5170 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5171 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5173 Mask[EltIdx] = EltIdx;
5177 // Let the shuffle legalizer deal with blend operations.
5178 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5179 if (V1.getSimpleValueType() != VT)
5180 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5181 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5184 // See if we can lower this build_vector to a INSERTPS.
5185 if (!Subtarget->hasSSE41())
5188 SDValue V2 = Elt.getOperand(0);
5189 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5192 bool CanFold = true;
5193 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5197 SDValue Current = Op->getOperand(i);
5198 SDValue SrcVector = Current->getOperand(0);
5201 CanFold = SrcVector == V1 &&
5202 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5208 assert(V1.getNode() && "Expected at least two non-zero elements!");
5209 if (V1.getSimpleValueType() != MVT::v4f32)
5210 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5211 if (V2.getSimpleValueType() != MVT::v4f32)
5212 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5214 // Ok, we can emit an INSERTPS instruction.
5215 unsigned ZMask = Zeroable.to_ulong();
5217 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5218 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5220 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5221 DAG.getIntPtrConstant(InsertPSMask, DL));
5222 return DAG.getBitcast(VT, Result);
5225 /// Return a vector logical shift node.
5226 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5227 unsigned NumBits, SelectionDAG &DAG,
5228 const TargetLowering &TLI, SDLoc dl) {
5229 assert(VT.is128BitVector() && "Unknown type for VShift");
5230 MVT ShVT = MVT::v2i64;
5231 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5232 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5233 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5234 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5235 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5236 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5240 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5242 // Check if the scalar load can be widened into a vector load. And if
5243 // the address is "base + cst" see if the cst can be "absorbed" into
5244 // the shuffle mask.
5245 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5246 SDValue Ptr = LD->getBasePtr();
5247 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5249 EVT PVT = LD->getValueType(0);
5250 if (PVT != MVT::i32 && PVT != MVT::f32)
5255 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5256 FI = FINode->getIndex();
5258 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5259 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5260 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5261 Offset = Ptr.getConstantOperandVal(1);
5262 Ptr = Ptr.getOperand(0);
5267 // FIXME: 256-bit vector instructions don't require a strict alignment,
5268 // improve this code to support it better.
5269 unsigned RequiredAlign = VT.getSizeInBits()/8;
5270 SDValue Chain = LD->getChain();
5271 // Make sure the stack object alignment is at least 16 or 32.
5272 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5273 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5274 if (MFI->isFixedObjectIndex(FI)) {
5275 // Can't change the alignment. FIXME: It's possible to compute
5276 // the exact stack offset and reference FI + adjust offset instead.
5277 // If someone *really* cares about this. That's the way to implement it.
5280 MFI->setObjectAlignment(FI, RequiredAlign);
5284 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5285 // Ptr + (Offset & ~15).
5288 if ((Offset % RequiredAlign) & 3)
5290 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5293 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5294 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5297 int EltNo = (Offset - StartOffset) >> 2;
5298 unsigned NumElems = VT.getVectorNumElements();
5300 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5301 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5302 LD->getPointerInfo().getWithOffset(StartOffset),
5303 false, false, false, 0);
5305 SmallVector<int, 8> Mask(NumElems, EltNo);
5307 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5313 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5314 /// elements can be replaced by a single large load which has the same value as
5315 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5317 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5319 /// FIXME: we'd also like to handle the case where the last elements are zero
5320 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5321 /// There's even a handy isZeroNode for that purpose.
5322 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5323 SDLoc &DL, SelectionDAG &DAG,
5324 bool isAfterLegalize) {
5325 unsigned NumElems = Elts.size();
5327 LoadSDNode *LDBase = nullptr;
5328 unsigned LastLoadedElt = -1U;
5330 // For each element in the initializer, see if we've found a load or an undef.
5331 // If we don't find an initial load element, or later load elements are
5332 // non-consecutive, bail out.
5333 for (unsigned i = 0; i < NumElems; ++i) {
5334 SDValue Elt = Elts[i];
5335 // Look through a bitcast.
5336 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5337 Elt = Elt.getOperand(0);
5338 if (!Elt.getNode() ||
5339 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5342 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5344 LDBase = cast<LoadSDNode>(Elt.getNode());
5348 if (Elt.getOpcode() == ISD::UNDEF)
5351 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5352 EVT LdVT = Elt.getValueType();
5353 // Each loaded element must be the correct fractional portion of the
5354 // requested vector load.
5355 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5357 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5362 // If we have found an entire vector of loads and undefs, then return a large
5363 // load of the entire vector width starting at the base pointer. If we found
5364 // consecutive loads for the low half, generate a vzext_load node.
5365 if (LastLoadedElt == NumElems - 1) {
5366 assert(LDBase && "Did not find base load for merging consecutive loads");
5367 EVT EltVT = LDBase->getValueType(0);
5368 // Ensure that the input vector size for the merged loads matches the
5369 // cumulative size of the input elements.
5370 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5373 if (isAfterLegalize &&
5374 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5377 SDValue NewLd = SDValue();
5379 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5380 LDBase->getPointerInfo(), LDBase->isVolatile(),
5381 LDBase->isNonTemporal(), LDBase->isInvariant(),
5382 LDBase->getAlignment());
5384 if (LDBase->hasAnyUseOfValue(1)) {
5385 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5387 SDValue(NewLd.getNode(), 1));
5388 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5389 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5390 SDValue(NewLd.getNode(), 1));
5396 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5397 //of a v4i32 / v4f32. It's probably worth generalizing.
5398 EVT EltVT = VT.getVectorElementType();
5399 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5400 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5401 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5402 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5404 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5405 LDBase->getPointerInfo(),
5406 LDBase->getAlignment(),
5407 false/*isVolatile*/, true/*ReadMem*/,
5410 // Make sure the newly-created LOAD is in the same position as LDBase in
5411 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5412 // update uses of LDBase's output chain to use the TokenFactor.
5413 if (LDBase->hasAnyUseOfValue(1)) {
5414 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5415 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5416 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5417 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5418 SDValue(ResNode.getNode(), 1));
5421 return DAG.getBitcast(VT, ResNode);
5426 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5427 /// to generate a splat value for the following cases:
5428 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5429 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5430 /// a scalar load, or a constant.
5431 /// The VBROADCAST node is returned when a pattern is found,
5432 /// or SDValue() otherwise.
5433 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5434 SelectionDAG &DAG) {
5435 // VBROADCAST requires AVX.
5436 // TODO: Splats could be generated for non-AVX CPUs using SSE
5437 // instructions, but there's less potential gain for only 128-bit vectors.
5438 if (!Subtarget->hasAVX())
5441 MVT VT = Op.getSimpleValueType();
5444 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5445 "Unsupported vector type for broadcast.");
5450 switch (Op.getOpcode()) {
5452 // Unknown pattern found.
5455 case ISD::BUILD_VECTOR: {
5456 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5457 BitVector UndefElements;
5458 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5460 // We need a splat of a single value to use broadcast, and it doesn't
5461 // make any sense if the value is only in one element of the vector.
5462 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5466 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5467 Ld.getOpcode() == ISD::ConstantFP);
5469 // Make sure that all of the users of a non-constant load are from the
5470 // BUILD_VECTOR node.
5471 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5476 case ISD::VECTOR_SHUFFLE: {
5477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5479 // Shuffles must have a splat mask where the first element is
5481 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5484 SDValue Sc = Op.getOperand(0);
5485 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5486 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5488 if (!Subtarget->hasInt256())
5491 // Use the register form of the broadcast instruction available on AVX2.
5492 if (VT.getSizeInBits() >= 256)
5493 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5494 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5497 Ld = Sc.getOperand(0);
5498 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5499 Ld.getOpcode() == ISD::ConstantFP);
5501 // The scalar_to_vector node and the suspected
5502 // load node must have exactly one user.
5503 // Constants may have multiple users.
5505 // AVX-512 has register version of the broadcast
5506 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5507 Ld.getValueType().getSizeInBits() >= 32;
5508 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5515 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5516 bool IsGE256 = (VT.getSizeInBits() >= 256);
5518 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5519 // instruction to save 8 or more bytes of constant pool data.
5520 // TODO: If multiple splats are generated to load the same constant,
5521 // it may be detrimental to overall size. There needs to be a way to detect
5522 // that condition to know if this is truly a size win.
5523 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5525 // Handle broadcasting a single constant scalar from the constant pool
5527 // On Sandybridge (no AVX2), it is still better to load a constant vector
5528 // from the constant pool and not to broadcast it from a scalar.
5529 // But override that restriction when optimizing for size.
5530 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5531 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5532 EVT CVT = Ld.getValueType();
5533 assert(!CVT.isVector() && "Must not broadcast a vector type");
5535 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5536 // For size optimization, also splat v2f64 and v2i64, and for size opt
5537 // with AVX2, also splat i8 and i16.
5538 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5539 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5540 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5541 const Constant *C = nullptr;
5542 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5543 C = CI->getConstantIntValue();
5544 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5545 C = CF->getConstantFPValue();
5547 assert(C && "Invalid constant type");
5549 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5551 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5552 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5554 CVT, dl, DAG.getEntryNode(), CP,
5555 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5556 false, false, Alignment);
5558 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5562 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5564 // Handle AVX2 in-register broadcasts.
5565 if (!IsLoad && Subtarget->hasInt256() &&
5566 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5567 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5569 // The scalar source must be a normal load.
5573 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5574 (Subtarget->hasVLX() && ScalarSize == 64))
5575 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5577 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5578 // double since there is no vbroadcastsd xmm
5579 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5580 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5581 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5584 // Unsupported broadcast.
5588 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5589 /// underlying vector and index.
5591 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5593 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5595 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5596 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5599 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5601 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5603 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5604 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5607 // In this case the vector is the extract_subvector expression and the index
5608 // is 2, as specified by the shuffle.
5609 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5610 SDValue ShuffleVec = SVOp->getOperand(0);
5611 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5612 assert(ShuffleVecVT.getVectorElementType() ==
5613 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5615 int ShuffleIdx = SVOp->getMaskElt(Idx);
5616 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5617 ExtractedFromVec = ShuffleVec;
5623 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5624 MVT VT = Op.getSimpleValueType();
5626 // Skip if insert_vec_elt is not supported.
5627 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5628 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5632 unsigned NumElems = Op.getNumOperands();
5636 SmallVector<unsigned, 4> InsertIndices;
5637 SmallVector<int, 8> Mask(NumElems, -1);
5639 for (unsigned i = 0; i != NumElems; ++i) {
5640 unsigned Opc = Op.getOperand(i).getOpcode();
5642 if (Opc == ISD::UNDEF)
5645 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5646 // Quit if more than 1 elements need inserting.
5647 if (InsertIndices.size() > 1)
5650 InsertIndices.push_back(i);
5654 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5655 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5656 // Quit if non-constant index.
5657 if (!isa<ConstantSDNode>(ExtIdx))
5659 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5661 // Quit if extracted from vector of different type.
5662 if (ExtractedFromVec.getValueType() != VT)
5665 if (!VecIn1.getNode())
5666 VecIn1 = ExtractedFromVec;
5667 else if (VecIn1 != ExtractedFromVec) {
5668 if (!VecIn2.getNode())
5669 VecIn2 = ExtractedFromVec;
5670 else if (VecIn2 != ExtractedFromVec)
5671 // Quit if more than 2 vectors to shuffle
5675 if (ExtractedFromVec == VecIn1)
5677 else if (ExtractedFromVec == VecIn2)
5678 Mask[i] = Idx + NumElems;
5681 if (!VecIn1.getNode())
5684 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5685 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5686 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5687 unsigned Idx = InsertIndices[i];
5688 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5689 DAG.getIntPtrConstant(Idx, DL));
5695 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5696 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5697 Op.getScalarValueSizeInBits() == 1 &&
5698 "Can not convert non-constant vector");
5699 uint64_t Immediate = 0;
5700 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5701 SDValue In = Op.getOperand(idx);
5702 if (In.getOpcode() != ISD::UNDEF)
5703 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5707 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5708 return DAG.getConstant(Immediate, dl, VT);
5710 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5712 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5714 MVT VT = Op.getSimpleValueType();
5715 assert((VT.getVectorElementType() == MVT::i1) &&
5716 "Unexpected type in LowerBUILD_VECTORvXi1!");
5719 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5720 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5721 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5722 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5725 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5726 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5727 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5728 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5731 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5732 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5733 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5734 return DAG.getBitcast(VT, Imm);
5735 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5736 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5737 DAG.getIntPtrConstant(0, dl));
5740 // Vector has one or more non-const elements
5741 uint64_t Immediate = 0;
5742 SmallVector<unsigned, 16> NonConstIdx;
5743 bool IsSplat = true;
5744 bool HasConstElts = false;
5746 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5747 SDValue In = Op.getOperand(idx);
5748 if (In.getOpcode() == ISD::UNDEF)
5750 if (!isa<ConstantSDNode>(In))
5751 NonConstIdx.push_back(idx);
5753 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5754 HasConstElts = true;
5758 else if (In != Op.getOperand(SplatIdx))
5762 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5764 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5765 DAG.getConstant(1, dl, VT),
5766 DAG.getConstant(0, dl, VT));
5768 // insert elements one by one
5772 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5773 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5775 else if (HasConstElts)
5776 Imm = DAG.getConstant(0, dl, VT);
5778 Imm = DAG.getUNDEF(VT);
5779 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5780 DstVec = DAG.getBitcast(VT, Imm);
5782 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5783 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5784 DAG.getIntPtrConstant(0, dl));
5787 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5788 unsigned InsertIdx = NonConstIdx[i];
5789 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5790 Op.getOperand(InsertIdx),
5791 DAG.getIntPtrConstant(InsertIdx, dl));
5796 /// \brief Return true if \p N implements a horizontal binop and return the
5797 /// operands for the horizontal binop into V0 and V1.
5799 /// This is a helper function of LowerToHorizontalOp().
5800 /// This function checks that the build_vector \p N in input implements a
5801 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5802 /// operation to match.
5803 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5804 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5805 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5808 /// This function only analyzes elements of \p N whose indices are
5809 /// in range [BaseIdx, LastIdx).
5810 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5812 unsigned BaseIdx, unsigned LastIdx,
5813 SDValue &V0, SDValue &V1) {
5814 EVT VT = N->getValueType(0);
5816 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5817 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5818 "Invalid Vector in input!");
5820 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5821 bool CanFold = true;
5822 unsigned ExpectedVExtractIdx = BaseIdx;
5823 unsigned NumElts = LastIdx - BaseIdx;
5824 V0 = DAG.getUNDEF(VT);
5825 V1 = DAG.getUNDEF(VT);
5827 // Check if N implements a horizontal binop.
5828 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5829 SDValue Op = N->getOperand(i + BaseIdx);
5832 if (Op->getOpcode() == ISD::UNDEF) {
5833 // Update the expected vector extract index.
5834 if (i * 2 == NumElts)
5835 ExpectedVExtractIdx = BaseIdx;
5836 ExpectedVExtractIdx += 2;
5840 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5845 SDValue Op0 = Op.getOperand(0);
5846 SDValue Op1 = Op.getOperand(1);
5848 // Try to match the following pattern:
5849 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5850 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5851 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5852 Op0.getOperand(0) == Op1.getOperand(0) &&
5853 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5854 isa<ConstantSDNode>(Op1.getOperand(1)));
5858 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5859 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5861 if (i * 2 < NumElts) {
5862 if (V0.getOpcode() == ISD::UNDEF) {
5863 V0 = Op0.getOperand(0);
5864 if (V0.getValueType() != VT)
5868 if (V1.getOpcode() == ISD::UNDEF) {
5869 V1 = Op0.getOperand(0);
5870 if (V1.getValueType() != VT)
5873 if (i * 2 == NumElts)
5874 ExpectedVExtractIdx = BaseIdx;
5877 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5878 if (I0 == ExpectedVExtractIdx)
5879 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5880 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5881 // Try to match the following dag sequence:
5882 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5883 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5887 ExpectedVExtractIdx += 2;
5893 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5894 /// a concat_vector.
5896 /// This is a helper function of LowerToHorizontalOp().
5897 /// This function expects two 256-bit vectors called V0 and V1.
5898 /// At first, each vector is split into two separate 128-bit vectors.
5899 /// Then, the resulting 128-bit vectors are used to implement two
5900 /// horizontal binary operations.
5902 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5904 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5905 /// the two new horizontal binop.
5906 /// When Mode is set, the first horizontal binop dag node would take as input
5907 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5908 /// horizontal binop dag node would take as input the lower 128-bit of V1
5909 /// and the upper 128-bit of V1.
5911 /// HADD V0_LO, V0_HI
5912 /// HADD V1_LO, V1_HI
5914 /// Otherwise, the first horizontal binop dag node takes as input the lower
5915 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5916 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5918 /// HADD V0_LO, V1_LO
5919 /// HADD V0_HI, V1_HI
5921 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5922 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5923 /// the upper 128-bits of the result.
5924 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5925 SDLoc DL, SelectionDAG &DAG,
5926 unsigned X86Opcode, bool Mode,
5927 bool isUndefLO, bool isUndefHI) {
5928 EVT VT = V0.getValueType();
5929 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5930 "Invalid nodes in input!");
5932 unsigned NumElts = VT.getVectorNumElements();
5933 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5934 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5935 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5936 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5937 EVT NewVT = V0_LO.getValueType();
5939 SDValue LO = DAG.getUNDEF(NewVT);
5940 SDValue HI = DAG.getUNDEF(NewVT);
5943 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5944 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5945 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5946 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5947 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5949 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5950 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5951 V1_LO->getOpcode() != ISD::UNDEF))
5952 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5954 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5955 V1_HI->getOpcode() != ISD::UNDEF))
5956 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5959 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5962 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5964 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5965 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5966 MVT VT = BV->getSimpleValueType(0);
5967 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5968 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5972 unsigned NumElts = VT.getVectorNumElements();
5973 SDValue InVec0 = DAG.getUNDEF(VT);
5974 SDValue InVec1 = DAG.getUNDEF(VT);
5976 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5977 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5979 // Odd-numbered elements in the input build vector are obtained from
5980 // adding two integer/float elements.
5981 // Even-numbered elements in the input build vector are obtained from
5982 // subtracting two integer/float elements.
5983 unsigned ExpectedOpcode = ISD::FSUB;
5984 unsigned NextExpectedOpcode = ISD::FADD;
5985 bool AddFound = false;
5986 bool SubFound = false;
5988 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5989 SDValue Op = BV->getOperand(i);
5991 // Skip 'undef' values.
5992 unsigned Opcode = Op.getOpcode();
5993 if (Opcode == ISD::UNDEF) {
5994 std::swap(ExpectedOpcode, NextExpectedOpcode);
5998 // Early exit if we found an unexpected opcode.
5999 if (Opcode != ExpectedOpcode)
6002 SDValue Op0 = Op.getOperand(0);
6003 SDValue Op1 = Op.getOperand(1);
6005 // Try to match the following pattern:
6006 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6007 // Early exit if we cannot match that sequence.
6008 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6009 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6010 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6011 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6012 Op0.getOperand(1) != Op1.getOperand(1))
6015 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6019 // We found a valid add/sub node. Update the information accordingly.
6025 // Update InVec0 and InVec1.
6026 if (InVec0.getOpcode() == ISD::UNDEF) {
6027 InVec0 = Op0.getOperand(0);
6028 if (InVec0.getSimpleValueType() != VT)
6031 if (InVec1.getOpcode() == ISD::UNDEF) {
6032 InVec1 = Op1.getOperand(0);
6033 if (InVec1.getSimpleValueType() != VT)
6037 // Make sure that operands in input to each add/sub node always
6038 // come from a same pair of vectors.
6039 if (InVec0 != Op0.getOperand(0)) {
6040 if (ExpectedOpcode == ISD::FSUB)
6043 // FADD is commutable. Try to commute the operands
6044 // and then test again.
6045 std::swap(Op0, Op1);
6046 if (InVec0 != Op0.getOperand(0))
6050 if (InVec1 != Op1.getOperand(0))
6053 // Update the pair of expected opcodes.
6054 std::swap(ExpectedOpcode, NextExpectedOpcode);
6057 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6058 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6059 InVec1.getOpcode() != ISD::UNDEF)
6060 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6065 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6066 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6067 const X86Subtarget *Subtarget,
6068 SelectionDAG &DAG) {
6069 MVT VT = BV->getSimpleValueType(0);
6070 unsigned NumElts = VT.getVectorNumElements();
6071 unsigned NumUndefsLO = 0;
6072 unsigned NumUndefsHI = 0;
6073 unsigned Half = NumElts/2;
6075 // Count the number of UNDEF operands in the build_vector in input.
6076 for (unsigned i = 0, e = Half; i != e; ++i)
6077 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6080 for (unsigned i = Half, e = NumElts; i != e; ++i)
6081 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6084 // Early exit if this is either a build_vector of all UNDEFs or all the
6085 // operands but one are UNDEF.
6086 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6090 SDValue InVec0, InVec1;
6091 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6092 // Try to match an SSE3 float HADD/HSUB.
6093 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6094 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6096 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6097 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6098 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6099 // Try to match an SSSE3 integer HADD/HSUB.
6100 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6101 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6103 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6104 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6107 if (!Subtarget->hasAVX())
6110 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6111 // Try to match an AVX horizontal add/sub of packed single/double
6112 // precision floating point values from 256-bit vectors.
6113 SDValue InVec2, InVec3;
6114 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6115 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6116 ((InVec0.getOpcode() == ISD::UNDEF ||
6117 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6118 ((InVec1.getOpcode() == ISD::UNDEF ||
6119 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6120 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6122 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6123 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6124 ((InVec0.getOpcode() == ISD::UNDEF ||
6125 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6126 ((InVec1.getOpcode() == ISD::UNDEF ||
6127 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6128 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6129 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6130 // Try to match an AVX2 horizontal add/sub of signed integers.
6131 SDValue InVec2, InVec3;
6133 bool CanFold = true;
6135 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6136 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6137 ((InVec0.getOpcode() == ISD::UNDEF ||
6138 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6139 ((InVec1.getOpcode() == ISD::UNDEF ||
6140 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6141 X86Opcode = X86ISD::HADD;
6142 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6143 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6144 ((InVec0.getOpcode() == ISD::UNDEF ||
6145 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6146 ((InVec1.getOpcode() == ISD::UNDEF ||
6147 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6148 X86Opcode = X86ISD::HSUB;
6153 // Fold this build_vector into a single horizontal add/sub.
6154 // Do this only if the target has AVX2.
6155 if (Subtarget->hasAVX2())
6156 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6158 // Do not try to expand this build_vector into a pair of horizontal
6159 // add/sub if we can emit a pair of scalar add/sub.
6160 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6163 // Convert this build_vector into a pair of horizontal binop followed by
6165 bool isUndefLO = NumUndefsLO == Half;
6166 bool isUndefHI = NumUndefsHI == Half;
6167 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6168 isUndefLO, isUndefHI);
6172 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6173 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6175 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6176 X86Opcode = X86ISD::HADD;
6177 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6178 X86Opcode = X86ISD::HSUB;
6179 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6180 X86Opcode = X86ISD::FHADD;
6181 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6182 X86Opcode = X86ISD::FHSUB;
6186 // Don't try to expand this build_vector into a pair of horizontal add/sub
6187 // if we can simply emit a pair of scalar add/sub.
6188 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6191 // Convert this build_vector into two horizontal add/sub followed by
6193 bool isUndefLO = NumUndefsLO == Half;
6194 bool isUndefHI = NumUndefsHI == Half;
6195 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6196 isUndefLO, isUndefHI);
6203 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6206 MVT VT = Op.getSimpleValueType();
6207 MVT ExtVT = VT.getVectorElementType();
6208 unsigned NumElems = Op.getNumOperands();
6210 // Generate vectors for predicate vectors.
6211 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6212 return LowerBUILD_VECTORvXi1(Op, DAG);
6214 // Vectors containing all zeros can be matched by pxor and xorps later
6215 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6216 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6217 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6218 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6221 return getZeroVector(VT, Subtarget, DAG, dl);
6224 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6225 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6226 // vpcmpeqd on 256-bit vectors.
6227 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6228 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6231 if (!VT.is512BitVector())
6232 return getOnesVector(VT, Subtarget, DAG, dl);
6235 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6236 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6238 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6239 return HorizontalOp;
6240 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6243 unsigned EVTBits = ExtVT.getSizeInBits();
6245 unsigned NumZero = 0;
6246 unsigned NumNonZero = 0;
6247 uint64_t NonZeros = 0;
6248 bool IsAllConstants = true;
6249 SmallSet<SDValue, 8> Values;
6250 for (unsigned i = 0; i < NumElems; ++i) {
6251 SDValue Elt = Op.getOperand(i);
6252 if (Elt.getOpcode() == ISD::UNDEF)
6255 if (Elt.getOpcode() != ISD::Constant &&
6256 Elt.getOpcode() != ISD::ConstantFP)
6257 IsAllConstants = false;
6258 if (X86::isZeroNode(Elt))
6261 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6262 NonZeros |= ((uint64_t)1 << i);
6267 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6268 if (NumNonZero == 0)
6269 return DAG.getUNDEF(VT);
6271 // Special case for single non-zero, non-undef, element.
6272 if (NumNonZero == 1) {
6273 unsigned Idx = countTrailingZeros(NonZeros);
6274 SDValue Item = Op.getOperand(Idx);
6276 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6277 // the value are obviously zero, truncate the value to i32 and do the
6278 // insertion that way. Only do this if the value is non-constant or if the
6279 // value is a constant being inserted into element 0. It is cheaper to do
6280 // a constant pool load than it is to do a movd + shuffle.
6281 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6282 (!IsAllConstants || Idx == 0)) {
6283 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6285 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6286 MVT VecVT = MVT::v4i32;
6288 // Truncate the value (which may itself be a constant) to i32, and
6289 // convert it to a vector with movd (S2V+shuffle to zero extend).
6290 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6291 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6292 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6293 Item, Idx * 2, true, Subtarget, DAG));
6297 // If we have a constant or non-constant insertion into the low element of
6298 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6299 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6300 // depending on what the source datatype is.
6303 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6305 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6306 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6307 if (VT.is512BitVector()) {
6308 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6309 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6310 Item, DAG.getIntPtrConstant(0, dl));
6312 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6313 "Expected an SSE value type!");
6314 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6315 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6316 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6319 // We can't directly insert an i8 or i16 into a vector, so zero extend
6321 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6322 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6323 if (VT.is256BitVector()) {
6324 if (Subtarget->hasAVX()) {
6325 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6326 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6328 // Without AVX, we need to extend to a 128-bit vector and then
6329 // insert into the 256-bit vector.
6330 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6331 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6332 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6335 assert(VT.is128BitVector() && "Expected an SSE value type!");
6336 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6337 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6339 return DAG.getBitcast(VT, Item);
6343 // Is it a vector logical left shift?
6344 if (NumElems == 2 && Idx == 1 &&
6345 X86::isZeroNode(Op.getOperand(0)) &&
6346 !X86::isZeroNode(Op.getOperand(1))) {
6347 unsigned NumBits = VT.getSizeInBits();
6348 return getVShift(true, VT,
6349 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6350 VT, Op.getOperand(1)),
6351 NumBits/2, DAG, *this, dl);
6354 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6357 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6358 // is a non-constant being inserted into an element other than the low one,
6359 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6360 // movd/movss) to move this into the low element, then shuffle it into
6362 if (EVTBits == 32) {
6363 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6364 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6368 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6369 if (Values.size() == 1) {
6370 if (EVTBits == 32) {
6371 // Instead of a shuffle like this:
6372 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6373 // Check if it's possible to issue this instead.
6374 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6375 unsigned Idx = countTrailingZeros(NonZeros);
6376 SDValue Item = Op.getOperand(Idx);
6377 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6378 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6383 // A vector full of immediates; various special cases are already
6384 // handled, so this is best done with a single constant-pool load.
6388 // For AVX-length vectors, see if we can use a vector load to get all of the
6389 // elements, otherwise build the individual 128-bit pieces and use
6390 // shuffles to put them in place.
6391 if (VT.is256BitVector() || VT.is512BitVector()) {
6392 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6394 // Check for a build vector of consecutive loads.
6395 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6398 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6400 // Build both the lower and upper subvector.
6401 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6402 makeArrayRef(&V[0], NumElems/2));
6403 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6404 makeArrayRef(&V[NumElems / 2], NumElems/2));
6406 // Recreate the wider vector with the lower and upper part.
6407 if (VT.is256BitVector())
6408 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6409 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6412 // Let legalizer expand 2-wide build_vectors.
6413 if (EVTBits == 64) {
6414 if (NumNonZero == 1) {
6415 // One half is zero or undef.
6416 unsigned Idx = countTrailingZeros(NonZeros);
6417 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6418 Op.getOperand(Idx));
6419 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6424 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6425 if (EVTBits == 8 && NumElems == 16)
6426 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6427 DAG, Subtarget, *this))
6430 if (EVTBits == 16 && NumElems == 8)
6431 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6432 DAG, Subtarget, *this))
6435 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6436 if (EVTBits == 32 && NumElems == 4)
6437 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6440 // If element VT is == 32 bits, turn it into a number of shuffles.
6441 SmallVector<SDValue, 8> V(NumElems);
6442 if (NumElems == 4 && NumZero > 0) {
6443 for (unsigned i = 0; i < 4; ++i) {
6444 bool isZero = !(NonZeros & (1ULL << i));
6446 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6448 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6451 for (unsigned i = 0; i < 2; ++i) {
6452 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6455 V[i] = V[i*2]; // Must be a zero vector.
6458 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6461 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6464 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6469 bool Reverse1 = (NonZeros & 0x3) == 2;
6470 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6474 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6475 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6477 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6480 if (Values.size() > 1 && VT.is128BitVector()) {
6481 // Check for a build vector of consecutive loads.
6482 for (unsigned i = 0; i < NumElems; ++i)
6483 V[i] = Op.getOperand(i);
6485 // Check for elements which are consecutive loads.
6486 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6489 // Check for a build vector from mostly shuffle plus few inserting.
6490 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6493 // For SSE 4.1, use insertps to put the high elements into the low element.
6494 if (Subtarget->hasSSE41()) {
6496 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6497 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6499 Result = DAG.getUNDEF(VT);
6501 for (unsigned i = 1; i < NumElems; ++i) {
6502 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6503 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6504 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6509 // Otherwise, expand into a number of unpckl*, start by extending each of
6510 // our (non-undef) elements to the full vector width with the element in the
6511 // bottom slot of the vector (which generates no code for SSE).
6512 for (unsigned i = 0; i < NumElems; ++i) {
6513 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6514 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6516 V[i] = DAG.getUNDEF(VT);
6519 // Next, we iteratively mix elements, e.g. for v4f32:
6520 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6521 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6522 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6523 unsigned EltStride = NumElems >> 1;
6524 while (EltStride != 0) {
6525 for (unsigned i = 0; i < EltStride; ++i) {
6526 // If V[i+EltStride] is undef and this is the first round of mixing,
6527 // then it is safe to just drop this shuffle: V[i] is already in the
6528 // right place, the one element (since it's the first round) being
6529 // inserted as undef can be dropped. This isn't safe for successive
6530 // rounds because they will permute elements within both vectors.
6531 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6532 EltStride == NumElems/2)
6535 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6544 // 256-bit AVX can use the vinsertf128 instruction
6545 // to create 256-bit vectors from two other 128-bit ones.
6546 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6548 MVT ResVT = Op.getSimpleValueType();
6550 assert((ResVT.is256BitVector() ||
6551 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6553 SDValue V1 = Op.getOperand(0);
6554 SDValue V2 = Op.getOperand(1);
6555 unsigned NumElems = ResVT.getVectorNumElements();
6556 if (ResVT.is256BitVector())
6557 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6559 if (Op.getNumOperands() == 4) {
6560 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6561 ResVT.getVectorNumElements()/2);
6562 SDValue V3 = Op.getOperand(2);
6563 SDValue V4 = Op.getOperand(3);
6564 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6565 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6567 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6570 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6571 const X86Subtarget *Subtarget,
6572 SelectionDAG & DAG) {
6574 MVT ResVT = Op.getSimpleValueType();
6575 unsigned NumOfOperands = Op.getNumOperands();
6577 assert(isPowerOf2_32(NumOfOperands) &&
6578 "Unexpected number of operands in CONCAT_VECTORS");
6580 SDValue Undef = DAG.getUNDEF(ResVT);
6581 if (NumOfOperands > 2) {
6582 // Specialize the cases when all, or all but one, of the operands are undef.
6583 unsigned NumOfDefinedOps = 0;
6585 for (unsigned i = 0; i < NumOfOperands; i++)
6586 if (!Op.getOperand(i).isUndef()) {
6590 if (NumOfDefinedOps == 0)
6592 if (NumOfDefinedOps == 1) {
6593 unsigned SubVecNumElts =
6594 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6595 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6596 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6597 Op.getOperand(OpIdx), IdxVal);
6600 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6601 ResVT.getVectorNumElements()/2);
6602 SmallVector<SDValue, 2> Ops;
6603 for (unsigned i = 0; i < NumOfOperands/2; i++)
6604 Ops.push_back(Op.getOperand(i));
6605 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6607 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6608 Ops.push_back(Op.getOperand(i));
6609 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6610 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6614 SDValue V1 = Op.getOperand(0);
6615 SDValue V2 = Op.getOperand(1);
6616 unsigned NumElems = ResVT.getVectorNumElements();
6617 assert(V1.getValueType() == V2.getValueType() &&
6618 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6619 "Unexpected operands in CONCAT_VECTORS");
6621 if (ResVT.getSizeInBits() >= 16)
6622 return Op; // The operation is legal with KUNPCK
6624 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6625 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6626 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6627 if (IsZeroV1 && IsZeroV2)
6630 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6632 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6634 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6636 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6638 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6641 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6643 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6644 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6647 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6648 const X86Subtarget *Subtarget,
6649 SelectionDAG &DAG) {
6650 MVT VT = Op.getSimpleValueType();
6651 if (VT.getVectorElementType() == MVT::i1)
6652 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6654 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6655 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6656 Op.getNumOperands() == 4)));
6658 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6659 // from two other 128-bit ones.
6661 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6662 return LowerAVXCONCAT_VECTORS(Op, DAG);
6665 //===----------------------------------------------------------------------===//
6666 // Vector shuffle lowering
6668 // This is an experimental code path for lowering vector shuffles on x86. It is
6669 // designed to handle arbitrary vector shuffles and blends, gracefully
6670 // degrading performance as necessary. It works hard to recognize idiomatic
6671 // shuffles and lower them to optimal instruction patterns without leaving
6672 // a framework that allows reasonably efficient handling of all vector shuffle
6674 //===----------------------------------------------------------------------===//
6676 /// \brief Tiny helper function to identify a no-op mask.
6678 /// This is a somewhat boring predicate function. It checks whether the mask
6679 /// array input, which is assumed to be a single-input shuffle mask of the kind
6680 /// used by the X86 shuffle instructions (not a fully general
6681 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6682 /// in-place shuffle are 'no-op's.
6683 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6684 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6685 if (Mask[i] != -1 && Mask[i] != i)
6690 /// \brief Helper function to classify a mask as a single-input mask.
6692 /// This isn't a generic single-input test because in the vector shuffle
6693 /// lowering we canonicalize single inputs to be the first input operand. This
6694 /// means we can more quickly test for a single input by only checking whether
6695 /// an input from the second operand exists. We also assume that the size of
6696 /// mask corresponds to the size of the input vectors which isn't true in the
6697 /// fully general case.
6698 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6700 if (M >= (int)Mask.size())
6705 /// \brief Test whether there are elements crossing 128-bit lanes in this
6708 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6709 /// and we routinely test for these.
6710 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6711 int LaneSize = 128 / VT.getScalarSizeInBits();
6712 int Size = Mask.size();
6713 for (int i = 0; i < Size; ++i)
6714 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6719 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6721 /// This checks a shuffle mask to see if it is performing the same
6722 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6723 /// that it is also not lane-crossing. It may however involve a blend from the
6724 /// same lane of a second vector.
6726 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6727 /// non-trivial to compute in the face of undef lanes. The representation is
6728 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6729 /// entries from both V1 and V2 inputs to the wider mask.
6731 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6732 SmallVectorImpl<int> &RepeatedMask) {
6733 int LaneSize = 128 / VT.getScalarSizeInBits();
6734 RepeatedMask.resize(LaneSize, -1);
6735 int Size = Mask.size();
6736 for (int i = 0; i < Size; ++i) {
6739 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6740 // This entry crosses lanes, so there is no way to model this shuffle.
6743 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6744 if (RepeatedMask[i % LaneSize] == -1)
6745 // This is the first non-undef entry in this slot of a 128-bit lane.
6746 RepeatedMask[i % LaneSize] =
6747 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6748 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6749 // Found a mismatch with the repeated mask.
6755 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6758 /// This is a fast way to test a shuffle mask against a fixed pattern:
6760 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6762 /// It returns true if the mask is exactly as wide as the argument list, and
6763 /// each element of the mask is either -1 (signifying undef) or the value given
6764 /// in the argument.
6765 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6766 ArrayRef<int> ExpectedMask) {
6767 if (Mask.size() != ExpectedMask.size())
6770 int Size = Mask.size();
6772 // If the values are build vectors, we can look through them to find
6773 // equivalent inputs that make the shuffles equivalent.
6774 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6775 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6777 for (int i = 0; i < Size; ++i)
6778 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6779 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6780 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6781 if (!MaskBV || !ExpectedBV ||
6782 MaskBV->getOperand(Mask[i] % Size) !=
6783 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6790 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6792 /// This helper function produces an 8-bit shuffle immediate corresponding to
6793 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6794 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6797 /// NB: We rely heavily on "undef" masks preserving the input lane.
6798 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6799 SelectionDAG &DAG) {
6800 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6801 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6802 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6803 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6804 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6807 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6808 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6809 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6810 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6811 return DAG.getConstant(Imm, DL, MVT::i8);
6814 /// \brief Compute whether each element of a shuffle is zeroable.
6816 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6817 /// Either it is an undef element in the shuffle mask, the element of the input
6818 /// referenced is undef, or the element of the input referenced is known to be
6819 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6820 /// as many lanes with this technique as possible to simplify the remaining
6822 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6823 SDValue V1, SDValue V2) {
6824 SmallBitVector Zeroable(Mask.size(), false);
6826 while (V1.getOpcode() == ISD::BITCAST)
6827 V1 = V1->getOperand(0);
6828 while (V2.getOpcode() == ISD::BITCAST)
6829 V2 = V2->getOperand(0);
6831 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6832 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6834 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6836 // Handle the easy cases.
6837 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6842 // If this is an index into a build_vector node (which has the same number
6843 // of elements), dig out the input value and use it.
6844 SDValue V = M < Size ? V1 : V2;
6845 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6848 SDValue Input = V.getOperand(M % Size);
6849 // The UNDEF opcode check really should be dead code here, but not quite
6850 // worth asserting on (it isn't invalid, just unexpected).
6851 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6858 // X86 has dedicated unpack instructions that can handle specific blend
6859 // operations: UNPCKH and UNPCKL.
6860 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6861 SDValue V1, SDValue V2,
6862 SelectionDAG &DAG) {
6863 int NumElts = VT.getVectorNumElements();
6864 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6865 SmallVector<int, 8> Unpckl;
6866 SmallVector<int, 8> Unpckh;
6868 for (int i = 0; i < NumElts; ++i) {
6869 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6870 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6871 int HiPos = LoPos + NumEltsInLane / 2;
6872 Unpckl.push_back(LoPos);
6873 Unpckh.push_back(HiPos);
6876 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6877 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6878 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6879 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6881 // Commute and try again.
6882 ShuffleVectorSDNode::commuteMask(Unpckl);
6883 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6884 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6886 ShuffleVectorSDNode::commuteMask(Unpckh);
6887 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6888 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6893 /// \brief Try to emit a bitmask instruction for a shuffle.
6895 /// This handles cases where we can model a blend exactly as a bitmask due to
6896 /// one of the inputs being zeroable.
6897 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6898 SDValue V2, ArrayRef<int> Mask,
6899 SelectionDAG &DAG) {
6900 MVT EltVT = VT.getVectorElementType();
6901 int NumEltBits = EltVT.getSizeInBits();
6902 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6903 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6904 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6906 if (EltVT.isFloatingPoint()) {
6907 Zero = DAG.getBitcast(EltVT, Zero);
6908 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6910 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6911 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6913 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6916 if (Mask[i] % Size != i)
6917 return SDValue(); // Not a blend.
6919 V = Mask[i] < Size ? V1 : V2;
6920 else if (V != (Mask[i] < Size ? V1 : V2))
6921 return SDValue(); // Can only let one input through the mask.
6923 VMaskOps[i] = AllOnes;
6926 return SDValue(); // No non-zeroable elements!
6928 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6929 V = DAG.getNode(VT.isFloatingPoint()
6930 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6935 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6937 /// This is used as a fallback approach when first class blend instructions are
6938 /// unavailable. Currently it is only suitable for integer vectors, but could
6939 /// be generalized for floating point vectors if desirable.
6940 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6941 SDValue V2, ArrayRef<int> Mask,
6942 SelectionDAG &DAG) {
6943 assert(VT.isInteger() && "Only supports integer vector types!");
6944 MVT EltVT = VT.getVectorElementType();
6945 int NumEltBits = EltVT.getSizeInBits();
6946 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6947 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6949 SmallVector<SDValue, 16> MaskOps;
6950 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6951 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6952 return SDValue(); // Shuffled input!
6953 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6956 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6957 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6958 // We have to cast V2 around.
6959 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6960 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6961 DAG.getBitcast(MaskVT, V1Mask),
6962 DAG.getBitcast(MaskVT, V2)));
6963 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6966 /// \brief Try to emit a blend instruction for a shuffle.
6968 /// This doesn't do any checks for the availability of instructions for blending
6969 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6970 /// be matched in the backend with the type given. What it does check for is
6971 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6972 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6973 SDValue V2, ArrayRef<int> Original,
6974 const X86Subtarget *Subtarget,
6975 SelectionDAG &DAG) {
6976 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6977 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6978 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6979 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6980 bool ForceV1Zero = false, ForceV2Zero = false;
6982 // Attempt to generate the binary blend mask. If an input is zero then
6983 // we can use any lane.
6984 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6985 unsigned BlendMask = 0;
6986 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6992 if (M == i + Size) {
6993 BlendMask |= 1u << i;
7004 BlendMask |= 1u << i;
7009 return SDValue(); // Shuffled input!
7012 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7014 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7016 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7018 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7019 unsigned ScaledMask = 0;
7020 for (int i = 0; i != Size; ++i)
7021 if (BlendMask & (1u << i))
7022 for (int j = 0; j != Scale; ++j)
7023 ScaledMask |= 1u << (i * Scale + j);
7027 switch (VT.SimpleTy) {
7032 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7033 DAG.getConstant(BlendMask, DL, MVT::i8));
7037 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7041 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7042 // that instruction.
7043 if (Subtarget->hasAVX2()) {
7044 // Scale the blend by the number of 32-bit dwords per element.
7045 int Scale = VT.getScalarSizeInBits() / 32;
7046 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7047 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7048 V1 = DAG.getBitcast(BlendVT, V1);
7049 V2 = DAG.getBitcast(BlendVT, V2);
7050 return DAG.getBitcast(
7051 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7052 DAG.getConstant(BlendMask, DL, MVT::i8)));
7056 // For integer shuffles we need to expand the mask and cast the inputs to
7057 // v8i16s prior to blending.
7058 int Scale = 8 / VT.getVectorNumElements();
7059 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7060 V1 = DAG.getBitcast(MVT::v8i16, V1);
7061 V2 = DAG.getBitcast(MVT::v8i16, V2);
7062 return DAG.getBitcast(VT,
7063 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7064 DAG.getConstant(BlendMask, DL, MVT::i8)));
7068 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7069 SmallVector<int, 8> RepeatedMask;
7070 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7071 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7072 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7074 for (int i = 0; i < 8; ++i)
7075 if (RepeatedMask[i] >= 16)
7076 BlendMask |= 1u << i;
7077 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7078 DAG.getConstant(BlendMask, DL, MVT::i8));
7084 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7085 "256-bit byte-blends require AVX2 support!");
7087 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7088 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7091 // Scale the blend by the number of bytes per element.
7092 int Scale = VT.getScalarSizeInBits() / 8;
7094 // This form of blend is always done on bytes. Compute the byte vector
7096 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7098 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7099 // mix of LLVM's code generator and the x86 backend. We tell the code
7100 // generator that boolean values in the elements of an x86 vector register
7101 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7102 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7103 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7104 // of the element (the remaining are ignored) and 0 in that high bit would
7105 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7106 // the LLVM model for boolean values in vector elements gets the relevant
7107 // bit set, it is set backwards and over constrained relative to x86's
7109 SmallVector<SDValue, 32> VSELECTMask;
7110 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7111 for (int j = 0; j < Scale; ++j)
7112 VSELECTMask.push_back(
7113 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7114 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7117 V1 = DAG.getBitcast(BlendVT, V1);
7118 V2 = DAG.getBitcast(BlendVT, V2);
7119 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7120 DAG.getNode(ISD::BUILD_VECTOR, DL,
7121 BlendVT, VSELECTMask),
7126 llvm_unreachable("Not a supported integer vector type!");
7130 /// \brief Try to lower as a blend of elements from two inputs followed by
7131 /// a single-input permutation.
7133 /// This matches the pattern where we can blend elements from two inputs and
7134 /// then reduce the shuffle to a single-input permutation.
7135 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7138 SelectionDAG &DAG) {
7139 // We build up the blend mask while checking whether a blend is a viable way
7140 // to reduce the shuffle.
7141 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7142 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7144 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7148 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7150 if (BlendMask[Mask[i] % Size] == -1)
7151 BlendMask[Mask[i] % Size] = Mask[i];
7152 else if (BlendMask[Mask[i] % Size] != Mask[i])
7153 return SDValue(); // Can't blend in the needed input!
7155 PermuteMask[i] = Mask[i] % Size;
7158 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7159 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7162 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7163 /// blends and permutes.
7165 /// This matches the extremely common pattern for handling combined
7166 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7167 /// operations. It will try to pick the best arrangement of shuffles and
7169 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7173 SelectionDAG &DAG) {
7174 // Shuffle the input elements into the desired positions in V1 and V2 and
7175 // blend them together.
7176 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7177 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7178 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7179 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7180 if (Mask[i] >= 0 && Mask[i] < Size) {
7181 V1Mask[i] = Mask[i];
7183 } else if (Mask[i] >= Size) {
7184 V2Mask[i] = Mask[i] - Size;
7185 BlendMask[i] = i + Size;
7188 // Try to lower with the simpler initial blend strategy unless one of the
7189 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7190 // shuffle may be able to fold with a load or other benefit. However, when
7191 // we'll have to do 2x as many shuffles in order to achieve this, blending
7192 // first is a better strategy.
7193 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7194 if (SDValue BlendPerm =
7195 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7198 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7199 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7200 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7203 /// \brief Try to lower a vector shuffle as a byte rotation.
7205 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7206 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7207 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7208 /// try to generically lower a vector shuffle through such an pattern. It
7209 /// does not check for the profitability of lowering either as PALIGNR or
7210 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7211 /// This matches shuffle vectors that look like:
7213 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7215 /// Essentially it concatenates V1 and V2, shifts right by some number of
7216 /// elements, and takes the low elements as the result. Note that while this is
7217 /// specified as a *right shift* because x86 is little-endian, it is a *left
7218 /// rotate* of the vector lanes.
7219 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7222 const X86Subtarget *Subtarget,
7223 SelectionDAG &DAG) {
7224 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7226 int NumElts = Mask.size();
7227 int NumLanes = VT.getSizeInBits() / 128;
7228 int NumLaneElts = NumElts / NumLanes;
7230 // We need to detect various ways of spelling a rotation:
7231 // [11, 12, 13, 14, 15, 0, 1, 2]
7232 // [-1, 12, 13, 14, -1, -1, 1, -1]
7233 // [-1, -1, -1, -1, -1, -1, 1, 2]
7234 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7235 // [-1, 4, 5, 6, -1, -1, 9, -1]
7236 // [-1, 4, 5, 6, -1, -1, -1, -1]
7239 for (int l = 0; l < NumElts; l += NumLaneElts) {
7240 for (int i = 0; i < NumLaneElts; ++i) {
7241 if (Mask[l + i] == -1)
7243 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7245 // Get the mod-Size index and lane correct it.
7246 int LaneIdx = (Mask[l + i] % NumElts) - l;
7247 // Make sure it was in this lane.
7248 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7251 // Determine where a rotated vector would have started.
7252 int StartIdx = i - LaneIdx;
7254 // The identity rotation isn't interesting, stop.
7257 // If we found the tail of a vector the rotation must be the missing
7258 // front. If we found the head of a vector, it must be how much of the
7260 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7263 Rotation = CandidateRotation;
7264 else if (Rotation != CandidateRotation)
7265 // The rotations don't match, so we can't match this mask.
7268 // Compute which value this mask is pointing at.
7269 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7271 // Compute which of the two target values this index should be assigned
7272 // to. This reflects whether the high elements are remaining or the low
7273 // elements are remaining.
7274 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7276 // Either set up this value if we've not encountered it before, or check
7277 // that it remains consistent.
7280 else if (TargetV != MaskV)
7281 // This may be a rotation, but it pulls from the inputs in some
7282 // unsupported interleaving.
7287 // Check that we successfully analyzed the mask, and normalize the results.
7288 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7289 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7295 // The actual rotate instruction rotates bytes, so we need to scale the
7296 // rotation based on how many bytes are in the vector lane.
7297 int Scale = 16 / NumLaneElts;
7299 // SSSE3 targets can use the palignr instruction.
7300 if (Subtarget->hasSSSE3()) {
7301 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7302 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7303 Lo = DAG.getBitcast(AlignVT, Lo);
7304 Hi = DAG.getBitcast(AlignVT, Hi);
7306 return DAG.getBitcast(
7307 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7308 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7311 assert(VT.is128BitVector() &&
7312 "Rotate-based lowering only supports 128-bit lowering!");
7313 assert(Mask.size() <= 16 &&
7314 "Can shuffle at most 16 bytes in a 128-bit vector!");
7316 // Default SSE2 implementation
7317 int LoByteShift = 16 - Rotation * Scale;
7318 int HiByteShift = Rotation * Scale;
7320 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7321 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7322 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7324 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7325 DAG.getConstant(LoByteShift, DL, MVT::i8));
7326 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7327 DAG.getConstant(HiByteShift, DL, MVT::i8));
7328 return DAG.getBitcast(VT,
7329 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7332 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7334 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7335 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7336 /// matches elements from one of the input vectors shuffled to the left or
7337 /// right with zeroable elements 'shifted in'. It handles both the strictly
7338 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7341 /// PSHL : (little-endian) left bit shift.
7342 /// [ zz, 0, zz, 2 ]
7343 /// [ -1, 4, zz, -1 ]
7344 /// PSRL : (little-endian) right bit shift.
7346 /// [ -1, -1, 7, zz]
7347 /// PSLLDQ : (little-endian) left byte shift
7348 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7349 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7350 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7351 /// PSRLDQ : (little-endian) right byte shift
7352 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7353 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7354 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7355 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7356 SDValue V2, ArrayRef<int> Mask,
7357 SelectionDAG &DAG) {
7358 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7360 int Size = Mask.size();
7361 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7363 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7364 for (int i = 0; i < Size; i += Scale)
7365 for (int j = 0; j < Shift; ++j)
7366 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7372 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7373 for (int i = 0; i != Size; i += Scale) {
7374 unsigned Pos = Left ? i + Shift : i;
7375 unsigned Low = Left ? i : i + Shift;
7376 unsigned Len = Scale - Shift;
7377 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7378 Low + (V == V1 ? 0 : Size)))
7382 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7383 bool ByteShift = ShiftEltBits > 64;
7384 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7385 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7386 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7388 // Normalize the scale for byte shifts to still produce an i64 element
7390 Scale = ByteShift ? Scale / 2 : Scale;
7392 // We need to round trip through the appropriate type for the shift.
7393 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7394 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7395 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7396 "Illegal integer vector type");
7397 V = DAG.getBitcast(ShiftVT, V);
7399 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7400 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7401 return DAG.getBitcast(VT, V);
7404 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7405 // keep doubling the size of the integer elements up to that. We can
7406 // then shift the elements of the integer vector by whole multiples of
7407 // their width within the elements of the larger integer vector. Test each
7408 // multiple to see if we can find a match with the moved element indices
7409 // and that the shifted in elements are all zeroable.
7410 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7411 for (int Shift = 1; Shift != Scale; ++Shift)
7412 for (bool Left : {true, false})
7413 if (CheckZeros(Shift, Scale, Left))
7414 for (SDValue V : {V1, V2})
7415 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7422 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7423 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7424 SDValue V2, ArrayRef<int> Mask,
7425 SelectionDAG &DAG) {
7426 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7427 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7429 int Size = Mask.size();
7430 int HalfSize = Size / 2;
7431 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7433 // Upper half must be undefined.
7434 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7437 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7438 // Remainder of lower half result is zero and upper half is all undef.
7439 auto LowerAsEXTRQ = [&]() {
7440 // Determine the extraction length from the part of the
7441 // lower half that isn't zeroable.
7443 for (; Len > 0; --Len)
7444 if (!Zeroable[Len - 1])
7446 assert(Len > 0 && "Zeroable shuffle mask");
7448 // Attempt to match first Len sequential elements from the lower half.
7451 for (int i = 0; i != Len; ++i) {
7455 SDValue &V = (M < Size ? V1 : V2);
7458 // The extracted elements must start at a valid index and all mask
7459 // elements must be in the lower half.
7460 if (i > M || M >= HalfSize)
7463 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7474 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7475 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7476 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7477 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7478 DAG.getConstant(BitLen, DL, MVT::i8),
7479 DAG.getConstant(BitIdx, DL, MVT::i8));
7482 if (SDValue ExtrQ = LowerAsEXTRQ())
7485 // INSERTQ: Extract lowest Len elements from lower half of second source and
7486 // insert over first source, starting at Idx.
7487 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7488 auto LowerAsInsertQ = [&]() {
7489 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7492 // Attempt to match first source from mask before insertion point.
7493 if (isUndefInRange(Mask, 0, Idx)) {
7495 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7497 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7503 // Extend the extraction length looking to match both the insertion of
7504 // the second source and the remaining elements of the first.
7505 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7510 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7512 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7518 // Match the remaining elements of the lower half.
7519 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7521 } else if ((!Base || (Base == V1)) &&
7522 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7524 } else if ((!Base || (Base == V2)) &&
7525 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7532 // We may not have a base (first source) - this can safely be undefined.
7534 Base = DAG.getUNDEF(VT);
7536 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7537 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7538 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7539 DAG.getConstant(BitLen, DL, MVT::i8),
7540 DAG.getConstant(BitIdx, DL, MVT::i8));
7547 if (SDValue InsertQ = LowerAsInsertQ())
7553 /// \brief Lower a vector shuffle as a zero or any extension.
7555 /// Given a specific number of elements, element bit width, and extension
7556 /// stride, produce either a zero or any extension based on the available
7557 /// features of the subtarget. The extended elements are consecutive and
7558 /// begin and can start from an offseted element index in the input; to
7559 /// avoid excess shuffling the offset must either being in the bottom lane
7560 /// or at the start of a higher lane. All extended elements must be from
7562 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7563 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7564 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7565 assert(Scale > 1 && "Need a scale to extend.");
7566 int EltBits = VT.getScalarSizeInBits();
7567 int NumElements = VT.getVectorNumElements();
7568 int NumEltsPerLane = 128 / EltBits;
7569 int OffsetLane = Offset / NumEltsPerLane;
7570 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7571 "Only 8, 16, and 32 bit elements can be extended.");
7572 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7573 assert(0 <= Offset && "Extension offset must be positive.");
7574 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7575 "Extension offset must be in the first lane or start an upper lane.");
7577 // Check that an index is in same lane as the base offset.
7578 auto SafeOffset = [&](int Idx) {
7579 return OffsetLane == (Idx / NumEltsPerLane);
7582 // Shift along an input so that the offset base moves to the first element.
7583 auto ShuffleOffset = [&](SDValue V) {
7587 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7588 for (int i = 0; i * Scale < NumElements; ++i) {
7589 int SrcIdx = i + Offset;
7590 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7592 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7595 // Found a valid zext mask! Try various lowering strategies based on the
7596 // input type and available ISA extensions.
7597 if (Subtarget->hasSSE41()) {
7598 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7599 // PUNPCK will catch this in a later shuffle match.
7600 if (Offset && Scale == 2 && VT.is128BitVector())
7602 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7603 NumElements / Scale);
7604 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7605 return DAG.getBitcast(VT, InputV);
7608 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7610 // For any extends we can cheat for larger element sizes and use shuffle
7611 // instructions that can fold with a load and/or copy.
7612 if (AnyExt && EltBits == 32) {
7613 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7615 return DAG.getBitcast(
7616 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7617 DAG.getBitcast(MVT::v4i32, InputV),
7618 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7620 if (AnyExt && EltBits == 16 && Scale > 2) {
7621 int PSHUFDMask[4] = {Offset / 2, -1,
7622 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7623 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7624 DAG.getBitcast(MVT::v4i32, InputV),
7625 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7626 int PSHUFWMask[4] = {1, -1, -1, -1};
7627 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7628 return DAG.getBitcast(
7629 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7630 DAG.getBitcast(MVT::v8i16, InputV),
7631 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7634 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7636 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7637 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7638 assert(VT.is128BitVector() && "Unexpected vector width!");
7640 int LoIdx = Offset * EltBits;
7641 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7642 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7643 DAG.getConstant(EltBits, DL, MVT::i8),
7644 DAG.getConstant(LoIdx, DL, MVT::i8)));
7646 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7647 !SafeOffset(Offset + 1))
7648 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7650 int HiIdx = (Offset + 1) * EltBits;
7651 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7652 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7653 DAG.getConstant(EltBits, DL, MVT::i8),
7654 DAG.getConstant(HiIdx, DL, MVT::i8)));
7655 return DAG.getNode(ISD::BITCAST, DL, VT,
7656 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7659 // If this would require more than 2 unpack instructions to expand, use
7660 // pshufb when available. We can only use more than 2 unpack instructions
7661 // when zero extending i8 elements which also makes it easier to use pshufb.
7662 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7663 assert(NumElements == 16 && "Unexpected byte vector width!");
7664 SDValue PSHUFBMask[16];
7665 for (int i = 0; i < 16; ++i) {
7666 int Idx = Offset + (i / Scale);
7667 PSHUFBMask[i] = DAG.getConstant(
7668 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7670 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7671 return DAG.getBitcast(VT,
7672 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7673 DAG.getNode(ISD::BUILD_VECTOR, DL,
7674 MVT::v16i8, PSHUFBMask)));
7677 // If we are extending from an offset, ensure we start on a boundary that
7678 // we can unpack from.
7679 int AlignToUnpack = Offset % (NumElements / Scale);
7680 if (AlignToUnpack) {
7681 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7682 for (int i = AlignToUnpack; i < NumElements; ++i)
7683 ShMask[i - AlignToUnpack] = i;
7684 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7685 Offset -= AlignToUnpack;
7688 // Otherwise emit a sequence of unpacks.
7690 unsigned UnpackLoHi = X86ISD::UNPCKL;
7691 if (Offset >= (NumElements / 2)) {
7692 UnpackLoHi = X86ISD::UNPCKH;
7693 Offset -= (NumElements / 2);
7696 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7697 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7698 : getZeroVector(InputVT, Subtarget, DAG, DL);
7699 InputV = DAG.getBitcast(InputVT, InputV);
7700 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7704 } while (Scale > 1);
7705 return DAG.getBitcast(VT, InputV);
7708 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7710 /// This routine will try to do everything in its power to cleverly lower
7711 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7712 /// check for the profitability of this lowering, it tries to aggressively
7713 /// match this pattern. It will use all of the micro-architectural details it
7714 /// can to emit an efficient lowering. It handles both blends with all-zero
7715 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7716 /// masking out later).
7718 /// The reason we have dedicated lowering for zext-style shuffles is that they
7719 /// are both incredibly common and often quite performance sensitive.
7720 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7721 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7722 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7723 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7725 int Bits = VT.getSizeInBits();
7726 int NumLanes = Bits / 128;
7727 int NumElements = VT.getVectorNumElements();
7728 int NumEltsPerLane = NumElements / NumLanes;
7729 assert(VT.getScalarSizeInBits() <= 32 &&
7730 "Exceeds 32-bit integer zero extension limit");
7731 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7733 // Define a helper function to check a particular ext-scale and lower to it if
7735 auto Lower = [&](int Scale) -> SDValue {
7740 for (int i = 0; i < NumElements; ++i) {
7743 continue; // Valid anywhere but doesn't tell us anything.
7744 if (i % Scale != 0) {
7745 // Each of the extended elements need to be zeroable.
7749 // We no longer are in the anyext case.
7754 // Each of the base elements needs to be consecutive indices into the
7755 // same input vector.
7756 SDValue V = M < NumElements ? V1 : V2;
7757 M = M % NumElements;
7760 Offset = M - (i / Scale);
7761 } else if (InputV != V)
7762 return SDValue(); // Flip-flopping inputs.
7764 // Offset must start in the lowest 128-bit lane or at the start of an
7766 // FIXME: Is it ever worth allowing a negative base offset?
7767 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7768 (Offset % NumEltsPerLane) == 0))
7771 // If we are offsetting, all referenced entries must come from the same
7773 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7776 if ((M % NumElements) != (Offset + (i / Scale)))
7777 return SDValue(); // Non-consecutive strided elements.
7781 // If we fail to find an input, we have a zero-shuffle which should always
7782 // have already been handled.
7783 // FIXME: Maybe handle this here in case during blending we end up with one?
7787 // If we are offsetting, don't extend if we only match a single input, we
7788 // can always do better by using a basic PSHUF or PUNPCK.
7789 if (Offset != 0 && Matches < 2)
7792 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7793 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7796 // The widest scale possible for extending is to a 64-bit integer.
7797 assert(Bits % 64 == 0 &&
7798 "The number of bits in a vector must be divisible by 64 on x86!");
7799 int NumExtElements = Bits / 64;
7801 // Each iteration, try extending the elements half as much, but into twice as
7803 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7804 assert(NumElements % NumExtElements == 0 &&
7805 "The input vector size must be divisible by the extended size.");
7806 if (SDValue V = Lower(NumElements / NumExtElements))
7810 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7814 // Returns one of the source operands if the shuffle can be reduced to a
7815 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7816 auto CanZExtLowHalf = [&]() {
7817 for (int i = NumElements / 2; i != NumElements; ++i)
7820 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7822 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7827 if (SDValue V = CanZExtLowHalf()) {
7828 V = DAG.getBitcast(MVT::v2i64, V);
7829 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7830 return DAG.getBitcast(VT, V);
7833 // No viable ext lowering found.
7837 /// \brief Try to get a scalar value for a specific element of a vector.
7839 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7840 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7841 SelectionDAG &DAG) {
7842 MVT VT = V.getSimpleValueType();
7843 MVT EltVT = VT.getVectorElementType();
7844 while (V.getOpcode() == ISD::BITCAST)
7845 V = V.getOperand(0);
7846 // If the bitcasts shift the element size, we can't extract an equivalent
7848 MVT NewVT = V.getSimpleValueType();
7849 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7852 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7853 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7854 // Ensure the scalar operand is the same size as the destination.
7855 // FIXME: Add support for scalar truncation where possible.
7856 SDValue S = V.getOperand(Idx);
7857 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7858 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7864 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7866 /// This is particularly important because the set of instructions varies
7867 /// significantly based on whether the operand is a load or not.
7868 static bool isShuffleFoldableLoad(SDValue V) {
7869 while (V.getOpcode() == ISD::BITCAST)
7870 V = V.getOperand(0);
7872 return ISD::isNON_EXTLoad(V.getNode());
7875 /// \brief Try to lower insertion of a single element into a zero vector.
7877 /// This is a common pattern that we have especially efficient patterns to lower
7878 /// across all subtarget feature sets.
7879 static SDValue lowerVectorShuffleAsElementInsertion(
7880 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7881 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7882 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7884 MVT EltVT = VT.getVectorElementType();
7886 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7887 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7889 bool IsV1Zeroable = true;
7890 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7891 if (i != V2Index && !Zeroable[i]) {
7892 IsV1Zeroable = false;
7896 // Check for a single input from a SCALAR_TO_VECTOR node.
7897 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7898 // all the smarts here sunk into that routine. However, the current
7899 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7900 // vector shuffle lowering is dead.
7901 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7903 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7904 // We need to zext the scalar if it is smaller than an i32.
7905 V2S = DAG.getBitcast(EltVT, V2S);
7906 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7907 // Using zext to expand a narrow element won't work for non-zero
7912 // Zero-extend directly to i32.
7914 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7916 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7917 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7918 EltVT == MVT::i16) {
7919 // Either not inserting from the low element of the input or the input
7920 // element size is too small to use VZEXT_MOVL to clear the high bits.
7924 if (!IsV1Zeroable) {
7925 // If V1 can't be treated as a zero vector we have fewer options to lower
7926 // this. We can't support integer vectors or non-zero targets cheaply, and
7927 // the V1 elements can't be permuted in any way.
7928 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7929 if (!VT.isFloatingPoint() || V2Index != 0)
7931 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7932 V1Mask[V2Index] = -1;
7933 if (!isNoopShuffleMask(V1Mask))
7935 // This is essentially a special case blend operation, but if we have
7936 // general purpose blend operations, they are always faster. Bail and let
7937 // the rest of the lowering handle these as blends.
7938 if (Subtarget->hasSSE41())
7941 // Otherwise, use MOVSD or MOVSS.
7942 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7943 "Only two types of floating point element types to handle!");
7944 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7948 // This lowering only works for the low element with floating point vectors.
7949 if (VT.isFloatingPoint() && V2Index != 0)
7952 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7954 V2 = DAG.getBitcast(VT, V2);
7957 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7958 // the desired position. Otherwise it is more efficient to do a vector
7959 // shift left. We know that we can do a vector shift left because all
7960 // the inputs are zero.
7961 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7962 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7963 V2Shuffle[V2Index] = 0;
7964 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7966 V2 = DAG.getBitcast(MVT::v2i64, V2);
7968 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7969 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7970 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7971 DAG.getDataLayout(), VT)));
7972 V2 = DAG.getBitcast(VT, V2);
7978 /// \brief Try to lower broadcast of a single - truncated - integer element,
7979 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7981 /// This assumes we have AVX2.
7982 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7984 const X86Subtarget *Subtarget,
7985 SelectionDAG &DAG) {
7986 assert(Subtarget->hasAVX2() &&
7987 "We can only lower integer broadcasts with AVX2!");
7989 EVT EltVT = VT.getVectorElementType();
7990 EVT V0VT = V0.getValueType();
7992 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7993 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7995 EVT V0EltVT = V0VT.getVectorElementType();
7996 if (!V0EltVT.isInteger())
7999 const unsigned EltSize = EltVT.getSizeInBits();
8000 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8002 // This is only a truncation if the original element type is larger.
8003 if (V0EltSize <= EltSize)
8006 assert(((V0EltSize % EltSize) == 0) &&
8007 "Scalar type sizes must all be powers of 2 on x86!");
8009 const unsigned V0Opc = V0.getOpcode();
8010 const unsigned Scale = V0EltSize / EltSize;
8011 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8013 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8014 V0Opc != ISD::BUILD_VECTOR)
8017 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8019 // If we're extracting non-least-significant bits, shift so we can truncate.
8020 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8021 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8022 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8023 if (const int OffsetIdx = BroadcastIdx % Scale)
8024 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8025 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8027 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8028 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8031 /// \brief Try to lower broadcast of a single element.
8033 /// For convenience, this code also bundles all of the subtarget feature set
8034 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8035 /// a convenient way to factor it out.
8036 /// FIXME: This is very similar to LowerVectorBroadcast - can we merge them?
8037 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8039 const X86Subtarget *Subtarget,
8040 SelectionDAG &DAG) {
8041 if (!Subtarget->hasAVX())
8043 if (VT.isInteger() && !Subtarget->hasAVX2())
8046 // Check that the mask is a broadcast.
8047 int BroadcastIdx = -1;
8049 if (M >= 0 && BroadcastIdx == -1)
8051 else if (M >= 0 && M != BroadcastIdx)
8054 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8055 "a sorted mask where the broadcast "
8058 // Go up the chain of (vector) values to find a scalar load that we can
8059 // combine with the broadcast.
8061 switch (V.getOpcode()) {
8062 case ISD::CONCAT_VECTORS: {
8063 int OperandSize = Mask.size() / V.getNumOperands();
8064 V = V.getOperand(BroadcastIdx / OperandSize);
8065 BroadcastIdx %= OperandSize;
8069 case ISD::INSERT_SUBVECTOR: {
8070 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8071 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8075 int BeginIdx = (int)ConstantIdx->getZExtValue();
8077 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8078 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8079 BroadcastIdx -= BeginIdx;
8090 // Check if this is a broadcast of a scalar. We special case lowering
8091 // for scalars so that we can more effectively fold with loads.
8092 // First, look through bitcast: if the original value has a larger element
8093 // type than the shuffle, the broadcast element is in essence truncated.
8094 // Make that explicit to ease folding.
8095 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8096 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8097 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8098 return TruncBroadcast;
8100 // Also check the simpler case, where we can directly reuse the scalar.
8101 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8102 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8103 V = V.getOperand(BroadcastIdx);
8105 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8106 // Only AVX2 has register broadcasts.
8107 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8109 } else if (MayFoldLoad(V) && !cast<LoadSDNode>(V)->isVolatile()) {
8110 // If we are broadcasting a load that is only used by the shuffle
8111 // then we can reduce the vector load to the broadcasted scalar load.
8112 LoadSDNode *Ld = cast<LoadSDNode>(V);
8113 SDValue BaseAddr = Ld->getOperand(1);
8114 EVT AddrVT = BaseAddr.getValueType();
8115 EVT SVT = VT.getScalarType();
8116 unsigned Offset = BroadcastIdx * SVT.getStoreSize();
8117 SDValue NewAddr = DAG.getNode(
8118 ISD::ADD, DL, AddrVT, BaseAddr,
8119 DAG.getConstant(Offset, DL, AddrVT));
8120 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr,
8121 DAG.getMachineFunction().getMachineMemOperand(
8122 Ld->getMemOperand(), Offset, SVT.getStoreSize()));
8123 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8124 // We can't broadcast from a vector register without AVX2, and we can only
8125 // broadcast from the zero-element of a vector register.
8129 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8132 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8133 // INSERTPS when the V1 elements are already in the correct locations
8134 // because otherwise we can just always use two SHUFPS instructions which
8135 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8136 // perform INSERTPS if a single V1 element is out of place and all V2
8137 // elements are zeroable.
8138 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8140 SelectionDAG &DAG) {
8141 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8142 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8143 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8144 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8146 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8149 int V1DstIndex = -1;
8150 int V2DstIndex = -1;
8151 bool V1UsedInPlace = false;
8153 for (int i = 0; i < 4; ++i) {
8154 // Synthesize a zero mask from the zeroable elements (includes undefs).
8160 // Flag if we use any V1 inputs in place.
8162 V1UsedInPlace = true;
8166 // We can only insert a single non-zeroable element.
8167 if (V1DstIndex != -1 || V2DstIndex != -1)
8171 // V1 input out of place for insertion.
8174 // V2 input for insertion.
8179 // Don't bother if we have no (non-zeroable) element for insertion.
8180 if (V1DstIndex == -1 && V2DstIndex == -1)
8183 // Determine element insertion src/dst indices. The src index is from the
8184 // start of the inserted vector, not the start of the concatenated vector.
8185 unsigned V2SrcIndex = 0;
8186 if (V1DstIndex != -1) {
8187 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8188 // and don't use the original V2 at all.
8189 V2SrcIndex = Mask[V1DstIndex];
8190 V2DstIndex = V1DstIndex;
8193 V2SrcIndex = Mask[V2DstIndex] - 4;
8196 // If no V1 inputs are used in place, then the result is created only from
8197 // the zero mask and the V2 insertion - so remove V1 dependency.
8199 V1 = DAG.getUNDEF(MVT::v4f32);
8201 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8202 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8204 // Insert the V2 element into the desired position.
8206 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8207 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8210 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8211 /// UNPCK instruction.
8213 /// This specifically targets cases where we end up with alternating between
8214 /// the two inputs, and so can permute them into something that feeds a single
8215 /// UNPCK instruction. Note that this routine only targets integer vectors
8216 /// because for floating point vectors we have a generalized SHUFPS lowering
8217 /// strategy that handles everything that doesn't *exactly* match an unpack,
8218 /// making this clever lowering unnecessary.
8219 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8220 SDValue V1, SDValue V2,
8222 SelectionDAG &DAG) {
8223 assert(!VT.isFloatingPoint() &&
8224 "This routine only supports integer vectors.");
8225 assert(!isSingleInputShuffleMask(Mask) &&
8226 "This routine should only be used when blending two inputs.");
8227 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8229 int Size = Mask.size();
8231 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8232 return M >= 0 && M % Size < Size / 2;
8234 int NumHiInputs = std::count_if(
8235 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8237 bool UnpackLo = NumLoInputs >= NumHiInputs;
8239 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8240 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8241 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8243 for (int i = 0; i < Size; ++i) {
8247 // Each element of the unpack contains Scale elements from this mask.
8248 int UnpackIdx = i / Scale;
8250 // We only handle the case where V1 feeds the first slots of the unpack.
8251 // We rely on canonicalization to ensure this is the case.
8252 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8255 // Setup the mask for this input. The indexing is tricky as we have to
8256 // handle the unpack stride.
8257 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8258 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8262 // If we will have to shuffle both inputs to use the unpack, check whether
8263 // we can just unpack first and shuffle the result. If so, skip this unpack.
8264 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8265 !isNoopShuffleMask(V2Mask))
8268 // Shuffle the inputs into place.
8269 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8270 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8272 // Cast the inputs to the type we will use to unpack them.
8273 V1 = DAG.getBitcast(UnpackVT, V1);
8274 V2 = DAG.getBitcast(UnpackVT, V2);
8276 // Unpack the inputs and cast the result back to the desired type.
8277 return DAG.getBitcast(
8278 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8282 // We try each unpack from the largest to the smallest to try and find one
8283 // that fits this mask.
8284 int OrigNumElements = VT.getVectorNumElements();
8285 int OrigScalarSize = VT.getScalarSizeInBits();
8286 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8287 int Scale = ScalarSize / OrigScalarSize;
8288 int NumElements = OrigNumElements / Scale;
8289 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8290 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8294 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8296 if (NumLoInputs == 0 || NumHiInputs == 0) {
8297 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8298 "We have to have *some* inputs!");
8299 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8301 // FIXME: We could consider the total complexity of the permute of each
8302 // possible unpacking. Or at the least we should consider how many
8303 // half-crossings are created.
8304 // FIXME: We could consider commuting the unpacks.
8306 SmallVector<int, 32> PermMask;
8307 PermMask.assign(Size, -1);
8308 for (int i = 0; i < Size; ++i) {
8312 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8315 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8317 return DAG.getVectorShuffle(
8318 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8320 DAG.getUNDEF(VT), PermMask);
8326 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8328 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8329 /// support for floating point shuffles but not integer shuffles. These
8330 /// instructions will incur a domain crossing penalty on some chips though so
8331 /// it is better to avoid lowering through this for integer vectors where
8333 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8334 const X86Subtarget *Subtarget,
8335 SelectionDAG &DAG) {
8337 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8338 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8339 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8340 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8341 ArrayRef<int> Mask = SVOp->getMask();
8342 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8344 if (isSingleInputShuffleMask(Mask)) {
8345 // Use low duplicate instructions for masks that match their pattern.
8346 if (Subtarget->hasSSE3())
8347 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8348 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8350 // Straight shuffle of a single input vector. Simulate this by using the
8351 // single input as both of the "inputs" to this instruction..
8352 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8354 if (Subtarget->hasAVX()) {
8355 // If we have AVX, we can use VPERMILPS which will allow folding a load
8356 // into the shuffle.
8357 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8358 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8361 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8362 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8364 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8365 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8367 // If we have a single input, insert that into V1 if we can do so cheaply.
8368 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8369 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8370 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8372 // Try inverting the insertion since for v2 masks it is easy to do and we
8373 // can't reliably sort the mask one way or the other.
8374 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8375 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8376 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8377 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8381 // Try to use one of the special instruction patterns to handle two common
8382 // blend patterns if a zero-blend above didn't work.
8383 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8384 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8385 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8386 // We can either use a special instruction to load over the low double or
8387 // to move just the low double.
8389 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8391 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8393 if (Subtarget->hasSSE41())
8394 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8398 // Use dedicated unpack instructions for masks that match their pattern.
8400 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8403 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8404 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8405 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8408 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8410 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8411 /// the integer unit to minimize domain crossing penalties. However, for blends
8412 /// it falls back to the floating point shuffle operation with appropriate bit
8414 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8415 const X86Subtarget *Subtarget,
8416 SelectionDAG &DAG) {
8418 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8419 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8420 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8421 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8422 ArrayRef<int> Mask = SVOp->getMask();
8423 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8425 if (isSingleInputShuffleMask(Mask)) {
8426 // Check for being able to broadcast a single element.
8427 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8428 Mask, Subtarget, DAG))
8431 // Straight shuffle of a single input vector. For everything from SSE2
8432 // onward this has a single fast instruction with no scary immediates.
8433 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8434 V1 = DAG.getBitcast(MVT::v4i32, V1);
8435 int WidenedMask[4] = {
8436 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8437 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8438 return DAG.getBitcast(
8440 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8441 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8443 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8444 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8445 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8446 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8448 // If we have a blend of two PACKUS operations an the blend aligns with the
8449 // low and half halves, we can just merge the PACKUS operations. This is
8450 // particularly important as it lets us merge shuffles that this routine itself
8452 auto GetPackNode = [](SDValue V) {
8453 while (V.getOpcode() == ISD::BITCAST)
8454 V = V.getOperand(0);
8456 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8458 if (SDValue V1Pack = GetPackNode(V1))
8459 if (SDValue V2Pack = GetPackNode(V2))
8460 return DAG.getBitcast(MVT::v2i64,
8461 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8462 Mask[0] == 0 ? V1Pack.getOperand(0)
8463 : V1Pack.getOperand(1),
8464 Mask[1] == 2 ? V2Pack.getOperand(0)
8465 : V2Pack.getOperand(1)));
8467 // Try to use shift instructions.
8469 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8472 // When loading a scalar and then shuffling it into a vector we can often do
8473 // the insertion cheaply.
8474 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8475 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8477 // Try inverting the insertion since for v2 masks it is easy to do and we
8478 // can't reliably sort the mask one way or the other.
8479 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8480 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8481 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8484 // We have different paths for blend lowering, but they all must use the
8485 // *exact* same predicate.
8486 bool IsBlendSupported = Subtarget->hasSSE41();
8487 if (IsBlendSupported)
8488 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8492 // Use dedicated unpack instructions for masks that match their pattern.
8494 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8497 // Try to use byte rotation instructions.
8498 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8499 if (Subtarget->hasSSSE3())
8500 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8501 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8504 // If we have direct support for blends, we should lower by decomposing into
8505 // a permute. That will be faster than the domain cross.
8506 if (IsBlendSupported)
8507 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8510 // We implement this with SHUFPD which is pretty lame because it will likely
8511 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8512 // However, all the alternatives are still more cycles and newer chips don't
8513 // have this problem. It would be really nice if x86 had better shuffles here.
8514 V1 = DAG.getBitcast(MVT::v2f64, V1);
8515 V2 = DAG.getBitcast(MVT::v2f64, V2);
8516 return DAG.getBitcast(MVT::v2i64,
8517 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8520 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8522 /// This is used to disable more specialized lowerings when the shufps lowering
8523 /// will happen to be efficient.
8524 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8525 // This routine only handles 128-bit shufps.
8526 assert(Mask.size() == 4 && "Unsupported mask size!");
8528 // To lower with a single SHUFPS we need to have the low half and high half
8529 // each requiring a single input.
8530 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8532 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8538 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8540 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8541 /// It makes no assumptions about whether this is the *best* lowering, it simply
8543 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8544 ArrayRef<int> Mask, SDValue V1,
8545 SDValue V2, SelectionDAG &DAG) {
8546 SDValue LowV = V1, HighV = V2;
8547 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8550 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8552 if (NumV2Elements == 1) {
8554 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8557 // Compute the index adjacent to V2Index and in the same half by toggling
8559 int V2AdjIndex = V2Index ^ 1;
8561 if (Mask[V2AdjIndex] == -1) {
8562 // Handles all the cases where we have a single V2 element and an undef.
8563 // This will only ever happen in the high lanes because we commute the
8564 // vector otherwise.
8566 std::swap(LowV, HighV);
8567 NewMask[V2Index] -= 4;
8569 // Handle the case where the V2 element ends up adjacent to a V1 element.
8570 // To make this work, blend them together as the first step.
8571 int V1Index = V2AdjIndex;
8572 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8573 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8574 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8576 // Now proceed to reconstruct the final blend as we have the necessary
8577 // high or low half formed.
8584 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8585 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8587 } else if (NumV2Elements == 2) {
8588 if (Mask[0] < 4 && Mask[1] < 4) {
8589 // Handle the easy case where we have V1 in the low lanes and V2 in the
8593 } else if (Mask[2] < 4 && Mask[3] < 4) {
8594 // We also handle the reversed case because this utility may get called
8595 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8596 // arrange things in the right direction.
8602 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8603 // trying to place elements directly, just blend them and set up the final
8604 // shuffle to place them.
8606 // The first two blend mask elements are for V1, the second two are for
8608 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8609 Mask[2] < 4 ? Mask[2] : Mask[3],
8610 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8611 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8612 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8613 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8615 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8618 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8619 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8620 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8621 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8624 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8625 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8628 /// \brief Lower 4-lane 32-bit floating point shuffles.
8630 /// Uses instructions exclusively from the floating point unit to minimize
8631 /// domain crossing penalties, as these are sufficient to implement all v4f32
8633 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8634 const X86Subtarget *Subtarget,
8635 SelectionDAG &DAG) {
8637 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8638 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8639 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8640 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8641 ArrayRef<int> Mask = SVOp->getMask();
8642 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8645 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8647 if (NumV2Elements == 0) {
8648 // Check for being able to broadcast a single element.
8649 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8650 Mask, Subtarget, DAG))
8653 // Use even/odd duplicate instructions for masks that match their pattern.
8654 if (Subtarget->hasSSE3()) {
8655 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8656 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8657 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8658 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8661 if (Subtarget->hasAVX()) {
8662 // If we have AVX, we can use VPERMILPS which will allow folding a load
8663 // into the shuffle.
8664 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8665 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8668 // Otherwise, use a straight shuffle of a single input vector. We pass the
8669 // input vector to both operands to simulate this with a SHUFPS.
8670 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8671 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8674 // There are special ways we can lower some single-element blends. However, we
8675 // have custom ways we can lower more complex single-element blends below that
8676 // we defer to if both this and BLENDPS fail to match, so restrict this to
8677 // when the V2 input is targeting element 0 of the mask -- that is the fast
8679 if (NumV2Elements == 1 && Mask[0] >= 4)
8680 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8681 Mask, Subtarget, DAG))
8684 if (Subtarget->hasSSE41()) {
8685 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8689 // Use INSERTPS if we can complete the shuffle efficiently.
8690 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8693 if (!isSingleSHUFPSMask(Mask))
8694 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8695 DL, MVT::v4f32, V1, V2, Mask, DAG))
8699 // Use dedicated unpack instructions for masks that match their pattern.
8701 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8704 // Otherwise fall back to a SHUFPS lowering strategy.
8705 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8708 /// \brief Lower 4-lane i32 vector shuffles.
8710 /// We try to handle these with integer-domain shuffles where we can, but for
8711 /// blends we use the floating point domain blend instructions.
8712 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8713 const X86Subtarget *Subtarget,
8714 SelectionDAG &DAG) {
8716 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8717 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8718 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8719 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8720 ArrayRef<int> Mask = SVOp->getMask();
8721 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8723 // Whenever we can lower this as a zext, that instruction is strictly faster
8724 // than any alternative. It also allows us to fold memory operands into the
8725 // shuffle in many cases.
8726 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8727 Mask, Subtarget, DAG))
8731 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8733 if (NumV2Elements == 0) {
8734 // Check for being able to broadcast a single element.
8735 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8736 Mask, Subtarget, DAG))
8739 // Straight shuffle of a single input vector. For everything from SSE2
8740 // onward this has a single fast instruction with no scary immediates.
8741 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8742 // but we aren't actually going to use the UNPCK instruction because doing
8743 // so prevents folding a load into this instruction or making a copy.
8744 const int UnpackLoMask[] = {0, 0, 1, 1};
8745 const int UnpackHiMask[] = {2, 2, 3, 3};
8746 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8747 Mask = UnpackLoMask;
8748 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8749 Mask = UnpackHiMask;
8751 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8752 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8755 // Try to use shift instructions.
8757 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8760 // There are special ways we can lower some single-element blends.
8761 if (NumV2Elements == 1)
8762 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8763 Mask, Subtarget, DAG))
8766 // We have different paths for blend lowering, but they all must use the
8767 // *exact* same predicate.
8768 bool IsBlendSupported = Subtarget->hasSSE41();
8769 if (IsBlendSupported)
8770 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8774 if (SDValue Masked =
8775 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8778 // Use dedicated unpack instructions for masks that match their pattern.
8780 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8783 // Try to use byte rotation instructions.
8784 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8785 if (Subtarget->hasSSSE3())
8786 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8787 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8790 // If we have direct support for blends, we should lower by decomposing into
8791 // a permute. That will be faster than the domain cross.
8792 if (IsBlendSupported)
8793 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8796 // Try to lower by permuting the inputs into an unpack instruction.
8797 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8801 // We implement this with SHUFPS because it can blend from two vectors.
8802 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8803 // up the inputs, bypassing domain shift penalties that we would encur if we
8804 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8806 return DAG.getBitcast(
8808 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8809 DAG.getBitcast(MVT::v4f32, V2), Mask));
8812 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8813 /// shuffle lowering, and the most complex part.
8815 /// The lowering strategy is to try to form pairs of input lanes which are
8816 /// targeted at the same half of the final vector, and then use a dword shuffle
8817 /// to place them onto the right half, and finally unpack the paired lanes into
8818 /// their final position.
8820 /// The exact breakdown of how to form these dword pairs and align them on the
8821 /// correct sides is really tricky. See the comments within the function for
8822 /// more of the details.
8824 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8825 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8826 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8827 /// vector, form the analogous 128-bit 8-element Mask.
8828 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8829 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8830 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8831 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8832 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8834 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8835 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8836 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8838 SmallVector<int, 4> LoInputs;
8839 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8840 [](int M) { return M >= 0; });
8841 std::sort(LoInputs.begin(), LoInputs.end());
8842 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8843 SmallVector<int, 4> HiInputs;
8844 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8845 [](int M) { return M >= 0; });
8846 std::sort(HiInputs.begin(), HiInputs.end());
8847 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8849 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8850 int NumHToL = LoInputs.size() - NumLToL;
8852 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8853 int NumHToH = HiInputs.size() - NumLToH;
8854 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8855 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8856 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8857 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8859 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8860 // such inputs we can swap two of the dwords across the half mark and end up
8861 // with <=2 inputs to each half in each half. Once there, we can fall through
8862 // to the generic code below. For example:
8864 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8865 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8867 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8868 // and an existing 2-into-2 on the other half. In this case we may have to
8869 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8870 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8871 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8872 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8873 // half than the one we target for fixing) will be fixed when we re-enter this
8874 // path. We will also combine away any sequence of PSHUFD instructions that
8875 // result into a single instruction. Here is an example of the tricky case:
8877 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8878 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8880 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8882 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8883 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8885 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8886 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8888 // The result is fine to be handled by the generic logic.
8889 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8890 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8891 int AOffset, int BOffset) {
8892 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8893 "Must call this with A having 3 or 1 inputs from the A half.");
8894 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8895 "Must call this with B having 1 or 3 inputs from the B half.");
8896 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8897 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8899 bool ThreeAInputs = AToAInputs.size() == 3;
8901 // Compute the index of dword with only one word among the three inputs in
8902 // a half by taking the sum of the half with three inputs and subtracting
8903 // the sum of the actual three inputs. The difference is the remaining
8906 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8907 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8908 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8909 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8910 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8911 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8912 int TripleNonInputIdx =
8913 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8914 TripleDWord = TripleNonInputIdx / 2;
8916 // We use xor with one to compute the adjacent DWord to whichever one the
8918 OneInputDWord = (OneInput / 2) ^ 1;
8920 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8921 // and BToA inputs. If there is also such a problem with the BToB and AToB
8922 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8923 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8924 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8925 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8926 // Compute how many inputs will be flipped by swapping these DWords. We
8928 // to balance this to ensure we don't form a 3-1 shuffle in the other
8930 int NumFlippedAToBInputs =
8931 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8932 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8933 int NumFlippedBToBInputs =
8934 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8935 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8936 if ((NumFlippedAToBInputs == 1 &&
8937 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8938 (NumFlippedBToBInputs == 1 &&
8939 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8940 // We choose whether to fix the A half or B half based on whether that
8941 // half has zero flipped inputs. At zero, we may not be able to fix it
8942 // with that half. We also bias towards fixing the B half because that
8943 // will more commonly be the high half, and we have to bias one way.
8944 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8945 ArrayRef<int> Inputs) {
8946 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8947 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8948 PinnedIdx ^ 1) != Inputs.end();
8949 // Determine whether the free index is in the flipped dword or the
8950 // unflipped dword based on where the pinned index is. We use this bit
8951 // in an xor to conditionally select the adjacent dword.
8952 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8953 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8954 FixFreeIdx) != Inputs.end();
8955 if (IsFixIdxInput == IsFixFreeIdxInput)
8957 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8958 FixFreeIdx) != Inputs.end();
8959 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8960 "We need to be changing the number of flipped inputs!");
8961 int PSHUFHalfMask[] = {0, 1, 2, 3};
8962 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8963 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8965 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8968 if (M != -1 && M == FixIdx)
8970 else if (M != -1 && M == FixFreeIdx)
8973 if (NumFlippedBToBInputs != 0) {
8975 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8976 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8978 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8979 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8980 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8985 int PSHUFDMask[] = {0, 1, 2, 3};
8986 PSHUFDMask[ADWord] = BDWord;
8987 PSHUFDMask[BDWord] = ADWord;
8990 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8991 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8993 // Adjust the mask to match the new locations of A and B.
8995 if (M != -1 && M/2 == ADWord)
8996 M = 2 * BDWord + M % 2;
8997 else if (M != -1 && M/2 == BDWord)
8998 M = 2 * ADWord + M % 2;
9000 // Recurse back into this routine to re-compute state now that this isn't
9001 // a 3 and 1 problem.
9002 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
9005 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
9006 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
9007 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
9008 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
9010 // At this point there are at most two inputs to the low and high halves from
9011 // each half. That means the inputs can always be grouped into dwords and
9012 // those dwords can then be moved to the correct half with a dword shuffle.
9013 // We use at most one low and one high word shuffle to collect these paired
9014 // inputs into dwords, and finally a dword shuffle to place them.
9015 int PSHUFLMask[4] = {-1, -1, -1, -1};
9016 int PSHUFHMask[4] = {-1, -1, -1, -1};
9017 int PSHUFDMask[4] = {-1, -1, -1, -1};
9019 // First fix the masks for all the inputs that are staying in their
9020 // original halves. This will then dictate the targets of the cross-half
9022 auto fixInPlaceInputs =
9023 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9024 MutableArrayRef<int> SourceHalfMask,
9025 MutableArrayRef<int> HalfMask, int HalfOffset) {
9026 if (InPlaceInputs.empty())
9028 if (InPlaceInputs.size() == 1) {
9029 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9030 InPlaceInputs[0] - HalfOffset;
9031 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9034 if (IncomingInputs.empty()) {
9035 // Just fix all of the in place inputs.
9036 for (int Input : InPlaceInputs) {
9037 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9038 PSHUFDMask[Input / 2] = Input / 2;
9043 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9044 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9045 InPlaceInputs[0] - HalfOffset;
9046 // Put the second input next to the first so that they are packed into
9047 // a dword. We find the adjacent index by toggling the low bit.
9048 int AdjIndex = InPlaceInputs[0] ^ 1;
9049 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9050 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9051 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9053 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9054 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9056 // Now gather the cross-half inputs and place them into a free dword of
9057 // their target half.
9058 // FIXME: This operation could almost certainly be simplified dramatically to
9059 // look more like the 3-1 fixing operation.
9060 auto moveInputsToRightHalf = [&PSHUFDMask](
9061 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9062 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9063 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9065 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9066 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9068 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9070 int LowWord = Word & ~1;
9071 int HighWord = Word | 1;
9072 return isWordClobbered(SourceHalfMask, LowWord) ||
9073 isWordClobbered(SourceHalfMask, HighWord);
9076 if (IncomingInputs.empty())
9079 if (ExistingInputs.empty()) {
9080 // Map any dwords with inputs from them into the right half.
9081 for (int Input : IncomingInputs) {
9082 // If the source half mask maps over the inputs, turn those into
9083 // swaps and use the swapped lane.
9084 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9085 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9086 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9087 Input - SourceOffset;
9088 // We have to swap the uses in our half mask in one sweep.
9089 for (int &M : HalfMask)
9090 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9092 else if (M == Input)
9093 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9095 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9096 Input - SourceOffset &&
9097 "Previous placement doesn't match!");
9099 // Note that this correctly re-maps both when we do a swap and when
9100 // we observe the other side of the swap above. We rely on that to
9101 // avoid swapping the members of the input list directly.
9102 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9105 // Map the input's dword into the correct half.
9106 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9107 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9109 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9111 "Previous placement doesn't match!");
9114 // And just directly shift any other-half mask elements to be same-half
9115 // as we will have mirrored the dword containing the element into the
9116 // same position within that half.
9117 for (int &M : HalfMask)
9118 if (M >= SourceOffset && M < SourceOffset + 4) {
9119 M = M - SourceOffset + DestOffset;
9120 assert(M >= 0 && "This should never wrap below zero!");
9125 // Ensure we have the input in a viable dword of its current half. This
9126 // is particularly tricky because the original position may be clobbered
9127 // by inputs being moved and *staying* in that half.
9128 if (IncomingInputs.size() == 1) {
9129 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9130 int InputFixed = std::find(std::begin(SourceHalfMask),
9131 std::end(SourceHalfMask), -1) -
9132 std::begin(SourceHalfMask) + SourceOffset;
9133 SourceHalfMask[InputFixed - SourceOffset] =
9134 IncomingInputs[0] - SourceOffset;
9135 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9137 IncomingInputs[0] = InputFixed;
9139 } else if (IncomingInputs.size() == 2) {
9140 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9141 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9142 // We have two non-adjacent or clobbered inputs we need to extract from
9143 // the source half. To do this, we need to map them into some adjacent
9144 // dword slot in the source mask.
9145 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9146 IncomingInputs[1] - SourceOffset};
9148 // If there is a free slot in the source half mask adjacent to one of
9149 // the inputs, place the other input in it. We use (Index XOR 1) to
9150 // compute an adjacent index.
9151 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9152 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9153 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9154 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9155 InputsFixed[1] = InputsFixed[0] ^ 1;
9156 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9157 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9158 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9159 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9160 InputsFixed[0] = InputsFixed[1] ^ 1;
9161 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9162 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9163 // The two inputs are in the same DWord but it is clobbered and the
9164 // adjacent DWord isn't used at all. Move both inputs to the free
9166 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9167 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9168 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9169 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9171 // The only way we hit this point is if there is no clobbering
9172 // (because there are no off-half inputs to this half) and there is no
9173 // free slot adjacent to one of the inputs. In this case, we have to
9174 // swap an input with a non-input.
9175 for (int i = 0; i < 4; ++i)
9176 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9177 "We can't handle any clobbers here!");
9178 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9179 "Cannot have adjacent inputs here!");
9181 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9182 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9184 // We also have to update the final source mask in this case because
9185 // it may need to undo the above swap.
9186 for (int &M : FinalSourceHalfMask)
9187 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9188 M = InputsFixed[1] + SourceOffset;
9189 else if (M == InputsFixed[1] + SourceOffset)
9190 M = (InputsFixed[0] ^ 1) + SourceOffset;
9192 InputsFixed[1] = InputsFixed[0] ^ 1;
9195 // Point everything at the fixed inputs.
9196 for (int &M : HalfMask)
9197 if (M == IncomingInputs[0])
9198 M = InputsFixed[0] + SourceOffset;
9199 else if (M == IncomingInputs[1])
9200 M = InputsFixed[1] + SourceOffset;
9202 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9203 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9206 llvm_unreachable("Unhandled input size!");
9209 // Now hoist the DWord down to the right half.
9210 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9211 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9212 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9213 for (int &M : HalfMask)
9214 for (int Input : IncomingInputs)
9216 M = FreeDWord * 2 + Input % 2;
9218 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9219 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9220 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9221 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9223 // Now enact all the shuffles we've computed to move the inputs into their
9225 if (!isNoopShuffleMask(PSHUFLMask))
9226 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9227 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9228 if (!isNoopShuffleMask(PSHUFHMask))
9229 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9230 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9231 if (!isNoopShuffleMask(PSHUFDMask))
9234 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9235 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9237 // At this point, each half should contain all its inputs, and we can then
9238 // just shuffle them into their final position.
9239 assert(std::count_if(LoMask.begin(), LoMask.end(),
9240 [](int M) { return M >= 4; }) == 0 &&
9241 "Failed to lift all the high half inputs to the low mask!");
9242 assert(std::count_if(HiMask.begin(), HiMask.end(),
9243 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9244 "Failed to lift all the low half inputs to the high mask!");
9246 // Do a half shuffle for the low mask.
9247 if (!isNoopShuffleMask(LoMask))
9248 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9249 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9251 // Do a half shuffle with the high mask after shifting its values down.
9252 for (int &M : HiMask)
9255 if (!isNoopShuffleMask(HiMask))
9256 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9257 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9262 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9263 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9264 SDValue V2, ArrayRef<int> Mask,
9265 SelectionDAG &DAG, bool &V1InUse,
9267 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9273 int Size = Mask.size();
9274 int Scale = 16 / Size;
9275 for (int i = 0; i < 16; ++i) {
9276 if (Mask[i / Scale] == -1) {
9277 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9279 const int ZeroMask = 0x80;
9280 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9282 int V2Idx = Mask[i / Scale] < Size
9284 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9285 if (Zeroable[i / Scale])
9286 V1Idx = V2Idx = ZeroMask;
9287 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9288 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9289 V1InUse |= (ZeroMask != V1Idx);
9290 V2InUse |= (ZeroMask != V2Idx);
9295 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9296 DAG.getBitcast(MVT::v16i8, V1),
9297 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9299 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9300 DAG.getBitcast(MVT::v16i8, V2),
9301 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9303 // If we need shuffled inputs from both, blend the two.
9305 if (V1InUse && V2InUse)
9306 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9308 V = V1InUse ? V1 : V2;
9310 // Cast the result back to the correct type.
9311 return DAG.getBitcast(VT, V);
9314 /// \brief Generic lowering of 8-lane i16 shuffles.
9316 /// This handles both single-input shuffles and combined shuffle/blends with
9317 /// two inputs. The single input shuffles are immediately delegated to
9318 /// a dedicated lowering routine.
9320 /// The blends are lowered in one of three fundamental ways. If there are few
9321 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9322 /// of the input is significantly cheaper when lowered as an interleaving of
9323 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9324 /// halves of the inputs separately (making them have relatively few inputs)
9325 /// and then concatenate them.
9326 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9327 const X86Subtarget *Subtarget,
9328 SelectionDAG &DAG) {
9330 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9331 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9332 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9333 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9334 ArrayRef<int> OrigMask = SVOp->getMask();
9335 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9336 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9337 MutableArrayRef<int> Mask(MaskStorage);
9339 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9341 // Whenever we can lower this as a zext, that instruction is strictly faster
9342 // than any alternative.
9343 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9344 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9347 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9349 auto isV2 = [](int M) { return M >= 8; };
9351 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9353 if (NumV2Inputs == 0) {
9354 // Check for being able to broadcast a single element.
9355 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9356 Mask, Subtarget, DAG))
9359 // Try to use shift instructions.
9361 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9364 // Use dedicated unpack instructions for masks that match their pattern.
9366 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9369 // Try to use byte rotation instructions.
9370 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9371 Mask, Subtarget, DAG))
9374 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9378 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9379 "All single-input shuffles should be canonicalized to be V1-input "
9382 // Try to use shift instructions.
9384 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9387 // See if we can use SSE4A Extraction / Insertion.
9388 if (Subtarget->hasSSE4A())
9389 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9392 // There are special ways we can lower some single-element blends.
9393 if (NumV2Inputs == 1)
9394 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9395 Mask, Subtarget, DAG))
9398 // We have different paths for blend lowering, but they all must use the
9399 // *exact* same predicate.
9400 bool IsBlendSupported = Subtarget->hasSSE41();
9401 if (IsBlendSupported)
9402 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9406 if (SDValue Masked =
9407 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9410 // Use dedicated unpack instructions for masks that match their pattern.
9412 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9415 // Try to use byte rotation instructions.
9416 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9417 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9420 if (SDValue BitBlend =
9421 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9424 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9428 // If we can't directly blend but can use PSHUFB, that will be better as it
9429 // can both shuffle and set up the inefficient blend.
9430 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9431 bool V1InUse, V2InUse;
9432 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9436 // We can always bit-blend if we have to so the fallback strategy is to
9437 // decompose into single-input permutes and blends.
9438 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9442 /// \brief Check whether a compaction lowering can be done by dropping even
9443 /// elements and compute how many times even elements must be dropped.
9445 /// This handles shuffles which take every Nth element where N is a power of
9446 /// two. Example shuffle masks:
9448 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9449 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9450 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9451 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9452 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9453 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9455 /// Any of these lanes can of course be undef.
9457 /// This routine only supports N <= 3.
9458 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9461 /// \returns N above, or the number of times even elements must be dropped if
9462 /// there is such a number. Otherwise returns zero.
9463 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9464 // Figure out whether we're looping over two inputs or just one.
9465 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9467 // The modulus for the shuffle vector entries is based on whether this is
9468 // a single input or not.
9469 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9470 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9471 "We should only be called with masks with a power-of-2 size!");
9473 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9475 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9476 // and 2^3 simultaneously. This is because we may have ambiguity with
9477 // partially undef inputs.
9478 bool ViableForN[3] = {true, true, true};
9480 for (int i = 0, e = Mask.size(); i < e; ++i) {
9481 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9486 bool IsAnyViable = false;
9487 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9488 if (ViableForN[j]) {
9491 // The shuffle mask must be equal to (i * 2^N) % M.
9492 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9495 ViableForN[j] = false;
9497 // Early exit if we exhaust the possible powers of two.
9502 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9506 // Return 0 as there is no viable power of two.
9510 /// \brief Generic lowering of v16i8 shuffles.
9512 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9513 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9514 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9515 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9517 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9518 const X86Subtarget *Subtarget,
9519 SelectionDAG &DAG) {
9521 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9522 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9523 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9524 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9525 ArrayRef<int> Mask = SVOp->getMask();
9526 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9528 // Try to use shift instructions.
9530 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9533 // Try to use byte rotation instructions.
9534 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9535 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9538 // Try to use a zext lowering.
9539 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9540 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9543 // See if we can use SSE4A Extraction / Insertion.
9544 if (Subtarget->hasSSE4A())
9545 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9549 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9551 // For single-input shuffles, there are some nicer lowering tricks we can use.
9552 if (NumV2Elements == 0) {
9553 // Check for being able to broadcast a single element.
9554 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9555 Mask, Subtarget, DAG))
9558 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9559 // Notably, this handles splat and partial-splat shuffles more efficiently.
9560 // However, it only makes sense if the pre-duplication shuffle simplifies
9561 // things significantly. Currently, this means we need to be able to
9562 // express the pre-duplication shuffle as an i16 shuffle.
9564 // FIXME: We should check for other patterns which can be widened into an
9565 // i16 shuffle as well.
9566 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9567 for (int i = 0; i < 16; i += 2)
9568 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9573 auto tryToWidenViaDuplication = [&]() -> SDValue {
9574 if (!canWidenViaDuplication(Mask))
9576 SmallVector<int, 4> LoInputs;
9577 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9578 [](int M) { return M >= 0 && M < 8; });
9579 std::sort(LoInputs.begin(), LoInputs.end());
9580 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9582 SmallVector<int, 4> HiInputs;
9583 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9584 [](int M) { return M >= 8; });
9585 std::sort(HiInputs.begin(), HiInputs.end());
9586 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9589 bool TargetLo = LoInputs.size() >= HiInputs.size();
9590 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9591 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9593 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9594 SmallDenseMap<int, int, 8> LaneMap;
9595 for (int I : InPlaceInputs) {
9596 PreDupI16Shuffle[I/2] = I/2;
9599 int j = TargetLo ? 0 : 4, je = j + 4;
9600 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9601 // Check if j is already a shuffle of this input. This happens when
9602 // there are two adjacent bytes after we move the low one.
9603 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9604 // If we haven't yet mapped the input, search for a slot into which
9606 while (j < je && PreDupI16Shuffle[j] != -1)
9610 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9613 // Map this input with the i16 shuffle.
9614 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9617 // Update the lane map based on the mapping we ended up with.
9618 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9620 V1 = DAG.getBitcast(
9622 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9623 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9625 // Unpack the bytes to form the i16s that will be shuffled into place.
9626 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9627 MVT::v16i8, V1, V1);
9629 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9630 for (int i = 0; i < 16; ++i)
9631 if (Mask[i] != -1) {
9632 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9633 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9634 if (PostDupI16Shuffle[i / 2] == -1)
9635 PostDupI16Shuffle[i / 2] = MappedMask;
9637 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9638 "Conflicting entrties in the original shuffle!");
9640 return DAG.getBitcast(
9642 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9643 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9645 if (SDValue V = tryToWidenViaDuplication())
9649 if (SDValue Masked =
9650 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9653 // Use dedicated unpack instructions for masks that match their pattern.
9655 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9658 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9659 // with PSHUFB. It is important to do this before we attempt to generate any
9660 // blends but after all of the single-input lowerings. If the single input
9661 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9662 // want to preserve that and we can DAG combine any longer sequences into
9663 // a PSHUFB in the end. But once we start blending from multiple inputs,
9664 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9665 // and there are *very* few patterns that would actually be faster than the
9666 // PSHUFB approach because of its ability to zero lanes.
9668 // FIXME: The only exceptions to the above are blends which are exact
9669 // interleavings with direct instructions supporting them. We currently don't
9670 // handle those well here.
9671 if (Subtarget->hasSSSE3()) {
9672 bool V1InUse = false;
9673 bool V2InUse = false;
9675 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9676 DAG, V1InUse, V2InUse);
9678 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9679 // do so. This avoids using them to handle blends-with-zero which is
9680 // important as a single pshufb is significantly faster for that.
9681 if (V1InUse && V2InUse) {
9682 if (Subtarget->hasSSE41())
9683 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9684 Mask, Subtarget, DAG))
9687 // We can use an unpack to do the blending rather than an or in some
9688 // cases. Even though the or may be (very minorly) more efficient, we
9689 // preference this lowering because there are common cases where part of
9690 // the complexity of the shuffles goes away when we do the final blend as
9692 // FIXME: It might be worth trying to detect if the unpack-feeding
9693 // shuffles will both be pshufb, in which case we shouldn't bother with
9695 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9696 DL, MVT::v16i8, V1, V2, Mask, DAG))
9703 // There are special ways we can lower some single-element blends.
9704 if (NumV2Elements == 1)
9705 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9706 Mask, Subtarget, DAG))
9709 if (SDValue BitBlend =
9710 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9713 // Check whether a compaction lowering can be done. This handles shuffles
9714 // which take every Nth element for some even N. See the helper function for
9717 // We special case these as they can be particularly efficiently handled with
9718 // the PACKUSB instruction on x86 and they show up in common patterns of
9719 // rearranging bytes to truncate wide elements.
9720 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9721 // NumEvenDrops is the power of two stride of the elements. Another way of
9722 // thinking about it is that we need to drop the even elements this many
9723 // times to get the original input.
9724 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9726 // First we need to zero all the dropped bytes.
9727 assert(NumEvenDrops <= 3 &&
9728 "No support for dropping even elements more than 3 times.");
9729 // We use the mask type to pick which bytes are preserved based on how many
9730 // elements are dropped.
9731 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9732 SDValue ByteClearMask = DAG.getBitcast(
9733 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9734 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9736 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9738 // Now pack things back together.
9739 V1 = DAG.getBitcast(MVT::v8i16, V1);
9740 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9741 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9742 for (int i = 1; i < NumEvenDrops; ++i) {
9743 Result = DAG.getBitcast(MVT::v8i16, Result);
9744 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9750 // Handle multi-input cases by blending single-input shuffles.
9751 if (NumV2Elements > 0)
9752 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9755 // The fallback path for single-input shuffles widens this into two v8i16
9756 // vectors with unpacks, shuffles those, and then pulls them back together
9760 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9761 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9762 for (int i = 0; i < 16; ++i)
9764 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9766 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9768 SDValue VLoHalf, VHiHalf;
9769 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9770 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9772 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9773 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9774 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9775 [](int M) { return M >= 0 && M % 2 == 1; })) {
9776 // Use a mask to drop the high bytes.
9777 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9778 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9779 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9781 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9782 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9784 // Squash the masks to point directly into VLoHalf.
9785 for (int &M : LoBlendMask)
9788 for (int &M : HiBlendMask)
9792 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9793 // VHiHalf so that we can blend them as i16s.
9794 VLoHalf = DAG.getBitcast(
9795 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9796 VHiHalf = DAG.getBitcast(
9797 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9800 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9801 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9803 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9806 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9808 /// This routine breaks down the specific type of 128-bit shuffle and
9809 /// dispatches to the lowering routines accordingly.
9810 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9811 MVT VT, const X86Subtarget *Subtarget,
9812 SelectionDAG &DAG) {
9813 switch (VT.SimpleTy) {
9815 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9817 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9819 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9821 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9823 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9825 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9828 llvm_unreachable("Unimplemented!");
9832 /// \brief Helper function to test whether a shuffle mask could be
9833 /// simplified by widening the elements being shuffled.
9835 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9836 /// leaves it in an unspecified state.
9838 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9839 /// shuffle masks. The latter have the special property of a '-2' representing
9840 /// a zero-ed lane of a vector.
9841 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9842 SmallVectorImpl<int> &WidenedMask) {
9843 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9844 // If both elements are undef, its trivial.
9845 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9846 WidenedMask.push_back(SM_SentinelUndef);
9850 // Check for an undef mask and a mask value properly aligned to fit with
9851 // a pair of values. If we find such a case, use the non-undef mask's value.
9852 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9853 WidenedMask.push_back(Mask[i + 1] / 2);
9856 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9857 WidenedMask.push_back(Mask[i] / 2);
9861 // When zeroing, we need to spread the zeroing across both lanes to widen.
9862 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9863 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9864 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9865 WidenedMask.push_back(SM_SentinelZero);
9871 // Finally check if the two mask values are adjacent and aligned with
9873 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9874 WidenedMask.push_back(Mask[i] / 2);
9878 // Otherwise we can't safely widen the elements used in this shuffle.
9881 assert(WidenedMask.size() == Mask.size() / 2 &&
9882 "Incorrect size of mask after widening the elements!");
9887 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9889 /// This routine just extracts two subvectors, shuffles them independently, and
9890 /// then concatenates them back together. This should work effectively with all
9891 /// AVX vector shuffle types.
9892 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9893 SDValue V2, ArrayRef<int> Mask,
9894 SelectionDAG &DAG) {
9895 assert(VT.getSizeInBits() >= 256 &&
9896 "Only for 256-bit or wider vector shuffles!");
9897 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9898 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9900 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9901 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9903 int NumElements = VT.getVectorNumElements();
9904 int SplitNumElements = NumElements / 2;
9905 MVT ScalarVT = VT.getVectorElementType();
9906 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9908 // Rather than splitting build-vectors, just build two narrower build
9909 // vectors. This helps shuffling with splats and zeros.
9910 auto SplitVector = [&](SDValue V) {
9911 while (V.getOpcode() == ISD::BITCAST)
9912 V = V->getOperand(0);
9914 MVT OrigVT = V.getSimpleValueType();
9915 int OrigNumElements = OrigVT.getVectorNumElements();
9916 int OrigSplitNumElements = OrigNumElements / 2;
9917 MVT OrigScalarVT = OrigVT.getVectorElementType();
9918 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9922 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9924 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9925 DAG.getIntPtrConstant(0, DL));
9926 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9927 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9930 SmallVector<SDValue, 16> LoOps, HiOps;
9931 for (int i = 0; i < OrigSplitNumElements; ++i) {
9932 LoOps.push_back(BV->getOperand(i));
9933 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9935 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9936 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9938 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9939 DAG.getBitcast(SplitVT, HiV));
9942 SDValue LoV1, HiV1, LoV2, HiV2;
9943 std::tie(LoV1, HiV1) = SplitVector(V1);
9944 std::tie(LoV2, HiV2) = SplitVector(V2);
9946 // Now create two 4-way blends of these half-width vectors.
9947 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9948 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9949 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9950 for (int i = 0; i < SplitNumElements; ++i) {
9951 int M = HalfMask[i];
9952 if (M >= NumElements) {
9953 if (M >= NumElements + SplitNumElements)
9957 V2BlendMask.push_back(M - NumElements);
9958 V1BlendMask.push_back(-1);
9959 BlendMask.push_back(SplitNumElements + i);
9960 } else if (M >= 0) {
9961 if (M >= SplitNumElements)
9965 V2BlendMask.push_back(-1);
9966 V1BlendMask.push_back(M);
9967 BlendMask.push_back(i);
9969 V2BlendMask.push_back(-1);
9970 V1BlendMask.push_back(-1);
9971 BlendMask.push_back(-1);
9975 // Because the lowering happens after all combining takes place, we need to
9976 // manually combine these blend masks as much as possible so that we create
9977 // a minimal number of high-level vector shuffle nodes.
9979 // First try just blending the halves of V1 or V2.
9980 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9981 return DAG.getUNDEF(SplitVT);
9982 if (!UseLoV2 && !UseHiV2)
9983 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9984 if (!UseLoV1 && !UseHiV1)
9985 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9987 SDValue V1Blend, V2Blend;
9988 if (UseLoV1 && UseHiV1) {
9990 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9992 // We only use half of V1 so map the usage down into the final blend mask.
9993 V1Blend = UseLoV1 ? LoV1 : HiV1;
9994 for (int i = 0; i < SplitNumElements; ++i)
9995 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9996 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9998 if (UseLoV2 && UseHiV2) {
10000 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10002 // We only use half of V2 so map the usage down into the final blend mask.
10003 V2Blend = UseLoV2 ? LoV2 : HiV2;
10004 for (int i = 0; i < SplitNumElements; ++i)
10005 if (BlendMask[i] >= SplitNumElements)
10006 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
10008 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
10010 SDValue Lo = HalfBlend(LoMask);
10011 SDValue Hi = HalfBlend(HiMask);
10012 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
10015 /// \brief Either split a vector in halves or decompose the shuffles and the
10018 /// This is provided as a good fallback for many lowerings of non-single-input
10019 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10020 /// between splitting the shuffle into 128-bit components and stitching those
10021 /// back together vs. extracting the single-input shuffles and blending those
10023 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10024 SDValue V2, ArrayRef<int> Mask,
10025 SelectionDAG &DAG) {
10026 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10027 "lower single-input shuffles as it "
10028 "could then recurse on itself.");
10029 int Size = Mask.size();
10031 // If this can be modeled as a broadcast of two elements followed by a blend,
10032 // prefer that lowering. This is especially important because broadcasts can
10033 // often fold with memory operands.
10034 auto DoBothBroadcast = [&] {
10035 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10038 if (V2BroadcastIdx == -1)
10039 V2BroadcastIdx = M - Size;
10040 else if (M - Size != V2BroadcastIdx)
10042 } else if (M >= 0) {
10043 if (V1BroadcastIdx == -1)
10044 V1BroadcastIdx = M;
10045 else if (M != V1BroadcastIdx)
10050 if (DoBothBroadcast())
10051 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10054 // If the inputs all stem from a single 128-bit lane of each input, then we
10055 // split them rather than blending because the split will decompose to
10056 // unusually few instructions.
10057 int LaneCount = VT.getSizeInBits() / 128;
10058 int LaneSize = Size / LaneCount;
10059 SmallBitVector LaneInputs[2];
10060 LaneInputs[0].resize(LaneCount, false);
10061 LaneInputs[1].resize(LaneCount, false);
10062 for (int i = 0; i < Size; ++i)
10064 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10065 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10066 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10068 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10069 // that the decomposed single-input shuffles don't end up here.
10070 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10073 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10074 /// a permutation and blend of those lanes.
10076 /// This essentially blends the out-of-lane inputs to each lane into the lane
10077 /// from a permuted copy of the vector. This lowering strategy results in four
10078 /// instructions in the worst case for a single-input cross lane shuffle which
10079 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10080 /// of. Special cases for each particular shuffle pattern should be handled
10081 /// prior to trying this lowering.
10082 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10083 SDValue V1, SDValue V2,
10084 ArrayRef<int> Mask,
10085 SelectionDAG &DAG) {
10086 // FIXME: This should probably be generalized for 512-bit vectors as well.
10087 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10088 int LaneSize = Mask.size() / 2;
10090 // If there are only inputs from one 128-bit lane, splitting will in fact be
10091 // less expensive. The flags track whether the given lane contains an element
10092 // that crosses to another lane.
10093 bool LaneCrossing[2] = {false, false};
10094 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10095 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10096 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10097 if (!LaneCrossing[0] || !LaneCrossing[1])
10098 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10100 if (isSingleInputShuffleMask(Mask)) {
10101 SmallVector<int, 32> FlippedBlendMask;
10102 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10103 FlippedBlendMask.push_back(
10104 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10106 : Mask[i] % LaneSize +
10107 (i / LaneSize) * LaneSize + Size));
10109 // Flip the vector, and blend the results which should now be in-lane. The
10110 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10111 // 5 for the high source. The value 3 selects the high half of source 2 and
10112 // the value 2 selects the low half of source 2. We only use source 2 to
10113 // allow folding it into a memory operand.
10114 unsigned PERMMask = 3 | 2 << 4;
10115 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10116 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10117 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10120 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10121 // will be handled by the above logic and a blend of the results, much like
10122 // other patterns in AVX.
10123 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10126 /// \brief Handle lowering 2-lane 128-bit shuffles.
10127 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10128 SDValue V2, ArrayRef<int> Mask,
10129 const X86Subtarget *Subtarget,
10130 SelectionDAG &DAG) {
10131 // TODO: If minimizing size and one of the inputs is a zero vector and the
10132 // the zero vector has only one use, we could use a VPERM2X128 to save the
10133 // instruction bytes needed to explicitly generate the zero vector.
10135 // Blends are faster and handle all the non-lane-crossing cases.
10136 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10140 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10141 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10143 // If either input operand is a zero vector, use VPERM2X128 because its mask
10144 // allows us to replace the zero input with an implicit zero.
10145 if (!IsV1Zero && !IsV2Zero) {
10146 // Check for patterns which can be matched with a single insert of a 128-bit
10148 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10149 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10150 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10151 VT.getVectorNumElements() / 2);
10152 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10153 DAG.getIntPtrConstant(0, DL));
10154 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10155 OnlyUsesV1 ? V1 : V2,
10156 DAG.getIntPtrConstant(0, DL));
10157 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10161 // Otherwise form a 128-bit permutation. After accounting for undefs,
10162 // convert the 64-bit shuffle mask selection values into 128-bit
10163 // selection bits by dividing the indexes by 2 and shifting into positions
10164 // defined by a vperm2*128 instruction's immediate control byte.
10166 // The immediate permute control byte looks like this:
10167 // [1:0] - select 128 bits from sources for low half of destination
10169 // [3] - zero low half of destination
10170 // [5:4] - select 128 bits from sources for high half of destination
10172 // [7] - zero high half of destination
10174 int MaskLO = Mask[0];
10175 if (MaskLO == SM_SentinelUndef)
10176 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10178 int MaskHI = Mask[2];
10179 if (MaskHI == SM_SentinelUndef)
10180 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10182 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10184 // If either input is a zero vector, replace it with an undef input.
10185 // Shuffle mask values < 4 are selecting elements of V1.
10186 // Shuffle mask values >= 4 are selecting elements of V2.
10187 // Adjust each half of the permute mask by clearing the half that was
10188 // selecting the zero vector and setting the zero mask bit.
10190 V1 = DAG.getUNDEF(VT);
10192 PermMask = (PermMask & 0xf0) | 0x08;
10194 PermMask = (PermMask & 0x0f) | 0x80;
10197 V2 = DAG.getUNDEF(VT);
10199 PermMask = (PermMask & 0xf0) | 0x08;
10201 PermMask = (PermMask & 0x0f) | 0x80;
10204 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10205 DAG.getConstant(PermMask, DL, MVT::i8));
10208 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10209 /// shuffling each lane.
10211 /// This will only succeed when the result of fixing the 128-bit lanes results
10212 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10213 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10214 /// the lane crosses early and then use simpler shuffles within each lane.
10216 /// FIXME: It might be worthwhile at some point to support this without
10217 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10218 /// in x86 only floating point has interesting non-repeating shuffles, and even
10219 /// those are still *marginally* more expensive.
10220 static SDValue lowerVectorShuffleByMerging128BitLanes(
10221 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10222 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10223 assert(!isSingleInputShuffleMask(Mask) &&
10224 "This is only useful with multiple inputs.");
10226 int Size = Mask.size();
10227 int LaneSize = 128 / VT.getScalarSizeInBits();
10228 int NumLanes = Size / LaneSize;
10229 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10231 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10232 // check whether the in-128-bit lane shuffles share a repeating pattern.
10233 SmallVector<int, 4> Lanes;
10234 Lanes.resize(NumLanes, -1);
10235 SmallVector<int, 4> InLaneMask;
10236 InLaneMask.resize(LaneSize, -1);
10237 for (int i = 0; i < Size; ++i) {
10241 int j = i / LaneSize;
10243 if (Lanes[j] < 0) {
10244 // First entry we've seen for this lane.
10245 Lanes[j] = Mask[i] / LaneSize;
10246 } else if (Lanes[j] != Mask[i] / LaneSize) {
10247 // This doesn't match the lane selected previously!
10251 // Check that within each lane we have a consistent shuffle mask.
10252 int k = i % LaneSize;
10253 if (InLaneMask[k] < 0) {
10254 InLaneMask[k] = Mask[i] % LaneSize;
10255 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10256 // This doesn't fit a repeating in-lane mask.
10261 // First shuffle the lanes into place.
10262 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10263 VT.getSizeInBits() / 64);
10264 SmallVector<int, 8> LaneMask;
10265 LaneMask.resize(NumLanes * 2, -1);
10266 for (int i = 0; i < NumLanes; ++i)
10267 if (Lanes[i] >= 0) {
10268 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10269 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10272 V1 = DAG.getBitcast(LaneVT, V1);
10273 V2 = DAG.getBitcast(LaneVT, V2);
10274 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10276 // Cast it back to the type we actually want.
10277 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10279 // Now do a simple shuffle that isn't lane crossing.
10280 SmallVector<int, 8> NewMask;
10281 NewMask.resize(Size, -1);
10282 for (int i = 0; i < Size; ++i)
10284 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10285 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10286 "Must not introduce lane crosses at this point!");
10288 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10291 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10294 /// This returns true if the elements from a particular input are already in the
10295 /// slot required by the given mask and require no permutation.
10296 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10297 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10298 int Size = Mask.size();
10299 for (int i = 0; i < Size; ++i)
10300 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10306 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10307 ArrayRef<int> Mask, SDValue V1,
10308 SDValue V2, SelectionDAG &DAG) {
10310 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10311 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10312 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10313 int NumElts = VT.getVectorNumElements();
10314 bool ShufpdMask = true;
10315 bool CommutableMask = true;
10316 unsigned Immediate = 0;
10317 for (int i = 0; i < NumElts; ++i) {
10320 int Val = (i & 6) + NumElts * (i & 1);
10321 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10322 if (Mask[i] < Val || Mask[i] > Val + 1)
10323 ShufpdMask = false;
10324 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10325 CommutableMask = false;
10326 Immediate |= (Mask[i] % 2) << i;
10329 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10330 DAG.getConstant(Immediate, DL, MVT::i8));
10331 if (CommutableMask)
10332 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10333 DAG.getConstant(Immediate, DL, MVT::i8));
10337 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10339 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10340 /// isn't available.
10341 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10342 const X86Subtarget *Subtarget,
10343 SelectionDAG &DAG) {
10345 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10346 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10347 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10348 ArrayRef<int> Mask = SVOp->getMask();
10349 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10351 SmallVector<int, 4> WidenedMask;
10352 if (canWidenShuffleElements(Mask, WidenedMask))
10353 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10356 if (isSingleInputShuffleMask(Mask)) {
10357 // Check for being able to broadcast a single element.
10358 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10359 Mask, Subtarget, DAG))
10362 // Use low duplicate instructions for masks that match their pattern.
10363 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10364 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10366 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10367 // Non-half-crossing single input shuffles can be lowerid with an
10368 // interleaved permutation.
10369 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10370 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10371 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10372 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10375 // With AVX2 we have direct support for this permutation.
10376 if (Subtarget->hasAVX2())
10377 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10378 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10380 // Otherwise, fall back.
10381 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10385 // Use dedicated unpack instructions for masks that match their pattern.
10387 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10390 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10394 // Check if the blend happens to exactly fit that of SHUFPD.
10396 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10399 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10400 // shuffle. However, if we have AVX2 and either inputs are already in place,
10401 // we will be able to shuffle even across lanes the other input in a single
10402 // instruction so skip this pattern.
10403 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10404 isShuffleMaskInputInPlace(1, Mask))))
10405 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10406 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10409 // If we have AVX2 then we always want to lower with a blend because an v4 we
10410 // can fully permute the elements.
10411 if (Subtarget->hasAVX2())
10412 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10415 // Otherwise fall back on generic lowering.
10416 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10419 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10421 /// This routine is only called when we have AVX2 and thus a reasonable
10422 /// instruction set for v4i64 shuffling..
10423 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10424 const X86Subtarget *Subtarget,
10425 SelectionDAG &DAG) {
10427 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10428 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10429 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10430 ArrayRef<int> Mask = SVOp->getMask();
10431 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10432 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10434 SmallVector<int, 4> WidenedMask;
10435 if (canWidenShuffleElements(Mask, WidenedMask))
10436 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10439 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10443 // Check for being able to broadcast a single element.
10444 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10445 Mask, Subtarget, DAG))
10448 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10449 // use lower latency instructions that will operate on both 128-bit lanes.
10450 SmallVector<int, 2> RepeatedMask;
10451 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10452 if (isSingleInputShuffleMask(Mask)) {
10453 int PSHUFDMask[] = {-1, -1, -1, -1};
10454 for (int i = 0; i < 2; ++i)
10455 if (RepeatedMask[i] >= 0) {
10456 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10457 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10459 return DAG.getBitcast(
10461 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10462 DAG.getBitcast(MVT::v8i32, V1),
10463 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10467 // AVX2 provides a direct instruction for permuting a single input across
10469 if (isSingleInputShuffleMask(Mask))
10470 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10471 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10473 // Try to use shift instructions.
10474 if (SDValue Shift =
10475 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10478 // Use dedicated unpack instructions for masks that match their pattern.
10480 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10483 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10484 // shuffle. However, if we have AVX2 and either inputs are already in place,
10485 // we will be able to shuffle even across lanes the other input in a single
10486 // instruction so skip this pattern.
10487 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10488 isShuffleMaskInputInPlace(1, Mask))))
10489 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10490 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10493 // Otherwise fall back on generic blend lowering.
10494 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10498 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10500 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10501 /// isn't available.
10502 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10503 const X86Subtarget *Subtarget,
10504 SelectionDAG &DAG) {
10506 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10507 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10508 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10509 ArrayRef<int> Mask = SVOp->getMask();
10510 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10512 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10516 // Check for being able to broadcast a single element.
10517 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10518 Mask, Subtarget, DAG))
10521 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10522 // options to efficiently lower the shuffle.
10523 SmallVector<int, 4> RepeatedMask;
10524 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10525 assert(RepeatedMask.size() == 4 &&
10526 "Repeated masks must be half the mask width!");
10528 // Use even/odd duplicate instructions for masks that match their pattern.
10529 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10530 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10531 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10532 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10534 if (isSingleInputShuffleMask(Mask))
10535 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10536 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10538 // Use dedicated unpack instructions for masks that match their pattern.
10540 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10543 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10544 // have already handled any direct blends. We also need to squash the
10545 // repeated mask into a simulated v4f32 mask.
10546 for (int i = 0; i < 4; ++i)
10547 if (RepeatedMask[i] >= 8)
10548 RepeatedMask[i] -= 4;
10549 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10552 // If we have a single input shuffle with different shuffle patterns in the
10553 // two 128-bit lanes use the variable mask to VPERMILPS.
10554 if (isSingleInputShuffleMask(Mask)) {
10555 SDValue VPermMask[8];
10556 for (int i = 0; i < 8; ++i)
10557 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10558 : DAG.getConstant(Mask[i], DL, MVT::i32);
10559 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10560 return DAG.getNode(
10561 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10562 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10564 if (Subtarget->hasAVX2())
10565 return DAG.getNode(
10566 X86ISD::VPERMV, DL, MVT::v8f32,
10567 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10569 // Otherwise, fall back.
10570 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10574 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10576 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10577 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10580 // If we have AVX2 then we always want to lower with a blend because at v8 we
10581 // can fully permute the elements.
10582 if (Subtarget->hasAVX2())
10583 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10586 // Otherwise fall back on generic lowering.
10587 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10590 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10592 /// This routine is only called when we have AVX2 and thus a reasonable
10593 /// instruction set for v8i32 shuffling..
10594 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10595 const X86Subtarget *Subtarget,
10596 SelectionDAG &DAG) {
10598 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10599 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10600 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10601 ArrayRef<int> Mask = SVOp->getMask();
10602 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10603 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10605 // Whenever we can lower this as a zext, that instruction is strictly faster
10606 // than any alternative. It also allows us to fold memory operands into the
10607 // shuffle in many cases.
10608 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10609 Mask, Subtarget, DAG))
10612 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10616 // Check for being able to broadcast a single element.
10617 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10618 Mask, Subtarget, DAG))
10621 // If the shuffle mask is repeated in each 128-bit lane we can use more
10622 // efficient instructions that mirror the shuffles across the two 128-bit
10624 SmallVector<int, 4> RepeatedMask;
10625 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10626 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10627 if (isSingleInputShuffleMask(Mask))
10628 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10629 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10631 // Use dedicated unpack instructions for masks that match their pattern.
10633 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10637 // Try to use shift instructions.
10638 if (SDValue Shift =
10639 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10642 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10643 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10646 // If the shuffle patterns aren't repeated but it is a single input, directly
10647 // generate a cross-lane VPERMD instruction.
10648 if (isSingleInputShuffleMask(Mask)) {
10649 SDValue VPermMask[8];
10650 for (int i = 0; i < 8; ++i)
10651 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10652 : DAG.getConstant(Mask[i], DL, MVT::i32);
10653 return DAG.getNode(
10654 X86ISD::VPERMV, DL, MVT::v8i32,
10655 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10658 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10660 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10661 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10664 // Otherwise fall back on generic blend lowering.
10665 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10669 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10671 /// This routine is only called when we have AVX2 and thus a reasonable
10672 /// instruction set for v16i16 shuffling..
10673 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10674 const X86Subtarget *Subtarget,
10675 SelectionDAG &DAG) {
10677 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10678 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10679 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10680 ArrayRef<int> Mask = SVOp->getMask();
10681 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10682 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10684 // Whenever we can lower this as a zext, that instruction is strictly faster
10685 // than any alternative. It also allows us to fold memory operands into the
10686 // shuffle in many cases.
10687 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10688 Mask, Subtarget, DAG))
10691 // Check for being able to broadcast a single element.
10692 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10693 Mask, Subtarget, DAG))
10696 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10700 // Use dedicated unpack instructions for masks that match their pattern.
10702 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10705 // Try to use shift instructions.
10706 if (SDValue Shift =
10707 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10710 // Try to use byte rotation instructions.
10711 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10712 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10715 if (isSingleInputShuffleMask(Mask)) {
10716 // There are no generalized cross-lane shuffle operations available on i16
10718 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10719 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10722 SmallVector<int, 8> RepeatedMask;
10723 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10724 // As this is a single-input shuffle, the repeated mask should be
10725 // a strictly valid v8i16 mask that we can pass through to the v8i16
10726 // lowering to handle even the v16 case.
10727 return lowerV8I16GeneralSingleInputVectorShuffle(
10728 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10731 SDValue PSHUFBMask[32];
10732 for (int i = 0; i < 16; ++i) {
10733 if (Mask[i] == -1) {
10734 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10738 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10739 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10740 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10741 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10743 return DAG.getBitcast(MVT::v16i16,
10744 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10745 DAG.getBitcast(MVT::v32i8, V1),
10746 DAG.getNode(ISD::BUILD_VECTOR, DL,
10747 MVT::v32i8, PSHUFBMask)));
10750 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10752 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10753 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10756 // Otherwise fall back on generic lowering.
10757 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10760 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10762 /// This routine is only called when we have AVX2 and thus a reasonable
10763 /// instruction set for v32i8 shuffling..
10764 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10765 const X86Subtarget *Subtarget,
10766 SelectionDAG &DAG) {
10768 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10769 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10770 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10771 ArrayRef<int> Mask = SVOp->getMask();
10772 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10773 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10775 // Whenever we can lower this as a zext, that instruction is strictly faster
10776 // than any alternative. It also allows us to fold memory operands into the
10777 // shuffle in many cases.
10778 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10779 Mask, Subtarget, DAG))
10782 // Check for being able to broadcast a single element.
10783 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10784 Mask, Subtarget, DAG))
10787 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10791 // Use dedicated unpack instructions for masks that match their pattern.
10793 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10796 // Try to use shift instructions.
10797 if (SDValue Shift =
10798 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10801 // Try to use byte rotation instructions.
10802 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10803 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10806 if (isSingleInputShuffleMask(Mask)) {
10807 // There are no generalized cross-lane shuffle operations available on i8
10809 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10810 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10813 SDValue PSHUFBMask[32];
10814 for (int i = 0; i < 32; ++i)
10817 ? DAG.getUNDEF(MVT::i8)
10818 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10821 return DAG.getNode(
10822 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10823 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10826 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10828 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10829 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10832 // Otherwise fall back on generic lowering.
10833 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10836 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10838 /// This routine either breaks down the specific type of a 256-bit x86 vector
10839 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10840 /// together based on the available instructions.
10841 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10842 MVT VT, const X86Subtarget *Subtarget,
10843 SelectionDAG &DAG) {
10845 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10846 ArrayRef<int> Mask = SVOp->getMask();
10848 // If we have a single input to the zero element, insert that into V1 if we
10849 // can do so cheaply.
10850 int NumElts = VT.getVectorNumElements();
10851 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10852 return M >= NumElts;
10855 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10856 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10857 DL, VT, V1, V2, Mask, Subtarget, DAG))
10860 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10861 // can check for those subtargets here and avoid much of the subtarget
10862 // querying in the per-vector-type lowering routines. With AVX1 we have
10863 // essentially *zero* ability to manipulate a 256-bit vector with integer
10864 // types. Since we'll use floating point types there eventually, just
10865 // immediately cast everything to a float and operate entirely in that domain.
10866 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10867 int ElementBits = VT.getScalarSizeInBits();
10868 if (ElementBits < 32)
10869 // No floating point type available, decompose into 128-bit vectors.
10870 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10872 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10873 VT.getVectorNumElements());
10874 V1 = DAG.getBitcast(FpVT, V1);
10875 V2 = DAG.getBitcast(FpVT, V2);
10876 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10879 switch (VT.SimpleTy) {
10881 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10883 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10885 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10887 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10889 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10891 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10894 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10898 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10899 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10900 ArrayRef<int> Mask,
10901 SDValue V1, SDValue V2,
10902 SelectionDAG &DAG) {
10903 assert(VT.getScalarSizeInBits() == 64 &&
10904 "Unexpected element type size for 128bit shuffle.");
10906 // To handle 256 bit vector requires VLX and most probably
10907 // function lowerV2X128VectorShuffle() is better solution.
10908 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10910 SmallVector<int, 4> WidenedMask;
10911 if (!canWidenShuffleElements(Mask, WidenedMask))
10914 // Form a 128-bit permutation.
10915 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10916 // bits defined by a vshuf64x2 instruction's immediate control byte.
10917 unsigned PermMask = 0, Imm = 0;
10918 unsigned ControlBitsNum = WidenedMask.size() / 2;
10920 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10921 if (WidenedMask[i] == SM_SentinelZero)
10924 // Use first element in place of undef mask.
10925 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10926 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10929 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10930 DAG.getConstant(PermMask, DL, MVT::i8));
10933 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10934 ArrayRef<int> Mask, SDValue V1,
10935 SDValue V2, SelectionDAG &DAG) {
10937 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10939 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10940 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10942 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10943 if (isSingleInputShuffleMask(Mask))
10944 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10946 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10949 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10950 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10951 const X86Subtarget *Subtarget,
10952 SelectionDAG &DAG) {
10954 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10955 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10956 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10957 ArrayRef<int> Mask = SVOp->getMask();
10958 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10960 if (SDValue Shuf128 =
10961 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10964 if (SDValue Unpck =
10965 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10968 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10971 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10972 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10973 const X86Subtarget *Subtarget,
10974 SelectionDAG &DAG) {
10976 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10977 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10978 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10979 ArrayRef<int> Mask = SVOp->getMask();
10980 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10982 if (SDValue Unpck =
10983 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10986 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10989 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10990 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10991 const X86Subtarget *Subtarget,
10992 SelectionDAG &DAG) {
10994 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10995 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10997 ArrayRef<int> Mask = SVOp->getMask();
10998 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11000 if (SDValue Shuf128 =
11001 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
11004 if (SDValue Unpck =
11005 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
11008 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
11011 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
11012 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11013 const X86Subtarget *Subtarget,
11014 SelectionDAG &DAG) {
11016 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11017 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11019 ArrayRef<int> Mask = SVOp->getMask();
11020 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11022 if (SDValue Unpck =
11023 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11026 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11029 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11030 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11031 const X86Subtarget *Subtarget,
11032 SelectionDAG &DAG) {
11034 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11035 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11036 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11037 ArrayRef<int> Mask = SVOp->getMask();
11038 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11039 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11041 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11044 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11045 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11046 const X86Subtarget *Subtarget,
11047 SelectionDAG &DAG) {
11049 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11050 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11051 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11052 ArrayRef<int> Mask = SVOp->getMask();
11053 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11054 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11056 // FIXME: Implement direct support for this type!
11057 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11060 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11062 /// This routine either breaks down the specific type of a 512-bit x86 vector
11063 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11064 /// together based on the available instructions.
11065 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11066 MVT VT, const X86Subtarget *Subtarget,
11067 SelectionDAG &DAG) {
11069 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11070 ArrayRef<int> Mask = SVOp->getMask();
11071 assert(Subtarget->hasAVX512() &&
11072 "Cannot lower 512-bit vectors w/ basic ISA!");
11074 // Check for being able to broadcast a single element.
11075 if (SDValue Broadcast =
11076 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11079 // Dispatch to each element type for lowering. If we don't have supprot for
11080 // specific element type shuffles at 512 bits, immediately split them and
11081 // lower them. Each lowering routine of a given type is allowed to assume that
11082 // the requisite ISA extensions for that element type are available.
11083 switch (VT.SimpleTy) {
11085 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11087 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11089 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11091 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11093 if (Subtarget->hasBWI())
11094 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11097 if (Subtarget->hasBWI())
11098 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11102 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11105 // Otherwise fall back on splitting.
11106 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11109 // Lower vXi1 vector shuffles.
11110 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11111 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11112 // vector, shuffle and then truncate it back.
11113 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11114 MVT VT, const X86Subtarget *Subtarget,
11115 SelectionDAG &DAG) {
11117 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11118 ArrayRef<int> Mask = SVOp->getMask();
11119 assert(Subtarget->hasAVX512() &&
11120 "Cannot lower 512-bit vectors w/o basic ISA!");
11122 switch (VT.SimpleTy) {
11124 llvm_unreachable("Expected a vector of i1 elements");
11126 ExtVT = MVT::v2i64;
11129 ExtVT = MVT::v4i32;
11132 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11135 ExtVT = MVT::v16i32;
11138 ExtVT = MVT::v32i16;
11141 ExtVT = MVT::v64i8;
11145 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11146 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11147 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11148 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11150 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11153 V2 = DAG.getUNDEF(ExtVT);
11154 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11155 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11156 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11157 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11159 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11160 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11161 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11163 /// \brief Top-level lowering for x86 vector shuffles.
11165 /// This handles decomposition, canonicalization, and lowering of all x86
11166 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11167 /// above in helper routines. The canonicalization attempts to widen shuffles
11168 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11169 /// s.t. only one of the two inputs needs to be tested, etc.
11170 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11171 SelectionDAG &DAG) {
11172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11173 ArrayRef<int> Mask = SVOp->getMask();
11174 SDValue V1 = Op.getOperand(0);
11175 SDValue V2 = Op.getOperand(1);
11176 MVT VT = Op.getSimpleValueType();
11177 int NumElements = VT.getVectorNumElements();
11179 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11181 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11182 "Can't lower MMX shuffles");
11184 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11185 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11186 if (V1IsUndef && V2IsUndef)
11187 return DAG.getUNDEF(VT);
11189 // When we create a shuffle node we put the UNDEF node to second operand,
11190 // but in some cases the first operand may be transformed to UNDEF.
11191 // In this case we should just commute the node.
11193 return DAG.getCommutedVectorShuffle(*SVOp);
11195 // Check for non-undef masks pointing at an undef vector and make the masks
11196 // undef as well. This makes it easier to match the shuffle based solely on
11200 if (M >= NumElements) {
11201 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11202 for (int &M : NewMask)
11203 if (M >= NumElements)
11205 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11208 // We actually see shuffles that are entirely re-arrangements of a set of
11209 // zero inputs. This mostly happens while decomposing complex shuffles into
11210 // simple ones. Directly lower these as a buildvector of zeros.
11211 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11212 if (Zeroable.all())
11213 return getZeroVector(VT, Subtarget, DAG, dl);
11215 // Try to collapse shuffles into using a vector type with fewer elements but
11216 // wider element types. We cap this to not form integers or floating point
11217 // elements wider than 64 bits, but it might be interesting to form i128
11218 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11219 SmallVector<int, 16> WidenedMask;
11220 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11221 canWidenShuffleElements(Mask, WidenedMask)) {
11222 MVT NewEltVT = VT.isFloatingPoint()
11223 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11224 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11225 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11226 // Make sure that the new vector type is legal. For example, v2f64 isn't
11228 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11229 V1 = DAG.getBitcast(NewVT, V1);
11230 V2 = DAG.getBitcast(NewVT, V2);
11231 return DAG.getBitcast(
11232 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11236 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11237 for (int M : SVOp->getMask())
11239 ++NumUndefElements;
11240 else if (M < NumElements)
11245 // Commute the shuffle as needed such that more elements come from V1 than
11246 // V2. This allows us to match the shuffle pattern strictly on how many
11247 // elements come from V1 without handling the symmetric cases.
11248 if (NumV2Elements > NumV1Elements)
11249 return DAG.getCommutedVectorShuffle(*SVOp);
11251 // When the number of V1 and V2 elements are the same, try to minimize the
11252 // number of uses of V2 in the low half of the vector. When that is tied,
11253 // ensure that the sum of indices for V1 is equal to or lower than the sum
11254 // indices for V2. When those are equal, try to ensure that the number of odd
11255 // indices for V1 is lower than the number of odd indices for V2.
11256 if (NumV1Elements == NumV2Elements) {
11257 int LowV1Elements = 0, LowV2Elements = 0;
11258 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11259 if (M >= NumElements)
11263 if (LowV2Elements > LowV1Elements) {
11264 return DAG.getCommutedVectorShuffle(*SVOp);
11265 } else if (LowV2Elements == LowV1Elements) {
11266 int SumV1Indices = 0, SumV2Indices = 0;
11267 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11268 if (SVOp->getMask()[i] >= NumElements)
11270 else if (SVOp->getMask()[i] >= 0)
11272 if (SumV2Indices < SumV1Indices) {
11273 return DAG.getCommutedVectorShuffle(*SVOp);
11274 } else if (SumV2Indices == SumV1Indices) {
11275 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11276 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11277 if (SVOp->getMask()[i] >= NumElements)
11278 NumV2OddIndices += i % 2;
11279 else if (SVOp->getMask()[i] >= 0)
11280 NumV1OddIndices += i % 2;
11281 if (NumV2OddIndices < NumV1OddIndices)
11282 return DAG.getCommutedVectorShuffle(*SVOp);
11287 // For each vector width, delegate to a specialized lowering routine.
11288 if (VT.is128BitVector())
11289 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11291 if (VT.is256BitVector())
11292 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11294 if (VT.is512BitVector())
11295 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11298 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11299 llvm_unreachable("Unimplemented!");
11302 // This function assumes its argument is a BUILD_VECTOR of constants or
11303 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11305 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11306 unsigned &MaskValue) {
11308 unsigned NumElems = BuildVector->getNumOperands();
11310 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11311 // We don't handle the >2 lanes case right now.
11312 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11316 unsigned NumElemsInLane = NumElems / NumLanes;
11318 // Blend for v16i16 should be symmetric for the both lanes.
11319 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11320 SDValue EltCond = BuildVector->getOperand(i);
11321 SDValue SndLaneEltCond =
11322 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11324 int Lane1Cond = -1, Lane2Cond = -1;
11325 if (isa<ConstantSDNode>(EltCond))
11326 Lane1Cond = !isNullConstant(EltCond);
11327 if (isa<ConstantSDNode>(SndLaneEltCond))
11328 Lane2Cond = !isNullConstant(SndLaneEltCond);
11330 unsigned LaneMask = 0;
11331 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11332 // Lane1Cond != 0, means we want the first argument.
11333 // Lane1Cond == 0, means we want the second argument.
11334 // The encoding of this argument is 0 for the first argument, 1
11335 // for the second. Therefore, invert the condition.
11336 LaneMask = !Lane1Cond << i;
11337 else if (Lane1Cond < 0)
11338 LaneMask = !Lane2Cond << i;
11342 MaskValue |= LaneMask;
11344 MaskValue |= LaneMask << NumElemsInLane;
11349 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11350 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11351 const X86Subtarget *Subtarget,
11352 SelectionDAG &DAG) {
11353 SDValue Cond = Op.getOperand(0);
11354 SDValue LHS = Op.getOperand(1);
11355 SDValue RHS = Op.getOperand(2);
11357 MVT VT = Op.getSimpleValueType();
11359 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11361 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11363 // Only non-legal VSELECTs reach this lowering, convert those into generic
11364 // shuffles and re-use the shuffle lowering path for blends.
11365 SmallVector<int, 32> Mask;
11366 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11367 SDValue CondElt = CondBV->getOperand(i);
11369 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11372 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11375 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11376 // A vselect where all conditions and data are constants can be optimized into
11377 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11378 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11379 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11380 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11383 // Try to lower this to a blend-style vector shuffle. This can handle all
11384 // constant condition cases.
11385 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11388 // Variable blends are only legal from SSE4.1 onward.
11389 if (!Subtarget->hasSSE41())
11392 // Only some types will be legal on some subtargets. If we can emit a legal
11393 // VSELECT-matching blend, return Op, and but if we need to expand, return
11395 switch (Op.getSimpleValueType().SimpleTy) {
11397 // Most of the vector types have blends past SSE4.1.
11401 // The byte blends for AVX vectors were introduced only in AVX2.
11402 if (Subtarget->hasAVX2())
11409 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11410 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11413 // FIXME: We should custom lower this by fixing the condition and using i8
11419 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11420 MVT VT = Op.getSimpleValueType();
11423 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11426 if (VT.getSizeInBits() == 8) {
11427 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11428 Op.getOperand(0), Op.getOperand(1));
11429 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11430 DAG.getValueType(VT));
11431 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11434 if (VT.getSizeInBits() == 16) {
11435 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11436 if (isNullConstant(Op.getOperand(1)))
11437 return DAG.getNode(
11438 ISD::TRUNCATE, dl, MVT::i16,
11439 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11440 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11441 Op.getOperand(1)));
11442 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11443 Op.getOperand(0), Op.getOperand(1));
11444 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11445 DAG.getValueType(VT));
11446 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11449 if (VT == MVT::f32) {
11450 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11451 // the result back to FR32 register. It's only worth matching if the
11452 // result has a single use which is a store or a bitcast to i32. And in
11453 // the case of a store, it's not worth it if the index is a constant 0,
11454 // because a MOVSSmr can be used instead, which is smaller and faster.
11455 if (!Op.hasOneUse())
11457 SDNode *User = *Op.getNode()->use_begin();
11458 if ((User->getOpcode() != ISD::STORE ||
11459 isNullConstant(Op.getOperand(1))) &&
11460 (User->getOpcode() != ISD::BITCAST ||
11461 User->getValueType(0) != MVT::i32))
11463 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11464 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11466 return DAG.getBitcast(MVT::f32, Extract);
11469 if (VT == MVT::i32 || VT == MVT::i64) {
11470 // ExtractPS/pextrq works with constant index.
11471 if (isa<ConstantSDNode>(Op.getOperand(1)))
11477 /// Extract one bit from mask vector, like v16i1 or v8i1.
11478 /// AVX-512 feature.
11480 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11481 SDValue Vec = Op.getOperand(0);
11483 MVT VecVT = Vec.getSimpleValueType();
11484 SDValue Idx = Op.getOperand(1);
11485 MVT EltVT = Op.getSimpleValueType();
11487 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11488 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11489 "Unexpected vector type in ExtractBitFromMaskVector");
11491 // variable index can't be handled in mask registers,
11492 // extend vector to VR512
11493 if (!isa<ConstantSDNode>(Idx)) {
11494 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11495 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11496 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11497 ExtVT.getVectorElementType(), Ext, Idx);
11498 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11501 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11502 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11503 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11504 rc = getRegClassFor(MVT::v16i1);
11505 unsigned MaxSift = rc->getSize()*8 - 1;
11506 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11507 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11508 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11509 DAG.getConstant(MaxSift, dl, MVT::i8));
11510 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11511 DAG.getIntPtrConstant(0, dl));
11515 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11516 SelectionDAG &DAG) const {
11518 SDValue Vec = Op.getOperand(0);
11519 MVT VecVT = Vec.getSimpleValueType();
11520 SDValue Idx = Op.getOperand(1);
11522 if (Op.getSimpleValueType() == MVT::i1)
11523 return ExtractBitFromMaskVector(Op, DAG);
11525 if (!isa<ConstantSDNode>(Idx)) {
11526 if (VecVT.is512BitVector() ||
11527 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11528 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11531 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11532 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11533 MaskEltVT.getSizeInBits());
11535 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11536 auto PtrVT = getPointerTy(DAG.getDataLayout());
11537 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11538 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11539 DAG.getConstant(0, dl, PtrVT));
11540 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11541 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11542 DAG.getConstant(0, dl, PtrVT));
11547 // If this is a 256-bit vector result, first extract the 128-bit vector and
11548 // then extract the element from the 128-bit vector.
11549 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11551 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11552 // Get the 128-bit vector.
11553 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11554 MVT EltVT = VecVT.getVectorElementType();
11556 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11557 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11559 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11560 // this can be done with a mask.
11561 IdxVal &= ElemsPerChunk - 1;
11562 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11563 DAG.getConstant(IdxVal, dl, MVT::i32));
11566 assert(VecVT.is128BitVector() && "Unexpected vector length");
11568 if (Subtarget->hasSSE41())
11569 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11572 MVT VT = Op.getSimpleValueType();
11573 // TODO: handle v16i8.
11574 if (VT.getSizeInBits() == 16) {
11575 SDValue Vec = Op.getOperand(0);
11576 if (isNullConstant(Op.getOperand(1)))
11577 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11578 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11579 DAG.getBitcast(MVT::v4i32, Vec),
11580 Op.getOperand(1)));
11581 // Transform it so it match pextrw which produces a 32-bit result.
11582 MVT EltVT = MVT::i32;
11583 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11584 Op.getOperand(0), Op.getOperand(1));
11585 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11586 DAG.getValueType(VT));
11587 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11590 if (VT.getSizeInBits() == 32) {
11591 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11595 // SHUFPS the element to the lowest double word, then movss.
11596 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11597 MVT VVT = Op.getOperand(0).getSimpleValueType();
11598 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11599 DAG.getUNDEF(VVT), Mask);
11600 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11601 DAG.getIntPtrConstant(0, dl));
11604 if (VT.getSizeInBits() == 64) {
11605 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11606 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11607 // to match extract_elt for f64.
11608 if (isNullConstant(Op.getOperand(1)))
11611 // UNPCKHPD the element to the lowest double word, then movsd.
11612 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11613 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11614 int Mask[2] = { 1, -1 };
11615 MVT VVT = Op.getOperand(0).getSimpleValueType();
11616 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11617 DAG.getUNDEF(VVT), Mask);
11618 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11619 DAG.getIntPtrConstant(0, dl));
11625 /// Insert one bit to mask vector, like v16i1 or v8i1.
11626 /// AVX-512 feature.
11628 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11630 SDValue Vec = Op.getOperand(0);
11631 SDValue Elt = Op.getOperand(1);
11632 SDValue Idx = Op.getOperand(2);
11633 MVT VecVT = Vec.getSimpleValueType();
11635 if (!isa<ConstantSDNode>(Idx)) {
11636 // Non constant index. Extend source and destination,
11637 // insert element and then truncate the result.
11638 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11639 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11640 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11641 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11642 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11643 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11646 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11647 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11649 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11650 DAG.getConstant(IdxVal, dl, MVT::i8));
11651 if (Vec.getOpcode() == ISD::UNDEF)
11653 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11656 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11657 SelectionDAG &DAG) const {
11658 MVT VT = Op.getSimpleValueType();
11659 MVT EltVT = VT.getVectorElementType();
11661 if (EltVT == MVT::i1)
11662 return InsertBitToMaskVector(Op, DAG);
11665 SDValue N0 = Op.getOperand(0);
11666 SDValue N1 = Op.getOperand(1);
11667 SDValue N2 = Op.getOperand(2);
11668 if (!isa<ConstantSDNode>(N2))
11670 auto *N2C = cast<ConstantSDNode>(N2);
11671 unsigned IdxVal = N2C->getZExtValue();
11673 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11674 // into that, and then insert the subvector back into the result.
11675 if (VT.is256BitVector() || VT.is512BitVector()) {
11676 // With a 256-bit vector, we can insert into the zero element efficiently
11677 // using a blend if we have AVX or AVX2 and the right data type.
11678 if (VT.is256BitVector() && IdxVal == 0) {
11679 // TODO: It is worthwhile to cast integer to floating point and back
11680 // and incur a domain crossing penalty if that's what we'll end up
11681 // doing anyway after extracting to a 128-bit vector.
11682 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11683 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11684 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11685 N2 = DAG.getIntPtrConstant(1, dl);
11686 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11690 // Get the desired 128-bit vector chunk.
11691 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11693 // Insert the element into the desired chunk.
11694 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11695 assert(isPowerOf2_32(NumEltsIn128));
11696 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11697 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11699 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11700 DAG.getConstant(IdxIn128, dl, MVT::i32));
11702 // Insert the changed part back into the bigger vector
11703 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11705 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11707 if (Subtarget->hasSSE41()) {
11708 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11710 if (VT == MVT::v8i16) {
11711 Opc = X86ISD::PINSRW;
11713 assert(VT == MVT::v16i8);
11714 Opc = X86ISD::PINSRB;
11717 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11719 if (N1.getValueType() != MVT::i32)
11720 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11721 if (N2.getValueType() != MVT::i32)
11722 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11723 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11726 if (EltVT == MVT::f32) {
11727 // Bits [7:6] of the constant are the source select. This will always be
11728 // zero here. The DAG Combiner may combine an extract_elt index into
11729 // these bits. For example (insert (extract, 3), 2) could be matched by
11730 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11731 // Bits [5:4] of the constant are the destination select. This is the
11732 // value of the incoming immediate.
11733 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11734 // combine either bitwise AND or insert of float 0.0 to set these bits.
11736 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11737 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11738 // If this is an insertion of 32-bits into the low 32-bits of
11739 // a vector, we prefer to generate a blend with immediate rather
11740 // than an insertps. Blends are simpler operations in hardware and so
11741 // will always have equal or better performance than insertps.
11742 // But if optimizing for size and there's a load folding opportunity,
11743 // generate insertps because blendps does not have a 32-bit memory
11745 N2 = DAG.getIntPtrConstant(1, dl);
11746 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11747 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11749 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11750 // Create this as a scalar to vector..
11751 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11752 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11755 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11756 // PINSR* works with constant index.
11761 if (EltVT == MVT::i8)
11764 if (EltVT.getSizeInBits() == 16) {
11765 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11766 // as its second argument.
11767 if (N1.getValueType() != MVT::i32)
11768 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11769 if (N2.getValueType() != MVT::i32)
11770 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11771 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11776 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11778 MVT OpVT = Op.getSimpleValueType();
11780 // If this is a 256-bit vector result, first insert into a 128-bit
11781 // vector and then insert into the 256-bit vector.
11782 if (!OpVT.is128BitVector()) {
11783 // Insert into a 128-bit vector.
11784 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11785 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11786 OpVT.getVectorNumElements() / SizeFactor);
11788 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11790 // Insert the 128-bit vector.
11791 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11794 if (OpVT == MVT::v1i64 &&
11795 Op.getOperand(0).getValueType() == MVT::i64)
11796 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11798 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11799 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11800 return DAG.getBitcast(
11801 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11804 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11805 // a simple subregister reference or explicit instructions to grab
11806 // upper bits of a vector.
11807 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11808 SelectionDAG &DAG) {
11810 SDValue In = Op.getOperand(0);
11811 SDValue Idx = Op.getOperand(1);
11812 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11813 MVT ResVT = Op.getSimpleValueType();
11814 MVT InVT = In.getSimpleValueType();
11816 if (Subtarget->hasFp256()) {
11817 if (ResVT.is128BitVector() &&
11818 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11819 isa<ConstantSDNode>(Idx)) {
11820 return Extract128BitVector(In, IdxVal, DAG, dl);
11822 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11823 isa<ConstantSDNode>(Idx)) {
11824 return Extract256BitVector(In, IdxVal, DAG, dl);
11830 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11831 // simple superregister reference or explicit instructions to insert
11832 // the upper bits of a vector.
11833 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11834 SelectionDAG &DAG) {
11835 if (!Subtarget->hasAVX())
11839 SDValue Vec = Op.getOperand(0);
11840 SDValue SubVec = Op.getOperand(1);
11841 SDValue Idx = Op.getOperand(2);
11843 if (!isa<ConstantSDNode>(Idx))
11846 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11847 MVT OpVT = Op.getSimpleValueType();
11848 MVT SubVecVT = SubVec.getSimpleValueType();
11850 // Fold two 16-byte subvector loads into one 32-byte load:
11851 // (insert_subvector (insert_subvector undef, (load addr), 0),
11852 // (load addr + 16), Elts/2)
11854 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11855 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11856 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11857 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11858 if (Idx2 && Idx2->getZExtValue() == 0) {
11859 SDValue SubVec2 = Vec.getOperand(1);
11860 // If needed, look through a bitcast to get to the load.
11861 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11862 SubVec2 = SubVec2.getOperand(0);
11864 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11866 unsigned Alignment = FirstLd->getAlignment();
11867 unsigned AS = FirstLd->getAddressSpace();
11868 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11869 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11870 OpVT, AS, Alignment, &Fast) && Fast) {
11871 SDValue Ops[] = { SubVec2, SubVec };
11872 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11879 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11880 SubVecVT.is128BitVector())
11881 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11883 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11884 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11886 if (OpVT.getVectorElementType() == MVT::i1)
11887 return Insert1BitVector(Op, DAG);
11892 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11893 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11894 // one of the above mentioned nodes. It has to be wrapped because otherwise
11895 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11896 // be used to form addressing mode. These wrapped nodes will be selected
11899 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11900 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11902 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11903 // global base reg.
11904 unsigned char OpFlag = 0;
11905 unsigned WrapperKind = X86ISD::Wrapper;
11906 CodeModel::Model M = DAG.getTarget().getCodeModel();
11908 if (Subtarget->isPICStyleRIPRel() &&
11909 (M == CodeModel::Small || M == CodeModel::Kernel))
11910 WrapperKind = X86ISD::WrapperRIP;
11911 else if (Subtarget->isPICStyleGOT())
11912 OpFlag = X86II::MO_GOTOFF;
11913 else if (Subtarget->isPICStyleStubPIC())
11914 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11916 auto PtrVT = getPointerTy(DAG.getDataLayout());
11917 SDValue Result = DAG.getTargetConstantPool(
11918 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11920 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11921 // With PIC, the address is actually $g + Offset.
11924 DAG.getNode(ISD::ADD, DL, PtrVT,
11925 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11931 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11932 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11934 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11935 // global base reg.
11936 unsigned char OpFlag = 0;
11937 unsigned WrapperKind = X86ISD::Wrapper;
11938 CodeModel::Model M = DAG.getTarget().getCodeModel();
11940 if (Subtarget->isPICStyleRIPRel() &&
11941 (M == CodeModel::Small || M == CodeModel::Kernel))
11942 WrapperKind = X86ISD::WrapperRIP;
11943 else if (Subtarget->isPICStyleGOT())
11944 OpFlag = X86II::MO_GOTOFF;
11945 else if (Subtarget->isPICStyleStubPIC())
11946 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11948 auto PtrVT = getPointerTy(DAG.getDataLayout());
11949 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11951 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11953 // With PIC, the address is actually $g + Offset.
11956 DAG.getNode(ISD::ADD, DL, PtrVT,
11957 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11963 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11964 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11966 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11967 // global base reg.
11968 unsigned char OpFlag = 0;
11969 unsigned WrapperKind = X86ISD::Wrapper;
11970 CodeModel::Model M = DAG.getTarget().getCodeModel();
11972 if (Subtarget->isPICStyleRIPRel() &&
11973 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11974 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11975 OpFlag = X86II::MO_GOTPCREL;
11976 WrapperKind = X86ISD::WrapperRIP;
11977 } else if (Subtarget->isPICStyleGOT()) {
11978 OpFlag = X86II::MO_GOT;
11979 } else if (Subtarget->isPICStyleStubPIC()) {
11980 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11981 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11982 OpFlag = X86II::MO_DARWIN_NONLAZY;
11985 auto PtrVT = getPointerTy(DAG.getDataLayout());
11986 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11989 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11991 // With PIC, the address is actually $g + Offset.
11992 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11993 !Subtarget->is64Bit()) {
11995 DAG.getNode(ISD::ADD, DL, PtrVT,
11996 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11999 // For symbols that require a load from a stub to get the address, emit the
12001 if (isGlobalStubReference(OpFlag))
12002 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
12003 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12004 false, false, false, 0);
12010 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12011 // Create the TargetBlockAddressAddress node.
12012 unsigned char OpFlags =
12013 Subtarget->ClassifyBlockAddressReference();
12014 CodeModel::Model M = DAG.getTarget().getCodeModel();
12015 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12016 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12018 auto PtrVT = getPointerTy(DAG.getDataLayout());
12019 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12021 if (Subtarget->isPICStyleRIPRel() &&
12022 (M == CodeModel::Small || M == CodeModel::Kernel))
12023 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12025 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12027 // With PIC, the address is actually $g + Offset.
12028 if (isGlobalRelativeToPICBase(OpFlags)) {
12029 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12030 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12037 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12038 int64_t Offset, SelectionDAG &DAG) const {
12039 // Create the TargetGlobalAddress node, folding in the constant
12040 // offset if it is legal.
12041 unsigned char OpFlags =
12042 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12043 CodeModel::Model M = DAG.getTarget().getCodeModel();
12044 auto PtrVT = getPointerTy(DAG.getDataLayout());
12046 if (OpFlags == X86II::MO_NO_FLAG &&
12047 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12048 // A direct static reference to a global.
12049 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12052 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12055 if (Subtarget->isPICStyleRIPRel() &&
12056 (M == CodeModel::Small || M == CodeModel::Kernel))
12057 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12059 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12061 // With PIC, the address is actually $g + Offset.
12062 if (isGlobalRelativeToPICBase(OpFlags)) {
12063 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12064 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12067 // For globals that require a load from a stub to get the address, emit the
12069 if (isGlobalStubReference(OpFlags))
12070 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12071 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12072 false, false, false, 0);
12074 // If there was a non-zero offset that we didn't fold, create an explicit
12075 // addition for it.
12077 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12078 DAG.getConstant(Offset, dl, PtrVT));
12084 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12085 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12086 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12087 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12091 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12092 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12093 unsigned char OperandFlags, bool LocalDynamic = false) {
12094 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12095 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12097 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12098 GA->getValueType(0),
12102 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12106 SDValue Ops[] = { Chain, TGA, *InFlag };
12107 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12109 SDValue Ops[] = { Chain, TGA };
12110 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12113 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12114 MFI->setAdjustsStack(true);
12115 MFI->setHasCalls(true);
12117 SDValue Flag = Chain.getValue(1);
12118 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12121 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12123 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12126 SDLoc dl(GA); // ? function entry point might be better
12127 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12128 DAG.getNode(X86ISD::GlobalBaseReg,
12129 SDLoc(), PtrVT), InFlag);
12130 InFlag = Chain.getValue(1);
12132 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12135 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12137 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12139 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12140 X86::RAX, X86II::MO_TLSGD);
12143 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12149 // Get the start address of the TLS block for this module.
12150 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12151 .getInfo<X86MachineFunctionInfo>();
12152 MFI->incNumLocalDynamicTLSAccesses();
12156 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12157 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12160 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12161 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12162 InFlag = Chain.getValue(1);
12163 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12164 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12167 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12171 unsigned char OperandFlags = X86II::MO_DTPOFF;
12172 unsigned WrapperKind = X86ISD::Wrapper;
12173 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12174 GA->getValueType(0),
12175 GA->getOffset(), OperandFlags);
12176 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12178 // Add x@dtpoff with the base.
12179 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12182 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12183 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12184 const EVT PtrVT, TLSModel::Model model,
12185 bool is64Bit, bool isPIC) {
12188 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12189 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12190 is64Bit ? 257 : 256));
12192 SDValue ThreadPointer =
12193 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12194 MachinePointerInfo(Ptr), false, false, false, 0);
12196 unsigned char OperandFlags = 0;
12197 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12199 unsigned WrapperKind = X86ISD::Wrapper;
12200 if (model == TLSModel::LocalExec) {
12201 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12202 } else if (model == TLSModel::InitialExec) {
12204 OperandFlags = X86II::MO_GOTTPOFF;
12205 WrapperKind = X86ISD::WrapperRIP;
12207 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12210 llvm_unreachable("Unexpected model");
12213 // emit "addl x@ntpoff,%eax" (local exec)
12214 // or "addl x@indntpoff,%eax" (initial exec)
12215 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12217 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12218 GA->getOffset(), OperandFlags);
12219 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12221 if (model == TLSModel::InitialExec) {
12222 if (isPIC && !is64Bit) {
12223 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12224 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12228 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12229 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12230 false, false, false, 0);
12233 // The address of the thread local variable is the add of the thread
12234 // pointer with the offset of the variable.
12235 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12239 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12241 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12242 const GlobalValue *GV = GA->getGlobal();
12243 auto PtrVT = getPointerTy(DAG.getDataLayout());
12245 if (Subtarget->isTargetELF()) {
12246 if (DAG.getTarget().Options.EmulatedTLS)
12247 return LowerToTLSEmulatedModel(GA, DAG);
12248 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12250 case TLSModel::GeneralDynamic:
12251 if (Subtarget->is64Bit())
12252 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12253 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12254 case TLSModel::LocalDynamic:
12255 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12256 Subtarget->is64Bit());
12257 case TLSModel::InitialExec:
12258 case TLSModel::LocalExec:
12259 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12260 DAG.getTarget().getRelocationModel() ==
12263 llvm_unreachable("Unknown TLS model.");
12266 if (Subtarget->isTargetDarwin()) {
12267 // Darwin only has one model of TLS. Lower to that.
12268 unsigned char OpFlag = 0;
12269 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12270 X86ISD::WrapperRIP : X86ISD::Wrapper;
12272 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12273 // global base reg.
12274 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12275 !Subtarget->is64Bit();
12277 OpFlag = X86II::MO_TLVP_PIC_BASE;
12279 OpFlag = X86II::MO_TLVP;
12281 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12282 GA->getValueType(0),
12283 GA->getOffset(), OpFlag);
12284 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12286 // With PIC32, the address is actually $g + Offset.
12288 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12289 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12292 // Lowering the machine isd will make sure everything is in the right
12294 SDValue Chain = DAG.getEntryNode();
12295 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12296 SDValue Args[] = { Chain, Offset };
12297 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12299 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12300 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12301 MFI->setAdjustsStack(true);
12303 // And our return value (tls address) is in the standard call return value
12305 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12306 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12309 if (Subtarget->isTargetKnownWindowsMSVC() ||
12310 Subtarget->isTargetWindowsGNU()) {
12311 // Just use the implicit TLS architecture
12312 // Need to generate someting similar to:
12313 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12315 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12316 // mov rcx, qword [rdx+rcx*8]
12317 // mov eax, .tls$:tlsvar
12318 // [rax+rcx] contains the address
12319 // Windows 64bit: gs:0x58
12320 // Windows 32bit: fs:__tls_array
12323 SDValue Chain = DAG.getEntryNode();
12325 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12326 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12327 // use its literal value of 0x2C.
12328 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12329 ? Type::getInt8PtrTy(*DAG.getContext(),
12331 : Type::getInt32PtrTy(*DAG.getContext(),
12334 SDValue TlsArray = Subtarget->is64Bit()
12335 ? DAG.getIntPtrConstant(0x58, dl)
12336 : (Subtarget->isTargetWindowsGNU()
12337 ? DAG.getIntPtrConstant(0x2C, dl)
12338 : DAG.getExternalSymbol("_tls_array", PtrVT));
12340 SDValue ThreadPointer =
12341 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12345 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12346 res = ThreadPointer;
12348 // Load the _tls_index variable
12349 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12350 if (Subtarget->is64Bit())
12351 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12352 MachinePointerInfo(), MVT::i32, false, false,
12355 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12358 auto &DL = DAG.getDataLayout();
12360 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12361 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12363 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12366 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12369 // Get the offset of start of .tls section
12370 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12371 GA->getValueType(0),
12372 GA->getOffset(), X86II::MO_SECREL);
12373 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12375 // The address of the thread local variable is the add of the thread
12376 // pointer with the offset of the variable.
12377 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12380 llvm_unreachable("TLS not implemented for this target.");
12383 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12384 /// and take a 2 x i32 value to shift plus a shift amount.
12385 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12386 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12387 MVT VT = Op.getSimpleValueType();
12388 unsigned VTBits = VT.getSizeInBits();
12390 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12391 SDValue ShOpLo = Op.getOperand(0);
12392 SDValue ShOpHi = Op.getOperand(1);
12393 SDValue ShAmt = Op.getOperand(2);
12394 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12395 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12397 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12398 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12399 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12400 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12401 : DAG.getConstant(0, dl, VT);
12403 SDValue Tmp2, Tmp3;
12404 if (Op.getOpcode() == ISD::SHL_PARTS) {
12405 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12406 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12408 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12409 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12412 // If the shift amount is larger or equal than the width of a part we can't
12413 // rely on the results of shld/shrd. Insert a test and select the appropriate
12414 // values for large shift amounts.
12415 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12416 DAG.getConstant(VTBits, dl, MVT::i8));
12417 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12418 AndNode, DAG.getConstant(0, dl, MVT::i8));
12421 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12422 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12423 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12425 if (Op.getOpcode() == ISD::SHL_PARTS) {
12426 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12427 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12429 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12430 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12433 SDValue Ops[2] = { Lo, Hi };
12434 return DAG.getMergeValues(Ops, dl);
12437 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12438 SelectionDAG &DAG) const {
12439 SDValue Src = Op.getOperand(0);
12440 MVT SrcVT = Src.getSimpleValueType();
12441 MVT VT = Op.getSimpleValueType();
12444 if (SrcVT.isVector()) {
12445 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12446 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12447 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12448 DAG.getUNDEF(SrcVT)));
12450 if (SrcVT.getVectorElementType() == MVT::i1) {
12451 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12452 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12453 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12458 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12459 "Unknown SINT_TO_FP to lower!");
12461 // These are really Legal; return the operand so the caller accepts it as
12463 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12465 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12466 Subtarget->is64Bit()) {
12470 unsigned Size = SrcVT.getSizeInBits()/8;
12471 MachineFunction &MF = DAG.getMachineFunction();
12472 auto PtrVT = getPointerTy(MF.getDataLayout());
12473 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12474 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12475 SDValue Chain = DAG.getStore(
12476 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12477 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12479 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12482 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12484 SelectionDAG &DAG) const {
12488 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12490 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12492 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12494 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12496 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12497 MachineMemOperand *MMO;
12499 int SSFI = FI->getIndex();
12500 MMO = DAG.getMachineFunction().getMachineMemOperand(
12501 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12502 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12504 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12505 StackSlot = StackSlot.getOperand(1);
12507 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12508 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12510 Tys, Ops, SrcVT, MMO);
12513 Chain = Result.getValue(1);
12514 SDValue InFlag = Result.getValue(2);
12516 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12517 // shouldn't be necessary except that RFP cannot be live across
12518 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12519 MachineFunction &MF = DAG.getMachineFunction();
12520 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12521 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12522 auto PtrVT = getPointerTy(MF.getDataLayout());
12523 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12524 Tys = DAG.getVTList(MVT::Other);
12526 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12528 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12529 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12530 MachineMemOperand::MOStore, SSFISize, SSFISize);
12532 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12533 Ops, Op.getValueType(), MMO);
12534 Result = DAG.getLoad(
12535 Op.getValueType(), DL, Chain, StackSlot,
12536 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12537 false, false, false, 0);
12543 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12544 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12545 SelectionDAG &DAG) const {
12546 // This algorithm is not obvious. Here it is what we're trying to output:
12549 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12550 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12552 haddpd %xmm0, %xmm0
12554 pshufd $0x4e, %xmm0, %xmm1
12560 LLVMContext *Context = DAG.getContext();
12562 // Build some magic constants.
12563 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12564 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12565 auto PtrVT = getPointerTy(DAG.getDataLayout());
12566 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12568 SmallVector<Constant*,2> CV1;
12570 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12571 APInt(64, 0x4330000000000000ULL))));
12573 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12574 APInt(64, 0x4530000000000000ULL))));
12575 Constant *C1 = ConstantVector::get(CV1);
12576 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12578 // Load the 64-bit value into an XMM register.
12579 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12582 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12583 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12584 false, false, false, 16);
12586 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12589 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12590 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12591 false, false, false, 16);
12592 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12593 // TODO: Are there any fast-math-flags to propagate here?
12594 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12597 if (Subtarget->hasSSE3()) {
12598 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12599 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12601 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12602 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12604 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12605 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12608 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12609 DAG.getIntPtrConstant(0, dl));
12612 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12613 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12614 SelectionDAG &DAG) const {
12616 // FP constant to bias correct the final result.
12617 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12620 // Load the 32-bit value into an XMM register.
12621 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12624 // Zero out the upper parts of the register.
12625 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12627 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12628 DAG.getBitcast(MVT::v2f64, Load),
12629 DAG.getIntPtrConstant(0, dl));
12631 // Or the load with the bias.
12632 SDValue Or = DAG.getNode(
12633 ISD::OR, dl, MVT::v2i64,
12634 DAG.getBitcast(MVT::v2i64,
12635 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12636 DAG.getBitcast(MVT::v2i64,
12637 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12639 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12640 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12642 // Subtract the bias.
12643 // TODO: Are there any fast-math-flags to propagate here?
12644 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12646 // Handle final rounding.
12647 MVT DestVT = Op.getSimpleValueType();
12649 if (DestVT.bitsLT(MVT::f64))
12650 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12651 DAG.getIntPtrConstant(0, dl));
12652 if (DestVT.bitsGT(MVT::f64))
12653 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12655 // Handle final rounding.
12659 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12660 const X86Subtarget &Subtarget) {
12661 // The algorithm is the following:
12662 // #ifdef __SSE4_1__
12663 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12664 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12665 // (uint4) 0x53000000, 0xaa);
12667 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12668 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12670 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12671 // return (float4) lo + fhi;
12673 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12674 // reassociate the two FADDs, and if we do that, the algorithm fails
12675 // spectacularly (PR24512).
12676 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12677 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12678 // there's also the MachineCombiner reassociations happening on Machine IR.
12679 if (DAG.getTarget().Options.UnsafeFPMath)
12683 SDValue V = Op->getOperand(0);
12684 MVT VecIntVT = V.getSimpleValueType();
12685 bool Is128 = VecIntVT == MVT::v4i32;
12686 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12687 // If we convert to something else than the supported type, e.g., to v4f64,
12689 if (VecFloatVT != Op->getSimpleValueType(0))
12692 unsigned NumElts = VecIntVT.getVectorNumElements();
12693 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12694 "Unsupported custom type");
12695 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12697 // In the #idef/#else code, we have in common:
12698 // - The vector of constants:
12704 // Create the splat vector for 0x4b000000.
12705 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12706 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12707 CstLow, CstLow, CstLow, CstLow};
12708 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12709 makeArrayRef(&CstLowArray[0], NumElts));
12710 // Create the splat vector for 0x53000000.
12711 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12712 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12713 CstHigh, CstHigh, CstHigh, CstHigh};
12714 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12715 makeArrayRef(&CstHighArray[0], NumElts));
12717 // Create the right shift.
12718 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12719 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12720 CstShift, CstShift, CstShift, CstShift};
12721 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12722 makeArrayRef(&CstShiftArray[0], NumElts));
12723 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12726 if (Subtarget.hasSSE41()) {
12727 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12728 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12729 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12730 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12731 // Low will be bitcasted right away, so do not bother bitcasting back to its
12733 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12734 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12735 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12736 // (uint4) 0x53000000, 0xaa);
12737 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12738 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12739 // High will be bitcasted right away, so do not bother bitcasting back to
12740 // its original type.
12741 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12742 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12744 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12745 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12746 CstMask, CstMask, CstMask);
12747 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12748 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12749 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12751 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12752 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12755 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12756 SDValue CstFAdd = DAG.getConstantFP(
12757 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12758 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12759 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12760 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12761 makeArrayRef(&CstFAddArray[0], NumElts));
12763 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12764 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12765 // TODO: Are there any fast-math-flags to propagate here?
12767 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12768 // return (float4) lo + fhi;
12769 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12770 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12773 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12774 SelectionDAG &DAG) const {
12775 SDValue N0 = Op.getOperand(0);
12776 MVT SVT = N0.getSimpleValueType();
12779 switch (SVT.SimpleTy) {
12781 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12786 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12787 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12788 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12792 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12795 assert(Subtarget->hasAVX512());
12796 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12797 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12801 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12802 SelectionDAG &DAG) const {
12803 SDValue N0 = Op.getOperand(0);
12805 auto PtrVT = getPointerTy(DAG.getDataLayout());
12807 if (Op.getSimpleValueType().isVector())
12808 return lowerUINT_TO_FP_vec(Op, DAG);
12810 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12811 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12812 // the optimization here.
12813 if (DAG.SignBitIsZero(N0))
12814 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12816 MVT SrcVT = N0.getSimpleValueType();
12817 MVT DstVT = Op.getSimpleValueType();
12819 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12820 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12821 // Conversions from unsigned i32 to f32/f64 are legal,
12822 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12826 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12827 return LowerUINT_TO_FP_i64(Op, DAG);
12828 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12829 return LowerUINT_TO_FP_i32(Op, DAG);
12830 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12833 // Make a 64-bit buffer, and use it to build an FILD.
12834 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12835 if (SrcVT == MVT::i32) {
12836 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12837 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12838 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12839 StackSlot, MachinePointerInfo(),
12841 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12842 OffsetSlot, MachinePointerInfo(),
12844 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12848 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12849 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12850 StackSlot, MachinePointerInfo(),
12852 // For i64 source, we need to add the appropriate power of 2 if the input
12853 // was negative. This is the same as the optimization in
12854 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12855 // we must be careful to do the computation in x87 extended precision, not
12856 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12857 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12858 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12859 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12860 MachineMemOperand::MOLoad, 8, 8);
12862 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12863 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12864 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12867 APInt FF(32, 0x5F800000ULL);
12869 // Check whether the sign bit is set.
12870 SDValue SignSet = DAG.getSetCC(
12871 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12872 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12874 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12875 SDValue FudgePtr = DAG.getConstantPool(
12876 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12878 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12879 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12880 SDValue Four = DAG.getIntPtrConstant(4, dl);
12881 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12883 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12885 // Load the value out, extending it from f32 to f80.
12886 // FIXME: Avoid the extend by constructing the right constant pool?
12887 SDValue Fudge = DAG.getExtLoad(
12888 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12889 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12890 false, false, false, 4);
12891 // Extend everything to 80 bits to force it to be done on x87.
12892 // TODO: Are there any fast-math-flags to propagate here?
12893 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12894 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12895 DAG.getIntPtrConstant(0, dl));
12898 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12899 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12900 // just return an <SDValue(), SDValue()> pair.
12901 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12902 // to i16, i32 or i64, and we lower it to a legal sequence.
12903 // If lowered to the final integer result we return a <result, SDValue()> pair.
12904 // Otherwise we lower it to a sequence ending with a FIST, return a
12905 // <FIST, StackSlot> pair, and the caller is responsible for loading
12906 // the final integer result from StackSlot.
12907 std::pair<SDValue,SDValue>
12908 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12909 bool IsSigned, bool IsReplace) const {
12912 EVT DstTy = Op.getValueType();
12913 EVT TheVT = Op.getOperand(0).getValueType();
12914 auto PtrVT = getPointerTy(DAG.getDataLayout());
12916 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12917 // f16 must be promoted before using the lowering in this routine.
12918 // fp128 does not use this lowering.
12919 return std::make_pair(SDValue(), SDValue());
12922 // If using FIST to compute an unsigned i64, we'll need some fixup
12923 // to handle values above the maximum signed i64. A FIST is always
12924 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12925 bool UnsignedFixup = !IsSigned &&
12926 DstTy == MVT::i64 &&
12927 (!Subtarget->is64Bit() ||
12928 !isScalarFPTypeInSSEReg(TheVT));
12930 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12931 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12932 // The low 32 bits of the fist result will have the correct uint32 result.
12933 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12937 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12938 DstTy.getSimpleVT() >= MVT::i16 &&
12939 "Unknown FP_TO_INT to lower!");
12941 // These are really Legal.
12942 if (DstTy == MVT::i32 &&
12943 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12944 return std::make_pair(SDValue(), SDValue());
12945 if (Subtarget->is64Bit() &&
12946 DstTy == MVT::i64 &&
12947 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12948 return std::make_pair(SDValue(), SDValue());
12950 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12952 MachineFunction &MF = DAG.getMachineFunction();
12953 unsigned MemSize = DstTy.getSizeInBits()/8;
12954 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12955 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12958 switch (DstTy.getSimpleVT().SimpleTy) {
12959 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12960 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12961 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12962 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12965 SDValue Chain = DAG.getEntryNode();
12966 SDValue Value = Op.getOperand(0);
12967 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12969 if (UnsignedFixup) {
12971 // Conversion to unsigned i64 is implemented with a select,
12972 // depending on whether the source value fits in the range
12973 // of a signed i64. Let Thresh be the FP equivalent of
12974 // 0x8000000000000000ULL.
12976 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12977 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12978 // Fist-to-mem64 FistSrc
12979 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12980 // to XOR'ing the high 32 bits with Adjust.
12982 // Being a power of 2, Thresh is exactly representable in all FP formats.
12983 // For X87 we'd like to use the smallest FP type for this constant, but
12984 // for DAG type consistency we have to match the FP operand type.
12986 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12987 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12988 bool LosesInfo = false;
12989 if (TheVT == MVT::f64)
12990 // The rounding mode is irrelevant as the conversion should be exact.
12991 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12993 else if (TheVT == MVT::f80)
12994 Status = Thresh.convert(APFloat::x87DoubleExtended,
12995 APFloat::rmNearestTiesToEven, &LosesInfo);
12997 assert(Status == APFloat::opOK && !LosesInfo &&
12998 "FP conversion should have been exact");
13000 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
13002 SDValue Cmp = DAG.getSetCC(DL,
13003 getSetCCResultType(DAG.getDataLayout(),
13004 *DAG.getContext(), TheVT),
13005 Value, ThreshVal, ISD::SETLT);
13006 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
13007 DAG.getConstant(0, DL, MVT::i32),
13008 DAG.getConstant(0x80000000, DL, MVT::i32));
13009 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
13010 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
13011 *DAG.getContext(), TheVT),
13012 Value, ThreshVal, ISD::SETLT);
13013 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13016 // FIXME This causes a redundant load/store if the SSE-class value is already
13017 // in memory, such as if it is on the callstack.
13018 if (isScalarFPTypeInSSEReg(TheVT)) {
13019 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13020 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13021 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13023 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13025 Chain, StackSlot, DAG.getValueType(TheVT)
13028 MachineMemOperand *MMO =
13029 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13030 MachineMemOperand::MOLoad, MemSize, MemSize);
13031 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13032 Chain = Value.getValue(1);
13033 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13034 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13037 MachineMemOperand *MMO =
13038 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13039 MachineMemOperand::MOStore, MemSize, MemSize);
13041 if (UnsignedFixup) {
13043 // Insert the FIST, load its result as two i32's,
13044 // and XOR the high i32 with Adjust.
13046 SDValue FistOps[] = { Chain, Value, StackSlot };
13047 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13048 FistOps, DstTy, MMO);
13050 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13051 MachinePointerInfo(),
13052 false, false, false, 0);
13053 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13054 DAG.getConstant(4, DL, PtrVT));
13056 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13057 MachinePointerInfo(),
13058 false, false, false, 0);
13059 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13061 if (Subtarget->is64Bit()) {
13062 // Join High32 and Low32 into a 64-bit result.
13063 // (High32 << 32) | Low32
13064 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13065 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13066 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13067 DAG.getConstant(32, DL, MVT::i8));
13068 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13069 return std::make_pair(Result, SDValue());
13072 SDValue ResultOps[] = { Low32, High32 };
13074 SDValue pair = IsReplace
13075 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13076 : DAG.getMergeValues(ResultOps, DL);
13077 return std::make_pair(pair, SDValue());
13079 // Build the FP_TO_INT*_IN_MEM
13080 SDValue Ops[] = { Chain, Value, StackSlot };
13081 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13083 return std::make_pair(FIST, StackSlot);
13087 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13088 const X86Subtarget *Subtarget) {
13089 MVT VT = Op->getSimpleValueType(0);
13090 SDValue In = Op->getOperand(0);
13091 MVT InVT = In.getSimpleValueType();
13094 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13095 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13097 // Optimize vectors in AVX mode:
13100 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13101 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13102 // Concat upper and lower parts.
13105 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13106 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13107 // Concat upper and lower parts.
13110 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13111 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13112 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13115 if (Subtarget->hasInt256())
13116 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13118 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13119 SDValue Undef = DAG.getUNDEF(InVT);
13120 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13121 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13122 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13124 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13125 VT.getVectorNumElements()/2);
13127 OpLo = DAG.getBitcast(HVT, OpLo);
13128 OpHi = DAG.getBitcast(HVT, OpHi);
13130 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13133 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13134 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13135 MVT VT = Op->getSimpleValueType(0);
13136 SDValue In = Op->getOperand(0);
13137 MVT InVT = In.getSimpleValueType();
13139 unsigned int NumElts = VT.getVectorNumElements();
13140 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13143 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13144 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13146 assert(InVT.getVectorElementType() == MVT::i1);
13147 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13149 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13151 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13153 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13154 if (VT.is512BitVector())
13156 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13159 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13160 SelectionDAG &DAG) {
13161 if (Subtarget->hasFp256())
13162 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13168 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13169 SelectionDAG &DAG) {
13171 MVT VT = Op.getSimpleValueType();
13172 SDValue In = Op.getOperand(0);
13173 MVT SVT = In.getSimpleValueType();
13175 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13176 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13178 if (Subtarget->hasFp256())
13179 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13182 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13183 VT.getVectorNumElements() != SVT.getVectorNumElements());
13187 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13189 MVT VT = Op.getSimpleValueType();
13190 SDValue In = Op.getOperand(0);
13191 MVT InVT = In.getSimpleValueType();
13193 if (VT == MVT::i1) {
13194 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13195 "Invalid scalar TRUNCATE operation");
13196 if (InVT.getSizeInBits() >= 32)
13198 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13199 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13201 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13202 "Invalid TRUNCATE operation");
13204 // move vector to mask - truncate solution for SKX
13205 if (VT.getVectorElementType() == MVT::i1) {
13206 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13207 Subtarget->hasBWI())
13208 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13209 if ((InVT.is256BitVector() || InVT.is128BitVector())
13210 && InVT.getScalarSizeInBits() <= 16 &&
13211 Subtarget->hasBWI() && Subtarget->hasVLX())
13212 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13213 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13214 Subtarget->hasDQI())
13215 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13216 if ((InVT.is256BitVector() || InVT.is128BitVector())
13217 && InVT.getScalarSizeInBits() >= 32 &&
13218 Subtarget->hasDQI() && Subtarget->hasVLX())
13219 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13222 if (VT.getVectorElementType() == MVT::i1) {
13223 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13224 unsigned NumElts = InVT.getVectorNumElements();
13225 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13226 if (InVT.getSizeInBits() < 512) {
13227 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13228 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13233 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13234 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13235 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13238 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13239 if (Subtarget->hasAVX512()) {
13240 // word to byte only under BWI
13241 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13242 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13243 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13244 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13246 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13247 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13248 if (Subtarget->hasInt256()) {
13249 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13250 In = DAG.getBitcast(MVT::v8i32, In);
13251 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13253 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13254 DAG.getIntPtrConstant(0, DL));
13257 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13258 DAG.getIntPtrConstant(0, DL));
13259 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13260 DAG.getIntPtrConstant(2, DL));
13261 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13262 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13263 static const int ShufMask[] = {0, 2, 4, 6};
13264 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13267 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13268 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13269 if (Subtarget->hasInt256()) {
13270 In = DAG.getBitcast(MVT::v32i8, In);
13272 SmallVector<SDValue,32> pshufbMask;
13273 for (unsigned i = 0; i < 2; ++i) {
13274 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13275 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13276 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13277 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13278 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13279 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13280 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13281 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13282 for (unsigned j = 0; j < 8; ++j)
13283 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13285 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13286 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13287 In = DAG.getBitcast(MVT::v4i64, In);
13289 static const int ShufMask[] = {0, 2, -1, -1};
13290 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13292 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13293 DAG.getIntPtrConstant(0, DL));
13294 return DAG.getBitcast(VT, In);
13297 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13298 DAG.getIntPtrConstant(0, DL));
13300 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13301 DAG.getIntPtrConstant(4, DL));
13303 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13304 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13306 // The PSHUFB mask:
13307 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13308 -1, -1, -1, -1, -1, -1, -1, -1};
13310 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13311 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13312 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13314 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13315 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13317 // The MOVLHPS Mask:
13318 static const int ShufMask2[] = {0, 1, 4, 5};
13319 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13320 return DAG.getBitcast(MVT::v8i16, res);
13323 // Handle truncation of V256 to V128 using shuffles.
13324 if (!VT.is128BitVector() || !InVT.is256BitVector())
13327 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13329 unsigned NumElems = VT.getVectorNumElements();
13330 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13332 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13333 // Prepare truncation shuffle mask
13334 for (unsigned i = 0; i != NumElems; ++i)
13335 MaskVec[i] = i * 2;
13336 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13337 DAG.getUNDEF(NVT), &MaskVec[0]);
13338 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13339 DAG.getIntPtrConstant(0, DL));
13342 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13343 SelectionDAG &DAG) const {
13344 assert(!Op.getSimpleValueType().isVector());
13346 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13347 /*IsSigned=*/ true, /*IsReplace=*/ false);
13348 SDValue FIST = Vals.first, StackSlot = Vals.second;
13349 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13350 if (!FIST.getNode())
13353 if (StackSlot.getNode())
13354 // Load the result.
13355 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13356 FIST, StackSlot, MachinePointerInfo(),
13357 false, false, false, 0);
13359 // The node is the result.
13363 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13364 SelectionDAG &DAG) const {
13365 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13366 /*IsSigned=*/ false, /*IsReplace=*/ false);
13367 SDValue FIST = Vals.first, StackSlot = Vals.second;
13368 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13369 if (!FIST.getNode())
13372 if (StackSlot.getNode())
13373 // Load the result.
13374 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13375 FIST, StackSlot, MachinePointerInfo(),
13376 false, false, false, 0);
13378 // The node is the result.
13382 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13384 MVT VT = Op.getSimpleValueType();
13385 SDValue In = Op.getOperand(0);
13386 MVT SVT = In.getSimpleValueType();
13388 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13390 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13391 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13392 In, DAG.getUNDEF(SVT)));
13395 /// The only differences between FABS and FNEG are the mask and the logic op.
13396 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13397 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13398 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13399 "Wrong opcode for lowering FABS or FNEG.");
13401 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13403 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13404 // into an FNABS. We'll lower the FABS after that if it is still in use.
13406 for (SDNode *User : Op->uses())
13407 if (User->getOpcode() == ISD::FNEG)
13411 MVT VT = Op.getSimpleValueType();
13413 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13414 // decide if we should generate a 16-byte constant mask when we only need 4 or
13415 // 8 bytes for the scalar case.
13421 if (VT.isVector()) {
13423 EltVT = VT.getVectorElementType();
13424 NumElts = VT.getVectorNumElements();
13426 // There are no scalar bitwise logical SSE/AVX instructions, so we
13427 // generate a 16-byte vector constant and logic op even for the scalar case.
13428 // Using a 16-byte mask allows folding the load of the mask with
13429 // the logic op, so it can save (~4 bytes) on code size.
13430 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13432 NumElts = (VT == MVT::f64) ? 2 : 4;
13435 unsigned EltBits = EltVT.getSizeInBits();
13436 LLVMContext *Context = DAG.getContext();
13437 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13439 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13440 Constant *C = ConstantInt::get(*Context, MaskElt);
13441 C = ConstantVector::getSplat(NumElts, C);
13442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13443 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13444 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13446 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13447 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13448 false, false, false, Alignment);
13450 SDValue Op0 = Op.getOperand(0);
13451 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13453 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13454 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13457 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13459 // For the scalar case extend to a 128-bit vector, perform the logic op,
13460 // and extract the scalar result back out.
13461 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13462 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13463 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13464 DAG.getIntPtrConstant(0, dl));
13467 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13468 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13469 LLVMContext *Context = DAG.getContext();
13470 SDValue Op0 = Op.getOperand(0);
13471 SDValue Op1 = Op.getOperand(1);
13473 MVT VT = Op.getSimpleValueType();
13474 MVT SrcVT = Op1.getSimpleValueType();
13476 // If second operand is smaller, extend it first.
13477 if (SrcVT.bitsLT(VT)) {
13478 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13481 // And if it is bigger, shrink it first.
13482 if (SrcVT.bitsGT(VT)) {
13483 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13487 // At this point the operands and the result should have the same
13488 // type, and that won't be f80 since that is not custom lowered.
13490 const fltSemantics &Sem =
13491 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13492 const unsigned SizeInBits = VT.getSizeInBits();
13494 SmallVector<Constant *, 4> CV(
13495 VT == MVT::f64 ? 2 : 4,
13496 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13498 // First, clear all bits but the sign bit from the second operand (sign).
13499 CV[0] = ConstantFP::get(*Context,
13500 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13501 Constant *C = ConstantVector::get(CV);
13502 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13503 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13505 // Perform all logic operations as 16-byte vectors because there are no
13506 // scalar FP logic instructions in SSE. This allows load folding of the
13507 // constants into the logic instructions.
13508 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13510 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13511 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13512 false, false, false, 16);
13513 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13514 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13516 // Next, clear the sign bit from the first operand (magnitude).
13517 // If it's a constant, we can clear it here.
13518 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13519 APFloat APF = Op0CN->getValueAPF();
13520 // If the magnitude is a positive zero, the sign bit alone is enough.
13521 if (APF.isPosZero())
13522 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13523 DAG.getIntPtrConstant(0, dl));
13525 CV[0] = ConstantFP::get(*Context, APF);
13527 CV[0] = ConstantFP::get(
13529 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13531 C = ConstantVector::get(CV);
13532 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13534 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13535 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13536 false, false, false, 16);
13537 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13538 if (!isa<ConstantFPSDNode>(Op0)) {
13539 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13540 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13542 // OR the magnitude value with the sign bit.
13543 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13544 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13545 DAG.getIntPtrConstant(0, dl));
13548 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13549 SDValue N0 = Op.getOperand(0);
13551 MVT VT = Op.getSimpleValueType();
13553 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13554 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13555 DAG.getConstant(1, dl, VT));
13556 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13559 // Check whether an OR'd tree is PTEST-able.
13560 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13561 SelectionDAG &DAG) {
13562 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13564 if (!Subtarget->hasSSE41())
13567 if (!Op->hasOneUse())
13570 SDNode *N = Op.getNode();
13573 SmallVector<SDValue, 8> Opnds;
13574 DenseMap<SDValue, unsigned> VecInMap;
13575 SmallVector<SDValue, 8> VecIns;
13576 EVT VT = MVT::Other;
13578 // Recognize a special case where a vector is casted into wide integer to
13580 Opnds.push_back(N->getOperand(0));
13581 Opnds.push_back(N->getOperand(1));
13583 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13584 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13585 // BFS traverse all OR'd operands.
13586 if (I->getOpcode() == ISD::OR) {
13587 Opnds.push_back(I->getOperand(0));
13588 Opnds.push_back(I->getOperand(1));
13589 // Re-evaluate the number of nodes to be traversed.
13590 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13594 // Quit if a non-EXTRACT_VECTOR_ELT
13595 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13598 // Quit if without a constant index.
13599 SDValue Idx = I->getOperand(1);
13600 if (!isa<ConstantSDNode>(Idx))
13603 SDValue ExtractedFromVec = I->getOperand(0);
13604 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13605 if (M == VecInMap.end()) {
13606 VT = ExtractedFromVec.getValueType();
13607 // Quit if not 128/256-bit vector.
13608 if (!VT.is128BitVector() && !VT.is256BitVector())
13610 // Quit if not the same type.
13611 if (VecInMap.begin() != VecInMap.end() &&
13612 VT != VecInMap.begin()->first.getValueType())
13614 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13615 VecIns.push_back(ExtractedFromVec);
13617 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13620 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13621 "Not extracted from 128-/256-bit vector.");
13623 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13625 for (DenseMap<SDValue, unsigned>::const_iterator
13626 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13627 // Quit if not all elements are used.
13628 if (I->second != FullMask)
13632 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13634 // Cast all vectors into TestVT for PTEST.
13635 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13636 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13638 // If more than one full vectors are evaluated, OR them first before PTEST.
13639 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13640 // Each iteration will OR 2 nodes and append the result until there is only
13641 // 1 node left, i.e. the final OR'd value of all vectors.
13642 SDValue LHS = VecIns[Slot];
13643 SDValue RHS = VecIns[Slot + 1];
13644 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13647 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13648 VecIns.back(), VecIns.back());
13651 /// \brief return true if \c Op has a use that doesn't just read flags.
13652 static bool hasNonFlagsUse(SDValue Op) {
13653 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13655 SDNode *User = *UI;
13656 unsigned UOpNo = UI.getOperandNo();
13657 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13658 // Look pass truncate.
13659 UOpNo = User->use_begin().getOperandNo();
13660 User = *User->use_begin();
13663 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13664 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13670 /// Emit nodes that will be selected as "test Op0,Op0", or something
13672 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13673 SelectionDAG &DAG) const {
13674 if (Op.getValueType() == MVT::i1) {
13675 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13676 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13677 DAG.getConstant(0, dl, MVT::i8));
13679 // CF and OF aren't always set the way we want. Determine which
13680 // of these we need.
13681 bool NeedCF = false;
13682 bool NeedOF = false;
13685 case X86::COND_A: case X86::COND_AE:
13686 case X86::COND_B: case X86::COND_BE:
13689 case X86::COND_G: case X86::COND_GE:
13690 case X86::COND_L: case X86::COND_LE:
13691 case X86::COND_O: case X86::COND_NO: {
13692 // Check if we really need to set the
13693 // Overflow flag. If NoSignedWrap is present
13694 // that is not actually needed.
13695 switch (Op->getOpcode()) {
13700 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13701 if (BinNode->Flags.hasNoSignedWrap())
13711 // See if we can use the EFLAGS value from the operand instead of
13712 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13713 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13714 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13715 // Emit a CMP with 0, which is the TEST pattern.
13716 //if (Op.getValueType() == MVT::i1)
13717 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13718 // DAG.getConstant(0, MVT::i1));
13719 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13720 DAG.getConstant(0, dl, Op.getValueType()));
13722 unsigned Opcode = 0;
13723 unsigned NumOperands = 0;
13725 // Truncate operations may prevent the merge of the SETCC instruction
13726 // and the arithmetic instruction before it. Attempt to truncate the operands
13727 // of the arithmetic instruction and use a reduced bit-width instruction.
13728 bool NeedTruncation = false;
13729 SDValue ArithOp = Op;
13730 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13731 SDValue Arith = Op->getOperand(0);
13732 // Both the trunc and the arithmetic op need to have one user each.
13733 if (Arith->hasOneUse())
13734 switch (Arith.getOpcode()) {
13741 NeedTruncation = true;
13747 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13748 // which may be the result of a CAST. We use the variable 'Op', which is the
13749 // non-casted variable when we check for possible users.
13750 switch (ArithOp.getOpcode()) {
13752 // Due to an isel shortcoming, be conservative if this add is likely to be
13753 // selected as part of a load-modify-store instruction. When the root node
13754 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13755 // uses of other nodes in the match, such as the ADD in this case. This
13756 // leads to the ADD being left around and reselected, with the result being
13757 // two adds in the output. Alas, even if none our users are stores, that
13758 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13759 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13760 // climbing the DAG back to the root, and it doesn't seem to be worth the
13762 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13763 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13764 if (UI->getOpcode() != ISD::CopyToReg &&
13765 UI->getOpcode() != ISD::SETCC &&
13766 UI->getOpcode() != ISD::STORE)
13769 if (ConstantSDNode *C =
13770 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13771 // An add of one will be selected as an INC.
13772 if (C->isOne() && !Subtarget->slowIncDec()) {
13773 Opcode = X86ISD::INC;
13778 // An add of negative one (subtract of one) will be selected as a DEC.
13779 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
13780 Opcode = X86ISD::DEC;
13786 // Otherwise use a regular EFLAGS-setting add.
13787 Opcode = X86ISD::ADD;
13792 // If we have a constant logical shift that's only used in a comparison
13793 // against zero turn it into an equivalent AND. This allows turning it into
13794 // a TEST instruction later.
13795 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13796 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13797 EVT VT = Op.getValueType();
13798 unsigned BitWidth = VT.getSizeInBits();
13799 unsigned ShAmt = Op->getConstantOperandVal(1);
13800 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13802 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13803 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13804 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13805 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13807 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13808 DAG.getConstant(Mask, dl, VT));
13809 DAG.ReplaceAllUsesWith(Op, New);
13815 // If the primary and result isn't used, don't bother using X86ISD::AND,
13816 // because a TEST instruction will be better.
13817 if (!hasNonFlagsUse(Op))
13823 // Due to the ISEL shortcoming noted above, be conservative if this op is
13824 // likely to be selected as part of a load-modify-store instruction.
13825 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13826 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13827 if (UI->getOpcode() == ISD::STORE)
13830 // Otherwise use a regular EFLAGS-setting instruction.
13831 switch (ArithOp.getOpcode()) {
13832 default: llvm_unreachable("unexpected operator!");
13833 case ISD::SUB: Opcode = X86ISD::SUB; break;
13834 case ISD::XOR: Opcode = X86ISD::XOR; break;
13835 case ISD::AND: Opcode = X86ISD::AND; break;
13837 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13838 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13839 if (EFLAGS.getNode())
13842 Opcode = X86ISD::OR;
13856 return SDValue(Op.getNode(), 1);
13862 // If we found that truncation is beneficial, perform the truncation and
13864 if (NeedTruncation) {
13865 EVT VT = Op.getValueType();
13866 SDValue WideVal = Op->getOperand(0);
13867 EVT WideVT = WideVal.getValueType();
13868 unsigned ConvertedOp = 0;
13869 // Use a target machine opcode to prevent further DAGCombine
13870 // optimizations that may separate the arithmetic operations
13871 // from the setcc node.
13872 switch (WideVal.getOpcode()) {
13874 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13875 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13876 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13877 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13878 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13882 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13883 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13884 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13885 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13886 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13892 // Emit a CMP with 0, which is the TEST pattern.
13893 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13894 DAG.getConstant(0, dl, Op.getValueType()));
13896 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13897 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13899 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13900 DAG.ReplaceAllUsesWith(Op, New);
13901 return SDValue(New.getNode(), 1);
13904 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13906 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13907 SDLoc dl, SelectionDAG &DAG) const {
13908 if (isNullConstant(Op1))
13909 return EmitTest(Op0, X86CC, dl, DAG);
13911 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
13912 "Unexpected comparison operation for MVT::i1 operands");
13914 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13915 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13916 // Do the comparison at i32 if it's smaller, besides the Atom case.
13917 // This avoids subregister aliasing issues. Keep the smaller reference
13918 // if we're optimizing for size, however, as that'll allow better folding
13919 // of memory operations.
13920 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13921 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13922 !Subtarget->isAtom()) {
13923 unsigned ExtendOp =
13924 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13925 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13926 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13928 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13929 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13930 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13932 return SDValue(Sub.getNode(), 1);
13934 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13937 /// Convert a comparison if required by the subtarget.
13938 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13939 SelectionDAG &DAG) const {
13940 // If the subtarget does not support the FUCOMI instruction, floating-point
13941 // comparisons have to be converted.
13942 if (Subtarget->hasCMov() ||
13943 Cmp.getOpcode() != X86ISD::CMP ||
13944 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13945 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13948 // The instruction selector will select an FUCOM instruction instead of
13949 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13950 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13951 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13953 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13954 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13955 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13956 DAG.getConstant(8, dl, MVT::i8));
13957 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13959 // Some 64-bit targets lack SAHF support, but they do support FCOMI.
13960 assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
13961 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13964 /// The minimum architected relative accuracy is 2^-12. We need one
13965 /// Newton-Raphson step to have a good float result (24 bits of precision).
13966 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13967 DAGCombinerInfo &DCI,
13968 unsigned &RefinementSteps,
13969 bool &UseOneConstNR) const {
13970 EVT VT = Op.getValueType();
13971 const char *RecipOp;
13973 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13974 // TODO: Add support for AVX512 (v16f32).
13975 // It is likely not profitable to do this for f64 because a double-precision
13976 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13977 // instructions: convert to single, rsqrtss, convert back to double, refine
13978 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13979 // along with FMA, this could be a throughput win.
13980 if (VT == MVT::f32 && Subtarget->hasSSE1())
13982 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13983 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13984 RecipOp = "vec-sqrtf";
13988 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13989 if (!Recips.isEnabled(RecipOp))
13992 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13993 UseOneConstNR = false;
13994 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13997 /// The minimum architected relative accuracy is 2^-12. We need one
13998 /// Newton-Raphson step to have a good float result (24 bits of precision).
13999 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14000 DAGCombinerInfo &DCI,
14001 unsigned &RefinementSteps) const {
14002 EVT VT = Op.getValueType();
14003 const char *RecipOp;
14005 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14006 // TODO: Add support for AVX512 (v16f32).
14007 // It is likely not profitable to do this for f64 because a double-precision
14008 // reciprocal estimate with refinement on x86 prior to FMA requires
14009 // 15 instructions: convert to single, rcpss, convert back to double, refine
14010 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14011 // along with FMA, this could be a throughput win.
14012 if (VT == MVT::f32 && Subtarget->hasSSE1())
14014 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14015 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14016 RecipOp = "vec-divf";
14020 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14021 if (!Recips.isEnabled(RecipOp))
14024 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14025 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14028 /// If we have at least two divisions that use the same divisor, convert to
14029 /// multplication by a reciprocal. This may need to be adjusted for a given
14030 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14031 /// This is because we still need one division to calculate the reciprocal and
14032 /// then we need two multiplies by that reciprocal as replacements for the
14033 /// original divisions.
14034 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14038 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14039 /// if it's possible.
14040 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14041 SDLoc dl, SelectionDAG &DAG) const {
14042 SDValue Op0 = And.getOperand(0);
14043 SDValue Op1 = And.getOperand(1);
14044 if (Op0.getOpcode() == ISD::TRUNCATE)
14045 Op0 = Op0.getOperand(0);
14046 if (Op1.getOpcode() == ISD::TRUNCATE)
14047 Op1 = Op1.getOperand(0);
14050 if (Op1.getOpcode() == ISD::SHL)
14051 std::swap(Op0, Op1);
14052 if (Op0.getOpcode() == ISD::SHL) {
14053 if (isOneConstant(Op0.getOperand(0))) {
14054 // If we looked past a truncate, check that it's only truncating away
14056 unsigned BitWidth = Op0.getValueSizeInBits();
14057 unsigned AndBitWidth = And.getValueSizeInBits();
14058 if (BitWidth > AndBitWidth) {
14060 DAG.computeKnownBits(Op0, Zeros, Ones);
14061 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14065 RHS = Op0.getOperand(1);
14067 } else if (Op1.getOpcode() == ISD::Constant) {
14068 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14069 uint64_t AndRHSVal = AndRHS->getZExtValue();
14070 SDValue AndLHS = Op0;
14072 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14073 LHS = AndLHS.getOperand(0);
14074 RHS = AndLHS.getOperand(1);
14077 // Use BT if the immediate can't be encoded in a TEST instruction.
14078 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14080 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14084 if (LHS.getNode()) {
14085 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14086 // instruction. Since the shift amount is in-range-or-undefined, we know
14087 // that doing a bittest on the i32 value is ok. We extend to i32 because
14088 // the encoding for the i16 version is larger than the i32 version.
14089 // Also promote i16 to i32 for performance / code size reason.
14090 if (LHS.getValueType() == MVT::i8 ||
14091 LHS.getValueType() == MVT::i16)
14092 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14094 // If the operand types disagree, extend the shift amount to match. Since
14095 // BT ignores high bits (like shifts) we can use anyextend.
14096 if (LHS.getValueType() != RHS.getValueType())
14097 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14099 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14100 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14101 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14102 DAG.getConstant(Cond, dl, MVT::i8), BT);
14108 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14110 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14115 // SSE Condition code mapping:
14124 switch (SetCCOpcode) {
14125 default: llvm_unreachable("Unexpected SETCC condition");
14127 case ISD::SETEQ: SSECC = 0; break;
14129 case ISD::SETGT: Swap = true; // Fallthrough
14131 case ISD::SETOLT: SSECC = 1; break;
14133 case ISD::SETGE: Swap = true; // Fallthrough
14135 case ISD::SETOLE: SSECC = 2; break;
14136 case ISD::SETUO: SSECC = 3; break;
14138 case ISD::SETNE: SSECC = 4; break;
14139 case ISD::SETULE: Swap = true; // Fallthrough
14140 case ISD::SETUGE: SSECC = 5; break;
14141 case ISD::SETULT: Swap = true; // Fallthrough
14142 case ISD::SETUGT: SSECC = 6; break;
14143 case ISD::SETO: SSECC = 7; break;
14145 case ISD::SETONE: SSECC = 8; break;
14148 std::swap(Op0, Op1);
14153 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14154 // ones, and then concatenate the result back.
14155 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14156 MVT VT = Op.getSimpleValueType();
14158 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14159 "Unsupported value type for operation");
14161 unsigned NumElems = VT.getVectorNumElements();
14163 SDValue CC = Op.getOperand(2);
14165 // Extract the LHS vectors
14166 SDValue LHS = Op.getOperand(0);
14167 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14168 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14170 // Extract the RHS vectors
14171 SDValue RHS = Op.getOperand(1);
14172 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14173 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14175 // Issue the operation on the smaller types and concatenate the result back
14176 MVT EltVT = VT.getVectorElementType();
14177 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14178 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14179 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14180 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14183 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14184 SDValue Op0 = Op.getOperand(0);
14185 SDValue Op1 = Op.getOperand(1);
14186 SDValue CC = Op.getOperand(2);
14187 MVT VT = Op.getSimpleValueType();
14190 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14191 "Unexpected type for boolean compare operation");
14192 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14193 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14194 DAG.getConstant(-1, dl, VT));
14195 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14196 DAG.getConstant(-1, dl, VT));
14197 switch (SetCCOpcode) {
14198 default: llvm_unreachable("Unexpected SETCC condition");
14200 // (x == y) -> ~(x ^ y)
14201 return DAG.getNode(ISD::XOR, dl, VT,
14202 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14203 DAG.getConstant(-1, dl, VT));
14205 // (x != y) -> (x ^ y)
14206 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14209 // (x > y) -> (x & ~y)
14210 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14213 // (x < y) -> (~x & y)
14214 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14217 // (x <= y) -> (~x | y)
14218 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14221 // (x >=y) -> (x | ~y)
14222 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14226 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14227 const X86Subtarget *Subtarget) {
14228 SDValue Op0 = Op.getOperand(0);
14229 SDValue Op1 = Op.getOperand(1);
14230 SDValue CC = Op.getOperand(2);
14231 MVT VT = Op.getSimpleValueType();
14234 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14235 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14236 "Cannot set masked compare for this operation");
14238 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14240 bool Unsigned = false;
14243 switch (SetCCOpcode) {
14244 default: llvm_unreachable("Unexpected SETCC condition");
14245 case ISD::SETNE: SSECC = 4; break;
14246 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14247 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14248 case ISD::SETLT: Swap = true; //fall-through
14249 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14250 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14251 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14252 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14253 case ISD::SETULE: Unsigned = true; //fall-through
14254 case ISD::SETLE: SSECC = 2; break;
14258 std::swap(Op0, Op1);
14260 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14261 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14262 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14263 DAG.getConstant(SSECC, dl, MVT::i8));
14266 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14267 /// operand \p Op1. If non-trivial (for example because it's not constant)
14268 /// return an empty value.
14269 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14271 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14275 MVT VT = Op1.getSimpleValueType();
14276 MVT EVT = VT.getVectorElementType();
14277 unsigned n = VT.getVectorNumElements();
14278 SmallVector<SDValue, 8> ULTOp1;
14280 for (unsigned i = 0; i < n; ++i) {
14281 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14282 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14285 // Avoid underflow.
14286 APInt Val = Elt->getAPIntValue();
14290 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14293 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14296 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14297 SelectionDAG &DAG) {
14298 SDValue Op0 = Op.getOperand(0);
14299 SDValue Op1 = Op.getOperand(1);
14300 SDValue CC = Op.getOperand(2);
14301 MVT VT = Op.getSimpleValueType();
14302 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14303 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14308 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14309 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14312 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14313 unsigned Opc = X86ISD::CMPP;
14314 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14315 assert(VT.getVectorNumElements() <= 16);
14316 Opc = X86ISD::CMPM;
14318 // In the two special cases we can't handle, emit two comparisons.
14321 unsigned CombineOpc;
14322 if (SetCCOpcode == ISD::SETUEQ) {
14323 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14325 assert(SetCCOpcode == ISD::SETONE);
14326 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14329 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14330 DAG.getConstant(CC0, dl, MVT::i8));
14331 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14332 DAG.getConstant(CC1, dl, MVT::i8));
14333 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14335 // Handle all other FP comparisons here.
14336 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14337 DAG.getConstant(SSECC, dl, MVT::i8));
14340 MVT VTOp0 = Op0.getSimpleValueType();
14341 assert(VTOp0 == Op1.getSimpleValueType() &&
14342 "Expected operands with same type!");
14343 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14344 "Invalid number of packed elements for source and destination!");
14346 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14347 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14348 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14349 // legalizer firstly checks if the first operand in input to the setcc has
14350 // a legal type. If so, then it promotes the return type to that same type.
14351 // Otherwise, the return type is promoted to the 'next legal type' which,
14352 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14354 // We reach this code only if the following two conditions are met:
14355 // 1. Both return type and operand type have been promoted to wider types
14356 // by the type legalizer.
14357 // 2. The original operand type has been promoted to a 256-bit vector.
14359 // Note that condition 2. only applies for AVX targets.
14360 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14361 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14364 // The non-AVX512 code below works under the assumption that source and
14365 // destination types are the same.
14366 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14367 "Value types for source and destination must be the same!");
14369 // Break 256-bit integer vector compare into smaller ones.
14370 if (VT.is256BitVector() && !Subtarget->hasInt256())
14371 return Lower256IntVSETCC(Op, DAG);
14373 MVT OpVT = Op1.getSimpleValueType();
14374 if (OpVT.getVectorElementType() == MVT::i1)
14375 return LowerBoolVSETCC_AVX512(Op, DAG);
14377 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14378 if (Subtarget->hasAVX512()) {
14379 if (Op1.getSimpleValueType().is512BitVector() ||
14380 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14381 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14382 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14384 // In AVX-512 architecture setcc returns mask with i1 elements,
14385 // But there is no compare instruction for i8 and i16 elements in KNL.
14386 // We are not talking about 512-bit operands in this case, these
14387 // types are illegal.
14389 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14390 OpVT.getVectorElementType().getSizeInBits() >= 8))
14391 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14392 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14395 // Lower using XOP integer comparisons.
14396 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14397 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14398 // Translate compare code to XOP PCOM compare mode.
14399 unsigned CmpMode = 0;
14400 switch (SetCCOpcode) {
14401 default: llvm_unreachable("Unexpected SETCC condition");
14403 case ISD::SETLT: CmpMode = 0x00; break;
14405 case ISD::SETLE: CmpMode = 0x01; break;
14407 case ISD::SETGT: CmpMode = 0x02; break;
14409 case ISD::SETGE: CmpMode = 0x03; break;
14410 case ISD::SETEQ: CmpMode = 0x04; break;
14411 case ISD::SETNE: CmpMode = 0x05; break;
14414 // Are we comparing unsigned or signed integers?
14415 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14416 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14418 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14419 DAG.getConstant(CmpMode, dl, MVT::i8));
14422 // We are handling one of the integer comparisons here. Since SSE only has
14423 // GT and EQ comparisons for integer, swapping operands and multiple
14424 // operations may be required for some comparisons.
14426 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14427 bool Subus = false;
14429 switch (SetCCOpcode) {
14430 default: llvm_unreachable("Unexpected SETCC condition");
14431 case ISD::SETNE: Invert = true;
14432 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14433 case ISD::SETLT: Swap = true;
14434 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14435 case ISD::SETGE: Swap = true;
14436 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14437 Invert = true; break;
14438 case ISD::SETULT: Swap = true;
14439 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14440 FlipSigns = true; break;
14441 case ISD::SETUGE: Swap = true;
14442 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14443 FlipSigns = true; Invert = true; break;
14446 // Special case: Use min/max operations for SETULE/SETUGE
14447 MVT VET = VT.getVectorElementType();
14449 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14450 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14453 switch (SetCCOpcode) {
14455 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14456 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14459 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14462 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14463 if (!MinMax && hasSubus) {
14464 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14466 // t = psubus Op0, Op1
14467 // pcmpeq t, <0..0>
14468 switch (SetCCOpcode) {
14470 case ISD::SETULT: {
14471 // If the comparison is against a constant we can turn this into a
14472 // setule. With psubus, setule does not require a swap. This is
14473 // beneficial because the constant in the register is no longer
14474 // destructed as the destination so it can be hoisted out of a loop.
14475 // Only do this pre-AVX since vpcmp* is no longer destructive.
14476 if (Subtarget->hasAVX())
14478 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14479 if (ULEOp1.getNode()) {
14481 Subus = true; Invert = false; Swap = false;
14485 // Psubus is better than flip-sign because it requires no inversion.
14486 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14487 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14491 Opc = X86ISD::SUBUS;
14497 std::swap(Op0, Op1);
14499 // Check that the operation in question is available (most are plain SSE2,
14500 // but PCMPGTQ and PCMPEQQ have different requirements).
14501 if (VT == MVT::v2i64) {
14502 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14503 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14505 // First cast everything to the right type.
14506 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14507 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14509 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14510 // bits of the inputs before performing those operations. The lower
14511 // compare is always unsigned.
14514 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14516 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14517 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14518 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14519 Sign, Zero, Sign, Zero);
14521 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14522 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14524 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14525 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14526 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14528 // Create masks for only the low parts/high parts of the 64 bit integers.
14529 static const int MaskHi[] = { 1, 1, 3, 3 };
14530 static const int MaskLo[] = { 0, 0, 2, 2 };
14531 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14532 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14533 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14535 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14536 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14539 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14541 return DAG.getBitcast(VT, Result);
14544 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14545 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14546 // pcmpeqd + pshufd + pand.
14547 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14549 // First cast everything to the right type.
14550 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14551 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14554 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14556 // Make sure the lower and upper halves are both all-ones.
14557 static const int Mask[] = { 1, 0, 3, 2 };
14558 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14559 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14562 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14564 return DAG.getBitcast(VT, Result);
14568 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14569 // bits of the inputs before performing those operations.
14571 MVT EltVT = VT.getVectorElementType();
14572 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14574 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14575 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14578 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14580 // If the logical-not of the result is required, perform that now.
14582 Result = DAG.getNOT(dl, Result, VT);
14585 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14588 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14589 getZeroVector(VT, Subtarget, DAG, dl));
14594 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14596 MVT VT = Op.getSimpleValueType();
14598 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14600 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14601 && "SetCC type must be 8-bit or 1-bit integer");
14602 SDValue Op0 = Op.getOperand(0);
14603 SDValue Op1 = Op.getOperand(1);
14605 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14607 // Optimize to BT if possible.
14608 // Lower (X & (1 << N)) == 0 to BT(X, N).
14609 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14610 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14611 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14612 isNullConstant(Op1) &&
14613 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14614 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14616 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14621 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14623 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14624 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14626 // If the input is a setcc, then reuse the input setcc or use a new one with
14627 // the inverted condition.
14628 if (Op0.getOpcode() == X86ISD::SETCC) {
14629 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14630 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14634 CCode = X86::GetOppositeBranchCondition(CCode);
14635 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14636 DAG.getConstant(CCode, dl, MVT::i8),
14637 Op0.getOperand(1));
14639 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14643 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14644 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14646 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14647 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14650 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14651 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14652 if (X86CC == X86::COND_INVALID)
14655 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14656 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14657 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14658 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14660 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14664 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14665 SDValue LHS = Op.getOperand(0);
14666 SDValue RHS = Op.getOperand(1);
14667 SDValue Carry = Op.getOperand(2);
14668 SDValue Cond = Op.getOperand(3);
14671 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14672 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14674 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14675 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14676 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14677 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14678 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14681 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14682 static bool isX86LogicalCmp(SDValue Op) {
14683 unsigned Opc = Op.getNode()->getOpcode();
14684 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14685 Opc == X86ISD::SAHF)
14687 if (Op.getResNo() == 1 &&
14688 (Opc == X86ISD::ADD ||
14689 Opc == X86ISD::SUB ||
14690 Opc == X86ISD::ADC ||
14691 Opc == X86ISD::SBB ||
14692 Opc == X86ISD::SMUL ||
14693 Opc == X86ISD::UMUL ||
14694 Opc == X86ISD::INC ||
14695 Opc == X86ISD::DEC ||
14696 Opc == X86ISD::OR ||
14697 Opc == X86ISD::XOR ||
14698 Opc == X86ISD::AND))
14701 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14707 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14708 if (V.getOpcode() != ISD::TRUNCATE)
14711 SDValue VOp0 = V.getOperand(0);
14712 unsigned InBits = VOp0.getValueSizeInBits();
14713 unsigned Bits = V.getValueSizeInBits();
14714 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14717 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14718 bool addTest = true;
14719 SDValue Cond = Op.getOperand(0);
14720 SDValue Op1 = Op.getOperand(1);
14721 SDValue Op2 = Op.getOperand(2);
14723 MVT VT = Op1.getSimpleValueType();
14726 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14727 // are available or VBLENDV if AVX is available.
14728 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14729 if (Cond.getOpcode() == ISD::SETCC &&
14730 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14731 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14732 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14733 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14734 int SSECC = translateX86FSETCC(
14735 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14738 if (Subtarget->hasAVX512()) {
14739 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14740 DAG.getConstant(SSECC, DL, MVT::i8));
14741 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14744 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14745 DAG.getConstant(SSECC, DL, MVT::i8));
14747 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14748 // of 3 logic instructions for size savings and potentially speed.
14749 // Unfortunately, there is no scalar form of VBLENDV.
14751 // If either operand is a constant, don't try this. We can expect to
14752 // optimize away at least one of the logic instructions later in that
14753 // case, so that sequence would be faster than a variable blend.
14755 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14756 // uses XMM0 as the selection register. That may need just as many
14757 // instructions as the AND/ANDN/OR sequence due to register moves, so
14760 if (Subtarget->hasAVX() &&
14761 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14763 // Convert to vectors, do a VSELECT, and convert back to scalar.
14764 // All of the conversions should be optimized away.
14766 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14767 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14768 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14769 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14771 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14772 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14774 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14776 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14777 VSel, DAG.getIntPtrConstant(0, DL));
14779 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14780 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14781 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14785 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14787 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14788 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14789 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14790 Op1Scalar = Op1.getOperand(0);
14792 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14793 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14794 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14795 Op2Scalar = Op2.getOperand(0);
14796 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14797 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14798 Op1Scalar.getValueType(),
14799 Cond, Op1Scalar, Op2Scalar);
14800 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14801 return DAG.getBitcast(VT, newSelect);
14802 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14803 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14804 DAG.getIntPtrConstant(0, DL));
14808 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14809 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14810 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14811 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14812 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14813 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14814 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14816 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14819 if (Cond.getOpcode() == ISD::SETCC) {
14820 SDValue NewCond = LowerSETCC(Cond, DAG);
14821 if (NewCond.getNode())
14825 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14826 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14827 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14828 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14829 if (Cond.getOpcode() == X86ISD::SETCC &&
14830 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14831 isNullConstant(Cond.getOperand(1).getOperand(1))) {
14832 SDValue Cmp = Cond.getOperand(1);
14834 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14836 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14837 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14838 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
14840 SDValue CmpOp0 = Cmp.getOperand(0);
14841 // Apply further optimizations for special cases
14842 // (select (x != 0), -1, 0) -> neg & sbb
14843 // (select (x == 0), 0, -1) -> neg & sbb
14844 if (isNullConstant(Y) &&
14845 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
14846 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14847 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14848 DAG.getConstant(0, DL,
14849 CmpOp0.getValueType()),
14851 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14852 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14853 SDValue(Neg.getNode(), 1));
14857 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14858 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14859 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14861 SDValue Res = // Res = 0 or -1.
14862 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14863 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14865 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
14866 Res = DAG.getNOT(DL, Res, Res.getValueType());
14868 if (!isNullConstant(Op2))
14869 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14874 // Look past (and (setcc_carry (cmp ...)), 1).
14875 if (Cond.getOpcode() == ISD::AND &&
14876 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
14877 isOneConstant(Cond.getOperand(1)))
14878 Cond = Cond.getOperand(0);
14880 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14881 // setting operand in place of the X86ISD::SETCC.
14882 unsigned CondOpcode = Cond.getOpcode();
14883 if (CondOpcode == X86ISD::SETCC ||
14884 CondOpcode == X86ISD::SETCC_CARRY) {
14885 CC = Cond.getOperand(0);
14887 SDValue Cmp = Cond.getOperand(1);
14888 unsigned Opc = Cmp.getOpcode();
14889 MVT VT = Op.getSimpleValueType();
14891 bool IllegalFPCMov = false;
14892 if (VT.isFloatingPoint() && !VT.isVector() &&
14893 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14894 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14896 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14897 Opc == X86ISD::BT) { // FIXME
14901 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14902 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14903 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14904 Cond.getOperand(0).getValueType() != MVT::i8)) {
14905 SDValue LHS = Cond.getOperand(0);
14906 SDValue RHS = Cond.getOperand(1);
14907 unsigned X86Opcode;
14910 switch (CondOpcode) {
14911 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14912 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14913 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14914 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14915 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14916 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14917 default: llvm_unreachable("unexpected overflowing operator");
14919 if (CondOpcode == ISD::UMULO)
14920 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14923 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14925 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14927 if (CondOpcode == ISD::UMULO)
14928 Cond = X86Op.getValue(2);
14930 Cond = X86Op.getValue(1);
14932 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14937 // Look past the truncate if the high bits are known zero.
14938 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14939 Cond = Cond.getOperand(0);
14941 // We know the result of AND is compared against zero. Try to match
14943 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14944 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
14945 CC = NewSetCC.getOperand(0);
14946 Cond = NewSetCC.getOperand(1);
14953 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14954 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14957 // a < b ? -1 : 0 -> RES = ~setcc_carry
14958 // a < b ? 0 : -1 -> RES = setcc_carry
14959 // a >= b ? -1 : 0 -> RES = setcc_carry
14960 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14961 if (Cond.getOpcode() == X86ISD::SUB) {
14962 Cond = ConvertCmpIfNecessary(Cond, DAG);
14963 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14965 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14966 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
14967 (isNullConstant(Op1) || isNullConstant(Op2))) {
14968 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14969 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14971 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
14972 return DAG.getNOT(DL, Res, Res.getValueType());
14977 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14978 // widen the cmov and push the truncate through. This avoids introducing a new
14979 // branch during isel and doesn't add any extensions.
14980 if (Op.getValueType() == MVT::i8 &&
14981 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14982 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14983 if (T1.getValueType() == T2.getValueType() &&
14984 // Blacklist CopyFromReg to avoid partial register stalls.
14985 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14986 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14987 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14988 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14992 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14993 // condition is true.
14994 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14995 SDValue Ops[] = { Op2, Op1, CC, Cond };
14996 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14999 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15000 const X86Subtarget *Subtarget,
15001 SelectionDAG &DAG) {
15002 MVT VT = Op->getSimpleValueType(0);
15003 SDValue In = Op->getOperand(0);
15004 MVT InVT = In.getSimpleValueType();
15005 MVT VTElt = VT.getVectorElementType();
15006 MVT InVTElt = InVT.getVectorElementType();
15010 if ((InVTElt == MVT::i1) &&
15011 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15012 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15014 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15015 VTElt.getSizeInBits() <= 16)) ||
15017 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15018 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15020 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15021 VTElt.getSizeInBits() >= 32))))
15022 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15024 unsigned int NumElts = VT.getVectorNumElements();
15026 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15029 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15030 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15031 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15032 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15035 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15036 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15038 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15041 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15043 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15044 if (VT.is512BitVector())
15046 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15049 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15050 const X86Subtarget *Subtarget,
15051 SelectionDAG &DAG) {
15052 SDValue In = Op->getOperand(0);
15053 MVT VT = Op->getSimpleValueType(0);
15054 MVT InVT = In.getSimpleValueType();
15055 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15057 MVT InSVT = InVT.getVectorElementType();
15058 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15060 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15062 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15067 // SSE41 targets can use the pmovsx* instructions directly.
15068 if (Subtarget->hasSSE41())
15069 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15071 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15075 // As SRAI is only available on i16/i32 types, we expand only up to i32
15076 // and handle i64 separately.
15077 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15078 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15079 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15080 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15081 Curr = DAG.getBitcast(CurrVT, Curr);
15084 SDValue SignExt = Curr;
15085 if (CurrVT != InVT) {
15086 unsigned SignExtShift =
15087 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15088 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15089 DAG.getConstant(SignExtShift, dl, MVT::i8));
15095 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15096 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15097 DAG.getConstant(31, dl, MVT::i8));
15098 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15099 return DAG.getBitcast(VT, Ext);
15105 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15106 SelectionDAG &DAG) {
15107 MVT VT = Op->getSimpleValueType(0);
15108 SDValue In = Op->getOperand(0);
15109 MVT InVT = In.getSimpleValueType();
15112 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15113 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15115 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15116 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15117 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15120 if (Subtarget->hasInt256())
15121 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15123 // Optimize vectors in AVX mode
15124 // Sign extend v8i16 to v8i32 and
15127 // Divide input vector into two parts
15128 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15129 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15130 // concat the vectors to original VT
15132 unsigned NumElems = InVT.getVectorNumElements();
15133 SDValue Undef = DAG.getUNDEF(InVT);
15135 SmallVector<int,8> ShufMask1(NumElems, -1);
15136 for (unsigned i = 0; i != NumElems/2; ++i)
15139 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15141 SmallVector<int,8> ShufMask2(NumElems, -1);
15142 for (unsigned i = 0; i != NumElems/2; ++i)
15143 ShufMask2[i] = i + NumElems/2;
15145 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15147 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15148 VT.getVectorNumElements()/2);
15150 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15151 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15153 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15156 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15157 // may emit an illegal shuffle but the expansion is still better than scalar
15158 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15159 // we'll emit a shuffle and a arithmetic shift.
15160 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15161 // TODO: It is possible to support ZExt by zeroing the undef values during
15162 // the shuffle phase or after the shuffle.
15163 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15164 SelectionDAG &DAG) {
15165 MVT RegVT = Op.getSimpleValueType();
15166 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15167 assert(RegVT.isInteger() &&
15168 "We only custom lower integer vector sext loads.");
15170 // Nothing useful we can do without SSE2 shuffles.
15171 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15173 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15175 EVT MemVT = Ld->getMemoryVT();
15176 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15177 unsigned RegSz = RegVT.getSizeInBits();
15179 ISD::LoadExtType Ext = Ld->getExtensionType();
15181 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15182 && "Only anyext and sext are currently implemented.");
15183 assert(MemVT != RegVT && "Cannot extend to the same type");
15184 assert(MemVT.isVector() && "Must load a vector from memory");
15186 unsigned NumElems = RegVT.getVectorNumElements();
15187 unsigned MemSz = MemVT.getSizeInBits();
15188 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15190 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15191 // The only way in which we have a legal 256-bit vector result but not the
15192 // integer 256-bit operations needed to directly lower a sextload is if we
15193 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15194 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15195 // correctly legalized. We do this late to allow the canonical form of
15196 // sextload to persist throughout the rest of the DAG combiner -- it wants
15197 // to fold together any extensions it can, and so will fuse a sign_extend
15198 // of an sextload into a sextload targeting a wider value.
15200 if (MemSz == 128) {
15201 // Just switch this to a normal load.
15202 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15203 "it must be a legal 128-bit vector "
15205 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15206 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15207 Ld->isInvariant(), Ld->getAlignment());
15209 assert(MemSz < 128 &&
15210 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15211 // Do an sext load to a 128-bit vector type. We want to use the same
15212 // number of elements, but elements half as wide. This will end up being
15213 // recursively lowered by this routine, but will succeed as we definitely
15214 // have all the necessary features if we're using AVX1.
15216 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15217 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15219 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15220 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15221 Ld->isNonTemporal(), Ld->isInvariant(),
15222 Ld->getAlignment());
15225 // Replace chain users with the new chain.
15226 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15227 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15229 // Finally, do a normal sign-extend to the desired register.
15230 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15233 // All sizes must be a power of two.
15234 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15235 "Non-power-of-two elements are not custom lowered!");
15237 // Attempt to load the original value using scalar loads.
15238 // Find the largest scalar type that divides the total loaded size.
15239 MVT SclrLoadTy = MVT::i8;
15240 for (MVT Tp : MVT::integer_valuetypes()) {
15241 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15246 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15247 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15249 SclrLoadTy = MVT::f64;
15251 // Calculate the number of scalar loads that we need to perform
15252 // in order to load our vector from memory.
15253 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15255 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15256 "Can only lower sext loads with a single scalar load!");
15258 unsigned loadRegZize = RegSz;
15259 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15262 // Represent our vector as a sequence of elements which are the
15263 // largest scalar that we can load.
15264 EVT LoadUnitVecVT = EVT::getVectorVT(
15265 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15267 // Represent the data using the same element type that is stored in
15268 // memory. In practice, we ''widen'' MemVT.
15270 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15271 loadRegZize / MemVT.getScalarSizeInBits());
15273 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15274 "Invalid vector type");
15276 // We can't shuffle using an illegal type.
15277 assert(TLI.isTypeLegal(WideVecVT) &&
15278 "We only lower types that form legal widened vector types");
15280 SmallVector<SDValue, 8> Chains;
15281 SDValue Ptr = Ld->getBasePtr();
15282 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15283 TLI.getPointerTy(DAG.getDataLayout()));
15284 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15286 for (unsigned i = 0; i < NumLoads; ++i) {
15287 // Perform a single load.
15288 SDValue ScalarLoad =
15289 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15290 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15291 Ld->getAlignment());
15292 Chains.push_back(ScalarLoad.getValue(1));
15293 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15294 // another round of DAGCombining.
15296 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15298 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15299 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15301 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15304 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15306 // Bitcast the loaded value to a vector of the original element type, in
15307 // the size of the target vector type.
15308 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15309 unsigned SizeRatio = RegSz / MemSz;
15311 if (Ext == ISD::SEXTLOAD) {
15312 // If we have SSE4.1, we can directly emit a VSEXT node.
15313 if (Subtarget->hasSSE41()) {
15314 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15315 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15319 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15321 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15322 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15324 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15325 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15329 // Redistribute the loaded elements into the different locations.
15330 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15331 for (unsigned i = 0; i != NumElems; ++i)
15332 ShuffleVec[i * SizeRatio] = i;
15334 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15335 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15337 // Bitcast to the requested type.
15338 Shuff = DAG.getBitcast(RegVT, Shuff);
15339 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15343 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15344 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15345 // from the AND / OR.
15346 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15347 Opc = Op.getOpcode();
15348 if (Opc != ISD::OR && Opc != ISD::AND)
15350 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15351 Op.getOperand(0).hasOneUse() &&
15352 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15353 Op.getOperand(1).hasOneUse());
15356 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15357 // 1 and that the SETCC node has a single use.
15358 static bool isXor1OfSetCC(SDValue Op) {
15359 if (Op.getOpcode() != ISD::XOR)
15361 if (isOneConstant(Op.getOperand(1)))
15362 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15363 Op.getOperand(0).hasOneUse();
15367 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15368 bool addTest = true;
15369 SDValue Chain = Op.getOperand(0);
15370 SDValue Cond = Op.getOperand(1);
15371 SDValue Dest = Op.getOperand(2);
15374 bool Inverted = false;
15376 if (Cond.getOpcode() == ISD::SETCC) {
15377 // Check for setcc([su]{add,sub,mul}o == 0).
15378 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15379 isNullConstant(Cond.getOperand(1)) &&
15380 Cond.getOperand(0).getResNo() == 1 &&
15381 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15382 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15383 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15384 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15385 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15386 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15388 Cond = Cond.getOperand(0);
15390 SDValue NewCond = LowerSETCC(Cond, DAG);
15391 if (NewCond.getNode())
15396 // FIXME: LowerXALUO doesn't handle these!!
15397 else if (Cond.getOpcode() == X86ISD::ADD ||
15398 Cond.getOpcode() == X86ISD::SUB ||
15399 Cond.getOpcode() == X86ISD::SMUL ||
15400 Cond.getOpcode() == X86ISD::UMUL)
15401 Cond = LowerXALUO(Cond, DAG);
15404 // Look pass (and (setcc_carry (cmp ...)), 1).
15405 if (Cond.getOpcode() == ISD::AND &&
15406 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15407 isOneConstant(Cond.getOperand(1)))
15408 Cond = Cond.getOperand(0);
15410 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15411 // setting operand in place of the X86ISD::SETCC.
15412 unsigned CondOpcode = Cond.getOpcode();
15413 if (CondOpcode == X86ISD::SETCC ||
15414 CondOpcode == X86ISD::SETCC_CARRY) {
15415 CC = Cond.getOperand(0);
15417 SDValue Cmp = Cond.getOperand(1);
15418 unsigned Opc = Cmp.getOpcode();
15419 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15420 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15424 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15428 // These can only come from an arithmetic instruction with overflow,
15429 // e.g. SADDO, UADDO.
15430 Cond = Cond.getNode()->getOperand(1);
15436 CondOpcode = Cond.getOpcode();
15437 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15438 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15439 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15440 Cond.getOperand(0).getValueType() != MVT::i8)) {
15441 SDValue LHS = Cond.getOperand(0);
15442 SDValue RHS = Cond.getOperand(1);
15443 unsigned X86Opcode;
15446 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15447 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15449 switch (CondOpcode) {
15450 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15452 if (isOneConstant(RHS)) {
15453 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15456 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15457 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15459 if (isOneConstant(RHS)) {
15460 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15463 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15464 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15465 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15466 default: llvm_unreachable("unexpected overflowing operator");
15469 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15470 if (CondOpcode == ISD::UMULO)
15471 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15474 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15476 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15478 if (CondOpcode == ISD::UMULO)
15479 Cond = X86Op.getValue(2);
15481 Cond = X86Op.getValue(1);
15483 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15487 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15488 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15489 if (CondOpc == ISD::OR) {
15490 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15491 // two branches instead of an explicit OR instruction with a
15493 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15494 isX86LogicalCmp(Cmp)) {
15495 CC = Cond.getOperand(0).getOperand(0);
15496 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15497 Chain, Dest, CC, Cmp);
15498 CC = Cond.getOperand(1).getOperand(0);
15502 } else { // ISD::AND
15503 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15504 // two branches instead of an explicit AND instruction with a
15505 // separate test. However, we only do this if this block doesn't
15506 // have a fall-through edge, because this requires an explicit
15507 // jmp when the condition is false.
15508 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15509 isX86LogicalCmp(Cmp) &&
15510 Op.getNode()->hasOneUse()) {
15511 X86::CondCode CCode =
15512 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15513 CCode = X86::GetOppositeBranchCondition(CCode);
15514 CC = DAG.getConstant(CCode, dl, MVT::i8);
15515 SDNode *User = *Op.getNode()->use_begin();
15516 // Look for an unconditional branch following this conditional branch.
15517 // We need this because we need to reverse the successors in order
15518 // to implement FCMP_OEQ.
15519 if (User->getOpcode() == ISD::BR) {
15520 SDValue FalseBB = User->getOperand(1);
15522 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15523 assert(NewBR == User);
15527 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15528 Chain, Dest, CC, Cmp);
15529 X86::CondCode CCode =
15530 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15531 CCode = X86::GetOppositeBranchCondition(CCode);
15532 CC = DAG.getConstant(CCode, dl, MVT::i8);
15538 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15539 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15540 // It should be transformed during dag combiner except when the condition
15541 // is set by a arithmetics with overflow node.
15542 X86::CondCode CCode =
15543 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15544 CCode = X86::GetOppositeBranchCondition(CCode);
15545 CC = DAG.getConstant(CCode, dl, MVT::i8);
15546 Cond = Cond.getOperand(0).getOperand(1);
15548 } else if (Cond.getOpcode() == ISD::SETCC &&
15549 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15550 // For FCMP_OEQ, we can emit
15551 // two branches instead of an explicit AND instruction with a
15552 // separate test. However, we only do this if this block doesn't
15553 // have a fall-through edge, because this requires an explicit
15554 // jmp when the condition is false.
15555 if (Op.getNode()->hasOneUse()) {
15556 SDNode *User = *Op.getNode()->use_begin();
15557 // Look for an unconditional branch following this conditional branch.
15558 // We need this because we need to reverse the successors in order
15559 // to implement FCMP_OEQ.
15560 if (User->getOpcode() == ISD::BR) {
15561 SDValue FalseBB = User->getOperand(1);
15563 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15564 assert(NewBR == User);
15568 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15569 Cond.getOperand(0), Cond.getOperand(1));
15570 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15571 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15572 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15573 Chain, Dest, CC, Cmp);
15574 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15579 } else if (Cond.getOpcode() == ISD::SETCC &&
15580 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15581 // For FCMP_UNE, we can emit
15582 // two branches instead of an explicit AND instruction with a
15583 // separate test. However, we only do this if this block doesn't
15584 // have a fall-through edge, because this requires an explicit
15585 // jmp when the condition is false.
15586 if (Op.getNode()->hasOneUse()) {
15587 SDNode *User = *Op.getNode()->use_begin();
15588 // Look for an unconditional branch following this conditional branch.
15589 // We need this because we need to reverse the successors in order
15590 // to implement FCMP_UNE.
15591 if (User->getOpcode() == ISD::BR) {
15592 SDValue FalseBB = User->getOperand(1);
15594 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15595 assert(NewBR == User);
15598 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15599 Cond.getOperand(0), Cond.getOperand(1));
15600 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15601 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15602 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15603 Chain, Dest, CC, Cmp);
15604 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15614 // Look pass the truncate if the high bits are known zero.
15615 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15616 Cond = Cond.getOperand(0);
15618 // We know the result of AND is compared against zero. Try to match
15620 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15621 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15622 CC = NewSetCC.getOperand(0);
15623 Cond = NewSetCC.getOperand(1);
15630 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15631 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15632 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15634 Cond = ConvertCmpIfNecessary(Cond, DAG);
15635 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15636 Chain, Dest, CC, Cond);
15639 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15640 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15641 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15642 // that the guard pages used by the OS virtual memory manager are allocated in
15643 // correct sequence.
15645 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15646 SelectionDAG &DAG) const {
15647 MachineFunction &MF = DAG.getMachineFunction();
15648 bool SplitStack = MF.shouldSplitStack();
15649 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15654 SDNode *Node = Op.getNode();
15655 SDValue Chain = Op.getOperand(0);
15656 SDValue Size = Op.getOperand(1);
15657 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15658 EVT VT = Node->getValueType(0);
15660 // Chain the dynamic stack allocation so that it doesn't modify the stack
15661 // pointer when other instructions are using the stack.
15662 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
15664 bool Is64Bit = Subtarget->is64Bit();
15665 MVT SPTy = getPointerTy(DAG.getDataLayout());
15669 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15670 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15671 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15672 " not tell us which reg is the stack pointer!");
15673 EVT VT = Node->getValueType(0);
15674 SDValue Tmp3 = Node->getOperand(2);
15676 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15677 Chain = SP.getValue(1);
15678 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15679 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15680 unsigned StackAlign = TFI.getStackAlignment();
15681 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15682 if (Align > StackAlign)
15683 Result = DAG.getNode(ISD::AND, dl, VT, Result,
15684 DAG.getConstant(-(uint64_t)Align, dl, VT));
15685 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
15686 } else if (SplitStack) {
15687 MachineRegisterInfo &MRI = MF.getRegInfo();
15690 // The 64 bit implementation of segmented stacks needs to clobber both r10
15691 // r11. This makes it impossible to use it along with nested parameters.
15692 const Function *F = MF.getFunction();
15694 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15696 if (I->hasNestAttr())
15697 report_fatal_error("Cannot use segmented stacks with functions that "
15698 "have nested arguments.");
15701 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15702 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15703 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15704 Result = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15705 DAG.getRegister(Vreg, SPTy));
15708 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15710 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15711 Flag = Chain.getValue(1);
15712 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15714 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15716 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15717 unsigned SPReg = RegInfo->getStackRegister();
15718 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15719 Chain = SP.getValue(1);
15722 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15723 DAG.getConstant(-(uint64_t)Align, dl, VT));
15724 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15730 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15731 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
15733 SDValue Ops[2] = {Result, Chain};
15734 return DAG.getMergeValues(Ops, dl);
15737 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15738 MachineFunction &MF = DAG.getMachineFunction();
15739 auto PtrVT = getPointerTy(MF.getDataLayout());
15740 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15742 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15745 if (!Subtarget->is64Bit() ||
15746 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15747 // vastart just stores the address of the VarArgsFrameIndex slot into the
15748 // memory location argument.
15749 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15750 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15751 MachinePointerInfo(SV), false, false, 0);
15755 // gp_offset (0 - 6 * 8)
15756 // fp_offset (48 - 48 + 8 * 16)
15757 // overflow_arg_area (point to parameters coming in memory).
15759 SmallVector<SDValue, 8> MemOps;
15760 SDValue FIN = Op.getOperand(1);
15762 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15763 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15765 FIN, MachinePointerInfo(SV), false, false, 0);
15766 MemOps.push_back(Store);
15769 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15770 Store = DAG.getStore(Op.getOperand(0), DL,
15771 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15773 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15774 MemOps.push_back(Store);
15776 // Store ptr to overflow_arg_area
15777 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15778 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15779 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15780 MachinePointerInfo(SV, 8),
15782 MemOps.push_back(Store);
15784 // Store ptr to reg_save_area.
15785 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15786 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15787 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15788 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15789 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15790 MemOps.push_back(Store);
15791 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15794 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15795 assert(Subtarget->is64Bit() &&
15796 "LowerVAARG only handles 64-bit va_arg!");
15797 assert(Op.getNode()->getNumOperands() == 4);
15799 MachineFunction &MF = DAG.getMachineFunction();
15800 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15801 // The Win64 ABI uses char* instead of a structure.
15802 return DAG.expandVAArg(Op.getNode());
15804 SDValue Chain = Op.getOperand(0);
15805 SDValue SrcPtr = Op.getOperand(1);
15806 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15807 unsigned Align = Op.getConstantOperandVal(3);
15810 EVT ArgVT = Op.getNode()->getValueType(0);
15811 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15812 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15815 // Decide which area this value should be read from.
15816 // TODO: Implement the AMD64 ABI in its entirety. This simple
15817 // selection mechanism works only for the basic types.
15818 if (ArgVT == MVT::f80) {
15819 llvm_unreachable("va_arg for f80 not yet implemented");
15820 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15821 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15822 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15823 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15825 llvm_unreachable("Unhandled argument type in LowerVAARG");
15828 if (ArgMode == 2) {
15829 // Sanity Check: Make sure using fp_offset makes sense.
15830 assert(!Subtarget->useSoftFloat() &&
15831 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15832 Subtarget->hasSSE1());
15835 // Insert VAARG_64 node into the DAG
15836 // VAARG_64 returns two values: Variable Argument Address, Chain
15837 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15838 DAG.getConstant(ArgMode, dl, MVT::i8),
15839 DAG.getConstant(Align, dl, MVT::i32)};
15840 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15841 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15842 VTs, InstOps, MVT::i64,
15843 MachinePointerInfo(SV),
15845 /*Volatile=*/false,
15847 /*WriteMem=*/true);
15848 Chain = VAARG.getValue(1);
15850 // Load the next argument and return it
15851 return DAG.getLoad(ArgVT, dl,
15854 MachinePointerInfo(),
15855 false, false, false, 0);
15858 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15859 SelectionDAG &DAG) {
15860 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15861 // where a va_list is still an i8*.
15862 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15863 if (Subtarget->isCallingConvWin64(
15864 DAG.getMachineFunction().getFunction()->getCallingConv()))
15865 // Probably a Win64 va_copy.
15866 return DAG.expandVACopy(Op.getNode());
15868 SDValue Chain = Op.getOperand(0);
15869 SDValue DstPtr = Op.getOperand(1);
15870 SDValue SrcPtr = Op.getOperand(2);
15871 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15872 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15875 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15876 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15878 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15881 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15882 // amount is a constant. Takes immediate version of shift as input.
15883 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15884 SDValue SrcOp, uint64_t ShiftAmt,
15885 SelectionDAG &DAG) {
15886 MVT ElementType = VT.getVectorElementType();
15888 // Fold this packed shift into its first operand if ShiftAmt is 0.
15892 // Check for ShiftAmt >= element width
15893 if (ShiftAmt >= ElementType.getSizeInBits()) {
15894 if (Opc == X86ISD::VSRAI)
15895 ShiftAmt = ElementType.getSizeInBits() - 1;
15897 return DAG.getConstant(0, dl, VT);
15900 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15901 && "Unknown target vector shift-by-constant node");
15903 // Fold this packed vector shift into a build vector if SrcOp is a
15904 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15905 if (VT == SrcOp.getSimpleValueType() &&
15906 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15907 SmallVector<SDValue, 8> Elts;
15908 unsigned NumElts = SrcOp->getNumOperands();
15909 ConstantSDNode *ND;
15912 default: llvm_unreachable(nullptr);
15913 case X86ISD::VSHLI:
15914 for (unsigned i=0; i!=NumElts; ++i) {
15915 SDValue CurrentOp = SrcOp->getOperand(i);
15916 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15917 Elts.push_back(CurrentOp);
15920 ND = cast<ConstantSDNode>(CurrentOp);
15921 const APInt &C = ND->getAPIntValue();
15922 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15925 case X86ISD::VSRLI:
15926 for (unsigned i=0; i!=NumElts; ++i) {
15927 SDValue CurrentOp = SrcOp->getOperand(i);
15928 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15929 Elts.push_back(CurrentOp);
15932 ND = cast<ConstantSDNode>(CurrentOp);
15933 const APInt &C = ND->getAPIntValue();
15934 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15937 case X86ISD::VSRAI:
15938 for (unsigned i=0; i!=NumElts; ++i) {
15939 SDValue CurrentOp = SrcOp->getOperand(i);
15940 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15941 Elts.push_back(CurrentOp);
15944 ND = cast<ConstantSDNode>(CurrentOp);
15945 const APInt &C = ND->getAPIntValue();
15946 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15951 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15954 return DAG.getNode(Opc, dl, VT, SrcOp,
15955 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15958 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15959 // may or may not be a constant. Takes immediate version of shift as input.
15960 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15961 SDValue SrcOp, SDValue ShAmt,
15962 SelectionDAG &DAG) {
15963 MVT SVT = ShAmt.getSimpleValueType();
15964 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15966 // Catch shift-by-constant.
15967 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15968 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15969 CShAmt->getZExtValue(), DAG);
15971 // Change opcode to non-immediate version
15973 default: llvm_unreachable("Unknown target vector shift node");
15974 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15975 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15976 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15979 const X86Subtarget &Subtarget =
15980 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15981 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15982 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15983 // Let the shuffle legalizer expand this shift amount node.
15984 SDValue Op0 = ShAmt.getOperand(0);
15985 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15986 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15988 // Need to build a vector containing shift amount.
15989 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15990 SmallVector<SDValue, 4> ShOps;
15991 ShOps.push_back(ShAmt);
15992 if (SVT == MVT::i32) {
15993 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15994 ShOps.push_back(DAG.getUNDEF(SVT));
15996 ShOps.push_back(DAG.getUNDEF(SVT));
15998 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15999 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16002 // The return type has to be a 128-bit type with the same element
16003 // type as the input type.
16004 MVT EltVT = VT.getVectorElementType();
16005 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16007 ShAmt = DAG.getBitcast(ShVT, ShAmt);
16008 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16011 /// \brief Return Mask with the necessary casting or extending
16012 /// for \p Mask according to \p MaskVT when lowering masking intrinsics
16013 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
16014 const X86Subtarget *Subtarget,
16015 SelectionDAG &DAG, SDLoc dl) {
16017 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16018 // Mask should be extended
16019 Mask = DAG.getNode(ISD::ANY_EXTEND, dl,
16020 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask);
16023 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget->is32Bit()) {
16024 if (MaskVT == MVT::v64i1) {
16025 assert(Subtarget->hasBWI() && "Expected AVX512BW target!");
16026 // In case 32bit mode, bitcast i64 is illegal, extend/split it.
16028 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16029 DAG.getConstant(0, dl, MVT::i32));
16030 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16031 DAG.getConstant(1, dl, MVT::i32));
16033 Lo = DAG.getBitcast(MVT::v32i1, Lo);
16034 Hi = DAG.getBitcast(MVT::v32i1, Hi);
16036 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
16038 // MaskVT require < 64bit. Truncate mask (should succeed in any case),
16040 MVT TruncVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16041 return DAG.getBitcast(MaskVT,
16042 DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Mask));
16046 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16047 Mask.getSimpleValueType().getSizeInBits());
16048 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16049 // are extracted by EXTRACT_SUBVECTOR.
16050 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16051 DAG.getBitcast(BitcastVT, Mask),
16052 DAG.getIntPtrConstant(0, dl));
16056 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16057 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16058 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16059 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16060 SDValue PreservedSrc,
16061 const X86Subtarget *Subtarget,
16062 SelectionDAG &DAG) {
16063 MVT VT = Op.getSimpleValueType();
16064 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16065 unsigned OpcodeSelect = ISD::VSELECT;
16068 if (isAllOnesConstant(Mask))
16071 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16073 switch (Op.getOpcode()) {
16075 case X86ISD::PCMPEQM:
16076 case X86ISD::PCMPGTM:
16078 case X86ISD::CMPMU:
16079 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16080 case X86ISD::VFPCLASS:
16081 case X86ISD::VFPCLASSS:
16082 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16083 case X86ISD::VTRUNC:
16084 case X86ISD::VTRUNCS:
16085 case X86ISD::VTRUNCUS:
16086 // We can't use ISD::VSELECT here because it is not always "Legal"
16087 // for the destination type. For example vpmovqb require only AVX512
16088 // and vselect that can operate on byte element type require BWI
16089 OpcodeSelect = X86ISD::SELECT;
16092 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16093 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16094 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16097 /// \brief Creates an SDNode for a predicated scalar operation.
16098 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16099 /// The mask is coming as MVT::i8 and it should be truncated
16100 /// to MVT::i1 while lowering masking intrinsics.
16101 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16102 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16103 /// for a scalar instruction.
16104 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16105 SDValue PreservedSrc,
16106 const X86Subtarget *Subtarget,
16107 SelectionDAG &DAG) {
16108 if (isAllOnesConstant(Mask))
16111 MVT VT = Op.getSimpleValueType();
16113 // The mask should be of type MVT::i1
16114 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16116 if (Op.getOpcode() == X86ISD::FSETCC)
16117 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16118 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16119 Op.getOpcode() == X86ISD::VFPCLASSS)
16120 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16122 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16123 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16124 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16127 static int getSEHRegistrationNodeSize(const Function *Fn) {
16128 if (!Fn->hasPersonalityFn())
16129 report_fatal_error(
16130 "querying registration node size for function without personality");
16131 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16132 // WinEHStatePass for the full struct definition.
16133 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16134 case EHPersonality::MSVC_X86SEH: return 24;
16135 case EHPersonality::MSVC_CXX: return 16;
16138 report_fatal_error("can only recover FP for MSVC EH personality functions");
16141 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16142 /// function or when returning to a parent frame after catching an exception, we
16143 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16144 /// Here's the math:
16145 /// RegNodeBase = EntryEBP - RegNodeSize
16146 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16147 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16148 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16149 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16150 SDValue EntryEBP) {
16151 MachineFunction &MF = DAG.getMachineFunction();
16154 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16155 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16157 // It's possible that the parent function no longer has a personality function
16158 // if the exceptional code was optimized away, in which case we just return
16159 // the incoming EBP.
16160 if (!Fn->hasPersonalityFn())
16163 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16165 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16167 MCSymbol *OffsetSym =
16168 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16169 GlobalValue::getRealLinkageName(Fn->getName()));
16170 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16171 SDValue RegNodeFrameOffset =
16172 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16174 // RegNodeBase = EntryEBP - RegNodeSize
16175 // ParentFP = RegNodeBase - RegNodeFrameOffset
16176 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16177 DAG.getConstant(RegNodeSize, dl, PtrVT));
16178 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16181 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16182 SelectionDAG &DAG) {
16184 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16185 MVT VT = Op.getSimpleValueType();
16186 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16188 switch(IntrData->Type) {
16189 case INTR_TYPE_1OP:
16190 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16191 case INTR_TYPE_2OP:
16192 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16194 case INTR_TYPE_2OP_IMM8:
16195 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16196 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16197 case INTR_TYPE_3OP:
16198 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16199 Op.getOperand(2), Op.getOperand(3));
16200 case INTR_TYPE_4OP:
16201 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16202 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16203 case INTR_TYPE_1OP_MASK_RM: {
16204 SDValue Src = Op.getOperand(1);
16205 SDValue PassThru = Op.getOperand(2);
16206 SDValue Mask = Op.getOperand(3);
16207 SDValue RoundingMode;
16208 // We allways add rounding mode to the Node.
16209 // If the rounding mode is not specified, we add the
16210 // "current direction" mode.
16211 if (Op.getNumOperands() == 4)
16213 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16215 RoundingMode = Op.getOperand(4);
16216 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16217 if (IntrWithRoundingModeOpcode != 0)
16218 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16219 X86::STATIC_ROUNDING::CUR_DIRECTION)
16220 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16221 dl, Op.getValueType(), Src, RoundingMode),
16222 Mask, PassThru, Subtarget, DAG);
16223 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16225 Mask, PassThru, Subtarget, DAG);
16227 case INTR_TYPE_1OP_MASK: {
16228 SDValue Src = Op.getOperand(1);
16229 SDValue PassThru = Op.getOperand(2);
16230 SDValue Mask = Op.getOperand(3);
16231 // We add rounding mode to the Node when
16232 // - RM Opcode is specified and
16233 // - RM is not "current direction".
16234 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16235 if (IntrWithRoundingModeOpcode != 0) {
16236 SDValue Rnd = Op.getOperand(4);
16237 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16238 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16239 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16240 dl, Op.getValueType(),
16242 Mask, PassThru, Subtarget, DAG);
16245 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16246 Mask, PassThru, Subtarget, DAG);
16248 case INTR_TYPE_SCALAR_MASK: {
16249 SDValue Src1 = Op.getOperand(1);
16250 SDValue Src2 = Op.getOperand(2);
16251 SDValue passThru = Op.getOperand(3);
16252 SDValue Mask = Op.getOperand(4);
16253 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16254 Mask, passThru, Subtarget, DAG);
16256 case INTR_TYPE_SCALAR_MASK_RM: {
16257 SDValue Src1 = Op.getOperand(1);
16258 SDValue Src2 = Op.getOperand(2);
16259 SDValue Src0 = Op.getOperand(3);
16260 SDValue Mask = Op.getOperand(4);
16261 // There are 2 kinds of intrinsics in this group:
16262 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16263 // (2) With rounding mode and sae - 7 operands.
16264 if (Op.getNumOperands() == 6) {
16265 SDValue Sae = Op.getOperand(5);
16266 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16267 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16269 Mask, Src0, Subtarget, DAG);
16271 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16272 SDValue RoundingMode = Op.getOperand(5);
16273 SDValue Sae = Op.getOperand(6);
16274 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16275 RoundingMode, Sae),
16276 Mask, Src0, Subtarget, DAG);
16278 case INTR_TYPE_2OP_MASK:
16279 case INTR_TYPE_2OP_IMM8_MASK: {
16280 SDValue Src1 = Op.getOperand(1);
16281 SDValue Src2 = Op.getOperand(2);
16282 SDValue PassThru = Op.getOperand(3);
16283 SDValue Mask = Op.getOperand(4);
16285 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16286 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16288 // We specify 2 possible opcodes for intrinsics with rounding modes.
16289 // First, we check if the intrinsic may have non-default rounding mode,
16290 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16291 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16292 if (IntrWithRoundingModeOpcode != 0) {
16293 SDValue Rnd = Op.getOperand(5);
16294 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16295 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16296 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16297 dl, Op.getValueType(),
16299 Mask, PassThru, Subtarget, DAG);
16302 // TODO: Intrinsics should have fast-math-flags to propagate.
16303 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16304 Mask, PassThru, Subtarget, DAG);
16306 case INTR_TYPE_2OP_MASK_RM: {
16307 SDValue Src1 = Op.getOperand(1);
16308 SDValue Src2 = Op.getOperand(2);
16309 SDValue PassThru = Op.getOperand(3);
16310 SDValue Mask = Op.getOperand(4);
16311 // We specify 2 possible modes for intrinsics, with/without rounding
16313 // First, we check if the intrinsic have rounding mode (6 operands),
16314 // if not, we set rounding mode to "current".
16316 if (Op.getNumOperands() == 6)
16317 Rnd = Op.getOperand(5);
16319 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16320 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16322 Mask, PassThru, Subtarget, DAG);
16324 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16325 SDValue Src1 = Op.getOperand(1);
16326 SDValue Src2 = Op.getOperand(2);
16327 SDValue Src3 = Op.getOperand(3);
16328 SDValue PassThru = Op.getOperand(4);
16329 SDValue Mask = Op.getOperand(5);
16330 SDValue Sae = Op.getOperand(6);
16332 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16334 Mask, PassThru, Subtarget, DAG);
16336 case INTR_TYPE_3OP_MASK_RM: {
16337 SDValue Src1 = Op.getOperand(1);
16338 SDValue Src2 = Op.getOperand(2);
16339 SDValue Imm = Op.getOperand(3);
16340 SDValue PassThru = Op.getOperand(4);
16341 SDValue Mask = Op.getOperand(5);
16342 // We specify 2 possible modes for intrinsics, with/without rounding
16344 // First, we check if the intrinsic have rounding mode (7 operands),
16345 // if not, we set rounding mode to "current".
16347 if (Op.getNumOperands() == 7)
16348 Rnd = Op.getOperand(6);
16350 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16351 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16352 Src1, Src2, Imm, Rnd),
16353 Mask, PassThru, Subtarget, DAG);
16355 case INTR_TYPE_3OP_IMM8_MASK:
16356 case INTR_TYPE_3OP_MASK:
16357 case INSERT_SUBVEC: {
16358 SDValue Src1 = Op.getOperand(1);
16359 SDValue Src2 = Op.getOperand(2);
16360 SDValue Src3 = Op.getOperand(3);
16361 SDValue PassThru = Op.getOperand(4);
16362 SDValue Mask = Op.getOperand(5);
16364 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16365 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16366 else if (IntrData->Type == INSERT_SUBVEC) {
16367 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16368 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16369 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16370 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16371 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16374 // We specify 2 possible opcodes for intrinsics with rounding modes.
16375 // First, we check if the intrinsic may have non-default rounding mode,
16376 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16377 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16378 if (IntrWithRoundingModeOpcode != 0) {
16379 SDValue Rnd = Op.getOperand(6);
16380 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16381 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16382 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16383 dl, Op.getValueType(),
16384 Src1, Src2, Src3, Rnd),
16385 Mask, PassThru, Subtarget, DAG);
16388 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16390 Mask, PassThru, Subtarget, DAG);
16392 case VPERM_3OP_MASKZ:
16393 case VPERM_3OP_MASK:{
16394 // Src2 is the PassThru
16395 SDValue Src1 = Op.getOperand(1);
16396 SDValue Src2 = Op.getOperand(2);
16397 SDValue Src3 = Op.getOperand(3);
16398 SDValue Mask = Op.getOperand(4);
16399 MVT VT = Op.getSimpleValueType();
16400 SDValue PassThru = SDValue();
16402 // set PassThru element
16403 if (IntrData->Type == VPERM_3OP_MASKZ)
16404 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16406 PassThru = DAG.getBitcast(VT, Src2);
16408 // Swap Src1 and Src2 in the node creation
16409 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16410 dl, Op.getValueType(),
16412 Mask, PassThru, Subtarget, DAG);
16416 case FMA_OP_MASK: {
16417 SDValue Src1 = Op.getOperand(1);
16418 SDValue Src2 = Op.getOperand(2);
16419 SDValue Src3 = Op.getOperand(3);
16420 SDValue Mask = Op.getOperand(4);
16421 MVT VT = Op.getSimpleValueType();
16422 SDValue PassThru = SDValue();
16424 // set PassThru element
16425 if (IntrData->Type == FMA_OP_MASKZ)
16426 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16427 else if (IntrData->Type == FMA_OP_MASK3)
16432 // We specify 2 possible opcodes for intrinsics with rounding modes.
16433 // First, we check if the intrinsic may have non-default rounding mode,
16434 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16435 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16436 if (IntrWithRoundingModeOpcode != 0) {
16437 SDValue Rnd = Op.getOperand(5);
16438 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16439 X86::STATIC_ROUNDING::CUR_DIRECTION)
16440 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16441 dl, Op.getValueType(),
16442 Src1, Src2, Src3, Rnd),
16443 Mask, PassThru, Subtarget, DAG);
16445 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16446 dl, Op.getValueType(),
16448 Mask, PassThru, Subtarget, DAG);
16450 case TERLOG_OP_MASK:
16451 case TERLOG_OP_MASKZ: {
16452 SDValue Src1 = Op.getOperand(1);
16453 SDValue Src2 = Op.getOperand(2);
16454 SDValue Src3 = Op.getOperand(3);
16455 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16456 SDValue Mask = Op.getOperand(5);
16457 MVT VT = Op.getSimpleValueType();
16458 SDValue PassThru = Src1;
16459 // Set PassThru element.
16460 if (IntrData->Type == TERLOG_OP_MASKZ)
16461 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16463 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16464 Src1, Src2, Src3, Src4),
16465 Mask, PassThru, Subtarget, DAG);
16468 // FPclass intrinsics with mask
16469 SDValue Src1 = Op.getOperand(1);
16470 MVT VT = Src1.getSimpleValueType();
16471 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16472 SDValue Imm = Op.getOperand(2);
16473 SDValue Mask = Op.getOperand(3);
16474 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16475 Mask.getSimpleValueType().getSizeInBits());
16476 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16477 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16478 DAG.getTargetConstant(0, dl, MaskVT),
16480 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16481 DAG.getUNDEF(BitcastVT), FPclassMask,
16482 DAG.getIntPtrConstant(0, dl));
16483 return DAG.getBitcast(Op.getValueType(), Res);
16486 SDValue Src1 = Op.getOperand(1);
16487 SDValue Imm = Op.getOperand(2);
16488 SDValue Mask = Op.getOperand(3);
16489 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16490 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16491 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16492 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16495 case CMP_MASK_CC: {
16496 // Comparison intrinsics with masks.
16497 // Example of transformation:
16498 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16499 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16501 // (v8i1 (insert_subvector undef,
16502 // (v2i1 (and (PCMPEQM %a, %b),
16503 // (extract_subvector
16504 // (v8i1 (bitcast %mask)), 0))), 0))))
16505 MVT VT = Op.getOperand(1).getSimpleValueType();
16506 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16507 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16508 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16509 Mask.getSimpleValueType().getSizeInBits());
16511 if (IntrData->Type == CMP_MASK_CC) {
16512 SDValue CC = Op.getOperand(3);
16513 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16514 // We specify 2 possible opcodes for intrinsics with rounding modes.
16515 // First, we check if the intrinsic may have non-default rounding mode,
16516 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16517 if (IntrData->Opc1 != 0) {
16518 SDValue Rnd = Op.getOperand(5);
16519 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16520 X86::STATIC_ROUNDING::CUR_DIRECTION)
16521 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16522 Op.getOperand(2), CC, Rnd);
16524 //default rounding mode
16526 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16527 Op.getOperand(2), CC);
16530 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16531 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16534 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16535 DAG.getTargetConstant(0, dl,
16538 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16539 DAG.getUNDEF(BitcastVT), CmpMask,
16540 DAG.getIntPtrConstant(0, dl));
16541 return DAG.getBitcast(Op.getValueType(), Res);
16543 case CMP_MASK_SCALAR_CC: {
16544 SDValue Src1 = Op.getOperand(1);
16545 SDValue Src2 = Op.getOperand(2);
16546 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16547 SDValue Mask = Op.getOperand(4);
16550 if (IntrData->Opc1 != 0) {
16551 SDValue Rnd = Op.getOperand(5);
16552 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16553 X86::STATIC_ROUNDING::CUR_DIRECTION)
16554 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16556 //default rounding mode
16558 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16560 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16561 DAG.getTargetConstant(0, dl,
16565 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16566 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16567 DAG.getValueType(MVT::i1));
16569 case COMI: { // Comparison intrinsics
16570 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16571 SDValue LHS = Op.getOperand(1);
16572 SDValue RHS = Op.getOperand(2);
16573 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16574 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16575 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16576 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16577 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16578 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16580 case COMI_RM: { // Comparison intrinsics with Sae
16581 SDValue LHS = Op.getOperand(1);
16582 SDValue RHS = Op.getOperand(2);
16583 SDValue CC = Op.getOperand(3);
16584 SDValue Sae = Op.getOperand(4);
16585 auto ComiType = TranslateX86ConstCondToX86CC(CC);
16586 // choose between ordered and unordered (comi/ucomi)
16587 unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;
16589 if (cast<ConstantSDNode>(Sae)->getZExtValue() !=
16590 X86::STATIC_ROUNDING::CUR_DIRECTION)
16591 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);
16593 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);
16594 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16595 DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);
16596 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16599 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16600 Op.getOperand(1), Op.getOperand(2), DAG);
16602 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16603 Op.getSimpleValueType(),
16605 Op.getOperand(2), DAG),
16606 Op.getOperand(4), Op.getOperand(3), Subtarget,
16608 case COMPRESS_EXPAND_IN_REG: {
16609 SDValue Mask = Op.getOperand(3);
16610 SDValue DataToCompress = Op.getOperand(1);
16611 SDValue PassThru = Op.getOperand(2);
16612 if (isAllOnesConstant(Mask)) // return data as is
16613 return Op.getOperand(1);
16615 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16617 Mask, PassThru, Subtarget, DAG);
16620 SDValue Mask = Op.getOperand(1);
16621 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16622 Mask = DAG.getBitcast(MaskVT, Mask);
16623 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16626 SDValue Mask = Op.getOperand(3);
16627 MVT VT = Op.getSimpleValueType();
16628 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16629 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16630 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16634 MVT VT = Op.getSimpleValueType();
16635 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits()/2);
16637 SDValue Src1 = getMaskNode(Op.getOperand(1), MaskVT, Subtarget, DAG, dl);
16638 SDValue Src2 = getMaskNode(Op.getOperand(2), MaskVT, Subtarget, DAG, dl);
16639 // Arguments should be swapped.
16640 SDValue Res = DAG.getNode(IntrData->Opc0, dl,
16641 MVT::getVectorVT(MVT::i1, VT.getSizeInBits()),
16643 return DAG.getBitcast(VT, Res);
16651 default: return SDValue(); // Don't custom lower most intrinsics.
16653 case Intrinsic::x86_avx2_permd:
16654 case Intrinsic::x86_avx2_permps:
16655 // Operands intentionally swapped. Mask is last operand to intrinsic,
16656 // but second operand for node/instruction.
16657 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16658 Op.getOperand(2), Op.getOperand(1));
16660 // ptest and testp intrinsics. The intrinsic these come from are designed to
16661 // return an integer value, not just an instruction so lower it to the ptest
16662 // or testp pattern and a setcc for the result.
16663 case Intrinsic::x86_sse41_ptestz:
16664 case Intrinsic::x86_sse41_ptestc:
16665 case Intrinsic::x86_sse41_ptestnzc:
16666 case Intrinsic::x86_avx_ptestz_256:
16667 case Intrinsic::x86_avx_ptestc_256:
16668 case Intrinsic::x86_avx_ptestnzc_256:
16669 case Intrinsic::x86_avx_vtestz_ps:
16670 case Intrinsic::x86_avx_vtestc_ps:
16671 case Intrinsic::x86_avx_vtestnzc_ps:
16672 case Intrinsic::x86_avx_vtestz_pd:
16673 case Intrinsic::x86_avx_vtestc_pd:
16674 case Intrinsic::x86_avx_vtestnzc_pd:
16675 case Intrinsic::x86_avx_vtestz_ps_256:
16676 case Intrinsic::x86_avx_vtestc_ps_256:
16677 case Intrinsic::x86_avx_vtestnzc_ps_256:
16678 case Intrinsic::x86_avx_vtestz_pd_256:
16679 case Intrinsic::x86_avx_vtestc_pd_256:
16680 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16681 bool IsTestPacked = false;
16684 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16685 case Intrinsic::x86_avx_vtestz_ps:
16686 case Intrinsic::x86_avx_vtestz_pd:
16687 case Intrinsic::x86_avx_vtestz_ps_256:
16688 case Intrinsic::x86_avx_vtestz_pd_256:
16689 IsTestPacked = true; // Fallthrough
16690 case Intrinsic::x86_sse41_ptestz:
16691 case Intrinsic::x86_avx_ptestz_256:
16693 X86CC = X86::COND_E;
16695 case Intrinsic::x86_avx_vtestc_ps:
16696 case Intrinsic::x86_avx_vtestc_pd:
16697 case Intrinsic::x86_avx_vtestc_ps_256:
16698 case Intrinsic::x86_avx_vtestc_pd_256:
16699 IsTestPacked = true; // Fallthrough
16700 case Intrinsic::x86_sse41_ptestc:
16701 case Intrinsic::x86_avx_ptestc_256:
16703 X86CC = X86::COND_B;
16705 case Intrinsic::x86_avx_vtestnzc_ps:
16706 case Intrinsic::x86_avx_vtestnzc_pd:
16707 case Intrinsic::x86_avx_vtestnzc_ps_256:
16708 case Intrinsic::x86_avx_vtestnzc_pd_256:
16709 IsTestPacked = true; // Fallthrough
16710 case Intrinsic::x86_sse41_ptestnzc:
16711 case Intrinsic::x86_avx_ptestnzc_256:
16713 X86CC = X86::COND_A;
16717 SDValue LHS = Op.getOperand(1);
16718 SDValue RHS = Op.getOperand(2);
16719 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16720 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16721 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16722 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16723 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16725 case Intrinsic::x86_avx512_kortestz_w:
16726 case Intrinsic::x86_avx512_kortestc_w: {
16727 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16728 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16729 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16730 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16731 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16732 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16733 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16736 case Intrinsic::x86_sse42_pcmpistria128:
16737 case Intrinsic::x86_sse42_pcmpestria128:
16738 case Intrinsic::x86_sse42_pcmpistric128:
16739 case Intrinsic::x86_sse42_pcmpestric128:
16740 case Intrinsic::x86_sse42_pcmpistrio128:
16741 case Intrinsic::x86_sse42_pcmpestrio128:
16742 case Intrinsic::x86_sse42_pcmpistris128:
16743 case Intrinsic::x86_sse42_pcmpestris128:
16744 case Intrinsic::x86_sse42_pcmpistriz128:
16745 case Intrinsic::x86_sse42_pcmpestriz128: {
16749 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16750 case Intrinsic::x86_sse42_pcmpistria128:
16751 Opcode = X86ISD::PCMPISTRI;
16752 X86CC = X86::COND_A;
16754 case Intrinsic::x86_sse42_pcmpestria128:
16755 Opcode = X86ISD::PCMPESTRI;
16756 X86CC = X86::COND_A;
16758 case Intrinsic::x86_sse42_pcmpistric128:
16759 Opcode = X86ISD::PCMPISTRI;
16760 X86CC = X86::COND_B;
16762 case Intrinsic::x86_sse42_pcmpestric128:
16763 Opcode = X86ISD::PCMPESTRI;
16764 X86CC = X86::COND_B;
16766 case Intrinsic::x86_sse42_pcmpistrio128:
16767 Opcode = X86ISD::PCMPISTRI;
16768 X86CC = X86::COND_O;
16770 case Intrinsic::x86_sse42_pcmpestrio128:
16771 Opcode = X86ISD::PCMPESTRI;
16772 X86CC = X86::COND_O;
16774 case Intrinsic::x86_sse42_pcmpistris128:
16775 Opcode = X86ISD::PCMPISTRI;
16776 X86CC = X86::COND_S;
16778 case Intrinsic::x86_sse42_pcmpestris128:
16779 Opcode = X86ISD::PCMPESTRI;
16780 X86CC = X86::COND_S;
16782 case Intrinsic::x86_sse42_pcmpistriz128:
16783 Opcode = X86ISD::PCMPISTRI;
16784 X86CC = X86::COND_E;
16786 case Intrinsic::x86_sse42_pcmpestriz128:
16787 Opcode = X86ISD::PCMPESTRI;
16788 X86CC = X86::COND_E;
16791 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16792 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16793 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16794 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16795 DAG.getConstant(X86CC, dl, MVT::i8),
16796 SDValue(PCMP.getNode(), 1));
16797 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16800 case Intrinsic::x86_sse42_pcmpistri128:
16801 case Intrinsic::x86_sse42_pcmpestri128: {
16803 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16804 Opcode = X86ISD::PCMPISTRI;
16806 Opcode = X86ISD::PCMPESTRI;
16808 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16809 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16810 return DAG.getNode(Opcode, dl, VTs, NewOps);
16813 case Intrinsic::x86_seh_lsda: {
16814 // Compute the symbol for the LSDA. We know it'll get emitted later.
16815 MachineFunction &MF = DAG.getMachineFunction();
16816 SDValue Op1 = Op.getOperand(1);
16817 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16818 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16819 GlobalValue::getRealLinkageName(Fn->getName()));
16821 // Generate a simple absolute symbol reference. This intrinsic is only
16822 // supported on 32-bit Windows, which isn't PIC.
16823 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16824 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16827 case Intrinsic::x86_seh_recoverfp: {
16828 SDValue FnOp = Op.getOperand(1);
16829 SDValue IncomingFPOp = Op.getOperand(2);
16830 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16831 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16833 report_fatal_error(
16834 "llvm.x86.seh.recoverfp must take a function as the first argument");
16835 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16838 case Intrinsic::localaddress: {
16839 // Returns one of the stack, base, or frame pointer registers, depending on
16840 // which is used to reference local variables.
16841 MachineFunction &MF = DAG.getMachineFunction();
16842 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16844 if (RegInfo->hasBasePointer(MF))
16845 Reg = RegInfo->getBaseRegister();
16846 else // This function handles the SP or FP case.
16847 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16848 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16853 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16854 SDValue Src, SDValue Mask, SDValue Base,
16855 SDValue Index, SDValue ScaleOp, SDValue Chain,
16856 const X86Subtarget * Subtarget) {
16858 auto *C = cast<ConstantSDNode>(ScaleOp);
16859 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16860 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16861 Index.getSimpleValueType().getVectorNumElements());
16863 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16865 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16867 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16868 Mask.getSimpleValueType().getSizeInBits());
16870 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16871 // are extracted by EXTRACT_SUBVECTOR.
16872 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16873 DAG.getBitcast(BitcastVT, Mask),
16874 DAG.getIntPtrConstant(0, dl));
16876 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16877 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16878 SDValue Segment = DAG.getRegister(0, MVT::i32);
16879 if (Src.getOpcode() == ISD::UNDEF)
16880 Src = getZeroVector(Op.getSimpleValueType(), Subtarget, DAG, dl);
16881 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16882 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16883 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16884 return DAG.getMergeValues(RetOps, dl);
16887 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16888 SDValue Src, SDValue Mask, SDValue Base,
16889 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16891 auto *C = cast<ConstantSDNode>(ScaleOp);
16892 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16893 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16894 SDValue Segment = DAG.getRegister(0, MVT::i32);
16895 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16896 Index.getSimpleValueType().getVectorNumElements());
16898 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16900 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16902 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16903 Mask.getSimpleValueType().getSizeInBits());
16905 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16906 // are extracted by EXTRACT_SUBVECTOR.
16907 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16908 DAG.getBitcast(BitcastVT, Mask),
16909 DAG.getIntPtrConstant(0, dl));
16911 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16912 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16913 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16914 return SDValue(Res, 1);
16917 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16918 SDValue Mask, SDValue Base, SDValue Index,
16919 SDValue ScaleOp, SDValue Chain) {
16921 auto *C = cast<ConstantSDNode>(ScaleOp);
16922 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16923 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16924 SDValue Segment = DAG.getRegister(0, MVT::i32);
16926 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16928 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16930 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16932 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16933 //SDVTList VTs = DAG.getVTList(MVT::Other);
16934 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16935 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16936 return SDValue(Res, 0);
16939 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16940 // read performance monitor counters (x86_rdpmc).
16941 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16942 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16943 SmallVectorImpl<SDValue> &Results) {
16944 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16945 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16948 // The ECX register is used to select the index of the performance counter
16950 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16952 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16954 // Reads the content of a 64-bit performance counter and returns it in the
16955 // registers EDX:EAX.
16956 if (Subtarget->is64Bit()) {
16957 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16958 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16961 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16962 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16965 Chain = HI.getValue(1);
16967 if (Subtarget->is64Bit()) {
16968 // The EAX register is loaded with the low-order 32 bits. The EDX register
16969 // is loaded with the supported high-order bits of the counter.
16970 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16971 DAG.getConstant(32, DL, MVT::i8));
16972 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16973 Results.push_back(Chain);
16977 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16978 SDValue Ops[] = { LO, HI };
16979 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16980 Results.push_back(Pair);
16981 Results.push_back(Chain);
16984 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16985 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16986 // also used to custom lower READCYCLECOUNTER nodes.
16987 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16988 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16989 SmallVectorImpl<SDValue> &Results) {
16990 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16991 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16994 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16995 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16996 // and the EAX register is loaded with the low-order 32 bits.
16997 if (Subtarget->is64Bit()) {
16998 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16999 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17002 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17003 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17006 SDValue Chain = HI.getValue(1);
17008 if (Opcode == X86ISD::RDTSCP_DAG) {
17009 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17011 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17012 // the ECX register. Add 'ecx' explicitly to the chain.
17013 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17015 // Explicitly store the content of ECX at the location passed in input
17016 // to the 'rdtscp' intrinsic.
17017 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17018 MachinePointerInfo(), false, false, 0);
17021 if (Subtarget->is64Bit()) {
17022 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17023 // the EAX register is loaded with the low-order 32 bits.
17024 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17025 DAG.getConstant(32, DL, MVT::i8));
17026 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17027 Results.push_back(Chain);
17031 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17032 SDValue Ops[] = { LO, HI };
17033 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17034 Results.push_back(Pair);
17035 Results.push_back(Chain);
17038 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17039 SelectionDAG &DAG) {
17040 SmallVector<SDValue, 2> Results;
17042 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17044 return DAG.getMergeValues(Results, DL);
17047 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
17048 SelectionDAG &DAG) {
17049 MachineFunction &MF = DAG.getMachineFunction();
17050 const Function *Fn = MF.getFunction();
17052 SDValue Chain = Op.getOperand(0);
17054 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
17055 "using llvm.x86.seh.restoreframe requires a frame pointer");
17057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17058 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
17060 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17061 unsigned FrameReg =
17062 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17063 unsigned SPReg = RegInfo->getStackRegister();
17064 unsigned SlotSize = RegInfo->getSlotSize();
17066 // Get incoming EBP.
17067 SDValue IncomingEBP =
17068 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
17070 // SP is saved in the first field of every registration node, so load
17071 // [EBP-RegNodeSize] into SP.
17072 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
17073 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
17074 DAG.getConstant(-RegNodeSize, dl, VT));
17076 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
17077 false, VT.getScalarSizeInBits() / 8);
17078 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
17080 if (!RegInfo->needsStackRealignment(MF)) {
17081 // Adjust EBP to point back to the original frame position.
17082 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
17083 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
17085 assert(RegInfo->hasBasePointer(MF) &&
17086 "functions with Win32 EH must use frame or base pointer register");
17088 // Reload the base pointer (ESI) with the adjusted incoming EBP.
17089 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
17090 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
17092 // Reload the spilled EBP value, now that the stack and base pointers are
17094 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
17095 X86FI->setHasSEHFramePtrSave(true);
17096 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
17097 X86FI->setSEHFramePtrSaveIndex(FI);
17098 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
17099 MachinePointerInfo(), false, false, false,
17100 VT.getScalarSizeInBits() / 8);
17101 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
17107 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17108 MachineFunction &MF = DAG.getMachineFunction();
17109 SDValue Chain = Op.getOperand(0);
17110 SDValue RegNode = Op.getOperand(2);
17111 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17113 report_fatal_error("EH registrations only live in functions using WinEH");
17115 // Cast the operand to an alloca, and remember the frame index.
17116 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17118 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17119 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17121 // Return the chain operand without making any DAG nodes.
17125 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17126 /// return truncate Store/MaskedStore Node
17127 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17131 SDValue Mask = Op.getOperand(4);
17132 SDValue DataToTruncate = Op.getOperand(3);
17133 SDValue Addr = Op.getOperand(2);
17134 SDValue Chain = Op.getOperand(0);
17136 MVT VT = DataToTruncate.getSimpleValueType();
17137 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17139 if (isAllOnesConstant(Mask)) // return just a truncate store
17140 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17141 MachinePointerInfo(), SVT, false, false,
17142 SVT.getScalarSizeInBits()/8);
17144 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17145 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17146 Mask.getSimpleValueType().getSizeInBits());
17147 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17148 // are extracted by EXTRACT_SUBVECTOR.
17149 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17150 DAG.getBitcast(BitcastVT, Mask),
17151 DAG.getIntPtrConstant(0, dl));
17153 MachineMemOperand *MMO = DAG.getMachineFunction().
17154 getMachineMemOperand(MachinePointerInfo(),
17155 MachineMemOperand::MOStore, SVT.getStoreSize(),
17156 SVT.getScalarSizeInBits()/8);
17158 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17159 VMask, SVT, MMO, true);
17162 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17163 SelectionDAG &DAG) {
17164 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17166 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17168 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17169 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17170 else if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17171 return MarkEHRegistrationNode(Op, DAG);
17176 switch(IntrData->Type) {
17177 default: llvm_unreachable("Unknown Intrinsic Type");
17180 // Emit the node with the right value type.
17181 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17182 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17184 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17185 // Otherwise return the value from Rand, which is always 0, casted to i32.
17186 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17187 DAG.getConstant(1, dl, Op->getValueType(1)),
17188 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17189 SDValue(Result.getNode(), 1) };
17190 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17191 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17194 // Return { result, isValid, chain }.
17195 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17196 SDValue(Result.getNode(), 2));
17199 //gather(v1, mask, index, base, scale);
17200 SDValue Chain = Op.getOperand(0);
17201 SDValue Src = Op.getOperand(2);
17202 SDValue Base = Op.getOperand(3);
17203 SDValue Index = Op.getOperand(4);
17204 SDValue Mask = Op.getOperand(5);
17205 SDValue Scale = Op.getOperand(6);
17206 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17210 //scatter(base, mask, index, v1, scale);
17211 SDValue Chain = Op.getOperand(0);
17212 SDValue Base = Op.getOperand(2);
17213 SDValue Mask = Op.getOperand(3);
17214 SDValue Index = Op.getOperand(4);
17215 SDValue Src = Op.getOperand(5);
17216 SDValue Scale = Op.getOperand(6);
17217 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17221 SDValue Hint = Op.getOperand(6);
17222 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17223 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17224 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17225 SDValue Chain = Op.getOperand(0);
17226 SDValue Mask = Op.getOperand(2);
17227 SDValue Index = Op.getOperand(3);
17228 SDValue Base = Op.getOperand(4);
17229 SDValue Scale = Op.getOperand(5);
17230 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17232 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17234 SmallVector<SDValue, 2> Results;
17235 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17237 return DAG.getMergeValues(Results, dl);
17239 // Read Performance Monitoring Counters.
17241 SmallVector<SDValue, 2> Results;
17242 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17243 return DAG.getMergeValues(Results, dl);
17245 // XTEST intrinsics.
17247 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17248 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17249 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17250 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17252 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17253 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17254 Ret, SDValue(InTrans.getNode(), 1));
17258 SmallVector<SDValue, 2> Results;
17259 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17260 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17261 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17262 DAG.getConstant(-1, dl, MVT::i8));
17263 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17264 Op.getOperand(4), GenCF.getValue(1));
17265 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17266 Op.getOperand(5), MachinePointerInfo(),
17268 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17269 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17271 Results.push_back(SetCC);
17272 Results.push_back(Store);
17273 return DAG.getMergeValues(Results, dl);
17275 case COMPRESS_TO_MEM: {
17277 SDValue Mask = Op.getOperand(4);
17278 SDValue DataToCompress = Op.getOperand(3);
17279 SDValue Addr = Op.getOperand(2);
17280 SDValue Chain = Op.getOperand(0);
17282 MVT VT = DataToCompress.getSimpleValueType();
17283 if (isAllOnesConstant(Mask)) // return just a store
17284 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17285 MachinePointerInfo(), false, false,
17286 VT.getScalarSizeInBits()/8);
17288 SDValue Compressed =
17289 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17290 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17291 return DAG.getStore(Chain, dl, Compressed, Addr,
17292 MachinePointerInfo(), false, false,
17293 VT.getScalarSizeInBits()/8);
17295 case TRUNCATE_TO_MEM_VI8:
17296 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17297 case TRUNCATE_TO_MEM_VI16:
17298 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17299 case TRUNCATE_TO_MEM_VI32:
17300 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17301 case EXPAND_FROM_MEM: {
17303 SDValue Mask = Op.getOperand(4);
17304 SDValue PassThru = Op.getOperand(3);
17305 SDValue Addr = Op.getOperand(2);
17306 SDValue Chain = Op.getOperand(0);
17307 MVT VT = Op.getSimpleValueType();
17309 if (isAllOnesConstant(Mask)) // return just a load
17310 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17311 false, VT.getScalarSizeInBits()/8);
17313 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17314 false, false, false,
17315 VT.getScalarSizeInBits()/8);
17317 SDValue Results[] = {
17318 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17319 Mask, PassThru, Subtarget, DAG), Chain};
17320 return DAG.getMergeValues(Results, dl);
17325 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17326 SelectionDAG &DAG) const {
17327 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17328 MFI->setReturnAddressIsTaken(true);
17330 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17333 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17335 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17338 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17339 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17340 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17341 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17342 DAG.getNode(ISD::ADD, dl, PtrVT,
17343 FrameAddr, Offset),
17344 MachinePointerInfo(), false, false, false, 0);
17347 // Just load the return address.
17348 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17349 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17350 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17353 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17354 MachineFunction &MF = DAG.getMachineFunction();
17355 MachineFrameInfo *MFI = MF.getFrameInfo();
17356 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17357 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17358 EVT VT = Op.getValueType();
17360 MFI->setFrameAddressIsTaken(true);
17362 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17363 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17364 // is not possible to crawl up the stack without looking at the unwind codes
17366 int FrameAddrIndex = FuncInfo->getFAIndex();
17367 if (!FrameAddrIndex) {
17368 // Set up a frame object for the return address.
17369 unsigned SlotSize = RegInfo->getSlotSize();
17370 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17371 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17372 FuncInfo->setFAIndex(FrameAddrIndex);
17374 return DAG.getFrameIndex(FrameAddrIndex, VT);
17377 unsigned FrameReg =
17378 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17379 SDLoc dl(Op); // FIXME probably not meaningful
17380 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17381 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17382 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17383 "Invalid Frame Register!");
17384 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17386 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17387 MachinePointerInfo(),
17388 false, false, false, 0);
17392 // FIXME? Maybe this could be a TableGen attribute on some registers and
17393 // this table could be generated automatically from RegInfo.
17394 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17395 SelectionDAG &DAG) const {
17396 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17397 const MachineFunction &MF = DAG.getMachineFunction();
17399 unsigned Reg = StringSwitch<unsigned>(RegName)
17400 .Case("esp", X86::ESP)
17401 .Case("rsp", X86::RSP)
17402 .Case("ebp", X86::EBP)
17403 .Case("rbp", X86::RBP)
17406 if (Reg == X86::EBP || Reg == X86::RBP) {
17407 if (!TFI.hasFP(MF))
17408 report_fatal_error("register " + StringRef(RegName) +
17409 " is allocatable: function has no frame pointer");
17412 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17413 unsigned FrameReg =
17414 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17415 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17416 "Invalid Frame Register!");
17424 report_fatal_error("Invalid register name global variable");
17427 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17428 SelectionDAG &DAG) const {
17429 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17430 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17433 unsigned X86TargetLowering::getExceptionPointerRegister(
17434 const Constant *PersonalityFn) const {
17435 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17436 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17438 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17441 unsigned X86TargetLowering::getExceptionSelectorRegister(
17442 const Constant *PersonalityFn) const {
17443 // Funclet personalities don't use selectors (the runtime does the selection).
17444 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17445 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17448 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17449 SDValue Chain = Op.getOperand(0);
17450 SDValue Offset = Op.getOperand(1);
17451 SDValue Handler = Op.getOperand(2);
17454 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17455 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17456 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17457 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17458 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17459 "Invalid Frame Register!");
17460 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17461 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17463 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17464 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17466 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17467 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17469 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17471 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17472 DAG.getRegister(StoreAddrReg, PtrVT));
17475 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17476 SelectionDAG &DAG) const {
17478 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17479 DAG.getVTList(MVT::i32, MVT::Other),
17480 Op.getOperand(0), Op.getOperand(1));
17483 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17484 SelectionDAG &DAG) const {
17486 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17487 Op.getOperand(0), Op.getOperand(1));
17490 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17491 return Op.getOperand(0);
17494 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17495 SelectionDAG &DAG) const {
17496 SDValue Root = Op.getOperand(0);
17497 SDValue Trmp = Op.getOperand(1); // trampoline
17498 SDValue FPtr = Op.getOperand(2); // nested function
17499 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17502 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17503 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17505 if (Subtarget->is64Bit()) {
17506 SDValue OutChains[6];
17508 // Large code-model.
17509 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17510 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17512 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17513 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17515 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17517 // Load the pointer to the nested function into R11.
17518 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17519 SDValue Addr = Trmp;
17520 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17521 Addr, MachinePointerInfo(TrmpAddr),
17524 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17525 DAG.getConstant(2, dl, MVT::i64));
17526 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17527 MachinePointerInfo(TrmpAddr, 2),
17530 // Load the 'nest' parameter value into R10.
17531 // R10 is specified in X86CallingConv.td
17532 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17533 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17534 DAG.getConstant(10, dl, MVT::i64));
17535 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17536 Addr, MachinePointerInfo(TrmpAddr, 10),
17539 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17540 DAG.getConstant(12, dl, MVT::i64));
17541 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17542 MachinePointerInfo(TrmpAddr, 12),
17545 // Jump to the nested function.
17546 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17547 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17548 DAG.getConstant(20, dl, MVT::i64));
17549 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17550 Addr, MachinePointerInfo(TrmpAddr, 20),
17553 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17554 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17555 DAG.getConstant(22, dl, MVT::i64));
17556 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17557 Addr, MachinePointerInfo(TrmpAddr, 22),
17560 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17562 const Function *Func =
17563 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17564 CallingConv::ID CC = Func->getCallingConv();
17569 llvm_unreachable("Unsupported calling convention");
17570 case CallingConv::C:
17571 case CallingConv::X86_StdCall: {
17572 // Pass 'nest' parameter in ECX.
17573 // Must be kept in sync with X86CallingConv.td
17574 NestReg = X86::ECX;
17576 // Check that ECX wasn't needed by an 'inreg' parameter.
17577 FunctionType *FTy = Func->getFunctionType();
17578 const AttributeSet &Attrs = Func->getAttributes();
17580 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17581 unsigned InRegCount = 0;
17584 for (FunctionType::param_iterator I = FTy->param_begin(),
17585 E = FTy->param_end(); I != E; ++I, ++Idx)
17586 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17587 auto &DL = DAG.getDataLayout();
17588 // FIXME: should only count parameters that are lowered to integers.
17589 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17592 if (InRegCount > 2) {
17593 report_fatal_error("Nest register in use - reduce number of inreg"
17599 case CallingConv::X86_FastCall:
17600 case CallingConv::X86_ThisCall:
17601 case CallingConv::Fast:
17602 // Pass 'nest' parameter in EAX.
17603 // Must be kept in sync with X86CallingConv.td
17604 NestReg = X86::EAX;
17608 SDValue OutChains[4];
17609 SDValue Addr, Disp;
17611 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17612 DAG.getConstant(10, dl, MVT::i32));
17613 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17615 // This is storing the opcode for MOV32ri.
17616 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17617 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17618 OutChains[0] = DAG.getStore(Root, dl,
17619 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17620 Trmp, MachinePointerInfo(TrmpAddr),
17623 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17624 DAG.getConstant(1, dl, MVT::i32));
17625 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17626 MachinePointerInfo(TrmpAddr, 1),
17629 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17630 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17631 DAG.getConstant(5, dl, MVT::i32));
17632 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17633 Addr, MachinePointerInfo(TrmpAddr, 5),
17636 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17637 DAG.getConstant(6, dl, MVT::i32));
17638 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17639 MachinePointerInfo(TrmpAddr, 6),
17642 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17646 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17647 SelectionDAG &DAG) const {
17649 The rounding mode is in bits 11:10 of FPSR, and has the following
17651 00 Round to nearest
17656 FLT_ROUNDS, on the other hand, expects the following:
17663 To perform the conversion, we do:
17664 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17667 MachineFunction &MF = DAG.getMachineFunction();
17668 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17669 unsigned StackAlignment = TFI.getStackAlignment();
17670 MVT VT = Op.getSimpleValueType();
17673 // Save FP Control Word to stack slot
17674 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17675 SDValue StackSlot =
17676 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17678 MachineMemOperand *MMO =
17679 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17680 MachineMemOperand::MOStore, 2, 2);
17682 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17683 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17684 DAG.getVTList(MVT::Other),
17685 Ops, MVT::i16, MMO);
17687 // Load FP Control Word from stack slot
17688 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17689 MachinePointerInfo(), false, false, false, 0);
17691 // Transform as necessary
17693 DAG.getNode(ISD::SRL, DL, MVT::i16,
17694 DAG.getNode(ISD::AND, DL, MVT::i16,
17695 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17696 DAG.getConstant(11, DL, MVT::i8));
17698 DAG.getNode(ISD::SRL, DL, MVT::i16,
17699 DAG.getNode(ISD::AND, DL, MVT::i16,
17700 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17701 DAG.getConstant(9, DL, MVT::i8));
17704 DAG.getNode(ISD::AND, DL, MVT::i16,
17705 DAG.getNode(ISD::ADD, DL, MVT::i16,
17706 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17707 DAG.getConstant(1, DL, MVT::i16)),
17708 DAG.getConstant(3, DL, MVT::i16));
17710 return DAG.getNode((VT.getSizeInBits() < 16 ?
17711 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17714 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17716 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17717 // to 512-bit vector.
17718 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17719 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17720 // split the vector, perform operation on it's Lo a Hi part and
17721 // concatenate the results.
17722 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17724 MVT VT = Op.getSimpleValueType();
17725 MVT EltVT = VT.getVectorElementType();
17726 unsigned NumElems = VT.getVectorNumElements();
17728 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17729 // Extend to 512 bit vector.
17730 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17731 "Unsupported value type for operation");
17733 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17734 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17735 DAG.getUNDEF(NewVT),
17737 DAG.getIntPtrConstant(0, dl));
17738 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17740 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17741 DAG.getIntPtrConstant(0, dl));
17744 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17745 "Unsupported element type");
17747 if (16 < NumElems) {
17748 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17750 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17751 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17753 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17754 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17756 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17759 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17761 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17762 "Unsupported value type for operation");
17764 // Use native supported vector instruction vplzcntd.
17765 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17766 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17767 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17768 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17770 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17773 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17774 SelectionDAG &DAG) {
17775 MVT VT = Op.getSimpleValueType();
17777 unsigned NumBits = VT.getSizeInBits();
17780 if (VT.isVector() && Subtarget->hasAVX512())
17781 return LowerVectorCTLZ_AVX512(Op, DAG);
17783 Op = Op.getOperand(0);
17784 if (VT == MVT::i8) {
17785 // Zero extend to i32 since there is not an i8 bsr.
17787 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17790 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17791 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17792 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17794 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17797 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17798 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17801 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17803 // Finally xor with NumBits-1.
17804 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17805 DAG.getConstant(NumBits - 1, dl, OpVT));
17808 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17812 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17813 SelectionDAG &DAG) {
17814 MVT VT = Op.getSimpleValueType();
17816 unsigned NumBits = VT.getSizeInBits();
17819 if (VT.isVector() && Subtarget->hasAVX512())
17820 return LowerVectorCTLZ_AVX512(Op, DAG);
17822 Op = Op.getOperand(0);
17823 if (VT == MVT::i8) {
17824 // Zero extend to i32 since there is not an i8 bsr.
17826 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17829 // Issue a bsr (scan bits in reverse).
17830 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17831 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17833 // And xor with NumBits-1.
17834 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17835 DAG.getConstant(NumBits - 1, dl, OpVT));
17838 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17842 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17843 MVT VT = Op.getSimpleValueType();
17844 unsigned NumBits = VT.getScalarSizeInBits();
17847 if (VT.isVector()) {
17848 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17850 SDValue N0 = Op.getOperand(0);
17851 SDValue Zero = DAG.getConstant(0, dl, VT);
17853 // lsb(x) = (x & -x)
17854 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17855 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17857 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17858 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17859 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17860 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17861 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17862 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17865 // cttz(x) = ctpop(lsb - 1)
17866 SDValue One = DAG.getConstant(1, dl, VT);
17867 return DAG.getNode(ISD::CTPOP, dl, VT,
17868 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17871 assert(Op.getOpcode() == ISD::CTTZ &&
17872 "Only scalar CTTZ requires custom lowering");
17874 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17875 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17876 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17878 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17881 DAG.getConstant(NumBits, dl, VT),
17882 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17885 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17888 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17889 // ones, and then concatenate the result back.
17890 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17891 MVT VT = Op.getSimpleValueType();
17893 assert(VT.is256BitVector() && VT.isInteger() &&
17894 "Unsupported value type for operation");
17896 unsigned NumElems = VT.getVectorNumElements();
17899 // Extract the LHS vectors
17900 SDValue LHS = Op.getOperand(0);
17901 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17902 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17904 // Extract the RHS vectors
17905 SDValue RHS = Op.getOperand(1);
17906 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17907 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17909 MVT EltVT = VT.getVectorElementType();
17910 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17912 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17913 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17914 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17917 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17918 if (Op.getValueType() == MVT::i1)
17919 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17920 Op.getOperand(0), Op.getOperand(1));
17921 assert(Op.getSimpleValueType().is256BitVector() &&
17922 Op.getSimpleValueType().isInteger() &&
17923 "Only handle AVX 256-bit vector integer operation");
17924 return Lower256IntArith(Op, DAG);
17927 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17928 if (Op.getValueType() == MVT::i1)
17929 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17930 Op.getOperand(0), Op.getOperand(1));
17931 assert(Op.getSimpleValueType().is256BitVector() &&
17932 Op.getSimpleValueType().isInteger() &&
17933 "Only handle AVX 256-bit vector integer operation");
17934 return Lower256IntArith(Op, DAG);
17937 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17938 assert(Op.getSimpleValueType().is256BitVector() &&
17939 Op.getSimpleValueType().isInteger() &&
17940 "Only handle AVX 256-bit vector integer operation");
17941 return Lower256IntArith(Op, DAG);
17944 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17945 SelectionDAG &DAG) {
17947 MVT VT = Op.getSimpleValueType();
17950 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17952 // Decompose 256-bit ops into smaller 128-bit ops.
17953 if (VT.is256BitVector() && !Subtarget->hasInt256())
17954 return Lower256IntArith(Op, DAG);
17956 SDValue A = Op.getOperand(0);
17957 SDValue B = Op.getOperand(1);
17959 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17960 // pairs, multiply and truncate.
17961 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17962 if (Subtarget->hasInt256()) {
17963 if (VT == MVT::v32i8) {
17964 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17965 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17966 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17967 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17968 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17969 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17970 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17971 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17972 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17973 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17976 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17977 return DAG.getNode(
17978 ISD::TRUNCATE, dl, VT,
17979 DAG.getNode(ISD::MUL, dl, ExVT,
17980 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17981 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17984 assert(VT == MVT::v16i8 &&
17985 "Pre-AVX2 support only supports v16i8 multiplication");
17986 MVT ExVT = MVT::v8i16;
17988 // Extract the lo parts and sign extend to i16
17990 if (Subtarget->hasSSE41()) {
17991 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17992 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17994 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17995 -1, 4, -1, 5, -1, 6, -1, 7};
17996 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17997 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17998 ALo = DAG.getBitcast(ExVT, ALo);
17999 BLo = DAG.getBitcast(ExVT, BLo);
18000 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
18001 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
18004 // Extract the hi parts and sign extend to i16
18006 if (Subtarget->hasSSE41()) {
18007 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
18008 -1, -1, -1, -1, -1, -1, -1, -1};
18009 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18010 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18011 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
18012 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
18014 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
18015 -1, 12, -1, 13, -1, 14, -1, 15};
18016 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18017 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18018 AHi = DAG.getBitcast(ExVT, AHi);
18019 BHi = DAG.getBitcast(ExVT, BHi);
18020 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
18021 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
18024 // Multiply, mask the lower 8bits of the lo/hi results and pack
18025 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
18026 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
18027 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
18028 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
18029 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18032 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18033 if (VT == MVT::v4i32) {
18034 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18035 "Should not custom lower when pmuldq is available!");
18037 // Extract the odd parts.
18038 static const int UnpackMask[] = { 1, -1, 3, -1 };
18039 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18040 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18042 // Multiply the even parts.
18043 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18044 // Now multiply odd parts.
18045 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18047 Evens = DAG.getBitcast(VT, Evens);
18048 Odds = DAG.getBitcast(VT, Odds);
18050 // Merge the two vectors back together with a shuffle. This expands into 2
18052 static const int ShufMask[] = { 0, 4, 2, 6 };
18053 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18056 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18057 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18059 // Ahi = psrlqi(a, 32);
18060 // Bhi = psrlqi(b, 32);
18062 // AloBlo = pmuludq(a, b);
18063 // AloBhi = pmuludq(a, Bhi);
18064 // AhiBlo = pmuludq(Ahi, b);
18066 // AloBhi = psllqi(AloBhi, 32);
18067 // AhiBlo = psllqi(AhiBlo, 32);
18068 // return AloBlo + AloBhi + AhiBlo;
18070 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18071 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18073 SDValue AhiBlo = Ahi;
18074 SDValue AloBhi = Bhi;
18075 // Bit cast to 32-bit vectors for MULUDQ
18076 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18077 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18078 A = DAG.getBitcast(MulVT, A);
18079 B = DAG.getBitcast(MulVT, B);
18080 Ahi = DAG.getBitcast(MulVT, Ahi);
18081 Bhi = DAG.getBitcast(MulVT, Bhi);
18083 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18084 // After shifting right const values the result may be all-zero.
18085 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18086 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18087 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18089 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18090 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18091 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18094 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18095 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18098 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18099 assert(Subtarget->isTargetWin64() && "Unexpected target");
18100 EVT VT = Op.getValueType();
18101 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18102 "Unexpected return type for lowering");
18106 switch (Op->getOpcode()) {
18107 default: llvm_unreachable("Unexpected request for libcall!");
18108 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18109 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18110 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18111 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18112 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18113 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18117 SDValue InChain = DAG.getEntryNode();
18119 TargetLowering::ArgListTy Args;
18120 TargetLowering::ArgListEntry Entry;
18121 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18122 EVT ArgVT = Op->getOperand(i).getValueType();
18123 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18124 "Unexpected argument type for lowering");
18125 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18126 Entry.Node = StackPtr;
18127 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18129 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18130 Entry.Ty = PointerType::get(ArgTy,0);
18131 Entry.isSExt = false;
18132 Entry.isZExt = false;
18133 Args.push_back(Entry);
18136 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18137 getPointerTy(DAG.getDataLayout()));
18139 TargetLowering::CallLoweringInfo CLI(DAG);
18140 CLI.setDebugLoc(dl).setChain(InChain)
18141 .setCallee(getLibcallCallingConv(LC),
18142 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18143 Callee, std::move(Args), 0)
18144 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18146 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18147 return DAG.getBitcast(VT, CallInfo.first);
18150 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18151 SelectionDAG &DAG) {
18152 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18153 MVT VT = Op0.getSimpleValueType();
18156 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18157 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18159 // PMULxD operations multiply each even value (starting at 0) of LHS with
18160 // the related value of RHS and produce a widen result.
18161 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18162 // => <2 x i64> <ae|cg>
18164 // In other word, to have all the results, we need to perform two PMULxD:
18165 // 1. one with the even values.
18166 // 2. one with the odd values.
18167 // To achieve #2, with need to place the odd values at an even position.
18169 // Place the odd value at an even position (basically, shift all values 1
18170 // step to the left):
18171 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18172 // <a|b|c|d> => <b|undef|d|undef>
18173 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18174 // <e|f|g|h> => <f|undef|h|undef>
18175 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18177 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18179 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18180 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18182 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18183 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18184 // => <2 x i64> <ae|cg>
18185 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18186 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18187 // => <2 x i64> <bf|dh>
18188 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18190 // Shuffle it back into the right order.
18191 SDValue Highs, Lows;
18192 if (VT == MVT::v8i32) {
18193 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18194 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18195 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18196 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18198 const int HighMask[] = {1, 5, 3, 7};
18199 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18200 const int LowMask[] = {0, 4, 2, 6};
18201 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18204 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18205 // unsigned multiply.
18206 if (IsSigned && !Subtarget->hasSSE41()) {
18207 SDValue ShAmt = DAG.getConstant(
18209 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18210 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18211 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18212 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18213 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18215 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18216 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18219 // The first result of MUL_LOHI is actually the low value, followed by the
18221 SDValue Ops[] = {Lows, Highs};
18222 return DAG.getMergeValues(Ops, dl);
18225 // Return true if the required (according to Opcode) shift-imm form is natively
18226 // supported by the Subtarget
18227 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18229 if (VT.getScalarSizeInBits() < 16)
18232 if (VT.is512BitVector() &&
18233 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18236 bool LShift = VT.is128BitVector() ||
18237 (VT.is256BitVector() && Subtarget->hasInt256());
18239 bool AShift = LShift && (Subtarget->hasVLX() ||
18240 (VT != MVT::v2i64 && VT != MVT::v4i64));
18241 return (Opcode == ISD::SRA) ? AShift : LShift;
18244 // The shift amount is a variable, but it is the same for all vector lanes.
18245 // These instructions are defined together with shift-immediate.
18247 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18249 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18252 // Return true if the required (according to Opcode) variable-shift form is
18253 // natively supported by the Subtarget
18254 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18257 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18260 // vXi16 supported only on AVX-512, BWI
18261 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18264 if (VT.is512BitVector() || Subtarget->hasVLX())
18267 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18268 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18269 return (Opcode == ISD::SRA) ? AShift : LShift;
18272 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18273 const X86Subtarget *Subtarget) {
18274 MVT VT = Op.getSimpleValueType();
18276 SDValue R = Op.getOperand(0);
18277 SDValue Amt = Op.getOperand(1);
18279 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18280 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18282 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18283 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18284 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18285 SDValue Ex = DAG.getBitcast(ExVT, R);
18287 if (ShiftAmt >= 32) {
18288 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18290 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18291 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18292 ShiftAmt - 32, DAG);
18293 if (VT == MVT::v2i64)
18294 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18295 if (VT == MVT::v4i64)
18296 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18297 {9, 1, 11, 3, 13, 5, 15, 7});
18299 // SRA upper i32, SHL whole i64 and select lower i32.
18300 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18303 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18304 Lower = DAG.getBitcast(ExVT, Lower);
18305 if (VT == MVT::v2i64)
18306 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18307 if (VT == MVT::v4i64)
18308 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18309 {8, 1, 10, 3, 12, 5, 14, 7});
18311 return DAG.getBitcast(VT, Ex);
18314 // Optimize shl/srl/sra with constant shift amount.
18315 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18316 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18317 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18319 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18320 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18322 // i64 SRA needs to be performed as partial shifts.
18323 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18324 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18325 return ArithmeticShiftRight64(ShiftAmt);
18327 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18328 unsigned NumElts = VT.getVectorNumElements();
18329 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18331 // Simple i8 add case
18332 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18333 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18335 // ashr(R, 7) === cmp_slt(R, 0)
18336 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18337 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18338 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18341 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18342 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18345 if (Op.getOpcode() == ISD::SHL) {
18346 // Make a large shift.
18347 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18349 SHL = DAG.getBitcast(VT, SHL);
18350 // Zero out the rightmost bits.
18351 SmallVector<SDValue, 32> V(
18352 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18353 return DAG.getNode(ISD::AND, dl, VT, SHL,
18354 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18356 if (Op.getOpcode() == ISD::SRL) {
18357 // Make a large shift.
18358 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18360 SRL = DAG.getBitcast(VT, SRL);
18361 // Zero out the leftmost bits.
18362 SmallVector<SDValue, 32> V(
18363 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18364 return DAG.getNode(ISD::AND, dl, VT, SRL,
18365 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18367 if (Op.getOpcode() == ISD::SRA) {
18368 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18369 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18370 SmallVector<SDValue, 32> V(NumElts,
18371 DAG.getConstant(128 >> ShiftAmt, dl,
18373 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18374 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18375 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18378 llvm_unreachable("Unknown shift opcode.");
18383 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18384 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18385 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18387 // Peek through any splat that was introduced for i64 shift vectorization.
18388 int SplatIndex = -1;
18389 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18390 if (SVN->isSplat()) {
18391 SplatIndex = SVN->getSplatIndex();
18392 Amt = Amt.getOperand(0);
18393 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18394 "Splat shuffle referencing second operand");
18397 if (Amt.getOpcode() != ISD::BITCAST ||
18398 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18401 Amt = Amt.getOperand(0);
18402 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18403 VT.getVectorNumElements();
18404 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18405 uint64_t ShiftAmt = 0;
18406 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18407 for (unsigned i = 0; i != Ratio; ++i) {
18408 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18412 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18415 // Check remaining shift amounts (if not a splat).
18416 if (SplatIndex < 0) {
18417 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18418 uint64_t ShAmt = 0;
18419 for (unsigned j = 0; j != Ratio; ++j) {
18420 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18424 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18426 if (ShAmt != ShiftAmt)
18431 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18432 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18434 if (Op.getOpcode() == ISD::SRA)
18435 return ArithmeticShiftRight64(ShiftAmt);
18441 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18442 const X86Subtarget* Subtarget) {
18443 MVT VT = Op.getSimpleValueType();
18445 SDValue R = Op.getOperand(0);
18446 SDValue Amt = Op.getOperand(1);
18448 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18449 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18451 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18452 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18454 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18456 MVT EltVT = VT.getVectorElementType();
18458 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18459 // Check if this build_vector node is doing a splat.
18460 // If so, then set BaseShAmt equal to the splat value.
18461 BaseShAmt = BV->getSplatValue();
18462 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18463 BaseShAmt = SDValue();
18465 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18466 Amt = Amt.getOperand(0);
18468 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18469 if (SVN && SVN->isSplat()) {
18470 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18471 SDValue InVec = Amt.getOperand(0);
18472 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18473 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18474 "Unexpected shuffle index found!");
18475 BaseShAmt = InVec.getOperand(SplatIdx);
18476 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18477 if (ConstantSDNode *C =
18478 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18479 if (C->getZExtValue() == SplatIdx)
18480 BaseShAmt = InVec.getOperand(1);
18485 // Avoid introducing an extract element from a shuffle.
18486 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18487 DAG.getIntPtrConstant(SplatIdx, dl));
18491 if (BaseShAmt.getNode()) {
18492 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18493 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18494 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18495 else if (EltVT.bitsLT(MVT::i32))
18496 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18498 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18502 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18503 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18504 Amt.getOpcode() == ISD::BITCAST &&
18505 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18506 Amt = Amt.getOperand(0);
18507 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18508 VT.getVectorNumElements();
18509 std::vector<SDValue> Vals(Ratio);
18510 for (unsigned i = 0; i != Ratio; ++i)
18511 Vals[i] = Amt.getOperand(i);
18512 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18513 for (unsigned j = 0; j != Ratio; ++j)
18514 if (Vals[j] != Amt.getOperand(i + j))
18518 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18519 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18524 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18525 SelectionDAG &DAG) {
18526 MVT VT = Op.getSimpleValueType();
18528 SDValue R = Op.getOperand(0);
18529 SDValue Amt = Op.getOperand(1);
18531 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18532 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18534 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18537 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18540 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18543 // XOP has 128-bit variable logical/arithmetic shifts.
18544 // +ve/-ve Amt = shift left/right.
18545 if (Subtarget->hasXOP() &&
18546 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18547 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18548 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18549 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18550 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18552 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18553 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18554 if (Op.getOpcode() == ISD::SRA)
18555 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18558 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18559 // shifts per-lane and then shuffle the partial results back together.
18560 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18561 // Splat the shift amounts so the scalar shifts above will catch it.
18562 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18563 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18564 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18565 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18566 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18569 // i64 vector arithmetic shift can be emulated with the transform:
18570 // M = lshr(SIGN_BIT, Amt)
18571 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18572 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18573 Op.getOpcode() == ISD::SRA) {
18574 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18575 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18576 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18577 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18578 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18582 // If possible, lower this packed shift into a vector multiply instead of
18583 // expanding it into a sequence of scalar shifts.
18584 // Do this only if the vector shift count is a constant build_vector.
18585 if (Op.getOpcode() == ISD::SHL &&
18586 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18587 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18588 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18589 SmallVector<SDValue, 8> Elts;
18590 MVT SVT = VT.getVectorElementType();
18591 unsigned SVTBits = SVT.getSizeInBits();
18592 APInt One(SVTBits, 1);
18593 unsigned NumElems = VT.getVectorNumElements();
18595 for (unsigned i=0; i !=NumElems; ++i) {
18596 SDValue Op = Amt->getOperand(i);
18597 if (Op->getOpcode() == ISD::UNDEF) {
18598 Elts.push_back(Op);
18602 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18603 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18604 uint64_t ShAmt = C.getZExtValue();
18605 if (ShAmt >= SVTBits) {
18606 Elts.push_back(DAG.getUNDEF(SVT));
18609 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18611 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18612 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18615 // Lower SHL with variable shift amount.
18616 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18617 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18619 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18620 DAG.getConstant(0x3f800000U, dl, VT));
18621 Op = DAG.getBitcast(MVT::v4f32, Op);
18622 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18623 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18626 // If possible, lower this shift as a sequence of two shifts by
18627 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18629 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18631 // Could be rewritten as:
18632 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18634 // The advantage is that the two shifts from the example would be
18635 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18636 // the vector shift into four scalar shifts plus four pairs of vector
18638 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18639 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18640 unsigned TargetOpcode = X86ISD::MOVSS;
18641 bool CanBeSimplified;
18642 // The splat value for the first packed shift (the 'X' from the example).
18643 SDValue Amt1 = Amt->getOperand(0);
18644 // The splat value for the second packed shift (the 'Y' from the example).
18645 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18646 Amt->getOperand(2);
18648 // See if it is possible to replace this node with a sequence of
18649 // two shifts followed by a MOVSS/MOVSD
18650 if (VT == MVT::v4i32) {
18651 // Check if it is legal to use a MOVSS.
18652 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18653 Amt2 == Amt->getOperand(3);
18654 if (!CanBeSimplified) {
18655 // Otherwise, check if we can still simplify this node using a MOVSD.
18656 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18657 Amt->getOperand(2) == Amt->getOperand(3);
18658 TargetOpcode = X86ISD::MOVSD;
18659 Amt2 = Amt->getOperand(2);
18662 // Do similar checks for the case where the machine value type
18664 CanBeSimplified = Amt1 == Amt->getOperand(1);
18665 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18666 CanBeSimplified = Amt2 == Amt->getOperand(i);
18668 if (!CanBeSimplified) {
18669 TargetOpcode = X86ISD::MOVSD;
18670 CanBeSimplified = true;
18671 Amt2 = Amt->getOperand(4);
18672 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18673 CanBeSimplified = Amt1 == Amt->getOperand(i);
18674 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18675 CanBeSimplified = Amt2 == Amt->getOperand(j);
18679 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18680 isa<ConstantSDNode>(Amt2)) {
18681 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18682 MVT CastVT = MVT::v4i32;
18684 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18685 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18687 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18688 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18689 if (TargetOpcode == X86ISD::MOVSD)
18690 CastVT = MVT::v2i64;
18691 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18692 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18693 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18695 return DAG.getBitcast(VT, Result);
18699 // v4i32 Non Uniform Shifts.
18700 // If the shift amount is constant we can shift each lane using the SSE2
18701 // immediate shifts, else we need to zero-extend each lane to the lower i64
18702 // and shift using the SSE2 variable shifts.
18703 // The separate results can then be blended together.
18704 if (VT == MVT::v4i32) {
18705 unsigned Opc = Op.getOpcode();
18706 SDValue Amt0, Amt1, Amt2, Amt3;
18707 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18708 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18709 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18710 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18711 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18713 // ISD::SHL is handled above but we include it here for completeness.
18716 llvm_unreachable("Unknown target vector shift node");
18718 Opc = X86ISD::VSHL;
18721 Opc = X86ISD::VSRL;
18724 Opc = X86ISD::VSRA;
18727 // The SSE2 shifts use the lower i64 as the same shift amount for
18728 // all lanes and the upper i64 is ignored. These shuffle masks
18729 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18730 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18731 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18732 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18733 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18734 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18737 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18738 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18739 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18740 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18741 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18742 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18743 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18746 if (VT == MVT::v16i8 ||
18747 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18748 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18749 unsigned ShiftOpcode = Op->getOpcode();
18751 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18752 // On SSE41 targets we make use of the fact that VSELECT lowers
18753 // to PBLENDVB which selects bytes based just on the sign bit.
18754 if (Subtarget->hasSSE41()) {
18755 V0 = DAG.getBitcast(VT, V0);
18756 V1 = DAG.getBitcast(VT, V1);
18757 Sel = DAG.getBitcast(VT, Sel);
18758 return DAG.getBitcast(SelVT,
18759 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18761 // On pre-SSE41 targets we test for the sign bit by comparing to
18762 // zero - a negative value will set all bits of the lanes to true
18763 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18764 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18765 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18766 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18769 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18770 // We can safely do this using i16 shifts as we're only interested in
18771 // the 3 lower bits of each byte.
18772 Amt = DAG.getBitcast(ExtVT, Amt);
18773 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18774 Amt = DAG.getBitcast(VT, Amt);
18776 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18777 // r = VSELECT(r, shift(r, 4), a);
18779 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18780 R = SignBitSelect(VT, Amt, M, R);
18783 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18785 // r = VSELECT(r, shift(r, 2), a);
18786 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18787 R = SignBitSelect(VT, Amt, M, R);
18790 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18792 // return VSELECT(r, shift(r, 1), a);
18793 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18794 R = SignBitSelect(VT, Amt, M, R);
18798 if (Op->getOpcode() == ISD::SRA) {
18799 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18800 // so we can correctly sign extend. We don't care what happens to the
18802 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18803 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18804 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18805 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18806 ALo = DAG.getBitcast(ExtVT, ALo);
18807 AHi = DAG.getBitcast(ExtVT, AHi);
18808 RLo = DAG.getBitcast(ExtVT, RLo);
18809 RHi = DAG.getBitcast(ExtVT, RHi);
18811 // r = VSELECT(r, shift(r, 4), a);
18812 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18813 DAG.getConstant(4, dl, ExtVT));
18814 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18815 DAG.getConstant(4, dl, ExtVT));
18816 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18817 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18820 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18821 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18823 // r = VSELECT(r, shift(r, 2), a);
18824 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18825 DAG.getConstant(2, dl, ExtVT));
18826 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18827 DAG.getConstant(2, dl, ExtVT));
18828 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18829 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18832 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18833 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18835 // r = VSELECT(r, shift(r, 1), a);
18836 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18837 DAG.getConstant(1, dl, ExtVT));
18838 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18839 DAG.getConstant(1, dl, ExtVT));
18840 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18841 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18843 // Logical shift the result back to the lower byte, leaving a zero upper
18845 // meaning that we can safely pack with PACKUSWB.
18847 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18849 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18850 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18854 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18855 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18856 // solution better.
18857 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18858 MVT ExtVT = MVT::v8i32;
18860 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18861 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18862 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18863 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18864 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18867 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18868 MVT ExtVT = MVT::v8i32;
18869 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18870 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18871 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18872 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18873 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18874 ALo = DAG.getBitcast(ExtVT, ALo);
18875 AHi = DAG.getBitcast(ExtVT, AHi);
18876 RLo = DAG.getBitcast(ExtVT, RLo);
18877 RHi = DAG.getBitcast(ExtVT, RHi);
18878 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18879 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18880 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18881 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18882 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18885 if (VT == MVT::v8i16) {
18886 unsigned ShiftOpcode = Op->getOpcode();
18888 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18889 // On SSE41 targets we make use of the fact that VSELECT lowers
18890 // to PBLENDVB which selects bytes based just on the sign bit.
18891 if (Subtarget->hasSSE41()) {
18892 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18893 V0 = DAG.getBitcast(ExtVT, V0);
18894 V1 = DAG.getBitcast(ExtVT, V1);
18895 Sel = DAG.getBitcast(ExtVT, Sel);
18896 return DAG.getBitcast(
18897 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18899 // On pre-SSE41 targets we splat the sign bit - a negative value will
18900 // set all bits of the lanes to true and VSELECT uses that in
18901 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18903 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18904 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18907 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18908 if (Subtarget->hasSSE41()) {
18909 // On SSE41 targets we need to replicate the shift mask in both
18910 // bytes for PBLENDVB.
18913 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18914 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18916 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18919 // r = VSELECT(r, shift(r, 8), a);
18920 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18921 R = SignBitSelect(Amt, M, R);
18924 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18926 // r = VSELECT(r, shift(r, 4), a);
18927 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18928 R = SignBitSelect(Amt, M, R);
18931 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18933 // r = VSELECT(r, shift(r, 2), a);
18934 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18935 R = SignBitSelect(Amt, M, R);
18938 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18940 // return VSELECT(r, shift(r, 1), a);
18941 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18942 R = SignBitSelect(Amt, M, R);
18946 // Decompose 256-bit shifts into smaller 128-bit shifts.
18947 if (VT.is256BitVector()) {
18948 unsigned NumElems = VT.getVectorNumElements();
18949 MVT EltVT = VT.getVectorElementType();
18950 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18952 // Extract the two vectors
18953 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18954 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18956 // Recreate the shift amount vectors
18957 SDValue Amt1, Amt2;
18958 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18959 // Constant shift amount
18960 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18961 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18962 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18964 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18965 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18967 // Variable shift amount
18968 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18969 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18972 // Issue new vector shifts for the smaller types
18973 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18974 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18976 // Concatenate the result back
18977 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18983 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18984 SelectionDAG &DAG) {
18985 MVT VT = Op.getSimpleValueType();
18987 SDValue R = Op.getOperand(0);
18988 SDValue Amt = Op.getOperand(1);
18990 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18991 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18992 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18994 // XOP has 128-bit vector variable + immediate rotates.
18995 // +ve/-ve Amt = rotate left/right.
18997 // Split 256-bit integers.
18998 if (VT.is256BitVector())
18999 return Lower256IntArith(Op, DAG);
19001 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
19003 // Attempt to rotate by immediate.
19004 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
19005 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
19006 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
19007 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
19008 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
19009 DAG.getConstant(RotateAmt, DL, MVT::i8));
19013 // Use general rotate by variable (per-element).
19014 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
19017 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
19018 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
19019 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
19020 // looks for this combo and may remove the "setcc" instruction if the "setcc"
19021 // has only one use.
19022 SDNode *N = Op.getNode();
19023 SDValue LHS = N->getOperand(0);
19024 SDValue RHS = N->getOperand(1);
19025 unsigned BaseOp = 0;
19028 switch (Op.getOpcode()) {
19029 default: llvm_unreachable("Unknown ovf instruction!");
19031 // A subtract of one will be selected as a INC. Note that INC doesn't
19032 // set CF, so we can't do this for UADDO.
19033 if (isOneConstant(RHS)) {
19034 BaseOp = X86ISD::INC;
19035 Cond = X86::COND_O;
19038 BaseOp = X86ISD::ADD;
19039 Cond = X86::COND_O;
19042 BaseOp = X86ISD::ADD;
19043 Cond = X86::COND_B;
19046 // A subtract of one will be selected as a DEC. Note that DEC doesn't
19047 // set CF, so we can't do this for USUBO.
19048 if (isOneConstant(RHS)) {
19049 BaseOp = X86ISD::DEC;
19050 Cond = X86::COND_O;
19053 BaseOp = X86ISD::SUB;
19054 Cond = X86::COND_O;
19057 BaseOp = X86ISD::SUB;
19058 Cond = X86::COND_B;
19061 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19062 Cond = X86::COND_O;
19064 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19065 if (N->getValueType(0) == MVT::i8) {
19066 BaseOp = X86ISD::UMUL8;
19067 Cond = X86::COND_O;
19070 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19072 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19075 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19076 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19077 SDValue(Sum.getNode(), 2));
19079 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19083 // Also sets EFLAGS.
19084 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19085 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19088 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19089 DAG.getConstant(Cond, DL, MVT::i32),
19090 SDValue(Sum.getNode(), 1));
19092 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19095 /// Returns true if the operand type is exactly twice the native width, and
19096 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19097 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19098 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19099 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19100 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19103 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19104 else if (OpWidth == 128)
19105 return Subtarget->hasCmpxchg16b();
19110 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19111 return needsCmpXchgNb(SI->getValueOperand()->getType());
19114 // Note: this turns large loads into lock cmpxchg8b/16b.
19115 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19116 TargetLowering::AtomicExpansionKind
19117 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19118 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19119 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19120 : AtomicExpansionKind::None;
19123 TargetLowering::AtomicExpansionKind
19124 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19125 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19126 Type *MemType = AI->getType();
19128 // If the operand is too big, we must see if cmpxchg8/16b is available
19129 // and default to library calls otherwise.
19130 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19131 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19132 : AtomicExpansionKind::None;
19135 AtomicRMWInst::BinOp Op = AI->getOperation();
19138 llvm_unreachable("Unknown atomic operation");
19139 case AtomicRMWInst::Xchg:
19140 case AtomicRMWInst::Add:
19141 case AtomicRMWInst::Sub:
19142 // It's better to use xadd, xsub or xchg for these in all cases.
19143 return AtomicExpansionKind::None;
19144 case AtomicRMWInst::Or:
19145 case AtomicRMWInst::And:
19146 case AtomicRMWInst::Xor:
19147 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19148 // prefix to a normal instruction for these operations.
19149 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19150 : AtomicExpansionKind::None;
19151 case AtomicRMWInst::Nand:
19152 case AtomicRMWInst::Max:
19153 case AtomicRMWInst::Min:
19154 case AtomicRMWInst::UMax:
19155 case AtomicRMWInst::UMin:
19156 // These always require a non-trivial set of data operations on x86. We must
19157 // use a cmpxchg loop.
19158 return AtomicExpansionKind::CmpXChg;
19162 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19163 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19164 // no-sse2). There isn't any reason to disable it if the target processor
19166 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19170 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19171 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19172 Type *MemType = AI->getType();
19173 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19174 // there is no benefit in turning such RMWs into loads, and it is actually
19175 // harmful as it introduces a mfence.
19176 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19179 auto Builder = IRBuilder<>(AI);
19180 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19181 auto SynchScope = AI->getSynchScope();
19182 // We must restrict the ordering to avoid generating loads with Release or
19183 // ReleaseAcquire orderings.
19184 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19185 auto Ptr = AI->getPointerOperand();
19187 // Before the load we need a fence. Here is an example lifted from
19188 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19191 // x.store(1, relaxed);
19192 // r1 = y.fetch_add(0, release);
19194 // y.fetch_add(42, acquire);
19195 // r2 = x.load(relaxed);
19196 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19197 // lowered to just a load without a fence. A mfence flushes the store buffer,
19198 // making the optimization clearly correct.
19199 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19200 // otherwise, we might be able to be more aggressive on relaxed idempotent
19201 // rmw. In practice, they do not look useful, so we don't try to be
19202 // especially clever.
19203 if (SynchScope == SingleThread)
19204 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19205 // the IR level, so we must wrap it in an intrinsic.
19208 if (!hasMFENCE(*Subtarget))
19209 // FIXME: it might make sense to use a locked operation here but on a
19210 // different cache-line to prevent cache-line bouncing. In practice it
19211 // is probably a small win, and x86 processors without mfence are rare
19212 // enough that we do not bother.
19216 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19217 Builder.CreateCall(MFence, {});
19219 // Finally we can emit the atomic load.
19220 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19221 AI->getType()->getPrimitiveSizeInBits());
19222 Loaded->setAtomic(Order, SynchScope);
19223 AI->replaceAllUsesWith(Loaded);
19224 AI->eraseFromParent();
19228 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19229 SelectionDAG &DAG) {
19231 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19232 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19233 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19234 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19236 // The only fence that needs an instruction is a sequentially-consistent
19237 // cross-thread fence.
19238 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19239 if (hasMFENCE(*Subtarget))
19240 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19242 SDValue Chain = Op.getOperand(0);
19243 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19245 DAG.getRegister(X86::ESP, MVT::i32), // Base
19246 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19247 DAG.getRegister(0, MVT::i32), // Index
19248 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19249 DAG.getRegister(0, MVT::i32), // Segment.
19253 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19254 return SDValue(Res, 0);
19257 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19258 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19261 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19262 SelectionDAG &DAG) {
19263 MVT T = Op.getSimpleValueType();
19267 switch(T.SimpleTy) {
19268 default: llvm_unreachable("Invalid value type!");
19269 case MVT::i8: Reg = X86::AL; size = 1; break;
19270 case MVT::i16: Reg = X86::AX; size = 2; break;
19271 case MVT::i32: Reg = X86::EAX; size = 4; break;
19273 assert(Subtarget->is64Bit() && "Node not type legal!");
19274 Reg = X86::RAX; size = 8;
19277 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19278 Op.getOperand(2), SDValue());
19279 SDValue Ops[] = { cpIn.getValue(0),
19282 DAG.getTargetConstant(size, DL, MVT::i8),
19283 cpIn.getValue(1) };
19284 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19285 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19286 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19290 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19291 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19292 MVT::i32, cpOut.getValue(2));
19293 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19294 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19297 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19298 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19299 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19303 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19304 SelectionDAG &DAG) {
19305 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19306 MVT DstVT = Op.getSimpleValueType();
19308 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19309 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19310 if (DstVT != MVT::f64)
19311 // This conversion needs to be expanded.
19314 SDValue InVec = Op->getOperand(0);
19316 unsigned NumElts = SrcVT.getVectorNumElements();
19317 MVT SVT = SrcVT.getVectorElementType();
19319 // Widen the vector in input in the case of MVT::v2i32.
19320 // Example: from MVT::v2i32 to MVT::v4i32.
19321 SmallVector<SDValue, 16> Elts;
19322 for (unsigned i = 0, e = NumElts; i != e; ++i)
19323 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19324 DAG.getIntPtrConstant(i, dl)));
19326 // Explicitly mark the extra elements as Undef.
19327 Elts.append(NumElts, DAG.getUNDEF(SVT));
19329 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19330 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19331 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19332 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19333 DAG.getIntPtrConstant(0, dl));
19336 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19337 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19338 assert((DstVT == MVT::i64 ||
19339 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19340 "Unexpected custom BITCAST");
19341 // i64 <=> MMX conversions are Legal.
19342 if (SrcVT==MVT::i64 && DstVT.isVector())
19344 if (DstVT==MVT::i64 && SrcVT.isVector())
19346 // MMX <=> MMX conversions are Legal.
19347 if (SrcVT.isVector() && DstVT.isVector())
19349 // All other conversions need to be expanded.
19353 /// Compute the horizontal sum of bytes in V for the elements of VT.
19355 /// Requires V to be a byte vector and VT to be an integer vector type with
19356 /// wider elements than V's type. The width of the elements of VT determines
19357 /// how many bytes of V are summed horizontally to produce each element of the
19359 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19360 const X86Subtarget *Subtarget,
19361 SelectionDAG &DAG) {
19363 MVT ByteVecVT = V.getSimpleValueType();
19364 MVT EltVT = VT.getVectorElementType();
19365 int NumElts = VT.getVectorNumElements();
19366 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19367 "Expected value to have byte element type.");
19368 assert(EltVT != MVT::i8 &&
19369 "Horizontal byte sum only makes sense for wider elements!");
19370 unsigned VecSize = VT.getSizeInBits();
19371 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19373 // PSADBW instruction horizontally add all bytes and leave the result in i64
19374 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19375 if (EltVT == MVT::i64) {
19376 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19377 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19378 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19379 return DAG.getBitcast(VT, V);
19382 if (EltVT == MVT::i32) {
19383 // We unpack the low half and high half into i32s interleaved with zeros so
19384 // that we can use PSADBW to horizontally sum them. The most useful part of
19385 // this is that it lines up the results of two PSADBW instructions to be
19386 // two v2i64 vectors which concatenated are the 4 population counts. We can
19387 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19388 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19389 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19390 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19392 // Do the horizontal sums into two v2i64s.
19393 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19394 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19395 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19396 DAG.getBitcast(ByteVecVT, Low), Zeros);
19397 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19398 DAG.getBitcast(ByteVecVT, High), Zeros);
19400 // Merge them together.
19401 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19402 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19403 DAG.getBitcast(ShortVecVT, Low),
19404 DAG.getBitcast(ShortVecVT, High));
19406 return DAG.getBitcast(VT, V);
19409 // The only element type left is i16.
19410 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19412 // To obtain pop count for each i16 element starting from the pop count for
19413 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19414 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19415 // directly supported.
19416 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19417 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19418 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19419 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19420 DAG.getBitcast(ByteVecVT, V));
19421 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19424 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19425 const X86Subtarget *Subtarget,
19426 SelectionDAG &DAG) {
19427 MVT VT = Op.getSimpleValueType();
19428 MVT EltVT = VT.getVectorElementType();
19429 unsigned VecSize = VT.getSizeInBits();
19431 // Implement a lookup table in register by using an algorithm based on:
19432 // http://wm.ite.pl/articles/sse-popcount.html
19434 // The general idea is that every lower byte nibble in the input vector is an
19435 // index into a in-register pre-computed pop count table. We then split up the
19436 // input vector in two new ones: (1) a vector with only the shifted-right
19437 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19438 // masked out higher ones) for each byte. PSHUB is used separately with both
19439 // to index the in-register table. Next, both are added and the result is a
19440 // i8 vector where each element contains the pop count for input byte.
19442 // To obtain the pop count for elements != i8, we follow up with the same
19443 // approach and use additional tricks as described below.
19445 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19446 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19447 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19448 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19450 int NumByteElts = VecSize / 8;
19451 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19452 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19453 SmallVector<SDValue, 16> LUTVec;
19454 for (int i = 0; i < NumByteElts; ++i)
19455 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19456 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19457 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19458 DAG.getConstant(0x0F, DL, MVT::i8));
19459 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19462 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19463 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19464 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19467 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19469 // The input vector is used as the shuffle mask that index elements into the
19470 // LUT. After counting low and high nibbles, add the vector to obtain the
19471 // final pop count per i8 element.
19472 SDValue HighPopCnt =
19473 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19474 SDValue LowPopCnt =
19475 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19476 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19478 if (EltVT == MVT::i8)
19481 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19484 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19485 const X86Subtarget *Subtarget,
19486 SelectionDAG &DAG) {
19487 MVT VT = Op.getSimpleValueType();
19488 assert(VT.is128BitVector() &&
19489 "Only 128-bit vector bitmath lowering supported.");
19491 int VecSize = VT.getSizeInBits();
19492 MVT EltVT = VT.getVectorElementType();
19493 int Len = EltVT.getSizeInBits();
19495 // This is the vectorized version of the "best" algorithm from
19496 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19497 // with a minor tweak to use a series of adds + shifts instead of vector
19498 // multiplications. Implemented for all integer vector types. We only use
19499 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19500 // much faster, even faster than using native popcnt instructions.
19502 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19503 MVT VT = V.getSimpleValueType();
19504 SmallVector<SDValue, 32> Shifters(
19505 VT.getVectorNumElements(),
19506 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19507 return DAG.getNode(OpCode, DL, VT, V,
19508 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19510 auto GetMask = [&](SDValue V, APInt Mask) {
19511 MVT VT = V.getSimpleValueType();
19512 SmallVector<SDValue, 32> Masks(
19513 VT.getVectorNumElements(),
19514 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19515 return DAG.getNode(ISD::AND, DL, VT, V,
19516 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19519 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19520 // x86, so set the SRL type to have elements at least i16 wide. This is
19521 // correct because all of our SRLs are followed immediately by a mask anyways
19522 // that handles any bits that sneak into the high bits of the byte elements.
19523 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19527 // v = v - ((v >> 1) & 0x55555555...)
19529 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19530 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19531 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19533 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19534 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19535 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19536 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19537 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19539 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19540 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19541 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19542 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19544 // At this point, V contains the byte-wise population count, and we are
19545 // merely doing a horizontal sum if necessary to get the wider element
19547 if (EltVT == MVT::i8)
19550 return LowerHorizontalByteSum(
19551 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19555 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19556 SelectionDAG &DAG) {
19557 MVT VT = Op.getSimpleValueType();
19558 // FIXME: Need to add AVX-512 support here!
19559 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19560 "Unknown CTPOP type to handle");
19561 SDLoc DL(Op.getNode());
19562 SDValue Op0 = Op.getOperand(0);
19564 if (!Subtarget->hasSSSE3()) {
19565 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19566 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19567 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19570 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19571 unsigned NumElems = VT.getVectorNumElements();
19573 // Extract each 128-bit vector, compute pop count and concat the result.
19574 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19575 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19577 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19578 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19579 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19582 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19585 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19586 SelectionDAG &DAG) {
19587 assert(Op.getSimpleValueType().isVector() &&
19588 "We only do custom lowering for vector population count.");
19589 return LowerVectorCTPOP(Op, Subtarget, DAG);
19592 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19593 SDNode *Node = Op.getNode();
19595 EVT T = Node->getValueType(0);
19596 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19597 DAG.getConstant(0, dl, T), Node->getOperand(2));
19598 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19599 cast<AtomicSDNode>(Node)->getMemoryVT(),
19600 Node->getOperand(0),
19601 Node->getOperand(1), negOp,
19602 cast<AtomicSDNode>(Node)->getMemOperand(),
19603 cast<AtomicSDNode>(Node)->getOrdering(),
19604 cast<AtomicSDNode>(Node)->getSynchScope());
19607 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19608 SDNode *Node = Op.getNode();
19610 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19612 // Convert seq_cst store -> xchg
19613 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19614 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19615 // (The only way to get a 16-byte store is cmpxchg16b)
19616 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19617 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19618 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19619 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19620 cast<AtomicSDNode>(Node)->getMemoryVT(),
19621 Node->getOperand(0),
19622 Node->getOperand(1), Node->getOperand(2),
19623 cast<AtomicSDNode>(Node)->getMemOperand(),
19624 cast<AtomicSDNode>(Node)->getOrdering(),
19625 cast<AtomicSDNode>(Node)->getSynchScope());
19626 return Swap.getValue(1);
19628 // Other atomic stores have a simple pattern.
19632 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19633 MVT VT = Op.getNode()->getSimpleValueType(0);
19635 // Let legalize expand this if it isn't a legal type yet.
19636 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19639 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19642 bool ExtraOp = false;
19643 switch (Op.getOpcode()) {
19644 default: llvm_unreachable("Invalid code");
19645 case ISD::ADDC: Opc = X86ISD::ADD; break;
19646 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19647 case ISD::SUBC: Opc = X86ISD::SUB; break;
19648 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19652 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19654 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19655 Op.getOperand(1), Op.getOperand(2));
19658 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19659 SelectionDAG &DAG) {
19660 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19662 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19663 // which returns the values as { float, float } (in XMM0) or
19664 // { double, double } (which is returned in XMM0, XMM1).
19666 SDValue Arg = Op.getOperand(0);
19667 EVT ArgVT = Arg.getValueType();
19668 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19670 TargetLowering::ArgListTy Args;
19671 TargetLowering::ArgListEntry Entry;
19675 Entry.isSExt = false;
19676 Entry.isZExt = false;
19677 Args.push_back(Entry);
19679 bool isF64 = ArgVT == MVT::f64;
19680 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19681 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19682 // the results are returned via SRet in memory.
19683 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19684 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19686 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19688 Type *RetTy = isF64
19689 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19690 : (Type*)VectorType::get(ArgTy, 4);
19692 TargetLowering::CallLoweringInfo CLI(DAG);
19693 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19694 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19696 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19699 // Returned in xmm0 and xmm1.
19700 return CallResult.first;
19702 // Returned in bits 0:31 and 32:64 xmm0.
19703 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19704 CallResult.first, DAG.getIntPtrConstant(0, dl));
19705 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19706 CallResult.first, DAG.getIntPtrConstant(1, dl));
19707 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19708 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19711 /// Widen a vector input to a vector of NVT. The
19712 /// input vector must have the same element type as NVT.
19713 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
19714 bool FillWithZeroes = false) {
19715 // Check if InOp already has the right width.
19716 MVT InVT = InOp.getSimpleValueType();
19720 if (InOp.isUndef())
19721 return DAG.getUNDEF(NVT);
19723 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
19724 "input and widen element type must match");
19726 unsigned InNumElts = InVT.getVectorNumElements();
19727 unsigned WidenNumElts = NVT.getVectorNumElements();
19728 assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&
19729 "Unexpected request for vector widening");
19731 EVT EltVT = NVT.getVectorElementType();
19734 if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) ||
19735 ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
19736 SmallVector<SDValue, 16> Ops;
19737 for (unsigned i = 0; i < InNumElts; ++i)
19738 Ops.push_back(InOp.getOperand(i));
19740 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
19741 DAG.getUNDEF(EltVT);
19742 for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)
19743 Ops.push_back(FillVal);
19744 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
19746 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :
19748 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,
19749 InOp, DAG.getIntPtrConstant(0, dl));
19752 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19753 SelectionDAG &DAG) {
19754 assert(Subtarget->hasAVX512() &&
19755 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19757 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19758 MVT VT = N->getValue().getSimpleValueType();
19759 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19762 // X86 scatter kills mask register, so its type should be added to
19763 // the list of return values
19764 if (N->getNumValues() == 1) {
19765 SDValue Index = N->getIndex();
19766 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19767 !Index.getSimpleValueType().is512BitVector())
19768 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19770 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19771 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19772 N->getOperand(3), Index };
19774 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19775 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19776 return SDValue(NewScatter.getNode(), 0);
19781 static SDValue LowerMLOAD(SDValue Op, const X86Subtarget *Subtarget,
19782 SelectionDAG &DAG) {
19784 MaskedLoadSDNode *N = cast<MaskedLoadSDNode>(Op.getNode());
19785 MVT VT = Op.getSimpleValueType();
19786 SDValue Mask = N->getMask();
19789 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
19790 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
19791 // This operation is legal for targets with VLX, but without
19792 // VLX the vector should be widened to 512 bit
19793 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
19794 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
19795 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
19796 SDValue Src0 = N->getSrc0();
19797 Src0 = ExtendToType(Src0, WideDataVT, DAG);
19798 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
19799 SDValue NewLoad = DAG.getMaskedLoad(WideDataVT, dl, N->getChain(),
19800 N->getBasePtr(), Mask, Src0,
19801 N->getMemoryVT(), N->getMemOperand(),
19802 N->getExtensionType());
19804 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
19805 NewLoad.getValue(0),
19806 DAG.getIntPtrConstant(0, dl));
19807 SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
19808 return DAG.getMergeValues(RetOps, dl);
19813 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget *Subtarget,
19814 SelectionDAG &DAG) {
19815 MaskedStoreSDNode *N = cast<MaskedStoreSDNode>(Op.getNode());
19816 SDValue DataToStore = N->getValue();
19817 MVT VT = DataToStore.getSimpleValueType();
19818 SDValue Mask = N->getMask();
19821 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
19822 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
19823 // This operation is legal for targets with VLX, but without
19824 // VLX the vector should be widened to 512 bit
19825 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
19826 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
19827 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
19828 DataToStore = ExtendToType(DataToStore, WideDataVT, DAG);
19829 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
19830 return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
19831 Mask, N->getMemoryVT(), N->getMemOperand(),
19832 N->isTruncatingStore());
19837 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19838 SelectionDAG &DAG) {
19839 assert(Subtarget->hasAVX512() &&
19840 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19842 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19843 MVT VT = Op.getSimpleValueType();
19844 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19847 SDValue Index = N->getIndex();
19848 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19849 !Index.getSimpleValueType().is512BitVector()) {
19850 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19851 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19852 N->getOperand(3), Index };
19853 DAG.UpdateNodeOperands(N, Ops);
19858 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19859 SelectionDAG &DAG) const {
19860 // TODO: Eventually, the lowering of these nodes should be informed by or
19861 // deferred to the GC strategy for the function in which they appear. For
19862 // now, however, they must be lowered to something. Since they are logically
19863 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19864 // require special handling for these nodes), lower them as literal NOOPs for
19866 SmallVector<SDValue, 2> Ops;
19868 Ops.push_back(Op.getOperand(0));
19869 if (Op->getGluedNode())
19870 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19873 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19874 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19879 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19880 SelectionDAG &DAG) const {
19881 // TODO: Eventually, the lowering of these nodes should be informed by or
19882 // deferred to the GC strategy for the function in which they appear. For
19883 // now, however, they must be lowered to something. Since they are logically
19884 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19885 // require special handling for these nodes), lower them as literal NOOPs for
19887 SmallVector<SDValue, 2> Ops;
19889 Ops.push_back(Op.getOperand(0));
19890 if (Op->getGluedNode())
19891 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19894 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19895 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19900 /// LowerOperation - Provide custom lowering hooks for some operations.
19902 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19903 switch (Op.getOpcode()) {
19904 default: llvm_unreachable("Should not custom lower this!");
19905 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19906 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19907 return LowerCMP_SWAP(Op, Subtarget, DAG);
19908 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19909 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19910 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19911 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19912 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19913 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19914 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19915 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19916 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19917 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19918 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19919 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19920 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19921 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19922 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19923 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19924 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19925 case ISD::SHL_PARTS:
19926 case ISD::SRA_PARTS:
19927 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19928 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19929 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19930 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19931 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19932 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19933 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19934 case ISD::SIGN_EXTEND_VECTOR_INREG:
19935 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19936 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19937 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19938 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19939 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19941 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19942 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19943 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19944 case ISD::SETCC: return LowerSETCC(Op, DAG);
19945 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
19946 case ISD::SELECT: return LowerSELECT(Op, DAG);
19947 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19948 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19949 case ISD::VASTART: return LowerVASTART(Op, DAG);
19950 case ISD::VAARG: return LowerVAARG(Op, DAG);
19951 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19952 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19953 case ISD::INTRINSIC_VOID:
19954 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19955 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19956 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19957 case ISD::FRAME_TO_ARGS_OFFSET:
19958 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19959 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19960 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19961 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19962 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19963 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19964 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19965 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19966 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19967 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19969 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19970 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19971 case ISD::UMUL_LOHI:
19972 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19973 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19976 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19982 case ISD::UMULO: return LowerXALUO(Op, DAG);
19983 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19984 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19988 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19989 case ISD::ADD: return LowerADD(Op, DAG);
19990 case ISD::SUB: return LowerSUB(Op, DAG);
19994 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19995 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19996 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG);
19997 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG);
19998 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19999 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
20000 case ISD::GC_TRANSITION_START:
20001 return LowerGC_TRANSITION_START(Op, DAG);
20002 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
20006 /// ReplaceNodeResults - Replace a node with an illegal result type
20007 /// with a new node built out of custom code.
20008 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
20009 SmallVectorImpl<SDValue>&Results,
20010 SelectionDAG &DAG) const {
20012 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20013 switch (N->getOpcode()) {
20015 llvm_unreachable("Do not know how to custom type legalize this operation!");
20016 case X86ISD::AVG: {
20017 // Legalize types for X86ISD::AVG by expanding vectors.
20018 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20020 auto InVT = N->getValueType(0);
20021 auto InVTSize = InVT.getSizeInBits();
20022 const unsigned RegSize =
20023 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
20024 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
20025 "512-bit vector requires AVX512");
20026 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
20027 "256-bit vector requires AVX2");
20029 auto ElemVT = InVT.getVectorElementType();
20030 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
20031 RegSize / ElemVT.getSizeInBits());
20032 assert(RegSize % InVT.getSizeInBits() == 0);
20033 unsigned NumConcat = RegSize / InVT.getSizeInBits();
20035 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
20036 Ops[0] = N->getOperand(0);
20037 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20038 Ops[0] = N->getOperand(1);
20039 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20041 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
20042 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
20043 DAG.getIntPtrConstant(0, dl)));
20046 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
20047 case X86ISD::FMINC:
20049 case X86ISD::FMAXC:
20050 case X86ISD::FMAX: {
20051 EVT VT = N->getValueType(0);
20052 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
20053 SDValue UNDEF = DAG.getUNDEF(VT);
20054 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20055 N->getOperand(0), UNDEF);
20056 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20057 N->getOperand(1), UNDEF);
20058 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
20061 case ISD::SIGN_EXTEND_INREG:
20066 // We don't want to expand or promote these.
20073 case ISD::UDIVREM: {
20074 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
20075 Results.push_back(V);
20078 case ISD::FP_TO_SINT:
20079 case ISD::FP_TO_UINT: {
20080 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
20082 std::pair<SDValue,SDValue> Vals =
20083 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
20084 SDValue FIST = Vals.first, StackSlot = Vals.second;
20085 if (FIST.getNode()) {
20086 EVT VT = N->getValueType(0);
20087 // Return a load from the stack slot.
20088 if (StackSlot.getNode())
20089 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
20090 MachinePointerInfo(),
20091 false, false, false, 0));
20093 Results.push_back(FIST);
20097 case ISD::UINT_TO_FP: {
20098 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20099 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
20100 N->getValueType(0) != MVT::v2f32)
20102 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
20104 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
20106 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
20107 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
20108 DAG.getBitcast(MVT::v2i64, VBias));
20109 Or = DAG.getBitcast(MVT::v2f64, Or);
20110 // TODO: Are there any fast-math-flags to propagate here?
20111 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
20112 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
20115 case ISD::FP_ROUND: {
20116 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
20118 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
20119 Results.push_back(V);
20122 case ISD::FP_EXTEND: {
20123 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
20124 // No other ValueType for FP_EXTEND should reach this point.
20125 assert(N->getValueType(0) == MVT::v2f32 &&
20126 "Do not know how to legalize this Node");
20129 case ISD::INTRINSIC_W_CHAIN: {
20130 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
20132 default : llvm_unreachable("Do not know how to custom type "
20133 "legalize this intrinsic operation!");
20134 case Intrinsic::x86_rdtsc:
20135 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20137 case Intrinsic::x86_rdtscp:
20138 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
20140 case Intrinsic::x86_rdpmc:
20141 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
20144 case ISD::INTRINSIC_WO_CHAIN: {
20145 if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG))
20146 Results.push_back(V);
20149 case ISD::READCYCLECOUNTER: {
20150 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20153 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
20154 EVT T = N->getValueType(0);
20155 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
20156 bool Regs64bit = T == MVT::i128;
20157 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
20158 SDValue cpInL, cpInH;
20159 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20160 DAG.getConstant(0, dl, HalfT));
20161 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20162 DAG.getConstant(1, dl, HalfT));
20163 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20164 Regs64bit ? X86::RAX : X86::EAX,
20166 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20167 Regs64bit ? X86::RDX : X86::EDX,
20168 cpInH, cpInL.getValue(1));
20169 SDValue swapInL, swapInH;
20170 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20171 DAG.getConstant(0, dl, HalfT));
20172 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20173 DAG.getConstant(1, dl, HalfT));
20174 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20175 Regs64bit ? X86::RBX : X86::EBX,
20176 swapInL, cpInH.getValue(1));
20177 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20178 Regs64bit ? X86::RCX : X86::ECX,
20179 swapInH, swapInL.getValue(1));
20180 SDValue Ops[] = { swapInH.getValue(0),
20182 swapInH.getValue(1) };
20183 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20184 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20185 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20186 X86ISD::LCMPXCHG8_DAG;
20187 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20188 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20189 Regs64bit ? X86::RAX : X86::EAX,
20190 HalfT, Result.getValue(1));
20191 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20192 Regs64bit ? X86::RDX : X86::EDX,
20193 HalfT, cpOutL.getValue(2));
20194 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20196 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20197 MVT::i32, cpOutH.getValue(2));
20199 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20200 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20201 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20203 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20204 Results.push_back(Success);
20205 Results.push_back(EFLAGS.getValue(1));
20208 case ISD::ATOMIC_SWAP:
20209 case ISD::ATOMIC_LOAD_ADD:
20210 case ISD::ATOMIC_LOAD_SUB:
20211 case ISD::ATOMIC_LOAD_AND:
20212 case ISD::ATOMIC_LOAD_OR:
20213 case ISD::ATOMIC_LOAD_XOR:
20214 case ISD::ATOMIC_LOAD_NAND:
20215 case ISD::ATOMIC_LOAD_MIN:
20216 case ISD::ATOMIC_LOAD_MAX:
20217 case ISD::ATOMIC_LOAD_UMIN:
20218 case ISD::ATOMIC_LOAD_UMAX:
20219 case ISD::ATOMIC_LOAD: {
20220 // Delegate to generic TypeLegalization. Situations we can really handle
20221 // should have already been dealt with by AtomicExpandPass.cpp.
20224 case ISD::BITCAST: {
20225 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20226 EVT DstVT = N->getValueType(0);
20227 EVT SrcVT = N->getOperand(0)->getValueType(0);
20229 if (SrcVT != MVT::f64 ||
20230 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20233 unsigned NumElts = DstVT.getVectorNumElements();
20234 EVT SVT = DstVT.getVectorElementType();
20235 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20236 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20237 MVT::v2f64, N->getOperand(0));
20238 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20240 if (ExperimentalVectorWideningLegalization) {
20241 // If we are legalizing vectors by widening, we already have the desired
20242 // legal vector type, just return it.
20243 Results.push_back(ToVecInt);
20247 SmallVector<SDValue, 8> Elts;
20248 for (unsigned i = 0, e = NumElts; i != e; ++i)
20249 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20250 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20252 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20257 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20258 switch ((X86ISD::NodeType)Opcode) {
20259 case X86ISD::FIRST_NUMBER: break;
20260 case X86ISD::BSF: return "X86ISD::BSF";
20261 case X86ISD::BSR: return "X86ISD::BSR";
20262 case X86ISD::SHLD: return "X86ISD::SHLD";
20263 case X86ISD::SHRD: return "X86ISD::SHRD";
20264 case X86ISD::FAND: return "X86ISD::FAND";
20265 case X86ISD::FANDN: return "X86ISD::FANDN";
20266 case X86ISD::FOR: return "X86ISD::FOR";
20267 case X86ISD::FXOR: return "X86ISD::FXOR";
20268 case X86ISD::FILD: return "X86ISD::FILD";
20269 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20270 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20271 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20272 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20273 case X86ISD::FLD: return "X86ISD::FLD";
20274 case X86ISD::FST: return "X86ISD::FST";
20275 case X86ISD::CALL: return "X86ISD::CALL";
20276 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20277 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20278 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20279 case X86ISD::BT: return "X86ISD::BT";
20280 case X86ISD::CMP: return "X86ISD::CMP";
20281 case X86ISD::COMI: return "X86ISD::COMI";
20282 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20283 case X86ISD::CMPM: return "X86ISD::CMPM";
20284 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20285 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20286 case X86ISD::SETCC: return "X86ISD::SETCC";
20287 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20288 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20289 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20290 case X86ISD::CMOV: return "X86ISD::CMOV";
20291 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20292 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20293 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20294 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20295 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20296 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20297 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20298 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20299 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20300 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20301 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20302 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20303 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20304 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20305 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20306 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20307 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20308 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20309 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20310 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20311 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20312 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20313 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20314 case X86ISD::HADD: return "X86ISD::HADD";
20315 case X86ISD::HSUB: return "X86ISD::HSUB";
20316 case X86ISD::FHADD: return "X86ISD::FHADD";
20317 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20318 case X86ISD::ABS: return "X86ISD::ABS";
20319 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20320 case X86ISD::FMAX: return "X86ISD::FMAX";
20321 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20322 case X86ISD::FMIN: return "X86ISD::FMIN";
20323 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20324 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20325 case X86ISD::FMINC: return "X86ISD::FMINC";
20326 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20327 case X86ISD::FRCP: return "X86ISD::FRCP";
20328 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20329 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20330 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20331 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20332 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20333 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20334 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20335 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20336 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20337 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20338 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20339 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20340 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20341 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20342 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20343 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20344 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20345 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20346 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20347 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20348 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20349 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20350 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20351 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20352 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20353 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20354 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20355 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20356 case X86ISD::VSHL: return "X86ISD::VSHL";
20357 case X86ISD::VSRL: return "X86ISD::VSRL";
20358 case X86ISD::VSRA: return "X86ISD::VSRA";
20359 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20360 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20361 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20362 case X86ISD::CMPP: return "X86ISD::CMPP";
20363 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20364 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20365 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20366 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20367 case X86ISD::ADD: return "X86ISD::ADD";
20368 case X86ISD::SUB: return "X86ISD::SUB";
20369 case X86ISD::ADC: return "X86ISD::ADC";
20370 case X86ISD::SBB: return "X86ISD::SBB";
20371 case X86ISD::SMUL: return "X86ISD::SMUL";
20372 case X86ISD::UMUL: return "X86ISD::UMUL";
20373 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20374 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20375 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20376 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20377 case X86ISD::INC: return "X86ISD::INC";
20378 case X86ISD::DEC: return "X86ISD::DEC";
20379 case X86ISD::OR: return "X86ISD::OR";
20380 case X86ISD::XOR: return "X86ISD::XOR";
20381 case X86ISD::AND: return "X86ISD::AND";
20382 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20383 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20384 case X86ISD::PTEST: return "X86ISD::PTEST";
20385 case X86ISD::TESTP: return "X86ISD::TESTP";
20386 case X86ISD::TESTM: return "X86ISD::TESTM";
20387 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20388 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20389 case X86ISD::KTEST: return "X86ISD::KTEST";
20390 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20391 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20392 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20393 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20394 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20395 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20396 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20397 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20398 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20399 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20400 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20401 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20402 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20403 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20404 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20405 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20406 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20407 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20408 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20409 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20410 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20411 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20412 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20413 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20414 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20415 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20416 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20417 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20418 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20419 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20420 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20421 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20422 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20423 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20424 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20425 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20426 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20427 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20428 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20429 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20430 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20431 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20432 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20433 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20434 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20435 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20436 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20437 case X86ISD::SAHF: return "X86ISD::SAHF";
20438 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20439 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20440 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20441 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20442 case X86ISD::VPROT: return "X86ISD::VPROT";
20443 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20444 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20445 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20446 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20447 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20448 case X86ISD::FMADD: return "X86ISD::FMADD";
20449 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20450 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20451 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20452 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20453 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20454 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20455 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20456 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20457 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20458 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20459 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20460 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20461 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20462 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20463 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20464 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20465 case X86ISD::XTEST: return "X86ISD::XTEST";
20466 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20467 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20468 case X86ISD::SELECT: return "X86ISD::SELECT";
20469 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20470 case X86ISD::RCP28: return "X86ISD::RCP28";
20471 case X86ISD::EXP2: return "X86ISD::EXP2";
20472 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20473 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20474 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20475 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20476 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20477 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20478 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20479 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20480 case X86ISD::ADDS: return "X86ISD::ADDS";
20481 case X86ISD::SUBS: return "X86ISD::SUBS";
20482 case X86ISD::AVG: return "X86ISD::AVG";
20483 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20484 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20485 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20486 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20487 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20488 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20489 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20494 // isLegalAddressingMode - Return true if the addressing mode represented
20495 // by AM is legal for this target, for a load/store of the specified type.
20496 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20497 const AddrMode &AM, Type *Ty,
20498 unsigned AS) const {
20499 // X86 supports extremely general addressing modes.
20500 CodeModel::Model M = getTargetMachine().getCodeModel();
20501 Reloc::Model R = getTargetMachine().getRelocationModel();
20503 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20504 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20509 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20511 // If a reference to this global requires an extra load, we can't fold it.
20512 if (isGlobalStubReference(GVFlags))
20515 // If BaseGV requires a register for the PIC base, we cannot also have a
20516 // BaseReg specified.
20517 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20520 // If lower 4G is not available, then we must use rip-relative addressing.
20521 if ((M != CodeModel::Small || R != Reloc::Static) &&
20522 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20526 switch (AM.Scale) {
20532 // These scales always work.
20537 // These scales are formed with basereg+scalereg. Only accept if there is
20542 default: // Other stuff never works.
20549 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20550 unsigned Bits = Ty->getScalarSizeInBits();
20552 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20553 // particularly cheaper than those without.
20557 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20558 // variable shifts just as cheap as scalar ones.
20559 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20562 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20563 // fully general vector.
20567 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20568 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20570 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20571 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20572 return NumBits1 > NumBits2;
20575 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20576 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20579 if (!isTypeLegal(EVT::getEVT(Ty1)))
20582 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20584 // Assuming the caller doesn't have a zeroext or signext return parameter,
20585 // truncation all the way down to i1 is valid.
20589 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20590 return isInt<32>(Imm);
20593 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20594 // Can also use sub to handle negated immediates.
20595 return isInt<32>(Imm);
20598 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20599 if (!VT1.isInteger() || !VT2.isInteger())
20601 unsigned NumBits1 = VT1.getSizeInBits();
20602 unsigned NumBits2 = VT2.getSizeInBits();
20603 return NumBits1 > NumBits2;
20606 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20607 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20608 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20611 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20612 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20613 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20616 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20617 EVT VT1 = Val.getValueType();
20618 if (isZExtFree(VT1, VT2))
20621 if (Val.getOpcode() != ISD::LOAD)
20624 if (!VT1.isSimple() || !VT1.isInteger() ||
20625 !VT2.isSimple() || !VT2.isInteger())
20628 switch (VT1.getSimpleVT().SimpleTy) {
20633 // X86 has 8, 16, and 32-bit zero-extending loads.
20640 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20643 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20644 if (!Subtarget->hasAnyFMA())
20647 VT = VT.getScalarType();
20649 if (!VT.isSimple())
20652 switch (VT.getSimpleVT().SimpleTy) {
20663 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20664 // i16 instructions are longer (0x66 prefix) and potentially slower.
20665 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20668 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20669 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20670 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20671 /// are assumed to be legal.
20673 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20675 if (!VT.isSimple())
20678 // Not for i1 vectors
20679 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20682 // Very little shuffling can be done for 64-bit vectors right now.
20683 if (VT.getSimpleVT().getSizeInBits() == 64)
20686 // We only care that the types being shuffled are legal. The lowering can
20687 // handle any possible shuffle mask that results.
20688 return isTypeLegal(VT.getSimpleVT());
20692 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20694 // Just delegate to the generic legality, clear masks aren't special.
20695 return isShuffleMaskLegal(Mask, VT);
20698 //===----------------------------------------------------------------------===//
20699 // X86 Scheduler Hooks
20700 //===----------------------------------------------------------------------===//
20702 /// Utility function to emit xbegin specifying the start of an RTM region.
20703 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20704 const TargetInstrInfo *TII) {
20705 DebugLoc DL = MI->getDebugLoc();
20707 const BasicBlock *BB = MBB->getBasicBlock();
20708 MachineFunction::iterator I = ++MBB->getIterator();
20710 // For the v = xbegin(), we generate
20721 MachineBasicBlock *thisMBB = MBB;
20722 MachineFunction *MF = MBB->getParent();
20723 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20724 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20725 MF->insert(I, mainMBB);
20726 MF->insert(I, sinkMBB);
20728 // Transfer the remainder of BB and its successor edges to sinkMBB.
20729 sinkMBB->splice(sinkMBB->begin(), MBB,
20730 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20731 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20735 // # fallthrough to mainMBB
20736 // # abortion to sinkMBB
20737 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20738 thisMBB->addSuccessor(mainMBB);
20739 thisMBB->addSuccessor(sinkMBB);
20743 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20744 mainMBB->addSuccessor(sinkMBB);
20747 // EAX is live into the sinkMBB
20748 sinkMBB->addLiveIn(X86::EAX);
20749 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20750 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20753 MI->eraseFromParent();
20757 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20758 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20759 // in the .td file.
20760 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20761 const TargetInstrInfo *TII) {
20763 switch (MI->getOpcode()) {
20764 default: llvm_unreachable("illegal opcode!");
20765 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20766 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20767 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20768 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20769 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20770 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20771 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20772 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20775 DebugLoc dl = MI->getDebugLoc();
20776 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20778 unsigned NumArgs = MI->getNumOperands();
20779 for (unsigned i = 1; i < NumArgs; ++i) {
20780 MachineOperand &Op = MI->getOperand(i);
20781 if (!(Op.isReg() && Op.isImplicit()))
20782 MIB.addOperand(Op);
20784 if (MI->hasOneMemOperand())
20785 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20787 BuildMI(*BB, MI, dl,
20788 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20789 .addReg(X86::XMM0);
20791 MI->eraseFromParent();
20795 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20796 // defs in an instruction pattern
20797 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20798 const TargetInstrInfo *TII) {
20800 switch (MI->getOpcode()) {
20801 default: llvm_unreachable("illegal opcode!");
20802 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20803 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20804 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20805 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20806 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20807 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20808 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20809 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20812 DebugLoc dl = MI->getDebugLoc();
20813 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20815 unsigned NumArgs = MI->getNumOperands(); // remove the results
20816 for (unsigned i = 1; i < NumArgs; ++i) {
20817 MachineOperand &Op = MI->getOperand(i);
20818 if (!(Op.isReg() && Op.isImplicit()))
20819 MIB.addOperand(Op);
20821 if (MI->hasOneMemOperand())
20822 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20824 BuildMI(*BB, MI, dl,
20825 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20828 MI->eraseFromParent();
20832 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20833 const X86Subtarget *Subtarget) {
20834 DebugLoc dl = MI->getDebugLoc();
20835 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20836 // Address into RAX/EAX, other two args into ECX, EDX.
20837 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20838 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20839 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20840 for (int i = 0; i < X86::AddrNumOperands; ++i)
20841 MIB.addOperand(MI->getOperand(i));
20843 unsigned ValOps = X86::AddrNumOperands;
20844 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20845 .addReg(MI->getOperand(ValOps).getReg());
20846 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20847 .addReg(MI->getOperand(ValOps+1).getReg());
20849 // The instruction doesn't actually take any operands though.
20850 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20852 MI->eraseFromParent(); // The pseudo is gone now.
20856 MachineBasicBlock *
20857 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20858 MachineBasicBlock *MBB) const {
20859 // Emit va_arg instruction on X86-64.
20861 // Operands to this pseudo-instruction:
20862 // 0 ) Output : destination address (reg)
20863 // 1-5) Input : va_list address (addr, i64mem)
20864 // 6 ) ArgSize : Size (in bytes) of vararg type
20865 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20866 // 8 ) Align : Alignment of type
20867 // 9 ) EFLAGS (implicit-def)
20869 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20870 static_assert(X86::AddrNumOperands == 5,
20871 "VAARG_64 assumes 5 address operands");
20873 unsigned DestReg = MI->getOperand(0).getReg();
20874 MachineOperand &Base = MI->getOperand(1);
20875 MachineOperand &Scale = MI->getOperand(2);
20876 MachineOperand &Index = MI->getOperand(3);
20877 MachineOperand &Disp = MI->getOperand(4);
20878 MachineOperand &Segment = MI->getOperand(5);
20879 unsigned ArgSize = MI->getOperand(6).getImm();
20880 unsigned ArgMode = MI->getOperand(7).getImm();
20881 unsigned Align = MI->getOperand(8).getImm();
20883 // Memory Reference
20884 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20885 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20886 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20888 // Machine Information
20889 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20890 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20891 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20892 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20893 DebugLoc DL = MI->getDebugLoc();
20895 // struct va_list {
20898 // i64 overflow_area (address)
20899 // i64 reg_save_area (address)
20901 // sizeof(va_list) = 24
20902 // alignment(va_list) = 8
20904 unsigned TotalNumIntRegs = 6;
20905 unsigned TotalNumXMMRegs = 8;
20906 bool UseGPOffset = (ArgMode == 1);
20907 bool UseFPOffset = (ArgMode == 2);
20908 unsigned MaxOffset = TotalNumIntRegs * 8 +
20909 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20911 /* Align ArgSize to a multiple of 8 */
20912 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20913 bool NeedsAlign = (Align > 8);
20915 MachineBasicBlock *thisMBB = MBB;
20916 MachineBasicBlock *overflowMBB;
20917 MachineBasicBlock *offsetMBB;
20918 MachineBasicBlock *endMBB;
20920 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20921 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20922 unsigned OffsetReg = 0;
20924 if (!UseGPOffset && !UseFPOffset) {
20925 // If we only pull from the overflow region, we don't create a branch.
20926 // We don't need to alter control flow.
20927 OffsetDestReg = 0; // unused
20928 OverflowDestReg = DestReg;
20930 offsetMBB = nullptr;
20931 overflowMBB = thisMBB;
20934 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20935 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20936 // If not, pull from overflow_area. (branch to overflowMBB)
20941 // offsetMBB overflowMBB
20946 // Registers for the PHI in endMBB
20947 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20948 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20950 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20951 MachineFunction *MF = MBB->getParent();
20952 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20953 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20954 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20956 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20958 // Insert the new basic blocks
20959 MF->insert(MBBIter, offsetMBB);
20960 MF->insert(MBBIter, overflowMBB);
20961 MF->insert(MBBIter, endMBB);
20963 // Transfer the remainder of MBB and its successor edges to endMBB.
20964 endMBB->splice(endMBB->begin(), thisMBB,
20965 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20966 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20968 // Make offsetMBB and overflowMBB successors of thisMBB
20969 thisMBB->addSuccessor(offsetMBB);
20970 thisMBB->addSuccessor(overflowMBB);
20972 // endMBB is a successor of both offsetMBB and overflowMBB
20973 offsetMBB->addSuccessor(endMBB);
20974 overflowMBB->addSuccessor(endMBB);
20976 // Load the offset value into a register
20977 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20978 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20982 .addDisp(Disp, UseFPOffset ? 4 : 0)
20983 .addOperand(Segment)
20984 .setMemRefs(MMOBegin, MMOEnd);
20986 // Check if there is enough room left to pull this argument.
20987 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20989 .addImm(MaxOffset + 8 - ArgSizeA8);
20991 // Branch to "overflowMBB" if offset >= max
20992 // Fall through to "offsetMBB" otherwise
20993 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20994 .addMBB(overflowMBB);
20997 // In offsetMBB, emit code to use the reg_save_area.
20999 assert(OffsetReg != 0);
21001 // Read the reg_save_area address.
21002 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
21003 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
21008 .addOperand(Segment)
21009 .setMemRefs(MMOBegin, MMOEnd);
21011 // Zero-extend the offset
21012 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
21013 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
21016 .addImm(X86::sub_32bit);
21018 // Add the offset to the reg_save_area to get the final address.
21019 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
21020 .addReg(OffsetReg64)
21021 .addReg(RegSaveReg);
21023 // Compute the offset for the next argument
21024 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21025 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
21027 .addImm(UseFPOffset ? 16 : 8);
21029 // Store it back into the va_list.
21030 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
21034 .addDisp(Disp, UseFPOffset ? 4 : 0)
21035 .addOperand(Segment)
21036 .addReg(NextOffsetReg)
21037 .setMemRefs(MMOBegin, MMOEnd);
21040 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
21045 // Emit code to use overflow area
21048 // Load the overflow_area address into a register.
21049 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
21050 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
21055 .addOperand(Segment)
21056 .setMemRefs(MMOBegin, MMOEnd);
21058 // If we need to align it, do so. Otherwise, just copy the address
21059 // to OverflowDestReg.
21061 // Align the overflow address
21062 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
21063 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
21065 // aligned_addr = (addr + (align-1)) & ~(align-1)
21066 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
21067 .addReg(OverflowAddrReg)
21070 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
21072 .addImm(~(uint64_t)(Align-1));
21074 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
21075 .addReg(OverflowAddrReg);
21078 // Compute the next overflow address after this argument.
21079 // (the overflow address should be kept 8-byte aligned)
21080 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
21081 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
21082 .addReg(OverflowDestReg)
21083 .addImm(ArgSizeA8);
21085 // Store the new overflow address.
21086 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
21091 .addOperand(Segment)
21092 .addReg(NextAddrReg)
21093 .setMemRefs(MMOBegin, MMOEnd);
21095 // If we branched, emit the PHI to the front of endMBB.
21097 BuildMI(*endMBB, endMBB->begin(), DL,
21098 TII->get(X86::PHI), DestReg)
21099 .addReg(OffsetDestReg).addMBB(offsetMBB)
21100 .addReg(OverflowDestReg).addMBB(overflowMBB);
21103 // Erase the pseudo instruction
21104 MI->eraseFromParent();
21109 MachineBasicBlock *
21110 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
21112 MachineBasicBlock *MBB) const {
21113 // Emit code to save XMM registers to the stack. The ABI says that the
21114 // number of registers to save is given in %al, so it's theoretically
21115 // possible to do an indirect jump trick to avoid saving all of them,
21116 // however this code takes a simpler approach and just executes all
21117 // of the stores if %al is non-zero. It's less code, and it's probably
21118 // easier on the hardware branch predictor, and stores aren't all that
21119 // expensive anyway.
21121 // Create the new basic blocks. One block contains all the XMM stores,
21122 // and one block is the final destination regardless of whether any
21123 // stores were performed.
21124 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21125 MachineFunction *F = MBB->getParent();
21126 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21127 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
21128 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
21129 F->insert(MBBIter, XMMSaveMBB);
21130 F->insert(MBBIter, EndMBB);
21132 // Transfer the remainder of MBB and its successor edges to EndMBB.
21133 EndMBB->splice(EndMBB->begin(), MBB,
21134 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21135 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
21137 // The original block will now fall through to the XMM save block.
21138 MBB->addSuccessor(XMMSaveMBB);
21139 // The XMMSaveMBB will fall through to the end block.
21140 XMMSaveMBB->addSuccessor(EndMBB);
21142 // Now add the instructions.
21143 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21144 DebugLoc DL = MI->getDebugLoc();
21146 unsigned CountReg = MI->getOperand(0).getReg();
21147 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
21148 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
21150 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
21151 // If %al is 0, branch around the XMM save block.
21152 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
21153 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
21154 MBB->addSuccessor(EndMBB);
21157 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
21158 // that was just emitted, but clearly shouldn't be "saved".
21159 assert((MI->getNumOperands() <= 3 ||
21160 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
21161 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21162 && "Expected last argument to be EFLAGS");
21163 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21164 // In the XMM save block, save all the XMM argument registers.
21165 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21166 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21167 MachineMemOperand *MMO = F->getMachineMemOperand(
21168 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21169 MachineMemOperand::MOStore,
21170 /*Size=*/16, /*Align=*/16);
21171 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21172 .addFrameIndex(RegSaveFrameIndex)
21173 .addImm(/*Scale=*/1)
21174 .addReg(/*IndexReg=*/0)
21175 .addImm(/*Disp=*/Offset)
21176 .addReg(/*Segment=*/0)
21177 .addReg(MI->getOperand(i).getReg())
21178 .addMemOperand(MMO);
21181 MI->eraseFromParent(); // The pseudo instruction is gone now.
21186 // The EFLAGS operand of SelectItr might be missing a kill marker
21187 // because there were multiple uses of EFLAGS, and ISel didn't know
21188 // which to mark. Figure out whether SelectItr should have had a
21189 // kill marker, and set it if it should. Returns the correct kill
21191 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21192 MachineBasicBlock* BB,
21193 const TargetRegisterInfo* TRI) {
21194 // Scan forward through BB for a use/def of EFLAGS.
21195 MachineBasicBlock::iterator miI(std::next(SelectItr));
21196 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21197 const MachineInstr& mi = *miI;
21198 if (mi.readsRegister(X86::EFLAGS))
21200 if (mi.definesRegister(X86::EFLAGS))
21201 break; // Should have kill-flag - update below.
21204 // If we hit the end of the block, check whether EFLAGS is live into a
21206 if (miI == BB->end()) {
21207 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21208 sEnd = BB->succ_end();
21209 sItr != sEnd; ++sItr) {
21210 MachineBasicBlock* succ = *sItr;
21211 if (succ->isLiveIn(X86::EFLAGS))
21216 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21217 // out. SelectMI should have a kill flag on EFLAGS.
21218 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21222 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21223 // together with other CMOV pseudo-opcodes into a single basic-block with
21224 // conditional jump around it.
21225 static bool isCMOVPseudo(MachineInstr *MI) {
21226 switch (MI->getOpcode()) {
21227 case X86::CMOV_FR32:
21228 case X86::CMOV_FR64:
21229 case X86::CMOV_GR8:
21230 case X86::CMOV_GR16:
21231 case X86::CMOV_GR32:
21232 case X86::CMOV_RFP32:
21233 case X86::CMOV_RFP64:
21234 case X86::CMOV_RFP80:
21235 case X86::CMOV_V2F64:
21236 case X86::CMOV_V2I64:
21237 case X86::CMOV_V4F32:
21238 case X86::CMOV_V4F64:
21239 case X86::CMOV_V4I64:
21240 case X86::CMOV_V16F32:
21241 case X86::CMOV_V8F32:
21242 case X86::CMOV_V8F64:
21243 case X86::CMOV_V8I64:
21244 case X86::CMOV_V8I1:
21245 case X86::CMOV_V16I1:
21246 case X86::CMOV_V32I1:
21247 case X86::CMOV_V64I1:
21255 MachineBasicBlock *
21256 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21257 MachineBasicBlock *BB) const {
21258 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21259 DebugLoc DL = MI->getDebugLoc();
21261 // To "insert" a SELECT_CC instruction, we actually have to insert the
21262 // diamond control-flow pattern. The incoming instruction knows the
21263 // destination vreg to set, the condition code register to branch on, the
21264 // true/false values to select between, and a branch opcode to use.
21265 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21266 MachineFunction::iterator It = ++BB->getIterator();
21271 // cmpTY ccX, r1, r2
21273 // fallthrough --> copy0MBB
21274 MachineBasicBlock *thisMBB = BB;
21275 MachineFunction *F = BB->getParent();
21277 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21278 // as described above, by inserting a BB, and then making a PHI at the join
21279 // point to select the true and false operands of the CMOV in the PHI.
21281 // The code also handles two different cases of multiple CMOV opcodes
21285 // In this case, there are multiple CMOVs in a row, all which are based on
21286 // the same condition setting (or the exact opposite condition setting).
21287 // In this case we can lower all the CMOVs using a single inserted BB, and
21288 // then make a number of PHIs at the join point to model the CMOVs. The only
21289 // trickiness here, is that in a case like:
21291 // t2 = CMOV cond1 t1, f1
21292 // t3 = CMOV cond1 t2, f2
21294 // when rewriting this into PHIs, we have to perform some renaming on the
21295 // temps since you cannot have a PHI operand refer to a PHI result earlier
21296 // in the same block. The "simple" but wrong lowering would be:
21298 // t2 = PHI t1(BB1), f1(BB2)
21299 // t3 = PHI t2(BB1), f2(BB2)
21301 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21302 // renaming is to note that on the path through BB1, t2 is really just a
21303 // copy of t1, and do that renaming, properly generating:
21305 // t2 = PHI t1(BB1), f1(BB2)
21306 // t3 = PHI t1(BB1), f2(BB2)
21308 // Case 2, we lower cascaded CMOVs such as
21310 // (CMOV (CMOV F, T, cc1), T, cc2)
21312 // to two successives branches. For that, we look for another CMOV as the
21313 // following instruction.
21315 // Without this, we would add a PHI between the two jumps, which ends up
21316 // creating a few copies all around. For instance, for
21318 // (sitofp (zext (fcmp une)))
21320 // we would generate:
21322 // ucomiss %xmm1, %xmm0
21323 // movss <1.0f>, %xmm0
21324 // movaps %xmm0, %xmm1
21326 // xorps %xmm1, %xmm1
21329 // movaps %xmm1, %xmm0
21333 // because this custom-inserter would have generated:
21345 // A: X = ...; Y = ...
21347 // C: Z = PHI [X, A], [Y, B]
21349 // E: PHI [X, C], [Z, D]
21351 // If we lower both CMOVs in a single step, we can instead generate:
21363 // A: X = ...; Y = ...
21365 // E: PHI [X, A], [X, C], [Y, D]
21367 // Which, in our sitofp/fcmp example, gives us something like:
21369 // ucomiss %xmm1, %xmm0
21370 // movss <1.0f>, %xmm0
21373 // xorps %xmm0, %xmm0
21377 MachineInstr *CascadedCMOV = nullptr;
21378 MachineInstr *LastCMOV = MI;
21379 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21380 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21381 MachineBasicBlock::iterator NextMIIt =
21382 std::next(MachineBasicBlock::iterator(MI));
21384 // Check for case 1, where there are multiple CMOVs with the same condition
21385 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21386 // number of jumps the most.
21388 if (isCMOVPseudo(MI)) {
21389 // See if we have a string of CMOVS with the same condition.
21390 while (NextMIIt != BB->end() &&
21391 isCMOVPseudo(NextMIIt) &&
21392 (NextMIIt->getOperand(3).getImm() == CC ||
21393 NextMIIt->getOperand(3).getImm() == OppCC)) {
21394 LastCMOV = &*NextMIIt;
21399 // This checks for case 2, but only do this if we didn't already find
21400 // case 1, as indicated by LastCMOV == MI.
21401 if (LastCMOV == MI &&
21402 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21403 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21404 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21405 CascadedCMOV = &*NextMIIt;
21408 MachineBasicBlock *jcc1MBB = nullptr;
21410 // If we have a cascaded CMOV, we lower it to two successive branches to
21411 // the same block. EFLAGS is used by both, so mark it as live in the second.
21412 if (CascadedCMOV) {
21413 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21414 F->insert(It, jcc1MBB);
21415 jcc1MBB->addLiveIn(X86::EFLAGS);
21418 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21419 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21420 F->insert(It, copy0MBB);
21421 F->insert(It, sinkMBB);
21423 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21424 // live into the sink and copy blocks.
21425 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21427 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21428 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21429 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21430 copy0MBB->addLiveIn(X86::EFLAGS);
21431 sinkMBB->addLiveIn(X86::EFLAGS);
21434 // Transfer the remainder of BB and its successor edges to sinkMBB.
21435 sinkMBB->splice(sinkMBB->begin(), BB,
21436 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21437 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21439 // Add the true and fallthrough blocks as its successors.
21440 if (CascadedCMOV) {
21441 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21442 BB->addSuccessor(jcc1MBB);
21444 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21445 // jump to the sinkMBB.
21446 jcc1MBB->addSuccessor(copy0MBB);
21447 jcc1MBB->addSuccessor(sinkMBB);
21449 BB->addSuccessor(copy0MBB);
21452 // The true block target of the first (or only) branch is always sinkMBB.
21453 BB->addSuccessor(sinkMBB);
21455 // Create the conditional branch instruction.
21456 unsigned Opc = X86::GetCondBranchFromCond(CC);
21457 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21459 if (CascadedCMOV) {
21460 unsigned Opc2 = X86::GetCondBranchFromCond(
21461 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21462 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21466 // %FalseValue = ...
21467 // # fallthrough to sinkMBB
21468 copy0MBB->addSuccessor(sinkMBB);
21471 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21473 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21474 MachineBasicBlock::iterator MIItEnd =
21475 std::next(MachineBasicBlock::iterator(LastCMOV));
21476 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21477 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21478 MachineInstrBuilder MIB;
21480 // As we are creating the PHIs, we have to be careful if there is more than
21481 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21482 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21483 // That also means that PHI construction must work forward from earlier to
21484 // later, and that the code must maintain a mapping from earlier PHI's
21485 // destination registers, and the registers that went into the PHI.
21487 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21488 unsigned DestReg = MIIt->getOperand(0).getReg();
21489 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21490 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21492 // If this CMOV we are generating is the opposite condition from
21493 // the jump we generated, then we have to swap the operands for the
21494 // PHI that is going to be generated.
21495 if (MIIt->getOperand(3).getImm() == OppCC)
21496 std::swap(Op1Reg, Op2Reg);
21498 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21499 Op1Reg = RegRewriteTable[Op1Reg].first;
21501 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21502 Op2Reg = RegRewriteTable[Op2Reg].second;
21504 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21505 TII->get(X86::PHI), DestReg)
21506 .addReg(Op1Reg).addMBB(copy0MBB)
21507 .addReg(Op2Reg).addMBB(thisMBB);
21509 // Add this PHI to the rewrite table.
21510 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21513 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21514 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21515 if (CascadedCMOV) {
21516 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21517 // Copy the PHI result to the register defined by the second CMOV.
21518 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21519 DL, TII->get(TargetOpcode::COPY),
21520 CascadedCMOV->getOperand(0).getReg())
21521 .addReg(MI->getOperand(0).getReg());
21522 CascadedCMOV->eraseFromParent();
21525 // Now remove the CMOV(s).
21526 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21527 (MIIt++)->eraseFromParent();
21532 MachineBasicBlock *
21533 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21534 MachineBasicBlock *BB) const {
21535 // Combine the following atomic floating-point modification pattern:
21536 // a.store(reg OP a.load(acquire), release)
21537 // Transform them into:
21538 // OPss (%gpr), %xmm
21539 // movss %xmm, (%gpr)
21540 // Or sd equivalent for 64-bit operations.
21542 switch (MI->getOpcode()) {
21543 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21544 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21545 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21547 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21548 DebugLoc DL = MI->getDebugLoc();
21549 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21550 MachineOperand MSrc = MI->getOperand(0);
21551 unsigned VSrc = MI->getOperand(5).getReg();
21552 const MachineOperand &Disp = MI->getOperand(3);
21553 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21554 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21555 if (hasDisp && MSrc.isReg())
21556 MSrc.setIsKill(false);
21557 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21558 .addOperand(/*Base=*/MSrc)
21559 .addImm(/*Scale=*/1)
21560 .addReg(/*Index=*/0)
21561 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21563 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21564 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21566 .addOperand(/*Base=*/MSrc)
21567 .addImm(/*Scale=*/1)
21568 .addReg(/*Index=*/0)
21569 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21570 .addReg(/*Segment=*/0);
21571 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21572 MI->eraseFromParent(); // The pseudo instruction is gone now.
21576 MachineBasicBlock *
21577 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21578 MachineBasicBlock *BB) const {
21579 MachineFunction *MF = BB->getParent();
21580 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21581 DebugLoc DL = MI->getDebugLoc();
21582 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21584 assert(MF->shouldSplitStack());
21586 const bool Is64Bit = Subtarget->is64Bit();
21587 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21589 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21590 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21593 // ... [Till the alloca]
21594 // If stacklet is not large enough, jump to mallocMBB
21597 // Allocate by subtracting from RSP
21598 // Jump to continueMBB
21601 // Allocate by call to runtime
21605 // [rest of original BB]
21608 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21609 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21610 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21612 MachineRegisterInfo &MRI = MF->getRegInfo();
21613 const TargetRegisterClass *AddrRegClass =
21614 getRegClassFor(getPointerTy(MF->getDataLayout()));
21616 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21617 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21618 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21619 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21620 sizeVReg = MI->getOperand(1).getReg(),
21621 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21623 MachineFunction::iterator MBBIter = ++BB->getIterator();
21625 MF->insert(MBBIter, bumpMBB);
21626 MF->insert(MBBIter, mallocMBB);
21627 MF->insert(MBBIter, continueMBB);
21629 continueMBB->splice(continueMBB->begin(), BB,
21630 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21631 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21633 // Add code to the main basic block to check if the stack limit has been hit,
21634 // and if so, jump to mallocMBB otherwise to bumpMBB.
21635 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21636 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21637 .addReg(tmpSPVReg).addReg(sizeVReg);
21638 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21639 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21640 .addReg(SPLimitVReg);
21641 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21643 // bumpMBB simply decreases the stack pointer, since we know the current
21644 // stacklet has enough space.
21645 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21646 .addReg(SPLimitVReg);
21647 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21648 .addReg(SPLimitVReg);
21649 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21651 // Calls into a routine in libgcc to allocate more space from the heap.
21652 const uint32_t *RegMask =
21653 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21655 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21657 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21658 .addExternalSymbol("__morestack_allocate_stack_space")
21659 .addRegMask(RegMask)
21660 .addReg(X86::RDI, RegState::Implicit)
21661 .addReg(X86::RAX, RegState::ImplicitDefine);
21662 } else if (Is64Bit) {
21663 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21665 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21666 .addExternalSymbol("__morestack_allocate_stack_space")
21667 .addRegMask(RegMask)
21668 .addReg(X86::EDI, RegState::Implicit)
21669 .addReg(X86::EAX, RegState::ImplicitDefine);
21671 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21673 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21674 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21675 .addExternalSymbol("__morestack_allocate_stack_space")
21676 .addRegMask(RegMask)
21677 .addReg(X86::EAX, RegState::ImplicitDefine);
21681 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21684 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21685 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21686 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21688 // Set up the CFG correctly.
21689 BB->addSuccessor(bumpMBB);
21690 BB->addSuccessor(mallocMBB);
21691 mallocMBB->addSuccessor(continueMBB);
21692 bumpMBB->addSuccessor(continueMBB);
21694 // Take care of the PHI nodes.
21695 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21696 MI->getOperand(0).getReg())
21697 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21698 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21700 // Delete the original pseudo instruction.
21701 MI->eraseFromParent();
21704 return continueMBB;
21707 MachineBasicBlock *
21708 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21709 MachineBasicBlock *BB) const {
21710 assert(!Subtarget->isTargetMachO());
21711 DebugLoc DL = MI->getDebugLoc();
21712 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21713 *BB->getParent(), *BB, MI, DL, false);
21714 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21715 MI->eraseFromParent(); // The pseudo instruction is gone now.
21719 MachineBasicBlock *
21720 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21721 MachineBasicBlock *BB) const {
21722 MachineFunction *MF = BB->getParent();
21723 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21724 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21725 DebugLoc DL = MI->getDebugLoc();
21727 assert(!isAsynchronousEHPersonality(
21728 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21729 "SEH does not use catchret!");
21731 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21732 if (!Subtarget->is32Bit())
21735 // C++ EH creates a new target block to hold the restore code, and wires up
21736 // the new block to the return destination with a normal JMP_4.
21737 MachineBasicBlock *RestoreMBB =
21738 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21739 assert(BB->succ_size() == 1);
21740 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21741 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21742 BB->addSuccessor(RestoreMBB);
21743 MI->getOperand(0).setMBB(RestoreMBB);
21745 auto RestoreMBBI = RestoreMBB->begin();
21746 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21747 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21751 MachineBasicBlock *
21752 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21753 MachineBasicBlock *BB) const {
21754 MachineFunction *MF = BB->getParent();
21755 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21756 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21757 // Only 32-bit SEH requires special handling for catchpad.
21758 if (IsSEH && Subtarget->is32Bit()) {
21759 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21760 DebugLoc DL = MI->getDebugLoc();
21761 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21763 MI->eraseFromParent();
21767 MachineBasicBlock *
21768 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21769 MachineBasicBlock *BB) const {
21770 // This is pretty easy. We're taking the value that we received from
21771 // our load from the relocation, sticking it in either RDI (x86-64)
21772 // or EAX and doing an indirect call. The return value will then
21773 // be in the normal return register.
21774 MachineFunction *F = BB->getParent();
21775 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21776 DebugLoc DL = MI->getDebugLoc();
21778 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21779 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21781 // Get a register mask for the lowered call.
21782 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21783 // proper register mask.
21784 const uint32_t *RegMask =
21785 Subtarget->is64Bit() ?
21786 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21787 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21788 if (Subtarget->is64Bit()) {
21789 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21790 TII->get(X86::MOV64rm), X86::RDI)
21792 .addImm(0).addReg(0)
21793 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21794 MI->getOperand(3).getTargetFlags())
21796 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21797 addDirectMem(MIB, X86::RDI);
21798 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21799 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21800 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21801 TII->get(X86::MOV32rm), X86::EAX)
21803 .addImm(0).addReg(0)
21804 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21805 MI->getOperand(3).getTargetFlags())
21807 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21808 addDirectMem(MIB, X86::EAX);
21809 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21811 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21812 TII->get(X86::MOV32rm), X86::EAX)
21813 .addReg(TII->getGlobalBaseReg(F))
21814 .addImm(0).addReg(0)
21815 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21816 MI->getOperand(3).getTargetFlags())
21818 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21819 addDirectMem(MIB, X86::EAX);
21820 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21823 MI->eraseFromParent(); // The pseudo instruction is gone now.
21827 MachineBasicBlock *
21828 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21829 MachineBasicBlock *MBB) const {
21830 DebugLoc DL = MI->getDebugLoc();
21831 MachineFunction *MF = MBB->getParent();
21832 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21833 MachineRegisterInfo &MRI = MF->getRegInfo();
21835 const BasicBlock *BB = MBB->getBasicBlock();
21836 MachineFunction::iterator I = ++MBB->getIterator();
21838 // Memory Reference
21839 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21840 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21843 unsigned MemOpndSlot = 0;
21845 unsigned CurOp = 0;
21847 DstReg = MI->getOperand(CurOp++).getReg();
21848 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21849 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21850 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21851 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21853 MemOpndSlot = CurOp;
21855 MVT PVT = getPointerTy(MF->getDataLayout());
21856 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21857 "Invalid Pointer Size!");
21859 // For v = setjmp(buf), we generate
21862 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21863 // SjLjSetup restoreMBB
21869 // v = phi(main, restore)
21872 // if base pointer being used, load it from frame
21875 MachineBasicBlock *thisMBB = MBB;
21876 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21877 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21878 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21879 MF->insert(I, mainMBB);
21880 MF->insert(I, sinkMBB);
21881 MF->push_back(restoreMBB);
21882 restoreMBB->setHasAddressTaken();
21884 MachineInstrBuilder MIB;
21886 // Transfer the remainder of BB and its successor edges to sinkMBB.
21887 sinkMBB->splice(sinkMBB->begin(), MBB,
21888 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21889 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21892 unsigned PtrStoreOpc = 0;
21893 unsigned LabelReg = 0;
21894 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21895 Reloc::Model RM = MF->getTarget().getRelocationModel();
21896 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21897 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21899 // Prepare IP either in reg or imm.
21900 if (!UseImmLabel) {
21901 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21902 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21903 LabelReg = MRI.createVirtualRegister(PtrRC);
21904 if (Subtarget->is64Bit()) {
21905 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21909 .addMBB(restoreMBB)
21912 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21913 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21914 .addReg(XII->getGlobalBaseReg(MF))
21917 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21921 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21923 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21924 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21925 if (i == X86::AddrDisp)
21926 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21928 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21931 MIB.addReg(LabelReg);
21933 MIB.addMBB(restoreMBB);
21934 MIB.setMemRefs(MMOBegin, MMOEnd);
21936 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21937 .addMBB(restoreMBB);
21939 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21940 MIB.addRegMask(RegInfo->getNoPreservedMask());
21941 thisMBB->addSuccessor(mainMBB);
21942 thisMBB->addSuccessor(restoreMBB);
21946 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21947 mainMBB->addSuccessor(sinkMBB);
21950 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21951 TII->get(X86::PHI), DstReg)
21952 .addReg(mainDstReg).addMBB(mainMBB)
21953 .addReg(restoreDstReg).addMBB(restoreMBB);
21956 if (RegInfo->hasBasePointer(*MF)) {
21957 const bool Uses64BitFramePtr =
21958 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21959 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21960 X86FI->setRestoreBasePointer(MF);
21961 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21962 unsigned BasePtr = RegInfo->getBaseRegister();
21963 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21964 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21965 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21966 .setMIFlag(MachineInstr::FrameSetup);
21968 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21969 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21970 restoreMBB->addSuccessor(sinkMBB);
21972 MI->eraseFromParent();
21976 MachineBasicBlock *
21977 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21978 MachineBasicBlock *MBB) const {
21979 DebugLoc DL = MI->getDebugLoc();
21980 MachineFunction *MF = MBB->getParent();
21981 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21982 MachineRegisterInfo &MRI = MF->getRegInfo();
21984 // Memory Reference
21985 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21986 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21988 MVT PVT = getPointerTy(MF->getDataLayout());
21989 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21990 "Invalid Pointer Size!");
21992 const TargetRegisterClass *RC =
21993 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21994 unsigned Tmp = MRI.createVirtualRegister(RC);
21995 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21996 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21997 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21998 unsigned SP = RegInfo->getStackRegister();
22000 MachineInstrBuilder MIB;
22002 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22003 const int64_t SPOffset = 2 * PVT.getStoreSize();
22005 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
22006 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
22009 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
22010 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
22011 MIB.addOperand(MI->getOperand(i));
22012 MIB.setMemRefs(MMOBegin, MMOEnd);
22014 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
22015 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22016 if (i == X86::AddrDisp)
22017 MIB.addDisp(MI->getOperand(i), LabelOffset);
22019 MIB.addOperand(MI->getOperand(i));
22021 MIB.setMemRefs(MMOBegin, MMOEnd);
22023 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
22024 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22025 if (i == X86::AddrDisp)
22026 MIB.addDisp(MI->getOperand(i), SPOffset);
22028 MIB.addOperand(MI->getOperand(i));
22030 MIB.setMemRefs(MMOBegin, MMOEnd);
22032 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
22034 MI->eraseFromParent();
22038 // Replace 213-type (isel default) FMA3 instructions with 231-type for
22039 // accumulator loops. Writing back to the accumulator allows the coalescer
22040 // to remove extra copies in the loop.
22041 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
22042 MachineBasicBlock *
22043 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
22044 MachineBasicBlock *MBB) const {
22045 MachineOperand &AddendOp = MI->getOperand(3);
22047 // Bail out early if the addend isn't a register - we can't switch these.
22048 if (!AddendOp.isReg())
22051 MachineFunction &MF = *MBB->getParent();
22052 MachineRegisterInfo &MRI = MF.getRegInfo();
22054 // Check whether the addend is defined by a PHI:
22055 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
22056 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
22057 if (!AddendDef.isPHI())
22060 // Look for the following pattern:
22062 // %addend = phi [%entry, 0], [%loop, %result]
22064 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
22068 // %addend = phi [%entry, 0], [%loop, %result]
22070 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
22072 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
22073 assert(AddendDef.getOperand(i).isReg());
22074 MachineOperand PHISrcOp = AddendDef.getOperand(i);
22075 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
22076 if (&PHISrcInst == MI) {
22077 // Found a matching instruction.
22078 unsigned NewFMAOpc = 0;
22079 switch (MI->getOpcode()) {
22080 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
22081 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
22082 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
22083 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
22084 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
22085 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
22086 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
22087 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
22088 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
22089 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
22090 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
22091 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
22092 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
22093 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
22094 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
22095 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
22096 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
22097 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
22098 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
22099 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
22101 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
22102 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
22103 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
22104 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
22105 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
22106 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
22107 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
22108 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
22109 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
22110 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
22111 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
22112 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
22113 default: llvm_unreachable("Unrecognized FMA variant.");
22116 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22117 MachineInstrBuilder MIB =
22118 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
22119 .addOperand(MI->getOperand(0))
22120 .addOperand(MI->getOperand(3))
22121 .addOperand(MI->getOperand(2))
22122 .addOperand(MI->getOperand(1));
22123 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
22124 MI->eraseFromParent();
22131 MachineBasicBlock *
22132 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
22133 MachineBasicBlock *BB) const {
22134 switch (MI->getOpcode()) {
22135 default: llvm_unreachable("Unexpected instr type to insert");
22136 case X86::TAILJMPd64:
22137 case X86::TAILJMPr64:
22138 case X86::TAILJMPm64:
22139 case X86::TAILJMPd64_REX:
22140 case X86::TAILJMPr64_REX:
22141 case X86::TAILJMPm64_REX:
22142 llvm_unreachable("TAILJMP64 would not be touched here.");
22143 case X86::TCRETURNdi64:
22144 case X86::TCRETURNri64:
22145 case X86::TCRETURNmi64:
22147 case X86::WIN_ALLOCA:
22148 return EmitLoweredWinAlloca(MI, BB);
22149 case X86::CATCHRET:
22150 return EmitLoweredCatchRet(MI, BB);
22151 case X86::CATCHPAD:
22152 return EmitLoweredCatchPad(MI, BB);
22153 case X86::SEG_ALLOCA_32:
22154 case X86::SEG_ALLOCA_64:
22155 return EmitLoweredSegAlloca(MI, BB);
22156 case X86::TLSCall_32:
22157 case X86::TLSCall_64:
22158 return EmitLoweredTLSCall(MI, BB);
22159 case X86::CMOV_FR32:
22160 case X86::CMOV_FR64:
22161 case X86::CMOV_GR8:
22162 case X86::CMOV_GR16:
22163 case X86::CMOV_GR32:
22164 case X86::CMOV_RFP32:
22165 case X86::CMOV_RFP64:
22166 case X86::CMOV_RFP80:
22167 case X86::CMOV_V2F64:
22168 case X86::CMOV_V2I64:
22169 case X86::CMOV_V4F32:
22170 case X86::CMOV_V4F64:
22171 case X86::CMOV_V4I64:
22172 case X86::CMOV_V16F32:
22173 case X86::CMOV_V8F32:
22174 case X86::CMOV_V8F64:
22175 case X86::CMOV_V8I64:
22176 case X86::CMOV_V8I1:
22177 case X86::CMOV_V16I1:
22178 case X86::CMOV_V32I1:
22179 case X86::CMOV_V64I1:
22180 return EmitLoweredSelect(MI, BB);
22182 case X86::RELEASE_FADD32mr:
22183 case X86::RELEASE_FADD64mr:
22184 return EmitLoweredAtomicFP(MI, BB);
22186 case X86::FP32_TO_INT16_IN_MEM:
22187 case X86::FP32_TO_INT32_IN_MEM:
22188 case X86::FP32_TO_INT64_IN_MEM:
22189 case X86::FP64_TO_INT16_IN_MEM:
22190 case X86::FP64_TO_INT32_IN_MEM:
22191 case X86::FP64_TO_INT64_IN_MEM:
22192 case X86::FP80_TO_INT16_IN_MEM:
22193 case X86::FP80_TO_INT32_IN_MEM:
22194 case X86::FP80_TO_INT64_IN_MEM: {
22195 MachineFunction *F = BB->getParent();
22196 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22197 DebugLoc DL = MI->getDebugLoc();
22199 // Change the floating point control register to use "round towards zero"
22200 // mode when truncating to an integer value.
22201 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22202 addFrameReference(BuildMI(*BB, MI, DL,
22203 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22205 // Load the old value of the high byte of the control word...
22207 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22208 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22211 // Set the high part to be round to zero...
22212 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22215 // Reload the modified control word now...
22216 addFrameReference(BuildMI(*BB, MI, DL,
22217 TII->get(X86::FLDCW16m)), CWFrameIdx);
22219 // Restore the memory image of control word to original value
22220 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22223 // Get the X86 opcode to use.
22225 switch (MI->getOpcode()) {
22226 default: llvm_unreachable("illegal opcode!");
22227 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22228 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22229 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22230 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22231 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22232 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22233 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22234 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22235 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22239 MachineOperand &Op = MI->getOperand(0);
22241 AM.BaseType = X86AddressMode::RegBase;
22242 AM.Base.Reg = Op.getReg();
22244 AM.BaseType = X86AddressMode::FrameIndexBase;
22245 AM.Base.FrameIndex = Op.getIndex();
22247 Op = MI->getOperand(1);
22249 AM.Scale = Op.getImm();
22250 Op = MI->getOperand(2);
22252 AM.IndexReg = Op.getImm();
22253 Op = MI->getOperand(3);
22254 if (Op.isGlobal()) {
22255 AM.GV = Op.getGlobal();
22257 AM.Disp = Op.getImm();
22259 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22260 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22262 // Reload the original control word now.
22263 addFrameReference(BuildMI(*BB, MI, DL,
22264 TII->get(X86::FLDCW16m)), CWFrameIdx);
22266 MI->eraseFromParent(); // The pseudo instruction is gone now.
22269 // String/text processing lowering.
22270 case X86::PCMPISTRM128REG:
22271 case X86::VPCMPISTRM128REG:
22272 case X86::PCMPISTRM128MEM:
22273 case X86::VPCMPISTRM128MEM:
22274 case X86::PCMPESTRM128REG:
22275 case X86::VPCMPESTRM128REG:
22276 case X86::PCMPESTRM128MEM:
22277 case X86::VPCMPESTRM128MEM:
22278 assert(Subtarget->hasSSE42() &&
22279 "Target must have SSE4.2 or AVX features enabled");
22280 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22282 // String/text processing lowering.
22283 case X86::PCMPISTRIREG:
22284 case X86::VPCMPISTRIREG:
22285 case X86::PCMPISTRIMEM:
22286 case X86::VPCMPISTRIMEM:
22287 case X86::PCMPESTRIREG:
22288 case X86::VPCMPESTRIREG:
22289 case X86::PCMPESTRIMEM:
22290 case X86::VPCMPESTRIMEM:
22291 assert(Subtarget->hasSSE42() &&
22292 "Target must have SSE4.2 or AVX features enabled");
22293 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22295 // Thread synchronization.
22297 return EmitMonitor(MI, BB, Subtarget);
22301 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22303 case X86::VASTART_SAVE_XMM_REGS:
22304 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22306 case X86::VAARG_64:
22307 return EmitVAARG64WithCustomInserter(MI, BB);
22309 case X86::EH_SjLj_SetJmp32:
22310 case X86::EH_SjLj_SetJmp64:
22311 return emitEHSjLjSetJmp(MI, BB);
22313 case X86::EH_SjLj_LongJmp32:
22314 case X86::EH_SjLj_LongJmp64:
22315 return emitEHSjLjLongJmp(MI, BB);
22317 case TargetOpcode::STATEPOINT:
22318 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22319 // this point in the process. We diverge later.
22320 return emitPatchPoint(MI, BB);
22322 case TargetOpcode::STACKMAP:
22323 case TargetOpcode::PATCHPOINT:
22324 return emitPatchPoint(MI, BB);
22326 case X86::VFMADDPDr213r:
22327 case X86::VFMADDPSr213r:
22328 case X86::VFMADDSDr213r:
22329 case X86::VFMADDSSr213r:
22330 case X86::VFMSUBPDr213r:
22331 case X86::VFMSUBPSr213r:
22332 case X86::VFMSUBSDr213r:
22333 case X86::VFMSUBSSr213r:
22334 case X86::VFNMADDPDr213r:
22335 case X86::VFNMADDPSr213r:
22336 case X86::VFNMADDSDr213r:
22337 case X86::VFNMADDSSr213r:
22338 case X86::VFNMSUBPDr213r:
22339 case X86::VFNMSUBPSr213r:
22340 case X86::VFNMSUBSDr213r:
22341 case X86::VFNMSUBSSr213r:
22342 case X86::VFMADDSUBPDr213r:
22343 case X86::VFMADDSUBPSr213r:
22344 case X86::VFMSUBADDPDr213r:
22345 case X86::VFMSUBADDPSr213r:
22346 case X86::VFMADDPDr213rY:
22347 case X86::VFMADDPSr213rY:
22348 case X86::VFMSUBPDr213rY:
22349 case X86::VFMSUBPSr213rY:
22350 case X86::VFNMADDPDr213rY:
22351 case X86::VFNMADDPSr213rY:
22352 case X86::VFNMSUBPDr213rY:
22353 case X86::VFNMSUBPSr213rY:
22354 case X86::VFMADDSUBPDr213rY:
22355 case X86::VFMADDSUBPSr213rY:
22356 case X86::VFMSUBADDPDr213rY:
22357 case X86::VFMSUBADDPSr213rY:
22358 return emitFMA3Instr(MI, BB);
22362 //===----------------------------------------------------------------------===//
22363 // X86 Optimization Hooks
22364 //===----------------------------------------------------------------------===//
22366 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22369 const SelectionDAG &DAG,
22370 unsigned Depth) const {
22371 unsigned BitWidth = KnownZero.getBitWidth();
22372 unsigned Opc = Op.getOpcode();
22373 assert((Opc >= ISD::BUILTIN_OP_END ||
22374 Opc == ISD::INTRINSIC_WO_CHAIN ||
22375 Opc == ISD::INTRINSIC_W_CHAIN ||
22376 Opc == ISD::INTRINSIC_VOID) &&
22377 "Should use MaskedValueIsZero if you don't know whether Op"
22378 " is a target node!");
22380 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22394 // These nodes' second result is a boolean.
22395 if (Op.getResNo() == 0)
22398 case X86ISD::SETCC:
22399 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22401 case ISD::INTRINSIC_WO_CHAIN: {
22402 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22403 unsigned NumLoBits = 0;
22406 case Intrinsic::x86_sse_movmsk_ps:
22407 case Intrinsic::x86_avx_movmsk_ps_256:
22408 case Intrinsic::x86_sse2_movmsk_pd:
22409 case Intrinsic::x86_avx_movmsk_pd_256:
22410 case Intrinsic::x86_mmx_pmovmskb:
22411 case Intrinsic::x86_sse2_pmovmskb_128:
22412 case Intrinsic::x86_avx2_pmovmskb: {
22413 // High bits of movmskp{s|d}, pmovmskb are known zero.
22415 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22416 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22417 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22418 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22419 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22420 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22421 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22422 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22424 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22433 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22435 const SelectionDAG &,
22436 unsigned Depth) const {
22437 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22438 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22439 return Op.getValueType().getScalarSizeInBits();
22445 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22446 /// node is a GlobalAddress + offset.
22447 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22448 const GlobalValue* &GA,
22449 int64_t &Offset) const {
22450 if (N->getOpcode() == X86ISD::Wrapper) {
22451 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22452 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22453 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22457 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22460 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22461 /// same as extracting the high 128-bit part of 256-bit vector and then
22462 /// inserting the result into the low part of a new 256-bit vector
22463 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22464 EVT VT = SVOp->getValueType(0);
22465 unsigned NumElems = VT.getVectorNumElements();
22467 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22468 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22469 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22470 SVOp->getMaskElt(j) >= 0)
22476 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22477 /// same as extracting the low 128-bit part of 256-bit vector and then
22478 /// inserting the result into the high part of a new 256-bit vector
22479 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22480 EVT VT = SVOp->getValueType(0);
22481 unsigned NumElems = VT.getVectorNumElements();
22483 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22484 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22485 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22486 SVOp->getMaskElt(j) >= 0)
22492 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22493 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22494 TargetLowering::DAGCombinerInfo &DCI,
22495 const X86Subtarget* Subtarget) {
22497 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22498 SDValue V1 = SVOp->getOperand(0);
22499 SDValue V2 = SVOp->getOperand(1);
22500 MVT VT = SVOp->getSimpleValueType(0);
22501 unsigned NumElems = VT.getVectorNumElements();
22503 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22504 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22508 // V UNDEF BUILD_VECTOR UNDEF
22510 // CONCAT_VECTOR CONCAT_VECTOR
22513 // RESULT: V + zero extended
22515 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22516 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22517 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22520 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22523 // To match the shuffle mask, the first half of the mask should
22524 // be exactly the first vector, and all the rest a splat with the
22525 // first element of the second one.
22526 for (unsigned i = 0; i != NumElems/2; ++i)
22527 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22528 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22531 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22532 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22533 if (Ld->hasNUsesOfValue(1, 0)) {
22534 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22535 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22537 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22539 Ld->getPointerInfo(),
22540 Ld->getAlignment(),
22541 false/*isVolatile*/, true/*ReadMem*/,
22542 false/*WriteMem*/);
22544 // Make sure the newly-created LOAD is in the same position as Ld in
22545 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22546 // and update uses of Ld's output chain to use the TokenFactor.
22547 if (Ld->hasAnyUseOfValue(1)) {
22548 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22549 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22550 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22551 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22552 SDValue(ResNode.getNode(), 1));
22555 return DAG.getBitcast(VT, ResNode);
22559 // Emit a zeroed vector and insert the desired subvector on its
22561 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22562 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22563 return DCI.CombineTo(N, InsV);
22566 //===--------------------------------------------------------------------===//
22567 // Combine some shuffles into subvector extracts and inserts:
22570 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22571 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22572 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22573 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22574 return DCI.CombineTo(N, InsV);
22577 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22578 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22579 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22580 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22581 return DCI.CombineTo(N, InsV);
22587 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22590 /// This is the leaf of the recursive combinine below. When we have found some
22591 /// chain of single-use x86 shuffle instructions and accumulated the combined
22592 /// shuffle mask represented by them, this will try to pattern match that mask
22593 /// into either a single instruction if there is a special purpose instruction
22594 /// for this operation, or into a PSHUFB instruction which is a fully general
22595 /// instruction but should only be used to replace chains over a certain depth.
22596 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22597 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22598 TargetLowering::DAGCombinerInfo &DCI,
22599 const X86Subtarget *Subtarget) {
22600 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22602 // Find the operand that enters the chain. Note that multiple uses are OK
22603 // here, we're not going to remove the operand we find.
22604 SDValue Input = Op.getOperand(0);
22605 while (Input.getOpcode() == ISD::BITCAST)
22606 Input = Input.getOperand(0);
22608 MVT VT = Input.getSimpleValueType();
22609 MVT RootVT = Root.getSimpleValueType();
22612 if (Mask.size() == 1) {
22613 int Index = Mask[0];
22614 assert((Index >= 0 || Index == SM_SentinelUndef ||
22615 Index == SM_SentinelZero) &&
22616 "Invalid shuffle index found!");
22618 // We may end up with an accumulated mask of size 1 as a result of
22619 // widening of shuffle operands (see function canWidenShuffleElements).
22620 // If the only shuffle index is equal to SM_SentinelZero then propagate
22621 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22622 // mask, and therefore the entire chain of shuffles can be folded away.
22623 if (Index == SM_SentinelZero)
22624 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22626 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22631 // Use the float domain if the operand type is a floating point type.
22632 bool FloatDomain = VT.isFloatingPoint();
22634 // For floating point shuffles, we don't have free copies in the shuffle
22635 // instructions or the ability to load as part of the instruction, so
22636 // canonicalize their shuffles to UNPCK or MOV variants.
22638 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22639 // vectors because it can have a load folded into it that UNPCK cannot. This
22640 // doesn't preclude something switching to the shorter encoding post-RA.
22642 // FIXME: Should teach these routines about AVX vector widths.
22643 if (FloatDomain && VT.is128BitVector()) {
22644 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22645 bool Lo = Mask.equals({0, 0});
22648 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22649 // is no slower than UNPCKLPD but has the option to fold the input operand
22650 // into even an unaligned memory load.
22651 if (Lo && Subtarget->hasSSE3()) {
22652 Shuffle = X86ISD::MOVDDUP;
22653 ShuffleVT = MVT::v2f64;
22655 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22656 // than the UNPCK variants.
22657 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22658 ShuffleVT = MVT::v4f32;
22660 if (Depth == 1 && Root->getOpcode() == Shuffle)
22661 return false; // Nothing to do!
22662 Op = DAG.getBitcast(ShuffleVT, Input);
22663 DCI.AddToWorklist(Op.getNode());
22664 if (Shuffle == X86ISD::MOVDDUP)
22665 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22667 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22668 DCI.AddToWorklist(Op.getNode());
22669 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22673 if (Subtarget->hasSSE3() &&
22674 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22675 bool Lo = Mask.equals({0, 0, 2, 2});
22676 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22677 MVT ShuffleVT = MVT::v4f32;
22678 if (Depth == 1 && Root->getOpcode() == Shuffle)
22679 return false; // Nothing to do!
22680 Op = DAG.getBitcast(ShuffleVT, Input);
22681 DCI.AddToWorklist(Op.getNode());
22682 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22683 DCI.AddToWorklist(Op.getNode());
22684 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22688 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22689 bool Lo = Mask.equals({0, 0, 1, 1});
22690 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22691 MVT ShuffleVT = MVT::v4f32;
22692 if (Depth == 1 && Root->getOpcode() == Shuffle)
22693 return false; // Nothing to do!
22694 Op = DAG.getBitcast(ShuffleVT, Input);
22695 DCI.AddToWorklist(Op.getNode());
22696 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22697 DCI.AddToWorklist(Op.getNode());
22698 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22704 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22705 // variants as none of these have single-instruction variants that are
22706 // superior to the UNPCK formulation.
22707 if (!FloatDomain && VT.is128BitVector() &&
22708 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22709 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22710 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22712 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22713 bool Lo = Mask[0] == 0;
22714 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22715 if (Depth == 1 && Root->getOpcode() == Shuffle)
22716 return false; // Nothing to do!
22718 switch (Mask.size()) {
22720 ShuffleVT = MVT::v8i16;
22723 ShuffleVT = MVT::v16i8;
22726 llvm_unreachable("Impossible mask size!");
22728 Op = DAG.getBitcast(ShuffleVT, Input);
22729 DCI.AddToWorklist(Op.getNode());
22730 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22731 DCI.AddToWorklist(Op.getNode());
22732 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22737 // Don't try to re-form single instruction chains under any circumstances now
22738 // that we've done encoding canonicalization for them.
22742 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22743 // can replace them with a single PSHUFB instruction profitably. Intel's
22744 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22745 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22746 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22747 SmallVector<SDValue, 16> PSHUFBMask;
22748 int NumBytes = VT.getSizeInBits() / 8;
22749 int Ratio = NumBytes / Mask.size();
22750 for (int i = 0; i < NumBytes; ++i) {
22751 if (Mask[i / Ratio] == SM_SentinelUndef) {
22752 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22755 int M = Mask[i / Ratio] != SM_SentinelZero
22756 ? Ratio * Mask[i / Ratio] + i % Ratio
22758 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22760 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22761 Op = DAG.getBitcast(ByteVT, Input);
22762 DCI.AddToWorklist(Op.getNode());
22763 SDValue PSHUFBMaskOp =
22764 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22765 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22766 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22767 DCI.AddToWorklist(Op.getNode());
22768 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22773 // Failed to find any combines.
22777 /// \brief Fully generic combining of x86 shuffle instructions.
22779 /// This should be the last combine run over the x86 shuffle instructions. Once
22780 /// they have been fully optimized, this will recursively consider all chains
22781 /// of single-use shuffle instructions, build a generic model of the cumulative
22782 /// shuffle operation, and check for simpler instructions which implement this
22783 /// operation. We use this primarily for two purposes:
22785 /// 1) Collapse generic shuffles to specialized single instructions when
22786 /// equivalent. In most cases, this is just an encoding size win, but
22787 /// sometimes we will collapse multiple generic shuffles into a single
22788 /// special-purpose shuffle.
22789 /// 2) Look for sequences of shuffle instructions with 3 or more total
22790 /// instructions, and replace them with the slightly more expensive SSSE3
22791 /// PSHUFB instruction if available. We do this as the last combining step
22792 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22793 /// a suitable short sequence of other instructions. The PHUFB will either
22794 /// use a register or have to read from memory and so is slightly (but only
22795 /// slightly) more expensive than the other shuffle instructions.
22797 /// Because this is inherently a quadratic operation (for each shuffle in
22798 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22799 /// This should never be an issue in practice as the shuffle lowering doesn't
22800 /// produce sequences of more than 8 instructions.
22802 /// FIXME: We will currently miss some cases where the redundant shuffling
22803 /// would simplify under the threshold for PSHUFB formation because of
22804 /// combine-ordering. To fix this, we should do the redundant instruction
22805 /// combining in this recursive walk.
22806 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22807 ArrayRef<int> RootMask,
22808 int Depth, bool HasPSHUFB,
22810 TargetLowering::DAGCombinerInfo &DCI,
22811 const X86Subtarget *Subtarget) {
22812 // Bound the depth of our recursive combine because this is ultimately
22813 // quadratic in nature.
22817 // Directly rip through bitcasts to find the underlying operand.
22818 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22819 Op = Op.getOperand(0);
22821 MVT VT = Op.getSimpleValueType();
22822 if (!VT.isVector())
22823 return false; // Bail if we hit a non-vector.
22825 assert(Root.getSimpleValueType().isVector() &&
22826 "Shuffles operate on vector types!");
22827 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22828 "Can only combine shuffles of the same vector register size.");
22830 if (!isTargetShuffle(Op.getOpcode()))
22832 SmallVector<int, 16> OpMask;
22834 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22835 // We only can combine unary shuffles which we can decode the mask for.
22836 if (!HaveMask || !IsUnary)
22839 assert(VT.getVectorNumElements() == OpMask.size() &&
22840 "Different mask size from vector size!");
22841 assert(((RootMask.size() > OpMask.size() &&
22842 RootMask.size() % OpMask.size() == 0) ||
22843 (OpMask.size() > RootMask.size() &&
22844 OpMask.size() % RootMask.size() == 0) ||
22845 OpMask.size() == RootMask.size()) &&
22846 "The smaller number of elements must divide the larger.");
22847 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22848 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22849 assert(((RootRatio == 1 && OpRatio == 1) ||
22850 (RootRatio == 1) != (OpRatio == 1)) &&
22851 "Must not have a ratio for both incoming and op masks!");
22853 SmallVector<int, 16> Mask;
22854 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22856 // Merge this shuffle operation's mask into our accumulated mask. Note that
22857 // this shuffle's mask will be the first applied to the input, followed by the
22858 // root mask to get us all the way to the root value arrangement. The reason
22859 // for this order is that we are recursing up the operation chain.
22860 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22861 int RootIdx = i / RootRatio;
22862 if (RootMask[RootIdx] < 0) {
22863 // This is a zero or undef lane, we're done.
22864 Mask.push_back(RootMask[RootIdx]);
22868 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22869 int OpIdx = RootMaskedIdx / OpRatio;
22870 if (OpMask[OpIdx] < 0) {
22871 // The incoming lanes are zero or undef, it doesn't matter which ones we
22873 Mask.push_back(OpMask[OpIdx]);
22877 // Ok, we have non-zero lanes, map them through.
22878 Mask.push_back(OpMask[OpIdx] * OpRatio +
22879 RootMaskedIdx % OpRatio);
22882 // See if we can recurse into the operand to combine more things.
22883 switch (Op.getOpcode()) {
22884 case X86ISD::PSHUFB:
22886 case X86ISD::PSHUFD:
22887 case X86ISD::PSHUFHW:
22888 case X86ISD::PSHUFLW:
22889 if (Op.getOperand(0).hasOneUse() &&
22890 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22891 HasPSHUFB, DAG, DCI, Subtarget))
22895 case X86ISD::UNPCKL:
22896 case X86ISD::UNPCKH:
22897 assert(Op.getOperand(0) == Op.getOperand(1) &&
22898 "We only combine unary shuffles!");
22899 // We can't check for single use, we have to check that this shuffle is the
22901 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22902 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22903 HasPSHUFB, DAG, DCI, Subtarget))
22908 // Minor canonicalization of the accumulated shuffle mask to make it easier
22909 // to match below. All this does is detect masks with squential pairs of
22910 // elements, and shrink them to the half-width mask. It does this in a loop
22911 // so it will reduce the size of the mask to the minimal width mask which
22912 // performs an equivalent shuffle.
22913 SmallVector<int, 16> WidenedMask;
22914 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22915 Mask = std::move(WidenedMask);
22916 WidenedMask.clear();
22919 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22923 /// \brief Get the PSHUF-style mask from PSHUF node.
22925 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22926 /// PSHUF-style masks that can be reused with such instructions.
22927 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22928 MVT VT = N.getSimpleValueType();
22929 SmallVector<int, 4> Mask;
22931 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22935 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22936 // matter. Check that the upper masks are repeats and remove them.
22937 if (VT.getSizeInBits() > 128) {
22938 int LaneElts = 128 / VT.getScalarSizeInBits();
22940 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22941 for (int j = 0; j < LaneElts; ++j)
22942 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22943 "Mask doesn't repeat in high 128-bit lanes!");
22945 Mask.resize(LaneElts);
22948 switch (N.getOpcode()) {
22949 case X86ISD::PSHUFD:
22951 case X86ISD::PSHUFLW:
22954 case X86ISD::PSHUFHW:
22955 Mask.erase(Mask.begin(), Mask.begin() + 4);
22956 for (int &M : Mask)
22960 llvm_unreachable("No valid shuffle instruction found!");
22964 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22966 /// We walk up the chain and look for a combinable shuffle, skipping over
22967 /// shuffles that we could hoist this shuffle's transformation past without
22968 /// altering anything.
22970 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22972 TargetLowering::DAGCombinerInfo &DCI) {
22973 assert(N.getOpcode() == X86ISD::PSHUFD &&
22974 "Called with something other than an x86 128-bit half shuffle!");
22977 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22978 // of the shuffles in the chain so that we can form a fresh chain to replace
22980 SmallVector<SDValue, 8> Chain;
22981 SDValue V = N.getOperand(0);
22982 for (; V.hasOneUse(); V = V.getOperand(0)) {
22983 switch (V.getOpcode()) {
22985 return SDValue(); // Nothing combined!
22988 // Skip bitcasts as we always know the type for the target specific
22992 case X86ISD::PSHUFD:
22993 // Found another dword shuffle.
22996 case X86ISD::PSHUFLW:
22997 // Check that the low words (being shuffled) are the identity in the
22998 // dword shuffle, and the high words are self-contained.
22999 if (Mask[0] != 0 || Mask[1] != 1 ||
23000 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
23003 Chain.push_back(V);
23006 case X86ISD::PSHUFHW:
23007 // Check that the high words (being shuffled) are the identity in the
23008 // dword shuffle, and the low words are self-contained.
23009 if (Mask[2] != 2 || Mask[3] != 3 ||
23010 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
23013 Chain.push_back(V);
23016 case X86ISD::UNPCKL:
23017 case X86ISD::UNPCKH:
23018 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
23019 // shuffle into a preceding word shuffle.
23020 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
23021 V.getSimpleValueType().getVectorElementType() != MVT::i16)
23024 // Search for a half-shuffle which we can combine with.
23025 unsigned CombineOp =
23026 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
23027 if (V.getOperand(0) != V.getOperand(1) ||
23028 !V->isOnlyUserOf(V.getOperand(0).getNode()))
23030 Chain.push_back(V);
23031 V = V.getOperand(0);
23033 switch (V.getOpcode()) {
23035 return SDValue(); // Nothing to combine.
23037 case X86ISD::PSHUFLW:
23038 case X86ISD::PSHUFHW:
23039 if (V.getOpcode() == CombineOp)
23042 Chain.push_back(V);
23046 V = V.getOperand(0);
23050 } while (V.hasOneUse());
23053 // Break out of the loop if we break out of the switch.
23057 if (!V.hasOneUse())
23058 // We fell out of the loop without finding a viable combining instruction.
23061 // Merge this node's mask and our incoming mask.
23062 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23063 for (int &M : Mask)
23065 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
23066 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23068 // Rebuild the chain around this new shuffle.
23069 while (!Chain.empty()) {
23070 SDValue W = Chain.pop_back_val();
23072 if (V.getValueType() != W.getOperand(0).getValueType())
23073 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
23075 switch (W.getOpcode()) {
23077 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
23079 case X86ISD::UNPCKL:
23080 case X86ISD::UNPCKH:
23081 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
23084 case X86ISD::PSHUFD:
23085 case X86ISD::PSHUFLW:
23086 case X86ISD::PSHUFHW:
23087 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
23091 if (V.getValueType() != N.getValueType())
23092 V = DAG.getBitcast(N.getValueType(), V);
23094 // Return the new chain to replace N.
23098 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
23101 /// We walk up the chain, skipping shuffles of the other half and looking
23102 /// through shuffles which switch halves trying to find a shuffle of the same
23103 /// pair of dwords.
23104 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
23106 TargetLowering::DAGCombinerInfo &DCI) {
23108 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
23109 "Called with something other than an x86 128-bit half shuffle!");
23111 unsigned CombineOpcode = N.getOpcode();
23113 // Walk up a single-use chain looking for a combinable shuffle.
23114 SDValue V = N.getOperand(0);
23115 for (; V.hasOneUse(); V = V.getOperand(0)) {
23116 switch (V.getOpcode()) {
23118 return false; // Nothing combined!
23121 // Skip bitcasts as we always know the type for the target specific
23125 case X86ISD::PSHUFLW:
23126 case X86ISD::PSHUFHW:
23127 if (V.getOpcode() == CombineOpcode)
23130 // Other-half shuffles are no-ops.
23133 // Break out of the loop if we break out of the switch.
23137 if (!V.hasOneUse())
23138 // We fell out of the loop without finding a viable combining instruction.
23141 // Combine away the bottom node as its shuffle will be accumulated into
23142 // a preceding shuffle.
23143 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23145 // Record the old value.
23148 // Merge this node's mask and our incoming mask (adjusted to account for all
23149 // the pshufd instructions encountered).
23150 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23151 for (int &M : Mask)
23153 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23154 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23156 // Check that the shuffles didn't cancel each other out. If not, we need to
23157 // combine to the new one.
23159 // Replace the combinable shuffle with the combined one, updating all users
23160 // so that we re-evaluate the chain here.
23161 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23166 /// \brief Try to combine x86 target specific shuffles.
23167 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23168 TargetLowering::DAGCombinerInfo &DCI,
23169 const X86Subtarget *Subtarget) {
23171 MVT VT = N.getSimpleValueType();
23172 SmallVector<int, 4> Mask;
23174 switch (N.getOpcode()) {
23175 case X86ISD::PSHUFD:
23176 case X86ISD::PSHUFLW:
23177 case X86ISD::PSHUFHW:
23178 Mask = getPSHUFShuffleMask(N);
23179 assert(Mask.size() == 4);
23181 case X86ISD::UNPCKL: {
23182 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23183 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23184 // moves upper half elements into the lower half part. For example:
23186 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23188 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23190 // will be combined to:
23192 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23194 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23195 // happen due to advanced instructions.
23196 if (!VT.is128BitVector())
23199 auto Op0 = N.getOperand(0);
23200 auto Op1 = N.getOperand(1);
23201 if (Op0.getOpcode() == ISD::UNDEF &&
23202 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23203 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23205 unsigned NumElts = VT.getVectorNumElements();
23206 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23207 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23210 auto ShufOp = Op1.getOperand(0);
23211 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23212 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23220 // Nuke no-op shuffles that show up after combining.
23221 if (isNoopShuffleMask(Mask))
23222 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23224 // Look for simplifications involving one or two shuffle instructions.
23225 SDValue V = N.getOperand(0);
23226 switch (N.getOpcode()) {
23229 case X86ISD::PSHUFLW:
23230 case X86ISD::PSHUFHW:
23231 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23233 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23234 return SDValue(); // We combined away this shuffle, so we're done.
23236 // See if this reduces to a PSHUFD which is no more expensive and can
23237 // combine with more operations. Note that it has to at least flip the
23238 // dwords as otherwise it would have been removed as a no-op.
23239 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23240 int DMask[] = {0, 1, 2, 3};
23241 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23242 DMask[DOffset + 0] = DOffset + 1;
23243 DMask[DOffset + 1] = DOffset + 0;
23244 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23245 V = DAG.getBitcast(DVT, V);
23246 DCI.AddToWorklist(V.getNode());
23247 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23248 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23249 DCI.AddToWorklist(V.getNode());
23250 return DAG.getBitcast(VT, V);
23253 // Look for shuffle patterns which can be implemented as a single unpack.
23254 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23255 // only works when we have a PSHUFD followed by two half-shuffles.
23256 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23257 (V.getOpcode() == X86ISD::PSHUFLW ||
23258 V.getOpcode() == X86ISD::PSHUFHW) &&
23259 V.getOpcode() != N.getOpcode() &&
23261 SDValue D = V.getOperand(0);
23262 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23263 D = D.getOperand(0);
23264 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23265 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23266 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23267 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23268 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23270 for (int i = 0; i < 4; ++i) {
23271 WordMask[i + NOffset] = Mask[i] + NOffset;
23272 WordMask[i + VOffset] = VMask[i] + VOffset;
23274 // Map the word mask through the DWord mask.
23276 for (int i = 0; i < 8; ++i)
23277 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23278 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23279 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23280 // We can replace all three shuffles with an unpack.
23281 V = DAG.getBitcast(VT, D.getOperand(0));
23282 DCI.AddToWorklist(V.getNode());
23283 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23292 case X86ISD::PSHUFD:
23293 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23302 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23304 /// We combine this directly on the abstract vector shuffle nodes so it is
23305 /// easier to generically match. We also insert dummy vector shuffle nodes for
23306 /// the operands which explicitly discard the lanes which are unused by this
23307 /// operation to try to flow through the rest of the combiner the fact that
23308 /// they're unused.
23309 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23311 EVT VT = N->getValueType(0);
23313 // We only handle target-independent shuffles.
23314 // FIXME: It would be easy and harmless to use the target shuffle mask
23315 // extraction tool to support more.
23316 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23319 auto *SVN = cast<ShuffleVectorSDNode>(N);
23320 SmallVector<int, 8> Mask;
23321 for (int M : SVN->getMask())
23324 SDValue V1 = N->getOperand(0);
23325 SDValue V2 = N->getOperand(1);
23327 // We require the first shuffle operand to be the FSUB node, and the second to
23328 // be the FADD node.
23329 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23330 ShuffleVectorSDNode::commuteMask(Mask);
23332 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23335 // If there are other uses of these operations we can't fold them.
23336 if (!V1->hasOneUse() || !V2->hasOneUse())
23339 // Ensure that both operations have the same operands. Note that we can
23340 // commute the FADD operands.
23341 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23342 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23343 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23346 // We're looking for blends between FADD and FSUB nodes. We insist on these
23347 // nodes being lined up in a specific expected pattern.
23348 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23349 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23350 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23353 // Only specific types are legal at this point, assert so we notice if and
23354 // when these change.
23355 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23356 VT == MVT::v4f64) &&
23357 "Unknown vector type encountered!");
23359 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23362 /// PerformShuffleCombine - Performs several different shuffle combines.
23363 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23364 TargetLowering::DAGCombinerInfo &DCI,
23365 const X86Subtarget *Subtarget) {
23367 SDValue N0 = N->getOperand(0);
23368 SDValue N1 = N->getOperand(1);
23369 EVT VT = N->getValueType(0);
23371 // Don't create instructions with illegal types after legalize types has run.
23372 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23373 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23376 // If we have legalized the vector types, look for blends of FADD and FSUB
23377 // nodes that we can fuse into an ADDSUB node.
23378 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23379 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23382 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23383 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23384 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23385 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23387 // During Type Legalization, when promoting illegal vector types,
23388 // the backend might introduce new shuffle dag nodes and bitcasts.
23390 // This code performs the following transformation:
23391 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23392 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23394 // We do this only if both the bitcast and the BINOP dag nodes have
23395 // one use. Also, perform this transformation only if the new binary
23396 // operation is legal. This is to avoid introducing dag nodes that
23397 // potentially need to be further expanded (or custom lowered) into a
23398 // less optimal sequence of dag nodes.
23399 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23400 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23401 N0.getOpcode() == ISD::BITCAST) {
23402 SDValue BC0 = N0.getOperand(0);
23403 EVT SVT = BC0.getValueType();
23404 unsigned Opcode = BC0.getOpcode();
23405 unsigned NumElts = VT.getVectorNumElements();
23407 if (BC0.hasOneUse() && SVT.isVector() &&
23408 SVT.getVectorNumElements() * 2 == NumElts &&
23409 TLI.isOperationLegal(Opcode, VT)) {
23410 bool CanFold = false;
23422 unsigned SVTNumElts = SVT.getVectorNumElements();
23423 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23424 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23425 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23426 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23427 CanFold = SVOp->getMaskElt(i) < 0;
23430 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23431 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23432 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23433 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23438 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23439 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23440 // consecutive, non-overlapping, and in the right order.
23441 SmallVector<SDValue, 16> Elts;
23442 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23443 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23445 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23448 if (isTargetShuffle(N->getOpcode())) {
23450 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23451 if (Shuffle.getNode())
23454 // Try recursively combining arbitrary sequences of x86 shuffle
23455 // instructions into higher-order shuffles. We do this after combining
23456 // specific PSHUF instruction sequences into their minimal form so that we
23457 // can evaluate how many specialized shuffle instructions are involved in
23458 // a particular chain.
23459 SmallVector<int, 1> NonceMask; // Just a placeholder.
23460 NonceMask.push_back(0);
23461 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23462 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23464 return SDValue(); // This routine will use CombineTo to replace N.
23470 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23471 /// specific shuffle of a load can be folded into a single element load.
23472 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23473 /// shuffles have been custom lowered so we need to handle those here.
23474 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23475 TargetLowering::DAGCombinerInfo &DCI) {
23476 if (DCI.isBeforeLegalizeOps())
23479 SDValue InVec = N->getOperand(0);
23480 SDValue EltNo = N->getOperand(1);
23482 if (!isa<ConstantSDNode>(EltNo))
23485 EVT OriginalVT = InVec.getValueType();
23487 if (InVec.getOpcode() == ISD::BITCAST) {
23488 // Don't duplicate a load with other uses.
23489 if (!InVec.hasOneUse())
23491 EVT BCVT = InVec.getOperand(0).getValueType();
23492 if (!BCVT.isVector() ||
23493 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23495 InVec = InVec.getOperand(0);
23498 EVT CurrentVT = InVec.getValueType();
23500 if (!isTargetShuffle(InVec.getOpcode()))
23503 // Don't duplicate a load with other uses.
23504 if (!InVec.hasOneUse())
23507 SmallVector<int, 16> ShuffleMask;
23509 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23510 ShuffleMask, UnaryShuffle))
23513 // Select the input vector, guarding against out of range extract vector.
23514 unsigned NumElems = CurrentVT.getVectorNumElements();
23515 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23516 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23517 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23518 : InVec.getOperand(1);
23520 // If inputs to shuffle are the same for both ops, then allow 2 uses
23521 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23522 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23524 if (LdNode.getOpcode() == ISD::BITCAST) {
23525 // Don't duplicate a load with other uses.
23526 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23529 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23530 LdNode = LdNode.getOperand(0);
23533 if (!ISD::isNormalLoad(LdNode.getNode()))
23536 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23538 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23541 EVT EltVT = N->getValueType(0);
23542 // If there's a bitcast before the shuffle, check if the load type and
23543 // alignment is valid.
23544 unsigned Align = LN0->getAlignment();
23545 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23546 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23547 EltVT.getTypeForEVT(*DAG.getContext()));
23549 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23552 // All checks match so transform back to vector_shuffle so that DAG combiner
23553 // can finish the job
23556 // Create shuffle node taking into account the case that its a unary shuffle
23557 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23558 : InVec.getOperand(1);
23559 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23560 InVec.getOperand(0), Shuffle,
23562 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23563 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23567 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23568 const X86Subtarget *Subtarget) {
23569 SDValue N0 = N->getOperand(0);
23570 EVT VT = N->getValueType(0);
23572 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23573 // special and don't usually play with other vector types, it's better to
23574 // handle them early to be sure we emit efficient code by avoiding
23575 // store-load conversions.
23576 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23577 N0.getValueType() == MVT::v2i32 &&
23578 isNullConstant(N0.getOperand(1))) {
23579 SDValue N00 = N0->getOperand(0);
23580 if (N00.getValueType() == MVT::i32)
23581 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23584 // Convert a bitcasted integer logic operation that has one bitcasted
23585 // floating-point operand and one constant operand into a floating-point
23586 // logic operation. This may create a load of the constant, but that is
23587 // cheaper than materializing the constant in an integer register and
23588 // transferring it to an SSE register or transferring the SSE operand to
23589 // integer register and back.
23591 switch (N0.getOpcode()) {
23592 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23593 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23594 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23595 default: return SDValue();
23597 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23598 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23599 isa<ConstantSDNode>(N0.getOperand(1)) &&
23600 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23601 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23602 SDValue N000 = N0.getOperand(0).getOperand(0);
23603 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23604 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23610 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23611 /// generation and convert it from being a bunch of shuffles and extracts
23612 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23613 /// storing the value and loading scalars back, while for x64 we should
23614 /// use 64-bit extracts and shifts.
23615 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23616 TargetLowering::DAGCombinerInfo &DCI) {
23617 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23620 SDValue InputVector = N->getOperand(0);
23621 SDLoc dl(InputVector);
23622 // Detect mmx to i32 conversion through a v2i32 elt extract.
23623 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23624 N->getValueType(0) == MVT::i32 &&
23625 InputVector.getValueType() == MVT::v2i32) {
23627 // The bitcast source is a direct mmx result.
23628 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23629 if (MMXSrc.getValueType() == MVT::x86mmx)
23630 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23631 N->getValueType(0),
23632 InputVector.getNode()->getOperand(0));
23634 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23635 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23636 MMXSrc.getValueType() == MVT::i64) {
23637 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23638 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23639 MMXSrcOp.getValueType() == MVT::v1i64 &&
23640 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23641 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23642 N->getValueType(0), MMXSrcOp.getOperand(0));
23646 EVT VT = N->getValueType(0);
23648 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23649 InputVector.getOpcode() == ISD::BITCAST &&
23650 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23651 uint64_t ExtractedElt =
23652 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23653 uint64_t InputValue =
23654 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23655 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23656 return DAG.getConstant(Res, dl, MVT::i1);
23658 // Only operate on vectors of 4 elements, where the alternative shuffling
23659 // gets to be more expensive.
23660 if (InputVector.getValueType() != MVT::v4i32)
23663 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23664 // single use which is a sign-extend or zero-extend, and all elements are
23666 SmallVector<SDNode *, 4> Uses;
23667 unsigned ExtractedElements = 0;
23668 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23669 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23670 if (UI.getUse().getResNo() != InputVector.getResNo())
23673 SDNode *Extract = *UI;
23674 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23677 if (Extract->getValueType(0) != MVT::i32)
23679 if (!Extract->hasOneUse())
23681 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23682 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23684 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23687 // Record which element was extracted.
23688 ExtractedElements |=
23689 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23691 Uses.push_back(Extract);
23694 // If not all the elements were used, this may not be worthwhile.
23695 if (ExtractedElements != 15)
23698 // Ok, we've now decided to do the transformation.
23699 // If 64-bit shifts are legal, use the extract-shift sequence,
23700 // otherwise bounce the vector off the cache.
23701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23704 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23705 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23706 auto &DL = DAG.getDataLayout();
23707 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23708 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23709 DAG.getConstant(0, dl, VecIdxTy));
23710 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23711 DAG.getConstant(1, dl, VecIdxTy));
23713 SDValue ShAmt = DAG.getConstant(
23714 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23715 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23716 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23717 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23718 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23719 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23720 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23722 // Store the value to a temporary stack slot.
23723 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23724 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23725 MachinePointerInfo(), false, false, 0);
23727 EVT ElementType = InputVector.getValueType().getVectorElementType();
23728 unsigned EltSize = ElementType.getSizeInBits() / 8;
23730 // Replace each use (extract) with a load of the appropriate element.
23731 for (unsigned i = 0; i < 4; ++i) {
23732 uint64_t Offset = EltSize * i;
23733 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23734 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23736 SDValue ScalarAddr =
23737 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23739 // Load the scalar.
23740 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23741 ScalarAddr, MachinePointerInfo(),
23742 false, false, false, 0);
23747 // Replace the extracts
23748 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23749 UE = Uses.end(); UI != UE; ++UI) {
23750 SDNode *Extract = *UI;
23752 SDValue Idx = Extract->getOperand(1);
23753 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23754 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23757 // The replacement was made in place; don't return anything.
23762 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23763 const X86Subtarget *Subtarget) {
23765 SDValue Cond = N->getOperand(0);
23766 SDValue LHS = N->getOperand(1);
23767 SDValue RHS = N->getOperand(2);
23769 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23770 SDValue CondSrc = Cond->getOperand(0);
23771 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23772 Cond = CondSrc->getOperand(0);
23775 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23778 // A vselect where all conditions and data are constants can be optimized into
23779 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23780 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23781 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23784 unsigned MaskValue = 0;
23785 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23788 MVT VT = N->getSimpleValueType(0);
23789 unsigned NumElems = VT.getVectorNumElements();
23790 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23791 for (unsigned i = 0; i < NumElems; ++i) {
23792 // Be sure we emit undef where we can.
23793 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23794 ShuffleMask[i] = -1;
23796 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23799 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23800 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23802 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23805 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23807 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23808 TargetLowering::DAGCombinerInfo &DCI,
23809 const X86Subtarget *Subtarget) {
23811 SDValue Cond = N->getOperand(0);
23812 // Get the LHS/RHS of the select.
23813 SDValue LHS = N->getOperand(1);
23814 SDValue RHS = N->getOperand(2);
23815 EVT VT = LHS.getValueType();
23816 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23818 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23819 // instructions match the semantics of the common C idiom x<y?x:y but not
23820 // x<=y?x:y, because of how they handle negative zero (which can be
23821 // ignored in unsafe-math mode).
23822 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23823 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23824 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23825 (Subtarget->hasSSE2() ||
23826 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23827 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23829 unsigned Opcode = 0;
23830 // Check for x CC y ? x : y.
23831 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23832 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23836 // Converting this to a min would handle NaNs incorrectly, and swapping
23837 // the operands would cause it to handle comparisons between positive
23838 // and negative zero incorrectly.
23839 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23840 if (!DAG.getTarget().Options.UnsafeFPMath &&
23841 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23843 std::swap(LHS, RHS);
23845 Opcode = X86ISD::FMIN;
23848 // Converting this to a min would handle comparisons between positive
23849 // and negative zero incorrectly.
23850 if (!DAG.getTarget().Options.UnsafeFPMath &&
23851 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23853 Opcode = X86ISD::FMIN;
23856 // Converting this to a min would handle both negative zeros and NaNs
23857 // incorrectly, but we can swap the operands to fix both.
23858 std::swap(LHS, RHS);
23862 Opcode = X86ISD::FMIN;
23866 // Converting this to a max would handle comparisons between positive
23867 // and negative zero incorrectly.
23868 if (!DAG.getTarget().Options.UnsafeFPMath &&
23869 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23871 Opcode = X86ISD::FMAX;
23874 // Converting this to a max would handle NaNs incorrectly, and swapping
23875 // the operands would cause it to handle comparisons between positive
23876 // and negative zero incorrectly.
23877 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23878 if (!DAG.getTarget().Options.UnsafeFPMath &&
23879 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23881 std::swap(LHS, RHS);
23883 Opcode = X86ISD::FMAX;
23886 // Converting this to a max would handle both negative zeros and NaNs
23887 // incorrectly, but we can swap the operands to fix both.
23888 std::swap(LHS, RHS);
23892 Opcode = X86ISD::FMAX;
23895 // Check for x CC y ? y : x -- a min/max with reversed arms.
23896 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23897 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23901 // Converting this to a min would handle comparisons between positive
23902 // and negative zero incorrectly, and swapping the operands would
23903 // cause it to handle NaNs incorrectly.
23904 if (!DAG.getTarget().Options.UnsafeFPMath &&
23905 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23906 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23908 std::swap(LHS, RHS);
23910 Opcode = X86ISD::FMIN;
23913 // Converting this to a min would handle NaNs incorrectly.
23914 if (!DAG.getTarget().Options.UnsafeFPMath &&
23915 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23917 Opcode = X86ISD::FMIN;
23920 // Converting this to a min would handle both negative zeros and NaNs
23921 // incorrectly, but we can swap the operands to fix both.
23922 std::swap(LHS, RHS);
23926 Opcode = X86ISD::FMIN;
23930 // Converting this to a max would handle NaNs incorrectly.
23931 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23933 Opcode = X86ISD::FMAX;
23936 // Converting this to a max would handle comparisons between positive
23937 // and negative zero incorrectly, and swapping the operands would
23938 // cause it to handle NaNs incorrectly.
23939 if (!DAG.getTarget().Options.UnsafeFPMath &&
23940 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23941 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23943 std::swap(LHS, RHS);
23945 Opcode = X86ISD::FMAX;
23948 // Converting this to a max would handle both negative zeros and NaNs
23949 // incorrectly, but we can swap the operands to fix both.
23950 std::swap(LHS, RHS);
23954 Opcode = X86ISD::FMAX;
23960 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23963 EVT CondVT = Cond.getValueType();
23964 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23965 CondVT.getVectorElementType() == MVT::i1) {
23966 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23967 // lowering on KNL. In this case we convert it to
23968 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23969 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23970 // Since SKX these selects have a proper lowering.
23971 EVT OpVT = LHS.getValueType();
23972 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23973 (OpVT.getVectorElementType() == MVT::i8 ||
23974 OpVT.getVectorElementType() == MVT::i16) &&
23975 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23976 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23977 DCI.AddToWorklist(Cond.getNode());
23978 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23981 // If this is a select between two integer constants, try to do some
23983 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23984 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23985 // Don't do this for crazy integer types.
23986 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23987 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23988 // so that TrueC (the true value) is larger than FalseC.
23989 bool NeedsCondInvert = false;
23991 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23992 // Efficiently invertible.
23993 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23994 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23995 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23996 NeedsCondInvert = true;
23997 std::swap(TrueC, FalseC);
24000 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
24001 if (FalseC->getAPIntValue() == 0 &&
24002 TrueC->getAPIntValue().isPowerOf2()) {
24003 if (NeedsCondInvert) // Invert the condition if needed.
24004 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24005 DAG.getConstant(1, DL, Cond.getValueType()));
24007 // Zero extend the condition if needed.
24008 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
24010 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24011 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
24012 DAG.getConstant(ShAmt, DL, MVT::i8));
24015 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
24016 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24017 if (NeedsCondInvert) // Invert the condition if needed.
24018 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24019 DAG.getConstant(1, DL, Cond.getValueType()));
24021 // Zero extend the condition if needed.
24022 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24023 FalseC->getValueType(0), Cond);
24024 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24025 SDValue(FalseC, 0));
24028 // Optimize cases that will turn into an LEA instruction. This requires
24029 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24030 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24031 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24032 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24034 bool isFastMultiplier = false;
24036 switch ((unsigned char)Diff) {
24038 case 1: // result = add base, cond
24039 case 2: // result = lea base( , cond*2)
24040 case 3: // result = lea base(cond, cond*2)
24041 case 4: // result = lea base( , cond*4)
24042 case 5: // result = lea base(cond, cond*4)
24043 case 8: // result = lea base( , cond*8)
24044 case 9: // result = lea base(cond, cond*8)
24045 isFastMultiplier = true;
24050 if (isFastMultiplier) {
24051 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24052 if (NeedsCondInvert) // Invert the condition if needed.
24053 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24054 DAG.getConstant(1, DL, Cond.getValueType()));
24056 // Zero extend the condition if needed.
24057 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24059 // Scale the condition by the difference.
24061 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24062 DAG.getConstant(Diff, DL,
24063 Cond.getValueType()));
24065 // Add the base if non-zero.
24066 if (FalseC->getAPIntValue() != 0)
24067 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24068 SDValue(FalseC, 0));
24075 // Canonicalize max and min:
24076 // (x > y) ? x : y -> (x >= y) ? x : y
24077 // (x < y) ? x : y -> (x <= y) ? x : y
24078 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
24079 // the need for an extra compare
24080 // against zero. e.g.
24081 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
24083 // testl %edi, %edi
24085 // cmovgl %edi, %eax
24089 // cmovsl %eax, %edi
24090 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24091 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24092 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24093 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24098 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
24099 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
24100 Cond.getOperand(0), Cond.getOperand(1), NewCC);
24101 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
24106 // Early exit check
24107 if (!TLI.isTypeLegal(VT))
24110 // Match VSELECTs into subs with unsigned saturation.
24111 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24112 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
24113 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
24114 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
24115 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24117 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
24118 // left side invert the predicate to simplify logic below.
24120 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
24122 CC = ISD::getSetCCInverse(CC, true);
24123 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
24127 if (Other.getNode() && Other->getNumOperands() == 2 &&
24128 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
24129 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
24130 SDValue CondRHS = Cond->getOperand(1);
24132 // Look for a general sub with unsigned saturation first.
24133 // x >= y ? x-y : 0 --> subus x, y
24134 // x > y ? x-y : 0 --> subus x, y
24135 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
24136 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
24137 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
24139 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
24140 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
24141 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
24142 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
24143 // If the RHS is a constant we have to reverse the const
24144 // canonicalization.
24145 // x > C-1 ? x+-C : 0 --> subus x, C
24146 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24147 CondRHSConst->getAPIntValue() ==
24148 (-OpRHSConst->getAPIntValue() - 1))
24149 return DAG.getNode(
24150 X86ISD::SUBUS, DL, VT, OpLHS,
24151 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
24153 // Another special case: If C was a sign bit, the sub has been
24154 // canonicalized into a xor.
24155 // FIXME: Would it be better to use computeKnownBits to determine
24156 // whether it's safe to decanonicalize the xor?
24157 // x s< 0 ? x^C : 0 --> subus x, C
24158 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24159 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
24160 OpRHSConst->getAPIntValue().isSignBit())
24161 // Note that we have to rebuild the RHS constant here to ensure we
24162 // don't rely on particular values of undef lanes.
24163 return DAG.getNode(
24164 X86ISD::SUBUS, DL, VT, OpLHS,
24165 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24170 // Simplify vector selection if condition value type matches vselect
24172 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24173 assert(Cond.getValueType().isVector() &&
24174 "vector select expects a vector selector!");
24176 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24177 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24179 // Try invert the condition if true value is not all 1s and false value
24181 if (!TValIsAllOnes && !FValIsAllZeros &&
24182 // Check if the selector will be produced by CMPP*/PCMP*
24183 Cond.getOpcode() == ISD::SETCC &&
24184 // Check if SETCC has already been promoted
24185 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24187 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24188 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24190 if (TValIsAllZeros || FValIsAllOnes) {
24191 SDValue CC = Cond.getOperand(2);
24192 ISD::CondCode NewCC =
24193 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24194 Cond.getOperand(0).getValueType().isInteger());
24195 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24196 std::swap(LHS, RHS);
24197 TValIsAllOnes = FValIsAllOnes;
24198 FValIsAllZeros = TValIsAllZeros;
24202 if (TValIsAllOnes || FValIsAllZeros) {
24205 if (TValIsAllOnes && FValIsAllZeros)
24207 else if (TValIsAllOnes)
24209 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24210 else if (FValIsAllZeros)
24211 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24212 DAG.getBitcast(CondVT, LHS));
24214 return DAG.getBitcast(VT, Ret);
24218 // We should generate an X86ISD::BLENDI from a vselect if its argument
24219 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24220 // constants. This specific pattern gets generated when we split a
24221 // selector for a 512 bit vector in a machine without AVX512 (but with
24222 // 256-bit vectors), during legalization:
24224 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24226 // Iff we find this pattern and the build_vectors are built from
24227 // constants, we translate the vselect into a shuffle_vector that we
24228 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24229 if ((N->getOpcode() == ISD::VSELECT ||
24230 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24231 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24232 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24233 if (Shuffle.getNode())
24237 // If this is a *dynamic* select (non-constant condition) and we can match
24238 // this node with one of the variable blend instructions, restructure the
24239 // condition so that the blends can use the high bit of each element and use
24240 // SimplifyDemandedBits to simplify the condition operand.
24241 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24242 !DCI.isBeforeLegalize() &&
24243 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24244 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24246 // Don't optimize vector selects that map to mask-registers.
24250 // We can only handle the cases where VSELECT is directly legal on the
24251 // subtarget. We custom lower VSELECT nodes with constant conditions and
24252 // this makes it hard to see whether a dynamic VSELECT will correctly
24253 // lower, so we both check the operation's status and explicitly handle the
24254 // cases where a *dynamic* blend will fail even though a constant-condition
24255 // blend could be custom lowered.
24256 // FIXME: We should find a better way to handle this class of problems.
24257 // Potentially, we should combine constant-condition vselect nodes
24258 // pre-legalization into shuffles and not mark as many types as custom
24260 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24262 // FIXME: We don't support i16-element blends currently. We could and
24263 // should support them by making *all* the bits in the condition be set
24264 // rather than just the high bit and using an i8-element blend.
24265 if (VT.getVectorElementType() == MVT::i16)
24267 // Dynamic blending was only available from SSE4.1 onward.
24268 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24270 // Byte blends are only available in AVX2
24271 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24274 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24275 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24277 APInt KnownZero, KnownOne;
24278 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24279 DCI.isBeforeLegalizeOps());
24280 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24281 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24283 // If we changed the computation somewhere in the DAG, this change
24284 // will affect all users of Cond.
24285 // Make sure it is fine and update all the nodes so that we do not
24286 // use the generic VSELECT anymore. Otherwise, we may perform
24287 // wrong optimizations as we messed up with the actual expectation
24288 // for the vector boolean values.
24289 if (Cond != TLO.Old) {
24290 // Check all uses of that condition operand to check whether it will be
24291 // consumed by non-BLEND instructions, which may depend on all bits are
24293 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24295 if (I->getOpcode() != ISD::VSELECT)
24296 // TODO: Add other opcodes eventually lowered into BLEND.
24299 // Update all the users of the condition, before committing the change,
24300 // so that the VSELECT optimizations that expect the correct vector
24301 // boolean value will not be triggered.
24302 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24304 DAG.ReplaceAllUsesOfValueWith(
24306 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24307 Cond, I->getOperand(1), I->getOperand(2)));
24308 DCI.CommitTargetLoweringOpt(TLO);
24311 // At this point, only Cond is changed. Change the condition
24312 // just for N to keep the opportunity to optimize all other
24313 // users their own way.
24314 DAG.ReplaceAllUsesOfValueWith(
24316 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24317 TLO.New, N->getOperand(1), N->getOperand(2)));
24325 // Check whether a boolean test is testing a boolean value generated by
24326 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24329 // Simplify the following patterns:
24330 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24331 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24332 // to (Op EFLAGS Cond)
24334 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24335 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24336 // to (Op EFLAGS !Cond)
24338 // where Op could be BRCOND or CMOV.
24340 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24341 // Quit if not CMP and SUB with its value result used.
24342 if (Cmp.getOpcode() != X86ISD::CMP &&
24343 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24346 // Quit if not used as a boolean value.
24347 if (CC != X86::COND_E && CC != X86::COND_NE)
24350 // Check CMP operands. One of them should be 0 or 1 and the other should be
24351 // an SetCC or extended from it.
24352 SDValue Op1 = Cmp.getOperand(0);
24353 SDValue Op2 = Cmp.getOperand(1);
24356 const ConstantSDNode* C = nullptr;
24357 bool needOppositeCond = (CC == X86::COND_E);
24358 bool checkAgainstTrue = false; // Is it a comparison against 1?
24360 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24362 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24364 else // Quit if all operands are not constants.
24367 if (C->getZExtValue() == 1) {
24368 needOppositeCond = !needOppositeCond;
24369 checkAgainstTrue = true;
24370 } else if (C->getZExtValue() != 0)
24371 // Quit if the constant is neither 0 or 1.
24374 bool truncatedToBoolWithAnd = false;
24375 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24376 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24377 SetCC.getOpcode() == ISD::TRUNCATE ||
24378 SetCC.getOpcode() == ISD::AND) {
24379 if (SetCC.getOpcode() == ISD::AND) {
24381 if (isOneConstant(SetCC.getOperand(0)))
24383 if (isOneConstant(SetCC.getOperand(1)))
24387 SetCC = SetCC.getOperand(OpIdx);
24388 truncatedToBoolWithAnd = true;
24390 SetCC = SetCC.getOperand(0);
24393 switch (SetCC.getOpcode()) {
24394 case X86ISD::SETCC_CARRY:
24395 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24396 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24397 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24398 // truncated to i1 using 'and'.
24399 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24401 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24402 "Invalid use of SETCC_CARRY!");
24404 case X86ISD::SETCC:
24405 // Set the condition code or opposite one if necessary.
24406 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24407 if (needOppositeCond)
24408 CC = X86::GetOppositeBranchCondition(CC);
24409 return SetCC.getOperand(1);
24410 case X86ISD::CMOV: {
24411 // Check whether false/true value has canonical one, i.e. 0 or 1.
24412 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24413 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24414 // Quit if true value is not a constant.
24417 // Quit if false value is not a constant.
24419 SDValue Op = SetCC.getOperand(0);
24420 // Skip 'zext' or 'trunc' node.
24421 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24422 Op.getOpcode() == ISD::TRUNCATE)
24423 Op = Op.getOperand(0);
24424 // A special case for rdrand/rdseed, where 0 is set if false cond is
24426 if ((Op.getOpcode() != X86ISD::RDRAND &&
24427 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24430 // Quit if false value is not the constant 0 or 1.
24431 bool FValIsFalse = true;
24432 if (FVal && FVal->getZExtValue() != 0) {
24433 if (FVal->getZExtValue() != 1)
24435 // If FVal is 1, opposite cond is needed.
24436 needOppositeCond = !needOppositeCond;
24437 FValIsFalse = false;
24439 // Quit if TVal is not the constant opposite of FVal.
24440 if (FValIsFalse && TVal->getZExtValue() != 1)
24442 if (!FValIsFalse && TVal->getZExtValue() != 0)
24444 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24445 if (needOppositeCond)
24446 CC = X86::GetOppositeBranchCondition(CC);
24447 return SetCC.getOperand(3);
24454 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24456 /// (X86or (X86setcc) (X86setcc))
24457 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24458 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24459 X86::CondCode &CC1, SDValue &Flags,
24461 if (Cond->getOpcode() == X86ISD::CMP) {
24462 if (!isNullConstant(Cond->getOperand(1)))
24465 Cond = Cond->getOperand(0);
24470 SDValue SetCC0, SetCC1;
24471 switch (Cond->getOpcode()) {
24472 default: return false;
24479 SetCC0 = Cond->getOperand(0);
24480 SetCC1 = Cond->getOperand(1);
24484 // Make sure we have SETCC nodes, using the same flags value.
24485 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24486 SetCC1.getOpcode() != X86ISD::SETCC ||
24487 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24490 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24491 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24492 Flags = SetCC0->getOperand(1);
24496 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24497 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24498 TargetLowering::DAGCombinerInfo &DCI,
24499 const X86Subtarget *Subtarget) {
24502 // If the flag operand isn't dead, don't touch this CMOV.
24503 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24506 SDValue FalseOp = N->getOperand(0);
24507 SDValue TrueOp = N->getOperand(1);
24508 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24509 SDValue Cond = N->getOperand(3);
24511 if (CC == X86::COND_E || CC == X86::COND_NE) {
24512 switch (Cond.getOpcode()) {
24516 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24517 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24518 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24524 Flags = checkBoolTestSetCCCombine(Cond, CC);
24525 if (Flags.getNode() &&
24526 // Extra check as FCMOV only supports a subset of X86 cond.
24527 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24528 SDValue Ops[] = { FalseOp, TrueOp,
24529 DAG.getConstant(CC, DL, MVT::i8), Flags };
24530 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24533 // If this is a select between two integer constants, try to do some
24534 // optimizations. Note that the operands are ordered the opposite of SELECT
24536 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24537 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24538 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24539 // larger than FalseC (the false value).
24540 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24541 CC = X86::GetOppositeBranchCondition(CC);
24542 std::swap(TrueC, FalseC);
24543 std::swap(TrueOp, FalseOp);
24546 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24547 // This is efficient for any integer data type (including i8/i16) and
24549 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24550 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24551 DAG.getConstant(CC, DL, MVT::i8), Cond);
24553 // Zero extend the condition if needed.
24554 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24556 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24557 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24558 DAG.getConstant(ShAmt, DL, MVT::i8));
24559 if (N->getNumValues() == 2) // Dead flag value?
24560 return DCI.CombineTo(N, Cond, SDValue());
24564 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24565 // for any integer data type, including i8/i16.
24566 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24567 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24568 DAG.getConstant(CC, DL, MVT::i8), Cond);
24570 // Zero extend the condition if needed.
24571 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24572 FalseC->getValueType(0), Cond);
24573 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24574 SDValue(FalseC, 0));
24576 if (N->getNumValues() == 2) // Dead flag value?
24577 return DCI.CombineTo(N, Cond, SDValue());
24581 // Optimize cases that will turn into an LEA instruction. This requires
24582 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24583 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24584 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24585 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24587 bool isFastMultiplier = false;
24589 switch ((unsigned char)Diff) {
24591 case 1: // result = add base, cond
24592 case 2: // result = lea base( , cond*2)
24593 case 3: // result = lea base(cond, cond*2)
24594 case 4: // result = lea base( , cond*4)
24595 case 5: // result = lea base(cond, cond*4)
24596 case 8: // result = lea base( , cond*8)
24597 case 9: // result = lea base(cond, cond*8)
24598 isFastMultiplier = true;
24603 if (isFastMultiplier) {
24604 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24605 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24606 DAG.getConstant(CC, DL, MVT::i8), Cond);
24607 // Zero extend the condition if needed.
24608 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24610 // Scale the condition by the difference.
24612 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24613 DAG.getConstant(Diff, DL, Cond.getValueType()));
24615 // Add the base if non-zero.
24616 if (FalseC->getAPIntValue() != 0)
24617 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24618 SDValue(FalseC, 0));
24619 if (N->getNumValues() == 2) // Dead flag value?
24620 return DCI.CombineTo(N, Cond, SDValue());
24627 // Handle these cases:
24628 // (select (x != c), e, c) -> select (x != c), e, x),
24629 // (select (x == c), c, e) -> select (x == c), x, e)
24630 // where the c is an integer constant, and the "select" is the combination
24631 // of CMOV and CMP.
24633 // The rationale for this change is that the conditional-move from a constant
24634 // needs two instructions, however, conditional-move from a register needs
24635 // only one instruction.
24637 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24638 // some instruction-combining opportunities. This opt needs to be
24639 // postponed as late as possible.
24641 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24642 // the DCI.xxxx conditions are provided to postpone the optimization as
24643 // late as possible.
24645 ConstantSDNode *CmpAgainst = nullptr;
24646 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24647 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24648 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24650 if (CC == X86::COND_NE &&
24651 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24652 CC = X86::GetOppositeBranchCondition(CC);
24653 std::swap(TrueOp, FalseOp);
24656 if (CC == X86::COND_E &&
24657 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24658 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24659 DAG.getConstant(CC, DL, MVT::i8), Cond };
24660 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24665 // Fold and/or of setcc's to double CMOV:
24666 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24667 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24669 // This combine lets us generate:
24670 // cmovcc1 (jcc1 if we don't have CMOV)
24676 // cmovne (jne if we don't have CMOV)
24677 // When we can't use the CMOV instruction, it might increase branch
24679 // When we can use CMOV, or when there is no mispredict, this improves
24680 // throughput and reduces register pressure.
24682 if (CC == X86::COND_NE) {
24684 X86::CondCode CC0, CC1;
24686 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24688 std::swap(FalseOp, TrueOp);
24689 CC0 = X86::GetOppositeBranchCondition(CC0);
24690 CC1 = X86::GetOppositeBranchCondition(CC1);
24693 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24695 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24696 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24697 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24698 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24706 /// PerformMulCombine - Optimize a single multiply with constant into two
24707 /// in order to implement it with two cheaper instructions, e.g.
24708 /// LEA + SHL, LEA + LEA.
24709 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24710 TargetLowering::DAGCombinerInfo &DCI) {
24711 // An imul is usually smaller than the alternative sequence.
24712 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24715 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24718 EVT VT = N->getValueType(0);
24719 if (VT != MVT::i64 && VT != MVT::i32)
24722 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24725 uint64_t MulAmt = C->getZExtValue();
24726 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24729 uint64_t MulAmt1 = 0;
24730 uint64_t MulAmt2 = 0;
24731 if ((MulAmt % 9) == 0) {
24733 MulAmt2 = MulAmt / 9;
24734 } else if ((MulAmt % 5) == 0) {
24736 MulAmt2 = MulAmt / 5;
24737 } else if ((MulAmt % 3) == 0) {
24739 MulAmt2 = MulAmt / 3;
24745 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24747 if (isPowerOf2_64(MulAmt2) &&
24748 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24749 // If second multiplifer is pow2, issue it first. We want the multiply by
24750 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24752 std::swap(MulAmt1, MulAmt2);
24754 if (isPowerOf2_64(MulAmt1))
24755 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24756 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24758 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24759 DAG.getConstant(MulAmt1, DL, VT));
24761 if (isPowerOf2_64(MulAmt2))
24762 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24763 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24765 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24766 DAG.getConstant(MulAmt2, DL, VT));
24770 uint64_t MaxVal = VT == MVT::i64 ? UINT64_MAX : UINT32_MAX;
24771 assert(MulAmt != 0 && MulAmt != MaxVal &&
24772 "Both cases that could cause potential "
24773 "overflows should have already been handled.");
24774 if (isPowerOf2_64(MulAmt - 1))
24775 // (mul x, 2^N + 1) => (add (shl x, N), x)
24776 NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
24777 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24778 DAG.getConstant(Log2_64(MulAmt - 1), DL,
24781 else if (isPowerOf2_64(MulAmt + 1))
24782 // (mul x, 2^N - 1) => (sub (shl x, N), x)
24783 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getNode(ISD::SHL, DL, VT,
24785 DAG.getConstant(Log2_64(MulAmt + 1),
24786 DL, MVT::i8)), N->getOperand(0));
24790 // Do not add new nodes to DAG combiner worklist.
24791 DCI.CombineTo(N, NewMul, false);
24796 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24797 SDValue N0 = N->getOperand(0);
24798 SDValue N1 = N->getOperand(1);
24799 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24800 EVT VT = N0.getValueType();
24802 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24803 // since the result of setcc_c is all zero's or all ones.
24804 if (VT.isInteger() && !VT.isVector() &&
24805 N1C && N0.getOpcode() == ISD::AND &&
24806 N0.getOperand(1).getOpcode() == ISD::Constant) {
24807 SDValue N00 = N0.getOperand(0);
24808 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24809 APInt ShAmt = N1C->getAPIntValue();
24810 Mask = Mask.shl(ShAmt);
24811 bool MaskOK = false;
24812 // We can handle cases concerning bit-widening nodes containing setcc_c if
24813 // we carefully interrogate the mask to make sure we are semantics
24815 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24816 // of the underlying setcc_c operation if the setcc_c was zero extended.
24817 // Consider the following example:
24818 // zext(setcc_c) -> i32 0x0000FFFF
24819 // c1 -> i32 0x0000FFFF
24820 // c2 -> i32 0x00000001
24821 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24822 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24823 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24825 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24826 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24828 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24829 N00.getOpcode() == ISD::ANY_EXTEND) &&
24830 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24831 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24833 if (MaskOK && Mask != 0) {
24835 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24839 // Hardware support for vector shifts is sparse which makes us scalarize the
24840 // vector operations in many cases. Also, on sandybridge ADD is faster than
24842 // (shl V, 1) -> add V,V
24843 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24844 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24845 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24846 // We shift all of the values by one. In many cases we do not have
24847 // hardware support for this operation. This is better expressed as an ADD
24849 if (N1SplatC->getAPIntValue() == 1)
24850 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24856 /// \brief Returns a vector of 0s if the node in input is a vector logical
24857 /// shift by a constant amount which is known to be bigger than or equal
24858 /// to the vector element size in bits.
24859 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24860 const X86Subtarget *Subtarget) {
24861 EVT VT = N->getValueType(0);
24863 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24864 (!Subtarget->hasInt256() ||
24865 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24868 SDValue Amt = N->getOperand(1);
24870 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24871 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24872 APInt ShiftAmt = AmtSplat->getAPIntValue();
24873 unsigned MaxAmount =
24874 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24876 // SSE2/AVX2 logical shifts always return a vector of 0s
24877 // if the shift amount is bigger than or equal to
24878 // the element size. The constant shift amount will be
24879 // encoded as a 8-bit immediate.
24880 if (ShiftAmt.trunc(8).uge(MaxAmount))
24881 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);
24887 /// PerformShiftCombine - Combine shifts.
24888 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24889 TargetLowering::DAGCombinerInfo &DCI,
24890 const X86Subtarget *Subtarget) {
24891 if (N->getOpcode() == ISD::SHL)
24892 if (SDValue V = PerformSHLCombine(N, DAG))
24895 // Try to fold this logical shift into a zero vector.
24896 if (N->getOpcode() != ISD::SRA)
24897 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24903 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24904 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24905 // and friends. Likewise for OR -> CMPNEQSS.
24906 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24907 TargetLowering::DAGCombinerInfo &DCI,
24908 const X86Subtarget *Subtarget) {
24911 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24912 // we're requiring SSE2 for both.
24913 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24914 SDValue N0 = N->getOperand(0);
24915 SDValue N1 = N->getOperand(1);
24916 SDValue CMP0 = N0->getOperand(1);
24917 SDValue CMP1 = N1->getOperand(1);
24920 // The SETCCs should both refer to the same CMP.
24921 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24924 SDValue CMP00 = CMP0->getOperand(0);
24925 SDValue CMP01 = CMP0->getOperand(1);
24926 EVT VT = CMP00.getValueType();
24928 if (VT == MVT::f32 || VT == MVT::f64) {
24929 bool ExpectingFlags = false;
24930 // Check for any users that want flags:
24931 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24932 !ExpectingFlags && UI != UE; ++UI)
24933 switch (UI->getOpcode()) {
24938 ExpectingFlags = true;
24940 case ISD::CopyToReg:
24941 case ISD::SIGN_EXTEND:
24942 case ISD::ZERO_EXTEND:
24943 case ISD::ANY_EXTEND:
24947 if (!ExpectingFlags) {
24948 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24949 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24951 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24952 X86::CondCode tmp = cc0;
24957 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24958 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24959 // FIXME: need symbolic constants for these magic numbers.
24960 // See X86ATTInstPrinter.cpp:printSSECC().
24961 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24962 if (Subtarget->hasAVX512()) {
24963 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24965 DAG.getConstant(x86cc, DL, MVT::i8));
24966 if (N->getValueType(0) != MVT::i1)
24967 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24971 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24972 CMP00.getValueType(), CMP00, CMP01,
24973 DAG.getConstant(x86cc, DL,
24976 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24977 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24979 if (is64BitFP && !Subtarget->is64Bit()) {
24980 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24981 // 64-bit integer, since that's not a legal type. Since
24982 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24983 // bits, but can do this little dance to extract the lowest 32 bits
24984 // and work with those going forward.
24985 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24987 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24988 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24989 Vector32, DAG.getIntPtrConstant(0, DL));
24993 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24994 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24995 DAG.getConstant(1, DL, IntVT));
24996 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24998 return OneBitOfTruth;
25006 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
25007 /// so it can be folded inside ANDNP.
25008 static bool CanFoldXORWithAllOnes(const SDNode *N) {
25009 EVT VT = N->getValueType(0);
25011 // Match direct AllOnes for 128 and 256-bit vectors
25012 if (ISD::isBuildVectorAllOnes(N))
25015 // Look through a bit convert.
25016 if (N->getOpcode() == ISD::BITCAST)
25017 N = N->getOperand(0).getNode();
25019 // Sometimes the operand may come from a insert_subvector building a 256-bit
25021 if (VT.is256BitVector() &&
25022 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
25023 SDValue V1 = N->getOperand(0);
25024 SDValue V2 = N->getOperand(1);
25026 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
25027 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
25028 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
25029 ISD::isBuildVectorAllOnes(V2.getNode()))
25036 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
25037 // register. In most cases we actually compare or select YMM-sized registers
25038 // and mixing the two types creates horrible code. This method optimizes
25039 // some of the transition sequences.
25040 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
25041 TargetLowering::DAGCombinerInfo &DCI,
25042 const X86Subtarget *Subtarget) {
25043 EVT VT = N->getValueType(0);
25044 if (!VT.is256BitVector())
25047 assert((N->getOpcode() == ISD::ANY_EXTEND ||
25048 N->getOpcode() == ISD::ZERO_EXTEND ||
25049 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
25051 SDValue Narrow = N->getOperand(0);
25052 EVT NarrowVT = Narrow->getValueType(0);
25053 if (!NarrowVT.is128BitVector())
25056 if (Narrow->getOpcode() != ISD::XOR &&
25057 Narrow->getOpcode() != ISD::AND &&
25058 Narrow->getOpcode() != ISD::OR)
25061 SDValue N0 = Narrow->getOperand(0);
25062 SDValue N1 = Narrow->getOperand(1);
25065 // The Left side has to be a trunc.
25066 if (N0.getOpcode() != ISD::TRUNCATE)
25069 // The type of the truncated inputs.
25070 EVT WideVT = N0->getOperand(0)->getValueType(0);
25074 // The right side has to be a 'trunc' or a constant vector.
25075 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
25076 ConstantSDNode *RHSConstSplat = nullptr;
25077 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
25078 RHSConstSplat = RHSBV->getConstantSplatNode();
25079 if (!RHSTrunc && !RHSConstSplat)
25082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25084 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25087 // Set N0 and N1 to hold the inputs to the new wide operation.
25088 N0 = N0->getOperand(0);
25089 if (RHSConstSplat) {
25090 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
25091 SDValue(RHSConstSplat, 0));
25092 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
25093 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
25094 } else if (RHSTrunc) {
25095 N1 = N1->getOperand(0);
25098 // Generate the wide operation.
25099 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
25100 unsigned Opcode = N->getOpcode();
25102 case ISD::ANY_EXTEND:
25104 case ISD::ZERO_EXTEND: {
25105 unsigned InBits = NarrowVT.getScalarSizeInBits();
25106 APInt Mask = APInt::getAllOnesValue(InBits);
25107 Mask = Mask.zext(VT.getScalarSizeInBits());
25108 return DAG.getNode(ISD::AND, DL, VT,
25109 Op, DAG.getConstant(Mask, DL, VT));
25111 case ISD::SIGN_EXTEND:
25112 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
25113 Op, DAG.getValueType(NarrowVT));
25115 llvm_unreachable("Unexpected opcode");
25119 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
25120 TargetLowering::DAGCombinerInfo &DCI,
25121 const X86Subtarget *Subtarget) {
25122 SDValue N0 = N->getOperand(0);
25123 SDValue N1 = N->getOperand(1);
25126 // A vector zext_in_reg may be represented as a shuffle,
25127 // feeding into a bitcast (this represents anyext) feeding into
25128 // an and with a mask.
25129 // We'd like to try to combine that into a shuffle with zero
25130 // plus a bitcast, removing the and.
25131 if (N0.getOpcode() != ISD::BITCAST ||
25132 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
25135 // The other side of the AND should be a splat of 2^C, where C
25136 // is the number of bits in the source type.
25137 if (N1.getOpcode() == ISD::BITCAST)
25138 N1 = N1.getOperand(0);
25139 if (N1.getOpcode() != ISD::BUILD_VECTOR)
25141 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
25143 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
25144 EVT SrcType = Shuffle->getValueType(0);
25146 // We expect a single-source shuffle
25147 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
25150 unsigned SrcSize = SrcType.getScalarSizeInBits();
25152 APInt SplatValue, SplatUndef;
25153 unsigned SplatBitSize;
25155 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
25156 SplatBitSize, HasAnyUndefs))
25159 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
25160 // Make sure the splat matches the mask we expect
25161 if (SplatBitSize > ResSize ||
25162 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
25165 // Make sure the input and output size make sense
25166 if (SrcSize >= ResSize || ResSize % SrcSize)
25169 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
25170 // The number of u's between each two values depends on the ratio between
25171 // the source and dest type.
25172 unsigned ZextRatio = ResSize / SrcSize;
25173 bool IsZext = true;
25174 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
25175 if (i % ZextRatio) {
25176 if (Shuffle->getMaskElt(i) > 0) {
25182 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
25183 // Expected element number
25193 // Ok, perform the transformation - replace the shuffle with
25194 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25195 // (instead of undef) where the k elements come from the zero vector.
25196 SmallVector<int, 8> Mask;
25197 unsigned NumElems = SrcType.getVectorNumElements();
25198 for (unsigned i = 0; i < NumElems; ++i)
25200 Mask.push_back(NumElems);
25202 Mask.push_back(i / ZextRatio);
25204 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25205 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25206 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25209 /// If both input operands of a logic op are being cast from floating point
25210 /// types, try to convert this into a floating point logic node to avoid
25211 /// unnecessary moves from SSE to integer registers.
25212 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25213 const X86Subtarget *Subtarget) {
25214 unsigned FPOpcode = ISD::DELETED_NODE;
25215 if (N->getOpcode() == ISD::AND)
25216 FPOpcode = X86ISD::FAND;
25217 else if (N->getOpcode() == ISD::OR)
25218 FPOpcode = X86ISD::FOR;
25219 else if (N->getOpcode() == ISD::XOR)
25220 FPOpcode = X86ISD::FXOR;
25222 assert(FPOpcode != ISD::DELETED_NODE &&
25223 "Unexpected input node for FP logic conversion");
25225 EVT VT = N->getValueType(0);
25226 SDValue N0 = N->getOperand(0);
25227 SDValue N1 = N->getOperand(1);
25229 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25230 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25231 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25232 SDValue N00 = N0.getOperand(0);
25233 SDValue N10 = N1.getOperand(0);
25234 EVT N00Type = N00.getValueType();
25235 EVT N10Type = N10.getValueType();
25236 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25237 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25238 return DAG.getBitcast(VT, FPLogic);
25244 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25245 TargetLowering::DAGCombinerInfo &DCI,
25246 const X86Subtarget *Subtarget) {
25247 if (DCI.isBeforeLegalizeOps())
25250 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25253 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25256 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25259 EVT VT = N->getValueType(0);
25260 SDValue N0 = N->getOperand(0);
25261 SDValue N1 = N->getOperand(1);
25264 // Create BEXTR instructions
25265 // BEXTR is ((X >> imm) & (2**size-1))
25266 if (VT == MVT::i32 || VT == MVT::i64) {
25267 // Check for BEXTR.
25268 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25269 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25270 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25271 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25272 if (MaskNode && ShiftNode) {
25273 uint64_t Mask = MaskNode->getZExtValue();
25274 uint64_t Shift = ShiftNode->getZExtValue();
25275 if (isMask_64(Mask)) {
25276 uint64_t MaskSize = countPopulation(Mask);
25277 if (Shift + MaskSize <= VT.getSizeInBits())
25278 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25279 DAG.getConstant(Shift | (MaskSize << 8), DL,
25288 // Want to form ANDNP nodes:
25289 // 1) In the hopes of then easily combining them with OR and AND nodes
25290 // to form PBLEND/PSIGN.
25291 // 2) To match ANDN packed intrinsics
25292 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25295 // Check LHS for vnot
25296 if (N0.getOpcode() == ISD::XOR &&
25297 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25298 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25299 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25301 // Check RHS for vnot
25302 if (N1.getOpcode() == ISD::XOR &&
25303 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25304 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25305 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25310 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25311 TargetLowering::DAGCombinerInfo &DCI,
25312 const X86Subtarget *Subtarget) {
25313 if (DCI.isBeforeLegalizeOps())
25316 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25319 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25322 SDValue N0 = N->getOperand(0);
25323 SDValue N1 = N->getOperand(1);
25324 EVT VT = N->getValueType(0);
25326 // look for psign/blend
25327 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25328 if (!Subtarget->hasSSSE3() ||
25329 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25332 // Canonicalize pandn to RHS
25333 if (N0.getOpcode() == X86ISD::ANDNP)
25335 // or (and (m, y), (pandn m, x))
25336 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25337 SDValue Mask = N1.getOperand(0);
25338 SDValue X = N1.getOperand(1);
25340 if (N0.getOperand(0) == Mask)
25341 Y = N0.getOperand(1);
25342 if (N0.getOperand(1) == Mask)
25343 Y = N0.getOperand(0);
25345 // Check to see if the mask appeared in both the AND and ANDNP and
25349 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25350 // Look through mask bitcast.
25351 if (Mask.getOpcode() == ISD::BITCAST)
25352 Mask = Mask.getOperand(0);
25353 if (X.getOpcode() == ISD::BITCAST)
25354 X = X.getOperand(0);
25355 if (Y.getOpcode() == ISD::BITCAST)
25356 Y = Y.getOperand(0);
25358 EVT MaskVT = Mask.getValueType();
25360 // Validate that the Mask operand is a vector sra node.
25361 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25362 // there is no psrai.b
25363 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25364 unsigned SraAmt = ~0;
25365 if (Mask.getOpcode() == ISD::SRA) {
25366 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25367 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25368 SraAmt = AmtConst->getZExtValue();
25369 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25370 SDValue SraC = Mask.getOperand(1);
25371 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25373 if ((SraAmt + 1) != EltBits)
25378 // Now we know we at least have a plendvb with the mask val. See if
25379 // we can form a psignb/w/d.
25380 // psign = x.type == y.type == mask.type && y = sub(0, x);
25381 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25382 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25383 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25384 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25385 "Unsupported VT for PSIGN");
25386 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25387 return DAG.getBitcast(VT, Mask);
25389 // PBLENDVB only available on SSE 4.1
25390 if (!Subtarget->hasSSE41())
25393 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25395 X = DAG.getBitcast(BlendVT, X);
25396 Y = DAG.getBitcast(BlendVT, Y);
25397 Mask = DAG.getBitcast(BlendVT, Mask);
25398 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25399 return DAG.getBitcast(VT, Mask);
25403 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25406 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25407 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25409 // SHLD/SHRD instructions have lower register pressure, but on some
25410 // platforms they have higher latency than the equivalent
25411 // series of shifts/or that would otherwise be generated.
25412 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25413 // have higher latencies and we are not optimizing for size.
25414 if (!OptForSize && Subtarget->isSHLDSlow())
25417 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25419 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25421 if (!N0.hasOneUse() || !N1.hasOneUse())
25424 SDValue ShAmt0 = N0.getOperand(1);
25425 if (ShAmt0.getValueType() != MVT::i8)
25427 SDValue ShAmt1 = N1.getOperand(1);
25428 if (ShAmt1.getValueType() != MVT::i8)
25430 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25431 ShAmt0 = ShAmt0.getOperand(0);
25432 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25433 ShAmt1 = ShAmt1.getOperand(0);
25436 unsigned Opc = X86ISD::SHLD;
25437 SDValue Op0 = N0.getOperand(0);
25438 SDValue Op1 = N1.getOperand(0);
25439 if (ShAmt0.getOpcode() == ISD::SUB) {
25440 Opc = X86ISD::SHRD;
25441 std::swap(Op0, Op1);
25442 std::swap(ShAmt0, ShAmt1);
25445 unsigned Bits = VT.getSizeInBits();
25446 if (ShAmt1.getOpcode() == ISD::SUB) {
25447 SDValue Sum = ShAmt1.getOperand(0);
25448 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25449 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25450 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25451 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25452 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25453 return DAG.getNode(Opc, DL, VT,
25455 DAG.getNode(ISD::TRUNCATE, DL,
25458 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25459 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25461 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25462 return DAG.getNode(Opc, DL, VT,
25463 N0.getOperand(0), N1.getOperand(0),
25464 DAG.getNode(ISD::TRUNCATE, DL,
25471 // Generate NEG and CMOV for integer abs.
25472 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25473 EVT VT = N->getValueType(0);
25475 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25476 // 8-bit integer abs to NEG and CMOV.
25477 if (VT.isInteger() && VT.getSizeInBits() == 8)
25480 SDValue N0 = N->getOperand(0);
25481 SDValue N1 = N->getOperand(1);
25484 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25485 // and change it to SUB and CMOV.
25486 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25487 N0.getOpcode() == ISD::ADD &&
25488 N0.getOperand(1) == N1 &&
25489 N1.getOpcode() == ISD::SRA &&
25490 N1.getOperand(0) == N0.getOperand(0))
25491 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25492 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25493 // Generate SUB & CMOV.
25494 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25495 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25497 SDValue Ops[] = { N0.getOperand(0), Neg,
25498 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25499 SDValue(Neg.getNode(), 1) };
25500 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25505 // Try to turn tests against the signbit in the form of:
25506 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25509 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25510 // This is only worth doing if the output type is i8.
25511 if (N->getValueType(0) != MVT::i8)
25514 SDValue N0 = N->getOperand(0);
25515 SDValue N1 = N->getOperand(1);
25517 // We should be performing an xor against a truncated shift.
25518 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25521 // Make sure we are performing an xor against one.
25522 if (!isOneConstant(N1))
25525 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25526 SDValue Shift = N0.getOperand(0);
25527 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25530 // Make sure we are truncating from one of i16, i32 or i64.
25531 EVT ShiftTy = Shift.getValueType();
25532 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25535 // Make sure the shift amount extracts the sign bit.
25536 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25537 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25540 // Create a greater-than comparison against -1.
25541 // N.B. Using SETGE against 0 works but we want a canonical looking
25542 // comparison, using SETGT matches up with what TranslateX86CC.
25544 SDValue ShiftOp = Shift.getOperand(0);
25545 EVT ShiftOpTy = ShiftOp.getValueType();
25546 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25547 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25551 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25552 TargetLowering::DAGCombinerInfo &DCI,
25553 const X86Subtarget *Subtarget) {
25554 if (DCI.isBeforeLegalizeOps())
25557 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25560 if (Subtarget->hasCMov())
25561 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25564 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25570 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25571 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25572 /// X86ISD::AVG instruction.
25573 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25574 const X86Subtarget *Subtarget, SDLoc DL) {
25575 if (!VT.isVector() || !VT.isSimple())
25577 EVT InVT = In.getValueType();
25578 unsigned NumElems = VT.getVectorNumElements();
25580 EVT ScalarVT = VT.getVectorElementType();
25581 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25582 isPowerOf2_32(NumElems)))
25585 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25586 // than the original input type (i8/i16).
25587 EVT InScalarVT = InVT.getVectorElementType();
25588 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25591 if (Subtarget->hasAVX512()) {
25592 if (VT.getSizeInBits() > 512)
25594 } else if (Subtarget->hasAVX2()) {
25595 if (VT.getSizeInBits() > 256)
25598 if (VT.getSizeInBits() > 128)
25602 // Detect the following pattern:
25604 // %1 = zext <N x i8> %a to <N x i32>
25605 // %2 = zext <N x i8> %b to <N x i32>
25606 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25607 // %4 = add nuw nsw <N x i32> %3, %2
25608 // %5 = lshr <N x i32> %N, <i32 1 x N>
25609 // %6 = trunc <N x i32> %5 to <N x i8>
25611 // In AVX512, the last instruction can also be a trunc store.
25613 if (In.getOpcode() != ISD::SRL)
25616 // A lambda checking the given SDValue is a constant vector and each element
25617 // is in the range [Min, Max].
25618 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25619 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25620 if (!BV || !BV->isConstant())
25622 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25623 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25626 uint64_t Val = C->getZExtValue();
25627 if (Val < Min || Val > Max)
25633 // Check if each element of the vector is left-shifted by one.
25634 auto LHS = In.getOperand(0);
25635 auto RHS = In.getOperand(1);
25636 if (!IsConstVectorInRange(RHS, 1, 1))
25638 if (LHS.getOpcode() != ISD::ADD)
25641 // Detect a pattern of a + b + 1 where the order doesn't matter.
25642 SDValue Operands[3];
25643 Operands[0] = LHS.getOperand(0);
25644 Operands[1] = LHS.getOperand(1);
25646 // Take care of the case when one of the operands is a constant vector whose
25647 // element is in the range [1, 256].
25648 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25649 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25650 Operands[0].getOperand(0).getValueType() == VT) {
25651 // The pattern is detected. Subtract one from the constant vector, then
25652 // demote it and emit X86ISD::AVG instruction.
25653 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25654 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25655 SmallVector<SDValue, 8>(NumElems, One));
25656 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25657 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25658 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25662 if (Operands[0].getOpcode() == ISD::ADD)
25663 std::swap(Operands[0], Operands[1]);
25664 else if (Operands[1].getOpcode() != ISD::ADD)
25666 Operands[2] = Operands[1].getOperand(0);
25667 Operands[1] = Operands[1].getOperand(1);
25669 // Now we have three operands of two additions. Check that one of them is a
25670 // constant vector with ones, and the other two are promoted from i8/i16.
25671 for (int i = 0; i < 3; ++i) {
25672 if (!IsConstVectorInRange(Operands[i], 1, 1))
25674 std::swap(Operands[i], Operands[2]);
25676 // Check if Operands[0] and Operands[1] are results of type promotion.
25677 for (int j = 0; j < 2; ++j)
25678 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25679 Operands[j].getOperand(0).getValueType() != VT)
25682 // The pattern is detected, emit X86ISD::AVG instruction.
25683 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25684 Operands[1].getOperand(0));
25690 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
25691 const X86Subtarget *Subtarget) {
25692 return detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG, Subtarget,
25696 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25697 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25698 TargetLowering::DAGCombinerInfo &DCI,
25699 const X86Subtarget *Subtarget) {
25700 LoadSDNode *Ld = cast<LoadSDNode>(N);
25701 EVT RegVT = Ld->getValueType(0);
25702 EVT MemVT = Ld->getMemoryVT();
25704 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25706 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25707 // into two 16-byte operations.
25708 ISD::LoadExtType Ext = Ld->getExtensionType();
25710 unsigned AddressSpace = Ld->getAddressSpace();
25711 unsigned Alignment = Ld->getAlignment();
25712 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25713 Ext == ISD::NON_EXTLOAD &&
25714 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25715 AddressSpace, Alignment, &Fast) && !Fast) {
25716 unsigned NumElems = RegVT.getVectorNumElements();
25720 SDValue Ptr = Ld->getBasePtr();
25721 SDValue Increment =
25722 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25724 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25726 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25727 Ld->getPointerInfo(), Ld->isVolatile(),
25728 Ld->isNonTemporal(), Ld->isInvariant(),
25730 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25731 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25732 Ld->getPointerInfo(), Ld->isVolatile(),
25733 Ld->isNonTemporal(), Ld->isInvariant(),
25734 std::min(16U, Alignment));
25735 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25737 Load2.getValue(1));
25739 SDValue NewVec = DAG.getUNDEF(RegVT);
25740 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25741 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25742 return DCI.CombineTo(N, NewVec, TF, true);
25748 /// PerformMLOADCombine - Resolve extending loads
25749 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25750 TargetLowering::DAGCombinerInfo &DCI,
25751 const X86Subtarget *Subtarget) {
25752 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25753 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25756 EVT VT = Mld->getValueType(0);
25757 unsigned NumElems = VT.getVectorNumElements();
25758 EVT LdVT = Mld->getMemoryVT();
25761 assert(LdVT != VT && "Cannot extend to the same type");
25762 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25763 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25764 // From, To sizes and ElemCount must be pow of two
25765 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25766 "Unexpected size for extending masked load");
25768 unsigned SizeRatio = ToSz / FromSz;
25769 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25771 // Create a type on which we perform the shuffle
25772 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25773 LdVT.getScalarType(), NumElems*SizeRatio);
25774 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25776 // Convert Src0 value
25777 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25778 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25779 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25780 for (unsigned i = 0; i != NumElems; ++i)
25781 ShuffleVec[i] = i * SizeRatio;
25783 // Can't shuffle using an illegal type.
25784 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25785 "WideVecVT should be legal");
25786 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25787 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25789 // Prepare the new mask
25791 SDValue Mask = Mld->getMask();
25792 if (Mask.getValueType() == VT) {
25793 // Mask and original value have the same type
25794 NewMask = DAG.getBitcast(WideVecVT, Mask);
25795 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25796 for (unsigned i = 0; i != NumElems; ++i)
25797 ShuffleVec[i] = i * SizeRatio;
25798 for (unsigned i = NumElems; i != NumElems * SizeRatio; ++i)
25799 ShuffleVec[i] = NumElems * SizeRatio;
25800 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25801 DAG.getConstant(0, dl, WideVecVT),
25805 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25806 unsigned WidenNumElts = NumElems*SizeRatio;
25807 unsigned MaskNumElts = VT.getVectorNumElements();
25808 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25811 unsigned NumConcat = WidenNumElts / MaskNumElts;
25812 SmallVector<SDValue, 16> Ops(NumConcat);
25813 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25815 for (unsigned i = 1; i != NumConcat; ++i)
25818 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25821 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25822 Mld->getBasePtr(), NewMask, WideSrc0,
25823 Mld->getMemoryVT(), Mld->getMemOperand(),
25825 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25826 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25828 /// PerformMSTORECombine - Resolve truncating stores
25829 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25830 const X86Subtarget *Subtarget) {
25831 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25832 if (!Mst->isTruncatingStore())
25835 EVT VT = Mst->getValue().getValueType();
25836 unsigned NumElems = VT.getVectorNumElements();
25837 EVT StVT = Mst->getMemoryVT();
25840 assert(StVT != VT && "Cannot truncate to the same type");
25841 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25842 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25844 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25846 // The truncating store is legal in some cases. For example
25847 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25848 // are designated for truncate store.
25849 // In this case we don't need any further transformations.
25850 if (TLI.isTruncStoreLegal(VT, StVT))
25853 // From, To sizes and ElemCount must be pow of two
25854 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25855 "Unexpected size for truncating masked store");
25856 // We are going to use the original vector elt for storing.
25857 // Accumulated smaller vector elements must be a multiple of the store size.
25858 assert (((NumElems * FromSz) % ToSz) == 0 &&
25859 "Unexpected ratio for truncating masked store");
25861 unsigned SizeRatio = FromSz / ToSz;
25862 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25864 // Create a type on which we perform the shuffle
25865 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25866 StVT.getScalarType(), NumElems*SizeRatio);
25868 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25870 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25871 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25872 for (unsigned i = 0; i != NumElems; ++i)
25873 ShuffleVec[i] = i * SizeRatio;
25875 // Can't shuffle using an illegal type.
25876 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25877 "WideVecVT should be legal");
25879 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25880 DAG.getUNDEF(WideVecVT),
25884 SDValue Mask = Mst->getMask();
25885 if (Mask.getValueType() == VT) {
25886 // Mask and original value have the same type
25887 NewMask = DAG.getBitcast(WideVecVT, Mask);
25888 for (unsigned i = 0; i != NumElems; ++i)
25889 ShuffleVec[i] = i * SizeRatio;
25890 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25891 ShuffleVec[i] = NumElems*SizeRatio;
25892 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25893 DAG.getConstant(0, dl, WideVecVT),
25897 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25898 unsigned WidenNumElts = NumElems*SizeRatio;
25899 unsigned MaskNumElts = VT.getVectorNumElements();
25900 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25903 unsigned NumConcat = WidenNumElts / MaskNumElts;
25904 SmallVector<SDValue, 16> Ops(NumConcat);
25905 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25907 for (unsigned i = 1; i != NumConcat; ++i)
25910 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25913 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal,
25914 Mst->getBasePtr(), NewMask, StVT,
25915 Mst->getMemOperand(), false);
25917 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25918 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25919 const X86Subtarget *Subtarget) {
25920 StoreSDNode *St = cast<StoreSDNode>(N);
25921 EVT VT = St->getValue().getValueType();
25922 EVT StVT = St->getMemoryVT();
25924 SDValue StoredVal = St->getOperand(1);
25925 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25927 // If we are saving a concatenation of two XMM registers and 32-byte stores
25928 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25930 unsigned AddressSpace = St->getAddressSpace();
25931 unsigned Alignment = St->getAlignment();
25932 if (VT.is256BitVector() && StVT == VT &&
25933 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25934 AddressSpace, Alignment, &Fast) && !Fast) {
25935 unsigned NumElems = VT.getVectorNumElements();
25939 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25940 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25943 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25944 SDValue Ptr0 = St->getBasePtr();
25945 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25947 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25948 St->getPointerInfo(), St->isVolatile(),
25949 St->isNonTemporal(), Alignment);
25950 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25951 St->getPointerInfo(), St->isVolatile(),
25952 St->isNonTemporal(),
25953 std::min(16U, Alignment));
25954 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25957 // Optimize trunc store (of multiple scalars) to shuffle and store.
25958 // First, pack all of the elements in one place. Next, store to memory
25959 // in fewer chunks.
25960 if (St->isTruncatingStore() && VT.isVector()) {
25961 // Check if we can detect an AVG pattern from the truncation. If yes,
25962 // replace the trunc store by a normal store with the result of X86ISD::AVG
25965 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
25967 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
25968 St->getPointerInfo(), St->isVolatile(),
25969 St->isNonTemporal(), St->getAlignment());
25971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25972 unsigned NumElems = VT.getVectorNumElements();
25973 assert(StVT != VT && "Cannot truncate to the same type");
25974 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25975 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25977 // The truncating store is legal in some cases. For example
25978 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25979 // are designated for truncate store.
25980 // In this case we don't need any further transformations.
25981 if (TLI.isTruncStoreLegal(VT, StVT))
25984 // From, To sizes and ElemCount must be pow of two
25985 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25986 // We are going to use the original vector elt for storing.
25987 // Accumulated smaller vector elements must be a multiple of the store size.
25988 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25990 unsigned SizeRatio = FromSz / ToSz;
25992 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25994 // Create a type on which we perform the shuffle
25995 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25996 StVT.getScalarType(), NumElems*SizeRatio);
25998 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26000 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
26001 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
26002 for (unsigned i = 0; i != NumElems; ++i)
26003 ShuffleVec[i] = i * SizeRatio;
26005 // Can't shuffle using an illegal type.
26006 if (!TLI.isTypeLegal(WideVecVT))
26009 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26010 DAG.getUNDEF(WideVecVT),
26012 // At this point all of the data is stored at the bottom of the
26013 // register. We now need to save it to mem.
26015 // Find the largest store unit
26016 MVT StoreType = MVT::i8;
26017 for (MVT Tp : MVT::integer_valuetypes()) {
26018 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
26022 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
26023 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
26024 (64 <= NumElems * ToSz))
26025 StoreType = MVT::f64;
26027 // Bitcast the original vector into a vector of store-size units
26028 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
26029 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
26030 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
26031 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
26032 SmallVector<SDValue, 8> Chains;
26033 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
26034 TLI.getPointerTy(DAG.getDataLayout()));
26035 SDValue Ptr = St->getBasePtr();
26037 // Perform one or more big stores into memory.
26038 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
26039 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
26040 StoreType, ShuffWide,
26041 DAG.getIntPtrConstant(i, dl));
26042 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
26043 St->getPointerInfo(), St->isVolatile(),
26044 St->isNonTemporal(), St->getAlignment());
26045 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26046 Chains.push_back(Ch);
26049 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
26052 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
26053 // the FP state in cases where an emms may be missing.
26054 // A preferable solution to the general problem is to figure out the right
26055 // places to insert EMMS. This qualifies as a quick hack.
26057 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
26058 if (VT.getSizeInBits() != 64)
26061 const Function *F = DAG.getMachineFunction().getFunction();
26062 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
26064 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
26065 if ((VT.isVector() ||
26066 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
26067 isa<LoadSDNode>(St->getValue()) &&
26068 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
26069 St->getChain().hasOneUse() && !St->isVolatile()) {
26070 SDNode* LdVal = St->getValue().getNode();
26071 LoadSDNode *Ld = nullptr;
26072 int TokenFactorIndex = -1;
26073 SmallVector<SDValue, 8> Ops;
26074 SDNode* ChainVal = St->getChain().getNode();
26075 // Must be a store of a load. We currently handle two cases: the load
26076 // is a direct child, and it's under an intervening TokenFactor. It is
26077 // possible to dig deeper under nested TokenFactors.
26078 if (ChainVal == LdVal)
26079 Ld = cast<LoadSDNode>(St->getChain());
26080 else if (St->getValue().hasOneUse() &&
26081 ChainVal->getOpcode() == ISD::TokenFactor) {
26082 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
26083 if (ChainVal->getOperand(i).getNode() == LdVal) {
26084 TokenFactorIndex = i;
26085 Ld = cast<LoadSDNode>(St->getValue());
26087 Ops.push_back(ChainVal->getOperand(i));
26091 if (!Ld || !ISD::isNormalLoad(Ld))
26094 // If this is not the MMX case, i.e. we are just turning i64 load/store
26095 // into f64 load/store, avoid the transformation if there are multiple
26096 // uses of the loaded value.
26097 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
26102 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
26103 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
26105 if (Subtarget->is64Bit() || F64IsLegal) {
26106 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
26107 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
26108 Ld->getPointerInfo(), Ld->isVolatile(),
26109 Ld->isNonTemporal(), Ld->isInvariant(),
26110 Ld->getAlignment());
26111 SDValue NewChain = NewLd.getValue(1);
26112 if (TokenFactorIndex != -1) {
26113 Ops.push_back(NewChain);
26114 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26116 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
26117 St->getPointerInfo(),
26118 St->isVolatile(), St->isNonTemporal(),
26119 St->getAlignment());
26122 // Otherwise, lower to two pairs of 32-bit loads / stores.
26123 SDValue LoAddr = Ld->getBasePtr();
26124 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
26125 DAG.getConstant(4, LdDL, MVT::i32));
26127 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
26128 Ld->getPointerInfo(),
26129 Ld->isVolatile(), Ld->isNonTemporal(),
26130 Ld->isInvariant(), Ld->getAlignment());
26131 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
26132 Ld->getPointerInfo().getWithOffset(4),
26133 Ld->isVolatile(), Ld->isNonTemporal(),
26135 MinAlign(Ld->getAlignment(), 4));
26137 SDValue NewChain = LoLd.getValue(1);
26138 if (TokenFactorIndex != -1) {
26139 Ops.push_back(LoLd);
26140 Ops.push_back(HiLd);
26141 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26144 LoAddr = St->getBasePtr();
26145 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
26146 DAG.getConstant(4, StDL, MVT::i32));
26148 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
26149 St->getPointerInfo(),
26150 St->isVolatile(), St->isNonTemporal(),
26151 St->getAlignment());
26152 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
26153 St->getPointerInfo().getWithOffset(4),
26155 St->isNonTemporal(),
26156 MinAlign(St->getAlignment(), 4));
26157 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
26160 // This is similar to the above case, but here we handle a scalar 64-bit
26161 // integer store that is extracted from a vector on a 32-bit target.
26162 // If we have SSE2, then we can treat it like a floating-point double
26163 // to get past legalization. The execution dependencies fixup pass will
26164 // choose the optimal machine instruction for the store if this really is
26165 // an integer or v2f32 rather than an f64.
26166 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
26167 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26168 SDValue OldExtract = St->getOperand(1);
26169 SDValue ExtOp0 = OldExtract.getOperand(0);
26170 unsigned VecSize = ExtOp0.getValueSizeInBits();
26171 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
26172 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
26173 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
26174 BitCast, OldExtract.getOperand(1));
26175 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
26176 St->getPointerInfo(), St->isVolatile(),
26177 St->isNonTemporal(), St->getAlignment());
26183 /// Return 'true' if this vector operation is "horizontal"
26184 /// and return the operands for the horizontal operation in LHS and RHS. A
26185 /// horizontal operation performs the binary operation on successive elements
26186 /// of its first operand, then on successive elements of its second operand,
26187 /// returning the resulting values in a vector. For example, if
26188 /// A = < float a0, float a1, float a2, float a3 >
26190 /// B = < float b0, float b1, float b2, float b3 >
26191 /// then the result of doing a horizontal operation on A and B is
26192 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26193 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26194 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26195 /// set to A, RHS to B, and the routine returns 'true'.
26196 /// Note that the binary operation should have the property that if one of the
26197 /// operands is UNDEF then the result is UNDEF.
26198 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26199 // Look for the following pattern: if
26200 // A = < float a0, float a1, float a2, float a3 >
26201 // B = < float b0, float b1, float b2, float b3 >
26203 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26204 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26205 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26206 // which is A horizontal-op B.
26208 // At least one of the operands should be a vector shuffle.
26209 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26210 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26213 MVT VT = LHS.getSimpleValueType();
26215 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26216 "Unsupported vector type for horizontal add/sub");
26218 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26219 // operate independently on 128-bit lanes.
26220 unsigned NumElts = VT.getVectorNumElements();
26221 unsigned NumLanes = VT.getSizeInBits()/128;
26222 unsigned NumLaneElts = NumElts / NumLanes;
26223 assert((NumLaneElts % 2 == 0) &&
26224 "Vector type should have an even number of elements in each lane");
26225 unsigned HalfLaneElts = NumLaneElts/2;
26227 // View LHS in the form
26228 // LHS = VECTOR_SHUFFLE A, B, LMask
26229 // If LHS is not a shuffle then pretend it is the shuffle
26230 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26231 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26234 SmallVector<int, 16> LMask(NumElts);
26235 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26236 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26237 A = LHS.getOperand(0);
26238 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26239 B = LHS.getOperand(1);
26240 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26241 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26243 if (LHS.getOpcode() != ISD::UNDEF)
26245 for (unsigned i = 0; i != NumElts; ++i)
26249 // Likewise, view RHS in the form
26250 // RHS = VECTOR_SHUFFLE C, D, RMask
26252 SmallVector<int, 16> RMask(NumElts);
26253 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26254 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26255 C = RHS.getOperand(0);
26256 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26257 D = RHS.getOperand(1);
26258 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26259 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26261 if (RHS.getOpcode() != ISD::UNDEF)
26263 for (unsigned i = 0; i != NumElts; ++i)
26267 // Check that the shuffles are both shuffling the same vectors.
26268 if (!(A == C && B == D) && !(A == D && B == C))
26271 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26272 if (!A.getNode() && !B.getNode())
26275 // If A and B occur in reverse order in RHS, then "swap" them (which means
26276 // rewriting the mask).
26278 ShuffleVectorSDNode::commuteMask(RMask);
26280 // At this point LHS and RHS are equivalent to
26281 // LHS = VECTOR_SHUFFLE A, B, LMask
26282 // RHS = VECTOR_SHUFFLE A, B, RMask
26283 // Check that the masks correspond to performing a horizontal operation.
26284 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26285 for (unsigned i = 0; i != NumLaneElts; ++i) {
26286 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26288 // Ignore any UNDEF components.
26289 if (LIdx < 0 || RIdx < 0 ||
26290 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26291 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26294 // Check that successive elements are being operated on. If not, this is
26295 // not a horizontal operation.
26296 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26297 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26298 if (!(LIdx == Index && RIdx == Index + 1) &&
26299 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26304 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26305 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26309 /// Do target-specific dag combines on floating point adds.
26310 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26311 const X86Subtarget *Subtarget) {
26312 EVT VT = N->getValueType(0);
26313 SDValue LHS = N->getOperand(0);
26314 SDValue RHS = N->getOperand(1);
26316 // Try to synthesize horizontal adds from adds of shuffles.
26317 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26318 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26319 isHorizontalBinOp(LHS, RHS, true))
26320 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26324 /// Do target-specific dag combines on floating point subs.
26325 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26326 const X86Subtarget *Subtarget) {
26327 EVT VT = N->getValueType(0);
26328 SDValue LHS = N->getOperand(0);
26329 SDValue RHS = N->getOperand(1);
26331 // Try to synthesize horizontal subs from subs of shuffles.
26332 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26333 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26334 isHorizontalBinOp(LHS, RHS, false))
26335 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26339 /// Do target-specific dag combines on floating point negations.
26340 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26341 const X86Subtarget *Subtarget) {
26342 EVT VT = N->getValueType(0);
26343 EVT SVT = VT.getScalarType();
26344 SDValue Arg = N->getOperand(0);
26347 // Let legalize expand this if it isn't a legal type yet.
26348 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26351 // If we're negating a FMUL node on a target with FMA, then we can avoid the
26352 // use of a constant by performing (-0 - A*B) instead.
26353 // FIXME: Check rounding control flags as well once it becomes available.
26354 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26355 Arg->getFlags()->hasNoSignedZeros() && Subtarget->hasAnyFMA()) {
26356 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
26357 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26358 Arg.getOperand(1), Zero);
26361 // If we're negating a FMA node, then we can adjust the
26362 // instruction to include the extra negation.
26363 if (Arg.hasOneUse()) {
26364 switch (Arg.getOpcode()) {
26365 case X86ISD::FMADD:
26366 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26367 Arg.getOperand(1), Arg.getOperand(2));
26368 case X86ISD::FMSUB:
26369 return DAG.getNode(X86ISD::FNMADD, DL, VT, Arg.getOperand(0),
26370 Arg.getOperand(1), Arg.getOperand(2));
26371 case X86ISD::FNMADD:
26372 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0),
26373 Arg.getOperand(1), Arg.getOperand(2));
26374 case X86ISD::FNMSUB:
26375 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
26376 Arg.getOperand(1), Arg.getOperand(2));
26382 static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
26383 const X86Subtarget *Subtarget) {
26384 EVT VT = N->getValueType(0);
26385 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26386 // VXORPS, VORPS, VANDPS, VANDNPS are supported only under DQ extention.
26387 // These logic operations may be executed in the integer domain.
26389 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26390 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26392 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26393 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26394 unsigned IntOpcode = 0;
26395 switch (N->getOpcode()) {
26396 default: llvm_unreachable("Unexpected FP logic op");
26397 case X86ISD::FOR: IntOpcode = ISD::OR; break;
26398 case X86ISD::FXOR: IntOpcode = ISD::XOR; break;
26399 case X86ISD::FAND: IntOpcode = ISD::AND; break;
26400 case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
26402 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26403 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26407 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26408 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26409 const X86Subtarget *Subtarget) {
26410 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26412 // F[X]OR(0.0, x) -> x
26413 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26414 if (C->getValueAPF().isPosZero())
26415 return N->getOperand(1);
26417 // F[X]OR(x, 0.0) -> x
26418 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26419 if (C->getValueAPF().isPosZero())
26420 return N->getOperand(0);
26422 return lowerX86FPLogicOp(N, DAG, Subtarget);
26425 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26426 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26427 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26429 // Only perform optimizations if UnsafeMath is used.
26430 if (!DAG.getTarget().Options.UnsafeFPMath)
26433 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26434 // into FMINC and FMAXC, which are Commutative operations.
26435 unsigned NewOp = 0;
26436 switch (N->getOpcode()) {
26437 default: llvm_unreachable("unknown opcode");
26438 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26439 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26442 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26443 N->getOperand(0), N->getOperand(1));
26446 /// Do target-specific dag combines on X86ISD::FAND nodes.
26447 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
26448 const X86Subtarget *Subtarget) {
26449 // FAND(0.0, x) -> 0.0
26450 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26451 if (C->getValueAPF().isPosZero())
26452 return N->getOperand(0);
26454 // FAND(x, 0.0) -> 0.0
26455 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26456 if (C->getValueAPF().isPosZero())
26457 return N->getOperand(1);
26459 return lowerX86FPLogicOp(N, DAG, Subtarget);
26462 /// Do target-specific dag combines on X86ISD::FANDN nodes
26463 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
26464 const X86Subtarget *Subtarget) {
26465 // FANDN(0.0, x) -> x
26466 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26467 if (C->getValueAPF().isPosZero())
26468 return N->getOperand(1);
26470 // FANDN(x, 0.0) -> 0.0
26471 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26472 if (C->getValueAPF().isPosZero())
26473 return N->getOperand(1);
26475 return lowerX86FPLogicOp(N, DAG, Subtarget);
26478 static SDValue PerformBTCombine(SDNode *N,
26480 TargetLowering::DAGCombinerInfo &DCI) {
26481 // BT ignores high bits in the bit index operand.
26482 SDValue Op1 = N->getOperand(1);
26483 if (Op1.hasOneUse()) {
26484 unsigned BitWidth = Op1.getValueSizeInBits();
26485 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26486 APInt KnownZero, KnownOne;
26487 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26488 !DCI.isBeforeLegalizeOps());
26489 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26490 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26491 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26492 DCI.CommitTargetLoweringOpt(TLO);
26497 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26498 SDValue Op = N->getOperand(0);
26499 if (Op.getOpcode() == ISD::BITCAST)
26500 Op = Op.getOperand(0);
26501 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26502 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26503 VT.getVectorElementType().getSizeInBits() ==
26504 OpVT.getVectorElementType().getSizeInBits()) {
26505 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26510 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26511 const X86Subtarget *Subtarget) {
26512 EVT VT = N->getValueType(0);
26513 if (!VT.isVector())
26516 SDValue N0 = N->getOperand(0);
26517 SDValue N1 = N->getOperand(1);
26518 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26521 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26522 // both SSE and AVX2 since there is no sign-extended shift right
26523 // operation on a vector with 64-bit elements.
26524 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26525 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26526 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26527 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26528 SDValue N00 = N0.getOperand(0);
26530 // EXTLOAD has a better solution on AVX2,
26531 // it may be replaced with X86ISD::VSEXT node.
26532 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26533 if (!ISD::isNormalLoad(N00.getNode()))
26536 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26537 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26539 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26545 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26546 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26547 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26548 /// eliminate extend, add, and shift instructions.
26549 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26550 const X86Subtarget *Subtarget) {
26551 // TODO: This should be valid for other integer types.
26552 EVT VT = Sext->getValueType(0);
26553 if (VT != MVT::i64)
26556 // We need an 'add nsw' feeding into the 'sext'.
26557 SDValue Add = Sext->getOperand(0);
26558 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26561 // Having a constant operand to the 'add' ensures that we are not increasing
26562 // the instruction count because the constant is extended for free below.
26563 // A constant operand can also become the displacement field of an LEA.
26564 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26568 // Don't make the 'add' bigger if there's no hope of combining it with some
26569 // other 'add' or 'shl' instruction.
26570 // TODO: It may be profitable to generate simpler LEA instructions in place
26571 // of single 'add' instructions, but the cost model for selecting an LEA
26572 // currently has a high threshold.
26573 bool HasLEAPotential = false;
26574 for (auto *User : Sext->uses()) {
26575 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26576 HasLEAPotential = true;
26580 if (!HasLEAPotential)
26583 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26584 int64_t AddConstant = AddOp1->getSExtValue();
26585 SDValue AddOp0 = Add.getOperand(0);
26586 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26587 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26589 // The wider add is guaranteed to not wrap because both operands are
26592 Flags.setNoSignedWrap(true);
26593 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26596 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26597 TargetLowering::DAGCombinerInfo &DCI,
26598 const X86Subtarget *Subtarget) {
26599 SDValue N0 = N->getOperand(0);
26600 EVT VT = N->getValueType(0);
26601 EVT SVT = VT.getScalarType();
26602 EVT InVT = N0.getValueType();
26603 EVT InSVT = InVT.getScalarType();
26606 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26607 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26608 // This exposes the sext to the sdivrem lowering, so that it directly extends
26609 // from AH (which we otherwise need to do contortions to access).
26610 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26611 InVT == MVT::i8 && VT == MVT::i32) {
26612 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26613 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26614 N0.getOperand(0), N0.getOperand(1));
26615 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26616 return R.getValue(1);
26619 if (!DCI.isBeforeLegalizeOps()) {
26620 if (InVT == MVT::i1) {
26621 SDValue Zero = DAG.getConstant(0, DL, VT);
26623 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26624 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26629 if (VT.isVector() && Subtarget->hasSSE2()) {
26630 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26631 EVT InVT = N.getValueType();
26632 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26633 Size / InVT.getScalarSizeInBits());
26634 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26635 DAG.getUNDEF(InVT));
26637 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26640 // If target-size is less than 128-bits, extend to a type that would extend
26641 // to 128 bits, extend that and extract the original target vector.
26642 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26643 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26644 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26645 unsigned Scale = 128 / VT.getSizeInBits();
26647 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26648 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26649 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26650 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26651 DAG.getIntPtrConstant(0, DL));
26654 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26655 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26656 if (VT.getSizeInBits() == 128 &&
26657 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26658 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26659 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26660 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26663 // On pre-AVX2 targets, split into 128-bit nodes of
26664 // ISD::SIGN_EXTEND_VECTOR_INREG.
26665 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26666 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26667 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26668 unsigned NumVecs = VT.getSizeInBits() / 128;
26669 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26670 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26671 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26673 SmallVector<SDValue, 8> Opnds;
26674 for (unsigned i = 0, Offset = 0; i != NumVecs;
26675 ++i, Offset += NumSubElts) {
26676 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26677 DAG.getIntPtrConstant(Offset, DL));
26678 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26679 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26680 Opnds.push_back(SrcVec);
26682 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26686 if (Subtarget->hasAVX() && VT.is256BitVector())
26687 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26690 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26696 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26697 const X86Subtarget* Subtarget) {
26699 EVT VT = N->getValueType(0);
26701 // Let legalize expand this if it isn't a legal type yet.
26702 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26705 EVT ScalarVT = VT.getScalarType();
26706 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasAnyFMA())
26709 SDValue A = N->getOperand(0);
26710 SDValue B = N->getOperand(1);
26711 SDValue C = N->getOperand(2);
26713 bool NegA = (A.getOpcode() == ISD::FNEG);
26714 bool NegB = (B.getOpcode() == ISD::FNEG);
26715 bool NegC = (C.getOpcode() == ISD::FNEG);
26717 // Negative multiplication when NegA xor NegB
26718 bool NegMul = (NegA != NegB);
26720 A = A.getOperand(0);
26722 B = B.getOperand(0);
26724 C = C.getOperand(0);
26728 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26730 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26732 return DAG.getNode(Opcode, dl, VT, A, B, C);
26735 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26736 TargetLowering::DAGCombinerInfo &DCI,
26737 const X86Subtarget *Subtarget) {
26738 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26739 // (and (i32 x86isd::setcc_carry), 1)
26740 // This eliminates the zext. This transformation is necessary because
26741 // ISD::SETCC is always legalized to i8.
26743 SDValue N0 = N->getOperand(0);
26744 EVT VT = N->getValueType(0);
26746 if (N0.getOpcode() == ISD::AND &&
26748 N0.getOperand(0).hasOneUse()) {
26749 SDValue N00 = N0.getOperand(0);
26750 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26751 if (!isOneConstant(N0.getOperand(1)))
26753 return DAG.getNode(ISD::AND, dl, VT,
26754 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26755 N00.getOperand(0), N00.getOperand(1)),
26756 DAG.getConstant(1, dl, VT));
26760 if (N0.getOpcode() == ISD::TRUNCATE &&
26762 N0.getOperand(0).hasOneUse()) {
26763 SDValue N00 = N0.getOperand(0);
26764 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26765 return DAG.getNode(ISD::AND, dl, VT,
26766 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26767 N00.getOperand(0), N00.getOperand(1)),
26768 DAG.getConstant(1, dl, VT));
26772 if (VT.is256BitVector())
26773 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26776 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26777 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26778 // This exposes the zext to the udivrem lowering, so that it directly extends
26779 // from AH (which we otherwise need to do contortions to access).
26780 if (N0.getOpcode() == ISD::UDIVREM &&
26781 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26782 (VT == MVT::i32 || VT == MVT::i64)) {
26783 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26784 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26785 N0.getOperand(0), N0.getOperand(1));
26786 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26787 return R.getValue(1);
26793 // Optimize x == -y --> x+y == 0
26794 // x != -y --> x+y != 0
26795 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26796 const X86Subtarget* Subtarget) {
26797 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26798 SDValue LHS = N->getOperand(0);
26799 SDValue RHS = N->getOperand(1);
26800 EVT VT = N->getValueType(0);
26803 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26804 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
26805 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26806 LHS.getOperand(1));
26807 return DAG.getSetCC(DL, N->getValueType(0), addV,
26808 DAG.getConstant(0, DL, addV.getValueType()), CC);
26810 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26811 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
26812 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26813 RHS.getOperand(1));
26814 return DAG.getSetCC(DL, N->getValueType(0), addV,
26815 DAG.getConstant(0, DL, addV.getValueType()), CC);
26818 if (VT.getScalarType() == MVT::i1 &&
26819 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26821 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26822 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26823 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26825 if (!IsSEXT0 || !IsVZero1) {
26826 // Swap the operands and update the condition code.
26827 std::swap(LHS, RHS);
26828 CC = ISD::getSetCCSwappedOperands(CC);
26830 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26831 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26832 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26835 if (IsSEXT0 && IsVZero1) {
26836 assert(VT == LHS.getOperand(0).getValueType() &&
26837 "Uexpected operand type");
26838 if (CC == ISD::SETGT)
26839 return DAG.getConstant(0, DL, VT);
26840 if (CC == ISD::SETLE)
26841 return DAG.getConstant(1, DL, VT);
26842 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26843 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26845 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26846 "Unexpected condition code!");
26847 return LHS.getOperand(0);
26854 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26855 SDValue V0 = N->getOperand(0);
26856 SDValue V1 = N->getOperand(1);
26858 EVT VT = N->getValueType(0);
26860 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26861 // operands and changing the mask to 1. This saves us a bunch of
26862 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26863 // x86InstrInfo knows how to commute this back after instruction selection
26864 // if it would help register allocation.
26866 // TODO: If optimizing for size or a processor that doesn't suffer from
26867 // partial register update stalls, this should be transformed into a MOVSD
26868 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26870 if (VT == MVT::v2f64)
26871 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26872 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26873 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26874 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26880 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26881 // as "sbb reg,reg", since it can be extended without zext and produces
26882 // an all-ones bit which is more useful than 0/1 in some cases.
26883 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26886 return DAG.getNode(ISD::AND, DL, VT,
26887 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26888 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26890 DAG.getConstant(1, DL, VT));
26891 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26892 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26893 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26894 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26898 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26899 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26900 TargetLowering::DAGCombinerInfo &DCI,
26901 const X86Subtarget *Subtarget) {
26903 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26904 SDValue EFLAGS = N->getOperand(1);
26906 if (CC == X86::COND_A) {
26907 // Try to convert COND_A into COND_B in an attempt to facilitate
26908 // materializing "setb reg".
26910 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26911 // cannot take an immediate as its first operand.
26913 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26914 EFLAGS.getValueType().isInteger() &&
26915 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26916 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26917 EFLAGS.getNode()->getVTList(),
26918 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26919 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26920 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26924 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26925 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26927 if (CC == X86::COND_B)
26928 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26930 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26931 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26932 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26938 // Optimize branch condition evaluation.
26940 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26941 TargetLowering::DAGCombinerInfo &DCI,
26942 const X86Subtarget *Subtarget) {
26944 SDValue Chain = N->getOperand(0);
26945 SDValue Dest = N->getOperand(1);
26946 SDValue EFLAGS = N->getOperand(3);
26947 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26949 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26950 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26951 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26958 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26959 SelectionDAG &DAG) {
26960 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26961 // optimize away operation when it's from a constant.
26963 // The general transformation is:
26964 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26965 // AND(VECTOR_CMP(x,y), constant2)
26966 // constant2 = UNARYOP(constant)
26968 // Early exit if this isn't a vector operation, the operand of the
26969 // unary operation isn't a bitwise AND, or if the sizes of the operations
26970 // aren't the same.
26971 EVT VT = N->getValueType(0);
26972 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26973 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26974 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26977 // Now check that the other operand of the AND is a constant. We could
26978 // make the transformation for non-constant splats as well, but it's unclear
26979 // that would be a benefit as it would not eliminate any operations, just
26980 // perform one more step in scalar code before moving to the vector unit.
26981 if (BuildVectorSDNode *BV =
26982 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26983 // Bail out if the vector isn't a constant.
26984 if (!BV->isConstant())
26987 // Everything checks out. Build up the new and improved node.
26989 EVT IntVT = BV->getValueType(0);
26990 // Create a new constant of the appropriate type for the transformed
26992 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26993 // The AND node needs bitcasts to/from an integer vector type around it.
26994 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26995 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26996 N->getOperand(0)->getOperand(0), MaskConst);
26997 SDValue Res = DAG.getBitcast(VT, NewAnd);
27004 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27005 const X86Subtarget *Subtarget) {
27006 SDValue Op0 = N->getOperand(0);
27007 EVT VT = N->getValueType(0);
27008 EVT InVT = Op0.getValueType();
27009 EVT InSVT = InVT.getScalarType();
27010 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
27012 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
27013 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
27014 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27016 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27017 InVT.getVectorNumElements());
27018 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
27020 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
27021 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
27023 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27029 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27030 const X86Subtarget *Subtarget) {
27031 // First try to optimize away the conversion entirely when it's
27032 // conditionally from a constant. Vectors only.
27033 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
27036 // Now move on to more general possibilities.
27037 SDValue Op0 = N->getOperand(0);
27038 EVT VT = N->getValueType(0);
27039 EVT InVT = Op0.getValueType();
27040 EVT InSVT = InVT.getScalarType();
27042 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
27043 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
27044 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27046 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27047 InVT.getVectorNumElements());
27048 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
27049 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27052 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
27053 // a 32-bit target where SSE doesn't support i64->FP operations.
27054 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
27055 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
27056 EVT LdVT = Ld->getValueType(0);
27058 // This transformation is not supported if the result type is f16
27059 if (VT == MVT::f16)
27062 if (!Ld->isVolatile() && !VT.isVector() &&
27063 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
27064 !Subtarget->is64Bit() && LdVT == MVT::i64) {
27065 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
27066 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
27067 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
27074 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
27075 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
27076 X86TargetLowering::DAGCombinerInfo &DCI) {
27077 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
27078 // the result is either zero or one (depending on the input carry bit).
27079 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
27080 if (X86::isZeroNode(N->getOperand(0)) &&
27081 X86::isZeroNode(N->getOperand(1)) &&
27082 // We don't have a good way to replace an EFLAGS use, so only do this when
27084 SDValue(N, 1).use_empty()) {
27086 EVT VT = N->getValueType(0);
27087 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
27088 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
27089 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
27090 DAG.getConstant(X86::COND_B, DL,
27093 DAG.getConstant(1, DL, VT));
27094 return DCI.CombineTo(N, Res1, CarryOut);
27100 // fold (add Y, (sete X, 0)) -> adc 0, Y
27101 // (add Y, (setne X, 0)) -> sbb -1, Y
27102 // (sub (sete X, 0), Y) -> sbb 0, Y
27103 // (sub (setne X, 0), Y) -> adc -1, Y
27104 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
27107 // Look through ZExts.
27108 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
27109 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
27112 SDValue SetCC = Ext.getOperand(0);
27113 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27116 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
27117 if (CC != X86::COND_E && CC != X86::COND_NE)
27120 SDValue Cmp = SetCC.getOperand(1);
27121 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
27122 !X86::isZeroNode(Cmp.getOperand(1)) ||
27123 !Cmp.getOperand(0).getValueType().isInteger())
27126 SDValue CmpOp0 = Cmp.getOperand(0);
27127 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
27128 DAG.getConstant(1, DL, CmpOp0.getValueType()));
27130 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
27131 if (CC == X86::COND_NE)
27132 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
27133 DL, OtherVal.getValueType(), OtherVal,
27134 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
27136 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
27137 DL, OtherVal.getValueType(), OtherVal,
27138 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
27141 /// PerformADDCombine - Do target-specific dag combines on integer adds.
27142 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
27143 const X86Subtarget *Subtarget) {
27144 EVT VT = N->getValueType(0);
27145 SDValue Op0 = N->getOperand(0);
27146 SDValue Op1 = N->getOperand(1);
27148 // Try to synthesize horizontal adds from adds of shuffles.
27149 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27150 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27151 isHorizontalBinOp(Op0, Op1, true))
27152 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
27154 return OptimizeConditionalInDecrement(N, DAG);
27157 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
27158 const X86Subtarget *Subtarget) {
27159 SDValue Op0 = N->getOperand(0);
27160 SDValue Op1 = N->getOperand(1);
27162 // X86 can't encode an immediate LHS of a sub. See if we can push the
27163 // negation into a preceding instruction.
27164 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
27165 // If the RHS of the sub is a XOR with one use and a constant, invert the
27166 // immediate. Then add one to the LHS of the sub so we can turn
27167 // X-Y -> X+~Y+1, saving one register.
27168 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
27169 isa<ConstantSDNode>(Op1.getOperand(1))) {
27170 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
27171 EVT VT = Op0.getValueType();
27172 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
27174 DAG.getConstant(~XorC, SDLoc(Op1), VT));
27175 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
27176 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
27180 // Try to synthesize horizontal adds from adds of shuffles.
27181 EVT VT = N->getValueType(0);
27182 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27183 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27184 isHorizontalBinOp(Op0, Op1, true))
27185 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
27187 return OptimizeConditionalInDecrement(N, DAG);
27190 /// performVZEXTCombine - Performs build vector combines
27191 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27192 TargetLowering::DAGCombinerInfo &DCI,
27193 const X86Subtarget *Subtarget) {
27195 MVT VT = N->getSimpleValueType(0);
27196 SDValue Op = N->getOperand(0);
27197 MVT OpVT = Op.getSimpleValueType();
27198 MVT OpEltVT = OpVT.getVectorElementType();
27199 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
27201 // (vzext (bitcast (vzext (x)) -> (vzext x)
27203 while (V.getOpcode() == ISD::BITCAST)
27204 V = V.getOperand(0);
27206 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27207 MVT InnerVT = V.getSimpleValueType();
27208 MVT InnerEltVT = InnerVT.getVectorElementType();
27210 // If the element sizes match exactly, we can just do one larger vzext. This
27211 // is always an exact type match as vzext operates on integer types.
27212 if (OpEltVT == InnerEltVT) {
27213 assert(OpVT == InnerVT && "Types must match for vzext!");
27214 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27217 // The only other way we can combine them is if only a single element of the
27218 // inner vzext is used in the input to the outer vzext.
27219 if (InnerEltVT.getSizeInBits() < InputBits)
27222 // In this case, the inner vzext is completely dead because we're going to
27223 // only look at bits inside of the low element. Just do the outer vzext on
27224 // a bitcast of the input to the inner.
27225 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27228 // Check if we can bypass extracting and re-inserting an element of an input
27229 // vector. Essentially:
27230 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27231 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27232 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27233 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27234 SDValue ExtractedV = V.getOperand(0);
27235 SDValue OrigV = ExtractedV.getOperand(0);
27236 if (isNullConstant(ExtractedV.getOperand(1))) {
27237 MVT OrigVT = OrigV.getSimpleValueType();
27238 // Extract a subvector if necessary...
27239 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27240 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27241 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27242 OrigVT.getVectorNumElements() / Ratio);
27243 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27244 DAG.getIntPtrConstant(0, DL));
27246 Op = DAG.getBitcast(OpVT, OrigV);
27247 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27254 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27255 DAGCombinerInfo &DCI) const {
27256 SelectionDAG &DAG = DCI.DAG;
27257 switch (N->getOpcode()) {
27259 case ISD::EXTRACT_VECTOR_ELT:
27260 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27263 case X86ISD::SHRUNKBLEND:
27264 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27265 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27266 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27267 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27268 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27269 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27270 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27273 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27274 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27275 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27276 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27277 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27278 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27279 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27280 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27281 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27282 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27283 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27284 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27285 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27286 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27288 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27290 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27291 case X86ISD::FAND: return PerformFANDCombine(N, DAG, Subtarget);
27292 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG, Subtarget);
27293 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27294 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27295 case ISD::ANY_EXTEND:
27296 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27297 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27298 case ISD::SIGN_EXTEND_INREG:
27299 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27300 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27301 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27302 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27303 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27304 case X86ISD::SHUFP: // Handle all target specific shuffles
27305 case X86ISD::PALIGNR:
27306 case X86ISD::UNPCKH:
27307 case X86ISD::UNPCKL:
27308 case X86ISD::MOVHLPS:
27309 case X86ISD::MOVLHPS:
27310 case X86ISD::PSHUFB:
27311 case X86ISD::PSHUFD:
27312 case X86ISD::PSHUFHW:
27313 case X86ISD::PSHUFLW:
27314 case X86ISD::MOVSS:
27315 case X86ISD::MOVSD:
27316 case X86ISD::VPERMILPI:
27317 case X86ISD::VPERM2X128:
27318 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27319 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27320 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27326 /// isTypeDesirableForOp - Return true if the target has native support for
27327 /// the specified value type and it is 'desirable' to use the type for the
27328 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27329 /// instruction encodings are longer and some i16 instructions are slow.
27330 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27331 if (!isTypeLegal(VT))
27333 if (VT != MVT::i16)
27340 case ISD::SIGN_EXTEND:
27341 case ISD::ZERO_EXTEND:
27342 case ISD::ANY_EXTEND:
27355 /// IsDesirableToPromoteOp - This method query the target whether it is
27356 /// beneficial for dag combiner to promote the specified node. If true, it
27357 /// should return the desired promotion type by reference.
27358 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27359 EVT VT = Op.getValueType();
27360 if (VT != MVT::i16)
27363 bool Promote = false;
27364 bool Commute = false;
27365 switch (Op.getOpcode()) {
27368 LoadSDNode *LD = cast<LoadSDNode>(Op);
27369 // If the non-extending load has a single use and it's not live out, then it
27370 // might be folded.
27371 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27372 Op.hasOneUse()*/) {
27373 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27374 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27375 // The only case where we'd want to promote LOAD (rather then it being
27376 // promoted as an operand is when it's only use is liveout.
27377 if (UI->getOpcode() != ISD::CopyToReg)
27384 case ISD::SIGN_EXTEND:
27385 case ISD::ZERO_EXTEND:
27386 case ISD::ANY_EXTEND:
27391 SDValue N0 = Op.getOperand(0);
27392 // Look out for (store (shl (load), x)).
27393 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27406 SDValue N0 = Op.getOperand(0);
27407 SDValue N1 = Op.getOperand(1);
27408 if (!Commute && MayFoldLoad(N1))
27410 // Avoid disabling potential load folding opportunities.
27411 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27413 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27423 //===----------------------------------------------------------------------===//
27424 // X86 Inline Assembly Support
27425 //===----------------------------------------------------------------------===//
27427 // Helper to match a string separated by whitespace.
27428 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27429 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27431 for (StringRef Piece : Pieces) {
27432 if (!S.startswith(Piece)) // Check if the piece matches.
27435 S = S.substr(Piece.size());
27436 StringRef::size_type Pos = S.find_first_not_of(" \t");
27437 if (Pos == 0) // We matched a prefix.
27446 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27448 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27449 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27450 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27451 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27453 if (AsmPieces.size() == 3)
27455 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27462 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27463 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27465 std::string AsmStr = IA->getAsmString();
27467 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27468 if (!Ty || Ty->getBitWidth() % 16 != 0)
27471 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27472 SmallVector<StringRef, 4> AsmPieces;
27473 SplitString(AsmStr, AsmPieces, ";\n");
27475 switch (AsmPieces.size()) {
27476 default: return false;
27478 // FIXME: this should verify that we are targeting a 486 or better. If not,
27479 // we will turn this bswap into something that will be lowered to logical
27480 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27481 // lower so don't worry about this.
27483 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27484 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27485 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27486 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27487 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27488 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27489 // No need to check constraints, nothing other than the equivalent of
27490 // "=r,0" would be valid here.
27491 return IntrinsicLowering::LowerToByteSwap(CI);
27494 // rorw $$8, ${0:w} --> llvm.bswap.i16
27495 if (CI->getType()->isIntegerTy(16) &&
27496 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27497 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27498 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27500 StringRef ConstraintsStr = IA->getConstraintString();
27501 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27502 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27503 if (clobbersFlagRegisters(AsmPieces))
27504 return IntrinsicLowering::LowerToByteSwap(CI);
27508 if (CI->getType()->isIntegerTy(32) &&
27509 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27510 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27511 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27512 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27514 StringRef ConstraintsStr = IA->getConstraintString();
27515 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27516 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27517 if (clobbersFlagRegisters(AsmPieces))
27518 return IntrinsicLowering::LowerToByteSwap(CI);
27521 if (CI->getType()->isIntegerTy(64)) {
27522 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27523 if (Constraints.size() >= 2 &&
27524 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27525 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27526 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27527 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27528 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27529 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27530 return IntrinsicLowering::LowerToByteSwap(CI);
27538 /// getConstraintType - Given a constraint letter, return the type of
27539 /// constraint it is for this target.
27540 X86TargetLowering::ConstraintType
27541 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27542 if (Constraint.size() == 1) {
27543 switch (Constraint[0]) {
27554 return C_RegisterClass;
27578 return TargetLowering::getConstraintType(Constraint);
27581 /// Examine constraint type and operand type and determine a weight value.
27582 /// This object must already have been set up with the operand type
27583 /// and the current alternative constraint selected.
27584 TargetLowering::ConstraintWeight
27585 X86TargetLowering::getSingleConstraintMatchWeight(
27586 AsmOperandInfo &info, const char *constraint) const {
27587 ConstraintWeight weight = CW_Invalid;
27588 Value *CallOperandVal = info.CallOperandVal;
27589 // If we don't have a value, we can't do a match,
27590 // but allow it at the lowest weight.
27591 if (!CallOperandVal)
27593 Type *type = CallOperandVal->getType();
27594 // Look at the constraint type.
27595 switch (*constraint) {
27597 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27608 if (CallOperandVal->getType()->isIntegerTy())
27609 weight = CW_SpecificReg;
27614 if (type->isFloatingPointTy())
27615 weight = CW_SpecificReg;
27618 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27619 weight = CW_SpecificReg;
27623 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27624 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27625 weight = CW_Register;
27628 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27629 if (C->getZExtValue() <= 31)
27630 weight = CW_Constant;
27634 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27635 if (C->getZExtValue() <= 63)
27636 weight = CW_Constant;
27640 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27641 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27642 weight = CW_Constant;
27646 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27647 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27648 weight = CW_Constant;
27652 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27653 if (C->getZExtValue() <= 3)
27654 weight = CW_Constant;
27658 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27659 if (C->getZExtValue() <= 0xff)
27660 weight = CW_Constant;
27665 if (isa<ConstantFP>(CallOperandVal)) {
27666 weight = CW_Constant;
27670 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27671 if ((C->getSExtValue() >= -0x80000000LL) &&
27672 (C->getSExtValue() <= 0x7fffffffLL))
27673 weight = CW_Constant;
27677 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27678 if (C->getZExtValue() <= 0xffffffff)
27679 weight = CW_Constant;
27686 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27687 /// with another that has more specific requirements based on the type of the
27688 /// corresponding operand.
27689 const char *X86TargetLowering::
27690 LowerXConstraint(EVT ConstraintVT) const {
27691 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27692 // 'f' like normal targets.
27693 if (ConstraintVT.isFloatingPoint()) {
27694 if (Subtarget->hasSSE2())
27696 if (Subtarget->hasSSE1())
27700 return TargetLowering::LowerXConstraint(ConstraintVT);
27703 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27704 /// vector. If it is invalid, don't add anything to Ops.
27705 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27706 std::string &Constraint,
27707 std::vector<SDValue>&Ops,
27708 SelectionDAG &DAG) const {
27711 // Only support length 1 constraints for now.
27712 if (Constraint.length() > 1) return;
27714 char ConstraintLetter = Constraint[0];
27715 switch (ConstraintLetter) {
27718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27719 if (C->getZExtValue() <= 31) {
27720 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27721 Op.getValueType());
27727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27728 if (C->getZExtValue() <= 63) {
27729 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27730 Op.getValueType());
27736 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27737 if (isInt<8>(C->getSExtValue())) {
27738 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27739 Op.getValueType());
27745 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27746 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27747 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27748 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27749 Op.getValueType());
27755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27756 if (C->getZExtValue() <= 3) {
27757 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27758 Op.getValueType());
27764 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27765 if (C->getZExtValue() <= 255) {
27766 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27767 Op.getValueType());
27773 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27774 if (C->getZExtValue() <= 127) {
27775 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27776 Op.getValueType());
27782 // 32-bit signed value
27783 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27784 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27785 C->getSExtValue())) {
27786 // Widen to 64 bits here to get it sign extended.
27787 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27790 // FIXME gcc accepts some relocatable values here too, but only in certain
27791 // memory models; it's complicated.
27796 // 32-bit unsigned value
27797 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27798 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27799 C->getZExtValue())) {
27800 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27801 Op.getValueType());
27805 // FIXME gcc accepts some relocatable values here too, but only in certain
27806 // memory models; it's complicated.
27810 // Literal immediates are always ok.
27811 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27812 // Widen to 64 bits here to get it sign extended.
27813 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27817 // In any sort of PIC mode addresses need to be computed at runtime by
27818 // adding in a register or some sort of table lookup. These can't
27819 // be used as immediates.
27820 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27823 // If we are in non-pic codegen mode, we allow the address of a global (with
27824 // an optional displacement) to be used with 'i'.
27825 GlobalAddressSDNode *GA = nullptr;
27826 int64_t Offset = 0;
27828 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27830 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27831 Offset += GA->getOffset();
27833 } else if (Op.getOpcode() == ISD::ADD) {
27834 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27835 Offset += C->getZExtValue();
27836 Op = Op.getOperand(0);
27839 } else if (Op.getOpcode() == ISD::SUB) {
27840 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27841 Offset += -C->getZExtValue();
27842 Op = Op.getOperand(0);
27847 // Otherwise, this isn't something we can handle, reject it.
27851 const GlobalValue *GV = GA->getGlobal();
27852 // If we require an extra load to get this address, as in PIC mode, we
27853 // can't accept it.
27854 if (isGlobalStubReference(
27855 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27858 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27859 GA->getValueType(0), Offset);
27864 if (Result.getNode()) {
27865 Ops.push_back(Result);
27868 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27871 std::pair<unsigned, const TargetRegisterClass *>
27872 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27873 StringRef Constraint,
27875 // First, see if this is a constraint that directly corresponds to an LLVM
27877 if (Constraint.size() == 1) {
27878 // GCC Constraint Letters
27879 switch (Constraint[0]) {
27881 // TODO: Slight differences here in allocation order and leaving
27882 // RIP in the class. Do they matter any more here than they do
27883 // in the normal allocation?
27884 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27885 if (Subtarget->is64Bit()) {
27886 if (VT == MVT::i32 || VT == MVT::f32)
27887 return std::make_pair(0U, &X86::GR32RegClass);
27888 if (VT == MVT::i16)
27889 return std::make_pair(0U, &X86::GR16RegClass);
27890 if (VT == MVT::i8 || VT == MVT::i1)
27891 return std::make_pair(0U, &X86::GR8RegClass);
27892 if (VT == MVT::i64 || VT == MVT::f64)
27893 return std::make_pair(0U, &X86::GR64RegClass);
27896 // 32-bit fallthrough
27897 case 'Q': // Q_REGS
27898 if (VT == MVT::i32 || VT == MVT::f32)
27899 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27900 if (VT == MVT::i16)
27901 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27902 if (VT == MVT::i8 || VT == MVT::i1)
27903 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27904 if (VT == MVT::i64)
27905 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27907 case 'r': // GENERAL_REGS
27908 case 'l': // INDEX_REGS
27909 if (VT == MVT::i8 || VT == MVT::i1)
27910 return std::make_pair(0U, &X86::GR8RegClass);
27911 if (VT == MVT::i16)
27912 return std::make_pair(0U, &X86::GR16RegClass);
27913 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27914 return std::make_pair(0U, &X86::GR32RegClass);
27915 return std::make_pair(0U, &X86::GR64RegClass);
27916 case 'R': // LEGACY_REGS
27917 if (VT == MVT::i8 || VT == MVT::i1)
27918 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27919 if (VT == MVT::i16)
27920 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27921 if (VT == MVT::i32 || !Subtarget->is64Bit())
27922 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27923 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27924 case 'f': // FP Stack registers.
27925 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27926 // value to the correct fpstack register class.
27927 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27928 return std::make_pair(0U, &X86::RFP32RegClass);
27929 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27930 return std::make_pair(0U, &X86::RFP64RegClass);
27931 return std::make_pair(0U, &X86::RFP80RegClass);
27932 case 'y': // MMX_REGS if MMX allowed.
27933 if (!Subtarget->hasMMX()) break;
27934 return std::make_pair(0U, &X86::VR64RegClass);
27935 case 'Y': // SSE_REGS if SSE2 allowed
27936 if (!Subtarget->hasSSE2()) break;
27938 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27939 if (!Subtarget->hasSSE1()) break;
27941 switch (VT.SimpleTy) {
27943 // Scalar SSE types.
27946 return std::make_pair(0U, &X86::FR32RegClass);
27949 return std::make_pair(0U, &X86::FR64RegClass);
27957 return std::make_pair(0U, &X86::VR128RegClass);
27965 return std::make_pair(0U, &X86::VR256RegClass);
27970 return std::make_pair(0U, &X86::VR512RegClass);
27976 // Use the default implementation in TargetLowering to convert the register
27977 // constraint into a member of a register class.
27978 std::pair<unsigned, const TargetRegisterClass*> Res;
27979 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27981 // Not found as a standard register?
27983 // Map st(0) -> st(7) -> ST0
27984 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27985 tolower(Constraint[1]) == 's' &&
27986 tolower(Constraint[2]) == 't' &&
27987 Constraint[3] == '(' &&
27988 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27989 Constraint[5] == ')' &&
27990 Constraint[6] == '}') {
27992 Res.first = X86::FP0+Constraint[4]-'0';
27993 Res.second = &X86::RFP80RegClass;
27997 // GCC allows "st(0)" to be called just plain "st".
27998 if (StringRef("{st}").equals_lower(Constraint)) {
27999 Res.first = X86::FP0;
28000 Res.second = &X86::RFP80RegClass;
28005 if (StringRef("{flags}").equals_lower(Constraint)) {
28006 Res.first = X86::EFLAGS;
28007 Res.second = &X86::CCRRegClass;
28011 // 'A' means EAX + EDX.
28012 if (Constraint == "A") {
28013 Res.first = X86::EAX;
28014 Res.second = &X86::GR32_ADRegClass;
28020 // Otherwise, check to see if this is a register class of the wrong value
28021 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
28022 // turn into {ax},{dx}.
28023 // MVT::Other is used to specify clobber names.
28024 if (Res.second->hasType(VT) || VT == MVT::Other)
28025 return Res; // Correct type already, nothing to do.
28027 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
28028 // return "eax". This should even work for things like getting 64bit integer
28029 // registers when given an f64 type.
28030 const TargetRegisterClass *Class = Res.second;
28031 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
28032 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
28033 unsigned Size = VT.getSizeInBits();
28034 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
28035 : Size == 16 ? MVT::i16
28036 : Size == 32 ? MVT::i32
28037 : Size == 64 ? MVT::i64
28039 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
28041 Res.first = DestReg;
28042 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
28043 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
28044 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
28045 : &X86::GR64RegClass;
28046 assert(Res.second->contains(Res.first) && "Register in register class");
28048 // No register found/type mismatch.
28050 Res.second = nullptr;
28052 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
28053 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
28054 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
28055 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
28056 Class == &X86::VR512RegClass) {
28057 // Handle references to XMM physical registers that got mapped into the
28058 // wrong class. This can happen with constraints like {xmm0} where the
28059 // target independent register mapper will just pick the first match it can
28060 // find, ignoring the required type.
28062 if (VT == MVT::f32 || VT == MVT::i32)
28063 Res.second = &X86::FR32RegClass;
28064 else if (VT == MVT::f64 || VT == MVT::i64)
28065 Res.second = &X86::FR64RegClass;
28066 else if (X86::VR128RegClass.hasType(VT))
28067 Res.second = &X86::VR128RegClass;
28068 else if (X86::VR256RegClass.hasType(VT))
28069 Res.second = &X86::VR256RegClass;
28070 else if (X86::VR512RegClass.hasType(VT))
28071 Res.second = &X86::VR512RegClass;
28073 // Type mismatch and not a clobber: Return an error;
28075 Res.second = nullptr;
28082 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
28083 const AddrMode &AM, Type *Ty,
28084 unsigned AS) const {
28085 // Scaling factors are not free at all.
28086 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
28087 // will take 2 allocations in the out of order engine instead of 1
28088 // for plain addressing mode, i.e. inst (reg1).
28090 // vaddps (%rsi,%drx), %ymm0, %ymm1
28091 // Requires two allocations (one for the load, one for the computation)
28093 // vaddps (%rsi), %ymm0, %ymm1
28094 // Requires just 1 allocation, i.e., freeing allocations for other operations
28095 // and having less micro operations to execute.
28097 // For some X86 architectures, this is even worse because for instance for
28098 // stores, the complex addressing mode forces the instruction to use the
28099 // "load" ports instead of the dedicated "store" port.
28100 // E.g., on Haswell:
28101 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
28102 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
28103 if (isLegalAddressingMode(DL, AM, Ty, AS))
28104 // Scale represents reg2 * scale, thus account for 1
28105 // as soon as we use a second register.
28106 return AM.Scale != 0;
28110 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
28111 // Integer division on x86 is expensive. However, when aggressively optimizing
28112 // for code size, we prefer to use a div instruction, as it is usually smaller
28113 // than the alternative sequence.
28114 // The exception to this is vector division. Since x86 doesn't have vector
28115 // integer division, leaving the division as-is is a loss even in terms of
28116 // size, because it will have to be scalarized, while the alternative code
28117 // sequence can be performed in vector form.
28118 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
28119 Attribute::MinSize);
28120 return OptSize && !VT.isVector();
28123 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
28124 TargetLowering::ArgListTy& Args) const {
28125 // The MCU psABI requires some arguments to be passed in-register.
28126 // For regular calls, the inreg arguments are marked by the front-end.
28127 // However, for compiler generated library calls, we have to patch this
28129 if (!Subtarget->isTargetMCU() || !Args.size())
28132 unsigned FreeRegs = 3;
28133 for (auto &Arg : Args) {
28134 // For library functions, we do not expect any fancy types.
28135 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
28136 unsigned SizeInRegs = (Size + 31) / 32;
28137 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
28140 Arg.isInReg = true;
28141 FreeRegs -= SizeInRegs;