1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/VariadicFunction.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/IR/CallSite.h"
35 #include "llvm/IR/CallingConv.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DerivedTypes.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/GlobalAlias.h"
40 #include "llvm/IR/GlobalVariable.h"
41 #include "llvm/IR/Instructions.h"
42 #include "llvm/IR/Intrinsics.h"
43 #include "llvm/MC/MCAsmInfo.h"
44 #include "llvm/MC/MCContext.h"
45 #include "llvm/MC/MCExpr.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "x86-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
61 static cl::opt<bool> ExperimentalVectorWideningLegalization(
62 "x86-experimental-vector-widening-legalization", cl::init(false),
63 cl::desc("Enable an experimental vector type legalization through widening "
64 "rather than promotion."),
67 static cl::opt<bool> ExperimentalVectorShuffleLowering(
68 "x86-experimental-vector-shuffle-lowering", cl::init(false),
69 cl::desc("Enable an experimental vector shuffle lowering code path."),
72 // Forward declarations.
73 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
76 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
77 SelectionDAG &DAG, SDLoc dl,
78 unsigned vectorWidth) {
79 assert((vectorWidth == 128 || vectorWidth == 256) &&
80 "Unsupported vector width");
81 EVT VT = Vec.getValueType();
82 EVT ElVT = VT.getVectorElementType();
83 unsigned Factor = VT.getSizeInBits()/vectorWidth;
84 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
85 VT.getVectorNumElements()/Factor);
87 // Extract from UNDEF is UNDEF.
88 if (Vec.getOpcode() == ISD::UNDEF)
89 return DAG.getUNDEF(ResultVT);
91 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
92 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
94 // This is the index of the first element of the vectorWidth-bit chunk
96 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
99 // If the input is a buildvector just emit a smaller one.
100 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
101 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
102 makeArrayRef(Vec->op_begin()+NormalizedIdxVal,
105 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
106 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
112 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
113 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
114 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
115 /// instructions or a simple subregister reference. Idx is an index in the
116 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
117 /// lowering EXTRACT_VECTOR_ELT operations easier.
118 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
119 SelectionDAG &DAG, SDLoc dl) {
120 assert((Vec.getValueType().is256BitVector() ||
121 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
122 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
125 /// Generate a DAG to grab 256-bits from a 512-bit vector.
126 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
127 SelectionDAG &DAG, SDLoc dl) {
128 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
129 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
132 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
133 unsigned IdxVal, SelectionDAG &DAG,
134 SDLoc dl, unsigned vectorWidth) {
135 assert((vectorWidth == 128 || vectorWidth == 256) &&
136 "Unsupported vector width");
137 // Inserting UNDEF is Result
138 if (Vec.getOpcode() == ISD::UNDEF)
140 EVT VT = Vec.getValueType();
141 EVT ElVT = VT.getVectorElementType();
142 EVT ResultVT = Result.getValueType();
144 // Insert the relevant vectorWidth bits.
145 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
147 // This is the index of the first element of the vectorWidth-bit chunk
149 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
152 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
153 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
156 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
157 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
158 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
159 /// simple superregister reference. Idx is an index in the 128 bits
160 /// we want. It need not be aligned to a 128-bit bounday. That makes
161 /// lowering INSERT_VECTOR_ELT operations easier.
162 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
163 unsigned IdxVal, SelectionDAG &DAG,
165 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
166 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
169 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
170 unsigned IdxVal, SelectionDAG &DAG,
172 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
173 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
176 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
177 /// instructions. This is used because creating CONCAT_VECTOR nodes of
178 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
179 /// large BUILD_VECTORS.
180 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
181 unsigned NumElems, SelectionDAG &DAG,
183 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
184 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
187 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
188 unsigned NumElems, SelectionDAG &DAG,
190 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
191 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
194 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
195 if (TT.isOSBinFormatMachO()) {
196 if (TT.getArch() == Triple::x86_64)
197 return new X86_64MachoTargetObjectFile();
198 return new TargetLoweringObjectFileMachO();
202 return new X86LinuxTargetObjectFile();
203 if (TT.isOSBinFormatELF())
204 return new TargetLoweringObjectFileELF();
205 if (TT.isKnownWindowsMSVCEnvironment())
206 return new X86WindowsTargetObjectFile();
207 if (TT.isOSBinFormatCOFF())
208 return new TargetLoweringObjectFileCOFF();
209 llvm_unreachable("unknown subtarget type");
212 // FIXME: This should stop caching the target machine as soon as
213 // we can remove resetOperationActions et al.
214 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
215 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))) {
216 Subtarget = &TM.getSubtarget<X86Subtarget>();
217 X86ScalarSSEf64 = Subtarget->hasSSE2();
218 X86ScalarSSEf32 = Subtarget->hasSSE1();
219 TD = getDataLayout();
221 resetOperationActions();
224 void X86TargetLowering::resetOperationActions() {
225 const TargetMachine &TM = getTargetMachine();
226 static bool FirstTimeThrough = true;
228 // If none of the target options have changed, then we don't need to reset the
229 // operation actions.
230 if (!FirstTimeThrough && TO == TM.Options) return;
232 if (!FirstTimeThrough) {
233 // Reinitialize the actions.
235 FirstTimeThrough = false;
240 // Set up the TargetLowering object.
241 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
243 // X86 is weird, it always uses i8 for shift amounts and setcc results.
244 setBooleanContents(ZeroOrOneBooleanContent);
245 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
246 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
248 // For 64-bit since we have so many registers use the ILP scheduler, for
249 // 32-bit code use the register pressure specific scheduling.
250 // For Atom, always use ILP scheduling.
251 if (Subtarget->isAtom())
252 setSchedulingPreference(Sched::ILP);
253 else if (Subtarget->is64Bit())
254 setSchedulingPreference(Sched::ILP);
256 setSchedulingPreference(Sched::RegPressure);
257 const X86RegisterInfo *RegInfo =
258 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
259 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
261 // Bypass expensive divides on Atom when compiling with O2
262 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
263 addBypassSlowDiv(32, 8);
264 if (Subtarget->is64Bit())
265 addBypassSlowDiv(64, 16);
268 if (Subtarget->isTargetKnownWindowsMSVC()) {
269 // Setup Windows compiler runtime calls.
270 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
271 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
272 setLibcallName(RTLIB::SREM_I64, "_allrem");
273 setLibcallName(RTLIB::UREM_I64, "_aullrem");
274 setLibcallName(RTLIB::MUL_I64, "_allmul");
275 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
276 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
277 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
278 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
279 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
281 // The _ftol2 runtime function has an unusual calling conv, which
282 // is modeled by a special pseudo-instruction.
283 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
284 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
285 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
286 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
289 if (Subtarget->isTargetDarwin()) {
290 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
291 setUseUnderscoreSetJmp(false);
292 setUseUnderscoreLongJmp(false);
293 } else if (Subtarget->isTargetWindowsGNU()) {
294 // MS runtime is weird: it exports _setjmp, but longjmp!
295 setUseUnderscoreSetJmp(true);
296 setUseUnderscoreLongJmp(false);
298 setUseUnderscoreSetJmp(true);
299 setUseUnderscoreLongJmp(true);
302 // Set up the register classes.
303 addRegisterClass(MVT::i8, &X86::GR8RegClass);
304 addRegisterClass(MVT::i16, &X86::GR16RegClass);
305 addRegisterClass(MVT::i32, &X86::GR32RegClass);
306 if (Subtarget->is64Bit())
307 addRegisterClass(MVT::i64, &X86::GR64RegClass);
309 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
311 // We don't accept any truncstore of integer registers.
312 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
313 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
314 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
315 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
316 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
317 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
319 // SETOEQ and SETUNE require checking two conditions.
320 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
323 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
327 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
329 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
330 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
331 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
335 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
336 } else if (!TM.Options.UseSoftFloat) {
337 // We have an algorithm for SSE2->double, and we turn this into a
338 // 64-bit FILD followed by conditional FADD for other targets.
339 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
340 // We have an algorithm for SSE2, and we turn this into a 64-bit
341 // FILD for other targets.
342 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
345 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
347 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
348 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
350 if (!TM.Options.UseSoftFloat) {
351 // SSE has no i16 to fp conversion, only i32
352 if (X86ScalarSSEf32) {
353 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
354 // f32 and f64 cases are Legal, f80 case is not
355 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
357 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
358 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
361 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
362 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
365 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
366 // are Legal, f80 is custom lowered.
367 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
368 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
370 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
372 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
373 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
375 if (X86ScalarSSEf32) {
376 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
377 // f32 and f64 cases are Legal, f80 case is not
378 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
380 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
381 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
384 // Handle FP_TO_UINT by promoting the destination to a larger signed
386 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
387 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
388 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
390 if (Subtarget->is64Bit()) {
391 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
392 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
393 } else if (!TM.Options.UseSoftFloat) {
394 // Since AVX is a superset of SSE3, only check for SSE here.
395 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
396 // Expand FP_TO_UINT into a select.
397 // FIXME: We would like to use a Custom expander here eventually to do
398 // the optimal thing for SSE vs. the default expansion in the legalizer.
399 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
401 // With SSE3 we can use fisttpll to convert to a signed i64; without
402 // SSE, we're stuck with a fistpll.
403 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
406 if (isTargetFTOL()) {
407 // Use the _ftol2 runtime function, which has a pseudo-instruction
408 // to handle its weird calling convention.
409 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
412 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
413 if (!X86ScalarSSEf64) {
414 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
415 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
416 if (Subtarget->is64Bit()) {
417 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
418 // Without SSE, i64->f64 goes through memory.
419 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
423 // Scalar integer divide and remainder are lowered to use operations that
424 // produce two results, to match the available instructions. This exposes
425 // the two-result form to trivial CSE, which is able to combine x/y and x%y
426 // into a single instruction.
428 // Scalar integer multiply-high is also lowered to use two-result
429 // operations, to match the available instructions. However, plain multiply
430 // (low) operations are left as Legal, as there are single-result
431 // instructions for this in x86. Using the two-result multiply instructions
432 // when both high and low results are needed must be arranged by dagcombine.
433 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
435 setOperationAction(ISD::MULHS, VT, Expand);
436 setOperationAction(ISD::MULHU, VT, Expand);
437 setOperationAction(ISD::SDIV, VT, Expand);
438 setOperationAction(ISD::UDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UREM, VT, Expand);
442 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
443 setOperationAction(ISD::ADDC, VT, Custom);
444 setOperationAction(ISD::ADDE, VT, Custom);
445 setOperationAction(ISD::SUBC, VT, Custom);
446 setOperationAction(ISD::SUBE, VT, Custom);
449 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
450 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
451 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
452 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
453 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
454 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
455 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
456 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
457 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
458 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
459 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
460 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
461 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
462 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
463 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
464 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
465 if (Subtarget->is64Bit())
466 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
468 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
470 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
471 setOperationAction(ISD::FREM , MVT::f32 , Expand);
472 setOperationAction(ISD::FREM , MVT::f64 , Expand);
473 setOperationAction(ISD::FREM , MVT::f80 , Expand);
474 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
476 // Promote the i8 variants and force them on up to i32 which has a shorter
478 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
479 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
480 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
481 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
482 if (Subtarget->hasBMI()) {
483 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
484 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
485 if (Subtarget->is64Bit())
486 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
488 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
489 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
490 if (Subtarget->is64Bit())
491 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
494 if (Subtarget->hasLZCNT()) {
495 // When promoting the i8 variants, force them to i32 for a shorter
497 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
498 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
500 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
501 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
503 if (Subtarget->is64Bit())
504 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
506 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
507 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
508 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
510 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
511 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
512 if (Subtarget->is64Bit()) {
513 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
514 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
518 // Special handling for half-precision floating point conversions.
519 // If we don't have F16C support, then lower half float conversions
520 // into library calls.
521 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
522 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
523 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
526 // There's never any support for operations beyond MVT::f32.
527 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
528 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
529 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
530 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
532 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
533 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
534 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
535 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
537 if (Subtarget->hasPOPCNT()) {
538 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
540 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
541 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
542 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
543 if (Subtarget->is64Bit())
544 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
547 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
549 if (!Subtarget->hasMOVBE())
550 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
552 // These should be promoted to a larger select which is supported.
553 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
554 // X86 wants to expand cmov itself.
555 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
556 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
557 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
558 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
559 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
560 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
561 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
562 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
563 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
564 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
565 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
566 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
567 if (Subtarget->is64Bit()) {
568 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
569 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
571 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
572 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
573 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
574 // support continuation, user-level threading, and etc.. As a result, no
575 // other SjLj exception interfaces are implemented and please don't build
576 // your own exception handling based on them.
577 // LLVM/Clang supports zero-cost DWARF exception handling.
578 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
579 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
582 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
583 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
584 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
585 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
586 if (Subtarget->is64Bit())
587 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
588 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
589 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
590 if (Subtarget->is64Bit()) {
591 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
592 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
593 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
594 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
595 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
597 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
598 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
599 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
600 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
601 if (Subtarget->is64Bit()) {
602 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
603 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
604 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
607 if (Subtarget->hasSSE1())
608 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
610 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
612 // Expand certain atomics
613 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
615 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
616 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
617 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
620 if (Subtarget->hasCmpxchg16b()) {
621 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
624 // FIXME - use subtarget debug flags
625 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
626 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
627 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
630 if (Subtarget->is64Bit()) {
631 setExceptionPointerRegister(X86::RAX);
632 setExceptionSelectorRegister(X86::RDX);
634 setExceptionPointerRegister(X86::EAX);
635 setExceptionSelectorRegister(X86::EDX);
637 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
638 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
640 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
641 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
643 setOperationAction(ISD::TRAP, MVT::Other, Legal);
644 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
646 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
647 setOperationAction(ISD::VASTART , MVT::Other, Custom);
648 setOperationAction(ISD::VAEND , MVT::Other, Expand);
649 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
650 // TargetInfo::X86_64ABIBuiltinVaList
651 setOperationAction(ISD::VAARG , MVT::Other, Custom);
652 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
654 // TargetInfo::CharPtrBuiltinVaList
655 setOperationAction(ISD::VAARG , MVT::Other, Expand);
656 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
659 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
660 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
662 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
663 MVT::i64 : MVT::i32, Custom);
665 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
666 // f32 and f64 use SSE.
667 // Set up the FP register classes.
668 addRegisterClass(MVT::f32, &X86::FR32RegClass);
669 addRegisterClass(MVT::f64, &X86::FR64RegClass);
671 // Use ANDPD to simulate FABS.
672 setOperationAction(ISD::FABS , MVT::f64, Custom);
673 setOperationAction(ISD::FABS , MVT::f32, Custom);
675 // Use XORP to simulate FNEG.
676 setOperationAction(ISD::FNEG , MVT::f64, Custom);
677 setOperationAction(ISD::FNEG , MVT::f32, Custom);
679 // Use ANDPD and ORPD to simulate FCOPYSIGN.
680 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
681 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
683 // Lower this to FGETSIGNx86 plus an AND.
684 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
685 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
687 // We don't support sin/cos/fmod
688 setOperationAction(ISD::FSIN , MVT::f64, Expand);
689 setOperationAction(ISD::FCOS , MVT::f64, Expand);
690 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
691 setOperationAction(ISD::FSIN , MVT::f32, Expand);
692 setOperationAction(ISD::FCOS , MVT::f32, Expand);
693 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
695 // Expand FP immediates into loads from the stack, except for the special
697 addLegalFPImmediate(APFloat(+0.0)); // xorpd
698 addLegalFPImmediate(APFloat(+0.0f)); // xorps
699 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
700 // Use SSE for f32, x87 for f64.
701 // Set up the FP register classes.
702 addRegisterClass(MVT::f32, &X86::FR32RegClass);
703 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
705 // Use ANDPS to simulate FABS.
706 setOperationAction(ISD::FABS , MVT::f32, Custom);
708 // Use XORP to simulate FNEG.
709 setOperationAction(ISD::FNEG , MVT::f32, Custom);
711 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
713 // Use ANDPS and ORPS to simulate FCOPYSIGN.
714 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
715 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
717 // We don't support sin/cos/fmod
718 setOperationAction(ISD::FSIN , MVT::f32, Expand);
719 setOperationAction(ISD::FCOS , MVT::f32, Expand);
720 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
722 // Special cases we handle for FP constants.
723 addLegalFPImmediate(APFloat(+0.0f)); // xorps
724 addLegalFPImmediate(APFloat(+0.0)); // FLD0
725 addLegalFPImmediate(APFloat(+1.0)); // FLD1
726 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
727 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
729 if (!TM.Options.UnsafeFPMath) {
730 setOperationAction(ISD::FSIN , MVT::f64, Expand);
731 setOperationAction(ISD::FCOS , MVT::f64, Expand);
732 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
734 } else if (!TM.Options.UseSoftFloat) {
735 // f32 and f64 in x87.
736 // Set up the FP register classes.
737 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
738 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
740 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
741 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
742 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
743 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
745 if (!TM.Options.UnsafeFPMath) {
746 setOperationAction(ISD::FSIN , MVT::f64, Expand);
747 setOperationAction(ISD::FSIN , MVT::f32, Expand);
748 setOperationAction(ISD::FCOS , MVT::f64, Expand);
749 setOperationAction(ISD::FCOS , MVT::f32, Expand);
750 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
751 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
753 addLegalFPImmediate(APFloat(+0.0)); // FLD0
754 addLegalFPImmediate(APFloat(+1.0)); // FLD1
755 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
756 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
757 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
758 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
759 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
760 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
763 // We don't support FMA.
764 setOperationAction(ISD::FMA, MVT::f64, Expand);
765 setOperationAction(ISD::FMA, MVT::f32, Expand);
767 // Long double always uses X87.
768 if (!TM.Options.UseSoftFloat) {
769 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
770 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
771 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
773 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
774 addLegalFPImmediate(TmpFlt); // FLD0
776 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
779 APFloat TmpFlt2(+1.0);
780 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
782 addLegalFPImmediate(TmpFlt2); // FLD1
783 TmpFlt2.changeSign();
784 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
787 if (!TM.Options.UnsafeFPMath) {
788 setOperationAction(ISD::FSIN , MVT::f80, Expand);
789 setOperationAction(ISD::FCOS , MVT::f80, Expand);
790 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
793 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
794 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
795 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
796 setOperationAction(ISD::FRINT, MVT::f80, Expand);
797 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
798 setOperationAction(ISD::FMA, MVT::f80, Expand);
801 // Always use a library call for pow.
802 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
803 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
804 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
806 setOperationAction(ISD::FLOG, MVT::f80, Expand);
807 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
808 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
809 setOperationAction(ISD::FEXP, MVT::f80, Expand);
810 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
812 // First set operation action for all vector types to either promote
813 // (for widening) or expand (for scalarization). Then we will selectively
814 // turn on ones that can be effectively codegen'd.
815 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
816 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
817 MVT VT = (MVT::SimpleValueType)i;
818 setOperationAction(ISD::ADD , VT, Expand);
819 setOperationAction(ISD::SUB , VT, Expand);
820 setOperationAction(ISD::FADD, VT, Expand);
821 setOperationAction(ISD::FNEG, VT, Expand);
822 setOperationAction(ISD::FSUB, VT, Expand);
823 setOperationAction(ISD::MUL , VT, Expand);
824 setOperationAction(ISD::FMUL, VT, Expand);
825 setOperationAction(ISD::SDIV, VT, Expand);
826 setOperationAction(ISD::UDIV, VT, Expand);
827 setOperationAction(ISD::FDIV, VT, Expand);
828 setOperationAction(ISD::SREM, VT, Expand);
829 setOperationAction(ISD::UREM, VT, Expand);
830 setOperationAction(ISD::LOAD, VT, Expand);
831 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
832 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
833 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
834 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
835 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
836 setOperationAction(ISD::FABS, VT, Expand);
837 setOperationAction(ISD::FSIN, VT, Expand);
838 setOperationAction(ISD::FSINCOS, VT, Expand);
839 setOperationAction(ISD::FCOS, VT, Expand);
840 setOperationAction(ISD::FSINCOS, VT, Expand);
841 setOperationAction(ISD::FREM, VT, Expand);
842 setOperationAction(ISD::FMA, VT, Expand);
843 setOperationAction(ISD::FPOWI, VT, Expand);
844 setOperationAction(ISD::FSQRT, VT, Expand);
845 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
846 setOperationAction(ISD::FFLOOR, VT, Expand);
847 setOperationAction(ISD::FCEIL, VT, Expand);
848 setOperationAction(ISD::FTRUNC, VT, Expand);
849 setOperationAction(ISD::FRINT, VT, Expand);
850 setOperationAction(ISD::FNEARBYINT, VT, Expand);
851 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
852 setOperationAction(ISD::MULHS, VT, Expand);
853 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
854 setOperationAction(ISD::MULHU, VT, Expand);
855 setOperationAction(ISD::SDIVREM, VT, Expand);
856 setOperationAction(ISD::UDIVREM, VT, Expand);
857 setOperationAction(ISD::FPOW, VT, Expand);
858 setOperationAction(ISD::CTPOP, VT, Expand);
859 setOperationAction(ISD::CTTZ, VT, Expand);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
861 setOperationAction(ISD::CTLZ, VT, Expand);
862 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
863 setOperationAction(ISD::SHL, VT, Expand);
864 setOperationAction(ISD::SRA, VT, Expand);
865 setOperationAction(ISD::SRL, VT, Expand);
866 setOperationAction(ISD::ROTL, VT, Expand);
867 setOperationAction(ISD::ROTR, VT, Expand);
868 setOperationAction(ISD::BSWAP, VT, Expand);
869 setOperationAction(ISD::SETCC, VT, Expand);
870 setOperationAction(ISD::FLOG, VT, Expand);
871 setOperationAction(ISD::FLOG2, VT, Expand);
872 setOperationAction(ISD::FLOG10, VT, Expand);
873 setOperationAction(ISD::FEXP, VT, Expand);
874 setOperationAction(ISD::FEXP2, VT, Expand);
875 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
876 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
877 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
878 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
879 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
880 setOperationAction(ISD::TRUNCATE, VT, Expand);
881 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
882 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
883 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
884 setOperationAction(ISD::VSELECT, VT, Expand);
885 setOperationAction(ISD::SELECT_CC, VT, Expand);
886 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
887 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
888 setTruncStoreAction(VT,
889 (MVT::SimpleValueType)InnerVT, Expand);
890 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
891 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
893 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
894 // we have to deal with them whether we ask for Expansion or not. Setting
895 // Expand causes its own optimisation problems though, so leave them legal.
896 if (VT.getVectorElementType() == MVT::i1)
897 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
900 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
901 // with -msoft-float, disable use of MMX as well.
902 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
903 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
904 // No operations on x86mmx supported, everything uses intrinsics.
907 // MMX-sized vectors (other than x86mmx) are expected to be expanded
908 // into smaller operations.
909 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
910 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
911 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
912 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
913 setOperationAction(ISD::AND, MVT::v8i8, Expand);
914 setOperationAction(ISD::AND, MVT::v4i16, Expand);
915 setOperationAction(ISD::AND, MVT::v2i32, Expand);
916 setOperationAction(ISD::AND, MVT::v1i64, Expand);
917 setOperationAction(ISD::OR, MVT::v8i8, Expand);
918 setOperationAction(ISD::OR, MVT::v4i16, Expand);
919 setOperationAction(ISD::OR, MVT::v2i32, Expand);
920 setOperationAction(ISD::OR, MVT::v1i64, Expand);
921 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
922 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
923 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
924 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
925 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
928 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
930 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
931 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
932 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
933 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
934 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
935 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
936 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
937 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
939 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
940 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
942 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
943 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
944 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
945 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
946 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
947 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
948 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
949 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
950 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
951 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
952 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
953 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
956 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
957 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
959 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
960 // registers cannot be used even for integer operations.
961 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
962 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
963 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
964 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
966 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
967 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
968 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
969 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
971 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
972 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
973 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
974 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
975 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
976 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
977 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
978 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
979 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
980 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
981 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
982 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
983 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
984 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
985 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
986 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
987 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
989 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
990 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
991 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
992 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
994 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
995 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
1001 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1002 MVT VT = (MVT::SimpleValueType)i;
1003 // Do not attempt to custom lower non-power-of-2 vectors
1004 if (!isPowerOf2_32(VT.getVectorNumElements()))
1006 // Do not attempt to custom lower non-128-bit vectors
1007 if (!VT.is128BitVector())
1009 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1010 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1014 // We support custom legalizing of sext and anyext loads for specific
1015 // memory vector types which we can load as a scalar (or sequence of
1016 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1017 // loads these must work with a single scalar load.
1018 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1019 if (Subtarget->is64Bit()) {
1020 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1021 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1023 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1024 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1025 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1026 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1027 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1028 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1030 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1031 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1032 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1033 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1034 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1035 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1037 if (Subtarget->is64Bit()) {
1038 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1039 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1042 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1043 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1044 MVT VT = (MVT::SimpleValueType)i;
1046 // Do not attempt to promote non-128-bit vectors
1047 if (!VT.is128BitVector())
1050 setOperationAction(ISD::AND, VT, Promote);
1051 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1052 setOperationAction(ISD::OR, VT, Promote);
1053 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1054 setOperationAction(ISD::XOR, VT, Promote);
1055 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1056 setOperationAction(ISD::LOAD, VT, Promote);
1057 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1058 setOperationAction(ISD::SELECT, VT, Promote);
1059 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1062 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1064 // Custom lower v2i64 and v2f64 selects.
1065 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1066 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1067 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1068 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1070 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1071 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1074 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1075 // As there is no 64-bit GPR available, we need build a special custom
1076 // sequence to convert from v2i32 to v2f32.
1077 if (!Subtarget->is64Bit())
1078 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1080 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1081 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1083 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1085 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1086 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1087 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1090 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1091 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1092 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1093 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1094 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1095 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1096 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1097 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1098 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1099 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1100 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1102 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1103 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1104 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1105 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1108 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1109 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1110 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1111 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1113 // FIXME: Do we need to handle scalar-to-vector here?
1114 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1116 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1117 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1118 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1119 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1120 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1121 // There is no BLENDI for byte vectors. We don't need to custom lower
1122 // some vselects for now.
1123 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1125 // SSE41 brings specific instructions for doing vector sign extend even in
1126 // cases where we don't have SRA.
1127 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1128 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1129 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1131 // i8 and i16 vectors are custom , because the source register and source
1132 // source memory operand types are not the same width. f32 vectors are
1133 // custom since the immediate controlling the insert encodes additional
1135 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1136 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1137 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1138 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1140 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1141 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1142 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1143 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1145 // FIXME: these should be Legal but thats only for the case where
1146 // the index is constant. For now custom expand to deal with that.
1147 if (Subtarget->is64Bit()) {
1148 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1149 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1153 if (Subtarget->hasSSE2()) {
1154 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1155 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1157 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1158 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1160 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1161 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1163 // In the customized shift lowering, the legal cases in AVX2 will be
1165 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1166 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1168 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1169 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1171 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1174 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1175 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1176 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1177 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1178 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1179 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1180 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1182 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1183 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1184 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1186 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1187 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1188 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1189 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1190 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1191 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1192 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1193 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1194 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1195 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1196 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1197 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1199 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1200 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1201 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1202 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1203 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1205 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1206 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1207 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1208 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1209 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1210 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1212 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1213 // even though v8i16 is a legal type.
1214 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1215 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1216 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1219 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1220 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1222 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1223 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1225 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1227 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1228 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1233 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1234 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1237 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1239 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1241 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1242 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1243 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1245 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1246 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1247 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1248 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1250 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1252 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1253 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1254 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1255 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1256 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1257 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1258 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1259 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1260 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1261 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1263 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1264 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1265 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1266 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1267 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1268 setOperationAction(ISD::FMA, MVT::f32, Legal);
1269 setOperationAction(ISD::FMA, MVT::f64, Legal);
1272 if (Subtarget->hasInt256()) {
1273 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1274 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1275 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1276 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1278 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1279 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1280 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1281 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1283 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1284 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1285 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1286 // Don't lower v32i8 because there is no 128-bit byte mul
1288 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1289 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1290 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1291 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1293 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1294 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1296 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1297 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1298 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1299 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1301 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1302 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1303 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1304 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1306 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1307 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1308 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1309 // Don't lower v32i8 because there is no 128-bit byte mul
1312 // In the customized shift lowering, the legal cases in AVX2 will be
1314 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1315 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1317 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1318 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1320 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1322 // Custom lower several nodes for 256-bit types.
1323 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1324 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1325 MVT VT = (MVT::SimpleValueType)i;
1327 // Extract subvector is special because the value type
1328 // (result) is 128-bit but the source is 256-bit wide.
1329 if (VT.is128BitVector())
1330 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1332 // Do not attempt to custom lower other non-256-bit vectors
1333 if (!VT.is256BitVector())
1336 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1337 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1338 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1339 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1340 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1341 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1342 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1345 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1346 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1347 MVT VT = (MVT::SimpleValueType)i;
1349 // Do not attempt to promote non-256-bit vectors
1350 if (!VT.is256BitVector())
1353 setOperationAction(ISD::AND, VT, Promote);
1354 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1355 setOperationAction(ISD::OR, VT, Promote);
1356 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1357 setOperationAction(ISD::XOR, VT, Promote);
1358 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1359 setOperationAction(ISD::LOAD, VT, Promote);
1360 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1361 setOperationAction(ISD::SELECT, VT, Promote);
1362 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1366 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1367 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1369 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1370 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1372 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1373 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1374 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1376 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1377 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1378 setOperationAction(ISD::XOR, MVT::i1, Legal);
1379 setOperationAction(ISD::OR, MVT::i1, Legal);
1380 setOperationAction(ISD::AND, MVT::i1, Legal);
1381 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1385 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1386 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1388 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1392 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1393 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1395 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1399 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1401 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1402 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1404 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1405 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1406 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1407 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1408 if (Subtarget->is64Bit()) {
1409 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1410 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1411 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1412 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1414 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1417 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1419 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1420 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1422 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1423 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1425 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1426 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1427 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1431 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1439 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1440 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1446 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1447 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1449 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1451 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1452 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1453 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1454 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1455 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1457 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1458 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1461 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1462 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1464 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1465 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1467 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1469 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1470 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1472 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1473 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1475 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1476 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1478 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1479 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1480 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1481 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1482 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1483 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1485 if (Subtarget->hasCDI()) {
1486 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1487 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1490 // Custom lower several nodes.
1491 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1492 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1493 MVT VT = (MVT::SimpleValueType)i;
1495 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1496 // Extract subvector is special because the value type
1497 // (result) is 256/128-bit but the source is 512-bit wide.
1498 if (VT.is128BitVector() || VT.is256BitVector())
1499 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1501 if (VT.getVectorElementType() == MVT::i1)
1502 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1504 // Do not attempt to custom lower other non-512-bit vectors
1505 if (!VT.is512BitVector())
1508 if ( EltSize >= 32) {
1509 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1510 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1511 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1512 setOperationAction(ISD::VSELECT, VT, Legal);
1513 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1514 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1515 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1518 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1519 MVT VT = (MVT::SimpleValueType)i;
1521 // Do not attempt to promote non-256-bit vectors
1522 if (!VT.is512BitVector())
1525 setOperationAction(ISD::SELECT, VT, Promote);
1526 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1530 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1531 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1532 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1535 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1536 // of this type with custom code.
1537 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1538 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1539 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1543 // We want to custom lower some of our intrinsics.
1544 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1545 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1546 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1547 if (!Subtarget->is64Bit())
1548 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1550 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1551 // handle type legalization for these operations here.
1553 // FIXME: We really should do custom legalization for addition and
1554 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1555 // than generic legalization for 64-bit multiplication-with-overflow, though.
1556 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1557 // Add/Sub/Mul with overflow operations are custom lowered.
1559 setOperationAction(ISD::SADDO, VT, Custom);
1560 setOperationAction(ISD::UADDO, VT, Custom);
1561 setOperationAction(ISD::SSUBO, VT, Custom);
1562 setOperationAction(ISD::USUBO, VT, Custom);
1563 setOperationAction(ISD::SMULO, VT, Custom);
1564 setOperationAction(ISD::UMULO, VT, Custom);
1567 // There are no 8-bit 3-address imul/mul instructions
1568 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1569 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1571 if (!Subtarget->is64Bit()) {
1572 // These libcalls are not available in 32-bit.
1573 setLibcallName(RTLIB::SHL_I128, nullptr);
1574 setLibcallName(RTLIB::SRL_I128, nullptr);
1575 setLibcallName(RTLIB::SRA_I128, nullptr);
1578 // Combine sin / cos into one node or libcall if possible.
1579 if (Subtarget->hasSinCos()) {
1580 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1581 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1582 if (Subtarget->isTargetDarwin()) {
1583 // For MacOSX, we don't want to the normal expansion of a libcall to
1584 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1586 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1587 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1591 if (Subtarget->isTargetWin64()) {
1592 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1593 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1594 setOperationAction(ISD::SREM, MVT::i128, Custom);
1595 setOperationAction(ISD::UREM, MVT::i128, Custom);
1596 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1597 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1600 // We have target-specific dag combine patterns for the following nodes:
1601 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1602 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1603 setTargetDAGCombine(ISD::VSELECT);
1604 setTargetDAGCombine(ISD::SELECT);
1605 setTargetDAGCombine(ISD::SHL);
1606 setTargetDAGCombine(ISD::SRA);
1607 setTargetDAGCombine(ISD::SRL);
1608 setTargetDAGCombine(ISD::OR);
1609 setTargetDAGCombine(ISD::AND);
1610 setTargetDAGCombine(ISD::ADD);
1611 setTargetDAGCombine(ISD::FADD);
1612 setTargetDAGCombine(ISD::FSUB);
1613 setTargetDAGCombine(ISD::FMA);
1614 setTargetDAGCombine(ISD::SUB);
1615 setTargetDAGCombine(ISD::LOAD);
1616 setTargetDAGCombine(ISD::STORE);
1617 setTargetDAGCombine(ISD::ZERO_EXTEND);
1618 setTargetDAGCombine(ISD::ANY_EXTEND);
1619 setTargetDAGCombine(ISD::SIGN_EXTEND);
1620 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1621 setTargetDAGCombine(ISD::TRUNCATE);
1622 setTargetDAGCombine(ISD::SINT_TO_FP);
1623 setTargetDAGCombine(ISD::SETCC);
1624 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1625 setTargetDAGCombine(ISD::BUILD_VECTOR);
1626 if (Subtarget->is64Bit())
1627 setTargetDAGCombine(ISD::MUL);
1628 setTargetDAGCombine(ISD::XOR);
1630 computeRegisterProperties();
1632 // On Darwin, -Os means optimize for size without hurting performance,
1633 // do not reduce the limit.
1634 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1635 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1636 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1637 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1638 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1639 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1640 setPrefLoopAlignment(4); // 2^4 bytes.
1642 // Predictable cmov don't hurt on atom because it's in-order.
1643 PredictableSelectIsExpensive = !Subtarget->isAtom();
1645 setPrefFunctionAlignment(4); // 2^4 bytes.
1648 // This has so far only been implemented for 64-bit MachO.
1649 bool X86TargetLowering::useLoadStackGuardNode() const {
1650 return Subtarget->getTargetTriple().getObjectFormat() == Triple::MachO &&
1651 Subtarget->is64Bit();
1654 TargetLoweringBase::LegalizeTypeAction
1655 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1656 if (ExperimentalVectorWideningLegalization &&
1657 VT.getVectorNumElements() != 1 &&
1658 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1659 return TypeWidenVector;
1661 return TargetLoweringBase::getPreferredVectorAction(VT);
1664 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1666 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1668 if (Subtarget->hasAVX512())
1669 switch(VT.getVectorNumElements()) {
1670 case 8: return MVT::v8i1;
1671 case 16: return MVT::v16i1;
1674 return VT.changeVectorElementTypeToInteger();
1677 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1678 /// the desired ByVal argument alignment.
1679 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1682 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1683 if (VTy->getBitWidth() == 128)
1685 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1686 unsigned EltAlign = 0;
1687 getMaxByValAlign(ATy->getElementType(), EltAlign);
1688 if (EltAlign > MaxAlign)
1689 MaxAlign = EltAlign;
1690 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1691 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1692 unsigned EltAlign = 0;
1693 getMaxByValAlign(STy->getElementType(i), EltAlign);
1694 if (EltAlign > MaxAlign)
1695 MaxAlign = EltAlign;
1702 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1703 /// function arguments in the caller parameter area. For X86, aggregates
1704 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1705 /// are at 4-byte boundaries.
1706 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1707 if (Subtarget->is64Bit()) {
1708 // Max of 8 and alignment of type.
1709 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1716 if (Subtarget->hasSSE1())
1717 getMaxByValAlign(Ty, Align);
1721 /// getOptimalMemOpType - Returns the target specific optimal type for load
1722 /// and store operations as a result of memset, memcpy, and memmove
1723 /// lowering. If DstAlign is zero that means it's safe to destination
1724 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1725 /// means there isn't a need to check it against alignment requirement,
1726 /// probably because the source does not need to be loaded. If 'IsMemset' is
1727 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1728 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1729 /// source is constant so it does not need to be loaded.
1730 /// It returns EVT::Other if the type should be determined using generic
1731 /// target-independent logic.
1733 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1734 unsigned DstAlign, unsigned SrcAlign,
1735 bool IsMemset, bool ZeroMemset,
1737 MachineFunction &MF) const {
1738 const Function *F = MF.getFunction();
1739 if ((!IsMemset || ZeroMemset) &&
1740 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1741 Attribute::NoImplicitFloat)) {
1743 (Subtarget->isUnalignedMemAccessFast() ||
1744 ((DstAlign == 0 || DstAlign >= 16) &&
1745 (SrcAlign == 0 || SrcAlign >= 16)))) {
1747 if (Subtarget->hasInt256())
1749 if (Subtarget->hasFp256())
1752 if (Subtarget->hasSSE2())
1754 if (Subtarget->hasSSE1())
1756 } else if (!MemcpyStrSrc && Size >= 8 &&
1757 !Subtarget->is64Bit() &&
1758 Subtarget->hasSSE2()) {
1759 // Do not use f64 to lower memcpy if source is string constant. It's
1760 // better to use i32 to avoid the loads.
1764 if (Subtarget->is64Bit() && Size >= 8)
1769 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1771 return X86ScalarSSEf32;
1772 else if (VT == MVT::f64)
1773 return X86ScalarSSEf64;
1778 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1783 *Fast = Subtarget->isUnalignedMemAccessFast();
1787 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1788 /// current function. The returned value is a member of the
1789 /// MachineJumpTableInfo::JTEntryKind enum.
1790 unsigned X86TargetLowering::getJumpTableEncoding() const {
1791 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1793 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1794 Subtarget->isPICStyleGOT())
1795 return MachineJumpTableInfo::EK_Custom32;
1797 // Otherwise, use the normal jump table encoding heuristics.
1798 return TargetLowering::getJumpTableEncoding();
1802 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1803 const MachineBasicBlock *MBB,
1804 unsigned uid,MCContext &Ctx) const{
1805 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1806 Subtarget->isPICStyleGOT());
1807 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1809 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1810 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1813 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1815 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1816 SelectionDAG &DAG) const {
1817 if (!Subtarget->is64Bit())
1818 // This doesn't have SDLoc associated with it, but is not really the
1819 // same as a Register.
1820 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1824 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1825 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1827 const MCExpr *X86TargetLowering::
1828 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1829 MCContext &Ctx) const {
1830 // X86-64 uses RIP relative addressing based on the jump table label.
1831 if (Subtarget->isPICStyleRIPRel())
1832 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1834 // Otherwise, the reference is relative to the PIC base.
1835 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1838 // FIXME: Why this routine is here? Move to RegInfo!
1839 std::pair<const TargetRegisterClass*, uint8_t>
1840 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1841 const TargetRegisterClass *RRC = nullptr;
1843 switch (VT.SimpleTy) {
1845 return TargetLowering::findRepresentativeClass(VT);
1846 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1847 RRC = Subtarget->is64Bit() ?
1848 (const TargetRegisterClass*)&X86::GR64RegClass :
1849 (const TargetRegisterClass*)&X86::GR32RegClass;
1852 RRC = &X86::VR64RegClass;
1854 case MVT::f32: case MVT::f64:
1855 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1856 case MVT::v4f32: case MVT::v2f64:
1857 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1859 RRC = &X86::VR128RegClass;
1862 return std::make_pair(RRC, Cost);
1865 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1866 unsigned &Offset) const {
1867 if (!Subtarget->isTargetLinux())
1870 if (Subtarget->is64Bit()) {
1871 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1873 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1885 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1886 unsigned DestAS) const {
1887 assert(SrcAS != DestAS && "Expected different address spaces!");
1889 return SrcAS < 256 && DestAS < 256;
1892 //===----------------------------------------------------------------------===//
1893 // Return Value Calling Convention Implementation
1894 //===----------------------------------------------------------------------===//
1896 #include "X86GenCallingConv.inc"
1899 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1900 MachineFunction &MF, bool isVarArg,
1901 const SmallVectorImpl<ISD::OutputArg> &Outs,
1902 LLVMContext &Context) const {
1903 SmallVector<CCValAssign, 16> RVLocs;
1904 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
1906 return CCInfo.CheckReturn(Outs, RetCC_X86);
1909 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1910 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1915 X86TargetLowering::LowerReturn(SDValue Chain,
1916 CallingConv::ID CallConv, bool isVarArg,
1917 const SmallVectorImpl<ISD::OutputArg> &Outs,
1918 const SmallVectorImpl<SDValue> &OutVals,
1919 SDLoc dl, SelectionDAG &DAG) const {
1920 MachineFunction &MF = DAG.getMachineFunction();
1921 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1923 SmallVector<CCValAssign, 16> RVLocs;
1924 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
1925 RVLocs, *DAG.getContext());
1926 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1929 SmallVector<SDValue, 6> RetOps;
1930 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1931 // Operand #1 = Bytes To Pop
1932 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1935 // Copy the result values into the output registers.
1936 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1937 CCValAssign &VA = RVLocs[i];
1938 assert(VA.isRegLoc() && "Can only return in registers!");
1939 SDValue ValToCopy = OutVals[i];
1940 EVT ValVT = ValToCopy.getValueType();
1942 // Promote values to the appropriate types
1943 if (VA.getLocInfo() == CCValAssign::SExt)
1944 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1945 else if (VA.getLocInfo() == CCValAssign::ZExt)
1946 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1947 else if (VA.getLocInfo() == CCValAssign::AExt)
1948 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1949 else if (VA.getLocInfo() == CCValAssign::BCvt)
1950 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1952 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1953 "Unexpected FP-extend for return value.");
1955 // If this is x86-64, and we disabled SSE, we can't return FP values,
1956 // or SSE or MMX vectors.
1957 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1958 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1959 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1960 report_fatal_error("SSE register return with SSE disabled");
1962 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1963 // llvm-gcc has never done it right and no one has noticed, so this
1964 // should be OK for now.
1965 if (ValVT == MVT::f64 &&
1966 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1967 report_fatal_error("SSE2 register return with SSE2 disabled");
1969 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1970 // the RET instruction and handled by the FP Stackifier.
1971 if (VA.getLocReg() == X86::FP0 ||
1972 VA.getLocReg() == X86::FP1) {
1973 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1974 // change the value to the FP stack register class.
1975 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1976 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1977 RetOps.push_back(ValToCopy);
1978 // Don't emit a copytoreg.
1982 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1983 // which is returned in RAX / RDX.
1984 if (Subtarget->is64Bit()) {
1985 if (ValVT == MVT::x86mmx) {
1986 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1987 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1988 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1990 // If we don't have SSE2 available, convert to v4f32 so the generated
1991 // register is legal.
1992 if (!Subtarget->hasSSE2())
1993 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1998 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1999 Flag = Chain.getValue(1);
2000 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2003 // The x86-64 ABIs require that for returning structs by value we copy
2004 // the sret argument into %rax/%eax (depending on ABI) for the return.
2005 // Win32 requires us to put the sret argument to %eax as well.
2006 // We saved the argument into a virtual register in the entry block,
2007 // so now we copy the value out and into %rax/%eax.
2008 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2009 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2010 MachineFunction &MF = DAG.getMachineFunction();
2011 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2012 unsigned Reg = FuncInfo->getSRetReturnReg();
2014 "SRetReturnReg should have been set in LowerFormalArguments().");
2015 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2018 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2019 X86::RAX : X86::EAX;
2020 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2021 Flag = Chain.getValue(1);
2023 // RAX/EAX now acts like a return value.
2024 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2027 RetOps[0] = Chain; // Update chain.
2029 // Add the flag if we have it.
2031 RetOps.push_back(Flag);
2033 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2036 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2037 if (N->getNumValues() != 1)
2039 if (!N->hasNUsesOfValue(1, 0))
2042 SDValue TCChain = Chain;
2043 SDNode *Copy = *N->use_begin();
2044 if (Copy->getOpcode() == ISD::CopyToReg) {
2045 // If the copy has a glue operand, we conservatively assume it isn't safe to
2046 // perform a tail call.
2047 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2049 TCChain = Copy->getOperand(0);
2050 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2053 bool HasRet = false;
2054 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2056 if (UI->getOpcode() != X86ISD::RET_FLAG)
2069 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
2070 ISD::NodeType ExtendKind) const {
2072 // TODO: Is this also valid on 32-bit?
2073 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2074 ReturnMVT = MVT::i8;
2076 ReturnMVT = MVT::i32;
2078 MVT MinVT = getRegisterType(ReturnMVT);
2079 return VT.bitsLT(MinVT) ? MinVT : VT;
2082 /// LowerCallResult - Lower the result values of a call into the
2083 /// appropriate copies out of appropriate physical registers.
2086 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2087 CallingConv::ID CallConv, bool isVarArg,
2088 const SmallVectorImpl<ISD::InputArg> &Ins,
2089 SDLoc dl, SelectionDAG &DAG,
2090 SmallVectorImpl<SDValue> &InVals) const {
2092 // Assign locations to each value returned by this call.
2093 SmallVector<CCValAssign, 16> RVLocs;
2094 bool Is64Bit = Subtarget->is64Bit();
2095 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2096 DAG.getTarget(), RVLocs, *DAG.getContext());
2097 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2099 // Copy all of the result registers out of their specified physreg.
2100 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2101 CCValAssign &VA = RVLocs[i];
2102 EVT CopyVT = VA.getValVT();
2104 // If this is x86-64, and we disabled SSE, we can't return FP values
2105 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2106 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2107 report_fatal_error("SSE register return with SSE disabled");
2110 // If we prefer to use the value in xmm registers, copy it out as f80 and
2111 // use a truncate to move it from fp stack reg to xmm reg.
2112 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2113 isScalarFPTypeInSSEReg(VA.getValVT()))
2116 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2117 CopyVT, InFlag).getValue(1);
2118 SDValue Val = Chain.getValue(0);
2120 if (CopyVT != VA.getValVT())
2121 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2122 // This truncation won't change the value.
2123 DAG.getIntPtrConstant(1));
2125 InFlag = Chain.getValue(2);
2126 InVals.push_back(Val);
2132 //===----------------------------------------------------------------------===//
2133 // C & StdCall & Fast Calling Convention implementation
2134 //===----------------------------------------------------------------------===//
2135 // StdCall calling convention seems to be standard for many Windows' API
2136 // routines and around. It differs from C calling convention just a little:
2137 // callee should clean up the stack, not caller. Symbols should be also
2138 // decorated in some fancy way :) It doesn't support any vector arguments.
2139 // For info on fast calling convention see Fast Calling Convention (tail call)
2140 // implementation LowerX86_32FastCCCallTo.
2142 /// CallIsStructReturn - Determines whether a call uses struct return
2144 enum StructReturnType {
2149 static StructReturnType
2150 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2152 return NotStructReturn;
2154 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2155 if (!Flags.isSRet())
2156 return NotStructReturn;
2157 if (Flags.isInReg())
2158 return RegStructReturn;
2159 return StackStructReturn;
2162 /// ArgsAreStructReturn - Determines whether a function uses struct
2163 /// return semantics.
2164 static StructReturnType
2165 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2167 return NotStructReturn;
2169 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2170 if (!Flags.isSRet())
2171 return NotStructReturn;
2172 if (Flags.isInReg())
2173 return RegStructReturn;
2174 return StackStructReturn;
2177 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2178 /// by "Src" to address "Dst" with size and alignment information specified by
2179 /// the specific parameter attribute. The copy will be passed as a byval
2180 /// function parameter.
2182 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2183 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2185 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2187 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2188 /*isVolatile*/false, /*AlwaysInline=*/true,
2189 MachinePointerInfo(), MachinePointerInfo());
2192 /// IsTailCallConvention - Return true if the calling convention is one that
2193 /// supports tail call optimization.
2194 static bool IsTailCallConvention(CallingConv::ID CC) {
2195 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2196 CC == CallingConv::HiPE);
2199 /// \brief Return true if the calling convention is a C calling convention.
2200 static bool IsCCallConvention(CallingConv::ID CC) {
2201 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2202 CC == CallingConv::X86_64_SysV);
2205 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2206 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2210 CallingConv::ID CalleeCC = CS.getCallingConv();
2211 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2217 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2218 /// a tailcall target by changing its ABI.
2219 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2220 bool GuaranteedTailCallOpt) {
2221 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2225 X86TargetLowering::LowerMemArgument(SDValue Chain,
2226 CallingConv::ID CallConv,
2227 const SmallVectorImpl<ISD::InputArg> &Ins,
2228 SDLoc dl, SelectionDAG &DAG,
2229 const CCValAssign &VA,
2230 MachineFrameInfo *MFI,
2232 // Create the nodes corresponding to a load from this parameter slot.
2233 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2234 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2235 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2236 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2239 // If value is passed by pointer we have address passed instead of the value
2241 if (VA.getLocInfo() == CCValAssign::Indirect)
2242 ValVT = VA.getLocVT();
2244 ValVT = VA.getValVT();
2246 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2247 // changed with more analysis.
2248 // In case of tail call optimization mark all arguments mutable. Since they
2249 // could be overwritten by lowering of arguments in case of a tail call.
2250 if (Flags.isByVal()) {
2251 unsigned Bytes = Flags.getByValSize();
2252 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2253 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2254 return DAG.getFrameIndex(FI, getPointerTy());
2256 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2257 VA.getLocMemOffset(), isImmutable);
2258 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2259 return DAG.getLoad(ValVT, dl, Chain, FIN,
2260 MachinePointerInfo::getFixedStack(FI),
2261 false, false, false, 0);
2266 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2267 CallingConv::ID CallConv,
2269 const SmallVectorImpl<ISD::InputArg> &Ins,
2272 SmallVectorImpl<SDValue> &InVals)
2274 MachineFunction &MF = DAG.getMachineFunction();
2275 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2277 const Function* Fn = MF.getFunction();
2278 if (Fn->hasExternalLinkage() &&
2279 Subtarget->isTargetCygMing() &&
2280 Fn->getName() == "main")
2281 FuncInfo->setForceFramePointer(true);
2283 MachineFrameInfo *MFI = MF.getFrameInfo();
2284 bool Is64Bit = Subtarget->is64Bit();
2285 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2287 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2288 "Var args not supported with calling convention fastcc, ghc or hipe");
2290 // Assign locations to all of the incoming arguments.
2291 SmallVector<CCValAssign, 16> ArgLocs;
2292 CCState CCInfo(CallConv, isVarArg, MF, DAG.getTarget(),
2293 ArgLocs, *DAG.getContext());
2295 // Allocate shadow area for Win64
2297 CCInfo.AllocateStack(32, 8);
2299 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2301 unsigned LastVal = ~0U;
2303 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2304 CCValAssign &VA = ArgLocs[i];
2305 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2307 assert(VA.getValNo() != LastVal &&
2308 "Don't support value assigned to multiple locs yet");
2310 LastVal = VA.getValNo();
2312 if (VA.isRegLoc()) {
2313 EVT RegVT = VA.getLocVT();
2314 const TargetRegisterClass *RC;
2315 if (RegVT == MVT::i32)
2316 RC = &X86::GR32RegClass;
2317 else if (Is64Bit && RegVT == MVT::i64)
2318 RC = &X86::GR64RegClass;
2319 else if (RegVT == MVT::f32)
2320 RC = &X86::FR32RegClass;
2321 else if (RegVT == MVT::f64)
2322 RC = &X86::FR64RegClass;
2323 else if (RegVT.is512BitVector())
2324 RC = &X86::VR512RegClass;
2325 else if (RegVT.is256BitVector())
2326 RC = &X86::VR256RegClass;
2327 else if (RegVT.is128BitVector())
2328 RC = &X86::VR128RegClass;
2329 else if (RegVT == MVT::x86mmx)
2330 RC = &X86::VR64RegClass;
2331 else if (RegVT == MVT::i1)
2332 RC = &X86::VK1RegClass;
2333 else if (RegVT == MVT::v8i1)
2334 RC = &X86::VK8RegClass;
2335 else if (RegVT == MVT::v16i1)
2336 RC = &X86::VK16RegClass;
2337 else if (RegVT == MVT::v32i1)
2338 RC = &X86::VK32RegClass;
2339 else if (RegVT == MVT::v64i1)
2340 RC = &X86::VK64RegClass;
2342 llvm_unreachable("Unknown argument type!");
2344 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2345 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2347 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2348 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2350 if (VA.getLocInfo() == CCValAssign::SExt)
2351 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2352 DAG.getValueType(VA.getValVT()));
2353 else if (VA.getLocInfo() == CCValAssign::ZExt)
2354 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2355 DAG.getValueType(VA.getValVT()));
2356 else if (VA.getLocInfo() == CCValAssign::BCvt)
2357 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2359 if (VA.isExtInLoc()) {
2360 // Handle MMX values passed in XMM regs.
2361 if (RegVT.isVector())
2362 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2364 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2367 assert(VA.isMemLoc());
2368 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2371 // If value is passed via pointer - do a load.
2372 if (VA.getLocInfo() == CCValAssign::Indirect)
2373 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2374 MachinePointerInfo(), false, false, false, 0);
2376 InVals.push_back(ArgValue);
2379 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2380 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2381 // The x86-64 ABIs require that for returning structs by value we copy
2382 // the sret argument into %rax/%eax (depending on ABI) for the return.
2383 // Win32 requires us to put the sret argument to %eax as well.
2384 // Save the argument into a virtual register so that we can access it
2385 // from the return points.
2386 if (Ins[i].Flags.isSRet()) {
2387 unsigned Reg = FuncInfo->getSRetReturnReg();
2389 MVT PtrTy = getPointerTy();
2390 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2391 FuncInfo->setSRetReturnReg(Reg);
2393 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2394 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2400 unsigned StackSize = CCInfo.getNextStackOffset();
2401 // Align stack specially for tail calls.
2402 if (FuncIsMadeTailCallSafe(CallConv,
2403 MF.getTarget().Options.GuaranteedTailCallOpt))
2404 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2406 // If the function takes variable number of arguments, make a frame index for
2407 // the start of the first vararg value... for expansion of llvm.va_start.
2409 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2410 CallConv != CallingConv::X86_ThisCall)) {
2411 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2414 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2416 // FIXME: We should really autogenerate these arrays
2417 static const MCPhysReg GPR64ArgRegsWin64[] = {
2418 X86::RCX, X86::RDX, X86::R8, X86::R9
2420 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2421 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2423 static const MCPhysReg XMMArgRegs64Bit[] = {
2424 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2425 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2427 const MCPhysReg *GPR64ArgRegs;
2428 unsigned NumXMMRegs = 0;
2431 // The XMM registers which might contain var arg parameters are shadowed
2432 // in their paired GPR. So we only need to save the GPR to their home
2434 TotalNumIntRegs = 4;
2435 GPR64ArgRegs = GPR64ArgRegsWin64;
2437 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2438 GPR64ArgRegs = GPR64ArgRegs64Bit;
2440 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2443 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2446 bool NoImplicitFloatOps = Fn->getAttributes().
2447 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2448 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2449 "SSE register cannot be used when SSE is disabled!");
2450 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2451 NoImplicitFloatOps) &&
2452 "SSE register cannot be used when SSE is disabled!");
2453 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2454 !Subtarget->hasSSE1())
2455 // Kernel mode asks for SSE to be disabled, so don't push them
2457 TotalNumXMMRegs = 0;
2460 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2461 // Get to the caller-allocated home save location. Add 8 to account
2462 // for the return address.
2463 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2464 FuncInfo->setRegSaveFrameIndex(
2465 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2466 // Fixup to set vararg frame on shadow area (4 x i64).
2468 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2470 // For X86-64, if there are vararg parameters that are passed via
2471 // registers, then we must store them to their spots on the stack so
2472 // they may be loaded by deferencing the result of va_next.
2473 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2474 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2475 FuncInfo->setRegSaveFrameIndex(
2476 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2480 // Store the integer parameter registers.
2481 SmallVector<SDValue, 8> MemOps;
2482 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2484 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2485 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2486 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2487 DAG.getIntPtrConstant(Offset));
2488 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2489 &X86::GR64RegClass);
2490 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2492 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2493 MachinePointerInfo::getFixedStack(
2494 FuncInfo->getRegSaveFrameIndex(), Offset),
2496 MemOps.push_back(Store);
2500 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2501 // Now store the XMM (fp + vector) parameter registers.
2502 SmallVector<SDValue, 11> SaveXMMOps;
2503 SaveXMMOps.push_back(Chain);
2505 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2506 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2507 SaveXMMOps.push_back(ALVal);
2509 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2510 FuncInfo->getRegSaveFrameIndex()));
2511 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2512 FuncInfo->getVarArgsFPOffset()));
2514 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2515 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2516 &X86::VR128RegClass);
2517 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2518 SaveXMMOps.push_back(Val);
2520 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2521 MVT::Other, SaveXMMOps));
2524 if (!MemOps.empty())
2525 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2529 // Some CCs need callee pop.
2530 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2531 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2532 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2534 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2535 // If this is an sret function, the return should pop the hidden pointer.
2536 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2537 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2538 argsAreStructReturn(Ins) == StackStructReturn)
2539 FuncInfo->setBytesToPopOnReturn(4);
2543 // RegSaveFrameIndex is X86-64 only.
2544 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2545 if (CallConv == CallingConv::X86_FastCall ||
2546 CallConv == CallingConv::X86_ThisCall)
2547 // fastcc functions can't have varargs.
2548 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2551 FuncInfo->setArgumentStackSize(StackSize);
2557 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2558 SDValue StackPtr, SDValue Arg,
2559 SDLoc dl, SelectionDAG &DAG,
2560 const CCValAssign &VA,
2561 ISD::ArgFlagsTy Flags) const {
2562 unsigned LocMemOffset = VA.getLocMemOffset();
2563 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2564 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2565 if (Flags.isByVal())
2566 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2568 return DAG.getStore(Chain, dl, Arg, PtrOff,
2569 MachinePointerInfo::getStack(LocMemOffset),
2573 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2574 /// optimization is performed and it is required.
2576 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2577 SDValue &OutRetAddr, SDValue Chain,
2578 bool IsTailCall, bool Is64Bit,
2579 int FPDiff, SDLoc dl) const {
2580 // Adjust the Return address stack slot.
2581 EVT VT = getPointerTy();
2582 OutRetAddr = getReturnAddressFrameIndex(DAG);
2584 // Load the "old" Return address.
2585 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2586 false, false, false, 0);
2587 return SDValue(OutRetAddr.getNode(), 1);
2590 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2591 /// optimization is performed and it is required (FPDiff!=0).
2592 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2593 SDValue Chain, SDValue RetAddrFrIdx,
2594 EVT PtrVT, unsigned SlotSize,
2595 int FPDiff, SDLoc dl) {
2596 // Store the return address to the appropriate stack slot.
2597 if (!FPDiff) return Chain;
2598 // Calculate the new stack slot for the return address.
2599 int NewReturnAddrFI =
2600 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2602 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2603 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2604 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2610 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2611 SmallVectorImpl<SDValue> &InVals) const {
2612 SelectionDAG &DAG = CLI.DAG;
2614 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2615 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2616 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2617 SDValue Chain = CLI.Chain;
2618 SDValue Callee = CLI.Callee;
2619 CallingConv::ID CallConv = CLI.CallConv;
2620 bool &isTailCall = CLI.IsTailCall;
2621 bool isVarArg = CLI.IsVarArg;
2623 MachineFunction &MF = DAG.getMachineFunction();
2624 bool Is64Bit = Subtarget->is64Bit();
2625 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2626 StructReturnType SR = callIsStructReturn(Outs);
2627 bool IsSibcall = false;
2629 if (MF.getTarget().Options.DisableTailCalls)
2632 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2634 // Force this to be a tail call. The verifier rules are enough to ensure
2635 // that we can lower this successfully without moving the return address
2638 } else if (isTailCall) {
2639 // Check if it's really possible to do a tail call.
2640 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2641 isVarArg, SR != NotStructReturn,
2642 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2643 Outs, OutVals, Ins, DAG);
2645 // Sibcalls are automatically detected tailcalls which do not require
2647 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2654 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2655 "Var args not supported with calling convention fastcc, ghc or hipe");
2657 // Analyze operands of the call, assigning locations to each operand.
2658 SmallVector<CCValAssign, 16> ArgLocs;
2659 CCState CCInfo(CallConv, isVarArg, MF, MF.getTarget(),
2660 ArgLocs, *DAG.getContext());
2662 // Allocate shadow area for Win64
2664 CCInfo.AllocateStack(32, 8);
2666 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2668 // Get a count of how many bytes are to be pushed on the stack.
2669 unsigned NumBytes = CCInfo.getNextStackOffset();
2671 // This is a sibcall. The memory operands are available in caller's
2672 // own caller's stack.
2674 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2675 IsTailCallConvention(CallConv))
2676 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2679 if (isTailCall && !IsSibcall && !IsMustTail) {
2680 // Lower arguments at fp - stackoffset + fpdiff.
2681 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2682 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2684 FPDiff = NumBytesCallerPushed - NumBytes;
2686 // Set the delta of movement of the returnaddr stackslot.
2687 // But only set if delta is greater than previous delta.
2688 if (FPDiff < X86Info->getTCReturnAddrDelta())
2689 X86Info->setTCReturnAddrDelta(FPDiff);
2692 unsigned NumBytesToPush = NumBytes;
2693 unsigned NumBytesToPop = NumBytes;
2695 // If we have an inalloca argument, all stack space has already been allocated
2696 // for us and be right at the top of the stack. We don't support multiple
2697 // arguments passed in memory when using inalloca.
2698 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2700 if (!ArgLocs.back().isMemLoc())
2701 report_fatal_error("cannot use inalloca attribute on a register "
2703 if (ArgLocs.back().getLocMemOffset() != 0)
2704 report_fatal_error("any parameter with the inalloca attribute must be "
2705 "the only memory argument");
2709 Chain = DAG.getCALLSEQ_START(
2710 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2712 SDValue RetAddrFrIdx;
2713 // Load return address for tail calls.
2714 if (isTailCall && FPDiff)
2715 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2716 Is64Bit, FPDiff, dl);
2718 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2719 SmallVector<SDValue, 8> MemOpChains;
2722 // Walk the register/memloc assignments, inserting copies/loads. In the case
2723 // of tail call optimization arguments are handle later.
2724 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2725 DAG.getSubtarget().getRegisterInfo());
2726 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2727 // Skip inalloca arguments, they have already been written.
2728 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2729 if (Flags.isInAlloca())
2732 CCValAssign &VA = ArgLocs[i];
2733 EVT RegVT = VA.getLocVT();
2734 SDValue Arg = OutVals[i];
2735 bool isByVal = Flags.isByVal();
2737 // Promote the value if needed.
2738 switch (VA.getLocInfo()) {
2739 default: llvm_unreachable("Unknown loc info!");
2740 case CCValAssign::Full: break;
2741 case CCValAssign::SExt:
2742 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2744 case CCValAssign::ZExt:
2745 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2747 case CCValAssign::AExt:
2748 if (RegVT.is128BitVector()) {
2749 // Special case: passing MMX values in XMM registers.
2750 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2751 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2752 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2754 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2756 case CCValAssign::BCvt:
2757 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2759 case CCValAssign::Indirect: {
2760 // Store the argument.
2761 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2762 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2763 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2764 MachinePointerInfo::getFixedStack(FI),
2771 if (VA.isRegLoc()) {
2772 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2773 if (isVarArg && IsWin64) {
2774 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2775 // shadow reg if callee is a varargs function.
2776 unsigned ShadowReg = 0;
2777 switch (VA.getLocReg()) {
2778 case X86::XMM0: ShadowReg = X86::RCX; break;
2779 case X86::XMM1: ShadowReg = X86::RDX; break;
2780 case X86::XMM2: ShadowReg = X86::R8; break;
2781 case X86::XMM3: ShadowReg = X86::R9; break;
2784 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2786 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2787 assert(VA.isMemLoc());
2788 if (!StackPtr.getNode())
2789 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2791 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2792 dl, DAG, VA, Flags));
2796 if (!MemOpChains.empty())
2797 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2799 if (Subtarget->isPICStyleGOT()) {
2800 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2803 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2804 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2806 // If we are tail calling and generating PIC/GOT style code load the
2807 // address of the callee into ECX. The value in ecx is used as target of
2808 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2809 // for tail calls on PIC/GOT architectures. Normally we would just put the
2810 // address of GOT into ebx and then call target@PLT. But for tail calls
2811 // ebx would be restored (since ebx is callee saved) before jumping to the
2814 // Note: The actual moving to ECX is done further down.
2815 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2816 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2817 !G->getGlobal()->hasProtectedVisibility())
2818 Callee = LowerGlobalAddress(Callee, DAG);
2819 else if (isa<ExternalSymbolSDNode>(Callee))
2820 Callee = LowerExternalSymbol(Callee, DAG);
2824 if (Is64Bit && isVarArg && !IsWin64) {
2825 // From AMD64 ABI document:
2826 // For calls that may call functions that use varargs or stdargs
2827 // (prototype-less calls or calls to functions containing ellipsis (...) in
2828 // the declaration) %al is used as hidden argument to specify the number
2829 // of SSE registers used. The contents of %al do not need to match exactly
2830 // the number of registers, but must be an ubound on the number of SSE
2831 // registers used and is in the range 0 - 8 inclusive.
2833 // Count the number of XMM registers allocated.
2834 static const MCPhysReg XMMArgRegs[] = {
2835 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2836 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2838 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2839 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2840 && "SSE registers cannot be used when SSE is disabled");
2842 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2843 DAG.getConstant(NumXMMRegs, MVT::i8)));
2846 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2847 // don't need this because the eligibility check rejects calls that require
2848 // shuffling arguments passed in memory.
2849 if (!IsSibcall && isTailCall) {
2850 // Force all the incoming stack arguments to be loaded from the stack
2851 // before any new outgoing arguments are stored to the stack, because the
2852 // outgoing stack slots may alias the incoming argument stack slots, and
2853 // the alias isn't otherwise explicit. This is slightly more conservative
2854 // than necessary, because it means that each store effectively depends
2855 // on every argument instead of just those arguments it would clobber.
2856 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2858 SmallVector<SDValue, 8> MemOpChains2;
2861 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2862 CCValAssign &VA = ArgLocs[i];
2865 assert(VA.isMemLoc());
2866 SDValue Arg = OutVals[i];
2867 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2868 // Skip inalloca arguments. They don't require any work.
2869 if (Flags.isInAlloca())
2871 // Create frame index.
2872 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2873 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2874 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2875 FIN = DAG.getFrameIndex(FI, getPointerTy());
2877 if (Flags.isByVal()) {
2878 // Copy relative to framepointer.
2879 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2880 if (!StackPtr.getNode())
2881 StackPtr = DAG.getCopyFromReg(Chain, dl,
2882 RegInfo->getStackRegister(),
2884 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2886 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2890 // Store relative to framepointer.
2891 MemOpChains2.push_back(
2892 DAG.getStore(ArgChain, dl, Arg, FIN,
2893 MachinePointerInfo::getFixedStack(FI),
2898 if (!MemOpChains2.empty())
2899 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
2901 // Store the return address to the appropriate stack slot.
2902 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2903 getPointerTy(), RegInfo->getSlotSize(),
2907 // Build a sequence of copy-to-reg nodes chained together with token chain
2908 // and flag operands which copy the outgoing args into registers.
2910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2911 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2912 RegsToPass[i].second, InFlag);
2913 InFlag = Chain.getValue(1);
2916 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
2917 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2918 // In the 64-bit large code model, we have to make all calls
2919 // through a register, since the call instruction's 32-bit
2920 // pc-relative offset may not be large enough to hold the whole
2922 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2923 // If the callee is a GlobalAddress node (quite common, every direct call
2924 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2927 // We should use extra load for direct calls to dllimported functions in
2929 const GlobalValue *GV = G->getGlobal();
2930 if (!GV->hasDLLImportStorageClass()) {
2931 unsigned char OpFlags = 0;
2932 bool ExtraLoad = false;
2933 unsigned WrapperKind = ISD::DELETED_NODE;
2935 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2936 // external symbols most go through the PLT in PIC mode. If the symbol
2937 // has hidden or protected visibility, or if it is static or local, then
2938 // we don't need to use the PLT - we can directly call it.
2939 if (Subtarget->isTargetELF() &&
2940 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
2941 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2942 OpFlags = X86II::MO_PLT;
2943 } else if (Subtarget->isPICStyleStubAny() &&
2944 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2945 (!Subtarget->getTargetTriple().isMacOSX() ||
2946 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2947 // PC-relative references to external symbols should go through $stub,
2948 // unless we're building with the leopard linker or later, which
2949 // automatically synthesizes these stubs.
2950 OpFlags = X86II::MO_DARWIN_STUB;
2951 } else if (Subtarget->isPICStyleRIPRel() &&
2952 isa<Function>(GV) &&
2953 cast<Function>(GV)->getAttributes().
2954 hasAttribute(AttributeSet::FunctionIndex,
2955 Attribute::NonLazyBind)) {
2956 // If the function is marked as non-lazy, generate an indirect call
2957 // which loads from the GOT directly. This avoids runtime overhead
2958 // at the cost of eager binding (and one extra byte of encoding).
2959 OpFlags = X86II::MO_GOTPCREL;
2960 WrapperKind = X86ISD::WrapperRIP;
2964 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2965 G->getOffset(), OpFlags);
2967 // Add a wrapper if needed.
2968 if (WrapperKind != ISD::DELETED_NODE)
2969 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2970 // Add extra indirection if needed.
2972 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2973 MachinePointerInfo::getGOT(),
2974 false, false, false, 0);
2976 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2977 unsigned char OpFlags = 0;
2979 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2980 // external symbols should go through the PLT.
2981 if (Subtarget->isTargetELF() &&
2982 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
2983 OpFlags = X86II::MO_PLT;
2984 } else if (Subtarget->isPICStyleStubAny() &&
2985 (!Subtarget->getTargetTriple().isMacOSX() ||
2986 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2987 // PC-relative references to external symbols should go through $stub,
2988 // unless we're building with the leopard linker or later, which
2989 // automatically synthesizes these stubs.
2990 OpFlags = X86II::MO_DARWIN_STUB;
2993 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2997 // Returns a chain & a flag for retval copy to use.
2998 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2999 SmallVector<SDValue, 8> Ops;
3001 if (!IsSibcall && isTailCall) {
3002 Chain = DAG.getCALLSEQ_END(Chain,
3003 DAG.getIntPtrConstant(NumBytesToPop, true),
3004 DAG.getIntPtrConstant(0, true), InFlag, dl);
3005 InFlag = Chain.getValue(1);
3008 Ops.push_back(Chain);
3009 Ops.push_back(Callee);
3012 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3014 // Add argument registers to the end of the list so that they are known live
3016 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3017 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3018 RegsToPass[i].second.getValueType()));
3020 // Add a register mask operand representing the call-preserved registers.
3021 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3022 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3023 assert(Mask && "Missing call preserved mask for calling convention");
3024 Ops.push_back(DAG.getRegisterMask(Mask));
3026 if (InFlag.getNode())
3027 Ops.push_back(InFlag);
3031 //// If this is the first return lowered for this function, add the regs
3032 //// to the liveout set for the function.
3033 // This isn't right, although it's probably harmless on x86; liveouts
3034 // should be computed from returns not tail calls. Consider a void
3035 // function making a tail call to a function returning int.
3036 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3039 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3040 InFlag = Chain.getValue(1);
3042 // Create the CALLSEQ_END node.
3043 unsigned NumBytesForCalleeToPop;
3044 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3045 DAG.getTarget().Options.GuaranteedTailCallOpt))
3046 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3047 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3048 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3049 SR == StackStructReturn)
3050 // If this is a call to a struct-return function, the callee
3051 // pops the hidden struct pointer, so we have to push it back.
3052 // This is common for Darwin/X86, Linux & Mingw32 targets.
3053 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3054 NumBytesForCalleeToPop = 4;
3056 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3058 // Returns a flag for retval copy to use.
3060 Chain = DAG.getCALLSEQ_END(Chain,
3061 DAG.getIntPtrConstant(NumBytesToPop, true),
3062 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3065 InFlag = Chain.getValue(1);
3068 // Handle result values, copying them out of physregs into vregs that we
3070 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3071 Ins, dl, DAG, InVals);
3074 //===----------------------------------------------------------------------===//
3075 // Fast Calling Convention (tail call) implementation
3076 //===----------------------------------------------------------------------===//
3078 // Like std call, callee cleans arguments, convention except that ECX is
3079 // reserved for storing the tail called function address. Only 2 registers are
3080 // free for argument passing (inreg). Tail call optimization is performed
3082 // * tailcallopt is enabled
3083 // * caller/callee are fastcc
3084 // On X86_64 architecture with GOT-style position independent code only local
3085 // (within module) calls are supported at the moment.
3086 // To keep the stack aligned according to platform abi the function
3087 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3088 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3089 // If a tail called function callee has more arguments than the caller the
3090 // caller needs to make sure that there is room to move the RETADDR to. This is
3091 // achieved by reserving an area the size of the argument delta right after the
3092 // original RETADDR, but before the saved framepointer or the spilled registers
3093 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3105 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3106 /// for a 16 byte align requirement.
3108 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3109 SelectionDAG& DAG) const {
3110 MachineFunction &MF = DAG.getMachineFunction();
3111 const TargetMachine &TM = MF.getTarget();
3112 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3113 TM.getSubtargetImpl()->getRegisterInfo());
3114 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3115 unsigned StackAlignment = TFI.getStackAlignment();
3116 uint64_t AlignMask = StackAlignment - 1;
3117 int64_t Offset = StackSize;
3118 unsigned SlotSize = RegInfo->getSlotSize();
3119 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3120 // Number smaller than 12 so just add the difference.
3121 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3123 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3124 Offset = ((~AlignMask) & Offset) + StackAlignment +
3125 (StackAlignment-SlotSize);
3130 /// MatchingStackOffset - Return true if the given stack call argument is
3131 /// already available in the same position (relatively) of the caller's
3132 /// incoming argument stack.
3134 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3135 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3136 const X86InstrInfo *TII) {
3137 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3139 if (Arg.getOpcode() == ISD::CopyFromReg) {
3140 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3141 if (!TargetRegisterInfo::isVirtualRegister(VR))
3143 MachineInstr *Def = MRI->getVRegDef(VR);
3146 if (!Flags.isByVal()) {
3147 if (!TII->isLoadFromStackSlot(Def, FI))
3150 unsigned Opcode = Def->getOpcode();
3151 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3152 Def->getOperand(1).isFI()) {
3153 FI = Def->getOperand(1).getIndex();
3154 Bytes = Flags.getByValSize();
3158 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3159 if (Flags.isByVal())
3160 // ByVal argument is passed in as a pointer but it's now being
3161 // dereferenced. e.g.
3162 // define @foo(%struct.X* %A) {
3163 // tail call @bar(%struct.X* byval %A)
3166 SDValue Ptr = Ld->getBasePtr();
3167 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3170 FI = FINode->getIndex();
3171 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3172 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3173 FI = FINode->getIndex();
3174 Bytes = Flags.getByValSize();
3178 assert(FI != INT_MAX);
3179 if (!MFI->isFixedObjectIndex(FI))
3181 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3184 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3185 /// for tail call optimization. Targets which want to do tail call
3186 /// optimization should implement this function.
3188 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3189 CallingConv::ID CalleeCC,
3191 bool isCalleeStructRet,
3192 bool isCallerStructRet,
3194 const SmallVectorImpl<ISD::OutputArg> &Outs,
3195 const SmallVectorImpl<SDValue> &OutVals,
3196 const SmallVectorImpl<ISD::InputArg> &Ins,
3197 SelectionDAG &DAG) const {
3198 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3201 // If -tailcallopt is specified, make fastcc functions tail-callable.
3202 const MachineFunction &MF = DAG.getMachineFunction();
3203 const Function *CallerF = MF.getFunction();
3205 // If the function return type is x86_fp80 and the callee return type is not,
3206 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3207 // perform a tailcall optimization here.
3208 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3211 CallingConv::ID CallerCC = CallerF->getCallingConv();
3212 bool CCMatch = CallerCC == CalleeCC;
3213 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3214 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3216 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3217 if (IsTailCallConvention(CalleeCC) && CCMatch)
3222 // Look for obvious safe cases to perform tail call optimization that do not
3223 // require ABI changes. This is what gcc calls sibcall.
3225 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3226 // emit a special epilogue.
3227 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3228 DAG.getSubtarget().getRegisterInfo());
3229 if (RegInfo->needsStackRealignment(MF))
3232 // Also avoid sibcall optimization if either caller or callee uses struct
3233 // return semantics.
3234 if (isCalleeStructRet || isCallerStructRet)
3237 // An stdcall/thiscall caller is expected to clean up its arguments; the
3238 // callee isn't going to do that.
3239 // FIXME: this is more restrictive than needed. We could produce a tailcall
3240 // when the stack adjustment matches. For example, with a thiscall that takes
3241 // only one argument.
3242 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3243 CallerCC == CallingConv::X86_ThisCall))
3246 // Do not sibcall optimize vararg calls unless all arguments are passed via
3248 if (isVarArg && !Outs.empty()) {
3250 // Optimizing for varargs on Win64 is unlikely to be safe without
3251 // additional testing.
3252 if (IsCalleeWin64 || IsCallerWin64)
3255 SmallVector<CCValAssign, 16> ArgLocs;
3256 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3257 DAG.getTarget(), ArgLocs, *DAG.getContext());
3259 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3260 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3261 if (!ArgLocs[i].isRegLoc())
3265 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3266 // stack. Therefore, if it's not used by the call it is not safe to optimize
3267 // this into a sibcall.
3268 bool Unused = false;
3269 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3276 SmallVector<CCValAssign, 16> RVLocs;
3277 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3278 DAG.getTarget(), RVLocs, *DAG.getContext());
3279 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3280 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3281 CCValAssign &VA = RVLocs[i];
3282 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3287 // If the calling conventions do not match, then we'd better make sure the
3288 // results are returned in the same way as what the caller expects.
3290 SmallVector<CCValAssign, 16> RVLocs1;
3291 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3292 DAG.getTarget(), RVLocs1, *DAG.getContext());
3293 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3295 SmallVector<CCValAssign, 16> RVLocs2;
3296 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3297 DAG.getTarget(), RVLocs2, *DAG.getContext());
3298 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3300 if (RVLocs1.size() != RVLocs2.size())
3302 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3303 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3305 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3307 if (RVLocs1[i].isRegLoc()) {
3308 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3311 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3317 // If the callee takes no arguments then go on to check the results of the
3319 if (!Outs.empty()) {
3320 // Check if stack adjustment is needed. For now, do not do this if any
3321 // argument is passed on the stack.
3322 SmallVector<CCValAssign, 16> ArgLocs;
3323 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3324 DAG.getTarget(), ArgLocs, *DAG.getContext());
3326 // Allocate shadow area for Win64
3328 CCInfo.AllocateStack(32, 8);
3330 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3331 if (CCInfo.getNextStackOffset()) {
3332 MachineFunction &MF = DAG.getMachineFunction();
3333 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3336 // Check if the arguments are already laid out in the right way as
3337 // the caller's fixed stack objects.
3338 MachineFrameInfo *MFI = MF.getFrameInfo();
3339 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3340 const X86InstrInfo *TII =
3341 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3342 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3343 CCValAssign &VA = ArgLocs[i];
3344 SDValue Arg = OutVals[i];
3345 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3346 if (VA.getLocInfo() == CCValAssign::Indirect)
3348 if (!VA.isRegLoc()) {
3349 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3356 // If the tailcall address may be in a register, then make sure it's
3357 // possible to register allocate for it. In 32-bit, the call address can
3358 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3359 // callee-saved registers are restored. These happen to be the same
3360 // registers used to pass 'inreg' arguments so watch out for those.
3361 if (!Subtarget->is64Bit() &&
3362 ((!isa<GlobalAddressSDNode>(Callee) &&
3363 !isa<ExternalSymbolSDNode>(Callee)) ||
3364 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3365 unsigned NumInRegs = 0;
3366 // In PIC we need an extra register to formulate the address computation
3368 unsigned MaxInRegs =
3369 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3371 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3372 CCValAssign &VA = ArgLocs[i];
3375 unsigned Reg = VA.getLocReg();
3378 case X86::EAX: case X86::EDX: case X86::ECX:
3379 if (++NumInRegs == MaxInRegs)
3391 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3392 const TargetLibraryInfo *libInfo) const {
3393 return X86::createFastISel(funcInfo, libInfo);
3396 //===----------------------------------------------------------------------===//
3397 // Other Lowering Hooks
3398 //===----------------------------------------------------------------------===//
3400 static bool MayFoldLoad(SDValue Op) {
3401 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3404 static bool MayFoldIntoStore(SDValue Op) {
3405 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3408 static bool isTargetShuffle(unsigned Opcode) {
3410 default: return false;
3411 case X86ISD::PSHUFB:
3412 case X86ISD::PSHUFD:
3413 case X86ISD::PSHUFHW:
3414 case X86ISD::PSHUFLW:
3416 case X86ISD::PALIGNR:
3417 case X86ISD::MOVLHPS:
3418 case X86ISD::MOVLHPD:
3419 case X86ISD::MOVHLPS:
3420 case X86ISD::MOVLPS:
3421 case X86ISD::MOVLPD:
3422 case X86ISD::MOVSHDUP:
3423 case X86ISD::MOVSLDUP:
3424 case X86ISD::MOVDDUP:
3427 case X86ISD::UNPCKL:
3428 case X86ISD::UNPCKH:
3429 case X86ISD::VPERMILP:
3430 case X86ISD::VPERM2X128:
3431 case X86ISD::VPERMI:
3436 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3437 SDValue V1, SelectionDAG &DAG) {
3439 default: llvm_unreachable("Unknown x86 shuffle node");
3440 case X86ISD::MOVSHDUP:
3441 case X86ISD::MOVSLDUP:
3442 case X86ISD::MOVDDUP:
3443 return DAG.getNode(Opc, dl, VT, V1);
3447 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3448 SDValue V1, unsigned TargetMask,
3449 SelectionDAG &DAG) {
3451 default: llvm_unreachable("Unknown x86 shuffle node");
3452 case X86ISD::PSHUFD:
3453 case X86ISD::PSHUFHW:
3454 case X86ISD::PSHUFLW:
3455 case X86ISD::VPERMILP:
3456 case X86ISD::VPERMI:
3457 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3461 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3462 SDValue V1, SDValue V2, unsigned TargetMask,
3463 SelectionDAG &DAG) {
3465 default: llvm_unreachable("Unknown x86 shuffle node");
3466 case X86ISD::PALIGNR:
3467 case X86ISD::VALIGN:
3469 case X86ISD::VPERM2X128:
3470 return DAG.getNode(Opc, dl, VT, V1, V2,
3471 DAG.getConstant(TargetMask, MVT::i8));
3475 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3476 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3478 default: llvm_unreachable("Unknown x86 shuffle node");
3479 case X86ISD::MOVLHPS:
3480 case X86ISD::MOVLHPD:
3481 case X86ISD::MOVHLPS:
3482 case X86ISD::MOVLPS:
3483 case X86ISD::MOVLPD:
3486 case X86ISD::UNPCKL:
3487 case X86ISD::UNPCKH:
3488 return DAG.getNode(Opc, dl, VT, V1, V2);
3492 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3493 MachineFunction &MF = DAG.getMachineFunction();
3494 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3495 DAG.getSubtarget().getRegisterInfo());
3496 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3497 int ReturnAddrIndex = FuncInfo->getRAIndex();
3499 if (ReturnAddrIndex == 0) {
3500 // Set up a frame object for the return address.
3501 unsigned SlotSize = RegInfo->getSlotSize();
3502 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3505 FuncInfo->setRAIndex(ReturnAddrIndex);
3508 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3511 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3512 bool hasSymbolicDisplacement) {
3513 // Offset should fit into 32 bit immediate field.
3514 if (!isInt<32>(Offset))
3517 // If we don't have a symbolic displacement - we don't have any extra
3519 if (!hasSymbolicDisplacement)
3522 // FIXME: Some tweaks might be needed for medium code model.
3523 if (M != CodeModel::Small && M != CodeModel::Kernel)
3526 // For small code model we assume that latest object is 16MB before end of 31
3527 // bits boundary. We may also accept pretty large negative constants knowing
3528 // that all objects are in the positive half of address space.
3529 if (M == CodeModel::Small && Offset < 16*1024*1024)
3532 // For kernel code model we know that all object resist in the negative half
3533 // of 32bits address space. We may not accept negative offsets, since they may
3534 // be just off and we may accept pretty large positive ones.
3535 if (M == CodeModel::Kernel && Offset > 0)
3541 /// isCalleePop - Determines whether the callee is required to pop its
3542 /// own arguments. Callee pop is necessary to support tail calls.
3543 bool X86::isCalleePop(CallingConv::ID CallingConv,
3544 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3548 switch (CallingConv) {
3551 case CallingConv::X86_StdCall:
3553 case CallingConv::X86_FastCall:
3555 case CallingConv::X86_ThisCall:
3557 case CallingConv::Fast:
3559 case CallingConv::GHC:
3561 case CallingConv::HiPE:
3566 /// \brief Return true if the condition is an unsigned comparison operation.
3567 static bool isX86CCUnsigned(unsigned X86CC) {
3569 default: llvm_unreachable("Invalid integer condition!");
3570 case X86::COND_E: return true;
3571 case X86::COND_G: return false;
3572 case X86::COND_GE: return false;
3573 case X86::COND_L: return false;
3574 case X86::COND_LE: return false;
3575 case X86::COND_NE: return true;
3576 case X86::COND_B: return true;
3577 case X86::COND_A: return true;
3578 case X86::COND_BE: return true;
3579 case X86::COND_AE: return true;
3581 llvm_unreachable("covered switch fell through?!");
3584 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3585 /// specific condition code, returning the condition code and the LHS/RHS of the
3586 /// comparison to make.
3587 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3588 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3590 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3591 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3592 // X > -1 -> X == 0, jump !sign.
3593 RHS = DAG.getConstant(0, RHS.getValueType());
3594 return X86::COND_NS;
3596 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3597 // X < 0 -> X == 0, jump on sign.
3600 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3602 RHS = DAG.getConstant(0, RHS.getValueType());
3603 return X86::COND_LE;
3607 switch (SetCCOpcode) {
3608 default: llvm_unreachable("Invalid integer condition!");
3609 case ISD::SETEQ: return X86::COND_E;
3610 case ISD::SETGT: return X86::COND_G;
3611 case ISD::SETGE: return X86::COND_GE;
3612 case ISD::SETLT: return X86::COND_L;
3613 case ISD::SETLE: return X86::COND_LE;
3614 case ISD::SETNE: return X86::COND_NE;
3615 case ISD::SETULT: return X86::COND_B;
3616 case ISD::SETUGT: return X86::COND_A;
3617 case ISD::SETULE: return X86::COND_BE;
3618 case ISD::SETUGE: return X86::COND_AE;
3622 // First determine if it is required or is profitable to flip the operands.
3624 // If LHS is a foldable load, but RHS is not, flip the condition.
3625 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3626 !ISD::isNON_EXTLoad(RHS.getNode())) {
3627 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3628 std::swap(LHS, RHS);
3631 switch (SetCCOpcode) {
3637 std::swap(LHS, RHS);
3641 // On a floating point condition, the flags are set as follows:
3643 // 0 | 0 | 0 | X > Y
3644 // 0 | 0 | 1 | X < Y
3645 // 1 | 0 | 0 | X == Y
3646 // 1 | 1 | 1 | unordered
3647 switch (SetCCOpcode) {
3648 default: llvm_unreachable("Condcode should be pre-legalized away");
3650 case ISD::SETEQ: return X86::COND_E;
3651 case ISD::SETOLT: // flipped
3653 case ISD::SETGT: return X86::COND_A;
3654 case ISD::SETOLE: // flipped
3656 case ISD::SETGE: return X86::COND_AE;
3657 case ISD::SETUGT: // flipped
3659 case ISD::SETLT: return X86::COND_B;
3660 case ISD::SETUGE: // flipped
3662 case ISD::SETLE: return X86::COND_BE;
3664 case ISD::SETNE: return X86::COND_NE;
3665 case ISD::SETUO: return X86::COND_P;
3666 case ISD::SETO: return X86::COND_NP;
3668 case ISD::SETUNE: return X86::COND_INVALID;
3672 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3673 /// code. Current x86 isa includes the following FP cmov instructions:
3674 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3675 static bool hasFPCMov(unsigned X86CC) {
3691 /// isFPImmLegal - Returns true if the target can instruction select the
3692 /// specified FP immediate natively. If false, the legalizer will
3693 /// materialize the FP immediate as a load from a constant pool.
3694 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3695 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3696 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3702 /// \brief Returns true if it is beneficial to convert a load of a constant
3703 /// to just the constant itself.
3704 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3706 assert(Ty->isIntegerTy());
3708 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3709 if (BitSize == 0 || BitSize > 64)
3714 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3715 /// the specified range (L, H].
3716 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3717 return (Val < 0) || (Val >= Low && Val < Hi);
3720 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3721 /// specified value.
3722 static bool isUndefOrEqual(int Val, int CmpVal) {
3723 return (Val < 0 || Val == CmpVal);
3726 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3727 /// from position Pos and ending in Pos+Size, falls within the specified
3728 /// sequential range (L, L+Pos]. or is undef.
3729 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3730 unsigned Pos, unsigned Size, int Low) {
3731 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3732 if (!isUndefOrEqual(Mask[i], Low))
3737 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3738 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3739 /// the second operand.
3740 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT) {
3741 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3742 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3743 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3744 return (Mask[0] < 2 && Mask[1] < 2);
3748 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3749 /// is suitable for input to PSHUFHW.
3750 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3751 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3754 // Lower quadword copied in order or undef.
3755 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3758 // Upper quadword shuffled.
3759 for (unsigned i = 4; i != 8; ++i)
3760 if (!isUndefOrInRange(Mask[i], 4, 8))
3763 if (VT == MVT::v16i16) {
3764 // Lower quadword copied in order or undef.
3765 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3768 // Upper quadword shuffled.
3769 for (unsigned i = 12; i != 16; ++i)
3770 if (!isUndefOrInRange(Mask[i], 12, 16))
3777 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3778 /// is suitable for input to PSHUFLW.
3779 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3780 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3783 // Upper quadword copied in order.
3784 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3787 // Lower quadword shuffled.
3788 for (unsigned i = 0; i != 4; ++i)
3789 if (!isUndefOrInRange(Mask[i], 0, 4))
3792 if (VT == MVT::v16i16) {
3793 // Upper quadword copied in order.
3794 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3797 // Lower quadword shuffled.
3798 for (unsigned i = 8; i != 12; ++i)
3799 if (!isUndefOrInRange(Mask[i], 8, 12))
3806 /// \brief Return true if the mask specifies a shuffle of elements that is
3807 /// suitable for input to intralane (palignr) or interlane (valign) vector
3809 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3810 unsigned NumElts = VT.getVectorNumElements();
3811 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3812 unsigned NumLaneElts = NumElts/NumLanes;
3814 // Do not handle 64-bit element shuffles with palignr.
3815 if (NumLaneElts == 2)
3818 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3820 for (i = 0; i != NumLaneElts; ++i) {
3825 // Lane is all undef, go to next lane
3826 if (i == NumLaneElts)
3829 int Start = Mask[i+l];
3831 // Make sure its in this lane in one of the sources
3832 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3833 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3836 // If not lane 0, then we must match lane 0
3837 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3840 // Correct second source to be contiguous with first source
3841 if (Start >= (int)NumElts)
3842 Start -= NumElts - NumLaneElts;
3844 // Make sure we're shifting in the right direction.
3845 if (Start <= (int)(i+l))
3850 // Check the rest of the elements to see if they are consecutive.
3851 for (++i; i != NumLaneElts; ++i) {
3852 int Idx = Mask[i+l];
3854 // Make sure its in this lane
3855 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3856 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3859 // If not lane 0, then we must match lane 0
3860 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3863 if (Idx >= (int)NumElts)
3864 Idx -= NumElts - NumLaneElts;
3866 if (!isUndefOrEqual(Idx, Start+i))
3875 /// \brief Return true if the node specifies a shuffle of elements that is
3876 /// suitable for input to PALIGNR.
3877 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
3878 const X86Subtarget *Subtarget) {
3879 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3880 (VT.is256BitVector() && !Subtarget->hasInt256()))
3881 // FIXME: Add AVX512BW.
3884 return isAlignrMask(Mask, VT, false);
3887 /// \brief Return true if the node specifies a shuffle of elements that is
3888 /// suitable for input to VALIGN.
3889 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
3890 const X86Subtarget *Subtarget) {
3891 // FIXME: Add AVX512VL.
3892 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
3894 return isAlignrMask(Mask, VT, true);
3897 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3898 /// the two vector operands have swapped position.
3899 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3900 unsigned NumElems) {
3901 for (unsigned i = 0; i != NumElems; ++i) {
3905 else if (idx < (int)NumElems)
3906 Mask[i] = idx + NumElems;
3908 Mask[i] = idx - NumElems;
3912 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3913 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3914 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3915 /// reverse of what x86 shuffles want.
3916 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
3918 unsigned NumElems = VT.getVectorNumElements();
3919 unsigned NumLanes = VT.getSizeInBits()/128;
3920 unsigned NumLaneElems = NumElems/NumLanes;
3922 if (NumLaneElems != 2 && NumLaneElems != 4)
3925 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3926 bool symetricMaskRequired =
3927 (VT.getSizeInBits() >= 256) && (EltSize == 32);
3929 // VSHUFPSY divides the resulting vector into 4 chunks.
3930 // The sources are also splitted into 4 chunks, and each destination
3931 // chunk must come from a different source chunk.
3933 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3934 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3936 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3937 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3939 // VSHUFPDY divides the resulting vector into 4 chunks.
3940 // The sources are also splitted into 4 chunks, and each destination
3941 // chunk must come from a different source chunk.
3943 // SRC1 => X3 X2 X1 X0
3944 // SRC2 => Y3 Y2 Y1 Y0
3946 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3948 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
3949 unsigned HalfLaneElems = NumLaneElems/2;
3950 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3951 for (unsigned i = 0; i != NumLaneElems; ++i) {
3952 int Idx = Mask[i+l];
3953 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3954 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3956 // For VSHUFPSY, the mask of the second half must be the same as the
3957 // first but with the appropriate offsets. This works in the same way as
3958 // VPERMILPS works with masks.
3959 if (!symetricMaskRequired || Idx < 0)
3961 if (MaskVal[i] < 0) {
3962 MaskVal[i] = Idx - l;
3965 if ((signed)(Idx - l) != MaskVal[i])
3973 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3974 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3975 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
3976 if (!VT.is128BitVector())
3979 unsigned NumElems = VT.getVectorNumElements();
3984 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3985 return isUndefOrEqual(Mask[0], 6) &&
3986 isUndefOrEqual(Mask[1], 7) &&
3987 isUndefOrEqual(Mask[2], 2) &&
3988 isUndefOrEqual(Mask[3], 3);
3991 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3992 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3994 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
3995 if (!VT.is128BitVector())
3998 unsigned NumElems = VT.getVectorNumElements();
4003 return isUndefOrEqual(Mask[0], 2) &&
4004 isUndefOrEqual(Mask[1], 3) &&
4005 isUndefOrEqual(Mask[2], 2) &&
4006 isUndefOrEqual(Mask[3], 3);
4009 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4010 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4011 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4012 if (!VT.is128BitVector())
4015 unsigned NumElems = VT.getVectorNumElements();
4017 if (NumElems != 2 && NumElems != 4)
4020 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4021 if (!isUndefOrEqual(Mask[i], i + NumElems))
4024 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4025 if (!isUndefOrEqual(Mask[i], i))
4031 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4032 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4033 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4034 if (!VT.is128BitVector())
4037 unsigned NumElems = VT.getVectorNumElements();
4039 if (NumElems != 2 && NumElems != 4)
4042 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4043 if (!isUndefOrEqual(Mask[i], i))
4046 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4047 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4053 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4054 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4055 /// i. e: If all but one element come from the same vector.
4056 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4057 // TODO: Deal with AVX's VINSERTPS
4058 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4061 unsigned CorrectPosV1 = 0;
4062 unsigned CorrectPosV2 = 0;
4063 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4064 if (Mask[i] == -1) {
4072 else if (Mask[i] == i + 4)
4076 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4077 // We have 3 elements (undefs count as elements from any vector) from one
4078 // vector, and one from another.
4085 // Some special combinations that can be optimized.
4088 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4089 SelectionDAG &DAG) {
4090 MVT VT = SVOp->getSimpleValueType(0);
4093 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4096 ArrayRef<int> Mask = SVOp->getMask();
4098 // These are the special masks that may be optimized.
4099 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4100 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4101 bool MatchEvenMask = true;
4102 bool MatchOddMask = true;
4103 for (int i=0; i<8; ++i) {
4104 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4105 MatchEvenMask = false;
4106 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4107 MatchOddMask = false;
4110 if (!MatchEvenMask && !MatchOddMask)
4113 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4115 SDValue Op0 = SVOp->getOperand(0);
4116 SDValue Op1 = SVOp->getOperand(1);
4118 if (MatchEvenMask) {
4119 // Shift the second operand right to 32 bits.
4120 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4121 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4123 // Shift the first operand left to 32 bits.
4124 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4125 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4127 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4128 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4131 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4132 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4133 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4134 bool HasInt256, bool V2IsSplat = false) {
4136 assert(VT.getSizeInBits() >= 128 &&
4137 "Unsupported vector type for unpckl");
4139 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4141 unsigned NumOf256BitLanes;
4142 unsigned NumElts = VT.getVectorNumElements();
4143 if (VT.is256BitVector()) {
4144 if (NumElts != 4 && NumElts != 8 &&
4145 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4148 NumOf256BitLanes = 1;
4149 } else if (VT.is512BitVector()) {
4150 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4151 "Unsupported vector type for unpckh");
4153 NumOf256BitLanes = 2;
4156 NumOf256BitLanes = 1;
4159 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4160 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4162 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4163 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4164 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4165 int BitI = Mask[l256*NumEltsInStride+l+i];
4166 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4167 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4169 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4171 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4179 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4180 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4181 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4182 bool HasInt256, bool V2IsSplat = false) {
4183 assert(VT.getSizeInBits() >= 128 &&
4184 "Unsupported vector type for unpckh");
4186 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4188 unsigned NumOf256BitLanes;
4189 unsigned NumElts = VT.getVectorNumElements();
4190 if (VT.is256BitVector()) {
4191 if (NumElts != 4 && NumElts != 8 &&
4192 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4195 NumOf256BitLanes = 1;
4196 } else if (VT.is512BitVector()) {
4197 assert(VT.getScalarType().getSizeInBits() >= 32 &&
4198 "Unsupported vector type for unpckh");
4200 NumOf256BitLanes = 2;
4203 NumOf256BitLanes = 1;
4206 unsigned NumEltsInStride = NumElts/NumOf256BitLanes;
4207 unsigned NumLaneElts = NumEltsInStride/NumLanes;
4209 for (unsigned l256 = 0; l256 < NumOf256BitLanes; l256 += 1) {
4210 for (unsigned l = 0; l != NumEltsInStride; l += NumLaneElts) {
4211 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4212 int BitI = Mask[l256*NumEltsInStride+l+i];
4213 int BitI1 = Mask[l256*NumEltsInStride+l+i+1];
4214 if (!isUndefOrEqual(BitI, j+l256*NumElts))
4216 if (V2IsSplat && !isUndefOrEqual(BitI1, NumElts))
4218 if (!isUndefOrEqual(BitI1, j+l256*NumElts+NumEltsInStride))
4226 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4227 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4229 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4230 unsigned NumElts = VT.getVectorNumElements();
4231 bool Is256BitVec = VT.is256BitVector();
4233 if (VT.is512BitVector())
4235 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4236 "Unsupported vector type for unpckh");
4238 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4239 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4242 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4243 // FIXME: Need a better way to get rid of this, there's no latency difference
4244 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4245 // the former later. We should also remove the "_undef" special mask.
4246 if (NumElts == 4 && Is256BitVec)
4249 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4250 // independently on 128-bit lanes.
4251 unsigned NumLanes = VT.getSizeInBits()/128;
4252 unsigned NumLaneElts = NumElts/NumLanes;
4254 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4255 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4256 int BitI = Mask[l+i];
4257 int BitI1 = Mask[l+i+1];
4259 if (!isUndefOrEqual(BitI, j))
4261 if (!isUndefOrEqual(BitI1, j))
4269 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4270 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4272 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4273 unsigned NumElts = VT.getVectorNumElements();
4275 if (VT.is512BitVector())
4278 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4279 "Unsupported vector type for unpckh");
4281 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4282 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4285 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4286 // independently on 128-bit lanes.
4287 unsigned NumLanes = VT.getSizeInBits()/128;
4288 unsigned NumLaneElts = NumElts/NumLanes;
4290 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4291 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4292 int BitI = Mask[l+i];
4293 int BitI1 = Mask[l+i+1];
4294 if (!isUndefOrEqual(BitI, j))
4296 if (!isUndefOrEqual(BitI1, j))
4303 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4304 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4305 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4306 if (!VT.is512BitVector())
4309 unsigned NumElts = VT.getVectorNumElements();
4310 unsigned HalfSize = NumElts/2;
4311 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4312 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4317 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4318 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4326 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4327 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4328 /// MOVSD, and MOVD, i.e. setting the lowest element.
4329 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4330 if (VT.getVectorElementType().getSizeInBits() < 32)
4332 if (!VT.is128BitVector())
4335 unsigned NumElts = VT.getVectorNumElements();
4337 if (!isUndefOrEqual(Mask[0], NumElts))
4340 for (unsigned i = 1; i != NumElts; ++i)
4341 if (!isUndefOrEqual(Mask[i], i))
4347 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4348 /// as permutations between 128-bit chunks or halves. As an example: this
4350 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4351 /// The first half comes from the second half of V1 and the second half from the
4352 /// the second half of V2.
4353 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4354 if (!HasFp256 || !VT.is256BitVector())
4357 // The shuffle result is divided into half A and half B. In total the two
4358 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4359 // B must come from C, D, E or F.
4360 unsigned HalfSize = VT.getVectorNumElements()/2;
4361 bool MatchA = false, MatchB = false;
4363 // Check if A comes from one of C, D, E, F.
4364 for (unsigned Half = 0; Half != 4; ++Half) {
4365 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4371 // Check if B comes from one of C, D, E, F.
4372 for (unsigned Half = 0; Half != 4; ++Half) {
4373 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4379 return MatchA && MatchB;
4382 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4383 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4384 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4385 MVT VT = SVOp->getSimpleValueType(0);
4387 unsigned HalfSize = VT.getVectorNumElements()/2;
4389 unsigned FstHalf = 0, SndHalf = 0;
4390 for (unsigned i = 0; i < HalfSize; ++i) {
4391 if (SVOp->getMaskElt(i) > 0) {
4392 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4396 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4397 if (SVOp->getMaskElt(i) > 0) {
4398 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4403 return (FstHalf | (SndHalf << 4));
4406 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4407 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4408 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4412 unsigned NumElts = VT.getVectorNumElements();
4414 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4415 for (unsigned i = 0; i != NumElts; ++i) {
4418 Imm8 |= Mask[i] << (i*2);
4423 unsigned LaneSize = 4;
4424 SmallVector<int, 4> MaskVal(LaneSize, -1);
4426 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4427 for (unsigned i = 0; i != LaneSize; ++i) {
4428 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4432 if (MaskVal[i] < 0) {
4433 MaskVal[i] = Mask[i+l] - l;
4434 Imm8 |= MaskVal[i] << (i*2);
4437 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4444 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4445 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4446 /// Note that VPERMIL mask matching is different depending whether theunderlying
4447 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4448 /// to the same elements of the low, but to the higher half of the source.
4449 /// In VPERMILPD the two lanes could be shuffled independently of each other
4450 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4451 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4452 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4453 if (VT.getSizeInBits() < 256 || EltSize < 32)
4455 bool symetricMaskRequired = (EltSize == 32);
4456 unsigned NumElts = VT.getVectorNumElements();
4458 unsigned NumLanes = VT.getSizeInBits()/128;
4459 unsigned LaneSize = NumElts/NumLanes;
4460 // 2 or 4 elements in one lane
4462 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4463 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4464 for (unsigned i = 0; i != LaneSize; ++i) {
4465 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4467 if (symetricMaskRequired) {
4468 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4469 ExpectedMaskVal[i] = Mask[i+l] - l;
4472 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4480 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4481 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4482 /// element of vector 2 and the other elements to come from vector 1 in order.
4483 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4484 bool V2IsSplat = false, bool V2IsUndef = false) {
4485 if (!VT.is128BitVector())
4488 unsigned NumOps = VT.getVectorNumElements();
4489 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4492 if (!isUndefOrEqual(Mask[0], 0))
4495 for (unsigned i = 1; i != NumOps; ++i)
4496 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4497 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4498 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4504 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4505 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4506 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4507 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4508 const X86Subtarget *Subtarget) {
4509 if (!Subtarget->hasSSE3())
4512 unsigned NumElems = VT.getVectorNumElements();
4514 if ((VT.is128BitVector() && NumElems != 4) ||
4515 (VT.is256BitVector() && NumElems != 8) ||
4516 (VT.is512BitVector() && NumElems != 16))
4519 // "i+1" is the value the indexed mask element must have
4520 for (unsigned i = 0; i != NumElems; i += 2)
4521 if (!isUndefOrEqual(Mask[i], i+1) ||
4522 !isUndefOrEqual(Mask[i+1], i+1))
4528 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4529 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4530 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4531 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4532 const X86Subtarget *Subtarget) {
4533 if (!Subtarget->hasSSE3())
4536 unsigned NumElems = VT.getVectorNumElements();
4538 if ((VT.is128BitVector() && NumElems != 4) ||
4539 (VT.is256BitVector() && NumElems != 8) ||
4540 (VT.is512BitVector() && NumElems != 16))
4543 // "i" is the value the indexed mask element must have
4544 for (unsigned i = 0; i != NumElems; i += 2)
4545 if (!isUndefOrEqual(Mask[i], i) ||
4546 !isUndefOrEqual(Mask[i+1], i))
4552 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4553 /// specifies a shuffle of elements that is suitable for input to 256-bit
4554 /// version of MOVDDUP.
4555 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4556 if (!HasFp256 || !VT.is256BitVector())
4559 unsigned NumElts = VT.getVectorNumElements();
4563 for (unsigned i = 0; i != NumElts/2; ++i)
4564 if (!isUndefOrEqual(Mask[i], 0))
4566 for (unsigned i = NumElts/2; i != NumElts; ++i)
4567 if (!isUndefOrEqual(Mask[i], NumElts/2))
4572 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4573 /// specifies a shuffle of elements that is suitable for input to 128-bit
4574 /// version of MOVDDUP.
4575 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4576 if (!VT.is128BitVector())
4579 unsigned e = VT.getVectorNumElements() / 2;
4580 for (unsigned i = 0; i != e; ++i)
4581 if (!isUndefOrEqual(Mask[i], i))
4583 for (unsigned i = 0; i != e; ++i)
4584 if (!isUndefOrEqual(Mask[e+i], i))
4589 /// isVEXTRACTIndex - Return true if the specified
4590 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4591 /// suitable for instruction that extract 128 or 256 bit vectors
4592 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4593 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4594 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4597 // The index should be aligned on a vecWidth-bit boundary.
4599 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4601 MVT VT = N->getSimpleValueType(0);
4602 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4603 bool Result = (Index * ElSize) % vecWidth == 0;
4608 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4609 /// operand specifies a subvector insert that is suitable for input to
4610 /// insertion of 128 or 256-bit subvectors
4611 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4612 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4613 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4615 // The index should be aligned on a vecWidth-bit boundary.
4617 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4619 MVT VT = N->getSimpleValueType(0);
4620 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4621 bool Result = (Index * ElSize) % vecWidth == 0;
4626 bool X86::isVINSERT128Index(SDNode *N) {
4627 return isVINSERTIndex(N, 128);
4630 bool X86::isVINSERT256Index(SDNode *N) {
4631 return isVINSERTIndex(N, 256);
4634 bool X86::isVEXTRACT128Index(SDNode *N) {
4635 return isVEXTRACTIndex(N, 128);
4638 bool X86::isVEXTRACT256Index(SDNode *N) {
4639 return isVEXTRACTIndex(N, 256);
4642 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4643 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4644 /// Handles 128-bit and 256-bit.
4645 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4646 MVT VT = N->getSimpleValueType(0);
4648 assert((VT.getSizeInBits() >= 128) &&
4649 "Unsupported vector type for PSHUF/SHUFP");
4651 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4652 // independently on 128-bit lanes.
4653 unsigned NumElts = VT.getVectorNumElements();
4654 unsigned NumLanes = VT.getSizeInBits()/128;
4655 unsigned NumLaneElts = NumElts/NumLanes;
4657 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4658 "Only supports 2, 4 or 8 elements per lane");
4660 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4662 for (unsigned i = 0; i != NumElts; ++i) {
4663 int Elt = N->getMaskElt(i);
4664 if (Elt < 0) continue;
4665 Elt &= NumLaneElts - 1;
4666 unsigned ShAmt = (i << Shift) % 8;
4667 Mask |= Elt << ShAmt;
4673 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4674 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4675 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4676 MVT VT = N->getSimpleValueType(0);
4678 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4679 "Unsupported vector type for PSHUFHW");
4681 unsigned NumElts = VT.getVectorNumElements();
4684 for (unsigned l = 0; l != NumElts; l += 8) {
4685 // 8 nodes per lane, but we only care about the last 4.
4686 for (unsigned i = 0; i < 4; ++i) {
4687 int Elt = N->getMaskElt(l+i+4);
4688 if (Elt < 0) continue;
4689 Elt &= 0x3; // only 2-bits.
4690 Mask |= Elt << (i * 2);
4697 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4698 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4699 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4700 MVT VT = N->getSimpleValueType(0);
4702 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4703 "Unsupported vector type for PSHUFHW");
4705 unsigned NumElts = VT.getVectorNumElements();
4708 for (unsigned l = 0; l != NumElts; l += 8) {
4709 // 8 nodes per lane, but we only care about the first 4.
4710 for (unsigned i = 0; i < 4; ++i) {
4711 int Elt = N->getMaskElt(l+i);
4712 if (Elt < 0) continue;
4713 Elt &= 0x3; // only 2-bits
4714 Mask |= Elt << (i * 2);
4721 /// \brief Return the appropriate immediate to shuffle the specified
4722 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4723 /// VALIGN (if Interlane is true) instructions.
4724 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4726 MVT VT = SVOp->getSimpleValueType(0);
4727 unsigned EltSize = InterLane ? 1 :
4728 VT.getVectorElementType().getSizeInBits() >> 3;
4730 unsigned NumElts = VT.getVectorNumElements();
4731 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4732 unsigned NumLaneElts = NumElts/NumLanes;
4736 for (i = 0; i != NumElts; ++i) {
4737 Val = SVOp->getMaskElt(i);
4741 if (Val >= (int)NumElts)
4742 Val -= NumElts - NumLaneElts;
4744 assert(Val - i > 0 && "PALIGNR imm should be positive");
4745 return (Val - i) * EltSize;
4748 /// \brief Return the appropriate immediate to shuffle the specified
4749 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4750 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4751 return getShuffleAlignrImmediate(SVOp, false);
4754 /// \brief Return the appropriate immediate to shuffle the specified
4755 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4756 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4757 return getShuffleAlignrImmediate(SVOp, true);
4761 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4762 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4763 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4764 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4767 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4769 MVT VecVT = N->getOperand(0).getSimpleValueType();
4770 MVT ElVT = VecVT.getVectorElementType();
4772 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4773 return Index / NumElemsPerChunk;
4776 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4777 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4778 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4779 llvm_unreachable("Illegal insert subvector for VINSERT");
4782 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4784 MVT VecVT = N->getSimpleValueType(0);
4785 MVT ElVT = VecVT.getVectorElementType();
4787 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4788 return Index / NumElemsPerChunk;
4791 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4792 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4793 /// and VINSERTI128 instructions.
4794 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4795 return getExtractVEXTRACTImmediate(N, 128);
4798 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4799 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4800 /// and VINSERTI64x4 instructions.
4801 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4802 return getExtractVEXTRACTImmediate(N, 256);
4805 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4806 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4807 /// and VINSERTI128 instructions.
4808 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4809 return getInsertVINSERTImmediate(N, 128);
4812 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4813 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4814 /// and VINSERTI64x4 instructions.
4815 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4816 return getInsertVINSERTImmediate(N, 256);
4819 /// isZero - Returns true if Elt is a constant integer zero
4820 static bool isZero(SDValue V) {
4821 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4822 return C && C->isNullValue();
4825 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4827 bool X86::isZeroNode(SDValue Elt) {
4830 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4831 return CFP->getValueAPF().isPosZero();
4835 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4836 /// match movhlps. The lower half elements should come from upper half of
4837 /// V1 (and in order), and the upper half elements should come from the upper
4838 /// half of V2 (and in order).
4839 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4840 if (!VT.is128BitVector())
4842 if (VT.getVectorNumElements() != 4)
4844 for (unsigned i = 0, e = 2; i != e; ++i)
4845 if (!isUndefOrEqual(Mask[i], i+2))
4847 for (unsigned i = 2; i != 4; ++i)
4848 if (!isUndefOrEqual(Mask[i], i+4))
4853 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4854 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4856 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4857 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4859 N = N->getOperand(0).getNode();
4860 if (!ISD::isNON_EXTLoad(N))
4863 *LD = cast<LoadSDNode>(N);
4867 // Test whether the given value is a vector value which will be legalized
4869 static bool WillBeConstantPoolLoad(SDNode *N) {
4870 if (N->getOpcode() != ISD::BUILD_VECTOR)
4873 // Check for any non-constant elements.
4874 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4875 switch (N->getOperand(i).getNode()->getOpcode()) {
4877 case ISD::ConstantFP:
4884 // Vectors of all-zeros and all-ones are materialized with special
4885 // instructions rather than being loaded.
4886 return !ISD::isBuildVectorAllZeros(N) &&
4887 !ISD::isBuildVectorAllOnes(N);
4890 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4891 /// match movlp{s|d}. The lower half elements should come from lower half of
4892 /// V1 (and in order), and the upper half elements should come from the upper
4893 /// half of V2 (and in order). And since V1 will become the source of the
4894 /// MOVLP, it must be either a vector load or a scalar load to vector.
4895 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4896 ArrayRef<int> Mask, MVT VT) {
4897 if (!VT.is128BitVector())
4900 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4902 // Is V2 is a vector load, don't do this transformation. We will try to use
4903 // load folding shufps op.
4904 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4907 unsigned NumElems = VT.getVectorNumElements();
4909 if (NumElems != 2 && NumElems != 4)
4911 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4912 if (!isUndefOrEqual(Mask[i], i))
4914 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4915 if (!isUndefOrEqual(Mask[i], i+NumElems))
4920 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4921 /// to an zero vector.
4922 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4923 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4924 SDValue V1 = N->getOperand(0);
4925 SDValue V2 = N->getOperand(1);
4926 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4927 for (unsigned i = 0; i != NumElems; ++i) {
4928 int Idx = N->getMaskElt(i);
4929 if (Idx >= (int)NumElems) {
4930 unsigned Opc = V2.getOpcode();
4931 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4933 if (Opc != ISD::BUILD_VECTOR ||
4934 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4936 } else if (Idx >= 0) {
4937 unsigned Opc = V1.getOpcode();
4938 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4940 if (Opc != ISD::BUILD_VECTOR ||
4941 !X86::isZeroNode(V1.getOperand(Idx)))
4948 /// getZeroVector - Returns a vector of specified type with all zero elements.
4950 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4951 SelectionDAG &DAG, SDLoc dl) {
4952 assert(VT.isVector() && "Expected a vector type");
4954 // Always build SSE zero vectors as <4 x i32> bitcasted
4955 // to their dest type. This ensures they get CSE'd.
4957 if (VT.is128BitVector()) { // SSE
4958 if (Subtarget->hasSSE2()) { // SSE2
4959 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4960 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4962 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4963 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4965 } else if (VT.is256BitVector()) { // AVX
4966 if (Subtarget->hasInt256()) { // AVX2
4967 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4968 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4969 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4971 // 256-bit logic and arithmetic instructions in AVX are all
4972 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4973 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4974 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4975 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4977 } else if (VT.is512BitVector()) { // AVX-512
4978 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4979 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4980 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4981 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4982 } else if (VT.getScalarType() == MVT::i1) {
4983 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
4984 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
4985 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
4986 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4988 llvm_unreachable("Unexpected vector type");
4990 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4993 /// getOnesVector - Returns a vector of specified type with all bits set.
4994 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4995 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4996 /// Then bitcast to their original type, ensuring they get CSE'd.
4997 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4999 assert(VT.isVector() && "Expected a vector type");
5001 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
5003 if (VT.is256BitVector()) {
5004 if (HasInt256) { // AVX2
5005 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5006 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5008 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5009 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5011 } else if (VT.is128BitVector()) {
5012 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5014 llvm_unreachable("Unexpected vector type");
5016 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5019 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5020 /// that point to V2 points to its first element.
5021 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5022 for (unsigned i = 0; i != NumElems; ++i) {
5023 if (Mask[i] > (int)NumElems) {
5029 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5030 /// operation of specified width.
5031 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5033 unsigned NumElems = VT.getVectorNumElements();
5034 SmallVector<int, 8> Mask;
5035 Mask.push_back(NumElems);
5036 for (unsigned i = 1; i != NumElems; ++i)
5038 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5041 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5042 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5044 unsigned NumElems = VT.getVectorNumElements();
5045 SmallVector<int, 8> Mask;
5046 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5048 Mask.push_back(i + NumElems);
5050 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5053 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5054 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5056 unsigned NumElems = VT.getVectorNumElements();
5057 SmallVector<int, 8> Mask;
5058 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5059 Mask.push_back(i + Half);
5060 Mask.push_back(i + NumElems + Half);
5062 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5065 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5066 // a generic shuffle instruction because the target has no such instructions.
5067 // Generate shuffles which repeat i16 and i8 several times until they can be
5068 // represented by v4f32 and then be manipulated by target suported shuffles.
5069 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5070 MVT VT = V.getSimpleValueType();
5071 int NumElems = VT.getVectorNumElements();
5074 while (NumElems > 4) {
5075 if (EltNo < NumElems/2) {
5076 V = getUnpackl(DAG, dl, VT, V, V);
5078 V = getUnpackh(DAG, dl, VT, V, V);
5079 EltNo -= NumElems/2;
5086 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5087 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5088 MVT VT = V.getSimpleValueType();
5091 if (VT.is128BitVector()) {
5092 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5093 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5094 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5096 } else if (VT.is256BitVector()) {
5097 // To use VPERMILPS to splat scalars, the second half of indicies must
5098 // refer to the higher part, which is a duplication of the lower one,
5099 // because VPERMILPS can only handle in-lane permutations.
5100 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5101 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5103 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5104 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5107 llvm_unreachable("Vector size not supported");
5109 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5112 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5113 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5114 MVT SrcVT = SV->getSimpleValueType(0);
5115 SDValue V1 = SV->getOperand(0);
5118 int EltNo = SV->getSplatIndex();
5119 int NumElems = SrcVT.getVectorNumElements();
5120 bool Is256BitVec = SrcVT.is256BitVector();
5122 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5123 "Unknown how to promote splat for type");
5125 // Extract the 128-bit part containing the splat element and update
5126 // the splat element index when it refers to the higher register.
5128 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5129 if (EltNo >= NumElems/2)
5130 EltNo -= NumElems/2;
5133 // All i16 and i8 vector types can't be used directly by a generic shuffle
5134 // instruction because the target has no such instruction. Generate shuffles
5135 // which repeat i16 and i8 several times until they fit in i32, and then can
5136 // be manipulated by target suported shuffles.
5137 MVT EltVT = SrcVT.getVectorElementType();
5138 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5139 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5141 // Recreate the 256-bit vector and place the same 128-bit vector
5142 // into the low and high part. This is necessary because we want
5143 // to use VPERM* to shuffle the vectors
5145 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5148 return getLegalSplat(DAG, V1, EltNo);
5151 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5152 /// vector of zero or undef vector. This produces a shuffle where the low
5153 /// element of V2 is swizzled into the zero/undef vector, landing at element
5154 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5155 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5157 const X86Subtarget *Subtarget,
5158 SelectionDAG &DAG) {
5159 MVT VT = V2.getSimpleValueType();
5161 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5162 unsigned NumElems = VT.getVectorNumElements();
5163 SmallVector<int, 16> MaskVec;
5164 for (unsigned i = 0; i != NumElems; ++i)
5165 // If this is the insertion idx, put the low elt of V2 here.
5166 MaskVec.push_back(i == Idx ? NumElems : i);
5167 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5170 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5171 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5172 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5173 /// shuffles which use a single input multiple times, and in those cases it will
5174 /// adjust the mask to only have indices within that single input.
5175 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5176 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5177 unsigned NumElems = VT.getVectorNumElements();
5181 bool IsFakeUnary = false;
5182 switch(N->getOpcode()) {
5184 ImmN = N->getOperand(N->getNumOperands()-1);
5185 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5186 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5188 case X86ISD::UNPCKH:
5189 DecodeUNPCKHMask(VT, Mask);
5190 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5192 case X86ISD::UNPCKL:
5193 DecodeUNPCKLMask(VT, Mask);
5194 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5196 case X86ISD::MOVHLPS:
5197 DecodeMOVHLPSMask(NumElems, Mask);
5198 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5200 case X86ISD::MOVLHPS:
5201 DecodeMOVLHPSMask(NumElems, Mask);
5202 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5204 case X86ISD::PALIGNR:
5205 ImmN = N->getOperand(N->getNumOperands()-1);
5206 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5208 case X86ISD::PSHUFD:
5209 case X86ISD::VPERMILP:
5210 ImmN = N->getOperand(N->getNumOperands()-1);
5211 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5214 case X86ISD::PSHUFHW:
5215 ImmN = N->getOperand(N->getNumOperands()-1);
5216 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5219 case X86ISD::PSHUFLW:
5220 ImmN = N->getOperand(N->getNumOperands()-1);
5221 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5224 case X86ISD::PSHUFB: {
5226 SDValue MaskNode = N->getOperand(1);
5227 while (MaskNode->getOpcode() == ISD::BITCAST)
5228 MaskNode = MaskNode->getOperand(0);
5230 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5231 // If we have a build-vector, then things are easy.
5232 EVT VT = MaskNode.getValueType();
5233 assert(VT.isVector() &&
5234 "Can't produce a non-vector with a build_vector!");
5235 if (!VT.isInteger())
5238 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5240 SmallVector<uint64_t, 32> RawMask;
5241 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5242 auto *CN = dyn_cast<ConstantSDNode>(MaskNode->getOperand(i));
5245 APInt MaskElement = CN->getAPIntValue();
5247 // We now have to decode the element which could be any integer size and
5248 // extract each byte of it.
5249 for (int j = 0; j < NumBytesPerElement; ++j) {
5250 // Note that this is x86 and so always little endian: the low byte is
5251 // the first byte of the mask.
5252 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5253 MaskElement = MaskElement.lshr(8);
5256 DecodePSHUFBMask(RawMask, Mask);
5260 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5264 SDValue Ptr = MaskLoad->getBasePtr();
5265 if (Ptr->getOpcode() == X86ISD::Wrapper)
5266 Ptr = Ptr->getOperand(0);
5268 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5269 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5272 if (auto *C = dyn_cast<ConstantDataSequential>(MaskCP->getConstVal())) {
5273 // FIXME: Support AVX-512 here.
5274 if (!C->getType()->isVectorTy() ||
5275 (C->getNumElements() != 16 && C->getNumElements() != 32))
5278 assert(C->getType()->isVectorTy() && "Expected a vector constant.");
5279 DecodePSHUFBMask(C, Mask);
5285 case X86ISD::VPERMI:
5286 ImmN = N->getOperand(N->getNumOperands()-1);
5287 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5291 case X86ISD::MOVSD: {
5292 // The index 0 always comes from the first element of the second source,
5293 // this is why MOVSS and MOVSD are used in the first place. The other
5294 // elements come from the other positions of the first source vector
5295 Mask.push_back(NumElems);
5296 for (unsigned i = 1; i != NumElems; ++i) {
5301 case X86ISD::VPERM2X128:
5302 ImmN = N->getOperand(N->getNumOperands()-1);
5303 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5304 if (Mask.empty()) return false;
5306 case X86ISD::MOVDDUP:
5307 case X86ISD::MOVLHPD:
5308 case X86ISD::MOVLPD:
5309 case X86ISD::MOVLPS:
5310 case X86ISD::MOVSHDUP:
5311 case X86ISD::MOVSLDUP:
5312 // Not yet implemented
5314 default: llvm_unreachable("unknown target shuffle node");
5317 // If we have a fake unary shuffle, the shuffle mask is spread across two
5318 // inputs that are actually the same node. Re-map the mask to always point
5319 // into the first input.
5322 if (M >= (int)Mask.size())
5328 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5329 /// element of the result of the vector shuffle.
5330 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5333 return SDValue(); // Limit search depth.
5335 SDValue V = SDValue(N, 0);
5336 EVT VT = V.getValueType();
5337 unsigned Opcode = V.getOpcode();
5339 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5340 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5341 int Elt = SV->getMaskElt(Index);
5344 return DAG.getUNDEF(VT.getVectorElementType());
5346 unsigned NumElems = VT.getVectorNumElements();
5347 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5348 : SV->getOperand(1);
5349 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5352 // Recurse into target specific vector shuffles to find scalars.
5353 if (isTargetShuffle(Opcode)) {
5354 MVT ShufVT = V.getSimpleValueType();
5355 unsigned NumElems = ShufVT.getVectorNumElements();
5356 SmallVector<int, 16> ShuffleMask;
5359 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5362 int Elt = ShuffleMask[Index];
5364 return DAG.getUNDEF(ShufVT.getVectorElementType());
5366 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5368 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5372 // Actual nodes that may contain scalar elements
5373 if (Opcode == ISD::BITCAST) {
5374 V = V.getOperand(0);
5375 EVT SrcVT = V.getValueType();
5376 unsigned NumElems = VT.getVectorNumElements();
5378 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5382 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5383 return (Index == 0) ? V.getOperand(0)
5384 : DAG.getUNDEF(VT.getVectorElementType());
5386 if (V.getOpcode() == ISD::BUILD_VECTOR)
5387 return V.getOperand(Index);
5392 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5393 /// shuffle operation which come from a consecutively from a zero. The
5394 /// search can start in two different directions, from left or right.
5395 /// We count undefs as zeros until PreferredNum is reached.
5396 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5397 unsigned NumElems, bool ZerosFromLeft,
5399 unsigned PreferredNum = -1U) {
5400 unsigned NumZeros = 0;
5401 for (unsigned i = 0; i != NumElems; ++i) {
5402 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5403 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5407 if (X86::isZeroNode(Elt))
5409 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5410 NumZeros = std::min(NumZeros + 1, PreferredNum);
5418 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5419 /// correspond consecutively to elements from one of the vector operands,
5420 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5422 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5423 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5424 unsigned NumElems, unsigned &OpNum) {
5425 bool SeenV1 = false;
5426 bool SeenV2 = false;
5428 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5429 int Idx = SVOp->getMaskElt(i);
5430 // Ignore undef indicies
5434 if (Idx < (int)NumElems)
5439 // Only accept consecutive elements from the same vector
5440 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5444 OpNum = SeenV1 ? 0 : 1;
5448 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5449 /// logical left shift of a vector.
5450 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5451 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5453 SVOp->getSimpleValueType(0).getVectorNumElements();
5454 unsigned NumZeros = getNumOfConsecutiveZeros(
5455 SVOp, NumElems, false /* check zeros from right */, DAG,
5456 SVOp->getMaskElt(0));
5462 // Considering the elements in the mask that are not consecutive zeros,
5463 // check if they consecutively come from only one of the source vectors.
5465 // V1 = {X, A, B, C} 0
5467 // vector_shuffle V1, V2 <1, 2, 3, X>
5469 if (!isShuffleMaskConsecutive(SVOp,
5470 0, // Mask Start Index
5471 NumElems-NumZeros, // Mask End Index(exclusive)
5472 NumZeros, // Where to start looking in the src vector
5473 NumElems, // Number of elements in vector
5474 OpSrc)) // Which source operand ?
5479 ShVal = SVOp->getOperand(OpSrc);
5483 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5484 /// logical left shift of a vector.
5485 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5486 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5488 SVOp->getSimpleValueType(0).getVectorNumElements();
5489 unsigned NumZeros = getNumOfConsecutiveZeros(
5490 SVOp, NumElems, true /* check zeros from left */, DAG,
5491 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5497 // Considering the elements in the mask that are not consecutive zeros,
5498 // check if they consecutively come from only one of the source vectors.
5500 // 0 { A, B, X, X } = V2
5502 // vector_shuffle V1, V2 <X, X, 4, 5>
5504 if (!isShuffleMaskConsecutive(SVOp,
5505 NumZeros, // Mask Start Index
5506 NumElems, // Mask End Index(exclusive)
5507 0, // Where to start looking in the src vector
5508 NumElems, // Number of elements in vector
5509 OpSrc)) // Which source operand ?
5514 ShVal = SVOp->getOperand(OpSrc);
5518 /// isVectorShift - Returns true if the shuffle can be implemented as a
5519 /// logical left or right shift of a vector.
5520 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5521 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5522 // Although the logic below support any bitwidth size, there are no
5523 // shift instructions which handle more than 128-bit vectors.
5524 if (!SVOp->getSimpleValueType(0).is128BitVector())
5527 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5528 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5534 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5536 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5537 unsigned NumNonZero, unsigned NumZero,
5539 const X86Subtarget* Subtarget,
5540 const TargetLowering &TLI) {
5547 for (unsigned i = 0; i < 16; ++i) {
5548 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5549 if (ThisIsNonZero && First) {
5551 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5553 V = DAG.getUNDEF(MVT::v8i16);
5558 SDValue ThisElt, LastElt;
5559 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5560 if (LastIsNonZero) {
5561 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5562 MVT::i16, Op.getOperand(i-1));
5564 if (ThisIsNonZero) {
5565 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5566 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5567 ThisElt, DAG.getConstant(8, MVT::i8));
5569 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5573 if (ThisElt.getNode())
5574 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5575 DAG.getIntPtrConstant(i/2));
5579 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5582 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5584 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5585 unsigned NumNonZero, unsigned NumZero,
5587 const X86Subtarget* Subtarget,
5588 const TargetLowering &TLI) {
5595 for (unsigned i = 0; i < 8; ++i) {
5596 bool isNonZero = (NonZeros & (1 << i)) != 0;
5600 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5602 V = DAG.getUNDEF(MVT::v8i16);
5605 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5606 MVT::v8i16, V, Op.getOperand(i),
5607 DAG.getIntPtrConstant(i));
5614 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5615 static SDValue LowerBuildVectorv4x32(SDValue Op, unsigned NumElems,
5616 unsigned NonZeros, unsigned NumNonZero,
5617 unsigned NumZero, SelectionDAG &DAG,
5618 const X86Subtarget *Subtarget,
5619 const TargetLowering &TLI) {
5620 // We know there's at least one non-zero element
5621 unsigned FirstNonZeroIdx = 0;
5622 SDValue FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5623 while (FirstNonZero.getOpcode() == ISD::UNDEF ||
5624 X86::isZeroNode(FirstNonZero)) {
5626 FirstNonZero = Op->getOperand(FirstNonZeroIdx);
5629 if (FirstNonZero.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5630 !isa<ConstantSDNode>(FirstNonZero.getOperand(1)))
5633 SDValue V = FirstNonZero.getOperand(0);
5634 MVT VVT = V.getSimpleValueType();
5635 if (!Subtarget->hasSSE41() || (VVT != MVT::v4f32 && VVT != MVT::v4i32))
5638 unsigned FirstNonZeroDst =
5639 cast<ConstantSDNode>(FirstNonZero.getOperand(1))->getZExtValue();
5640 unsigned CorrectIdx = FirstNonZeroDst == FirstNonZeroIdx;
5641 unsigned IncorrectIdx = CorrectIdx ? -1U : FirstNonZeroIdx;
5642 unsigned IncorrectDst = CorrectIdx ? -1U : FirstNonZeroDst;
5644 for (unsigned Idx = FirstNonZeroIdx + 1; Idx < NumElems; ++Idx) {
5645 SDValue Elem = Op.getOperand(Idx);
5646 if (Elem.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elem))
5649 // TODO: What else can be here? Deal with it.
5650 if (Elem.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5653 // TODO: Some optimizations are still possible here
5654 // ex: Getting one element from a vector, and the rest from another.
5655 if (Elem.getOperand(0) != V)
5658 unsigned Dst = cast<ConstantSDNode>(Elem.getOperand(1))->getZExtValue();
5661 else if (IncorrectIdx == -1U) {
5665 // There was already one element with an incorrect index.
5666 // We can't optimize this case to an insertps.
5670 if (NumNonZero == CorrectIdx || NumNonZero == CorrectIdx + 1) {
5672 EVT VT = Op.getSimpleValueType();
5673 unsigned ElementMoveMask = 0;
5674 if (IncorrectIdx == -1U)
5675 ElementMoveMask = FirstNonZeroIdx << 6 | FirstNonZeroIdx << 4;
5677 ElementMoveMask = IncorrectDst << 6 | IncorrectIdx << 4;
5679 SDValue InsertpsMask =
5680 DAG.getIntPtrConstant(ElementMoveMask | (~NonZeros & 0xf));
5681 return DAG.getNode(X86ISD::INSERTPS, dl, VT, V, V, InsertpsMask);
5687 /// getVShift - Return a vector logical shift node.
5689 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5690 unsigned NumBits, SelectionDAG &DAG,
5691 const TargetLowering &TLI, SDLoc dl) {
5692 assert(VT.is128BitVector() && "Unknown type for VShift");
5693 EVT ShVT = MVT::v2i64;
5694 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5695 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5696 return DAG.getNode(ISD::BITCAST, dl, VT,
5697 DAG.getNode(Opc, dl, ShVT, SrcOp,
5698 DAG.getConstant(NumBits,
5699 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5703 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5705 // Check if the scalar load can be widened into a vector load. And if
5706 // the address is "base + cst" see if the cst can be "absorbed" into
5707 // the shuffle mask.
5708 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5709 SDValue Ptr = LD->getBasePtr();
5710 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5712 EVT PVT = LD->getValueType(0);
5713 if (PVT != MVT::i32 && PVT != MVT::f32)
5718 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5719 FI = FINode->getIndex();
5721 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5722 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5723 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5724 Offset = Ptr.getConstantOperandVal(1);
5725 Ptr = Ptr.getOperand(0);
5730 // FIXME: 256-bit vector instructions don't require a strict alignment,
5731 // improve this code to support it better.
5732 unsigned RequiredAlign = VT.getSizeInBits()/8;
5733 SDValue Chain = LD->getChain();
5734 // Make sure the stack object alignment is at least 16 or 32.
5735 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5736 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5737 if (MFI->isFixedObjectIndex(FI)) {
5738 // Can't change the alignment. FIXME: It's possible to compute
5739 // the exact stack offset and reference FI + adjust offset instead.
5740 // If someone *really* cares about this. That's the way to implement it.
5743 MFI->setObjectAlignment(FI, RequiredAlign);
5747 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5748 // Ptr + (Offset & ~15).
5751 if ((Offset % RequiredAlign) & 3)
5753 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5755 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5756 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5758 int EltNo = (Offset - StartOffset) >> 2;
5759 unsigned NumElems = VT.getVectorNumElements();
5761 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5762 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5763 LD->getPointerInfo().getWithOffset(StartOffset),
5764 false, false, false, 0);
5766 SmallVector<int, 8> Mask;
5767 for (unsigned i = 0; i != NumElems; ++i)
5768 Mask.push_back(EltNo);
5770 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5776 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5777 /// vector of type 'VT', see if the elements can be replaced by a single large
5778 /// load which has the same value as a build_vector whose operands are 'elts'.
5780 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5782 /// FIXME: we'd also like to handle the case where the last elements are zero
5783 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5784 /// There's even a handy isZeroNode for that purpose.
5785 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5786 SDLoc &DL, SelectionDAG &DAG,
5787 bool isAfterLegalize) {
5788 EVT EltVT = VT.getVectorElementType();
5789 unsigned NumElems = Elts.size();
5791 LoadSDNode *LDBase = nullptr;
5792 unsigned LastLoadedElt = -1U;
5794 // For each element in the initializer, see if we've found a load or an undef.
5795 // If we don't find an initial load element, or later load elements are
5796 // non-consecutive, bail out.
5797 for (unsigned i = 0; i < NumElems; ++i) {
5798 SDValue Elt = Elts[i];
5800 if (!Elt.getNode() ||
5801 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5804 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5806 LDBase = cast<LoadSDNode>(Elt.getNode());
5810 if (Elt.getOpcode() == ISD::UNDEF)
5813 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5814 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5819 // If we have found an entire vector of loads and undefs, then return a large
5820 // load of the entire vector width starting at the base pointer. If we found
5821 // consecutive loads for the low half, generate a vzext_load node.
5822 if (LastLoadedElt == NumElems - 1) {
5824 if (isAfterLegalize &&
5825 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5828 SDValue NewLd = SDValue();
5830 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5831 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5832 LDBase->getPointerInfo(),
5833 LDBase->isVolatile(), LDBase->isNonTemporal(),
5834 LDBase->isInvariant(), 0);
5835 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5836 LDBase->getPointerInfo(),
5837 LDBase->isVolatile(), LDBase->isNonTemporal(),
5838 LDBase->isInvariant(), LDBase->getAlignment());
5840 if (LDBase->hasAnyUseOfValue(1)) {
5841 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5843 SDValue(NewLd.getNode(), 1));
5844 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5845 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5846 SDValue(NewLd.getNode(), 1));
5851 if (NumElems == 4 && LastLoadedElt == 1 &&
5852 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5853 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5854 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5856 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5857 LDBase->getPointerInfo(),
5858 LDBase->getAlignment(),
5859 false/*isVolatile*/, true/*ReadMem*/,
5862 // Make sure the newly-created LOAD is in the same position as LDBase in
5863 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5864 // update uses of LDBase's output chain to use the TokenFactor.
5865 if (LDBase->hasAnyUseOfValue(1)) {
5866 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5867 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5868 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5869 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5870 SDValue(ResNode.getNode(), 1));
5873 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5878 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5879 /// to generate a splat value for the following cases:
5880 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5881 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5882 /// a scalar load, or a constant.
5883 /// The VBROADCAST node is returned when a pattern is found,
5884 /// or SDValue() otherwise.
5885 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5886 SelectionDAG &DAG) {
5887 if (!Subtarget->hasFp256())
5890 MVT VT = Op.getSimpleValueType();
5893 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5894 "Unsupported vector type for broadcast.");
5899 switch (Op.getOpcode()) {
5901 // Unknown pattern found.
5904 case ISD::BUILD_VECTOR: {
5905 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5906 BitVector UndefElements;
5907 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5909 // We need a splat of a single value to use broadcast, and it doesn't
5910 // make any sense if the value is only in one element of the vector.
5911 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5915 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5916 Ld.getOpcode() == ISD::ConstantFP);
5918 // Make sure that all of the users of a non-constant load are from the
5919 // BUILD_VECTOR node.
5920 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5925 case ISD::VECTOR_SHUFFLE: {
5926 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5928 // Shuffles must have a splat mask where the first element is
5930 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5933 SDValue Sc = Op.getOperand(0);
5934 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5935 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5937 if (!Subtarget->hasInt256())
5940 // Use the register form of the broadcast instruction available on AVX2.
5941 if (VT.getSizeInBits() >= 256)
5942 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5943 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5946 Ld = Sc.getOperand(0);
5947 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5948 Ld.getOpcode() == ISD::ConstantFP);
5950 // The scalar_to_vector node and the suspected
5951 // load node must have exactly one user.
5952 // Constants may have multiple users.
5954 // AVX-512 has register version of the broadcast
5955 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5956 Ld.getValueType().getSizeInBits() >= 32;
5957 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5964 bool IsGE256 = (VT.getSizeInBits() >= 256);
5966 // Handle the broadcasting a single constant scalar from the constant pool
5967 // into a vector. On Sandybridge it is still better to load a constant vector
5968 // from the constant pool and not to broadcast it from a scalar.
5969 if (ConstSplatVal && Subtarget->hasInt256()) {
5970 EVT CVT = Ld.getValueType();
5971 assert(!CVT.isVector() && "Must not broadcast a vector type");
5972 unsigned ScalarSize = CVT.getSizeInBits();
5974 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)) {
5975 const Constant *C = nullptr;
5976 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5977 C = CI->getConstantIntValue();
5978 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5979 C = CF->getConstantFPValue();
5981 assert(C && "Invalid constant type");
5983 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5984 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5985 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5986 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5987 MachinePointerInfo::getConstantPool(),
5988 false, false, false, Alignment);
5990 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5994 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5995 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5997 // Handle AVX2 in-register broadcasts.
5998 if (!IsLoad && Subtarget->hasInt256() &&
5999 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6000 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6002 // The scalar source must be a normal load.
6006 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6007 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6009 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6010 // double since there is no vbroadcastsd xmm
6011 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6012 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6013 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6016 // Unsupported broadcast.
6020 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6021 /// underlying vector and index.
6023 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6025 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6027 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6028 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6031 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6033 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6035 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6036 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6039 // In this case the vector is the extract_subvector expression and the index
6040 // is 2, as specified by the shuffle.
6041 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6042 SDValue ShuffleVec = SVOp->getOperand(0);
6043 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6044 assert(ShuffleVecVT.getVectorElementType() ==
6045 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6047 int ShuffleIdx = SVOp->getMaskElt(Idx);
6048 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6049 ExtractedFromVec = ShuffleVec;
6055 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6056 MVT VT = Op.getSimpleValueType();
6058 // Skip if insert_vec_elt is not supported.
6059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6060 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6064 unsigned NumElems = Op.getNumOperands();
6068 SmallVector<unsigned, 4> InsertIndices;
6069 SmallVector<int, 8> Mask(NumElems, -1);
6071 for (unsigned i = 0; i != NumElems; ++i) {
6072 unsigned Opc = Op.getOperand(i).getOpcode();
6074 if (Opc == ISD::UNDEF)
6077 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6078 // Quit if more than 1 elements need inserting.
6079 if (InsertIndices.size() > 1)
6082 InsertIndices.push_back(i);
6086 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6087 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6088 // Quit if non-constant index.
6089 if (!isa<ConstantSDNode>(ExtIdx))
6091 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6093 // Quit if extracted from vector of different type.
6094 if (ExtractedFromVec.getValueType() != VT)
6097 if (!VecIn1.getNode())
6098 VecIn1 = ExtractedFromVec;
6099 else if (VecIn1 != ExtractedFromVec) {
6100 if (!VecIn2.getNode())
6101 VecIn2 = ExtractedFromVec;
6102 else if (VecIn2 != ExtractedFromVec)
6103 // Quit if more than 2 vectors to shuffle
6107 if (ExtractedFromVec == VecIn1)
6109 else if (ExtractedFromVec == VecIn2)
6110 Mask[i] = Idx + NumElems;
6113 if (!VecIn1.getNode())
6116 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6117 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6118 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6119 unsigned Idx = InsertIndices[i];
6120 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6121 DAG.getIntPtrConstant(Idx));
6127 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6129 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6131 MVT VT = Op.getSimpleValueType();
6132 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6133 "Unexpected type in LowerBUILD_VECTORvXi1!");
6136 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6137 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6138 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6139 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6142 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6143 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6144 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6145 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6148 bool AllContants = true;
6149 uint64_t Immediate = 0;
6150 int NonConstIdx = -1;
6151 bool IsSplat = true;
6152 unsigned NumNonConsts = 0;
6153 unsigned NumConsts = 0;
6154 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6155 SDValue In = Op.getOperand(idx);
6156 if (In.getOpcode() == ISD::UNDEF)
6158 if (!isa<ConstantSDNode>(In)) {
6159 AllContants = false;
6165 if (cast<ConstantSDNode>(In)->getZExtValue())
6166 Immediate |= (1ULL << idx);
6168 if (In != Op.getOperand(0))
6173 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6174 DAG.getConstant(Immediate, MVT::i16));
6175 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6176 DAG.getIntPtrConstant(0));
6179 if (NumNonConsts == 1 && NonConstIdx != 0) {
6182 SDValue VecAsImm = DAG.getConstant(Immediate,
6183 MVT::getIntegerVT(VT.getSizeInBits()));
6184 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6187 DstVec = DAG.getUNDEF(VT);
6188 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6189 Op.getOperand(NonConstIdx),
6190 DAG.getIntPtrConstant(NonConstIdx));
6192 if (!IsSplat && (NonConstIdx != 0))
6193 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6194 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6197 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6198 DAG.getConstant(-1, SelectVT),
6199 DAG.getConstant(0, SelectVT));
6201 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6202 DAG.getConstant((Immediate | 1), SelectVT),
6203 DAG.getConstant(Immediate, SelectVT));
6204 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6207 /// \brief Return true if \p N implements a horizontal binop and return the
6208 /// operands for the horizontal binop into V0 and V1.
6210 /// This is a helper function of PerformBUILD_VECTORCombine.
6211 /// This function checks that the build_vector \p N in input implements a
6212 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6213 /// operation to match.
6214 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6215 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6216 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6219 /// This function only analyzes elements of \p N whose indices are
6220 /// in range [BaseIdx, LastIdx).
6221 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6223 unsigned BaseIdx, unsigned LastIdx,
6224 SDValue &V0, SDValue &V1) {
6225 EVT VT = N->getValueType(0);
6227 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6228 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6229 "Invalid Vector in input!");
6231 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6232 bool CanFold = true;
6233 unsigned ExpectedVExtractIdx = BaseIdx;
6234 unsigned NumElts = LastIdx - BaseIdx;
6235 V0 = DAG.getUNDEF(VT);
6236 V1 = DAG.getUNDEF(VT);
6238 // Check if N implements a horizontal binop.
6239 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6240 SDValue Op = N->getOperand(i + BaseIdx);
6243 if (Op->getOpcode() == ISD::UNDEF) {
6244 // Update the expected vector extract index.
6245 if (i * 2 == NumElts)
6246 ExpectedVExtractIdx = BaseIdx;
6247 ExpectedVExtractIdx += 2;
6251 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6256 SDValue Op0 = Op.getOperand(0);
6257 SDValue Op1 = Op.getOperand(1);
6259 // Try to match the following pattern:
6260 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6261 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6262 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6263 Op0.getOperand(0) == Op1.getOperand(0) &&
6264 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6265 isa<ConstantSDNode>(Op1.getOperand(1)));
6269 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6270 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6272 if (i * 2 < NumElts) {
6273 if (V0.getOpcode() == ISD::UNDEF)
6274 V0 = Op0.getOperand(0);
6276 if (V1.getOpcode() == ISD::UNDEF)
6277 V1 = Op0.getOperand(0);
6278 if (i * 2 == NumElts)
6279 ExpectedVExtractIdx = BaseIdx;
6282 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6283 if (I0 == ExpectedVExtractIdx)
6284 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6285 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6286 // Try to match the following dag sequence:
6287 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6288 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6292 ExpectedVExtractIdx += 2;
6298 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6299 /// a concat_vector.
6301 /// This is a helper function of PerformBUILD_VECTORCombine.
6302 /// This function expects two 256-bit vectors called V0 and V1.
6303 /// At first, each vector is split into two separate 128-bit vectors.
6304 /// Then, the resulting 128-bit vectors are used to implement two
6305 /// horizontal binary operations.
6307 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6309 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6310 /// the two new horizontal binop.
6311 /// When Mode is set, the first horizontal binop dag node would take as input
6312 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6313 /// horizontal binop dag node would take as input the lower 128-bit of V1
6314 /// and the upper 128-bit of V1.
6316 /// HADD V0_LO, V0_HI
6317 /// HADD V1_LO, V1_HI
6319 /// Otherwise, the first horizontal binop dag node takes as input the lower
6320 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6321 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6323 /// HADD V0_LO, V1_LO
6324 /// HADD V0_HI, V1_HI
6326 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6327 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6328 /// the upper 128-bits of the result.
6329 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6330 SDLoc DL, SelectionDAG &DAG,
6331 unsigned X86Opcode, bool Mode,
6332 bool isUndefLO, bool isUndefHI) {
6333 EVT VT = V0.getValueType();
6334 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6335 "Invalid nodes in input!");
6337 unsigned NumElts = VT.getVectorNumElements();
6338 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6339 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6340 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6341 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6342 EVT NewVT = V0_LO.getValueType();
6344 SDValue LO = DAG.getUNDEF(NewVT);
6345 SDValue HI = DAG.getUNDEF(NewVT);
6348 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6349 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6350 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6351 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6352 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6354 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6355 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6356 V1_LO->getOpcode() != ISD::UNDEF))
6357 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6359 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6360 V1_HI->getOpcode() != ISD::UNDEF))
6361 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6364 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6367 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6368 /// sequence of 'vadd + vsub + blendi'.
6369 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6370 const X86Subtarget *Subtarget) {
6372 EVT VT = BV->getValueType(0);
6373 unsigned NumElts = VT.getVectorNumElements();
6374 SDValue InVec0 = DAG.getUNDEF(VT);
6375 SDValue InVec1 = DAG.getUNDEF(VT);
6377 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6378 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6380 // Don't try to emit a VSELECT that cannot be lowered into a blend.
6381 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6382 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
6385 // Odd-numbered elements in the input build vector are obtained from
6386 // adding two integer/float elements.
6387 // Even-numbered elements in the input build vector are obtained from
6388 // subtracting two integer/float elements.
6389 unsigned ExpectedOpcode = ISD::FSUB;
6390 unsigned NextExpectedOpcode = ISD::FADD;
6391 bool AddFound = false;
6392 bool SubFound = false;
6394 for (unsigned i = 0, e = NumElts; i != e; i++) {
6395 SDValue Op = BV->getOperand(i);
6397 // Skip 'undef' values.
6398 unsigned Opcode = Op.getOpcode();
6399 if (Opcode == ISD::UNDEF) {
6400 std::swap(ExpectedOpcode, NextExpectedOpcode);
6404 // Early exit if we found an unexpected opcode.
6405 if (Opcode != ExpectedOpcode)
6408 SDValue Op0 = Op.getOperand(0);
6409 SDValue Op1 = Op.getOperand(1);
6411 // Try to match the following pattern:
6412 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6413 // Early exit if we cannot match that sequence.
6414 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6415 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6416 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6417 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6418 Op0.getOperand(1) != Op1.getOperand(1))
6421 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6425 // We found a valid add/sub node. Update the information accordingly.
6431 // Update InVec0 and InVec1.
6432 if (InVec0.getOpcode() == ISD::UNDEF)
6433 InVec0 = Op0.getOperand(0);
6434 if (InVec1.getOpcode() == ISD::UNDEF)
6435 InVec1 = Op1.getOperand(0);
6437 // Make sure that operands in input to each add/sub node always
6438 // come from a same pair of vectors.
6439 if (InVec0 != Op0.getOperand(0)) {
6440 if (ExpectedOpcode == ISD::FSUB)
6443 // FADD is commutable. Try to commute the operands
6444 // and then test again.
6445 std::swap(Op0, Op1);
6446 if (InVec0 != Op0.getOperand(0))
6450 if (InVec1 != Op1.getOperand(0))
6453 // Update the pair of expected opcodes.
6454 std::swap(ExpectedOpcode, NextExpectedOpcode);
6457 // Don't try to fold this build_vector into a VSELECT if it has
6458 // too many UNDEF operands.
6459 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6460 InVec1.getOpcode() != ISD::UNDEF) {
6461 // Emit a sequence of vector add and sub followed by a VSELECT.
6462 // The new VSELECT will be lowered into a BLENDI.
6463 // At ISel stage, we pattern-match the sequence 'add + sub + BLENDI'
6464 // and emit a single ADDSUB instruction.
6465 SDValue Sub = DAG.getNode(ExpectedOpcode, DL, VT, InVec0, InVec1);
6466 SDValue Add = DAG.getNode(NextExpectedOpcode, DL, VT, InVec0, InVec1);
6468 // Construct the VSELECT mask.
6469 EVT MaskVT = VT.changeVectorElementTypeToInteger();
6470 EVT SVT = MaskVT.getVectorElementType();
6471 unsigned SVTBits = SVT.getSizeInBits();
6472 SmallVector<SDValue, 8> Ops;
6474 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6475 APInt Value = i & 1 ? APInt::getNullValue(SVTBits) :
6476 APInt::getAllOnesValue(SVTBits);
6477 SDValue Constant = DAG.getConstant(Value, SVT);
6478 Ops.push_back(Constant);
6481 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVT, Ops);
6482 return DAG.getSelect(DL, VT, Mask, Sub, Add);
6488 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6489 const X86Subtarget *Subtarget) {
6491 EVT VT = N->getValueType(0);
6492 unsigned NumElts = VT.getVectorNumElements();
6493 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6494 SDValue InVec0, InVec1;
6496 // Try to match an ADDSUB.
6497 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6498 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6499 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6500 if (Value.getNode())
6504 // Try to match horizontal ADD/SUB.
6505 unsigned NumUndefsLO = 0;
6506 unsigned NumUndefsHI = 0;
6507 unsigned Half = NumElts/2;
6509 // Count the number of UNDEF operands in the build_vector in input.
6510 for (unsigned i = 0, e = Half; i != e; ++i)
6511 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6514 for (unsigned i = Half, e = NumElts; i != e; ++i)
6515 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6518 // Early exit if this is either a build_vector of all UNDEFs or all the
6519 // operands but one are UNDEF.
6520 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6523 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6524 // Try to match an SSE3 float HADD/HSUB.
6525 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6526 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6528 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6529 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6530 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6531 // Try to match an SSSE3 integer HADD/HSUB.
6532 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6533 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6535 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6536 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6539 if (!Subtarget->hasAVX())
6542 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6543 // Try to match an AVX horizontal add/sub of packed single/double
6544 // precision floating point values from 256-bit vectors.
6545 SDValue InVec2, InVec3;
6546 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6547 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6548 ((InVec0.getOpcode() == ISD::UNDEF ||
6549 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6550 ((InVec1.getOpcode() == ISD::UNDEF ||
6551 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6552 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6554 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6555 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6556 ((InVec0.getOpcode() == ISD::UNDEF ||
6557 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6558 ((InVec1.getOpcode() == ISD::UNDEF ||
6559 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6560 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6561 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6562 // Try to match an AVX2 horizontal add/sub of signed integers.
6563 SDValue InVec2, InVec3;
6565 bool CanFold = true;
6567 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6568 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6569 ((InVec0.getOpcode() == ISD::UNDEF ||
6570 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6571 ((InVec1.getOpcode() == ISD::UNDEF ||
6572 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6573 X86Opcode = X86ISD::HADD;
6574 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6575 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6576 ((InVec0.getOpcode() == ISD::UNDEF ||
6577 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6578 ((InVec1.getOpcode() == ISD::UNDEF ||
6579 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6580 X86Opcode = X86ISD::HSUB;
6585 // Fold this build_vector into a single horizontal add/sub.
6586 // Do this only if the target has AVX2.
6587 if (Subtarget->hasAVX2())
6588 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6590 // Do not try to expand this build_vector into a pair of horizontal
6591 // add/sub if we can emit a pair of scalar add/sub.
6592 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6595 // Convert this build_vector into a pair of horizontal binop followed by
6597 bool isUndefLO = NumUndefsLO == Half;
6598 bool isUndefHI = NumUndefsHI == Half;
6599 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6600 isUndefLO, isUndefHI);
6604 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6605 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6607 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6608 X86Opcode = X86ISD::HADD;
6609 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6610 X86Opcode = X86ISD::HSUB;
6611 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6612 X86Opcode = X86ISD::FHADD;
6613 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6614 X86Opcode = X86ISD::FHSUB;
6618 // Don't try to expand this build_vector into a pair of horizontal add/sub
6619 // if we can simply emit a pair of scalar add/sub.
6620 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6623 // Convert this build_vector into two horizontal add/sub followed by
6625 bool isUndefLO = NumUndefsLO == Half;
6626 bool isUndefHI = NumUndefsHI == Half;
6627 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6628 isUndefLO, isUndefHI);
6635 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6638 MVT VT = Op.getSimpleValueType();
6639 MVT ExtVT = VT.getVectorElementType();
6640 unsigned NumElems = Op.getNumOperands();
6642 // Generate vectors for predicate vectors.
6643 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6644 return LowerBUILD_VECTORvXi1(Op, DAG);
6646 // Vectors containing all zeros can be matched by pxor and xorps later
6647 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6648 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6649 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6650 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6653 return getZeroVector(VT, Subtarget, DAG, dl);
6656 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6657 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6658 // vpcmpeqd on 256-bit vectors.
6659 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6660 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6663 if (!VT.is512BitVector())
6664 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6667 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6668 if (Broadcast.getNode())
6671 unsigned EVTBits = ExtVT.getSizeInBits();
6673 unsigned NumZero = 0;
6674 unsigned NumNonZero = 0;
6675 unsigned NonZeros = 0;
6676 bool IsAllConstants = true;
6677 SmallSet<SDValue, 8> Values;
6678 for (unsigned i = 0; i < NumElems; ++i) {
6679 SDValue Elt = Op.getOperand(i);
6680 if (Elt.getOpcode() == ISD::UNDEF)
6683 if (Elt.getOpcode() != ISD::Constant &&
6684 Elt.getOpcode() != ISD::ConstantFP)
6685 IsAllConstants = false;
6686 if (X86::isZeroNode(Elt))
6689 NonZeros |= (1 << i);
6694 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6695 if (NumNonZero == 0)
6696 return DAG.getUNDEF(VT);
6698 // Special case for single non-zero, non-undef, element.
6699 if (NumNonZero == 1) {
6700 unsigned Idx = countTrailingZeros(NonZeros);
6701 SDValue Item = Op.getOperand(Idx);
6703 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6704 // the value are obviously zero, truncate the value to i32 and do the
6705 // insertion that way. Only do this if the value is non-constant or if the
6706 // value is a constant being inserted into element 0. It is cheaper to do
6707 // a constant pool load than it is to do a movd + shuffle.
6708 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6709 (!IsAllConstants || Idx == 0)) {
6710 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6712 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6713 EVT VecVT = MVT::v4i32;
6714 unsigned VecElts = 4;
6716 // Truncate the value (which may itself be a constant) to i32, and
6717 // convert it to a vector with movd (S2V+shuffle to zero extend).
6718 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6719 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6720 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6722 // Now we have our 32-bit value zero extended in the low element of
6723 // a vector. If Idx != 0, swizzle it into place.
6725 SmallVector<int, 4> Mask;
6726 Mask.push_back(Idx);
6727 for (unsigned i = 1; i != VecElts; ++i)
6729 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6732 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6736 // If we have a constant or non-constant insertion into the low element of
6737 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6738 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6739 // depending on what the source datatype is.
6742 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6744 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6745 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6746 if (VT.is256BitVector() || VT.is512BitVector()) {
6747 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6748 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6749 Item, DAG.getIntPtrConstant(0));
6751 assert(VT.is128BitVector() && "Expected an SSE value type!");
6752 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6753 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6754 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6757 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6758 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6759 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6760 if (VT.is256BitVector()) {
6761 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6762 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6764 assert(VT.is128BitVector() && "Expected an SSE value type!");
6765 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6767 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6771 // Is it a vector logical left shift?
6772 if (NumElems == 2 && Idx == 1 &&
6773 X86::isZeroNode(Op.getOperand(0)) &&
6774 !X86::isZeroNode(Op.getOperand(1))) {
6775 unsigned NumBits = VT.getSizeInBits();
6776 return getVShift(true, VT,
6777 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6778 VT, Op.getOperand(1)),
6779 NumBits/2, DAG, *this, dl);
6782 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6785 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6786 // is a non-constant being inserted into an element other than the low one,
6787 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6788 // movd/movss) to move this into the low element, then shuffle it into
6790 if (EVTBits == 32) {
6791 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6793 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6794 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6795 SmallVector<int, 8> MaskVec;
6796 for (unsigned i = 0; i != NumElems; ++i)
6797 MaskVec.push_back(i == Idx ? 0 : 1);
6798 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6802 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6803 if (Values.size() == 1) {
6804 if (EVTBits == 32) {
6805 // Instead of a shuffle like this:
6806 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6807 // Check if it's possible to issue this instead.
6808 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6809 unsigned Idx = countTrailingZeros(NonZeros);
6810 SDValue Item = Op.getOperand(Idx);
6811 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6812 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6817 // A vector full of immediates; various special cases are already
6818 // handled, so this is best done with a single constant-pool load.
6822 // For AVX-length vectors, build the individual 128-bit pieces and use
6823 // shuffles to put them in place.
6824 if (VT.is256BitVector() || VT.is512BitVector()) {
6825 SmallVector<SDValue, 64> V;
6826 for (unsigned i = 0; i != NumElems; ++i)
6827 V.push_back(Op.getOperand(i));
6829 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6831 // Build both the lower and upper subvector.
6832 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6833 makeArrayRef(&V[0], NumElems/2));
6834 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6835 makeArrayRef(&V[NumElems / 2], NumElems/2));
6837 // Recreate the wider vector with the lower and upper part.
6838 if (VT.is256BitVector())
6839 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6840 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6843 // Let legalizer expand 2-wide build_vectors.
6844 if (EVTBits == 64) {
6845 if (NumNonZero == 1) {
6846 // One half is zero or undef.
6847 unsigned Idx = countTrailingZeros(NonZeros);
6848 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6849 Op.getOperand(Idx));
6850 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6855 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6856 if (EVTBits == 8 && NumElems == 16) {
6857 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6859 if (V.getNode()) return V;
6862 if (EVTBits == 16 && NumElems == 8) {
6863 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6865 if (V.getNode()) return V;
6868 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6869 if (EVTBits == 32 && NumElems == 4) {
6870 SDValue V = LowerBuildVectorv4x32(Op, NumElems, NonZeros, NumNonZero,
6871 NumZero, DAG, Subtarget, *this);
6876 // If element VT is == 32 bits, turn it into a number of shuffles.
6877 SmallVector<SDValue, 8> V(NumElems);
6878 if (NumElems == 4 && NumZero > 0) {
6879 for (unsigned i = 0; i < 4; ++i) {
6880 bool isZero = !(NonZeros & (1 << i));
6882 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6884 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6887 for (unsigned i = 0; i < 2; ++i) {
6888 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6891 V[i] = V[i*2]; // Must be a zero vector.
6894 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6897 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6900 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6905 bool Reverse1 = (NonZeros & 0x3) == 2;
6906 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6910 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6911 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6913 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6916 if (Values.size() > 1 && VT.is128BitVector()) {
6917 // Check for a build vector of consecutive loads.
6918 for (unsigned i = 0; i < NumElems; ++i)
6919 V[i] = Op.getOperand(i);
6921 // Check for elements which are consecutive loads.
6922 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
6926 // Check for a build vector from mostly shuffle plus few inserting.
6927 SDValue Sh = buildFromShuffleMostly(Op, DAG);
6931 // For SSE 4.1, use insertps to put the high elements into the low element.
6932 if (getSubtarget()->hasSSE41()) {
6934 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6935 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6937 Result = DAG.getUNDEF(VT);
6939 for (unsigned i = 1; i < NumElems; ++i) {
6940 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6941 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6942 Op.getOperand(i), DAG.getIntPtrConstant(i));
6947 // Otherwise, expand into a number of unpckl*, start by extending each of
6948 // our (non-undef) elements to the full vector width with the element in the
6949 // bottom slot of the vector (which generates no code for SSE).
6950 for (unsigned i = 0; i < NumElems; ++i) {
6951 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6952 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6954 V[i] = DAG.getUNDEF(VT);
6957 // Next, we iteratively mix elements, e.g. for v4f32:
6958 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6959 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6960 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6961 unsigned EltStride = NumElems >> 1;
6962 while (EltStride != 0) {
6963 for (unsigned i = 0; i < EltStride; ++i) {
6964 // If V[i+EltStride] is undef and this is the first round of mixing,
6965 // then it is safe to just drop this shuffle: V[i] is already in the
6966 // right place, the one element (since it's the first round) being
6967 // inserted as undef can be dropped. This isn't safe for successive
6968 // rounds because they will permute elements within both vectors.
6969 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6970 EltStride == NumElems/2)
6973 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6982 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6983 // to create 256-bit vectors from two other 128-bit ones.
6984 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6986 MVT ResVT = Op.getSimpleValueType();
6988 assert((ResVT.is256BitVector() ||
6989 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6991 SDValue V1 = Op.getOperand(0);
6992 SDValue V2 = Op.getOperand(1);
6993 unsigned NumElems = ResVT.getVectorNumElements();
6994 if(ResVT.is256BitVector())
6995 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6997 if (Op.getNumOperands() == 4) {
6998 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6999 ResVT.getVectorNumElements()/2);
7000 SDValue V3 = Op.getOperand(2);
7001 SDValue V4 = Op.getOperand(3);
7002 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7003 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7005 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7008 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7009 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7010 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7011 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7012 Op.getNumOperands() == 4)));
7014 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7015 // from two other 128-bit ones.
7017 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7018 return LowerAVXCONCAT_VECTORS(Op, DAG);
7022 //===----------------------------------------------------------------------===//
7023 // Vector shuffle lowering
7025 // This is an experimental code path for lowering vector shuffles on x86. It is
7026 // designed to handle arbitrary vector shuffles and blends, gracefully
7027 // degrading performance as necessary. It works hard to recognize idiomatic
7028 // shuffles and lower them to optimal instruction patterns without leaving
7029 // a framework that allows reasonably efficient handling of all vector shuffle
7031 //===----------------------------------------------------------------------===//
7033 /// \brief Tiny helper function to identify a no-op mask.
7035 /// This is a somewhat boring predicate function. It checks whether the mask
7036 /// array input, which is assumed to be a single-input shuffle mask of the kind
7037 /// used by the X86 shuffle instructions (not a fully general
7038 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7039 /// in-place shuffle are 'no-op's.
7040 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7041 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7042 if (Mask[i] != -1 && Mask[i] != i)
7047 /// \brief Helper function to classify a mask as a single-input mask.
7049 /// This isn't a generic single-input test because in the vector shuffle
7050 /// lowering we canonicalize single inputs to be the first input operand. This
7051 /// means we can more quickly test for a single input by only checking whether
7052 /// an input from the second operand exists. We also assume that the size of
7053 /// mask corresponds to the size of the input vectors which isn't true in the
7054 /// fully general case.
7055 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7057 if (M >= (int)Mask.size())
7062 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7064 /// This helper function produces an 8-bit shuffle immediate corresponding to
7065 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7066 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7069 /// NB: We rely heavily on "undef" masks preserving the input lane.
7070 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7071 SelectionDAG &DAG) {
7072 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7073 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7074 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7075 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7076 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7079 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7080 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7081 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7082 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7083 return DAG.getConstant(Imm, MVT::i8);
7086 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7088 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7089 /// support for floating point shuffles but not integer shuffles. These
7090 /// instructions will incur a domain crossing penalty on some chips though so
7091 /// it is better to avoid lowering through this for integer vectors where
7093 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7094 const X86Subtarget *Subtarget,
7095 SelectionDAG &DAG) {
7097 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7098 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7099 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7100 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7101 ArrayRef<int> Mask = SVOp->getMask();
7102 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7104 if (isSingleInputShuffleMask(Mask)) {
7105 // Straight shuffle of a single input vector. Simulate this by using the
7106 // single input as both of the "inputs" to this instruction..
7107 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7108 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
7109 DAG.getConstant(SHUFPDMask, MVT::i8));
7111 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7112 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7114 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7115 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
7116 DAG.getConstant(SHUFPDMask, MVT::i8));
7119 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7121 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7122 /// the integer unit to minimize domain crossing penalties. However, for blends
7123 /// it falls back to the floating point shuffle operation with appropriate bit
7125 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7126 const X86Subtarget *Subtarget,
7127 SelectionDAG &DAG) {
7129 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7130 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7131 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7132 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7133 ArrayRef<int> Mask = SVOp->getMask();
7134 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7136 if (isSingleInputShuffleMask(Mask)) {
7137 // Straight shuffle of a single input vector. For everything from SSE2
7138 // onward this has a single fast instruction with no scary immediates.
7139 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7140 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
7141 int WidenedMask[4] = {
7142 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7143 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7145 ISD::BITCAST, DL, MVT::v2i64,
7146 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
7147 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
7150 // We implement this with SHUFPD which is pretty lame because it will likely
7151 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7152 // However, all the alternatives are still more cycles and newer chips don't
7153 // have this problem. It would be really nice if x86 had better shuffles here.
7154 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
7155 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
7156 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7157 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7160 /// \brief Lower 4-lane 32-bit floating point shuffles.
7162 /// Uses instructions exclusively from the floating point unit to minimize
7163 /// domain crossing penalties, as these are sufficient to implement all v4f32
7165 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7166 const X86Subtarget *Subtarget,
7167 SelectionDAG &DAG) {
7169 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7170 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7171 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7172 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7173 ArrayRef<int> Mask = SVOp->getMask();
7174 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7176 SDValue LowV = V1, HighV = V2;
7177 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7180 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7182 if (NumV2Elements == 0)
7183 // Straight shuffle of a single input vector. We pass the input vector to
7184 // both operands to simulate this with a SHUFPS.
7185 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7186 getV4X86ShuffleImm8ForMask(Mask, DAG));
7188 if (NumV2Elements == 1) {
7190 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7192 // Compute the index adjacent to V2Index and in the same half by toggling
7194 int V2AdjIndex = V2Index ^ 1;
7196 if (Mask[V2AdjIndex] == -1) {
7197 // Handles all the cases where we have a single V2 element and an undef.
7198 // This will only ever happen in the high lanes because we commute the
7199 // vector otherwise.
7201 std::swap(LowV, HighV);
7202 NewMask[V2Index] -= 4;
7204 // Handle the case where the V2 element ends up adjacent to a V1 element.
7205 // To make this work, blend them together as the first step.
7206 int V1Index = V2AdjIndex;
7207 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7208 V2 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V2, V1,
7209 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7211 // Now proceed to reconstruct the final blend as we have the necessary
7212 // high or low half formed.
7219 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7220 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7222 } else if (NumV2Elements == 2) {
7223 if (Mask[0] < 4 && Mask[1] < 4) {
7224 // Handle the easy case where we have V1 in the low lanes and V2 in the
7225 // high lanes. We never see this reversed because we sort the shuffle.
7229 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7230 // trying to place elements directly, just blend them and set up the final
7231 // shuffle to place them.
7233 // The first two blend mask elements are for V1, the second two are for
7235 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7236 Mask[2] < 4 ? Mask[2] : Mask[3],
7237 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7238 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7239 V1 = DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V2,
7240 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
7242 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7245 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7246 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7247 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7248 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7251 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, LowV, HighV,
7252 getV4X86ShuffleImm8ForMask(NewMask, DAG));
7255 /// \brief Lower 4-lane i32 vector shuffles.
7257 /// We try to handle these with integer-domain shuffles where we can, but for
7258 /// blends we use the floating point domain blend instructions.
7259 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7260 const X86Subtarget *Subtarget,
7261 SelectionDAG &DAG) {
7263 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7264 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7265 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7266 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7267 ArrayRef<int> Mask = SVOp->getMask();
7268 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7270 if (isSingleInputShuffleMask(Mask))
7271 // Straight shuffle of a single input vector. For everything from SSE2
7272 // onward this has a single fast instruction with no scary immediates.
7273 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7274 getV4X86ShuffleImm8ForMask(Mask, DAG));
7276 // We implement this with SHUFPS because it can blend from two vectors.
7277 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7278 // up the inputs, bypassing domain shift penalties that we would encur if we
7279 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7281 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
7282 DAG.getVectorShuffle(
7284 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
7285 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
7288 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7289 /// shuffle lowering, and the most complex part.
7291 /// The lowering strategy is to try to form pairs of input lanes which are
7292 /// targeted at the same half of the final vector, and then use a dword shuffle
7293 /// to place them onto the right half, and finally unpack the paired lanes into
7294 /// their final position.
7296 /// The exact breakdown of how to form these dword pairs and align them on the
7297 /// correct sides is really tricky. See the comments within the function for
7298 /// more of the details.
7299 static SDValue lowerV8I16SingleInputVectorShuffle(
7300 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
7301 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7302 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7303 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7304 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7306 SmallVector<int, 4> LoInputs;
7307 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7308 [](int M) { return M >= 0; });
7309 std::sort(LoInputs.begin(), LoInputs.end());
7310 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7311 SmallVector<int, 4> HiInputs;
7312 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7313 [](int M) { return M >= 0; });
7314 std::sort(HiInputs.begin(), HiInputs.end());
7315 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7317 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7318 int NumHToL = LoInputs.size() - NumLToL;
7320 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7321 int NumHToH = HiInputs.size() - NumLToH;
7322 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7323 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7324 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7325 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7327 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7328 // such inputs we can swap two of the dwords across the half mark and end up
7329 // with <=2 inputs to each half in each half. Once there, we can fall through
7330 // to the generic code below. For example:
7332 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7333 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
7335 // Before we had 3-1 in the low half and 3-1 in the high half. Afterward, 2-2
7337 auto balanceSides = [&](ArrayRef<int> ThreeInputs, int OneInput,
7338 int ThreeInputHalfSum, int OneInputHalfOffset) {
7339 // Compute the index of dword with only one word among the three inputs in
7340 // a half by taking the sum of the half with three inputs and subtracting
7341 // the sum of the actual three inputs. The difference is the remaining
7343 int DWordA = (ThreeInputHalfSum -
7344 std::accumulate(ThreeInputs.begin(), ThreeInputs.end(), 0)) /
7346 int DWordB = OneInputHalfOffset / 2 + (OneInput / 2 + 1) % 2;
7348 int PSHUFDMask[] = {0, 1, 2, 3};
7349 PSHUFDMask[DWordA] = DWordB;
7350 PSHUFDMask[DWordB] = DWordA;
7351 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7352 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7353 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7354 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7356 // Adjust the mask to match the new locations of A and B.
7358 if (M != -1 && M/2 == DWordA)
7359 M = 2 * DWordB + M % 2;
7360 else if (M != -1 && M/2 == DWordB)
7361 M = 2 * DWordA + M % 2;
7363 // Recurse back into this routine to re-compute state now that this isn't
7364 // a 3 and 1 problem.
7365 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7368 if (NumLToL == 3 && NumHToL == 1)
7369 return balanceSides(LToLInputs, HToLInputs[0], 0 + 1 + 2 + 3, 4);
7370 else if (NumLToL == 1 && NumHToL == 3)
7371 return balanceSides(HToLInputs, LToLInputs[0], 4 + 5 + 6 + 7, 0);
7372 else if (NumLToH == 1 && NumHToH == 3)
7373 return balanceSides(HToHInputs, LToHInputs[0], 4 + 5 + 6 + 7, 0);
7374 else if (NumLToH == 3 && NumHToH == 1)
7375 return balanceSides(LToHInputs, HToHInputs[0], 0 + 1 + 2 + 3, 4);
7377 // At this point there are at most two inputs to the low and high halves from
7378 // each half. That means the inputs can always be grouped into dwords and
7379 // those dwords can then be moved to the correct half with a dword shuffle.
7380 // We use at most one low and one high word shuffle to collect these paired
7381 // inputs into dwords, and finally a dword shuffle to place them.
7382 int PSHUFLMask[4] = {-1, -1, -1, -1};
7383 int PSHUFHMask[4] = {-1, -1, -1, -1};
7384 int PSHUFDMask[4] = {-1, -1, -1, -1};
7386 // First fix the masks for all the inputs that are staying in their
7387 // original halves. This will then dictate the targets of the cross-half
7389 auto fixInPlaceInputs = [&PSHUFDMask](
7390 ArrayRef<int> InPlaceInputs, MutableArrayRef<int> SourceHalfMask,
7391 MutableArrayRef<int> HalfMask, int HalfOffset) {
7392 if (InPlaceInputs.empty())
7394 if (InPlaceInputs.size() == 1) {
7395 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7396 InPlaceInputs[0] - HalfOffset;
7397 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
7401 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
7402 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
7403 InPlaceInputs[0] - HalfOffset;
7404 // Put the second input next to the first so that they are packed into
7405 // a dword. We find the adjacent index by toggling the low bit.
7406 int AdjIndex = InPlaceInputs[0] ^ 1;
7407 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
7408 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
7409 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
7411 if (!HToLInputs.empty())
7412 fixInPlaceInputs(LToLInputs, PSHUFLMask, LoMask, 0);
7413 if (!LToHInputs.empty())
7414 fixInPlaceInputs(HToHInputs, PSHUFHMask, HiMask, 4);
7416 // Now gather the cross-half inputs and place them into a free dword of
7417 // their target half.
7418 // FIXME: This operation could almost certainly be simplified dramatically to
7419 // look more like the 3-1 fixing operation.
7420 auto moveInputsToRightHalf = [&PSHUFDMask](
7421 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
7422 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
7423 int SourceOffset, int DestOffset) {
7424 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
7425 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
7427 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
7429 int LowWord = Word & ~1;
7430 int HighWord = Word | 1;
7431 return isWordClobbered(SourceHalfMask, LowWord) ||
7432 isWordClobbered(SourceHalfMask, HighWord);
7435 if (IncomingInputs.empty())
7438 if (ExistingInputs.empty()) {
7439 // Map any dwords with inputs from them into the right half.
7440 for (int Input : IncomingInputs) {
7441 // If the source half mask maps over the inputs, turn those into
7442 // swaps and use the swapped lane.
7443 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
7444 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
7445 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
7446 Input - SourceOffset;
7447 // We have to swap the uses in our half mask in one sweep.
7448 for (int &M : HalfMask)
7449 if (M == SourceHalfMask[Input - SourceOffset])
7451 else if (M == Input)
7452 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7454 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
7455 Input - SourceOffset &&
7456 "Previous placement doesn't match!");
7458 // Note that this correctly re-maps both when we do a swap and when
7459 // we observe the other side of the swap above. We rely on that to
7460 // avoid swapping the members of the input list directly.
7461 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
7464 // Map the input's dword into the correct half.
7465 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
7466 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
7468 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
7470 "Previous placement doesn't match!");
7473 // And just directly shift any other-half mask elements to be same-half
7474 // as we will have mirrored the dword containing the element into the
7475 // same position within that half.
7476 for (int &M : HalfMask)
7477 if (M >= SourceOffset && M < SourceOffset + 4) {
7478 M = M - SourceOffset + DestOffset;
7479 assert(M >= 0 && "This should never wrap below zero!");
7484 // Ensure we have the input in a viable dword of its current half. This
7485 // is particularly tricky because the original position may be clobbered
7486 // by inputs being moved and *staying* in that half.
7487 if (IncomingInputs.size() == 1) {
7488 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7489 int InputFixed = std::find(std::begin(SourceHalfMask),
7490 std::end(SourceHalfMask), -1) -
7491 std::begin(SourceHalfMask) + SourceOffset;
7492 SourceHalfMask[InputFixed - SourceOffset] =
7493 IncomingInputs[0] - SourceOffset;
7494 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
7496 IncomingInputs[0] = InputFixed;
7498 } else if (IncomingInputs.size() == 2) {
7499 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
7500 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
7501 int SourceDWordBase = !isDWordClobbered(SourceHalfMask, 0) ? 0 : 2;
7502 assert(!isDWordClobbered(SourceHalfMask, SourceDWordBase) &&
7503 "Not all dwords can be clobbered!");
7504 SourceHalfMask[SourceDWordBase] = IncomingInputs[0] - SourceOffset;
7505 SourceHalfMask[SourceDWordBase + 1] = IncomingInputs[1] - SourceOffset;
7506 for (int &M : HalfMask)
7507 if (M == IncomingInputs[0])
7508 M = SourceDWordBase + SourceOffset;
7509 else if (M == IncomingInputs[1])
7510 M = SourceDWordBase + 1 + SourceOffset;
7511 IncomingInputs[0] = SourceDWordBase + SourceOffset;
7512 IncomingInputs[1] = SourceDWordBase + 1 + SourceOffset;
7515 llvm_unreachable("Unhandled input size!");
7518 // Now hoist the DWord down to the right half.
7519 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
7520 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
7521 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
7522 for (int &M : HalfMask)
7523 for (int Input : IncomingInputs)
7525 M = FreeDWord * 2 + Input % 2;
7527 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask,
7528 /*SourceOffset*/ 4, /*DestOffset*/ 0);
7529 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask,
7530 /*SourceOffset*/ 0, /*DestOffset*/ 4);
7532 // Now enact all the shuffles we've computed to move the inputs into their
7534 if (!isNoopShuffleMask(PSHUFLMask))
7535 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7536 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
7537 if (!isNoopShuffleMask(PSHUFHMask))
7538 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7539 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
7540 if (!isNoopShuffleMask(PSHUFDMask))
7541 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7542 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7543 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
7544 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7546 // At this point, each half should contain all its inputs, and we can then
7547 // just shuffle them into their final position.
7548 assert(std::count_if(LoMask.begin(), LoMask.end(),
7549 [](int M) { return M >= 4; }) == 0 &&
7550 "Failed to lift all the high half inputs to the low mask!");
7551 assert(std::count_if(HiMask.begin(), HiMask.end(),
7552 [](int M) { return M >= 0 && M < 4; }) == 0 &&
7553 "Failed to lift all the low half inputs to the high mask!");
7555 // Do a half shuffle for the low mask.
7556 if (!isNoopShuffleMask(LoMask))
7557 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
7558 getV4X86ShuffleImm8ForMask(LoMask, DAG));
7560 // Do a half shuffle with the high mask after shifting its values down.
7561 for (int &M : HiMask)
7564 if (!isNoopShuffleMask(HiMask))
7565 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
7566 getV4X86ShuffleImm8ForMask(HiMask, DAG));
7571 /// \brief Detect whether the mask pattern should be lowered through
7574 /// This essentially tests whether viewing the mask as an interleaving of two
7575 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
7576 /// lowering it through interleaving is a significantly better strategy.
7577 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
7578 int NumEvenInputs[2] = {0, 0};
7579 int NumOddInputs[2] = {0, 0};
7580 int NumLoInputs[2] = {0, 0};
7581 int NumHiInputs[2] = {0, 0};
7582 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7586 int InputIdx = Mask[i] >= Size;
7589 ++NumLoInputs[InputIdx];
7591 ++NumHiInputs[InputIdx];
7594 ++NumEvenInputs[InputIdx];
7596 ++NumOddInputs[InputIdx];
7599 // The minimum number of cross-input results for both the interleaved and
7600 // split cases. If interleaving results in fewer cross-input results, return
7602 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
7603 NumEvenInputs[0] + NumOddInputs[1]);
7604 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
7605 NumLoInputs[0] + NumHiInputs[1]);
7606 return InterleavedCrosses < SplitCrosses;
7609 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
7611 /// This strategy only works when the inputs from each vector fit into a single
7612 /// half of that vector, and generally there are not so many inputs as to leave
7613 /// the in-place shuffles required highly constrained (and thus expensive). It
7614 /// shifts all the inputs into a single side of both input vectors and then
7615 /// uses an unpack to interleave these inputs in a single vector. At that
7616 /// point, we will fall back on the generic single input shuffle lowering.
7617 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
7619 MutableArrayRef<int> Mask,
7620 const X86Subtarget *Subtarget,
7621 SelectionDAG &DAG) {
7622 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7623 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
7624 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
7625 for (int i = 0; i < 8; ++i)
7626 if (Mask[i] >= 0 && Mask[i] < 4)
7627 LoV1Inputs.push_back(i);
7628 else if (Mask[i] >= 4 && Mask[i] < 8)
7629 HiV1Inputs.push_back(i);
7630 else if (Mask[i] >= 8 && Mask[i] < 12)
7631 LoV2Inputs.push_back(i);
7632 else if (Mask[i] >= 12)
7633 HiV2Inputs.push_back(i);
7635 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
7636 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
7639 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
7640 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
7641 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
7643 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
7644 HiV1Inputs.size() + HiV2Inputs.size();
7646 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
7647 ArrayRef<int> HiInputs, bool MoveToLo,
7649 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
7650 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
7651 if (BadInputs.empty())
7654 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7655 int MoveOffset = MoveToLo ? 0 : 4;
7657 if (GoodInputs.empty()) {
7658 for (int BadInput : BadInputs) {
7659 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
7660 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
7663 if (GoodInputs.size() == 2) {
7664 // If the low inputs are spread across two dwords, pack them into
7666 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
7667 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
7668 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
7669 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
7671 // Otherwise pin the good inputs.
7672 for (int GoodInput : GoodInputs)
7673 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
7676 if (BadInputs.size() == 2) {
7677 // If we have two bad inputs then there may be either one or two good
7678 // inputs fixed in place. Find a fixed input, and then find the *other*
7679 // two adjacent indices by using modular arithmetic.
7681 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
7682 [](int M) { return M >= 0; }) -
7683 std::begin(MoveMask);
7685 (((GoodMaskIdx - MoveOffset) & ~1) + 2 % 4) + MoveOffset;
7686 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
7687 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
7688 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7689 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
7690 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7691 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
7693 assert(BadInputs.size() == 1 && "All sizes handled");
7694 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
7695 std::end(MoveMask), -1) -
7696 std::begin(MoveMask);
7697 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
7698 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
7702 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
7705 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
7707 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
7710 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
7711 // cross-half traffic in the final shuffle.
7713 // Munge the mask to be a single-input mask after the unpack merges the
7717 M = 2 * (M % 4) + (M / 8);
7719 return DAG.getVectorShuffle(
7720 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
7721 DL, MVT::v8i16, V1, V2),
7722 DAG.getUNDEF(MVT::v8i16), Mask);
7725 /// \brief Generic lowering of 8-lane i16 shuffles.
7727 /// This handles both single-input shuffles and combined shuffle/blends with
7728 /// two inputs. The single input shuffles are immediately delegated to
7729 /// a dedicated lowering routine.
7731 /// The blends are lowered in one of three fundamental ways. If there are few
7732 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
7733 /// of the input is significantly cheaper when lowered as an interleaving of
7734 /// the two inputs, try to interleave them. Otherwise, blend the low and high
7735 /// halves of the inputs separately (making them have relatively few inputs)
7736 /// and then concatenate them.
7737 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7738 const X86Subtarget *Subtarget,
7739 SelectionDAG &DAG) {
7741 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
7742 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7743 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
7744 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7745 ArrayRef<int> OrigMask = SVOp->getMask();
7746 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7747 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
7748 MutableArrayRef<int> Mask(MaskStorage);
7750 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
7752 auto isV1 = [](int M) { return M >= 0 && M < 8; };
7753 auto isV2 = [](int M) { return M >= 8; };
7755 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
7756 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
7758 if (NumV2Inputs == 0)
7759 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
7761 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
7762 "to be V1-input shuffles.");
7764 if (NumV1Inputs + NumV2Inputs <= 4)
7765 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
7767 // Check whether an interleaving lowering is likely to be more efficient.
7768 // This isn't perfect but it is a strong heuristic that tends to work well on
7769 // the kinds of shuffles that show up in practice.
7771 // FIXME: Handle 1x, 2x, and 4x interleaving.
7772 if (shouldLowerAsInterleaving(Mask)) {
7773 // FIXME: Figure out whether we should pack these into the low or high
7776 int EMask[8], OMask[8];
7777 for (int i = 0; i < 4; ++i) {
7778 EMask[i] = Mask[2*i];
7779 OMask[i] = Mask[2*i + 1];
7784 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
7785 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
7787 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
7790 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7791 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7793 for (int i = 0; i < 4; ++i) {
7794 LoBlendMask[i] = Mask[i];
7795 HiBlendMask[i] = Mask[i + 4];
7798 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
7799 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
7800 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
7801 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
7803 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
7804 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
7807 /// \brief Check whether a compaction lowering can be done by dropping even
7808 /// elements and compute how many times even elements must be dropped.
7810 /// This handles shuffles which take every Nth element where N is a power of
7811 /// two. Example shuffle masks:
7813 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
7814 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
7815 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
7816 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
7817 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
7818 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
7820 /// Any of these lanes can of course be undef.
7822 /// This routine only supports N <= 3.
7823 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
7826 /// \returns N above, or the number of times even elements must be dropped if
7827 /// there is such a number. Otherwise returns zero.
7828 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
7829 // Figure out whether we're looping over two inputs or just one.
7830 bool IsSingleInput = isSingleInputShuffleMask(Mask);
7832 // The modulus for the shuffle vector entries is based on whether this is
7833 // a single input or not.
7834 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
7835 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
7836 "We should only be called with masks with a power-of-2 size!");
7838 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
7840 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
7841 // and 2^3 simultaneously. This is because we may have ambiguity with
7842 // partially undef inputs.
7843 bool ViableForN[3] = {true, true, true};
7845 for (int i = 0, e = Mask.size(); i < e; ++i) {
7846 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
7851 bool IsAnyViable = false;
7852 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
7853 if (ViableForN[j]) {
7856 // The shuffle mask must be equal to (i * 2^N) % M.
7857 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
7860 ViableForN[j] = false;
7862 // Early exit if we exhaust the possible powers of two.
7867 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
7871 // Return 0 as there is no viable power of two.
7875 /// \brief Generic lowering of v16i8 shuffles.
7877 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
7878 /// detect any complexity reducing interleaving. If that doesn't help, it uses
7879 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
7880 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
7882 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7883 const X86Subtarget *Subtarget,
7884 SelectionDAG &DAG) {
7886 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
7887 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7888 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
7889 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7890 ArrayRef<int> OrigMask = SVOp->getMask();
7891 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
7892 int MaskStorage[16] = {
7893 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
7894 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
7895 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
7896 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
7897 MutableArrayRef<int> Mask(MaskStorage);
7898 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
7899 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
7901 // For single-input shuffles, there are some nicer lowering tricks we can use.
7902 if (isSingleInputShuffleMask(Mask)) {
7903 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
7904 // Notably, this handles splat and partial-splat shuffles more efficiently.
7905 // However, it only makes sense if the pre-duplication shuffle simplifies
7906 // things significantly. Currently, this means we need to be able to
7907 // express the pre-duplication shuffle as an i16 shuffle.
7909 // FIXME: We should check for other patterns which can be widened into an
7910 // i16 shuffle as well.
7911 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
7912 for (int i = 0; i < 16; i += 2) {
7913 if (Mask[i] != Mask[i + 1])
7918 auto tryToWidenViaDuplication = [&]() -> SDValue {
7919 if (!canWidenViaDuplication(Mask))
7921 SmallVector<int, 4> LoInputs;
7922 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
7923 [](int M) { return M >= 0 && M < 8; });
7924 std::sort(LoInputs.begin(), LoInputs.end());
7925 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
7927 SmallVector<int, 4> HiInputs;
7928 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
7929 [](int M) { return M >= 8; });
7930 std::sort(HiInputs.begin(), HiInputs.end());
7931 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
7934 bool TargetLo = LoInputs.size() >= HiInputs.size();
7935 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
7936 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
7938 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
7939 SmallDenseMap<int, int, 8> LaneMap;
7940 for (int I : InPlaceInputs) {
7941 PreDupI16Shuffle[I/2] = I/2;
7944 int j = TargetLo ? 0 : 4, je = j + 4;
7945 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
7946 // Check if j is already a shuffle of this input. This happens when
7947 // there are two adjacent bytes after we move the low one.
7948 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
7949 // If we haven't yet mapped the input, search for a slot into which
7951 while (j < je && PreDupI16Shuffle[j] != -1)
7955 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
7958 // Map this input with the i16 shuffle.
7959 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
7962 // Update the lane map based on the mapping we ended up with.
7963 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
7966 ISD::BITCAST, DL, MVT::v16i8,
7967 DAG.getVectorShuffle(MVT::v8i16, DL,
7968 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7969 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
7971 // Unpack the bytes to form the i16s that will be shuffled into place.
7972 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7973 MVT::v16i8, V1, V1);
7975 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
7976 for (int i = 0; i < 16; i += 2) {
7978 PostDupI16Shuffle[i / 2] = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
7979 assert(PostDupI16Shuffle[i / 2] < 8 && "Invalid v8 shuffle mask!");
7982 ISD::BITCAST, DL, MVT::v16i8,
7983 DAG.getVectorShuffle(MVT::v8i16, DL,
7984 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
7985 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
7987 if (SDValue V = tryToWidenViaDuplication())
7991 // Check whether an interleaving lowering is likely to be more efficient.
7992 // This isn't perfect but it is a strong heuristic that tends to work well on
7993 // the kinds of shuffles that show up in practice.
7995 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
7996 if (shouldLowerAsInterleaving(Mask)) {
7997 // FIXME: Figure out whether we should pack these into the low or high
8000 int EMask[16], OMask[16];
8001 for (int i = 0; i < 8; ++i) {
8002 EMask[i] = Mask[2*i];
8003 OMask[i] = Mask[2*i + 1];
8008 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
8009 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
8011 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, Evens, Odds);
8014 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8015 // with PSHUFB. It is important to do this before we attempt to generate any
8016 // blends but after all of the single-input lowerings. If the single input
8017 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8018 // want to preserve that and we can DAG combine any longer sequences into
8019 // a PSHUFB in the end. But once we start blending from multiple inputs,
8020 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8021 // and there are *very* few patterns that would actually be faster than the
8022 // PSHUFB approach because of its ability to zero lanes.
8024 // FIXME: The only exceptions to the above are blends which are exact
8025 // interleavings with direct instructions supporting them. We currently don't
8026 // handle those well here.
8027 if (Subtarget->hasSSSE3()) {
8030 for (int i = 0; i < 16; ++i)
8031 if (Mask[i] == -1) {
8032 V1Mask[i] = V2Mask[i] = DAG.getConstant(0x80, MVT::i8);
8034 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
8036 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
8038 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
8039 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8040 if (isSingleInputShuffleMask(Mask))
8041 return V1; // Single inputs are easy.
8043 // Otherwise, blend the two.
8044 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
8045 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8046 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8049 // Check whether a compaction lowering can be done. This handles shuffles
8050 // which take every Nth element for some even N. See the helper function for
8053 // We special case these as they can be particularly efficiently handled with
8054 // the PACKUSB instruction on x86 and they show up in common patterns of
8055 // rearranging bytes to truncate wide elements.
8056 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8057 // NumEvenDrops is the power of two stride of the elements. Another way of
8058 // thinking about it is that we need to drop the even elements this many
8059 // times to get the original input.
8060 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8062 // First we need to zero all the dropped bytes.
8063 assert(NumEvenDrops <= 3 &&
8064 "No support for dropping even elements more than 3 times.");
8065 // We use the mask type to pick which bytes are preserved based on how many
8066 // elements are dropped.
8067 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8068 SDValue ByteClearMask =
8069 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
8070 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
8071 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8073 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8075 // Now pack things back together.
8076 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
8077 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
8078 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8079 for (int i = 1; i < NumEvenDrops; ++i) {
8080 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
8081 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8087 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8088 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8089 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8090 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8092 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
8093 MutableArrayRef<int> V1HalfBlendMask,
8094 MutableArrayRef<int> V2HalfBlendMask) {
8095 for (int i = 0; i < 8; ++i)
8096 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
8097 V1HalfBlendMask[i] = HalfMask[i];
8099 } else if (HalfMask[i] >= 16) {
8100 V2HalfBlendMask[i] = HalfMask[i] - 16;
8101 HalfMask[i] = i + 8;
8104 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
8105 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
8107 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8109 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
8110 MutableArrayRef<int> HiBlendMask) {
8112 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8113 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8115 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
8116 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8117 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
8118 [](int M) { return M >= 0 && M % 2 == 1; })) {
8119 // Use a mask to drop the high bytes.
8120 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
8121 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
8122 DAG.getConstant(0x00FF, MVT::v8i16));
8124 // This will be a single vector shuffle instead of a blend so nuke V2.
8125 V2 = DAG.getUNDEF(MVT::v8i16);
8127 // Squash the masks to point directly into V1.
8128 for (int &M : LoBlendMask)
8131 for (int &M : HiBlendMask)
8135 // Otherwise just unpack the low half of V into V1 and the high half into
8136 // V2 so that we can blend them as i16s.
8137 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8138 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8139 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8140 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8143 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
8144 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
8145 return std::make_pair(BlendedLo, BlendedHi);
8147 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
8148 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
8149 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
8151 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
8152 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
8154 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8157 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8159 /// This routine breaks down the specific type of 128-bit shuffle and
8160 /// dispatches to the lowering routines accordingly.
8161 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8162 MVT VT, const X86Subtarget *Subtarget,
8163 SelectionDAG &DAG) {
8164 switch (VT.SimpleTy) {
8166 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8168 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8170 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8172 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8174 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8176 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8179 llvm_unreachable("Unimplemented!");
8183 /// \brief Tiny helper function to test whether adjacent masks are sequential.
8184 static bool areAdjacentMasksSequential(ArrayRef<int> Mask) {
8185 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8186 if (Mask[i] + 1 != Mask[i+1])
8192 /// \brief Top-level lowering for x86 vector shuffles.
8194 /// This handles decomposition, canonicalization, and lowering of all x86
8195 /// vector shuffles. Most of the specific lowering strategies are encapsulated
8196 /// above in helper routines. The canonicalization attempts to widen shuffles
8197 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
8198 /// s.t. only one of the two inputs needs to be tested, etc.
8199 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
8200 SelectionDAG &DAG) {
8201 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8202 ArrayRef<int> Mask = SVOp->getMask();
8203 SDValue V1 = Op.getOperand(0);
8204 SDValue V2 = Op.getOperand(1);
8205 MVT VT = Op.getSimpleValueType();
8206 int NumElements = VT.getVectorNumElements();
8209 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
8211 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
8212 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8213 if (V1IsUndef && V2IsUndef)
8214 return DAG.getUNDEF(VT);
8216 // When we create a shuffle node we put the UNDEF node to second operand,
8217 // but in some cases the first operand may be transformed to UNDEF.
8218 // In this case we should just commute the node.
8220 return DAG.getCommutedVectorShuffle(*SVOp);
8222 // Check for non-undef masks pointing at an undef vector and make the masks
8223 // undef as well. This makes it easier to match the shuffle based solely on
8227 if (M >= NumElements) {
8228 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
8229 for (int &M : NewMask)
8230 if (M >= NumElements)
8232 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
8235 // For integer vector shuffles, try to collapse them into a shuffle of fewer
8236 // lanes but wider integers. We cap this to not form integers larger than i64
8237 // but it might be interesting to form i128 integers to handle flipping the
8238 // low and high halves of AVX 256-bit vectors.
8239 if (VT.isInteger() && VT.getScalarSizeInBits() < 64 &&
8240 areAdjacentMasksSequential(Mask)) {
8241 SmallVector<int, 8> NewMask;
8242 for (int i = 0, Size = Mask.size(); i < Size; i += 2)
8243 NewMask.push_back(Mask[i] / 2);
8245 MVT::getVectorVT(MVT::getIntegerVT(VT.getScalarSizeInBits() * 2),
8246 VT.getVectorNumElements() / 2);
8247 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
8248 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
8249 return DAG.getNode(ISD::BITCAST, dl, VT,
8250 DAG.getVectorShuffle(NewVT, dl, V1, V2, NewMask));
8253 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
8254 for (int M : SVOp->getMask())
8257 else if (M < NumElements)
8262 // Commute the shuffle as needed such that more elements come from V1 than
8263 // V2. This allows us to match the shuffle pattern strictly on how many
8264 // elements come from V1 without handling the symmetric cases.
8265 if (NumV2Elements > NumV1Elements)
8266 return DAG.getCommutedVectorShuffle(*SVOp);
8268 // When the number of V1 and V2 elements are the same, try to minimize the
8269 // number of uses of V2 in the low half of the vector.
8270 if (NumV1Elements == NumV2Elements) {
8271 int LowV1Elements = 0, LowV2Elements = 0;
8272 for (int M : SVOp->getMask().slice(0, NumElements / 2))
8273 if (M >= NumElements)
8277 if (LowV2Elements > LowV1Elements)
8278 return DAG.getCommutedVectorShuffle(*SVOp);
8281 // For each vector width, delegate to a specialized lowering routine.
8282 if (VT.getSizeInBits() == 128)
8283 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
8285 llvm_unreachable("Unimplemented!");
8289 //===----------------------------------------------------------------------===//
8290 // Legacy vector shuffle lowering
8292 // This code is the legacy code handling vector shuffles until the above
8293 // replaces its functionality and performance.
8294 //===----------------------------------------------------------------------===//
8296 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
8297 bool hasInt256, unsigned *MaskOut = nullptr) {
8298 MVT EltVT = VT.getVectorElementType();
8300 // There is no blend with immediate in AVX-512.
8301 if (VT.is512BitVector())
8304 if (!hasSSE41 || EltVT == MVT::i8)
8306 if (!hasInt256 && VT == MVT::v16i16)
8309 unsigned MaskValue = 0;
8310 unsigned NumElems = VT.getVectorNumElements();
8311 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
8312 unsigned NumLanes = (NumElems - 1) / 8 + 1;
8313 unsigned NumElemsInLane = NumElems / NumLanes;
8315 // Blend for v16i16 should be symetric for the both lanes.
8316 for (unsigned i = 0; i < NumElemsInLane; ++i) {
8318 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
8319 int EltIdx = MaskVals[i];
8321 if ((EltIdx < 0 || EltIdx == (int)i) &&
8322 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
8325 if (((unsigned)EltIdx == (i + NumElems)) &&
8326 (SndLaneEltIdx < 0 ||
8327 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
8328 MaskValue |= (1 << i);
8334 *MaskOut = MaskValue;
8338 // Try to lower a shuffle node into a simple blend instruction.
8339 // This function assumes isBlendMask returns true for this
8340 // SuffleVectorSDNode
8341 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
8343 const X86Subtarget *Subtarget,
8344 SelectionDAG &DAG) {
8345 MVT VT = SVOp->getSimpleValueType(0);
8346 MVT EltVT = VT.getVectorElementType();
8347 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
8348 Subtarget->hasInt256() && "Trying to lower a "
8349 "VECTOR_SHUFFLE to a Blend but "
8350 "with the wrong mask"));
8351 SDValue V1 = SVOp->getOperand(0);
8352 SDValue V2 = SVOp->getOperand(1);
8354 unsigned NumElems = VT.getVectorNumElements();
8356 // Convert i32 vectors to floating point if it is not AVX2.
8357 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
8359 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
8360 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
8362 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
8363 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
8366 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
8367 DAG.getConstant(MaskValue, MVT::i32));
8368 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
8371 /// In vector type \p VT, return true if the element at index \p InputIdx
8372 /// falls on a different 128-bit lane than \p OutputIdx.
8373 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
8374 unsigned OutputIdx) {
8375 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
8376 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
8379 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
8380 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
8381 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
8382 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
8384 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
8385 SelectionDAG &DAG) {
8386 MVT VT = V1.getSimpleValueType();
8387 assert(VT.is128BitVector() || VT.is256BitVector());
8389 MVT EltVT = VT.getVectorElementType();
8390 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
8391 unsigned NumElts = VT.getVectorNumElements();
8393 SmallVector<SDValue, 32> PshufbMask;
8394 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
8395 int InputIdx = MaskVals[OutputIdx];
8396 unsigned InputByteIdx;
8398 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
8399 InputByteIdx = 0x80;
8401 // Cross lane is not allowed.
8402 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
8404 InputByteIdx = InputIdx * EltSizeInBytes;
8405 // Index is an byte offset within the 128-bit lane.
8406 InputByteIdx &= 0xf;
8409 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
8410 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
8411 if (InputByteIdx != 0x80)
8416 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
8418 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
8419 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
8420 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
8423 // v8i16 shuffles - Prefer shuffles in the following order:
8424 // 1. [all] pshuflw, pshufhw, optional move
8425 // 2. [ssse3] 1 x pshufb
8426 // 3. [ssse3] 2 x pshufb + 1 x por
8427 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
8429 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
8430 SelectionDAG &DAG) {
8431 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8432 SDValue V1 = SVOp->getOperand(0);
8433 SDValue V2 = SVOp->getOperand(1);
8435 SmallVector<int, 8> MaskVals;
8437 // Determine if more than 1 of the words in each of the low and high quadwords
8438 // of the result come from the same quadword of one of the two inputs. Undef
8439 // mask values count as coming from any quadword, for better codegen.
8441 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
8442 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
8443 unsigned LoQuad[] = { 0, 0, 0, 0 };
8444 unsigned HiQuad[] = { 0, 0, 0, 0 };
8445 // Indices of quads used.
8446 std::bitset<4> InputQuads;
8447 for (unsigned i = 0; i < 8; ++i) {
8448 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
8449 int EltIdx = SVOp->getMaskElt(i);
8450 MaskVals.push_back(EltIdx);
8459 InputQuads.set(EltIdx / 4);
8462 int BestLoQuad = -1;
8463 unsigned MaxQuad = 1;
8464 for (unsigned i = 0; i < 4; ++i) {
8465 if (LoQuad[i] > MaxQuad) {
8467 MaxQuad = LoQuad[i];
8471 int BestHiQuad = -1;
8473 for (unsigned i = 0; i < 4; ++i) {
8474 if (HiQuad[i] > MaxQuad) {
8476 MaxQuad = HiQuad[i];
8480 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
8481 // of the two input vectors, shuffle them into one input vector so only a
8482 // single pshufb instruction is necessary. If there are more than 2 input
8483 // quads, disable the next transformation since it does not help SSSE3.
8484 bool V1Used = InputQuads[0] || InputQuads[1];
8485 bool V2Used = InputQuads[2] || InputQuads[3];
8486 if (Subtarget->hasSSSE3()) {
8487 if (InputQuads.count() == 2 && V1Used && V2Used) {
8488 BestLoQuad = InputQuads[0] ? 0 : 1;
8489 BestHiQuad = InputQuads[2] ? 2 : 3;
8491 if (InputQuads.count() > 2) {
8497 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
8498 // the shuffle mask. If a quad is scored as -1, that means that it contains
8499 // words from all 4 input quadwords.
8501 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
8503 BestLoQuad < 0 ? 0 : BestLoQuad,
8504 BestHiQuad < 0 ? 1 : BestHiQuad
8506 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
8507 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
8508 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
8509 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
8511 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
8512 // source words for the shuffle, to aid later transformations.
8513 bool AllWordsInNewV = true;
8514 bool InOrder[2] = { true, true };
8515 for (unsigned i = 0; i != 8; ++i) {
8516 int idx = MaskVals[i];
8518 InOrder[i/4] = false;
8519 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
8521 AllWordsInNewV = false;
8525 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
8526 if (AllWordsInNewV) {
8527 for (int i = 0; i != 8; ++i) {
8528 int idx = MaskVals[i];
8531 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
8532 if ((idx != i) && idx < 4)
8534 if ((idx != i) && idx > 3)
8543 // If we've eliminated the use of V2, and the new mask is a pshuflw or
8544 // pshufhw, that's as cheap as it gets. Return the new shuffle.
8545 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
8546 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
8547 unsigned TargetMask = 0;
8548 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
8549 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
8550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8551 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
8552 getShufflePSHUFLWImmediate(SVOp);
8553 V1 = NewV.getOperand(0);
8554 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
8558 // Promote splats to a larger type which usually leads to more efficient code.
8559 // FIXME: Is this true if pshufb is available?
8560 if (SVOp->isSplat())
8561 return PromoteSplat(SVOp, DAG);
8563 // If we have SSSE3, and all words of the result are from 1 input vector,
8564 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
8565 // is present, fall back to case 4.
8566 if (Subtarget->hasSSSE3()) {
8567 SmallVector<SDValue,16> pshufbMask;
8569 // If we have elements from both input vectors, set the high bit of the
8570 // shuffle mask element to zero out elements that come from V2 in the V1
8571 // mask, and elements that come from V1 in the V2 mask, so that the two
8572 // results can be OR'd together.
8573 bool TwoInputs = V1Used && V2Used;
8574 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
8576 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8578 // Calculate the shuffle mask for the second input, shuffle it, and
8579 // OR it with the first shuffled input.
8580 CommuteVectorShuffleMask(MaskVals, 8);
8581 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
8582 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8583 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8586 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
8587 // and update MaskVals with new element order.
8588 std::bitset<8> InOrder;
8589 if (BestLoQuad >= 0) {
8590 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
8591 for (int i = 0; i != 4; ++i) {
8592 int idx = MaskVals[i];
8595 } else if ((idx / 4) == BestLoQuad) {
8600 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8603 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8604 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8605 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
8607 getShufflePSHUFLWImmediate(SVOp), DAG);
8611 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
8612 // and update MaskVals with the new element order.
8613 if (BestHiQuad >= 0) {
8614 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
8615 for (unsigned i = 4; i != 8; ++i) {
8616 int idx = MaskVals[i];
8619 } else if ((idx / 4) == BestHiQuad) {
8620 MaskV[i] = (idx & 3) + 4;
8624 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
8627 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
8628 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
8629 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
8631 getShufflePSHUFHWImmediate(SVOp), DAG);
8635 // In case BestHi & BestLo were both -1, which means each quadword has a word
8636 // from each of the four input quadwords, calculate the InOrder bitvector now
8637 // before falling through to the insert/extract cleanup.
8638 if (BestLoQuad == -1 && BestHiQuad == -1) {
8640 for (int i = 0; i != 8; ++i)
8641 if (MaskVals[i] < 0 || MaskVals[i] == i)
8645 // The other elements are put in the right place using pextrw and pinsrw.
8646 for (unsigned i = 0; i != 8; ++i) {
8649 int EltIdx = MaskVals[i];
8652 SDValue ExtOp = (EltIdx < 8) ?
8653 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
8654 DAG.getIntPtrConstant(EltIdx)) :
8655 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
8656 DAG.getIntPtrConstant(EltIdx - 8));
8657 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
8658 DAG.getIntPtrConstant(i));
8663 /// \brief v16i16 shuffles
8665 /// FIXME: We only support generation of a single pshufb currently. We can
8666 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
8667 /// well (e.g 2 x pshufb + 1 x por).
8669 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
8670 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8671 SDValue V1 = SVOp->getOperand(0);
8672 SDValue V2 = SVOp->getOperand(1);
8675 if (V2.getOpcode() != ISD::UNDEF)
8678 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8679 return getPSHUFB(MaskVals, V1, dl, DAG);
8682 // v16i8 shuffles - Prefer shuffles in the following order:
8683 // 1. [ssse3] 1 x pshufb
8684 // 2. [ssse3] 2 x pshufb + 1 x por
8685 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
8686 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
8687 const X86Subtarget* Subtarget,
8688 SelectionDAG &DAG) {
8689 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8690 SDValue V1 = SVOp->getOperand(0);
8691 SDValue V2 = SVOp->getOperand(1);
8693 ArrayRef<int> MaskVals = SVOp->getMask();
8695 // Promote splats to a larger type which usually leads to more efficient code.
8696 // FIXME: Is this true if pshufb is available?
8697 if (SVOp->isSplat())
8698 return PromoteSplat(SVOp, DAG);
8700 // If we have SSSE3, case 1 is generated when all result bytes come from
8701 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
8702 // present, fall back to case 3.
8704 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
8705 if (Subtarget->hasSSSE3()) {
8706 SmallVector<SDValue,16> pshufbMask;
8708 // If all result elements are from one input vector, then only translate
8709 // undef mask values to 0x80 (zero out result) in the pshufb mask.
8711 // Otherwise, we have elements from both input vectors, and must zero out
8712 // elements that come from V2 in the first mask, and V1 in the second mask
8713 // so that we can OR them together.
8714 for (unsigned i = 0; i != 16; ++i) {
8715 int EltIdx = MaskVals[i];
8716 if (EltIdx < 0 || EltIdx >= 16)
8718 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8720 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
8721 DAG.getNode(ISD::BUILD_VECTOR, dl,
8722 MVT::v16i8, pshufbMask));
8724 // As PSHUFB will zero elements with negative indices, it's safe to ignore
8725 // the 2nd operand if it's undefined or zero.
8726 if (V2.getOpcode() == ISD::UNDEF ||
8727 ISD::isBuildVectorAllZeros(V2.getNode()))
8730 // Calculate the shuffle mask for the second input, shuffle it, and
8731 // OR it with the first shuffled input.
8733 for (unsigned i = 0; i != 16; ++i) {
8734 int EltIdx = MaskVals[i];
8735 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
8736 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
8738 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
8739 DAG.getNode(ISD::BUILD_VECTOR, dl,
8740 MVT::v16i8, pshufbMask));
8741 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
8744 // No SSSE3 - Calculate in place words and then fix all out of place words
8745 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
8746 // the 16 different words that comprise the two doublequadword input vectors.
8747 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
8748 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
8750 for (int i = 0; i != 8; ++i) {
8751 int Elt0 = MaskVals[i*2];
8752 int Elt1 = MaskVals[i*2+1];
8754 // This word of the result is all undef, skip it.
8755 if (Elt0 < 0 && Elt1 < 0)
8758 // This word of the result is already in the correct place, skip it.
8759 if ((Elt0 == i*2) && (Elt1 == i*2+1))
8762 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
8763 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
8766 // If Elt0 and Elt1 are defined, are consecutive, and can be load
8767 // using a single extract together, load it and store it.
8768 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
8769 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8770 DAG.getIntPtrConstant(Elt1 / 2));
8771 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8772 DAG.getIntPtrConstant(i));
8776 // If Elt1 is defined, extract it from the appropriate source. If the
8777 // source byte is not also odd, shift the extracted word left 8 bits
8778 // otherwise clear the bottom 8 bits if we need to do an or.
8780 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
8781 DAG.getIntPtrConstant(Elt1 / 2));
8782 if ((Elt1 & 1) == 0)
8783 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
8785 TLI.getShiftAmountTy(InsElt.getValueType())));
8787 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
8788 DAG.getConstant(0xFF00, MVT::i16));
8790 // If Elt0 is defined, extract it from the appropriate source. If the
8791 // source byte is not also even, shift the extracted word right 8 bits. If
8792 // Elt1 was also defined, OR the extracted values together before
8793 // inserting them in the result.
8795 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
8796 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
8797 if ((Elt0 & 1) != 0)
8798 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
8800 TLI.getShiftAmountTy(InsElt0.getValueType())));
8802 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
8803 DAG.getConstant(0x00FF, MVT::i16));
8804 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
8807 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
8808 DAG.getIntPtrConstant(i));
8810 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
8813 // v32i8 shuffles - Translate to VPSHUFB if possible.
8815 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
8816 const X86Subtarget *Subtarget,
8817 SelectionDAG &DAG) {
8818 MVT VT = SVOp->getSimpleValueType(0);
8819 SDValue V1 = SVOp->getOperand(0);
8820 SDValue V2 = SVOp->getOperand(1);
8822 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
8824 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
8825 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
8826 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
8828 // VPSHUFB may be generated if
8829 // (1) one of input vector is undefined or zeroinitializer.
8830 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
8831 // And (2) the mask indexes don't cross the 128-bit lane.
8832 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
8833 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
8836 if (V1IsAllZero && !V2IsAllZero) {
8837 CommuteVectorShuffleMask(MaskVals, 32);
8840 return getPSHUFB(MaskVals, V1, dl, DAG);
8843 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
8844 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
8845 /// done when every pair / quad of shuffle mask elements point to elements in
8846 /// the right sequence. e.g.
8847 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
8849 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
8850 SelectionDAG &DAG) {
8851 MVT VT = SVOp->getSimpleValueType(0);
8853 unsigned NumElems = VT.getVectorNumElements();
8856 switch (VT.SimpleTy) {
8857 default: llvm_unreachable("Unexpected!");
8860 return SDValue(SVOp, 0);
8861 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
8862 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
8863 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
8864 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
8865 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
8866 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
8869 SmallVector<int, 8> MaskVec;
8870 for (unsigned i = 0; i != NumElems; i += Scale) {
8872 for (unsigned j = 0; j != Scale; ++j) {
8873 int EltIdx = SVOp->getMaskElt(i+j);
8877 StartIdx = (EltIdx / Scale);
8878 if (EltIdx != (int)(StartIdx*Scale + j))
8881 MaskVec.push_back(StartIdx);
8884 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
8885 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
8886 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
8889 /// getVZextMovL - Return a zero-extending vector move low node.
8891 static SDValue getVZextMovL(MVT VT, MVT OpVT,
8892 SDValue SrcOp, SelectionDAG &DAG,
8893 const X86Subtarget *Subtarget, SDLoc dl) {
8894 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
8895 LoadSDNode *LD = nullptr;
8896 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
8897 LD = dyn_cast<LoadSDNode>(SrcOp);
8899 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
8901 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
8902 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
8903 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
8904 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
8905 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
8907 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
8908 return DAG.getNode(ISD::BITCAST, dl, VT,
8909 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8910 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8918 return DAG.getNode(ISD::BITCAST, dl, VT,
8919 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
8920 DAG.getNode(ISD::BITCAST, dl,
8924 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
8925 /// which could not be matched by any known target speficic shuffle
8927 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
8929 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
8930 if (NewOp.getNode())
8933 MVT VT = SVOp->getSimpleValueType(0);
8935 unsigned NumElems = VT.getVectorNumElements();
8936 unsigned NumLaneElems = NumElems / 2;
8939 MVT EltVT = VT.getVectorElementType();
8940 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
8943 SmallVector<int, 16> Mask;
8944 for (unsigned l = 0; l < 2; ++l) {
8945 // Build a shuffle mask for the output, discovering on the fly which
8946 // input vectors to use as shuffle operands (recorded in InputUsed).
8947 // If building a suitable shuffle vector proves too hard, then bail
8948 // out with UseBuildVector set.
8949 bool UseBuildVector = false;
8950 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
8951 unsigned LaneStart = l * NumLaneElems;
8952 for (unsigned i = 0; i != NumLaneElems; ++i) {
8953 // The mask element. This indexes into the input.
8954 int Idx = SVOp->getMaskElt(i+LaneStart);
8956 // the mask element does not index into any input vector.
8961 // The input vector this mask element indexes into.
8962 int Input = Idx / NumLaneElems;
8964 // Turn the index into an offset from the start of the input vector.
8965 Idx -= Input * NumLaneElems;
8967 // Find or create a shuffle vector operand to hold this input.
8969 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
8970 if (InputUsed[OpNo] == Input)
8971 // This input vector is already an operand.
8973 if (InputUsed[OpNo] < 0) {
8974 // Create a new operand for this input vector.
8975 InputUsed[OpNo] = Input;
8980 if (OpNo >= array_lengthof(InputUsed)) {
8981 // More than two input vectors used! Give up on trying to create a
8982 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
8983 UseBuildVector = true;
8987 // Add the mask index for the new shuffle vector.
8988 Mask.push_back(Idx + OpNo * NumLaneElems);
8991 if (UseBuildVector) {
8992 SmallVector<SDValue, 16> SVOps;
8993 for (unsigned i = 0; i != NumLaneElems; ++i) {
8994 // The mask element. This indexes into the input.
8995 int Idx = SVOp->getMaskElt(i+LaneStart);
8997 SVOps.push_back(DAG.getUNDEF(EltVT));
9001 // The input vector this mask element indexes into.
9002 int Input = Idx / NumElems;
9004 // Turn the index into an offset from the start of the input vector.
9005 Idx -= Input * NumElems;
9007 // Extract the vector element by hand.
9008 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
9009 SVOp->getOperand(Input),
9010 DAG.getIntPtrConstant(Idx)));
9013 // Construct the output using a BUILD_VECTOR.
9014 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
9015 } else if (InputUsed[0] < 0) {
9016 // No input vectors were used! The result is undefined.
9017 Output[l] = DAG.getUNDEF(NVT);
9019 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
9020 (InputUsed[0] % 2) * NumLaneElems,
9022 // If only one input was used, use an undefined vector for the other.
9023 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
9024 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
9025 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
9026 // At least one input vector was used. Create a new shuffle vector.
9027 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
9033 // Concatenate the result back
9034 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
9037 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
9038 /// 4 elements, and match them with several different shuffle types.
9040 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
9041 SDValue V1 = SVOp->getOperand(0);
9042 SDValue V2 = SVOp->getOperand(1);
9044 MVT VT = SVOp->getSimpleValueType(0);
9046 assert(VT.is128BitVector() && "Unsupported vector size");
9048 std::pair<int, int> Locs[4];
9049 int Mask1[] = { -1, -1, -1, -1 };
9050 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
9054 for (unsigned i = 0; i != 4; ++i) {
9055 int Idx = PermMask[i];
9057 Locs[i] = std::make_pair(-1, -1);
9059 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
9061 Locs[i] = std::make_pair(0, NumLo);
9065 Locs[i] = std::make_pair(1, NumHi);
9067 Mask1[2+NumHi] = Idx;
9073 if (NumLo <= 2 && NumHi <= 2) {
9074 // If no more than two elements come from either vector. This can be
9075 // implemented with two shuffles. First shuffle gather the elements.
9076 // The second shuffle, which takes the first shuffle as both of its
9077 // vector operands, put the elements into the right order.
9078 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9080 int Mask2[] = { -1, -1, -1, -1 };
9082 for (unsigned i = 0; i != 4; ++i)
9083 if (Locs[i].first != -1) {
9084 unsigned Idx = (i < 2) ? 0 : 4;
9085 Idx += Locs[i].first * 2 + Locs[i].second;
9089 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
9092 if (NumLo == 3 || NumHi == 3) {
9093 // Otherwise, we must have three elements from one vector, call it X, and
9094 // one element from the other, call it Y. First, use a shufps to build an
9095 // intermediate vector with the one element from Y and the element from X
9096 // that will be in the same half in the final destination (the indexes don't
9097 // matter). Then, use a shufps to build the final vector, taking the half
9098 // containing the element from Y from the intermediate, and the other half
9101 // Normalize it so the 3 elements come from V1.
9102 CommuteVectorShuffleMask(PermMask, 4);
9106 // Find the element from V2.
9108 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
9109 int Val = PermMask[HiIndex];
9116 Mask1[0] = PermMask[HiIndex];
9118 Mask1[2] = PermMask[HiIndex^1];
9120 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9123 Mask1[0] = PermMask[0];
9124 Mask1[1] = PermMask[1];
9125 Mask1[2] = HiIndex & 1 ? 6 : 4;
9126 Mask1[3] = HiIndex & 1 ? 4 : 6;
9127 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
9130 Mask1[0] = HiIndex & 1 ? 2 : 0;
9131 Mask1[1] = HiIndex & 1 ? 0 : 2;
9132 Mask1[2] = PermMask[2];
9133 Mask1[3] = PermMask[3];
9138 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
9141 // Break it into (shuffle shuffle_hi, shuffle_lo).
9142 int LoMask[] = { -1, -1, -1, -1 };
9143 int HiMask[] = { -1, -1, -1, -1 };
9145 int *MaskPtr = LoMask;
9146 unsigned MaskIdx = 0;
9149 for (unsigned i = 0; i != 4; ++i) {
9156 int Idx = PermMask[i];
9158 Locs[i] = std::make_pair(-1, -1);
9159 } else if (Idx < 4) {
9160 Locs[i] = std::make_pair(MaskIdx, LoIdx);
9161 MaskPtr[LoIdx] = Idx;
9164 Locs[i] = std::make_pair(MaskIdx, HiIdx);
9165 MaskPtr[HiIdx] = Idx;
9170 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
9171 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
9172 int MaskOps[] = { -1, -1, -1, -1 };
9173 for (unsigned i = 0; i != 4; ++i)
9174 if (Locs[i].first != -1)
9175 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
9176 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
9179 static bool MayFoldVectorLoad(SDValue V) {
9180 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
9181 V = V.getOperand(0);
9183 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
9184 V = V.getOperand(0);
9185 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
9186 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
9187 // BUILD_VECTOR (load), undef
9188 V = V.getOperand(0);
9190 return MayFoldLoad(V);
9194 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
9195 MVT VT = Op.getSimpleValueType();
9197 // Canonizalize to v2f64.
9198 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
9199 return DAG.getNode(ISD::BITCAST, dl, VT,
9200 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
9205 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
9207 SDValue V1 = Op.getOperand(0);
9208 SDValue V2 = Op.getOperand(1);
9209 MVT VT = Op.getSimpleValueType();
9211 assert(VT != MVT::v2i64 && "unsupported shuffle type");
9213 if (HasSSE2 && VT == MVT::v2f64)
9214 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
9216 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
9217 return DAG.getNode(ISD::BITCAST, dl, VT,
9218 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
9219 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
9220 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
9224 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
9225 SDValue V1 = Op.getOperand(0);
9226 SDValue V2 = Op.getOperand(1);
9227 MVT VT = Op.getSimpleValueType();
9229 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
9230 "unsupported shuffle type");
9232 if (V2.getOpcode() == ISD::UNDEF)
9236 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
9240 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
9241 SDValue V1 = Op.getOperand(0);
9242 SDValue V2 = Op.getOperand(1);
9243 MVT VT = Op.getSimpleValueType();
9244 unsigned NumElems = VT.getVectorNumElements();
9246 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
9247 // operand of these instructions is only memory, so check if there's a
9248 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
9250 bool CanFoldLoad = false;
9252 // Trivial case, when V2 comes from a load.
9253 if (MayFoldVectorLoad(V2))
9256 // When V1 is a load, it can be folded later into a store in isel, example:
9257 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
9259 // (MOVLPSmr addr:$src1, VR128:$src2)
9260 // So, recognize this potential and also use MOVLPS or MOVLPD
9261 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
9264 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9266 if (HasSSE2 && NumElems == 2)
9267 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
9270 // If we don't care about the second element, proceed to use movss.
9271 if (SVOp->getMaskElt(1) != -1)
9272 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
9275 // movl and movlp will both match v2i64, but v2i64 is never matched by
9276 // movl earlier because we make it strict to avoid messing with the movlp load
9277 // folding logic (see the code above getMOVLP call). Match it here then,
9278 // this is horrible, but will stay like this until we move all shuffle
9279 // matching to x86 specific nodes. Note that for the 1st condition all
9280 // types are matched with movsd.
9282 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
9283 // as to remove this logic from here, as much as possible
9284 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
9285 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9286 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9289 assert(VT != MVT::v4i32 && "unsupported shuffle type");
9291 // Invert the operand order and use SHUFPS to match it.
9292 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
9293 getShuffleSHUFImmediate(SVOp), DAG);
9296 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
9297 SelectionDAG &DAG) {
9299 MVT VT = Load->getSimpleValueType(0);
9300 MVT EVT = VT.getVectorElementType();
9301 SDValue Addr = Load->getOperand(1);
9302 SDValue NewAddr = DAG.getNode(
9303 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
9304 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
9307 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
9308 DAG.getMachineFunction().getMachineMemOperand(
9309 Load->getMemOperand(), 0, EVT.getStoreSize()));
9313 // It is only safe to call this function if isINSERTPSMask is true for
9314 // this shufflevector mask.
9315 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
9316 SelectionDAG &DAG) {
9317 // Generate an insertps instruction when inserting an f32 from memory onto a
9318 // v4f32 or when copying a member from one v4f32 to another.
9319 // We also use it for transferring i32 from one register to another,
9320 // since it simply copies the same bits.
9321 // If we're transferring an i32 from memory to a specific element in a
9322 // register, we output a generic DAG that will match the PINSRD
9324 MVT VT = SVOp->getSimpleValueType(0);
9325 MVT EVT = VT.getVectorElementType();
9326 SDValue V1 = SVOp->getOperand(0);
9327 SDValue V2 = SVOp->getOperand(1);
9328 auto Mask = SVOp->getMask();
9329 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
9330 "unsupported vector type for insertps/pinsrd");
9332 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
9333 auto FromV2Predicate = [](const int &i) { return i >= 4; };
9334 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
9342 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
9345 // If we have 1 element from each vector, we have to check if we're
9346 // changing V1's element's place. If so, we're done. Otherwise, we
9347 // should assume we're changing V2's element's place and behave
9349 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
9350 assert(DestIndex <= INT32_MAX && "truncated destination index");
9351 if (FromV1 == FromV2 &&
9352 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
9356 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9359 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
9360 "More than one element from V1 and from V2, or no elements from one "
9361 "of the vectors. This case should not have returned true from "
9366 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
9369 // Get an index into the source vector in the range [0,4) (the mask is
9370 // in the range [0,8) because it can address V1 and V2)
9371 unsigned SrcIndex = Mask[DestIndex] % 4;
9372 if (MayFoldLoad(From)) {
9373 // Trivial case, when From comes from a load and is only used by the
9374 // shuffle. Make it use insertps from the vector that we need from that
9377 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
9378 if (!NewLoad.getNode())
9381 if (EVT == MVT::f32) {
9382 // Create this as a scalar to vector to match the instruction pattern.
9383 SDValue LoadScalarToVector =
9384 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
9385 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
9386 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
9388 } else { // EVT == MVT::i32
9389 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
9390 // instruction, to match the PINSRD instruction, which loads an i32 to a
9391 // certain vector element.
9392 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
9393 DAG.getConstant(DestIndex, MVT::i32));
9397 // Vector-element-to-vector
9398 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
9399 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
9402 // Reduce a vector shuffle to zext.
9403 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
9404 SelectionDAG &DAG) {
9405 // PMOVZX is only available from SSE41.
9406 if (!Subtarget->hasSSE41())
9409 MVT VT = Op.getSimpleValueType();
9411 // Only AVX2 support 256-bit vector integer extending.
9412 if (!Subtarget->hasInt256() && VT.is256BitVector())
9415 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9417 SDValue V1 = Op.getOperand(0);
9418 SDValue V2 = Op.getOperand(1);
9419 unsigned NumElems = VT.getVectorNumElements();
9421 // Extending is an unary operation and the element type of the source vector
9422 // won't be equal to or larger than i64.
9423 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
9424 VT.getVectorElementType() == MVT::i64)
9427 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
9428 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
9429 while ((1U << Shift) < NumElems) {
9430 if (SVOp->getMaskElt(1U << Shift) == 1)
9433 // The maximal ratio is 8, i.e. from i8 to i64.
9438 // Check the shuffle mask.
9439 unsigned Mask = (1U << Shift) - 1;
9440 for (unsigned i = 0; i != NumElems; ++i) {
9441 int EltIdx = SVOp->getMaskElt(i);
9442 if ((i & Mask) != 0 && EltIdx != -1)
9444 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
9448 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
9449 MVT NeVT = MVT::getIntegerVT(NBits);
9450 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
9452 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
9455 // Simplify the operand as it's prepared to be fed into shuffle.
9456 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
9457 if (V1.getOpcode() == ISD::BITCAST &&
9458 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
9459 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
9460 V1.getOperand(0).getOperand(0)
9461 .getSimpleValueType().getSizeInBits() == SignificantBits) {
9462 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
9463 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
9464 ConstantSDNode *CIdx =
9465 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
9466 // If it's foldable, i.e. normal load with single use, we will let code
9467 // selection to fold it. Otherwise, we will short the conversion sequence.
9468 if (CIdx && CIdx->getZExtValue() == 0 &&
9469 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
9470 MVT FullVT = V.getSimpleValueType();
9471 MVT V1VT = V1.getSimpleValueType();
9472 if (FullVT.getSizeInBits() > V1VT.getSizeInBits()) {
9473 // The "ext_vec_elt" node is wider than the result node.
9474 // In this case we should extract subvector from V.
9475 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
9476 unsigned Ratio = FullVT.getSizeInBits() / V1VT.getSizeInBits();
9477 MVT SubVecVT = MVT::getVectorVT(FullVT.getVectorElementType(),
9478 FullVT.getVectorNumElements()/Ratio);
9479 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
9480 DAG.getIntPtrConstant(0));
9482 V1 = DAG.getNode(ISD::BITCAST, DL, V1VT, V);
9486 return DAG.getNode(ISD::BITCAST, DL, VT,
9487 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
9490 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
9491 SelectionDAG &DAG) {
9492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9493 MVT VT = Op.getSimpleValueType();
9495 SDValue V1 = Op.getOperand(0);
9496 SDValue V2 = Op.getOperand(1);
9498 if (isZeroShuffle(SVOp))
9499 return getZeroVector(VT, Subtarget, DAG, dl);
9501 // Handle splat operations
9502 if (SVOp->isSplat()) {
9503 // Use vbroadcast whenever the splat comes from a foldable load
9504 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
9505 if (Broadcast.getNode())
9509 // Check integer expanding shuffles.
9510 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
9511 if (NewOp.getNode())
9514 // If the shuffle can be profitably rewritten as a narrower shuffle, then
9516 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
9518 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9519 if (NewOp.getNode())
9520 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
9521 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
9522 // FIXME: Figure out a cleaner way to do this.
9523 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
9524 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9525 if (NewOp.getNode()) {
9526 MVT NewVT = NewOp.getSimpleValueType();
9527 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
9528 NewVT, true, false))
9529 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
9532 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
9533 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
9534 if (NewOp.getNode()) {
9535 MVT NewVT = NewOp.getSimpleValueType();
9536 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
9537 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
9546 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
9547 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9548 SDValue V1 = Op.getOperand(0);
9549 SDValue V2 = Op.getOperand(1);
9550 MVT VT = Op.getSimpleValueType();
9552 unsigned NumElems = VT.getVectorNumElements();
9553 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
9554 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
9555 bool V1IsSplat = false;
9556 bool V2IsSplat = false;
9557 bool HasSSE2 = Subtarget->hasSSE2();
9558 bool HasFp256 = Subtarget->hasFp256();
9559 bool HasInt256 = Subtarget->hasInt256();
9560 MachineFunction &MF = DAG.getMachineFunction();
9561 bool OptForSize = MF.getFunction()->getAttributes().
9562 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
9564 // Check if we should use the experimental vector shuffle lowering. If so,
9565 // delegate completely to that code path.
9566 if (ExperimentalVectorShuffleLowering)
9567 return lowerVectorShuffle(Op, Subtarget, DAG);
9569 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
9571 if (V1IsUndef && V2IsUndef)
9572 return DAG.getUNDEF(VT);
9574 // When we create a shuffle node we put the UNDEF node to second operand,
9575 // but in some cases the first operand may be transformed to UNDEF.
9576 // In this case we should just commute the node.
9578 return DAG.getCommutedVectorShuffle(*SVOp);
9580 // Vector shuffle lowering takes 3 steps:
9582 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
9583 // narrowing and commutation of operands should be handled.
9584 // 2) Matching of shuffles with known shuffle masks to x86 target specific
9586 // 3) Rewriting of unmatched masks into new generic shuffle operations,
9587 // so the shuffle can be broken into other shuffles and the legalizer can
9588 // try the lowering again.
9590 // The general idea is that no vector_shuffle operation should be left to
9591 // be matched during isel, all of them must be converted to a target specific
9594 // Normalize the input vectors. Here splats, zeroed vectors, profitable
9595 // narrowing and commutation of operands should be handled. The actual code
9596 // doesn't include all of those, work in progress...
9597 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
9598 if (NewOp.getNode())
9601 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
9603 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
9604 // unpckh_undef). Only use pshufd if speed is more important than size.
9605 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9606 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9607 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9608 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9610 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
9611 V2IsUndef && MayFoldVectorLoad(V1))
9612 return getMOVDDup(Op, dl, V1, DAG);
9614 if (isMOVHLPS_v_undef_Mask(M, VT))
9615 return getMOVHighToLow(Op, dl, DAG);
9617 // Use to match splats
9618 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
9619 (VT == MVT::v2f64 || VT == MVT::v2i64))
9620 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9622 if (isPSHUFDMask(M, VT)) {
9623 // The actual implementation will match the mask in the if above and then
9624 // during isel it can match several different instructions, not only pshufd
9625 // as its name says, sad but true, emulate the behavior for now...
9626 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
9627 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
9629 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
9631 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
9632 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
9634 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
9635 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
9638 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
9642 if (isPALIGNRMask(M, VT, Subtarget))
9643 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
9644 getShufflePALIGNRImmediate(SVOp),
9647 if (isVALIGNMask(M, VT, Subtarget))
9648 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
9649 getShuffleVALIGNImmediate(SVOp),
9652 // Check if this can be converted into a logical shift.
9653 bool isLeft = false;
9656 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
9657 if (isShift && ShVal.hasOneUse()) {
9658 // If the shifted value has multiple uses, it may be cheaper to use
9659 // v_set0 + movlhps or movhlps, etc.
9660 MVT EltVT = VT.getVectorElementType();
9661 ShAmt *= EltVT.getSizeInBits();
9662 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9665 if (isMOVLMask(M, VT)) {
9666 if (ISD::isBuildVectorAllZeros(V1.getNode()))
9667 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
9668 if (!isMOVLPMask(M, VT)) {
9669 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
9670 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
9672 if (VT == MVT::v4i32 || VT == MVT::v4f32)
9673 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
9677 // FIXME: fold these into legal mask.
9678 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
9679 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
9681 if (isMOVHLPSMask(M, VT))
9682 return getMOVHighToLow(Op, dl, DAG);
9684 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
9685 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
9687 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
9688 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
9690 if (isMOVLPMask(M, VT))
9691 return getMOVLP(Op, dl, DAG, HasSSE2);
9693 if (ShouldXformToMOVHLPS(M, VT) ||
9694 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
9695 return DAG.getCommutedVectorShuffle(*SVOp);
9698 // No better options. Use a vshldq / vsrldq.
9699 MVT EltVT = VT.getVectorElementType();
9700 ShAmt *= EltVT.getSizeInBits();
9701 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
9704 bool Commuted = false;
9705 // FIXME: This should also accept a bitcast of a splat? Be careful, not
9706 // 1,1,1,1 -> v8i16 though.
9707 BitVector UndefElements;
9708 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
9709 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9711 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
9712 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
9715 // Canonicalize the splat or undef, if present, to be on the RHS.
9716 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
9717 CommuteVectorShuffleMask(M, NumElems);
9719 std::swap(V1IsSplat, V2IsSplat);
9723 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
9724 // Shuffling low element of v1 into undef, just return v1.
9727 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
9728 // the instruction selector will not match, so get a canonical MOVL with
9729 // swapped operands to undo the commute.
9730 return getMOVL(DAG, dl, VT, V2, V1);
9733 if (isUNPCKLMask(M, VT, HasInt256))
9734 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9736 if (isUNPCKHMask(M, VT, HasInt256))
9737 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9740 // Normalize mask so all entries that point to V2 points to its first
9741 // element then try to match unpck{h|l} again. If match, return a
9742 // new vector_shuffle with the corrected mask.p
9743 SmallVector<int, 8> NewMask(M.begin(), M.end());
9744 NormalizeMask(NewMask, NumElems);
9745 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
9746 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9747 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
9748 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9752 // Commute is back and try unpck* again.
9753 // FIXME: this seems wrong.
9754 CommuteVectorShuffleMask(M, NumElems);
9756 std::swap(V1IsSplat, V2IsSplat);
9758 if (isUNPCKLMask(M, VT, HasInt256))
9759 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
9761 if (isUNPCKHMask(M, VT, HasInt256))
9762 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
9765 // Normalize the node to match x86 shuffle ops if needed
9766 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
9767 return DAG.getCommutedVectorShuffle(*SVOp);
9769 // The checks below are all present in isShuffleMaskLegal, but they are
9770 // inlined here right now to enable us to directly emit target specific
9771 // nodes, and remove one by one until they don't return Op anymore.
9773 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
9774 SVOp->getSplatIndex() == 0 && V2IsUndef) {
9775 if (VT == MVT::v2f64 || VT == MVT::v2i64)
9776 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9779 if (isPSHUFHWMask(M, VT, HasInt256))
9780 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
9781 getShufflePSHUFHWImmediate(SVOp),
9784 if (isPSHUFLWMask(M, VT, HasInt256))
9785 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
9786 getShufflePSHUFLWImmediate(SVOp),
9790 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
9792 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
9794 if (isSHUFPMask(M, VT))
9795 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
9796 getShuffleSHUFImmediate(SVOp), DAG);
9798 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
9799 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
9800 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
9801 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
9803 //===--------------------------------------------------------------------===//
9804 // Generate target specific nodes for 128 or 256-bit shuffles only
9805 // supported in the AVX instruction set.
9808 // Handle VMOVDDUPY permutations
9809 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
9810 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
9812 // Handle VPERMILPS/D* permutations
9813 if (isVPERMILPMask(M, VT)) {
9814 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
9815 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
9816 getShuffleSHUFImmediate(SVOp), DAG);
9817 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
9818 getShuffleSHUFImmediate(SVOp), DAG);
9822 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
9823 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
9824 Idx*(NumElems/2), DAG, dl);
9826 // Handle VPERM2F128/VPERM2I128 permutations
9827 if (isVPERM2X128Mask(M, VT, HasFp256))
9828 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
9829 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
9831 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
9832 return getINSERTPS(SVOp, dl, DAG);
9835 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
9836 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
9838 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
9839 VT.is512BitVector()) {
9840 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
9841 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
9842 SmallVector<SDValue, 16> permclMask;
9843 for (unsigned i = 0; i != NumElems; ++i) {
9844 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
9847 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
9849 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
9850 return DAG.getNode(X86ISD::VPERMV, dl, VT,
9851 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
9852 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
9853 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
9856 //===--------------------------------------------------------------------===//
9857 // Since no target specific shuffle was selected for this generic one,
9858 // lower it into other known shuffles. FIXME: this isn't true yet, but
9859 // this is the plan.
9862 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
9863 if (VT == MVT::v8i16) {
9864 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
9865 if (NewOp.getNode())
9869 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
9870 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
9871 if (NewOp.getNode())
9875 if (VT == MVT::v16i8) {
9876 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
9877 if (NewOp.getNode())
9881 if (VT == MVT::v32i8) {
9882 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
9883 if (NewOp.getNode())
9887 // Handle all 128-bit wide vectors with 4 elements, and match them with
9888 // several different shuffle types.
9889 if (NumElems == 4 && VT.is128BitVector())
9890 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
9892 // Handle general 256-bit shuffles
9893 if (VT.is256BitVector())
9894 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
9899 // This function assumes its argument is a BUILD_VECTOR of constants or
9900 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
9902 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
9903 unsigned &MaskValue) {
9905 unsigned NumElems = BuildVector->getNumOperands();
9906 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
9907 unsigned NumLanes = (NumElems - 1) / 8 + 1;
9908 unsigned NumElemsInLane = NumElems / NumLanes;
9910 // Blend for v16i16 should be symetric for the both lanes.
9911 for (unsigned i = 0; i < NumElemsInLane; ++i) {
9912 SDValue EltCond = BuildVector->getOperand(i);
9913 SDValue SndLaneEltCond =
9914 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
9916 int Lane1Cond = -1, Lane2Cond = -1;
9917 if (isa<ConstantSDNode>(EltCond))
9918 Lane1Cond = !isZero(EltCond);
9919 if (isa<ConstantSDNode>(SndLaneEltCond))
9920 Lane2Cond = !isZero(SndLaneEltCond);
9922 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
9923 // Lane1Cond != 0, means we want the first argument.
9924 // Lane1Cond == 0, means we want the second argument.
9925 // The encoding of this argument is 0 for the first argument, 1
9926 // for the second. Therefore, invert the condition.
9927 MaskValue |= !Lane1Cond << i;
9928 else if (Lane1Cond < 0)
9929 MaskValue |= !Lane2Cond << i;
9936 // Try to lower a vselect node into a simple blend instruction.
9937 static SDValue LowerVSELECTtoBlend(SDValue Op, const X86Subtarget *Subtarget,
9938 SelectionDAG &DAG) {
9939 SDValue Cond = Op.getOperand(0);
9940 SDValue LHS = Op.getOperand(1);
9941 SDValue RHS = Op.getOperand(2);
9943 MVT VT = Op.getSimpleValueType();
9944 MVT EltVT = VT.getVectorElementType();
9945 unsigned NumElems = VT.getVectorNumElements();
9947 // There is no blend with immediate in AVX-512.
9948 if (VT.is512BitVector())
9951 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
9953 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
9956 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
9959 // Check the mask for BLEND and build the value.
9960 unsigned MaskValue = 0;
9961 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
9964 // Convert i32 vectors to floating point if it is not AVX2.
9965 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
9967 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
9968 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
9970 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
9971 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
9974 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
9975 DAG.getConstant(MaskValue, MVT::i32));
9976 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
9979 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
9980 SDValue BlendOp = LowerVSELECTtoBlend(Op, Subtarget, DAG);
9981 if (BlendOp.getNode())
9984 // Some types for vselect were previously set to Expand, not Legal or
9985 // Custom. Return an empty SDValue so we fall-through to Expand, after
9986 // the Custom lowering phase.
9987 MVT VT = Op.getSimpleValueType();
9988 switch (VT.SimpleTy) {
9996 // We couldn't create a "Blend with immediate" node.
9997 // This node should still be legal, but we'll have to emit a blendv*
10002 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10003 MVT VT = Op.getSimpleValueType();
10006 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10009 if (VT.getSizeInBits() == 8) {
10010 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10011 Op.getOperand(0), Op.getOperand(1));
10012 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10013 DAG.getValueType(VT));
10014 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10017 if (VT.getSizeInBits() == 16) {
10018 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10019 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10021 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10022 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10023 DAG.getNode(ISD::BITCAST, dl,
10026 Op.getOperand(1)));
10027 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10028 Op.getOperand(0), Op.getOperand(1));
10029 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10030 DAG.getValueType(VT));
10031 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10034 if (VT == MVT::f32) {
10035 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10036 // the result back to FR32 register. It's only worth matching if the
10037 // result has a single use which is a store or a bitcast to i32. And in
10038 // the case of a store, it's not worth it if the index is a constant 0,
10039 // because a MOVSSmr can be used instead, which is smaller and faster.
10040 if (!Op.hasOneUse())
10042 SDNode *User = *Op.getNode()->use_begin();
10043 if ((User->getOpcode() != ISD::STORE ||
10044 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10045 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10046 (User->getOpcode() != ISD::BITCAST ||
10047 User->getValueType(0) != MVT::i32))
10049 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10050 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
10053 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
10056 if (VT == MVT::i32 || VT == MVT::i64) {
10057 // ExtractPS/pextrq works with constant index.
10058 if (isa<ConstantSDNode>(Op.getOperand(1)))
10064 /// Extract one bit from mask vector, like v16i1 or v8i1.
10065 /// AVX-512 feature.
10067 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10068 SDValue Vec = Op.getOperand(0);
10070 MVT VecVT = Vec.getSimpleValueType();
10071 SDValue Idx = Op.getOperand(1);
10072 MVT EltVT = Op.getSimpleValueType();
10074 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10076 // variable index can't be handled in mask registers,
10077 // extend vector to VR512
10078 if (!isa<ConstantSDNode>(Idx)) {
10079 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10080 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10081 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10082 ExtVT.getVectorElementType(), Ext, Idx);
10083 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10086 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10087 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10088 unsigned MaxSift = rc->getSize()*8 - 1;
10089 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10090 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10091 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10092 DAG.getConstant(MaxSift, MVT::i8));
10093 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10094 DAG.getIntPtrConstant(0));
10098 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10099 SelectionDAG &DAG) const {
10101 SDValue Vec = Op.getOperand(0);
10102 MVT VecVT = Vec.getSimpleValueType();
10103 SDValue Idx = Op.getOperand(1);
10105 if (Op.getSimpleValueType() == MVT::i1)
10106 return ExtractBitFromMaskVector(Op, DAG);
10108 if (!isa<ConstantSDNode>(Idx)) {
10109 if (VecVT.is512BitVector() ||
10110 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10111 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10114 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10115 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10116 MaskEltVT.getSizeInBits());
10118 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10119 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10120 getZeroVector(MaskVT, Subtarget, DAG, dl),
10121 Idx, DAG.getConstant(0, getPointerTy()));
10122 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10123 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10124 Perm, DAG.getConstant(0, getPointerTy()));
10129 // If this is a 256-bit vector result, first extract the 128-bit vector and
10130 // then extract the element from the 128-bit vector.
10131 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10133 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10134 // Get the 128-bit vector.
10135 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10136 MVT EltVT = VecVT.getVectorElementType();
10138 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10140 //if (IdxVal >= NumElems/2)
10141 // IdxVal -= NumElems/2;
10142 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10143 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10144 DAG.getConstant(IdxVal, MVT::i32));
10147 assert(VecVT.is128BitVector() && "Unexpected vector length");
10149 if (Subtarget->hasSSE41()) {
10150 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
10155 MVT VT = Op.getSimpleValueType();
10156 // TODO: handle v16i8.
10157 if (VT.getSizeInBits() == 16) {
10158 SDValue Vec = Op.getOperand(0);
10159 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10161 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10162 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10163 DAG.getNode(ISD::BITCAST, dl,
10165 Op.getOperand(1)));
10166 // Transform it so it match pextrw which produces a 32-bit result.
10167 MVT EltVT = MVT::i32;
10168 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10169 Op.getOperand(0), Op.getOperand(1));
10170 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10171 DAG.getValueType(VT));
10172 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10175 if (VT.getSizeInBits() == 32) {
10176 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10180 // SHUFPS the element to the lowest double word, then movss.
10181 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10182 MVT VVT = Op.getOperand(0).getSimpleValueType();
10183 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10184 DAG.getUNDEF(VVT), Mask);
10185 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10186 DAG.getIntPtrConstant(0));
10189 if (VT.getSizeInBits() == 64) {
10190 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10191 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10192 // to match extract_elt for f64.
10193 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10197 // UNPCKHPD the element to the lowest double word, then movsd.
10198 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10199 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10200 int Mask[2] = { 1, -1 };
10201 MVT VVT = Op.getOperand(0).getSimpleValueType();
10202 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10203 DAG.getUNDEF(VVT), Mask);
10204 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10205 DAG.getIntPtrConstant(0));
10211 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10212 MVT VT = Op.getSimpleValueType();
10213 MVT EltVT = VT.getVectorElementType();
10216 SDValue N0 = Op.getOperand(0);
10217 SDValue N1 = Op.getOperand(1);
10218 SDValue N2 = Op.getOperand(2);
10220 if (!VT.is128BitVector())
10223 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
10224 isa<ConstantSDNode>(N2)) {
10226 if (VT == MVT::v8i16)
10227 Opc = X86ISD::PINSRW;
10228 else if (VT == MVT::v16i8)
10229 Opc = X86ISD::PINSRB;
10231 Opc = X86ISD::PINSRB;
10233 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10235 if (N1.getValueType() != MVT::i32)
10236 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10237 if (N2.getValueType() != MVT::i32)
10238 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10239 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10242 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
10243 // Bits [7:6] of the constant are the source select. This will always be
10244 // zero here. The DAG Combiner may combine an extract_elt index into these
10245 // bits. For example (insert (extract, 3), 2) could be matched by putting
10246 // the '3' into bits [7:6] of X86ISD::INSERTPS.
10247 // Bits [5:4] of the constant are the destination select. This is the
10248 // value of the incoming immediate.
10249 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10250 // combine either bitwise AND or insert of float 0.0 to set these bits.
10251 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
10252 // Create this as a scalar to vector..
10253 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10254 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10257 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
10258 // PINSR* works with constant index.
10264 /// Insert one bit to mask vector, like v16i1 or v8i1.
10265 /// AVX-512 feature.
10267 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10269 SDValue Vec = Op.getOperand(0);
10270 SDValue Elt = Op.getOperand(1);
10271 SDValue Idx = Op.getOperand(2);
10272 MVT VecVT = Vec.getSimpleValueType();
10274 if (!isa<ConstantSDNode>(Idx)) {
10275 // Non constant index. Extend source and destination,
10276 // insert element and then truncate the result.
10277 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10278 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10279 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10280 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10281 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10282 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10285 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10286 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10287 if (Vec.getOpcode() == ISD::UNDEF)
10288 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10289 DAG.getConstant(IdxVal, MVT::i8));
10290 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10291 unsigned MaxSift = rc->getSize()*8 - 1;
10292 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10293 DAG.getConstant(MaxSift, MVT::i8));
10294 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
10295 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
10296 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10299 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
10300 MVT VT = Op.getSimpleValueType();
10301 MVT EltVT = VT.getVectorElementType();
10303 if (EltVT == MVT::i1)
10304 return InsertBitToMaskVector(Op, DAG);
10307 SDValue N0 = Op.getOperand(0);
10308 SDValue N1 = Op.getOperand(1);
10309 SDValue N2 = Op.getOperand(2);
10311 // If this is a 256-bit vector result, first extract the 128-bit vector,
10312 // insert the element into the extracted half and then place it back.
10313 if (VT.is256BitVector() || VT.is512BitVector()) {
10314 if (!isa<ConstantSDNode>(N2))
10317 // Get the desired 128-bit vector half.
10318 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
10319 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10321 // Insert the element into the desired half.
10322 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
10323 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
10325 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10326 DAG.getConstant(IdxIn128, MVT::i32));
10328 // Insert the changed part back to the 256-bit vector
10329 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10332 if (Subtarget->hasSSE41())
10333 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
10335 if (EltVT == MVT::i8)
10338 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
10339 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10340 // as its second argument.
10341 if (N1.getValueType() != MVT::i32)
10342 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10343 if (N2.getValueType() != MVT::i32)
10344 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
10345 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10350 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10352 MVT OpVT = Op.getSimpleValueType();
10354 // If this is a 256-bit vector result, first insert into a 128-bit
10355 // vector and then insert into the 256-bit vector.
10356 if (!OpVT.is128BitVector()) {
10357 // Insert into a 128-bit vector.
10358 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10359 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10360 OpVT.getVectorNumElements() / SizeFactor);
10362 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10364 // Insert the 128-bit vector.
10365 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10368 if (OpVT == MVT::v1i64 &&
10369 Op.getOperand(0).getValueType() == MVT::i64)
10370 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10372 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10373 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10374 return DAG.getNode(ISD::BITCAST, dl, OpVT,
10375 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
10378 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10379 // a simple subregister reference or explicit instructions to grab
10380 // upper bits of a vector.
10381 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10382 SelectionDAG &DAG) {
10384 SDValue In = Op.getOperand(0);
10385 SDValue Idx = Op.getOperand(1);
10386 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10387 MVT ResVT = Op.getSimpleValueType();
10388 MVT InVT = In.getSimpleValueType();
10390 if (Subtarget->hasFp256()) {
10391 if (ResVT.is128BitVector() &&
10392 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10393 isa<ConstantSDNode>(Idx)) {
10394 return Extract128BitVector(In, IdxVal, DAG, dl);
10396 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10397 isa<ConstantSDNode>(Idx)) {
10398 return Extract256BitVector(In, IdxVal, DAG, dl);
10404 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10405 // simple superregister reference or explicit instructions to insert
10406 // the upper bits of a vector.
10407 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10408 SelectionDAG &DAG) {
10409 if (Subtarget->hasFp256()) {
10410 SDLoc dl(Op.getNode());
10411 SDValue Vec = Op.getNode()->getOperand(0);
10412 SDValue SubVec = Op.getNode()->getOperand(1);
10413 SDValue Idx = Op.getNode()->getOperand(2);
10415 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
10416 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
10417 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
10418 isa<ConstantSDNode>(Idx)) {
10419 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10420 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10423 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
10424 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
10425 isa<ConstantSDNode>(Idx)) {
10426 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10427 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10433 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10434 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10435 // one of the above mentioned nodes. It has to be wrapped because otherwise
10436 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10437 // be used to form addressing mode. These wrapped nodes will be selected
10440 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10441 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10443 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10444 // global base reg.
10445 unsigned char OpFlag = 0;
10446 unsigned WrapperKind = X86ISD::Wrapper;
10447 CodeModel::Model M = DAG.getTarget().getCodeModel();
10449 if (Subtarget->isPICStyleRIPRel() &&
10450 (M == CodeModel::Small || M == CodeModel::Kernel))
10451 WrapperKind = X86ISD::WrapperRIP;
10452 else if (Subtarget->isPICStyleGOT())
10453 OpFlag = X86II::MO_GOTOFF;
10454 else if (Subtarget->isPICStyleStubPIC())
10455 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10457 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
10458 CP->getAlignment(),
10459 CP->getOffset(), OpFlag);
10461 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10462 // With PIC, the address is actually $g + Offset.
10464 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10465 DAG.getNode(X86ISD::GlobalBaseReg,
10466 SDLoc(), getPointerTy()),
10473 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
10474 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
10476 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10477 // global base reg.
10478 unsigned char OpFlag = 0;
10479 unsigned WrapperKind = X86ISD::Wrapper;
10480 CodeModel::Model M = DAG.getTarget().getCodeModel();
10482 if (Subtarget->isPICStyleRIPRel() &&
10483 (M == CodeModel::Small || M == CodeModel::Kernel))
10484 WrapperKind = X86ISD::WrapperRIP;
10485 else if (Subtarget->isPICStyleGOT())
10486 OpFlag = X86II::MO_GOTOFF;
10487 else if (Subtarget->isPICStyleStubPIC())
10488 OpFlag = X86II::MO_PIC_BASE_OFFSET;
10490 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
10493 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10495 // With PIC, the address is actually $g + Offset.
10497 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10498 DAG.getNode(X86ISD::GlobalBaseReg,
10499 SDLoc(), getPointerTy()),
10506 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
10507 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
10509 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10510 // global base reg.
10511 unsigned char OpFlag = 0;
10512 unsigned WrapperKind = X86ISD::Wrapper;
10513 CodeModel::Model M = DAG.getTarget().getCodeModel();
10515 if (Subtarget->isPICStyleRIPRel() &&
10516 (M == CodeModel::Small || M == CodeModel::Kernel)) {
10517 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
10518 OpFlag = X86II::MO_GOTPCREL;
10519 WrapperKind = X86ISD::WrapperRIP;
10520 } else if (Subtarget->isPICStyleGOT()) {
10521 OpFlag = X86II::MO_GOT;
10522 } else if (Subtarget->isPICStyleStubPIC()) {
10523 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
10524 } else if (Subtarget->isPICStyleStubNoDynamic()) {
10525 OpFlag = X86II::MO_DARWIN_NONLAZY;
10528 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
10531 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10533 // With PIC, the address is actually $g + Offset.
10534 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
10535 !Subtarget->is64Bit()) {
10536 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10537 DAG.getNode(X86ISD::GlobalBaseReg,
10538 SDLoc(), getPointerTy()),
10542 // For symbols that require a load from a stub to get the address, emit the
10544 if (isGlobalStubReference(OpFlag))
10545 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
10546 MachinePointerInfo::getGOT(), false, false, false, 0);
10552 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
10553 // Create the TargetBlockAddressAddress node.
10554 unsigned char OpFlags =
10555 Subtarget->ClassifyBlockAddressReference();
10556 CodeModel::Model M = DAG.getTarget().getCodeModel();
10557 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
10558 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
10560 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
10563 if (Subtarget->isPICStyleRIPRel() &&
10564 (M == CodeModel::Small || M == CodeModel::Kernel))
10565 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10567 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10569 // With PIC, the address is actually $g + Offset.
10570 if (isGlobalRelativeToPICBase(OpFlags)) {
10571 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10572 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10580 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
10581 int64_t Offset, SelectionDAG &DAG) const {
10582 // Create the TargetGlobalAddress node, folding in the constant
10583 // offset if it is legal.
10584 unsigned char OpFlags =
10585 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
10586 CodeModel::Model M = DAG.getTarget().getCodeModel();
10588 if (OpFlags == X86II::MO_NO_FLAG &&
10589 X86::isOffsetSuitableForCodeModel(Offset, M)) {
10590 // A direct static reference to a global.
10591 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
10594 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
10597 if (Subtarget->isPICStyleRIPRel() &&
10598 (M == CodeModel::Small || M == CodeModel::Kernel))
10599 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
10601 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
10603 // With PIC, the address is actually $g + Offset.
10604 if (isGlobalRelativeToPICBase(OpFlags)) {
10605 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
10606 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
10610 // For globals that require a load from a stub to get the address, emit the
10612 if (isGlobalStubReference(OpFlags))
10613 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
10614 MachinePointerInfo::getGOT(), false, false, false, 0);
10616 // If there was a non-zero offset that we didn't fold, create an explicit
10617 // addition for it.
10619 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
10620 DAG.getConstant(Offset, getPointerTy()));
10626 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
10627 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
10628 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
10629 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
10633 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
10634 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
10635 unsigned char OperandFlags, bool LocalDynamic = false) {
10636 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10637 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10639 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10640 GA->getValueType(0),
10644 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
10648 SDValue Ops[] = { Chain, TGA, *InFlag };
10649 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10651 SDValue Ops[] = { Chain, TGA };
10652 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
10655 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
10656 MFI->setAdjustsStack(true);
10658 SDValue Flag = Chain.getValue(1);
10659 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
10662 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
10664 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10667 SDLoc dl(GA); // ? function entry point might be better
10668 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10669 DAG.getNode(X86ISD::GlobalBaseReg,
10670 SDLoc(), PtrVT), InFlag);
10671 InFlag = Chain.getValue(1);
10673 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
10676 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
10678 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10680 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
10681 X86::RAX, X86II::MO_TLSGD);
10684 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
10690 // Get the start address of the TLS block for this module.
10691 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
10692 .getInfo<X86MachineFunctionInfo>();
10693 MFI->incNumLocalDynamicTLSAccesses();
10697 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
10698 X86II::MO_TLSLD, /*LocalDynamic=*/true);
10701 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
10702 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
10703 InFlag = Chain.getValue(1);
10704 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
10705 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
10708 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
10712 unsigned char OperandFlags = X86II::MO_DTPOFF;
10713 unsigned WrapperKind = X86ISD::Wrapper;
10714 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10715 GA->getValueType(0),
10716 GA->getOffset(), OperandFlags);
10717 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10719 // Add x@dtpoff with the base.
10720 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
10723 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
10724 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
10725 const EVT PtrVT, TLSModel::Model model,
10726 bool is64Bit, bool isPIC) {
10729 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
10730 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
10731 is64Bit ? 257 : 256));
10733 SDValue ThreadPointer =
10734 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
10735 MachinePointerInfo(Ptr), false, false, false, 0);
10737 unsigned char OperandFlags = 0;
10738 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
10740 unsigned WrapperKind = X86ISD::Wrapper;
10741 if (model == TLSModel::LocalExec) {
10742 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
10743 } else if (model == TLSModel::InitialExec) {
10745 OperandFlags = X86II::MO_GOTTPOFF;
10746 WrapperKind = X86ISD::WrapperRIP;
10748 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
10751 llvm_unreachable("Unexpected model");
10754 // emit "addl x@ntpoff,%eax" (local exec)
10755 // or "addl x@indntpoff,%eax" (initial exec)
10756 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
10758 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
10759 GA->getOffset(), OperandFlags);
10760 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
10762 if (model == TLSModel::InitialExec) {
10763 if (isPIC && !is64Bit) {
10764 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
10765 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
10769 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
10770 MachinePointerInfo::getGOT(), false, false, false, 0);
10773 // The address of the thread local variable is the add of the thread
10774 // pointer with the offset of the variable.
10775 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
10779 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
10781 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
10782 const GlobalValue *GV = GA->getGlobal();
10784 if (Subtarget->isTargetELF()) {
10785 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
10788 case TLSModel::GeneralDynamic:
10789 if (Subtarget->is64Bit())
10790 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
10791 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
10792 case TLSModel::LocalDynamic:
10793 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
10794 Subtarget->is64Bit());
10795 case TLSModel::InitialExec:
10796 case TLSModel::LocalExec:
10797 return LowerToTLSExecModel(
10798 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
10799 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
10801 llvm_unreachable("Unknown TLS model.");
10804 if (Subtarget->isTargetDarwin()) {
10805 // Darwin only has one model of TLS. Lower to that.
10806 unsigned char OpFlag = 0;
10807 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
10808 X86ISD::WrapperRIP : X86ISD::Wrapper;
10810 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10811 // global base reg.
10812 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
10813 !Subtarget->is64Bit();
10815 OpFlag = X86II::MO_TLVP_PIC_BASE;
10817 OpFlag = X86II::MO_TLVP;
10819 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
10820 GA->getValueType(0),
10821 GA->getOffset(), OpFlag);
10822 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
10824 // With PIC32, the address is actually $g + Offset.
10826 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10827 DAG.getNode(X86ISD::GlobalBaseReg,
10828 SDLoc(), getPointerTy()),
10831 // Lowering the machine isd will make sure everything is in the right
10833 SDValue Chain = DAG.getEntryNode();
10834 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10835 SDValue Args[] = { Chain, Offset };
10836 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
10838 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
10839 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10840 MFI->setAdjustsStack(true);
10842 // And our return value (tls address) is in the standard call return value
10844 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
10845 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
10846 Chain.getValue(1));
10849 if (Subtarget->isTargetKnownWindowsMSVC() ||
10850 Subtarget->isTargetWindowsGNU()) {
10851 // Just use the implicit TLS architecture
10852 // Need to generate someting similar to:
10853 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
10855 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
10856 // mov rcx, qword [rdx+rcx*8]
10857 // mov eax, .tls$:tlsvar
10858 // [rax+rcx] contains the address
10859 // Windows 64bit: gs:0x58
10860 // Windows 32bit: fs:__tls_array
10863 SDValue Chain = DAG.getEntryNode();
10865 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
10866 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
10867 // use its literal value of 0x2C.
10868 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
10869 ? Type::getInt8PtrTy(*DAG.getContext(),
10871 : Type::getInt32PtrTy(*DAG.getContext(),
10875 Subtarget->is64Bit()
10876 ? DAG.getIntPtrConstant(0x58)
10877 : (Subtarget->isTargetWindowsGNU()
10878 ? DAG.getIntPtrConstant(0x2C)
10879 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
10881 SDValue ThreadPointer =
10882 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
10883 MachinePointerInfo(Ptr), false, false, false, 0);
10885 // Load the _tls_index variable
10886 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
10887 if (Subtarget->is64Bit())
10888 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
10889 IDX, MachinePointerInfo(), MVT::i32,
10890 false, false, false, 0);
10892 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
10893 false, false, false, 0);
10895 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
10897 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
10899 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
10900 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
10901 false, false, false, 0);
10903 // Get the offset of start of .tls section
10904 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
10905 GA->getValueType(0),
10906 GA->getOffset(), X86II::MO_SECREL);
10907 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
10909 // The address of the thread local variable is the add of the thread
10910 // pointer with the offset of the variable.
10911 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
10914 llvm_unreachable("TLS not implemented for this target.");
10917 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
10918 /// and take a 2 x i32 value to shift plus a shift amount.
10919 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
10920 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
10921 MVT VT = Op.getSimpleValueType();
10922 unsigned VTBits = VT.getSizeInBits();
10924 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
10925 SDValue ShOpLo = Op.getOperand(0);
10926 SDValue ShOpHi = Op.getOperand(1);
10927 SDValue ShAmt = Op.getOperand(2);
10928 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
10929 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
10931 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10932 DAG.getConstant(VTBits - 1, MVT::i8));
10933 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
10934 DAG.getConstant(VTBits - 1, MVT::i8))
10935 : DAG.getConstant(0, VT);
10937 SDValue Tmp2, Tmp3;
10938 if (Op.getOpcode() == ISD::SHL_PARTS) {
10939 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
10940 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
10942 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
10943 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
10946 // If the shift amount is larger or equal than the width of a part we can't
10947 // rely on the results of shld/shrd. Insert a test and select the appropriate
10948 // values for large shift amounts.
10949 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
10950 DAG.getConstant(VTBits, MVT::i8));
10951 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10952 AndNode, DAG.getConstant(0, MVT::i8));
10955 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10956 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
10957 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
10959 if (Op.getOpcode() == ISD::SHL_PARTS) {
10960 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10961 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10963 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
10964 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
10967 SDValue Ops[2] = { Lo, Hi };
10968 return DAG.getMergeValues(Ops, dl);
10971 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
10972 SelectionDAG &DAG) const {
10973 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
10975 if (SrcVT.isVector())
10978 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
10979 "Unknown SINT_TO_FP to lower!");
10981 // These are really Legal; return the operand so the caller accepts it as
10983 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
10985 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
10986 Subtarget->is64Bit()) {
10991 unsigned Size = SrcVT.getSizeInBits()/8;
10992 MachineFunction &MF = DAG.getMachineFunction();
10993 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
10994 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
10995 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
10997 MachinePointerInfo::getFixedStack(SSFI),
10999 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11002 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11004 SelectionDAG &DAG) const {
11008 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11010 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11012 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11014 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11016 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11017 MachineMemOperand *MMO;
11019 int SSFI = FI->getIndex();
11021 DAG.getMachineFunction()
11022 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11023 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11025 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11026 StackSlot = StackSlot.getOperand(1);
11028 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11029 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11031 Tys, Ops, SrcVT, MMO);
11034 Chain = Result.getValue(1);
11035 SDValue InFlag = Result.getValue(2);
11037 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11038 // shouldn't be necessary except that RFP cannot be live across
11039 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11040 MachineFunction &MF = DAG.getMachineFunction();
11041 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11042 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11043 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11044 Tys = DAG.getVTList(MVT::Other);
11046 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11048 MachineMemOperand *MMO =
11049 DAG.getMachineFunction()
11050 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11051 MachineMemOperand::MOStore, SSFISize, SSFISize);
11053 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11054 Ops, Op.getValueType(), MMO);
11055 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11056 MachinePointerInfo::getFixedStack(SSFI),
11057 false, false, false, 0);
11063 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11064 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11065 SelectionDAG &DAG) const {
11066 // This algorithm is not obvious. Here it is what we're trying to output:
11069 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11070 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11072 haddpd %xmm0, %xmm0
11074 pshufd $0x4e, %xmm0, %xmm1
11080 LLVMContext *Context = DAG.getContext();
11082 // Build some magic constants.
11083 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11084 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11085 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11087 SmallVector<Constant*,2> CV1;
11089 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11090 APInt(64, 0x4330000000000000ULL))));
11092 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11093 APInt(64, 0x4530000000000000ULL))));
11094 Constant *C1 = ConstantVector::get(CV1);
11095 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11097 // Load the 64-bit value into an XMM register.
11098 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11100 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11101 MachinePointerInfo::getConstantPool(),
11102 false, false, false, 16);
11103 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
11104 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
11107 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11108 MachinePointerInfo::getConstantPool(),
11109 false, false, false, 16);
11110 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
11111 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11114 if (Subtarget->hasSSE3()) {
11115 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11116 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11118 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
11119 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11121 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11122 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
11126 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11127 DAG.getIntPtrConstant(0));
11130 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11131 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11132 SelectionDAG &DAG) const {
11134 // FP constant to bias correct the final result.
11135 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
11138 // Load the 32-bit value into an XMM register.
11139 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11142 // Zero out the upper parts of the register.
11143 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11145 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11146 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
11147 DAG.getIntPtrConstant(0));
11149 // Or the load with the bias.
11150 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
11151 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11152 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11153 MVT::v2f64, Load)),
11154 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
11155 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11156 MVT::v2f64, Bias)));
11157 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11158 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
11159 DAG.getIntPtrConstant(0));
11161 // Subtract the bias.
11162 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11164 // Handle final rounding.
11165 EVT DestVT = Op.getValueType();
11167 if (DestVT.bitsLT(MVT::f64))
11168 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11169 DAG.getIntPtrConstant(0));
11170 if (DestVT.bitsGT(MVT::f64))
11171 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11173 // Handle final rounding.
11177 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11178 SelectionDAG &DAG) const {
11179 SDValue N0 = Op.getOperand(0);
11180 MVT SVT = N0.getSimpleValueType();
11183 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
11184 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
11185 "Custom UINT_TO_FP is not supported!");
11187 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11188 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11189 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11192 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11193 SelectionDAG &DAG) const {
11194 SDValue N0 = Op.getOperand(0);
11197 if (Op.getValueType().isVector())
11198 return lowerUINT_TO_FP_vec(Op, DAG);
11200 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11201 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11202 // the optimization here.
11203 if (DAG.SignBitIsZero(N0))
11204 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11206 MVT SrcVT = N0.getSimpleValueType();
11207 MVT DstVT = Op.getSimpleValueType();
11208 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11209 return LowerUINT_TO_FP_i64(Op, DAG);
11210 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11211 return LowerUINT_TO_FP_i32(Op, DAG);
11212 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11215 // Make a 64-bit buffer, and use it to build an FILD.
11216 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11217 if (SrcVT == MVT::i32) {
11218 SDValue WordOff = DAG.getConstant(4, getPointerTy());
11219 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11220 getPointerTy(), StackSlot, WordOff);
11221 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11222 StackSlot, MachinePointerInfo(),
11224 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
11225 OffsetSlot, MachinePointerInfo(),
11227 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11231 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11232 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11233 StackSlot, MachinePointerInfo(),
11235 // For i64 source, we need to add the appropriate power of 2 if the input
11236 // was negative. This is the same as the optimization in
11237 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11238 // we must be careful to do the computation in x87 extended precision, not
11239 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11240 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11241 MachineMemOperand *MMO =
11242 DAG.getMachineFunction()
11243 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11244 MachineMemOperand::MOLoad, 8, 8);
11246 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11247 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11248 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11251 APInt FF(32, 0x5F800000ULL);
11253 // Check whether the sign bit is set.
11254 SDValue SignSet = DAG.getSetCC(dl,
11255 getSetCCResultType(*DAG.getContext(), MVT::i64),
11256 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
11259 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11260 SDValue FudgePtr = DAG.getConstantPool(
11261 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11264 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11265 SDValue Zero = DAG.getIntPtrConstant(0);
11266 SDValue Four = DAG.getIntPtrConstant(4);
11267 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11269 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11271 // Load the value out, extending it from f32 to f80.
11272 // FIXME: Avoid the extend by constructing the right constant pool?
11273 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11274 FudgePtr, MachinePointerInfo::getConstantPool(),
11275 MVT::f32, false, false, false, 4);
11276 // Extend everything to 80 bits to force it to be done on x87.
11277 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11278 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
11281 std::pair<SDValue,SDValue>
11282 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11283 bool IsSigned, bool IsReplace) const {
11286 EVT DstTy = Op.getValueType();
11288 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11289 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11293 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11294 DstTy.getSimpleVT() >= MVT::i16 &&
11295 "Unknown FP_TO_INT to lower!");
11297 // These are really Legal.
11298 if (DstTy == MVT::i32 &&
11299 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11300 return std::make_pair(SDValue(), SDValue());
11301 if (Subtarget->is64Bit() &&
11302 DstTy == MVT::i64 &&
11303 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11304 return std::make_pair(SDValue(), SDValue());
11306 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11307 // stack slot, or into the FTOL runtime function.
11308 MachineFunction &MF = DAG.getMachineFunction();
11309 unsigned MemSize = DstTy.getSizeInBits()/8;
11310 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11311 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11314 if (!IsSigned && isIntegerTypeFTOL(DstTy))
11315 Opc = X86ISD::WIN_FTOL;
11317 switch (DstTy.getSimpleVT().SimpleTy) {
11318 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
11319 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
11320 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
11321 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
11324 SDValue Chain = DAG.getEntryNode();
11325 SDValue Value = Op.getOperand(0);
11326 EVT TheVT = Op.getOperand(0).getValueType();
11327 // FIXME This causes a redundant load/store if the SSE-class value is already
11328 // in memory, such as if it is on the callstack.
11329 if (isScalarFPTypeInSSEReg(TheVT)) {
11330 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
11331 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
11332 MachinePointerInfo::getFixedStack(SSFI),
11334 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
11336 Chain, StackSlot, DAG.getValueType(TheVT)
11339 MachineMemOperand *MMO =
11340 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11341 MachineMemOperand::MOLoad, MemSize, MemSize);
11342 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
11343 Chain = Value.getValue(1);
11344 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
11345 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11348 MachineMemOperand *MMO =
11349 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11350 MachineMemOperand::MOStore, MemSize, MemSize);
11352 if (Opc != X86ISD::WIN_FTOL) {
11353 // Build the FP_TO_INT*_IN_MEM
11354 SDValue Ops[] = { Chain, Value, StackSlot };
11355 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
11357 return std::make_pair(FIST, StackSlot);
11359 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
11360 DAG.getVTList(MVT::Other, MVT::Glue),
11362 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
11363 MVT::i32, ftol.getValue(1));
11364 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
11365 MVT::i32, eax.getValue(2));
11366 SDValue Ops[] = { eax, edx };
11367 SDValue pair = IsReplace
11368 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
11369 : DAG.getMergeValues(Ops, DL);
11370 return std::make_pair(pair, SDValue());
11374 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
11375 const X86Subtarget *Subtarget) {
11376 MVT VT = Op->getSimpleValueType(0);
11377 SDValue In = Op->getOperand(0);
11378 MVT InVT = In.getSimpleValueType();
11381 // Optimize vectors in AVX mode:
11384 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
11385 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
11386 // Concat upper and lower parts.
11389 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
11390 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
11391 // Concat upper and lower parts.
11394 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
11395 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
11396 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
11399 if (Subtarget->hasInt256())
11400 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
11402 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
11403 SDValue Undef = DAG.getUNDEF(InVT);
11404 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
11405 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11406 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
11408 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
11409 VT.getVectorNumElements()/2);
11411 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
11412 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
11414 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
11417 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
11418 SelectionDAG &DAG) {
11419 MVT VT = Op->getSimpleValueType(0);
11420 SDValue In = Op->getOperand(0);
11421 MVT InVT = In.getSimpleValueType();
11423 unsigned int NumElts = VT.getVectorNumElements();
11424 if (NumElts != 8 && NumElts != 16)
11427 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
11428 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
11430 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
11431 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11432 // Now we have only mask extension
11433 assert(InVT.getVectorElementType() == MVT::i1);
11434 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
11435 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11436 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
11437 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11438 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11439 MachinePointerInfo::getConstantPool(),
11440 false, false, false, Alignment);
11442 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
11443 if (VT.is512BitVector())
11445 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
11448 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11449 SelectionDAG &DAG) {
11450 if (Subtarget->hasFp256()) {
11451 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11459 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
11460 SelectionDAG &DAG) {
11462 MVT VT = Op.getSimpleValueType();
11463 SDValue In = Op.getOperand(0);
11464 MVT SVT = In.getSimpleValueType();
11466 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
11467 return LowerZERO_EXTEND_AVX512(Op, DAG);
11469 if (Subtarget->hasFp256()) {
11470 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
11475 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
11476 VT.getVectorNumElements() != SVT.getVectorNumElements());
11480 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
11482 MVT VT = Op.getSimpleValueType();
11483 SDValue In = Op.getOperand(0);
11484 MVT InVT = In.getSimpleValueType();
11486 if (VT == MVT::i1) {
11487 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
11488 "Invalid scalar TRUNCATE operation");
11489 if (InVT == MVT::i32)
11491 if (InVT.getSizeInBits() == 64)
11492 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::i32, In);
11493 else if (InVT.getSizeInBits() < 32)
11494 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
11495 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
11497 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
11498 "Invalid TRUNCATE operation");
11500 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
11501 if (VT.getVectorElementType().getSizeInBits() >=8)
11502 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
11504 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
11505 unsigned NumElts = InVT.getVectorNumElements();
11506 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
11507 if (InVT.getSizeInBits() < 512) {
11508 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
11509 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
11513 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
11514 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
11515 SDValue CP = DAG.getConstantPool(C, getPointerTy());
11516 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
11517 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
11518 MachinePointerInfo::getConstantPool(),
11519 false, false, false, Alignment);
11520 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
11521 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
11522 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
11525 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
11526 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
11527 if (Subtarget->hasInt256()) {
11528 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
11529 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
11530 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
11532 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
11533 DAG.getIntPtrConstant(0));
11536 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11537 DAG.getIntPtrConstant(0));
11538 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11539 DAG.getIntPtrConstant(2));
11540 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11541 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11542 static const int ShufMask[] = {0, 2, 4, 6};
11543 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
11546 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
11547 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
11548 if (Subtarget->hasInt256()) {
11549 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
11551 SmallVector<SDValue,32> pshufbMask;
11552 for (unsigned i = 0; i < 2; ++i) {
11553 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
11554 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
11555 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
11556 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
11557 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
11558 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
11559 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
11560 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
11561 for (unsigned j = 0; j < 8; ++j)
11562 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
11564 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
11565 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
11566 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
11568 static const int ShufMask[] = {0, 2, -1, -1};
11569 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
11571 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
11572 DAG.getIntPtrConstant(0));
11573 return DAG.getNode(ISD::BITCAST, DL, VT, In);
11576 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11577 DAG.getIntPtrConstant(0));
11579 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
11580 DAG.getIntPtrConstant(4));
11582 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
11583 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
11585 // The PSHUFB mask:
11586 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
11587 -1, -1, -1, -1, -1, -1, -1, -1};
11589 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
11590 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
11591 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
11593 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
11594 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
11596 // The MOVLHPS Mask:
11597 static const int ShufMask2[] = {0, 1, 4, 5};
11598 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
11599 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
11602 // Handle truncation of V256 to V128 using shuffles.
11603 if (!VT.is128BitVector() || !InVT.is256BitVector())
11606 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
11608 unsigned NumElems = VT.getVectorNumElements();
11609 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
11611 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
11612 // Prepare truncation shuffle mask
11613 for (unsigned i = 0; i != NumElems; ++i)
11614 MaskVec[i] = i * 2;
11615 SDValue V = DAG.getVectorShuffle(NVT, DL,
11616 DAG.getNode(ISD::BITCAST, DL, NVT, In),
11617 DAG.getUNDEF(NVT), &MaskVec[0]);
11618 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
11619 DAG.getIntPtrConstant(0));
11622 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
11623 SelectionDAG &DAG) const {
11624 assert(!Op.getSimpleValueType().isVector());
11626 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11627 /*IsSigned=*/ true, /*IsReplace=*/ false);
11628 SDValue FIST = Vals.first, StackSlot = Vals.second;
11629 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
11630 if (!FIST.getNode()) return Op;
11632 if (StackSlot.getNode())
11633 // Load the result.
11634 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11635 FIST, StackSlot, MachinePointerInfo(),
11636 false, false, false, 0);
11638 // The node is the result.
11642 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
11643 SelectionDAG &DAG) const {
11644 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
11645 /*IsSigned=*/ false, /*IsReplace=*/ false);
11646 SDValue FIST = Vals.first, StackSlot = Vals.second;
11647 assert(FIST.getNode() && "Unexpected failure");
11649 if (StackSlot.getNode())
11650 // Load the result.
11651 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
11652 FIST, StackSlot, MachinePointerInfo(),
11653 false, false, false, 0);
11655 // The node is the result.
11659 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
11661 MVT VT = Op.getSimpleValueType();
11662 SDValue In = Op.getOperand(0);
11663 MVT SVT = In.getSimpleValueType();
11665 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
11667 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
11668 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
11669 In, DAG.getUNDEF(SVT)));
11672 static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) {
11673 LLVMContext *Context = DAG.getContext();
11675 MVT VT = Op.getSimpleValueType();
11677 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11678 if (VT.isVector()) {
11679 EltVT = VT.getVectorElementType();
11680 NumElts = VT.getVectorNumElements();
11683 if (EltVT == MVT::f64)
11684 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11685 APInt(64, ~(1ULL << 63))));
11687 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11688 APInt(32, ~(1U << 31))));
11689 C = ConstantVector::getSplat(NumElts, C);
11690 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11691 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11692 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11693 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11694 MachinePointerInfo::getConstantPool(),
11695 false, false, false, Alignment);
11696 if (VT.isVector()) {
11697 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11698 return DAG.getNode(ISD::BITCAST, dl, VT,
11699 DAG.getNode(ISD::AND, dl, ANDVT,
11700 DAG.getNode(ISD::BITCAST, dl, ANDVT,
11702 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
11704 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
11707 static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) {
11708 LLVMContext *Context = DAG.getContext();
11710 MVT VT = Op.getSimpleValueType();
11712 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
11713 if (VT.isVector()) {
11714 EltVT = VT.getVectorElementType();
11715 NumElts = VT.getVectorNumElements();
11718 if (EltVT == MVT::f64)
11719 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11720 APInt(64, 1ULL << 63)));
11722 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
11723 APInt(32, 1U << 31)));
11724 C = ConstantVector::getSplat(NumElts, C);
11725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11726 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
11727 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11728 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11729 MachinePointerInfo::getConstantPool(),
11730 false, false, false, Alignment);
11731 if (VT.isVector()) {
11732 MVT XORVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits()/64);
11733 return DAG.getNode(ISD::BITCAST, dl, VT,
11734 DAG.getNode(ISD::XOR, dl, XORVT,
11735 DAG.getNode(ISD::BITCAST, dl, XORVT,
11737 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
11740 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
11743 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
11744 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11745 LLVMContext *Context = DAG.getContext();
11746 SDValue Op0 = Op.getOperand(0);
11747 SDValue Op1 = Op.getOperand(1);
11749 MVT VT = Op.getSimpleValueType();
11750 MVT SrcVT = Op1.getSimpleValueType();
11752 // If second operand is smaller, extend it first.
11753 if (SrcVT.bitsLT(VT)) {
11754 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
11757 // And if it is bigger, shrink it first.
11758 if (SrcVT.bitsGT(VT)) {
11759 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
11763 // At this point the operands and the result should have the same
11764 // type, and that won't be f80 since that is not custom lowered.
11766 // First get the sign bit of second operand.
11767 SmallVector<Constant*,4> CV;
11768 if (SrcVT == MVT::f64) {
11769 const fltSemantics &Sem = APFloat::IEEEdouble;
11770 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
11771 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11773 const fltSemantics &Sem = APFloat::IEEEsingle;
11774 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
11775 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11776 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11777 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11779 Constant *C = ConstantVector::get(CV);
11780 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11781 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
11782 MachinePointerInfo::getConstantPool(),
11783 false, false, false, 16);
11784 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
11786 // Shift sign bit right or left if the two operands have different types.
11787 if (SrcVT.bitsGT(VT)) {
11788 // Op0 is MVT::f32, Op1 is MVT::f64.
11789 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
11790 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
11791 DAG.getConstant(32, MVT::i32));
11792 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
11793 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
11794 DAG.getIntPtrConstant(0));
11797 // Clear first operand sign bit.
11799 if (VT == MVT::f64) {
11800 const fltSemantics &Sem = APFloat::IEEEdouble;
11801 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11802 APInt(64, ~(1ULL << 63)))));
11803 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
11805 const fltSemantics &Sem = APFloat::IEEEsingle;
11806 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
11807 APInt(32, ~(1U << 31)))));
11808 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11809 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11810 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
11812 C = ConstantVector::get(CV);
11813 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
11814 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11815 MachinePointerInfo::getConstantPool(),
11816 false, false, false, 16);
11817 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
11819 // Or the value with the sign bit.
11820 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
11823 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
11824 SDValue N0 = Op.getOperand(0);
11826 MVT VT = Op.getSimpleValueType();
11828 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
11829 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
11830 DAG.getConstant(1, VT));
11831 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
11834 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
11836 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
11837 SelectionDAG &DAG) {
11838 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
11840 if (!Subtarget->hasSSE41())
11843 if (!Op->hasOneUse())
11846 SDNode *N = Op.getNode();
11849 SmallVector<SDValue, 8> Opnds;
11850 DenseMap<SDValue, unsigned> VecInMap;
11851 SmallVector<SDValue, 8> VecIns;
11852 EVT VT = MVT::Other;
11854 // Recognize a special case where a vector is casted into wide integer to
11856 Opnds.push_back(N->getOperand(0));
11857 Opnds.push_back(N->getOperand(1));
11859 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
11860 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
11861 // BFS traverse all OR'd operands.
11862 if (I->getOpcode() == ISD::OR) {
11863 Opnds.push_back(I->getOperand(0));
11864 Opnds.push_back(I->getOperand(1));
11865 // Re-evaluate the number of nodes to be traversed.
11866 e += 2; // 2 more nodes (LHS and RHS) are pushed.
11870 // Quit if a non-EXTRACT_VECTOR_ELT
11871 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
11874 // Quit if without a constant index.
11875 SDValue Idx = I->getOperand(1);
11876 if (!isa<ConstantSDNode>(Idx))
11879 SDValue ExtractedFromVec = I->getOperand(0);
11880 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
11881 if (M == VecInMap.end()) {
11882 VT = ExtractedFromVec.getValueType();
11883 // Quit if not 128/256-bit vector.
11884 if (!VT.is128BitVector() && !VT.is256BitVector())
11886 // Quit if not the same type.
11887 if (VecInMap.begin() != VecInMap.end() &&
11888 VT != VecInMap.begin()->first.getValueType())
11890 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
11891 VecIns.push_back(ExtractedFromVec);
11893 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
11896 assert((VT.is128BitVector() || VT.is256BitVector()) &&
11897 "Not extracted from 128-/256-bit vector.");
11899 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
11901 for (DenseMap<SDValue, unsigned>::const_iterator
11902 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
11903 // Quit if not all elements are used.
11904 if (I->second != FullMask)
11908 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
11910 // Cast all vectors into TestVT for PTEST.
11911 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
11912 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
11914 // If more than one full vectors are evaluated, OR them first before PTEST.
11915 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
11916 // Each iteration will OR 2 nodes and append the result until there is only
11917 // 1 node left, i.e. the final OR'd value of all vectors.
11918 SDValue LHS = VecIns[Slot];
11919 SDValue RHS = VecIns[Slot + 1];
11920 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
11923 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
11924 VecIns.back(), VecIns.back());
11927 /// \brief return true if \c Op has a use that doesn't just read flags.
11928 static bool hasNonFlagsUse(SDValue Op) {
11929 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
11931 SDNode *User = *UI;
11932 unsigned UOpNo = UI.getOperandNo();
11933 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
11934 // Look pass truncate.
11935 UOpNo = User->use_begin().getOperandNo();
11936 User = *User->use_begin();
11939 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
11940 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
11946 /// Emit nodes that will be selected as "test Op0,Op0", or something
11948 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
11949 SelectionDAG &DAG) const {
11950 if (Op.getValueType() == MVT::i1)
11951 // KORTEST instruction should be selected
11952 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11953 DAG.getConstant(0, Op.getValueType()));
11955 // CF and OF aren't always set the way we want. Determine which
11956 // of these we need.
11957 bool NeedCF = false;
11958 bool NeedOF = false;
11961 case X86::COND_A: case X86::COND_AE:
11962 case X86::COND_B: case X86::COND_BE:
11965 case X86::COND_G: case X86::COND_GE:
11966 case X86::COND_L: case X86::COND_LE:
11967 case X86::COND_O: case X86::COND_NO: {
11968 // Check if we really need to set the
11969 // Overflow flag. If NoSignedWrap is present
11970 // that is not actually needed.
11971 switch (Op->getOpcode()) {
11976 const BinaryWithFlagsSDNode *BinNode =
11977 cast<BinaryWithFlagsSDNode>(Op.getNode());
11978 if (BinNode->hasNoSignedWrap())
11988 // See if we can use the EFLAGS value from the operand instead of
11989 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
11990 // we prove that the arithmetic won't overflow, we can't use OF or CF.
11991 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
11992 // Emit a CMP with 0, which is the TEST pattern.
11993 //if (Op.getValueType() == MVT::i1)
11994 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
11995 // DAG.getConstant(0, MVT::i1));
11996 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
11997 DAG.getConstant(0, Op.getValueType()));
11999 unsigned Opcode = 0;
12000 unsigned NumOperands = 0;
12002 // Truncate operations may prevent the merge of the SETCC instruction
12003 // and the arithmetic instruction before it. Attempt to truncate the operands
12004 // of the arithmetic instruction and use a reduced bit-width instruction.
12005 bool NeedTruncation = false;
12006 SDValue ArithOp = Op;
12007 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12008 SDValue Arith = Op->getOperand(0);
12009 // Both the trunc and the arithmetic op need to have one user each.
12010 if (Arith->hasOneUse())
12011 switch (Arith.getOpcode()) {
12018 NeedTruncation = true;
12024 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12025 // which may be the result of a CAST. We use the variable 'Op', which is the
12026 // non-casted variable when we check for possible users.
12027 switch (ArithOp.getOpcode()) {
12029 // Due to an isel shortcoming, be conservative if this add is likely to be
12030 // selected as part of a load-modify-store instruction. When the root node
12031 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12032 // uses of other nodes in the match, such as the ADD in this case. This
12033 // leads to the ADD being left around and reselected, with the result being
12034 // two adds in the output. Alas, even if none our users are stores, that
12035 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12036 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12037 // climbing the DAG back to the root, and it doesn't seem to be worth the
12039 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12040 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12041 if (UI->getOpcode() != ISD::CopyToReg &&
12042 UI->getOpcode() != ISD::SETCC &&
12043 UI->getOpcode() != ISD::STORE)
12046 if (ConstantSDNode *C =
12047 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12048 // An add of one will be selected as an INC.
12049 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12050 Opcode = X86ISD::INC;
12055 // An add of negative one (subtract of one) will be selected as a DEC.
12056 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12057 Opcode = X86ISD::DEC;
12063 // Otherwise use a regular EFLAGS-setting add.
12064 Opcode = X86ISD::ADD;
12069 // If we have a constant logical shift that's only used in a comparison
12070 // against zero turn it into an equivalent AND. This allows turning it into
12071 // a TEST instruction later.
12072 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12073 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12074 EVT VT = Op.getValueType();
12075 unsigned BitWidth = VT.getSizeInBits();
12076 unsigned ShAmt = Op->getConstantOperandVal(1);
12077 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12079 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12080 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12081 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12082 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12084 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12085 DAG.getConstant(Mask, VT));
12086 DAG.ReplaceAllUsesWith(Op, New);
12092 // If the primary and result isn't used, don't bother using X86ISD::AND,
12093 // because a TEST instruction will be better.
12094 if (!hasNonFlagsUse(Op))
12100 // Due to the ISEL shortcoming noted above, be conservative if this op is
12101 // likely to be selected as part of a load-modify-store instruction.
12102 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12103 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12104 if (UI->getOpcode() == ISD::STORE)
12107 // Otherwise use a regular EFLAGS-setting instruction.
12108 switch (ArithOp.getOpcode()) {
12109 default: llvm_unreachable("unexpected operator!");
12110 case ISD::SUB: Opcode = X86ISD::SUB; break;
12111 case ISD::XOR: Opcode = X86ISD::XOR; break;
12112 case ISD::AND: Opcode = X86ISD::AND; break;
12114 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12115 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12116 if (EFLAGS.getNode())
12119 Opcode = X86ISD::OR;
12133 return SDValue(Op.getNode(), 1);
12139 // If we found that truncation is beneficial, perform the truncation and
12141 if (NeedTruncation) {
12142 EVT VT = Op.getValueType();
12143 SDValue WideVal = Op->getOperand(0);
12144 EVT WideVT = WideVal.getValueType();
12145 unsigned ConvertedOp = 0;
12146 // Use a target machine opcode to prevent further DAGCombine
12147 // optimizations that may separate the arithmetic operations
12148 // from the setcc node.
12149 switch (WideVal.getOpcode()) {
12151 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12152 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12153 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12154 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12155 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12159 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12160 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12161 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12162 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12163 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12169 // Emit a CMP with 0, which is the TEST pattern.
12170 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12171 DAG.getConstant(0, Op.getValueType()));
12173 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12174 SmallVector<SDValue, 4> Ops;
12175 for (unsigned i = 0; i != NumOperands; ++i)
12176 Ops.push_back(Op.getOperand(i));
12178 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12179 DAG.ReplaceAllUsesWith(Op, New);
12180 return SDValue(New.getNode(), 1);
12183 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12185 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12186 SDLoc dl, SelectionDAG &DAG) const {
12187 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12188 if (C->getAPIntValue() == 0)
12189 return EmitTest(Op0, X86CC, dl, DAG);
12191 if (Op0.getValueType() == MVT::i1)
12192 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12195 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12196 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12197 // Do the comparison at i32 if it's smaller, besides the Atom case.
12198 // This avoids subregister aliasing issues. Keep the smaller reference
12199 // if we're optimizing for size, however, as that'll allow better folding
12200 // of memory operations.
12201 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12202 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
12203 AttributeSet::FunctionIndex, Attribute::MinSize) &&
12204 !Subtarget->isAtom()) {
12205 unsigned ExtendOp =
12206 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12207 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12208 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12210 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12211 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12212 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12214 return SDValue(Sub.getNode(), 1);
12216 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12219 /// Convert a comparison if required by the subtarget.
12220 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12221 SelectionDAG &DAG) const {
12222 // If the subtarget does not support the FUCOMI instruction, floating-point
12223 // comparisons have to be converted.
12224 if (Subtarget->hasCMov() ||
12225 Cmp.getOpcode() != X86ISD::CMP ||
12226 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12227 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12230 // The instruction selector will select an FUCOM instruction instead of
12231 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12232 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12233 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12235 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12236 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12237 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12238 DAG.getConstant(8, MVT::i8));
12239 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12240 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12243 static bool isAllOnes(SDValue V) {
12244 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12245 return C && C->isAllOnesValue();
12248 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12249 /// if it's possible.
12250 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12251 SDLoc dl, SelectionDAG &DAG) const {
12252 SDValue Op0 = And.getOperand(0);
12253 SDValue Op1 = And.getOperand(1);
12254 if (Op0.getOpcode() == ISD::TRUNCATE)
12255 Op0 = Op0.getOperand(0);
12256 if (Op1.getOpcode() == ISD::TRUNCATE)
12257 Op1 = Op1.getOperand(0);
12260 if (Op1.getOpcode() == ISD::SHL)
12261 std::swap(Op0, Op1);
12262 if (Op0.getOpcode() == ISD::SHL) {
12263 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
12264 if (And00C->getZExtValue() == 1) {
12265 // If we looked past a truncate, check that it's only truncating away
12267 unsigned BitWidth = Op0.getValueSizeInBits();
12268 unsigned AndBitWidth = And.getValueSizeInBits();
12269 if (BitWidth > AndBitWidth) {
12271 DAG.computeKnownBits(Op0, Zeros, Ones);
12272 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
12276 RHS = Op0.getOperand(1);
12278 } else if (Op1.getOpcode() == ISD::Constant) {
12279 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
12280 uint64_t AndRHSVal = AndRHS->getZExtValue();
12281 SDValue AndLHS = Op0;
12283 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
12284 LHS = AndLHS.getOperand(0);
12285 RHS = AndLHS.getOperand(1);
12288 // Use BT if the immediate can't be encoded in a TEST instruction.
12289 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
12291 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
12295 if (LHS.getNode()) {
12296 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
12297 // instruction. Since the shift amount is in-range-or-undefined, we know
12298 // that doing a bittest on the i32 value is ok. We extend to i32 because
12299 // the encoding for the i16 version is larger than the i32 version.
12300 // Also promote i16 to i32 for performance / code size reason.
12301 if (LHS.getValueType() == MVT::i8 ||
12302 LHS.getValueType() == MVT::i16)
12303 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
12305 // If the operand types disagree, extend the shift amount to match. Since
12306 // BT ignores high bits (like shifts) we can use anyextend.
12307 if (LHS.getValueType() != RHS.getValueType())
12308 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
12310 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
12311 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
12312 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12313 DAG.getConstant(Cond, MVT::i8), BT);
12319 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
12321 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
12326 // SSE Condition code mapping:
12335 switch (SetCCOpcode) {
12336 default: llvm_unreachable("Unexpected SETCC condition");
12338 case ISD::SETEQ: SSECC = 0; break;
12340 case ISD::SETGT: Swap = true; // Fallthrough
12342 case ISD::SETOLT: SSECC = 1; break;
12344 case ISD::SETGE: Swap = true; // Fallthrough
12346 case ISD::SETOLE: SSECC = 2; break;
12347 case ISD::SETUO: SSECC = 3; break;
12349 case ISD::SETNE: SSECC = 4; break;
12350 case ISD::SETULE: Swap = true; // Fallthrough
12351 case ISD::SETUGE: SSECC = 5; break;
12352 case ISD::SETULT: Swap = true; // Fallthrough
12353 case ISD::SETUGT: SSECC = 6; break;
12354 case ISD::SETO: SSECC = 7; break;
12356 case ISD::SETONE: SSECC = 8; break;
12359 std::swap(Op0, Op1);
12364 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
12365 // ones, and then concatenate the result back.
12366 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
12367 MVT VT = Op.getSimpleValueType();
12369 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
12370 "Unsupported value type for operation");
12372 unsigned NumElems = VT.getVectorNumElements();
12374 SDValue CC = Op.getOperand(2);
12376 // Extract the LHS vectors
12377 SDValue LHS = Op.getOperand(0);
12378 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12379 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12381 // Extract the RHS vectors
12382 SDValue RHS = Op.getOperand(1);
12383 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
12384 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
12386 // Issue the operation on the smaller types and concatenate the result back
12387 MVT EltVT = VT.getVectorElementType();
12388 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12389 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
12390 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
12391 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
12394 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
12395 const X86Subtarget *Subtarget) {
12396 SDValue Op0 = Op.getOperand(0);
12397 SDValue Op1 = Op.getOperand(1);
12398 SDValue CC = Op.getOperand(2);
12399 MVT VT = Op.getSimpleValueType();
12402 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 32 &&
12403 Op.getValueType().getScalarType() == MVT::i1 &&
12404 "Cannot set masked compare for this operation");
12406 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12408 bool Unsigned = false;
12411 switch (SetCCOpcode) {
12412 default: llvm_unreachable("Unexpected SETCC condition");
12413 case ISD::SETNE: SSECC = 4; break;
12414 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
12415 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
12416 case ISD::SETLT: Swap = true; //fall-through
12417 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
12418 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
12419 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
12420 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
12421 case ISD::SETULE: Unsigned = true; //fall-through
12422 case ISD::SETLE: SSECC = 2; break;
12426 std::swap(Op0, Op1);
12428 return DAG.getNode(Opc, dl, VT, Op0, Op1);
12429 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
12430 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12431 DAG.getConstant(SSECC, MVT::i8));
12434 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
12435 /// operand \p Op1. If non-trivial (for example because it's not constant)
12436 /// return an empty value.
12437 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
12439 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
12443 MVT VT = Op1.getSimpleValueType();
12444 MVT EVT = VT.getVectorElementType();
12445 unsigned n = VT.getVectorNumElements();
12446 SmallVector<SDValue, 8> ULTOp1;
12448 for (unsigned i = 0; i < n; ++i) {
12449 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
12450 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
12453 // Avoid underflow.
12454 APInt Val = Elt->getAPIntValue();
12458 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
12461 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
12464 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
12465 SelectionDAG &DAG) {
12466 SDValue Op0 = Op.getOperand(0);
12467 SDValue Op1 = Op.getOperand(1);
12468 SDValue CC = Op.getOperand(2);
12469 MVT VT = Op.getSimpleValueType();
12470 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
12471 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
12476 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
12477 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
12480 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
12481 unsigned Opc = X86ISD::CMPP;
12482 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
12483 assert(VT.getVectorNumElements() <= 16);
12484 Opc = X86ISD::CMPM;
12486 // In the two special cases we can't handle, emit two comparisons.
12489 unsigned CombineOpc;
12490 if (SetCCOpcode == ISD::SETUEQ) {
12491 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
12493 assert(SetCCOpcode == ISD::SETONE);
12494 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
12497 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12498 DAG.getConstant(CC0, MVT::i8));
12499 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
12500 DAG.getConstant(CC1, MVT::i8));
12501 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
12503 // Handle all other FP comparisons here.
12504 return DAG.getNode(Opc, dl, VT, Op0, Op1,
12505 DAG.getConstant(SSECC, MVT::i8));
12508 // Break 256-bit integer vector compare into smaller ones.
12509 if (VT.is256BitVector() && !Subtarget->hasInt256())
12510 return Lower256IntVSETCC(Op, DAG);
12512 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
12513 EVT OpVT = Op1.getValueType();
12514 if (Subtarget->hasAVX512()) {
12515 if (Op1.getValueType().is512BitVector() ||
12516 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
12517 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
12519 // In AVX-512 architecture setcc returns mask with i1 elements,
12520 // But there is no compare instruction for i8 and i16 elements.
12521 // We are not talking about 512-bit operands in this case, these
12522 // types are illegal.
12524 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
12525 OpVT.getVectorElementType().getSizeInBits() >= 8))
12526 return DAG.getNode(ISD::TRUNCATE, dl, VT,
12527 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
12530 // We are handling one of the integer comparisons here. Since SSE only has
12531 // GT and EQ comparisons for integer, swapping operands and multiple
12532 // operations may be required for some comparisons.
12534 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
12535 bool Subus = false;
12537 switch (SetCCOpcode) {
12538 default: llvm_unreachable("Unexpected SETCC condition");
12539 case ISD::SETNE: Invert = true;
12540 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
12541 case ISD::SETLT: Swap = true;
12542 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
12543 case ISD::SETGE: Swap = true;
12544 case ISD::SETLE: Opc = X86ISD::PCMPGT;
12545 Invert = true; break;
12546 case ISD::SETULT: Swap = true;
12547 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
12548 FlipSigns = true; break;
12549 case ISD::SETUGE: Swap = true;
12550 case ISD::SETULE: Opc = X86ISD::PCMPGT;
12551 FlipSigns = true; Invert = true; break;
12554 // Special case: Use min/max operations for SETULE/SETUGE
12555 MVT VET = VT.getVectorElementType();
12557 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
12558 || (Subtarget->hasSSE2() && (VET == MVT::i8));
12561 switch (SetCCOpcode) {
12563 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
12564 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
12567 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
12570 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
12571 if (!MinMax && hasSubus) {
12572 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
12574 // t = psubus Op0, Op1
12575 // pcmpeq t, <0..0>
12576 switch (SetCCOpcode) {
12578 case ISD::SETULT: {
12579 // If the comparison is against a constant we can turn this into a
12580 // setule. With psubus, setule does not require a swap. This is
12581 // beneficial because the constant in the register is no longer
12582 // destructed as the destination so it can be hoisted out of a loop.
12583 // Only do this pre-AVX since vpcmp* is no longer destructive.
12584 if (Subtarget->hasAVX())
12586 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
12587 if (ULEOp1.getNode()) {
12589 Subus = true; Invert = false; Swap = false;
12593 // Psubus is better than flip-sign because it requires no inversion.
12594 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
12595 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
12599 Opc = X86ISD::SUBUS;
12605 std::swap(Op0, Op1);
12607 // Check that the operation in question is available (most are plain SSE2,
12608 // but PCMPGTQ and PCMPEQQ have different requirements).
12609 if (VT == MVT::v2i64) {
12610 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
12611 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
12613 // First cast everything to the right type.
12614 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12615 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12617 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12618 // bits of the inputs before performing those operations. The lower
12619 // compare is always unsigned.
12622 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
12624 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
12625 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
12626 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
12627 Sign, Zero, Sign, Zero);
12629 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
12630 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
12632 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
12633 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
12634 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
12636 // Create masks for only the low parts/high parts of the 64 bit integers.
12637 static const int MaskHi[] = { 1, 1, 3, 3 };
12638 static const int MaskLo[] = { 0, 0, 2, 2 };
12639 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
12640 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
12641 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
12643 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
12644 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
12647 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12649 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12652 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
12653 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
12654 // pcmpeqd + pshufd + pand.
12655 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
12657 // First cast everything to the right type.
12658 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
12659 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
12662 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
12664 // Make sure the lower and upper halves are both all-ones.
12665 static const int Mask[] = { 1, 0, 3, 2 };
12666 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
12667 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
12670 Result = DAG.getNOT(dl, Result, MVT::v4i32);
12672 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
12676 // Since SSE has no unsigned integer comparisons, we need to flip the sign
12677 // bits of the inputs before performing those operations.
12679 EVT EltVT = VT.getVectorElementType();
12680 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
12681 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
12682 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
12685 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
12687 // If the logical-not of the result is required, perform that now.
12689 Result = DAG.getNOT(dl, Result, VT);
12692 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
12695 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
12696 getZeroVector(VT, Subtarget, DAG, dl));
12701 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
12703 MVT VT = Op.getSimpleValueType();
12705 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
12707 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
12708 && "SetCC type must be 8-bit or 1-bit integer");
12709 SDValue Op0 = Op.getOperand(0);
12710 SDValue Op1 = Op.getOperand(1);
12712 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
12714 // Optimize to BT if possible.
12715 // Lower (X & (1 << N)) == 0 to BT(X, N).
12716 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
12717 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
12718 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
12719 Op1.getOpcode() == ISD::Constant &&
12720 cast<ConstantSDNode>(Op1)->isNullValue() &&
12721 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12722 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
12723 if (NewSetCC.getNode())
12727 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
12729 if (Op1.getOpcode() == ISD::Constant &&
12730 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
12731 cast<ConstantSDNode>(Op1)->isNullValue()) &&
12732 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12734 // If the input is a setcc, then reuse the input setcc or use a new one with
12735 // the inverted condition.
12736 if (Op0.getOpcode() == X86ISD::SETCC) {
12737 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
12738 bool Invert = (CC == ISD::SETNE) ^
12739 cast<ConstantSDNode>(Op1)->isNullValue();
12743 CCode = X86::GetOppositeBranchCondition(CCode);
12744 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12745 DAG.getConstant(CCode, MVT::i8),
12746 Op0.getOperand(1));
12748 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12752 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
12753 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
12754 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
12756 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
12757 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
12760 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
12761 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
12762 if (X86CC == X86::COND_INVALID)
12765 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
12766 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
12767 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
12768 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
12770 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
12774 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
12775 static bool isX86LogicalCmp(SDValue Op) {
12776 unsigned Opc = Op.getNode()->getOpcode();
12777 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
12778 Opc == X86ISD::SAHF)
12780 if (Op.getResNo() == 1 &&
12781 (Opc == X86ISD::ADD ||
12782 Opc == X86ISD::SUB ||
12783 Opc == X86ISD::ADC ||
12784 Opc == X86ISD::SBB ||
12785 Opc == X86ISD::SMUL ||
12786 Opc == X86ISD::UMUL ||
12787 Opc == X86ISD::INC ||
12788 Opc == X86ISD::DEC ||
12789 Opc == X86ISD::OR ||
12790 Opc == X86ISD::XOR ||
12791 Opc == X86ISD::AND))
12794 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
12800 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
12801 if (V.getOpcode() != ISD::TRUNCATE)
12804 SDValue VOp0 = V.getOperand(0);
12805 unsigned InBits = VOp0.getValueSizeInBits();
12806 unsigned Bits = V.getValueSizeInBits();
12807 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
12810 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
12811 bool addTest = true;
12812 SDValue Cond = Op.getOperand(0);
12813 SDValue Op1 = Op.getOperand(1);
12814 SDValue Op2 = Op.getOperand(2);
12816 EVT VT = Op1.getValueType();
12819 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
12820 // are available. Otherwise fp cmovs get lowered into a less efficient branch
12821 // sequence later on.
12822 if (Cond.getOpcode() == ISD::SETCC &&
12823 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
12824 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
12825 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
12826 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
12827 int SSECC = translateX86FSETCC(
12828 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
12831 if (Subtarget->hasAVX512()) {
12832 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
12833 DAG.getConstant(SSECC, MVT::i8));
12834 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
12836 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
12837 DAG.getConstant(SSECC, MVT::i8));
12838 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
12839 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
12840 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
12844 if (Cond.getOpcode() == ISD::SETCC) {
12845 SDValue NewCond = LowerSETCC(Cond, DAG);
12846 if (NewCond.getNode())
12850 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
12851 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
12852 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
12853 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
12854 if (Cond.getOpcode() == X86ISD::SETCC &&
12855 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
12856 isZero(Cond.getOperand(1).getOperand(1))) {
12857 SDValue Cmp = Cond.getOperand(1);
12859 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
12861 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
12862 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
12863 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
12865 SDValue CmpOp0 = Cmp.getOperand(0);
12866 // Apply further optimizations for special cases
12867 // (select (x != 0), -1, 0) -> neg & sbb
12868 // (select (x == 0), 0, -1) -> neg & sbb
12869 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
12870 if (YC->isNullValue() &&
12871 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
12872 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
12873 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
12874 DAG.getConstant(0, CmpOp0.getValueType()),
12876 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12877 DAG.getConstant(X86::COND_B, MVT::i8),
12878 SDValue(Neg.getNode(), 1));
12882 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
12883 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
12884 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
12886 SDValue Res = // Res = 0 or -1.
12887 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12888 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
12890 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
12891 Res = DAG.getNOT(DL, Res, Res.getValueType());
12893 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
12894 if (!N2C || !N2C->isNullValue())
12895 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
12900 // Look past (and (setcc_carry (cmp ...)), 1).
12901 if (Cond.getOpcode() == ISD::AND &&
12902 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
12903 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
12904 if (C && C->getAPIntValue() == 1)
12905 Cond = Cond.getOperand(0);
12908 // If condition flag is set by a X86ISD::CMP, then use it as the condition
12909 // setting operand in place of the X86ISD::SETCC.
12910 unsigned CondOpcode = Cond.getOpcode();
12911 if (CondOpcode == X86ISD::SETCC ||
12912 CondOpcode == X86ISD::SETCC_CARRY) {
12913 CC = Cond.getOperand(0);
12915 SDValue Cmp = Cond.getOperand(1);
12916 unsigned Opc = Cmp.getOpcode();
12917 MVT VT = Op.getSimpleValueType();
12919 bool IllegalFPCMov = false;
12920 if (VT.isFloatingPoint() && !VT.isVector() &&
12921 !isScalarFPTypeInSSEReg(VT)) // FPStack?
12922 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
12924 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
12925 Opc == X86ISD::BT) { // FIXME
12929 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
12930 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
12931 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
12932 Cond.getOperand(0).getValueType() != MVT::i8)) {
12933 SDValue LHS = Cond.getOperand(0);
12934 SDValue RHS = Cond.getOperand(1);
12935 unsigned X86Opcode;
12938 switch (CondOpcode) {
12939 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
12940 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
12941 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
12942 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
12943 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
12944 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
12945 default: llvm_unreachable("unexpected overflowing operator");
12947 if (CondOpcode == ISD::UMULO)
12948 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
12951 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
12953 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
12955 if (CondOpcode == ISD::UMULO)
12956 Cond = X86Op.getValue(2);
12958 Cond = X86Op.getValue(1);
12960 CC = DAG.getConstant(X86Cond, MVT::i8);
12965 // Look pass the truncate if the high bits are known zero.
12966 if (isTruncWithZeroHighBitsInput(Cond, DAG))
12967 Cond = Cond.getOperand(0);
12969 // We know the result of AND is compared against zero. Try to match
12971 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
12972 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
12973 if (NewSetCC.getNode()) {
12974 CC = NewSetCC.getOperand(0);
12975 Cond = NewSetCC.getOperand(1);
12982 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
12983 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
12986 // a < b ? -1 : 0 -> RES = ~setcc_carry
12987 // a < b ? 0 : -1 -> RES = setcc_carry
12988 // a >= b ? -1 : 0 -> RES = setcc_carry
12989 // a >= b ? 0 : -1 -> RES = ~setcc_carry
12990 if (Cond.getOpcode() == X86ISD::SUB) {
12991 Cond = ConvertCmpIfNecessary(Cond, DAG);
12992 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
12994 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
12995 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
12996 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
12997 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
12998 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
12999 return DAG.getNOT(DL, Res, Res.getValueType());
13004 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13005 // widen the cmov and push the truncate through. This avoids introducing a new
13006 // branch during isel and doesn't add any extensions.
13007 if (Op.getValueType() == MVT::i8 &&
13008 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13009 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13010 if (T1.getValueType() == T2.getValueType() &&
13011 // Blacklist CopyFromReg to avoid partial register stalls.
13012 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13013 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13014 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13015 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13019 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13020 // condition is true.
13021 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13022 SDValue Ops[] = { Op2, Op1, CC, Cond };
13023 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13026 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, SelectionDAG &DAG) {
13027 MVT VT = Op->getSimpleValueType(0);
13028 SDValue In = Op->getOperand(0);
13029 MVT InVT = In.getSimpleValueType();
13032 unsigned int NumElts = VT.getVectorNumElements();
13033 if (NumElts != 8 && NumElts != 16)
13036 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13037 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13039 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13040 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13042 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
13043 Constant *C = ConstantInt::get(*DAG.getContext(),
13044 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
13046 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
13047 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
13048 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
13049 MachinePointerInfo::getConstantPool(),
13050 false, false, false, Alignment);
13051 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
13052 if (VT.is512BitVector())
13054 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
13057 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13058 SelectionDAG &DAG) {
13059 MVT VT = Op->getSimpleValueType(0);
13060 SDValue In = Op->getOperand(0);
13061 MVT InVT = In.getSimpleValueType();
13064 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13065 return LowerSIGN_EXTEND_AVX512(Op, DAG);
13067 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
13068 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
13069 (VT != MVT::v16i16 || InVT != MVT::v16i8))
13072 if (Subtarget->hasInt256())
13073 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13075 // Optimize vectors in AVX mode
13076 // Sign extend v8i16 to v8i32 and
13079 // Divide input vector into two parts
13080 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
13081 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
13082 // concat the vectors to original VT
13084 unsigned NumElems = InVT.getVectorNumElements();
13085 SDValue Undef = DAG.getUNDEF(InVT);
13087 SmallVector<int,8> ShufMask1(NumElems, -1);
13088 for (unsigned i = 0; i != NumElems/2; ++i)
13091 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
13093 SmallVector<int,8> ShufMask2(NumElems, -1);
13094 for (unsigned i = 0; i != NumElems/2; ++i)
13095 ShufMask2[i] = i + NumElems/2;
13097 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
13099 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
13100 VT.getVectorNumElements()/2);
13102 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
13103 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
13105 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13108 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
13109 // may emit an illegal shuffle but the expansion is still better than scalar
13110 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
13111 // we'll emit a shuffle and a arithmetic shift.
13112 // TODO: It is possible to support ZExt by zeroing the undef values during
13113 // the shuffle phase or after the shuffle.
13114 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
13115 SelectionDAG &DAG) {
13116 MVT RegVT = Op.getSimpleValueType();
13117 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
13118 assert(RegVT.isInteger() &&
13119 "We only custom lower integer vector sext loads.");
13121 // Nothing useful we can do without SSE2 shuffles.
13122 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
13124 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
13126 EVT MemVT = Ld->getMemoryVT();
13127 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13128 unsigned RegSz = RegVT.getSizeInBits();
13130 ISD::LoadExtType Ext = Ld->getExtensionType();
13132 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
13133 && "Only anyext and sext are currently implemented.");
13134 assert(MemVT != RegVT && "Cannot extend to the same type");
13135 assert(MemVT.isVector() && "Must load a vector from memory");
13137 unsigned NumElems = RegVT.getVectorNumElements();
13138 unsigned MemSz = MemVT.getSizeInBits();
13139 assert(RegSz > MemSz && "Register size must be greater than the mem size");
13141 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
13142 // The only way in which we have a legal 256-bit vector result but not the
13143 // integer 256-bit operations needed to directly lower a sextload is if we
13144 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
13145 // a 128-bit vector and a normal sign_extend to 256-bits that should get
13146 // correctly legalized. We do this late to allow the canonical form of
13147 // sextload to persist throughout the rest of the DAG combiner -- it wants
13148 // to fold together any extensions it can, and so will fuse a sign_extend
13149 // of an sextload into an sextload targeting a wider value.
13151 if (MemSz == 128) {
13152 // Just switch this to a normal load.
13153 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
13154 "it must be a legal 128-bit vector "
13156 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
13157 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
13158 Ld->isInvariant(), Ld->getAlignment());
13160 assert(MemSz < 128 &&
13161 "Can't extend a type wider than 128 bits to a 256 bit vector!");
13162 // Do an sext load to a 128-bit vector type. We want to use the same
13163 // number of elements, but elements half as wide. This will end up being
13164 // recursively lowered by this routine, but will succeed as we definitely
13165 // have all the necessary features if we're using AVX1.
13167 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
13168 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
13170 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
13171 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
13172 Ld->isNonTemporal(), Ld->isInvariant(),
13173 Ld->getAlignment());
13176 // Replace chain users with the new chain.
13177 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
13178 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
13180 // Finally, do a normal sign-extend to the desired register.
13181 return DAG.getSExtOrTrunc(Load, dl, RegVT);
13184 // All sizes must be a power of two.
13185 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
13186 "Non-power-of-two elements are not custom lowered!");
13188 // Attempt to load the original value using scalar loads.
13189 // Find the largest scalar type that divides the total loaded size.
13190 MVT SclrLoadTy = MVT::i8;
13191 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13192 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13193 MVT Tp = (MVT::SimpleValueType)tp;
13194 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
13199 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
13200 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
13202 SclrLoadTy = MVT::f64;
13204 // Calculate the number of scalar loads that we need to perform
13205 // in order to load our vector from memory.
13206 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
13208 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
13209 "Can only lower sext loads with a single scalar load!");
13211 unsigned loadRegZize = RegSz;
13212 if (Ext == ISD::SEXTLOAD && RegSz == 256)
13215 // Represent our vector as a sequence of elements which are the
13216 // largest scalar that we can load.
13217 EVT LoadUnitVecVT = EVT::getVectorVT(
13218 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
13220 // Represent the data using the same element type that is stored in
13221 // memory. In practice, we ''widen'' MemVT.
13223 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
13224 loadRegZize / MemVT.getScalarType().getSizeInBits());
13226 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
13227 "Invalid vector type");
13229 // We can't shuffle using an illegal type.
13230 assert(TLI.isTypeLegal(WideVecVT) &&
13231 "We only lower types that form legal widened vector types");
13233 SmallVector<SDValue, 8> Chains;
13234 SDValue Ptr = Ld->getBasePtr();
13235 SDValue Increment =
13236 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
13237 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
13239 for (unsigned i = 0; i < NumLoads; ++i) {
13240 // Perform a single load.
13241 SDValue ScalarLoad =
13242 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
13243 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
13244 Ld->getAlignment());
13245 Chains.push_back(ScalarLoad.getValue(1));
13246 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
13247 // another round of DAGCombining.
13249 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
13251 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
13252 ScalarLoad, DAG.getIntPtrConstant(i));
13254 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13257 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
13259 // Bitcast the loaded value to a vector of the original element type, in
13260 // the size of the target vector type.
13261 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
13262 unsigned SizeRatio = RegSz / MemSz;
13264 if (Ext == ISD::SEXTLOAD) {
13265 // If we have SSE4.1 we can directly emit a VSEXT node.
13266 if (Subtarget->hasSSE41()) {
13267 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
13268 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13272 // Otherwise we'll shuffle the small elements in the high bits of the
13273 // larger type and perform an arithmetic shift. If the shift is not legal
13274 // it's better to scalarize.
13275 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
13276 "We can't implement an sext load without a arithmetic right shift!");
13278 // Redistribute the loaded elements into the different locations.
13279 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13280 for (unsigned i = 0; i != NumElems; ++i)
13281 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
13283 SDValue Shuff = DAG.getVectorShuffle(
13284 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13286 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13288 // Build the arithmetic shift.
13289 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
13290 MemVT.getVectorElementType().getSizeInBits();
13292 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
13294 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13298 // Redistribute the loaded elements into the different locations.
13299 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13300 for (unsigned i = 0; i != NumElems; ++i)
13301 ShuffleVec[i * SizeRatio] = i;
13303 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
13304 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
13306 // Bitcast to the requested type.
13307 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
13308 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
13312 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
13313 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
13314 // from the AND / OR.
13315 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
13316 Opc = Op.getOpcode();
13317 if (Opc != ISD::OR && Opc != ISD::AND)
13319 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13320 Op.getOperand(0).hasOneUse() &&
13321 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
13322 Op.getOperand(1).hasOneUse());
13325 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
13326 // 1 and that the SETCC node has a single use.
13327 static bool isXor1OfSetCC(SDValue Op) {
13328 if (Op.getOpcode() != ISD::XOR)
13330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
13331 if (N1C && N1C->getAPIntValue() == 1) {
13332 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
13333 Op.getOperand(0).hasOneUse();
13338 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
13339 bool addTest = true;
13340 SDValue Chain = Op.getOperand(0);
13341 SDValue Cond = Op.getOperand(1);
13342 SDValue Dest = Op.getOperand(2);
13345 bool Inverted = false;
13347 if (Cond.getOpcode() == ISD::SETCC) {
13348 // Check for setcc([su]{add,sub,mul}o == 0).
13349 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
13350 isa<ConstantSDNode>(Cond.getOperand(1)) &&
13351 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
13352 Cond.getOperand(0).getResNo() == 1 &&
13353 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
13354 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
13355 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
13356 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
13357 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
13358 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
13360 Cond = Cond.getOperand(0);
13362 SDValue NewCond = LowerSETCC(Cond, DAG);
13363 if (NewCond.getNode())
13368 // FIXME: LowerXALUO doesn't handle these!!
13369 else if (Cond.getOpcode() == X86ISD::ADD ||
13370 Cond.getOpcode() == X86ISD::SUB ||
13371 Cond.getOpcode() == X86ISD::SMUL ||
13372 Cond.getOpcode() == X86ISD::UMUL)
13373 Cond = LowerXALUO(Cond, DAG);
13376 // Look pass (and (setcc_carry (cmp ...)), 1).
13377 if (Cond.getOpcode() == ISD::AND &&
13378 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13379 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13380 if (C && C->getAPIntValue() == 1)
13381 Cond = Cond.getOperand(0);
13384 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13385 // setting operand in place of the X86ISD::SETCC.
13386 unsigned CondOpcode = Cond.getOpcode();
13387 if (CondOpcode == X86ISD::SETCC ||
13388 CondOpcode == X86ISD::SETCC_CARRY) {
13389 CC = Cond.getOperand(0);
13391 SDValue Cmp = Cond.getOperand(1);
13392 unsigned Opc = Cmp.getOpcode();
13393 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
13394 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
13398 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
13402 // These can only come from an arithmetic instruction with overflow,
13403 // e.g. SADDO, UADDO.
13404 Cond = Cond.getNode()->getOperand(1);
13410 CondOpcode = Cond.getOpcode();
13411 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13412 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13413 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13414 Cond.getOperand(0).getValueType() != MVT::i8)) {
13415 SDValue LHS = Cond.getOperand(0);
13416 SDValue RHS = Cond.getOperand(1);
13417 unsigned X86Opcode;
13420 // Keep this in sync with LowerXALUO, otherwise we might create redundant
13421 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
13423 switch (CondOpcode) {
13424 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13426 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13428 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
13431 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13432 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13434 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
13436 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
13439 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13440 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13441 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13442 default: llvm_unreachable("unexpected overflowing operator");
13445 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
13446 if (CondOpcode == ISD::UMULO)
13447 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13450 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13452 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
13454 if (CondOpcode == ISD::UMULO)
13455 Cond = X86Op.getValue(2);
13457 Cond = X86Op.getValue(1);
13459 CC = DAG.getConstant(X86Cond, MVT::i8);
13463 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
13464 SDValue Cmp = Cond.getOperand(0).getOperand(1);
13465 if (CondOpc == ISD::OR) {
13466 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
13467 // two branches instead of an explicit OR instruction with a
13469 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13470 isX86LogicalCmp(Cmp)) {
13471 CC = Cond.getOperand(0).getOperand(0);
13472 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13473 Chain, Dest, CC, Cmp);
13474 CC = Cond.getOperand(1).getOperand(0);
13478 } else { // ISD::AND
13479 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
13480 // two branches instead of an explicit AND instruction with a
13481 // separate test. However, we only do this if this block doesn't
13482 // have a fall-through edge, because this requires an explicit
13483 // jmp when the condition is false.
13484 if (Cmp == Cond.getOperand(1).getOperand(1) &&
13485 isX86LogicalCmp(Cmp) &&
13486 Op.getNode()->hasOneUse()) {
13487 X86::CondCode CCode =
13488 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13489 CCode = X86::GetOppositeBranchCondition(CCode);
13490 CC = DAG.getConstant(CCode, MVT::i8);
13491 SDNode *User = *Op.getNode()->use_begin();
13492 // Look for an unconditional branch following this conditional branch.
13493 // We need this because we need to reverse the successors in order
13494 // to implement FCMP_OEQ.
13495 if (User->getOpcode() == ISD::BR) {
13496 SDValue FalseBB = User->getOperand(1);
13498 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13499 assert(NewBR == User);
13503 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13504 Chain, Dest, CC, Cmp);
13505 X86::CondCode CCode =
13506 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
13507 CCode = X86::GetOppositeBranchCondition(CCode);
13508 CC = DAG.getConstant(CCode, MVT::i8);
13514 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
13515 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
13516 // It should be transformed during dag combiner except when the condition
13517 // is set by a arithmetics with overflow node.
13518 X86::CondCode CCode =
13519 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
13520 CCode = X86::GetOppositeBranchCondition(CCode);
13521 CC = DAG.getConstant(CCode, MVT::i8);
13522 Cond = Cond.getOperand(0).getOperand(1);
13524 } else if (Cond.getOpcode() == ISD::SETCC &&
13525 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
13526 // For FCMP_OEQ, we can emit
13527 // two branches instead of an explicit AND instruction with a
13528 // separate test. However, we only do this if this block doesn't
13529 // have a fall-through edge, because this requires an explicit
13530 // jmp when the condition is false.
13531 if (Op.getNode()->hasOneUse()) {
13532 SDNode *User = *Op.getNode()->use_begin();
13533 // Look for an unconditional branch following this conditional branch.
13534 // We need this because we need to reverse the successors in order
13535 // to implement FCMP_OEQ.
13536 if (User->getOpcode() == ISD::BR) {
13537 SDValue FalseBB = User->getOperand(1);
13539 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13540 assert(NewBR == User);
13544 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13545 Cond.getOperand(0), Cond.getOperand(1));
13546 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13547 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13548 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13549 Chain, Dest, CC, Cmp);
13550 CC = DAG.getConstant(X86::COND_P, MVT::i8);
13555 } else if (Cond.getOpcode() == ISD::SETCC &&
13556 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
13557 // For FCMP_UNE, we can emit
13558 // two branches instead of an explicit AND instruction with a
13559 // separate test. However, we only do this if this block doesn't
13560 // have a fall-through edge, because this requires an explicit
13561 // jmp when the condition is false.
13562 if (Op.getNode()->hasOneUse()) {
13563 SDNode *User = *Op.getNode()->use_begin();
13564 // Look for an unconditional branch following this conditional branch.
13565 // We need this because we need to reverse the successors in order
13566 // to implement FCMP_UNE.
13567 if (User->getOpcode() == ISD::BR) {
13568 SDValue FalseBB = User->getOperand(1);
13570 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
13571 assert(NewBR == User);
13574 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13575 Cond.getOperand(0), Cond.getOperand(1));
13576 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13577 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13578 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13579 Chain, Dest, CC, Cmp);
13580 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
13590 // Look pass the truncate if the high bits are known zero.
13591 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13592 Cond = Cond.getOperand(0);
13594 // We know the result of AND is compared against zero. Try to match
13596 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13597 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
13598 if (NewSetCC.getNode()) {
13599 CC = NewSetCC.getOperand(0);
13600 Cond = NewSetCC.getOperand(1);
13607 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
13608 CC = DAG.getConstant(X86Cond, MVT::i8);
13609 Cond = EmitTest(Cond, X86Cond, dl, DAG);
13611 Cond = ConvertCmpIfNecessary(Cond, DAG);
13612 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
13613 Chain, Dest, CC, Cond);
13616 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
13617 // Calls to _alloca is needed to probe the stack when allocating more than 4k
13618 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
13619 // that the guard pages used by the OS virtual memory manager are allocated in
13620 // correct sequence.
13622 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
13623 SelectionDAG &DAG) const {
13624 MachineFunction &MF = DAG.getMachineFunction();
13625 bool SplitStack = MF.shouldSplitStack();
13626 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMacho()) ||
13631 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13632 SDNode* Node = Op.getNode();
13634 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
13635 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
13636 " not tell us which reg is the stack pointer!");
13637 EVT VT = Node->getValueType(0);
13638 SDValue Tmp1 = SDValue(Node, 0);
13639 SDValue Tmp2 = SDValue(Node, 1);
13640 SDValue Tmp3 = Node->getOperand(2);
13641 SDValue Chain = Tmp1.getOperand(0);
13643 // Chain the dynamic stack allocation so that it doesn't modify the stack
13644 // pointer when other instructions are using the stack.
13645 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
13648 SDValue Size = Tmp2.getOperand(1);
13649 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
13650 Chain = SP.getValue(1);
13651 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
13652 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
13653 unsigned StackAlign = TFI.getStackAlignment();
13654 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
13655 if (Align > StackAlign)
13656 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
13657 DAG.getConstant(-(uint64_t)Align, VT));
13658 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
13660 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
13661 DAG.getIntPtrConstant(0, true), SDValue(),
13664 SDValue Ops[2] = { Tmp1, Tmp2 };
13665 return DAG.getMergeValues(Ops, dl);
13669 SDValue Chain = Op.getOperand(0);
13670 SDValue Size = Op.getOperand(1);
13671 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
13672 EVT VT = Op.getNode()->getValueType(0);
13674 bool Is64Bit = Subtarget->is64Bit();
13675 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
13678 MachineRegisterInfo &MRI = MF.getRegInfo();
13681 // The 64 bit implementation of segmented stacks needs to clobber both r10
13682 // r11. This makes it impossible to use it along with nested parameters.
13683 const Function *F = MF.getFunction();
13685 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
13687 if (I->hasNestAttr())
13688 report_fatal_error("Cannot use segmented stacks with functions that "
13689 "have nested arguments.");
13692 const TargetRegisterClass *AddrRegClass =
13693 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
13694 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
13695 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
13696 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
13697 DAG.getRegister(Vreg, SPTy));
13698 SDValue Ops1[2] = { Value, Chain };
13699 return DAG.getMergeValues(Ops1, dl);
13702 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
13704 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
13705 Flag = Chain.getValue(1);
13706 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13708 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
13710 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
13711 DAG.getSubtarget().getRegisterInfo());
13712 unsigned SPReg = RegInfo->getStackRegister();
13713 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
13714 Chain = SP.getValue(1);
13717 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
13718 DAG.getConstant(-(uint64_t)Align, VT));
13719 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
13722 SDValue Ops1[2] = { SP, Chain };
13723 return DAG.getMergeValues(Ops1, dl);
13727 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
13728 MachineFunction &MF = DAG.getMachineFunction();
13729 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
13731 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13734 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
13735 // vastart just stores the address of the VarArgsFrameIndex slot into the
13736 // memory location argument.
13737 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13739 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
13740 MachinePointerInfo(SV), false, false, 0);
13744 // gp_offset (0 - 6 * 8)
13745 // fp_offset (48 - 48 + 8 * 16)
13746 // overflow_arg_area (point to parameters coming in memory).
13748 SmallVector<SDValue, 8> MemOps;
13749 SDValue FIN = Op.getOperand(1);
13751 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
13752 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
13754 FIN, MachinePointerInfo(SV), false, false, 0);
13755 MemOps.push_back(Store);
13758 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13759 FIN, DAG.getIntPtrConstant(4));
13760 Store = DAG.getStore(Op.getOperand(0), DL,
13761 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
13763 FIN, MachinePointerInfo(SV, 4), false, false, 0);
13764 MemOps.push_back(Store);
13766 // Store ptr to overflow_arg_area
13767 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13768 FIN, DAG.getIntPtrConstant(4));
13769 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
13771 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
13772 MachinePointerInfo(SV, 8),
13774 MemOps.push_back(Store);
13776 // Store ptr to reg_save_area.
13777 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13778 FIN, DAG.getIntPtrConstant(8));
13779 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
13781 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
13782 MachinePointerInfo(SV, 16), false, false, 0);
13783 MemOps.push_back(Store);
13784 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
13787 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
13788 assert(Subtarget->is64Bit() &&
13789 "LowerVAARG only handles 64-bit va_arg!");
13790 assert((Subtarget->isTargetLinux() ||
13791 Subtarget->isTargetDarwin()) &&
13792 "Unhandled target in LowerVAARG");
13793 assert(Op.getNode()->getNumOperands() == 4);
13794 SDValue Chain = Op.getOperand(0);
13795 SDValue SrcPtr = Op.getOperand(1);
13796 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
13797 unsigned Align = Op.getConstantOperandVal(3);
13800 EVT ArgVT = Op.getNode()->getValueType(0);
13801 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
13802 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
13805 // Decide which area this value should be read from.
13806 // TODO: Implement the AMD64 ABI in its entirety. This simple
13807 // selection mechanism works only for the basic types.
13808 if (ArgVT == MVT::f80) {
13809 llvm_unreachable("va_arg for f80 not yet implemented");
13810 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
13811 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
13812 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
13813 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
13815 llvm_unreachable("Unhandled argument type in LowerVAARG");
13818 if (ArgMode == 2) {
13819 // Sanity Check: Make sure using fp_offset makes sense.
13820 assert(!DAG.getTarget().Options.UseSoftFloat &&
13821 !(DAG.getMachineFunction()
13822 .getFunction()->getAttributes()
13823 .hasAttribute(AttributeSet::FunctionIndex,
13824 Attribute::NoImplicitFloat)) &&
13825 Subtarget->hasSSE1());
13828 // Insert VAARG_64 node into the DAG
13829 // VAARG_64 returns two values: Variable Argument Address, Chain
13830 SmallVector<SDValue, 11> InstOps;
13831 InstOps.push_back(Chain);
13832 InstOps.push_back(SrcPtr);
13833 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
13834 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
13835 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
13836 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
13837 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
13838 VTs, InstOps, MVT::i64,
13839 MachinePointerInfo(SV),
13841 /*Volatile=*/false,
13843 /*WriteMem=*/true);
13844 Chain = VAARG.getValue(1);
13846 // Load the next argument and return it
13847 return DAG.getLoad(ArgVT, dl,
13850 MachinePointerInfo(),
13851 false, false, false, 0);
13854 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
13855 SelectionDAG &DAG) {
13856 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
13857 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
13858 SDValue Chain = Op.getOperand(0);
13859 SDValue DstPtr = Op.getOperand(1);
13860 SDValue SrcPtr = Op.getOperand(2);
13861 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
13862 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
13865 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
13866 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
13868 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
13871 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
13872 // amount is a constant. Takes immediate version of shift as input.
13873 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
13874 SDValue SrcOp, uint64_t ShiftAmt,
13875 SelectionDAG &DAG) {
13876 MVT ElementType = VT.getVectorElementType();
13878 // Fold this packed shift into its first operand if ShiftAmt is 0.
13882 // Check for ShiftAmt >= element width
13883 if (ShiftAmt >= ElementType.getSizeInBits()) {
13884 if (Opc == X86ISD::VSRAI)
13885 ShiftAmt = ElementType.getSizeInBits() - 1;
13887 return DAG.getConstant(0, VT);
13890 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
13891 && "Unknown target vector shift-by-constant node");
13893 // Fold this packed vector shift into a build vector if SrcOp is a
13894 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
13895 if (VT == SrcOp.getSimpleValueType() &&
13896 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
13897 SmallVector<SDValue, 8> Elts;
13898 unsigned NumElts = SrcOp->getNumOperands();
13899 ConstantSDNode *ND;
13902 default: llvm_unreachable(nullptr);
13903 case X86ISD::VSHLI:
13904 for (unsigned i=0; i!=NumElts; ++i) {
13905 SDValue CurrentOp = SrcOp->getOperand(i);
13906 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13907 Elts.push_back(CurrentOp);
13910 ND = cast<ConstantSDNode>(CurrentOp);
13911 const APInt &C = ND->getAPIntValue();
13912 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
13915 case X86ISD::VSRLI:
13916 for (unsigned i=0; i!=NumElts; ++i) {
13917 SDValue CurrentOp = SrcOp->getOperand(i);
13918 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13919 Elts.push_back(CurrentOp);
13922 ND = cast<ConstantSDNode>(CurrentOp);
13923 const APInt &C = ND->getAPIntValue();
13924 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
13927 case X86ISD::VSRAI:
13928 for (unsigned i=0; i!=NumElts; ++i) {
13929 SDValue CurrentOp = SrcOp->getOperand(i);
13930 if (CurrentOp->getOpcode() == ISD::UNDEF) {
13931 Elts.push_back(CurrentOp);
13934 ND = cast<ConstantSDNode>(CurrentOp);
13935 const APInt &C = ND->getAPIntValue();
13936 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
13941 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
13944 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
13947 // getTargetVShiftNode - Handle vector element shifts where the shift amount
13948 // may or may not be a constant. Takes immediate version of shift as input.
13949 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
13950 SDValue SrcOp, SDValue ShAmt,
13951 SelectionDAG &DAG) {
13952 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
13954 // Catch shift-by-constant.
13955 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
13956 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
13957 CShAmt->getZExtValue(), DAG);
13959 // Change opcode to non-immediate version
13961 default: llvm_unreachable("Unknown target vector shift node");
13962 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
13963 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
13964 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
13967 // Need to build a vector containing shift amount
13968 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
13971 ShOps[1] = DAG.getConstant(0, MVT::i32);
13972 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
13973 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, ShOps);
13975 // The return type has to be a 128-bit type with the same element
13976 // type as the input type.
13977 MVT EltVT = VT.getVectorElementType();
13978 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
13980 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
13981 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
13984 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
13986 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
13988 default: return SDValue(); // Don't custom lower most intrinsics.
13989 // Comparison intrinsics.
13990 case Intrinsic::x86_sse_comieq_ss:
13991 case Intrinsic::x86_sse_comilt_ss:
13992 case Intrinsic::x86_sse_comile_ss:
13993 case Intrinsic::x86_sse_comigt_ss:
13994 case Intrinsic::x86_sse_comige_ss:
13995 case Intrinsic::x86_sse_comineq_ss:
13996 case Intrinsic::x86_sse_ucomieq_ss:
13997 case Intrinsic::x86_sse_ucomilt_ss:
13998 case Intrinsic::x86_sse_ucomile_ss:
13999 case Intrinsic::x86_sse_ucomigt_ss:
14000 case Intrinsic::x86_sse_ucomige_ss:
14001 case Intrinsic::x86_sse_ucomineq_ss:
14002 case Intrinsic::x86_sse2_comieq_sd:
14003 case Intrinsic::x86_sse2_comilt_sd:
14004 case Intrinsic::x86_sse2_comile_sd:
14005 case Intrinsic::x86_sse2_comigt_sd:
14006 case Intrinsic::x86_sse2_comige_sd:
14007 case Intrinsic::x86_sse2_comineq_sd:
14008 case Intrinsic::x86_sse2_ucomieq_sd:
14009 case Intrinsic::x86_sse2_ucomilt_sd:
14010 case Intrinsic::x86_sse2_ucomile_sd:
14011 case Intrinsic::x86_sse2_ucomigt_sd:
14012 case Intrinsic::x86_sse2_ucomige_sd:
14013 case Intrinsic::x86_sse2_ucomineq_sd: {
14017 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14018 case Intrinsic::x86_sse_comieq_ss:
14019 case Intrinsic::x86_sse2_comieq_sd:
14020 Opc = X86ISD::COMI;
14023 case Intrinsic::x86_sse_comilt_ss:
14024 case Intrinsic::x86_sse2_comilt_sd:
14025 Opc = X86ISD::COMI;
14028 case Intrinsic::x86_sse_comile_ss:
14029 case Intrinsic::x86_sse2_comile_sd:
14030 Opc = X86ISD::COMI;
14033 case Intrinsic::x86_sse_comigt_ss:
14034 case Intrinsic::x86_sse2_comigt_sd:
14035 Opc = X86ISD::COMI;
14038 case Intrinsic::x86_sse_comige_ss:
14039 case Intrinsic::x86_sse2_comige_sd:
14040 Opc = X86ISD::COMI;
14043 case Intrinsic::x86_sse_comineq_ss:
14044 case Intrinsic::x86_sse2_comineq_sd:
14045 Opc = X86ISD::COMI;
14048 case Intrinsic::x86_sse_ucomieq_ss:
14049 case Intrinsic::x86_sse2_ucomieq_sd:
14050 Opc = X86ISD::UCOMI;
14053 case Intrinsic::x86_sse_ucomilt_ss:
14054 case Intrinsic::x86_sse2_ucomilt_sd:
14055 Opc = X86ISD::UCOMI;
14058 case Intrinsic::x86_sse_ucomile_ss:
14059 case Intrinsic::x86_sse2_ucomile_sd:
14060 Opc = X86ISD::UCOMI;
14063 case Intrinsic::x86_sse_ucomigt_ss:
14064 case Intrinsic::x86_sse2_ucomigt_sd:
14065 Opc = X86ISD::UCOMI;
14068 case Intrinsic::x86_sse_ucomige_ss:
14069 case Intrinsic::x86_sse2_ucomige_sd:
14070 Opc = X86ISD::UCOMI;
14073 case Intrinsic::x86_sse_ucomineq_ss:
14074 case Intrinsic::x86_sse2_ucomineq_sd:
14075 Opc = X86ISD::UCOMI;
14080 SDValue LHS = Op.getOperand(1);
14081 SDValue RHS = Op.getOperand(2);
14082 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
14083 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
14084 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
14085 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14086 DAG.getConstant(X86CC, MVT::i8), Cond);
14087 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14090 // Arithmetic intrinsics.
14091 case Intrinsic::x86_sse2_pmulu_dq:
14092 case Intrinsic::x86_avx2_pmulu_dq:
14093 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
14094 Op.getOperand(1), Op.getOperand(2));
14096 case Intrinsic::x86_sse41_pmuldq:
14097 case Intrinsic::x86_avx2_pmul_dq:
14098 return DAG.getNode(X86ISD::PMULDQ, dl, Op.getValueType(),
14099 Op.getOperand(1), Op.getOperand(2));
14101 case Intrinsic::x86_sse2_pmulhu_w:
14102 case Intrinsic::x86_avx2_pmulhu_w:
14103 return DAG.getNode(ISD::MULHU, dl, Op.getValueType(),
14104 Op.getOperand(1), Op.getOperand(2));
14106 case Intrinsic::x86_sse2_pmulh_w:
14107 case Intrinsic::x86_avx2_pmulh_w:
14108 return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
14109 Op.getOperand(1), Op.getOperand(2));
14111 // SSE2/AVX2 sub with unsigned saturation intrinsics
14112 case Intrinsic::x86_sse2_psubus_b:
14113 case Intrinsic::x86_sse2_psubus_w:
14114 case Intrinsic::x86_avx2_psubus_b:
14115 case Intrinsic::x86_avx2_psubus_w:
14116 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
14117 Op.getOperand(1), Op.getOperand(2));
14119 // SSE3/AVX horizontal add/sub intrinsics
14120 case Intrinsic::x86_sse3_hadd_ps:
14121 case Intrinsic::x86_sse3_hadd_pd:
14122 case Intrinsic::x86_avx_hadd_ps_256:
14123 case Intrinsic::x86_avx_hadd_pd_256:
14124 case Intrinsic::x86_sse3_hsub_ps:
14125 case Intrinsic::x86_sse3_hsub_pd:
14126 case Intrinsic::x86_avx_hsub_ps_256:
14127 case Intrinsic::x86_avx_hsub_pd_256:
14128 case Intrinsic::x86_ssse3_phadd_w_128:
14129 case Intrinsic::x86_ssse3_phadd_d_128:
14130 case Intrinsic::x86_avx2_phadd_w:
14131 case Intrinsic::x86_avx2_phadd_d:
14132 case Intrinsic::x86_ssse3_phsub_w_128:
14133 case Intrinsic::x86_ssse3_phsub_d_128:
14134 case Intrinsic::x86_avx2_phsub_w:
14135 case Intrinsic::x86_avx2_phsub_d: {
14138 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14139 case Intrinsic::x86_sse3_hadd_ps:
14140 case Intrinsic::x86_sse3_hadd_pd:
14141 case Intrinsic::x86_avx_hadd_ps_256:
14142 case Intrinsic::x86_avx_hadd_pd_256:
14143 Opcode = X86ISD::FHADD;
14145 case Intrinsic::x86_sse3_hsub_ps:
14146 case Intrinsic::x86_sse3_hsub_pd:
14147 case Intrinsic::x86_avx_hsub_ps_256:
14148 case Intrinsic::x86_avx_hsub_pd_256:
14149 Opcode = X86ISD::FHSUB;
14151 case Intrinsic::x86_ssse3_phadd_w_128:
14152 case Intrinsic::x86_ssse3_phadd_d_128:
14153 case Intrinsic::x86_avx2_phadd_w:
14154 case Intrinsic::x86_avx2_phadd_d:
14155 Opcode = X86ISD::HADD;
14157 case Intrinsic::x86_ssse3_phsub_w_128:
14158 case Intrinsic::x86_ssse3_phsub_d_128:
14159 case Intrinsic::x86_avx2_phsub_w:
14160 case Intrinsic::x86_avx2_phsub_d:
14161 Opcode = X86ISD::HSUB;
14164 return DAG.getNode(Opcode, dl, Op.getValueType(),
14165 Op.getOperand(1), Op.getOperand(2));
14168 // SSE2/SSE41/AVX2 integer max/min intrinsics.
14169 case Intrinsic::x86_sse2_pmaxu_b:
14170 case Intrinsic::x86_sse41_pmaxuw:
14171 case Intrinsic::x86_sse41_pmaxud:
14172 case Intrinsic::x86_avx2_pmaxu_b:
14173 case Intrinsic::x86_avx2_pmaxu_w:
14174 case Intrinsic::x86_avx2_pmaxu_d:
14175 case Intrinsic::x86_sse2_pminu_b:
14176 case Intrinsic::x86_sse41_pminuw:
14177 case Intrinsic::x86_sse41_pminud:
14178 case Intrinsic::x86_avx2_pminu_b:
14179 case Intrinsic::x86_avx2_pminu_w:
14180 case Intrinsic::x86_avx2_pminu_d:
14181 case Intrinsic::x86_sse41_pmaxsb:
14182 case Intrinsic::x86_sse2_pmaxs_w:
14183 case Intrinsic::x86_sse41_pmaxsd:
14184 case Intrinsic::x86_avx2_pmaxs_b:
14185 case Intrinsic::x86_avx2_pmaxs_w:
14186 case Intrinsic::x86_avx2_pmaxs_d:
14187 case Intrinsic::x86_sse41_pminsb:
14188 case Intrinsic::x86_sse2_pmins_w:
14189 case Intrinsic::x86_sse41_pminsd:
14190 case Intrinsic::x86_avx2_pmins_b:
14191 case Intrinsic::x86_avx2_pmins_w:
14192 case Intrinsic::x86_avx2_pmins_d: {
14195 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14196 case Intrinsic::x86_sse2_pmaxu_b:
14197 case Intrinsic::x86_sse41_pmaxuw:
14198 case Intrinsic::x86_sse41_pmaxud:
14199 case Intrinsic::x86_avx2_pmaxu_b:
14200 case Intrinsic::x86_avx2_pmaxu_w:
14201 case Intrinsic::x86_avx2_pmaxu_d:
14202 Opcode = X86ISD::UMAX;
14204 case Intrinsic::x86_sse2_pminu_b:
14205 case Intrinsic::x86_sse41_pminuw:
14206 case Intrinsic::x86_sse41_pminud:
14207 case Intrinsic::x86_avx2_pminu_b:
14208 case Intrinsic::x86_avx2_pminu_w:
14209 case Intrinsic::x86_avx2_pminu_d:
14210 Opcode = X86ISD::UMIN;
14212 case Intrinsic::x86_sse41_pmaxsb:
14213 case Intrinsic::x86_sse2_pmaxs_w:
14214 case Intrinsic::x86_sse41_pmaxsd:
14215 case Intrinsic::x86_avx2_pmaxs_b:
14216 case Intrinsic::x86_avx2_pmaxs_w:
14217 case Intrinsic::x86_avx2_pmaxs_d:
14218 Opcode = X86ISD::SMAX;
14220 case Intrinsic::x86_sse41_pminsb:
14221 case Intrinsic::x86_sse2_pmins_w:
14222 case Intrinsic::x86_sse41_pminsd:
14223 case Intrinsic::x86_avx2_pmins_b:
14224 case Intrinsic::x86_avx2_pmins_w:
14225 case Intrinsic::x86_avx2_pmins_d:
14226 Opcode = X86ISD::SMIN;
14229 return DAG.getNode(Opcode, dl, Op.getValueType(),
14230 Op.getOperand(1), Op.getOperand(2));
14233 // SSE/SSE2/AVX floating point max/min intrinsics.
14234 case Intrinsic::x86_sse_max_ps:
14235 case Intrinsic::x86_sse2_max_pd:
14236 case Intrinsic::x86_avx_max_ps_256:
14237 case Intrinsic::x86_avx_max_pd_256:
14238 case Intrinsic::x86_sse_min_ps:
14239 case Intrinsic::x86_sse2_min_pd:
14240 case Intrinsic::x86_avx_min_ps_256:
14241 case Intrinsic::x86_avx_min_pd_256: {
14244 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14245 case Intrinsic::x86_sse_max_ps:
14246 case Intrinsic::x86_sse2_max_pd:
14247 case Intrinsic::x86_avx_max_ps_256:
14248 case Intrinsic::x86_avx_max_pd_256:
14249 Opcode = X86ISD::FMAX;
14251 case Intrinsic::x86_sse_min_ps:
14252 case Intrinsic::x86_sse2_min_pd:
14253 case Intrinsic::x86_avx_min_ps_256:
14254 case Intrinsic::x86_avx_min_pd_256:
14255 Opcode = X86ISD::FMIN;
14258 return DAG.getNode(Opcode, dl, Op.getValueType(),
14259 Op.getOperand(1), Op.getOperand(2));
14262 // AVX2 variable shift intrinsics
14263 case Intrinsic::x86_avx2_psllv_d:
14264 case Intrinsic::x86_avx2_psllv_q:
14265 case Intrinsic::x86_avx2_psllv_d_256:
14266 case Intrinsic::x86_avx2_psllv_q_256:
14267 case Intrinsic::x86_avx2_psrlv_d:
14268 case Intrinsic::x86_avx2_psrlv_q:
14269 case Intrinsic::x86_avx2_psrlv_d_256:
14270 case Intrinsic::x86_avx2_psrlv_q_256:
14271 case Intrinsic::x86_avx2_psrav_d:
14272 case Intrinsic::x86_avx2_psrav_d_256: {
14275 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14276 case Intrinsic::x86_avx2_psllv_d:
14277 case Intrinsic::x86_avx2_psllv_q:
14278 case Intrinsic::x86_avx2_psllv_d_256:
14279 case Intrinsic::x86_avx2_psllv_q_256:
14282 case Intrinsic::x86_avx2_psrlv_d:
14283 case Intrinsic::x86_avx2_psrlv_q:
14284 case Intrinsic::x86_avx2_psrlv_d_256:
14285 case Intrinsic::x86_avx2_psrlv_q_256:
14288 case Intrinsic::x86_avx2_psrav_d:
14289 case Intrinsic::x86_avx2_psrav_d_256:
14293 return DAG.getNode(Opcode, dl, Op.getValueType(),
14294 Op.getOperand(1), Op.getOperand(2));
14297 case Intrinsic::x86_sse2_packssdw_128:
14298 case Intrinsic::x86_sse2_packsswb_128:
14299 case Intrinsic::x86_avx2_packssdw:
14300 case Intrinsic::x86_avx2_packsswb:
14301 return DAG.getNode(X86ISD::PACKSS, dl, Op.getValueType(),
14302 Op.getOperand(1), Op.getOperand(2));
14304 case Intrinsic::x86_sse2_packuswb_128:
14305 case Intrinsic::x86_sse41_packusdw:
14306 case Intrinsic::x86_avx2_packuswb:
14307 case Intrinsic::x86_avx2_packusdw:
14308 return DAG.getNode(X86ISD::PACKUS, dl, Op.getValueType(),
14309 Op.getOperand(1), Op.getOperand(2));
14311 case Intrinsic::x86_ssse3_pshuf_b_128:
14312 case Intrinsic::x86_avx2_pshuf_b:
14313 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
14314 Op.getOperand(1), Op.getOperand(2));
14316 case Intrinsic::x86_sse2_pshuf_d:
14317 return DAG.getNode(X86ISD::PSHUFD, dl, Op.getValueType(),
14318 Op.getOperand(1), Op.getOperand(2));
14320 case Intrinsic::x86_sse2_pshufl_w:
14321 return DAG.getNode(X86ISD::PSHUFLW, dl, Op.getValueType(),
14322 Op.getOperand(1), Op.getOperand(2));
14324 case Intrinsic::x86_sse2_pshufh_w:
14325 return DAG.getNode(X86ISD::PSHUFHW, dl, Op.getValueType(),
14326 Op.getOperand(1), Op.getOperand(2));
14328 case Intrinsic::x86_ssse3_psign_b_128:
14329 case Intrinsic::x86_ssse3_psign_w_128:
14330 case Intrinsic::x86_ssse3_psign_d_128:
14331 case Intrinsic::x86_avx2_psign_b:
14332 case Intrinsic::x86_avx2_psign_w:
14333 case Intrinsic::x86_avx2_psign_d:
14334 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
14335 Op.getOperand(1), Op.getOperand(2));
14337 case Intrinsic::x86_sse41_insertps:
14338 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
14339 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14341 case Intrinsic::x86_avx_vperm2f128_ps_256:
14342 case Intrinsic::x86_avx_vperm2f128_pd_256:
14343 case Intrinsic::x86_avx_vperm2f128_si_256:
14344 case Intrinsic::x86_avx2_vperm2i128:
14345 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
14346 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
14348 case Intrinsic::x86_avx2_permd:
14349 case Intrinsic::x86_avx2_permps:
14350 // Operands intentionally swapped. Mask is last operand to intrinsic,
14351 // but second operand for node/instruction.
14352 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
14353 Op.getOperand(2), Op.getOperand(1));
14355 case Intrinsic::x86_sse_sqrt_ps:
14356 case Intrinsic::x86_sse2_sqrt_pd:
14357 case Intrinsic::x86_avx_sqrt_ps_256:
14358 case Intrinsic::x86_avx_sqrt_pd_256:
14359 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
14361 // ptest and testp intrinsics. The intrinsic these come from are designed to
14362 // return an integer value, not just an instruction so lower it to the ptest
14363 // or testp pattern and a setcc for the result.
14364 case Intrinsic::x86_sse41_ptestz:
14365 case Intrinsic::x86_sse41_ptestc:
14366 case Intrinsic::x86_sse41_ptestnzc:
14367 case Intrinsic::x86_avx_ptestz_256:
14368 case Intrinsic::x86_avx_ptestc_256:
14369 case Intrinsic::x86_avx_ptestnzc_256:
14370 case Intrinsic::x86_avx_vtestz_ps:
14371 case Intrinsic::x86_avx_vtestc_ps:
14372 case Intrinsic::x86_avx_vtestnzc_ps:
14373 case Intrinsic::x86_avx_vtestz_pd:
14374 case Intrinsic::x86_avx_vtestc_pd:
14375 case Intrinsic::x86_avx_vtestnzc_pd:
14376 case Intrinsic::x86_avx_vtestz_ps_256:
14377 case Intrinsic::x86_avx_vtestc_ps_256:
14378 case Intrinsic::x86_avx_vtestnzc_ps_256:
14379 case Intrinsic::x86_avx_vtestz_pd_256:
14380 case Intrinsic::x86_avx_vtestc_pd_256:
14381 case Intrinsic::x86_avx_vtestnzc_pd_256: {
14382 bool IsTestPacked = false;
14385 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
14386 case Intrinsic::x86_avx_vtestz_ps:
14387 case Intrinsic::x86_avx_vtestz_pd:
14388 case Intrinsic::x86_avx_vtestz_ps_256:
14389 case Intrinsic::x86_avx_vtestz_pd_256:
14390 IsTestPacked = true; // Fallthrough
14391 case Intrinsic::x86_sse41_ptestz:
14392 case Intrinsic::x86_avx_ptestz_256:
14394 X86CC = X86::COND_E;
14396 case Intrinsic::x86_avx_vtestc_ps:
14397 case Intrinsic::x86_avx_vtestc_pd:
14398 case Intrinsic::x86_avx_vtestc_ps_256:
14399 case Intrinsic::x86_avx_vtestc_pd_256:
14400 IsTestPacked = true; // Fallthrough
14401 case Intrinsic::x86_sse41_ptestc:
14402 case Intrinsic::x86_avx_ptestc_256:
14404 X86CC = X86::COND_B;
14406 case Intrinsic::x86_avx_vtestnzc_ps:
14407 case Intrinsic::x86_avx_vtestnzc_pd:
14408 case Intrinsic::x86_avx_vtestnzc_ps_256:
14409 case Intrinsic::x86_avx_vtestnzc_pd_256:
14410 IsTestPacked = true; // Fallthrough
14411 case Intrinsic::x86_sse41_ptestnzc:
14412 case Intrinsic::x86_avx_ptestnzc_256:
14414 X86CC = X86::COND_A;
14418 SDValue LHS = Op.getOperand(1);
14419 SDValue RHS = Op.getOperand(2);
14420 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
14421 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
14422 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14423 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
14424 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14426 case Intrinsic::x86_avx512_kortestz_w:
14427 case Intrinsic::x86_avx512_kortestc_w: {
14428 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
14429 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
14430 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
14431 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
14432 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
14433 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
14434 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14437 // SSE/AVX shift intrinsics
14438 case Intrinsic::x86_sse2_psll_w:
14439 case Intrinsic::x86_sse2_psll_d:
14440 case Intrinsic::x86_sse2_psll_q:
14441 case Intrinsic::x86_avx2_psll_w:
14442 case Intrinsic::x86_avx2_psll_d:
14443 case Intrinsic::x86_avx2_psll_q:
14444 case Intrinsic::x86_sse2_psrl_w:
14445 case Intrinsic::x86_sse2_psrl_d:
14446 case Intrinsic::x86_sse2_psrl_q:
14447 case Intrinsic::x86_avx2_psrl_w:
14448 case Intrinsic::x86_avx2_psrl_d:
14449 case Intrinsic::x86_avx2_psrl_q:
14450 case Intrinsic::x86_sse2_psra_w:
14451 case Intrinsic::x86_sse2_psra_d:
14452 case Intrinsic::x86_avx2_psra_w:
14453 case Intrinsic::x86_avx2_psra_d: {
14456 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14457 case Intrinsic::x86_sse2_psll_w:
14458 case Intrinsic::x86_sse2_psll_d:
14459 case Intrinsic::x86_sse2_psll_q:
14460 case Intrinsic::x86_avx2_psll_w:
14461 case Intrinsic::x86_avx2_psll_d:
14462 case Intrinsic::x86_avx2_psll_q:
14463 Opcode = X86ISD::VSHL;
14465 case Intrinsic::x86_sse2_psrl_w:
14466 case Intrinsic::x86_sse2_psrl_d:
14467 case Intrinsic::x86_sse2_psrl_q:
14468 case Intrinsic::x86_avx2_psrl_w:
14469 case Intrinsic::x86_avx2_psrl_d:
14470 case Intrinsic::x86_avx2_psrl_q:
14471 Opcode = X86ISD::VSRL;
14473 case Intrinsic::x86_sse2_psra_w:
14474 case Intrinsic::x86_sse2_psra_d:
14475 case Intrinsic::x86_avx2_psra_w:
14476 case Intrinsic::x86_avx2_psra_d:
14477 Opcode = X86ISD::VSRA;
14480 return DAG.getNode(Opcode, dl, Op.getValueType(),
14481 Op.getOperand(1), Op.getOperand(2));
14484 // SSE/AVX immediate shift intrinsics
14485 case Intrinsic::x86_sse2_pslli_w:
14486 case Intrinsic::x86_sse2_pslli_d:
14487 case Intrinsic::x86_sse2_pslli_q:
14488 case Intrinsic::x86_avx2_pslli_w:
14489 case Intrinsic::x86_avx2_pslli_d:
14490 case Intrinsic::x86_avx2_pslli_q:
14491 case Intrinsic::x86_sse2_psrli_w:
14492 case Intrinsic::x86_sse2_psrli_d:
14493 case Intrinsic::x86_sse2_psrli_q:
14494 case Intrinsic::x86_avx2_psrli_w:
14495 case Intrinsic::x86_avx2_psrli_d:
14496 case Intrinsic::x86_avx2_psrli_q:
14497 case Intrinsic::x86_sse2_psrai_w:
14498 case Intrinsic::x86_sse2_psrai_d:
14499 case Intrinsic::x86_avx2_psrai_w:
14500 case Intrinsic::x86_avx2_psrai_d: {
14503 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14504 case Intrinsic::x86_sse2_pslli_w:
14505 case Intrinsic::x86_sse2_pslli_d:
14506 case Intrinsic::x86_sse2_pslli_q:
14507 case Intrinsic::x86_avx2_pslli_w:
14508 case Intrinsic::x86_avx2_pslli_d:
14509 case Intrinsic::x86_avx2_pslli_q:
14510 Opcode = X86ISD::VSHLI;
14512 case Intrinsic::x86_sse2_psrli_w:
14513 case Intrinsic::x86_sse2_psrli_d:
14514 case Intrinsic::x86_sse2_psrli_q:
14515 case Intrinsic::x86_avx2_psrli_w:
14516 case Intrinsic::x86_avx2_psrli_d:
14517 case Intrinsic::x86_avx2_psrli_q:
14518 Opcode = X86ISD::VSRLI;
14520 case Intrinsic::x86_sse2_psrai_w:
14521 case Intrinsic::x86_sse2_psrai_d:
14522 case Intrinsic::x86_avx2_psrai_w:
14523 case Intrinsic::x86_avx2_psrai_d:
14524 Opcode = X86ISD::VSRAI;
14527 return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
14528 Op.getOperand(1), Op.getOperand(2), DAG);
14531 case Intrinsic::x86_sse42_pcmpistria128:
14532 case Intrinsic::x86_sse42_pcmpestria128:
14533 case Intrinsic::x86_sse42_pcmpistric128:
14534 case Intrinsic::x86_sse42_pcmpestric128:
14535 case Intrinsic::x86_sse42_pcmpistrio128:
14536 case Intrinsic::x86_sse42_pcmpestrio128:
14537 case Intrinsic::x86_sse42_pcmpistris128:
14538 case Intrinsic::x86_sse42_pcmpestris128:
14539 case Intrinsic::x86_sse42_pcmpistriz128:
14540 case Intrinsic::x86_sse42_pcmpestriz128: {
14544 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14545 case Intrinsic::x86_sse42_pcmpistria128:
14546 Opcode = X86ISD::PCMPISTRI;
14547 X86CC = X86::COND_A;
14549 case Intrinsic::x86_sse42_pcmpestria128:
14550 Opcode = X86ISD::PCMPESTRI;
14551 X86CC = X86::COND_A;
14553 case Intrinsic::x86_sse42_pcmpistric128:
14554 Opcode = X86ISD::PCMPISTRI;
14555 X86CC = X86::COND_B;
14557 case Intrinsic::x86_sse42_pcmpestric128:
14558 Opcode = X86ISD::PCMPESTRI;
14559 X86CC = X86::COND_B;
14561 case Intrinsic::x86_sse42_pcmpistrio128:
14562 Opcode = X86ISD::PCMPISTRI;
14563 X86CC = X86::COND_O;
14565 case Intrinsic::x86_sse42_pcmpestrio128:
14566 Opcode = X86ISD::PCMPESTRI;
14567 X86CC = X86::COND_O;
14569 case Intrinsic::x86_sse42_pcmpistris128:
14570 Opcode = X86ISD::PCMPISTRI;
14571 X86CC = X86::COND_S;
14573 case Intrinsic::x86_sse42_pcmpestris128:
14574 Opcode = X86ISD::PCMPESTRI;
14575 X86CC = X86::COND_S;
14577 case Intrinsic::x86_sse42_pcmpistriz128:
14578 Opcode = X86ISD::PCMPISTRI;
14579 X86CC = X86::COND_E;
14581 case Intrinsic::x86_sse42_pcmpestriz128:
14582 Opcode = X86ISD::PCMPESTRI;
14583 X86CC = X86::COND_E;
14586 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14587 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14588 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
14589 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14590 DAG.getConstant(X86CC, MVT::i8),
14591 SDValue(PCMP.getNode(), 1));
14592 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
14595 case Intrinsic::x86_sse42_pcmpistri128:
14596 case Intrinsic::x86_sse42_pcmpestri128: {
14598 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
14599 Opcode = X86ISD::PCMPISTRI;
14601 Opcode = X86ISD::PCMPESTRI;
14603 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
14604 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14605 return DAG.getNode(Opcode, dl, VTs, NewOps);
14607 case Intrinsic::x86_fma_vfmadd_ps:
14608 case Intrinsic::x86_fma_vfmadd_pd:
14609 case Intrinsic::x86_fma_vfmsub_ps:
14610 case Intrinsic::x86_fma_vfmsub_pd:
14611 case Intrinsic::x86_fma_vfnmadd_ps:
14612 case Intrinsic::x86_fma_vfnmadd_pd:
14613 case Intrinsic::x86_fma_vfnmsub_ps:
14614 case Intrinsic::x86_fma_vfnmsub_pd:
14615 case Intrinsic::x86_fma_vfmaddsub_ps:
14616 case Intrinsic::x86_fma_vfmaddsub_pd:
14617 case Intrinsic::x86_fma_vfmsubadd_ps:
14618 case Intrinsic::x86_fma_vfmsubadd_pd:
14619 case Intrinsic::x86_fma_vfmadd_ps_256:
14620 case Intrinsic::x86_fma_vfmadd_pd_256:
14621 case Intrinsic::x86_fma_vfmsub_ps_256:
14622 case Intrinsic::x86_fma_vfmsub_pd_256:
14623 case Intrinsic::x86_fma_vfnmadd_ps_256:
14624 case Intrinsic::x86_fma_vfnmadd_pd_256:
14625 case Intrinsic::x86_fma_vfnmsub_ps_256:
14626 case Intrinsic::x86_fma_vfnmsub_pd_256:
14627 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14628 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14629 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14630 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14631 case Intrinsic::x86_fma_vfmadd_ps_512:
14632 case Intrinsic::x86_fma_vfmadd_pd_512:
14633 case Intrinsic::x86_fma_vfmsub_ps_512:
14634 case Intrinsic::x86_fma_vfmsub_pd_512:
14635 case Intrinsic::x86_fma_vfnmadd_ps_512:
14636 case Intrinsic::x86_fma_vfnmadd_pd_512:
14637 case Intrinsic::x86_fma_vfnmsub_ps_512:
14638 case Intrinsic::x86_fma_vfnmsub_pd_512:
14639 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14640 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14641 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14642 case Intrinsic::x86_fma_vfmsubadd_pd_512: {
14645 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14646 case Intrinsic::x86_fma_vfmadd_ps:
14647 case Intrinsic::x86_fma_vfmadd_pd:
14648 case Intrinsic::x86_fma_vfmadd_ps_256:
14649 case Intrinsic::x86_fma_vfmadd_pd_256:
14650 case Intrinsic::x86_fma_vfmadd_ps_512:
14651 case Intrinsic::x86_fma_vfmadd_pd_512:
14652 Opc = X86ISD::FMADD;
14654 case Intrinsic::x86_fma_vfmsub_ps:
14655 case Intrinsic::x86_fma_vfmsub_pd:
14656 case Intrinsic::x86_fma_vfmsub_ps_256:
14657 case Intrinsic::x86_fma_vfmsub_pd_256:
14658 case Intrinsic::x86_fma_vfmsub_ps_512:
14659 case Intrinsic::x86_fma_vfmsub_pd_512:
14660 Opc = X86ISD::FMSUB;
14662 case Intrinsic::x86_fma_vfnmadd_ps:
14663 case Intrinsic::x86_fma_vfnmadd_pd:
14664 case Intrinsic::x86_fma_vfnmadd_ps_256:
14665 case Intrinsic::x86_fma_vfnmadd_pd_256:
14666 case Intrinsic::x86_fma_vfnmadd_ps_512:
14667 case Intrinsic::x86_fma_vfnmadd_pd_512:
14668 Opc = X86ISD::FNMADD;
14670 case Intrinsic::x86_fma_vfnmsub_ps:
14671 case Intrinsic::x86_fma_vfnmsub_pd:
14672 case Intrinsic::x86_fma_vfnmsub_ps_256:
14673 case Intrinsic::x86_fma_vfnmsub_pd_256:
14674 case Intrinsic::x86_fma_vfnmsub_ps_512:
14675 case Intrinsic::x86_fma_vfnmsub_pd_512:
14676 Opc = X86ISD::FNMSUB;
14678 case Intrinsic::x86_fma_vfmaddsub_ps:
14679 case Intrinsic::x86_fma_vfmaddsub_pd:
14680 case Intrinsic::x86_fma_vfmaddsub_ps_256:
14681 case Intrinsic::x86_fma_vfmaddsub_pd_256:
14682 case Intrinsic::x86_fma_vfmaddsub_ps_512:
14683 case Intrinsic::x86_fma_vfmaddsub_pd_512:
14684 Opc = X86ISD::FMADDSUB;
14686 case Intrinsic::x86_fma_vfmsubadd_ps:
14687 case Intrinsic::x86_fma_vfmsubadd_pd:
14688 case Intrinsic::x86_fma_vfmsubadd_ps_256:
14689 case Intrinsic::x86_fma_vfmsubadd_pd_256:
14690 case Intrinsic::x86_fma_vfmsubadd_ps_512:
14691 case Intrinsic::x86_fma_vfmsubadd_pd_512:
14692 Opc = X86ISD::FMSUBADD;
14696 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
14697 Op.getOperand(2), Op.getOperand(3));
14702 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14703 SDValue Src, SDValue Mask, SDValue Base,
14704 SDValue Index, SDValue ScaleOp, SDValue Chain,
14705 const X86Subtarget * Subtarget) {
14707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14708 assert(C && "Invalid scale type");
14709 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14710 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14711 Index.getSimpleValueType().getVectorNumElements());
14713 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14715 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14717 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14718 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
14719 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14720 SDValue Segment = DAG.getRegister(0, MVT::i32);
14721 if (Src.getOpcode() == ISD::UNDEF)
14722 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
14723 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14724 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14725 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
14726 return DAG.getMergeValues(RetOps, dl);
14729 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14730 SDValue Src, SDValue Mask, SDValue Base,
14731 SDValue Index, SDValue ScaleOp, SDValue Chain) {
14733 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14734 assert(C && "Invalid scale type");
14735 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14736 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14737 SDValue Segment = DAG.getRegister(0, MVT::i32);
14738 EVT MaskVT = MVT::getVectorVT(MVT::i1,
14739 Index.getSimpleValueType().getVectorNumElements());
14741 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14743 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14745 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14746 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
14747 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
14748 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
14749 return SDValue(Res, 1);
14752 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
14753 SDValue Mask, SDValue Base, SDValue Index,
14754 SDValue ScaleOp, SDValue Chain) {
14756 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
14757 assert(C && "Invalid scale type");
14758 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
14759 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
14760 SDValue Segment = DAG.getRegister(0, MVT::i32);
14762 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
14764 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
14766 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
14768 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
14769 //SDVTList VTs = DAG.getVTList(MVT::Other);
14770 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
14771 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
14772 return SDValue(Res, 0);
14775 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
14776 // read performance monitor counters (x86_rdpmc).
14777 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
14778 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14779 SmallVectorImpl<SDValue> &Results) {
14780 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14781 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14784 // The ECX register is used to select the index of the performance counter
14786 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
14788 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
14790 // Reads the content of a 64-bit performance counter and returns it in the
14791 // registers EDX:EAX.
14792 if (Subtarget->is64Bit()) {
14793 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14794 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14797 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14798 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14801 Chain = HI.getValue(1);
14803 if (Subtarget->is64Bit()) {
14804 // The EAX register is loaded with the low-order 32 bits. The EDX register
14805 // is loaded with the supported high-order bits of the counter.
14806 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14807 DAG.getConstant(32, MVT::i8));
14808 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14809 Results.push_back(Chain);
14813 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14814 SDValue Ops[] = { LO, HI };
14815 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14816 Results.push_back(Pair);
14817 Results.push_back(Chain);
14820 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
14821 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
14822 // also used to custom lower READCYCLECOUNTER nodes.
14823 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
14824 SelectionDAG &DAG, const X86Subtarget *Subtarget,
14825 SmallVectorImpl<SDValue> &Results) {
14826 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
14827 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
14830 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
14831 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
14832 // and the EAX register is loaded with the low-order 32 bits.
14833 if (Subtarget->is64Bit()) {
14834 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
14835 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
14838 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
14839 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
14842 SDValue Chain = HI.getValue(1);
14844 if (Opcode == X86ISD::RDTSCP_DAG) {
14845 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
14847 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
14848 // the ECX register. Add 'ecx' explicitly to the chain.
14849 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
14851 // Explicitly store the content of ECX at the location passed in input
14852 // to the 'rdtscp' intrinsic.
14853 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
14854 MachinePointerInfo(), false, false, 0);
14857 if (Subtarget->is64Bit()) {
14858 // The EDX register is loaded with the high-order 32 bits of the MSR, and
14859 // the EAX register is loaded with the low-order 32 bits.
14860 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
14861 DAG.getConstant(32, MVT::i8));
14862 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
14863 Results.push_back(Chain);
14867 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
14868 SDValue Ops[] = { LO, HI };
14869 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
14870 Results.push_back(Pair);
14871 Results.push_back(Chain);
14874 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
14875 SelectionDAG &DAG) {
14876 SmallVector<SDValue, 2> Results;
14878 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
14880 return DAG.getMergeValues(Results, DL);
14883 enum IntrinsicType {
14884 GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
14887 struct IntrinsicData {
14888 IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
14889 :Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
14890 IntrinsicType Type;
14895 std::map < unsigned, IntrinsicData> IntrMap;
14896 static void InitIntinsicsMap() {
14897 static bool Initialized = false;
14900 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14901 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14902 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
14903 IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
14904 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
14905 IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
14906 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
14907 IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
14908 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
14909 IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
14910 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
14911 IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
14912 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
14913 IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
14914 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
14915 IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
14916 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
14917 IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
14919 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
14920 IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
14921 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
14922 IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
14923 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
14924 IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
14925 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
14926 IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
14927 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
14928 IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
14929 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
14930 IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
14931 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
14932 IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
14933 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
14934 IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
14936 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
14937 IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
14938 X86::VGATHERPF1QPSm)));
14939 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
14940 IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
14941 X86::VGATHERPF1QPDm)));
14942 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
14943 IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
14944 X86::VGATHERPF1DPDm)));
14945 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
14946 IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
14947 X86::VGATHERPF1DPSm)));
14948 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
14949 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
14950 X86::VSCATTERPF1QPSm)));
14951 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
14952 IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
14953 X86::VSCATTERPF1QPDm)));
14954 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
14955 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
14956 X86::VSCATTERPF1DPDm)));
14957 IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
14958 IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
14959 X86::VSCATTERPF1DPSm)));
14960 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
14961 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14962 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
14963 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14964 IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
14965 IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
14966 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
14967 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14968 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
14969 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14970 IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
14971 IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
14972 IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
14973 IntrinsicData(XTEST, X86ISD::XTEST, 0)));
14974 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
14975 IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
14976 IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
14977 IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
14978 IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
14979 IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
14980 Initialized = true;
14983 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14984 SelectionDAG &DAG) {
14985 InitIntinsicsMap();
14986 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
14987 std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
14988 if (itr == IntrMap.end())
14992 IntrinsicData Intr = itr->second;
14993 switch(Intr.Type) {
14996 // Emit the node with the right value type.
14997 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
14998 SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
15000 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15001 // Otherwise return the value from Rand, which is always 0, casted to i32.
15002 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15003 DAG.getConstant(1, Op->getValueType(1)),
15004 DAG.getConstant(X86::COND_B, MVT::i32),
15005 SDValue(Result.getNode(), 1) };
15006 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15007 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15010 // Return { result, isValid, chain }.
15011 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15012 SDValue(Result.getNode(), 2));
15015 //gather(v1, mask, index, base, scale);
15016 SDValue Chain = Op.getOperand(0);
15017 SDValue Src = Op.getOperand(2);
15018 SDValue Base = Op.getOperand(3);
15019 SDValue Index = Op.getOperand(4);
15020 SDValue Mask = Op.getOperand(5);
15021 SDValue Scale = Op.getOperand(6);
15022 return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
15026 //scatter(base, mask, index, v1, scale);
15027 SDValue Chain = Op.getOperand(0);
15028 SDValue Base = Op.getOperand(2);
15029 SDValue Mask = Op.getOperand(3);
15030 SDValue Index = Op.getOperand(4);
15031 SDValue Src = Op.getOperand(5);
15032 SDValue Scale = Op.getOperand(6);
15033 return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
15036 SDValue Hint = Op.getOperand(6);
15038 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
15039 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
15040 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
15041 unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
15042 SDValue Chain = Op.getOperand(0);
15043 SDValue Mask = Op.getOperand(2);
15044 SDValue Index = Op.getOperand(3);
15045 SDValue Base = Op.getOperand(4);
15046 SDValue Scale = Op.getOperand(5);
15047 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15049 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15051 SmallVector<SDValue, 2> Results;
15052 getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
15053 return DAG.getMergeValues(Results, dl);
15055 // Read Performance Monitoring Counters.
15057 SmallVector<SDValue, 2> Results;
15058 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15059 return DAG.getMergeValues(Results, dl);
15061 // XTEST intrinsics.
15063 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15064 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
15065 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15066 DAG.getConstant(X86::COND_NE, MVT::i8),
15068 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15069 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15070 Ret, SDValue(InTrans.getNode(), 1));
15073 llvm_unreachable("Unknown Intrinsic Type");
15076 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15077 SelectionDAG &DAG) const {
15078 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15079 MFI->setReturnAddressIsTaken(true);
15081 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15084 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15086 EVT PtrVT = getPointerTy();
15089 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15090 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15091 DAG.getSubtarget().getRegisterInfo());
15092 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
15093 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15094 DAG.getNode(ISD::ADD, dl, PtrVT,
15095 FrameAddr, Offset),
15096 MachinePointerInfo(), false, false, false, 0);
15099 // Just load the return address.
15100 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15101 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15102 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15105 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15106 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15107 MFI->setFrameAddressIsTaken(true);
15109 EVT VT = Op.getValueType();
15110 SDLoc dl(Op); // FIXME probably not meaningful
15111 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15112 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15113 DAG.getSubtarget().getRegisterInfo());
15114 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15115 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15116 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15117 "Invalid Frame Register!");
15118 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15120 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15121 MachinePointerInfo(),
15122 false, false, false, 0);
15126 // FIXME? Maybe this could be a TableGen attribute on some registers and
15127 // this table could be generated automatically from RegInfo.
15128 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15130 unsigned Reg = StringSwitch<unsigned>(RegName)
15131 .Case("esp", X86::ESP)
15132 .Case("rsp", X86::RSP)
15136 report_fatal_error("Invalid register name global variable");
15139 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15140 SelectionDAG &DAG) const {
15141 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15142 DAG.getSubtarget().getRegisterInfo());
15143 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
15146 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15147 SDValue Chain = Op.getOperand(0);
15148 SDValue Offset = Op.getOperand(1);
15149 SDValue Handler = Op.getOperand(2);
15152 EVT PtrVT = getPointerTy();
15153 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
15154 DAG.getSubtarget().getRegisterInfo());
15155 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15156 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15157 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15158 "Invalid Frame Register!");
15159 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15160 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15162 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15163 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
15164 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15165 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15167 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15169 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15170 DAG.getRegister(StoreAddrReg, PtrVT));
15173 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15174 SelectionDAG &DAG) const {
15176 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15177 DAG.getVTList(MVT::i32, MVT::Other),
15178 Op.getOperand(0), Op.getOperand(1));
15181 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15182 SelectionDAG &DAG) const {
15184 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15185 Op.getOperand(0), Op.getOperand(1));
15188 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15189 return Op.getOperand(0);
15192 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15193 SelectionDAG &DAG) const {
15194 SDValue Root = Op.getOperand(0);
15195 SDValue Trmp = Op.getOperand(1); // trampoline
15196 SDValue FPtr = Op.getOperand(2); // nested function
15197 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15200 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15201 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
15203 if (Subtarget->is64Bit()) {
15204 SDValue OutChains[6];
15206 // Large code-model.
15207 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15208 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15210 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15211 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15213 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15215 // Load the pointer to the nested function into R11.
15216 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15217 SDValue Addr = Trmp;
15218 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15219 Addr, MachinePointerInfo(TrmpAddr),
15222 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15223 DAG.getConstant(2, MVT::i64));
15224 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15225 MachinePointerInfo(TrmpAddr, 2),
15228 // Load the 'nest' parameter value into R10.
15229 // R10 is specified in X86CallingConv.td
15230 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15231 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15232 DAG.getConstant(10, MVT::i64));
15233 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15234 Addr, MachinePointerInfo(TrmpAddr, 10),
15237 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15238 DAG.getConstant(12, MVT::i64));
15239 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15240 MachinePointerInfo(TrmpAddr, 12),
15243 // Jump to the nested function.
15244 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15245 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15246 DAG.getConstant(20, MVT::i64));
15247 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
15248 Addr, MachinePointerInfo(TrmpAddr, 20),
15251 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15252 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15253 DAG.getConstant(22, MVT::i64));
15254 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
15255 MachinePointerInfo(TrmpAddr, 22),
15258 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15260 const Function *Func =
15261 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15262 CallingConv::ID CC = Func->getCallingConv();
15267 llvm_unreachable("Unsupported calling convention");
15268 case CallingConv::C:
15269 case CallingConv::X86_StdCall: {
15270 // Pass 'nest' parameter in ECX.
15271 // Must be kept in sync with X86CallingConv.td
15272 NestReg = X86::ECX;
15274 // Check that ECX wasn't needed by an 'inreg' parameter.
15275 FunctionType *FTy = Func->getFunctionType();
15276 const AttributeSet &Attrs = Func->getAttributes();
15278 if (!Attrs.isEmpty() && !Func->isVarArg()) {
15279 unsigned InRegCount = 0;
15282 for (FunctionType::param_iterator I = FTy->param_begin(),
15283 E = FTy->param_end(); I != E; ++I, ++Idx)
15284 if (Attrs.hasAttribute(Idx, Attribute::InReg))
15285 // FIXME: should only count parameters that are lowered to integers.
15286 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
15288 if (InRegCount > 2) {
15289 report_fatal_error("Nest register in use - reduce number of inreg"
15295 case CallingConv::X86_FastCall:
15296 case CallingConv::X86_ThisCall:
15297 case CallingConv::Fast:
15298 // Pass 'nest' parameter in EAX.
15299 // Must be kept in sync with X86CallingConv.td
15300 NestReg = X86::EAX;
15304 SDValue OutChains[4];
15305 SDValue Addr, Disp;
15307 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15308 DAG.getConstant(10, MVT::i32));
15309 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
15311 // This is storing the opcode for MOV32ri.
15312 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
15313 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
15314 OutChains[0] = DAG.getStore(Root, dl,
15315 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
15316 Trmp, MachinePointerInfo(TrmpAddr),
15319 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15320 DAG.getConstant(1, MVT::i32));
15321 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
15322 MachinePointerInfo(TrmpAddr, 1),
15325 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
15326 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15327 DAG.getConstant(5, MVT::i32));
15328 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
15329 MachinePointerInfo(TrmpAddr, 5),
15332 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
15333 DAG.getConstant(6, MVT::i32));
15334 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
15335 MachinePointerInfo(TrmpAddr, 6),
15338 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15342 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
15343 SelectionDAG &DAG) const {
15345 The rounding mode is in bits 11:10 of FPSR, and has the following
15347 00 Round to nearest
15352 FLT_ROUNDS, on the other hand, expects the following:
15359 To perform the conversion, we do:
15360 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
15363 MachineFunction &MF = DAG.getMachineFunction();
15364 const TargetMachine &TM = MF.getTarget();
15365 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
15366 unsigned StackAlignment = TFI.getStackAlignment();
15367 MVT VT = Op.getSimpleValueType();
15370 // Save FP Control Word to stack slot
15371 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
15372 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
15374 MachineMemOperand *MMO =
15375 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
15376 MachineMemOperand::MOStore, 2, 2);
15378 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
15379 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
15380 DAG.getVTList(MVT::Other),
15381 Ops, MVT::i16, MMO);
15383 // Load FP Control Word from stack slot
15384 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
15385 MachinePointerInfo(), false, false, false, 0);
15387 // Transform as necessary
15389 DAG.getNode(ISD::SRL, DL, MVT::i16,
15390 DAG.getNode(ISD::AND, DL, MVT::i16,
15391 CWD, DAG.getConstant(0x800, MVT::i16)),
15392 DAG.getConstant(11, MVT::i8));
15394 DAG.getNode(ISD::SRL, DL, MVT::i16,
15395 DAG.getNode(ISD::AND, DL, MVT::i16,
15396 CWD, DAG.getConstant(0x400, MVT::i16)),
15397 DAG.getConstant(9, MVT::i8));
15400 DAG.getNode(ISD::AND, DL, MVT::i16,
15401 DAG.getNode(ISD::ADD, DL, MVT::i16,
15402 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
15403 DAG.getConstant(1, MVT::i16)),
15404 DAG.getConstant(3, MVT::i16));
15406 return DAG.getNode((VT.getSizeInBits() < 16 ?
15407 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
15410 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
15411 MVT VT = Op.getSimpleValueType();
15413 unsigned NumBits = VT.getSizeInBits();
15416 Op = Op.getOperand(0);
15417 if (VT == MVT::i8) {
15418 // Zero extend to i32 since there is not an i8 bsr.
15420 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15423 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
15424 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15425 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15427 // If src is zero (i.e. bsr sets ZF), returns NumBits.
15430 DAG.getConstant(NumBits+NumBits-1, OpVT),
15431 DAG.getConstant(X86::COND_E, MVT::i8),
15434 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
15436 // Finally xor with NumBits-1.
15437 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15440 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15444 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
15445 MVT VT = Op.getSimpleValueType();
15447 unsigned NumBits = VT.getSizeInBits();
15450 Op = Op.getOperand(0);
15451 if (VT == MVT::i8) {
15452 // Zero extend to i32 since there is not an i8 bsr.
15454 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
15457 // Issue a bsr (scan bits in reverse).
15458 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
15459 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
15461 // And xor with NumBits-1.
15462 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
15465 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
15469 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
15470 MVT VT = Op.getSimpleValueType();
15471 unsigned NumBits = VT.getSizeInBits();
15473 Op = Op.getOperand(0);
15475 // Issue a bsf (scan bits forward) which also sets EFLAGS.
15476 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
15477 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
15479 // If src is zero (i.e. bsf sets ZF), returns NumBits.
15482 DAG.getConstant(NumBits, VT),
15483 DAG.getConstant(X86::COND_E, MVT::i8),
15486 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
15489 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
15490 // ones, and then concatenate the result back.
15491 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
15492 MVT VT = Op.getSimpleValueType();
15494 assert(VT.is256BitVector() && VT.isInteger() &&
15495 "Unsupported value type for operation");
15497 unsigned NumElems = VT.getVectorNumElements();
15500 // Extract the LHS vectors
15501 SDValue LHS = Op.getOperand(0);
15502 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15503 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15505 // Extract the RHS vectors
15506 SDValue RHS = Op.getOperand(1);
15507 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15508 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15510 MVT EltVT = VT.getVectorElementType();
15511 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15513 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15514 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
15515 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
15518 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
15519 assert(Op.getSimpleValueType().is256BitVector() &&
15520 Op.getSimpleValueType().isInteger() &&
15521 "Only handle AVX 256-bit vector integer operation");
15522 return Lower256IntArith(Op, DAG);
15525 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
15526 assert(Op.getSimpleValueType().is256BitVector() &&
15527 Op.getSimpleValueType().isInteger() &&
15528 "Only handle AVX 256-bit vector integer operation");
15529 return Lower256IntArith(Op, DAG);
15532 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
15533 SelectionDAG &DAG) {
15535 MVT VT = Op.getSimpleValueType();
15537 // Decompose 256-bit ops into smaller 128-bit ops.
15538 if (VT.is256BitVector() && !Subtarget->hasInt256())
15539 return Lower256IntArith(Op, DAG);
15541 SDValue A = Op.getOperand(0);
15542 SDValue B = Op.getOperand(1);
15544 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
15545 if (VT == MVT::v4i32) {
15546 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
15547 "Should not custom lower when pmuldq is available!");
15549 // Extract the odd parts.
15550 static const int UnpackMask[] = { 1, -1, 3, -1 };
15551 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
15552 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
15554 // Multiply the even parts.
15555 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
15556 // Now multiply odd parts.
15557 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
15559 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
15560 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
15562 // Merge the two vectors back together with a shuffle. This expands into 2
15564 static const int ShufMask[] = { 0, 4, 2, 6 };
15565 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
15568 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
15569 "Only know how to lower V2I64/V4I64/V8I64 multiply");
15571 // Ahi = psrlqi(a, 32);
15572 // Bhi = psrlqi(b, 32);
15574 // AloBlo = pmuludq(a, b);
15575 // AloBhi = pmuludq(a, Bhi);
15576 // AhiBlo = pmuludq(Ahi, b);
15578 // AloBhi = psllqi(AloBhi, 32);
15579 // AhiBlo = psllqi(AhiBlo, 32);
15580 // return AloBlo + AloBhi + AhiBlo;
15582 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
15583 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
15585 // Bit cast to 32-bit vectors for MULUDQ
15586 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
15587 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
15588 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
15589 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
15590 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
15591 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
15593 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
15594 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
15595 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
15597 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
15598 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
15600 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
15601 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
15604 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
15605 assert(Subtarget->isTargetWin64() && "Unexpected target");
15606 EVT VT = Op.getValueType();
15607 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
15608 "Unexpected return type for lowering");
15612 switch (Op->getOpcode()) {
15613 default: llvm_unreachable("Unexpected request for libcall!");
15614 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
15615 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
15616 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
15617 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
15618 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
15619 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
15623 SDValue InChain = DAG.getEntryNode();
15625 TargetLowering::ArgListTy Args;
15626 TargetLowering::ArgListEntry Entry;
15627 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
15628 EVT ArgVT = Op->getOperand(i).getValueType();
15629 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
15630 "Unexpected argument type for lowering");
15631 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
15632 Entry.Node = StackPtr;
15633 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
15635 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15636 Entry.Ty = PointerType::get(ArgTy,0);
15637 Entry.isSExt = false;
15638 Entry.isZExt = false;
15639 Args.push_back(Entry);
15642 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
15645 TargetLowering::CallLoweringInfo CLI(DAG);
15646 CLI.setDebugLoc(dl).setChain(InChain)
15647 .setCallee(getLibcallCallingConv(LC),
15648 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
15649 Callee, std::move(Args), 0)
15650 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
15652 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
15653 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
15656 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
15657 SelectionDAG &DAG) {
15658 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
15659 EVT VT = Op0.getValueType();
15662 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
15663 (VT == MVT::v8i32 && Subtarget->hasInt256()));
15665 // PMULxD operations multiply each even value (starting at 0) of LHS with
15666 // the related value of RHS and produce a widen result.
15667 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15668 // => <2 x i64> <ae|cg>
15670 // In other word, to have all the results, we need to perform two PMULxD:
15671 // 1. one with the even values.
15672 // 2. one with the odd values.
15673 // To achieve #2, with need to place the odd values at an even position.
15675 // Place the odd value at an even position (basically, shift all values 1
15676 // step to the left):
15677 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
15678 // <a|b|c|d> => <b|undef|d|undef>
15679 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
15680 // <e|f|g|h> => <f|undef|h|undef>
15681 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
15683 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
15685 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
15686 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
15688 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
15689 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
15690 // => <2 x i64> <ae|cg>
15691 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
15692 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
15693 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
15694 // => <2 x i64> <bf|dh>
15695 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
15696 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
15698 // Shuffle it back into the right order.
15699 SDValue Highs, Lows;
15700 if (VT == MVT::v8i32) {
15701 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
15702 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15703 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
15704 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15706 const int HighMask[] = {1, 5, 3, 7};
15707 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
15708 const int LowMask[] = {1, 4, 2, 6};
15709 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
15712 // If we have a signed multiply but no PMULDQ fix up the high parts of a
15713 // unsigned multiply.
15714 if (IsSigned && !Subtarget->hasSSE41()) {
15716 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
15717 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
15718 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
15719 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
15720 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
15722 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
15723 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
15726 // The first result of MUL_LOHI is actually the low value, followed by the
15728 SDValue Ops[] = {Lows, Highs};
15729 return DAG.getMergeValues(Ops, dl);
15732 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
15733 const X86Subtarget *Subtarget) {
15734 MVT VT = Op.getSimpleValueType();
15736 SDValue R = Op.getOperand(0);
15737 SDValue Amt = Op.getOperand(1);
15739 // Optimize shl/srl/sra with constant shift amount.
15740 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
15741 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
15742 uint64_t ShiftAmt = ShiftConst->getZExtValue();
15744 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
15745 (Subtarget->hasInt256() &&
15746 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15747 (Subtarget->hasAVX512() &&
15748 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15749 if (Op.getOpcode() == ISD::SHL)
15750 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15752 if (Op.getOpcode() == ISD::SRL)
15753 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15755 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
15756 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15760 if (VT == MVT::v16i8) {
15761 if (Op.getOpcode() == ISD::SHL) {
15762 // Make a large shift.
15763 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15764 MVT::v8i16, R, ShiftAmt,
15766 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15767 // Zero out the rightmost bits.
15768 SmallVector<SDValue, 16> V(16,
15769 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15771 return DAG.getNode(ISD::AND, dl, VT, SHL,
15772 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15774 if (Op.getOpcode() == ISD::SRL) {
15775 // Make a large shift.
15776 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15777 MVT::v8i16, R, ShiftAmt,
15779 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15780 // Zero out the leftmost bits.
15781 SmallVector<SDValue, 16> V(16,
15782 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15784 return DAG.getNode(ISD::AND, dl, VT, SRL,
15785 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15787 if (Op.getOpcode() == ISD::SRA) {
15788 if (ShiftAmt == 7) {
15789 // R s>> 7 === R s< 0
15790 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15791 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15794 // R s>> a === ((R u>> a) ^ m) - m
15795 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15796 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
15798 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15799 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15800 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15803 llvm_unreachable("Unknown shift opcode.");
15806 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
15807 if (Op.getOpcode() == ISD::SHL) {
15808 // Make a large shift.
15809 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
15810 MVT::v16i16, R, ShiftAmt,
15812 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
15813 // Zero out the rightmost bits.
15814 SmallVector<SDValue, 32> V(32,
15815 DAG.getConstant(uint8_t(-1U << ShiftAmt),
15817 return DAG.getNode(ISD::AND, dl, VT, SHL,
15818 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15820 if (Op.getOpcode() == ISD::SRL) {
15821 // Make a large shift.
15822 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
15823 MVT::v16i16, R, ShiftAmt,
15825 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
15826 // Zero out the leftmost bits.
15827 SmallVector<SDValue, 32> V(32,
15828 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
15830 return DAG.getNode(ISD::AND, dl, VT, SRL,
15831 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
15833 if (Op.getOpcode() == ISD::SRA) {
15834 if (ShiftAmt == 7) {
15835 // R s>> 7 === R s< 0
15836 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15837 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
15840 // R s>> a === ((R u>> a) ^ m) - m
15841 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
15842 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
15844 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
15845 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
15846 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
15849 llvm_unreachable("Unknown shift opcode.");
15854 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
15855 if (!Subtarget->is64Bit() &&
15856 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
15857 Amt.getOpcode() == ISD::BITCAST &&
15858 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
15859 Amt = Amt.getOperand(0);
15860 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
15861 VT.getVectorNumElements();
15862 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
15863 uint64_t ShiftAmt = 0;
15864 for (unsigned i = 0; i != Ratio; ++i) {
15865 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
15869 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
15871 // Check remaining shift amounts.
15872 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
15873 uint64_t ShAmt = 0;
15874 for (unsigned j = 0; j != Ratio; ++j) {
15875 ConstantSDNode *C =
15876 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
15880 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
15882 if (ShAmt != ShiftAmt)
15885 switch (Op.getOpcode()) {
15887 llvm_unreachable("Unknown shift opcode!");
15889 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
15892 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
15895 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
15903 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
15904 const X86Subtarget* Subtarget) {
15905 MVT VT = Op.getSimpleValueType();
15907 SDValue R = Op.getOperand(0);
15908 SDValue Amt = Op.getOperand(1);
15910 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
15911 VT == MVT::v4i32 || VT == MVT::v8i16 ||
15912 (Subtarget->hasInt256() &&
15913 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
15914 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
15915 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
15917 EVT EltVT = VT.getVectorElementType();
15919 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
15920 unsigned NumElts = VT.getVectorNumElements();
15922 for (i = 0; i != NumElts; ++i) {
15923 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
15927 for (j = i; j != NumElts; ++j) {
15928 SDValue Arg = Amt.getOperand(j);
15929 if (Arg.getOpcode() == ISD::UNDEF) continue;
15930 if (Arg != Amt.getOperand(i))
15933 if (i != NumElts && j == NumElts)
15934 BaseShAmt = Amt.getOperand(i);
15936 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
15937 Amt = Amt.getOperand(0);
15938 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
15939 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
15940 SDValue InVec = Amt.getOperand(0);
15941 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15942 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15944 for (; i != NumElts; ++i) {
15945 SDValue Arg = InVec.getOperand(i);
15946 if (Arg.getOpcode() == ISD::UNDEF) continue;
15950 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15951 if (ConstantSDNode *C =
15952 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15953 unsigned SplatIdx =
15954 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
15955 if (C->getZExtValue() == SplatIdx)
15956 BaseShAmt = InVec.getOperand(1);
15959 if (!BaseShAmt.getNode())
15960 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
15961 DAG.getIntPtrConstant(0));
15965 if (BaseShAmt.getNode()) {
15966 if (EltVT.bitsGT(MVT::i32))
15967 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
15968 else if (EltVT.bitsLT(MVT::i32))
15969 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
15971 switch (Op.getOpcode()) {
15973 llvm_unreachable("Unknown shift opcode!");
15975 switch (VT.SimpleTy) {
15976 default: return SDValue();
15985 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
15988 switch (VT.SimpleTy) {
15989 default: return SDValue();
15996 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
15999 switch (VT.SimpleTy) {
16000 default: return SDValue();
16009 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
16015 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16016 if (!Subtarget->is64Bit() &&
16017 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
16018 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
16019 Amt.getOpcode() == ISD::BITCAST &&
16020 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16021 Amt = Amt.getOperand(0);
16022 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16023 VT.getVectorNumElements();
16024 std::vector<SDValue> Vals(Ratio);
16025 for (unsigned i = 0; i != Ratio; ++i)
16026 Vals[i] = Amt.getOperand(i);
16027 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16028 for (unsigned j = 0; j != Ratio; ++j)
16029 if (Vals[j] != Amt.getOperand(i + j))
16032 switch (Op.getOpcode()) {
16034 llvm_unreachable("Unknown shift opcode!");
16036 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
16038 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
16040 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
16047 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16048 SelectionDAG &DAG) {
16049 MVT VT = Op.getSimpleValueType();
16051 SDValue R = Op.getOperand(0);
16052 SDValue Amt = Op.getOperand(1);
16055 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16056 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16058 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
16062 V = LowerScalarVariableShift(Op, DAG, Subtarget);
16066 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
16068 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
16069 if (Subtarget->hasInt256()) {
16070 if (Op.getOpcode() == ISD::SRL &&
16071 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16072 VT == MVT::v4i64 || VT == MVT::v8i32))
16074 if (Op.getOpcode() == ISD::SHL &&
16075 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
16076 VT == MVT::v4i64 || VT == MVT::v8i32))
16078 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
16082 // If possible, lower this packed shift into a vector multiply instead of
16083 // expanding it into a sequence of scalar shifts.
16084 // Do this only if the vector shift count is a constant build_vector.
16085 if (Op.getOpcode() == ISD::SHL &&
16086 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16087 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16088 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16089 SmallVector<SDValue, 8> Elts;
16090 EVT SVT = VT.getScalarType();
16091 unsigned SVTBits = SVT.getSizeInBits();
16092 const APInt &One = APInt(SVTBits, 1);
16093 unsigned NumElems = VT.getVectorNumElements();
16095 for (unsigned i=0; i !=NumElems; ++i) {
16096 SDValue Op = Amt->getOperand(i);
16097 if (Op->getOpcode() == ISD::UNDEF) {
16098 Elts.push_back(Op);
16102 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16103 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16104 uint64_t ShAmt = C.getZExtValue();
16105 if (ShAmt >= SVTBits) {
16106 Elts.push_back(DAG.getUNDEF(SVT));
16109 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
16111 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16112 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16115 // Lower SHL with variable shift amount.
16116 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16117 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
16119 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
16120 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
16121 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16122 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16125 // If possible, lower this shift as a sequence of two shifts by
16126 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16128 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16130 // Could be rewritten as:
16131 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16133 // The advantage is that the two shifts from the example would be
16134 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16135 // the vector shift into four scalar shifts plus four pairs of vector
16137 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16138 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16139 unsigned TargetOpcode = X86ISD::MOVSS;
16140 bool CanBeSimplified;
16141 // The splat value for the first packed shift (the 'X' from the example).
16142 SDValue Amt1 = Amt->getOperand(0);
16143 // The splat value for the second packed shift (the 'Y' from the example).
16144 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16145 Amt->getOperand(2);
16147 // See if it is possible to replace this node with a sequence of
16148 // two shifts followed by a MOVSS/MOVSD
16149 if (VT == MVT::v4i32) {
16150 // Check if it is legal to use a MOVSS.
16151 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16152 Amt2 == Amt->getOperand(3);
16153 if (!CanBeSimplified) {
16154 // Otherwise, check if we can still simplify this node using a MOVSD.
16155 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16156 Amt->getOperand(2) == Amt->getOperand(3);
16157 TargetOpcode = X86ISD::MOVSD;
16158 Amt2 = Amt->getOperand(2);
16161 // Do similar checks for the case where the machine value type
16163 CanBeSimplified = Amt1 == Amt->getOperand(1);
16164 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16165 CanBeSimplified = Amt2 == Amt->getOperand(i);
16167 if (!CanBeSimplified) {
16168 TargetOpcode = X86ISD::MOVSD;
16169 CanBeSimplified = true;
16170 Amt2 = Amt->getOperand(4);
16171 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16172 CanBeSimplified = Amt1 == Amt->getOperand(i);
16173 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16174 CanBeSimplified = Amt2 == Amt->getOperand(j);
16178 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16179 isa<ConstantSDNode>(Amt2)) {
16180 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16181 EVT CastVT = MVT::v4i32;
16183 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
16184 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16186 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
16187 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16188 if (TargetOpcode == X86ISD::MOVSD)
16189 CastVT = MVT::v2i64;
16190 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
16191 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
16192 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16194 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
16198 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
16199 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
16202 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
16203 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
16205 // Turn 'a' into a mask suitable for VSELECT
16206 SDValue VSelM = DAG.getConstant(0x80, VT);
16207 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16208 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16210 SDValue CM1 = DAG.getConstant(0x0f, VT);
16211 SDValue CM2 = DAG.getConstant(0x3f, VT);
16213 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
16214 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
16215 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
16216 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16217 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16220 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16221 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16222 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16224 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
16225 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
16226 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
16227 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
16228 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
16231 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
16232 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
16233 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
16235 // return VSELECT(r, r+r, a);
16236 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
16237 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
16241 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
16242 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
16243 // solution better.
16244 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
16245 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
16247 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
16248 R = DAG.getNode(ExtOpc, dl, NewVT, R);
16249 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
16250 return DAG.getNode(ISD::TRUNCATE, dl, VT,
16251 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
16254 // Decompose 256-bit shifts into smaller 128-bit shifts.
16255 if (VT.is256BitVector()) {
16256 unsigned NumElems = VT.getVectorNumElements();
16257 MVT EltVT = VT.getVectorElementType();
16258 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16260 // Extract the two vectors
16261 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
16262 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
16264 // Recreate the shift amount vectors
16265 SDValue Amt1, Amt2;
16266 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
16267 // Constant shift amount
16268 SmallVector<SDValue, 4> Amt1Csts;
16269 SmallVector<SDValue, 4> Amt2Csts;
16270 for (unsigned i = 0; i != NumElems/2; ++i)
16271 Amt1Csts.push_back(Amt->getOperand(i));
16272 for (unsigned i = NumElems/2; i != NumElems; ++i)
16273 Amt2Csts.push_back(Amt->getOperand(i));
16275 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
16276 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
16278 // Variable shift amount
16279 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
16280 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
16283 // Issue new vector shifts for the smaller types
16284 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
16285 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
16287 // Concatenate the result back
16288 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
16294 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
16295 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
16296 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
16297 // looks for this combo and may remove the "setcc" instruction if the "setcc"
16298 // has only one use.
16299 SDNode *N = Op.getNode();
16300 SDValue LHS = N->getOperand(0);
16301 SDValue RHS = N->getOperand(1);
16302 unsigned BaseOp = 0;
16305 switch (Op.getOpcode()) {
16306 default: llvm_unreachable("Unknown ovf instruction!");
16308 // A subtract of one will be selected as a INC. Note that INC doesn't
16309 // set CF, so we can't do this for UADDO.
16310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16312 BaseOp = X86ISD::INC;
16313 Cond = X86::COND_O;
16316 BaseOp = X86ISD::ADD;
16317 Cond = X86::COND_O;
16320 BaseOp = X86ISD::ADD;
16321 Cond = X86::COND_B;
16324 // A subtract of one will be selected as a DEC. Note that DEC doesn't
16325 // set CF, so we can't do this for USUBO.
16326 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16328 BaseOp = X86ISD::DEC;
16329 Cond = X86::COND_O;
16332 BaseOp = X86ISD::SUB;
16333 Cond = X86::COND_O;
16336 BaseOp = X86ISD::SUB;
16337 Cond = X86::COND_B;
16340 BaseOp = X86ISD::SMUL;
16341 Cond = X86::COND_O;
16343 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
16344 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
16346 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
16349 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16350 DAG.getConstant(X86::COND_O, MVT::i32),
16351 SDValue(Sum.getNode(), 2));
16353 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16357 // Also sets EFLAGS.
16358 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
16359 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
16362 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
16363 DAG.getConstant(Cond, MVT::i32),
16364 SDValue(Sum.getNode(), 1));
16366 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
16369 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
16370 SelectionDAG &DAG) const {
16372 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
16373 MVT VT = Op.getSimpleValueType();
16375 if (!Subtarget->hasSSE2() || !VT.isVector())
16378 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
16379 ExtraVT.getScalarType().getSizeInBits();
16381 switch (VT.SimpleTy) {
16382 default: return SDValue();
16385 if (!Subtarget->hasFp256())
16387 if (!Subtarget->hasInt256()) {
16388 // needs to be split
16389 unsigned NumElems = VT.getVectorNumElements();
16391 // Extract the LHS vectors
16392 SDValue LHS = Op.getOperand(0);
16393 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16394 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16396 MVT EltVT = VT.getVectorElementType();
16397 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16399 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16400 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
16401 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
16403 SDValue Extra = DAG.getValueType(ExtraVT);
16405 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
16406 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
16408 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
16413 SDValue Op0 = Op.getOperand(0);
16414 SDValue Op00 = Op0.getOperand(0);
16416 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
16417 if (Op0.getOpcode() == ISD::BITCAST &&
16418 Op00.getOpcode() == ISD::VECTOR_SHUFFLE) {
16419 // (sext (vzext x)) -> (vsext x)
16420 Tmp1 = LowerVectorIntExtend(Op00, Subtarget, DAG);
16421 if (Tmp1.getNode()) {
16422 EVT ExtraEltVT = ExtraVT.getVectorElementType();
16423 // This folding is only valid when the in-reg type is a vector of i8,
16425 if (ExtraEltVT == MVT::i8 || ExtraEltVT == MVT::i16 ||
16426 ExtraEltVT == MVT::i32) {
16427 SDValue Tmp1Op0 = Tmp1.getOperand(0);
16428 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
16429 "This optimization is invalid without a VZEXT.");
16430 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
16436 // If the above didn't work, then just use Shift-Left + Shift-Right.
16437 Tmp1 = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0, BitsDiff,
16439 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Tmp1, BitsDiff,
16445 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
16446 SelectionDAG &DAG) {
16448 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
16449 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
16450 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
16451 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
16453 // The only fence that needs an instruction is a sequentially-consistent
16454 // cross-thread fence.
16455 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
16456 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
16457 // no-sse2). There isn't any reason to disable it if the target processor
16459 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
16460 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
16462 SDValue Chain = Op.getOperand(0);
16463 SDValue Zero = DAG.getConstant(0, MVT::i32);
16465 DAG.getRegister(X86::ESP, MVT::i32), // Base
16466 DAG.getTargetConstant(1, MVT::i8), // Scale
16467 DAG.getRegister(0, MVT::i32), // Index
16468 DAG.getTargetConstant(0, MVT::i32), // Disp
16469 DAG.getRegister(0, MVT::i32), // Segment.
16473 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
16474 return SDValue(Res, 0);
16477 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
16478 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
16481 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
16482 SelectionDAG &DAG) {
16483 MVT T = Op.getSimpleValueType();
16487 switch(T.SimpleTy) {
16488 default: llvm_unreachable("Invalid value type!");
16489 case MVT::i8: Reg = X86::AL; size = 1; break;
16490 case MVT::i16: Reg = X86::AX; size = 2; break;
16491 case MVT::i32: Reg = X86::EAX; size = 4; break;
16493 assert(Subtarget->is64Bit() && "Node not type legal!");
16494 Reg = X86::RAX; size = 8;
16497 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
16498 Op.getOperand(2), SDValue());
16499 SDValue Ops[] = { cpIn.getValue(0),
16502 DAG.getTargetConstant(size, MVT::i8),
16503 cpIn.getValue(1) };
16504 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16505 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
16506 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
16510 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
16511 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
16512 MVT::i32, cpOut.getValue(2));
16513 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
16514 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16516 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
16517 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
16518 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
16522 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
16523 SelectionDAG &DAG) {
16524 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
16525 MVT DstVT = Op.getSimpleValueType();
16527 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
16528 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16529 if (DstVT != MVT::f64)
16530 // This conversion needs to be expanded.
16533 SDValue InVec = Op->getOperand(0);
16535 unsigned NumElts = SrcVT.getVectorNumElements();
16536 EVT SVT = SrcVT.getVectorElementType();
16538 // Widen the vector in input in the case of MVT::v2i32.
16539 // Example: from MVT::v2i32 to MVT::v4i32.
16540 SmallVector<SDValue, 16> Elts;
16541 for (unsigned i = 0, e = NumElts; i != e; ++i)
16542 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
16543 DAG.getIntPtrConstant(i)));
16545 // Explicitly mark the extra elements as Undef.
16546 SDValue Undef = DAG.getUNDEF(SVT);
16547 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
16548 Elts.push_back(Undef);
16550 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16551 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
16552 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
16553 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
16554 DAG.getIntPtrConstant(0));
16557 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
16558 Subtarget->hasMMX() && "Unexpected custom BITCAST");
16559 assert((DstVT == MVT::i64 ||
16560 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
16561 "Unexpected custom BITCAST");
16562 // i64 <=> MMX conversions are Legal.
16563 if (SrcVT==MVT::i64 && DstVT.isVector())
16565 if (DstVT==MVT::i64 && SrcVT.isVector())
16567 // MMX <=> MMX conversions are Legal.
16568 if (SrcVT.isVector() && DstVT.isVector())
16570 // All other conversions need to be expanded.
16574 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
16575 SDNode *Node = Op.getNode();
16577 EVT T = Node->getValueType(0);
16578 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
16579 DAG.getConstant(0, T), Node->getOperand(2));
16580 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
16581 cast<AtomicSDNode>(Node)->getMemoryVT(),
16582 Node->getOperand(0),
16583 Node->getOperand(1), negOp,
16584 cast<AtomicSDNode>(Node)->getMemOperand(),
16585 cast<AtomicSDNode>(Node)->getOrdering(),
16586 cast<AtomicSDNode>(Node)->getSynchScope());
16589 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
16590 SDNode *Node = Op.getNode();
16592 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16594 // Convert seq_cst store -> xchg
16595 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
16596 // FIXME: On 32-bit, store -> fist or movq would be more efficient
16597 // (The only way to get a 16-byte store is cmpxchg16b)
16598 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
16599 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
16600 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
16601 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
16602 cast<AtomicSDNode>(Node)->getMemoryVT(),
16603 Node->getOperand(0),
16604 Node->getOperand(1), Node->getOperand(2),
16605 cast<AtomicSDNode>(Node)->getMemOperand(),
16606 cast<AtomicSDNode>(Node)->getOrdering(),
16607 cast<AtomicSDNode>(Node)->getSynchScope());
16608 return Swap.getValue(1);
16610 // Other atomic stores have a simple pattern.
16614 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
16615 EVT VT = Op.getNode()->getSimpleValueType(0);
16617 // Let legalize expand this if it isn't a legal type yet.
16618 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16621 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16624 bool ExtraOp = false;
16625 switch (Op.getOpcode()) {
16626 default: llvm_unreachable("Invalid code");
16627 case ISD::ADDC: Opc = X86ISD::ADD; break;
16628 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
16629 case ISD::SUBC: Opc = X86ISD::SUB; break;
16630 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
16634 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16636 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
16637 Op.getOperand(1), Op.getOperand(2));
16640 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
16641 SelectionDAG &DAG) {
16642 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
16644 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
16645 // which returns the values as { float, float } (in XMM0) or
16646 // { double, double } (which is returned in XMM0, XMM1).
16648 SDValue Arg = Op.getOperand(0);
16649 EVT ArgVT = Arg.getValueType();
16650 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16652 TargetLowering::ArgListTy Args;
16653 TargetLowering::ArgListEntry Entry;
16657 Entry.isSExt = false;
16658 Entry.isZExt = false;
16659 Args.push_back(Entry);
16661 bool isF64 = ArgVT == MVT::f64;
16662 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
16663 // the small struct {f32, f32} is returned in (eax, edx). For f64,
16664 // the results are returned via SRet in memory.
16665 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
16666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16667 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
16669 Type *RetTy = isF64
16670 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
16671 : (Type*)VectorType::get(ArgTy, 4);
16673 TargetLowering::CallLoweringInfo CLI(DAG);
16674 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
16675 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
16677 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
16680 // Returned in xmm0 and xmm1.
16681 return CallResult.first;
16683 // Returned in bits 0:31 and 32:64 xmm0.
16684 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16685 CallResult.first, DAG.getIntPtrConstant(0));
16686 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
16687 CallResult.first, DAG.getIntPtrConstant(1));
16688 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
16689 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
16692 /// LowerOperation - Provide custom lowering hooks for some operations.
16694 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
16695 switch (Op.getOpcode()) {
16696 default: llvm_unreachable("Should not custom lower this!");
16697 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
16698 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
16699 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
16700 return LowerCMP_SWAP(Op, Subtarget, DAG);
16701 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
16702 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
16703 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
16704 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
16705 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
16706 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
16707 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
16708 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
16709 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
16710 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
16711 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
16712 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
16713 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
16714 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
16715 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
16716 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
16717 case ISD::SHL_PARTS:
16718 case ISD::SRA_PARTS:
16719 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
16720 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
16721 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
16722 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
16723 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
16724 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
16725 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
16726 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
16727 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
16728 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
16729 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
16730 case ISD::FABS: return LowerFABS(Op, DAG);
16731 case ISD::FNEG: return LowerFNEG(Op, DAG);
16732 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
16733 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
16734 case ISD::SETCC: return LowerSETCC(Op, DAG);
16735 case ISD::SELECT: return LowerSELECT(Op, DAG);
16736 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
16737 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
16738 case ISD::VASTART: return LowerVASTART(Op, DAG);
16739 case ISD::VAARG: return LowerVAARG(Op, DAG);
16740 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
16741 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
16742 case ISD::INTRINSIC_VOID:
16743 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
16744 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
16745 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
16746 case ISD::FRAME_TO_ARGS_OFFSET:
16747 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
16748 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
16749 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
16750 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
16751 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
16752 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
16753 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
16754 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
16755 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
16756 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
16757 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
16758 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
16759 case ISD::UMUL_LOHI:
16760 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
16763 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
16769 case ISD::UMULO: return LowerXALUO(Op, DAG);
16770 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
16771 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
16775 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
16776 case ISD::ADD: return LowerADD(Op, DAG);
16777 case ISD::SUB: return LowerSUB(Op, DAG);
16778 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
16782 static void ReplaceATOMIC_LOAD(SDNode *Node,
16783 SmallVectorImpl<SDValue> &Results,
16784 SelectionDAG &DAG) {
16786 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
16788 // Convert wide load -> cmpxchg8b/cmpxchg16b
16789 // FIXME: On 32-bit, load -> fild or movq would be more efficient
16790 // (The only way to get a 16-byte load is cmpxchg16b)
16791 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
16792 SDValue Zero = DAG.getConstant(0, VT);
16793 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
16795 DAG.getAtomicCmpSwap(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, VT, VTs,
16796 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
16797 cast<AtomicSDNode>(Node)->getMemOperand(),
16798 cast<AtomicSDNode>(Node)->getOrdering(),
16799 cast<AtomicSDNode>(Node)->getOrdering(),
16800 cast<AtomicSDNode>(Node)->getSynchScope());
16801 Results.push_back(Swap.getValue(0));
16802 Results.push_back(Swap.getValue(2));
16805 /// ReplaceNodeResults - Replace a node with an illegal result type
16806 /// with a new node built out of custom code.
16807 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
16808 SmallVectorImpl<SDValue>&Results,
16809 SelectionDAG &DAG) const {
16811 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16812 switch (N->getOpcode()) {
16814 llvm_unreachable("Do not know how to custom type legalize this operation!");
16815 case ISD::SIGN_EXTEND_INREG:
16820 // We don't want to expand or promote these.
16827 case ISD::UDIVREM: {
16828 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
16829 Results.push_back(V);
16832 case ISD::FP_TO_SINT:
16833 case ISD::FP_TO_UINT: {
16834 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
16836 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
16839 std::pair<SDValue,SDValue> Vals =
16840 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
16841 SDValue FIST = Vals.first, StackSlot = Vals.second;
16842 if (FIST.getNode()) {
16843 EVT VT = N->getValueType(0);
16844 // Return a load from the stack slot.
16845 if (StackSlot.getNode())
16846 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
16847 MachinePointerInfo(),
16848 false, false, false, 0));
16850 Results.push_back(FIST);
16854 case ISD::UINT_TO_FP: {
16855 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16856 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
16857 N->getValueType(0) != MVT::v2f32)
16859 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
16861 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
16863 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
16864 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
16865 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
16866 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
16867 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
16868 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
16871 case ISD::FP_ROUND: {
16872 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
16874 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
16875 Results.push_back(V);
16878 case ISD::INTRINSIC_W_CHAIN: {
16879 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
16881 default : llvm_unreachable("Do not know how to custom type "
16882 "legalize this intrinsic operation!");
16883 case Intrinsic::x86_rdtsc:
16884 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16886 case Intrinsic::x86_rdtscp:
16887 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
16889 case Intrinsic::x86_rdpmc:
16890 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
16893 case ISD::READCYCLECOUNTER: {
16894 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
16897 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
16898 EVT T = N->getValueType(0);
16899 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
16900 bool Regs64bit = T == MVT::i128;
16901 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
16902 SDValue cpInL, cpInH;
16903 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16904 DAG.getConstant(0, HalfT));
16905 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
16906 DAG.getConstant(1, HalfT));
16907 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
16908 Regs64bit ? X86::RAX : X86::EAX,
16910 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
16911 Regs64bit ? X86::RDX : X86::EDX,
16912 cpInH, cpInL.getValue(1));
16913 SDValue swapInL, swapInH;
16914 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16915 DAG.getConstant(0, HalfT));
16916 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
16917 DAG.getConstant(1, HalfT));
16918 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
16919 Regs64bit ? X86::RBX : X86::EBX,
16920 swapInL, cpInH.getValue(1));
16921 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
16922 Regs64bit ? X86::RCX : X86::ECX,
16923 swapInH, swapInL.getValue(1));
16924 SDValue Ops[] = { swapInH.getValue(0),
16926 swapInH.getValue(1) };
16927 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16928 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
16929 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
16930 X86ISD::LCMPXCHG8_DAG;
16931 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
16932 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
16933 Regs64bit ? X86::RAX : X86::EAX,
16934 HalfT, Result.getValue(1));
16935 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
16936 Regs64bit ? X86::RDX : X86::EDX,
16937 HalfT, cpOutL.getValue(2));
16938 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
16940 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
16941 MVT::i32, cpOutH.getValue(2));
16943 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16944 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
16945 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
16947 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
16948 Results.push_back(Success);
16949 Results.push_back(EFLAGS.getValue(1));
16952 case ISD::ATOMIC_SWAP:
16953 case ISD::ATOMIC_LOAD_ADD:
16954 case ISD::ATOMIC_LOAD_SUB:
16955 case ISD::ATOMIC_LOAD_AND:
16956 case ISD::ATOMIC_LOAD_OR:
16957 case ISD::ATOMIC_LOAD_XOR:
16958 case ISD::ATOMIC_LOAD_NAND:
16959 case ISD::ATOMIC_LOAD_MIN:
16960 case ISD::ATOMIC_LOAD_MAX:
16961 case ISD::ATOMIC_LOAD_UMIN:
16962 case ISD::ATOMIC_LOAD_UMAX:
16963 // Delegate to generic TypeLegalization. Situations we can really handle
16964 // should have already been dealt with by X86AtomicExpandPass.cpp.
16966 case ISD::ATOMIC_LOAD: {
16967 ReplaceATOMIC_LOAD(N, Results, DAG);
16970 case ISD::BITCAST: {
16971 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
16972 EVT DstVT = N->getValueType(0);
16973 EVT SrcVT = N->getOperand(0)->getValueType(0);
16975 if (SrcVT != MVT::f64 ||
16976 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
16979 unsigned NumElts = DstVT.getVectorNumElements();
16980 EVT SVT = DstVT.getVectorElementType();
16981 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
16982 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
16983 MVT::v2f64, N->getOperand(0));
16984 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
16986 if (ExperimentalVectorWideningLegalization) {
16987 // If we are legalizing vectors by widening, we already have the desired
16988 // legal vector type, just return it.
16989 Results.push_back(ToVecInt);
16993 SmallVector<SDValue, 8> Elts;
16994 for (unsigned i = 0, e = NumElts; i != e; ++i)
16995 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
16996 ToVecInt, DAG.getIntPtrConstant(i)));
16998 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
17003 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
17005 default: return nullptr;
17006 case X86ISD::BSF: return "X86ISD::BSF";
17007 case X86ISD::BSR: return "X86ISD::BSR";
17008 case X86ISD::SHLD: return "X86ISD::SHLD";
17009 case X86ISD::SHRD: return "X86ISD::SHRD";
17010 case X86ISD::FAND: return "X86ISD::FAND";
17011 case X86ISD::FANDN: return "X86ISD::FANDN";
17012 case X86ISD::FOR: return "X86ISD::FOR";
17013 case X86ISD::FXOR: return "X86ISD::FXOR";
17014 case X86ISD::FSRL: return "X86ISD::FSRL";
17015 case X86ISD::FILD: return "X86ISD::FILD";
17016 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
17017 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
17018 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
17019 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
17020 case X86ISD::FLD: return "X86ISD::FLD";
17021 case X86ISD::FST: return "X86ISD::FST";
17022 case X86ISD::CALL: return "X86ISD::CALL";
17023 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
17024 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
17025 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
17026 case X86ISD::BT: return "X86ISD::BT";
17027 case X86ISD::CMP: return "X86ISD::CMP";
17028 case X86ISD::COMI: return "X86ISD::COMI";
17029 case X86ISD::UCOMI: return "X86ISD::UCOMI";
17030 case X86ISD::CMPM: return "X86ISD::CMPM";
17031 case X86ISD::CMPMU: return "X86ISD::CMPMU";
17032 case X86ISD::SETCC: return "X86ISD::SETCC";
17033 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
17034 case X86ISD::FSETCC: return "X86ISD::FSETCC";
17035 case X86ISD::CMOV: return "X86ISD::CMOV";
17036 case X86ISD::BRCOND: return "X86ISD::BRCOND";
17037 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
17038 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
17039 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
17040 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
17041 case X86ISD::Wrapper: return "X86ISD::Wrapper";
17042 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
17043 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
17044 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
17045 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
17046 case X86ISD::PINSRB: return "X86ISD::PINSRB";
17047 case X86ISD::PINSRW: return "X86ISD::PINSRW";
17048 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
17049 case X86ISD::ANDNP: return "X86ISD::ANDNP";
17050 case X86ISD::PSIGN: return "X86ISD::PSIGN";
17051 case X86ISD::BLENDV: return "X86ISD::BLENDV";
17052 case X86ISD::BLENDI: return "X86ISD::BLENDI";
17053 case X86ISD::SUBUS: return "X86ISD::SUBUS";
17054 case X86ISD::HADD: return "X86ISD::HADD";
17055 case X86ISD::HSUB: return "X86ISD::HSUB";
17056 case X86ISD::FHADD: return "X86ISD::FHADD";
17057 case X86ISD::FHSUB: return "X86ISD::FHSUB";
17058 case X86ISD::UMAX: return "X86ISD::UMAX";
17059 case X86ISD::UMIN: return "X86ISD::UMIN";
17060 case X86ISD::SMAX: return "X86ISD::SMAX";
17061 case X86ISD::SMIN: return "X86ISD::SMIN";
17062 case X86ISD::FMAX: return "X86ISD::FMAX";
17063 case X86ISD::FMIN: return "X86ISD::FMIN";
17064 case X86ISD::FMAXC: return "X86ISD::FMAXC";
17065 case X86ISD::FMINC: return "X86ISD::FMINC";
17066 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
17067 case X86ISD::FRCP: return "X86ISD::FRCP";
17068 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
17069 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
17070 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
17071 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
17072 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
17073 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
17074 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
17075 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
17076 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
17077 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
17078 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
17079 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
17080 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
17081 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
17082 case X86ISD::VZEXT: return "X86ISD::VZEXT";
17083 case X86ISD::VSEXT: return "X86ISD::VSEXT";
17084 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
17085 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
17086 case X86ISD::VINSERT: return "X86ISD::VINSERT";
17087 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
17088 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
17089 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
17090 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
17091 case X86ISD::VSHL: return "X86ISD::VSHL";
17092 case X86ISD::VSRL: return "X86ISD::VSRL";
17093 case X86ISD::VSRA: return "X86ISD::VSRA";
17094 case X86ISD::VSHLI: return "X86ISD::VSHLI";
17095 case X86ISD::VSRLI: return "X86ISD::VSRLI";
17096 case X86ISD::VSRAI: return "X86ISD::VSRAI";
17097 case X86ISD::CMPP: return "X86ISD::CMPP";
17098 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
17099 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
17100 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
17101 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
17102 case X86ISD::ADD: return "X86ISD::ADD";
17103 case X86ISD::SUB: return "X86ISD::SUB";
17104 case X86ISD::ADC: return "X86ISD::ADC";
17105 case X86ISD::SBB: return "X86ISD::SBB";
17106 case X86ISD::SMUL: return "X86ISD::SMUL";
17107 case X86ISD::UMUL: return "X86ISD::UMUL";
17108 case X86ISD::INC: return "X86ISD::INC";
17109 case X86ISD::DEC: return "X86ISD::DEC";
17110 case X86ISD::OR: return "X86ISD::OR";
17111 case X86ISD::XOR: return "X86ISD::XOR";
17112 case X86ISD::AND: return "X86ISD::AND";
17113 case X86ISD::BEXTR: return "X86ISD::BEXTR";
17114 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
17115 case X86ISD::PTEST: return "X86ISD::PTEST";
17116 case X86ISD::TESTP: return "X86ISD::TESTP";
17117 case X86ISD::TESTM: return "X86ISD::TESTM";
17118 case X86ISD::TESTNM: return "X86ISD::TESTNM";
17119 case X86ISD::KORTEST: return "X86ISD::KORTEST";
17120 case X86ISD::PACKSS: return "X86ISD::PACKSS";
17121 case X86ISD::PACKUS: return "X86ISD::PACKUS";
17122 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
17123 case X86ISD::VALIGN: return "X86ISD::VALIGN";
17124 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
17125 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
17126 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
17127 case X86ISD::SHUFP: return "X86ISD::SHUFP";
17128 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
17129 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
17130 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
17131 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
17132 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
17133 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
17134 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
17135 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
17136 case X86ISD::MOVSD: return "X86ISD::MOVSD";
17137 case X86ISD::MOVSS: return "X86ISD::MOVSS";
17138 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
17139 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
17140 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
17141 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
17142 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
17143 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
17144 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
17145 case X86ISD::VPERMV: return "X86ISD::VPERMV";
17146 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
17147 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
17148 case X86ISD::VPERMI: return "X86ISD::VPERMI";
17149 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
17150 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
17151 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
17152 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
17153 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
17154 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
17155 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
17156 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
17157 case X86ISD::SAHF: return "X86ISD::SAHF";
17158 case X86ISD::RDRAND: return "X86ISD::RDRAND";
17159 case X86ISD::RDSEED: return "X86ISD::RDSEED";
17160 case X86ISD::FMADD: return "X86ISD::FMADD";
17161 case X86ISD::FMSUB: return "X86ISD::FMSUB";
17162 case X86ISD::FNMADD: return "X86ISD::FNMADD";
17163 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
17164 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
17165 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
17166 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
17167 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
17168 case X86ISD::XTEST: return "X86ISD::XTEST";
17172 // isLegalAddressingMode - Return true if the addressing mode represented
17173 // by AM is legal for this target, for a load/store of the specified type.
17174 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
17176 // X86 supports extremely general addressing modes.
17177 CodeModel::Model M = getTargetMachine().getCodeModel();
17178 Reloc::Model R = getTargetMachine().getRelocationModel();
17180 // X86 allows a sign-extended 32-bit immediate field as a displacement.
17181 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
17186 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
17188 // If a reference to this global requires an extra load, we can't fold it.
17189 if (isGlobalStubReference(GVFlags))
17192 // If BaseGV requires a register for the PIC base, we cannot also have a
17193 // BaseReg specified.
17194 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
17197 // If lower 4G is not available, then we must use rip-relative addressing.
17198 if ((M != CodeModel::Small || R != Reloc::Static) &&
17199 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
17203 switch (AM.Scale) {
17209 // These scales always work.
17214 // These scales are formed with basereg+scalereg. Only accept if there is
17219 default: // Other stuff never works.
17226 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
17227 unsigned Bits = Ty->getScalarSizeInBits();
17229 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
17230 // particularly cheaper than those without.
17234 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
17235 // variable shifts just as cheap as scalar ones.
17236 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
17239 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
17240 // fully general vector.
17244 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
17245 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17247 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
17248 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
17249 return NumBits1 > NumBits2;
17252 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
17253 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
17256 if (!isTypeLegal(EVT::getEVT(Ty1)))
17259 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
17261 // Assuming the caller doesn't have a zeroext or signext return parameter,
17262 // truncation all the way down to i1 is valid.
17266 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
17267 return isInt<32>(Imm);
17270 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
17271 // Can also use sub to handle negated immediates.
17272 return isInt<32>(Imm);
17275 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
17276 if (!VT1.isInteger() || !VT2.isInteger())
17278 unsigned NumBits1 = VT1.getSizeInBits();
17279 unsigned NumBits2 = VT2.getSizeInBits();
17280 return NumBits1 > NumBits2;
17283 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
17284 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17285 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
17288 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
17289 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
17290 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
17293 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
17294 EVT VT1 = Val.getValueType();
17295 if (isZExtFree(VT1, VT2))
17298 if (Val.getOpcode() != ISD::LOAD)
17301 if (!VT1.isSimple() || !VT1.isInteger() ||
17302 !VT2.isSimple() || !VT2.isInteger())
17305 switch (VT1.getSimpleVT().SimpleTy) {
17310 // X86 has 8, 16, and 32-bit zero-extending loads.
17318 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
17319 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
17322 VT = VT.getScalarType();
17324 if (!VT.isSimple())
17327 switch (VT.getSimpleVT().SimpleTy) {
17338 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
17339 // i16 instructions are longer (0x66 prefix) and potentially slower.
17340 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
17343 /// isShuffleMaskLegal - Targets can use this to indicate that they only
17344 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
17345 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
17346 /// are assumed to be legal.
17348 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
17350 if (!VT.isSimple())
17353 MVT SVT = VT.getSimpleVT();
17355 // Very little shuffling can be done for 64-bit vectors right now.
17356 if (VT.getSizeInBits() == 64)
17359 // If this is a single-input shuffle with no 128 bit lane crossings we can
17360 // lower it into pshufb.
17361 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
17362 (SVT.is256BitVector() && Subtarget->hasInt256())) {
17363 bool isLegal = true;
17364 for (unsigned I = 0, E = M.size(); I != E; ++I) {
17365 if (M[I] >= (int)SVT.getVectorNumElements() ||
17366 ShuffleCrosses128bitLane(SVT, I, M[I])) {
17375 // FIXME: blends, shifts.
17376 return (SVT.getVectorNumElements() == 2 ||
17377 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
17378 isMOVLMask(M, SVT) ||
17379 isMOVHLPSMask(M, SVT) ||
17380 isSHUFPMask(M, SVT) ||
17381 isPSHUFDMask(M, SVT) ||
17382 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
17383 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
17384 isPALIGNRMask(M, SVT, Subtarget) ||
17385 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
17386 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
17387 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17388 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
17389 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()));
17393 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
17395 if (!VT.isSimple())
17398 MVT SVT = VT.getSimpleVT();
17399 unsigned NumElts = SVT.getVectorNumElements();
17400 // FIXME: This collection of masks seems suspect.
17403 if (NumElts == 4 && SVT.is128BitVector()) {
17404 return (isMOVLMask(Mask, SVT) ||
17405 isCommutedMOVLMask(Mask, SVT, true) ||
17406 isSHUFPMask(Mask, SVT) ||
17407 isSHUFPMask(Mask, SVT, /* Commuted */ true));
17412 //===----------------------------------------------------------------------===//
17413 // X86 Scheduler Hooks
17414 //===----------------------------------------------------------------------===//
17416 /// Utility function to emit xbegin specifying the start of an RTM region.
17417 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
17418 const TargetInstrInfo *TII) {
17419 DebugLoc DL = MI->getDebugLoc();
17421 const BasicBlock *BB = MBB->getBasicBlock();
17422 MachineFunction::iterator I = MBB;
17425 // For the v = xbegin(), we generate
17436 MachineBasicBlock *thisMBB = MBB;
17437 MachineFunction *MF = MBB->getParent();
17438 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
17439 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
17440 MF->insert(I, mainMBB);
17441 MF->insert(I, sinkMBB);
17443 // Transfer the remainder of BB and its successor edges to sinkMBB.
17444 sinkMBB->splice(sinkMBB->begin(), MBB,
17445 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17446 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
17450 // # fallthrough to mainMBB
17451 // # abortion to sinkMBB
17452 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
17453 thisMBB->addSuccessor(mainMBB);
17454 thisMBB->addSuccessor(sinkMBB);
17458 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
17459 mainMBB->addSuccessor(sinkMBB);
17462 // EAX is live into the sinkMBB
17463 sinkMBB->addLiveIn(X86::EAX);
17464 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
17465 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17468 MI->eraseFromParent();
17472 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
17473 // or XMM0_V32I8 in AVX all of this code can be replaced with that
17474 // in the .td file.
17475 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
17476 const TargetInstrInfo *TII) {
17478 switch (MI->getOpcode()) {
17479 default: llvm_unreachable("illegal opcode!");
17480 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
17481 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
17482 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
17483 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
17484 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
17485 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
17486 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
17487 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
17490 DebugLoc dl = MI->getDebugLoc();
17491 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17493 unsigned NumArgs = MI->getNumOperands();
17494 for (unsigned i = 1; i < NumArgs; ++i) {
17495 MachineOperand &Op = MI->getOperand(i);
17496 if (!(Op.isReg() && Op.isImplicit()))
17497 MIB.addOperand(Op);
17499 if (MI->hasOneMemOperand())
17500 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17502 BuildMI(*BB, MI, dl,
17503 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17504 .addReg(X86::XMM0);
17506 MI->eraseFromParent();
17510 // FIXME: Custom handling because TableGen doesn't support multiple implicit
17511 // defs in an instruction pattern
17512 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
17513 const TargetInstrInfo *TII) {
17515 switch (MI->getOpcode()) {
17516 default: llvm_unreachable("illegal opcode!");
17517 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
17518 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
17519 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
17520 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
17521 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
17522 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
17523 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
17524 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
17527 DebugLoc dl = MI->getDebugLoc();
17528 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
17530 unsigned NumArgs = MI->getNumOperands(); // remove the results
17531 for (unsigned i = 1; i < NumArgs; ++i) {
17532 MachineOperand &Op = MI->getOperand(i);
17533 if (!(Op.isReg() && Op.isImplicit()))
17534 MIB.addOperand(Op);
17536 if (MI->hasOneMemOperand())
17537 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
17539 BuildMI(*BB, MI, dl,
17540 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
17543 MI->eraseFromParent();
17547 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
17548 const TargetInstrInfo *TII,
17549 const X86Subtarget* Subtarget) {
17550 DebugLoc dl = MI->getDebugLoc();
17552 // Address into RAX/EAX, other two args into ECX, EDX.
17553 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17554 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
17555 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
17556 for (int i = 0; i < X86::AddrNumOperands; ++i)
17557 MIB.addOperand(MI->getOperand(i));
17559 unsigned ValOps = X86::AddrNumOperands;
17560 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
17561 .addReg(MI->getOperand(ValOps).getReg());
17562 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
17563 .addReg(MI->getOperand(ValOps+1).getReg());
17565 // The instruction doesn't actually take any operands though.
17566 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
17568 MI->eraseFromParent(); // The pseudo is gone now.
17572 MachineBasicBlock *
17573 X86TargetLowering::EmitVAARG64WithCustomInserter(
17575 MachineBasicBlock *MBB) const {
17576 // Emit va_arg instruction on X86-64.
17578 // Operands to this pseudo-instruction:
17579 // 0 ) Output : destination address (reg)
17580 // 1-5) Input : va_list address (addr, i64mem)
17581 // 6 ) ArgSize : Size (in bytes) of vararg type
17582 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
17583 // 8 ) Align : Alignment of type
17584 // 9 ) EFLAGS (implicit-def)
17586 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
17587 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
17589 unsigned DestReg = MI->getOperand(0).getReg();
17590 MachineOperand &Base = MI->getOperand(1);
17591 MachineOperand &Scale = MI->getOperand(2);
17592 MachineOperand &Index = MI->getOperand(3);
17593 MachineOperand &Disp = MI->getOperand(4);
17594 MachineOperand &Segment = MI->getOperand(5);
17595 unsigned ArgSize = MI->getOperand(6).getImm();
17596 unsigned ArgMode = MI->getOperand(7).getImm();
17597 unsigned Align = MI->getOperand(8).getImm();
17599 // Memory Reference
17600 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
17601 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
17602 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
17604 // Machine Information
17605 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17606 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
17607 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
17608 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
17609 DebugLoc DL = MI->getDebugLoc();
17611 // struct va_list {
17614 // i64 overflow_area (address)
17615 // i64 reg_save_area (address)
17617 // sizeof(va_list) = 24
17618 // alignment(va_list) = 8
17620 unsigned TotalNumIntRegs = 6;
17621 unsigned TotalNumXMMRegs = 8;
17622 bool UseGPOffset = (ArgMode == 1);
17623 bool UseFPOffset = (ArgMode == 2);
17624 unsigned MaxOffset = TotalNumIntRegs * 8 +
17625 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
17627 /* Align ArgSize to a multiple of 8 */
17628 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
17629 bool NeedsAlign = (Align > 8);
17631 MachineBasicBlock *thisMBB = MBB;
17632 MachineBasicBlock *overflowMBB;
17633 MachineBasicBlock *offsetMBB;
17634 MachineBasicBlock *endMBB;
17636 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
17637 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
17638 unsigned OffsetReg = 0;
17640 if (!UseGPOffset && !UseFPOffset) {
17641 // If we only pull from the overflow region, we don't create a branch.
17642 // We don't need to alter control flow.
17643 OffsetDestReg = 0; // unused
17644 OverflowDestReg = DestReg;
17646 offsetMBB = nullptr;
17647 overflowMBB = thisMBB;
17650 // First emit code to check if gp_offset (or fp_offset) is below the bound.
17651 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
17652 // If not, pull from overflow_area. (branch to overflowMBB)
17657 // offsetMBB overflowMBB
17662 // Registers for the PHI in endMBB
17663 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
17664 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
17666 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17667 MachineFunction *MF = MBB->getParent();
17668 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17669 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17670 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
17672 MachineFunction::iterator MBBIter = MBB;
17675 // Insert the new basic blocks
17676 MF->insert(MBBIter, offsetMBB);
17677 MF->insert(MBBIter, overflowMBB);
17678 MF->insert(MBBIter, endMBB);
17680 // Transfer the remainder of MBB and its successor edges to endMBB.
17681 endMBB->splice(endMBB->begin(), thisMBB,
17682 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
17683 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
17685 // Make offsetMBB and overflowMBB successors of thisMBB
17686 thisMBB->addSuccessor(offsetMBB);
17687 thisMBB->addSuccessor(overflowMBB);
17689 // endMBB is a successor of both offsetMBB and overflowMBB
17690 offsetMBB->addSuccessor(endMBB);
17691 overflowMBB->addSuccessor(endMBB);
17693 // Load the offset value into a register
17694 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17695 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
17699 .addDisp(Disp, UseFPOffset ? 4 : 0)
17700 .addOperand(Segment)
17701 .setMemRefs(MMOBegin, MMOEnd);
17703 // Check if there is enough room left to pull this argument.
17704 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
17706 .addImm(MaxOffset + 8 - ArgSizeA8);
17708 // Branch to "overflowMBB" if offset >= max
17709 // Fall through to "offsetMBB" otherwise
17710 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
17711 .addMBB(overflowMBB);
17714 // In offsetMBB, emit code to use the reg_save_area.
17716 assert(OffsetReg != 0);
17718 // Read the reg_save_area address.
17719 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
17720 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
17725 .addOperand(Segment)
17726 .setMemRefs(MMOBegin, MMOEnd);
17728 // Zero-extend the offset
17729 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
17730 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
17733 .addImm(X86::sub_32bit);
17735 // Add the offset to the reg_save_area to get the final address.
17736 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
17737 .addReg(OffsetReg64)
17738 .addReg(RegSaveReg);
17740 // Compute the offset for the next argument
17741 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
17742 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
17744 .addImm(UseFPOffset ? 16 : 8);
17746 // Store it back into the va_list.
17747 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
17751 .addDisp(Disp, UseFPOffset ? 4 : 0)
17752 .addOperand(Segment)
17753 .addReg(NextOffsetReg)
17754 .setMemRefs(MMOBegin, MMOEnd);
17757 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
17762 // Emit code to use overflow area
17765 // Load the overflow_area address into a register.
17766 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
17767 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
17772 .addOperand(Segment)
17773 .setMemRefs(MMOBegin, MMOEnd);
17775 // If we need to align it, do so. Otherwise, just copy the address
17776 // to OverflowDestReg.
17778 // Align the overflow address
17779 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
17780 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
17782 // aligned_addr = (addr + (align-1)) & ~(align-1)
17783 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
17784 .addReg(OverflowAddrReg)
17787 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
17789 .addImm(~(uint64_t)(Align-1));
17791 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
17792 .addReg(OverflowAddrReg);
17795 // Compute the next overflow address after this argument.
17796 // (the overflow address should be kept 8-byte aligned)
17797 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
17798 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
17799 .addReg(OverflowDestReg)
17800 .addImm(ArgSizeA8);
17802 // Store the new overflow address.
17803 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
17808 .addOperand(Segment)
17809 .addReg(NextAddrReg)
17810 .setMemRefs(MMOBegin, MMOEnd);
17812 // If we branched, emit the PHI to the front of endMBB.
17814 BuildMI(*endMBB, endMBB->begin(), DL,
17815 TII->get(X86::PHI), DestReg)
17816 .addReg(OffsetDestReg).addMBB(offsetMBB)
17817 .addReg(OverflowDestReg).addMBB(overflowMBB);
17820 // Erase the pseudo instruction
17821 MI->eraseFromParent();
17826 MachineBasicBlock *
17827 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
17829 MachineBasicBlock *MBB) const {
17830 // Emit code to save XMM registers to the stack. The ABI says that the
17831 // number of registers to save is given in %al, so it's theoretically
17832 // possible to do an indirect jump trick to avoid saving all of them,
17833 // however this code takes a simpler approach and just executes all
17834 // of the stores if %al is non-zero. It's less code, and it's probably
17835 // easier on the hardware branch predictor, and stores aren't all that
17836 // expensive anyway.
17838 // Create the new basic blocks. One block contains all the XMM stores,
17839 // and one block is the final destination regardless of whether any
17840 // stores were performed.
17841 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
17842 MachineFunction *F = MBB->getParent();
17843 MachineFunction::iterator MBBIter = MBB;
17845 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
17846 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
17847 F->insert(MBBIter, XMMSaveMBB);
17848 F->insert(MBBIter, EndMBB);
17850 // Transfer the remainder of MBB and its successor edges to EndMBB.
17851 EndMBB->splice(EndMBB->begin(), MBB,
17852 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
17853 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
17855 // The original block will now fall through to the XMM save block.
17856 MBB->addSuccessor(XMMSaveMBB);
17857 // The XMMSaveMBB will fall through to the end block.
17858 XMMSaveMBB->addSuccessor(EndMBB);
17860 // Now add the instructions.
17861 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
17862 DebugLoc DL = MI->getDebugLoc();
17864 unsigned CountReg = MI->getOperand(0).getReg();
17865 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
17866 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
17868 if (!Subtarget->isTargetWin64()) {
17869 // If %al is 0, branch around the XMM save block.
17870 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
17871 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
17872 MBB->addSuccessor(EndMBB);
17875 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
17876 // that was just emitted, but clearly shouldn't be "saved".
17877 assert((MI->getNumOperands() <= 3 ||
17878 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
17879 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
17880 && "Expected last argument to be EFLAGS");
17881 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
17882 // In the XMM save block, save all the XMM argument registers.
17883 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
17884 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
17885 MachineMemOperand *MMO =
17886 F->getMachineMemOperand(
17887 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
17888 MachineMemOperand::MOStore,
17889 /*Size=*/16, /*Align=*/16);
17890 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
17891 .addFrameIndex(RegSaveFrameIndex)
17892 .addImm(/*Scale=*/1)
17893 .addReg(/*IndexReg=*/0)
17894 .addImm(/*Disp=*/Offset)
17895 .addReg(/*Segment=*/0)
17896 .addReg(MI->getOperand(i).getReg())
17897 .addMemOperand(MMO);
17900 MI->eraseFromParent(); // The pseudo instruction is gone now.
17905 // The EFLAGS operand of SelectItr might be missing a kill marker
17906 // because there were multiple uses of EFLAGS, and ISel didn't know
17907 // which to mark. Figure out whether SelectItr should have had a
17908 // kill marker, and set it if it should. Returns the correct kill
17910 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
17911 MachineBasicBlock* BB,
17912 const TargetRegisterInfo* TRI) {
17913 // Scan forward through BB for a use/def of EFLAGS.
17914 MachineBasicBlock::iterator miI(std::next(SelectItr));
17915 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
17916 const MachineInstr& mi = *miI;
17917 if (mi.readsRegister(X86::EFLAGS))
17919 if (mi.definesRegister(X86::EFLAGS))
17920 break; // Should have kill-flag - update below.
17923 // If we hit the end of the block, check whether EFLAGS is live into a
17925 if (miI == BB->end()) {
17926 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
17927 sEnd = BB->succ_end();
17928 sItr != sEnd; ++sItr) {
17929 MachineBasicBlock* succ = *sItr;
17930 if (succ->isLiveIn(X86::EFLAGS))
17935 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
17936 // out. SelectMI should have a kill flag on EFLAGS.
17937 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
17941 MachineBasicBlock *
17942 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
17943 MachineBasicBlock *BB) const {
17944 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
17945 DebugLoc DL = MI->getDebugLoc();
17947 // To "insert" a SELECT_CC instruction, we actually have to insert the
17948 // diamond control-flow pattern. The incoming instruction knows the
17949 // destination vreg to set, the condition code register to branch on, the
17950 // true/false values to select between, and a branch opcode to use.
17951 const BasicBlock *LLVM_BB = BB->getBasicBlock();
17952 MachineFunction::iterator It = BB;
17958 // cmpTY ccX, r1, r2
17960 // fallthrough --> copy0MBB
17961 MachineBasicBlock *thisMBB = BB;
17962 MachineFunction *F = BB->getParent();
17963 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
17964 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
17965 F->insert(It, copy0MBB);
17966 F->insert(It, sinkMBB);
17968 // If the EFLAGS register isn't dead in the terminator, then claim that it's
17969 // live into the sink and copy blocks.
17970 const TargetRegisterInfo *TRI =
17971 BB->getParent()->getSubtarget().getRegisterInfo();
17972 if (!MI->killsRegister(X86::EFLAGS) &&
17973 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
17974 copy0MBB->addLiveIn(X86::EFLAGS);
17975 sinkMBB->addLiveIn(X86::EFLAGS);
17978 // Transfer the remainder of BB and its successor edges to sinkMBB.
17979 sinkMBB->splice(sinkMBB->begin(), BB,
17980 std::next(MachineBasicBlock::iterator(MI)), BB->end());
17981 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
17983 // Add the true and fallthrough blocks as its successors.
17984 BB->addSuccessor(copy0MBB);
17985 BB->addSuccessor(sinkMBB);
17987 // Create the conditional branch instruction.
17989 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
17990 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
17993 // %FalseValue = ...
17994 // # fallthrough to sinkMBB
17995 copy0MBB->addSuccessor(sinkMBB);
17998 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
18000 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18001 TII->get(X86::PHI), MI->getOperand(0).getReg())
18002 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
18003 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
18005 MI->eraseFromParent(); // The pseudo instruction is gone now.
18009 MachineBasicBlock *
18010 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
18011 bool Is64Bit) const {
18012 MachineFunction *MF = BB->getParent();
18013 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18014 DebugLoc DL = MI->getDebugLoc();
18015 const BasicBlock *LLVM_BB = BB->getBasicBlock();
18017 assert(MF->shouldSplitStack());
18019 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
18020 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
18023 // ... [Till the alloca]
18024 // If stacklet is not large enough, jump to mallocMBB
18027 // Allocate by subtracting from RSP
18028 // Jump to continueMBB
18031 // Allocate by call to runtime
18035 // [rest of original BB]
18038 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18039 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18040 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18042 MachineRegisterInfo &MRI = MF->getRegInfo();
18043 const TargetRegisterClass *AddrRegClass =
18044 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
18046 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18047 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
18048 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
18049 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
18050 sizeVReg = MI->getOperand(1).getReg(),
18051 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
18053 MachineFunction::iterator MBBIter = BB;
18056 MF->insert(MBBIter, bumpMBB);
18057 MF->insert(MBBIter, mallocMBB);
18058 MF->insert(MBBIter, continueMBB);
18060 continueMBB->splice(continueMBB->begin(), BB,
18061 std::next(MachineBasicBlock::iterator(MI)), BB->end());
18062 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
18064 // Add code to the main basic block to check if the stack limit has been hit,
18065 // and if so, jump to mallocMBB otherwise to bumpMBB.
18066 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
18067 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
18068 .addReg(tmpSPVReg).addReg(sizeVReg);
18069 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
18070 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
18071 .addReg(SPLimitVReg);
18072 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
18074 // bumpMBB simply decreases the stack pointer, since we know the current
18075 // stacklet has enough space.
18076 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
18077 .addReg(SPLimitVReg);
18078 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
18079 .addReg(SPLimitVReg);
18080 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18082 // Calls into a routine in libgcc to allocate more space from the heap.
18083 const uint32_t *RegMask = MF->getTarget()
18084 .getSubtargetImpl()
18085 ->getRegisterInfo()
18086 ->getCallPreservedMask(CallingConv::C);
18088 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
18090 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
18091 .addExternalSymbol("__morestack_allocate_stack_space")
18092 .addRegMask(RegMask)
18093 .addReg(X86::RDI, RegState::Implicit)
18094 .addReg(X86::RAX, RegState::ImplicitDefine);
18096 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
18098 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
18099 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
18100 .addExternalSymbol("__morestack_allocate_stack_space")
18101 .addRegMask(RegMask)
18102 .addReg(X86::EAX, RegState::ImplicitDefine);
18106 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
18109 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
18110 .addReg(Is64Bit ? X86::RAX : X86::EAX);
18111 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
18113 // Set up the CFG correctly.
18114 BB->addSuccessor(bumpMBB);
18115 BB->addSuccessor(mallocMBB);
18116 mallocMBB->addSuccessor(continueMBB);
18117 bumpMBB->addSuccessor(continueMBB);
18119 // Take care of the PHI nodes.
18120 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
18121 MI->getOperand(0).getReg())
18122 .addReg(mallocPtrVReg).addMBB(mallocMBB)
18123 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
18125 // Delete the original pseudo instruction.
18126 MI->eraseFromParent();
18129 return continueMBB;
18132 MachineBasicBlock *
18133 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
18134 MachineBasicBlock *BB) const {
18135 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
18136 DebugLoc DL = MI->getDebugLoc();
18138 assert(!Subtarget->isTargetMacho());
18140 // The lowering is pretty easy: we're just emitting the call to _alloca. The
18141 // non-trivial part is impdef of ESP.
18143 if (Subtarget->isTargetWin64()) {
18144 if (Subtarget->isTargetCygMing()) {
18145 // ___chkstk(Mingw64):
18146 // Clobbers R10, R11, RAX and EFLAGS.
18148 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18149 .addExternalSymbol("___chkstk")
18150 .addReg(X86::RAX, RegState::Implicit)
18151 .addReg(X86::RSP, RegState::Implicit)
18152 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
18153 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
18154 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18156 // __chkstk(MSVCRT): does not update stack pointer.
18157 // Clobbers R10, R11 and EFLAGS.
18158 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
18159 .addExternalSymbol("__chkstk")
18160 .addReg(X86::RAX, RegState::Implicit)
18161 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18162 // RAX has the offset to be subtracted from RSP.
18163 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
18168 const char *StackProbeSymbol =
18169 Subtarget->isTargetKnownWindowsMSVC() ? "_chkstk" : "_alloca";
18171 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
18172 .addExternalSymbol(StackProbeSymbol)
18173 .addReg(X86::EAX, RegState::Implicit)
18174 .addReg(X86::ESP, RegState::Implicit)
18175 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
18176 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
18177 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
18180 MI->eraseFromParent(); // The pseudo instruction is gone now.
18184 MachineBasicBlock *
18185 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
18186 MachineBasicBlock *BB) const {
18187 // This is pretty easy. We're taking the value that we received from
18188 // our load from the relocation, sticking it in either RDI (x86-64)
18189 // or EAX and doing an indirect call. The return value will then
18190 // be in the normal return register.
18191 MachineFunction *F = BB->getParent();
18192 const X86InstrInfo *TII =
18193 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
18194 DebugLoc DL = MI->getDebugLoc();
18196 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
18197 assert(MI->getOperand(3).isGlobal() && "This should be a global");
18199 // Get a register mask for the lowered call.
18200 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
18201 // proper register mask.
18202 const uint32_t *RegMask = F->getTarget()
18203 .getSubtargetImpl()
18204 ->getRegisterInfo()
18205 ->getCallPreservedMask(CallingConv::C);
18206 if (Subtarget->is64Bit()) {
18207 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18208 TII->get(X86::MOV64rm), X86::RDI)
18210 .addImm(0).addReg(0)
18211 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18212 MI->getOperand(3).getTargetFlags())
18214 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
18215 addDirectMem(MIB, X86::RDI);
18216 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
18217 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
18218 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18219 TII->get(X86::MOV32rm), X86::EAX)
18221 .addImm(0).addReg(0)
18222 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18223 MI->getOperand(3).getTargetFlags())
18225 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18226 addDirectMem(MIB, X86::EAX);
18227 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18229 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
18230 TII->get(X86::MOV32rm), X86::EAX)
18231 .addReg(TII->getGlobalBaseReg(F))
18232 .addImm(0).addReg(0)
18233 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
18234 MI->getOperand(3).getTargetFlags())
18236 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
18237 addDirectMem(MIB, X86::EAX);
18238 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
18241 MI->eraseFromParent(); // The pseudo instruction is gone now.
18245 MachineBasicBlock *
18246 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
18247 MachineBasicBlock *MBB) const {
18248 DebugLoc DL = MI->getDebugLoc();
18249 MachineFunction *MF = MBB->getParent();
18250 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18251 MachineRegisterInfo &MRI = MF->getRegInfo();
18253 const BasicBlock *BB = MBB->getBasicBlock();
18254 MachineFunction::iterator I = MBB;
18257 // Memory Reference
18258 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18259 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18262 unsigned MemOpndSlot = 0;
18264 unsigned CurOp = 0;
18266 DstReg = MI->getOperand(CurOp++).getReg();
18267 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
18268 assert(RC->hasType(MVT::i32) && "Invalid destination!");
18269 unsigned mainDstReg = MRI.createVirtualRegister(RC);
18270 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
18272 MemOpndSlot = CurOp;
18274 MVT PVT = getPointerTy();
18275 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18276 "Invalid Pointer Size!");
18278 // For v = setjmp(buf), we generate
18281 // buf[LabelOffset] = restoreMBB
18282 // SjLjSetup restoreMBB
18288 // v = phi(main, restore)
18293 MachineBasicBlock *thisMBB = MBB;
18294 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18295 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18296 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
18297 MF->insert(I, mainMBB);
18298 MF->insert(I, sinkMBB);
18299 MF->push_back(restoreMBB);
18301 MachineInstrBuilder MIB;
18303 // Transfer the remainder of BB and its successor edges to sinkMBB.
18304 sinkMBB->splice(sinkMBB->begin(), MBB,
18305 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18306 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18309 unsigned PtrStoreOpc = 0;
18310 unsigned LabelReg = 0;
18311 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18312 Reloc::Model RM = MF->getTarget().getRelocationModel();
18313 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
18314 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
18316 // Prepare IP either in reg or imm.
18317 if (!UseImmLabel) {
18318 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
18319 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
18320 LabelReg = MRI.createVirtualRegister(PtrRC);
18321 if (Subtarget->is64Bit()) {
18322 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
18326 .addMBB(restoreMBB)
18329 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
18330 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
18331 .addReg(XII->getGlobalBaseReg(MF))
18334 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
18338 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
18340 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
18341 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18342 if (i == X86::AddrDisp)
18343 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
18345 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
18348 MIB.addReg(LabelReg);
18350 MIB.addMBB(restoreMBB);
18351 MIB.setMemRefs(MMOBegin, MMOEnd);
18353 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
18354 .addMBB(restoreMBB);
18356 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18357 MF->getSubtarget().getRegisterInfo());
18358 MIB.addRegMask(RegInfo->getNoPreservedMask());
18359 thisMBB->addSuccessor(mainMBB);
18360 thisMBB->addSuccessor(restoreMBB);
18364 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
18365 mainMBB->addSuccessor(sinkMBB);
18368 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18369 TII->get(X86::PHI), DstReg)
18370 .addReg(mainDstReg).addMBB(mainMBB)
18371 .addReg(restoreDstReg).addMBB(restoreMBB);
18374 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
18375 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
18376 restoreMBB->addSuccessor(sinkMBB);
18378 MI->eraseFromParent();
18382 MachineBasicBlock *
18383 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
18384 MachineBasicBlock *MBB) const {
18385 DebugLoc DL = MI->getDebugLoc();
18386 MachineFunction *MF = MBB->getParent();
18387 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
18388 MachineRegisterInfo &MRI = MF->getRegInfo();
18390 // Memory Reference
18391 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18392 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18394 MVT PVT = getPointerTy();
18395 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
18396 "Invalid Pointer Size!");
18398 const TargetRegisterClass *RC =
18399 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
18400 unsigned Tmp = MRI.createVirtualRegister(RC);
18401 // Since FP is only updated here but NOT referenced, it's treated as GPR.
18402 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
18403 MF->getSubtarget().getRegisterInfo());
18404 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
18405 unsigned SP = RegInfo->getStackRegister();
18407 MachineInstrBuilder MIB;
18409 const int64_t LabelOffset = 1 * PVT.getStoreSize();
18410 const int64_t SPOffset = 2 * PVT.getStoreSize();
18412 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
18413 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
18416 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
18417 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
18418 MIB.addOperand(MI->getOperand(i));
18419 MIB.setMemRefs(MMOBegin, MMOEnd);
18421 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
18422 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18423 if (i == X86::AddrDisp)
18424 MIB.addDisp(MI->getOperand(i), LabelOffset);
18426 MIB.addOperand(MI->getOperand(i));
18428 MIB.setMemRefs(MMOBegin, MMOEnd);
18430 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
18431 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
18432 if (i == X86::AddrDisp)
18433 MIB.addDisp(MI->getOperand(i), SPOffset);
18435 MIB.addOperand(MI->getOperand(i));
18437 MIB.setMemRefs(MMOBegin, MMOEnd);
18439 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
18441 MI->eraseFromParent();
18445 // Replace 213-type (isel default) FMA3 instructions with 231-type for
18446 // accumulator loops. Writing back to the accumulator allows the coalescer
18447 // to remove extra copies in the loop.
18448 MachineBasicBlock *
18449 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
18450 MachineBasicBlock *MBB) const {
18451 MachineOperand &AddendOp = MI->getOperand(3);
18453 // Bail out early if the addend isn't a register - we can't switch these.
18454 if (!AddendOp.isReg())
18457 MachineFunction &MF = *MBB->getParent();
18458 MachineRegisterInfo &MRI = MF.getRegInfo();
18460 // Check whether the addend is defined by a PHI:
18461 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
18462 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
18463 if (!AddendDef.isPHI())
18466 // Look for the following pattern:
18468 // %addend = phi [%entry, 0], [%loop, %result]
18470 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
18474 // %addend = phi [%entry, 0], [%loop, %result]
18476 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
18478 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
18479 assert(AddendDef.getOperand(i).isReg());
18480 MachineOperand PHISrcOp = AddendDef.getOperand(i);
18481 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
18482 if (&PHISrcInst == MI) {
18483 // Found a matching instruction.
18484 unsigned NewFMAOpc = 0;
18485 switch (MI->getOpcode()) {
18486 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
18487 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
18488 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
18489 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
18490 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
18491 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
18492 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
18493 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
18494 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
18495 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
18496 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
18497 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
18498 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
18499 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
18500 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
18501 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
18502 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
18503 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
18504 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
18505 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
18506 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
18507 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
18508 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
18509 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
18510 default: llvm_unreachable("Unrecognized FMA variant.");
18513 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
18514 MachineInstrBuilder MIB =
18515 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
18516 .addOperand(MI->getOperand(0))
18517 .addOperand(MI->getOperand(3))
18518 .addOperand(MI->getOperand(2))
18519 .addOperand(MI->getOperand(1));
18520 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
18521 MI->eraseFromParent();
18528 MachineBasicBlock *
18529 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
18530 MachineBasicBlock *BB) const {
18531 switch (MI->getOpcode()) {
18532 default: llvm_unreachable("Unexpected instr type to insert");
18533 case X86::TAILJMPd64:
18534 case X86::TAILJMPr64:
18535 case X86::TAILJMPm64:
18536 llvm_unreachable("TAILJMP64 would not be touched here.");
18537 case X86::TCRETURNdi64:
18538 case X86::TCRETURNri64:
18539 case X86::TCRETURNmi64:
18541 case X86::WIN_ALLOCA:
18542 return EmitLoweredWinAlloca(MI, BB);
18543 case X86::SEG_ALLOCA_32:
18544 return EmitLoweredSegAlloca(MI, BB, false);
18545 case X86::SEG_ALLOCA_64:
18546 return EmitLoweredSegAlloca(MI, BB, true);
18547 case X86::TLSCall_32:
18548 case X86::TLSCall_64:
18549 return EmitLoweredTLSCall(MI, BB);
18550 case X86::CMOV_GR8:
18551 case X86::CMOV_FR32:
18552 case X86::CMOV_FR64:
18553 case X86::CMOV_V4F32:
18554 case X86::CMOV_V2F64:
18555 case X86::CMOV_V2I64:
18556 case X86::CMOV_V8F32:
18557 case X86::CMOV_V4F64:
18558 case X86::CMOV_V4I64:
18559 case X86::CMOV_V16F32:
18560 case X86::CMOV_V8F64:
18561 case X86::CMOV_V8I64:
18562 case X86::CMOV_GR16:
18563 case X86::CMOV_GR32:
18564 case X86::CMOV_RFP32:
18565 case X86::CMOV_RFP64:
18566 case X86::CMOV_RFP80:
18567 return EmitLoweredSelect(MI, BB);
18569 case X86::FP32_TO_INT16_IN_MEM:
18570 case X86::FP32_TO_INT32_IN_MEM:
18571 case X86::FP32_TO_INT64_IN_MEM:
18572 case X86::FP64_TO_INT16_IN_MEM:
18573 case X86::FP64_TO_INT32_IN_MEM:
18574 case X86::FP64_TO_INT64_IN_MEM:
18575 case X86::FP80_TO_INT16_IN_MEM:
18576 case X86::FP80_TO_INT32_IN_MEM:
18577 case X86::FP80_TO_INT64_IN_MEM: {
18578 MachineFunction *F = BB->getParent();
18579 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
18580 DebugLoc DL = MI->getDebugLoc();
18582 // Change the floating point control register to use "round towards zero"
18583 // mode when truncating to an integer value.
18584 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
18585 addFrameReference(BuildMI(*BB, MI, DL,
18586 TII->get(X86::FNSTCW16m)), CWFrameIdx);
18588 // Load the old value of the high byte of the control word...
18590 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
18591 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
18594 // Set the high part to be round to zero...
18595 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
18598 // Reload the modified control word now...
18599 addFrameReference(BuildMI(*BB, MI, DL,
18600 TII->get(X86::FLDCW16m)), CWFrameIdx);
18602 // Restore the memory image of control word to original value
18603 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
18606 // Get the X86 opcode to use.
18608 switch (MI->getOpcode()) {
18609 default: llvm_unreachable("illegal opcode!");
18610 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
18611 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
18612 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
18613 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
18614 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
18615 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
18616 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
18617 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
18618 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
18622 MachineOperand &Op = MI->getOperand(0);
18624 AM.BaseType = X86AddressMode::RegBase;
18625 AM.Base.Reg = Op.getReg();
18627 AM.BaseType = X86AddressMode::FrameIndexBase;
18628 AM.Base.FrameIndex = Op.getIndex();
18630 Op = MI->getOperand(1);
18632 AM.Scale = Op.getImm();
18633 Op = MI->getOperand(2);
18635 AM.IndexReg = Op.getImm();
18636 Op = MI->getOperand(3);
18637 if (Op.isGlobal()) {
18638 AM.GV = Op.getGlobal();
18640 AM.Disp = Op.getImm();
18642 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
18643 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
18645 // Reload the original control word now.
18646 addFrameReference(BuildMI(*BB, MI, DL,
18647 TII->get(X86::FLDCW16m)), CWFrameIdx);
18649 MI->eraseFromParent(); // The pseudo instruction is gone now.
18652 // String/text processing lowering.
18653 case X86::PCMPISTRM128REG:
18654 case X86::VPCMPISTRM128REG:
18655 case X86::PCMPISTRM128MEM:
18656 case X86::VPCMPISTRM128MEM:
18657 case X86::PCMPESTRM128REG:
18658 case X86::VPCMPESTRM128REG:
18659 case X86::PCMPESTRM128MEM:
18660 case X86::VPCMPESTRM128MEM:
18661 assert(Subtarget->hasSSE42() &&
18662 "Target must have SSE4.2 or AVX features enabled");
18663 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18665 // String/text processing lowering.
18666 case X86::PCMPISTRIREG:
18667 case X86::VPCMPISTRIREG:
18668 case X86::PCMPISTRIMEM:
18669 case X86::VPCMPISTRIMEM:
18670 case X86::PCMPESTRIREG:
18671 case X86::VPCMPESTRIREG:
18672 case X86::PCMPESTRIMEM:
18673 case X86::VPCMPESTRIMEM:
18674 assert(Subtarget->hasSSE42() &&
18675 "Target must have SSE4.2 or AVX features enabled");
18676 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18678 // Thread synchronization.
18680 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
18685 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
18687 case X86::VASTART_SAVE_XMM_REGS:
18688 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
18690 case X86::VAARG_64:
18691 return EmitVAARG64WithCustomInserter(MI, BB);
18693 case X86::EH_SjLj_SetJmp32:
18694 case X86::EH_SjLj_SetJmp64:
18695 return emitEHSjLjSetJmp(MI, BB);
18697 case X86::EH_SjLj_LongJmp32:
18698 case X86::EH_SjLj_LongJmp64:
18699 return emitEHSjLjLongJmp(MI, BB);
18701 case TargetOpcode::STACKMAP:
18702 case TargetOpcode::PATCHPOINT:
18703 return emitPatchPoint(MI, BB);
18705 case X86::VFMADDPDr213r:
18706 case X86::VFMADDPSr213r:
18707 case X86::VFMADDSDr213r:
18708 case X86::VFMADDSSr213r:
18709 case X86::VFMSUBPDr213r:
18710 case X86::VFMSUBPSr213r:
18711 case X86::VFMSUBSDr213r:
18712 case X86::VFMSUBSSr213r:
18713 case X86::VFNMADDPDr213r:
18714 case X86::VFNMADDPSr213r:
18715 case X86::VFNMADDSDr213r:
18716 case X86::VFNMADDSSr213r:
18717 case X86::VFNMSUBPDr213r:
18718 case X86::VFNMSUBPSr213r:
18719 case X86::VFNMSUBSDr213r:
18720 case X86::VFNMSUBSSr213r:
18721 case X86::VFMADDPDr213rY:
18722 case X86::VFMADDPSr213rY:
18723 case X86::VFMSUBPDr213rY:
18724 case X86::VFMSUBPSr213rY:
18725 case X86::VFNMADDPDr213rY:
18726 case X86::VFNMADDPSr213rY:
18727 case X86::VFNMSUBPDr213rY:
18728 case X86::VFNMSUBPSr213rY:
18729 return emitFMA3Instr(MI, BB);
18733 //===----------------------------------------------------------------------===//
18734 // X86 Optimization Hooks
18735 //===----------------------------------------------------------------------===//
18737 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
18740 const SelectionDAG &DAG,
18741 unsigned Depth) const {
18742 unsigned BitWidth = KnownZero.getBitWidth();
18743 unsigned Opc = Op.getOpcode();
18744 assert((Opc >= ISD::BUILTIN_OP_END ||
18745 Opc == ISD::INTRINSIC_WO_CHAIN ||
18746 Opc == ISD::INTRINSIC_W_CHAIN ||
18747 Opc == ISD::INTRINSIC_VOID) &&
18748 "Should use MaskedValueIsZero if you don't know whether Op"
18749 " is a target node!");
18751 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
18765 // These nodes' second result is a boolean.
18766 if (Op.getResNo() == 0)
18769 case X86ISD::SETCC:
18770 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
18772 case ISD::INTRINSIC_WO_CHAIN: {
18773 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
18774 unsigned NumLoBits = 0;
18777 case Intrinsic::x86_sse_movmsk_ps:
18778 case Intrinsic::x86_avx_movmsk_ps_256:
18779 case Intrinsic::x86_sse2_movmsk_pd:
18780 case Intrinsic::x86_avx_movmsk_pd_256:
18781 case Intrinsic::x86_mmx_pmovmskb:
18782 case Intrinsic::x86_sse2_pmovmskb_128:
18783 case Intrinsic::x86_avx2_pmovmskb: {
18784 // High bits of movmskp{s|d}, pmovmskb are known zero.
18786 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
18787 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
18788 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
18789 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
18790 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
18791 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
18792 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
18793 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
18795 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
18804 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
18806 const SelectionDAG &,
18807 unsigned Depth) const {
18808 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
18809 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
18810 return Op.getValueType().getScalarType().getSizeInBits();
18816 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
18817 /// node is a GlobalAddress + offset.
18818 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
18819 const GlobalValue* &GA,
18820 int64_t &Offset) const {
18821 if (N->getOpcode() == X86ISD::Wrapper) {
18822 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
18823 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
18824 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
18828 return TargetLowering::isGAPlusOffset(N, GA, Offset);
18831 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
18832 /// same as extracting the high 128-bit part of 256-bit vector and then
18833 /// inserting the result into the low part of a new 256-bit vector
18834 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
18835 EVT VT = SVOp->getValueType(0);
18836 unsigned NumElems = VT.getVectorNumElements();
18838 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18839 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
18840 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18841 SVOp->getMaskElt(j) >= 0)
18847 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
18848 /// same as extracting the low 128-bit part of 256-bit vector and then
18849 /// inserting the result into the high part of a new 256-bit vector
18850 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
18851 EVT VT = SVOp->getValueType(0);
18852 unsigned NumElems = VT.getVectorNumElements();
18854 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18855 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
18856 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
18857 SVOp->getMaskElt(j) >= 0)
18863 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
18864 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
18865 TargetLowering::DAGCombinerInfo &DCI,
18866 const X86Subtarget* Subtarget) {
18868 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
18869 SDValue V1 = SVOp->getOperand(0);
18870 SDValue V2 = SVOp->getOperand(1);
18871 EVT VT = SVOp->getValueType(0);
18872 unsigned NumElems = VT.getVectorNumElements();
18874 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
18875 V2.getOpcode() == ISD::CONCAT_VECTORS) {
18879 // V UNDEF BUILD_VECTOR UNDEF
18881 // CONCAT_VECTOR CONCAT_VECTOR
18884 // RESULT: V + zero extended
18886 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
18887 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
18888 V1.getOperand(1).getOpcode() != ISD::UNDEF)
18891 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
18894 // To match the shuffle mask, the first half of the mask should
18895 // be exactly the first vector, and all the rest a splat with the
18896 // first element of the second one.
18897 for (unsigned i = 0; i != NumElems/2; ++i)
18898 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
18899 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
18902 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
18903 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
18904 if (Ld->hasNUsesOfValue(1, 0)) {
18905 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
18906 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
18908 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
18910 Ld->getPointerInfo(),
18911 Ld->getAlignment(),
18912 false/*isVolatile*/, true/*ReadMem*/,
18913 false/*WriteMem*/);
18915 // Make sure the newly-created LOAD is in the same position as Ld in
18916 // terms of dependency. We create a TokenFactor for Ld and ResNode,
18917 // and update uses of Ld's output chain to use the TokenFactor.
18918 if (Ld->hasAnyUseOfValue(1)) {
18919 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
18920 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
18921 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
18922 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
18923 SDValue(ResNode.getNode(), 1));
18926 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
18930 // Emit a zeroed vector and insert the desired subvector on its
18932 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18933 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
18934 return DCI.CombineTo(N, InsV);
18937 //===--------------------------------------------------------------------===//
18938 // Combine some shuffles into subvector extracts and inserts:
18941 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
18942 if (isShuffleHigh128VectorInsertLow(SVOp)) {
18943 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
18944 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
18945 return DCI.CombineTo(N, InsV);
18948 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
18949 if (isShuffleLow128VectorInsertHigh(SVOp)) {
18950 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
18951 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
18952 return DCI.CombineTo(N, InsV);
18958 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
18961 /// This is the leaf of the recursive combinine below. When we have found some
18962 /// chain of single-use x86 shuffle instructions and accumulated the combined
18963 /// shuffle mask represented by them, this will try to pattern match that mask
18964 /// into either a single instruction if there is a special purpose instruction
18965 /// for this operation, or into a PSHUFB instruction which is a fully general
18966 /// instruction but should only be used to replace chains over a certain depth.
18967 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
18968 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
18969 TargetLowering::DAGCombinerInfo &DCI,
18970 const X86Subtarget *Subtarget) {
18971 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
18973 // Find the operand that enters the chain. Note that multiple uses are OK
18974 // here, we're not going to remove the operand we find.
18975 SDValue Input = Op.getOperand(0);
18976 while (Input.getOpcode() == ISD::BITCAST)
18977 Input = Input.getOperand(0);
18979 MVT VT = Input.getSimpleValueType();
18980 MVT RootVT = Root.getSimpleValueType();
18983 // Just remove no-op shuffle masks.
18984 if (Mask.size() == 1) {
18985 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
18990 // Use the float domain if the operand type is a floating point type.
18991 bool FloatDomain = VT.isFloatingPoint();
18993 // If we don't have access to VEX encodings, the generic PSHUF instructions
18994 // are preferable to some of the specialized forms despite requiring one more
18995 // byte to encode because they can implicitly copy.
18997 // IF we *do* have VEX encodings, than we can use shorter, more specific
18998 // shuffle instructions freely as they can copy due to the extra register
19000 if (Subtarget->hasAVX()) {
19001 // We have both floating point and integer variants of shuffles that dup
19002 // either the low or high half of the vector.
19003 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
19004 bool Lo = Mask.equals(0, 0);
19005 unsigned Shuffle = FloatDomain ? (Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS)
19006 : (Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH);
19007 if (Depth == 1 && Root->getOpcode() == Shuffle)
19008 return false; // Nothing to do!
19009 MVT ShuffleVT = FloatDomain ? MVT::v4f32 : MVT::v2i64;
19010 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19011 DCI.AddToWorklist(Op.getNode());
19012 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19013 DCI.AddToWorklist(Op.getNode());
19014 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19019 // FIXME: We should match UNPCKLPS and UNPCKHPS here.
19021 // For the integer domain we have specialized instructions for duplicating
19022 // any element size from the low or high half.
19023 if (!FloatDomain &&
19024 (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3) ||
19025 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
19026 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
19027 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
19028 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
19030 bool Lo = Mask[0] == 0;
19031 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
19032 if (Depth == 1 && Root->getOpcode() == Shuffle)
19033 return false; // Nothing to do!
19035 switch (Mask.size()) {
19036 case 4: ShuffleVT = MVT::v4i32; break;
19037 case 8: ShuffleVT = MVT::v8i16; break;
19038 case 16: ShuffleVT = MVT::v16i8; break;
19040 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
19041 DCI.AddToWorklist(Op.getNode());
19042 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
19043 DCI.AddToWorklist(Op.getNode());
19044 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19050 // Don't try to re-form single instruction chains under any circumstances now
19051 // that we've done encoding canonicalization for them.
19055 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
19056 // can replace them with a single PSHUFB instruction profitably. Intel's
19057 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
19058 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
19059 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
19060 SmallVector<SDValue, 16> PSHUFBMask;
19061 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
19062 int Ratio = 16 / Mask.size();
19063 for (unsigned i = 0; i < 16; ++i) {
19064 int M = Ratio * Mask[i / Ratio] + i % Ratio;
19065 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
19067 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
19068 DCI.AddToWorklist(Op.getNode());
19069 SDValue PSHUFBMaskOp =
19070 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
19071 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
19072 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
19073 DCI.AddToWorklist(Op.getNode());
19074 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
19079 // Failed to find any combines.
19083 /// \brief Fully generic combining of x86 shuffle instructions.
19085 /// This should be the last combine run over the x86 shuffle instructions. Once
19086 /// they have been fully optimized, this will recursively consdier all chains
19087 /// of single-use shuffle instructions, build a generic model of the cumulative
19088 /// shuffle operation, and check for simpler instructions which implement this
19089 /// operation. We use this primarily for two purposes:
19091 /// 1) Collapse generic shuffles to specialized single instructions when
19092 /// equivalent. In most cases, this is just an encoding size win, but
19093 /// sometimes we will collapse multiple generic shuffles into a single
19094 /// special-purpose shuffle.
19095 /// 2) Look for sequences of shuffle instructions with 3 or more total
19096 /// instructions, and replace them with the slightly more expensive SSSE3
19097 /// PSHUFB instruction if available. We do this as the last combining step
19098 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
19099 /// a suitable short sequence of other instructions. The PHUFB will either
19100 /// use a register or have to read from memory and so is slightly (but only
19101 /// slightly) more expensive than the other shuffle instructions.
19103 /// Because this is inherently a quadratic operation (for each shuffle in
19104 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
19105 /// This should never be an issue in practice as the shuffle lowering doesn't
19106 /// produce sequences of more than 8 instructions.
19108 /// FIXME: We will currently miss some cases where the redundant shuffling
19109 /// would simplify under the threshold for PSHUFB formation because of
19110 /// combine-ordering. To fix this, we should do the redundant instruction
19111 /// combining in this recursive walk.
19112 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
19113 ArrayRef<int> IncomingMask, int Depth,
19114 bool HasPSHUFB, SelectionDAG &DAG,
19115 TargetLowering::DAGCombinerInfo &DCI,
19116 const X86Subtarget *Subtarget) {
19117 // Bound the depth of our recursive combine because this is ultimately
19118 // quadratic in nature.
19122 // Directly rip through bitcasts to find the underlying operand.
19123 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
19124 Op = Op.getOperand(0);
19126 MVT VT = Op.getSimpleValueType();
19127 if (!VT.isVector())
19128 return false; // Bail if we hit a non-vector.
19129 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
19130 // version should be added.
19131 if (VT.getSizeInBits() != 128)
19134 assert(Root.getSimpleValueType().isVector() &&
19135 "Shuffles operate on vector types!");
19136 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
19137 "Can only combine shuffles of the same vector register size.");
19139 if (!isTargetShuffle(Op.getOpcode()))
19141 SmallVector<int, 16> OpMask;
19143 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
19144 // We only can combine unary shuffles which we can decode the mask for.
19145 if (!HaveMask || !IsUnary)
19148 assert(VT.getVectorNumElements() == OpMask.size() &&
19149 "Different mask size from vector size!");
19151 SmallVector<int, 16> Mask;
19152 Mask.reserve(std::max(OpMask.size(), IncomingMask.size()));
19154 // Merge this shuffle operation's mask into our accumulated mask. This is
19155 // a bit tricky as the shuffle may have a different size from the root.
19156 if (OpMask.size() == IncomingMask.size()) {
19157 for (int M : IncomingMask)
19158 Mask.push_back(OpMask[M]);
19159 } else if (OpMask.size() < IncomingMask.size()) {
19160 assert(IncomingMask.size() % OpMask.size() == 0 &&
19161 "The smaller number of elements must divide the larger.");
19162 int Ratio = IncomingMask.size() / OpMask.size();
19163 for (int M : IncomingMask)
19164 Mask.push_back(Ratio * OpMask[M / Ratio] + M % Ratio);
19166 assert(OpMask.size() > IncomingMask.size() && "All other cases handled!");
19167 assert(OpMask.size() % IncomingMask.size() == 0 &&
19168 "The smaller number of elements must divide the larger.");
19169 int Ratio = OpMask.size() / IncomingMask.size();
19170 for (int i = 0, e = OpMask.size(); i < e; ++i)
19171 Mask.push_back(OpMask[Ratio * IncomingMask[i / Ratio] + i % Ratio]);
19174 // See if we can recurse into the operand to combine more things.
19175 switch (Op.getOpcode()) {
19176 case X86ISD::PSHUFB:
19178 case X86ISD::PSHUFD:
19179 case X86ISD::PSHUFHW:
19180 case X86ISD::PSHUFLW:
19181 if (Op.getOperand(0).hasOneUse() &&
19182 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19183 HasPSHUFB, DAG, DCI, Subtarget))
19187 case X86ISD::UNPCKL:
19188 case X86ISD::UNPCKH:
19189 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
19190 // We can't check for single use, we have to check that this shuffle is the only user.
19191 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
19192 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
19193 HasPSHUFB, DAG, DCI, Subtarget))
19198 // Minor canonicalization of the accumulated shuffle mask to make it easier
19199 // to match below. All this does is detect masks with squential pairs of
19200 // elements, and shrink them to the half-width mask. It does this in a loop
19201 // so it will reduce the size of the mask to the minimal width mask which
19202 // performs an equivalent shuffle.
19203 while (Mask.size() > 1) {
19204 SmallVector<int, 16> NewMask;
19205 for (int i = 0, e = Mask.size()/2; i < e; ++i) {
19206 if (Mask[2*i] % 2 != 0 || Mask[2*i] != Mask[2*i + 1] + 1) {
19210 NewMask.push_back(Mask[2*i] / 2);
19212 if (NewMask.empty())
19214 Mask.swap(NewMask);
19217 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
19221 /// \brief Get the PSHUF-style mask from PSHUF node.
19223 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
19224 /// PSHUF-style masks that can be reused with such instructions.
19225 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
19226 SmallVector<int, 4> Mask;
19228 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
19232 switch (N.getOpcode()) {
19233 case X86ISD::PSHUFD:
19235 case X86ISD::PSHUFLW:
19238 case X86ISD::PSHUFHW:
19239 Mask.erase(Mask.begin(), Mask.begin() + 4);
19240 for (int &M : Mask)
19244 llvm_unreachable("No valid shuffle instruction found!");
19248 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
19250 /// We walk up the chain and look for a combinable shuffle, skipping over
19251 /// shuffles that we could hoist this shuffle's transformation past without
19252 /// altering anything.
19253 static bool combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
19255 TargetLowering::DAGCombinerInfo &DCI) {
19256 assert(N.getOpcode() == X86ISD::PSHUFD &&
19257 "Called with something other than an x86 128-bit half shuffle!");
19260 // Walk up a single-use chain looking for a combinable shuffle.
19261 SDValue V = N.getOperand(0);
19262 for (; V.hasOneUse(); V = V.getOperand(0)) {
19263 switch (V.getOpcode()) {
19265 return false; // Nothing combined!
19268 // Skip bitcasts as we always know the type for the target specific
19272 case X86ISD::PSHUFD:
19273 // Found another dword shuffle.
19276 case X86ISD::PSHUFLW:
19277 // Check that the low words (being shuffled) are the identity in the
19278 // dword shuffle, and the high words are self-contained.
19279 if (Mask[0] != 0 || Mask[1] != 1 ||
19280 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
19285 case X86ISD::PSHUFHW:
19286 // Check that the high words (being shuffled) are the identity in the
19287 // dword shuffle, and the low words are self-contained.
19288 if (Mask[2] != 2 || Mask[3] != 3 ||
19289 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
19294 case X86ISD::UNPCKL:
19295 case X86ISD::UNPCKH:
19296 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
19297 // shuffle into a preceding word shuffle.
19298 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
19301 // Search for a half-shuffle which we can combine with.
19302 unsigned CombineOp =
19303 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19304 if (V.getOperand(0) != V.getOperand(1) ||
19305 !V->isOnlyUserOf(V.getOperand(0).getNode()))
19307 V = V.getOperand(0);
19309 switch (V.getOpcode()) {
19311 return false; // Nothing to combine.
19313 case X86ISD::PSHUFLW:
19314 case X86ISD::PSHUFHW:
19315 if (V.getOpcode() == CombineOp)
19320 V = V.getOperand(0);
19324 } while (V.hasOneUse());
19327 // Break out of the loop if we break out of the switch.
19331 if (!V.hasOneUse())
19332 // We fell out of the loop without finding a viable combining instruction.
19335 // Record the old value to use in RAUW-ing.
19338 // Merge this node's mask and our incoming mask.
19339 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19340 for (int &M : Mask)
19342 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
19343 getV4X86ShuffleImm8ForMask(Mask, DAG));
19345 // It is possible that one of the combinable shuffles was completely absorbed
19346 // by the other, just replace it and revisit all users in that case.
19347 if (Old.getNode() == V.getNode()) {
19348 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo=*/true);
19352 // Replace N with its operand as we're going to combine that shuffle away.
19353 DAG.ReplaceAllUsesWith(N, N.getOperand(0));
19355 // Replace the combinable shuffle with the combined one, updating all users
19356 // so that we re-evaluate the chain here.
19357 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19361 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
19363 /// We walk up the chain, skipping shuffles of the other half and looking
19364 /// through shuffles which switch halves trying to find a shuffle of the same
19365 /// pair of dwords.
19366 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
19368 TargetLowering::DAGCombinerInfo &DCI) {
19370 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
19371 "Called with something other than an x86 128-bit half shuffle!");
19373 unsigned CombineOpcode = N.getOpcode();
19375 // Walk up a single-use chain looking for a combinable shuffle.
19376 SDValue V = N.getOperand(0);
19377 for (; V.hasOneUse(); V = V.getOperand(0)) {
19378 switch (V.getOpcode()) {
19380 return false; // Nothing combined!
19383 // Skip bitcasts as we always know the type for the target specific
19387 case X86ISD::PSHUFLW:
19388 case X86ISD::PSHUFHW:
19389 if (V.getOpcode() == CombineOpcode)
19392 // Other-half shuffles are no-ops.
19395 case X86ISD::PSHUFD: {
19396 // We can only handle pshufd if the half we are combining either stays in
19397 // its half, or switches to the other half. Bail if one of these isn't
19399 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19400 int DOffset = CombineOpcode == X86ISD::PSHUFLW ? 0 : 2;
19401 if (!((VMask[DOffset + 0] < 2 && VMask[DOffset + 1] < 2) ||
19402 (VMask[DOffset + 0] >= 2 && VMask[DOffset + 1] >= 2)))
19405 // Map the mask through the pshufd and keep walking up the chain.
19406 for (int i = 0; i < 4; ++i)
19407 Mask[i] = 2 * (VMask[DOffset + Mask[i] / 2] % 2) + Mask[i] % 2;
19409 // Switch halves if the pshufd does.
19411 VMask[DOffset + Mask[0] / 2] < 2 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
19415 // Break out of the loop if we break out of the switch.
19419 if (!V.hasOneUse())
19420 // We fell out of the loop without finding a viable combining instruction.
19423 // Combine away the bottom node as its shuffle will be accumulated into
19424 // a preceding shuffle.
19425 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19427 // Record the old value.
19430 // Merge this node's mask and our incoming mask (adjusted to account for all
19431 // the pshufd instructions encountered).
19432 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19433 for (int &M : Mask)
19435 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
19436 getV4X86ShuffleImm8ForMask(Mask, DAG));
19438 // Check that the shuffles didn't cancel each other out. If not, we need to
19439 // combine to the new one.
19441 // Replace the combinable shuffle with the combined one, updating all users
19442 // so that we re-evaluate the chain here.
19443 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
19448 /// \brief Try to combine x86 target specific shuffles.
19449 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
19450 TargetLowering::DAGCombinerInfo &DCI,
19451 const X86Subtarget *Subtarget) {
19453 MVT VT = N.getSimpleValueType();
19454 SmallVector<int, 4> Mask;
19456 switch (N.getOpcode()) {
19457 case X86ISD::PSHUFD:
19458 case X86ISD::PSHUFLW:
19459 case X86ISD::PSHUFHW:
19460 Mask = getPSHUFShuffleMask(N);
19461 assert(Mask.size() == 4);
19467 // Nuke no-op shuffles that show up after combining.
19468 if (isNoopShuffleMask(Mask))
19469 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
19471 // Look for simplifications involving one or two shuffle instructions.
19472 SDValue V = N.getOperand(0);
19473 switch (N.getOpcode()) {
19476 case X86ISD::PSHUFLW:
19477 case X86ISD::PSHUFHW:
19478 assert(VT == MVT::v8i16);
19481 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
19482 return SDValue(); // We combined away this shuffle, so we're done.
19484 // See if this reduces to a PSHUFD which is no more expensive and can
19485 // combine with more operations.
19486 if (Mask[0] % 2 == 0 && Mask[2] % 2 == 0 &&
19487 areAdjacentMasksSequential(Mask)) {
19488 int DMask[] = {-1, -1, -1, -1};
19489 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
19490 DMask[DOffset + 0] = DOffset + Mask[0] / 2;
19491 DMask[DOffset + 1] = DOffset + Mask[2] / 2;
19492 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
19493 DCI.AddToWorklist(V.getNode());
19494 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
19495 getV4X86ShuffleImm8ForMask(DMask, DAG));
19496 DCI.AddToWorklist(V.getNode());
19497 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
19500 // Look for shuffle patterns which can be implemented as a single unpack.
19501 // FIXME: This doesn't handle the location of the PSHUFD generically, and
19502 // only works when we have a PSHUFD followed by two half-shuffles.
19503 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
19504 (V.getOpcode() == X86ISD::PSHUFLW ||
19505 V.getOpcode() == X86ISD::PSHUFHW) &&
19506 V.getOpcode() != N.getOpcode() &&
19508 SDValue D = V.getOperand(0);
19509 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
19510 D = D.getOperand(0);
19511 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
19512 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
19513 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
19514 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19515 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
19517 for (int i = 0; i < 4; ++i) {
19518 WordMask[i + NOffset] = Mask[i] + NOffset;
19519 WordMask[i + VOffset] = VMask[i] + VOffset;
19521 // Map the word mask through the DWord mask.
19523 for (int i = 0; i < 8; ++i)
19524 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
19525 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
19526 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
19527 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
19528 std::begin(UnpackLoMask)) ||
19529 std::equal(std::begin(MappedMask), std::end(MappedMask),
19530 std::begin(UnpackHiMask))) {
19531 // We can replace all three shuffles with an unpack.
19532 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
19533 DCI.AddToWorklist(V.getNode());
19534 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
19536 DL, MVT::v8i16, V, V);
19543 case X86ISD::PSHUFD:
19544 if (combineRedundantDWordShuffle(N, Mask, DAG, DCI))
19545 return SDValue(); // We combined away this shuffle.
19553 /// PerformShuffleCombine - Performs several different shuffle combines.
19554 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
19555 TargetLowering::DAGCombinerInfo &DCI,
19556 const X86Subtarget *Subtarget) {
19558 SDValue N0 = N->getOperand(0);
19559 SDValue N1 = N->getOperand(1);
19560 EVT VT = N->getValueType(0);
19562 // Don't create instructions with illegal types after legalize types has run.
19563 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19564 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
19567 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
19568 if (Subtarget->hasFp256() && VT.is256BitVector() &&
19569 N->getOpcode() == ISD::VECTOR_SHUFFLE)
19570 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
19572 // During Type Legalization, when promoting illegal vector types,
19573 // the backend might introduce new shuffle dag nodes and bitcasts.
19575 // This code performs the following transformation:
19576 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
19577 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
19579 // We do this only if both the bitcast and the BINOP dag nodes have
19580 // one use. Also, perform this transformation only if the new binary
19581 // operation is legal. This is to avoid introducing dag nodes that
19582 // potentially need to be further expanded (or custom lowered) into a
19583 // less optimal sequence of dag nodes.
19584 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
19585 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
19586 N0.getOpcode() == ISD::BITCAST) {
19587 SDValue BC0 = N0.getOperand(0);
19588 EVT SVT = BC0.getValueType();
19589 unsigned Opcode = BC0.getOpcode();
19590 unsigned NumElts = VT.getVectorNumElements();
19592 if (BC0.hasOneUse() && SVT.isVector() &&
19593 SVT.getVectorNumElements() * 2 == NumElts &&
19594 TLI.isOperationLegal(Opcode, VT)) {
19595 bool CanFold = false;
19607 unsigned SVTNumElts = SVT.getVectorNumElements();
19608 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
19609 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
19610 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
19611 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
19612 CanFold = SVOp->getMaskElt(i) < 0;
19615 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
19616 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
19617 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
19618 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
19623 // Only handle 128 wide vector from here on.
19624 if (!VT.is128BitVector())
19627 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
19628 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
19629 // consecutive, non-overlapping, and in the right order.
19630 SmallVector<SDValue, 16> Elts;
19631 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
19632 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
19634 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
19638 if (isTargetShuffle(N->getOpcode())) {
19640 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
19641 if (Shuffle.getNode())
19644 // Try recursively combining arbitrary sequences of x86 shuffle
19645 // instructions into higher-order shuffles. We do this after combining
19646 // specific PSHUF instruction sequences into their minimal form so that we
19647 // can evaluate how many specialized shuffle instructions are involved in
19648 // a particular chain.
19649 SmallVector<int, 1> NonceMask; // Just a placeholder.
19650 NonceMask.push_back(0);
19651 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
19652 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
19654 return SDValue(); // This routine will use CombineTo to replace N.
19660 /// PerformTruncateCombine - Converts truncate operation to
19661 /// a sequence of vector shuffle operations.
19662 /// It is possible when we truncate 256-bit vector to 128-bit vector
19663 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
19664 TargetLowering::DAGCombinerInfo &DCI,
19665 const X86Subtarget *Subtarget) {
19669 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
19670 /// specific shuffle of a load can be folded into a single element load.
19671 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
19672 /// shuffles have been customed lowered so we need to handle those here.
19673 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
19674 TargetLowering::DAGCombinerInfo &DCI) {
19675 if (DCI.isBeforeLegalizeOps())
19678 SDValue InVec = N->getOperand(0);
19679 SDValue EltNo = N->getOperand(1);
19681 if (!isa<ConstantSDNode>(EltNo))
19684 EVT VT = InVec.getValueType();
19686 bool HasShuffleIntoBitcast = false;
19687 if (InVec.getOpcode() == ISD::BITCAST) {
19688 // Don't duplicate a load with other uses.
19689 if (!InVec.hasOneUse())
19691 EVT BCVT = InVec.getOperand(0).getValueType();
19692 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
19694 InVec = InVec.getOperand(0);
19695 HasShuffleIntoBitcast = true;
19698 if (!isTargetShuffle(InVec.getOpcode()))
19701 // Don't duplicate a load with other uses.
19702 if (!InVec.hasOneUse())
19705 SmallVector<int, 16> ShuffleMask;
19707 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
19711 // Select the input vector, guarding against out of range extract vector.
19712 unsigned NumElems = VT.getVectorNumElements();
19713 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
19714 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
19715 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
19716 : InVec.getOperand(1);
19718 // If inputs to shuffle are the same for both ops, then allow 2 uses
19719 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
19721 if (LdNode.getOpcode() == ISD::BITCAST) {
19722 // Don't duplicate a load with other uses.
19723 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
19726 AllowedUses = 1; // only allow 1 load use if we have a bitcast
19727 LdNode = LdNode.getOperand(0);
19730 if (!ISD::isNormalLoad(LdNode.getNode()))
19733 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
19735 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
19738 if (HasShuffleIntoBitcast) {
19739 // If there's a bitcast before the shuffle, check if the load type and
19740 // alignment is valid.
19741 unsigned Align = LN0->getAlignment();
19742 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19743 unsigned NewAlign = TLI.getDataLayout()->
19744 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
19746 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
19750 // All checks match so transform back to vector_shuffle so that DAG combiner
19751 // can finish the job
19754 // Create shuffle node taking into account the case that its a unary shuffle
19755 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
19756 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
19757 InVec.getOperand(0), Shuffle,
19759 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
19760 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
19764 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
19765 /// generation and convert it from being a bunch of shuffles and extracts
19766 /// to a simple store and scalar loads to extract the elements.
19767 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
19768 TargetLowering::DAGCombinerInfo &DCI) {
19769 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
19770 if (NewOp.getNode())
19773 SDValue InputVector = N->getOperand(0);
19775 // Detect whether we are trying to convert from mmx to i32 and the bitcast
19776 // from mmx to v2i32 has a single usage.
19777 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
19778 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
19779 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
19780 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
19781 N->getValueType(0),
19782 InputVector.getNode()->getOperand(0));
19784 // Only operate on vectors of 4 elements, where the alternative shuffling
19785 // gets to be more expensive.
19786 if (InputVector.getValueType() != MVT::v4i32)
19789 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
19790 // single use which is a sign-extend or zero-extend, and all elements are
19792 SmallVector<SDNode *, 4> Uses;
19793 unsigned ExtractedElements = 0;
19794 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
19795 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
19796 if (UI.getUse().getResNo() != InputVector.getResNo())
19799 SDNode *Extract = *UI;
19800 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
19803 if (Extract->getValueType(0) != MVT::i32)
19805 if (!Extract->hasOneUse())
19807 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
19808 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
19810 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
19813 // Record which element was extracted.
19814 ExtractedElements |=
19815 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
19817 Uses.push_back(Extract);
19820 // If not all the elements were used, this may not be worthwhile.
19821 if (ExtractedElements != 15)
19824 // Ok, we've now decided to do the transformation.
19825 SDLoc dl(InputVector);
19827 // Store the value to a temporary stack slot.
19828 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
19829 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
19830 MachinePointerInfo(), false, false, 0);
19832 // Replace each use (extract) with a load of the appropriate element.
19833 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
19834 UE = Uses.end(); UI != UE; ++UI) {
19835 SDNode *Extract = *UI;
19837 // cOMpute the element's address.
19838 SDValue Idx = Extract->getOperand(1);
19840 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
19841 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
19842 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19843 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
19845 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
19846 StackPtr, OffsetVal);
19848 // Load the scalar.
19849 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
19850 ScalarAddr, MachinePointerInfo(),
19851 false, false, false, 0);
19853 // Replace the exact with the load.
19854 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
19857 // The replacement was made in place; don't return anything.
19861 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
19862 static std::pair<unsigned, bool>
19863 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
19864 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
19865 if (!VT.isVector())
19866 return std::make_pair(0, false);
19868 bool NeedSplit = false;
19869 switch (VT.getSimpleVT().SimpleTy) {
19870 default: return std::make_pair(0, false);
19874 if (!Subtarget->hasAVX2())
19876 if (!Subtarget->hasAVX())
19877 return std::make_pair(0, false);
19882 if (!Subtarget->hasSSE2())
19883 return std::make_pair(0, false);
19886 // SSE2 has only a small subset of the operations.
19887 bool hasUnsigned = Subtarget->hasSSE41() ||
19888 (Subtarget->hasSSE2() && VT == MVT::v16i8);
19889 bool hasSigned = Subtarget->hasSSE41() ||
19890 (Subtarget->hasSSE2() && VT == MVT::v8i16);
19892 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
19895 // Check for x CC y ? x : y.
19896 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
19897 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
19902 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19905 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19908 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19911 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19913 // Check for x CC y ? y : x -- a min/max with reversed arms.
19914 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
19915 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
19920 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
19923 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
19926 Opc = hasSigned ? X86ISD::SMAX : 0; break;
19929 Opc = hasSigned ? X86ISD::SMIN : 0; break;
19933 return std::make_pair(Opc, NeedSplit);
19937 TransformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
19938 const X86Subtarget *Subtarget) {
19940 SDValue Cond = N->getOperand(0);
19941 SDValue LHS = N->getOperand(1);
19942 SDValue RHS = N->getOperand(2);
19944 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
19945 SDValue CondSrc = Cond->getOperand(0);
19946 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
19947 Cond = CondSrc->getOperand(0);
19950 MVT VT = N->getSimpleValueType(0);
19951 MVT EltVT = VT.getVectorElementType();
19952 unsigned NumElems = VT.getVectorNumElements();
19953 // There is no blend with immediate in AVX-512.
19954 if (VT.is512BitVector())
19957 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
19959 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
19962 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
19965 unsigned MaskValue = 0;
19966 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
19969 SmallVector<int, 8> ShuffleMask(NumElems, -1);
19970 for (unsigned i = 0; i < NumElems; ++i) {
19971 // Be sure we emit undef where we can.
19972 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
19973 ShuffleMask[i] = -1;
19975 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
19978 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
19981 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
19983 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
19984 TargetLowering::DAGCombinerInfo &DCI,
19985 const X86Subtarget *Subtarget) {
19987 SDValue Cond = N->getOperand(0);
19988 // Get the LHS/RHS of the select.
19989 SDValue LHS = N->getOperand(1);
19990 SDValue RHS = N->getOperand(2);
19991 EVT VT = LHS.getValueType();
19992 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19994 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
19995 // instructions match the semantics of the common C idiom x<y?x:y but not
19996 // x<=y?x:y, because of how they handle negative zero (which can be
19997 // ignored in unsafe-math mode).
19998 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
19999 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
20000 (Subtarget->hasSSE2() ||
20001 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
20002 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20004 unsigned Opcode = 0;
20005 // Check for x CC y ? x : y.
20006 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20007 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20011 // Converting this to a min would handle NaNs incorrectly, and swapping
20012 // the operands would cause it to handle comparisons between positive
20013 // and negative zero incorrectly.
20014 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20015 if (!DAG.getTarget().Options.UnsafeFPMath &&
20016 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20018 std::swap(LHS, RHS);
20020 Opcode = X86ISD::FMIN;
20023 // Converting this to a min would handle comparisons between positive
20024 // and negative zero incorrectly.
20025 if (!DAG.getTarget().Options.UnsafeFPMath &&
20026 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20028 Opcode = X86ISD::FMIN;
20031 // Converting this to a min would handle both negative zeros and NaNs
20032 // incorrectly, but we can swap the operands to fix both.
20033 std::swap(LHS, RHS);
20037 Opcode = X86ISD::FMIN;
20041 // Converting this to a max would handle comparisons between positive
20042 // and negative zero incorrectly.
20043 if (!DAG.getTarget().Options.UnsafeFPMath &&
20044 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
20046 Opcode = X86ISD::FMAX;
20049 // Converting this to a max would handle NaNs incorrectly, and swapping
20050 // the operands would cause it to handle comparisons between positive
20051 // and negative zero incorrectly.
20052 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
20053 if (!DAG.getTarget().Options.UnsafeFPMath &&
20054 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
20056 std::swap(LHS, RHS);
20058 Opcode = X86ISD::FMAX;
20061 // Converting this to a max would handle both negative zeros and NaNs
20062 // incorrectly, but we can swap the operands to fix both.
20063 std::swap(LHS, RHS);
20067 Opcode = X86ISD::FMAX;
20070 // Check for x CC y ? y : x -- a min/max with reversed arms.
20071 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
20072 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
20076 // Converting this to a min would handle comparisons between positive
20077 // and negative zero incorrectly, and swapping the operands would
20078 // cause it to handle NaNs incorrectly.
20079 if (!DAG.getTarget().Options.UnsafeFPMath &&
20080 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
20081 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20083 std::swap(LHS, RHS);
20085 Opcode = X86ISD::FMIN;
20088 // Converting this to a min would handle NaNs incorrectly.
20089 if (!DAG.getTarget().Options.UnsafeFPMath &&
20090 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
20092 Opcode = X86ISD::FMIN;
20095 // Converting this to a min would handle both negative zeros and NaNs
20096 // incorrectly, but we can swap the operands to fix both.
20097 std::swap(LHS, RHS);
20101 Opcode = X86ISD::FMIN;
20105 // Converting this to a max would handle NaNs incorrectly.
20106 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20108 Opcode = X86ISD::FMAX;
20111 // Converting this to a max would handle comparisons between positive
20112 // and negative zero incorrectly, and swapping the operands would
20113 // cause it to handle NaNs incorrectly.
20114 if (!DAG.getTarget().Options.UnsafeFPMath &&
20115 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
20116 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
20118 std::swap(LHS, RHS);
20120 Opcode = X86ISD::FMAX;
20123 // Converting this to a max would handle both negative zeros and NaNs
20124 // incorrectly, but we can swap the operands to fix both.
20125 std::swap(LHS, RHS);
20129 Opcode = X86ISD::FMAX;
20135 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
20138 EVT CondVT = Cond.getValueType();
20139 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
20140 CondVT.getVectorElementType() == MVT::i1) {
20141 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
20142 // lowering on AVX-512. In this case we convert it to
20143 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
20144 // The same situation for all 128 and 256-bit vectors of i8 and i16
20145 EVT OpVT = LHS.getValueType();
20146 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
20147 (OpVT.getVectorElementType() == MVT::i8 ||
20148 OpVT.getVectorElementType() == MVT::i16)) {
20149 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
20150 DCI.AddToWorklist(Cond.getNode());
20151 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
20154 // If this is a select between two integer constants, try to do some
20156 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
20157 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
20158 // Don't do this for crazy integer types.
20159 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
20160 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
20161 // so that TrueC (the true value) is larger than FalseC.
20162 bool NeedsCondInvert = false;
20164 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
20165 // Efficiently invertible.
20166 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
20167 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
20168 isa<ConstantSDNode>(Cond.getOperand(1))))) {
20169 NeedsCondInvert = true;
20170 std::swap(TrueC, FalseC);
20173 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
20174 if (FalseC->getAPIntValue() == 0 &&
20175 TrueC->getAPIntValue().isPowerOf2()) {
20176 if (NeedsCondInvert) // Invert the condition if needed.
20177 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20178 DAG.getConstant(1, Cond.getValueType()));
20180 // Zero extend the condition if needed.
20181 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
20183 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20184 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
20185 DAG.getConstant(ShAmt, MVT::i8));
20188 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
20189 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20190 if (NeedsCondInvert) // Invert the condition if needed.
20191 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20192 DAG.getConstant(1, Cond.getValueType()));
20194 // Zero extend the condition if needed.
20195 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20196 FalseC->getValueType(0), Cond);
20197 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20198 SDValue(FalseC, 0));
20201 // Optimize cases that will turn into an LEA instruction. This requires
20202 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20203 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20204 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20205 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20207 bool isFastMultiplier = false;
20209 switch ((unsigned char)Diff) {
20211 case 1: // result = add base, cond
20212 case 2: // result = lea base( , cond*2)
20213 case 3: // result = lea base(cond, cond*2)
20214 case 4: // result = lea base( , cond*4)
20215 case 5: // result = lea base(cond, cond*4)
20216 case 8: // result = lea base( , cond*8)
20217 case 9: // result = lea base(cond, cond*8)
20218 isFastMultiplier = true;
20223 if (isFastMultiplier) {
20224 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20225 if (NeedsCondInvert) // Invert the condition if needed.
20226 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
20227 DAG.getConstant(1, Cond.getValueType()));
20229 // Zero extend the condition if needed.
20230 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20232 // Scale the condition by the difference.
20234 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20235 DAG.getConstant(Diff, Cond.getValueType()));
20237 // Add the base if non-zero.
20238 if (FalseC->getAPIntValue() != 0)
20239 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20240 SDValue(FalseC, 0));
20247 // Canonicalize max and min:
20248 // (x > y) ? x : y -> (x >= y) ? x : y
20249 // (x < y) ? x : y -> (x <= y) ? x : y
20250 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
20251 // the need for an extra compare
20252 // against zero. e.g.
20253 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
20255 // testl %edi, %edi
20257 // cmovgl %edi, %eax
20261 // cmovsl %eax, %edi
20262 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
20263 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
20264 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
20265 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20270 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
20271 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
20272 Cond.getOperand(0), Cond.getOperand(1), NewCC);
20273 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
20278 // Early exit check
20279 if (!TLI.isTypeLegal(VT))
20282 // Match VSELECTs into subs with unsigned saturation.
20283 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20284 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
20285 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
20286 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
20287 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
20289 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
20290 // left side invert the predicate to simplify logic below.
20292 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
20294 CC = ISD::getSetCCInverse(CC, true);
20295 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
20299 if (Other.getNode() && Other->getNumOperands() == 2 &&
20300 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
20301 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
20302 SDValue CondRHS = Cond->getOperand(1);
20304 // Look for a general sub with unsigned saturation first.
20305 // x >= y ? x-y : 0 --> subus x, y
20306 // x > y ? x-y : 0 --> subus x, y
20307 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
20308 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
20309 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
20311 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
20312 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
20313 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
20314 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
20315 // If the RHS is a constant we have to reverse the const
20316 // canonicalization.
20317 // x > C-1 ? x+-C : 0 --> subus x, C
20318 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
20319 CondRHSConst->getAPIntValue() ==
20320 (-OpRHSConst->getAPIntValue() - 1))
20321 return DAG.getNode(
20322 X86ISD::SUBUS, DL, VT, OpLHS,
20323 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
20325 // Another special case: If C was a sign bit, the sub has been
20326 // canonicalized into a xor.
20327 // FIXME: Would it be better to use computeKnownBits to determine
20328 // whether it's safe to decanonicalize the xor?
20329 // x s< 0 ? x^C : 0 --> subus x, C
20330 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
20331 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
20332 OpRHSConst->getAPIntValue().isSignBit())
20333 // Note that we have to rebuild the RHS constant here to ensure we
20334 // don't rely on particular values of undef lanes.
20335 return DAG.getNode(
20336 X86ISD::SUBUS, DL, VT, OpLHS,
20337 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
20342 // Try to match a min/max vector operation.
20343 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
20344 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
20345 unsigned Opc = ret.first;
20346 bool NeedSplit = ret.second;
20348 if (Opc && NeedSplit) {
20349 unsigned NumElems = VT.getVectorNumElements();
20350 // Extract the LHS vectors
20351 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
20352 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
20354 // Extract the RHS vectors
20355 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
20356 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
20358 // Create min/max for each subvector
20359 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
20360 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
20362 // Merge the result
20363 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
20365 return DAG.getNode(Opc, DL, VT, LHS, RHS);
20368 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
20369 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
20370 // Check if SETCC has already been promoted
20371 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
20372 // Check that condition value type matches vselect operand type
20375 assert(Cond.getValueType().isVector() &&
20376 "vector select expects a vector selector!");
20378 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
20379 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
20381 if (!TValIsAllOnes && !FValIsAllZeros) {
20382 // Try invert the condition if true value is not all 1s and false value
20384 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
20385 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
20387 if (TValIsAllZeros || FValIsAllOnes) {
20388 SDValue CC = Cond.getOperand(2);
20389 ISD::CondCode NewCC =
20390 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
20391 Cond.getOperand(0).getValueType().isInteger());
20392 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
20393 std::swap(LHS, RHS);
20394 TValIsAllOnes = FValIsAllOnes;
20395 FValIsAllZeros = TValIsAllZeros;
20399 if (TValIsAllOnes || FValIsAllZeros) {
20402 if (TValIsAllOnes && FValIsAllZeros)
20404 else if (TValIsAllOnes)
20405 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
20406 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
20407 else if (FValIsAllZeros)
20408 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
20409 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
20411 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
20415 // Try to fold this VSELECT into a MOVSS/MOVSD
20416 if (N->getOpcode() == ISD::VSELECT &&
20417 Cond.getOpcode() == ISD::BUILD_VECTOR && !DCI.isBeforeLegalize()) {
20418 if (VT == MVT::v4i32 || VT == MVT::v4f32 ||
20419 (Subtarget->hasSSE2() && (VT == MVT::v2i64 || VT == MVT::v2f64))) {
20420 bool CanFold = false;
20421 unsigned NumElems = Cond.getNumOperands();
20425 if (isZero(Cond.getOperand(0))) {
20428 // fold (vselect <0,-1,-1,-1>, A, B) -> (movss A, B)
20429 // fold (vselect <0,-1> -> (movsd A, B)
20430 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20431 CanFold = isAllOnes(Cond.getOperand(i));
20432 } else if (isAllOnes(Cond.getOperand(0))) {
20436 // fold (vselect <-1,0,0,0>, A, B) -> (movss B, A)
20437 // fold (vselect <-1,0> -> (movsd B, A)
20438 for (unsigned i = 1, e = NumElems; i != e && CanFold; ++i)
20439 CanFold = isZero(Cond.getOperand(i));
20443 if (VT == MVT::v4i32 || VT == MVT::v4f32)
20444 return getTargetShuffleNode(X86ISD::MOVSS, DL, VT, A, B, DAG);
20445 return getTargetShuffleNode(X86ISD::MOVSD, DL, VT, A, B, DAG);
20448 if (Subtarget->hasSSE2() && (VT == MVT::v4i32 || VT == MVT::v4f32)) {
20449 // fold (v4i32: vselect <0,0,-1,-1>, A, B) ->
20450 // (v4i32 (bitcast (movsd (v2i64 (bitcast A)),
20451 // (v2i64 (bitcast B)))))
20453 // fold (v4f32: vselect <0,0,-1,-1>, A, B) ->
20454 // (v4f32 (bitcast (movsd (v2f64 (bitcast A)),
20455 // (v2f64 (bitcast B)))))
20457 // fold (v4i32: vselect <-1,-1,0,0>, A, B) ->
20458 // (v4i32 (bitcast (movsd (v2i64 (bitcast B)),
20459 // (v2i64 (bitcast A)))))
20461 // fold (v4f32: vselect <-1,-1,0,0>, A, B) ->
20462 // (v4f32 (bitcast (movsd (v2f64 (bitcast B)),
20463 // (v2f64 (bitcast A)))))
20465 CanFold = (isZero(Cond.getOperand(0)) &&
20466 isZero(Cond.getOperand(1)) &&
20467 isAllOnes(Cond.getOperand(2)) &&
20468 isAllOnes(Cond.getOperand(3)));
20470 if (!CanFold && isAllOnes(Cond.getOperand(0)) &&
20471 isAllOnes(Cond.getOperand(1)) &&
20472 isZero(Cond.getOperand(2)) &&
20473 isZero(Cond.getOperand(3))) {
20475 std::swap(LHS, RHS);
20479 EVT NVT = (VT == MVT::v4i32) ? MVT::v2i64 : MVT::v2f64;
20480 SDValue NewA = DAG.getNode(ISD::BITCAST, DL, NVT, LHS);
20481 SDValue NewB = DAG.getNode(ISD::BITCAST, DL, NVT, RHS);
20482 SDValue Select = getTargetShuffleNode(X86ISD::MOVSD, DL, NVT, NewA,
20484 return DAG.getNode(ISD::BITCAST, DL, VT, Select);
20490 // If we know that this node is legal then we know that it is going to be
20491 // matched by one of the SSE/AVX BLEND instructions. These instructions only
20492 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
20493 // to simplify previous instructions.
20494 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
20495 !DCI.isBeforeLegalize() &&
20496 // We explicitly check against v8i16 and v16i16 because, although
20497 // they're marked as Custom, they might only be legal when Cond is a
20498 // build_vector of constants. This will be taken care in a later
20500 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
20501 VT != MVT::v8i16)) {
20502 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
20504 // Don't optimize vector selects that map to mask-registers.
20508 // Check all uses of that condition operand to check whether it will be
20509 // consumed by non-BLEND instructions, which may depend on all bits are set
20511 for (SDNode::use_iterator I = Cond->use_begin(),
20512 E = Cond->use_end(); I != E; ++I)
20513 if (I->getOpcode() != ISD::VSELECT)
20514 // TODO: Add other opcodes eventually lowered into BLEND.
20517 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
20518 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
20520 APInt KnownZero, KnownOne;
20521 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
20522 DCI.isBeforeLegalizeOps());
20523 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
20524 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
20525 DCI.CommitTargetLoweringOpt(TLO);
20528 // We should generate an X86ISD::BLENDI from a vselect if its argument
20529 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
20530 // constants. This specific pattern gets generated when we split a
20531 // selector for a 512 bit vector in a machine without AVX512 (but with
20532 // 256-bit vectors), during legalization:
20534 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
20536 // Iff we find this pattern and the build_vectors are built from
20537 // constants, we translate the vselect into a shuffle_vector that we
20538 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
20539 if (N->getOpcode() == ISD::VSELECT && !DCI.isBeforeLegalize()) {
20540 SDValue Shuffle = TransformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
20541 if (Shuffle.getNode())
20548 // Check whether a boolean test is testing a boolean value generated by
20549 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
20552 // Simplify the following patterns:
20553 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
20554 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
20555 // to (Op EFLAGS Cond)
20557 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
20558 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
20559 // to (Op EFLAGS !Cond)
20561 // where Op could be BRCOND or CMOV.
20563 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
20564 // Quit if not CMP and SUB with its value result used.
20565 if (Cmp.getOpcode() != X86ISD::CMP &&
20566 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
20569 // Quit if not used as a boolean value.
20570 if (CC != X86::COND_E && CC != X86::COND_NE)
20573 // Check CMP operands. One of them should be 0 or 1 and the other should be
20574 // an SetCC or extended from it.
20575 SDValue Op1 = Cmp.getOperand(0);
20576 SDValue Op2 = Cmp.getOperand(1);
20579 const ConstantSDNode* C = nullptr;
20580 bool needOppositeCond = (CC == X86::COND_E);
20581 bool checkAgainstTrue = false; // Is it a comparison against 1?
20583 if ((C = dyn_cast<ConstantSDNode>(Op1)))
20585 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
20587 else // Quit if all operands are not constants.
20590 if (C->getZExtValue() == 1) {
20591 needOppositeCond = !needOppositeCond;
20592 checkAgainstTrue = true;
20593 } else if (C->getZExtValue() != 0)
20594 // Quit if the constant is neither 0 or 1.
20597 bool truncatedToBoolWithAnd = false;
20598 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
20599 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
20600 SetCC.getOpcode() == ISD::TRUNCATE ||
20601 SetCC.getOpcode() == ISD::AND) {
20602 if (SetCC.getOpcode() == ISD::AND) {
20604 ConstantSDNode *CS;
20605 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
20606 CS->getZExtValue() == 1)
20608 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
20609 CS->getZExtValue() == 1)
20613 SetCC = SetCC.getOperand(OpIdx);
20614 truncatedToBoolWithAnd = true;
20616 SetCC = SetCC.getOperand(0);
20619 switch (SetCC.getOpcode()) {
20620 case X86ISD::SETCC_CARRY:
20621 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
20622 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
20623 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
20624 // truncated to i1 using 'and'.
20625 if (checkAgainstTrue && !truncatedToBoolWithAnd)
20627 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
20628 "Invalid use of SETCC_CARRY!");
20630 case X86ISD::SETCC:
20631 // Set the condition code or opposite one if necessary.
20632 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
20633 if (needOppositeCond)
20634 CC = X86::GetOppositeBranchCondition(CC);
20635 return SetCC.getOperand(1);
20636 case X86ISD::CMOV: {
20637 // Check whether false/true value has canonical one, i.e. 0 or 1.
20638 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
20639 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
20640 // Quit if true value is not a constant.
20643 // Quit if false value is not a constant.
20645 SDValue Op = SetCC.getOperand(0);
20646 // Skip 'zext' or 'trunc' node.
20647 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
20648 Op.getOpcode() == ISD::TRUNCATE)
20649 Op = Op.getOperand(0);
20650 // A special case for rdrand/rdseed, where 0 is set if false cond is
20652 if ((Op.getOpcode() != X86ISD::RDRAND &&
20653 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
20656 // Quit if false value is not the constant 0 or 1.
20657 bool FValIsFalse = true;
20658 if (FVal && FVal->getZExtValue() != 0) {
20659 if (FVal->getZExtValue() != 1)
20661 // If FVal is 1, opposite cond is needed.
20662 needOppositeCond = !needOppositeCond;
20663 FValIsFalse = false;
20665 // Quit if TVal is not the constant opposite of FVal.
20666 if (FValIsFalse && TVal->getZExtValue() != 1)
20668 if (!FValIsFalse && TVal->getZExtValue() != 0)
20670 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
20671 if (needOppositeCond)
20672 CC = X86::GetOppositeBranchCondition(CC);
20673 return SetCC.getOperand(3);
20680 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
20681 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
20682 TargetLowering::DAGCombinerInfo &DCI,
20683 const X86Subtarget *Subtarget) {
20686 // If the flag operand isn't dead, don't touch this CMOV.
20687 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
20690 SDValue FalseOp = N->getOperand(0);
20691 SDValue TrueOp = N->getOperand(1);
20692 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
20693 SDValue Cond = N->getOperand(3);
20695 if (CC == X86::COND_E || CC == X86::COND_NE) {
20696 switch (Cond.getOpcode()) {
20700 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
20701 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
20702 return (CC == X86::COND_E) ? FalseOp : TrueOp;
20708 Flags = checkBoolTestSetCCCombine(Cond, CC);
20709 if (Flags.getNode() &&
20710 // Extra check as FCMOV only supports a subset of X86 cond.
20711 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
20712 SDValue Ops[] = { FalseOp, TrueOp,
20713 DAG.getConstant(CC, MVT::i8), Flags };
20714 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
20717 // If this is a select between two integer constants, try to do some
20718 // optimizations. Note that the operands are ordered the opposite of SELECT
20720 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
20721 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
20722 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
20723 // larger than FalseC (the false value).
20724 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
20725 CC = X86::GetOppositeBranchCondition(CC);
20726 std::swap(TrueC, FalseC);
20727 std::swap(TrueOp, FalseOp);
20730 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
20731 // This is efficient for any integer data type (including i8/i16) and
20733 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
20734 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20735 DAG.getConstant(CC, MVT::i8), Cond);
20737 // Zero extend the condition if needed.
20738 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
20740 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
20741 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
20742 DAG.getConstant(ShAmt, MVT::i8));
20743 if (N->getNumValues() == 2) // Dead flag value?
20744 return DCI.CombineTo(N, Cond, SDValue());
20748 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
20749 // for any integer data type, including i8/i16.
20750 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
20751 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20752 DAG.getConstant(CC, MVT::i8), Cond);
20754 // Zero extend the condition if needed.
20755 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
20756 FalseC->getValueType(0), Cond);
20757 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20758 SDValue(FalseC, 0));
20760 if (N->getNumValues() == 2) // Dead flag value?
20761 return DCI.CombineTo(N, Cond, SDValue());
20765 // Optimize cases that will turn into an LEA instruction. This requires
20766 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
20767 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
20768 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
20769 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
20771 bool isFastMultiplier = false;
20773 switch ((unsigned char)Diff) {
20775 case 1: // result = add base, cond
20776 case 2: // result = lea base( , cond*2)
20777 case 3: // result = lea base(cond, cond*2)
20778 case 4: // result = lea base( , cond*4)
20779 case 5: // result = lea base(cond, cond*4)
20780 case 8: // result = lea base( , cond*8)
20781 case 9: // result = lea base(cond, cond*8)
20782 isFastMultiplier = true;
20787 if (isFastMultiplier) {
20788 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
20789 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
20790 DAG.getConstant(CC, MVT::i8), Cond);
20791 // Zero extend the condition if needed.
20792 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
20794 // Scale the condition by the difference.
20796 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
20797 DAG.getConstant(Diff, Cond.getValueType()));
20799 // Add the base if non-zero.
20800 if (FalseC->getAPIntValue() != 0)
20801 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
20802 SDValue(FalseC, 0));
20803 if (N->getNumValues() == 2) // Dead flag value?
20804 return DCI.CombineTo(N, Cond, SDValue());
20811 // Handle these cases:
20812 // (select (x != c), e, c) -> select (x != c), e, x),
20813 // (select (x == c), c, e) -> select (x == c), x, e)
20814 // where the c is an integer constant, and the "select" is the combination
20815 // of CMOV and CMP.
20817 // The rationale for this change is that the conditional-move from a constant
20818 // needs two instructions, however, conditional-move from a register needs
20819 // only one instruction.
20821 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
20822 // some instruction-combining opportunities. This opt needs to be
20823 // postponed as late as possible.
20825 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
20826 // the DCI.xxxx conditions are provided to postpone the optimization as
20827 // late as possible.
20829 ConstantSDNode *CmpAgainst = nullptr;
20830 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
20831 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
20832 !isa<ConstantSDNode>(Cond.getOperand(0))) {
20834 if (CC == X86::COND_NE &&
20835 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
20836 CC = X86::GetOppositeBranchCondition(CC);
20837 std::swap(TrueOp, FalseOp);
20840 if (CC == X86::COND_E &&
20841 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
20842 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
20843 DAG.getConstant(CC, MVT::i8), Cond };
20844 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
20852 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
20853 const X86Subtarget *Subtarget) {
20854 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
20856 default: return SDValue();
20857 // SSE/AVX/AVX2 blend intrinsics.
20858 case Intrinsic::x86_avx2_pblendvb:
20859 case Intrinsic::x86_avx2_pblendw:
20860 case Intrinsic::x86_avx2_pblendd_128:
20861 case Intrinsic::x86_avx2_pblendd_256:
20862 // Don't try to simplify this intrinsic if we don't have AVX2.
20863 if (!Subtarget->hasAVX2())
20866 case Intrinsic::x86_avx_blend_pd_256:
20867 case Intrinsic::x86_avx_blend_ps_256:
20868 case Intrinsic::x86_avx_blendv_pd_256:
20869 case Intrinsic::x86_avx_blendv_ps_256:
20870 // Don't try to simplify this intrinsic if we don't have AVX.
20871 if (!Subtarget->hasAVX())
20874 case Intrinsic::x86_sse41_pblendw:
20875 case Intrinsic::x86_sse41_blendpd:
20876 case Intrinsic::x86_sse41_blendps:
20877 case Intrinsic::x86_sse41_blendvps:
20878 case Intrinsic::x86_sse41_blendvpd:
20879 case Intrinsic::x86_sse41_pblendvb: {
20880 SDValue Op0 = N->getOperand(1);
20881 SDValue Op1 = N->getOperand(2);
20882 SDValue Mask = N->getOperand(3);
20884 // Don't try to simplify this intrinsic if we don't have SSE4.1.
20885 if (!Subtarget->hasSSE41())
20888 // fold (blend A, A, Mask) -> A
20891 // fold (blend A, B, allZeros) -> A
20892 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
20894 // fold (blend A, B, allOnes) -> B
20895 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
20898 // Simplify the case where the mask is a constant i32 value.
20899 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
20900 if (C->isNullValue())
20902 if (C->isAllOnesValue())
20909 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
20910 case Intrinsic::x86_sse2_psrai_w:
20911 case Intrinsic::x86_sse2_psrai_d:
20912 case Intrinsic::x86_avx2_psrai_w:
20913 case Intrinsic::x86_avx2_psrai_d:
20914 case Intrinsic::x86_sse2_psra_w:
20915 case Intrinsic::x86_sse2_psra_d:
20916 case Intrinsic::x86_avx2_psra_w:
20917 case Intrinsic::x86_avx2_psra_d: {
20918 SDValue Op0 = N->getOperand(1);
20919 SDValue Op1 = N->getOperand(2);
20920 EVT VT = Op0.getValueType();
20921 assert(VT.isVector() && "Expected a vector type!");
20923 if (isa<BuildVectorSDNode>(Op1))
20924 Op1 = Op1.getOperand(0);
20926 if (!isa<ConstantSDNode>(Op1))
20929 EVT SVT = VT.getVectorElementType();
20930 unsigned SVTBits = SVT.getSizeInBits();
20932 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
20933 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
20934 uint64_t ShAmt = C.getZExtValue();
20936 // Don't try to convert this shift into a ISD::SRA if the shift
20937 // count is bigger than or equal to the element size.
20938 if (ShAmt >= SVTBits)
20941 // Trivial case: if the shift count is zero, then fold this
20942 // into the first operand.
20946 // Replace this packed shift intrinsic with a target independent
20948 SDValue Splat = DAG.getConstant(C, VT);
20949 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
20954 /// PerformMulCombine - Optimize a single multiply with constant into two
20955 /// in order to implement it with two cheaper instructions, e.g.
20956 /// LEA + SHL, LEA + LEA.
20957 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
20958 TargetLowering::DAGCombinerInfo &DCI) {
20959 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
20962 EVT VT = N->getValueType(0);
20963 if (VT != MVT::i64)
20966 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
20969 uint64_t MulAmt = C->getZExtValue();
20970 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
20973 uint64_t MulAmt1 = 0;
20974 uint64_t MulAmt2 = 0;
20975 if ((MulAmt % 9) == 0) {
20977 MulAmt2 = MulAmt / 9;
20978 } else if ((MulAmt % 5) == 0) {
20980 MulAmt2 = MulAmt / 5;
20981 } else if ((MulAmt % 3) == 0) {
20983 MulAmt2 = MulAmt / 3;
20986 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
20989 if (isPowerOf2_64(MulAmt2) &&
20990 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
20991 // If second multiplifer is pow2, issue it first. We want the multiply by
20992 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
20994 std::swap(MulAmt1, MulAmt2);
20997 if (isPowerOf2_64(MulAmt1))
20998 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
20999 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
21001 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
21002 DAG.getConstant(MulAmt1, VT));
21004 if (isPowerOf2_64(MulAmt2))
21005 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
21006 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
21008 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
21009 DAG.getConstant(MulAmt2, VT));
21011 // Do not add new nodes to DAG combiner worklist.
21012 DCI.CombineTo(N, NewMul, false);
21017 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
21018 SDValue N0 = N->getOperand(0);
21019 SDValue N1 = N->getOperand(1);
21020 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
21021 EVT VT = N0.getValueType();
21023 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
21024 // since the result of setcc_c is all zero's or all ones.
21025 if (VT.isInteger() && !VT.isVector() &&
21026 N1C && N0.getOpcode() == ISD::AND &&
21027 N0.getOperand(1).getOpcode() == ISD::Constant) {
21028 SDValue N00 = N0.getOperand(0);
21029 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
21030 ((N00.getOpcode() == ISD::ANY_EXTEND ||
21031 N00.getOpcode() == ISD::ZERO_EXTEND) &&
21032 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
21033 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
21034 APInt ShAmt = N1C->getAPIntValue();
21035 Mask = Mask.shl(ShAmt);
21037 return DAG.getNode(ISD::AND, SDLoc(N), VT,
21038 N00, DAG.getConstant(Mask, VT));
21042 // Hardware support for vector shifts is sparse which makes us scalarize the
21043 // vector operations in many cases. Also, on sandybridge ADD is faster than
21045 // (shl V, 1) -> add V,V
21046 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
21047 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
21048 assert(N0.getValueType().isVector() && "Invalid vector shift type");
21049 // We shift all of the values by one. In many cases we do not have
21050 // hardware support for this operation. This is better expressed as an ADD
21052 if (N1SplatC->getZExtValue() == 1)
21053 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
21059 /// \brief Returns a vector of 0s if the node in input is a vector logical
21060 /// shift by a constant amount which is known to be bigger than or equal
21061 /// to the vector element size in bits.
21062 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
21063 const X86Subtarget *Subtarget) {
21064 EVT VT = N->getValueType(0);
21066 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
21067 (!Subtarget->hasInt256() ||
21068 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
21071 SDValue Amt = N->getOperand(1);
21073 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
21074 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
21075 APInt ShiftAmt = AmtSplat->getAPIntValue();
21076 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
21078 // SSE2/AVX2 logical shifts always return a vector of 0s
21079 // if the shift amount is bigger than or equal to
21080 // the element size. The constant shift amount will be
21081 // encoded as a 8-bit immediate.
21082 if (ShiftAmt.trunc(8).uge(MaxAmount))
21083 return getZeroVector(VT, Subtarget, DAG, DL);
21089 /// PerformShiftCombine - Combine shifts.
21090 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
21091 TargetLowering::DAGCombinerInfo &DCI,
21092 const X86Subtarget *Subtarget) {
21093 if (N->getOpcode() == ISD::SHL) {
21094 SDValue V = PerformSHLCombine(N, DAG);
21095 if (V.getNode()) return V;
21098 if (N->getOpcode() != ISD::SRA) {
21099 // Try to fold this logical shift into a zero vector.
21100 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
21101 if (V.getNode()) return V;
21107 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
21108 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
21109 // and friends. Likewise for OR -> CMPNEQSS.
21110 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
21111 TargetLowering::DAGCombinerInfo &DCI,
21112 const X86Subtarget *Subtarget) {
21115 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
21116 // we're requiring SSE2 for both.
21117 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
21118 SDValue N0 = N->getOperand(0);
21119 SDValue N1 = N->getOperand(1);
21120 SDValue CMP0 = N0->getOperand(1);
21121 SDValue CMP1 = N1->getOperand(1);
21124 // The SETCCs should both refer to the same CMP.
21125 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
21128 SDValue CMP00 = CMP0->getOperand(0);
21129 SDValue CMP01 = CMP0->getOperand(1);
21130 EVT VT = CMP00.getValueType();
21132 if (VT == MVT::f32 || VT == MVT::f64) {
21133 bool ExpectingFlags = false;
21134 // Check for any users that want flags:
21135 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
21136 !ExpectingFlags && UI != UE; ++UI)
21137 switch (UI->getOpcode()) {
21142 ExpectingFlags = true;
21144 case ISD::CopyToReg:
21145 case ISD::SIGN_EXTEND:
21146 case ISD::ZERO_EXTEND:
21147 case ISD::ANY_EXTEND:
21151 if (!ExpectingFlags) {
21152 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
21153 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
21155 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
21156 X86::CondCode tmp = cc0;
21161 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
21162 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
21163 // FIXME: need symbolic constants for these magic numbers.
21164 // See X86ATTInstPrinter.cpp:printSSECC().
21165 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
21166 if (Subtarget->hasAVX512()) {
21167 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
21168 CMP01, DAG.getConstant(x86cc, MVT::i8));
21169 if (N->getValueType(0) != MVT::i1)
21170 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
21174 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
21175 CMP00.getValueType(), CMP00, CMP01,
21176 DAG.getConstant(x86cc, MVT::i8));
21178 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
21179 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
21181 if (is64BitFP && !Subtarget->is64Bit()) {
21182 // On a 32-bit target, we cannot bitcast the 64-bit float to a
21183 // 64-bit integer, since that's not a legal type. Since
21184 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
21185 // bits, but can do this little dance to extract the lowest 32 bits
21186 // and work with those going forward.
21187 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
21189 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
21191 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
21192 Vector32, DAG.getIntPtrConstant(0));
21196 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
21197 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
21198 DAG.getConstant(1, IntVT));
21199 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
21200 return OneBitOfTruth;
21208 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
21209 /// so it can be folded inside ANDNP.
21210 static bool CanFoldXORWithAllOnes(const SDNode *N) {
21211 EVT VT = N->getValueType(0);
21213 // Match direct AllOnes for 128 and 256-bit vectors
21214 if (ISD::isBuildVectorAllOnes(N))
21217 // Look through a bit convert.
21218 if (N->getOpcode() == ISD::BITCAST)
21219 N = N->getOperand(0).getNode();
21221 // Sometimes the operand may come from a insert_subvector building a 256-bit
21223 if (VT.is256BitVector() &&
21224 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
21225 SDValue V1 = N->getOperand(0);
21226 SDValue V2 = N->getOperand(1);
21228 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
21229 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
21230 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
21231 ISD::isBuildVectorAllOnes(V2.getNode()))
21238 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
21239 // register. In most cases we actually compare or select YMM-sized registers
21240 // and mixing the two types creates horrible code. This method optimizes
21241 // some of the transition sequences.
21242 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
21243 TargetLowering::DAGCombinerInfo &DCI,
21244 const X86Subtarget *Subtarget) {
21245 EVT VT = N->getValueType(0);
21246 if (!VT.is256BitVector())
21249 assert((N->getOpcode() == ISD::ANY_EXTEND ||
21250 N->getOpcode() == ISD::ZERO_EXTEND ||
21251 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
21253 SDValue Narrow = N->getOperand(0);
21254 EVT NarrowVT = Narrow->getValueType(0);
21255 if (!NarrowVT.is128BitVector())
21258 if (Narrow->getOpcode() != ISD::XOR &&
21259 Narrow->getOpcode() != ISD::AND &&
21260 Narrow->getOpcode() != ISD::OR)
21263 SDValue N0 = Narrow->getOperand(0);
21264 SDValue N1 = Narrow->getOperand(1);
21267 // The Left side has to be a trunc.
21268 if (N0.getOpcode() != ISD::TRUNCATE)
21271 // The type of the truncated inputs.
21272 EVT WideVT = N0->getOperand(0)->getValueType(0);
21276 // The right side has to be a 'trunc' or a constant vector.
21277 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
21278 ConstantSDNode *RHSConstSplat = nullptr;
21279 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
21280 RHSConstSplat = RHSBV->getConstantSplatNode();
21281 if (!RHSTrunc && !RHSConstSplat)
21284 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21286 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
21289 // Set N0 and N1 to hold the inputs to the new wide operation.
21290 N0 = N0->getOperand(0);
21291 if (RHSConstSplat) {
21292 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
21293 SDValue(RHSConstSplat, 0));
21294 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
21295 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
21296 } else if (RHSTrunc) {
21297 N1 = N1->getOperand(0);
21300 // Generate the wide operation.
21301 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
21302 unsigned Opcode = N->getOpcode();
21304 case ISD::ANY_EXTEND:
21306 case ISD::ZERO_EXTEND: {
21307 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
21308 APInt Mask = APInt::getAllOnesValue(InBits);
21309 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
21310 return DAG.getNode(ISD::AND, DL, VT,
21311 Op, DAG.getConstant(Mask, VT));
21313 case ISD::SIGN_EXTEND:
21314 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
21315 Op, DAG.getValueType(NarrowVT));
21317 llvm_unreachable("Unexpected opcode");
21321 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
21322 TargetLowering::DAGCombinerInfo &DCI,
21323 const X86Subtarget *Subtarget) {
21324 EVT VT = N->getValueType(0);
21325 if (DCI.isBeforeLegalizeOps())
21328 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21332 // Create BEXTR instructions
21333 // BEXTR is ((X >> imm) & (2**size-1))
21334 if (VT == MVT::i32 || VT == MVT::i64) {
21335 SDValue N0 = N->getOperand(0);
21336 SDValue N1 = N->getOperand(1);
21339 // Check for BEXTR.
21340 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
21341 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
21342 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
21343 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
21344 if (MaskNode && ShiftNode) {
21345 uint64_t Mask = MaskNode->getZExtValue();
21346 uint64_t Shift = ShiftNode->getZExtValue();
21347 if (isMask_64(Mask)) {
21348 uint64_t MaskSize = CountPopulation_64(Mask);
21349 if (Shift + MaskSize <= VT.getSizeInBits())
21350 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
21351 DAG.getConstant(Shift | (MaskSize << 8), VT));
21359 // Want to form ANDNP nodes:
21360 // 1) In the hopes of then easily combining them with OR and AND nodes
21361 // to form PBLEND/PSIGN.
21362 // 2) To match ANDN packed intrinsics
21363 if (VT != MVT::v2i64 && VT != MVT::v4i64)
21366 SDValue N0 = N->getOperand(0);
21367 SDValue N1 = N->getOperand(1);
21370 // Check LHS for vnot
21371 if (N0.getOpcode() == ISD::XOR &&
21372 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
21373 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
21374 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
21376 // Check RHS for vnot
21377 if (N1.getOpcode() == ISD::XOR &&
21378 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
21379 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
21380 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
21385 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
21386 TargetLowering::DAGCombinerInfo &DCI,
21387 const X86Subtarget *Subtarget) {
21388 if (DCI.isBeforeLegalizeOps())
21391 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
21395 SDValue N0 = N->getOperand(0);
21396 SDValue N1 = N->getOperand(1);
21397 EVT VT = N->getValueType(0);
21399 // look for psign/blend
21400 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
21401 if (!Subtarget->hasSSSE3() ||
21402 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
21405 // Canonicalize pandn to RHS
21406 if (N0.getOpcode() == X86ISD::ANDNP)
21408 // or (and (m, y), (pandn m, x))
21409 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
21410 SDValue Mask = N1.getOperand(0);
21411 SDValue X = N1.getOperand(1);
21413 if (N0.getOperand(0) == Mask)
21414 Y = N0.getOperand(1);
21415 if (N0.getOperand(1) == Mask)
21416 Y = N0.getOperand(0);
21418 // Check to see if the mask appeared in both the AND and ANDNP and
21422 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
21423 // Look through mask bitcast.
21424 if (Mask.getOpcode() == ISD::BITCAST)
21425 Mask = Mask.getOperand(0);
21426 if (X.getOpcode() == ISD::BITCAST)
21427 X = X.getOperand(0);
21428 if (Y.getOpcode() == ISD::BITCAST)
21429 Y = Y.getOperand(0);
21431 EVT MaskVT = Mask.getValueType();
21433 // Validate that the Mask operand is a vector sra node.
21434 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
21435 // there is no psrai.b
21436 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
21437 unsigned SraAmt = ~0;
21438 if (Mask.getOpcode() == ISD::SRA) {
21439 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
21440 if (auto *AmtConst = AmtBV->getConstantSplatNode())
21441 SraAmt = AmtConst->getZExtValue();
21442 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
21443 SDValue SraC = Mask.getOperand(1);
21444 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
21446 if ((SraAmt + 1) != EltBits)
21451 // Now we know we at least have a plendvb with the mask val. See if
21452 // we can form a psignb/w/d.
21453 // psign = x.type == y.type == mask.type && y = sub(0, x);
21454 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
21455 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
21456 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
21457 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
21458 "Unsupported VT for PSIGN");
21459 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
21460 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21462 // PBLENDVB only available on SSE 4.1
21463 if (!Subtarget->hasSSE41())
21466 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
21468 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
21469 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
21470 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
21471 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
21472 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
21476 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
21479 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
21480 MachineFunction &MF = DAG.getMachineFunction();
21481 bool OptForSize = MF.getFunction()->getAttributes().
21482 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
21484 // SHLD/SHRD instructions have lower register pressure, but on some
21485 // platforms they have higher latency than the equivalent
21486 // series of shifts/or that would otherwise be generated.
21487 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
21488 // have higher latencies and we are not optimizing for size.
21489 if (!OptForSize && Subtarget->isSHLDSlow())
21492 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
21494 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
21496 if (!N0.hasOneUse() || !N1.hasOneUse())
21499 SDValue ShAmt0 = N0.getOperand(1);
21500 if (ShAmt0.getValueType() != MVT::i8)
21502 SDValue ShAmt1 = N1.getOperand(1);
21503 if (ShAmt1.getValueType() != MVT::i8)
21505 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
21506 ShAmt0 = ShAmt0.getOperand(0);
21507 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
21508 ShAmt1 = ShAmt1.getOperand(0);
21511 unsigned Opc = X86ISD::SHLD;
21512 SDValue Op0 = N0.getOperand(0);
21513 SDValue Op1 = N1.getOperand(0);
21514 if (ShAmt0.getOpcode() == ISD::SUB) {
21515 Opc = X86ISD::SHRD;
21516 std::swap(Op0, Op1);
21517 std::swap(ShAmt0, ShAmt1);
21520 unsigned Bits = VT.getSizeInBits();
21521 if (ShAmt1.getOpcode() == ISD::SUB) {
21522 SDValue Sum = ShAmt1.getOperand(0);
21523 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
21524 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
21525 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
21526 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
21527 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
21528 return DAG.getNode(Opc, DL, VT,
21530 DAG.getNode(ISD::TRUNCATE, DL,
21533 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
21534 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
21536 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
21537 return DAG.getNode(Opc, DL, VT,
21538 N0.getOperand(0), N1.getOperand(0),
21539 DAG.getNode(ISD::TRUNCATE, DL,
21546 // Generate NEG and CMOV for integer abs.
21547 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
21548 EVT VT = N->getValueType(0);
21550 // Since X86 does not have CMOV for 8-bit integer, we don't convert
21551 // 8-bit integer abs to NEG and CMOV.
21552 if (VT.isInteger() && VT.getSizeInBits() == 8)
21555 SDValue N0 = N->getOperand(0);
21556 SDValue N1 = N->getOperand(1);
21559 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
21560 // and change it to SUB and CMOV.
21561 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
21562 N0.getOpcode() == ISD::ADD &&
21563 N0.getOperand(1) == N1 &&
21564 N1.getOpcode() == ISD::SRA &&
21565 N1.getOperand(0) == N0.getOperand(0))
21566 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
21567 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
21568 // Generate SUB & CMOV.
21569 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
21570 DAG.getConstant(0, VT), N0.getOperand(0));
21572 SDValue Ops[] = { N0.getOperand(0), Neg,
21573 DAG.getConstant(X86::COND_GE, MVT::i8),
21574 SDValue(Neg.getNode(), 1) };
21575 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
21580 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
21581 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
21582 TargetLowering::DAGCombinerInfo &DCI,
21583 const X86Subtarget *Subtarget) {
21584 if (DCI.isBeforeLegalizeOps())
21587 if (Subtarget->hasCMov()) {
21588 SDValue RV = performIntegerAbsCombine(N, DAG);
21596 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
21597 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
21598 TargetLowering::DAGCombinerInfo &DCI,
21599 const X86Subtarget *Subtarget) {
21600 LoadSDNode *Ld = cast<LoadSDNode>(N);
21601 EVT RegVT = Ld->getValueType(0);
21602 EVT MemVT = Ld->getMemoryVT();
21604 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21606 // On Sandybridge unaligned 256bit loads are inefficient.
21607 ISD::LoadExtType Ext = Ld->getExtensionType();
21608 unsigned Alignment = Ld->getAlignment();
21609 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
21610 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
21611 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
21612 unsigned NumElems = RegVT.getVectorNumElements();
21616 SDValue Ptr = Ld->getBasePtr();
21617 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
21619 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
21621 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21622 Ld->getPointerInfo(), Ld->isVolatile(),
21623 Ld->isNonTemporal(), Ld->isInvariant(),
21625 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21626 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
21627 Ld->getPointerInfo(), Ld->isVolatile(),
21628 Ld->isNonTemporal(), Ld->isInvariant(),
21629 std::min(16U, Alignment));
21630 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21632 Load2.getValue(1));
21634 SDValue NewVec = DAG.getUNDEF(RegVT);
21635 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
21636 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
21637 return DCI.CombineTo(N, NewVec, TF, true);
21643 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
21644 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
21645 const X86Subtarget *Subtarget) {
21646 StoreSDNode *St = cast<StoreSDNode>(N);
21647 EVT VT = St->getValue().getValueType();
21648 EVT StVT = St->getMemoryVT();
21650 SDValue StoredVal = St->getOperand(1);
21651 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21653 // If we are saving a concatenation of two XMM registers, perform two stores.
21654 // On Sandy Bridge, 256-bit memory operations are executed by two
21655 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
21656 // memory operation.
21657 unsigned Alignment = St->getAlignment();
21658 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
21659 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
21660 StVT == VT && !IsAligned) {
21661 unsigned NumElems = VT.getVectorNumElements();
21665 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
21666 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
21668 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
21669 SDValue Ptr0 = St->getBasePtr();
21670 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
21672 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
21673 St->getPointerInfo(), St->isVolatile(),
21674 St->isNonTemporal(), Alignment);
21675 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
21676 St->getPointerInfo(), St->isVolatile(),
21677 St->isNonTemporal(),
21678 std::min(16U, Alignment));
21679 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
21682 // Optimize trunc store (of multiple scalars) to shuffle and store.
21683 // First, pack all of the elements in one place. Next, store to memory
21684 // in fewer chunks.
21685 if (St->isTruncatingStore() && VT.isVector()) {
21686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21687 unsigned NumElems = VT.getVectorNumElements();
21688 assert(StVT != VT && "Cannot truncate to the same type");
21689 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
21690 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
21692 // From, To sizes and ElemCount must be pow of two
21693 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
21694 // We are going to use the original vector elt for storing.
21695 // Accumulated smaller vector elements must be a multiple of the store size.
21696 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
21698 unsigned SizeRatio = FromSz / ToSz;
21700 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
21702 // Create a type on which we perform the shuffle
21703 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
21704 StVT.getScalarType(), NumElems*SizeRatio);
21706 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
21708 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
21709 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
21710 for (unsigned i = 0; i != NumElems; ++i)
21711 ShuffleVec[i] = i * SizeRatio;
21713 // Can't shuffle using an illegal type.
21714 if (!TLI.isTypeLegal(WideVecVT))
21717 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
21718 DAG.getUNDEF(WideVecVT),
21720 // At this point all of the data is stored at the bottom of the
21721 // register. We now need to save it to mem.
21723 // Find the largest store unit
21724 MVT StoreType = MVT::i8;
21725 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
21726 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
21727 MVT Tp = (MVT::SimpleValueType)tp;
21728 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
21732 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
21733 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
21734 (64 <= NumElems * ToSz))
21735 StoreType = MVT::f64;
21737 // Bitcast the original vector into a vector of store-size units
21738 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
21739 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
21740 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
21741 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
21742 SmallVector<SDValue, 8> Chains;
21743 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
21744 TLI.getPointerTy());
21745 SDValue Ptr = St->getBasePtr();
21747 // Perform one or more big stores into memory.
21748 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
21749 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
21750 StoreType, ShuffWide,
21751 DAG.getIntPtrConstant(i));
21752 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
21753 St->getPointerInfo(), St->isVolatile(),
21754 St->isNonTemporal(), St->getAlignment());
21755 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
21756 Chains.push_back(Ch);
21759 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
21762 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
21763 // the FP state in cases where an emms may be missing.
21764 // A preferable solution to the general problem is to figure out the right
21765 // places to insert EMMS. This qualifies as a quick hack.
21767 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
21768 if (VT.getSizeInBits() != 64)
21771 const Function *F = DAG.getMachineFunction().getFunction();
21772 bool NoImplicitFloatOps = F->getAttributes().
21773 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
21774 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
21775 && Subtarget->hasSSE2();
21776 if ((VT.isVector() ||
21777 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
21778 isa<LoadSDNode>(St->getValue()) &&
21779 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
21780 St->getChain().hasOneUse() && !St->isVolatile()) {
21781 SDNode* LdVal = St->getValue().getNode();
21782 LoadSDNode *Ld = nullptr;
21783 int TokenFactorIndex = -1;
21784 SmallVector<SDValue, 8> Ops;
21785 SDNode* ChainVal = St->getChain().getNode();
21786 // Must be a store of a load. We currently handle two cases: the load
21787 // is a direct child, and it's under an intervening TokenFactor. It is
21788 // possible to dig deeper under nested TokenFactors.
21789 if (ChainVal == LdVal)
21790 Ld = cast<LoadSDNode>(St->getChain());
21791 else if (St->getValue().hasOneUse() &&
21792 ChainVal->getOpcode() == ISD::TokenFactor) {
21793 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
21794 if (ChainVal->getOperand(i).getNode() == LdVal) {
21795 TokenFactorIndex = i;
21796 Ld = cast<LoadSDNode>(St->getValue());
21798 Ops.push_back(ChainVal->getOperand(i));
21802 if (!Ld || !ISD::isNormalLoad(Ld))
21805 // If this is not the MMX case, i.e. we are just turning i64 load/store
21806 // into f64 load/store, avoid the transformation if there are multiple
21807 // uses of the loaded value.
21808 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
21813 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
21814 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
21816 if (Subtarget->is64Bit() || F64IsLegal) {
21817 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
21818 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
21819 Ld->getPointerInfo(), Ld->isVolatile(),
21820 Ld->isNonTemporal(), Ld->isInvariant(),
21821 Ld->getAlignment());
21822 SDValue NewChain = NewLd.getValue(1);
21823 if (TokenFactorIndex != -1) {
21824 Ops.push_back(NewChain);
21825 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21827 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
21828 St->getPointerInfo(),
21829 St->isVolatile(), St->isNonTemporal(),
21830 St->getAlignment());
21833 // Otherwise, lower to two pairs of 32-bit loads / stores.
21834 SDValue LoAddr = Ld->getBasePtr();
21835 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
21836 DAG.getConstant(4, MVT::i32));
21838 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
21839 Ld->getPointerInfo(),
21840 Ld->isVolatile(), Ld->isNonTemporal(),
21841 Ld->isInvariant(), Ld->getAlignment());
21842 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
21843 Ld->getPointerInfo().getWithOffset(4),
21844 Ld->isVolatile(), Ld->isNonTemporal(),
21846 MinAlign(Ld->getAlignment(), 4));
21848 SDValue NewChain = LoLd.getValue(1);
21849 if (TokenFactorIndex != -1) {
21850 Ops.push_back(LoLd);
21851 Ops.push_back(HiLd);
21852 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
21855 LoAddr = St->getBasePtr();
21856 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
21857 DAG.getConstant(4, MVT::i32));
21859 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
21860 St->getPointerInfo(),
21861 St->isVolatile(), St->isNonTemporal(),
21862 St->getAlignment());
21863 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
21864 St->getPointerInfo().getWithOffset(4),
21866 St->isNonTemporal(),
21867 MinAlign(St->getAlignment(), 4));
21868 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
21873 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
21874 /// and return the operands for the horizontal operation in LHS and RHS. A
21875 /// horizontal operation performs the binary operation on successive elements
21876 /// of its first operand, then on successive elements of its second operand,
21877 /// returning the resulting values in a vector. For example, if
21878 /// A = < float a0, float a1, float a2, float a3 >
21880 /// B = < float b0, float b1, float b2, float b3 >
21881 /// then the result of doing a horizontal operation on A and B is
21882 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
21883 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
21884 /// A horizontal-op B, for some already available A and B, and if so then LHS is
21885 /// set to A, RHS to B, and the routine returns 'true'.
21886 /// Note that the binary operation should have the property that if one of the
21887 /// operands is UNDEF then the result is UNDEF.
21888 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
21889 // Look for the following pattern: if
21890 // A = < float a0, float a1, float a2, float a3 >
21891 // B = < float b0, float b1, float b2, float b3 >
21893 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
21894 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
21895 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
21896 // which is A horizontal-op B.
21898 // At least one of the operands should be a vector shuffle.
21899 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
21900 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
21903 MVT VT = LHS.getSimpleValueType();
21905 assert((VT.is128BitVector() || VT.is256BitVector()) &&
21906 "Unsupported vector type for horizontal add/sub");
21908 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
21909 // operate independently on 128-bit lanes.
21910 unsigned NumElts = VT.getVectorNumElements();
21911 unsigned NumLanes = VT.getSizeInBits()/128;
21912 unsigned NumLaneElts = NumElts / NumLanes;
21913 assert((NumLaneElts % 2 == 0) &&
21914 "Vector type should have an even number of elements in each lane");
21915 unsigned HalfLaneElts = NumLaneElts/2;
21917 // View LHS in the form
21918 // LHS = VECTOR_SHUFFLE A, B, LMask
21919 // If LHS is not a shuffle then pretend it is the shuffle
21920 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
21921 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
21924 SmallVector<int, 16> LMask(NumElts);
21925 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21926 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
21927 A = LHS.getOperand(0);
21928 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
21929 B = LHS.getOperand(1);
21930 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
21931 std::copy(Mask.begin(), Mask.end(), LMask.begin());
21933 if (LHS.getOpcode() != ISD::UNDEF)
21935 for (unsigned i = 0; i != NumElts; ++i)
21939 // Likewise, view RHS in the form
21940 // RHS = VECTOR_SHUFFLE C, D, RMask
21942 SmallVector<int, 16> RMask(NumElts);
21943 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
21944 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
21945 C = RHS.getOperand(0);
21946 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
21947 D = RHS.getOperand(1);
21948 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
21949 std::copy(Mask.begin(), Mask.end(), RMask.begin());
21951 if (RHS.getOpcode() != ISD::UNDEF)
21953 for (unsigned i = 0; i != NumElts; ++i)
21957 // Check that the shuffles are both shuffling the same vectors.
21958 if (!(A == C && B == D) && !(A == D && B == C))
21961 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
21962 if (!A.getNode() && !B.getNode())
21965 // If A and B occur in reverse order in RHS, then "swap" them (which means
21966 // rewriting the mask).
21968 CommuteVectorShuffleMask(RMask, NumElts);
21970 // At this point LHS and RHS are equivalent to
21971 // LHS = VECTOR_SHUFFLE A, B, LMask
21972 // RHS = VECTOR_SHUFFLE A, B, RMask
21973 // Check that the masks correspond to performing a horizontal operation.
21974 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
21975 for (unsigned i = 0; i != NumLaneElts; ++i) {
21976 int LIdx = LMask[i+l], RIdx = RMask[i+l];
21978 // Ignore any UNDEF components.
21979 if (LIdx < 0 || RIdx < 0 ||
21980 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
21981 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
21984 // Check that successive elements are being operated on. If not, this is
21985 // not a horizontal operation.
21986 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
21987 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
21988 if (!(LIdx == Index && RIdx == Index + 1) &&
21989 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
21994 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
21995 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
21999 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
22000 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
22001 const X86Subtarget *Subtarget) {
22002 EVT VT = N->getValueType(0);
22003 SDValue LHS = N->getOperand(0);
22004 SDValue RHS = N->getOperand(1);
22006 // Try to synthesize horizontal adds from adds of shuffles.
22007 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22008 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22009 isHorizontalBinOp(LHS, RHS, true))
22010 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
22014 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
22015 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
22016 const X86Subtarget *Subtarget) {
22017 EVT VT = N->getValueType(0);
22018 SDValue LHS = N->getOperand(0);
22019 SDValue RHS = N->getOperand(1);
22021 // Try to synthesize horizontal subs from subs of shuffles.
22022 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
22023 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
22024 isHorizontalBinOp(LHS, RHS, false))
22025 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
22029 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
22030 /// X86ISD::FXOR nodes.
22031 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
22032 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
22033 // F[X]OR(0.0, x) -> x
22034 // F[X]OR(x, 0.0) -> x
22035 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22036 if (C->getValueAPF().isPosZero())
22037 return N->getOperand(1);
22038 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22039 if (C->getValueAPF().isPosZero())
22040 return N->getOperand(0);
22044 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
22045 /// X86ISD::FMAX nodes.
22046 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
22047 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
22049 // Only perform optimizations if UnsafeMath is used.
22050 if (!DAG.getTarget().Options.UnsafeFPMath)
22053 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
22054 // into FMINC and FMAXC, which are Commutative operations.
22055 unsigned NewOp = 0;
22056 switch (N->getOpcode()) {
22057 default: llvm_unreachable("unknown opcode");
22058 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
22059 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
22062 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
22063 N->getOperand(0), N->getOperand(1));
22066 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
22067 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
22068 // FAND(0.0, x) -> 0.0
22069 // FAND(x, 0.0) -> 0.0
22070 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22071 if (C->getValueAPF().isPosZero())
22072 return N->getOperand(0);
22073 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22074 if (C->getValueAPF().isPosZero())
22075 return N->getOperand(1);
22079 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
22080 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
22081 // FANDN(x, 0.0) -> 0.0
22082 // FANDN(0.0, x) -> x
22083 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
22084 if (C->getValueAPF().isPosZero())
22085 return N->getOperand(1);
22086 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
22087 if (C->getValueAPF().isPosZero())
22088 return N->getOperand(1);
22092 static SDValue PerformBTCombine(SDNode *N,
22094 TargetLowering::DAGCombinerInfo &DCI) {
22095 // BT ignores high bits in the bit index operand.
22096 SDValue Op1 = N->getOperand(1);
22097 if (Op1.hasOneUse()) {
22098 unsigned BitWidth = Op1.getValueSizeInBits();
22099 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
22100 APInt KnownZero, KnownOne;
22101 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
22102 !DCI.isBeforeLegalizeOps());
22103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22104 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
22105 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
22106 DCI.CommitTargetLoweringOpt(TLO);
22111 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
22112 SDValue Op = N->getOperand(0);
22113 if (Op.getOpcode() == ISD::BITCAST)
22114 Op = Op.getOperand(0);
22115 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
22116 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
22117 VT.getVectorElementType().getSizeInBits() ==
22118 OpVT.getVectorElementType().getSizeInBits()) {
22119 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
22124 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
22125 const X86Subtarget *Subtarget) {
22126 EVT VT = N->getValueType(0);
22127 if (!VT.isVector())
22130 SDValue N0 = N->getOperand(0);
22131 SDValue N1 = N->getOperand(1);
22132 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
22135 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
22136 // both SSE and AVX2 since there is no sign-extended shift right
22137 // operation on a vector with 64-bit elements.
22138 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
22139 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
22140 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
22141 N0.getOpcode() == ISD::SIGN_EXTEND)) {
22142 SDValue N00 = N0.getOperand(0);
22144 // EXTLOAD has a better solution on AVX2,
22145 // it may be replaced with X86ISD::VSEXT node.
22146 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
22147 if (!ISD::isNormalLoad(N00.getNode()))
22150 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
22151 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
22153 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
22159 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
22160 TargetLowering::DAGCombinerInfo &DCI,
22161 const X86Subtarget *Subtarget) {
22162 if (!DCI.isBeforeLegalizeOps())
22165 if (!Subtarget->hasFp256())
22168 EVT VT = N->getValueType(0);
22169 if (VT.isVector() && VT.getSizeInBits() == 256) {
22170 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22178 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
22179 const X86Subtarget* Subtarget) {
22181 EVT VT = N->getValueType(0);
22183 // Let legalize expand this if it isn't a legal type yet.
22184 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
22187 EVT ScalarVT = VT.getScalarType();
22188 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
22189 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
22192 SDValue A = N->getOperand(0);
22193 SDValue B = N->getOperand(1);
22194 SDValue C = N->getOperand(2);
22196 bool NegA = (A.getOpcode() == ISD::FNEG);
22197 bool NegB = (B.getOpcode() == ISD::FNEG);
22198 bool NegC = (C.getOpcode() == ISD::FNEG);
22200 // Negative multiplication when NegA xor NegB
22201 bool NegMul = (NegA != NegB);
22203 A = A.getOperand(0);
22205 B = B.getOperand(0);
22207 C = C.getOperand(0);
22211 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
22213 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
22215 return DAG.getNode(Opcode, dl, VT, A, B, C);
22218 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
22219 TargetLowering::DAGCombinerInfo &DCI,
22220 const X86Subtarget *Subtarget) {
22221 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
22222 // (and (i32 x86isd::setcc_carry), 1)
22223 // This eliminates the zext. This transformation is necessary because
22224 // ISD::SETCC is always legalized to i8.
22226 SDValue N0 = N->getOperand(0);
22227 EVT VT = N->getValueType(0);
22229 if (N0.getOpcode() == ISD::AND &&
22231 N0.getOperand(0).hasOneUse()) {
22232 SDValue N00 = N0.getOperand(0);
22233 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22234 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
22235 if (!C || C->getZExtValue() != 1)
22237 return DAG.getNode(ISD::AND, dl, VT,
22238 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22239 N00.getOperand(0), N00.getOperand(1)),
22240 DAG.getConstant(1, VT));
22244 if (N0.getOpcode() == ISD::TRUNCATE &&
22246 N0.getOperand(0).hasOneUse()) {
22247 SDValue N00 = N0.getOperand(0);
22248 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
22249 return DAG.getNode(ISD::AND, dl, VT,
22250 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
22251 N00.getOperand(0), N00.getOperand(1)),
22252 DAG.getConstant(1, VT));
22255 if (VT.is256BitVector()) {
22256 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
22264 // Optimize x == -y --> x+y == 0
22265 // x != -y --> x+y != 0
22266 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
22267 const X86Subtarget* Subtarget) {
22268 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
22269 SDValue LHS = N->getOperand(0);
22270 SDValue RHS = N->getOperand(1);
22271 EVT VT = N->getValueType(0);
22274 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
22275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
22276 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
22277 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22278 LHS.getValueType(), RHS, LHS.getOperand(1));
22279 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22280 addV, DAG.getConstant(0, addV.getValueType()), CC);
22282 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
22283 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
22284 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
22285 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
22286 RHS.getValueType(), LHS, RHS.getOperand(1));
22287 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
22288 addV, DAG.getConstant(0, addV.getValueType()), CC);
22291 if (VT.getScalarType() == MVT::i1) {
22292 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
22293 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22294 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
22295 if (!IsSEXT0 && !IsVZero0)
22297 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
22298 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
22299 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
22301 if (!IsSEXT1 && !IsVZero1)
22304 if (IsSEXT0 && IsVZero1) {
22305 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
22306 if (CC == ISD::SETEQ)
22307 return DAG.getNOT(DL, LHS.getOperand(0), VT);
22308 return LHS.getOperand(0);
22310 if (IsSEXT1 && IsVZero0) {
22311 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
22312 if (CC == ISD::SETEQ)
22313 return DAG.getNOT(DL, RHS.getOperand(0), VT);
22314 return RHS.getOperand(0);
22321 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
22322 const X86Subtarget *Subtarget) {
22324 MVT VT = N->getOperand(1)->getSimpleValueType(0);
22325 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
22326 "X86insertps is only defined for v4x32");
22328 SDValue Ld = N->getOperand(1);
22329 if (MayFoldLoad(Ld)) {
22330 // Extract the countS bits from the immediate so we can get the proper
22331 // address when narrowing the vector load to a specific element.
22332 // When the second source op is a memory address, interps doesn't use
22333 // countS and just gets an f32 from that address.
22334 unsigned DestIndex =
22335 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
22336 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
22340 // Create this as a scalar to vector to match the instruction pattern.
22341 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
22342 // countS bits are ignored when loading from memory on insertps, which
22343 // means we don't need to explicitly set them to 0.
22344 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
22345 LoadScalarToVector, N->getOperand(2));
22348 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
22349 // as "sbb reg,reg", since it can be extended without zext and produces
22350 // an all-ones bit which is more useful than 0/1 in some cases.
22351 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
22354 return DAG.getNode(ISD::AND, DL, VT,
22355 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22356 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
22357 DAG.getConstant(1, VT));
22358 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
22359 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
22360 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
22361 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
22364 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
22365 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
22366 TargetLowering::DAGCombinerInfo &DCI,
22367 const X86Subtarget *Subtarget) {
22369 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
22370 SDValue EFLAGS = N->getOperand(1);
22372 if (CC == X86::COND_A) {
22373 // Try to convert COND_A into COND_B in an attempt to facilitate
22374 // materializing "setb reg".
22376 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
22377 // cannot take an immediate as its first operand.
22379 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
22380 EFLAGS.getValueType().isInteger() &&
22381 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
22382 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
22383 EFLAGS.getNode()->getVTList(),
22384 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
22385 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
22386 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
22390 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
22391 // a zext and produces an all-ones bit which is more useful than 0/1 in some
22393 if (CC == X86::COND_B)
22394 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
22398 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22399 if (Flags.getNode()) {
22400 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22401 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
22407 // Optimize branch condition evaluation.
22409 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
22410 TargetLowering::DAGCombinerInfo &DCI,
22411 const X86Subtarget *Subtarget) {
22413 SDValue Chain = N->getOperand(0);
22414 SDValue Dest = N->getOperand(1);
22415 SDValue EFLAGS = N->getOperand(3);
22416 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
22420 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
22421 if (Flags.getNode()) {
22422 SDValue Cond = DAG.getConstant(CC, MVT::i8);
22423 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
22430 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
22431 SelectionDAG &DAG) {
22432 // Take advantage of vector comparisons producing 0 or -1 in each lane to
22433 // optimize away operation when it's from a constant.
22435 // The general transformation is:
22436 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
22437 // AND(VECTOR_CMP(x,y), constant2)
22438 // constant2 = UNARYOP(constant)
22440 // Early exit if this isn't a vector operation, the operand of the
22441 // unary operation isn't a bitwise AND, or if the sizes of the operations
22442 // aren't the same.
22443 EVT VT = N->getValueType(0);
22444 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
22445 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
22446 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
22449 // Now check that the other operand of the AND is a constant. We could
22450 // make the transformation for non-constant splats as well, but it's unclear
22451 // that would be a benefit as it would not eliminate any operations, just
22452 // perform one more step in scalar code before moving to the vector unit.
22453 if (BuildVectorSDNode *BV =
22454 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
22455 // Bail out if the vector isn't a constant.
22456 if (!BV->isConstant())
22459 // Everything checks out. Build up the new and improved node.
22461 EVT IntVT = BV->getValueType(0);
22462 // Create a new constant of the appropriate type for the transformed
22464 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
22465 // The AND node needs bitcasts to/from an integer vector type around it.
22466 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
22467 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
22468 N->getOperand(0)->getOperand(0), MaskConst);
22469 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
22476 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
22477 const X86TargetLowering *XTLI) {
22478 // First try to optimize away the conversion entirely when it's
22479 // conditionally from a constant. Vectors only.
22480 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
22481 if (Res != SDValue())
22484 // Now move on to more general possibilities.
22485 SDValue Op0 = N->getOperand(0);
22486 EVT InVT = Op0->getValueType(0);
22488 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
22489 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
22491 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
22492 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
22493 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
22496 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
22497 // a 32-bit target where SSE doesn't support i64->FP operations.
22498 if (Op0.getOpcode() == ISD::LOAD) {
22499 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
22500 EVT VT = Ld->getValueType(0);
22501 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
22502 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
22503 !XTLI->getSubtarget()->is64Bit() &&
22505 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
22506 Ld->getChain(), Op0, DAG);
22507 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
22514 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
22515 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
22516 X86TargetLowering::DAGCombinerInfo &DCI) {
22517 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
22518 // the result is either zero or one (depending on the input carry bit).
22519 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
22520 if (X86::isZeroNode(N->getOperand(0)) &&
22521 X86::isZeroNode(N->getOperand(1)) &&
22522 // We don't have a good way to replace an EFLAGS use, so only do this when
22524 SDValue(N, 1).use_empty()) {
22526 EVT VT = N->getValueType(0);
22527 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
22528 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
22529 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
22530 DAG.getConstant(X86::COND_B,MVT::i8),
22532 DAG.getConstant(1, VT));
22533 return DCI.CombineTo(N, Res1, CarryOut);
22539 // fold (add Y, (sete X, 0)) -> adc 0, Y
22540 // (add Y, (setne X, 0)) -> sbb -1, Y
22541 // (sub (sete X, 0), Y) -> sbb 0, Y
22542 // (sub (setne X, 0), Y) -> adc -1, Y
22543 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
22546 // Look through ZExts.
22547 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
22548 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
22551 SDValue SetCC = Ext.getOperand(0);
22552 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
22555 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
22556 if (CC != X86::COND_E && CC != X86::COND_NE)
22559 SDValue Cmp = SetCC.getOperand(1);
22560 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
22561 !X86::isZeroNode(Cmp.getOperand(1)) ||
22562 !Cmp.getOperand(0).getValueType().isInteger())
22565 SDValue CmpOp0 = Cmp.getOperand(0);
22566 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
22567 DAG.getConstant(1, CmpOp0.getValueType()));
22569 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
22570 if (CC == X86::COND_NE)
22571 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
22572 DL, OtherVal.getValueType(), OtherVal,
22573 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
22574 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
22575 DL, OtherVal.getValueType(), OtherVal,
22576 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
22579 /// PerformADDCombine - Do target-specific dag combines on integer adds.
22580 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
22581 const X86Subtarget *Subtarget) {
22582 EVT VT = N->getValueType(0);
22583 SDValue Op0 = N->getOperand(0);
22584 SDValue Op1 = N->getOperand(1);
22586 // Try to synthesize horizontal adds from adds of shuffles.
22587 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22588 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22589 isHorizontalBinOp(Op0, Op1, true))
22590 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
22592 return OptimizeConditionalInDecrement(N, DAG);
22595 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
22596 const X86Subtarget *Subtarget) {
22597 SDValue Op0 = N->getOperand(0);
22598 SDValue Op1 = N->getOperand(1);
22600 // X86 can't encode an immediate LHS of a sub. See if we can push the
22601 // negation into a preceding instruction.
22602 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
22603 // If the RHS of the sub is a XOR with one use and a constant, invert the
22604 // immediate. Then add one to the LHS of the sub so we can turn
22605 // X-Y -> X+~Y+1, saving one register.
22606 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
22607 isa<ConstantSDNode>(Op1.getOperand(1))) {
22608 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
22609 EVT VT = Op0.getValueType();
22610 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
22612 DAG.getConstant(~XorC, VT));
22613 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
22614 DAG.getConstant(C->getAPIntValue()+1, VT));
22618 // Try to synthesize horizontal adds from adds of shuffles.
22619 EVT VT = N->getValueType(0);
22620 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
22621 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
22622 isHorizontalBinOp(Op0, Op1, true))
22623 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
22625 return OptimizeConditionalInDecrement(N, DAG);
22628 /// performVZEXTCombine - Performs build vector combines
22629 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
22630 TargetLowering::DAGCombinerInfo &DCI,
22631 const X86Subtarget *Subtarget) {
22632 // (vzext (bitcast (vzext (x)) -> (vzext x)
22633 SDValue In = N->getOperand(0);
22634 while (In.getOpcode() == ISD::BITCAST)
22635 In = In.getOperand(0);
22637 if (In.getOpcode() != X86ISD::VZEXT)
22640 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
22644 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
22645 DAGCombinerInfo &DCI) const {
22646 SelectionDAG &DAG = DCI.DAG;
22647 switch (N->getOpcode()) {
22649 case ISD::EXTRACT_VECTOR_ELT:
22650 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
22652 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
22653 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
22654 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
22655 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
22656 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
22657 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
22660 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
22661 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
22662 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
22663 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
22664 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
22665 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
22666 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
22667 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
22668 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
22670 case X86ISD::FOR: return PerformFORCombine(N, DAG);
22672 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
22673 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
22674 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
22675 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
22676 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
22677 case ISD::ANY_EXTEND:
22678 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
22679 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
22680 case ISD::SIGN_EXTEND_INREG:
22681 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
22682 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
22683 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
22684 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
22685 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
22686 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
22687 case X86ISD::SHUFP: // Handle all target specific shuffles
22688 case X86ISD::PALIGNR:
22689 case X86ISD::UNPCKH:
22690 case X86ISD::UNPCKL:
22691 case X86ISD::MOVHLPS:
22692 case X86ISD::MOVLHPS:
22693 case X86ISD::PSHUFB:
22694 case X86ISD::PSHUFD:
22695 case X86ISD::PSHUFHW:
22696 case X86ISD::PSHUFLW:
22697 case X86ISD::MOVSS:
22698 case X86ISD::MOVSD:
22699 case X86ISD::VPERMILP:
22700 case X86ISD::VPERM2X128:
22701 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
22702 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
22703 case ISD::INTRINSIC_WO_CHAIN:
22704 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
22705 case X86ISD::INSERTPS:
22706 return PerformINSERTPSCombine(N, DAG, Subtarget);
22707 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
22713 /// isTypeDesirableForOp - Return true if the target has native support for
22714 /// the specified value type and it is 'desirable' to use the type for the
22715 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
22716 /// instruction encodings are longer and some i16 instructions are slow.
22717 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
22718 if (!isTypeLegal(VT))
22720 if (VT != MVT::i16)
22727 case ISD::SIGN_EXTEND:
22728 case ISD::ZERO_EXTEND:
22729 case ISD::ANY_EXTEND:
22742 /// IsDesirableToPromoteOp - This method query the target whether it is
22743 /// beneficial for dag combiner to promote the specified node. If true, it
22744 /// should return the desired promotion type by reference.
22745 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
22746 EVT VT = Op.getValueType();
22747 if (VT != MVT::i16)
22750 bool Promote = false;
22751 bool Commute = false;
22752 switch (Op.getOpcode()) {
22755 LoadSDNode *LD = cast<LoadSDNode>(Op);
22756 // If the non-extending load has a single use and it's not live out, then it
22757 // might be folded.
22758 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
22759 Op.hasOneUse()*/) {
22760 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
22761 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
22762 // The only case where we'd want to promote LOAD (rather then it being
22763 // promoted as an operand is when it's only use is liveout.
22764 if (UI->getOpcode() != ISD::CopyToReg)
22771 case ISD::SIGN_EXTEND:
22772 case ISD::ZERO_EXTEND:
22773 case ISD::ANY_EXTEND:
22778 SDValue N0 = Op.getOperand(0);
22779 // Look out for (store (shl (load), x)).
22780 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
22793 SDValue N0 = Op.getOperand(0);
22794 SDValue N1 = Op.getOperand(1);
22795 if (!Commute && MayFoldLoad(N1))
22797 // Avoid disabling potential load folding opportunities.
22798 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
22800 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
22810 //===----------------------------------------------------------------------===//
22811 // X86 Inline Assembly Support
22812 //===----------------------------------------------------------------------===//
22815 // Helper to match a string separated by whitespace.
22816 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
22817 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
22819 for (unsigned i = 0, e = args.size(); i != e; ++i) {
22820 StringRef piece(*args[i]);
22821 if (!s.startswith(piece)) // Check if the piece matches.
22824 s = s.substr(piece.size());
22825 StringRef::size_type pos = s.find_first_not_of(" \t");
22826 if (pos == 0) // We matched a prefix.
22834 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
22837 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
22839 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
22840 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
22841 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
22842 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
22844 if (AsmPieces.size() == 3)
22846 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
22853 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
22854 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
22856 std::string AsmStr = IA->getAsmString();
22858 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
22859 if (!Ty || Ty->getBitWidth() % 16 != 0)
22862 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
22863 SmallVector<StringRef, 4> AsmPieces;
22864 SplitString(AsmStr, AsmPieces, ";\n");
22866 switch (AsmPieces.size()) {
22867 default: return false;
22869 // FIXME: this should verify that we are targeting a 486 or better. If not,
22870 // we will turn this bswap into something that will be lowered to logical
22871 // ops instead of emitting the bswap asm. For now, we don't support 486 or
22872 // lower so don't worry about this.
22874 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
22875 matchAsm(AsmPieces[0], "bswapl", "$0") ||
22876 matchAsm(AsmPieces[0], "bswapq", "$0") ||
22877 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
22878 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
22879 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
22880 // No need to check constraints, nothing other than the equivalent of
22881 // "=r,0" would be valid here.
22882 return IntrinsicLowering::LowerToByteSwap(CI);
22885 // rorw $$8, ${0:w} --> llvm.bswap.i16
22886 if (CI->getType()->isIntegerTy(16) &&
22887 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22888 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
22889 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
22891 const std::string &ConstraintsStr = IA->getConstraintString();
22892 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22893 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22894 if (clobbersFlagRegisters(AsmPieces))
22895 return IntrinsicLowering::LowerToByteSwap(CI);
22899 if (CI->getType()->isIntegerTy(32) &&
22900 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
22901 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
22902 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
22903 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
22905 const std::string &ConstraintsStr = IA->getConstraintString();
22906 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
22907 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
22908 if (clobbersFlagRegisters(AsmPieces))
22909 return IntrinsicLowering::LowerToByteSwap(CI);
22912 if (CI->getType()->isIntegerTy(64)) {
22913 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
22914 if (Constraints.size() >= 2 &&
22915 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
22916 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
22917 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
22918 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
22919 matchAsm(AsmPieces[1], "bswap", "%edx") &&
22920 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
22921 return IntrinsicLowering::LowerToByteSwap(CI);
22929 /// getConstraintType - Given a constraint letter, return the type of
22930 /// constraint it is for this target.
22931 X86TargetLowering::ConstraintType
22932 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
22933 if (Constraint.size() == 1) {
22934 switch (Constraint[0]) {
22945 return C_RegisterClass;
22969 return TargetLowering::getConstraintType(Constraint);
22972 /// Examine constraint type and operand type and determine a weight value.
22973 /// This object must already have been set up with the operand type
22974 /// and the current alternative constraint selected.
22975 TargetLowering::ConstraintWeight
22976 X86TargetLowering::getSingleConstraintMatchWeight(
22977 AsmOperandInfo &info, const char *constraint) const {
22978 ConstraintWeight weight = CW_Invalid;
22979 Value *CallOperandVal = info.CallOperandVal;
22980 // If we don't have a value, we can't do a match,
22981 // but allow it at the lowest weight.
22982 if (!CallOperandVal)
22984 Type *type = CallOperandVal->getType();
22985 // Look at the constraint type.
22986 switch (*constraint) {
22988 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
22999 if (CallOperandVal->getType()->isIntegerTy())
23000 weight = CW_SpecificReg;
23005 if (type->isFloatingPointTy())
23006 weight = CW_SpecificReg;
23009 if (type->isX86_MMXTy() && Subtarget->hasMMX())
23010 weight = CW_SpecificReg;
23014 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
23015 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
23016 weight = CW_Register;
23019 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
23020 if (C->getZExtValue() <= 31)
23021 weight = CW_Constant;
23025 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23026 if (C->getZExtValue() <= 63)
23027 weight = CW_Constant;
23031 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23032 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
23033 weight = CW_Constant;
23037 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23038 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
23039 weight = CW_Constant;
23043 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23044 if (C->getZExtValue() <= 3)
23045 weight = CW_Constant;
23049 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23050 if (C->getZExtValue() <= 0xff)
23051 weight = CW_Constant;
23056 if (dyn_cast<ConstantFP>(CallOperandVal)) {
23057 weight = CW_Constant;
23061 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23062 if ((C->getSExtValue() >= -0x80000000LL) &&
23063 (C->getSExtValue() <= 0x7fffffffLL))
23064 weight = CW_Constant;
23068 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
23069 if (C->getZExtValue() <= 0xffffffff)
23070 weight = CW_Constant;
23077 /// LowerXConstraint - try to replace an X constraint, which matches anything,
23078 /// with another that has more specific requirements based on the type of the
23079 /// corresponding operand.
23080 const char *X86TargetLowering::
23081 LowerXConstraint(EVT ConstraintVT) const {
23082 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
23083 // 'f' like normal targets.
23084 if (ConstraintVT.isFloatingPoint()) {
23085 if (Subtarget->hasSSE2())
23087 if (Subtarget->hasSSE1())
23091 return TargetLowering::LowerXConstraint(ConstraintVT);
23094 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
23095 /// vector. If it is invalid, don't add anything to Ops.
23096 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
23097 std::string &Constraint,
23098 std::vector<SDValue>&Ops,
23099 SelectionDAG &DAG) const {
23102 // Only support length 1 constraints for now.
23103 if (Constraint.length() > 1) return;
23105 char ConstraintLetter = Constraint[0];
23106 switch (ConstraintLetter) {
23109 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23110 if (C->getZExtValue() <= 31) {
23111 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23117 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23118 if (C->getZExtValue() <= 63) {
23119 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23125 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23126 if (isInt<8>(C->getSExtValue())) {
23127 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23133 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23134 if (C->getZExtValue() <= 255) {
23135 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23141 // 32-bit signed value
23142 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23143 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23144 C->getSExtValue())) {
23145 // Widen to 64 bits here to get it sign extended.
23146 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
23149 // FIXME gcc accepts some relocatable values here too, but only in certain
23150 // memory models; it's complicated.
23155 // 32-bit unsigned value
23156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
23157 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
23158 C->getZExtValue())) {
23159 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
23163 // FIXME gcc accepts some relocatable values here too, but only in certain
23164 // memory models; it's complicated.
23168 // Literal immediates are always ok.
23169 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
23170 // Widen to 64 bits here to get it sign extended.
23171 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
23175 // In any sort of PIC mode addresses need to be computed at runtime by
23176 // adding in a register or some sort of table lookup. These can't
23177 // be used as immediates.
23178 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
23181 // If we are in non-pic codegen mode, we allow the address of a global (with
23182 // an optional displacement) to be used with 'i'.
23183 GlobalAddressSDNode *GA = nullptr;
23184 int64_t Offset = 0;
23186 // Match either (GA), (GA+C), (GA+C1+C2), etc.
23188 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
23189 Offset += GA->getOffset();
23191 } else if (Op.getOpcode() == ISD::ADD) {
23192 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23193 Offset += C->getZExtValue();
23194 Op = Op.getOperand(0);
23197 } else if (Op.getOpcode() == ISD::SUB) {
23198 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
23199 Offset += -C->getZExtValue();
23200 Op = Op.getOperand(0);
23205 // Otherwise, this isn't something we can handle, reject it.
23209 const GlobalValue *GV = GA->getGlobal();
23210 // If we require an extra load to get this address, as in PIC mode, we
23211 // can't accept it.
23212 if (isGlobalStubReference(
23213 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
23216 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
23217 GA->getValueType(0), Offset);
23222 if (Result.getNode()) {
23223 Ops.push_back(Result);
23226 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
23229 std::pair<unsigned, const TargetRegisterClass*>
23230 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
23232 // First, see if this is a constraint that directly corresponds to an LLVM
23234 if (Constraint.size() == 1) {
23235 // GCC Constraint Letters
23236 switch (Constraint[0]) {
23238 // TODO: Slight differences here in allocation order and leaving
23239 // RIP in the class. Do they matter any more here than they do
23240 // in the normal allocation?
23241 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
23242 if (Subtarget->is64Bit()) {
23243 if (VT == MVT::i32 || VT == MVT::f32)
23244 return std::make_pair(0U, &X86::GR32RegClass);
23245 if (VT == MVT::i16)
23246 return std::make_pair(0U, &X86::GR16RegClass);
23247 if (VT == MVT::i8 || VT == MVT::i1)
23248 return std::make_pair(0U, &X86::GR8RegClass);
23249 if (VT == MVT::i64 || VT == MVT::f64)
23250 return std::make_pair(0U, &X86::GR64RegClass);
23253 // 32-bit fallthrough
23254 case 'Q': // Q_REGS
23255 if (VT == MVT::i32 || VT == MVT::f32)
23256 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
23257 if (VT == MVT::i16)
23258 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
23259 if (VT == MVT::i8 || VT == MVT::i1)
23260 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
23261 if (VT == MVT::i64)
23262 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
23264 case 'r': // GENERAL_REGS
23265 case 'l': // INDEX_REGS
23266 if (VT == MVT::i8 || VT == MVT::i1)
23267 return std::make_pair(0U, &X86::GR8RegClass);
23268 if (VT == MVT::i16)
23269 return std::make_pair(0U, &X86::GR16RegClass);
23270 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
23271 return std::make_pair(0U, &X86::GR32RegClass);
23272 return std::make_pair(0U, &X86::GR64RegClass);
23273 case 'R': // LEGACY_REGS
23274 if (VT == MVT::i8 || VT == MVT::i1)
23275 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
23276 if (VT == MVT::i16)
23277 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
23278 if (VT == MVT::i32 || !Subtarget->is64Bit())
23279 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
23280 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
23281 case 'f': // FP Stack registers.
23282 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
23283 // value to the correct fpstack register class.
23284 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
23285 return std::make_pair(0U, &X86::RFP32RegClass);
23286 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
23287 return std::make_pair(0U, &X86::RFP64RegClass);
23288 return std::make_pair(0U, &X86::RFP80RegClass);
23289 case 'y': // MMX_REGS if MMX allowed.
23290 if (!Subtarget->hasMMX()) break;
23291 return std::make_pair(0U, &X86::VR64RegClass);
23292 case 'Y': // SSE_REGS if SSE2 allowed
23293 if (!Subtarget->hasSSE2()) break;
23295 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
23296 if (!Subtarget->hasSSE1()) break;
23298 switch (VT.SimpleTy) {
23300 // Scalar SSE types.
23303 return std::make_pair(0U, &X86::FR32RegClass);
23306 return std::make_pair(0U, &X86::FR64RegClass);
23314 return std::make_pair(0U, &X86::VR128RegClass);
23322 return std::make_pair(0U, &X86::VR256RegClass);
23327 return std::make_pair(0U, &X86::VR512RegClass);
23333 // Use the default implementation in TargetLowering to convert the register
23334 // constraint into a member of a register class.
23335 std::pair<unsigned, const TargetRegisterClass*> Res;
23336 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
23338 // Not found as a standard register?
23340 // Map st(0) -> st(7) -> ST0
23341 if (Constraint.size() == 7 && Constraint[0] == '{' &&
23342 tolower(Constraint[1]) == 's' &&
23343 tolower(Constraint[2]) == 't' &&
23344 Constraint[3] == '(' &&
23345 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
23346 Constraint[5] == ')' &&
23347 Constraint[6] == '}') {
23349 Res.first = X86::FP0+Constraint[4]-'0';
23350 Res.second = &X86::RFP80RegClass;
23354 // GCC allows "st(0)" to be called just plain "st".
23355 if (StringRef("{st}").equals_lower(Constraint)) {
23356 Res.first = X86::FP0;
23357 Res.second = &X86::RFP80RegClass;
23362 if (StringRef("{flags}").equals_lower(Constraint)) {
23363 Res.first = X86::EFLAGS;
23364 Res.second = &X86::CCRRegClass;
23368 // 'A' means EAX + EDX.
23369 if (Constraint == "A") {
23370 Res.first = X86::EAX;
23371 Res.second = &X86::GR32_ADRegClass;
23377 // Otherwise, check to see if this is a register class of the wrong value
23378 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
23379 // turn into {ax},{dx}.
23380 if (Res.second->hasType(VT))
23381 return Res; // Correct type already, nothing to do.
23383 // All of the single-register GCC register classes map their values onto
23384 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
23385 // really want an 8-bit or 32-bit register, map to the appropriate register
23386 // class and return the appropriate register.
23387 if (Res.second == &X86::GR16RegClass) {
23388 if (VT == MVT::i8 || VT == MVT::i1) {
23389 unsigned DestReg = 0;
23390 switch (Res.first) {
23392 case X86::AX: DestReg = X86::AL; break;
23393 case X86::DX: DestReg = X86::DL; break;
23394 case X86::CX: DestReg = X86::CL; break;
23395 case X86::BX: DestReg = X86::BL; break;
23398 Res.first = DestReg;
23399 Res.second = &X86::GR8RegClass;
23401 } else if (VT == MVT::i32 || VT == MVT::f32) {
23402 unsigned DestReg = 0;
23403 switch (Res.first) {
23405 case X86::AX: DestReg = X86::EAX; break;
23406 case X86::DX: DestReg = X86::EDX; break;
23407 case X86::CX: DestReg = X86::ECX; break;
23408 case X86::BX: DestReg = X86::EBX; break;
23409 case X86::SI: DestReg = X86::ESI; break;
23410 case X86::DI: DestReg = X86::EDI; break;
23411 case X86::BP: DestReg = X86::EBP; break;
23412 case X86::SP: DestReg = X86::ESP; break;
23415 Res.first = DestReg;
23416 Res.second = &X86::GR32RegClass;
23418 } else if (VT == MVT::i64 || VT == MVT::f64) {
23419 unsigned DestReg = 0;
23420 switch (Res.first) {
23422 case X86::AX: DestReg = X86::RAX; break;
23423 case X86::DX: DestReg = X86::RDX; break;
23424 case X86::CX: DestReg = X86::RCX; break;
23425 case X86::BX: DestReg = X86::RBX; break;
23426 case X86::SI: DestReg = X86::RSI; break;
23427 case X86::DI: DestReg = X86::RDI; break;
23428 case X86::BP: DestReg = X86::RBP; break;
23429 case X86::SP: DestReg = X86::RSP; break;
23432 Res.first = DestReg;
23433 Res.second = &X86::GR64RegClass;
23436 } else if (Res.second == &X86::FR32RegClass ||
23437 Res.second == &X86::FR64RegClass ||
23438 Res.second == &X86::VR128RegClass ||
23439 Res.second == &X86::VR256RegClass ||
23440 Res.second == &X86::FR32XRegClass ||
23441 Res.second == &X86::FR64XRegClass ||
23442 Res.second == &X86::VR128XRegClass ||
23443 Res.second == &X86::VR256XRegClass ||
23444 Res.second == &X86::VR512RegClass) {
23445 // Handle references to XMM physical registers that got mapped into the
23446 // wrong class. This can happen with constraints like {xmm0} where the
23447 // target independent register mapper will just pick the first match it can
23448 // find, ignoring the required type.
23450 if (VT == MVT::f32 || VT == MVT::i32)
23451 Res.second = &X86::FR32RegClass;
23452 else if (VT == MVT::f64 || VT == MVT::i64)
23453 Res.second = &X86::FR64RegClass;
23454 else if (X86::VR128RegClass.hasType(VT))
23455 Res.second = &X86::VR128RegClass;
23456 else if (X86::VR256RegClass.hasType(VT))
23457 Res.second = &X86::VR256RegClass;
23458 else if (X86::VR512RegClass.hasType(VT))
23459 Res.second = &X86::VR512RegClass;
23465 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
23467 // Scaling factors are not free at all.
23468 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
23469 // will take 2 allocations in the out of order engine instead of 1
23470 // for plain addressing mode, i.e. inst (reg1).
23472 // vaddps (%rsi,%drx), %ymm0, %ymm1
23473 // Requires two allocations (one for the load, one for the computation)
23475 // vaddps (%rsi), %ymm0, %ymm1
23476 // Requires just 1 allocation, i.e., freeing allocations for other operations
23477 // and having less micro operations to execute.
23479 // For some X86 architectures, this is even worse because for instance for
23480 // stores, the complex addressing mode forces the instruction to use the
23481 // "load" ports instead of the dedicated "store" port.
23482 // E.g., on Haswell:
23483 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
23484 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
23485 if (isLegalAddressingMode(AM, Ty))
23486 // Scale represents reg2 * scale, thus account for 1
23487 // as soon as we use a second register.
23488 return AM.Scale != 0;
23492 bool X86TargetLowering::isTargetFTOL() const {
23493 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();