1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/VectorExtras.h"
27 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/StringExtras.h"
39 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
40 : TargetLowering(TM) {
41 Subtarget = &TM.getSubtarget<X86Subtarget>();
42 X86ScalarSSE = Subtarget->hasSSE2();
43 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
45 // Set up the TargetLowering object.
47 // X86 is weird, it always uses i8 for shift amounts and setcc results.
48 setShiftAmountType(MVT::i8);
49 setSetCCResultType(MVT::i8);
50 setSetCCResultContents(ZeroOrOneSetCCResult);
51 setSchedulingPreference(SchedulingForRegPressure);
52 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
53 setStackPointerRegisterToSaveRestore(X86StackPtr);
55 if (Subtarget->isTargetDarwin()) {
56 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
57 setUseUnderscoreSetJmp(false);
58 setUseUnderscoreLongJmp(false);
59 } else if (Subtarget->isTargetMingw()) {
60 // MS runtime is weird: it exports _setjmp, but longjmp!
61 setUseUnderscoreSetJmp(true);
62 setUseUnderscoreLongJmp(false);
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
68 // Set up the register classes.
69 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
70 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
71 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
72 if (Subtarget->is64Bit())
73 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
75 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
77 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
79 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
80 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
81 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
83 if (Subtarget->is64Bit()) {
84 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
85 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
88 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
89 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
91 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
94 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
96 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
97 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
98 // SSE has no i16 to fp conversion, only i32
100 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
102 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
103 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
106 if (!Subtarget->is64Bit()) {
107 // Custom lower SINT_TO_FP and FP_TO_SINT from/to i64 in 32-bit mode.
108 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
109 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
112 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
114 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
115 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
118 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
120 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
121 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
124 // Handle FP_TO_UINT by promoting the destination to a larger signed
126 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
127 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
128 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
130 if (Subtarget->is64Bit()) {
131 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
132 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
134 if (X86ScalarSSE && !Subtarget->hasSSE3())
135 // Expand FP_TO_UINT into a select.
136 // FIXME: We would like to use a Custom expander here eventually to do
137 // the optimal thing for SSE vs. the default expansion in the legalizer.
138 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
140 // With SSE3 we can use fisttpll to convert to a signed i64.
141 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
144 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
146 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
147 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
150 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
151 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
152 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
153 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
154 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
155 if (Subtarget->is64Bit())
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
160 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
161 setOperationAction(ISD::FREM , MVT::f64 , Expand);
163 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
164 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
165 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
166 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
167 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
168 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
169 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
170 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
171 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
172 if (Subtarget->is64Bit()) {
173 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
175 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
178 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
179 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
181 // These should be promoted to a larger select which is supported.
182 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
183 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
184 // X86 wants to expand cmov itself.
185 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
186 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
187 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
188 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
189 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
190 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
191 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
192 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
193 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
194 if (Subtarget->is64Bit()) {
195 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
196 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
198 // X86 ret instruction may pop stack.
199 setOperationAction(ISD::RET , MVT::Other, Custom);
201 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
202 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
203 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
204 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
205 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
206 if (Subtarget->is64Bit()) {
207 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
208 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
209 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
210 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
212 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
213 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
214 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
215 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
216 // X86 wants to expand memset / memcpy itself.
217 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
218 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
220 // We don't have line number support yet.
221 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
222 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
223 // FIXME - use subtarget debug flags
224 if (!Subtarget->isTargetDarwin() &&
225 !Subtarget->isTargetELF() &&
226 !Subtarget->isTargetCygMing())
227 setOperationAction(ISD::LABEL, MVT::Other, Expand);
229 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
230 setOperationAction(ISD::VASTART , MVT::Other, Custom);
231 setOperationAction(ISD::VAARG , MVT::Other, Expand);
232 setOperationAction(ISD::VAEND , MVT::Other, Expand);
233 if (Subtarget->is64Bit())
234 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
236 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
238 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
239 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
240 if (Subtarget->is64Bit())
241 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
242 if (Subtarget->isTargetCygMing())
243 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
245 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
248 // Set up the FP register classes.
249 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
250 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
252 // Use ANDPD to simulate FABS.
253 setOperationAction(ISD::FABS , MVT::f64, Custom);
254 setOperationAction(ISD::FABS , MVT::f32, Custom);
256 // Use XORP to simulate FNEG.
257 setOperationAction(ISD::FNEG , MVT::f64, Custom);
258 setOperationAction(ISD::FNEG , MVT::f32, Custom);
260 // Use ANDPD and ORPD to simulate FCOPYSIGN.
261 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
262 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
264 // We don't support sin/cos/fmod
265 setOperationAction(ISD::FSIN , MVT::f64, Expand);
266 setOperationAction(ISD::FCOS , MVT::f64, Expand);
267 setOperationAction(ISD::FREM , MVT::f64, Expand);
268 setOperationAction(ISD::FSIN , MVT::f32, Expand);
269 setOperationAction(ISD::FCOS , MVT::f32, Expand);
270 setOperationAction(ISD::FREM , MVT::f32, Expand);
272 // Expand FP immediates into loads from the stack, except for the special
274 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
275 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
276 addLegalFPImmediate(+0.0); // xorps / xorpd
278 // Set up the FP register classes.
279 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
281 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
282 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
283 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
286 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
287 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
290 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
291 addLegalFPImmediate(+0.0); // FLD0
292 addLegalFPImmediate(+1.0); // FLD1
293 addLegalFPImmediate(-0.0); // FLD0/FCHS
294 addLegalFPImmediate(-1.0); // FLD1/FCHS
297 // First set operation action for all vector types to expand. Then we
298 // will selectively turn on ones that can be effectively codegen'd.
299 for (unsigned VT = (unsigned)MVT::Vector + 1;
300 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
301 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
302 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
303 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
304 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
305 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
306 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
307 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
308 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
309 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
310 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
311 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
312 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
313 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
314 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
315 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
318 if (Subtarget->hasMMX()) {
319 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
320 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
321 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
322 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
324 // FIXME: add MMX packed arithmetics
326 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
327 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
328 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
329 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
331 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
332 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
333 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
335 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
336 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
338 setOperationAction(ISD::AND, MVT::v8i8, Promote);
339 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
340 setOperationAction(ISD::AND, MVT::v4i16, Promote);
341 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
342 setOperationAction(ISD::AND, MVT::v2i32, Promote);
343 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
344 setOperationAction(ISD::AND, MVT::v1i64, Legal);
346 setOperationAction(ISD::OR, MVT::v8i8, Promote);
347 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
348 setOperationAction(ISD::OR, MVT::v4i16, Promote);
349 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
350 setOperationAction(ISD::OR, MVT::v2i32, Promote);
351 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
352 setOperationAction(ISD::OR, MVT::v1i64, Legal);
354 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
355 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
356 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
357 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
358 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
359 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
360 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
362 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
363 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
364 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
365 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
366 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
367 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
368 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
370 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
371 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
372 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
373 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
375 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
376 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
377 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
378 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
380 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
381 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
384 if (Subtarget->hasSSE1()) {
385 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
387 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
388 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
389 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
390 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
391 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
392 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
393 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
394 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
395 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
398 if (Subtarget->hasSSE2()) {
399 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
400 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
401 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
402 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
403 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
405 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
406 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
407 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
408 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
409 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
410 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
411 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
412 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
413 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
414 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
415 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
416 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
417 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
419 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
420 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
421 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
422 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
423 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
424 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
426 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
427 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
428 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
429 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
430 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
432 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
433 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
434 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
435 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
436 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
437 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
439 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
440 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
441 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
442 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
443 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
444 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
445 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
446 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
447 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
448 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
449 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
450 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
453 // Custom lower v2i64 and v2f64 selects.
454 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
455 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
456 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
457 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
460 // We want to custom lower some of our intrinsics.
461 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
463 // We have target-specific dag combine patterns for the following nodes:
464 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
465 setTargetDAGCombine(ISD::SELECT);
467 computeRegisterProperties();
469 // FIXME: These should be based on subtarget info. Plus, the values should
470 // be smaller when we are in optimizing for size mode.
471 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
472 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
473 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
474 allowUnalignedMemoryAccesses = true; // x86 supports it!
478 //===----------------------------------------------------------------------===//
479 // Return Value Calling Convention Implementation
480 //===----------------------------------------------------------------------===//
482 #include "X86GenCallingConv.inc"
484 /// LowerRET - Lower an ISD::RET node.
485 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
486 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
488 SmallVector<CCValAssign, 16> RVLocs;
489 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
490 CCState CCInfo(CC, getTargetMachine(), RVLocs);
491 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
494 // If this is the first return lowered for this function, add the regs to the
495 // liveout set for the function.
496 if (DAG.getMachineFunction().liveout_empty()) {
497 for (unsigned i = 0; i != RVLocs.size(); ++i)
498 if (RVLocs[i].isRegLoc())
499 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
502 SDOperand Chain = Op.getOperand(0);
505 // Copy the result values into the output registers.
506 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
507 RVLocs[0].getLocReg() != X86::ST0) {
508 for (unsigned i = 0; i != RVLocs.size(); ++i) {
509 CCValAssign &VA = RVLocs[i];
510 assert(VA.isRegLoc() && "Can only return in registers!");
511 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
513 Flag = Chain.getValue(1);
516 // We need to handle a destination of ST0 specially, because it isn't really
518 SDOperand Value = Op.getOperand(1);
520 // If this is an FP return with ScalarSSE, we need to move the value from
521 // an XMM register onto the fp-stack.
525 // If this is a load into a scalarsse value, don't store the loaded value
526 // back to the stack, only to reload it: just replace the scalar-sse load.
527 if (ISD::isNON_EXTLoad(Value.Val) &&
528 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
529 Chain = Value.getOperand(0);
530 MemLoc = Value.getOperand(1);
532 // Spill the value to memory and reload it into top of stack.
533 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
534 MachineFunction &MF = DAG.getMachineFunction();
535 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
536 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
537 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
539 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
540 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
541 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
542 Chain = Value.getValue(1);
545 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
546 SDOperand Ops[] = { Chain, Value };
547 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
548 Flag = Chain.getValue(1);
551 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
553 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
555 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
559 /// LowerCallResult - Lower the result values of an ISD::CALL into the
560 /// appropriate copies out of appropriate physical registers. This assumes that
561 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
562 /// being lowered. The returns a SDNode with the same number of values as the
564 SDNode *X86TargetLowering::
565 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
566 unsigned CallingConv, SelectionDAG &DAG) {
568 // Assign locations to each value returned by this call.
569 SmallVector<CCValAssign, 16> RVLocs;
570 CCState CCInfo(CallingConv, getTargetMachine(), RVLocs);
571 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
574 SmallVector<SDOperand, 8> ResultVals;
576 // Copy all of the result registers out of their specified physreg.
577 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
578 for (unsigned i = 0; i != RVLocs.size(); ++i) {
579 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
580 RVLocs[i].getValVT(), InFlag).getValue(1);
581 InFlag = Chain.getValue(2);
582 ResultVals.push_back(Chain.getValue(0));
585 // Copies from the FP stack are special, as ST0 isn't a valid register
586 // before the fp stackifier runs.
588 // Copy ST0 into an RFP register with FP_GET_RESULT.
589 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
590 SDOperand GROps[] = { Chain, InFlag };
591 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
592 Chain = RetVal.getValue(1);
593 InFlag = RetVal.getValue(2);
595 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
598 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
599 // shouldn't be necessary except that RFP cannot be live across
600 // multiple blocks. When stackifier is fixed, they can be uncoupled.
601 MachineFunction &MF = DAG.getMachineFunction();
602 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
603 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
605 Chain, RetVal, StackSlot, DAG.getValueType(RVLocs[0].getValVT()), InFlag
607 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
608 RetVal = DAG.getLoad(RVLocs[0].getValVT(), Chain, StackSlot, NULL, 0);
609 Chain = RetVal.getValue(1);
612 if (RVLocs[0].getValVT() == MVT::f32 && !X86ScalarSSE)
613 // FIXME: we would really like to remember that this FP_ROUND
614 // operation is okay to eliminate if we allow excess FP precision.
615 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
616 ResultVals.push_back(RetVal);
619 // Merge everything together with a MERGE_VALUES node.
620 ResultVals.push_back(Chain);
621 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
622 &ResultVals[0], ResultVals.size()).Val;
626 //===----------------------------------------------------------------------===//
627 // C & StdCall Calling Convention implementation
628 //===----------------------------------------------------------------------===//
629 // StdCall calling convention seems to be standard for many Windows' API
630 // routines and around. It differs from C calling convention just a little:
631 // callee should clean up the stack, not caller. Symbols should be also
632 // decorated in some fancy way :) It doesn't support any vector arguments.
634 /// AddLiveIn - This helper function adds the specified physical register to the
635 /// MachineFunction as a live in value. It also creates a corresponding virtual
637 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
638 const TargetRegisterClass *RC) {
639 assert(RC->contains(PReg) && "Not the correct regclass!");
640 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
641 MF.addLiveIn(PReg, VReg);
645 SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
647 unsigned NumArgs = Op.Val->getNumValues() - 1;
648 MachineFunction &MF = DAG.getMachineFunction();
649 MachineFrameInfo *MFI = MF.getFrameInfo();
650 SDOperand Root = Op.getOperand(0);
651 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
653 // Assign locations to all of the incoming arguments.
654 SmallVector<CCValAssign, 16> ArgLocs;
655 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
657 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_C);
659 SmallVector<SDOperand, 8> ArgValues;
660 unsigned LastVal = ~0U;
661 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
662 CCValAssign &VA = ArgLocs[i];
663 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
665 assert(VA.getValNo() != LastVal &&
666 "Don't support value assigned to multiple locs yet");
667 LastVal = VA.getValNo();
670 MVT::ValueType RegVT = VA.getLocVT();
671 TargetRegisterClass *RC;
672 if (RegVT == MVT::i32)
673 RC = X86::GR32RegisterClass;
675 assert(MVT::isVector(RegVT));
676 RC = X86::VR128RegisterClass;
679 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
680 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
682 // If this is an 8 or 16-bit value, it is really passed promoted to 32
683 // bits. Insert an assert[sz]ext to capture this, then truncate to the
685 if (VA.getLocInfo() == CCValAssign::SExt)
686 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
687 DAG.getValueType(VA.getValVT()));
688 else if (VA.getLocInfo() == CCValAssign::ZExt)
689 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
690 DAG.getValueType(VA.getValVT()));
692 if (VA.getLocInfo() != CCValAssign::Full)
693 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
695 ArgValues.push_back(ArgValue);
697 assert(VA.isMemLoc());
699 // Create the nodes corresponding to a load from this parameter slot.
700 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
701 VA.getLocMemOffset());
702 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
703 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
707 unsigned StackSize = CCInfo.getNextStackOffset();
709 ArgValues.push_back(Root);
711 // If the function takes variable number of arguments, make a frame index for
712 // the start of the first vararg value... for expansion of llvm.va_start.
714 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
716 if (isStdCall && !isVarArg) {
717 BytesToPopOnReturn = StackSize; // Callee pops everything..
718 BytesCallerReserves = 0;
720 BytesToPopOnReturn = 0; // Callee pops nothing.
722 // If this is an sret function, the return should pop the hidden pointer.
724 (cast<ConstantSDNode>(Op.getOperand(3))->getValue() &
725 ISD::ParamFlags::StructReturn))
726 BytesToPopOnReturn = 4;
728 BytesCallerReserves = StackSize;
731 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
732 ReturnAddrIndex = 0; // No return address slot generated yet.
734 MF.getInfo<X86MachineFunctionInfo>()
735 ->setBytesToPopOnReturn(BytesToPopOnReturn);
737 // Return the new list of results.
738 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
739 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
742 SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
744 SDOperand Chain = Op.getOperand(0);
745 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
746 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
747 SDOperand Callee = Op.getOperand(4);
748 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
750 // Analyze operands of the call, assigning locations to each operand.
751 SmallVector<CCValAssign, 16> ArgLocs;
752 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
753 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_C);
755 // Get a count of how many bytes are to be pushed on the stack.
756 unsigned NumBytes = CCInfo.getNextStackOffset();
758 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
760 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
761 SmallVector<SDOperand, 8> MemOpChains;
765 // Walk the register/memloc assignments, inserting copies/loads.
766 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
767 CCValAssign &VA = ArgLocs[i];
768 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
770 // Promote the value if needed.
771 switch (VA.getLocInfo()) {
772 default: assert(0 && "Unknown loc info!");
773 case CCValAssign::Full: break;
774 case CCValAssign::SExt:
775 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
777 case CCValAssign::ZExt:
778 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
780 case CCValAssign::AExt:
781 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
786 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
788 assert(VA.isMemLoc());
789 if (StackPtr.Val == 0)
790 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
791 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
792 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
793 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
797 // If the first argument is an sret pointer, remember it.
798 bool isSRet = NumOps &&
799 (cast<ConstantSDNode>(Op.getOperand(6))->getValue() &
800 ISD::ParamFlags::StructReturn);
802 if (!MemOpChains.empty())
803 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
804 &MemOpChains[0], MemOpChains.size());
806 // Build a sequence of copy-to-reg nodes chained together with token chain
807 // and flag operands which copy the outgoing args into registers.
809 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
810 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
812 InFlag = Chain.getValue(1);
815 // ELF / PIC requires GOT in the EBX register before function calls via PLT
817 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
818 Subtarget->isPICStyleGOT()) {
819 Chain = DAG.getCopyToReg(Chain, X86::EBX,
820 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
822 InFlag = Chain.getValue(1);
825 // If the callee is a GlobalAddress node (quite common, every direct call is)
826 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
827 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
828 // We should use extra load for direct calls to dllimported functions in
830 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
831 getTargetMachine(), true))
832 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
833 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
834 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
836 // Returns a chain & a flag for retval copy to use.
837 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
838 SmallVector<SDOperand, 8> Ops;
839 Ops.push_back(Chain);
840 Ops.push_back(Callee);
842 // Add argument registers to the end of the list so that they are known live
844 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
845 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
846 RegsToPass[i].second.getValueType()));
848 // Add an implicit use GOT pointer in EBX.
849 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
850 Subtarget->isPICStyleGOT())
851 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
854 Ops.push_back(InFlag);
856 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
857 NodeTys, &Ops[0], Ops.size());
858 InFlag = Chain.getValue(1);
860 // Create the CALLSEQ_END node.
861 unsigned NumBytesForCalleeToPush = 0;
863 if (CC == CallingConv::X86_StdCall) {
865 NumBytesForCalleeToPush = isSRet ? 4 : 0;
867 NumBytesForCalleeToPush = NumBytes;
869 // If this is is a call to a struct-return function, the callee
870 // pops the hidden struct pointer, so we have to push it back.
871 // This is common for Darwin/X86, Linux & Mingw32 targets.
872 NumBytesForCalleeToPush = isSRet ? 4 : 0;
875 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
877 Ops.push_back(Chain);
878 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
879 Ops.push_back(DAG.getConstant(NumBytesForCalleeToPush, getPointerTy()));
880 Ops.push_back(InFlag);
881 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
882 InFlag = Chain.getValue(1);
884 // Handle result values, copying them out of physregs into vregs that we
886 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
890 //===----------------------------------------------------------------------===//
891 // FastCall Calling Convention implementation
892 //===----------------------------------------------------------------------===//
894 // The X86 'fastcall' calling convention passes up to two integer arguments in
895 // registers (an appropriate portion of ECX/EDX), passes arguments in C order,
896 // and requires that the callee pop its arguments off the stack (allowing proper
897 // tail calls), and has the same return value conventions as C calling convs.
899 // This calling convention always arranges for the callee pop value to be 8n+4
900 // bytes, which is needed for tail recursion elimination and stack alignment
903 X86TargetLowering::LowerFastCCArguments(SDOperand Op, SelectionDAG &DAG) {
904 MachineFunction &MF = DAG.getMachineFunction();
905 MachineFrameInfo *MFI = MF.getFrameInfo();
906 SDOperand Root = Op.getOperand(0);
908 // Assign locations to all of the incoming arguments.
909 SmallVector<CCValAssign, 16> ArgLocs;
910 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
912 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_32_FastCall);
914 SmallVector<SDOperand, 8> ArgValues;
915 unsigned LastVal = ~0U;
916 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
917 CCValAssign &VA = ArgLocs[i];
918 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
920 assert(VA.getValNo() != LastVal &&
921 "Don't support value assigned to multiple locs yet");
922 LastVal = VA.getValNo();
925 MVT::ValueType RegVT = VA.getLocVT();
926 TargetRegisterClass *RC;
927 if (RegVT == MVT::i32)
928 RC = X86::GR32RegisterClass;
930 assert(MVT::isVector(RegVT));
931 RC = X86::VR128RegisterClass;
934 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
935 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
937 // If this is an 8 or 16-bit value, it is really passed promoted to 32
938 // bits. Insert an assert[sz]ext to capture this, then truncate to the
940 if (VA.getLocInfo() == CCValAssign::SExt)
941 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
942 DAG.getValueType(VA.getValVT()));
943 else if (VA.getLocInfo() == CCValAssign::ZExt)
944 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
945 DAG.getValueType(VA.getValVT()));
947 if (VA.getLocInfo() != CCValAssign::Full)
948 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
950 ArgValues.push_back(ArgValue);
952 assert(VA.isMemLoc());
954 // Create the nodes corresponding to a load from this parameter slot.
955 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
956 VA.getLocMemOffset());
957 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
958 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
962 ArgValues.push_back(Root);
964 unsigned StackSize = CCInfo.getNextStackOffset();
966 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
967 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
968 // arguments and the arguments after the retaddr has been pushed are aligned.
969 if ((StackSize & 7) == 0)
973 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
974 RegSaveFrameIndex = 0xAAAAAAA; // X86-64 only.
975 ReturnAddrIndex = 0; // No return address slot generated yet.
976 BytesToPopOnReturn = StackSize; // Callee pops all stack arguments.
977 BytesCallerReserves = 0;
979 MF.getInfo<X86MachineFunctionInfo>()
980 ->setBytesToPopOnReturn(BytesToPopOnReturn);
982 // Return the new list of results.
983 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
984 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
987 SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
989 SDOperand Chain = Op.getOperand(0);
990 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
991 SDOperand Callee = Op.getOperand(4);
993 // Analyze operands of the call, assigning locations to each operand.
994 SmallVector<CCValAssign, 16> ArgLocs;
995 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
996 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_32_FastCall);
998 // Get a count of how many bytes are to be pushed on the stack.
999 unsigned NumBytes = CCInfo.getNextStackOffset();
1001 if (!Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows()) {
1002 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1003 // arguments and the arguments after the retaddr has been pushed are aligned.
1004 if ((NumBytes & 7) == 0)
1008 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1010 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1011 SmallVector<SDOperand, 8> MemOpChains;
1015 // Walk the register/memloc assignments, inserting copies/loads.
1016 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1017 CCValAssign &VA = ArgLocs[i];
1018 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1020 // Promote the value if needed.
1021 switch (VA.getLocInfo()) {
1022 default: assert(0 && "Unknown loc info!");
1023 case CCValAssign::Full: break;
1024 case CCValAssign::SExt:
1025 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1027 case CCValAssign::ZExt:
1028 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1030 case CCValAssign::AExt:
1031 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1035 if (VA.isRegLoc()) {
1036 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1038 assert(VA.isMemLoc());
1039 if (StackPtr.Val == 0)
1040 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1041 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1042 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1043 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1047 if (!MemOpChains.empty())
1048 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1049 &MemOpChains[0], MemOpChains.size());
1051 // Build a sequence of copy-to-reg nodes chained together with token chain
1052 // and flag operands which copy the outgoing args into registers.
1054 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1055 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1057 InFlag = Chain.getValue(1);
1060 // If the callee is a GlobalAddress node (quite common, every direct call is)
1061 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1062 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1063 // We should use extra load for direct calls to dllimported functions in
1065 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1066 getTargetMachine(), true))
1067 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1068 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1069 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1071 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1073 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1074 Subtarget->isPICStyleGOT()) {
1075 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1076 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1078 InFlag = Chain.getValue(1);
1081 // Returns a chain & a flag for retval copy to use.
1082 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1083 SmallVector<SDOperand, 8> Ops;
1084 Ops.push_back(Chain);
1085 Ops.push_back(Callee);
1087 // Add argument registers to the end of the list so that they are known live
1089 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1090 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1091 RegsToPass[i].second.getValueType()));
1093 // Add an implicit use GOT pointer in EBX.
1094 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1095 Subtarget->isPICStyleGOT())
1096 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1099 Ops.push_back(InFlag);
1101 // FIXME: Do not generate X86ISD::TAILCALL for now.
1102 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1103 NodeTys, &Ops[0], Ops.size());
1104 InFlag = Chain.getValue(1);
1106 // Returns a flag for retval copy to use.
1107 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1109 Ops.push_back(Chain);
1110 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1111 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1112 Ops.push_back(InFlag);
1113 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1114 InFlag = Chain.getValue(1);
1116 // Handle result values, copying them out of physregs into vregs that we
1118 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1122 //===----------------------------------------------------------------------===//
1123 // X86-64 C Calling Convention implementation
1124 //===----------------------------------------------------------------------===//
1127 X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
1128 MachineFunction &MF = DAG.getMachineFunction();
1129 MachineFrameInfo *MFI = MF.getFrameInfo();
1130 SDOperand Root = Op.getOperand(0);
1131 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1133 static const unsigned GPR64ArgRegs[] = {
1134 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1136 static const unsigned XMMArgRegs[] = {
1137 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1138 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1142 // Assign locations to all of the incoming arguments.
1143 SmallVector<CCValAssign, 16> ArgLocs;
1144 CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
1146 CCInfo.AnalyzeFormalArguments(Op.Val, CC_X86_64_C);
1148 SmallVector<SDOperand, 8> ArgValues;
1149 unsigned LastVal = ~0U;
1150 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1151 CCValAssign &VA = ArgLocs[i];
1152 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1154 assert(VA.getValNo() != LastVal &&
1155 "Don't support value assigned to multiple locs yet");
1156 LastVal = VA.getValNo();
1158 if (VA.isRegLoc()) {
1159 MVT::ValueType RegVT = VA.getLocVT();
1160 TargetRegisterClass *RC;
1161 if (RegVT == MVT::i32)
1162 RC = X86::GR32RegisterClass;
1163 else if (RegVT == MVT::i64)
1164 RC = X86::GR64RegisterClass;
1165 else if (RegVT == MVT::f32)
1166 RC = X86::FR32RegisterClass;
1167 else if (RegVT == MVT::f64)
1168 RC = X86::FR64RegisterClass;
1170 assert(MVT::isVector(RegVT));
1171 RC = X86::VR128RegisterClass;
1174 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1175 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1177 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1178 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1180 if (VA.getLocInfo() == CCValAssign::SExt)
1181 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1182 DAG.getValueType(VA.getValVT()));
1183 else if (VA.getLocInfo() == CCValAssign::ZExt)
1184 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1185 DAG.getValueType(VA.getValVT()));
1187 if (VA.getLocInfo() != CCValAssign::Full)
1188 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1190 ArgValues.push_back(ArgValue);
1192 assert(VA.isMemLoc());
1194 // Create the nodes corresponding to a load from this parameter slot.
1195 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1196 VA.getLocMemOffset());
1197 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1198 ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
1202 unsigned StackSize = CCInfo.getNextStackOffset();
1204 // If the function takes variable number of arguments, make a frame index for
1205 // the start of the first vararg value... for expansion of llvm.va_start.
1207 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1208 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1210 // For X86-64, if there are vararg parameters that are passed via
1211 // registers, then we must store them to their spots on the stack so they
1212 // may be loaded by deferencing the result of va_next.
1213 VarArgsGPOffset = NumIntRegs * 8;
1214 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1215 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1216 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1218 // Store the integer parameter registers.
1219 SmallVector<SDOperand, 8> MemOps;
1220 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1221 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1222 DAG.getConstant(VarArgsGPOffset, getPointerTy()));
1223 for (; NumIntRegs != 6; ++NumIntRegs) {
1224 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1225 X86::GR64RegisterClass);
1226 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1227 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1228 MemOps.push_back(Store);
1229 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1230 DAG.getConstant(8, getPointerTy()));
1233 // Now store the XMM (fp + vector) parameter registers.
1234 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1235 DAG.getConstant(VarArgsFPOffset, getPointerTy()));
1236 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1237 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1238 X86::VR128RegisterClass);
1239 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1240 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1241 MemOps.push_back(Store);
1242 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1243 DAG.getConstant(16, getPointerTy()));
1245 if (!MemOps.empty())
1246 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1247 &MemOps[0], MemOps.size());
1250 ArgValues.push_back(Root);
1252 ReturnAddrIndex = 0; // No return address slot generated yet.
1253 BytesToPopOnReturn = 0; // Callee pops nothing.
1254 BytesCallerReserves = StackSize;
1256 // Return the new list of results.
1257 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1258 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1262 X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
1264 SDOperand Chain = Op.getOperand(0);
1265 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1266 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
1267 SDOperand Callee = Op.getOperand(4);
1269 // Analyze operands of the call, assigning locations to each operand.
1270 SmallVector<CCValAssign, 16> ArgLocs;
1271 CCState CCInfo(CC, getTargetMachine(), ArgLocs);
1272 CCInfo.AnalyzeCallOperands(Op.Val, CC_X86_64_C);
1274 // Get a count of how many bytes are to be pushed on the stack.
1275 unsigned NumBytes = CCInfo.getNextStackOffset();
1276 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
1278 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1279 SmallVector<SDOperand, 8> MemOpChains;
1283 // Walk the register/memloc assignments, inserting copies/loads.
1284 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1285 CCValAssign &VA = ArgLocs[i];
1286 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1288 // Promote the value if needed.
1289 switch (VA.getLocInfo()) {
1290 default: assert(0 && "Unknown loc info!");
1291 case CCValAssign::Full: break;
1292 case CCValAssign::SExt:
1293 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1295 case CCValAssign::ZExt:
1296 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1298 case CCValAssign::AExt:
1299 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1303 if (VA.isRegLoc()) {
1304 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1306 assert(VA.isMemLoc());
1307 if (StackPtr.Val == 0)
1308 StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
1309 SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
1310 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1311 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1315 if (!MemOpChains.empty())
1316 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1317 &MemOpChains[0], MemOpChains.size());
1319 // Build a sequence of copy-to-reg nodes chained together with token chain
1320 // and flag operands which copy the outgoing args into registers.
1322 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1323 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1325 InFlag = Chain.getValue(1);
1329 // From AMD64 ABI document:
1330 // For calls that may call functions that use varargs or stdargs
1331 // (prototype-less calls or calls to functions containing ellipsis (...) in
1332 // the declaration) %al is used as hidden argument to specify the number
1333 // of SSE registers used. The contents of %al do not need to match exactly
1334 // the number of registers, but must be an ubound on the number of SSE
1335 // registers used and is in the range 0 - 8 inclusive.
1337 // Count the number of XMM registers allocated.
1338 static const unsigned XMMArgRegs[] = {
1339 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1340 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1342 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1344 Chain = DAG.getCopyToReg(Chain, X86::AL,
1345 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1346 InFlag = Chain.getValue(1);
1349 // If the callee is a GlobalAddress node (quite common, every direct call is)
1350 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1351 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1352 // We should use extra load for direct calls to dllimported functions in
1354 if (getTargetMachine().getCodeModel() != CodeModel::Large
1355 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1356 getTargetMachine(), true))
1357 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1358 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1359 if (getTargetMachine().getCodeModel() != CodeModel::Large)
1360 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1362 // Returns a chain & a flag for retval copy to use.
1363 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1364 SmallVector<SDOperand, 8> Ops;
1365 Ops.push_back(Chain);
1366 Ops.push_back(Callee);
1368 // Add argument registers to the end of the list so that they are known live
1370 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1371 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1372 RegsToPass[i].second.getValueType()));
1375 Ops.push_back(InFlag);
1377 // FIXME: Do not generate X86ISD::TAILCALL for now.
1378 Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
1379 NodeTys, &Ops[0], Ops.size());
1380 InFlag = Chain.getValue(1);
1382 // Returns a flag for retval copy to use.
1383 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1385 Ops.push_back(Chain);
1386 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
1387 Ops.push_back(DAG.getConstant(0, getPointerTy()));
1388 Ops.push_back(InFlag);
1389 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1390 InFlag = Chain.getValue(1);
1392 // Handle result values, copying them out of physregs into vregs that we
1394 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1398 //===----------------------------------------------------------------------===//
1399 // Other Lowering Hooks
1400 //===----------------------------------------------------------------------===//
1403 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1404 if (ReturnAddrIndex == 0) {
1405 // Set up a frame object for the return address.
1406 MachineFunction &MF = DAG.getMachineFunction();
1407 if (Subtarget->is64Bit())
1408 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1410 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1413 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1418 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1419 /// specific condition code. It returns a false if it cannot do a direct
1420 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1422 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1423 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1424 SelectionDAG &DAG) {
1425 X86CC = X86::COND_INVALID;
1427 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1428 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1429 // X > -1 -> X == 0, jump !sign.
1430 RHS = DAG.getConstant(0, RHS.getValueType());
1431 X86CC = X86::COND_NS;
1433 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1434 // X < 0 -> X == 0, jump on sign.
1435 X86CC = X86::COND_S;
1440 switch (SetCCOpcode) {
1442 case ISD::SETEQ: X86CC = X86::COND_E; break;
1443 case ISD::SETGT: X86CC = X86::COND_G; break;
1444 case ISD::SETGE: X86CC = X86::COND_GE; break;
1445 case ISD::SETLT: X86CC = X86::COND_L; break;
1446 case ISD::SETLE: X86CC = X86::COND_LE; break;
1447 case ISD::SETNE: X86CC = X86::COND_NE; break;
1448 case ISD::SETULT: X86CC = X86::COND_B; break;
1449 case ISD::SETUGT: X86CC = X86::COND_A; break;
1450 case ISD::SETULE: X86CC = X86::COND_BE; break;
1451 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1454 // On a floating point condition, the flags are set as follows:
1456 // 0 | 0 | 0 | X > Y
1457 // 0 | 0 | 1 | X < Y
1458 // 1 | 0 | 0 | X == Y
1459 // 1 | 1 | 1 | unordered
1461 switch (SetCCOpcode) {
1464 case ISD::SETEQ: X86CC = X86::COND_E; break;
1465 case ISD::SETOLT: Flip = true; // Fallthrough
1467 case ISD::SETGT: X86CC = X86::COND_A; break;
1468 case ISD::SETOLE: Flip = true; // Fallthrough
1470 case ISD::SETGE: X86CC = X86::COND_AE; break;
1471 case ISD::SETUGT: Flip = true; // Fallthrough
1473 case ISD::SETLT: X86CC = X86::COND_B; break;
1474 case ISD::SETUGE: Flip = true; // Fallthrough
1476 case ISD::SETLE: X86CC = X86::COND_BE; break;
1478 case ISD::SETNE: X86CC = X86::COND_NE; break;
1479 case ISD::SETUO: X86CC = X86::COND_P; break;
1480 case ISD::SETO: X86CC = X86::COND_NP; break;
1483 std::swap(LHS, RHS);
1486 return X86CC != X86::COND_INVALID;
1489 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1490 /// code. Current x86 isa includes the following FP cmov instructions:
1491 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1492 static bool hasFPCMov(unsigned X86CC) {
1508 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1509 /// true if Op is undef or if its value falls within the specified range (L, H].
1510 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1511 if (Op.getOpcode() == ISD::UNDEF)
1514 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1515 return (Val >= Low && Val < Hi);
1518 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1519 /// true if Op is undef or if its value equal to the specified value.
1520 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1521 if (Op.getOpcode() == ISD::UNDEF)
1523 return cast<ConstantSDNode>(Op)->getValue() == Val;
1526 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1527 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1528 bool X86::isPSHUFDMask(SDNode *N) {
1529 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1531 if (N->getNumOperands() != 4)
1534 // Check if the value doesn't reference the second vector.
1535 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1536 SDOperand Arg = N->getOperand(i);
1537 if (Arg.getOpcode() == ISD::UNDEF) continue;
1538 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1539 if (cast<ConstantSDNode>(Arg)->getValue() >= 4)
1546 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1547 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1548 bool X86::isPSHUFHWMask(SDNode *N) {
1549 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1551 if (N->getNumOperands() != 8)
1554 // Lower quadword copied in order.
1555 for (unsigned i = 0; i != 4; ++i) {
1556 SDOperand Arg = N->getOperand(i);
1557 if (Arg.getOpcode() == ISD::UNDEF) continue;
1558 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1559 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1563 // Upper quadword shuffled.
1564 for (unsigned i = 4; i != 8; ++i) {
1565 SDOperand Arg = N->getOperand(i);
1566 if (Arg.getOpcode() == ISD::UNDEF) continue;
1567 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1568 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1569 if (Val < 4 || Val > 7)
1576 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1577 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1578 bool X86::isPSHUFLWMask(SDNode *N) {
1579 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1581 if (N->getNumOperands() != 8)
1584 // Upper quadword copied in order.
1585 for (unsigned i = 4; i != 8; ++i)
1586 if (!isUndefOrEqual(N->getOperand(i), i))
1589 // Lower quadword shuffled.
1590 for (unsigned i = 0; i != 4; ++i)
1591 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1597 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1598 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1599 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1600 if (NumElems != 2 && NumElems != 4) return false;
1602 unsigned Half = NumElems / 2;
1603 for (unsigned i = 0; i < Half; ++i)
1604 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1606 for (unsigned i = Half; i < NumElems; ++i)
1607 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1613 bool X86::isSHUFPMask(SDNode *N) {
1614 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1615 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1618 /// isCommutedSHUFP - Returns true if the shuffle mask is except
1619 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1620 /// half elements to come from vector 1 (which would equal the dest.) and
1621 /// the upper half to come from vector 2.
1622 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1623 if (NumOps != 2 && NumOps != 4) return false;
1625 unsigned Half = NumOps / 2;
1626 for (unsigned i = 0; i < Half; ++i)
1627 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1629 for (unsigned i = Half; i < NumOps; ++i)
1630 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1635 static bool isCommutedSHUFP(SDNode *N) {
1636 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1637 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1640 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1641 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1642 bool X86::isMOVHLPSMask(SDNode *N) {
1643 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1645 if (N->getNumOperands() != 4)
1648 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1649 return isUndefOrEqual(N->getOperand(0), 6) &&
1650 isUndefOrEqual(N->getOperand(1), 7) &&
1651 isUndefOrEqual(N->getOperand(2), 2) &&
1652 isUndefOrEqual(N->getOperand(3), 3);
1655 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1656 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1658 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1659 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1661 if (N->getNumOperands() != 4)
1664 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1665 return isUndefOrEqual(N->getOperand(0), 2) &&
1666 isUndefOrEqual(N->getOperand(1), 3) &&
1667 isUndefOrEqual(N->getOperand(2), 2) &&
1668 isUndefOrEqual(N->getOperand(3), 3);
1671 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1672 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1673 bool X86::isMOVLPMask(SDNode *N) {
1674 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1676 unsigned NumElems = N->getNumOperands();
1677 if (NumElems != 2 && NumElems != 4)
1680 for (unsigned i = 0; i < NumElems/2; ++i)
1681 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1684 for (unsigned i = NumElems/2; i < NumElems; ++i)
1685 if (!isUndefOrEqual(N->getOperand(i), i))
1691 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1692 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1694 bool X86::isMOVHPMask(SDNode *N) {
1695 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1697 unsigned NumElems = N->getNumOperands();
1698 if (NumElems != 2 && NumElems != 4)
1701 for (unsigned i = 0; i < NumElems/2; ++i)
1702 if (!isUndefOrEqual(N->getOperand(i), i))
1705 for (unsigned i = 0; i < NumElems/2; ++i) {
1706 SDOperand Arg = N->getOperand(i + NumElems/2);
1707 if (!isUndefOrEqual(Arg, i + NumElems))
1714 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1715 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1716 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1717 bool V2IsSplat = false) {
1718 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1721 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1722 SDOperand BitI = Elts[i];
1723 SDOperand BitI1 = Elts[i+1];
1724 if (!isUndefOrEqual(BitI, j))
1727 if (isUndefOrEqual(BitI1, NumElts))
1730 if (!isUndefOrEqual(BitI1, j + NumElts))
1738 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
1739 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1740 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1743 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
1744 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
1745 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
1746 bool V2IsSplat = false) {
1747 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1750 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
1751 SDOperand BitI = Elts[i];
1752 SDOperand BitI1 = Elts[i+1];
1753 if (!isUndefOrEqual(BitI, j + NumElts/2))
1756 if (isUndefOrEqual(BitI1, NumElts))
1759 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
1767 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
1768 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1769 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
1772 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
1773 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
1775 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
1776 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1778 unsigned NumElems = N->getNumOperands();
1779 if (NumElems != 4 && NumElems != 8 && NumElems != 16)
1782 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
1783 SDOperand BitI = N->getOperand(i);
1784 SDOperand BitI1 = N->getOperand(i+1);
1786 if (!isUndefOrEqual(BitI, j))
1788 if (!isUndefOrEqual(BitI1, j))
1795 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
1796 /// specifies a shuffle of elements that is suitable for input to MOVSS,
1797 /// MOVSD, and MOVD, i.e. setting the lowest element.
1798 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
1799 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
1802 if (!isUndefOrEqual(Elts[0], NumElts))
1805 for (unsigned i = 1; i < NumElts; ++i) {
1806 if (!isUndefOrEqual(Elts[i], i))
1813 bool X86::isMOVLMask(SDNode *N) {
1814 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1815 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
1818 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
1819 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
1820 /// element of vector 2 and the other elements to come from vector 1 in order.
1821 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
1822 bool V2IsSplat = false,
1823 bool V2IsUndef = false) {
1824 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
1827 if (!isUndefOrEqual(Ops[0], 0))
1830 for (unsigned i = 1; i < NumOps; ++i) {
1831 SDOperand Arg = Ops[i];
1832 if (!(isUndefOrEqual(Arg, i+NumOps) ||
1833 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
1834 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
1841 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
1842 bool V2IsUndef = false) {
1843 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1844 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
1845 V2IsSplat, V2IsUndef);
1848 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1849 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
1850 bool X86::isMOVSHDUPMask(SDNode *N) {
1851 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1853 if (N->getNumOperands() != 4)
1856 // Expect 1, 1, 3, 3
1857 for (unsigned i = 0; i < 2; ++i) {
1858 SDOperand Arg = N->getOperand(i);
1859 if (Arg.getOpcode() == ISD::UNDEF) continue;
1860 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1861 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1862 if (Val != 1) return false;
1866 for (unsigned i = 2; i < 4; ++i) {
1867 SDOperand Arg = N->getOperand(i);
1868 if (Arg.getOpcode() == ISD::UNDEF) continue;
1869 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1870 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1871 if (Val != 3) return false;
1875 // Don't use movshdup if it can be done with a shufps.
1879 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
1880 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
1881 bool X86::isMOVSLDUPMask(SDNode *N) {
1882 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1884 if (N->getNumOperands() != 4)
1887 // Expect 0, 0, 2, 2
1888 for (unsigned i = 0; i < 2; ++i) {
1889 SDOperand Arg = N->getOperand(i);
1890 if (Arg.getOpcode() == ISD::UNDEF) continue;
1891 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1892 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1893 if (Val != 0) return false;
1897 for (unsigned i = 2; i < 4; ++i) {
1898 SDOperand Arg = N->getOperand(i);
1899 if (Arg.getOpcode() == ISD::UNDEF) continue;
1900 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1901 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1902 if (Val != 2) return false;
1906 // Don't use movshdup if it can be done with a shufps.
1910 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
1911 /// a splat of a single element.
1912 static bool isSplatMask(SDNode *N) {
1913 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1915 // This is a splat operation if each element of the permute is the same, and
1916 // if the value doesn't reference the second vector.
1917 unsigned NumElems = N->getNumOperands();
1918 SDOperand ElementBase;
1920 for (; i != NumElems; ++i) {
1921 SDOperand Elt = N->getOperand(i);
1922 if (isa<ConstantSDNode>(Elt)) {
1928 if (!ElementBase.Val)
1931 for (; i != NumElems; ++i) {
1932 SDOperand Arg = N->getOperand(i);
1933 if (Arg.getOpcode() == ISD::UNDEF) continue;
1934 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1935 if (Arg != ElementBase) return false;
1938 // Make sure it is a splat of the first vector operand.
1939 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
1942 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
1943 /// a splat of a single element and it's a 2 or 4 element mask.
1944 bool X86::isSplatMask(SDNode *N) {
1945 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1947 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
1948 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
1950 return ::isSplatMask(N);
1953 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
1954 /// specifies a splat of zero element.
1955 bool X86::isSplatLoMask(SDNode *N) {
1956 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1958 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
1959 if (!isUndefOrEqual(N->getOperand(i), 0))
1964 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
1965 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
1967 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
1968 unsigned NumOperands = N->getNumOperands();
1969 unsigned Shift = (NumOperands == 4) ? 2 : 1;
1971 for (unsigned i = 0; i < NumOperands; ++i) {
1973 SDOperand Arg = N->getOperand(NumOperands-i-1);
1974 if (Arg.getOpcode() != ISD::UNDEF)
1975 Val = cast<ConstantSDNode>(Arg)->getValue();
1976 if (Val >= NumOperands) Val -= NumOperands;
1978 if (i != NumOperands - 1)
1985 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
1986 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
1988 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
1990 // 8 nodes, but we only care about the last 4.
1991 for (unsigned i = 7; i >= 4; --i) {
1993 SDOperand Arg = N->getOperand(i);
1994 if (Arg.getOpcode() != ISD::UNDEF)
1995 Val = cast<ConstantSDNode>(Arg)->getValue();
2004 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2005 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2007 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2009 // 8 nodes, but we only care about the first 4.
2010 for (int i = 3; i >= 0; --i) {
2012 SDOperand Arg = N->getOperand(i);
2013 if (Arg.getOpcode() != ISD::UNDEF)
2014 Val = cast<ConstantSDNode>(Arg)->getValue();
2023 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2024 /// specifies a 8 element shuffle that can be broken into a pair of
2025 /// PSHUFHW and PSHUFLW.
2026 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2027 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2029 if (N->getNumOperands() != 8)
2032 // Lower quadword shuffled.
2033 for (unsigned i = 0; i != 4; ++i) {
2034 SDOperand Arg = N->getOperand(i);
2035 if (Arg.getOpcode() == ISD::UNDEF) continue;
2036 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2037 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2042 // Upper quadword shuffled.
2043 for (unsigned i = 4; i != 8; ++i) {
2044 SDOperand Arg = N->getOperand(i);
2045 if (Arg.getOpcode() == ISD::UNDEF) continue;
2046 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2047 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2048 if (Val < 4 || Val > 7)
2055 /// CommuteVectorShuffle - Swap vector_shuffle operandsas well as
2056 /// values in ther permute mask.
2057 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2058 SDOperand &V2, SDOperand &Mask,
2059 SelectionDAG &DAG) {
2060 MVT::ValueType VT = Op.getValueType();
2061 MVT::ValueType MaskVT = Mask.getValueType();
2062 MVT::ValueType EltVT = MVT::getVectorBaseType(MaskVT);
2063 unsigned NumElems = Mask.getNumOperands();
2064 SmallVector<SDOperand, 8> MaskVec;
2066 for (unsigned i = 0; i != NumElems; ++i) {
2067 SDOperand Arg = Mask.getOperand(i);
2068 if (Arg.getOpcode() == ISD::UNDEF) {
2069 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2072 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2073 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2075 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2077 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2081 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2082 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2085 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2086 /// match movhlps. The lower half elements should come from upper half of
2087 /// V1 (and in order), and the upper half elements should come from the upper
2088 /// half of V2 (and in order).
2089 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2090 unsigned NumElems = Mask->getNumOperands();
2093 for (unsigned i = 0, e = 2; i != e; ++i)
2094 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2096 for (unsigned i = 2; i != 4; ++i)
2097 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2102 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2103 /// is promoted to a vector.
2104 static inline bool isScalarLoadToVector(SDNode *N) {
2105 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2106 N = N->getOperand(0).Val;
2107 return ISD::isNON_EXTLoad(N);
2112 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2113 /// match movlp{s|d}. The lower half elements should come from lower half of
2114 /// V1 (and in order), and the upper half elements should come from the upper
2115 /// half of V2 (and in order). And since V1 will become the source of the
2116 /// MOVLP, it must be either a vector load or a scalar load to vector.
2117 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2118 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2120 // Is V2 is a vector load, don't do this transformation. We will try to use
2121 // load folding shufps op.
2122 if (ISD::isNON_EXTLoad(V2))
2125 unsigned NumElems = Mask->getNumOperands();
2126 if (NumElems != 2 && NumElems != 4)
2128 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2129 if (!isUndefOrEqual(Mask->getOperand(i), i))
2131 for (unsigned i = NumElems/2; i != NumElems; ++i)
2132 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2137 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2139 static bool isSplatVector(SDNode *N) {
2140 if (N->getOpcode() != ISD::BUILD_VECTOR)
2143 SDOperand SplatValue = N->getOperand(0);
2144 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2145 if (N->getOperand(i) != SplatValue)
2150 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2152 static bool isUndefShuffle(SDNode *N) {
2153 if (N->getOpcode() != ISD::BUILD_VECTOR)
2156 SDOperand V1 = N->getOperand(0);
2157 SDOperand V2 = N->getOperand(1);
2158 SDOperand Mask = N->getOperand(2);
2159 unsigned NumElems = Mask.getNumOperands();
2160 for (unsigned i = 0; i != NumElems; ++i) {
2161 SDOperand Arg = Mask.getOperand(i);
2162 if (Arg.getOpcode() != ISD::UNDEF) {
2163 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2164 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2166 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2173 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2174 /// that point to V2 points to its first element.
2175 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2176 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2178 bool Changed = false;
2179 SmallVector<SDOperand, 8> MaskVec;
2180 unsigned NumElems = Mask.getNumOperands();
2181 for (unsigned i = 0; i != NumElems; ++i) {
2182 SDOperand Arg = Mask.getOperand(i);
2183 if (Arg.getOpcode() != ISD::UNDEF) {
2184 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2185 if (Val > NumElems) {
2186 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2190 MaskVec.push_back(Arg);
2194 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2195 &MaskVec[0], MaskVec.size());
2199 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2200 /// operation of specified width.
2201 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2202 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2203 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2205 SmallVector<SDOperand, 8> MaskVec;
2206 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2207 for (unsigned i = 1; i != NumElems; ++i)
2208 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2209 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2212 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2213 /// of specified width.
2214 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2215 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2216 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2217 SmallVector<SDOperand, 8> MaskVec;
2218 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2219 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2220 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2222 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2225 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2226 /// of specified width.
2227 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2228 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2229 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2230 unsigned Half = NumElems/2;
2231 SmallVector<SDOperand, 8> MaskVec;
2232 for (unsigned i = 0; i != Half; ++i) {
2233 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2234 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2236 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2239 /// getZeroVector - Returns a vector of specified type with all zero elements.
2241 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2242 assert(MVT::isVector(VT) && "Expected a vector type");
2243 unsigned NumElems = getVectorNumElements(VT);
2244 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2245 bool isFP = MVT::isFloatingPoint(EVT);
2246 SDOperand Zero = isFP ? DAG.getConstantFP(0.0, EVT) : DAG.getConstant(0, EVT);
2247 SmallVector<SDOperand, 8> ZeroVec(NumElems, Zero);
2248 return DAG.getNode(ISD::BUILD_VECTOR, VT, &ZeroVec[0], ZeroVec.size());
2251 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2253 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2254 SDOperand V1 = Op.getOperand(0);
2255 SDOperand Mask = Op.getOperand(2);
2256 MVT::ValueType VT = Op.getValueType();
2257 unsigned NumElems = Mask.getNumOperands();
2258 Mask = getUnpacklMask(NumElems, DAG);
2259 while (NumElems != 4) {
2260 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2263 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2265 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2266 Mask = getZeroVector(MaskVT, DAG);
2267 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2268 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2269 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2272 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2274 static inline bool isZeroNode(SDOperand Elt) {
2275 return ((isa<ConstantSDNode>(Elt) &&
2276 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2277 (isa<ConstantFPSDNode>(Elt) &&
2278 cast<ConstantFPSDNode>(Elt)->isExactlyValue(0.0)));
2281 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2282 /// vector and zero or undef vector.
2283 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2284 unsigned NumElems, unsigned Idx,
2285 bool isZero, SelectionDAG &DAG) {
2286 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2287 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2288 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2289 SDOperand Zero = DAG.getConstant(0, EVT);
2290 SmallVector<SDOperand, 8> MaskVec(NumElems, Zero);
2291 MaskVec[Idx] = DAG.getConstant(NumElems, EVT);
2292 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2293 &MaskVec[0], MaskVec.size());
2294 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2297 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2299 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2300 unsigned NumNonZero, unsigned NumZero,
2301 SelectionDAG &DAG, TargetLowering &TLI) {
2307 for (unsigned i = 0; i < 16; ++i) {
2308 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2309 if (ThisIsNonZero && First) {
2311 V = getZeroVector(MVT::v8i16, DAG);
2313 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2318 SDOperand ThisElt(0, 0), LastElt(0, 0);
2319 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2320 if (LastIsNonZero) {
2321 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2323 if (ThisIsNonZero) {
2324 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2325 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2326 ThisElt, DAG.getConstant(8, MVT::i8));
2328 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2333 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2334 DAG.getConstant(i/2, TLI.getPointerTy()));
2338 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2341 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2343 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2344 unsigned NumNonZero, unsigned NumZero,
2345 SelectionDAG &DAG, TargetLowering &TLI) {
2351 for (unsigned i = 0; i < 8; ++i) {
2352 bool isNonZero = (NonZeros & (1 << i)) != 0;
2356 V = getZeroVector(MVT::v8i16, DAG);
2358 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2361 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2362 DAG.getConstant(i, TLI.getPointerTy()));
2370 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2371 // All zero's are handled with pxor.
2372 if (ISD::isBuildVectorAllZeros(Op.Val))
2375 // All one's are handled with pcmpeqd.
2376 if (ISD::isBuildVectorAllOnes(Op.Val))
2379 MVT::ValueType VT = Op.getValueType();
2380 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
2381 unsigned EVTBits = MVT::getSizeInBits(EVT);
2383 unsigned NumElems = Op.getNumOperands();
2384 unsigned NumZero = 0;
2385 unsigned NumNonZero = 0;
2386 unsigned NonZeros = 0;
2387 std::set<SDOperand> Values;
2388 for (unsigned i = 0; i < NumElems; ++i) {
2389 SDOperand Elt = Op.getOperand(i);
2390 if (Elt.getOpcode() != ISD::UNDEF) {
2392 if (isZeroNode(Elt))
2395 NonZeros |= (1 << i);
2401 if (NumNonZero == 0)
2402 // Must be a mix of zero and undef. Return a zero vector.
2403 return getZeroVector(VT, DAG);
2405 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2406 if (Values.size() == 1)
2409 // Special case for single non-zero element.
2410 if (NumNonZero == 1) {
2411 unsigned Idx = CountTrailingZeros_32(NonZeros);
2412 SDOperand Item = Op.getOperand(Idx);
2413 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2415 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2416 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2419 if (EVTBits == 32) {
2420 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2421 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2423 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2424 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2425 SmallVector<SDOperand, 8> MaskVec;
2426 for (unsigned i = 0; i < NumElems; i++)
2427 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2428 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2429 &MaskVec[0], MaskVec.size());
2430 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2431 DAG.getNode(ISD::UNDEF, VT), Mask);
2435 // Let legalizer expand 2-wide build_vector's.
2439 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2440 if (EVTBits == 8 && NumElems == 16) {
2441 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2443 if (V.Val) return V;
2446 if (EVTBits == 16 && NumElems == 8) {
2447 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2449 if (V.Val) return V;
2452 // If element VT is == 32 bits, turn it into a number of shuffles.
2453 SmallVector<SDOperand, 8> V;
2455 if (NumElems == 4 && NumZero > 0) {
2456 for (unsigned i = 0; i < 4; ++i) {
2457 bool isZero = !(NonZeros & (1 << i));
2459 V[i] = getZeroVector(VT, DAG);
2461 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2464 for (unsigned i = 0; i < 2; ++i) {
2465 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2468 V[i] = V[i*2]; // Must be a zero vector.
2471 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2472 getMOVLMask(NumElems, DAG));
2475 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2476 getMOVLMask(NumElems, DAG));
2479 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2480 getUnpacklMask(NumElems, DAG));
2485 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2486 // clears the upper bits.
2487 // FIXME: we can do the same for v4f32 case when we know both parts of
2488 // the lower half come from scalar_to_vector (loadf32). We should do
2489 // that in post legalizer dag combiner with target specific hooks.
2490 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2492 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2493 MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
2494 SmallVector<SDOperand, 8> MaskVec;
2495 bool Reverse = (NonZeros & 0x3) == 2;
2496 for (unsigned i = 0; i < 2; ++i)
2498 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2500 MaskVec.push_back(DAG.getConstant(i, EVT));
2501 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2502 for (unsigned i = 0; i < 2; ++i)
2504 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2506 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2507 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2508 &MaskVec[0], MaskVec.size());
2509 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2512 if (Values.size() > 2) {
2513 // Expand into a number of unpckl*.
2515 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2516 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2517 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2518 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2519 for (unsigned i = 0; i < NumElems; ++i)
2520 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2522 while (NumElems != 0) {
2523 for (unsigned i = 0; i < NumElems; ++i)
2524 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2535 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2536 SDOperand V1 = Op.getOperand(0);
2537 SDOperand V2 = Op.getOperand(1);
2538 SDOperand PermMask = Op.getOperand(2);
2539 MVT::ValueType VT = Op.getValueType();
2540 unsigned NumElems = PermMask.getNumOperands();
2541 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
2542 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
2543 bool V1IsSplat = false;
2544 bool V2IsSplat = false;
2546 if (isUndefShuffle(Op.Val))
2547 return DAG.getNode(ISD::UNDEF, VT);
2549 if (isSplatMask(PermMask.Val)) {
2550 if (NumElems <= 4) return Op;
2551 // Promote it to a v4i32 splat.
2552 return PromoteSplat(Op, DAG);
2555 if (X86::isMOVLMask(PermMask.Val))
2556 return (V1IsUndef) ? V2 : Op;
2558 if (X86::isMOVSHDUPMask(PermMask.Val) ||
2559 X86::isMOVSLDUPMask(PermMask.Val) ||
2560 X86::isMOVHLPSMask(PermMask.Val) ||
2561 X86::isMOVHPMask(PermMask.Val) ||
2562 X86::isMOVLPMask(PermMask.Val))
2565 if (ShouldXformToMOVHLPS(PermMask.Val) ||
2566 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
2567 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2569 bool Commuted = false;
2570 V1IsSplat = isSplatVector(V1.Val);
2571 V2IsSplat = isSplatVector(V2.Val);
2572 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
2573 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2574 std::swap(V1IsSplat, V2IsSplat);
2575 std::swap(V1IsUndef, V2IsUndef);
2579 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
2580 if (V2IsUndef) return V1;
2581 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2583 // V2 is a splat, so the mask may be malformed. That is, it may point
2584 // to any V2 element. The instruction selectior won't like this. Get
2585 // a corrected mask and commute to form a proper MOVS{S|D}.
2586 SDOperand NewMask = getMOVLMask(NumElems, DAG);
2587 if (NewMask.Val != PermMask.Val)
2588 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2593 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2594 X86::isUNPCKLMask(PermMask.Val) ||
2595 X86::isUNPCKHMask(PermMask.Val))
2599 // Normalize mask so all entries that point to V2 points to its first
2600 // element then try to match unpck{h|l} again. If match, return a
2601 // new vector_shuffle with the corrected mask.
2602 SDOperand NewMask = NormalizeMask(PermMask, DAG);
2603 if (NewMask.Val != PermMask.Val) {
2604 if (X86::isUNPCKLMask(PermMask.Val, true)) {
2605 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
2606 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2607 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
2608 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
2609 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
2614 // Normalize the node to match x86 shuffle ops if needed
2615 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
2616 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2619 // Commute is back and try unpck* again.
2620 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
2621 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
2622 X86::isUNPCKLMask(PermMask.Val) ||
2623 X86::isUNPCKHMask(PermMask.Val))
2627 // If VT is integer, try PSHUF* first, then SHUFP*.
2628 if (MVT::isInteger(VT)) {
2629 if (X86::isPSHUFDMask(PermMask.Val) ||
2630 X86::isPSHUFHWMask(PermMask.Val) ||
2631 X86::isPSHUFLWMask(PermMask.Val)) {
2632 if (V2.getOpcode() != ISD::UNDEF)
2633 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2634 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2638 if (X86::isSHUFPMask(PermMask.Val))
2641 // Handle v8i16 shuffle high / low shuffle node pair.
2642 if (VT == MVT::v8i16 && isPSHUFHW_PSHUFLWMask(PermMask.Val)) {
2643 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2644 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2645 SmallVector<SDOperand, 8> MaskVec;
2646 for (unsigned i = 0; i != 4; ++i)
2647 MaskVec.push_back(PermMask.getOperand(i));
2648 for (unsigned i = 4; i != 8; ++i)
2649 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2650 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2651 &MaskVec[0], MaskVec.size());
2652 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2654 for (unsigned i = 0; i != 4; ++i)
2655 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2656 for (unsigned i = 4; i != 8; ++i)
2657 MaskVec.push_back(PermMask.getOperand(i));
2658 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
2659 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2662 // Floating point cases in the other order.
2663 if (X86::isSHUFPMask(PermMask.Val))
2665 if (X86::isPSHUFDMask(PermMask.Val) ||
2666 X86::isPSHUFHWMask(PermMask.Val) ||
2667 X86::isPSHUFLWMask(PermMask.Val)) {
2668 if (V2.getOpcode() != ISD::UNDEF)
2669 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
2670 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
2675 if (NumElems == 4) {
2676 MVT::ValueType MaskVT = PermMask.getValueType();
2677 MVT::ValueType MaskEVT = MVT::getVectorBaseType(MaskVT);
2678 SmallVector<std::pair<int, int>, 8> Locs;
2679 Locs.reserve(NumElems);
2680 SmallVector<SDOperand, 8> Mask1(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2681 SmallVector<SDOperand, 8> Mask2(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2684 // If no more than two elements come from either vector. This can be
2685 // implemented with two shuffles. First shuffle gather the elements.
2686 // The second shuffle, which takes the first shuffle as both of its
2687 // vector operands, put the elements into the right order.
2688 for (unsigned i = 0; i != NumElems; ++i) {
2689 SDOperand Elt = PermMask.getOperand(i);
2690 if (Elt.getOpcode() == ISD::UNDEF) {
2691 Locs[i] = std::make_pair(-1, -1);
2693 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
2694 if (Val < NumElems) {
2695 Locs[i] = std::make_pair(0, NumLo);
2699 Locs[i] = std::make_pair(1, NumHi);
2700 if (2+NumHi < NumElems)
2701 Mask1[2+NumHi] = Elt;
2706 if (NumLo <= 2 && NumHi <= 2) {
2707 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2708 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2709 &Mask1[0], Mask1.size()));
2710 for (unsigned i = 0; i != NumElems; ++i) {
2711 if (Locs[i].first == -1)
2714 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
2715 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
2716 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
2720 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
2721 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2722 &Mask2[0], Mask2.size()));
2725 // Break it into (shuffle shuffle_hi, shuffle_lo).
2727 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2728 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
2729 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
2730 unsigned MaskIdx = 0;
2732 unsigned HiIdx = NumElems/2;
2733 for (unsigned i = 0; i != NumElems; ++i) {
2734 if (i == NumElems/2) {
2740 SDOperand Elt = PermMask.getOperand(i);
2741 if (Elt.getOpcode() == ISD::UNDEF) {
2742 Locs[i] = std::make_pair(-1, -1);
2743 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
2744 Locs[i] = std::make_pair(MaskIdx, LoIdx);
2745 (*MaskPtr)[LoIdx] = Elt;
2748 Locs[i] = std::make_pair(MaskIdx, HiIdx);
2749 (*MaskPtr)[HiIdx] = Elt;
2754 SDOperand LoShuffle =
2755 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2756 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2757 &LoMask[0], LoMask.size()));
2758 SDOperand HiShuffle =
2759 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
2760 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2761 &HiMask[0], HiMask.size()));
2762 SmallVector<SDOperand, 8> MaskOps;
2763 for (unsigned i = 0; i != NumElems; ++i) {
2764 if (Locs[i].first == -1) {
2765 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
2767 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
2768 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
2771 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
2772 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2773 &MaskOps[0], MaskOps.size()));
2780 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2781 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2784 MVT::ValueType VT = Op.getValueType();
2785 // TODO: handle v16i8.
2786 if (MVT::getSizeInBits(VT) == 16) {
2787 // Transform it so it match pextrw which produces a 32-bit result.
2788 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
2789 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
2790 Op.getOperand(0), Op.getOperand(1));
2791 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
2792 DAG.getValueType(VT));
2793 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
2794 } else if (MVT::getSizeInBits(VT) == 32) {
2795 SDOperand Vec = Op.getOperand(0);
2796 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2799 // SHUFPS the element to the lowest double word, then movss.
2800 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2801 SmallVector<SDOperand, 8> IdxVec;
2802 IdxVec.push_back(DAG.getConstant(Idx, MVT::getVectorBaseType(MaskVT)));
2803 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2804 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2805 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2806 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2807 &IdxVec[0], IdxVec.size());
2808 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2809 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2810 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2811 DAG.getConstant(0, getPointerTy()));
2812 } else if (MVT::getSizeInBits(VT) == 64) {
2813 SDOperand Vec = Op.getOperand(0);
2814 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
2818 // UNPCKHPD the element to the lowest double word, then movsd.
2819 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
2820 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
2821 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2822 SmallVector<SDOperand, 8> IdxVec;
2823 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
2824 IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
2825 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2826 &IdxVec[0], IdxVec.size());
2827 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
2828 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
2829 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
2830 DAG.getConstant(0, getPointerTy()));
2837 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
2838 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
2839 // as its second argument.
2840 MVT::ValueType VT = Op.getValueType();
2841 MVT::ValueType BaseVT = MVT::getVectorBaseType(VT);
2842 SDOperand N0 = Op.getOperand(0);
2843 SDOperand N1 = Op.getOperand(1);
2844 SDOperand N2 = Op.getOperand(2);
2845 if (MVT::getSizeInBits(BaseVT) == 16) {
2846 if (N1.getValueType() != MVT::i32)
2847 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
2848 if (N2.getValueType() != MVT::i32)
2849 N2 = DAG.getConstant(cast<ConstantSDNode>(N2)->getValue(), MVT::i32);
2850 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
2851 } else if (MVT::getSizeInBits(BaseVT) == 32) {
2852 unsigned Idx = cast<ConstantSDNode>(N2)->getValue();
2855 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, N1);
2856 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
2857 MVT::ValueType BaseVT = MVT::getVectorBaseType(MaskVT);
2858 SmallVector<SDOperand, 8> MaskVec;
2859 MaskVec.push_back(DAG.getConstant(4, BaseVT));
2860 for (unsigned i = 1; i <= 3; ++i)
2861 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2862 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
2863 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2864 &MaskVec[0], MaskVec.size()));
2866 // Use two pinsrw instructions to insert a 32 bit value.
2868 if (MVT::isFloatingPoint(N1.getValueType())) {
2869 if (ISD::isNON_EXTLoad(N1.Val)) {
2870 // Just load directly from f32mem to GR32.
2871 LoadSDNode *LD = cast<LoadSDNode>(N1);
2872 N1 = DAG.getLoad(MVT::i32, LD->getChain(), LD->getBasePtr(),
2873 LD->getSrcValue(), LD->getSrcValueOffset());
2875 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4f32, N1);
2876 N1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, N1);
2877 N1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32, N1,
2878 DAG.getConstant(0, getPointerTy()));
2881 N0 = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, N0);
2882 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2883 DAG.getConstant(Idx, getPointerTy()));
2884 N1 = DAG.getNode(ISD::SRL, MVT::i32, N1, DAG.getConstant(16, MVT::i8));
2885 N0 = DAG.getNode(X86ISD::PINSRW, MVT::v8i16, N0, N1,
2886 DAG.getConstant(Idx+1, getPointerTy()));
2887 return DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2895 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2896 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
2897 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
2900 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2901 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
2902 // one of the above mentioned nodes. It has to be wrapped because otherwise
2903 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2904 // be used to form addressing mode. These wrapped nodes will be selected
2907 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
2908 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2909 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
2911 CP->getAlignment());
2912 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2913 // With PIC, the address is actually $g + Offset.
2914 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2915 !Subtarget->isPICStyleRIPRel()) {
2916 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2917 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2925 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
2926 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2927 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
2928 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
2929 // With PIC, the address is actually $g + Offset.
2930 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2931 !Subtarget->isPICStyleRIPRel()) {
2932 Result = DAG.getNode(ISD::ADD, getPointerTy(),
2933 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
2937 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
2938 // load the value at address GV, not the value of GV itself. This means that
2939 // the GlobalAddress must be in the base or index register of the address, not
2940 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
2941 // The same applies for external symbols during PIC codegen
2942 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
2943 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
2948 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2950 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
2951 const MVT::ValueType PtrVT) {
2953 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
2954 DAG.getNode(X86ISD::GlobalBaseReg,
2956 InFlag = Chain.getValue(1);
2958 // emit leal symbol@TLSGD(,%ebx,1), %eax
2959 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
2960 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
2961 GA->getValueType(0),
2963 SDOperand Ops[] = { Chain, TGA, InFlag };
2964 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
2965 InFlag = Result.getValue(2);
2966 Chain = Result.getValue(1);
2968 // call ___tls_get_addr. This function receives its argument in
2969 // the register EAX.
2970 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
2971 InFlag = Chain.getValue(1);
2973 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2974 SDOperand Ops1[] = { Chain,
2975 DAG.getTargetExternalSymbol("___tls_get_addr",
2977 DAG.getRegister(X86::EAX, PtrVT),
2978 DAG.getRegister(X86::EBX, PtrVT),
2980 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
2981 InFlag = Chain.getValue(1);
2983 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
2986 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
2987 // "local exec" model.
2989 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
2990 const MVT::ValueType PtrVT) {
2991 // Get the Thread Pointer
2992 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
2993 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
2995 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
2996 GA->getValueType(0),
2998 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
2999 // The address of the thread local variable is the add of the thread
3000 // pointer with the offset of the variable.
3001 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3005 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3006 // TODO: implement the "local dynamic" model
3007 // TODO: implement the "initial exec"model for pic executables
3008 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3009 "TLS not implemented for non-ELF and 64-bit targets");
3010 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3011 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3012 // otherwise use the "Local Exec"TLS Model
3013 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3014 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3016 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3020 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3021 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3022 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3023 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3024 // With PIC, the address is actually $g + Offset.
3025 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3026 !Subtarget->isPICStyleRIPRel()) {
3027 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3028 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3035 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3036 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3037 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3038 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3039 // With PIC, the address is actually $g + Offset.
3040 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3041 !Subtarget->isPICStyleRIPRel()) {
3042 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3043 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3050 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3051 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3052 "Not an i64 shift!");
3053 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3054 SDOperand ShOpLo = Op.getOperand(0);
3055 SDOperand ShOpHi = Op.getOperand(1);
3056 SDOperand ShAmt = Op.getOperand(2);
3057 SDOperand Tmp1 = isSRA ?
3058 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3059 DAG.getConstant(0, MVT::i32);
3061 SDOperand Tmp2, Tmp3;
3062 if (Op.getOpcode() == ISD::SHL_PARTS) {
3063 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3064 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3066 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3067 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3070 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3071 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3072 DAG.getConstant(32, MVT::i8));
3073 SDOperand COps[]={DAG.getEntryNode(), AndNode, DAG.getConstant(0, MVT::i8)};
3074 SDOperand InFlag = DAG.getNode(X86ISD::CMP, VTs, 2, COps, 3).getValue(1);
3077 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3079 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3080 SmallVector<SDOperand, 4> Ops;
3081 if (Op.getOpcode() == ISD::SHL_PARTS) {
3082 Ops.push_back(Tmp2);
3083 Ops.push_back(Tmp3);
3085 Ops.push_back(InFlag);
3086 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3087 InFlag = Hi.getValue(1);
3090 Ops.push_back(Tmp3);
3091 Ops.push_back(Tmp1);
3093 Ops.push_back(InFlag);
3094 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3096 Ops.push_back(Tmp2);
3097 Ops.push_back(Tmp3);
3099 Ops.push_back(InFlag);
3100 Lo = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3101 InFlag = Lo.getValue(1);
3104 Ops.push_back(Tmp3);
3105 Ops.push_back(Tmp1);
3107 Ops.push_back(InFlag);
3108 Hi = DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3111 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3115 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3118 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3119 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3120 Op.getOperand(0).getValueType() >= MVT::i16 &&
3121 "Unknown SINT_TO_FP to lower!");
3124 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3125 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3126 MachineFunction &MF = DAG.getMachineFunction();
3127 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3128 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3129 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3130 StackSlot, NULL, 0);
3135 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3137 Tys = DAG.getVTList(MVT::f64, MVT::Other);
3138 SmallVector<SDOperand, 8> Ops;
3139 Ops.push_back(Chain);
3140 Ops.push_back(StackSlot);
3141 Ops.push_back(DAG.getValueType(SrcVT));
3142 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3143 Tys, &Ops[0], Ops.size());
3146 Chain = Result.getValue(1);
3147 SDOperand InFlag = Result.getValue(2);
3149 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3150 // shouldn't be necessary except that RFP cannot be live across
3151 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3152 MachineFunction &MF = DAG.getMachineFunction();
3153 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3154 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3155 Tys = DAG.getVTList(MVT::Other);
3156 SmallVector<SDOperand, 8> Ops;
3157 Ops.push_back(Chain);
3158 Ops.push_back(Result);
3159 Ops.push_back(StackSlot);
3160 Ops.push_back(DAG.getValueType(Op.getValueType()));
3161 Ops.push_back(InFlag);
3162 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3163 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3169 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3170 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3171 "Unknown FP_TO_SINT to lower!");
3172 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3174 MachineFunction &MF = DAG.getMachineFunction();
3175 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3176 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3177 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3180 switch (Op.getValueType()) {
3181 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3182 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3183 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3184 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3187 SDOperand Chain = DAG.getEntryNode();
3188 SDOperand Value = Op.getOperand(0);
3190 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3191 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3192 SDVTList Tys = DAG.getVTList(MVT::f64, MVT::Other);
3194 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3196 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3197 Chain = Value.getValue(1);
3198 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3199 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3202 // Build the FP_TO_INT*_IN_MEM
3203 SDOperand Ops[] = { Chain, Value, StackSlot };
3204 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3207 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3210 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3211 MVT::ValueType VT = Op.getValueType();
3212 const Type *OpNTy = MVT::getTypeForValueType(VT);
3213 std::vector<Constant*> CV;
3214 if (VT == MVT::f64) {
3215 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
3216 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3218 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
3219 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3220 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3221 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3223 Constant *CS = ConstantStruct::get(CV);
3224 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3225 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3226 SmallVector<SDOperand, 3> Ops;
3227 Ops.push_back(DAG.getEntryNode());
3228 Ops.push_back(CPIdx);
3229 Ops.push_back(DAG.getSrcValue(NULL));
3230 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3231 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
3234 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
3235 MVT::ValueType VT = Op.getValueType();
3236 const Type *OpNTy = MVT::getTypeForValueType(VT);
3237 std::vector<Constant*> CV;
3238 if (VT == MVT::f64) {
3239 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
3240 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3242 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
3243 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3244 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3245 CV.push_back(ConstantFP::get(OpNTy, 0.0));
3247 Constant *CS = ConstantStruct::get(CV);
3248 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3249 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
3250 SmallVector<SDOperand, 3> Ops;
3251 Ops.push_back(DAG.getEntryNode());
3252 Ops.push_back(CPIdx);
3253 Ops.push_back(DAG.getSrcValue(NULL));
3254 SDOperand Mask = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3255 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
3258 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
3259 SDOperand Op0 = Op.getOperand(0);
3260 SDOperand Op1 = Op.getOperand(1);
3261 MVT::ValueType VT = Op.getValueType();
3262 MVT::ValueType SrcVT = Op1.getValueType();
3263 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
3265 // If second operand is smaller, extend it first.
3266 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
3267 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
3271 // First get the sign bit of second operand.
3272 std::vector<Constant*> CV;
3273 if (SrcVT == MVT::f64) {
3274 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(1ULL << 63)));
3275 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3277 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(1U << 31)));
3278 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3279 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3280 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3282 Constant *CS = ConstantStruct::get(CV);
3283 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3284 SDVTList Tys = DAG.getVTList(SrcVT, MVT::Other);
3285 SmallVector<SDOperand, 3> Ops;
3286 Ops.push_back(DAG.getEntryNode());
3287 Ops.push_back(CPIdx);
3288 Ops.push_back(DAG.getSrcValue(NULL));
3289 SDOperand Mask1 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3290 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
3292 // Shift sign bit right or left if the two operands have different types.
3293 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
3294 // Op0 is MVT::f32, Op1 is MVT::f64.
3295 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
3296 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
3297 DAG.getConstant(32, MVT::i32));
3298 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
3299 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
3300 DAG.getConstant(0, getPointerTy()));
3303 // Clear first operand sign bit.
3305 if (VT == MVT::f64) {
3306 CV.push_back(ConstantFP::get(SrcTy, BitsToDouble(~(1ULL << 63))));
3307 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3309 CV.push_back(ConstantFP::get(SrcTy, BitsToFloat(~(1U << 31))));
3310 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3311 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3312 CV.push_back(ConstantFP::get(SrcTy, 0.0));
3314 CS = ConstantStruct::get(CV);
3315 CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
3316 Tys = DAG.getVTList(VT, MVT::Other);
3318 Ops.push_back(DAG.getEntryNode());
3319 Ops.push_back(CPIdx);
3320 Ops.push_back(DAG.getSrcValue(NULL));
3321 SDOperand Mask2 = DAG.getNode(X86ISD::LOAD_PACK, Tys, &Ops[0], Ops.size());
3322 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
3324 // Or the value with the sign bit.
3325 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
3328 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG,
3330 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
3332 SDOperand Op0 = Op.getOperand(0);
3333 SDOperand Op1 = Op.getOperand(1);
3334 SDOperand CC = Op.getOperand(2);
3335 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3336 const MVT::ValueType *VTs1 = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3337 const MVT::ValueType *VTs2 = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
3338 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
3341 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
3343 SDOperand Ops1[] = { Chain, Op0, Op1 };
3344 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, Ops1, 3).getValue(1);
3345 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
3346 return DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3349 assert(isFP && "Illegal integer SetCC!");
3351 SDOperand COps[] = { Chain, Op0, Op1 };
3352 Cond = DAG.getNode(X86ISD::CMP, VTs1, 2, COps, 3).getValue(1);
3354 switch (SetCCOpcode) {
3355 default: assert(false && "Illegal floating point SetCC!");
3356 case ISD::SETOEQ: { // !PF & ZF
3357 SDOperand Ops1[] = { DAG.getConstant(X86::COND_NP, MVT::i8), Cond };
3358 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3359 SDOperand Ops2[] = { DAG.getConstant(X86::COND_E, MVT::i8),
3361 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3362 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
3364 case ISD::SETUNE: { // PF | !ZF
3365 SDOperand Ops1[] = { DAG.getConstant(X86::COND_P, MVT::i8), Cond };
3366 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops1, 2);
3367 SDOperand Ops2[] = { DAG.getConstant(X86::COND_NE, MVT::i8),
3369 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, VTs2, 2, Ops2, 2);
3370 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
3375 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
3376 bool addTest = true;
3377 SDOperand Chain = DAG.getEntryNode();
3378 SDOperand Cond = Op.getOperand(0);
3380 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3382 if (Cond.getOpcode() == ISD::SETCC)
3383 Cond = LowerSETCC(Cond, DAG, Chain);
3385 if (Cond.getOpcode() == X86ISD::SETCC) {
3386 CC = Cond.getOperand(0);
3388 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3389 // (since flag operand cannot be shared). Use it as the condition setting
3390 // operand in place of the X86ISD::SETCC.
3391 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3392 // to use a test instead of duplicating the X86ISD::CMP (for register
3393 // pressure reason)?
3394 SDOperand Cmp = Cond.getOperand(1);
3395 unsigned Opc = Cmp.getOpcode();
3396 bool IllegalFPCMov = !X86ScalarSSE &&
3397 MVT::isFloatingPoint(Op.getValueType()) &&
3398 !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
3399 if ((Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) &&
3401 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3402 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3408 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3409 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3410 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3413 VTs = DAG.getNodeValueTypes(Op.getValueType(), MVT::Flag);
3414 SmallVector<SDOperand, 4> Ops;
3415 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
3416 // condition is true.
3417 Ops.push_back(Op.getOperand(2));
3418 Ops.push_back(Op.getOperand(1));
3420 Ops.push_back(Cond.getValue(1));
3421 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
3424 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
3425 bool addTest = true;
3426 SDOperand Chain = Op.getOperand(0);
3427 SDOperand Cond = Op.getOperand(1);
3428 SDOperand Dest = Op.getOperand(2);
3430 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3432 if (Cond.getOpcode() == ISD::SETCC)
3433 Cond = LowerSETCC(Cond, DAG, Chain);
3435 if (Cond.getOpcode() == X86ISD::SETCC) {
3436 CC = Cond.getOperand(0);
3438 // If condition flag is set by a X86ISD::CMP, then make a copy of it
3439 // (since flag operand cannot be shared). Use it as the condition setting
3440 // operand in place of the X86ISD::SETCC.
3441 // If the X86ISD::SETCC has more than one use, then perhaps it's better
3442 // to use a test instead of duplicating the X86ISD::CMP (for register
3443 // pressure reason)?
3444 SDOperand Cmp = Cond.getOperand(1);
3445 unsigned Opc = Cmp.getOpcode();
3446 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) {
3447 SDOperand Ops[] = { Chain, Cmp.getOperand(1), Cmp.getOperand(2) };
3448 Cond = DAG.getNode(Opc, VTs, 2, Ops, 3);
3454 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3455 SDOperand Ops[] = { Chain, Cond, DAG.getConstant(0, MVT::i8) };
3456 Cond = DAG.getNode(X86ISD::CMP, VTs, 2, Ops, 3);
3458 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
3459 Cond, Op.getOperand(2), CC, Cond.getValue(1));
3462 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
3463 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3465 if (Subtarget->is64Bit())
3466 return LowerX86_64CCCCallTo(Op, DAG, CallingConv);
3468 switch (CallingConv) {
3470 assert(0 && "Unsupported calling convention");
3471 case CallingConv::Fast:
3472 // TODO: Implement fastcc
3474 case CallingConv::C:
3475 case CallingConv::X86_StdCall:
3476 return LowerCCCCallTo(Op, DAG, CallingConv);
3477 case CallingConv::X86_FastCall:
3478 return LowerFastCCCallTo(Op, DAG, CallingConv);
3483 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
3484 // Calls to _alloca is needed to probe the stack when allocating more than 4k
3485 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
3486 // that the guard pages used by the OS virtual memory manager are allocated in
3487 // correct sequence.
3488 SDOperand X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
3489 SelectionDAG &DAG) {
3490 assert(Subtarget->isTargetCygMing() &&
3491 "This should be used only on Cygwin/Mingw targets");
3494 SDOperand Chain = Op.getOperand(0);
3495 SDOperand Size = Op.getOperand(1);
3496 // FIXME: Ensure alignment here
3498 TargetLowering::ArgListTy Args;
3499 TargetLowering::ArgListEntry Entry;
3500 MVT::ValueType IntPtr = getPointerTy();
3501 MVT::ValueType SPTy = (Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
3502 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3505 Entry.Ty = IntPtrTy;
3506 Entry.isInReg = true; // Should pass in EAX
3507 Args.push_back(Entry);
3508 std::pair<SDOperand, SDOperand> CallResult =
3509 LowerCallTo(Chain, IntPtrTy, false, false, CallingConv::C, false,
3510 DAG.getExternalSymbol("_alloca", IntPtr), Args, DAG);
3512 SDOperand SP = DAG.getCopyFromReg(CallResult.second, X86StackPtr, SPTy);
3514 std::vector<MVT::ValueType> Tys;
3515 Tys.push_back(SPTy);
3516 Tys.push_back(MVT::Other);
3517 SDOperand Ops[2] = { SP, CallResult.second };
3518 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
3522 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
3523 MachineFunction &MF = DAG.getMachineFunction();
3524 const Function* Fn = MF.getFunction();
3525 if (Fn->hasExternalLinkage() &&
3526 Subtarget->isTargetCygMing() &&
3527 Fn->getName() == "main")
3528 MF.getInfo<X86MachineFunctionInfo>()->setForceFramePointer(true);
3530 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3531 if (Subtarget->is64Bit())
3532 return LowerX86_64CCCArguments(Op, DAG);
3536 assert(0 && "Unsupported calling convention");
3537 case CallingConv::Fast:
3538 // TODO: implement fastcc.
3541 case CallingConv::C:
3542 return LowerCCCArguments(Op, DAG);
3543 case CallingConv::X86_StdCall:
3544 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(StdCall);
3545 return LowerCCCArguments(Op, DAG, true);
3546 case CallingConv::X86_FastCall:
3547 MF.getInfo<X86MachineFunctionInfo>()->setDecorationStyle(FastCall);
3548 return LowerFastCCArguments(Op, DAG);
3552 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
3553 SDOperand InFlag(0, 0);
3554 SDOperand Chain = Op.getOperand(0);
3556 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3557 if (Align == 0) Align = 1;
3559 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3560 // If not DWORD aligned, call memset if size is less than the threshold.
3561 // It knows how to align to the right boundary first.
3562 if ((Align & 3) != 0 ||
3563 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3564 MVT::ValueType IntPtr = getPointerTy();
3565 const Type *IntPtrTy = getTargetData()->getIntPtrType();
3566 TargetLowering::ArgListTy Args;
3567 TargetLowering::ArgListEntry Entry;
3568 Entry.Node = Op.getOperand(1);
3569 Entry.Ty = IntPtrTy;
3570 Args.push_back(Entry);
3571 // Extend the unsigned i8 argument to be an int value for the call.
3572 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
3573 Entry.Ty = IntPtrTy;
3574 Args.push_back(Entry);
3575 Entry.Node = Op.getOperand(3);
3576 Args.push_back(Entry);
3577 std::pair<SDOperand,SDOperand> CallResult =
3578 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3579 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
3580 return CallResult.second;
3585 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
3586 unsigned BytesLeft = 0;
3587 bool TwoRepStos = false;
3590 uint64_t Val = ValC->getValue() & 255;
3592 // If the value is a constant, then we can potentially use larger sets.
3593 switch (Align & 3) {
3594 case 2: // WORD aligned
3597 Val = (Val << 8) | Val;
3599 case 0: // DWORD aligned
3602 Val = (Val << 8) | Val;
3603 Val = (Val << 16) | Val;
3604 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
3607 Val = (Val << 32) | Val;
3610 default: // Byte aligned
3613 Count = Op.getOperand(3);
3617 if (AVT > MVT::i8) {
3619 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3620 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3621 BytesLeft = I->getValue() % UBytes;
3623 assert(AVT >= MVT::i32 &&
3624 "Do not use rep;stos if not at least DWORD aligned");
3625 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3626 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3631 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
3633 InFlag = Chain.getValue(1);
3636 Count = Op.getOperand(3);
3637 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
3638 InFlag = Chain.getValue(1);
3641 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3643 InFlag = Chain.getValue(1);
3644 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3645 Op.getOperand(1), InFlag);
3646 InFlag = Chain.getValue(1);
3648 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3649 SmallVector<SDOperand, 8> Ops;
3650 Ops.push_back(Chain);
3651 Ops.push_back(DAG.getValueType(AVT));
3652 Ops.push_back(InFlag);
3653 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3656 InFlag = Chain.getValue(1);
3657 Count = Op.getOperand(3);
3658 MVT::ValueType CVT = Count.getValueType();
3659 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3660 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3661 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3663 InFlag = Chain.getValue(1);
3664 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3666 Ops.push_back(Chain);
3667 Ops.push_back(DAG.getValueType(MVT::i8));
3668 Ops.push_back(InFlag);
3669 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
3670 } else if (BytesLeft) {
3671 // Issue stores for the last 1 - 7 bytes.
3673 unsigned Val = ValC->getValue() & 255;
3674 unsigned Offset = I->getValue() - BytesLeft;
3675 SDOperand DstAddr = Op.getOperand(1);
3676 MVT::ValueType AddrVT = DstAddr.getValueType();
3677 if (BytesLeft >= 4) {
3678 Val = (Val << 8) | Val;
3679 Val = (Val << 16) | Val;
3680 Value = DAG.getConstant(Val, MVT::i32);
3681 Chain = DAG.getStore(Chain, Value,
3682 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3683 DAG.getConstant(Offset, AddrVT)),
3688 if (BytesLeft >= 2) {
3689 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
3690 Chain = DAG.getStore(Chain, Value,
3691 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3692 DAG.getConstant(Offset, AddrVT)),
3697 if (BytesLeft == 1) {
3698 Value = DAG.getConstant(Val, MVT::i8);
3699 Chain = DAG.getStore(Chain, Value,
3700 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
3701 DAG.getConstant(Offset, AddrVT)),
3709 SDOperand X86TargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) {
3710 SDOperand Chain = Op.getOperand(0);
3712 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
3713 if (Align == 0) Align = 1;
3715 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
3716 // If not DWORD aligned, call memcpy if size is less than the threshold.
3717 // It knows how to align to the right boundary first.
3718 if ((Align & 3) != 0 ||
3719 (I && I->getValue() < Subtarget->getMinRepStrSizeThreshold())) {
3720 MVT::ValueType IntPtr = getPointerTy();
3721 TargetLowering::ArgListTy Args;
3722 TargetLowering::ArgListEntry Entry;
3723 Entry.Ty = getTargetData()->getIntPtrType();
3724 Entry.Node = Op.getOperand(1); Args.push_back(Entry);
3725 Entry.Node = Op.getOperand(2); Args.push_back(Entry);
3726 Entry.Node = Op.getOperand(3); Args.push_back(Entry);
3727 std::pair<SDOperand,SDOperand> CallResult =
3728 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
3729 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
3730 return CallResult.second;
3735 unsigned BytesLeft = 0;
3736 bool TwoRepMovs = false;
3737 switch (Align & 3) {
3738 case 2: // WORD aligned
3741 case 0: // DWORD aligned
3743 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
3746 default: // Byte aligned
3748 Count = Op.getOperand(3);
3752 if (AVT > MVT::i8) {
3754 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
3755 Count = DAG.getConstant(I->getValue() / UBytes, getPointerTy());
3756 BytesLeft = I->getValue() % UBytes;
3758 assert(AVT >= MVT::i32 &&
3759 "Do not use rep;movs if not at least DWORD aligned");
3760 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
3761 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
3766 SDOperand InFlag(0, 0);
3767 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
3769 InFlag = Chain.getValue(1);
3770 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
3771 Op.getOperand(1), InFlag);
3772 InFlag = Chain.getValue(1);
3773 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
3774 Op.getOperand(2), InFlag);
3775 InFlag = Chain.getValue(1);
3777 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3778 SmallVector<SDOperand, 8> Ops;
3779 Ops.push_back(Chain);
3780 Ops.push_back(DAG.getValueType(AVT));
3781 Ops.push_back(InFlag);
3782 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3785 InFlag = Chain.getValue(1);
3786 Count = Op.getOperand(3);
3787 MVT::ValueType CVT = Count.getValueType();
3788 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
3789 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
3790 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
3792 InFlag = Chain.getValue(1);
3793 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3795 Ops.push_back(Chain);
3796 Ops.push_back(DAG.getValueType(MVT::i8));
3797 Ops.push_back(InFlag);
3798 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
3799 } else if (BytesLeft) {
3800 // Issue loads and stores for the last 1 - 7 bytes.
3801 unsigned Offset = I->getValue() - BytesLeft;
3802 SDOperand DstAddr = Op.getOperand(1);
3803 MVT::ValueType DstVT = DstAddr.getValueType();
3804 SDOperand SrcAddr = Op.getOperand(2);
3805 MVT::ValueType SrcVT = SrcAddr.getValueType();
3807 if (BytesLeft >= 4) {
3808 Value = DAG.getLoad(MVT::i32, Chain,
3809 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3810 DAG.getConstant(Offset, SrcVT)),
3812 Chain = Value.getValue(1);
3813 Chain = DAG.getStore(Chain, Value,
3814 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3815 DAG.getConstant(Offset, DstVT)),
3820 if (BytesLeft >= 2) {
3821 Value = DAG.getLoad(MVT::i16, Chain,
3822 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3823 DAG.getConstant(Offset, SrcVT)),
3825 Chain = Value.getValue(1);
3826 Chain = DAG.getStore(Chain, Value,
3827 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3828 DAG.getConstant(Offset, DstVT)),
3834 if (BytesLeft == 1) {
3835 Value = DAG.getLoad(MVT::i8, Chain,
3836 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
3837 DAG.getConstant(Offset, SrcVT)),
3839 Chain = Value.getValue(1);
3840 Chain = DAG.getStore(Chain, Value,
3841 DAG.getNode(ISD::ADD, DstVT, DstAddr,
3842 DAG.getConstant(Offset, DstVT)),
3851 X86TargetLowering::LowerREADCYCLCECOUNTER(SDOperand Op, SelectionDAG &DAG) {
3852 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
3853 SDOperand TheOp = Op.getOperand(0);
3854 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheOp, 1);
3855 if (Subtarget->is64Bit()) {
3856 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
3857 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::RDX,
3858 MVT::i64, Copy1.getValue(2));
3859 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, Copy2,
3860 DAG.getConstant(32, MVT::i8));
3862 DAG.getNode(ISD::OR, MVT::i64, Copy1, Tmp), Copy2.getValue(1)
3865 Tys = DAG.getVTList(MVT::i64, MVT::Other);
3866 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
3869 SDOperand Copy1 = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
3870 SDOperand Copy2 = DAG.getCopyFromReg(Copy1.getValue(1), X86::EDX,
3871 MVT::i32, Copy1.getValue(2));
3872 SDOperand Ops[] = { Copy1, Copy2, Copy2.getValue(1) };
3873 Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
3874 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 3);
3877 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
3878 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
3880 if (!Subtarget->is64Bit()) {
3881 // vastart just stores the address of the VarArgsFrameIndex slot into the
3882 // memory location argument.
3883 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
3884 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
3889 // gp_offset (0 - 6 * 8)
3890 // fp_offset (48 - 48 + 8 * 16)
3891 // overflow_arg_area (point to parameters coming in memory).
3893 SmallVector<SDOperand, 8> MemOps;
3894 SDOperand FIN = Op.getOperand(1);
3896 SDOperand Store = DAG.getStore(Op.getOperand(0),
3897 DAG.getConstant(VarArgsGPOffset, MVT::i32),
3898 FIN, SV->getValue(), SV->getOffset());
3899 MemOps.push_back(Store);
3902 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3903 DAG.getConstant(4, getPointerTy()));
3904 Store = DAG.getStore(Op.getOperand(0),
3905 DAG.getConstant(VarArgsFPOffset, MVT::i32),
3906 FIN, SV->getValue(), SV->getOffset());
3907 MemOps.push_back(Store);
3909 // Store ptr to overflow_arg_area
3910 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3911 DAG.getConstant(4, getPointerTy()));
3912 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
3913 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
3915 MemOps.push_back(Store);
3917 // Store ptr to reg_save_area.
3918 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
3919 DAG.getConstant(8, getPointerTy()));
3920 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
3921 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
3923 MemOps.push_back(Store);
3924 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
3927 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
3928 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
3929 SDOperand Chain = Op.getOperand(0);
3930 SDOperand DstPtr = Op.getOperand(1);
3931 SDOperand SrcPtr = Op.getOperand(2);
3932 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
3933 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
3935 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
3936 SrcSV->getValue(), SrcSV->getOffset());
3937 Chain = SrcPtr.getValue(1);
3938 for (unsigned i = 0; i < 3; ++i) {
3939 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
3940 SrcSV->getValue(), SrcSV->getOffset());
3941 Chain = Val.getValue(1);
3942 Chain = DAG.getStore(Chain, Val, DstPtr,
3943 DstSV->getValue(), DstSV->getOffset());
3946 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
3947 DAG.getConstant(8, getPointerTy()));
3948 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
3949 DAG.getConstant(8, getPointerTy()));
3955 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
3956 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
3958 default: return SDOperand(); // Don't custom lower most intrinsics.
3959 // Comparison intrinsics.
3960 case Intrinsic::x86_sse_comieq_ss:
3961 case Intrinsic::x86_sse_comilt_ss:
3962 case Intrinsic::x86_sse_comile_ss:
3963 case Intrinsic::x86_sse_comigt_ss:
3964 case Intrinsic::x86_sse_comige_ss:
3965 case Intrinsic::x86_sse_comineq_ss:
3966 case Intrinsic::x86_sse_ucomieq_ss:
3967 case Intrinsic::x86_sse_ucomilt_ss:
3968 case Intrinsic::x86_sse_ucomile_ss:
3969 case Intrinsic::x86_sse_ucomigt_ss:
3970 case Intrinsic::x86_sse_ucomige_ss:
3971 case Intrinsic::x86_sse_ucomineq_ss:
3972 case Intrinsic::x86_sse2_comieq_sd:
3973 case Intrinsic::x86_sse2_comilt_sd:
3974 case Intrinsic::x86_sse2_comile_sd:
3975 case Intrinsic::x86_sse2_comigt_sd:
3976 case Intrinsic::x86_sse2_comige_sd:
3977 case Intrinsic::x86_sse2_comineq_sd:
3978 case Intrinsic::x86_sse2_ucomieq_sd:
3979 case Intrinsic::x86_sse2_ucomilt_sd:
3980 case Intrinsic::x86_sse2_ucomile_sd:
3981 case Intrinsic::x86_sse2_ucomigt_sd:
3982 case Intrinsic::x86_sse2_ucomige_sd:
3983 case Intrinsic::x86_sse2_ucomineq_sd: {
3985 ISD::CondCode CC = ISD::SETCC_INVALID;
3988 case Intrinsic::x86_sse_comieq_ss:
3989 case Intrinsic::x86_sse2_comieq_sd:
3993 case Intrinsic::x86_sse_comilt_ss:
3994 case Intrinsic::x86_sse2_comilt_sd:
3998 case Intrinsic::x86_sse_comile_ss:
3999 case Intrinsic::x86_sse2_comile_sd:
4003 case Intrinsic::x86_sse_comigt_ss:
4004 case Intrinsic::x86_sse2_comigt_sd:
4008 case Intrinsic::x86_sse_comige_ss:
4009 case Intrinsic::x86_sse2_comige_sd:
4013 case Intrinsic::x86_sse_comineq_ss:
4014 case Intrinsic::x86_sse2_comineq_sd:
4018 case Intrinsic::x86_sse_ucomieq_ss:
4019 case Intrinsic::x86_sse2_ucomieq_sd:
4020 Opc = X86ISD::UCOMI;
4023 case Intrinsic::x86_sse_ucomilt_ss:
4024 case Intrinsic::x86_sse2_ucomilt_sd:
4025 Opc = X86ISD::UCOMI;
4028 case Intrinsic::x86_sse_ucomile_ss:
4029 case Intrinsic::x86_sse2_ucomile_sd:
4030 Opc = X86ISD::UCOMI;
4033 case Intrinsic::x86_sse_ucomigt_ss:
4034 case Intrinsic::x86_sse2_ucomigt_sd:
4035 Opc = X86ISD::UCOMI;
4038 case Intrinsic::x86_sse_ucomige_ss:
4039 case Intrinsic::x86_sse2_ucomige_sd:
4040 Opc = X86ISD::UCOMI;
4043 case Intrinsic::x86_sse_ucomineq_ss:
4044 case Intrinsic::x86_sse2_ucomineq_sd:
4045 Opc = X86ISD::UCOMI;
4051 SDOperand LHS = Op.getOperand(1);
4052 SDOperand RHS = Op.getOperand(2);
4053 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4055 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
4056 SDOperand Ops1[] = { DAG.getEntryNode(), LHS, RHS };
4057 SDOperand Cond = DAG.getNode(Opc, VTs, 2, Ops1, 3);
4058 VTs = DAG.getNodeValueTypes(MVT::i8, MVT::Flag);
4059 SDOperand Ops2[] = { DAG.getConstant(X86CC, MVT::i8), Cond };
4060 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, VTs, 2, Ops2, 2);
4061 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4066 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4067 // Depths > 0 not supported yet!
4068 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4071 // Just load the return address
4072 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4073 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4076 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4077 // Depths > 0 not supported yet!
4078 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4081 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4082 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4083 DAG.getConstant(4, getPointerTy()));
4086 /// LowerOperation - Provide custom lowering hooks for some operations.
4088 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
4089 switch (Op.getOpcode()) {
4090 default: assert(0 && "Should not custom lower this!");
4091 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4092 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4093 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4094 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
4095 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4096 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4097 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4098 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4099 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
4100 case ISD::SHL_PARTS:
4101 case ISD::SRA_PARTS:
4102 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
4103 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4104 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
4105 case ISD::FABS: return LowerFABS(Op, DAG);
4106 case ISD::FNEG: return LowerFNEG(Op, DAG);
4107 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4108 case ISD::SETCC: return LowerSETCC(Op, DAG, DAG.getEntryNode());
4109 case ISD::SELECT: return LowerSELECT(Op, DAG);
4110 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
4111 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4112 case ISD::CALL: return LowerCALL(Op, DAG);
4113 case ISD::RET: return LowerRET(Op, DAG);
4114 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
4115 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
4116 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
4117 case ISD::READCYCLECOUNTER: return LowerREADCYCLCECOUNTER(Op, DAG);
4118 case ISD::VASTART: return LowerVASTART(Op, DAG);
4119 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
4120 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4121 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4122 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4123 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
4128 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
4130 default: return NULL;
4131 case X86ISD::SHLD: return "X86ISD::SHLD";
4132 case X86ISD::SHRD: return "X86ISD::SHRD";
4133 case X86ISD::FAND: return "X86ISD::FAND";
4134 case X86ISD::FOR: return "X86ISD::FOR";
4135 case X86ISD::FXOR: return "X86ISD::FXOR";
4136 case X86ISD::FSRL: return "X86ISD::FSRL";
4137 case X86ISD::FILD: return "X86ISD::FILD";
4138 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
4139 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
4140 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
4141 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
4142 case X86ISD::FLD: return "X86ISD::FLD";
4143 case X86ISD::FST: return "X86ISD::FST";
4144 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
4145 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
4146 case X86ISD::CALL: return "X86ISD::CALL";
4147 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
4148 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
4149 case X86ISD::CMP: return "X86ISD::CMP";
4150 case X86ISD::COMI: return "X86ISD::COMI";
4151 case X86ISD::UCOMI: return "X86ISD::UCOMI";
4152 case X86ISD::SETCC: return "X86ISD::SETCC";
4153 case X86ISD::CMOV: return "X86ISD::CMOV";
4154 case X86ISD::BRCOND: return "X86ISD::BRCOND";
4155 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
4156 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
4157 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
4158 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
4159 case X86ISD::LOAD_UA: return "X86ISD::LOAD_UA";
4160 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
4161 case X86ISD::Wrapper: return "X86ISD::Wrapper";
4162 case X86ISD::S2VEC: return "X86ISD::S2VEC";
4163 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
4164 case X86ISD::PINSRW: return "X86ISD::PINSRW";
4165 case X86ISD::FMAX: return "X86ISD::FMAX";
4166 case X86ISD::FMIN: return "X86ISD::FMIN";
4167 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
4168 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
4172 // isLegalAddressingMode - Return true if the addressing mode represented
4173 // by AM is legal for this target, for a load/store of the specified type.
4174 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
4175 const Type *Ty) const {
4176 // X86 supports extremely general addressing modes.
4178 // X86 allows a sign-extended 32-bit immediate field as a displacement.
4179 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
4183 // X86-64 only supports addr of globals in small code model.
4184 if (Subtarget->is64Bit() &&
4185 getTargetMachine().getCodeModel() != CodeModel::Small)
4188 // We can only fold this if we don't need a load either.
4189 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
4199 // These scales always work.
4204 // These scales are formed with basereg+scalereg. Only accept if there is
4209 default: // Other stuff never works.
4217 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4218 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4219 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4220 /// are assumed to be legal.
4222 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
4223 // Only do shuffles on 128-bit vector types for now.
4224 if (MVT::getSizeInBits(VT) == 64) return false;
4225 return (Mask.Val->getNumOperands() <= 4 ||
4226 isSplatMask(Mask.Val) ||
4227 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
4228 X86::isUNPCKLMask(Mask.Val) ||
4229 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
4230 X86::isUNPCKHMask(Mask.Val));
4233 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
4235 SelectionDAG &DAG) const {
4236 unsigned NumElts = BVOps.size();
4237 // Only do shuffles on 128-bit vector types for now.
4238 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
4239 if (NumElts == 2) return true;
4241 return (isMOVLMask(&BVOps[0], 4) ||
4242 isCommutedMOVL(&BVOps[0], 4, true) ||
4243 isSHUFPMask(&BVOps[0], 4) ||
4244 isCommutedSHUFP(&BVOps[0], 4));
4249 //===----------------------------------------------------------------------===//
4250 // X86 Scheduler Hooks
4251 //===----------------------------------------------------------------------===//
4254 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
4255 MachineBasicBlock *BB) {
4256 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4257 switch (MI->getOpcode()) {
4258 default: assert(false && "Unexpected instr type to insert");
4259 case X86::CMOV_FR32:
4260 case X86::CMOV_FR64:
4261 case X86::CMOV_V4F32:
4262 case X86::CMOV_V2F64:
4263 case X86::CMOV_V2I64: {
4264 // To "insert" a SELECT_CC instruction, we actually have to insert the
4265 // diamond control-flow pattern. The incoming instruction knows the
4266 // destination vreg to set, the condition code register to branch on, the
4267 // true/false values to select between, and a branch opcode to use.
4268 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4269 ilist<MachineBasicBlock>::iterator It = BB;
4275 // cmpTY ccX, r1, r2
4277 // fallthrough --> copy0MBB
4278 MachineBasicBlock *thisMBB = BB;
4279 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
4280 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
4282 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
4283 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
4284 MachineFunction *F = BB->getParent();
4285 F->getBasicBlockList().insert(It, copy0MBB);
4286 F->getBasicBlockList().insert(It, sinkMBB);
4287 // Update machine-CFG edges by first adding all successors of the current
4288 // block to the new block which will contain the Phi node for the select.
4289 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
4290 e = BB->succ_end(); i != e; ++i)
4291 sinkMBB->addSuccessor(*i);
4292 // Next, remove all successors of the current block, and add the true
4293 // and fallthrough blocks as its successors.
4294 while(!BB->succ_empty())
4295 BB->removeSuccessor(BB->succ_begin());
4296 BB->addSuccessor(copy0MBB);
4297 BB->addSuccessor(sinkMBB);
4300 // %FalseValue = ...
4301 // # fallthrough to sinkMBB
4304 // Update machine-CFG edges
4305 BB->addSuccessor(sinkMBB);
4308 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4311 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
4312 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4313 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4315 delete MI; // The pseudo instruction is gone now.
4319 case X86::FP_TO_INT16_IN_MEM:
4320 case X86::FP_TO_INT32_IN_MEM:
4321 case X86::FP_TO_INT64_IN_MEM: {
4322 // Change the floating point control register to use "round towards zero"
4323 // mode when truncating to an integer value.
4324 MachineFunction *F = BB->getParent();
4325 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
4326 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
4328 // Load the old value of the high byte of the control word...
4330 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
4331 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
4333 // Set the high part to be round to zero...
4334 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
4337 // Reload the modified control word now...
4338 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4340 // Restore the memory image of control word to original value
4341 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
4344 // Get the X86 opcode to use.
4346 switch (MI->getOpcode()) {
4347 default: assert(0 && "illegal opcode!");
4348 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
4349 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
4350 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
4354 MachineOperand &Op = MI->getOperand(0);
4355 if (Op.isRegister()) {
4356 AM.BaseType = X86AddressMode::RegBase;
4357 AM.Base.Reg = Op.getReg();
4359 AM.BaseType = X86AddressMode::FrameIndexBase;
4360 AM.Base.FrameIndex = Op.getFrameIndex();
4362 Op = MI->getOperand(1);
4363 if (Op.isImmediate())
4364 AM.Scale = Op.getImm();
4365 Op = MI->getOperand(2);
4366 if (Op.isImmediate())
4367 AM.IndexReg = Op.getImm();
4368 Op = MI->getOperand(3);
4369 if (Op.isGlobalAddress()) {
4370 AM.GV = Op.getGlobal();
4372 AM.Disp = Op.getImm();
4374 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
4375 .addReg(MI->getOperand(4).getReg());
4377 // Reload the original control word now.
4378 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
4380 delete MI; // The pseudo instruction is gone now.
4386 //===----------------------------------------------------------------------===//
4387 // X86 Optimization Hooks
4388 //===----------------------------------------------------------------------===//
4390 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
4392 uint64_t &KnownZero,
4394 unsigned Depth) const {
4395 unsigned Opc = Op.getOpcode();
4396 assert((Opc >= ISD::BUILTIN_OP_END ||
4397 Opc == ISD::INTRINSIC_WO_CHAIN ||
4398 Opc == ISD::INTRINSIC_W_CHAIN ||
4399 Opc == ISD::INTRINSIC_VOID) &&
4400 "Should use MaskedValueIsZero if you don't know whether Op"
4401 " is a target node!");
4403 KnownZero = KnownOne = 0; // Don't know anything.
4407 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
4412 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4413 /// element of the result of the vector shuffle.
4414 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
4415 MVT::ValueType VT = N->getValueType(0);
4416 SDOperand PermMask = N->getOperand(2);
4417 unsigned NumElems = PermMask.getNumOperands();
4418 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
4420 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4422 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4423 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
4424 SDOperand Idx = PermMask.getOperand(i);
4425 if (Idx.getOpcode() == ISD::UNDEF)
4426 return DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(VT));
4427 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
4432 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
4433 /// node is a GlobalAddress + an offset.
4434 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
4435 unsigned Opc = N->getOpcode();
4436 if (Opc == X86ISD::Wrapper) {
4437 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
4438 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
4441 } else if (Opc == ISD::ADD) {
4442 SDOperand N1 = N->getOperand(0);
4443 SDOperand N2 = N->getOperand(1);
4444 if (isGAPlusOffset(N1.Val, GA, Offset)) {
4445 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
4447 Offset += V->getSignExtended();
4450 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
4451 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
4453 Offset += V->getSignExtended();
4461 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
4463 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
4464 MachineFrameInfo *MFI) {
4465 if (N->getOperand(0).Val != Base->getOperand(0).Val)
4468 SDOperand Loc = N->getOperand(1);
4469 SDOperand BaseLoc = Base->getOperand(1);
4470 if (Loc.getOpcode() == ISD::FrameIndex) {
4471 if (BaseLoc.getOpcode() != ISD::FrameIndex)
4473 int FI = dyn_cast<FrameIndexSDNode>(Loc)->getIndex();
4474 int BFI = dyn_cast<FrameIndexSDNode>(BaseLoc)->getIndex();
4475 int FS = MFI->getObjectSize(FI);
4476 int BFS = MFI->getObjectSize(BFI);
4477 if (FS != BFS || FS != Size) return false;
4478 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
4480 GlobalValue *GV1 = NULL;
4481 GlobalValue *GV2 = NULL;
4482 int64_t Offset1 = 0;
4483 int64_t Offset2 = 0;
4484 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
4485 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
4486 if (isGA1 && isGA2 && GV1 == GV2)
4487 return Offset1 == (Offset2 + Dist*Size);
4493 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
4494 const X86Subtarget *Subtarget) {
4497 if (isGAPlusOffset(Base, GV, Offset))
4498 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
4500 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
4501 int BFI = dyn_cast<FrameIndexSDNode>(Base)->getIndex();
4503 // Fixed objects do not specify alignment, however the offsets are known.
4504 return ((Subtarget->getStackAlignment() % 16) == 0 &&
4505 (MFI->getObjectOffset(BFI) % 16) == 0);
4507 return MFI->getObjectAlignment(BFI) >= 16;
4513 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
4514 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
4515 /// if the load addresses are consecutive, non-overlapping, and in the right
4517 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
4518 const X86Subtarget *Subtarget) {
4519 MachineFunction &MF = DAG.getMachineFunction();
4520 MachineFrameInfo *MFI = MF.getFrameInfo();
4521 MVT::ValueType VT = N->getValueType(0);
4522 MVT::ValueType EVT = MVT::getVectorBaseType(VT);
4523 SDOperand PermMask = N->getOperand(2);
4524 int NumElems = (int)PermMask.getNumOperands();
4525 SDNode *Base = NULL;
4526 for (int i = 0; i < NumElems; ++i) {
4527 SDOperand Idx = PermMask.getOperand(i);
4528 if (Idx.getOpcode() == ISD::UNDEF) {
4529 if (!Base) return SDOperand();
4532 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
4533 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
4537 else if (!isConsecutiveLoad(Arg.Val, Base,
4538 i, MVT::getSizeInBits(EVT)/8,MFI))
4543 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
4545 LoadSDNode *LD = cast<LoadSDNode>(Base);
4546 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
4547 LD->getSrcValueOffset());
4549 // Just use movups, it's shorter.
4550 SDVTList Tys = DAG.getVTList(MVT::v4f32, MVT::Other);
4551 SmallVector<SDOperand, 3> Ops;
4552 Ops.push_back(Base->getOperand(0));
4553 Ops.push_back(Base->getOperand(1));
4554 Ops.push_back(Base->getOperand(2));
4555 return DAG.getNode(ISD::BIT_CONVERT, VT,
4556 DAG.getNode(X86ISD::LOAD_UA, Tys, &Ops[0], Ops.size()));
4560 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
4561 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
4562 const X86Subtarget *Subtarget) {
4563 SDOperand Cond = N->getOperand(0);
4565 // If we have SSE[12] support, try to form min/max nodes.
4566 if (Subtarget->hasSSE2() &&
4567 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
4568 if (Cond.getOpcode() == ISD::SETCC) {
4569 // Get the LHS/RHS of the select.
4570 SDOperand LHS = N->getOperand(1);
4571 SDOperand RHS = N->getOperand(2);
4572 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4574 unsigned Opcode = 0;
4575 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
4578 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
4581 if (!UnsafeFPMath) break;
4583 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
4585 Opcode = X86ISD::FMIN;
4588 case ISD::SETOGT: // (X > Y) ? X : Y -> max
4591 if (!UnsafeFPMath) break;
4593 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
4595 Opcode = X86ISD::FMAX;
4598 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
4601 case ISD::SETOGT: // (X > Y) ? Y : X -> min
4604 if (!UnsafeFPMath) break;
4606 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
4608 Opcode = X86ISD::FMIN;
4611 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
4614 if (!UnsafeFPMath) break;
4616 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
4618 Opcode = X86ISD::FMAX;
4624 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
4633 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
4634 DAGCombinerInfo &DCI) const {
4635 SelectionDAG &DAG = DCI.DAG;
4636 switch (N->getOpcode()) {
4638 case ISD::VECTOR_SHUFFLE:
4639 return PerformShuffleCombine(N, DAG, Subtarget);
4641 return PerformSELECTCombine(N, DAG, Subtarget);
4647 //===----------------------------------------------------------------------===//
4648 // X86 Inline Assembly Support
4649 //===----------------------------------------------------------------------===//
4651 /// getConstraintType - Given a constraint letter, return the type of
4652 /// constraint it is for this target.
4653 X86TargetLowering::ConstraintType
4654 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
4655 if (Constraint.size() == 1) {
4656 switch (Constraint[0]) {
4665 return C_RegisterClass;
4670 return TargetLowering::getConstraintType(Constraint);
4673 /// isOperandValidForConstraint - Return the specified operand (possibly
4674 /// modified) if the specified SDOperand is valid for the specified target
4675 /// constraint letter, otherwise return null.
4676 SDOperand X86TargetLowering::
4677 isOperandValidForConstraint(SDOperand Op, char Constraint, SelectionDAG &DAG) {
4678 switch (Constraint) {
4681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4682 if (C->getValue() <= 31)
4685 return SDOperand(0,0);
4687 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4688 if (C->getValue() <= 255)
4691 return SDOperand(0,0);
4693 // Literal immediates are always ok.
4694 if (isa<ConstantSDNode>(Op)) return Op;
4696 // If we are in non-pic codegen mode, we allow the address of a global to
4697 // be used with 'i'.
4698 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
4699 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4700 return SDOperand(0, 0);
4702 if (GA->getOpcode() != ISD::TargetGlobalAddress)
4703 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4708 // Otherwise, not valid for this mode.
4709 return SDOperand(0, 0);
4711 return TargetLowering::isOperandValidForConstraint(Op, Constraint, DAG);
4714 std::vector<unsigned> X86TargetLowering::
4715 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4716 MVT::ValueType VT) const {
4717 if (Constraint.size() == 1) {
4718 // FIXME: not handling fp-stack yet!
4719 switch (Constraint[0]) { // GCC X86 Constraint Letters
4720 default: break; // Unknown constraint letter
4721 case 'A': // EAX/EDX
4722 if (VT == MVT::i32 || VT == MVT::i64)
4723 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
4725 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
4728 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
4729 else if (VT == MVT::i16)
4730 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
4731 else if (VT == MVT::i8)
4732 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::DL, 0);
4737 return std::vector<unsigned>();
4740 std::pair<unsigned, const TargetRegisterClass*>
4741 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4742 MVT::ValueType VT) const {
4743 // First, see if this is a constraint that directly corresponds to an LLVM
4745 if (Constraint.size() == 1) {
4746 // GCC Constraint Letters
4747 switch (Constraint[0]) {
4749 case 'r': // GENERAL_REGS
4750 case 'R': // LEGACY_REGS
4751 case 'l': // INDEX_REGS
4752 if (VT == MVT::i64 && Subtarget->is64Bit())
4753 return std::make_pair(0U, X86::GR64RegisterClass);
4755 return std::make_pair(0U, X86::GR32RegisterClass);
4756 else if (VT == MVT::i16)
4757 return std::make_pair(0U, X86::GR16RegisterClass);
4758 else if (VT == MVT::i8)
4759 return std::make_pair(0U, X86::GR8RegisterClass);
4761 case 'y': // MMX_REGS if MMX allowed.
4762 if (!Subtarget->hasMMX()) break;
4763 return std::make_pair(0U, X86::VR64RegisterClass);
4765 case 'Y': // SSE_REGS if SSE2 allowed
4766 if (!Subtarget->hasSSE2()) break;
4768 case 'x': // SSE_REGS if SSE1 allowed
4769 if (!Subtarget->hasSSE1()) break;
4773 // Scalar SSE types.
4776 return std::make_pair(0U, X86::FR32RegisterClass);
4779 return std::make_pair(0U, X86::FR64RegisterClass);
4788 return std::make_pair(0U, X86::VR128RegisterClass);
4794 // Use the default implementation in TargetLowering to convert the register
4795 // constraint into a member of a register class.
4796 std::pair<unsigned, const TargetRegisterClass*> Res;
4797 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4799 // Not found as a standard register?
4800 if (Res.second == 0) {
4801 // GCC calls "st(0)" just plain "st".
4802 if (StringsEqualNoCase("{st}", Constraint)) {
4803 Res.first = X86::ST0;
4804 Res.second = X86::RSTRegisterClass;
4810 // Otherwise, check to see if this is a register class of the wrong value
4811 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
4812 // turn into {ax},{dx}.
4813 if (Res.second->hasType(VT))
4814 return Res; // Correct type already, nothing to do.
4816 // All of the single-register GCC register classes map their values onto
4817 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
4818 // really want an 8-bit or 32-bit register, map to the appropriate register
4819 // class and return the appropriate register.
4820 if (Res.second != X86::GR16RegisterClass)
4823 if (VT == MVT::i8) {
4824 unsigned DestReg = 0;
4825 switch (Res.first) {
4827 case X86::AX: DestReg = X86::AL; break;
4828 case X86::DX: DestReg = X86::DL; break;
4829 case X86::CX: DestReg = X86::CL; break;
4830 case X86::BX: DestReg = X86::BL; break;
4833 Res.first = DestReg;
4834 Res.second = Res.second = X86::GR8RegisterClass;
4836 } else if (VT == MVT::i32) {
4837 unsigned DestReg = 0;
4838 switch (Res.first) {
4840 case X86::AX: DestReg = X86::EAX; break;
4841 case X86::DX: DestReg = X86::EDX; break;
4842 case X86::CX: DestReg = X86::ECX; break;
4843 case X86::BX: DestReg = X86::EBX; break;
4844 case X86::SI: DestReg = X86::ESI; break;
4845 case X86::DI: DestReg = X86::EDI; break;
4846 case X86::BP: DestReg = X86::EBP; break;
4847 case X86::SP: DestReg = X86::ESP; break;
4850 Res.first = DestReg;
4851 Res.second = Res.second = X86::GR32RegisterClass;
4853 } else if (VT == MVT::i64) {
4854 unsigned DestReg = 0;
4855 switch (Res.first) {
4857 case X86::AX: DestReg = X86::RAX; break;
4858 case X86::DX: DestReg = X86::RDX; break;
4859 case X86::CX: DestReg = X86::RCX; break;
4860 case X86::BX: DestReg = X86::RBX; break;
4861 case X86::SI: DestReg = X86::RSI; break;
4862 case X86::DI: DestReg = X86::RDI; break;
4863 case X86::BP: DestReg = X86::RBP; break;
4864 case X86::SP: DestReg = X86::RSP; break;
4867 Res.first = DestReg;
4868 Res.second = Res.second = X86::GR64RegisterClass;