1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
29 #include "llvm/CodeGen/CallingConvLower.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallSet.h"
39 #include "llvm/ADT/StringExtras.h"
40 #include "llvm/ParameterAttributes.h"
43 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
44 : TargetLowering(TM) {
45 Subtarget = &TM.getSubtarget<X86Subtarget>();
46 X86ScalarSSEf64 = Subtarget->hasSSE2();
47 X86ScalarSSEf32 = Subtarget->hasSSE1();
48 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
51 RegInfo = TM.getRegisterInfo();
53 // Set up the TargetLowering object.
55 // X86 is weird, it always uses i8 for shift amounts and setcc results.
56 setShiftAmountType(MVT::i8);
57 setSetCCResultType(MVT::i8);
58 setSetCCResultContents(ZeroOrOneSetCCResult);
59 setSchedulingPreference(SchedulingForRegPressure);
60 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
61 setStackPointerRegisterToSaveRestore(X86StackPtr);
63 if (Subtarget->isTargetDarwin()) {
64 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(false);
66 setUseUnderscoreLongJmp(false);
67 } else if (Subtarget->isTargetMingw()) {
68 // MS runtime is weird: it exports _setjmp, but longjmp!
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(false);
72 setUseUnderscoreSetJmp(true);
73 setUseUnderscoreLongJmp(true);
76 // Set up the register classes.
77 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
78 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
79 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
80 if (Subtarget->is64Bit())
81 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
83 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
85 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
87 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
88 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
89 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
91 if (Subtarget->is64Bit()) {
92 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
93 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
96 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
97 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
99 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
102 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
104 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
105 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
106 // SSE has no i16 to fp conversion, only i32
107 if (X86ScalarSSEf32) {
108 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
109 // f32 and f64 cases are Legal, f80 case is not
110 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
112 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
113 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
116 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
117 // are Legal, f80 is custom lowered.
118 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
119 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
121 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
123 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
124 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
126 if (X86ScalarSSEf32) {
127 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
128 // f32 and f64 cases are Legal, f80 case is not
129 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
131 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
132 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
135 // Handle FP_TO_UINT by promoting the destination to a larger signed
137 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
138 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
139 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
141 if (Subtarget->is64Bit()) {
142 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
143 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
145 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
146 // Expand FP_TO_UINT into a select.
147 // FIXME: We would like to use a Custom expander here eventually to do
148 // the optimal thing for SSE vs. the default expansion in the legalizer.
149 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
151 // With SSE3 we can use fisttpll to convert to a signed i64.
152 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
155 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
156 if (!X86ScalarSSEf64) {
157 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
158 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
161 // Scalar integer multiply, multiply-high, divide, and remainder are
162 // lowered to use operations that produce two results, to match the
163 // available instructions. This exposes the two-result form to trivial
164 // CSE, which is able to combine x/y and x%y into a single instruction,
165 // for example. The single-result multiply instructions are introduced
166 // in X86ISelDAGToDAG.cpp, after CSE, for uses where the the high part
168 setOperationAction(ISD::MUL , MVT::i8 , Expand);
169 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
170 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
171 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
172 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
173 setOperationAction(ISD::SREM , MVT::i8 , Expand);
174 setOperationAction(ISD::UREM , MVT::i8 , Expand);
175 setOperationAction(ISD::MUL , MVT::i16 , Expand);
176 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
177 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
178 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
179 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
180 setOperationAction(ISD::SREM , MVT::i16 , Expand);
181 setOperationAction(ISD::UREM , MVT::i16 , Expand);
182 setOperationAction(ISD::MUL , MVT::i32 , Expand);
183 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
184 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
185 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
186 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
187 setOperationAction(ISD::SREM , MVT::i32 , Expand);
188 setOperationAction(ISD::UREM , MVT::i32 , Expand);
189 setOperationAction(ISD::MUL , MVT::i64 , Expand);
190 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
191 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
192 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
193 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
194 setOperationAction(ISD::SREM , MVT::i64 , Expand);
195 setOperationAction(ISD::UREM , MVT::i64 , Expand);
197 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
198 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
199 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
200 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
201 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
202 if (Subtarget->is64Bit())
203 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
205 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
206 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
207 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
208 setOperationAction(ISD::FREM , MVT::f64 , Expand);
209 setOperationAction(ISD::FLT_ROUNDS , MVT::i32 , Custom);
211 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
212 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
213 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
214 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
216 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
217 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
218 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
219 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
220 if (Subtarget->is64Bit()) {
221 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
222 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
223 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
226 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
227 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
229 // These should be promoted to a larger select which is supported.
230 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
231 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
232 // X86 wants to expand cmov itself.
233 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
234 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
235 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
236 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
237 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
238 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
239 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
240 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
241 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
242 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
243 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
244 if (Subtarget->is64Bit()) {
245 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
246 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
248 // X86 ret instruction may pop stack.
249 setOperationAction(ISD::RET , MVT::Other, Custom);
250 if (!Subtarget->is64Bit())
251 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
254 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
255 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
256 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
257 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
258 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
259 if (Subtarget->is64Bit()) {
260 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
261 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
262 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
263 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
265 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
266 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
267 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
268 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
269 // X86 wants to expand memset / memcpy itself.
270 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
271 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
273 // Use the default ISD::LOCATION expansion.
274 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
275 // FIXME - use subtarget debug flags
276 if (!Subtarget->isTargetDarwin() &&
277 !Subtarget->isTargetELF() &&
278 !Subtarget->isTargetCygMing())
279 setOperationAction(ISD::LABEL, MVT::Other, Expand);
281 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
282 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
283 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
284 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
285 if (Subtarget->is64Bit()) {
287 setExceptionPointerRegister(X86::RAX);
288 setExceptionSelectorRegister(X86::RDX);
290 setExceptionPointerRegister(X86::EAX);
291 setExceptionSelectorRegister(X86::EDX);
293 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
295 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
297 setOperationAction(ISD::TRAP, MVT::Other, Legal);
299 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
300 setOperationAction(ISD::VASTART , MVT::Other, Custom);
301 setOperationAction(ISD::VAARG , MVT::Other, Expand);
302 setOperationAction(ISD::VAEND , MVT::Other, Expand);
303 if (Subtarget->is64Bit())
304 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
306 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
308 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
309 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
312 if (Subtarget->isTargetCygMing())
313 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
315 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
317 if (X86ScalarSSEf64) {
318 // f32 and f64 use SSE.
319 // Set up the FP register classes.
320 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
321 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
323 // Use ANDPD to simulate FABS.
324 setOperationAction(ISD::FABS , MVT::f64, Custom);
325 setOperationAction(ISD::FABS , MVT::f32, Custom);
327 // Use XORP to simulate FNEG.
328 setOperationAction(ISD::FNEG , MVT::f64, Custom);
329 setOperationAction(ISD::FNEG , MVT::f32, Custom);
331 // Use ANDPD and ORPD to simulate FCOPYSIGN.
332 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
333 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
335 // We don't support sin/cos/fmod
336 setOperationAction(ISD::FSIN , MVT::f64, Expand);
337 setOperationAction(ISD::FCOS , MVT::f64, Expand);
338 setOperationAction(ISD::FREM , MVT::f64, Expand);
339 setOperationAction(ISD::FSIN , MVT::f32, Expand);
340 setOperationAction(ISD::FCOS , MVT::f32, Expand);
341 setOperationAction(ISD::FREM , MVT::f32, Expand);
343 // Expand FP immediates into loads from the stack, except for the special
345 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
346 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
347 addLegalFPImmediate(APFloat(+0.0)); // xorpd
348 addLegalFPImmediate(APFloat(+0.0f)); // xorps
350 // Conversions to long double (in X87) go through memory.
351 setConvertAction(MVT::f32, MVT::f80, Expand);
352 setConvertAction(MVT::f64, MVT::f80, Expand);
354 // Conversions from long double (in X87) go through memory.
355 setConvertAction(MVT::f80, MVT::f32, Expand);
356 setConvertAction(MVT::f80, MVT::f64, Expand);
357 } else if (X86ScalarSSEf32) {
358 // Use SSE for f32, x87 for f64.
359 // Set up the FP register classes.
360 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
361 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
363 // Use ANDPS to simulate FABS.
364 setOperationAction(ISD::FABS , MVT::f32, Custom);
366 // Use XORP to simulate FNEG.
367 setOperationAction(ISD::FNEG , MVT::f32, Custom);
369 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
371 // Use ANDPS and ORPS to simulate FCOPYSIGN.
372 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
373 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
375 // We don't support sin/cos/fmod
376 setOperationAction(ISD::FSIN , MVT::f32, Expand);
377 setOperationAction(ISD::FCOS , MVT::f32, Expand);
378 setOperationAction(ISD::FREM , MVT::f32, Expand);
380 // Expand FP immediates into loads from the stack, except for the special
382 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
383 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
384 addLegalFPImmediate(APFloat(+0.0f)); // xorps
385 addLegalFPImmediate(APFloat(+0.0)); // FLD0
386 addLegalFPImmediate(APFloat(+1.0)); // FLD1
387 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
388 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
390 // SSE->x87 conversions go through memory.
391 setConvertAction(MVT::f32, MVT::f64, Expand);
392 setConvertAction(MVT::f32, MVT::f80, Expand);
394 // x87->SSE truncations need to go through memory.
395 setConvertAction(MVT::f80, MVT::f32, Expand);
396 setConvertAction(MVT::f64, MVT::f32, Expand);
397 // And x87->x87 truncations also.
398 setConvertAction(MVT::f80, MVT::f64, Expand);
401 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
402 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
405 // f32 and f64 in x87.
406 // Set up the FP register classes.
407 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
408 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
410 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
411 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
412 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
413 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
415 // Floating truncations need to go through memory.
416 setConvertAction(MVT::f80, MVT::f32, Expand);
417 setConvertAction(MVT::f64, MVT::f32, Expand);
418 setConvertAction(MVT::f80, MVT::f64, Expand);
421 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
422 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
425 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
426 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
427 addLegalFPImmediate(APFloat(+0.0)); // FLD0
428 addLegalFPImmediate(APFloat(+1.0)); // FLD1
429 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
430 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
431 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
432 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
433 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
434 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
437 // Long double always uses X87.
438 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
439 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
440 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
441 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
443 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
444 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
447 // Always use a library call for pow.
448 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
449 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
450 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
452 // First set operation action for all vector types to expand. Then we
453 // will selectively turn on ones that can be effectively codegen'd.
454 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
455 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
456 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
457 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
458 setOperationAction(ISD::FADD, (MVT::ValueType)VT, Expand);
459 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
460 setOperationAction(ISD::FSUB, (MVT::ValueType)VT, Expand);
461 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
462 setOperationAction(ISD::FMUL, (MVT::ValueType)VT, Expand);
463 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
464 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
465 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
466 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
467 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
468 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
469 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
470 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
471 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
472 setOperationAction(ISD::FABS, (MVT::ValueType)VT, Expand);
473 setOperationAction(ISD::FSIN, (MVT::ValueType)VT, Expand);
474 setOperationAction(ISD::FCOS, (MVT::ValueType)VT, Expand);
475 setOperationAction(ISD::FREM, (MVT::ValueType)VT, Expand);
476 setOperationAction(ISD::FPOWI, (MVT::ValueType)VT, Expand);
477 setOperationAction(ISD::FSQRT, (MVT::ValueType)VT, Expand);
478 setOperationAction(ISD::FCOPYSIGN, (MVT::ValueType)VT, Expand);
479 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
480 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
481 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
482 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
483 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
484 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
485 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
486 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
487 setOperationAction(ISD::SHL, (MVT::ValueType)VT, Expand);
488 setOperationAction(ISD::SRA, (MVT::ValueType)VT, Expand);
489 setOperationAction(ISD::SRL, (MVT::ValueType)VT, Expand);
490 setOperationAction(ISD::ROTL, (MVT::ValueType)VT, Expand);
491 setOperationAction(ISD::ROTR, (MVT::ValueType)VT, Expand);
492 setOperationAction(ISD::BSWAP, (MVT::ValueType)VT, Expand);
495 if (Subtarget->hasMMX()) {
496 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
497 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
498 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
499 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
501 // FIXME: add MMX packed arithmetics
503 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
504 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
505 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
506 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
508 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
509 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
510 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
511 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
513 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
516 setOperationAction(ISD::AND, MVT::v8i8, Promote);
517 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
518 setOperationAction(ISD::AND, MVT::v4i16, Promote);
519 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
520 setOperationAction(ISD::AND, MVT::v2i32, Promote);
521 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
522 setOperationAction(ISD::AND, MVT::v1i64, Legal);
524 setOperationAction(ISD::OR, MVT::v8i8, Promote);
525 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
526 setOperationAction(ISD::OR, MVT::v4i16, Promote);
527 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
528 setOperationAction(ISD::OR, MVT::v2i32, Promote);
529 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
530 setOperationAction(ISD::OR, MVT::v1i64, Legal);
532 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
533 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
534 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
535 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
536 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
537 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
538 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
540 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
541 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
542 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
543 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
544 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
545 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
546 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
548 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
549 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
550 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
551 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
553 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
554 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
555 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
556 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
558 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
559 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
560 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Custom);
561 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
564 if (Subtarget->hasSSE1()) {
565 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
567 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
568 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
569 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
570 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
571 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
572 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
573 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
574 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
576 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
577 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
580 if (Subtarget->hasSSE2()) {
581 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
582 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
583 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
584 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
585 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
587 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
588 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
589 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
590 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
591 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
592 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
593 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
594 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
595 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
596 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
597 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
598 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
599 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
600 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
601 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
603 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
604 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
605 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
606 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
607 // Implement v4f32 insert_vector_elt in terms of SSE2 v8i16 ones.
608 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
610 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
611 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
612 // Do not attempt to custom lower non-power-of-2 vectors
613 if (!isPowerOf2_32(MVT::getVectorNumElements(VT)))
615 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Custom);
616 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
617 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Custom);
619 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
620 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
621 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
622 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
623 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
624 if (Subtarget->is64Bit())
625 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
627 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
628 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
629 setOperationAction(ISD::AND, (MVT::ValueType)VT, Promote);
630 AddPromotedToType (ISD::AND, (MVT::ValueType)VT, MVT::v2i64);
631 setOperationAction(ISD::OR, (MVT::ValueType)VT, Promote);
632 AddPromotedToType (ISD::OR, (MVT::ValueType)VT, MVT::v2i64);
633 setOperationAction(ISD::XOR, (MVT::ValueType)VT, Promote);
634 AddPromotedToType (ISD::XOR, (MVT::ValueType)VT, MVT::v2i64);
635 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Promote);
636 AddPromotedToType (ISD::LOAD, (MVT::ValueType)VT, MVT::v2i64);
637 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
638 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v2i64);
641 // Custom lower v2i64 and v2f64 selects.
642 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
643 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
644 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
645 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
648 // We want to custom lower some of our intrinsics.
649 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
651 // We have target-specific dag combine patterns for the following nodes:
652 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
653 setTargetDAGCombine(ISD::SELECT);
655 computeRegisterProperties();
657 // FIXME: These should be based on subtarget info. Plus, the values should
658 // be smaller when we are in optimizing for size mode.
659 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
660 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
661 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
662 allowUnalignedMemoryAccesses = true; // x86 supports it!
666 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
668 SDOperand X86TargetLowering::getPICJumpTableRelocBase(SDOperand Table,
669 SelectionDAG &DAG) const {
670 if (usesGlobalOffsetTable())
671 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
672 if (!Subtarget->isPICStyleRIPRel())
673 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
677 //===----------------------------------------------------------------------===//
678 // Return Value Calling Convention Implementation
679 //===----------------------------------------------------------------------===//
681 #include "X86GenCallingConv.inc"
683 /// GetPossiblePreceedingTailCall - Get preceeding X86ISD::TAILCALL node if it
684 /// exists skip possible ISD:TokenFactor.
685 static SDOperand GetPossiblePreceedingTailCall(SDOperand Chain) {
686 if (Chain.getOpcode() == X86ISD::TAILCALL) {
688 } else if (Chain.getOpcode() == ISD::TokenFactor) {
689 if (Chain.getNumOperands() &&
690 Chain.getOperand(0).getOpcode() == X86ISD::TAILCALL)
691 return Chain.getOperand(0);
696 /// LowerRET - Lower an ISD::RET node.
697 SDOperand X86TargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG) {
698 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
700 SmallVector<CCValAssign, 16> RVLocs;
701 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
702 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
703 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
704 CCInfo.AnalyzeReturn(Op.Val, RetCC_X86);
706 // If this is the first return lowered for this function, add the regs to the
707 // liveout set for the function.
708 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
709 for (unsigned i = 0; i != RVLocs.size(); ++i)
710 if (RVLocs[i].isRegLoc())
711 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
713 SDOperand Chain = Op.getOperand(0);
715 // Handle tail call return.
716 Chain = GetPossiblePreceedingTailCall(Chain);
717 if (Chain.getOpcode() == X86ISD::TAILCALL) {
718 SDOperand TailCall = Chain;
719 SDOperand TargetAddress = TailCall.getOperand(1);
720 SDOperand StackAdjustment = TailCall.getOperand(2);
721 assert(((TargetAddress.getOpcode() == ISD::Register &&
722 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::ECX ||
723 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
724 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
725 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
726 "Expecting an global address, external symbol, or register");
727 assert(StackAdjustment.getOpcode() == ISD::Constant &&
728 "Expecting a const value");
730 SmallVector<SDOperand,8> Operands;
731 Operands.push_back(Chain.getOperand(0));
732 Operands.push_back(TargetAddress);
733 Operands.push_back(StackAdjustment);
734 // Copy registers used by the call. Last operand is a flag so it is not
736 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
737 Operands.push_back(Chain.getOperand(i));
739 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
746 // Copy the result values into the output registers.
747 if (RVLocs.size() != 1 || !RVLocs[0].isRegLoc() ||
748 RVLocs[0].getLocReg() != X86::ST0) {
749 for (unsigned i = 0; i != RVLocs.size(); ++i) {
750 CCValAssign &VA = RVLocs[i];
751 assert(VA.isRegLoc() && "Can only return in registers!");
752 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1),
754 Flag = Chain.getValue(1);
757 // We need to handle a destination of ST0 specially, because it isn't really
759 SDOperand Value = Op.getOperand(1);
761 // If this is an FP return with ScalarSSE, we need to move the value from
762 // an XMM register onto the fp-stack.
763 if (isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
766 // If this is a load into a scalarsse value, don't store the loaded value
767 // back to the stack, only to reload it: just replace the scalar-sse load.
768 if (ISD::isNON_EXTLoad(Value.Val) &&
769 Chain.reachesChainWithoutSideEffects(Value.getOperand(0))) {
770 Chain = Value.getOperand(0);
771 MemLoc = Value.getOperand(1);
773 // Spill the value to memory and reload it into top of stack.
774 unsigned Size = MVT::getSizeInBits(RVLocs[0].getValVT())/8;
775 MachineFunction &MF = DAG.getMachineFunction();
776 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
777 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
778 Chain = DAG.getStore(Op.getOperand(0), Value, MemLoc, NULL, 0);
780 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other);
781 SDOperand Ops[] = {Chain, MemLoc, DAG.getValueType(RVLocs[0].getValVT())};
782 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
783 Chain = Value.getValue(1);
786 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
787 SDOperand Ops[] = { Chain, Value };
788 Chain = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops, 2);
789 Flag = Chain.getValue(1);
792 SDOperand BytesToPop = DAG.getConstant(getBytesToPopOnReturn(), MVT::i16);
794 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop, Flag);
796 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Chain, BytesToPop);
800 /// LowerCallResult - Lower the result values of an ISD::CALL into the
801 /// appropriate copies out of appropriate physical registers. This assumes that
802 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
803 /// being lowered. The returns a SDNode with the same number of values as the
805 SDNode *X86TargetLowering::
806 LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
807 unsigned CallingConv, SelectionDAG &DAG) {
809 // Assign locations to each value returned by this call.
810 SmallVector<CCValAssign, 16> RVLocs;
811 bool isVarArg = cast<ConstantSDNode>(TheCall->getOperand(2))->getValue() != 0;
812 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
813 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
815 SmallVector<SDOperand, 8> ResultVals;
817 // Copy all of the result registers out of their specified physreg.
818 if (RVLocs.size() != 1 || RVLocs[0].getLocReg() != X86::ST0) {
819 for (unsigned i = 0; i != RVLocs.size(); ++i) {
820 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
821 RVLocs[i].getValVT(), InFlag).getValue(1);
822 InFlag = Chain.getValue(2);
823 ResultVals.push_back(Chain.getValue(0));
826 // Copies from the FP stack are special, as ST0 isn't a valid register
827 // before the fp stackifier runs.
829 // Copy ST0 into an RFP register with FP_GET_RESULT.
830 SDVTList Tys = DAG.getVTList(RVLocs[0].getValVT(), MVT::Other, MVT::Flag);
831 SDOperand GROps[] = { Chain, InFlag };
832 SDOperand RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, GROps, 2);
833 Chain = RetVal.getValue(1);
834 InFlag = RetVal.getValue(2);
836 // If we are using ScalarSSE, store ST(0) to the stack and reload it into
838 if (isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
840 const Value *SrcVal = 0;
841 int SrcValOffset = 0;
842 MVT::ValueType RetStoreVT = RVLocs[0].getValVT();
844 // Determine where to store the value. If the call result is directly
845 // used by a store, see if we can store directly into the location. In
846 // this case, we'll end up producing a fst + movss[load] + movss[store] to
847 // the same location, and the two movss's will be nuked as dead. This
848 // optimizes common things like "*D = atof(..)" to not need an
849 // intermediate stack slot.
850 if (SDOperand(TheCall, 0).hasOneUse() &&
851 SDOperand(TheCall, 1).hasOneUse()) {
852 // In addition to direct uses, we also support a FP_ROUND that uses the
853 // value, if it is directly stored somewhere.
854 SDNode *User = *TheCall->use_begin();
855 if (User->getOpcode() == ISD::FP_ROUND && User->hasOneUse())
856 User = *User->use_begin();
858 // Ok, we have one use of the value and one use of the chain. See if
859 // they are the same node: a store.
860 if (StoreSDNode *N = dyn_cast<StoreSDNode>(User)) {
861 // Verify that the value being stored is either the call or a
862 // truncation of the call.
863 SDNode *StoreVal = N->getValue().Val;
864 if (StoreVal == TheCall)
866 else if (StoreVal->getOpcode() == ISD::FP_ROUND &&
867 StoreVal->hasOneUse() &&
868 StoreVal->getOperand(0).Val == TheCall)
873 if (N && N->getChain().Val == TheCall &&
874 !N->isVolatile() && !N->isTruncatingStore() &&
875 N->getAddressingMode() == ISD::UNINDEXED) {
876 StoreLoc = N->getBasePtr();
877 SrcVal = N->getSrcValue();
878 SrcValOffset = N->getSrcValueOffset();
879 RetStoreVT = N->getValue().getValueType();
884 // If we weren't able to optimize the result, just create a temporary
886 if (StoreLoc.Val == 0) {
887 MachineFunction &MF = DAG.getMachineFunction();
888 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
889 StoreLoc = DAG.getFrameIndex(SSFI, getPointerTy());
892 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
893 // shouldn't be necessary except that RFP cannot be live across
894 // multiple blocks (which could happen if a select gets lowered into
895 // multiple blocks and scheduled in between them). When stackifier is
896 // fixed, they can be uncoupled.
898 Chain, RetVal, StoreLoc, DAG.getValueType(RetStoreVT), InFlag
900 Chain = DAG.getNode(X86ISD::FST, MVT::Other, Ops, 5);
901 RetVal = DAG.getLoad(RetStoreVT, Chain,
902 StoreLoc, SrcVal, SrcValOffset);
903 Chain = RetVal.getValue(1);
905 // If we optimized a truncate, then extend the result back to its desired
907 if (RVLocs[0].getValVT() != RetStoreVT)
908 RetVal = DAG.getNode(ISD::FP_EXTEND, RVLocs[0].getValVT(), RetVal);
910 ResultVals.push_back(RetVal);
913 // Merge everything together with a MERGE_VALUES node.
914 ResultVals.push_back(Chain);
915 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
916 &ResultVals[0], ResultVals.size()).Val;
920 //===----------------------------------------------------------------------===//
921 // C & StdCall & Fast Calling Convention implementation
922 //===----------------------------------------------------------------------===//
923 // StdCall calling convention seems to be standard for many Windows' API
924 // routines and around. It differs from C calling convention just a little:
925 // callee should clean up the stack, not caller. Symbols should be also
926 // decorated in some fancy way :) It doesn't support any vector arguments.
927 // For info on fast calling convention see Fast Calling Convention (tail call)
928 // implementation LowerX86_32FastCCCallTo.
930 /// AddLiveIn - This helper function adds the specified physical register to the
931 /// MachineFunction as a live in value. It also creates a corresponding virtual
933 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
934 const TargetRegisterClass *RC) {
935 assert(RC->contains(PReg) && "Not the correct regclass!");
936 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
937 MF.getRegInfo().addLiveIn(PReg, VReg);
941 // Determines whether a CALL node uses struct return semantics.
942 static bool CallIsStructReturn(SDOperand Op) {
943 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
947 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(6));
948 return Flags->getValue() & ISD::ParamFlags::StructReturn;
951 // Determines whether a FORMAL_ARGUMENTS node uses struct return semantics.
952 static bool ArgsAreStructReturn(SDOperand Op) {
953 unsigned NumArgs = Op.Val->getNumValues() - 1;
957 ConstantSDNode *Flags = cast<ConstantSDNode>(Op.getOperand(3));
958 return Flags->getValue() & ISD::ParamFlags::StructReturn;
961 // Determines whether a CALL or FORMAL_ARGUMENTS node requires the callee to pop
962 // its own arguments. Callee pop is necessary to support tail calls.
963 bool X86TargetLowering::IsCalleePop(SDOperand Op) {
964 bool IsVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
968 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
971 case CallingConv::X86_StdCall:
972 return !Subtarget->is64Bit();
973 case CallingConv::X86_FastCall:
974 return !Subtarget->is64Bit();
975 case CallingConv::Fast:
976 return PerformTailCallOpt;
980 // Selects the correct CCAssignFn for a CALL or FORMAL_ARGUMENTS node.
981 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
982 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
984 if (Subtarget->is64Bit())
985 if (CC == CallingConv::Fast && PerformTailCallOpt)
986 return CC_X86_64_TailCall;
990 if (CC == CallingConv::X86_FastCall)
991 return CC_X86_32_FastCall;
992 else if (CC == CallingConv::Fast && PerformTailCallOpt)
993 return CC_X86_32_TailCall;
998 // Selects the appropriate decoration to apply to a MachineFunction containing a
999 // given FORMAL_ARGUMENTS node.
1001 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDOperand Op) {
1002 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1003 if (CC == CallingConv::X86_FastCall)
1005 else if (CC == CallingConv::X86_StdCall)
1011 // IsPossiblyOverwrittenArgumentOfTailCall - Check if the operand could possibly
1012 // be overwritten when lowering the outgoing arguments in a tail call. Currently
1013 // the implementation of this call is very conservative and assumes all
1014 // arguments sourcing from FORMAL_ARGUMENTS or a CopyFromReg with virtual
1015 // registers would be overwritten by direct lowering.
1016 // Possible improvement:
1017 // Check FORMAL_ARGUMENTS corresponding MERGE_VALUES for CopyFromReg nodes
1018 // indicating inreg passed arguments which also need not be lowered to a safe
1020 static bool IsPossiblyOverwrittenArgumentOfTailCall(SDOperand Op) {
1021 RegisterSDNode * OpReg = NULL;
1022 if (Op.getOpcode() == ISD::FORMAL_ARGUMENTS ||
1023 (Op.getOpcode()== ISD::CopyFromReg &&
1024 (OpReg = cast<RegisterSDNode>(Op.getOperand(1))) &&
1025 OpReg->getReg() >= MRegisterInfo::FirstVirtualRegister))
1030 // CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1031 // by "Src" to address "Dst" with size and alignment information specified by
1032 // the specific parameter attribute. The copy will be passed as a byval function
1035 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1036 unsigned Flags, SelectionDAG &DAG) {
1037 unsigned Align = 1 <<
1038 ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs);
1039 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1040 ISD::ParamFlags::ByValSizeOffs;
1041 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1042 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1043 SDOperand AlwaysInline = DAG.getConstant(1, MVT::i32);
1044 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline);
1047 SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
1048 const CCValAssign &VA,
1049 MachineFrameInfo *MFI,
1050 SDOperand Root, unsigned i) {
1051 // Create the nodes corresponding to a load from this parameter slot.
1052 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
1053 bool isByVal = Flags & ISD::ParamFlags::ByVal;
1055 // FIXME: For now, all byval parameter objects are marked mutable. This
1056 // can be changed with more analysis.
1057 int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
1058 VA.getLocMemOffset(), !isByVal);
1059 SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
1062 return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0);
1066 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
1067 MachineFunction &MF = DAG.getMachineFunction();
1068 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1070 const Function* Fn = MF.getFunction();
1071 if (Fn->hasExternalLinkage() &&
1072 Subtarget->isTargetCygMing() &&
1073 Fn->getName() == "main")
1074 FuncInfo->setForceFramePointer(true);
1076 // Decorate the function name.
1077 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1079 MachineFrameInfo *MFI = MF.getFrameInfo();
1080 SDOperand Root = Op.getOperand(0);
1081 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1082 unsigned CC = MF.getFunction()->getCallingConv();
1083 bool Is64Bit = Subtarget->is64Bit();
1085 assert(!(isVarArg && CC == CallingConv::Fast) &&
1086 "Var args not supported with calling convention fastcc");
1088 // Assign locations to all of the incoming arguments.
1089 SmallVector<CCValAssign, 16> ArgLocs;
1090 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1091 CCInfo.AnalyzeFormalArguments(Op.Val, CCAssignFnForNode(Op));
1093 SmallVector<SDOperand, 8> ArgValues;
1094 unsigned LastVal = ~0U;
1095 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1096 CCValAssign &VA = ArgLocs[i];
1097 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1099 assert(VA.getValNo() != LastVal &&
1100 "Don't support value assigned to multiple locs yet");
1101 LastVal = VA.getValNo();
1103 if (VA.isRegLoc()) {
1104 MVT::ValueType RegVT = VA.getLocVT();
1105 TargetRegisterClass *RC;
1106 if (RegVT == MVT::i32)
1107 RC = X86::GR32RegisterClass;
1108 else if (Is64Bit && RegVT == MVT::i64)
1109 RC = X86::GR64RegisterClass;
1110 else if (Is64Bit && RegVT == MVT::f32)
1111 RC = X86::FR32RegisterClass;
1112 else if (Is64Bit && RegVT == MVT::f64)
1113 RC = X86::FR64RegisterClass;
1115 assert(MVT::isVector(RegVT));
1116 if (Is64Bit && MVT::getSizeInBits(RegVT) == 64) {
1117 RC = X86::GR64RegisterClass; // MMX values are passed in GPRs.
1120 RC = X86::VR128RegisterClass;
1123 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1124 SDOperand ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1126 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1127 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1129 if (VA.getLocInfo() == CCValAssign::SExt)
1130 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1131 DAG.getValueType(VA.getValVT()));
1132 else if (VA.getLocInfo() == CCValAssign::ZExt)
1133 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1134 DAG.getValueType(VA.getValVT()));
1136 if (VA.getLocInfo() != CCValAssign::Full)
1137 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1139 // Handle MMX values passed in GPRs.
1140 if (Is64Bit && RegVT != VA.getLocVT() && RC == X86::GR64RegisterClass &&
1141 MVT::getSizeInBits(RegVT) == 64)
1142 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1144 ArgValues.push_back(ArgValue);
1146 assert(VA.isMemLoc());
1147 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
1151 unsigned StackSize = CCInfo.getNextStackOffset();
1152 // align stack specially for tail calls
1153 if (CC == CallingConv::Fast)
1154 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1156 // If the function takes variable number of arguments, make a frame index for
1157 // the start of the first vararg value... for expansion of llvm.va_start.
1159 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1160 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1163 static const unsigned GPR64ArgRegs[] = {
1164 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1166 static const unsigned XMMArgRegs[] = {
1167 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1168 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1171 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
1172 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1174 // For X86-64, if there are vararg parameters that are passed via
1175 // registers, then we must store them to their spots on the stack so they
1176 // may be loaded by deferencing the result of va_next.
1177 VarArgsGPOffset = NumIntRegs * 8;
1178 VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
1179 RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
1181 // Store the integer parameter registers.
1182 SmallVector<SDOperand, 8> MemOps;
1183 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1184 SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1185 DAG.getIntPtrConstant(VarArgsGPOffset));
1186 for (; NumIntRegs != 6; ++NumIntRegs) {
1187 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1188 X86::GR64RegisterClass);
1189 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1190 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1191 MemOps.push_back(Store);
1192 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1193 DAG.getIntPtrConstant(8));
1196 // Now store the XMM (fp + vector) parameter registers.
1197 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1198 DAG.getIntPtrConstant(VarArgsFPOffset));
1199 for (; NumXMMRegs != 8; ++NumXMMRegs) {
1200 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1201 X86::VR128RegisterClass);
1202 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1203 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1204 MemOps.push_back(Store);
1205 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1206 DAG.getIntPtrConstant(16));
1208 if (!MemOps.empty())
1209 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1210 &MemOps[0], MemOps.size());
1214 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1215 // arguments and the arguments after the retaddr has been pushed are
1217 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1218 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1219 (StackSize & 7) == 0)
1222 ArgValues.push_back(Root);
1224 // Some CCs need callee pop.
1225 if (IsCalleePop(Op)) {
1226 BytesToPopOnReturn = StackSize; // Callee pops everything.
1227 BytesCallerReserves = 0;
1229 BytesToPopOnReturn = 0; // Callee pops nothing.
1230 // If this is an sret function, the return should pop the hidden pointer.
1231 if (!Is64Bit && ArgsAreStructReturn(Op))
1232 BytesToPopOnReturn = 4;
1233 BytesCallerReserves = StackSize;
1237 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1238 if (CC == CallingConv::X86_FastCall)
1239 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1242 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1244 // Return the new list of results.
1245 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
1246 &ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
1250 X86TargetLowering::LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
1251 const SDOperand &StackPtr,
1252 const CCValAssign &VA,
1255 SDOperand PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset());
1256 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1257 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1258 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1259 if (Flags & ISD::ParamFlags::ByVal) {
1260 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1262 return DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1265 SDOperand X86TargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
1266 MachineFunction &MF = DAG.getMachineFunction();
1267 SDOperand Chain = Op.getOperand(0);
1268 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
1269 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1270 bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
1271 && CC == CallingConv::Fast && PerformTailCallOpt;
1272 SDOperand Callee = Op.getOperand(4);
1273 bool Is64Bit = Subtarget->is64Bit();
1275 assert(!(isVarArg && CC == CallingConv::Fast) &&
1276 "Var args not supported with calling convention fastcc");
1278 // Analyze operands of the call, assigning locations to each operand.
1279 SmallVector<CCValAssign, 16> ArgLocs;
1280 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1281 CCInfo.AnalyzeCallOperands(Op.Val, CCAssignFnForNode(Op));
1283 // Get a count of how many bytes are to be pushed on the stack.
1284 unsigned NumBytes = CCInfo.getNextStackOffset();
1285 if (CC == CallingConv::Fast)
1286 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1288 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
1289 // arguments and the arguments after the retaddr has been pushed are aligned.
1290 if (!Is64Bit && CC == CallingConv::X86_FastCall &&
1291 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWindows() &&
1292 (NumBytes & 7) == 0)
1297 // Lower arguments at fp - stackoffset + fpdiff.
1298 unsigned NumBytesCallerPushed =
1299 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1300 FPDiff = NumBytesCallerPushed - NumBytes;
1302 // Set the delta of movement of the returnaddr stackslot.
1303 // But only set if delta is greater than previous delta.
1304 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1305 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1308 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes));
1310 SDOperand RetAddrFrIdx, NewRetAddrFrIdx;
1312 // Adjust the Return address stack slot.
1314 MVT::ValueType VT = Is64Bit ? MVT::i64 : MVT::i32;
1315 RetAddrFrIdx = getReturnAddressFrameIndex(DAG);
1316 // Load the "old" Return address.
1318 DAG.getLoad(VT, Chain,RetAddrFrIdx, NULL, 0);
1319 // Calculate the new stack slot for the return address.
1320 int SlotSize = Is64Bit ? 8 : 4;
1321 int NewReturnAddrFI =
1322 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1323 NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1324 Chain = SDOperand(RetAddrFrIdx.Val, 1);
1328 SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
1329 SmallVector<SDOperand, 8> MemOpChains;
1333 // Walk the register/memloc assignments, inserting copies/loads. For tail
1334 // calls, lower arguments which could otherwise be possibly overwritten to the
1335 // stack slot where they would go on normal function calls.
1336 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1337 CCValAssign &VA = ArgLocs[i];
1338 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1340 // Promote the value if needed.
1341 switch (VA.getLocInfo()) {
1342 default: assert(0 && "Unknown loc info!");
1343 case CCValAssign::Full: break;
1344 case CCValAssign::SExt:
1345 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1347 case CCValAssign::ZExt:
1348 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1350 case CCValAssign::AExt:
1351 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1355 if (VA.isRegLoc()) {
1356 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1358 if (!IsTailCall || IsPossiblyOverwrittenArgumentOfTailCall(Arg)) {
1359 assert(VA.isMemLoc());
1360 if (StackPtr.Val == 0)
1361 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1363 MemOpChains.push_back(LowerMemOpCallTo(Op, DAG, StackPtr, VA, Chain,
1369 if (!MemOpChains.empty())
1370 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1371 &MemOpChains[0], MemOpChains.size());
1373 // Build a sequence of copy-to-reg nodes chained together with token chain
1374 // and flag operands which copy the outgoing args into registers.
1376 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1377 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1379 InFlag = Chain.getValue(1);
1383 InFlag = SDOperand(); // ??? Isn't this nuking the preceding loop's output?
1385 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1387 // Does not work with tail call since ebx is not restored correctly by
1388 // tailcaller. TODO: at least for x86 - verify for x86-64
1389 if (!IsTailCall && !Is64Bit &&
1390 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1391 Subtarget->isPICStyleGOT()) {
1392 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1393 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1395 InFlag = Chain.getValue(1);
1398 if (Is64Bit && isVarArg) {
1399 // From AMD64 ABI document:
1400 // For calls that may call functions that use varargs or stdargs
1401 // (prototype-less calls or calls to functions containing ellipsis (...) in
1402 // the declaration) %al is used as hidden argument to specify the number
1403 // of SSE registers used. The contents of %al do not need to match exactly
1404 // the number of registers, but must be an ubound on the number of SSE
1405 // registers used and is in the range 0 - 8 inclusive.
1407 // Count the number of XMM registers allocated.
1408 static const unsigned XMMArgRegs[] = {
1409 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1410 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1412 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1414 Chain = DAG.getCopyToReg(Chain, X86::AL,
1415 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1416 InFlag = Chain.getValue(1);
1419 // For tail calls lower the arguments to the 'real' stack slot.
1421 SmallVector<SDOperand, 8> MemOpChains2;
1424 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1425 CCValAssign &VA = ArgLocs[i];
1426 if (!VA.isRegLoc()) {
1427 assert(VA.isMemLoc());
1428 SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
1429 SDOperand FlagsOp = Op.getOperand(6+2*VA.getValNo());
1430 unsigned Flags = cast<ConstantSDNode>(FlagsOp)->getValue();
1431 // Create frame index.
1432 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1433 uint32_t OpSize = (MVT::getSizeInBits(VA.getLocVT())+7)/8;
1434 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1435 FIN = DAG.getFrameIndex(FI, MVT::i32);
1436 SDOperand Source = Arg;
1437 if (IsPossiblyOverwrittenArgumentOfTailCall(Arg)) {
1438 // Copy from stack slots to stack slot of a tail called function. This
1439 // needs to be done because if we would lower the arguments directly
1440 // to their real stack slot we might end up overwriting each other.
1441 // Get source stack slot.
1442 Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1443 if (StackPtr.Val == 0)
1444 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1445 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1446 if ((Flags & ISD::ParamFlags::ByVal)==0)
1447 Source = DAG.getLoad(VA.getValVT(), Chain, Source, NULL, 0);
1450 if (Flags & ISD::ParamFlags::ByVal) {
1451 // Copy relative to framepointer.
1452 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1455 // Store relative to framepointer.
1456 MemOpChains2.push_back(DAG.getStore(Chain, Source, FIN, NULL, 0));
1461 if (!MemOpChains2.empty())
1462 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1463 &MemOpChains2[0], MemOpChains2.size());
1465 // Store the return address to the appropriate stack slot.
1467 Chain = DAG.getStore(Chain,RetAddrFrIdx, NewRetAddrFrIdx, NULL, 0);
1470 // If the callee is a GlobalAddress node (quite common, every direct call is)
1471 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1472 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1473 // We should use extra load for direct calls to dllimported functions in
1475 if ((IsTailCall || !Is64Bit ||
1476 getTargetMachine().getCodeModel() != CodeModel::Large)
1477 && !Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1478 getTargetMachine(), true))
1479 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
1480 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1481 if (IsTailCall || !Is64Bit ||
1482 getTargetMachine().getCodeModel() != CodeModel::Large)
1483 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1484 } else if (IsTailCall) {
1485 assert(Callee.getOpcode() == ISD::LOAD &&
1486 "Function destination must be loaded into virtual register");
1487 unsigned Opc = Is64Bit ? X86::R9 : X86::ECX;
1489 Chain = DAG.getCopyToReg(Chain,
1490 DAG.getRegister(Opc, getPointerTy()) ,
1492 Callee = DAG.getRegister(Opc, getPointerTy());
1493 // Add register as live out.
1494 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1497 // Returns a chain & a flag for retval copy to use.
1498 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1499 SmallVector<SDOperand, 8> Ops;
1502 Ops.push_back(Chain);
1503 Ops.push_back(DAG.getIntPtrConstant(NumBytes));
1504 Ops.push_back(DAG.getIntPtrConstant(0));
1506 Ops.push_back(InFlag);
1507 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1508 InFlag = Chain.getValue(1);
1510 // Returns a chain & a flag for retval copy to use.
1511 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1515 Ops.push_back(Chain);
1516 Ops.push_back(Callee);
1519 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1521 // Add an implicit use GOT pointer in EBX.
1522 if (!IsTailCall && !Is64Bit &&
1523 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1524 Subtarget->isPICStyleGOT())
1525 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1527 // Add argument registers to the end of the list so that they are known live
1529 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1530 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1531 RegsToPass[i].second.getValueType()));
1534 Ops.push_back(InFlag);
1537 assert(InFlag.Val &&
1538 "Flag must be set. Depend on flag being set in LowerRET");
1539 Chain = DAG.getNode(X86ISD::TAILCALL,
1540 Op.Val->getVTList(), &Ops[0], Ops.size());
1542 return SDOperand(Chain.Val, Op.ResNo);
1545 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1546 InFlag = Chain.getValue(1);
1548 // Create the CALLSEQ_END node.
1549 unsigned NumBytesForCalleeToPush;
1550 if (IsCalleePop(Op))
1551 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1552 else if (!Is64Bit && CallIsStructReturn(Op))
1553 // If this is is a call to a struct-return function, the callee
1554 // pops the hidden struct pointer, so we have to push it back.
1555 // This is common for Darwin/X86, Linux & Mingw32 targets.
1556 NumBytesForCalleeToPush = 4;
1558 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1560 // Returns a flag for retval copy to use.
1561 Chain = DAG.getCALLSEQ_END(Chain,
1562 DAG.getIntPtrConstant(NumBytes),
1563 DAG.getIntPtrConstant(NumBytesForCalleeToPush),
1565 InFlag = Chain.getValue(1);
1567 // Handle result values, copying them out of physregs into vregs that we
1569 return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
1573 //===----------------------------------------------------------------------===//
1574 // Fast Calling Convention (tail call) implementation
1575 //===----------------------------------------------------------------------===//
1577 // Like std call, callee cleans arguments, convention except that ECX is
1578 // reserved for storing the tail called function address. Only 2 registers are
1579 // free for argument passing (inreg). Tail call optimization is performed
1581 // * tailcallopt is enabled
1582 // * caller/callee are fastcc
1583 // * elf/pic is disabled OR
1584 // * elf/pic enabled + callee is in module + callee has
1585 // visibility protected or hidden
1586 // To keep the stack aligned according to platform abi the function
1587 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1588 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1589 // If a tail called function callee has more arguments than the caller the
1590 // caller needs to make sure that there is room to move the RETADDR to. This is
1591 // achieved by reserving an area the size of the argument delta right after the
1592 // original REtADDR, but before the saved framepointer or the spilled registers
1593 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1605 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1606 /// for a 16 byte align requirement.
1607 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1608 SelectionDAG& DAG) {
1609 if (PerformTailCallOpt) {
1610 MachineFunction &MF = DAG.getMachineFunction();
1611 const TargetMachine &TM = MF.getTarget();
1612 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1613 unsigned StackAlignment = TFI.getStackAlignment();
1614 uint64_t AlignMask = StackAlignment - 1;
1615 int64_t Offset = StackSize;
1616 unsigned SlotSize = Subtarget->is64Bit() ? 8 : 4;
1617 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1618 // Number smaller than 12 so just add the difference.
1619 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1621 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1622 Offset = ((~AlignMask) & Offset) + StackAlignment +
1623 (StackAlignment-SlotSize);
1630 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1631 /// following the call is a return. A function is eligible if caller/callee
1632 /// calling conventions match, currently only fastcc supports tail calls, and
1633 /// the function CALL is immediatly followed by a RET.
1634 bool X86TargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
1636 SelectionDAG& DAG) const {
1637 if (!PerformTailCallOpt)
1640 // Check whether CALL node immediatly preceeds the RET node and whether the
1641 // return uses the result of the node or is a void return.
1642 unsigned NumOps = Ret.getNumOperands();
1644 (Ret.getOperand(0) == SDOperand(Call.Val,1) ||
1645 Ret.getOperand(0) == SDOperand(Call.Val,0))) ||
1647 Ret.getOperand(0) == SDOperand(Call.Val,Call.Val->getNumValues()-1) &&
1648 Ret.getOperand(1) == SDOperand(Call.Val,0))) {
1649 MachineFunction &MF = DAG.getMachineFunction();
1650 unsigned CallerCC = MF.getFunction()->getCallingConv();
1651 unsigned CalleeCC = cast<ConstantSDNode>(Call.getOperand(1))->getValue();
1652 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1653 SDOperand Callee = Call.getOperand(4);
1654 // On elf/pic %ebx needs to be livein.
1655 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1656 !Subtarget->isPICStyleGOT())
1659 // Can only do local tail calls with PIC.
1660 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1661 return G->getGlobal()->hasHiddenVisibility()
1662 || G->getGlobal()->hasProtectedVisibility();
1669 //===----------------------------------------------------------------------===//
1670 // Other Lowering Hooks
1671 //===----------------------------------------------------------------------===//
1674 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1675 MachineFunction &MF = DAG.getMachineFunction();
1676 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1677 int ReturnAddrIndex = FuncInfo->getRAIndex();
1679 if (ReturnAddrIndex == 0) {
1680 // Set up a frame object for the return address.
1681 if (Subtarget->is64Bit())
1682 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(8, -8);
1684 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1686 FuncInfo->setRAIndex(ReturnAddrIndex);
1689 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1694 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1695 /// specific condition code. It returns a false if it cannot do a direct
1696 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1698 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1699 unsigned &X86CC, SDOperand &LHS, SDOperand &RHS,
1700 SelectionDAG &DAG) {
1701 X86CC = X86::COND_INVALID;
1703 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1704 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1705 // X > -1 -> X == 0, jump !sign.
1706 RHS = DAG.getConstant(0, RHS.getValueType());
1707 X86CC = X86::COND_NS;
1709 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1710 // X < 0 -> X == 0, jump on sign.
1711 X86CC = X86::COND_S;
1713 } else if (SetCCOpcode == ISD::SETLT && RHSC->getValue() == 1) {
1715 RHS = DAG.getConstant(0, RHS.getValueType());
1716 X86CC = X86::COND_LE;
1721 switch (SetCCOpcode) {
1723 case ISD::SETEQ: X86CC = X86::COND_E; break;
1724 case ISD::SETGT: X86CC = X86::COND_G; break;
1725 case ISD::SETGE: X86CC = X86::COND_GE; break;
1726 case ISD::SETLT: X86CC = X86::COND_L; break;
1727 case ISD::SETLE: X86CC = X86::COND_LE; break;
1728 case ISD::SETNE: X86CC = X86::COND_NE; break;
1729 case ISD::SETULT: X86CC = X86::COND_B; break;
1730 case ISD::SETUGT: X86CC = X86::COND_A; break;
1731 case ISD::SETULE: X86CC = X86::COND_BE; break;
1732 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1735 // On a floating point condition, the flags are set as follows:
1737 // 0 | 0 | 0 | X > Y
1738 // 0 | 0 | 1 | X < Y
1739 // 1 | 0 | 0 | X == Y
1740 // 1 | 1 | 1 | unordered
1742 switch (SetCCOpcode) {
1745 case ISD::SETEQ: X86CC = X86::COND_E; break;
1746 case ISD::SETOLT: Flip = true; // Fallthrough
1748 case ISD::SETGT: X86CC = X86::COND_A; break;
1749 case ISD::SETOLE: Flip = true; // Fallthrough
1751 case ISD::SETGE: X86CC = X86::COND_AE; break;
1752 case ISD::SETUGT: Flip = true; // Fallthrough
1754 case ISD::SETLT: X86CC = X86::COND_B; break;
1755 case ISD::SETUGE: Flip = true; // Fallthrough
1757 case ISD::SETLE: X86CC = X86::COND_BE; break;
1759 case ISD::SETNE: X86CC = X86::COND_NE; break;
1760 case ISD::SETUO: X86CC = X86::COND_P; break;
1761 case ISD::SETO: X86CC = X86::COND_NP; break;
1764 std::swap(LHS, RHS);
1767 return X86CC != X86::COND_INVALID;
1770 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1771 /// code. Current x86 isa includes the following FP cmov instructions:
1772 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1773 static bool hasFPCMov(unsigned X86CC) {
1789 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
1790 /// true if Op is undef or if its value falls within the specified range (L, H].
1791 static bool isUndefOrInRange(SDOperand Op, unsigned Low, unsigned Hi) {
1792 if (Op.getOpcode() == ISD::UNDEF)
1795 unsigned Val = cast<ConstantSDNode>(Op)->getValue();
1796 return (Val >= Low && Val < Hi);
1799 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
1800 /// true if Op is undef or if its value equal to the specified value.
1801 static bool isUndefOrEqual(SDOperand Op, unsigned Val) {
1802 if (Op.getOpcode() == ISD::UNDEF)
1804 return cast<ConstantSDNode>(Op)->getValue() == Val;
1807 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
1808 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
1809 bool X86::isPSHUFDMask(SDNode *N) {
1810 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1812 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
1815 // Check if the value doesn't reference the second vector.
1816 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1817 SDOperand Arg = N->getOperand(i);
1818 if (Arg.getOpcode() == ISD::UNDEF) continue;
1819 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1820 if (cast<ConstantSDNode>(Arg)->getValue() >= e)
1827 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
1828 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
1829 bool X86::isPSHUFHWMask(SDNode *N) {
1830 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1832 if (N->getNumOperands() != 8)
1835 // Lower quadword copied in order.
1836 for (unsigned i = 0; i != 4; ++i) {
1837 SDOperand Arg = N->getOperand(i);
1838 if (Arg.getOpcode() == ISD::UNDEF) continue;
1839 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1840 if (cast<ConstantSDNode>(Arg)->getValue() != i)
1844 // Upper quadword shuffled.
1845 for (unsigned i = 4; i != 8; ++i) {
1846 SDOperand Arg = N->getOperand(i);
1847 if (Arg.getOpcode() == ISD::UNDEF) continue;
1848 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1849 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
1850 if (Val < 4 || Val > 7)
1857 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
1858 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
1859 bool X86::isPSHUFLWMask(SDNode *N) {
1860 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1862 if (N->getNumOperands() != 8)
1865 // Upper quadword copied in order.
1866 for (unsigned i = 4; i != 8; ++i)
1867 if (!isUndefOrEqual(N->getOperand(i), i))
1870 // Lower quadword shuffled.
1871 for (unsigned i = 0; i != 4; ++i)
1872 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
1878 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
1879 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
1880 static bool isSHUFPMask(const SDOperand *Elems, unsigned NumElems) {
1881 if (NumElems != 2 && NumElems != 4) return false;
1883 unsigned Half = NumElems / 2;
1884 for (unsigned i = 0; i < Half; ++i)
1885 if (!isUndefOrInRange(Elems[i], 0, NumElems))
1887 for (unsigned i = Half; i < NumElems; ++i)
1888 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
1894 bool X86::isSHUFPMask(SDNode *N) {
1895 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1896 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
1899 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
1900 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
1901 /// half elements to come from vector 1 (which would equal the dest.) and
1902 /// the upper half to come from vector 2.
1903 static bool isCommutedSHUFP(const SDOperand *Ops, unsigned NumOps) {
1904 if (NumOps != 2 && NumOps != 4) return false;
1906 unsigned Half = NumOps / 2;
1907 for (unsigned i = 0; i < Half; ++i)
1908 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
1910 for (unsigned i = Half; i < NumOps; ++i)
1911 if (!isUndefOrInRange(Ops[i], 0, NumOps))
1916 static bool isCommutedSHUFP(SDNode *N) {
1917 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1918 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
1921 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
1922 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
1923 bool X86::isMOVHLPSMask(SDNode *N) {
1924 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1926 if (N->getNumOperands() != 4)
1929 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
1930 return isUndefOrEqual(N->getOperand(0), 6) &&
1931 isUndefOrEqual(N->getOperand(1), 7) &&
1932 isUndefOrEqual(N->getOperand(2), 2) &&
1933 isUndefOrEqual(N->getOperand(3), 3);
1936 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
1937 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
1939 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
1940 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1942 if (N->getNumOperands() != 4)
1945 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
1946 return isUndefOrEqual(N->getOperand(0), 2) &&
1947 isUndefOrEqual(N->getOperand(1), 3) &&
1948 isUndefOrEqual(N->getOperand(2), 2) &&
1949 isUndefOrEqual(N->getOperand(3), 3);
1952 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
1953 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
1954 bool X86::isMOVLPMask(SDNode *N) {
1955 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1957 unsigned NumElems = N->getNumOperands();
1958 if (NumElems != 2 && NumElems != 4)
1961 for (unsigned i = 0; i < NumElems/2; ++i)
1962 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
1965 for (unsigned i = NumElems/2; i < NumElems; ++i)
1966 if (!isUndefOrEqual(N->getOperand(i), i))
1972 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
1973 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
1975 bool X86::isMOVHPMask(SDNode *N) {
1976 assert(N->getOpcode() == ISD::BUILD_VECTOR);
1978 unsigned NumElems = N->getNumOperands();
1979 if (NumElems != 2 && NumElems != 4)
1982 for (unsigned i = 0; i < NumElems/2; ++i)
1983 if (!isUndefOrEqual(N->getOperand(i), i))
1986 for (unsigned i = 0; i < NumElems/2; ++i) {
1987 SDOperand Arg = N->getOperand(i + NumElems/2);
1988 if (!isUndefOrEqual(Arg, i + NumElems))
1995 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
1996 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
1997 bool static isUNPCKLMask(const SDOperand *Elts, unsigned NumElts,
1998 bool V2IsSplat = false) {
1999 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2002 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2003 SDOperand BitI = Elts[i];
2004 SDOperand BitI1 = Elts[i+1];
2005 if (!isUndefOrEqual(BitI, j))
2008 if (isUndefOrEqual(BitI1, NumElts))
2011 if (!isUndefOrEqual(BitI1, j + NumElts))
2019 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2020 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2021 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2024 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2025 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2026 bool static isUNPCKHMask(const SDOperand *Elts, unsigned NumElts,
2027 bool V2IsSplat = false) {
2028 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2031 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2032 SDOperand BitI = Elts[i];
2033 SDOperand BitI1 = Elts[i+1];
2034 if (!isUndefOrEqual(BitI, j + NumElts/2))
2037 if (isUndefOrEqual(BitI1, NumElts))
2040 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2048 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2049 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2050 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2053 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2054 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2056 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2057 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2059 unsigned NumElems = N->getNumOperands();
2060 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2063 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2064 SDOperand BitI = N->getOperand(i);
2065 SDOperand BitI1 = N->getOperand(i+1);
2067 if (!isUndefOrEqual(BitI, j))
2069 if (!isUndefOrEqual(BitI1, j))
2076 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2077 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2079 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2080 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2082 unsigned NumElems = N->getNumOperands();
2083 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2086 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2087 SDOperand BitI = N->getOperand(i);
2088 SDOperand BitI1 = N->getOperand(i + 1);
2090 if (!isUndefOrEqual(BitI, j))
2092 if (!isUndefOrEqual(BitI1, j))
2099 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2100 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2101 /// MOVSD, and MOVD, i.e. setting the lowest element.
2102 static bool isMOVLMask(const SDOperand *Elts, unsigned NumElts) {
2103 if (NumElts != 2 && NumElts != 4)
2106 if (!isUndefOrEqual(Elts[0], NumElts))
2109 for (unsigned i = 1; i < NumElts; ++i) {
2110 if (!isUndefOrEqual(Elts[i], i))
2117 bool X86::isMOVLMask(SDNode *N) {
2118 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2119 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2122 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2123 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2124 /// element of vector 2 and the other elements to come from vector 1 in order.
2125 static bool isCommutedMOVL(const SDOperand *Ops, unsigned NumOps,
2126 bool V2IsSplat = false,
2127 bool V2IsUndef = false) {
2128 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2131 if (!isUndefOrEqual(Ops[0], 0))
2134 for (unsigned i = 1; i < NumOps; ++i) {
2135 SDOperand Arg = Ops[i];
2136 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2137 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2138 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2145 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2146 bool V2IsUndef = false) {
2147 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2148 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2149 V2IsSplat, V2IsUndef);
2152 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2153 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2154 bool X86::isMOVSHDUPMask(SDNode *N) {
2155 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2157 if (N->getNumOperands() != 4)
2160 // Expect 1, 1, 3, 3
2161 for (unsigned i = 0; i < 2; ++i) {
2162 SDOperand Arg = N->getOperand(i);
2163 if (Arg.getOpcode() == ISD::UNDEF) continue;
2164 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2165 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2166 if (Val != 1) return false;
2170 for (unsigned i = 2; i < 4; ++i) {
2171 SDOperand Arg = N->getOperand(i);
2172 if (Arg.getOpcode() == ISD::UNDEF) continue;
2173 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2174 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2175 if (Val != 3) return false;
2179 // Don't use movshdup if it can be done with a shufps.
2183 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2184 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2185 bool X86::isMOVSLDUPMask(SDNode *N) {
2186 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2188 if (N->getNumOperands() != 4)
2191 // Expect 0, 0, 2, 2
2192 for (unsigned i = 0; i < 2; ++i) {
2193 SDOperand Arg = N->getOperand(i);
2194 if (Arg.getOpcode() == ISD::UNDEF) continue;
2195 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2196 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2197 if (Val != 0) return false;
2201 for (unsigned i = 2; i < 4; ++i) {
2202 SDOperand Arg = N->getOperand(i);
2203 if (Arg.getOpcode() == ISD::UNDEF) continue;
2204 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2205 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2206 if (Val != 2) return false;
2210 // Don't use movshdup if it can be done with a shufps.
2214 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2215 /// specifies a identity operation on the LHS or RHS.
2216 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2217 unsigned NumElems = N->getNumOperands();
2218 for (unsigned i = 0; i < NumElems; ++i)
2219 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2224 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2225 /// a splat of a single element.
2226 static bool isSplatMask(SDNode *N) {
2227 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2229 // This is a splat operation if each element of the permute is the same, and
2230 // if the value doesn't reference the second vector.
2231 unsigned NumElems = N->getNumOperands();
2232 SDOperand ElementBase;
2234 for (; i != NumElems; ++i) {
2235 SDOperand Elt = N->getOperand(i);
2236 if (isa<ConstantSDNode>(Elt)) {
2242 if (!ElementBase.Val)
2245 for (; i != NumElems; ++i) {
2246 SDOperand Arg = N->getOperand(i);
2247 if (Arg.getOpcode() == ISD::UNDEF) continue;
2248 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2249 if (Arg != ElementBase) return false;
2252 // Make sure it is a splat of the first vector operand.
2253 return cast<ConstantSDNode>(ElementBase)->getValue() < NumElems;
2256 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2257 /// a splat of a single element and it's a 2 or 4 element mask.
2258 bool X86::isSplatMask(SDNode *N) {
2259 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2261 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2262 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2264 return ::isSplatMask(N);
2267 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2268 /// specifies a splat of zero element.
2269 bool X86::isSplatLoMask(SDNode *N) {
2270 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2272 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2273 if (!isUndefOrEqual(N->getOperand(i), 0))
2278 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2279 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2281 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2282 unsigned NumOperands = N->getNumOperands();
2283 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2285 for (unsigned i = 0; i < NumOperands; ++i) {
2287 SDOperand Arg = N->getOperand(NumOperands-i-1);
2288 if (Arg.getOpcode() != ISD::UNDEF)
2289 Val = cast<ConstantSDNode>(Arg)->getValue();
2290 if (Val >= NumOperands) Val -= NumOperands;
2292 if (i != NumOperands - 1)
2299 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2300 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2302 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2304 // 8 nodes, but we only care about the last 4.
2305 for (unsigned i = 7; i >= 4; --i) {
2307 SDOperand Arg = N->getOperand(i);
2308 if (Arg.getOpcode() != ISD::UNDEF)
2309 Val = cast<ConstantSDNode>(Arg)->getValue();
2318 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2319 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2321 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2323 // 8 nodes, but we only care about the first 4.
2324 for (int i = 3; i >= 0; --i) {
2326 SDOperand Arg = N->getOperand(i);
2327 if (Arg.getOpcode() != ISD::UNDEF)
2328 Val = cast<ConstantSDNode>(Arg)->getValue();
2337 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2338 /// specifies a 8 element shuffle that can be broken into a pair of
2339 /// PSHUFHW and PSHUFLW.
2340 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2341 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2343 if (N->getNumOperands() != 8)
2346 // Lower quadword shuffled.
2347 for (unsigned i = 0; i != 4; ++i) {
2348 SDOperand Arg = N->getOperand(i);
2349 if (Arg.getOpcode() == ISD::UNDEF) continue;
2350 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2351 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2356 // Upper quadword shuffled.
2357 for (unsigned i = 4; i != 8; ++i) {
2358 SDOperand Arg = N->getOperand(i);
2359 if (Arg.getOpcode() == ISD::UNDEF) continue;
2360 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2361 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2362 if (Val < 4 || Val > 7)
2369 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2370 /// values in ther permute mask.
2371 static SDOperand CommuteVectorShuffle(SDOperand Op, SDOperand &V1,
2372 SDOperand &V2, SDOperand &Mask,
2373 SelectionDAG &DAG) {
2374 MVT::ValueType VT = Op.getValueType();
2375 MVT::ValueType MaskVT = Mask.getValueType();
2376 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2377 unsigned NumElems = Mask.getNumOperands();
2378 SmallVector<SDOperand, 8> MaskVec;
2380 for (unsigned i = 0; i != NumElems; ++i) {
2381 SDOperand Arg = Mask.getOperand(i);
2382 if (Arg.getOpcode() == ISD::UNDEF) {
2383 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2386 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2387 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2389 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2391 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2395 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2396 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2399 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2400 /// the two vector operands have swapped position.
2402 SDOperand CommuteVectorShuffleMask(SDOperand Mask, SelectionDAG &DAG) {
2403 MVT::ValueType MaskVT = Mask.getValueType();
2404 MVT::ValueType EltVT = MVT::getVectorElementType(MaskVT);
2405 unsigned NumElems = Mask.getNumOperands();
2406 SmallVector<SDOperand, 8> MaskVec;
2407 for (unsigned i = 0; i != NumElems; ++i) {
2408 SDOperand Arg = Mask.getOperand(i);
2409 if (Arg.getOpcode() == ISD::UNDEF) {
2410 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2413 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2414 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2416 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2418 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2420 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2424 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2425 /// match movhlps. The lower half elements should come from upper half of
2426 /// V1 (and in order), and the upper half elements should come from the upper
2427 /// half of V2 (and in order).
2428 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2429 unsigned NumElems = Mask->getNumOperands();
2432 for (unsigned i = 0, e = 2; i != e; ++i)
2433 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2435 for (unsigned i = 2; i != 4; ++i)
2436 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2441 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2442 /// is promoted to a vector.
2443 static inline bool isScalarLoadToVector(SDNode *N) {
2444 if (N->getOpcode() == ISD::SCALAR_TO_VECTOR) {
2445 N = N->getOperand(0).Val;
2446 return ISD::isNON_EXTLoad(N);
2451 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2452 /// match movlp{s|d}. The lower half elements should come from lower half of
2453 /// V1 (and in order), and the upper half elements should come from the upper
2454 /// half of V2 (and in order). And since V1 will become the source of the
2455 /// MOVLP, it must be either a vector load or a scalar load to vector.
2456 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2457 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2459 // Is V2 is a vector load, don't do this transformation. We will try to use
2460 // load folding shufps op.
2461 if (ISD::isNON_EXTLoad(V2))
2464 unsigned NumElems = Mask->getNumOperands();
2465 if (NumElems != 2 && NumElems != 4)
2467 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2468 if (!isUndefOrEqual(Mask->getOperand(i), i))
2470 for (unsigned i = NumElems/2; i != NumElems; ++i)
2471 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2476 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2478 static bool isSplatVector(SDNode *N) {
2479 if (N->getOpcode() != ISD::BUILD_VECTOR)
2482 SDOperand SplatValue = N->getOperand(0);
2483 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2484 if (N->getOperand(i) != SplatValue)
2489 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2491 static bool isUndefShuffle(SDNode *N) {
2492 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2495 SDOperand V1 = N->getOperand(0);
2496 SDOperand V2 = N->getOperand(1);
2497 SDOperand Mask = N->getOperand(2);
2498 unsigned NumElems = Mask.getNumOperands();
2499 for (unsigned i = 0; i != NumElems; ++i) {
2500 SDOperand Arg = Mask.getOperand(i);
2501 if (Arg.getOpcode() != ISD::UNDEF) {
2502 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2503 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2505 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2512 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2514 static inline bool isZeroNode(SDOperand Elt) {
2515 return ((isa<ConstantSDNode>(Elt) &&
2516 cast<ConstantSDNode>(Elt)->getValue() == 0) ||
2517 (isa<ConstantFPSDNode>(Elt) &&
2518 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2521 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2522 /// to an zero vector.
2523 static bool isZeroShuffle(SDNode *N) {
2524 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2527 SDOperand V1 = N->getOperand(0);
2528 SDOperand V2 = N->getOperand(1);
2529 SDOperand Mask = N->getOperand(2);
2530 unsigned NumElems = Mask.getNumOperands();
2531 for (unsigned i = 0; i != NumElems; ++i) {
2532 SDOperand Arg = Mask.getOperand(i);
2533 if (Arg.getOpcode() == ISD::UNDEF)
2536 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
2537 if (Idx < NumElems) {
2538 unsigned Opc = V1.Val->getOpcode();
2539 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.Val))
2541 if (Opc != ISD::BUILD_VECTOR ||
2542 !isZeroNode(V1.Val->getOperand(Idx)))
2544 } else if (Idx >= NumElems) {
2545 unsigned Opc = V2.Val->getOpcode();
2546 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.Val))
2548 if (Opc != ISD::BUILD_VECTOR ||
2549 !isZeroNode(V2.Val->getOperand(Idx - NumElems)))
2556 /// getZeroVector - Returns a vector of specified type with all zero elements.
2558 static SDOperand getZeroVector(MVT::ValueType VT, SelectionDAG &DAG) {
2559 assert(MVT::isVector(VT) && "Expected a vector type");
2561 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2562 // type. This ensures they get CSE'd.
2563 SDOperand Cst = DAG.getTargetConstant(0, MVT::i32);
2565 if (MVT::getSizeInBits(VT) == 64) // MMX
2566 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2568 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2569 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2572 /// getOnesVector - Returns a vector of specified type with all bits set.
2574 static SDOperand getOnesVector(MVT::ValueType VT, SelectionDAG &DAG) {
2575 assert(MVT::isVector(VT) && "Expected a vector type");
2577 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2578 // type. This ensures they get CSE'd.
2579 SDOperand Cst = DAG.getTargetConstant(~0U, MVT::i32);
2581 if (MVT::getSizeInBits(VT) == 64) // MMX
2582 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2584 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2585 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2589 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2590 /// that point to V2 points to its first element.
2591 static SDOperand NormalizeMask(SDOperand Mask, SelectionDAG &DAG) {
2592 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2594 bool Changed = false;
2595 SmallVector<SDOperand, 8> MaskVec;
2596 unsigned NumElems = Mask.getNumOperands();
2597 for (unsigned i = 0; i != NumElems; ++i) {
2598 SDOperand Arg = Mask.getOperand(i);
2599 if (Arg.getOpcode() != ISD::UNDEF) {
2600 unsigned Val = cast<ConstantSDNode>(Arg)->getValue();
2601 if (Val > NumElems) {
2602 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2606 MaskVec.push_back(Arg);
2610 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2611 &MaskVec[0], MaskVec.size());
2615 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2616 /// operation of specified width.
2617 static SDOperand getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2618 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2619 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2621 SmallVector<SDOperand, 8> MaskVec;
2622 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2623 for (unsigned i = 1; i != NumElems; ++i)
2624 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2625 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2628 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2629 /// of specified width.
2630 static SDOperand getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2631 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2632 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2633 SmallVector<SDOperand, 8> MaskVec;
2634 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2635 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2636 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2638 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2641 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2642 /// of specified width.
2643 static SDOperand getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2644 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2645 MVT::ValueType BaseVT = MVT::getVectorElementType(MaskVT);
2646 unsigned Half = NumElems/2;
2647 SmallVector<SDOperand, 8> MaskVec;
2648 for (unsigned i = 0; i != Half; ++i) {
2649 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2650 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2652 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2655 /// PromoteSplat - Promote a splat of v8i16 or v16i8 to v4i32.
2657 static SDOperand PromoteSplat(SDOperand Op, SelectionDAG &DAG) {
2658 SDOperand V1 = Op.getOperand(0);
2659 SDOperand Mask = Op.getOperand(2);
2660 MVT::ValueType VT = Op.getValueType();
2661 unsigned NumElems = Mask.getNumOperands();
2662 Mask = getUnpacklMask(NumElems, DAG);
2663 while (NumElems != 4) {
2664 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2667 V1 = DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, V1);
2669 Mask = getZeroVector(MVT::v4i32, DAG);
2670 SDOperand Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32, V1,
2671 DAG.getNode(ISD::UNDEF, MVT::v4i32), Mask);
2672 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2675 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
2676 /// vector of zero or undef vector. This produces a shuffle where the low
2677 /// element of V2 is swizzled into the zero/undef vector, landing at element
2678 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
2679 static SDOperand getShuffleVectorZeroOrUndef(SDOperand V2, MVT::ValueType VT,
2680 unsigned NumElems, unsigned Idx,
2681 bool isZero, SelectionDAG &DAG) {
2682 SDOperand V1 = isZero ? getZeroVector(VT, DAG) : DAG.getNode(ISD::UNDEF, VT);
2683 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2684 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2685 SmallVector<SDOperand, 16> MaskVec;
2686 for (unsigned i = 0; i != NumElems; ++i)
2687 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
2688 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
2690 MaskVec.push_back(DAG.getConstant(i, EVT));
2691 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2692 &MaskVec[0], MaskVec.size());
2693 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2696 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
2698 static SDOperand LowerBuildVectorv16i8(SDOperand Op, unsigned NonZeros,
2699 unsigned NumNonZero, unsigned NumZero,
2700 SelectionDAG &DAG, TargetLowering &TLI) {
2706 for (unsigned i = 0; i < 16; ++i) {
2707 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
2708 if (ThisIsNonZero && First) {
2710 V = getZeroVector(MVT::v8i16, DAG);
2712 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2717 SDOperand ThisElt(0, 0), LastElt(0, 0);
2718 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
2719 if (LastIsNonZero) {
2720 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
2722 if (ThisIsNonZero) {
2723 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
2724 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
2725 ThisElt, DAG.getConstant(8, MVT::i8));
2727 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
2732 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
2733 DAG.getIntPtrConstant(i/2));
2737 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
2740 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
2742 static SDOperand LowerBuildVectorv8i16(SDOperand Op, unsigned NonZeros,
2743 unsigned NumNonZero, unsigned NumZero,
2744 SelectionDAG &DAG, TargetLowering &TLI) {
2750 for (unsigned i = 0; i < 8; ++i) {
2751 bool isNonZero = (NonZeros & (1 << i)) != 0;
2755 V = getZeroVector(MVT::v8i16, DAG);
2757 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
2760 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
2761 DAG.getIntPtrConstant(i));
2769 X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2770 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
2771 if (ISD::isBuildVectorAllZeros(Op.Val) || ISD::isBuildVectorAllOnes(Op.Val)) {
2772 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
2773 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
2774 // eliminated on x86-32 hosts.
2775 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
2778 if (ISD::isBuildVectorAllOnes(Op.Val))
2779 return getOnesVector(Op.getValueType(), DAG);
2780 return getZeroVector(Op.getValueType(), DAG);
2783 MVT::ValueType VT = Op.getValueType();
2784 MVT::ValueType EVT = MVT::getVectorElementType(VT);
2785 unsigned EVTBits = MVT::getSizeInBits(EVT);
2787 unsigned NumElems = Op.getNumOperands();
2788 unsigned NumZero = 0;
2789 unsigned NumNonZero = 0;
2790 unsigned NonZeros = 0;
2791 bool HasNonImms = false;
2792 SmallSet<SDOperand, 8> Values;
2793 for (unsigned i = 0; i < NumElems; ++i) {
2794 SDOperand Elt = Op.getOperand(i);
2795 if (Elt.getOpcode() == ISD::UNDEF)
2798 if (Elt.getOpcode() != ISD::Constant &&
2799 Elt.getOpcode() != ISD::ConstantFP)
2801 if (isZeroNode(Elt))
2804 NonZeros |= (1 << i);
2809 if (NumNonZero == 0) {
2810 // All undef vector. Return an UNDEF. All zero vectors were handled above.
2811 return DAG.getNode(ISD::UNDEF, VT);
2814 // Splat is obviously ok. Let legalizer expand it to a shuffle.
2815 if (Values.size() == 1)
2818 // Special case for single non-zero element.
2819 if (NumNonZero == 1 && NumElems <= 4) {
2820 unsigned Idx = CountTrailingZeros_32(NonZeros);
2821 SDOperand Item = Op.getOperand(Idx);
2822 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
2824 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
2825 return getShuffleVectorZeroOrUndef(Item, VT, NumElems, Idx,
2827 else if (!HasNonImms) // Otherwise, it's better to do a constpool load.
2830 if (EVTBits == 32) {
2831 // Turn it into a shuffle of zero and zero-extended scalar to vector.
2832 Item = getShuffleVectorZeroOrUndef(Item, VT, NumElems, 0, NumZero > 0,
2834 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2835 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2836 SmallVector<SDOperand, 8> MaskVec;
2837 for (unsigned i = 0; i < NumElems; i++)
2838 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
2839 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2840 &MaskVec[0], MaskVec.size());
2841 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
2842 DAG.getNode(ISD::UNDEF, VT), Mask);
2846 // A vector full of immediates; various special cases are already
2847 // handled, so this is best done with a single constant-pool load.
2851 // Let legalizer expand 2-wide build_vectors.
2855 // If element VT is < 32 bits, convert it to inserts into a zero vector.
2856 if (EVTBits == 8 && NumElems == 16) {
2857 SDOperand V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
2859 if (V.Val) return V;
2862 if (EVTBits == 16 && NumElems == 8) {
2863 SDOperand V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
2865 if (V.Val) return V;
2868 // If element VT is == 32 bits, turn it into a number of shuffles.
2869 SmallVector<SDOperand, 8> V;
2871 if (NumElems == 4 && NumZero > 0) {
2872 for (unsigned i = 0; i < 4; ++i) {
2873 bool isZero = !(NonZeros & (1 << i));
2875 V[i] = getZeroVector(VT, DAG);
2877 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2880 for (unsigned i = 0; i < 2; ++i) {
2881 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
2884 V[i] = V[i*2]; // Must be a zero vector.
2887 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
2888 getMOVLMask(NumElems, DAG));
2891 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2892 getMOVLMask(NumElems, DAG));
2895 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
2896 getUnpacklMask(NumElems, DAG));
2901 // Take advantage of the fact GR32 to VR128 scalar_to_vector (i.e. movd)
2902 // clears the upper bits.
2903 // FIXME: we can do the same for v4f32 case when we know both parts of
2904 // the lower half come from scalar_to_vector (loadf32). We should do
2905 // that in post legalizer dag combiner with target specific hooks.
2906 if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
2908 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2909 MVT::ValueType EVT = MVT::getVectorElementType(MaskVT);
2910 SmallVector<SDOperand, 8> MaskVec;
2911 bool Reverse = (NonZeros & 0x3) == 2;
2912 for (unsigned i = 0; i < 2; ++i)
2914 MaskVec.push_back(DAG.getConstant(1-i, EVT));
2916 MaskVec.push_back(DAG.getConstant(i, EVT));
2917 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
2918 for (unsigned i = 0; i < 2; ++i)
2920 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
2922 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
2923 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
2924 &MaskVec[0], MaskVec.size());
2925 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
2928 if (Values.size() > 2) {
2929 // Expand into a number of unpckl*.
2931 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
2932 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
2933 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
2934 SDOperand UnpckMask = getUnpacklMask(NumElems, DAG);
2935 for (unsigned i = 0; i < NumElems; ++i)
2936 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
2938 while (NumElems != 0) {
2939 for (unsigned i = 0; i < NumElems; ++i)
2940 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
2951 SDOperand LowerVECTOR_SHUFFLEv8i16(SDOperand V1, SDOperand V2,
2952 SDOperand PermMask, SelectionDAG &DAG,
2953 TargetLowering &TLI) {
2955 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(8);
2956 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
2957 MVT::ValueType PtrVT = TLI.getPointerTy();
2958 SmallVector<SDOperand, 8> MaskElts(PermMask.Val->op_begin(),
2959 PermMask.Val->op_end());
2961 // First record which half of which vector the low elements come from.
2962 SmallVector<unsigned, 4> LowQuad(4);
2963 for (unsigned i = 0; i < 4; ++i) {
2964 SDOperand Elt = MaskElts[i];
2965 if (Elt.getOpcode() == ISD::UNDEF)
2967 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
2968 int QuadIdx = EltIdx / 4;
2971 int BestLowQuad = -1;
2972 unsigned MaxQuad = 1;
2973 for (unsigned i = 0; i < 4; ++i) {
2974 if (LowQuad[i] > MaxQuad) {
2976 MaxQuad = LowQuad[i];
2980 // Record which half of which vector the high elements come from.
2981 SmallVector<unsigned, 4> HighQuad(4);
2982 for (unsigned i = 4; i < 8; ++i) {
2983 SDOperand Elt = MaskElts[i];
2984 if (Elt.getOpcode() == ISD::UNDEF)
2986 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
2987 int QuadIdx = EltIdx / 4;
2988 ++HighQuad[QuadIdx];
2990 int BestHighQuad = -1;
2992 for (unsigned i = 0; i < 4; ++i) {
2993 if (HighQuad[i] > MaxQuad) {
2995 MaxQuad = HighQuad[i];
2999 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3000 if (BestLowQuad != -1 || BestHighQuad != -1) {
3001 // First sort the 4 chunks in order using shufpd.
3002 SmallVector<SDOperand, 8> MaskVec;
3003 if (BestLowQuad != -1)
3004 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3006 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3007 if (BestHighQuad != -1)
3008 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3010 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3011 SDOperand Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3012 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3013 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3014 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3015 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3017 // Now sort high and low parts separately.
3018 BitVector InOrder(8);
3019 if (BestLowQuad != -1) {
3020 // Sort lower half in order using PSHUFLW.
3022 bool AnyOutOrder = false;
3023 for (unsigned i = 0; i != 4; ++i) {
3024 SDOperand Elt = MaskElts[i];
3025 if (Elt.getOpcode() == ISD::UNDEF) {
3026 MaskVec.push_back(Elt);
3029 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3032 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3033 // If this element is in the right place after this shuffle, then
3035 if ((int)(EltIdx / 4) == BestLowQuad)
3040 for (unsigned i = 4; i != 8; ++i)
3041 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3042 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3043 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3047 if (BestHighQuad != -1) {
3048 // Sort high half in order using PSHUFHW if possible.
3050 for (unsigned i = 0; i != 4; ++i)
3051 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3052 bool AnyOutOrder = false;
3053 for (unsigned i = 4; i != 8; ++i) {
3054 SDOperand Elt = MaskElts[i];
3055 if (Elt.getOpcode() == ISD::UNDEF) {
3056 MaskVec.push_back(Elt);
3059 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3062 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3063 // If this element is in the right place after this shuffle, then
3065 if ((int)(EltIdx / 4) == BestHighQuad)
3070 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3071 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3075 // The other elements are put in the right place using pextrw and pinsrw.
3076 for (unsigned i = 0; i != 8; ++i) {
3079 SDOperand Elt = MaskElts[i];
3080 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3083 SDOperand ExtOp = (EltIdx < 8)
3084 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3085 DAG.getConstant(EltIdx, PtrVT))
3086 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3087 DAG.getConstant(EltIdx - 8, PtrVT));
3088 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3089 DAG.getConstant(i, PtrVT));
3094 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use
3095 ///as few as possible.
3096 // First, let's find out how many elements are already in the right order.
3097 unsigned V1InOrder = 0;
3098 unsigned V1FromV1 = 0;
3099 unsigned V2InOrder = 0;
3100 unsigned V2FromV2 = 0;
3101 SmallVector<SDOperand, 8> V1Elts;
3102 SmallVector<SDOperand, 8> V2Elts;
3103 for (unsigned i = 0; i < 8; ++i) {
3104 SDOperand Elt = MaskElts[i];
3105 if (Elt.getOpcode() == ISD::UNDEF) {
3106 V1Elts.push_back(Elt);
3107 V2Elts.push_back(Elt);
3112 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3114 V1Elts.push_back(Elt);
3115 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3117 } else if (EltIdx == i+8) {
3118 V1Elts.push_back(Elt);
3119 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3121 } else if (EltIdx < 8) {
3122 V1Elts.push_back(Elt);
3125 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3130 if (V2InOrder > V1InOrder) {
3131 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3133 std::swap(V1Elts, V2Elts);
3134 std::swap(V1FromV1, V2FromV2);
3137 if ((V1FromV1 + V1InOrder) != 8) {
3138 // Some elements are from V2.
3140 // If there are elements that are from V1 but out of place,
3141 // then first sort them in place
3142 SmallVector<SDOperand, 8> MaskVec;
3143 for (unsigned i = 0; i < 8; ++i) {
3144 SDOperand Elt = V1Elts[i];
3145 if (Elt.getOpcode() == ISD::UNDEF) {
3146 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3149 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3151 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3153 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3155 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3156 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3160 for (unsigned i = 0; i < 8; ++i) {
3161 SDOperand Elt = V1Elts[i];
3162 if (Elt.getOpcode() == ISD::UNDEF)
3164 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3167 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3168 DAG.getConstant(EltIdx - 8, PtrVT));
3169 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3170 DAG.getConstant(i, PtrVT));
3174 // All elements are from V1.
3176 for (unsigned i = 0; i < 8; ++i) {
3177 SDOperand Elt = V1Elts[i];
3178 if (Elt.getOpcode() == ISD::UNDEF)
3180 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3181 SDOperand ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3182 DAG.getConstant(EltIdx, PtrVT));
3183 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3184 DAG.getConstant(i, PtrVT));
3190 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3191 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3192 /// done when every pair / quad of shuffle mask elements point to elements in
3193 /// the right sequence. e.g.
3194 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3196 SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
3198 SDOperand PermMask, SelectionDAG &DAG,
3199 TargetLowering &TLI) {
3200 unsigned NumElems = PermMask.getNumOperands();
3201 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3202 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3203 MVT::ValueType NewVT = MaskVT;
3205 case MVT::v4f32: NewVT = MVT::v2f64; break;
3206 case MVT::v4i32: NewVT = MVT::v2i64; break;
3207 case MVT::v8i16: NewVT = MVT::v4i32; break;
3208 case MVT::v16i8: NewVT = MVT::v4i32; break;
3209 default: assert(false && "Unexpected!");
3213 if (MVT::isInteger(VT))
3217 unsigned Scale = NumElems / NewWidth;
3218 SmallVector<SDOperand, 8> MaskVec;
3219 for (unsigned i = 0; i < NumElems; i += Scale) {
3220 unsigned StartIdx = ~0U;
3221 for (unsigned j = 0; j < Scale; ++j) {
3222 SDOperand Elt = PermMask.getOperand(i+j);
3223 if (Elt.getOpcode() == ISD::UNDEF)
3225 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getValue();
3226 if (StartIdx == ~0U)
3227 StartIdx = EltIdx - (EltIdx % Scale);
3228 if (EltIdx != StartIdx + j)
3231 if (StartIdx == ~0U)
3232 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3234 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
3237 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3238 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3239 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3240 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3241 &MaskVec[0], MaskVec.size()));
3245 X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
3246 SDOperand V1 = Op.getOperand(0);
3247 SDOperand V2 = Op.getOperand(1);
3248 SDOperand PermMask = Op.getOperand(2);
3249 MVT::ValueType VT = Op.getValueType();
3250 unsigned NumElems = PermMask.getNumOperands();
3251 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3252 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3253 bool V1IsSplat = false;
3254 bool V2IsSplat = false;
3256 if (isUndefShuffle(Op.Val))
3257 return DAG.getNode(ISD::UNDEF, VT);
3259 if (isZeroShuffle(Op.Val))
3260 return getZeroVector(VT, DAG);
3262 if (isIdentityMask(PermMask.Val))
3264 else if (isIdentityMask(PermMask.Val, true))
3267 if (isSplatMask(PermMask.Val)) {
3268 if (NumElems <= 4) return Op;
3269 // Promote it to a v4i32 splat.
3270 return PromoteSplat(Op, DAG);
3273 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3275 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3276 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3278 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3279 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3280 // FIXME: Figure out a cleaner way to do this.
3281 // Try to make use of movq to zero out the top part.
3282 if (ISD::isBuildVectorAllZeros(V2.Val)) {
3283 SDOperand NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3285 SDOperand NewV1 = NewOp.getOperand(0);
3286 SDOperand NewV2 = NewOp.getOperand(1);
3287 SDOperand NewMask = NewOp.getOperand(2);
3288 if (isCommutedMOVL(NewMask.Val, true, false)) {
3289 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
3290 NewOp = DAG.getNode(ISD::VECTOR_SHUFFLE, NewOp.getValueType(),
3291 NewV1, NewV2, getMOVLMask(2, DAG));
3292 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3295 } else if (ISD::isBuildVectorAllZeros(V1.Val)) {
3296 SDOperand NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3297 if (NewOp.Val && X86::isMOVLMask(NewOp.getOperand(2).Val))
3298 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3302 if (X86::isMOVLMask(PermMask.Val))
3303 return (V1IsUndef) ? V2 : Op;
3305 if (X86::isMOVSHDUPMask(PermMask.Val) ||
3306 X86::isMOVSLDUPMask(PermMask.Val) ||
3307 X86::isMOVHLPSMask(PermMask.Val) ||
3308 X86::isMOVHPMask(PermMask.Val) ||
3309 X86::isMOVLPMask(PermMask.Val))
3312 if (ShouldXformToMOVHLPS(PermMask.Val) ||
3313 ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
3314 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3316 bool Commuted = false;
3317 // FIXME: This should also accept a bitcast of a splat? Be careful, not
3318 // 1,1,1,1 -> v8i16 though.
3319 V1IsSplat = isSplatVector(V1.Val);
3320 V2IsSplat = isSplatVector(V2.Val);
3322 // Canonicalize the splat or undef, if present, to be on the RHS.
3323 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
3324 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3325 std::swap(V1IsSplat, V2IsSplat);
3326 std::swap(V1IsUndef, V2IsUndef);
3330 // FIXME: Figure out a cleaner way to do this.
3331 if (isCommutedMOVL(PermMask.Val, V2IsSplat, V2IsUndef)) {
3332 if (V2IsUndef) return V1;
3333 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3335 // V2 is a splat, so the mask may be malformed. That is, it may point
3336 // to any V2 element. The instruction selectior won't like this. Get
3337 // a corrected mask and commute to form a proper MOVS{S|D}.
3338 SDOperand NewMask = getMOVLMask(NumElems, DAG);
3339 if (NewMask.Val != PermMask.Val)
3340 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3345 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3346 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3347 X86::isUNPCKLMask(PermMask.Val) ||
3348 X86::isUNPCKHMask(PermMask.Val))
3352 // Normalize mask so all entries that point to V2 points to its first
3353 // element then try to match unpck{h|l} again. If match, return a
3354 // new vector_shuffle with the corrected mask.
3355 SDOperand NewMask = NormalizeMask(PermMask, DAG);
3356 if (NewMask.Val != PermMask.Val) {
3357 if (X86::isUNPCKLMask(PermMask.Val, true)) {
3358 SDOperand NewMask = getUnpacklMask(NumElems, DAG);
3359 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3360 } else if (X86::isUNPCKHMask(PermMask.Val, true)) {
3361 SDOperand NewMask = getUnpackhMask(NumElems, DAG);
3362 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
3367 // Normalize the node to match x86 shuffle ops if needed
3368 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.Val))
3369 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3372 // Commute is back and try unpck* again.
3373 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
3374 if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
3375 X86::isUNPCKH_v_undef_Mask(PermMask.Val) ||
3376 X86::isUNPCKLMask(PermMask.Val) ||
3377 X86::isUNPCKHMask(PermMask.Val))
3381 // If VT is integer, try PSHUF* first, then SHUFP*.
3382 if (MVT::isInteger(VT)) {
3383 // MMX doesn't have PSHUFD; it does have PSHUFW. While it's theoretically
3384 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
3385 if (((MVT::getSizeInBits(VT) != 64 || NumElems == 4) &&
3386 X86::isPSHUFDMask(PermMask.Val)) ||
3387 X86::isPSHUFHWMask(PermMask.Val) ||
3388 X86::isPSHUFLWMask(PermMask.Val)) {
3389 if (V2.getOpcode() != ISD::UNDEF)
3390 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3391 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3395 if (X86::isSHUFPMask(PermMask.Val) &&
3396 MVT::getSizeInBits(VT) != 64) // Don't do this for MMX.
3399 // Floating point cases in the other order.
3400 if (X86::isSHUFPMask(PermMask.Val))
3402 if (X86::isPSHUFDMask(PermMask.Val) ||
3403 X86::isPSHUFHWMask(PermMask.Val) ||
3404 X86::isPSHUFLWMask(PermMask.Val)) {
3405 if (V2.getOpcode() != ISD::UNDEF)
3406 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
3407 DAG.getNode(ISD::UNDEF, V1.getValueType()),PermMask);
3412 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
3413 if (VT == MVT::v8i16) {
3414 SDOperand NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
3419 // Handle all 4 wide cases with a number of shuffles.
3420 if (NumElems == 4 && MVT::getSizeInBits(VT) != 64) {
3421 // Don't do this for MMX.
3422 MVT::ValueType MaskVT = PermMask.getValueType();
3423 MVT::ValueType MaskEVT = MVT::getVectorElementType(MaskVT);
3424 SmallVector<std::pair<int, int>, 8> Locs;
3425 Locs.reserve(NumElems);
3426 SmallVector<SDOperand, 8> Mask1(NumElems,
3427 DAG.getNode(ISD::UNDEF, MaskEVT));
3428 SmallVector<SDOperand, 8> Mask2(NumElems,
3429 DAG.getNode(ISD::UNDEF, MaskEVT));
3432 // If no more than two elements come from either vector. This can be
3433 // implemented with two shuffles. First shuffle gather the elements.
3434 // The second shuffle, which takes the first shuffle as both of its
3435 // vector operands, put the elements into the right order.
3436 for (unsigned i = 0; i != NumElems; ++i) {
3437 SDOperand Elt = PermMask.getOperand(i);
3438 if (Elt.getOpcode() == ISD::UNDEF) {
3439 Locs[i] = std::make_pair(-1, -1);
3441 unsigned Val = cast<ConstantSDNode>(Elt)->getValue();
3442 if (Val < NumElems) {
3443 Locs[i] = std::make_pair(0, NumLo);
3447 Locs[i] = std::make_pair(1, NumHi);
3448 if (2+NumHi < NumElems)
3449 Mask1[2+NumHi] = Elt;
3454 if (NumLo <= 2 && NumHi <= 2) {
3455 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3456 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3457 &Mask1[0], Mask1.size()));
3458 for (unsigned i = 0; i != NumElems; ++i) {
3459 if (Locs[i].first == -1)
3462 unsigned Idx = (i < NumElems/2) ? 0 : NumElems;
3463 Idx += Locs[i].first * (NumElems/2) + Locs[i].second;
3464 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3468 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3469 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3470 &Mask2[0], Mask2.size()));
3473 // Break it into (shuffle shuffle_hi, shuffle_lo).
3475 SmallVector<SDOperand,8> LoMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3476 SmallVector<SDOperand,8> HiMask(NumElems, DAG.getNode(ISD::UNDEF, MaskEVT));
3477 SmallVector<SDOperand,8> *MaskPtr = &LoMask;
3478 unsigned MaskIdx = 0;
3480 unsigned HiIdx = NumElems/2;
3481 for (unsigned i = 0; i != NumElems; ++i) {
3482 if (i == NumElems/2) {
3488 SDOperand Elt = PermMask.getOperand(i);
3489 if (Elt.getOpcode() == ISD::UNDEF) {
3490 Locs[i] = std::make_pair(-1, -1);
3491 } else if (cast<ConstantSDNode>(Elt)->getValue() < NumElems) {
3492 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3493 (*MaskPtr)[LoIdx] = Elt;
3496 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3497 (*MaskPtr)[HiIdx] = Elt;
3502 SDOperand LoShuffle =
3503 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3504 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3505 &LoMask[0], LoMask.size()));
3506 SDOperand HiShuffle =
3507 DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3508 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3509 &HiMask[0], HiMask.size()));
3510 SmallVector<SDOperand, 8> MaskOps;
3511 for (unsigned i = 0; i != NumElems; ++i) {
3512 if (Locs[i].first == -1) {
3513 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3515 unsigned Idx = Locs[i].first * NumElems + Locs[i].second;
3516 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3519 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3520 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3521 &MaskOps[0], MaskOps.size()));
3528 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3529 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3532 MVT::ValueType VT = Op.getValueType();
3533 // TODO: handle v16i8.
3534 if (MVT::getSizeInBits(VT) == 16) {
3535 SDOperand Vec = Op.getOperand(0);
3536 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3538 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
3539 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
3540 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
3542 // Transform it so it match pextrw which produces a 32-bit result.
3543 MVT::ValueType EVT = (MVT::ValueType)(VT+1);
3544 SDOperand Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
3545 Op.getOperand(0), Op.getOperand(1));
3546 SDOperand Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
3547 DAG.getValueType(VT));
3548 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
3549 } else if (MVT::getSizeInBits(VT) == 32) {
3550 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3553 // SHUFPS the element to the lowest double word, then movss.
3554 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3555 SmallVector<SDOperand, 8> IdxVec;
3557 push_back(DAG.getConstant(Idx, MVT::getVectorElementType(MaskVT)));
3559 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3561 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3563 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3564 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3565 &IdxVec[0], IdxVec.size());
3566 SDOperand Vec = Op.getOperand(0);
3567 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3568 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3569 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3570 DAG.getIntPtrConstant(0));
3571 } else if (MVT::getSizeInBits(VT) == 64) {
3572 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
3576 // UNPCKHPD the element to the lowest double word, then movsd.
3577 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
3578 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
3579 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(4);
3580 SmallVector<SDOperand, 8> IdxVec;
3581 IdxVec.push_back(DAG.getConstant(1, MVT::getVectorElementType(MaskVT)));
3583 push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(MaskVT)));
3584 SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3585 &IdxVec[0], IdxVec.size());
3586 SDOperand Vec = Op.getOperand(0);
3587 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
3588 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
3589 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
3590 DAG.getIntPtrConstant(0));
3597 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
3598 MVT::ValueType VT = Op.getValueType();
3599 MVT::ValueType EVT = MVT::getVectorElementType(VT);
3603 SDOperand N0 = Op.getOperand(0);
3604 SDOperand N1 = Op.getOperand(1);
3605 SDOperand N2 = Op.getOperand(2);
3607 if (MVT::getSizeInBits(EVT) == 16) {
3608 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
3609 // as its second argument.
3610 if (N1.getValueType() != MVT::i32)
3611 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
3612 if (N2.getValueType() != MVT::i32)
3613 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getValue());
3614 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
3620 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
3621 SDOperand AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
3622 return DAG.getNode(X86ISD::S2VEC, Op.getValueType(), AnyExt);
3625 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
3626 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
3627 // one of the above mentioned nodes. It has to be wrapped because otherwise
3628 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
3629 // be used to form addressing mode. These wrapped nodes will be selected
3632 X86TargetLowering::LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
3633 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
3634 SDOperand Result = DAG.getTargetConstantPool(CP->getConstVal(),
3636 CP->getAlignment());
3637 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3638 // With PIC, the address is actually $g + Offset.
3639 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3640 !Subtarget->isPICStyleRIPRel()) {
3641 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3642 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3650 X86TargetLowering::LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
3651 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
3652 SDOperand Result = DAG.getTargetGlobalAddress(GV, getPointerTy());
3653 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3654 // With PIC, the address is actually $g + Offset.
3655 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3656 !Subtarget->isPICStyleRIPRel()) {
3657 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3658 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3662 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
3663 // load the value at address GV, not the value of GV itself. This means that
3664 // the GlobalAddress must be in the base or index register of the address, not
3665 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
3666 // The same applies for external symbols during PIC codegen
3667 if (Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false))
3668 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result, NULL, 0);
3673 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
3675 LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3676 const MVT::ValueType PtrVT) {
3678 SDOperand Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
3679 DAG.getNode(X86ISD::GlobalBaseReg,
3681 InFlag = Chain.getValue(1);
3683 // emit leal symbol@TLSGD(,%ebx,1), %eax
3684 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
3685 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3686 GA->getValueType(0),
3688 SDOperand Ops[] = { Chain, TGA, InFlag };
3689 SDOperand Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
3690 InFlag = Result.getValue(2);
3691 Chain = Result.getValue(1);
3693 // call ___tls_get_addr. This function receives its argument in
3694 // the register EAX.
3695 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
3696 InFlag = Chain.getValue(1);
3698 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
3699 SDOperand Ops1[] = { Chain,
3700 DAG.getTargetExternalSymbol("___tls_get_addr",
3702 DAG.getRegister(X86::EAX, PtrVT),
3703 DAG.getRegister(X86::EBX, PtrVT),
3705 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
3706 InFlag = Chain.getValue(1);
3708 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
3711 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
3712 // "local exec" model.
3714 LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
3715 const MVT::ValueType PtrVT) {
3716 // Get the Thread Pointer
3717 SDOperand ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
3718 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
3720 SDOperand TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
3721 GA->getValueType(0),
3723 SDOperand Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
3725 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
3726 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset, NULL, 0);
3728 // The address of the thread local variable is the add of the thread
3729 // pointer with the offset of the variable.
3730 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
3734 X86TargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
3735 // TODO: implement the "local dynamic" model
3736 // TODO: implement the "initial exec"model for pic executables
3737 assert(!Subtarget->is64Bit() && Subtarget->isTargetELF() &&
3738 "TLS not implemented for non-ELF and 64-bit targets");
3739 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
3740 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
3741 // otherwise use the "Local Exec"TLS Model
3742 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
3743 return LowerToTLSGeneralDynamicModel(GA, DAG, getPointerTy());
3745 return LowerToTLSExecModel(GA, DAG, getPointerTy());
3749 X86TargetLowering::LowerExternalSymbol(SDOperand Op, SelectionDAG &DAG) {
3750 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
3751 SDOperand Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
3752 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3753 // With PIC, the address is actually $g + Offset.
3754 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3755 !Subtarget->isPICStyleRIPRel()) {
3756 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3757 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3764 SDOperand X86TargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
3765 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
3766 SDOperand Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
3767 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
3768 // With PIC, the address is actually $g + Offset.
3769 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
3770 !Subtarget->isPICStyleRIPRel()) {
3771 Result = DAG.getNode(ISD::ADD, getPointerTy(),
3772 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
3779 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
3780 /// take a 2 x i32 value to shift plus a shift amount.
3781 SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
3782 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
3783 "Not an i64 shift!");
3784 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
3785 SDOperand ShOpLo = Op.getOperand(0);
3786 SDOperand ShOpHi = Op.getOperand(1);
3787 SDOperand ShAmt = Op.getOperand(2);
3788 SDOperand Tmp1 = isSRA ?
3789 DAG.getNode(ISD::SRA, MVT::i32, ShOpHi, DAG.getConstant(31, MVT::i8)) :
3790 DAG.getConstant(0, MVT::i32);
3792 SDOperand Tmp2, Tmp3;
3793 if (Op.getOpcode() == ISD::SHL_PARTS) {
3794 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
3795 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
3797 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
3798 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
3801 const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::Other, MVT::Flag);
3802 SDOperand AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
3803 DAG.getConstant(32, MVT::i8));
3804 SDOperand Cond = DAG.getNode(X86ISD::CMP, MVT::i32,
3805 AndNode, DAG.getConstant(0, MVT::i8));
3808 SDOperand CC = DAG.getConstant(X86::COND_NE, MVT::i8);
3809 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::Flag);
3810 SmallVector<SDOperand, 4> Ops;
3811 if (Op.getOpcode() == ISD::SHL_PARTS) {
3812 Ops.push_back(Tmp2);
3813 Ops.push_back(Tmp3);
3815 Ops.push_back(Cond);
3816 Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3819 Ops.push_back(Tmp3);
3820 Ops.push_back(Tmp1);
3822 Ops.push_back(Cond);
3823 Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3825 Ops.push_back(Tmp2);
3826 Ops.push_back(Tmp3);
3828 Ops.push_back(Cond);
3829 Lo = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3832 Ops.push_back(Tmp3);
3833 Ops.push_back(Tmp1);
3835 Ops.push_back(Cond);
3836 Hi = DAG.getNode(X86ISD::CMOV, MVT::i32, &Ops[0], Ops.size());
3839 VTs = DAG.getNodeValueTypes(MVT::i32, MVT::i32);
3843 return DAG.getNode(ISD::MERGE_VALUES, VTs, 2, &Ops[0], Ops.size());
3846 SDOperand X86TargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
3847 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
3848 Op.getOperand(0).getValueType() >= MVT::i16 &&
3849 "Unknown SINT_TO_FP to lower!");
3852 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3853 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
3854 MachineFunction &MF = DAG.getMachineFunction();
3855 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
3856 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3857 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
3858 StackSlot, NULL, 0);
3860 // These are really Legal; caller falls through into that case.
3861 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
3863 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
3864 Subtarget->is64Bit())
3869 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
3871 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
3873 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
3874 SmallVector<SDOperand, 8> Ops;
3875 Ops.push_back(Chain);
3876 Ops.push_back(StackSlot);
3877 Ops.push_back(DAG.getValueType(SrcVT));
3878 Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
3879 Tys, &Ops[0], Ops.size());
3882 Chain = Result.getValue(1);
3883 SDOperand InFlag = Result.getValue(2);
3885 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
3886 // shouldn't be necessary except that RFP cannot be live across
3887 // multiple blocks. When stackifier is fixed, they can be uncoupled.
3888 MachineFunction &MF = DAG.getMachineFunction();
3889 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3890 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3891 Tys = DAG.getVTList(MVT::Other);
3892 SmallVector<SDOperand, 8> Ops;
3893 Ops.push_back(Chain);
3894 Ops.push_back(Result);
3895 Ops.push_back(StackSlot);
3896 Ops.push_back(DAG.getValueType(Op.getValueType()));
3897 Ops.push_back(InFlag);
3898 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
3899 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot, NULL, 0);
3905 std::pair<SDOperand,SDOperand> X86TargetLowering::
3906 FP_TO_SINTHelper(SDOperand Op, SelectionDAG &DAG) {
3907 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
3908 "Unknown FP_TO_SINT to lower!");
3910 // These are really Legal.
3911 if (Op.getValueType() == MVT::i32 &&
3912 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
3913 return std::make_pair(SDOperand(), SDOperand());
3914 if (Subtarget->is64Bit() &&
3915 Op.getValueType() == MVT::i64 &&
3916 Op.getOperand(0).getValueType() != MVT::f80)
3917 return std::make_pair(SDOperand(), SDOperand());
3919 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
3921 MachineFunction &MF = DAG.getMachineFunction();
3922 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
3923 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3924 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3926 switch (Op.getValueType()) {
3927 default: assert(0 && "Invalid FP_TO_SINT to lower!");
3928 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
3929 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
3930 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
3933 SDOperand Chain = DAG.getEntryNode();
3934 SDOperand Value = Op.getOperand(0);
3935 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
3936 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
3937 Chain = DAG.getStore(Chain, Value, StackSlot, NULL, 0);
3938 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
3940 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
3942 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
3943 Chain = Value.getValue(1);
3944 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
3945 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
3948 // Build the FP_TO_INT*_IN_MEM
3949 SDOperand Ops[] = { Chain, Value, StackSlot };
3950 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
3952 return std::make_pair(FIST, StackSlot);
3955 SDOperand X86TargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
3956 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(Op, DAG);
3957 SDOperand FIST = Vals.first, StackSlot = Vals.second;
3958 if (FIST.Val == 0) return SDOperand();
3961 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
3964 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
3965 std::pair<SDOperand,SDOperand> Vals = FP_TO_SINTHelper(SDOperand(N, 0), DAG);
3966 SDOperand FIST = Vals.first, StackSlot = Vals.second;
3967 if (FIST.Val == 0) return 0;
3969 // Return an i64 load from the stack slot.
3970 SDOperand Res = DAG.getLoad(MVT::i64, FIST, StackSlot, NULL, 0);
3972 // Use a MERGE_VALUES node to drop the chain result value.
3973 return DAG.getNode(ISD::MERGE_VALUES, MVT::i64, Res).Val;
3976 SDOperand X86TargetLowering::LowerFABS(SDOperand Op, SelectionDAG &DAG) {
3977 MVT::ValueType VT = Op.getValueType();
3978 MVT::ValueType EltVT = VT;
3979 if (MVT::isVector(VT))
3980 EltVT = MVT::getVectorElementType(VT);
3981 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
3982 std::vector<Constant*> CV;
3983 if (EltVT == MVT::f64) {
3984 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, ~(1ULL << 63))));
3988 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, ~(1U << 31))));
3994 Constant *C = ConstantVector::get(CV);
3995 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
3996 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
3998 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4001 SDOperand X86TargetLowering::LowerFNEG(SDOperand Op, SelectionDAG &DAG) {
4002 MVT::ValueType VT = Op.getValueType();
4003 MVT::ValueType EltVT = VT;
4004 unsigned EltNum = 1;
4005 if (MVT::isVector(VT)) {
4006 EltVT = MVT::getVectorElementType(VT);
4007 EltNum = MVT::getVectorNumElements(VT);
4009 const Type *OpNTy = MVT::getTypeForValueType(EltVT);
4010 std::vector<Constant*> CV;
4011 if (EltVT == MVT::f64) {
4012 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(64, 1ULL << 63)));
4016 Constant *C = ConstantFP::get(OpNTy, APFloat(APInt(32, 1U << 31)));
4022 Constant *C = ConstantVector::get(CV);
4023 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4024 SDOperand Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4026 if (MVT::isVector(VT)) {
4027 return DAG.getNode(ISD::BIT_CONVERT, VT,
4028 DAG.getNode(ISD::XOR, MVT::v2i64,
4029 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4030 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4032 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4036 SDOperand X86TargetLowering::LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
4037 SDOperand Op0 = Op.getOperand(0);
4038 SDOperand Op1 = Op.getOperand(1);
4039 MVT::ValueType VT = Op.getValueType();
4040 MVT::ValueType SrcVT = Op1.getValueType();
4041 const Type *SrcTy = MVT::getTypeForValueType(SrcVT);
4043 // If second operand is smaller, extend it first.
4044 if (MVT::getSizeInBits(SrcVT) < MVT::getSizeInBits(VT)) {
4045 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4047 SrcTy = MVT::getTypeForValueType(SrcVT);
4049 // And if it is bigger, shrink it first.
4050 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4051 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4053 SrcTy = MVT::getTypeForValueType(SrcVT);
4056 // At this point the operands and the result should have the same
4057 // type, and that won't be f80 since that is not custom lowered.
4059 // First get the sign bit of second operand.
4060 std::vector<Constant*> CV;
4061 if (SrcVT == MVT::f64) {
4062 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 1ULL << 63))));
4063 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
4065 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 1U << 31))));
4066 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4067 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4068 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4070 Constant *C = ConstantVector::get(CV);
4071 SDOperand CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4072 SDOperand Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx, NULL, 0,
4074 SDOperand SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4076 // Shift sign bit right or left if the two operands have different types.
4077 if (MVT::getSizeInBits(SrcVT) > MVT::getSizeInBits(VT)) {
4078 // Op0 is MVT::f32, Op1 is MVT::f64.
4079 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4080 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4081 DAG.getConstant(32, MVT::i32));
4082 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4083 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4084 DAG.getIntPtrConstant(0));
4087 // Clear first operand sign bit.
4089 if (VT == MVT::f64) {
4090 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, ~(1ULL << 63)))));
4091 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(64, 0))));
4093 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, ~(1U << 31)))));
4094 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4095 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4096 CV.push_back(ConstantFP::get(SrcTy, APFloat(APInt(32, 0))));
4098 C = ConstantVector::get(CV);
4099 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4100 SDOperand Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0,
4102 SDOperand Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4104 // Or the value with the sign bit.
4105 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4108 SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
4109 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4111 SDOperand Op0 = Op.getOperand(0);
4112 SDOperand Op1 = Op.getOperand(1);
4113 SDOperand CC = Op.getOperand(2);
4114 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4115 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
4118 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4120 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4121 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4122 DAG.getConstant(X86CC, MVT::i8), Cond);
4125 assert(isFP && "Illegal integer SetCC!");
4127 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4128 switch (SetCCOpcode) {
4129 default: assert(false && "Illegal floating point SetCC!");
4130 case ISD::SETOEQ: { // !PF & ZF
4131 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4132 DAG.getConstant(X86::COND_NP, MVT::i8), Cond);
4133 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4134 DAG.getConstant(X86::COND_E, MVT::i8), Cond);
4135 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
4137 case ISD::SETUNE: { // PF | !ZF
4138 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4139 DAG.getConstant(X86::COND_P, MVT::i8), Cond);
4140 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
4141 DAG.getConstant(X86::COND_NE, MVT::i8), Cond);
4142 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
4148 SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
4149 bool addTest = true;
4150 SDOperand Cond = Op.getOperand(0);
4153 if (Cond.getOpcode() == ISD::SETCC)
4154 Cond = LowerSETCC(Cond, DAG);
4156 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4157 // setting operand in place of the X86ISD::SETCC.
4158 if (Cond.getOpcode() == X86ISD::SETCC) {
4159 CC = Cond.getOperand(0);
4161 SDOperand Cmp = Cond.getOperand(1);
4162 unsigned Opc = Cmp.getOpcode();
4163 MVT::ValueType VT = Op.getValueType();
4165 bool IllegalFPCMov = false;
4166 if (MVT::isFloatingPoint(VT) && !MVT::isVector(VT) &&
4167 !isScalarFPTypeInSSEReg(VT)) // FPStack?
4168 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
4170 if ((Opc == X86ISD::CMP ||
4171 Opc == X86ISD::COMI ||
4172 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
4179 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4180 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4183 const MVT::ValueType *VTs = DAG.getNodeValueTypes(Op.getValueType(),
4185 SmallVector<SDOperand, 4> Ops;
4186 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
4187 // condition is true.
4188 Ops.push_back(Op.getOperand(2));
4189 Ops.push_back(Op.getOperand(1));
4191 Ops.push_back(Cond);
4192 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
4195 SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
4196 bool addTest = true;
4197 SDOperand Chain = Op.getOperand(0);
4198 SDOperand Cond = Op.getOperand(1);
4199 SDOperand Dest = Op.getOperand(2);
4202 if (Cond.getOpcode() == ISD::SETCC)
4203 Cond = LowerSETCC(Cond, DAG);
4205 // If condition flag is set by a X86ISD::CMP, then use it as the condition
4206 // setting operand in place of the X86ISD::SETCC.
4207 if (Cond.getOpcode() == X86ISD::SETCC) {
4208 CC = Cond.getOperand(0);
4210 SDOperand Cmp = Cond.getOperand(1);
4211 unsigned Opc = Cmp.getOpcode();
4212 if (Opc == X86ISD::CMP ||
4213 Opc == X86ISD::COMI ||
4214 Opc == X86ISD::UCOMI) {
4221 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4222 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
4224 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
4225 Chain, Op.getOperand(2), CC, Cond);
4229 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
4230 // Calls to _alloca is needed to probe the stack when allocating more than 4k
4231 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
4232 // that the guard pages used by the OS virtual memory manager are allocated in
4233 // correct sequence.
4235 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
4236 SelectionDAG &DAG) {
4237 assert(Subtarget->isTargetCygMing() &&
4238 "This should be used only on Cygwin/Mingw targets");
4241 SDOperand Chain = Op.getOperand(0);
4242 SDOperand Size = Op.getOperand(1);
4243 // FIXME: Ensure alignment here
4247 MVT::ValueType IntPtr = getPointerTy();
4248 MVT::ValueType SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
4250 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
4251 Flag = Chain.getValue(1);
4253 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4254 SDOperand Ops[] = { Chain,
4255 DAG.getTargetExternalSymbol("_alloca", IntPtr),
4256 DAG.getRegister(X86::EAX, IntPtr),
4258 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 4);
4259 Flag = Chain.getValue(1);
4261 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
4263 std::vector<MVT::ValueType> Tys;
4264 Tys.push_back(SPTy);
4265 Tys.push_back(MVT::Other);
4266 SDOperand Ops1[2] = { Chain.getValue(0), Chain };
4267 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops1, 2);
4270 SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
4271 SDOperand InFlag(0, 0);
4272 SDOperand Chain = Op.getOperand(0);
4274 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
4275 if (Align == 0) Align = 1;
4277 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
4278 // If not DWORD aligned or size is more than the threshold, call memset.
4279 // The libc version is likely to be faster for these cases. It can use the
4280 // address value and run time information about the CPU.
4281 if ((Align & 3) != 0 ||
4282 (I && I->getValue() > Subtarget->getMaxInlineSizeThreshold())) {
4283 MVT::ValueType IntPtr = getPointerTy();
4284 const Type *IntPtrTy = getTargetData()->getIntPtrType();
4285 TargetLowering::ArgListTy Args;
4286 TargetLowering::ArgListEntry Entry;
4287 Entry.Node = Op.getOperand(1);
4288 Entry.Ty = IntPtrTy;
4289 Args.push_back(Entry);
4290 // Extend the unsigned i8 argument to be an int value for the call.
4291 Entry.Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
4292 Entry.Ty = IntPtrTy;
4293 Args.push_back(Entry);
4294 Entry.Node = Op.getOperand(3);
4295 Args.push_back(Entry);
4296 std::pair<SDOperand,SDOperand> CallResult =
4297 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false,
4298 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
4299 return CallResult.second;
4304 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2));
4305 unsigned BytesLeft = 0;
4306 bool TwoRepStos = false;
4309 uint64_t Val = ValC->getValue() & 255;
4311 // If the value is a constant, then we can potentially use larger sets.
4312 switch (Align & 3) {
4313 case 2: // WORD aligned
4316 Val = (Val << 8) | Val;
4318 case 0: // DWORD aligned
4321 Val = (Val << 8) | Val;
4322 Val = (Val << 16) | Val;
4323 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) { // QWORD aligned
4326 Val = (Val << 32) | Val;
4329 default: // Byte aligned
4332 Count = Op.getOperand(3);
4336 if (AVT > MVT::i8) {
4338 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4339 Count = DAG.getIntPtrConstant(I->getValue() / UBytes);
4340 BytesLeft = I->getValue() % UBytes;
4342 assert(AVT >= MVT::i32 &&
4343 "Do not use rep;stos if not at least DWORD aligned");
4344 Count = DAG.getNode(ISD::SRL, Op.getOperand(3).getValueType(),
4345 Op.getOperand(3), DAG.getConstant(2, MVT::i8));
4350 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
4352 InFlag = Chain.getValue(1);
4355 Count = Op.getOperand(3);
4356 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
4357 InFlag = Chain.getValue(1);
4360 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4362 InFlag = Chain.getValue(1);
4363 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4364 Op.getOperand(1), InFlag);
4365 InFlag = Chain.getValue(1);
4367 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4368 SmallVector<SDOperand, 8> Ops;
4369 Ops.push_back(Chain);
4370 Ops.push_back(DAG.getValueType(AVT));
4371 Ops.push_back(InFlag);
4372 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4375 InFlag = Chain.getValue(1);
4376 Count = Op.getOperand(3);
4377 MVT::ValueType CVT = Count.getValueType();
4378 SDOperand Left = DAG.getNode(ISD::AND, CVT, Count,
4379 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
4380 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
4382 InFlag = Chain.getValue(1);
4383 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4385 Ops.push_back(Chain);
4386 Ops.push_back(DAG.getValueType(MVT::i8));
4387 Ops.push_back(InFlag);
4388 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
4389 } else if (BytesLeft) {
4390 // Issue stores for the last 1 - 7 bytes.
4392 unsigned Val = ValC->getValue() & 255;
4393 unsigned Offset = I->getValue() - BytesLeft;
4394 SDOperand DstAddr = Op.getOperand(1);
4395 MVT::ValueType AddrVT = DstAddr.getValueType();
4396 if (BytesLeft >= 4) {
4397 Val = (Val << 8) | Val;
4398 Val = (Val << 16) | Val;
4399 Value = DAG.getConstant(Val, MVT::i32);
4400 Chain = DAG.getStore(Chain, Value,
4401 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4402 DAG.getConstant(Offset, AddrVT)),
4407 if (BytesLeft >= 2) {
4408 Value = DAG.getConstant((Val << 8) | Val, MVT::i16);
4409 Chain = DAG.getStore(Chain, Value,
4410 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4411 DAG.getConstant(Offset, AddrVT)),
4416 if (BytesLeft == 1) {
4417 Value = DAG.getConstant(Val, MVT::i8);
4418 Chain = DAG.getStore(Chain, Value,
4419 DAG.getNode(ISD::ADD, AddrVT, DstAddr,
4420 DAG.getConstant(Offset, AddrVT)),
4428 SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
4433 SelectionDAG &DAG) {
4435 unsigned BytesLeft = 0;
4436 switch (Align & 3) {
4437 case 2: // WORD aligned
4440 case 0: // DWORD aligned
4442 if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) // QWORD aligned
4445 default: // Byte aligned
4450 unsigned UBytes = MVT::getSizeInBits(AVT) / 8;
4451 SDOperand Count = DAG.getIntPtrConstant(Size / UBytes);
4452 BytesLeft = Size % UBytes;
4454 SDOperand InFlag(0, 0);
4455 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
4457 InFlag = Chain.getValue(1);
4458 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
4460 InFlag = Chain.getValue(1);
4461 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
4463 InFlag = Chain.getValue(1);
4465 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4466 SmallVector<SDOperand, 8> Ops;
4467 Ops.push_back(Chain);
4468 Ops.push_back(DAG.getValueType(AVT));
4469 Ops.push_back(InFlag);
4470 Chain = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
4473 // Issue loads and stores for the last 1 - 7 bytes.
4474 unsigned Offset = Size - BytesLeft;
4475 SDOperand DstAddr = Dest;
4476 MVT::ValueType DstVT = DstAddr.getValueType();
4477 SDOperand SrcAddr = Source;
4478 MVT::ValueType SrcVT = SrcAddr.getValueType();
4480 if (BytesLeft >= 4) {
4481 Value = DAG.getLoad(MVT::i32, Chain,
4482 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4483 DAG.getConstant(Offset, SrcVT)),
4485 Chain = Value.getValue(1);
4486 Chain = DAG.getStore(Chain, Value,
4487 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4488 DAG.getConstant(Offset, DstVT)),
4493 if (BytesLeft >= 2) {
4494 Value = DAG.getLoad(MVT::i16, Chain,
4495 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4496 DAG.getConstant(Offset, SrcVT)),
4498 Chain = Value.getValue(1);
4499 Chain = DAG.getStore(Chain, Value,
4500 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4501 DAG.getConstant(Offset, DstVT)),
4507 if (BytesLeft == 1) {
4508 Value = DAG.getLoad(MVT::i8, Chain,
4509 DAG.getNode(ISD::ADD, SrcVT, SrcAddr,
4510 DAG.getConstant(Offset, SrcVT)),
4512 Chain = Value.getValue(1);
4513 Chain = DAG.getStore(Chain, Value,
4514 DAG.getNode(ISD::ADD, DstVT, DstAddr,
4515 DAG.getConstant(Offset, DstVT)),
4523 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
4524 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
4525 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
4526 SDOperand TheChain = N->getOperand(0);
4527 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
4528 if (Subtarget->is64Bit()) {
4529 SDOperand rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
4530 SDOperand rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
4531 MVT::i64, rax.getValue(2));
4532 SDOperand Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
4533 DAG.getConstant(32, MVT::i8));
4535 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
4538 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4539 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4542 SDOperand eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
4543 SDOperand edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
4544 MVT::i32, eax.getValue(2));
4545 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
4546 SDOperand Ops[] = { eax, edx };
4547 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
4549 // Use a MERGE_VALUES to return the value and chain.
4550 Ops[1] = edx.getValue(1);
4551 Tys = DAG.getVTList(MVT::i64, MVT::Other);
4552 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2).Val;
4555 SDOperand X86TargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG) {
4556 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
4558 if (!Subtarget->is64Bit()) {
4559 // vastart just stores the address of the VarArgsFrameIndex slot into the
4560 // memory location argument.
4561 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4562 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV->getValue(),
4567 // gp_offset (0 - 6 * 8)
4568 // fp_offset (48 - 48 + 8 * 16)
4569 // overflow_arg_area (point to parameters coming in memory).
4571 SmallVector<SDOperand, 8> MemOps;
4572 SDOperand FIN = Op.getOperand(1);
4574 SDOperand Store = DAG.getStore(Op.getOperand(0),
4575 DAG.getConstant(VarArgsGPOffset, MVT::i32),
4576 FIN, SV->getValue(), SV->getOffset());
4577 MemOps.push_back(Store);
4580 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
4581 Store = DAG.getStore(Op.getOperand(0),
4582 DAG.getConstant(VarArgsFPOffset, MVT::i32),
4583 FIN, SV->getValue(), SV->getOffset());
4584 MemOps.push_back(Store);
4586 // Store ptr to overflow_arg_area
4587 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
4588 SDOperand OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
4589 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV->getValue(),
4591 MemOps.push_back(Store);
4593 // Store ptr to reg_save_area.
4594 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
4595 SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
4596 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV->getValue(),
4598 MemOps.push_back(Store);
4599 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
4602 SDOperand X86TargetLowering::LowerVACOPY(SDOperand Op, SelectionDAG &DAG) {
4603 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
4604 SDOperand Chain = Op.getOperand(0);
4605 SDOperand DstPtr = Op.getOperand(1);
4606 SDOperand SrcPtr = Op.getOperand(2);
4607 SrcValueSDNode *DstSV = cast<SrcValueSDNode>(Op.getOperand(3));
4608 SrcValueSDNode *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4));
4610 SrcPtr = DAG.getLoad(getPointerTy(), Chain, SrcPtr,
4611 SrcSV->getValue(), SrcSV->getOffset());
4612 Chain = SrcPtr.getValue(1);
4613 for (unsigned i = 0; i < 3; ++i) {
4614 SDOperand Val = DAG.getLoad(MVT::i64, Chain, SrcPtr,
4615 SrcSV->getValue(), SrcSV->getOffset());
4616 Chain = Val.getValue(1);
4617 Chain = DAG.getStore(Chain, Val, DstPtr,
4618 DstSV->getValue(), DstSV->getOffset());
4621 SrcPtr = DAG.getNode(ISD::ADD, getPointerTy(), SrcPtr,
4622 DAG.getIntPtrConstant(8));
4623 DstPtr = DAG.getNode(ISD::ADD, getPointerTy(), DstPtr,
4624 DAG.getIntPtrConstant(8));
4630 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
4631 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
4633 default: return SDOperand(); // Don't custom lower most intrinsics.
4634 // Comparison intrinsics.
4635 case Intrinsic::x86_sse_comieq_ss:
4636 case Intrinsic::x86_sse_comilt_ss:
4637 case Intrinsic::x86_sse_comile_ss:
4638 case Intrinsic::x86_sse_comigt_ss:
4639 case Intrinsic::x86_sse_comige_ss:
4640 case Intrinsic::x86_sse_comineq_ss:
4641 case Intrinsic::x86_sse_ucomieq_ss:
4642 case Intrinsic::x86_sse_ucomilt_ss:
4643 case Intrinsic::x86_sse_ucomile_ss:
4644 case Intrinsic::x86_sse_ucomigt_ss:
4645 case Intrinsic::x86_sse_ucomige_ss:
4646 case Intrinsic::x86_sse_ucomineq_ss:
4647 case Intrinsic::x86_sse2_comieq_sd:
4648 case Intrinsic::x86_sse2_comilt_sd:
4649 case Intrinsic::x86_sse2_comile_sd:
4650 case Intrinsic::x86_sse2_comigt_sd:
4651 case Intrinsic::x86_sse2_comige_sd:
4652 case Intrinsic::x86_sse2_comineq_sd:
4653 case Intrinsic::x86_sse2_ucomieq_sd:
4654 case Intrinsic::x86_sse2_ucomilt_sd:
4655 case Intrinsic::x86_sse2_ucomile_sd:
4656 case Intrinsic::x86_sse2_ucomigt_sd:
4657 case Intrinsic::x86_sse2_ucomige_sd:
4658 case Intrinsic::x86_sse2_ucomineq_sd: {
4660 ISD::CondCode CC = ISD::SETCC_INVALID;
4663 case Intrinsic::x86_sse_comieq_ss:
4664 case Intrinsic::x86_sse2_comieq_sd:
4668 case Intrinsic::x86_sse_comilt_ss:
4669 case Intrinsic::x86_sse2_comilt_sd:
4673 case Intrinsic::x86_sse_comile_ss:
4674 case Intrinsic::x86_sse2_comile_sd:
4678 case Intrinsic::x86_sse_comigt_ss:
4679 case Intrinsic::x86_sse2_comigt_sd:
4683 case Intrinsic::x86_sse_comige_ss:
4684 case Intrinsic::x86_sse2_comige_sd:
4688 case Intrinsic::x86_sse_comineq_ss:
4689 case Intrinsic::x86_sse2_comineq_sd:
4693 case Intrinsic::x86_sse_ucomieq_ss:
4694 case Intrinsic::x86_sse2_ucomieq_sd:
4695 Opc = X86ISD::UCOMI;
4698 case Intrinsic::x86_sse_ucomilt_ss:
4699 case Intrinsic::x86_sse2_ucomilt_sd:
4700 Opc = X86ISD::UCOMI;
4703 case Intrinsic::x86_sse_ucomile_ss:
4704 case Intrinsic::x86_sse2_ucomile_sd:
4705 Opc = X86ISD::UCOMI;
4708 case Intrinsic::x86_sse_ucomigt_ss:
4709 case Intrinsic::x86_sse2_ucomigt_sd:
4710 Opc = X86ISD::UCOMI;
4713 case Intrinsic::x86_sse_ucomige_ss:
4714 case Intrinsic::x86_sse2_ucomige_sd:
4715 Opc = X86ISD::UCOMI;
4718 case Intrinsic::x86_sse_ucomineq_ss:
4719 case Intrinsic::x86_sse2_ucomineq_sd:
4720 Opc = X86ISD::UCOMI;
4726 SDOperand LHS = Op.getOperand(1);
4727 SDOperand RHS = Op.getOperand(2);
4728 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
4730 SDOperand Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
4731 SDOperand SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
4732 DAG.getConstant(X86CC, MVT::i8), Cond);
4733 return DAG.getNode(ISD::ANY_EXTEND, MVT::i32, SetCC);
4738 SDOperand X86TargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
4739 // Depths > 0 not supported yet!
4740 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4743 // Just load the return address
4744 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4745 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4748 SDOperand X86TargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
4749 // Depths > 0 not supported yet!
4750 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
4753 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
4754 return DAG.getNode(ISD::SUB, getPointerTy(), RetAddrFI,
4755 DAG.getIntPtrConstant(4));
4758 SDOperand X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDOperand Op,
4759 SelectionDAG &DAG) {
4760 // Is not yet supported on x86-64
4761 if (Subtarget->is64Bit())
4764 return DAG.getIntPtrConstant(8);
4767 SDOperand X86TargetLowering::LowerEH_RETURN(SDOperand Op, SelectionDAG &DAG)
4769 assert(!Subtarget->is64Bit() &&
4770 "Lowering of eh_return builtin is not supported yet on x86-64");
4772 MachineFunction &MF = DAG.getMachineFunction();
4773 SDOperand Chain = Op.getOperand(0);
4774 SDOperand Offset = Op.getOperand(1);
4775 SDOperand Handler = Op.getOperand(2);
4777 SDOperand Frame = DAG.getRegister(RegInfo->getFrameRegister(MF),
4780 SDOperand StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
4781 DAG.getIntPtrConstant(-4UL));
4782 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
4783 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
4784 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
4785 MF.getRegInfo().addLiveOut(X86::ECX);
4787 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
4788 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
4791 SDOperand X86TargetLowering::LowerTRAMPOLINE(SDOperand Op,
4792 SelectionDAG &DAG) {
4793 SDOperand Root = Op.getOperand(0);
4794 SDOperand Trmp = Op.getOperand(1); // trampoline
4795 SDOperand FPtr = Op.getOperand(2); // nested function
4796 SDOperand Nest = Op.getOperand(3); // 'nest' parameter value
4798 SrcValueSDNode *TrmpSV = cast<SrcValueSDNode>(Op.getOperand(4));
4800 const X86InstrInfo *TII =
4801 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
4803 if (Subtarget->is64Bit()) {
4804 SDOperand OutChains[6];
4806 // Large code-model.
4808 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
4809 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
4811 const unsigned char N86R10 =
4812 ((X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R10);
4813 const unsigned char N86R11 =
4814 ((X86RegisterInfo*)RegInfo)->getX86RegNum(X86::R11);
4816 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
4818 // Load the pointer to the nested function into R11.
4819 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
4820 SDOperand Addr = Trmp;
4821 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
4822 TrmpSV->getValue(), TrmpSV->getOffset());
4824 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
4825 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpSV->getValue(),
4826 TrmpSV->getOffset() + 2, false, 2);
4828 // Load the 'nest' parameter value into R10.
4829 // R10 is specified in X86CallingConv.td
4830 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
4831 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
4832 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
4833 TrmpSV->getValue(), TrmpSV->getOffset() + 10);
4835 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
4836 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4837 TrmpSV->getOffset() + 12, false, 2);
4839 // Jump to the nested function.
4840 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
4841 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
4842 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
4843 TrmpSV->getValue(), TrmpSV->getOffset() + 20);
4845 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
4846 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
4847 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
4848 TrmpSV->getValue(), TrmpSV->getOffset() + 22);
4851 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
4852 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
4854 Function *Func = (Function *)
4855 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
4856 unsigned CC = Func->getCallingConv();
4861 assert(0 && "Unsupported calling convention");
4862 case CallingConv::C:
4863 case CallingConv::X86_StdCall: {
4864 // Pass 'nest' parameter in ECX.
4865 // Must be kept in sync with X86CallingConv.td
4868 // Check that ECX wasn't needed by an 'inreg' parameter.
4869 const FunctionType *FTy = Func->getFunctionType();
4870 const ParamAttrsList *Attrs = Func->getParamAttrs();
4872 if (Attrs && !Func->isVarArg()) {
4873 unsigned InRegCount = 0;
4876 for (FunctionType::param_iterator I = FTy->param_begin(),
4877 E = FTy->param_end(); I != E; ++I, ++Idx)
4878 if (Attrs->paramHasAttr(Idx, ParamAttr::InReg))
4879 // FIXME: should only count parameters that are lowered to integers.
4880 InRegCount += (getTargetData()->getTypeSizeInBits(*I) + 31) / 32;
4882 if (InRegCount > 2) {
4883 cerr << "Nest register in use - reduce number of inreg parameters!\n";
4889 case CallingConv::X86_FastCall:
4890 // Pass 'nest' parameter in EAX.
4891 // Must be kept in sync with X86CallingConv.td
4896 SDOperand OutChains[4];
4897 SDOperand Addr, Disp;
4899 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
4900 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
4902 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
4903 const unsigned char N86Reg =
4904 ((X86RegisterInfo*)RegInfo)->getX86RegNum(NestReg);
4905 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
4906 Trmp, TrmpSV->getValue(), TrmpSV->getOffset());
4908 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
4909 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpSV->getValue(),
4910 TrmpSV->getOffset() + 1, false, 1);
4912 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
4913 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
4914 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
4915 TrmpSV->getValue() + 5, TrmpSV->getOffset());
4917 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
4918 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpSV->getValue(),
4919 TrmpSV->getOffset() + 6, false, 1);
4922 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
4923 return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(), Ops, 2);
4927 SDOperand X86TargetLowering::LowerFLT_ROUNDS(SDOperand Op, SelectionDAG &DAG) {
4929 The rounding mode is in bits 11:10 of FPSR, and has the following
4936 FLT_ROUNDS, on the other hand, expects the following:
4943 To perform the conversion, we do:
4944 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
4947 MachineFunction &MF = DAG.getMachineFunction();
4948 const TargetMachine &TM = MF.getTarget();
4949 const TargetFrameInfo &TFI = *TM.getFrameInfo();
4950 unsigned StackAlignment = TFI.getStackAlignment();
4951 MVT::ValueType VT = Op.getValueType();
4953 // Save FP Control Word to stack slot
4954 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
4955 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4957 SDOperand Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
4958 DAG.getEntryNode(), StackSlot);
4960 // Load FP Control Word from stack slot
4961 SDOperand CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
4963 // Transform as necessary
4965 DAG.getNode(ISD::SRL, MVT::i16,
4966 DAG.getNode(ISD::AND, MVT::i16,
4967 CWD, DAG.getConstant(0x800, MVT::i16)),
4968 DAG.getConstant(11, MVT::i8));
4970 DAG.getNode(ISD::SRL, MVT::i16,
4971 DAG.getNode(ISD::AND, MVT::i16,
4972 CWD, DAG.getConstant(0x400, MVT::i16)),
4973 DAG.getConstant(9, MVT::i8));
4976 DAG.getNode(ISD::AND, MVT::i16,
4977 DAG.getNode(ISD::ADD, MVT::i16,
4978 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
4979 DAG.getConstant(1, MVT::i16)),
4980 DAG.getConstant(3, MVT::i16));
4983 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
4984 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
4987 SDOperand X86TargetLowering::LowerCTLZ(SDOperand Op, SelectionDAG &DAG) {
4988 MVT::ValueType VT = Op.getValueType();
4989 MVT::ValueType OpVT = VT;
4990 unsigned NumBits = MVT::getSizeInBits(VT);
4992 Op = Op.getOperand(0);
4993 if (VT == MVT::i8) {
4994 // Zero extend to i32 since there is not an i8 bsr.
4996 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
4999 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5000 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5001 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5003 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5004 SmallVector<SDOperand, 4> Ops;
5006 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5007 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5008 Ops.push_back(Op.getValue(1));
5009 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5011 // Finally xor with NumBits-1.
5012 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5015 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5019 SDOperand X86TargetLowering::LowerCTTZ(SDOperand Op, SelectionDAG &DAG) {
5020 MVT::ValueType VT = Op.getValueType();
5021 MVT::ValueType OpVT = VT;
5022 unsigned NumBits = MVT::getSizeInBits(VT);
5024 Op = Op.getOperand(0);
5025 if (VT == MVT::i8) {
5027 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5030 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5031 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5032 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5034 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5035 SmallVector<SDOperand, 4> Ops;
5037 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5038 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5039 Ops.push_back(Op.getValue(1));
5040 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5043 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5047 /// LowerOperation - Provide custom lowering hooks for some operations.
5049 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
5050 switch (Op.getOpcode()) {
5051 default: assert(0 && "Should not custom lower this!");
5052 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5053 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5054 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5055 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5056 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5057 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5058 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5059 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5060 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
5061 case ISD::SHL_PARTS:
5062 case ISD::SRA_PARTS:
5063 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
5064 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5065 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
5066 case ISD::FABS: return LowerFABS(Op, DAG);
5067 case ISD::FNEG: return LowerFNEG(Op, DAG);
5068 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5069 case ISD::SETCC: return LowerSETCC(Op, DAG);
5070 case ISD::SELECT: return LowerSELECT(Op, DAG);
5071 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
5072 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5073 case ISD::CALL: return LowerCALL(Op, DAG);
5074 case ISD::RET: return LowerRET(Op, DAG);
5075 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
5076 case ISD::MEMSET: return LowerMEMSET(Op, DAG);
5077 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
5078 case ISD::VASTART: return LowerVASTART(Op, DAG);
5079 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
5080 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5081 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5082 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5083 case ISD::FRAME_TO_ARGS_OFFSET:
5084 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
5085 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
5086 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
5087 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
5088 case ISD::FLT_ROUNDS: return LowerFLT_ROUNDS(Op, DAG);
5089 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
5090 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
5092 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
5093 case ISD::READCYCLECOUNTER:
5094 return SDOperand(ExpandREADCYCLECOUNTER(Op.Val, DAG), 0);
5098 /// ExpandOperation - Provide custom lowering hooks for expanding operations.
5099 SDNode *X86TargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
5100 switch (N->getOpcode()) {
5101 default: assert(0 && "Should not custom lower this!");
5102 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
5103 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
5107 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
5109 default: return NULL;
5110 case X86ISD::BSF: return "X86ISD::BSF";
5111 case X86ISD::BSR: return "X86ISD::BSR";
5112 case X86ISD::SHLD: return "X86ISD::SHLD";
5113 case X86ISD::SHRD: return "X86ISD::SHRD";
5114 case X86ISD::FAND: return "X86ISD::FAND";
5115 case X86ISD::FOR: return "X86ISD::FOR";
5116 case X86ISD::FXOR: return "X86ISD::FXOR";
5117 case X86ISD::FSRL: return "X86ISD::FSRL";
5118 case X86ISD::FILD: return "X86ISD::FILD";
5119 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
5120 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
5121 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
5122 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
5123 case X86ISD::FLD: return "X86ISD::FLD";
5124 case X86ISD::FST: return "X86ISD::FST";
5125 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
5126 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
5127 case X86ISD::CALL: return "X86ISD::CALL";
5128 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
5129 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
5130 case X86ISD::CMP: return "X86ISD::CMP";
5131 case X86ISD::COMI: return "X86ISD::COMI";
5132 case X86ISD::UCOMI: return "X86ISD::UCOMI";
5133 case X86ISD::SETCC: return "X86ISD::SETCC";
5134 case X86ISD::CMOV: return "X86ISD::CMOV";
5135 case X86ISD::BRCOND: return "X86ISD::BRCOND";
5136 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
5137 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
5138 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
5139 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
5140 case X86ISD::Wrapper: return "X86ISD::Wrapper";
5141 case X86ISD::S2VEC: return "X86ISD::S2VEC";
5142 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
5143 case X86ISD::PINSRW: return "X86ISD::PINSRW";
5144 case X86ISD::FMAX: return "X86ISD::FMAX";
5145 case X86ISD::FMIN: return "X86ISD::FMIN";
5146 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
5147 case X86ISD::FRCP: return "X86ISD::FRCP";
5148 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
5149 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
5150 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
5151 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
5152 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
5156 // isLegalAddressingMode - Return true if the addressing mode represented
5157 // by AM is legal for this target, for a load/store of the specified type.
5158 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
5159 const Type *Ty) const {
5160 // X86 supports extremely general addressing modes.
5162 // X86 allows a sign-extended 32-bit immediate field as a displacement.
5163 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
5167 // We can only fold this if we don't need an extra load.
5168 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
5171 // X86-64 only supports addr of globals in small code model.
5172 if (Subtarget->is64Bit()) {
5173 if (getTargetMachine().getCodeModel() != CodeModel::Small)
5175 // If lower 4G is not available, then we must use rip-relative addressing.
5176 if (AM.BaseOffs || AM.Scale > 1)
5187 // These scales always work.
5192 // These scales are formed with basereg+scalereg. Only accept if there is
5197 default: // Other stuff never works.
5205 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
5206 if (!Ty1->isInteger() || !Ty2->isInteger())
5208 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
5209 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
5210 if (NumBits1 <= NumBits2)
5212 return Subtarget->is64Bit() || NumBits1 < 64;
5215 bool X86TargetLowering::isTruncateFree(MVT::ValueType VT1,
5216 MVT::ValueType VT2) const {
5217 if (!MVT::isInteger(VT1) || !MVT::isInteger(VT2))
5219 unsigned NumBits1 = MVT::getSizeInBits(VT1);
5220 unsigned NumBits2 = MVT::getSizeInBits(VT2);
5221 if (NumBits1 <= NumBits2)
5223 return Subtarget->is64Bit() || NumBits1 < 64;
5226 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5227 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5228 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5229 /// are assumed to be legal.
5231 X86TargetLowering::isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
5232 // Only do shuffles on 128-bit vector types for now.
5233 if (MVT::getSizeInBits(VT) == 64) return false;
5234 return (Mask.Val->getNumOperands() <= 4 ||
5235 isIdentityMask(Mask.Val) ||
5236 isIdentityMask(Mask.Val, true) ||
5237 isSplatMask(Mask.Val) ||
5238 isPSHUFHW_PSHUFLWMask(Mask.Val) ||
5239 X86::isUNPCKLMask(Mask.Val) ||
5240 X86::isUNPCKHMask(Mask.Val) ||
5241 X86::isUNPCKL_v_undef_Mask(Mask.Val) ||
5242 X86::isUNPCKH_v_undef_Mask(Mask.Val));
5245 bool X86TargetLowering::isVectorClearMaskLegal(std::vector<SDOperand> &BVOps,
5247 SelectionDAG &DAG) const {
5248 unsigned NumElts = BVOps.size();
5249 // Only do shuffles on 128-bit vector types for now.
5250 if (MVT::getSizeInBits(EVT) * NumElts == 64) return false;
5251 if (NumElts == 2) return true;
5253 return (isMOVLMask(&BVOps[0], 4) ||
5254 isCommutedMOVL(&BVOps[0], 4, true) ||
5255 isSHUFPMask(&BVOps[0], 4) ||
5256 isCommutedSHUFP(&BVOps[0], 4));
5261 //===----------------------------------------------------------------------===//
5262 // X86 Scheduler Hooks
5263 //===----------------------------------------------------------------------===//
5266 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
5267 MachineBasicBlock *BB) {
5268 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5269 switch (MI->getOpcode()) {
5270 default: assert(false && "Unexpected instr type to insert");
5271 case X86::CMOV_FR32:
5272 case X86::CMOV_FR64:
5273 case X86::CMOV_V4F32:
5274 case X86::CMOV_V2F64:
5275 case X86::CMOV_V2I64: {
5276 // To "insert" a SELECT_CC instruction, we actually have to insert the
5277 // diamond control-flow pattern. The incoming instruction knows the
5278 // destination vreg to set, the condition code register to branch on, the
5279 // true/false values to select between, and a branch opcode to use.
5280 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5281 ilist<MachineBasicBlock>::iterator It = BB;
5287 // cmpTY ccX, r1, r2
5289 // fallthrough --> copy0MBB
5290 MachineBasicBlock *thisMBB = BB;
5291 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
5292 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
5294 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
5295 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
5296 MachineFunction *F = BB->getParent();
5297 F->getBasicBlockList().insert(It, copy0MBB);
5298 F->getBasicBlockList().insert(It, sinkMBB);
5299 // Update machine-CFG edges by first adding all successors of the current
5300 // block to the new block which will contain the Phi node for the select.
5301 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
5302 e = BB->succ_end(); i != e; ++i)
5303 sinkMBB->addSuccessor(*i);
5304 // Next, remove all successors of the current block, and add the true
5305 // and fallthrough blocks as its successors.
5306 while(!BB->succ_empty())
5307 BB->removeSuccessor(BB->succ_begin());
5308 BB->addSuccessor(copy0MBB);
5309 BB->addSuccessor(sinkMBB);
5312 // %FalseValue = ...
5313 // # fallthrough to sinkMBB
5316 // Update machine-CFG edges
5317 BB->addSuccessor(sinkMBB);
5320 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5323 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
5324 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5325 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5327 delete MI; // The pseudo instruction is gone now.
5331 case X86::FP32_TO_INT16_IN_MEM:
5332 case X86::FP32_TO_INT32_IN_MEM:
5333 case X86::FP32_TO_INT64_IN_MEM:
5334 case X86::FP64_TO_INT16_IN_MEM:
5335 case X86::FP64_TO_INT32_IN_MEM:
5336 case X86::FP64_TO_INT64_IN_MEM:
5337 case X86::FP80_TO_INT16_IN_MEM:
5338 case X86::FP80_TO_INT32_IN_MEM:
5339 case X86::FP80_TO_INT64_IN_MEM: {
5340 // Change the floating point control register to use "round towards zero"
5341 // mode when truncating to an integer value.
5342 MachineFunction *F = BB->getParent();
5343 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
5344 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
5346 // Load the old value of the high byte of the control word...
5348 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
5349 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
5351 // Set the high part to be round to zero...
5352 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
5355 // Reload the modified control word now...
5356 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5358 // Restore the memory image of control word to original value
5359 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
5362 // Get the X86 opcode to use.
5364 switch (MI->getOpcode()) {
5365 default: assert(0 && "illegal opcode!");
5366 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
5367 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
5368 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
5369 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
5370 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
5371 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
5372 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
5373 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
5374 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
5378 MachineOperand &Op = MI->getOperand(0);
5379 if (Op.isRegister()) {
5380 AM.BaseType = X86AddressMode::RegBase;
5381 AM.Base.Reg = Op.getReg();
5383 AM.BaseType = X86AddressMode::FrameIndexBase;
5384 AM.Base.FrameIndex = Op.getIndex();
5386 Op = MI->getOperand(1);
5387 if (Op.isImmediate())
5388 AM.Scale = Op.getImm();
5389 Op = MI->getOperand(2);
5390 if (Op.isImmediate())
5391 AM.IndexReg = Op.getImm();
5392 Op = MI->getOperand(3);
5393 if (Op.isGlobalAddress()) {
5394 AM.GV = Op.getGlobal();
5396 AM.Disp = Op.getImm();
5398 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
5399 .addReg(MI->getOperand(4).getReg());
5401 // Reload the original control word now.
5402 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
5404 delete MI; // The pseudo instruction is gone now.
5410 //===----------------------------------------------------------------------===//
5411 // X86 Optimization Hooks
5412 //===----------------------------------------------------------------------===//
5414 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
5416 uint64_t &KnownZero,
5418 const SelectionDAG &DAG,
5419 unsigned Depth) const {
5420 unsigned Opc = Op.getOpcode();
5421 assert((Opc >= ISD::BUILTIN_OP_END ||
5422 Opc == ISD::INTRINSIC_WO_CHAIN ||
5423 Opc == ISD::INTRINSIC_W_CHAIN ||
5424 Opc == ISD::INTRINSIC_VOID) &&
5425 "Should use MaskedValueIsZero if you don't know whether Op"
5426 " is a target node!");
5428 KnownZero = KnownOne = 0; // Don't know anything.
5432 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
5437 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5438 /// element of the result of the vector shuffle.
5439 static SDOperand getShuffleScalarElt(SDNode *N, unsigned i, SelectionDAG &DAG) {
5440 MVT::ValueType VT = N->getValueType(0);
5441 SDOperand PermMask = N->getOperand(2);
5442 unsigned NumElems = PermMask.getNumOperands();
5443 SDOperand V = (i < NumElems) ? N->getOperand(0) : N->getOperand(1);
5445 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5447 ? V.getOperand(0) : DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5448 } else if (V.getOpcode() == ISD::VECTOR_SHUFFLE) {
5449 SDOperand Idx = PermMask.getOperand(i);
5450 if (Idx.getOpcode() == ISD::UNDEF)
5451 return DAG.getNode(ISD::UNDEF, MVT::getVectorElementType(VT));
5452 return getShuffleScalarElt(V.Val,cast<ConstantSDNode>(Idx)->getValue(),DAG);
5457 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
5458 /// node is a GlobalAddress + an offset.
5459 static bool isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) {
5460 unsigned Opc = N->getOpcode();
5461 if (Opc == X86ISD::Wrapper) {
5462 if (dyn_cast<GlobalAddressSDNode>(N->getOperand(0))) {
5463 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
5466 } else if (Opc == ISD::ADD) {
5467 SDOperand N1 = N->getOperand(0);
5468 SDOperand N2 = N->getOperand(1);
5469 if (isGAPlusOffset(N1.Val, GA, Offset)) {
5470 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
5472 Offset += V->getSignExtended();
5475 } else if (isGAPlusOffset(N2.Val, GA, Offset)) {
5476 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
5478 Offset += V->getSignExtended();
5486 /// isConsecutiveLoad - Returns true if N is loading from an address of Base
5488 static bool isConsecutiveLoad(SDNode *N, SDNode *Base, int Dist, int Size,
5489 MachineFrameInfo *MFI) {
5490 if (N->getOperand(0).Val != Base->getOperand(0).Val)
5493 SDOperand Loc = N->getOperand(1);
5494 SDOperand BaseLoc = Base->getOperand(1);
5495 if (Loc.getOpcode() == ISD::FrameIndex) {
5496 if (BaseLoc.getOpcode() != ISD::FrameIndex)
5498 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
5499 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
5500 int FS = MFI->getObjectSize(FI);
5501 int BFS = MFI->getObjectSize(BFI);
5502 if (FS != BFS || FS != Size) return false;
5503 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Size);
5505 GlobalValue *GV1 = NULL;
5506 GlobalValue *GV2 = NULL;
5507 int64_t Offset1 = 0;
5508 int64_t Offset2 = 0;
5509 bool isGA1 = isGAPlusOffset(Loc.Val, GV1, Offset1);
5510 bool isGA2 = isGAPlusOffset(BaseLoc.Val, GV2, Offset2);
5511 if (isGA1 && isGA2 && GV1 == GV2)
5512 return Offset1 == (Offset2 + Dist*Size);
5518 static bool isBaseAlignment16(SDNode *Base, MachineFrameInfo *MFI,
5519 const X86Subtarget *Subtarget) {
5522 if (isGAPlusOffset(Base, GV, Offset))
5523 return (GV->getAlignment() >= 16 && (Offset % 16) == 0);
5525 assert(Base->getOpcode() == ISD::FrameIndex && "Unexpected base node!");
5526 int BFI = cast<FrameIndexSDNode>(Base)->getIndex();
5528 // Fixed objects do not specify alignment, however the offsets are known.
5529 return ((Subtarget->getStackAlignment() % 16) == 0 &&
5530 (MFI->getObjectOffset(BFI) % 16) == 0);
5532 return MFI->getObjectAlignment(BFI) >= 16;
5538 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
5539 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
5540 /// if the load addresses are consecutive, non-overlapping, and in the right
5542 static SDOperand PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
5543 const X86Subtarget *Subtarget) {
5544 MachineFunction &MF = DAG.getMachineFunction();
5545 MachineFrameInfo *MFI = MF.getFrameInfo();
5546 MVT::ValueType VT = N->getValueType(0);
5547 MVT::ValueType EVT = MVT::getVectorElementType(VT);
5548 SDOperand PermMask = N->getOperand(2);
5549 int NumElems = (int)PermMask.getNumOperands();
5550 SDNode *Base = NULL;
5551 for (int i = 0; i < NumElems; ++i) {
5552 SDOperand Idx = PermMask.getOperand(i);
5553 if (Idx.getOpcode() == ISD::UNDEF) {
5554 if (!Base) return SDOperand();
5557 getShuffleScalarElt(N, cast<ConstantSDNode>(Idx)->getValue(), DAG);
5558 if (!Arg.Val || !ISD::isNON_EXTLoad(Arg.Val))
5562 else if (!isConsecutiveLoad(Arg.Val, Base,
5563 i, MVT::getSizeInBits(EVT)/8,MFI))
5568 bool isAlign16 = isBaseAlignment16(Base->getOperand(1).Val, MFI, Subtarget);
5569 LoadSDNode *LD = cast<LoadSDNode>(Base);
5571 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5572 LD->getSrcValueOffset(), LD->isVolatile());
5574 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
5575 LD->getSrcValueOffset(), LD->isVolatile(),
5576 LD->getAlignment());
5580 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
5581 static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
5582 const X86Subtarget *Subtarget) {
5583 SDOperand Cond = N->getOperand(0);
5585 // If we have SSE[12] support, try to form min/max nodes.
5586 if (Subtarget->hasSSE2() &&
5587 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
5588 if (Cond.getOpcode() == ISD::SETCC) {
5589 // Get the LHS/RHS of the select.
5590 SDOperand LHS = N->getOperand(1);
5591 SDOperand RHS = N->getOperand(2);
5592 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
5594 unsigned Opcode = 0;
5595 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
5598 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
5601 if (!UnsafeFPMath) break;
5603 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
5605 Opcode = X86ISD::FMIN;
5608 case ISD::SETOGT: // (X > Y) ? X : Y -> max
5611 if (!UnsafeFPMath) break;
5613 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
5615 Opcode = X86ISD::FMAX;
5618 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
5621 case ISD::SETOGT: // (X > Y) ? Y : X -> min
5624 if (!UnsafeFPMath) break;
5626 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
5628 Opcode = X86ISD::FMIN;
5631 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
5634 if (!UnsafeFPMath) break;
5636 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
5638 Opcode = X86ISD::FMAX;
5644 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
5653 SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
5654 DAGCombinerInfo &DCI) const {
5655 SelectionDAG &DAG = DCI.DAG;
5656 switch (N->getOpcode()) {
5658 case ISD::VECTOR_SHUFFLE:
5659 return PerformShuffleCombine(N, DAG, Subtarget);
5661 return PerformSELECTCombine(N, DAG, Subtarget);
5667 //===----------------------------------------------------------------------===//
5668 // X86 Inline Assembly Support
5669 //===----------------------------------------------------------------------===//
5671 /// getConstraintType - Given a constraint letter, return the type of
5672 /// constraint it is for this target.
5673 X86TargetLowering::ConstraintType
5674 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
5675 if (Constraint.size() == 1) {
5676 switch (Constraint[0]) {
5685 return C_RegisterClass;
5690 return TargetLowering::getConstraintType(Constraint);
5693 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5694 /// vector. If it is invalid, don't add anything to Ops.
5695 void X86TargetLowering::LowerAsmOperandForConstraint(SDOperand Op,
5697 std::vector<SDOperand>&Ops,
5698 SelectionDAG &DAG) {
5699 SDOperand Result(0, 0);
5701 switch (Constraint) {
5704 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5705 if (C->getValue() <= 31) {
5706 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5712 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
5713 if (C->getValue() <= 255) {
5714 Result = DAG.getTargetConstant(C->getValue(), Op.getValueType());
5720 // Literal immediates are always ok.
5721 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
5722 Result = DAG.getTargetConstant(CST->getValue(), Op.getValueType());
5726 // If we are in non-pic codegen mode, we allow the address of a global (with
5727 // an optional displacement) to be used with 'i'.
5728 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
5731 // Match either (GA) or (GA+C)
5733 Offset = GA->getOffset();
5734 } else if (Op.getOpcode() == ISD::ADD) {
5735 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5736 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5738 Offset = GA->getOffset()+C->getValue();
5740 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5741 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
5743 Offset = GA->getOffset()+C->getValue();
5750 // If addressing this global requires a load (e.g. in PIC mode), we can't
5752 if (Subtarget->GVRequiresExtraLoad(GA->getGlobal(), getTargetMachine(),
5756 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
5762 // Otherwise, not valid for this mode.
5768 Ops.push_back(Result);
5771 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5774 std::vector<unsigned> X86TargetLowering::
5775 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5776 MVT::ValueType VT) const {
5777 if (Constraint.size() == 1) {
5778 // FIXME: not handling fp-stack yet!
5779 switch (Constraint[0]) { // GCC X86 Constraint Letters
5780 default: break; // Unknown constraint letter
5781 case 'A': // EAX/EDX
5782 if (VT == MVT::i32 || VT == MVT::i64)
5783 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
5785 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
5788 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
5789 else if (VT == MVT::i16)
5790 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
5791 else if (VT == MVT::i8)
5792 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
5793 else if (VT == MVT::i64)
5794 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
5799 return std::vector<unsigned>();
5802 std::pair<unsigned, const TargetRegisterClass*>
5803 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5804 MVT::ValueType VT) const {
5805 // First, see if this is a constraint that directly corresponds to an LLVM
5807 if (Constraint.size() == 1) {
5808 // GCC Constraint Letters
5809 switch (Constraint[0]) {
5811 case 'r': // GENERAL_REGS
5812 case 'R': // LEGACY_REGS
5813 case 'l': // INDEX_REGS
5814 if (VT == MVT::i64 && Subtarget->is64Bit())
5815 return std::make_pair(0U, X86::GR64RegisterClass);
5817 return std::make_pair(0U, X86::GR32RegisterClass);
5818 else if (VT == MVT::i16)
5819 return std::make_pair(0U, X86::GR16RegisterClass);
5820 else if (VT == MVT::i8)
5821 return std::make_pair(0U, X86::GR8RegisterClass);
5823 case 'y': // MMX_REGS if MMX allowed.
5824 if (!Subtarget->hasMMX()) break;
5825 return std::make_pair(0U, X86::VR64RegisterClass);
5827 case 'Y': // SSE_REGS if SSE2 allowed
5828 if (!Subtarget->hasSSE2()) break;
5830 case 'x': // SSE_REGS if SSE1 allowed
5831 if (!Subtarget->hasSSE1()) break;
5835 // Scalar SSE types.
5838 return std::make_pair(0U, X86::FR32RegisterClass);
5841 return std::make_pair(0U, X86::FR64RegisterClass);
5849 return std::make_pair(0U, X86::VR128RegisterClass);
5855 // Use the default implementation in TargetLowering to convert the register
5856 // constraint into a member of a register class.
5857 std::pair<unsigned, const TargetRegisterClass*> Res;
5858 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5860 // Not found as a standard register?
5861 if (Res.second == 0) {
5862 // GCC calls "st(0)" just plain "st".
5863 if (StringsEqualNoCase("{st}", Constraint)) {
5864 Res.first = X86::ST0;
5865 Res.second = X86::RFP80RegisterClass;
5871 // Otherwise, check to see if this is a register class of the wrong value
5872 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
5873 // turn into {ax},{dx}.
5874 if (Res.second->hasType(VT))
5875 return Res; // Correct type already, nothing to do.
5877 // All of the single-register GCC register classes map their values onto
5878 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
5879 // really want an 8-bit or 32-bit register, map to the appropriate register
5880 // class and return the appropriate register.
5881 if (Res.second != X86::GR16RegisterClass)
5884 if (VT == MVT::i8) {
5885 unsigned DestReg = 0;
5886 switch (Res.first) {
5888 case X86::AX: DestReg = X86::AL; break;
5889 case X86::DX: DestReg = X86::DL; break;
5890 case X86::CX: DestReg = X86::CL; break;
5891 case X86::BX: DestReg = X86::BL; break;
5894 Res.first = DestReg;
5895 Res.second = Res.second = X86::GR8RegisterClass;
5897 } else if (VT == MVT::i32) {
5898 unsigned DestReg = 0;
5899 switch (Res.first) {
5901 case X86::AX: DestReg = X86::EAX; break;
5902 case X86::DX: DestReg = X86::EDX; break;
5903 case X86::CX: DestReg = X86::ECX; break;
5904 case X86::BX: DestReg = X86::EBX; break;
5905 case X86::SI: DestReg = X86::ESI; break;
5906 case X86::DI: DestReg = X86::EDI; break;
5907 case X86::BP: DestReg = X86::EBP; break;
5908 case X86::SP: DestReg = X86::ESP; break;
5911 Res.first = DestReg;
5912 Res.second = Res.second = X86::GR32RegisterClass;
5914 } else if (VT == MVT::i64) {
5915 unsigned DestReg = 0;
5916 switch (Res.first) {
5918 case X86::AX: DestReg = X86::RAX; break;
5919 case X86::DX: DestReg = X86::RDX; break;
5920 case X86::CX: DestReg = X86::RCX; break;
5921 case X86::BX: DestReg = X86::RBX; break;
5922 case X86::SI: DestReg = X86::RSI; break;
5923 case X86::DI: DestReg = X86::RDI; break;
5924 case X86::BP: DestReg = X86::RBP; break;
5925 case X86::SP: DestReg = X86::RSP; break;
5928 Res.first = DestReg;
5929 Res.second = Res.second = X86::GR64RegisterClass;