1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
61 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
62 SelectionDAG &DAG, SDLoc dl,
63 unsigned vectorWidth) {
64 assert((vectorWidth == 128 || vectorWidth == 256) &&
65 "Unsupported vector width");
66 EVT VT = Vec.getValueType();
67 EVT ElVT = VT.getVectorElementType();
68 unsigned Factor = VT.getSizeInBits()/vectorWidth;
69 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
70 VT.getVectorNumElements()/Factor);
72 // Extract from UNDEF is UNDEF.
73 if (Vec.getOpcode() == ISD::UNDEF)
74 return DAG.getUNDEF(ResultVT);
76 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
77 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
79 // This is the index of the first element of the vectorWidth-bit chunk
81 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
84 // If the input is a buildvector just emit a smaller one.
85 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
86 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
87 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
89 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
90 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
96 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
97 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
98 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
99 /// instructions or a simple subregister reference. Idx is an index in the
100 /// 128 bits we want. It need not be aligned to a 128-bit bounday. That makes
101 /// lowering EXTRACT_VECTOR_ELT operations easier.
102 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
103 SelectionDAG &DAG, SDLoc dl) {
104 assert((Vec.getValueType().is256BitVector() ||
105 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
106 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
109 /// Generate a DAG to grab 256-bits from a 512-bit vector.
110 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
111 SelectionDAG &DAG, SDLoc dl) {
112 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
113 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
116 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
117 unsigned IdxVal, SelectionDAG &DAG,
118 SDLoc dl, unsigned vectorWidth) {
119 assert((vectorWidth == 128 || vectorWidth == 256) &&
120 "Unsupported vector width");
121 // Inserting UNDEF is Result
122 if (Vec.getOpcode() == ISD::UNDEF)
124 EVT VT = Vec.getValueType();
125 EVT ElVT = VT.getVectorElementType();
126 EVT ResultVT = Result.getValueType();
128 // Insert the relevant vectorWidth bits.
129 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
131 // This is the index of the first element of the vectorWidth-bit chunk
133 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
136 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
137 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
140 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
141 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
142 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
143 /// simple superregister reference. Idx is an index in the 128 bits
144 /// we want. It need not be aligned to a 128-bit bounday. That makes
145 /// lowering INSERT_VECTOR_ELT operations easier.
146 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
147 unsigned IdxVal, SelectionDAG &DAG,
149 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
150 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
153 static SDValue Insert256BitVector(SDValue Result, SDValue Vec,
154 unsigned IdxVal, SelectionDAG &DAG,
156 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
157 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
160 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
161 /// instructions. This is used because creating CONCAT_VECTOR nodes of
162 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
163 /// large BUILD_VECTORS.
164 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
165 unsigned NumElems, SelectionDAG &DAG,
167 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
168 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
171 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
172 unsigned NumElems, SelectionDAG &DAG,
174 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
175 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
178 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
179 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
180 bool is64Bit = Subtarget->is64Bit();
182 if (Subtarget->isTargetEnvMacho()) {
184 return new X86_64MachoTargetObjectFile();
185 return new TargetLoweringObjectFileMachO();
188 if (Subtarget->isTargetLinux())
189 return new X86LinuxTargetObjectFile();
190 if (Subtarget->isTargetELF())
191 return new TargetLoweringObjectFileELF();
192 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
193 return new TargetLoweringObjectFileCOFF();
194 llvm_unreachable("unknown subtarget type");
197 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
198 : TargetLowering(TM, createTLOF(TM)) {
199 Subtarget = &TM.getSubtarget<X86Subtarget>();
200 X86ScalarSSEf64 = Subtarget->hasSSE2();
201 X86ScalarSSEf32 = Subtarget->hasSSE1();
202 TD = getDataLayout();
204 resetOperationActions();
207 void X86TargetLowering::resetOperationActions() {
208 const TargetMachine &TM = getTargetMachine();
209 static bool FirstTimeThrough = true;
211 // If none of the target options have changed, then we don't need to reset the
212 // operation actions.
213 if (!FirstTimeThrough && TO == TM.Options) return;
215 if (!FirstTimeThrough) {
216 // Reinitialize the actions.
218 FirstTimeThrough = false;
223 // Set up the TargetLowering object.
224 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
226 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 setBooleanContents(ZeroOrOneBooleanContent);
228 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
229 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
231 // For 64-bit since we have so many registers use the ILP scheduler, for
232 // 32-bit code use the register pressure specific scheduling.
233 // For Atom, always use ILP scheduling.
234 if (Subtarget->isAtom())
235 setSchedulingPreference(Sched::ILP);
236 else if (Subtarget->is64Bit())
237 setSchedulingPreference(Sched::ILP);
239 setSchedulingPreference(Sched::RegPressure);
240 const X86RegisterInfo *RegInfo =
241 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
242 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
244 // Bypass expensive divides on Atom when compiling with O2
245 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
246 addBypassSlowDiv(32, 8);
247 if (Subtarget->is64Bit())
248 addBypassSlowDiv(64, 16);
251 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
252 // Setup Windows compiler runtime calls.
253 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
254 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
255 setLibcallName(RTLIB::SREM_I64, "_allrem");
256 setLibcallName(RTLIB::UREM_I64, "_aullrem");
257 setLibcallName(RTLIB::MUL_I64, "_allmul");
258 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
259 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
260 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
261 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
264 // The _ftol2 runtime function has an unusual calling conv, which
265 // is modeled by a special pseudo-instruction.
266 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
267 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
268 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
269 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
272 if (Subtarget->isTargetDarwin()) {
273 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
274 setUseUnderscoreSetJmp(false);
275 setUseUnderscoreLongJmp(false);
276 } else if (Subtarget->isTargetMingw()) {
277 // MS runtime is weird: it exports _setjmp, but longjmp!
278 setUseUnderscoreSetJmp(true);
279 setUseUnderscoreLongJmp(false);
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(true);
285 // Set up the register classes.
286 addRegisterClass(MVT::i8, &X86::GR8RegClass);
287 addRegisterClass(MVT::i16, &X86::GR16RegClass);
288 addRegisterClass(MVT::i32, &X86::GR32RegClass);
289 if (Subtarget->is64Bit())
290 addRegisterClass(MVT::i64, &X86::GR64RegClass);
292 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
294 // We don't accept any truncstore of integer registers.
295 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
296 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
297 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
298 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
299 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
300 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
302 // SETOEQ and SETUNE require checking two conditions.
303 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
306 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
310 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
312 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
313 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
314 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
316 if (Subtarget->is64Bit()) {
317 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
319 } else if (!TM.Options.UseSoftFloat) {
320 // We have an algorithm for SSE2->double, and we turn this into a
321 // 64-bit FILD followed by conditional FADD for other targets.
322 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
323 // We have an algorithm for SSE2, and we turn this into a 64-bit
324 // FILD for other targets.
325 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
328 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
330 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
331 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
333 if (!TM.Options.UseSoftFloat) {
334 // SSE has no i16 to fp conversion, only i32
335 if (X86ScalarSSEf32) {
336 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
337 // f32 and f64 cases are Legal, f80 case is not
338 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
340 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
341 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
344 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
348 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
349 // are Legal, f80 is custom lowered.
350 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
351 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
353 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
355 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
356 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
358 if (X86ScalarSSEf32) {
359 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
360 // f32 and f64 cases are Legal, f80 case is not
361 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
363 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
364 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
367 // Handle FP_TO_UINT by promoting the destination to a larger signed
369 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
370 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
371 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
373 if (Subtarget->is64Bit()) {
374 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
376 } else if (!TM.Options.UseSoftFloat) {
377 // Since AVX is a superset of SSE3, only check for SSE here.
378 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
379 // Expand FP_TO_UINT into a select.
380 // FIXME: We would like to use a Custom expander here eventually to do
381 // the optimal thing for SSE vs. the default expansion in the legalizer.
382 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
384 // With SSE3 we can use fisttpll to convert to a signed i64; without
385 // SSE, we're stuck with a fistpll.
386 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
389 if (isTargetFTOL()) {
390 // Use the _ftol2 runtime function, which has a pseudo-instruction
391 // to handle its weird calling convention.
392 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
395 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
396 if (!X86ScalarSSEf64) {
397 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
398 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
399 if (Subtarget->is64Bit()) {
400 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
401 // Without SSE, i64->f64 goes through memory.
402 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
406 // Scalar integer divide and remainder are lowered to use operations that
407 // produce two results, to match the available instructions. This exposes
408 // the two-result form to trivial CSE, which is able to combine x/y and x%y
409 // into a single instruction.
411 // Scalar integer multiply-high is also lowered to use two-result
412 // operations, to match the available instructions. However, plain multiply
413 // (low) operations are left as Legal, as there are single-result
414 // instructions for this in x86. Using the two-result multiply instructions
415 // when both high and low results are needed must be arranged by dagcombine.
416 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::MULHU, VT, Expand);
420 setOperationAction(ISD::SDIV, VT, Expand);
421 setOperationAction(ISD::UDIV, VT, Expand);
422 setOperationAction(ISD::SREM, VT, Expand);
423 setOperationAction(ISD::UREM, VT, Expand);
425 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
426 setOperationAction(ISD::ADDC, VT, Custom);
427 setOperationAction(ISD::ADDE, VT, Custom);
428 setOperationAction(ISD::SUBC, VT, Custom);
429 setOperationAction(ISD::SUBE, VT, Custom);
432 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
433 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
434 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
435 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
436 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
437 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
438 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
439 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
441 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
442 if (Subtarget->is64Bit())
443 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
444 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
446 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
447 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
448 setOperationAction(ISD::FREM , MVT::f32 , Expand);
449 setOperationAction(ISD::FREM , MVT::f64 , Expand);
450 setOperationAction(ISD::FREM , MVT::f80 , Expand);
451 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
453 // Promote the i8 variants and force them on up to i32 which has a shorter
455 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
456 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
457 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
458 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
459 if (Subtarget->hasBMI()) {
460 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
462 if (Subtarget->is64Bit())
463 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
465 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
466 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
467 if (Subtarget->is64Bit())
468 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
471 if (Subtarget->hasLZCNT()) {
472 // When promoting the i8 variants, force them to i32 for a shorter
474 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
475 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
476 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
477 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
478 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
479 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
480 if (Subtarget->is64Bit())
481 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
483 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
484 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
485 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
486 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
488 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
489 if (Subtarget->is64Bit()) {
490 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
491 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
495 if (Subtarget->hasPOPCNT()) {
496 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
498 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
499 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
500 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
501 if (Subtarget->is64Bit())
502 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
505 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
506 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
508 // These should be promoted to a larger select which is supported.
509 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
510 // X86 wants to expand cmov itself.
511 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
512 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
513 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
514 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
515 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
516 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
517 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
518 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
519 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
520 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
521 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
522 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
523 if (Subtarget->is64Bit()) {
524 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
525 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
527 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
528 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
529 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
530 // support continuation, user-level threading, and etc.. As a result, no
531 // other SjLj exception interfaces are implemented and please don't build
532 // your own exception handling based on them.
533 // LLVM/Clang supports zero-cost DWARF exception handling.
534 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
535 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
538 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
539 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
540 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
541 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
542 if (Subtarget->is64Bit())
543 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
544 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
545 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
546 if (Subtarget->is64Bit()) {
547 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
548 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
549 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
550 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
551 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
553 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
554 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
555 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
556 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
557 if (Subtarget->is64Bit()) {
558 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
559 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
560 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
563 if (Subtarget->hasSSE1())
564 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
566 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
568 // Expand certain atomics
569 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
571 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
573 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
576 if (!Subtarget->is64Bit()) {
577 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
578 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
579 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
583 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
584 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
585 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
586 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
587 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
588 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
591 if (Subtarget->hasCmpxchg16b()) {
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
595 // FIXME - use subtarget debug flags
596 if (!Subtarget->isTargetDarwin() &&
597 !Subtarget->isTargetELF() &&
598 !Subtarget->isTargetCygMing()) {
599 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
602 if (Subtarget->is64Bit()) {
603 setExceptionPointerRegister(X86::RAX);
604 setExceptionSelectorRegister(X86::RDX);
606 setExceptionPointerRegister(X86::EAX);
607 setExceptionSelectorRegister(X86::EDX);
609 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
610 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
612 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
613 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
615 setOperationAction(ISD::TRAP, MVT::Other, Legal);
616 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
618 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
619 setOperationAction(ISD::VASTART , MVT::Other, Custom);
620 setOperationAction(ISD::VAEND , MVT::Other, Expand);
621 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
622 // TargetInfo::X86_64ABIBuiltinVaList
623 setOperationAction(ISD::VAARG , MVT::Other, Custom);
624 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
626 // TargetInfo::CharPtrBuiltinVaList
627 setOperationAction(ISD::VAARG , MVT::Other, Expand);
628 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
631 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
632 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
634 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
635 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
636 MVT::i64 : MVT::i32, Custom);
637 else if (TM.Options.EnableSegmentedStacks)
638 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
639 MVT::i64 : MVT::i32, Custom);
641 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
642 MVT::i64 : MVT::i32, Expand);
644 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
645 // f32 and f64 use SSE.
646 // Set up the FP register classes.
647 addRegisterClass(MVT::f32, &X86::FR32RegClass);
648 addRegisterClass(MVT::f64, &X86::FR64RegClass);
650 // Use ANDPD to simulate FABS.
651 setOperationAction(ISD::FABS , MVT::f64, Custom);
652 setOperationAction(ISD::FABS , MVT::f32, Custom);
654 // Use XORP to simulate FNEG.
655 setOperationAction(ISD::FNEG , MVT::f64, Custom);
656 setOperationAction(ISD::FNEG , MVT::f32, Custom);
658 // Use ANDPD and ORPD to simulate FCOPYSIGN.
659 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
660 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
662 // Lower this to FGETSIGNx86 plus an AND.
663 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
664 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
666 // We don't support sin/cos/fmod
667 setOperationAction(ISD::FSIN , MVT::f64, Expand);
668 setOperationAction(ISD::FCOS , MVT::f64, Expand);
669 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN , MVT::f32, Expand);
671 setOperationAction(ISD::FCOS , MVT::f32, Expand);
672 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
674 // Expand FP immediates into loads from the stack, except for the special
676 addLegalFPImmediate(APFloat(+0.0)); // xorpd
677 addLegalFPImmediate(APFloat(+0.0f)); // xorps
678 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
679 // Use SSE for f32, x87 for f64.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f32, &X86::FR32RegClass);
682 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
684 // Use ANDPS to simulate FABS.
685 setOperationAction(ISD::FABS , MVT::f32, Custom);
687 // Use XORP to simulate FNEG.
688 setOperationAction(ISD::FNEG , MVT::f32, Custom);
690 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
692 // Use ANDPS and ORPS to simulate FCOPYSIGN.
693 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
694 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
696 // We don't support sin/cos/fmod
697 setOperationAction(ISD::FSIN , MVT::f32, Expand);
698 setOperationAction(ISD::FCOS , MVT::f32, Expand);
699 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
701 // Special cases we handle for FP constants.
702 addLegalFPImmediate(APFloat(+0.0f)); // xorps
703 addLegalFPImmediate(APFloat(+0.0)); // FLD0
704 addLegalFPImmediate(APFloat(+1.0)); // FLD1
705 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
706 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
708 if (!TM.Options.UnsafeFPMath) {
709 setOperationAction(ISD::FSIN , MVT::f64, Expand);
710 setOperationAction(ISD::FCOS , MVT::f64, Expand);
711 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
713 } else if (!TM.Options.UseSoftFloat) {
714 // f32 and f64 in x87.
715 // Set up the FP register classes.
716 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
717 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
719 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
720 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
721 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
722 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
724 if (!TM.Options.UnsafeFPMath) {
725 setOperationAction(ISD::FSIN , MVT::f64, Expand);
726 setOperationAction(ISD::FSIN , MVT::f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::f64, Expand);
728 setOperationAction(ISD::FCOS , MVT::f32, Expand);
729 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
730 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
732 addLegalFPImmediate(APFloat(+0.0)); // FLD0
733 addLegalFPImmediate(APFloat(+1.0)); // FLD1
734 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
735 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
736 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
737 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
738 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
739 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
742 // We don't support FMA.
743 setOperationAction(ISD::FMA, MVT::f64, Expand);
744 setOperationAction(ISD::FMA, MVT::f32, Expand);
746 // Long double always uses X87.
747 if (!TM.Options.UseSoftFloat) {
748 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
749 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
752 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
753 addLegalFPImmediate(TmpFlt); // FLD0
755 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
758 APFloat TmpFlt2(+1.0);
759 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
761 addLegalFPImmediate(TmpFlt2); // FLD1
762 TmpFlt2.changeSign();
763 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
766 if (!TM.Options.UnsafeFPMath) {
767 setOperationAction(ISD::FSIN , MVT::f80, Expand);
768 setOperationAction(ISD::FCOS , MVT::f80, Expand);
769 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
772 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
773 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
774 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
775 setOperationAction(ISD::FRINT, MVT::f80, Expand);
776 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
777 setOperationAction(ISD::FMA, MVT::f80, Expand);
780 // Always use a library call for pow.
781 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
782 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
783 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
785 setOperationAction(ISD::FLOG, MVT::f80, Expand);
786 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
787 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
788 setOperationAction(ISD::FEXP, MVT::f80, Expand);
789 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
791 // First set operation action for all vector types to either promote
792 // (for widening) or expand (for scalarization). Then we will selectively
793 // turn on ones that can be effectively codegen'd.
794 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
795 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
796 MVT VT = (MVT::SimpleValueType)i;
797 setOperationAction(ISD::ADD , VT, Expand);
798 setOperationAction(ISD::SUB , VT, Expand);
799 setOperationAction(ISD::FADD, VT, Expand);
800 setOperationAction(ISD::FNEG, VT, Expand);
801 setOperationAction(ISD::FSUB, VT, Expand);
802 setOperationAction(ISD::MUL , VT, Expand);
803 setOperationAction(ISD::FMUL, VT, Expand);
804 setOperationAction(ISD::SDIV, VT, Expand);
805 setOperationAction(ISD::UDIV, VT, Expand);
806 setOperationAction(ISD::FDIV, VT, Expand);
807 setOperationAction(ISD::SREM, VT, Expand);
808 setOperationAction(ISD::UREM, VT, Expand);
809 setOperationAction(ISD::LOAD, VT, Expand);
810 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
811 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
812 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
813 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
814 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
815 setOperationAction(ISD::FABS, VT, Expand);
816 setOperationAction(ISD::FSIN, VT, Expand);
817 setOperationAction(ISD::FSINCOS, VT, Expand);
818 setOperationAction(ISD::FCOS, VT, Expand);
819 setOperationAction(ISD::FSINCOS, VT, Expand);
820 setOperationAction(ISD::FREM, VT, Expand);
821 setOperationAction(ISD::FMA, VT, Expand);
822 setOperationAction(ISD::FPOWI, VT, Expand);
823 setOperationAction(ISD::FSQRT, VT, Expand);
824 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
825 setOperationAction(ISD::FFLOOR, VT, Expand);
826 setOperationAction(ISD::FCEIL, VT, Expand);
827 setOperationAction(ISD::FTRUNC, VT, Expand);
828 setOperationAction(ISD::FRINT, VT, Expand);
829 setOperationAction(ISD::FNEARBYINT, VT, Expand);
830 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
831 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
832 setOperationAction(ISD::SDIVREM, VT, Expand);
833 setOperationAction(ISD::UDIVREM, VT, Expand);
834 setOperationAction(ISD::FPOW, VT, Expand);
835 setOperationAction(ISD::CTPOP, VT, Expand);
836 setOperationAction(ISD::CTTZ, VT, Expand);
837 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
838 setOperationAction(ISD::CTLZ, VT, Expand);
839 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
840 setOperationAction(ISD::SHL, VT, Expand);
841 setOperationAction(ISD::SRA, VT, Expand);
842 setOperationAction(ISD::SRL, VT, Expand);
843 setOperationAction(ISD::ROTL, VT, Expand);
844 setOperationAction(ISD::ROTR, VT, Expand);
845 setOperationAction(ISD::BSWAP, VT, Expand);
846 setOperationAction(ISD::SETCC, VT, Expand);
847 setOperationAction(ISD::FLOG, VT, Expand);
848 setOperationAction(ISD::FLOG2, VT, Expand);
849 setOperationAction(ISD::FLOG10, VT, Expand);
850 setOperationAction(ISD::FEXP, VT, Expand);
851 setOperationAction(ISD::FEXP2, VT, Expand);
852 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
853 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
854 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
855 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
856 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
857 setOperationAction(ISD::TRUNCATE, VT, Expand);
858 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
859 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
860 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
861 setOperationAction(ISD::VSELECT, VT, Expand);
862 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
863 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
864 setTruncStoreAction(VT,
865 (MVT::SimpleValueType)InnerVT, Expand);
866 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
867 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
868 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
871 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
872 // with -msoft-float, disable use of MMX as well.
873 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
874 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
875 // No operations on x86mmx supported, everything uses intrinsics.
878 // MMX-sized vectors (other than x86mmx) are expected to be expanded
879 // into smaller operations.
880 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
881 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
882 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
883 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
884 setOperationAction(ISD::AND, MVT::v8i8, Expand);
885 setOperationAction(ISD::AND, MVT::v4i16, Expand);
886 setOperationAction(ISD::AND, MVT::v2i32, Expand);
887 setOperationAction(ISD::AND, MVT::v1i64, Expand);
888 setOperationAction(ISD::OR, MVT::v8i8, Expand);
889 setOperationAction(ISD::OR, MVT::v4i16, Expand);
890 setOperationAction(ISD::OR, MVT::v2i32, Expand);
891 setOperationAction(ISD::OR, MVT::v1i64, Expand);
892 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
893 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
894 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
895 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
896 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
897 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
898 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
899 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
901 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
902 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
903 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
904 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
905 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
906 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
907 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
908 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
910 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
911 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
913 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
914 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
915 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
916 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
918 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
919 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
920 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
921 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
922 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
923 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
924 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
927 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
928 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
930 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
931 // registers cannot be used even for integer operations.
932 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
933 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
934 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
935 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
937 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
938 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
939 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
940 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
941 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
942 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
943 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
944 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
945 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
946 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
947 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
948 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
949 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
950 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
951 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
952 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
953 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
954 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
956 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
957 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
958 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
959 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
961 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
962 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
963 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
964 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
967 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
968 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
969 MVT VT = (MVT::SimpleValueType)i;
970 // Do not attempt to custom lower non-power-of-2 vectors
971 if (!isPowerOf2_32(VT.getVectorNumElements()))
973 // Do not attempt to custom lower non-128-bit vectors
974 if (!VT.is128BitVector())
976 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
977 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
978 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
981 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
982 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
983 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
984 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
985 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
988 if (Subtarget->is64Bit()) {
989 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
990 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
993 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
994 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
995 MVT VT = (MVT::SimpleValueType)i;
997 // Do not attempt to promote non-128-bit vectors
998 if (!VT.is128BitVector())
1001 setOperationAction(ISD::AND, VT, Promote);
1002 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1003 setOperationAction(ISD::OR, VT, Promote);
1004 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1005 setOperationAction(ISD::XOR, VT, Promote);
1006 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1007 setOperationAction(ISD::LOAD, VT, Promote);
1008 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1009 setOperationAction(ISD::SELECT, VT, Promote);
1010 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1013 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1015 // Custom lower v2i64 and v2f64 selects.
1016 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1017 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1018 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1021 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1022 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1024 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1025 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1026 // As there is no 64-bit GPR available, we need build a special custom
1027 // sequence to convert from v2i32 to v2f32.
1028 if (!Subtarget->is64Bit())
1029 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1031 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1032 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1034 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1037 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1038 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1039 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1040 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1041 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1042 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1043 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1044 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1045 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1046 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1047 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1049 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1050 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1051 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1052 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1053 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1060 // FIXME: Do we need to handle scalar-to-vector here?
1061 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1063 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1064 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1065 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1066 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1067 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1069 // i8 and i16 vectors are custom , because the source register and source
1070 // source memory operand types are not the same width. f32 vectors are
1071 // custom since the immediate controlling the insert encodes additional
1073 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1074 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1075 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1076 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1078 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1079 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1080 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1081 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1083 // FIXME: these should be Legal but thats only for the case where
1084 // the index is constant. For now custom expand to deal with that.
1085 if (Subtarget->is64Bit()) {
1086 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1087 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1091 if (Subtarget->hasSSE2()) {
1092 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1093 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1095 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1098 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1101 // In the customized shift lowering, the legal cases in AVX2 will be
1103 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1104 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1106 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1107 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1109 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1111 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1112 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1115 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1116 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1117 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1118 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1119 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1120 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1121 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1123 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1124 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1125 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1127 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1128 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1129 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1130 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1132 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1133 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1134 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1135 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1136 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1138 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1140 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1141 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1142 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1143 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1144 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1145 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1146 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1147 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1148 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1149 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1150 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1151 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1153 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1154 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1156 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1158 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1159 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1160 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1161 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1163 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1164 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1165 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1167 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1169 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1170 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1172 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1173 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1176 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1178 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1180 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1181 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1182 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1183 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1186 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1187 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1189 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1191 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1192 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1194 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1195 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1196 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1197 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1198 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1199 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1201 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1202 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1203 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1204 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1205 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1206 setOperationAction(ISD::FMA, MVT::f32, Legal);
1207 setOperationAction(ISD::FMA, MVT::f64, Legal);
1210 if (Subtarget->hasInt256()) {
1211 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1212 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1214 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1216 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1217 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1218 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1219 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1221 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1222 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1223 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1224 // Don't lower v32i8 because there is no 128-bit byte mul
1226 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1228 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1230 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1231 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1232 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1233 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1236 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1237 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1238 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1240 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1241 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1242 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1243 // Don't lower v32i8 because there is no 128-bit byte mul
1246 // In the customized shift lowering, the legal cases in AVX2 will be
1248 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1254 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1256 // Custom lower several nodes for 256-bit types.
1257 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1258 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1259 MVT VT = (MVT::SimpleValueType)i;
1261 // Extract subvector is special because the value type
1262 // (result) is 128-bit but the source is 256-bit wide.
1263 if (VT.is128BitVector())
1264 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1266 // Do not attempt to custom lower other non-256-bit vectors
1267 if (!VT.is256BitVector())
1270 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1280 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1281 MVT VT = (MVT::SimpleValueType)i;
1283 // Do not attempt to promote non-256-bit vectors
1284 if (!VT.is256BitVector())
1287 setOperationAction(ISD::AND, VT, Promote);
1288 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1289 setOperationAction(ISD::OR, VT, Promote);
1290 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1291 setOperationAction(ISD::XOR, VT, Promote);
1292 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1293 setOperationAction(ISD::LOAD, VT, Promote);
1294 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1295 setOperationAction(ISD::SELECT, VT, Promote);
1296 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1300 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1301 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1302 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1303 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1304 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1307 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1309 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1310 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1311 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1312 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1313 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1314 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1316 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1317 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1318 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1319 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1320 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1321 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1323 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1324 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1325 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1326 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1327 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1328 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1329 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1330 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1331 setOperationAction(ISD::SDIV, MVT::v16i32, Custom);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1338 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1340 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1341 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1343 setOperationAction(ISD::TRUNCATE, MVT::i1, Legal);
1344 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1345 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1346 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1347 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1348 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1349 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1350 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1351 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1352 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1353 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1354 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1368 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1369 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1370 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1371 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1373 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1374 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1376 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1377 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1379 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1381 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1382 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1384 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1385 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1387 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1390 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1391 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1392 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1394 // Custom lower several nodes.
1395 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1396 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1397 MVT VT = (MVT::SimpleValueType)i;
1399 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1400 // Extract subvector is special because the value type
1401 // (result) is 256/128-bit but the source is 512-bit wide.
1402 if (VT.is128BitVector() || VT.is256BitVector())
1403 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1405 if (VT.getVectorElementType() == MVT::i1)
1406 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1408 // Do not attempt to custom lower other non-512-bit vectors
1409 if (!VT.is512BitVector())
1412 if (VT != MVT::v8i64) {
1413 setOperationAction(ISD::XOR, VT, Promote);
1414 AddPromotedToType (ISD::XOR, VT, MVT::v8i64);
1415 setOperationAction(ISD::OR, VT, Promote);
1416 AddPromotedToType (ISD::OR, VT, MVT::v8i64);
1417 setOperationAction(ISD::AND, VT, Promote);
1418 AddPromotedToType (ISD::AND, VT, MVT::v8i64);
1420 if ( EltSize >= 32) {
1421 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1422 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1423 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1424 setOperationAction(ISD::VSELECT, VT, Legal);
1425 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1426 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1427 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1430 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1431 MVT VT = (MVT::SimpleValueType)i;
1433 // Do not attempt to promote non-256-bit vectors
1434 if (!VT.is512BitVector())
1437 setOperationAction(ISD::LOAD, VT, Promote);
1438 AddPromotedToType (ISD::LOAD, VT, MVT::v8i64);
1439 setOperationAction(ISD::SELECT, VT, Promote);
1440 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1444 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1445 // of this type with custom code.
1446 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1447 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1448 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1452 // We want to custom lower some of our intrinsics.
1453 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1454 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1456 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1457 // handle type legalization for these operations here.
1459 // FIXME: We really should do custom legalization for addition and
1460 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1461 // than generic legalization for 64-bit multiplication-with-overflow, though.
1462 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1463 // Add/Sub/Mul with overflow operations are custom lowered.
1465 setOperationAction(ISD::SADDO, VT, Custom);
1466 setOperationAction(ISD::UADDO, VT, Custom);
1467 setOperationAction(ISD::SSUBO, VT, Custom);
1468 setOperationAction(ISD::USUBO, VT, Custom);
1469 setOperationAction(ISD::SMULO, VT, Custom);
1470 setOperationAction(ISD::UMULO, VT, Custom);
1473 // There are no 8-bit 3-address imul/mul instructions
1474 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1475 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1477 if (!Subtarget->is64Bit()) {
1478 // These libcalls are not available in 32-bit.
1479 setLibcallName(RTLIB::SHL_I128, 0);
1480 setLibcallName(RTLIB::SRL_I128, 0);
1481 setLibcallName(RTLIB::SRA_I128, 0);
1484 // Combine sin / cos into one node or libcall if possible.
1485 if (Subtarget->hasSinCos()) {
1486 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1487 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1488 if (Subtarget->isTargetDarwin()) {
1489 // For MacOSX, we don't want to the normal expansion of a libcall to
1490 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1492 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1493 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1497 // We have target-specific dag combine patterns for the following nodes:
1498 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1499 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1500 setTargetDAGCombine(ISD::VSELECT);
1501 setTargetDAGCombine(ISD::SELECT);
1502 setTargetDAGCombine(ISD::SHL);
1503 setTargetDAGCombine(ISD::SRA);
1504 setTargetDAGCombine(ISD::SRL);
1505 setTargetDAGCombine(ISD::OR);
1506 setTargetDAGCombine(ISD::AND);
1507 setTargetDAGCombine(ISD::ADD);
1508 setTargetDAGCombine(ISD::FADD);
1509 setTargetDAGCombine(ISD::FSUB);
1510 setTargetDAGCombine(ISD::FMA);
1511 setTargetDAGCombine(ISD::SUB);
1512 setTargetDAGCombine(ISD::LOAD);
1513 setTargetDAGCombine(ISD::STORE);
1514 setTargetDAGCombine(ISD::ZERO_EXTEND);
1515 setTargetDAGCombine(ISD::ANY_EXTEND);
1516 setTargetDAGCombine(ISD::SIGN_EXTEND);
1517 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1518 setTargetDAGCombine(ISD::TRUNCATE);
1519 setTargetDAGCombine(ISD::SINT_TO_FP);
1520 setTargetDAGCombine(ISD::SETCC);
1521 if (Subtarget->is64Bit())
1522 setTargetDAGCombine(ISD::MUL);
1523 setTargetDAGCombine(ISD::XOR);
1525 computeRegisterProperties();
1527 // On Darwin, -Os means optimize for size without hurting performance,
1528 // do not reduce the limit.
1529 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1530 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1531 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1532 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1533 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1534 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1535 setPrefLoopAlignment(4); // 2^4 bytes.
1537 // Predictable cmov don't hurt on atom because it's in-order.
1538 PredictableSelectIsExpensive = !Subtarget->isAtom();
1540 setPrefFunctionAlignment(4); // 2^4 bytes.
1543 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1544 if (!VT.isVector()) return MVT::i8;
1545 return VT.changeVectorElementTypeToInteger();
1548 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1549 /// the desired ByVal argument alignment.
1550 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1553 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1554 if (VTy->getBitWidth() == 128)
1556 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1557 unsigned EltAlign = 0;
1558 getMaxByValAlign(ATy->getElementType(), EltAlign);
1559 if (EltAlign > MaxAlign)
1560 MaxAlign = EltAlign;
1561 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1562 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1563 unsigned EltAlign = 0;
1564 getMaxByValAlign(STy->getElementType(i), EltAlign);
1565 if (EltAlign > MaxAlign)
1566 MaxAlign = EltAlign;
1573 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1574 /// function arguments in the caller parameter area. For X86, aggregates
1575 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1576 /// are at 4-byte boundaries.
1577 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1578 if (Subtarget->is64Bit()) {
1579 // Max of 8 and alignment of type.
1580 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1587 if (Subtarget->hasSSE1())
1588 getMaxByValAlign(Ty, Align);
1592 /// getOptimalMemOpType - Returns the target specific optimal type for load
1593 /// and store operations as a result of memset, memcpy, and memmove
1594 /// lowering. If DstAlign is zero that means it's safe to destination
1595 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1596 /// means there isn't a need to check it against alignment requirement,
1597 /// probably because the source does not need to be loaded. If 'IsMemset' is
1598 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1599 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1600 /// source is constant so it does not need to be loaded.
1601 /// It returns EVT::Other if the type should be determined using generic
1602 /// target-independent logic.
1604 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1605 unsigned DstAlign, unsigned SrcAlign,
1606 bool IsMemset, bool ZeroMemset,
1608 MachineFunction &MF) const {
1609 const Function *F = MF.getFunction();
1610 if ((!IsMemset || ZeroMemset) &&
1611 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1612 Attribute::NoImplicitFloat)) {
1614 (Subtarget->isUnalignedMemAccessFast() ||
1615 ((DstAlign == 0 || DstAlign >= 16) &&
1616 (SrcAlign == 0 || SrcAlign >= 16)))) {
1618 if (Subtarget->hasInt256())
1620 if (Subtarget->hasFp256())
1623 if (Subtarget->hasSSE2())
1625 if (Subtarget->hasSSE1())
1627 } else if (!MemcpyStrSrc && Size >= 8 &&
1628 !Subtarget->is64Bit() &&
1629 Subtarget->hasSSE2()) {
1630 // Do not use f64 to lower memcpy if source is string constant. It's
1631 // better to use i32 to avoid the loads.
1635 if (Subtarget->is64Bit() && Size >= 8)
1640 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1642 return X86ScalarSSEf32;
1643 else if (VT == MVT::f64)
1644 return X86ScalarSSEf64;
1649 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1651 *Fast = Subtarget->isUnalignedMemAccessFast();
1655 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1656 /// current function. The returned value is a member of the
1657 /// MachineJumpTableInfo::JTEntryKind enum.
1658 unsigned X86TargetLowering::getJumpTableEncoding() const {
1659 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1661 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1662 Subtarget->isPICStyleGOT())
1663 return MachineJumpTableInfo::EK_Custom32;
1665 // Otherwise, use the normal jump table encoding heuristics.
1666 return TargetLowering::getJumpTableEncoding();
1670 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1671 const MachineBasicBlock *MBB,
1672 unsigned uid,MCContext &Ctx) const{
1673 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1674 Subtarget->isPICStyleGOT());
1675 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1677 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1678 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1681 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1683 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1684 SelectionDAG &DAG) const {
1685 if (!Subtarget->is64Bit())
1686 // This doesn't have SDLoc associated with it, but is not really the
1687 // same as a Register.
1688 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1692 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1693 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1695 const MCExpr *X86TargetLowering::
1696 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1697 MCContext &Ctx) const {
1698 // X86-64 uses RIP relative addressing based on the jump table label.
1699 if (Subtarget->isPICStyleRIPRel())
1700 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1702 // Otherwise, the reference is relative to the PIC base.
1703 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1706 // FIXME: Why this routine is here? Move to RegInfo!
1707 std::pair<const TargetRegisterClass*, uint8_t>
1708 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1709 const TargetRegisterClass *RRC = 0;
1711 switch (VT.SimpleTy) {
1713 return TargetLowering::findRepresentativeClass(VT);
1714 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1715 RRC = Subtarget->is64Bit() ?
1716 (const TargetRegisterClass*)&X86::GR64RegClass :
1717 (const TargetRegisterClass*)&X86::GR32RegClass;
1720 RRC = &X86::VR64RegClass;
1722 case MVT::f32: case MVT::f64:
1723 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1724 case MVT::v4f32: case MVT::v2f64:
1725 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1727 RRC = &X86::VR128RegClass;
1730 return std::make_pair(RRC, Cost);
1733 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1734 unsigned &Offset) const {
1735 if (!Subtarget->isTargetLinux())
1738 if (Subtarget->is64Bit()) {
1739 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1741 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1753 //===----------------------------------------------------------------------===//
1754 // Return Value Calling Convention Implementation
1755 //===----------------------------------------------------------------------===//
1757 #include "X86GenCallingConv.inc"
1760 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1761 MachineFunction &MF, bool isVarArg,
1762 const SmallVectorImpl<ISD::OutputArg> &Outs,
1763 LLVMContext &Context) const {
1764 SmallVector<CCValAssign, 16> RVLocs;
1765 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1767 return CCInfo.CheckReturn(Outs, RetCC_X86);
1771 X86TargetLowering::LowerReturn(SDValue Chain,
1772 CallingConv::ID CallConv, bool isVarArg,
1773 const SmallVectorImpl<ISD::OutputArg> &Outs,
1774 const SmallVectorImpl<SDValue> &OutVals,
1775 SDLoc dl, SelectionDAG &DAG) const {
1776 MachineFunction &MF = DAG.getMachineFunction();
1777 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1779 SmallVector<CCValAssign, 16> RVLocs;
1780 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1781 RVLocs, *DAG.getContext());
1782 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1785 SmallVector<SDValue, 6> RetOps;
1786 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1787 // Operand #1 = Bytes To Pop
1788 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1791 // Copy the result values into the output registers.
1792 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1793 CCValAssign &VA = RVLocs[i];
1794 assert(VA.isRegLoc() && "Can only return in registers!");
1795 SDValue ValToCopy = OutVals[i];
1796 EVT ValVT = ValToCopy.getValueType();
1798 // Promote values to the appropriate types
1799 if (VA.getLocInfo() == CCValAssign::SExt)
1800 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1801 else if (VA.getLocInfo() == CCValAssign::ZExt)
1802 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1803 else if (VA.getLocInfo() == CCValAssign::AExt)
1804 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1805 else if (VA.getLocInfo() == CCValAssign::BCvt)
1806 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1808 // If this is x86-64, and we disabled SSE, we can't return FP values,
1809 // or SSE or MMX vectors.
1810 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1811 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1812 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1813 report_fatal_error("SSE register return with SSE disabled");
1815 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1816 // llvm-gcc has never done it right and no one has noticed, so this
1817 // should be OK for now.
1818 if (ValVT == MVT::f64 &&
1819 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1820 report_fatal_error("SSE2 register return with SSE2 disabled");
1822 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1823 // the RET instruction and handled by the FP Stackifier.
1824 if (VA.getLocReg() == X86::ST0 ||
1825 VA.getLocReg() == X86::ST1) {
1826 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1827 // change the value to the FP stack register class.
1828 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1829 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1830 RetOps.push_back(ValToCopy);
1831 // Don't emit a copytoreg.
1835 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1836 // which is returned in RAX / RDX.
1837 if (Subtarget->is64Bit()) {
1838 if (ValVT == MVT::x86mmx) {
1839 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1840 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1841 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1843 // If we don't have SSE2 available, convert to v4f32 so the generated
1844 // register is legal.
1845 if (!Subtarget->hasSSE2())
1846 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1851 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1852 Flag = Chain.getValue(1);
1853 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1856 // The x86-64 ABIs require that for returning structs by value we copy
1857 // the sret argument into %rax/%eax (depending on ABI) for the return.
1858 // Win32 requires us to put the sret argument to %eax as well.
1859 // We saved the argument into a virtual register in the entry block,
1860 // so now we copy the value out and into %rax/%eax.
1861 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1862 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1863 MachineFunction &MF = DAG.getMachineFunction();
1864 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1865 unsigned Reg = FuncInfo->getSRetReturnReg();
1867 "SRetReturnReg should have been set in LowerFormalArguments().");
1868 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1871 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1872 X86::RAX : X86::EAX;
1873 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1874 Flag = Chain.getValue(1);
1876 // RAX/EAX now acts like a return value.
1877 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1880 RetOps[0] = Chain; // Update chain.
1882 // Add the flag if we have it.
1884 RetOps.push_back(Flag);
1886 return DAG.getNode(X86ISD::RET_FLAG, dl,
1887 MVT::Other, &RetOps[0], RetOps.size());
1890 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1891 if (N->getNumValues() != 1)
1893 if (!N->hasNUsesOfValue(1, 0))
1896 SDValue TCChain = Chain;
1897 SDNode *Copy = *N->use_begin();
1898 if (Copy->getOpcode() == ISD::CopyToReg) {
1899 // If the copy has a glue operand, we conservatively assume it isn't safe to
1900 // perform a tail call.
1901 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1903 TCChain = Copy->getOperand(0);
1904 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1907 bool HasRet = false;
1908 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1910 if (UI->getOpcode() != X86ISD::RET_FLAG)
1923 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1924 ISD::NodeType ExtendKind) const {
1926 // TODO: Is this also valid on 32-bit?
1927 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1928 ReturnMVT = MVT::i8;
1930 ReturnMVT = MVT::i32;
1932 MVT MinVT = getRegisterType(ReturnMVT);
1933 return VT.bitsLT(MinVT) ? MinVT : VT;
1936 /// LowerCallResult - Lower the result values of a call into the
1937 /// appropriate copies out of appropriate physical registers.
1940 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1941 CallingConv::ID CallConv, bool isVarArg,
1942 const SmallVectorImpl<ISD::InputArg> &Ins,
1943 SDLoc dl, SelectionDAG &DAG,
1944 SmallVectorImpl<SDValue> &InVals) const {
1946 // Assign locations to each value returned by this call.
1947 SmallVector<CCValAssign, 16> RVLocs;
1948 bool Is64Bit = Subtarget->is64Bit();
1949 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1950 getTargetMachine(), RVLocs, *DAG.getContext());
1951 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1953 // Copy all of the result registers out of their specified physreg.
1954 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1955 CCValAssign &VA = RVLocs[i];
1956 EVT CopyVT = VA.getValVT();
1958 // If this is x86-64, and we disabled SSE, we can't return FP values
1959 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1960 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1961 report_fatal_error("SSE register return with SSE disabled");
1966 // If this is a call to a function that returns an fp value on the floating
1967 // point stack, we must guarantee the value is popped from the stack, so
1968 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1969 // if the return value is not used. We use the FpPOP_RETVAL instruction
1971 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1972 // If we prefer to use the value in xmm registers, copy it out as f80 and
1973 // use a truncate to move it from fp stack reg to xmm reg.
1974 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1975 SDValue Ops[] = { Chain, InFlag };
1976 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1977 MVT::Other, MVT::Glue, Ops), 1);
1978 Val = Chain.getValue(0);
1980 // Round the f80 to the right size, which also moves it to the appropriate
1982 if (CopyVT != VA.getValVT())
1983 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1984 // This truncation won't change the value.
1985 DAG.getIntPtrConstant(1));
1987 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1988 CopyVT, InFlag).getValue(1);
1989 Val = Chain.getValue(0);
1991 InFlag = Chain.getValue(2);
1992 InVals.push_back(Val);
1998 //===----------------------------------------------------------------------===//
1999 // C & StdCall & Fast Calling Convention implementation
2000 //===----------------------------------------------------------------------===//
2001 // StdCall calling convention seems to be standard for many Windows' API
2002 // routines and around. It differs from C calling convention just a little:
2003 // callee should clean up the stack, not caller. Symbols should be also
2004 // decorated in some fancy way :) It doesn't support any vector arguments.
2005 // For info on fast calling convention see Fast Calling Convention (tail call)
2006 // implementation LowerX86_32FastCCCallTo.
2008 /// CallIsStructReturn - Determines whether a call uses struct return
2010 enum StructReturnType {
2015 static StructReturnType
2016 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2018 return NotStructReturn;
2020 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2021 if (!Flags.isSRet())
2022 return NotStructReturn;
2023 if (Flags.isInReg())
2024 return RegStructReturn;
2025 return StackStructReturn;
2028 /// ArgsAreStructReturn - Determines whether a function uses struct
2029 /// return semantics.
2030 static StructReturnType
2031 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2033 return NotStructReturn;
2035 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2036 if (!Flags.isSRet())
2037 return NotStructReturn;
2038 if (Flags.isInReg())
2039 return RegStructReturn;
2040 return StackStructReturn;
2043 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2044 /// by "Src" to address "Dst" with size and alignment information specified by
2045 /// the specific parameter attribute. The copy will be passed as a byval
2046 /// function parameter.
2048 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2049 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2051 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2053 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2054 /*isVolatile*/false, /*AlwaysInline=*/true,
2055 MachinePointerInfo(), MachinePointerInfo());
2058 /// IsTailCallConvention - Return true if the calling convention is one that
2059 /// supports tail call optimization.
2060 static bool IsTailCallConvention(CallingConv::ID CC) {
2061 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2062 CC == CallingConv::HiPE);
2065 /// \brief Return true if the calling convention is a C calling convention.
2066 static bool IsCCallConvention(CallingConv::ID CC) {
2067 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2068 CC == CallingConv::X86_64_SysV);
2071 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2072 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2076 CallingConv::ID CalleeCC = CS.getCallingConv();
2077 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2083 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2084 /// a tailcall target by changing its ABI.
2085 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2086 bool GuaranteedTailCallOpt) {
2087 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2091 X86TargetLowering::LowerMemArgument(SDValue Chain,
2092 CallingConv::ID CallConv,
2093 const SmallVectorImpl<ISD::InputArg> &Ins,
2094 SDLoc dl, SelectionDAG &DAG,
2095 const CCValAssign &VA,
2096 MachineFrameInfo *MFI,
2098 // Create the nodes corresponding to a load from this parameter slot.
2099 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2100 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
2101 getTargetMachine().Options.GuaranteedTailCallOpt);
2102 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2105 // If value is passed by pointer we have address passed instead of the value
2107 if (VA.getLocInfo() == CCValAssign::Indirect)
2108 ValVT = VA.getLocVT();
2110 ValVT = VA.getValVT();
2112 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2113 // changed with more analysis.
2114 // In case of tail call optimization mark all arguments mutable. Since they
2115 // could be overwritten by lowering of arguments in case of a tail call.
2116 if (Flags.isByVal()) {
2117 unsigned Bytes = Flags.getByValSize();
2118 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2119 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2120 return DAG.getFrameIndex(FI, getPointerTy());
2122 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2123 VA.getLocMemOffset(), isImmutable);
2124 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2125 return DAG.getLoad(ValVT, dl, Chain, FIN,
2126 MachinePointerInfo::getFixedStack(FI),
2127 false, false, false, 0);
2132 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2133 CallingConv::ID CallConv,
2135 const SmallVectorImpl<ISD::InputArg> &Ins,
2138 SmallVectorImpl<SDValue> &InVals)
2140 MachineFunction &MF = DAG.getMachineFunction();
2141 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2143 const Function* Fn = MF.getFunction();
2144 if (Fn->hasExternalLinkage() &&
2145 Subtarget->isTargetCygMing() &&
2146 Fn->getName() == "main")
2147 FuncInfo->setForceFramePointer(true);
2149 MachineFrameInfo *MFI = MF.getFrameInfo();
2150 bool Is64Bit = Subtarget->is64Bit();
2151 bool IsWindows = Subtarget->isTargetWindows();
2152 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2154 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2155 "Var args not supported with calling convention fastcc, ghc or hipe");
2157 // Assign locations to all of the incoming arguments.
2158 SmallVector<CCValAssign, 16> ArgLocs;
2159 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2160 ArgLocs, *DAG.getContext());
2162 // Allocate shadow area for Win64
2164 CCInfo.AllocateStack(32, 8);
2166 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2168 unsigned LastVal = ~0U;
2170 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2171 CCValAssign &VA = ArgLocs[i];
2172 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2174 assert(VA.getValNo() != LastVal &&
2175 "Don't support value assigned to multiple locs yet");
2177 LastVal = VA.getValNo();
2179 if (VA.isRegLoc()) {
2180 EVT RegVT = VA.getLocVT();
2181 const TargetRegisterClass *RC;
2182 if (RegVT == MVT::i32)
2183 RC = &X86::GR32RegClass;
2184 else if (Is64Bit && RegVT == MVT::i64)
2185 RC = &X86::GR64RegClass;
2186 else if (RegVT == MVT::f32)
2187 RC = &X86::FR32RegClass;
2188 else if (RegVT == MVT::f64)
2189 RC = &X86::FR64RegClass;
2190 else if (RegVT.is512BitVector())
2191 RC = &X86::VR512RegClass;
2192 else if (RegVT.is256BitVector())
2193 RC = &X86::VR256RegClass;
2194 else if (RegVT.is128BitVector())
2195 RC = &X86::VR128RegClass;
2196 else if (RegVT == MVT::x86mmx)
2197 RC = &X86::VR64RegClass;
2198 else if (RegVT == MVT::v8i1)
2199 RC = &X86::VK8RegClass;
2200 else if (RegVT == MVT::v16i1)
2201 RC = &X86::VK16RegClass;
2203 llvm_unreachable("Unknown argument type!");
2205 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2206 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2208 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2209 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2211 if (VA.getLocInfo() == CCValAssign::SExt)
2212 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2213 DAG.getValueType(VA.getValVT()));
2214 else if (VA.getLocInfo() == CCValAssign::ZExt)
2215 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2216 DAG.getValueType(VA.getValVT()));
2217 else if (VA.getLocInfo() == CCValAssign::BCvt)
2218 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2220 if (VA.isExtInLoc()) {
2221 // Handle MMX values passed in XMM regs.
2222 if (RegVT.isVector())
2223 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2225 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2228 assert(VA.isMemLoc());
2229 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2232 // If value is passed via pointer - do a load.
2233 if (VA.getLocInfo() == CCValAssign::Indirect)
2234 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2235 MachinePointerInfo(), false, false, false, 0);
2237 InVals.push_back(ArgValue);
2240 // The x86-64 ABIs require that for returning structs by value we copy
2241 // the sret argument into %rax/%eax (depending on ABI) for the return.
2242 // Win32 requires us to put the sret argument to %eax as well.
2243 // Save the argument into a virtual register so that we can access it
2244 // from the return points.
2245 if (MF.getFunction()->hasStructRetAttr() &&
2246 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2247 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2248 unsigned Reg = FuncInfo->getSRetReturnReg();
2250 MVT PtrTy = getPointerTy();
2251 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2252 FuncInfo->setSRetReturnReg(Reg);
2254 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2255 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2258 unsigned StackSize = CCInfo.getNextStackOffset();
2259 // Align stack specially for tail calls.
2260 if (FuncIsMadeTailCallSafe(CallConv,
2261 MF.getTarget().Options.GuaranteedTailCallOpt))
2262 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2264 // If the function takes variable number of arguments, make a frame index for
2265 // the start of the first vararg value... for expansion of llvm.va_start.
2267 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2268 CallConv != CallingConv::X86_ThisCall)) {
2269 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2272 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2274 // FIXME: We should really autogenerate these arrays
2275 static const uint16_t GPR64ArgRegsWin64[] = {
2276 X86::RCX, X86::RDX, X86::R8, X86::R9
2278 static const uint16_t GPR64ArgRegs64Bit[] = {
2279 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2281 static const uint16_t XMMArgRegs64Bit[] = {
2282 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2283 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2285 const uint16_t *GPR64ArgRegs;
2286 unsigned NumXMMRegs = 0;
2289 // The XMM registers which might contain var arg parameters are shadowed
2290 // in their paired GPR. So we only need to save the GPR to their home
2292 TotalNumIntRegs = 4;
2293 GPR64ArgRegs = GPR64ArgRegsWin64;
2295 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2296 GPR64ArgRegs = GPR64ArgRegs64Bit;
2298 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2301 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2304 bool NoImplicitFloatOps = Fn->getAttributes().
2305 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2306 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2307 "SSE register cannot be used when SSE is disabled!");
2308 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2309 NoImplicitFloatOps) &&
2310 "SSE register cannot be used when SSE is disabled!");
2311 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2312 !Subtarget->hasSSE1())
2313 // Kernel mode asks for SSE to be disabled, so don't push them
2315 TotalNumXMMRegs = 0;
2318 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2319 // Get to the caller-allocated home save location. Add 8 to account
2320 // for the return address.
2321 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2322 FuncInfo->setRegSaveFrameIndex(
2323 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2324 // Fixup to set vararg frame on shadow area (4 x i64).
2326 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2328 // For X86-64, if there are vararg parameters that are passed via
2329 // registers, then we must store them to their spots on the stack so
2330 // they may be loaded by deferencing the result of va_next.
2331 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2332 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2333 FuncInfo->setRegSaveFrameIndex(
2334 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2338 // Store the integer parameter registers.
2339 SmallVector<SDValue, 8> MemOps;
2340 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2342 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2343 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2344 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2345 DAG.getIntPtrConstant(Offset));
2346 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2347 &X86::GR64RegClass);
2348 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2350 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2351 MachinePointerInfo::getFixedStack(
2352 FuncInfo->getRegSaveFrameIndex(), Offset),
2354 MemOps.push_back(Store);
2358 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2359 // Now store the XMM (fp + vector) parameter registers.
2360 SmallVector<SDValue, 11> SaveXMMOps;
2361 SaveXMMOps.push_back(Chain);
2363 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2364 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2365 SaveXMMOps.push_back(ALVal);
2367 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2368 FuncInfo->getRegSaveFrameIndex()));
2369 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2370 FuncInfo->getVarArgsFPOffset()));
2372 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2373 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2374 &X86::VR128RegClass);
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2376 SaveXMMOps.push_back(Val);
2378 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2380 &SaveXMMOps[0], SaveXMMOps.size()));
2383 if (!MemOps.empty())
2384 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2385 &MemOps[0], MemOps.size());
2389 // Some CCs need callee pop.
2390 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2391 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2392 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2394 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2395 // If this is an sret function, the return should pop the hidden pointer.
2396 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2397 argsAreStructReturn(Ins) == StackStructReturn)
2398 FuncInfo->setBytesToPopOnReturn(4);
2402 // RegSaveFrameIndex is X86-64 only.
2403 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2404 if (CallConv == CallingConv::X86_FastCall ||
2405 CallConv == CallingConv::X86_ThisCall)
2406 // fastcc functions can't have varargs.
2407 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2410 FuncInfo->setArgumentStackSize(StackSize);
2416 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2417 SDValue StackPtr, SDValue Arg,
2418 SDLoc dl, SelectionDAG &DAG,
2419 const CCValAssign &VA,
2420 ISD::ArgFlagsTy Flags) const {
2421 unsigned LocMemOffset = VA.getLocMemOffset();
2422 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2423 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2424 if (Flags.isByVal())
2425 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2427 return DAG.getStore(Chain, dl, Arg, PtrOff,
2428 MachinePointerInfo::getStack(LocMemOffset),
2432 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2433 /// optimization is performed and it is required.
2435 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2436 SDValue &OutRetAddr, SDValue Chain,
2437 bool IsTailCall, bool Is64Bit,
2438 int FPDiff, SDLoc dl) const {
2439 // Adjust the Return address stack slot.
2440 EVT VT = getPointerTy();
2441 OutRetAddr = getReturnAddressFrameIndex(DAG);
2443 // Load the "old" Return address.
2444 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2445 false, false, false, 0);
2446 return SDValue(OutRetAddr.getNode(), 1);
2449 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2450 /// optimization is performed and it is required (FPDiff!=0).
2452 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2453 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2454 unsigned SlotSize, int FPDiff, SDLoc dl) {
2455 // Store the return address to the appropriate stack slot.
2456 if (!FPDiff) return Chain;
2457 // Calculate the new stack slot for the return address.
2458 int NewReturnAddrFI =
2459 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2460 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2461 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2462 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2468 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2469 SmallVectorImpl<SDValue> &InVals) const {
2470 SelectionDAG &DAG = CLI.DAG;
2472 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2473 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2474 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2475 SDValue Chain = CLI.Chain;
2476 SDValue Callee = CLI.Callee;
2477 CallingConv::ID CallConv = CLI.CallConv;
2478 bool &isTailCall = CLI.IsTailCall;
2479 bool isVarArg = CLI.IsVarArg;
2481 MachineFunction &MF = DAG.getMachineFunction();
2482 bool Is64Bit = Subtarget->is64Bit();
2483 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2484 bool IsWindows = Subtarget->isTargetWindows();
2485 StructReturnType SR = callIsStructReturn(Outs);
2486 bool IsSibcall = false;
2488 if (MF.getTarget().Options.DisableTailCalls)
2492 // Check if it's really possible to do a tail call.
2493 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2494 isVarArg, SR != NotStructReturn,
2495 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2496 Outs, OutVals, Ins, DAG);
2498 // Sibcalls are automatically detected tailcalls which do not require
2500 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2507 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2508 "Var args not supported with calling convention fastcc, ghc or hipe");
2510 // Analyze operands of the call, assigning locations to each operand.
2511 SmallVector<CCValAssign, 16> ArgLocs;
2512 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2513 ArgLocs, *DAG.getContext());
2515 // Allocate shadow area for Win64
2517 CCInfo.AllocateStack(32, 8);
2519 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2521 // Get a count of how many bytes are to be pushed on the stack.
2522 unsigned NumBytes = CCInfo.getNextStackOffset();
2524 // This is a sibcall. The memory operands are available in caller's
2525 // own caller's stack.
2527 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2528 IsTailCallConvention(CallConv))
2529 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2532 if (isTailCall && !IsSibcall) {
2533 // Lower arguments at fp - stackoffset + fpdiff.
2534 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2535 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2537 FPDiff = NumBytesCallerPushed - NumBytes;
2539 // Set the delta of movement of the returnaddr stackslot.
2540 // But only set if delta is greater than previous delta.
2541 if (FPDiff < X86Info->getTCReturnAddrDelta())
2542 X86Info->setTCReturnAddrDelta(FPDiff);
2546 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
2549 SDValue RetAddrFrIdx;
2550 // Load return address for tail calls.
2551 if (isTailCall && FPDiff)
2552 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2553 Is64Bit, FPDiff, dl);
2555 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2556 SmallVector<SDValue, 8> MemOpChains;
2559 // Walk the register/memloc assignments, inserting copies/loads. In the case
2560 // of tail call optimization arguments are handle later.
2561 const X86RegisterInfo *RegInfo =
2562 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
2563 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2564 CCValAssign &VA = ArgLocs[i];
2565 EVT RegVT = VA.getLocVT();
2566 SDValue Arg = OutVals[i];
2567 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2568 bool isByVal = Flags.isByVal();
2570 // Promote the value if needed.
2571 switch (VA.getLocInfo()) {
2572 default: llvm_unreachable("Unknown loc info!");
2573 case CCValAssign::Full: break;
2574 case CCValAssign::SExt:
2575 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2577 case CCValAssign::ZExt:
2578 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2580 case CCValAssign::AExt:
2581 if (RegVT.is128BitVector()) {
2582 // Special case: passing MMX values in XMM registers.
2583 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2584 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2585 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2587 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2589 case CCValAssign::BCvt:
2590 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2592 case CCValAssign::Indirect: {
2593 // Store the argument.
2594 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2595 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2596 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2597 MachinePointerInfo::getFixedStack(FI),
2604 if (VA.isRegLoc()) {
2605 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2606 if (isVarArg && IsWin64) {
2607 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2608 // shadow reg if callee is a varargs function.
2609 unsigned ShadowReg = 0;
2610 switch (VA.getLocReg()) {
2611 case X86::XMM0: ShadowReg = X86::RCX; break;
2612 case X86::XMM1: ShadowReg = X86::RDX; break;
2613 case X86::XMM2: ShadowReg = X86::R8; break;
2614 case X86::XMM3: ShadowReg = X86::R9; break;
2617 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2619 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2620 assert(VA.isMemLoc());
2621 if (StackPtr.getNode() == 0)
2622 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2624 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2625 dl, DAG, VA, Flags));
2629 if (!MemOpChains.empty())
2630 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2631 &MemOpChains[0], MemOpChains.size());
2633 if (Subtarget->isPICStyleGOT()) {
2634 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2637 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2638 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2640 // If we are tail calling and generating PIC/GOT style code load the
2641 // address of the callee into ECX. The value in ecx is used as target of
2642 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2643 // for tail calls on PIC/GOT architectures. Normally we would just put the
2644 // address of GOT into ebx and then call target@PLT. But for tail calls
2645 // ebx would be restored (since ebx is callee saved) before jumping to the
2648 // Note: The actual moving to ECX is done further down.
2649 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2650 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2651 !G->getGlobal()->hasProtectedVisibility())
2652 Callee = LowerGlobalAddress(Callee, DAG);
2653 else if (isa<ExternalSymbolSDNode>(Callee))
2654 Callee = LowerExternalSymbol(Callee, DAG);
2658 if (Is64Bit && isVarArg && !IsWin64) {
2659 // From AMD64 ABI document:
2660 // For calls that may call functions that use varargs or stdargs
2661 // (prototype-less calls or calls to functions containing ellipsis (...) in
2662 // the declaration) %al is used as hidden argument to specify the number
2663 // of SSE registers used. The contents of %al do not need to match exactly
2664 // the number of registers, but must be an ubound on the number of SSE
2665 // registers used and is in the range 0 - 8 inclusive.
2667 // Count the number of XMM registers allocated.
2668 static const uint16_t XMMArgRegs[] = {
2669 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2670 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2672 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2673 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2674 && "SSE registers cannot be used when SSE is disabled");
2676 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2677 DAG.getConstant(NumXMMRegs, MVT::i8)));
2680 // For tail calls lower the arguments to the 'real' stack slot.
2682 // Force all the incoming stack arguments to be loaded from the stack
2683 // before any new outgoing arguments are stored to the stack, because the
2684 // outgoing stack slots may alias the incoming argument stack slots, and
2685 // the alias isn't otherwise explicit. This is slightly more conservative
2686 // than necessary, because it means that each store effectively depends
2687 // on every argument instead of just those arguments it would clobber.
2688 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2690 SmallVector<SDValue, 8> MemOpChains2;
2693 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2694 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2695 CCValAssign &VA = ArgLocs[i];
2698 assert(VA.isMemLoc());
2699 SDValue Arg = OutVals[i];
2700 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2701 // Create frame index.
2702 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2703 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2704 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2705 FIN = DAG.getFrameIndex(FI, getPointerTy());
2707 if (Flags.isByVal()) {
2708 // Copy relative to framepointer.
2709 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2710 if (StackPtr.getNode() == 0)
2711 StackPtr = DAG.getCopyFromReg(Chain, dl,
2712 RegInfo->getStackRegister(),
2714 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2716 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2720 // Store relative to framepointer.
2721 MemOpChains2.push_back(
2722 DAG.getStore(ArgChain, dl, Arg, FIN,
2723 MachinePointerInfo::getFixedStack(FI),
2729 if (!MemOpChains2.empty())
2730 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2731 &MemOpChains2[0], MemOpChains2.size());
2733 // Store the return address to the appropriate stack slot.
2734 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2735 getPointerTy(), RegInfo->getSlotSize(),
2739 // Build a sequence of copy-to-reg nodes chained together with token chain
2740 // and flag operands which copy the outgoing args into registers.
2742 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2743 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2744 RegsToPass[i].second, InFlag);
2745 InFlag = Chain.getValue(1);
2748 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2749 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2750 // In the 64-bit large code model, we have to make all calls
2751 // through a register, since the call instruction's 32-bit
2752 // pc-relative offset may not be large enough to hold the whole
2754 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2755 // If the callee is a GlobalAddress node (quite common, every direct call
2756 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2759 // We should use extra load for direct calls to dllimported functions in
2761 const GlobalValue *GV = G->getGlobal();
2762 if (!GV->hasDLLImportLinkage()) {
2763 unsigned char OpFlags = 0;
2764 bool ExtraLoad = false;
2765 unsigned WrapperKind = ISD::DELETED_NODE;
2767 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2768 // external symbols most go through the PLT in PIC mode. If the symbol
2769 // has hidden or protected visibility, or if it is static or local, then
2770 // we don't need to use the PLT - we can directly call it.
2771 if (Subtarget->isTargetELF() &&
2772 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2773 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2774 OpFlags = X86II::MO_PLT;
2775 } else if (Subtarget->isPICStyleStubAny() &&
2776 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2777 (!Subtarget->getTargetTriple().isMacOSX() ||
2778 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2779 // PC-relative references to external symbols should go through $stub,
2780 // unless we're building with the leopard linker or later, which
2781 // automatically synthesizes these stubs.
2782 OpFlags = X86II::MO_DARWIN_STUB;
2783 } else if (Subtarget->isPICStyleRIPRel() &&
2784 isa<Function>(GV) &&
2785 cast<Function>(GV)->getAttributes().
2786 hasAttribute(AttributeSet::FunctionIndex,
2787 Attribute::NonLazyBind)) {
2788 // If the function is marked as non-lazy, generate an indirect call
2789 // which loads from the GOT directly. This avoids runtime overhead
2790 // at the cost of eager binding (and one extra byte of encoding).
2791 OpFlags = X86II::MO_GOTPCREL;
2792 WrapperKind = X86ISD::WrapperRIP;
2796 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2797 G->getOffset(), OpFlags);
2799 // Add a wrapper if needed.
2800 if (WrapperKind != ISD::DELETED_NODE)
2801 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2802 // Add extra indirection if needed.
2804 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2805 MachinePointerInfo::getGOT(),
2806 false, false, false, 0);
2808 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2809 unsigned char OpFlags = 0;
2811 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2812 // external symbols should go through the PLT.
2813 if (Subtarget->isTargetELF() &&
2814 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2815 OpFlags = X86II::MO_PLT;
2816 } else if (Subtarget->isPICStyleStubAny() &&
2817 (!Subtarget->getTargetTriple().isMacOSX() ||
2818 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2819 // PC-relative references to external symbols should go through $stub,
2820 // unless we're building with the leopard linker or later, which
2821 // automatically synthesizes these stubs.
2822 OpFlags = X86II::MO_DARWIN_STUB;
2825 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2829 // Returns a chain & a flag for retval copy to use.
2830 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2831 SmallVector<SDValue, 8> Ops;
2833 if (!IsSibcall && isTailCall) {
2834 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2835 DAG.getIntPtrConstant(0, true), InFlag, dl);
2836 InFlag = Chain.getValue(1);
2839 Ops.push_back(Chain);
2840 Ops.push_back(Callee);
2843 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2845 // Add argument registers to the end of the list so that they are known live
2847 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2848 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2849 RegsToPass[i].second.getValueType()));
2851 // Add a register mask operand representing the call-preserved registers.
2852 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2853 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2854 assert(Mask && "Missing call preserved mask for calling convention");
2855 Ops.push_back(DAG.getRegisterMask(Mask));
2857 if (InFlag.getNode())
2858 Ops.push_back(InFlag);
2862 //// If this is the first return lowered for this function, add the regs
2863 //// to the liveout set for the function.
2864 // This isn't right, although it's probably harmless on x86; liveouts
2865 // should be computed from returns not tail calls. Consider a void
2866 // function making a tail call to a function returning int.
2867 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2870 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2871 InFlag = Chain.getValue(1);
2873 // Create the CALLSEQ_END node.
2874 unsigned NumBytesForCalleeToPush;
2875 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2876 getTargetMachine().Options.GuaranteedTailCallOpt))
2877 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2878 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2879 SR == StackStructReturn)
2880 // If this is a call to a struct-return function, the callee
2881 // pops the hidden struct pointer, so we have to push it back.
2882 // This is common for Darwin/X86, Linux & Mingw32 targets.
2883 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2884 NumBytesForCalleeToPush = 4;
2886 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2888 // Returns a flag for retval copy to use.
2890 Chain = DAG.getCALLSEQ_END(Chain,
2891 DAG.getIntPtrConstant(NumBytes, true),
2892 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2895 InFlag = Chain.getValue(1);
2898 // Handle result values, copying them out of physregs into vregs that we
2900 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2901 Ins, dl, DAG, InVals);
2904 //===----------------------------------------------------------------------===//
2905 // Fast Calling Convention (tail call) implementation
2906 //===----------------------------------------------------------------------===//
2908 // Like std call, callee cleans arguments, convention except that ECX is
2909 // reserved for storing the tail called function address. Only 2 registers are
2910 // free for argument passing (inreg). Tail call optimization is performed
2912 // * tailcallopt is enabled
2913 // * caller/callee are fastcc
2914 // On X86_64 architecture with GOT-style position independent code only local
2915 // (within module) calls are supported at the moment.
2916 // To keep the stack aligned according to platform abi the function
2917 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2918 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2919 // If a tail called function callee has more arguments than the caller the
2920 // caller needs to make sure that there is room to move the RETADDR to. This is
2921 // achieved by reserving an area the size of the argument delta right after the
2922 // original REtADDR, but before the saved framepointer or the spilled registers
2923 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2935 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2936 /// for a 16 byte align requirement.
2938 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2939 SelectionDAG& DAG) const {
2940 MachineFunction &MF = DAG.getMachineFunction();
2941 const TargetMachine &TM = MF.getTarget();
2942 const X86RegisterInfo *RegInfo =
2943 static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
2944 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2945 unsigned StackAlignment = TFI.getStackAlignment();
2946 uint64_t AlignMask = StackAlignment - 1;
2947 int64_t Offset = StackSize;
2948 unsigned SlotSize = RegInfo->getSlotSize();
2949 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2950 // Number smaller than 12 so just add the difference.
2951 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2953 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2954 Offset = ((~AlignMask) & Offset) + StackAlignment +
2955 (StackAlignment-SlotSize);
2960 /// MatchingStackOffset - Return true if the given stack call argument is
2961 /// already available in the same position (relatively) of the caller's
2962 /// incoming argument stack.
2964 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2965 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2966 const X86InstrInfo *TII) {
2967 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2969 if (Arg.getOpcode() == ISD::CopyFromReg) {
2970 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2971 if (!TargetRegisterInfo::isVirtualRegister(VR))
2973 MachineInstr *Def = MRI->getVRegDef(VR);
2976 if (!Flags.isByVal()) {
2977 if (!TII->isLoadFromStackSlot(Def, FI))
2980 unsigned Opcode = Def->getOpcode();
2981 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2982 Def->getOperand(1).isFI()) {
2983 FI = Def->getOperand(1).getIndex();
2984 Bytes = Flags.getByValSize();
2988 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2989 if (Flags.isByVal())
2990 // ByVal argument is passed in as a pointer but it's now being
2991 // dereferenced. e.g.
2992 // define @foo(%struct.X* %A) {
2993 // tail call @bar(%struct.X* byval %A)
2996 SDValue Ptr = Ld->getBasePtr();
2997 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3000 FI = FINode->getIndex();
3001 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3002 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3003 FI = FINode->getIndex();
3004 Bytes = Flags.getByValSize();
3008 assert(FI != INT_MAX);
3009 if (!MFI->isFixedObjectIndex(FI))
3011 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3014 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3015 /// for tail call optimization. Targets which want to do tail call
3016 /// optimization should implement this function.
3018 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3019 CallingConv::ID CalleeCC,
3021 bool isCalleeStructRet,
3022 bool isCallerStructRet,
3024 const SmallVectorImpl<ISD::OutputArg> &Outs,
3025 const SmallVectorImpl<SDValue> &OutVals,
3026 const SmallVectorImpl<ISD::InputArg> &Ins,
3027 SelectionDAG &DAG) const {
3028 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3031 // If -tailcallopt is specified, make fastcc functions tail-callable.
3032 const MachineFunction &MF = DAG.getMachineFunction();
3033 const Function *CallerF = MF.getFunction();
3035 // If the function return type is x86_fp80 and the callee return type is not,
3036 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3037 // perform a tailcall optimization here.
3038 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3041 CallingConv::ID CallerCC = CallerF->getCallingConv();
3042 bool CCMatch = CallerCC == CalleeCC;
3043 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3044 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3046 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
3047 if (IsTailCallConvention(CalleeCC) && CCMatch)
3052 // Look for obvious safe cases to perform tail call optimization that do not
3053 // require ABI changes. This is what gcc calls sibcall.
3055 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3056 // emit a special epilogue.
3057 const X86RegisterInfo *RegInfo =
3058 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3059 if (RegInfo->needsStackRealignment(MF))
3062 // Also avoid sibcall optimization if either caller or callee uses struct
3063 // return semantics.
3064 if (isCalleeStructRet || isCallerStructRet)
3067 // An stdcall caller is expected to clean up its arguments; the callee
3068 // isn't going to do that.
3069 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
3072 // Do not sibcall optimize vararg calls unless all arguments are passed via
3074 if (isVarArg && !Outs.empty()) {
3076 // Optimizing for varargs on Win64 is unlikely to be safe without
3077 // additional testing.
3078 if (IsCalleeWin64 || IsCallerWin64)
3081 SmallVector<CCValAssign, 16> ArgLocs;
3082 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3083 getTargetMachine(), ArgLocs, *DAG.getContext());
3085 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3086 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3087 if (!ArgLocs[i].isRegLoc())
3091 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3092 // stack. Therefore, if it's not used by the call it is not safe to optimize
3093 // this into a sibcall.
3094 bool Unused = false;
3095 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3102 SmallVector<CCValAssign, 16> RVLocs;
3103 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
3104 getTargetMachine(), RVLocs, *DAG.getContext());
3105 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3106 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3107 CCValAssign &VA = RVLocs[i];
3108 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
3113 // If the calling conventions do not match, then we'd better make sure the
3114 // results are returned in the same way as what the caller expects.
3116 SmallVector<CCValAssign, 16> RVLocs1;
3117 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
3118 getTargetMachine(), RVLocs1, *DAG.getContext());
3119 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3121 SmallVector<CCValAssign, 16> RVLocs2;
3122 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
3123 getTargetMachine(), RVLocs2, *DAG.getContext());
3124 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3126 if (RVLocs1.size() != RVLocs2.size())
3128 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3129 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3131 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3133 if (RVLocs1[i].isRegLoc()) {
3134 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3137 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3143 // If the callee takes no arguments then go on to check the results of the
3145 if (!Outs.empty()) {
3146 // Check if stack adjustment is needed. For now, do not do this if any
3147 // argument is passed on the stack.
3148 SmallVector<CCValAssign, 16> ArgLocs;
3149 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
3150 getTargetMachine(), ArgLocs, *DAG.getContext());
3152 // Allocate shadow area for Win64
3154 CCInfo.AllocateStack(32, 8);
3156 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3157 if (CCInfo.getNextStackOffset()) {
3158 MachineFunction &MF = DAG.getMachineFunction();
3159 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3162 // Check if the arguments are already laid out in the right way as
3163 // the caller's fixed stack objects.
3164 MachineFrameInfo *MFI = MF.getFrameInfo();
3165 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3166 const X86InstrInfo *TII =
3167 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
3168 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3169 CCValAssign &VA = ArgLocs[i];
3170 SDValue Arg = OutVals[i];
3171 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3172 if (VA.getLocInfo() == CCValAssign::Indirect)
3174 if (!VA.isRegLoc()) {
3175 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3182 // If the tailcall address may be in a register, then make sure it's
3183 // possible to register allocate for it. In 32-bit, the call address can
3184 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3185 // callee-saved registers are restored. These happen to be the same
3186 // registers used to pass 'inreg' arguments so watch out for those.
3187 if (!Subtarget->is64Bit() &&
3188 ((!isa<GlobalAddressSDNode>(Callee) &&
3189 !isa<ExternalSymbolSDNode>(Callee)) ||
3190 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
3191 unsigned NumInRegs = 0;
3192 // In PIC we need an extra register to formulate the address computation
3194 unsigned MaxInRegs =
3195 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3197 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3198 CCValAssign &VA = ArgLocs[i];
3201 unsigned Reg = VA.getLocReg();
3204 case X86::EAX: case X86::EDX: case X86::ECX:
3205 if (++NumInRegs == MaxInRegs)
3217 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3218 const TargetLibraryInfo *libInfo) const {
3219 return X86::createFastISel(funcInfo, libInfo);
3222 //===----------------------------------------------------------------------===//
3223 // Other Lowering Hooks
3224 //===----------------------------------------------------------------------===//
3226 static bool MayFoldLoad(SDValue Op) {
3227 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3230 static bool MayFoldIntoStore(SDValue Op) {
3231 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3234 static bool isTargetShuffle(unsigned Opcode) {
3236 default: return false;
3237 case X86ISD::PSHUFD:
3238 case X86ISD::PSHUFHW:
3239 case X86ISD::PSHUFLW:
3241 case X86ISD::PALIGNR:
3242 case X86ISD::MOVLHPS:
3243 case X86ISD::MOVLHPD:
3244 case X86ISD::MOVHLPS:
3245 case X86ISD::MOVLPS:
3246 case X86ISD::MOVLPD:
3247 case X86ISD::MOVSHDUP:
3248 case X86ISD::MOVSLDUP:
3249 case X86ISD::MOVDDUP:
3252 case X86ISD::UNPCKL:
3253 case X86ISD::UNPCKH:
3254 case X86ISD::VPERMILP:
3255 case X86ISD::VPERM2X128:
3256 case X86ISD::VPERMI:
3261 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3262 SDValue V1, SelectionDAG &DAG) {
3264 default: llvm_unreachable("Unknown x86 shuffle node");
3265 case X86ISD::MOVSHDUP:
3266 case X86ISD::MOVSLDUP:
3267 case X86ISD::MOVDDUP:
3268 return DAG.getNode(Opc, dl, VT, V1);
3272 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3273 SDValue V1, unsigned TargetMask,
3274 SelectionDAG &DAG) {
3276 default: llvm_unreachable("Unknown x86 shuffle node");
3277 case X86ISD::PSHUFD:
3278 case X86ISD::PSHUFHW:
3279 case X86ISD::PSHUFLW:
3280 case X86ISD::VPERMILP:
3281 case X86ISD::VPERMI:
3282 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3286 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3287 SDValue V1, SDValue V2, unsigned TargetMask,
3288 SelectionDAG &DAG) {
3290 default: llvm_unreachable("Unknown x86 shuffle node");
3291 case X86ISD::PALIGNR:
3293 case X86ISD::VPERM2X128:
3294 return DAG.getNode(Opc, dl, VT, V1, V2,
3295 DAG.getConstant(TargetMask, MVT::i8));
3299 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3300 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3302 default: llvm_unreachable("Unknown x86 shuffle node");
3303 case X86ISD::MOVLHPS:
3304 case X86ISD::MOVLHPD:
3305 case X86ISD::MOVHLPS:
3306 case X86ISD::MOVLPS:
3307 case X86ISD::MOVLPD:
3310 case X86ISD::UNPCKL:
3311 case X86ISD::UNPCKH:
3312 return DAG.getNode(Opc, dl, VT, V1, V2);
3316 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3317 MachineFunction &MF = DAG.getMachineFunction();
3318 const X86RegisterInfo *RegInfo =
3319 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
3320 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3321 int ReturnAddrIndex = FuncInfo->getRAIndex();
3323 if (ReturnAddrIndex == 0) {
3324 // Set up a frame object for the return address.
3325 unsigned SlotSize = RegInfo->getSlotSize();
3326 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3328 FuncInfo->setRAIndex(ReturnAddrIndex);
3331 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3334 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3335 bool hasSymbolicDisplacement) {
3336 // Offset should fit into 32 bit immediate field.
3337 if (!isInt<32>(Offset))
3340 // If we don't have a symbolic displacement - we don't have any extra
3342 if (!hasSymbolicDisplacement)
3345 // FIXME: Some tweaks might be needed for medium code model.
3346 if (M != CodeModel::Small && M != CodeModel::Kernel)
3349 // For small code model we assume that latest object is 16MB before end of 31
3350 // bits boundary. We may also accept pretty large negative constants knowing
3351 // that all objects are in the positive half of address space.
3352 if (M == CodeModel::Small && Offset < 16*1024*1024)
3355 // For kernel code model we know that all object resist in the negative half
3356 // of 32bits address space. We may not accept negative offsets, since they may
3357 // be just off and we may accept pretty large positive ones.
3358 if (M == CodeModel::Kernel && Offset > 0)
3364 /// isCalleePop - Determines whether the callee is required to pop its
3365 /// own arguments. Callee pop is necessary to support tail calls.
3366 bool X86::isCalleePop(CallingConv::ID CallingConv,
3367 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3371 switch (CallingConv) {
3374 case CallingConv::X86_StdCall:
3376 case CallingConv::X86_FastCall:
3378 case CallingConv::X86_ThisCall:
3380 case CallingConv::Fast:
3382 case CallingConv::GHC:
3384 case CallingConv::HiPE:
3389 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3390 /// specific condition code, returning the condition code and the LHS/RHS of the
3391 /// comparison to make.
3392 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3393 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3395 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3396 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3397 // X > -1 -> X == 0, jump !sign.
3398 RHS = DAG.getConstant(0, RHS.getValueType());
3399 return X86::COND_NS;
3401 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3402 // X < 0 -> X == 0, jump on sign.
3405 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3407 RHS = DAG.getConstant(0, RHS.getValueType());
3408 return X86::COND_LE;
3412 switch (SetCCOpcode) {
3413 default: llvm_unreachable("Invalid integer condition!");
3414 case ISD::SETEQ: return X86::COND_E;
3415 case ISD::SETGT: return X86::COND_G;
3416 case ISD::SETGE: return X86::COND_GE;
3417 case ISD::SETLT: return X86::COND_L;
3418 case ISD::SETLE: return X86::COND_LE;
3419 case ISD::SETNE: return X86::COND_NE;
3420 case ISD::SETULT: return X86::COND_B;
3421 case ISD::SETUGT: return X86::COND_A;
3422 case ISD::SETULE: return X86::COND_BE;
3423 case ISD::SETUGE: return X86::COND_AE;
3427 // First determine if it is required or is profitable to flip the operands.
3429 // If LHS is a foldable load, but RHS is not, flip the condition.
3430 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3431 !ISD::isNON_EXTLoad(RHS.getNode())) {
3432 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3433 std::swap(LHS, RHS);
3436 switch (SetCCOpcode) {
3442 std::swap(LHS, RHS);
3446 // On a floating point condition, the flags are set as follows:
3448 // 0 | 0 | 0 | X > Y
3449 // 0 | 0 | 1 | X < Y
3450 // 1 | 0 | 0 | X == Y
3451 // 1 | 1 | 1 | unordered
3452 switch (SetCCOpcode) {
3453 default: llvm_unreachable("Condcode should be pre-legalized away");
3455 case ISD::SETEQ: return X86::COND_E;
3456 case ISD::SETOLT: // flipped
3458 case ISD::SETGT: return X86::COND_A;
3459 case ISD::SETOLE: // flipped
3461 case ISD::SETGE: return X86::COND_AE;
3462 case ISD::SETUGT: // flipped
3464 case ISD::SETLT: return X86::COND_B;
3465 case ISD::SETUGE: // flipped
3467 case ISD::SETLE: return X86::COND_BE;
3469 case ISD::SETNE: return X86::COND_NE;
3470 case ISD::SETUO: return X86::COND_P;
3471 case ISD::SETO: return X86::COND_NP;
3473 case ISD::SETUNE: return X86::COND_INVALID;
3477 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3478 /// code. Current x86 isa includes the following FP cmov instructions:
3479 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3480 static bool hasFPCMov(unsigned X86CC) {
3496 /// isFPImmLegal - Returns true if the target can instruction select the
3497 /// specified FP immediate natively. If false, the legalizer will
3498 /// materialize the FP immediate as a load from a constant pool.
3499 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3500 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3501 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3507 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3508 /// the specified range (L, H].
3509 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3510 return (Val < 0) || (Val >= Low && Val < Hi);
3513 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3514 /// specified value.
3515 static bool isUndefOrEqual(int Val, int CmpVal) {
3516 return (Val < 0 || Val == CmpVal);
3519 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3520 /// from position Pos and ending in Pos+Size, falls within the specified
3521 /// sequential range (L, L+Pos]. or is undef.
3522 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3523 unsigned Pos, unsigned Size, int Low) {
3524 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3525 if (!isUndefOrEqual(Mask[i], Low))
3530 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3531 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3532 /// the second operand.
3533 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3534 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3535 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3536 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3537 return (Mask[0] < 2 && Mask[1] < 2);
3541 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3542 /// is suitable for input to PSHUFHW.
3543 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3544 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3547 // Lower quadword copied in order or undef.
3548 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3551 // Upper quadword shuffled.
3552 for (unsigned i = 4; i != 8; ++i)
3553 if (!isUndefOrInRange(Mask[i], 4, 8))
3556 if (VT == MVT::v16i16) {
3557 // Lower quadword copied in order or undef.
3558 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3561 // Upper quadword shuffled.
3562 for (unsigned i = 12; i != 16; ++i)
3563 if (!isUndefOrInRange(Mask[i], 12, 16))
3570 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3571 /// is suitable for input to PSHUFLW.
3572 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3573 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3576 // Upper quadword copied in order.
3577 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3580 // Lower quadword shuffled.
3581 for (unsigned i = 0; i != 4; ++i)
3582 if (!isUndefOrInRange(Mask[i], 0, 4))
3585 if (VT == MVT::v16i16) {
3586 // Upper quadword copied in order.
3587 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3590 // Lower quadword shuffled.
3591 for (unsigned i = 8; i != 12; ++i)
3592 if (!isUndefOrInRange(Mask[i], 8, 12))
3599 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3600 /// is suitable for input to PALIGNR.
3601 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3602 const X86Subtarget *Subtarget) {
3603 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3604 (VT.is256BitVector() && !Subtarget->hasInt256()))
3607 unsigned NumElts = VT.getVectorNumElements();
3608 unsigned NumLanes = VT.getSizeInBits()/128;
3609 unsigned NumLaneElts = NumElts/NumLanes;
3611 // Do not handle 64-bit element shuffles with palignr.
3612 if (NumLaneElts == 2)
3615 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3617 for (i = 0; i != NumLaneElts; ++i) {
3622 // Lane is all undef, go to next lane
3623 if (i == NumLaneElts)
3626 int Start = Mask[i+l];
3628 // Make sure its in this lane in one of the sources
3629 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3630 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3633 // If not lane 0, then we must match lane 0
3634 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3637 // Correct second source to be contiguous with first source
3638 if (Start >= (int)NumElts)
3639 Start -= NumElts - NumLaneElts;
3641 // Make sure we're shifting in the right direction.
3642 if (Start <= (int)(i+l))
3647 // Check the rest of the elements to see if they are consecutive.
3648 for (++i; i != NumLaneElts; ++i) {
3649 int Idx = Mask[i+l];
3651 // Make sure its in this lane
3652 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3653 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3656 // If not lane 0, then we must match lane 0
3657 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3660 if (Idx >= (int)NumElts)
3661 Idx -= NumElts - NumLaneElts;
3663 if (!isUndefOrEqual(Idx, Start+i))
3672 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3673 /// the two vector operands have swapped position.
3674 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3675 unsigned NumElems) {
3676 for (unsigned i = 0; i != NumElems; ++i) {
3680 else if (idx < (int)NumElems)
3681 Mask[i] = idx + NumElems;
3683 Mask[i] = idx - NumElems;
3687 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3688 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3689 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3690 /// reverse of what x86 shuffles want.
3691 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3692 bool Commuted = false) {
3693 if (!HasFp256 && VT.is256BitVector())
3696 unsigned NumElems = VT.getVectorNumElements();
3697 unsigned NumLanes = VT.getSizeInBits()/128;
3698 unsigned NumLaneElems = NumElems/NumLanes;
3700 if (NumLaneElems != 2 && NumLaneElems != 4)
3703 // VSHUFPSY divides the resulting vector into 4 chunks.
3704 // The sources are also splitted into 4 chunks, and each destination
3705 // chunk must come from a different source chunk.
3707 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3708 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3710 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3711 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3713 // VSHUFPDY divides the resulting vector into 4 chunks.
3714 // The sources are also splitted into 4 chunks, and each destination
3715 // chunk must come from a different source chunk.
3717 // SRC1 => X3 X2 X1 X0
3718 // SRC2 => Y3 Y2 Y1 Y0
3720 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3722 unsigned HalfLaneElems = NumLaneElems/2;
3723 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3724 for (unsigned i = 0; i != NumLaneElems; ++i) {
3725 int Idx = Mask[i+l];
3726 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3727 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3729 // For VSHUFPSY, the mask of the second half must be the same as the
3730 // first but with the appropriate offsets. This works in the same way as
3731 // VPERMILPS works with masks.
3732 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3734 if (!isUndefOrEqual(Idx, Mask[i]+l))
3742 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3743 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3744 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3745 if (!VT.is128BitVector())
3748 unsigned NumElems = VT.getVectorNumElements();
3753 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3754 return isUndefOrEqual(Mask[0], 6) &&
3755 isUndefOrEqual(Mask[1], 7) &&
3756 isUndefOrEqual(Mask[2], 2) &&
3757 isUndefOrEqual(Mask[3], 3);
3760 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3761 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3763 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3764 if (!VT.is128BitVector())
3767 unsigned NumElems = VT.getVectorNumElements();
3772 return isUndefOrEqual(Mask[0], 2) &&
3773 isUndefOrEqual(Mask[1], 3) &&
3774 isUndefOrEqual(Mask[2], 2) &&
3775 isUndefOrEqual(Mask[3], 3);
3778 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3779 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3780 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3781 if (!VT.is128BitVector())
3784 unsigned NumElems = VT.getVectorNumElements();
3786 if (NumElems != 2 && NumElems != 4)
3789 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3790 if (!isUndefOrEqual(Mask[i], i + NumElems))
3793 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3794 if (!isUndefOrEqual(Mask[i], i))
3800 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3801 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3802 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3803 if (!VT.is128BitVector())
3806 unsigned NumElems = VT.getVectorNumElements();
3808 if (NumElems != 2 && NumElems != 4)
3811 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3812 if (!isUndefOrEqual(Mask[i], i))
3815 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3816 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3823 // Some special combinations that can be optimized.
3826 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3827 SelectionDAG &DAG) {
3828 MVT VT = SVOp->getValueType(0).getSimpleVT();
3831 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3834 ArrayRef<int> Mask = SVOp->getMask();
3836 // These are the special masks that may be optimized.
3837 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3838 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3839 bool MatchEvenMask = true;
3840 bool MatchOddMask = true;
3841 for (int i=0; i<8; ++i) {
3842 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3843 MatchEvenMask = false;
3844 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3845 MatchOddMask = false;
3848 if (!MatchEvenMask && !MatchOddMask)
3851 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3853 SDValue Op0 = SVOp->getOperand(0);
3854 SDValue Op1 = SVOp->getOperand(1);
3856 if (MatchEvenMask) {
3857 // Shift the second operand right to 32 bits.
3858 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3859 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3861 // Shift the first operand left to 32 bits.
3862 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3863 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3865 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3866 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3869 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3870 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3871 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3872 bool HasInt256, bool V2IsSplat = false) {
3873 unsigned NumElts = VT.getVectorNumElements();
3875 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3876 "Unsupported vector type for unpckh");
3878 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3879 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3882 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3883 // independently on 128-bit lanes.
3884 unsigned NumLanes = VT.getSizeInBits()/128;
3885 unsigned NumLaneElts = NumElts/NumLanes;
3887 for (unsigned l = 0; l != NumLanes; ++l) {
3888 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3889 i != (l+1)*NumLaneElts;
3892 int BitI1 = Mask[i+1];
3893 if (!isUndefOrEqual(BitI, j))
3896 if (!isUndefOrEqual(BitI1, NumElts))
3899 if (!isUndefOrEqual(BitI1, j + NumElts))
3908 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3909 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3910 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3911 bool HasInt256, bool V2IsSplat = false) {
3912 unsigned NumElts = VT.getVectorNumElements();
3914 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3915 "Unsupported vector type for unpckh");
3917 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3918 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3921 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3922 // independently on 128-bit lanes.
3923 unsigned NumLanes = VT.getSizeInBits()/128;
3924 unsigned NumLaneElts = NumElts/NumLanes;
3926 for (unsigned l = 0; l != NumLanes; ++l) {
3927 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3928 i != (l+1)*NumLaneElts; i += 2, ++j) {
3930 int BitI1 = Mask[i+1];
3931 if (!isUndefOrEqual(BitI, j))
3934 if (isUndefOrEqual(BitI1, NumElts))
3937 if (!isUndefOrEqual(BitI1, j+NumElts))
3945 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3946 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3948 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3949 unsigned NumElts = VT.getVectorNumElements();
3950 bool Is256BitVec = VT.is256BitVector();
3952 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3953 "Unsupported vector type for unpckh");
3955 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3956 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3959 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3960 // FIXME: Need a better way to get rid of this, there's no latency difference
3961 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3962 // the former later. We should also remove the "_undef" special mask.
3963 if (NumElts == 4 && Is256BitVec)
3966 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3967 // independently on 128-bit lanes.
3968 unsigned NumLanes = VT.getSizeInBits()/128;
3969 unsigned NumLaneElts = NumElts/NumLanes;
3971 for (unsigned l = 0; l != NumLanes; ++l) {
3972 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3973 i != (l+1)*NumLaneElts;
3976 int BitI1 = Mask[i+1];
3978 if (!isUndefOrEqual(BitI, j))
3980 if (!isUndefOrEqual(BitI1, j))
3988 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3989 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3991 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3992 unsigned NumElts = VT.getVectorNumElements();
3994 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3995 "Unsupported vector type for unpckh");
3997 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3998 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4001 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4002 // independently on 128-bit lanes.
4003 unsigned NumLanes = VT.getSizeInBits()/128;
4004 unsigned NumLaneElts = NumElts/NumLanes;
4006 for (unsigned l = 0; l != NumLanes; ++l) {
4007 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
4008 i != (l+1)*NumLaneElts; i += 2, ++j) {
4010 int BitI1 = Mask[i+1];
4011 if (!isUndefOrEqual(BitI, j))
4013 if (!isUndefOrEqual(BitI1, j))
4020 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4021 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4022 /// MOVSD, and MOVD, i.e. setting the lowest element.
4023 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4024 if (VT.getVectorElementType().getSizeInBits() < 32)
4026 if (!VT.is128BitVector())
4029 unsigned NumElts = VT.getVectorNumElements();
4031 if (!isUndefOrEqual(Mask[0], NumElts))
4034 for (unsigned i = 1; i != NumElts; ++i)
4035 if (!isUndefOrEqual(Mask[i], i))
4041 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4042 /// as permutations between 128-bit chunks or halves. As an example: this
4044 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4045 /// The first half comes from the second half of V1 and the second half from the
4046 /// the second half of V2.
4047 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
4048 if (!HasFp256 || !VT.is256BitVector())
4051 // The shuffle result is divided into half A and half B. In total the two
4052 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4053 // B must come from C, D, E or F.
4054 unsigned HalfSize = VT.getVectorNumElements()/2;
4055 bool MatchA = false, MatchB = false;
4057 // Check if A comes from one of C, D, E, F.
4058 for (unsigned Half = 0; Half != 4; ++Half) {
4059 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4065 // Check if B comes from one of C, D, E, F.
4066 for (unsigned Half = 0; Half != 4; ++Half) {
4067 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4073 return MatchA && MatchB;
4076 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4077 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4078 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4079 MVT VT = SVOp->getValueType(0).getSimpleVT();
4081 unsigned HalfSize = VT.getVectorNumElements()/2;
4083 unsigned FstHalf = 0, SndHalf = 0;
4084 for (unsigned i = 0; i < HalfSize; ++i) {
4085 if (SVOp->getMaskElt(i) > 0) {
4086 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4090 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4091 if (SVOp->getMaskElt(i) > 0) {
4092 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4097 return (FstHalf | (SndHalf << 4));
4100 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4101 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4102 /// Note that VPERMIL mask matching is different depending whether theunderlying
4103 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4104 /// to the same elements of the low, but to the higher half of the source.
4105 /// In VPERMILPD the two lanes could be shuffled independently of each other
4106 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4107 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
4111 unsigned NumElts = VT.getVectorNumElements();
4112 // Only match 256-bit with 32/64-bit types
4113 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
4116 unsigned NumLanes = VT.getSizeInBits()/128;
4117 unsigned LaneSize = NumElts/NumLanes;
4118 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4119 for (unsigned i = 0; i != LaneSize; ++i) {
4120 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4122 if (NumElts != 8 || l == 0)
4124 // VPERMILPS handling
4127 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
4135 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4136 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4137 /// element of vector 2 and the other elements to come from vector 1 in order.
4138 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
4139 bool V2IsSplat = false, bool V2IsUndef = false) {
4140 if (!VT.is128BitVector())
4143 unsigned NumOps = VT.getVectorNumElements();
4144 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4147 if (!isUndefOrEqual(Mask[0], 0))
4150 for (unsigned i = 1; i != NumOps; ++i)
4151 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4152 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4153 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4159 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4160 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4161 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4162 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
4163 const X86Subtarget *Subtarget) {
4164 if (!Subtarget->hasSSE3())
4167 unsigned NumElems = VT.getVectorNumElements();
4169 if ((VT.is128BitVector() && NumElems != 4) ||
4170 (VT.is256BitVector() && NumElems != 8))
4173 // "i+1" is the value the indexed mask element must have
4174 for (unsigned i = 0; i != NumElems; i += 2)
4175 if (!isUndefOrEqual(Mask[i], i+1) ||
4176 !isUndefOrEqual(Mask[i+1], i+1))
4182 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4183 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4184 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4185 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
4186 const X86Subtarget *Subtarget) {
4187 if (!Subtarget->hasSSE3())
4190 unsigned NumElems = VT.getVectorNumElements();
4192 if ((VT.is128BitVector() && NumElems != 4) ||
4193 (VT.is256BitVector() && NumElems != 8))
4196 // "i" is the value the indexed mask element must have
4197 for (unsigned i = 0; i != NumElems; i += 2)
4198 if (!isUndefOrEqual(Mask[i], i) ||
4199 !isUndefOrEqual(Mask[i+1], i))
4205 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4206 /// specifies a shuffle of elements that is suitable for input to 256-bit
4207 /// version of MOVDDUP.
4208 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
4209 if (!HasFp256 || !VT.is256BitVector())
4212 unsigned NumElts = VT.getVectorNumElements();
4216 for (unsigned i = 0; i != NumElts/2; ++i)
4217 if (!isUndefOrEqual(Mask[i], 0))
4219 for (unsigned i = NumElts/2; i != NumElts; ++i)
4220 if (!isUndefOrEqual(Mask[i], NumElts/2))
4225 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4226 /// specifies a shuffle of elements that is suitable for input to 128-bit
4227 /// version of MOVDDUP.
4228 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
4229 if (!VT.is128BitVector())
4232 unsigned e = VT.getVectorNumElements() / 2;
4233 for (unsigned i = 0; i != e; ++i)
4234 if (!isUndefOrEqual(Mask[i], i))
4236 for (unsigned i = 0; i != e; ++i)
4237 if (!isUndefOrEqual(Mask[e+i], i))
4242 /// isVEXTRACTIndex - Return true if the specified
4243 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4244 /// suitable for instruction that extract 128 or 256 bit vectors
4245 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4246 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4247 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4250 // The index should be aligned on a vecWidth-bit boundary.
4252 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4254 MVT VT = N->getValueType(0).getSimpleVT();
4255 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4256 bool Result = (Index * ElSize) % vecWidth == 0;
4261 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4262 /// operand specifies a subvector insert that is suitable for input to
4263 /// insertion of 128 or 256-bit subvectors
4264 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4265 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4266 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4268 // The index should be aligned on a vecWidth-bit boundary.
4270 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4272 MVT VT = N->getValueType(0).getSimpleVT();
4273 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4274 bool Result = (Index * ElSize) % vecWidth == 0;
4279 bool X86::isVINSERT128Index(SDNode *N) {
4280 return isVINSERTIndex(N, 128);
4283 bool X86::isVINSERT256Index(SDNode *N) {
4284 return isVINSERTIndex(N, 256);
4287 bool X86::isVEXTRACT128Index(SDNode *N) {
4288 return isVEXTRACTIndex(N, 128);
4291 bool X86::isVEXTRACT256Index(SDNode *N) {
4292 return isVEXTRACTIndex(N, 256);
4295 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4296 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4297 /// Handles 128-bit and 256-bit.
4298 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4299 MVT VT = N->getValueType(0).getSimpleVT();
4301 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4302 "Unsupported vector type for PSHUF/SHUFP");
4304 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4305 // independently on 128-bit lanes.
4306 unsigned NumElts = VT.getVectorNumElements();
4307 unsigned NumLanes = VT.getSizeInBits()/128;
4308 unsigned NumLaneElts = NumElts/NumLanes;
4310 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4311 "Only supports 2 or 4 elements per lane");
4313 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4315 for (unsigned i = 0; i != NumElts; ++i) {
4316 int Elt = N->getMaskElt(i);
4317 if (Elt < 0) continue;
4318 Elt &= NumLaneElts - 1;
4319 unsigned ShAmt = (i << Shift) % 8;
4320 Mask |= Elt << ShAmt;
4326 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4327 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4328 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4329 MVT VT = N->getValueType(0).getSimpleVT();
4331 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4332 "Unsupported vector type for PSHUFHW");
4334 unsigned NumElts = VT.getVectorNumElements();
4337 for (unsigned l = 0; l != NumElts; l += 8) {
4338 // 8 nodes per lane, but we only care about the last 4.
4339 for (unsigned i = 0; i < 4; ++i) {
4340 int Elt = N->getMaskElt(l+i+4);
4341 if (Elt < 0) continue;
4342 Elt &= 0x3; // only 2-bits.
4343 Mask |= Elt << (i * 2);
4350 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4351 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4352 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4353 MVT VT = N->getValueType(0).getSimpleVT();
4355 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4356 "Unsupported vector type for PSHUFHW");
4358 unsigned NumElts = VT.getVectorNumElements();
4361 for (unsigned l = 0; l != NumElts; l += 8) {
4362 // 8 nodes per lane, but we only care about the first 4.
4363 for (unsigned i = 0; i < 4; ++i) {
4364 int Elt = N->getMaskElt(l+i);
4365 if (Elt < 0) continue;
4366 Elt &= 0x3; // only 2-bits
4367 Mask |= Elt << (i * 2);
4374 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4375 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4376 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4377 MVT VT = SVOp->getValueType(0).getSimpleVT();
4378 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4380 unsigned NumElts = VT.getVectorNumElements();
4381 unsigned NumLanes = VT.getSizeInBits()/128;
4382 unsigned NumLaneElts = NumElts/NumLanes;
4386 for (i = 0; i != NumElts; ++i) {
4387 Val = SVOp->getMaskElt(i);
4391 if (Val >= (int)NumElts)
4392 Val -= NumElts - NumLaneElts;
4394 assert(Val - i > 0 && "PALIGNR imm should be positive");
4395 return (Val - i) * EltSize;
4398 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4399 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4400 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4401 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4404 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4406 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT();
4407 MVT ElVT = VecVT.getVectorElementType();
4409 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4410 return Index / NumElemsPerChunk;
4413 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4414 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4415 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4416 llvm_unreachable("Illegal insert subvector for VINSERT");
4419 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4421 MVT VecVT = N->getValueType(0).getSimpleVT();
4422 MVT ElVT = VecVT.getVectorElementType();
4424 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4425 return Index / NumElemsPerChunk;
4428 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4429 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4430 /// and VINSERTI128 instructions.
4431 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4432 return getExtractVEXTRACTImmediate(N, 128);
4435 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4436 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4437 /// and VINSERTI64x4 instructions.
4438 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4439 return getExtractVEXTRACTImmediate(N, 256);
4442 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4443 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4444 /// and VINSERTI128 instructions.
4445 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4446 return getInsertVINSERTImmediate(N, 128);
4449 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4450 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4451 /// and VINSERTI64x4 instructions.
4452 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4453 return getInsertVINSERTImmediate(N, 256);
4456 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4457 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4458 /// Handles 256-bit.
4459 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4460 MVT VT = N->getValueType(0).getSimpleVT();
4462 unsigned NumElts = VT.getVectorNumElements();
4464 assert((VT.is256BitVector() && NumElts == 4) &&
4465 "Unsupported vector type for VPERMQ/VPERMPD");
4468 for (unsigned i = 0; i != NumElts; ++i) {
4469 int Elt = N->getMaskElt(i);
4472 Mask |= Elt << (i*2);
4477 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4479 bool X86::isZeroNode(SDValue Elt) {
4480 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4481 return CN->isNullValue();
4482 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4483 return CFP->getValueAPF().isPosZero();
4487 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4488 /// their permute mask.
4489 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4490 SelectionDAG &DAG) {
4491 MVT VT = SVOp->getValueType(0).getSimpleVT();
4492 unsigned NumElems = VT.getVectorNumElements();
4493 SmallVector<int, 8> MaskVec;
4495 for (unsigned i = 0; i != NumElems; ++i) {
4496 int Idx = SVOp->getMaskElt(i);
4498 if (Idx < (int)NumElems)
4503 MaskVec.push_back(Idx);
4505 return DAG.getVectorShuffle(VT, SDLoc(SVOp), SVOp->getOperand(1),
4506 SVOp->getOperand(0), &MaskVec[0]);
4509 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4510 /// match movhlps. The lower half elements should come from upper half of
4511 /// V1 (and in order), and the upper half elements should come from the upper
4512 /// half of V2 (and in order).
4513 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4514 if (!VT.is128BitVector())
4516 if (VT.getVectorNumElements() != 4)
4518 for (unsigned i = 0, e = 2; i != e; ++i)
4519 if (!isUndefOrEqual(Mask[i], i+2))
4521 for (unsigned i = 2; i != 4; ++i)
4522 if (!isUndefOrEqual(Mask[i], i+4))
4527 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4528 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4530 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4531 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4533 N = N->getOperand(0).getNode();
4534 if (!ISD::isNON_EXTLoad(N))
4537 *LD = cast<LoadSDNode>(N);
4541 // Test whether the given value is a vector value which will be legalized
4543 static bool WillBeConstantPoolLoad(SDNode *N) {
4544 if (N->getOpcode() != ISD::BUILD_VECTOR)
4547 // Check for any non-constant elements.
4548 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4549 switch (N->getOperand(i).getNode()->getOpcode()) {
4551 case ISD::ConstantFP:
4558 // Vectors of all-zeros and all-ones are materialized with special
4559 // instructions rather than being loaded.
4560 return !ISD::isBuildVectorAllZeros(N) &&
4561 !ISD::isBuildVectorAllOnes(N);
4564 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4565 /// match movlp{s|d}. The lower half elements should come from lower half of
4566 /// V1 (and in order), and the upper half elements should come from the upper
4567 /// half of V2 (and in order). And since V1 will become the source of the
4568 /// MOVLP, it must be either a vector load or a scalar load to vector.
4569 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4570 ArrayRef<int> Mask, EVT VT) {
4571 if (!VT.is128BitVector())
4574 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4576 // Is V2 is a vector load, don't do this transformation. We will try to use
4577 // load folding shufps op.
4578 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4581 unsigned NumElems = VT.getVectorNumElements();
4583 if (NumElems != 2 && NumElems != 4)
4585 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4586 if (!isUndefOrEqual(Mask[i], i))
4588 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4589 if (!isUndefOrEqual(Mask[i], i+NumElems))
4594 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4596 static bool isSplatVector(SDNode *N) {
4597 if (N->getOpcode() != ISD::BUILD_VECTOR)
4600 SDValue SplatValue = N->getOperand(0);
4601 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4602 if (N->getOperand(i) != SplatValue)
4607 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4608 /// to an zero vector.
4609 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4610 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4611 SDValue V1 = N->getOperand(0);
4612 SDValue V2 = N->getOperand(1);
4613 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4614 for (unsigned i = 0; i != NumElems; ++i) {
4615 int Idx = N->getMaskElt(i);
4616 if (Idx >= (int)NumElems) {
4617 unsigned Opc = V2.getOpcode();
4618 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4620 if (Opc != ISD::BUILD_VECTOR ||
4621 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4623 } else if (Idx >= 0) {
4624 unsigned Opc = V1.getOpcode();
4625 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4627 if (Opc != ISD::BUILD_VECTOR ||
4628 !X86::isZeroNode(V1.getOperand(Idx)))
4635 /// getZeroVector - Returns a vector of specified type with all zero elements.
4637 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4638 SelectionDAG &DAG, SDLoc dl) {
4639 assert(VT.isVector() && "Expected a vector type");
4641 // Always build SSE zero vectors as <4 x i32> bitcasted
4642 // to their dest type. This ensures they get CSE'd.
4644 if (VT.is128BitVector()) { // SSE
4645 if (Subtarget->hasSSE2()) { // SSE2
4646 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4647 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4649 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4650 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4652 } else if (VT.is256BitVector()) { // AVX
4653 if (Subtarget->hasInt256()) { // AVX2
4654 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4655 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4656 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4657 array_lengthof(Ops));
4659 // 256-bit logic and arithmetic instructions in AVX are all
4660 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4661 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4662 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4663 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4664 array_lengthof(Ops));
4667 llvm_unreachable("Unexpected vector type");
4669 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4672 /// getOnesVector - Returns a vector of specified type with all bits set.
4673 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4674 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4675 /// Then bitcast to their original type, ensuring they get CSE'd.
4676 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4678 assert(VT.isVector() && "Expected a vector type");
4680 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4682 if (VT.is256BitVector()) {
4683 if (HasInt256) { // AVX2
4684 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4685 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4686 array_lengthof(Ops));
4688 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4689 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4691 } else if (VT.is128BitVector()) {
4692 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4694 llvm_unreachable("Unexpected vector type");
4696 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4699 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4700 /// that point to V2 points to its first element.
4701 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4702 for (unsigned i = 0; i != NumElems; ++i) {
4703 if (Mask[i] > (int)NumElems) {
4709 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4710 /// operation of specified width.
4711 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4713 unsigned NumElems = VT.getVectorNumElements();
4714 SmallVector<int, 8> Mask;
4715 Mask.push_back(NumElems);
4716 for (unsigned i = 1; i != NumElems; ++i)
4718 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4721 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4722 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4724 unsigned NumElems = VT.getVectorNumElements();
4725 SmallVector<int, 8> Mask;
4726 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4728 Mask.push_back(i + NumElems);
4730 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4733 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4734 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4736 unsigned NumElems = VT.getVectorNumElements();
4737 SmallVector<int, 8> Mask;
4738 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4739 Mask.push_back(i + Half);
4740 Mask.push_back(i + NumElems + Half);
4742 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4745 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4746 // a generic shuffle instruction because the target has no such instructions.
4747 // Generate shuffles which repeat i16 and i8 several times until they can be
4748 // represented by v4f32 and then be manipulated by target suported shuffles.
4749 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4750 EVT VT = V.getValueType();
4751 int NumElems = VT.getVectorNumElements();
4754 while (NumElems > 4) {
4755 if (EltNo < NumElems/2) {
4756 V = getUnpackl(DAG, dl, VT, V, V);
4758 V = getUnpackh(DAG, dl, VT, V, V);
4759 EltNo -= NumElems/2;
4766 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4767 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4768 EVT VT = V.getValueType();
4771 if (VT.is128BitVector()) {
4772 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4773 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4774 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4776 } else if (VT.is256BitVector()) {
4777 // To use VPERMILPS to splat scalars, the second half of indicies must
4778 // refer to the higher part, which is a duplication of the lower one,
4779 // because VPERMILPS can only handle in-lane permutations.
4780 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4781 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4783 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4784 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4787 llvm_unreachable("Vector size not supported");
4789 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4792 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4793 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4794 EVT SrcVT = SV->getValueType(0);
4795 SDValue V1 = SV->getOperand(0);
4798 int EltNo = SV->getSplatIndex();
4799 int NumElems = SrcVT.getVectorNumElements();
4800 bool Is256BitVec = SrcVT.is256BitVector();
4802 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4803 "Unknown how to promote splat for type");
4805 // Extract the 128-bit part containing the splat element and update
4806 // the splat element index when it refers to the higher register.
4808 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4809 if (EltNo >= NumElems/2)
4810 EltNo -= NumElems/2;
4813 // All i16 and i8 vector types can't be used directly by a generic shuffle
4814 // instruction because the target has no such instruction. Generate shuffles
4815 // which repeat i16 and i8 several times until they fit in i32, and then can
4816 // be manipulated by target suported shuffles.
4817 EVT EltVT = SrcVT.getVectorElementType();
4818 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4819 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4821 // Recreate the 256-bit vector and place the same 128-bit vector
4822 // into the low and high part. This is necessary because we want
4823 // to use VPERM* to shuffle the vectors
4825 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4828 return getLegalSplat(DAG, V1, EltNo);
4831 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4832 /// vector of zero or undef vector. This produces a shuffle where the low
4833 /// element of V2 is swizzled into the zero/undef vector, landing at element
4834 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4835 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4837 const X86Subtarget *Subtarget,
4838 SelectionDAG &DAG) {
4839 EVT VT = V2.getValueType();
4841 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4842 unsigned NumElems = VT.getVectorNumElements();
4843 SmallVector<int, 16> MaskVec;
4844 for (unsigned i = 0; i != NumElems; ++i)
4845 // If this is the insertion idx, put the low elt of V2 here.
4846 MaskVec.push_back(i == Idx ? NumElems : i);
4847 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4850 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4851 /// target specific opcode. Returns true if the Mask could be calculated.
4852 /// Sets IsUnary to true if only uses one source.
4853 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4854 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4855 unsigned NumElems = VT.getVectorNumElements();
4859 switch(N->getOpcode()) {
4861 ImmN = N->getOperand(N->getNumOperands()-1);
4862 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4864 case X86ISD::UNPCKH:
4865 DecodeUNPCKHMask(VT, Mask);
4867 case X86ISD::UNPCKL:
4868 DecodeUNPCKLMask(VT, Mask);
4870 case X86ISD::MOVHLPS:
4871 DecodeMOVHLPSMask(NumElems, Mask);
4873 case X86ISD::MOVLHPS:
4874 DecodeMOVLHPSMask(NumElems, Mask);
4876 case X86ISD::PALIGNR:
4877 ImmN = N->getOperand(N->getNumOperands()-1);
4878 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4880 case X86ISD::PSHUFD:
4881 case X86ISD::VPERMILP:
4882 ImmN = N->getOperand(N->getNumOperands()-1);
4883 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4886 case X86ISD::PSHUFHW:
4887 ImmN = N->getOperand(N->getNumOperands()-1);
4888 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4891 case X86ISD::PSHUFLW:
4892 ImmN = N->getOperand(N->getNumOperands()-1);
4893 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4896 case X86ISD::VPERMI:
4897 ImmN = N->getOperand(N->getNumOperands()-1);
4898 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4902 case X86ISD::MOVSD: {
4903 // The index 0 always comes from the first element of the second source,
4904 // this is why MOVSS and MOVSD are used in the first place. The other
4905 // elements come from the other positions of the first source vector
4906 Mask.push_back(NumElems);
4907 for (unsigned i = 1; i != NumElems; ++i) {
4912 case X86ISD::VPERM2X128:
4913 ImmN = N->getOperand(N->getNumOperands()-1);
4914 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4915 if (Mask.empty()) return false;
4917 case X86ISD::MOVDDUP:
4918 case X86ISD::MOVLHPD:
4919 case X86ISD::MOVLPD:
4920 case X86ISD::MOVLPS:
4921 case X86ISD::MOVSHDUP:
4922 case X86ISD::MOVSLDUP:
4923 // Not yet implemented
4925 default: llvm_unreachable("unknown target shuffle node");
4931 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4932 /// element of the result of the vector shuffle.
4933 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4936 return SDValue(); // Limit search depth.
4938 SDValue V = SDValue(N, 0);
4939 EVT VT = V.getValueType();
4940 unsigned Opcode = V.getOpcode();
4942 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4943 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4944 int Elt = SV->getMaskElt(Index);
4947 return DAG.getUNDEF(VT.getVectorElementType());
4949 unsigned NumElems = VT.getVectorNumElements();
4950 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4951 : SV->getOperand(1);
4952 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4955 // Recurse into target specific vector shuffles to find scalars.
4956 if (isTargetShuffle(Opcode)) {
4957 MVT ShufVT = V.getValueType().getSimpleVT();
4958 unsigned NumElems = ShufVT.getVectorNumElements();
4959 SmallVector<int, 16> ShuffleMask;
4962 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4965 int Elt = ShuffleMask[Index];
4967 return DAG.getUNDEF(ShufVT.getVectorElementType());
4969 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4971 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4975 // Actual nodes that may contain scalar elements
4976 if (Opcode == ISD::BITCAST) {
4977 V = V.getOperand(0);
4978 EVT SrcVT = V.getValueType();
4979 unsigned NumElems = VT.getVectorNumElements();
4981 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4985 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4986 return (Index == 0) ? V.getOperand(0)
4987 : DAG.getUNDEF(VT.getVectorElementType());
4989 if (V.getOpcode() == ISD::BUILD_VECTOR)
4990 return V.getOperand(Index);
4995 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4996 /// shuffle operation which come from a consecutively from a zero. The
4997 /// search can start in two different directions, from left or right.
4998 /// We count undefs as zeros until PreferredNum is reached.
4999 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5000 unsigned NumElems, bool ZerosFromLeft,
5002 unsigned PreferredNum = -1U) {
5003 unsigned NumZeros = 0;
5004 for (unsigned i = 0; i != NumElems; ++i) {
5005 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5006 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5010 if (X86::isZeroNode(Elt))
5012 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5013 NumZeros = std::min(NumZeros + 1, PreferredNum);
5021 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5022 /// correspond consecutively to elements from one of the vector operands,
5023 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5025 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5026 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5027 unsigned NumElems, unsigned &OpNum) {
5028 bool SeenV1 = false;
5029 bool SeenV2 = false;
5031 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5032 int Idx = SVOp->getMaskElt(i);
5033 // Ignore undef indicies
5037 if (Idx < (int)NumElems)
5042 // Only accept consecutive elements from the same vector
5043 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5047 OpNum = SeenV1 ? 0 : 1;
5051 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5052 /// logical left shift of a vector.
5053 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5054 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5055 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
5056 unsigned NumZeros = getNumOfConsecutiveZeros(
5057 SVOp, NumElems, false /* check zeros from right */, DAG,
5058 SVOp->getMaskElt(0));
5064 // Considering the elements in the mask that are not consecutive zeros,
5065 // check if they consecutively come from only one of the source vectors.
5067 // V1 = {X, A, B, C} 0
5069 // vector_shuffle V1, V2 <1, 2, 3, X>
5071 if (!isShuffleMaskConsecutive(SVOp,
5072 0, // Mask Start Index
5073 NumElems-NumZeros, // Mask End Index(exclusive)
5074 NumZeros, // Where to start looking in the src vector
5075 NumElems, // Number of elements in vector
5076 OpSrc)) // Which source operand ?
5081 ShVal = SVOp->getOperand(OpSrc);
5085 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5086 /// logical left shift of a vector.
5087 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5088 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5089 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
5090 unsigned NumZeros = getNumOfConsecutiveZeros(
5091 SVOp, NumElems, true /* check zeros from left */, DAG,
5092 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5098 // Considering the elements in the mask that are not consecutive zeros,
5099 // check if they consecutively come from only one of the source vectors.
5101 // 0 { A, B, X, X } = V2
5103 // vector_shuffle V1, V2 <X, X, 4, 5>
5105 if (!isShuffleMaskConsecutive(SVOp,
5106 NumZeros, // Mask Start Index
5107 NumElems, // Mask End Index(exclusive)
5108 0, // Where to start looking in the src vector
5109 NumElems, // Number of elements in vector
5110 OpSrc)) // Which source operand ?
5115 ShVal = SVOp->getOperand(OpSrc);
5119 /// isVectorShift - Returns true if the shuffle can be implemented as a
5120 /// logical left or right shift of a vector.
5121 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5122 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5123 // Although the logic below support any bitwidth size, there are no
5124 // shift instructions which handle more than 128-bit vectors.
5125 if (!SVOp->getValueType(0).is128BitVector())
5128 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5129 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5135 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5137 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5138 unsigned NumNonZero, unsigned NumZero,
5140 const X86Subtarget* Subtarget,
5141 const TargetLowering &TLI) {
5148 for (unsigned i = 0; i < 16; ++i) {
5149 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5150 if (ThisIsNonZero && First) {
5152 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5154 V = DAG.getUNDEF(MVT::v8i16);
5159 SDValue ThisElt(0, 0), LastElt(0, 0);
5160 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5161 if (LastIsNonZero) {
5162 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5163 MVT::i16, Op.getOperand(i-1));
5165 if (ThisIsNonZero) {
5166 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5167 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5168 ThisElt, DAG.getConstant(8, MVT::i8));
5170 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5174 if (ThisElt.getNode())
5175 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5176 DAG.getIntPtrConstant(i/2));
5180 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5183 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5185 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5186 unsigned NumNonZero, unsigned NumZero,
5188 const X86Subtarget* Subtarget,
5189 const TargetLowering &TLI) {
5196 for (unsigned i = 0; i < 8; ++i) {
5197 bool isNonZero = (NonZeros & (1 << i)) != 0;
5201 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5203 V = DAG.getUNDEF(MVT::v8i16);
5206 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5207 MVT::v8i16, V, Op.getOperand(i),
5208 DAG.getIntPtrConstant(i));
5215 /// getVShift - Return a vector logical shift node.
5217 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5218 unsigned NumBits, SelectionDAG &DAG,
5219 const TargetLowering &TLI, SDLoc dl) {
5220 assert(VT.is128BitVector() && "Unknown type for VShift");
5221 EVT ShVT = MVT::v2i64;
5222 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5223 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5224 return DAG.getNode(ISD::BITCAST, dl, VT,
5225 DAG.getNode(Opc, dl, ShVT, SrcOp,
5226 DAG.getConstant(NumBits,
5227 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5231 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, SDLoc dl,
5232 SelectionDAG &DAG) const {
5234 // Check if the scalar load can be widened into a vector load. And if
5235 // the address is "base + cst" see if the cst can be "absorbed" into
5236 // the shuffle mask.
5237 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5238 SDValue Ptr = LD->getBasePtr();
5239 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5241 EVT PVT = LD->getValueType(0);
5242 if (PVT != MVT::i32 && PVT != MVT::f32)
5247 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5248 FI = FINode->getIndex();
5250 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5251 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5252 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5253 Offset = Ptr.getConstantOperandVal(1);
5254 Ptr = Ptr.getOperand(0);
5259 // FIXME: 256-bit vector instructions don't require a strict alignment,
5260 // improve this code to support it better.
5261 unsigned RequiredAlign = VT.getSizeInBits()/8;
5262 SDValue Chain = LD->getChain();
5263 // Make sure the stack object alignment is at least 16 or 32.
5264 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5265 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5266 if (MFI->isFixedObjectIndex(FI)) {
5267 // Can't change the alignment. FIXME: It's possible to compute
5268 // the exact stack offset and reference FI + adjust offset instead.
5269 // If someone *really* cares about this. That's the way to implement it.
5272 MFI->setObjectAlignment(FI, RequiredAlign);
5276 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5277 // Ptr + (Offset & ~15).
5280 if ((Offset % RequiredAlign) & 3)
5282 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5284 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5285 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5287 int EltNo = (Offset - StartOffset) >> 2;
5288 unsigned NumElems = VT.getVectorNumElements();
5290 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5291 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5292 LD->getPointerInfo().getWithOffset(StartOffset),
5293 false, false, false, 0);
5295 SmallVector<int, 8> Mask;
5296 for (unsigned i = 0; i != NumElems; ++i)
5297 Mask.push_back(EltNo);
5299 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5305 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5306 /// vector of type 'VT', see if the elements can be replaced by a single large
5307 /// load which has the same value as a build_vector whose operands are 'elts'.
5309 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5311 /// FIXME: we'd also like to handle the case where the last elements are zero
5312 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5313 /// There's even a handy isZeroNode for that purpose.
5314 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5315 SDLoc &DL, SelectionDAG &DAG) {
5316 EVT EltVT = VT.getVectorElementType();
5317 unsigned NumElems = Elts.size();
5319 LoadSDNode *LDBase = NULL;
5320 unsigned LastLoadedElt = -1U;
5322 // For each element in the initializer, see if we've found a load or an undef.
5323 // If we don't find an initial load element, or later load elements are
5324 // non-consecutive, bail out.
5325 for (unsigned i = 0; i < NumElems; ++i) {
5326 SDValue Elt = Elts[i];
5328 if (!Elt.getNode() ||
5329 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5332 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5334 LDBase = cast<LoadSDNode>(Elt.getNode());
5338 if (Elt.getOpcode() == ISD::UNDEF)
5341 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5342 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5347 // If we have found an entire vector of loads and undefs, then return a large
5348 // load of the entire vector width starting at the base pointer. If we found
5349 // consecutive loads for the low half, generate a vzext_load node.
5350 if (LastLoadedElt == NumElems - 1) {
5351 SDValue NewLd = SDValue();
5352 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5353 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5354 LDBase->getPointerInfo(),
5355 LDBase->isVolatile(), LDBase->isNonTemporal(),
5356 LDBase->isInvariant(), 0);
5357 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5358 LDBase->getPointerInfo(),
5359 LDBase->isVolatile(), LDBase->isNonTemporal(),
5360 LDBase->isInvariant(), LDBase->getAlignment());
5362 if (LDBase->hasAnyUseOfValue(1)) {
5363 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5365 SDValue(NewLd.getNode(), 1));
5366 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5367 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5368 SDValue(NewLd.getNode(), 1));
5373 if (NumElems == 4 && LastLoadedElt == 1 &&
5374 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5375 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5376 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5378 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5379 array_lengthof(Ops), MVT::i64,
5380 LDBase->getPointerInfo(),
5381 LDBase->getAlignment(),
5382 false/*isVolatile*/, true/*ReadMem*/,
5385 // Make sure the newly-created LOAD is in the same position as LDBase in
5386 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5387 // update uses of LDBase's output chain to use the TokenFactor.
5388 if (LDBase->hasAnyUseOfValue(1)) {
5389 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5390 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5391 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5392 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5393 SDValue(ResNode.getNode(), 1));
5396 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5401 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5402 /// to generate a splat value for the following cases:
5403 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5404 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5405 /// a scalar load, or a constant.
5406 /// The VBROADCAST node is returned when a pattern is found,
5407 /// or SDValue() otherwise.
5409 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5410 if (!Subtarget->hasFp256())
5413 MVT VT = Op.getValueType().getSimpleVT();
5416 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5417 "Unsupported vector type for broadcast.");
5422 switch (Op.getOpcode()) {
5424 // Unknown pattern found.
5427 case ISD::BUILD_VECTOR: {
5428 // The BUILD_VECTOR node must be a splat.
5429 if (!isSplatVector(Op.getNode()))
5432 Ld = Op.getOperand(0);
5433 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5434 Ld.getOpcode() == ISD::ConstantFP);
5436 // The suspected load node has several users. Make sure that all
5437 // of its users are from the BUILD_VECTOR node.
5438 // Constants may have multiple users.
5439 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5444 case ISD::VECTOR_SHUFFLE: {
5445 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5447 // Shuffles must have a splat mask where the first element is
5449 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5452 SDValue Sc = Op.getOperand(0);
5453 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5454 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5456 if (!Subtarget->hasInt256())
5459 // Use the register form of the broadcast instruction available on AVX2.
5460 if (VT.is256BitVector())
5461 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5462 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5465 Ld = Sc.getOperand(0);
5466 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5467 Ld.getOpcode() == ISD::ConstantFP);
5469 // The scalar_to_vector node and the suspected
5470 // load node must have exactly one user.
5471 // Constants may have multiple users.
5472 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5478 bool Is256 = VT.is256BitVector();
5480 // Handle the broadcasting a single constant scalar from the constant pool
5481 // into a vector. On Sandybridge it is still better to load a constant vector
5482 // from the constant pool and not to broadcast it from a scalar.
5483 if (ConstSplatVal && Subtarget->hasInt256()) {
5484 EVT CVT = Ld.getValueType();
5485 assert(!CVT.isVector() && "Must not broadcast a vector type");
5486 unsigned ScalarSize = CVT.getSizeInBits();
5488 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5489 const Constant *C = 0;
5490 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5491 C = CI->getConstantIntValue();
5492 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5493 C = CF->getConstantFPValue();
5495 assert(C && "Invalid constant type");
5497 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5498 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5499 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5500 MachinePointerInfo::getConstantPool(),
5501 false, false, false, Alignment);
5503 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5507 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5508 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5510 // Handle AVX2 in-register broadcasts.
5511 if (!IsLoad && Subtarget->hasInt256() &&
5512 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5513 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5515 // The scalar source must be a normal load.
5519 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5520 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5522 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5523 // double since there is no vbroadcastsd xmm
5524 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5525 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5526 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5529 // Unsupported broadcast.
5534 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5535 EVT VT = Op.getValueType();
5537 // Skip if insert_vec_elt is not supported.
5538 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5542 unsigned NumElems = Op.getNumOperands();
5546 SmallVector<unsigned, 4> InsertIndices;
5547 SmallVector<int, 8> Mask(NumElems, -1);
5549 for (unsigned i = 0; i != NumElems; ++i) {
5550 unsigned Opc = Op.getOperand(i).getOpcode();
5552 if (Opc == ISD::UNDEF)
5555 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5556 // Quit if more than 1 elements need inserting.
5557 if (InsertIndices.size() > 1)
5560 InsertIndices.push_back(i);
5564 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5565 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5567 // Quit if extracted from vector of different type.
5568 if (ExtractedFromVec.getValueType() != VT)
5571 // Quit if non-constant index.
5572 if (!isa<ConstantSDNode>(ExtIdx))
5575 if (VecIn1.getNode() == 0)
5576 VecIn1 = ExtractedFromVec;
5577 else if (VecIn1 != ExtractedFromVec) {
5578 if (VecIn2.getNode() == 0)
5579 VecIn2 = ExtractedFromVec;
5580 else if (VecIn2 != ExtractedFromVec)
5581 // Quit if more than 2 vectors to shuffle
5585 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5587 if (ExtractedFromVec == VecIn1)
5589 else if (ExtractedFromVec == VecIn2)
5590 Mask[i] = Idx + NumElems;
5593 if (VecIn1.getNode() == 0)
5596 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5597 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5598 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5599 unsigned Idx = InsertIndices[i];
5600 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5601 DAG.getIntPtrConstant(Idx));
5608 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5611 MVT VT = Op.getValueType().getSimpleVT();
5612 MVT ExtVT = VT.getVectorElementType();
5613 unsigned NumElems = Op.getNumOperands();
5615 // Vectors containing all zeros can be matched by pxor and xorps later
5616 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5617 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5618 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5619 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5622 return getZeroVector(VT, Subtarget, DAG, dl);
5625 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5626 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5627 // vpcmpeqd on 256-bit vectors.
5628 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5629 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5632 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5635 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5636 if (Broadcast.getNode())
5639 unsigned EVTBits = ExtVT.getSizeInBits();
5641 unsigned NumZero = 0;
5642 unsigned NumNonZero = 0;
5643 unsigned NonZeros = 0;
5644 bool IsAllConstants = true;
5645 SmallSet<SDValue, 8> Values;
5646 for (unsigned i = 0; i < NumElems; ++i) {
5647 SDValue Elt = Op.getOperand(i);
5648 if (Elt.getOpcode() == ISD::UNDEF)
5651 if (Elt.getOpcode() != ISD::Constant &&
5652 Elt.getOpcode() != ISD::ConstantFP)
5653 IsAllConstants = false;
5654 if (X86::isZeroNode(Elt))
5657 NonZeros |= (1 << i);
5662 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5663 if (NumNonZero == 0)
5664 return DAG.getUNDEF(VT);
5666 // Special case for single non-zero, non-undef, element.
5667 if (NumNonZero == 1) {
5668 unsigned Idx = countTrailingZeros(NonZeros);
5669 SDValue Item = Op.getOperand(Idx);
5671 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5672 // the value are obviously zero, truncate the value to i32 and do the
5673 // insertion that way. Only do this if the value is non-constant or if the
5674 // value is a constant being inserted into element 0. It is cheaper to do
5675 // a constant pool load than it is to do a movd + shuffle.
5676 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5677 (!IsAllConstants || Idx == 0)) {
5678 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5680 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5681 EVT VecVT = MVT::v4i32;
5682 unsigned VecElts = 4;
5684 // Truncate the value (which may itself be a constant) to i32, and
5685 // convert it to a vector with movd (S2V+shuffle to zero extend).
5686 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5687 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5688 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5690 // Now we have our 32-bit value zero extended in the low element of
5691 // a vector. If Idx != 0, swizzle it into place.
5693 SmallVector<int, 4> Mask;
5694 Mask.push_back(Idx);
5695 for (unsigned i = 1; i != VecElts; ++i)
5697 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5700 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5704 // If we have a constant or non-constant insertion into the low element of
5705 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5706 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5707 // depending on what the source datatype is.
5710 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5712 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5713 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5714 if (VT.is256BitVector()) {
5715 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5716 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5717 Item, DAG.getIntPtrConstant(0));
5719 assert(VT.is128BitVector() && "Expected an SSE value type!");
5720 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5721 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5722 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5725 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5726 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5727 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5728 if (VT.is256BitVector()) {
5729 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5730 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5732 assert(VT.is128BitVector() && "Expected an SSE value type!");
5733 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5735 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5739 // Is it a vector logical left shift?
5740 if (NumElems == 2 && Idx == 1 &&
5741 X86::isZeroNode(Op.getOperand(0)) &&
5742 !X86::isZeroNode(Op.getOperand(1))) {
5743 unsigned NumBits = VT.getSizeInBits();
5744 return getVShift(true, VT,
5745 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5746 VT, Op.getOperand(1)),
5747 NumBits/2, DAG, *this, dl);
5750 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5753 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5754 // is a non-constant being inserted into an element other than the low one,
5755 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5756 // movd/movss) to move this into the low element, then shuffle it into
5758 if (EVTBits == 32) {
5759 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5761 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5762 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5763 SmallVector<int, 8> MaskVec;
5764 for (unsigned i = 0; i != NumElems; ++i)
5765 MaskVec.push_back(i == Idx ? 0 : 1);
5766 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5770 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5771 if (Values.size() == 1) {
5772 if (EVTBits == 32) {
5773 // Instead of a shuffle like this:
5774 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5775 // Check if it's possible to issue this instead.
5776 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5777 unsigned Idx = countTrailingZeros(NonZeros);
5778 SDValue Item = Op.getOperand(Idx);
5779 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5780 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5785 // A vector full of immediates; various special cases are already
5786 // handled, so this is best done with a single constant-pool load.
5790 // For AVX-length vectors, build the individual 128-bit pieces and use
5791 // shuffles to put them in place.
5792 if (VT.is256BitVector()) {
5793 SmallVector<SDValue, 32> V;
5794 for (unsigned i = 0; i != NumElems; ++i)
5795 V.push_back(Op.getOperand(i));
5797 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5799 // Build both the lower and upper subvector.
5800 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5801 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5804 // Recreate the wider vector with the lower and upper part.
5805 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5808 // Let legalizer expand 2-wide build_vectors.
5809 if (EVTBits == 64) {
5810 if (NumNonZero == 1) {
5811 // One half is zero or undef.
5812 unsigned Idx = countTrailingZeros(NonZeros);
5813 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5814 Op.getOperand(Idx));
5815 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5820 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5821 if (EVTBits == 8 && NumElems == 16) {
5822 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5824 if (V.getNode()) return V;
5827 if (EVTBits == 16 && NumElems == 8) {
5828 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5830 if (V.getNode()) return V;
5833 // If element VT is == 32 bits, turn it into a number of shuffles.
5834 SmallVector<SDValue, 8> V(NumElems);
5835 if (NumElems == 4 && NumZero > 0) {
5836 for (unsigned i = 0; i < 4; ++i) {
5837 bool isZero = !(NonZeros & (1 << i));
5839 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5841 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5844 for (unsigned i = 0; i < 2; ++i) {
5845 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5848 V[i] = V[i*2]; // Must be a zero vector.
5851 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5854 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5857 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5862 bool Reverse1 = (NonZeros & 0x3) == 2;
5863 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5867 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5868 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5870 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5873 if (Values.size() > 1 && VT.is128BitVector()) {
5874 // Check for a build vector of consecutive loads.
5875 for (unsigned i = 0; i < NumElems; ++i)
5876 V[i] = Op.getOperand(i);
5878 // Check for elements which are consecutive loads.
5879 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5883 // Check for a build vector from mostly shuffle plus few inserting.
5884 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5888 // For SSE 4.1, use insertps to put the high elements into the low element.
5889 if (getSubtarget()->hasSSE41()) {
5891 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5892 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5894 Result = DAG.getUNDEF(VT);
5896 for (unsigned i = 1; i < NumElems; ++i) {
5897 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5898 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5899 Op.getOperand(i), DAG.getIntPtrConstant(i));
5904 // Otherwise, expand into a number of unpckl*, start by extending each of
5905 // our (non-undef) elements to the full vector width with the element in the
5906 // bottom slot of the vector (which generates no code for SSE).
5907 for (unsigned i = 0; i < NumElems; ++i) {
5908 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5909 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5911 V[i] = DAG.getUNDEF(VT);
5914 // Next, we iteratively mix elements, e.g. for v4f32:
5915 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5916 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5917 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5918 unsigned EltStride = NumElems >> 1;
5919 while (EltStride != 0) {
5920 for (unsigned i = 0; i < EltStride; ++i) {
5921 // If V[i+EltStride] is undef and this is the first round of mixing,
5922 // then it is safe to just drop this shuffle: V[i] is already in the
5923 // right place, the one element (since it's the first round) being
5924 // inserted as undef can be dropped. This isn't safe for successive
5925 // rounds because they will permute elements within both vectors.
5926 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5927 EltStride == NumElems/2)
5930 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5939 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5940 // to create 256-bit vectors from two other 128-bit ones.
5941 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5943 MVT ResVT = Op.getValueType().getSimpleVT();
5945 assert((ResVT.is256BitVector() ||
5946 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
5948 SDValue V1 = Op.getOperand(0);
5949 SDValue V2 = Op.getOperand(1);
5950 unsigned NumElems = ResVT.getVectorNumElements();
5951 if(ResVT.is256BitVector())
5952 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5954 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5957 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5958 assert(Op.getNumOperands() == 2);
5960 // AVX/AVX-512 can use the vinsertf128 instruction to create 256-bit vectors
5961 // from two other 128-bit ones.
5962 return LowerAVXCONCAT_VECTORS(Op, DAG);
5965 // Try to lower a shuffle node into a simple blend instruction.
5967 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5968 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5969 SDValue V1 = SVOp->getOperand(0);
5970 SDValue V2 = SVOp->getOperand(1);
5972 MVT VT = SVOp->getValueType(0).getSimpleVT();
5973 MVT EltVT = VT.getVectorElementType();
5974 unsigned NumElems = VT.getVectorNumElements();
5976 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5978 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5981 // Check the mask for BLEND and build the value.
5982 unsigned MaskValue = 0;
5983 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5984 unsigned NumLanes = (NumElems-1)/8 + 1;
5985 unsigned NumElemsInLane = NumElems / NumLanes;
5987 // Blend for v16i16 should be symetric for the both lanes.
5988 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5990 int SndLaneEltIdx = (NumLanes == 2) ?
5991 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5992 int EltIdx = SVOp->getMaskElt(i);
5994 if ((EltIdx < 0 || EltIdx == (int)i) &&
5995 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5998 if (((unsigned)EltIdx == (i + NumElems)) &&
5999 (SndLaneEltIdx < 0 ||
6000 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
6001 MaskValue |= (1<<i);
6006 // Convert i32 vectors to floating point if it is not AVX2.
6007 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
6009 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
6010 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
6012 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
6013 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
6016 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
6017 DAG.getConstant(MaskValue, MVT::i32));
6018 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
6021 // v8i16 shuffles - Prefer shuffles in the following order:
6022 // 1. [all] pshuflw, pshufhw, optional move
6023 // 2. [ssse3] 1 x pshufb
6024 // 3. [ssse3] 2 x pshufb + 1 x por
6025 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
6027 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
6028 SelectionDAG &DAG) {
6029 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6030 SDValue V1 = SVOp->getOperand(0);
6031 SDValue V2 = SVOp->getOperand(1);
6033 SmallVector<int, 8> MaskVals;
6035 // Determine if more than 1 of the words in each of the low and high quadwords
6036 // of the result come from the same quadword of one of the two inputs. Undef
6037 // mask values count as coming from any quadword, for better codegen.
6038 unsigned LoQuad[] = { 0, 0, 0, 0 };
6039 unsigned HiQuad[] = { 0, 0, 0, 0 };
6040 std::bitset<4> InputQuads;
6041 for (unsigned i = 0; i < 8; ++i) {
6042 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
6043 int EltIdx = SVOp->getMaskElt(i);
6044 MaskVals.push_back(EltIdx);
6053 InputQuads.set(EltIdx / 4);
6056 int BestLoQuad = -1;
6057 unsigned MaxQuad = 1;
6058 for (unsigned i = 0; i < 4; ++i) {
6059 if (LoQuad[i] > MaxQuad) {
6061 MaxQuad = LoQuad[i];
6065 int BestHiQuad = -1;
6067 for (unsigned i = 0; i < 4; ++i) {
6068 if (HiQuad[i] > MaxQuad) {
6070 MaxQuad = HiQuad[i];
6074 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
6075 // of the two input vectors, shuffle them into one input vector so only a
6076 // single pshufb instruction is necessary. If There are more than 2 input
6077 // quads, disable the next transformation since it does not help SSSE3.
6078 bool V1Used = InputQuads[0] || InputQuads[1];
6079 bool V2Used = InputQuads[2] || InputQuads[3];
6080 if (Subtarget->hasSSSE3()) {
6081 if (InputQuads.count() == 2 && V1Used && V2Used) {
6082 BestLoQuad = InputQuads[0] ? 0 : 1;
6083 BestHiQuad = InputQuads[2] ? 2 : 3;
6085 if (InputQuads.count() > 2) {
6091 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
6092 // the shuffle mask. If a quad is scored as -1, that means that it contains
6093 // words from all 4 input quadwords.
6095 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
6097 BestLoQuad < 0 ? 0 : BestLoQuad,
6098 BestHiQuad < 0 ? 1 : BestHiQuad
6100 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
6101 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
6102 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
6103 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
6105 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
6106 // source words for the shuffle, to aid later transformations.
6107 bool AllWordsInNewV = true;
6108 bool InOrder[2] = { true, true };
6109 for (unsigned i = 0; i != 8; ++i) {
6110 int idx = MaskVals[i];
6112 InOrder[i/4] = false;
6113 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
6115 AllWordsInNewV = false;
6119 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
6120 if (AllWordsInNewV) {
6121 for (int i = 0; i != 8; ++i) {
6122 int idx = MaskVals[i];
6125 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
6126 if ((idx != i) && idx < 4)
6128 if ((idx != i) && idx > 3)
6137 // If we've eliminated the use of V2, and the new mask is a pshuflw or
6138 // pshufhw, that's as cheap as it gets. Return the new shuffle.
6139 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
6140 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
6141 unsigned TargetMask = 0;
6142 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
6143 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
6144 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6145 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
6146 getShufflePSHUFLWImmediate(SVOp);
6147 V1 = NewV.getOperand(0);
6148 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
6152 // Promote splats to a larger type which usually leads to more efficient code.
6153 // FIXME: Is this true if pshufb is available?
6154 if (SVOp->isSplat())
6155 return PromoteSplat(SVOp, DAG);
6157 // If we have SSSE3, and all words of the result are from 1 input vector,
6158 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
6159 // is present, fall back to case 4.
6160 if (Subtarget->hasSSSE3()) {
6161 SmallVector<SDValue,16> pshufbMask;
6163 // If we have elements from both input vectors, set the high bit of the
6164 // shuffle mask element to zero out elements that come from V2 in the V1
6165 // mask, and elements that come from V1 in the V2 mask, so that the two
6166 // results can be OR'd together.
6167 bool TwoInputs = V1Used && V2Used;
6168 for (unsigned i = 0; i != 8; ++i) {
6169 int EltIdx = MaskVals[i] * 2;
6170 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
6171 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
6172 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6173 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6175 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
6176 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6177 DAG.getNode(ISD::BUILD_VECTOR, dl,
6178 MVT::v16i8, &pshufbMask[0], 16));
6180 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6182 // Calculate the shuffle mask for the second input, shuffle it, and
6183 // OR it with the first shuffled input.
6185 for (unsigned i = 0; i != 8; ++i) {
6186 int EltIdx = MaskVals[i] * 2;
6187 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6188 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
6189 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
6190 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
6192 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
6193 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6194 DAG.getNode(ISD::BUILD_VECTOR, dl,
6195 MVT::v16i8, &pshufbMask[0], 16));
6196 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6197 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6200 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
6201 // and update MaskVals with new element order.
6202 std::bitset<8> InOrder;
6203 if (BestLoQuad >= 0) {
6204 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
6205 for (int i = 0; i != 4; ++i) {
6206 int idx = MaskVals[i];
6209 } else if ((idx / 4) == BestLoQuad) {
6214 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6217 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6218 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6219 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
6221 getShufflePSHUFLWImmediate(SVOp), DAG);
6225 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
6226 // and update MaskVals with the new element order.
6227 if (BestHiQuad >= 0) {
6228 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
6229 for (unsigned i = 4; i != 8; ++i) {
6230 int idx = MaskVals[i];
6233 } else if ((idx / 4) == BestHiQuad) {
6234 MaskV[i] = (idx & 3) + 4;
6238 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
6241 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
6242 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
6243 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
6245 getShufflePSHUFHWImmediate(SVOp), DAG);
6249 // In case BestHi & BestLo were both -1, which means each quadword has a word
6250 // from each of the four input quadwords, calculate the InOrder bitvector now
6251 // before falling through to the insert/extract cleanup.
6252 if (BestLoQuad == -1 && BestHiQuad == -1) {
6254 for (int i = 0; i != 8; ++i)
6255 if (MaskVals[i] < 0 || MaskVals[i] == i)
6259 // The other elements are put in the right place using pextrw and pinsrw.
6260 for (unsigned i = 0; i != 8; ++i) {
6263 int EltIdx = MaskVals[i];
6266 SDValue ExtOp = (EltIdx < 8) ?
6267 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6268 DAG.getIntPtrConstant(EltIdx)) :
6269 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6270 DAG.getIntPtrConstant(EltIdx - 8));
6271 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6272 DAG.getIntPtrConstant(i));
6277 // v16i8 shuffles - Prefer shuffles in the following order:
6278 // 1. [ssse3] 1 x pshufb
6279 // 2. [ssse3] 2 x pshufb + 1 x por
6280 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6282 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6284 const X86TargetLowering &TLI) {
6285 SDValue V1 = SVOp->getOperand(0);
6286 SDValue V2 = SVOp->getOperand(1);
6288 ArrayRef<int> MaskVals = SVOp->getMask();
6290 // Promote splats to a larger type which usually leads to more efficient code.
6291 // FIXME: Is this true if pshufb is available?
6292 if (SVOp->isSplat())
6293 return PromoteSplat(SVOp, DAG);
6295 // If we have SSSE3, case 1 is generated when all result bytes come from
6296 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6297 // present, fall back to case 3.
6299 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6300 if (TLI.getSubtarget()->hasSSSE3()) {
6301 SmallVector<SDValue,16> pshufbMask;
6303 // If all result elements are from one input vector, then only translate
6304 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6306 // Otherwise, we have elements from both input vectors, and must zero out
6307 // elements that come from V2 in the first mask, and V1 in the second mask
6308 // so that we can OR them together.
6309 for (unsigned i = 0; i != 16; ++i) {
6310 int EltIdx = MaskVals[i];
6311 if (EltIdx < 0 || EltIdx >= 16)
6313 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6315 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6316 DAG.getNode(ISD::BUILD_VECTOR, dl,
6317 MVT::v16i8, &pshufbMask[0], 16));
6319 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6320 // the 2nd operand if it's undefined or zero.
6321 if (V2.getOpcode() == ISD::UNDEF ||
6322 ISD::isBuildVectorAllZeros(V2.getNode()))
6325 // Calculate the shuffle mask for the second input, shuffle it, and
6326 // OR it with the first shuffled input.
6328 for (unsigned i = 0; i != 16; ++i) {
6329 int EltIdx = MaskVals[i];
6330 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6331 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6333 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6334 DAG.getNode(ISD::BUILD_VECTOR, dl,
6335 MVT::v16i8, &pshufbMask[0], 16));
6336 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6339 // No SSSE3 - Calculate in place words and then fix all out of place words
6340 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6341 // the 16 different words that comprise the two doublequadword input vectors.
6342 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6343 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6345 for (int i = 0; i != 8; ++i) {
6346 int Elt0 = MaskVals[i*2];
6347 int Elt1 = MaskVals[i*2+1];
6349 // This word of the result is all undef, skip it.
6350 if (Elt0 < 0 && Elt1 < 0)
6353 // This word of the result is already in the correct place, skip it.
6354 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6357 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6358 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6361 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6362 // using a single extract together, load it and store it.
6363 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6364 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6365 DAG.getIntPtrConstant(Elt1 / 2));
6366 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6367 DAG.getIntPtrConstant(i));
6371 // If Elt1 is defined, extract it from the appropriate source. If the
6372 // source byte is not also odd, shift the extracted word left 8 bits
6373 // otherwise clear the bottom 8 bits if we need to do an or.
6375 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6376 DAG.getIntPtrConstant(Elt1 / 2));
6377 if ((Elt1 & 1) == 0)
6378 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6380 TLI.getShiftAmountTy(InsElt.getValueType())));
6382 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6383 DAG.getConstant(0xFF00, MVT::i16));
6385 // If Elt0 is defined, extract it from the appropriate source. If the
6386 // source byte is not also even, shift the extracted word right 8 bits. If
6387 // Elt1 was also defined, OR the extracted values together before
6388 // inserting them in the result.
6390 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6391 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6392 if ((Elt0 & 1) != 0)
6393 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6395 TLI.getShiftAmountTy(InsElt0.getValueType())));
6397 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6398 DAG.getConstant(0x00FF, MVT::i16));
6399 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6402 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6403 DAG.getIntPtrConstant(i));
6405 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6408 // v32i8 shuffles - Translate to VPSHUFB if possible.
6410 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6411 const X86Subtarget *Subtarget,
6412 SelectionDAG &DAG) {
6413 MVT VT = SVOp->getValueType(0).getSimpleVT();
6414 SDValue V1 = SVOp->getOperand(0);
6415 SDValue V2 = SVOp->getOperand(1);
6417 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6419 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6420 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6421 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6423 // VPSHUFB may be generated if
6424 // (1) one of input vector is undefined or zeroinitializer.
6425 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6426 // And (2) the mask indexes don't cross the 128-bit lane.
6427 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6428 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6431 if (V1IsAllZero && !V2IsAllZero) {
6432 CommuteVectorShuffleMask(MaskVals, 32);
6435 SmallVector<SDValue, 32> pshufbMask;
6436 for (unsigned i = 0; i != 32; i++) {
6437 int EltIdx = MaskVals[i];
6438 if (EltIdx < 0 || EltIdx >= 32)
6441 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6442 // Cross lane is not allowed.
6446 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6448 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6449 DAG.getNode(ISD::BUILD_VECTOR, dl,
6450 MVT::v32i8, &pshufbMask[0], 32));
6453 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6454 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6455 /// done when every pair / quad of shuffle mask elements point to elements in
6456 /// the right sequence. e.g.
6457 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6459 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6460 SelectionDAG &DAG) {
6461 MVT VT = SVOp->getValueType(0).getSimpleVT();
6463 unsigned NumElems = VT.getVectorNumElements();
6466 switch (VT.SimpleTy) {
6467 default: llvm_unreachable("Unexpected!");
6468 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6469 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6470 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6471 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6472 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6473 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6476 SmallVector<int, 8> MaskVec;
6477 for (unsigned i = 0; i != NumElems; i += Scale) {
6479 for (unsigned j = 0; j != Scale; ++j) {
6480 int EltIdx = SVOp->getMaskElt(i+j);
6484 StartIdx = (EltIdx / Scale);
6485 if (EltIdx != (int)(StartIdx*Scale + j))
6488 MaskVec.push_back(StartIdx);
6491 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6492 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6493 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6496 /// getVZextMovL - Return a zero-extending vector move low node.
6498 static SDValue getVZextMovL(MVT VT, EVT OpVT,
6499 SDValue SrcOp, SelectionDAG &DAG,
6500 const X86Subtarget *Subtarget, SDLoc dl) {
6501 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6502 LoadSDNode *LD = NULL;
6503 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6504 LD = dyn_cast<LoadSDNode>(SrcOp);
6506 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6508 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6509 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6510 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6511 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6512 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6514 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6515 return DAG.getNode(ISD::BITCAST, dl, VT,
6516 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6517 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6525 return DAG.getNode(ISD::BITCAST, dl, VT,
6526 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6527 DAG.getNode(ISD::BITCAST, dl,
6531 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6532 /// which could not be matched by any known target speficic shuffle
6534 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6536 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6537 if (NewOp.getNode())
6540 MVT VT = SVOp->getValueType(0).getSimpleVT();
6542 unsigned NumElems = VT.getVectorNumElements();
6543 unsigned NumLaneElems = NumElems / 2;
6546 MVT EltVT = VT.getVectorElementType();
6547 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6550 SmallVector<int, 16> Mask;
6551 for (unsigned l = 0; l < 2; ++l) {
6552 // Build a shuffle mask for the output, discovering on the fly which
6553 // input vectors to use as shuffle operands (recorded in InputUsed).
6554 // If building a suitable shuffle vector proves too hard, then bail
6555 // out with UseBuildVector set.
6556 bool UseBuildVector = false;
6557 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6558 unsigned LaneStart = l * NumLaneElems;
6559 for (unsigned i = 0; i != NumLaneElems; ++i) {
6560 // The mask element. This indexes into the input.
6561 int Idx = SVOp->getMaskElt(i+LaneStart);
6563 // the mask element does not index into any input vector.
6568 // The input vector this mask element indexes into.
6569 int Input = Idx / NumLaneElems;
6571 // Turn the index into an offset from the start of the input vector.
6572 Idx -= Input * NumLaneElems;
6574 // Find or create a shuffle vector operand to hold this input.
6576 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6577 if (InputUsed[OpNo] == Input)
6578 // This input vector is already an operand.
6580 if (InputUsed[OpNo] < 0) {
6581 // Create a new operand for this input vector.
6582 InputUsed[OpNo] = Input;
6587 if (OpNo >= array_lengthof(InputUsed)) {
6588 // More than two input vectors used! Give up on trying to create a
6589 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6590 UseBuildVector = true;
6594 // Add the mask index for the new shuffle vector.
6595 Mask.push_back(Idx + OpNo * NumLaneElems);
6598 if (UseBuildVector) {
6599 SmallVector<SDValue, 16> SVOps;
6600 for (unsigned i = 0; i != NumLaneElems; ++i) {
6601 // The mask element. This indexes into the input.
6602 int Idx = SVOp->getMaskElt(i+LaneStart);
6604 SVOps.push_back(DAG.getUNDEF(EltVT));
6608 // The input vector this mask element indexes into.
6609 int Input = Idx / NumElems;
6611 // Turn the index into an offset from the start of the input vector.
6612 Idx -= Input * NumElems;
6614 // Extract the vector element by hand.
6615 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6616 SVOp->getOperand(Input),
6617 DAG.getIntPtrConstant(Idx)));
6620 // Construct the output using a BUILD_VECTOR.
6621 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6623 } else if (InputUsed[0] < 0) {
6624 // No input vectors were used! The result is undefined.
6625 Output[l] = DAG.getUNDEF(NVT);
6627 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6628 (InputUsed[0] % 2) * NumLaneElems,
6630 // If only one input was used, use an undefined vector for the other.
6631 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6632 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6633 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6634 // At least one input vector was used. Create a new shuffle vector.
6635 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6641 // Concatenate the result back
6642 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6645 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6646 /// 4 elements, and match them with several different shuffle types.
6648 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6649 SDValue V1 = SVOp->getOperand(0);
6650 SDValue V2 = SVOp->getOperand(1);
6652 MVT VT = SVOp->getValueType(0).getSimpleVT();
6654 assert(VT.is128BitVector() && "Unsupported vector size");
6656 std::pair<int, int> Locs[4];
6657 int Mask1[] = { -1, -1, -1, -1 };
6658 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6662 for (unsigned i = 0; i != 4; ++i) {
6663 int Idx = PermMask[i];
6665 Locs[i] = std::make_pair(-1, -1);
6667 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6669 Locs[i] = std::make_pair(0, NumLo);
6673 Locs[i] = std::make_pair(1, NumHi);
6675 Mask1[2+NumHi] = Idx;
6681 if (NumLo <= 2 && NumHi <= 2) {
6682 // If no more than two elements come from either vector. This can be
6683 // implemented with two shuffles. First shuffle gather the elements.
6684 // The second shuffle, which takes the first shuffle as both of its
6685 // vector operands, put the elements into the right order.
6686 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6688 int Mask2[] = { -1, -1, -1, -1 };
6690 for (unsigned i = 0; i != 4; ++i)
6691 if (Locs[i].first != -1) {
6692 unsigned Idx = (i < 2) ? 0 : 4;
6693 Idx += Locs[i].first * 2 + Locs[i].second;
6697 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6700 if (NumLo == 3 || NumHi == 3) {
6701 // Otherwise, we must have three elements from one vector, call it X, and
6702 // one element from the other, call it Y. First, use a shufps to build an
6703 // intermediate vector with the one element from Y and the element from X
6704 // that will be in the same half in the final destination (the indexes don't
6705 // matter). Then, use a shufps to build the final vector, taking the half
6706 // containing the element from Y from the intermediate, and the other half
6709 // Normalize it so the 3 elements come from V1.
6710 CommuteVectorShuffleMask(PermMask, 4);
6714 // Find the element from V2.
6716 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6717 int Val = PermMask[HiIndex];
6724 Mask1[0] = PermMask[HiIndex];
6726 Mask1[2] = PermMask[HiIndex^1];
6728 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6731 Mask1[0] = PermMask[0];
6732 Mask1[1] = PermMask[1];
6733 Mask1[2] = HiIndex & 1 ? 6 : 4;
6734 Mask1[3] = HiIndex & 1 ? 4 : 6;
6735 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6738 Mask1[0] = HiIndex & 1 ? 2 : 0;
6739 Mask1[1] = HiIndex & 1 ? 0 : 2;
6740 Mask1[2] = PermMask[2];
6741 Mask1[3] = PermMask[3];
6746 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6749 // Break it into (shuffle shuffle_hi, shuffle_lo).
6750 int LoMask[] = { -1, -1, -1, -1 };
6751 int HiMask[] = { -1, -1, -1, -1 };
6753 int *MaskPtr = LoMask;
6754 unsigned MaskIdx = 0;
6757 for (unsigned i = 0; i != 4; ++i) {
6764 int Idx = PermMask[i];
6766 Locs[i] = std::make_pair(-1, -1);
6767 } else if (Idx < 4) {
6768 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6769 MaskPtr[LoIdx] = Idx;
6772 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6773 MaskPtr[HiIdx] = Idx;
6778 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6779 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6780 int MaskOps[] = { -1, -1, -1, -1 };
6781 for (unsigned i = 0; i != 4; ++i)
6782 if (Locs[i].first != -1)
6783 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6784 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6787 static bool MayFoldVectorLoad(SDValue V) {
6788 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6789 V = V.getOperand(0);
6791 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6792 V = V.getOperand(0);
6793 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6794 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6795 // BUILD_VECTOR (load), undef
6796 V = V.getOperand(0);
6798 return MayFoldLoad(V);
6802 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
6803 EVT VT = Op.getValueType();
6805 // Canonizalize to v2f64.
6806 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6807 return DAG.getNode(ISD::BITCAST, dl, VT,
6808 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6813 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
6815 SDValue V1 = Op.getOperand(0);
6816 SDValue V2 = Op.getOperand(1);
6817 EVT VT = Op.getValueType();
6819 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6821 if (HasSSE2 && VT == MVT::v2f64)
6822 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6824 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6825 return DAG.getNode(ISD::BITCAST, dl, VT,
6826 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6827 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6828 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6832 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
6833 SDValue V1 = Op.getOperand(0);
6834 SDValue V2 = Op.getOperand(1);
6835 EVT VT = Op.getValueType();
6837 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6838 "unsupported shuffle type");
6840 if (V2.getOpcode() == ISD::UNDEF)
6844 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6848 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6849 SDValue V1 = Op.getOperand(0);
6850 SDValue V2 = Op.getOperand(1);
6851 EVT VT = Op.getValueType();
6852 unsigned NumElems = VT.getVectorNumElements();
6854 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6855 // operand of these instructions is only memory, so check if there's a
6856 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6858 bool CanFoldLoad = false;
6860 // Trivial case, when V2 comes from a load.
6861 if (MayFoldVectorLoad(V2))
6864 // When V1 is a load, it can be folded later into a store in isel, example:
6865 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6867 // (MOVLPSmr addr:$src1, VR128:$src2)
6868 // So, recognize this potential and also use MOVLPS or MOVLPD
6869 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6872 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6874 if (HasSSE2 && NumElems == 2)
6875 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6878 // If we don't care about the second element, proceed to use movss.
6879 if (SVOp->getMaskElt(1) != -1)
6880 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6883 // movl and movlp will both match v2i64, but v2i64 is never matched by
6884 // movl earlier because we make it strict to avoid messing with the movlp load
6885 // folding logic (see the code above getMOVLP call). Match it here then,
6886 // this is horrible, but will stay like this until we move all shuffle
6887 // matching to x86 specific nodes. Note that for the 1st condition all
6888 // types are matched with movsd.
6890 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6891 // as to remove this logic from here, as much as possible
6892 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6893 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6894 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6897 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6899 // Invert the operand order and use SHUFPS to match it.
6900 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6901 getShuffleSHUFImmediate(SVOp), DAG);
6904 // Reduce a vector shuffle to zext.
6906 X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6907 // PMOVZX is only available from SSE41.
6908 if (!Subtarget->hasSSE41())
6911 EVT VT = Op.getValueType();
6913 // Only AVX2 support 256-bit vector integer extending.
6914 if (!Subtarget->hasInt256() && VT.is256BitVector())
6917 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6919 SDValue V1 = Op.getOperand(0);
6920 SDValue V2 = Op.getOperand(1);
6921 unsigned NumElems = VT.getVectorNumElements();
6923 // Extending is an unary operation and the element type of the source vector
6924 // won't be equal to or larger than i64.
6925 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6926 VT.getVectorElementType() == MVT::i64)
6929 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6930 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6931 while ((1U << Shift) < NumElems) {
6932 if (SVOp->getMaskElt(1U << Shift) == 1)
6935 // The maximal ratio is 8, i.e. from i8 to i64.
6940 // Check the shuffle mask.
6941 unsigned Mask = (1U << Shift) - 1;
6942 for (unsigned i = 0; i != NumElems; ++i) {
6943 int EltIdx = SVOp->getMaskElt(i);
6944 if ((i & Mask) != 0 && EltIdx != -1)
6946 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6950 LLVMContext *Context = DAG.getContext();
6951 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6952 EVT NeVT = EVT::getIntegerVT(*Context, NBits);
6953 EVT NVT = EVT::getVectorVT(*Context, NeVT, NumElems >> Shift);
6955 if (!isTypeLegal(NVT))
6958 // Simplify the operand as it's prepared to be fed into shuffle.
6959 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6960 if (V1.getOpcode() == ISD::BITCAST &&
6961 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6962 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6964 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6965 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6966 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6967 ConstantSDNode *CIdx =
6968 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6969 // If it's foldable, i.e. normal load with single use, we will let code
6970 // selection to fold it. Otherwise, we will short the conversion sequence.
6971 if (CIdx && CIdx->getZExtValue() == 0 &&
6972 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
6973 if (V.getValueSizeInBits() > V1.getValueSizeInBits()) {
6974 // The "ext_vec_elt" node is wider than the result node.
6975 // In this case we should extract subvector from V.
6976 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
6977 unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits();
6978 EVT FullVT = V.getValueType();
6979 EVT SubVecVT = EVT::getVectorVT(*Context,
6980 FullVT.getVectorElementType(),
6981 FullVT.getVectorNumElements()/Ratio);
6982 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
6983 DAG.getIntPtrConstant(0));
6985 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6989 return DAG.getNode(ISD::BITCAST, DL, VT,
6990 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6994 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6995 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6996 MVT VT = Op.getValueType().getSimpleVT();
6998 SDValue V1 = Op.getOperand(0);
6999 SDValue V2 = Op.getOperand(1);
7001 if (isZeroShuffle(SVOp))
7002 return getZeroVector(VT, Subtarget, DAG, dl);
7004 // Handle splat operations
7005 if (SVOp->isSplat()) {
7006 // Use vbroadcast whenever the splat comes from a foldable load
7007 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
7008 if (Broadcast.getNode())
7012 // Check integer expanding shuffles.
7013 SDValue NewOp = LowerVectorIntExtend(Op, DAG);
7014 if (NewOp.getNode())
7017 // If the shuffle can be profitably rewritten as a narrower shuffle, then
7019 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
7020 VT == MVT::v16i16 || VT == MVT::v32i8) {
7021 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7022 if (NewOp.getNode())
7023 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
7024 } else if ((VT == MVT::v4i32 ||
7025 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
7026 // FIXME: Figure out a cleaner way to do this.
7027 // Try to make use of movq to zero out the top part.
7028 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
7029 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7030 if (NewOp.getNode()) {
7031 MVT NewVT = NewOp.getValueType().getSimpleVT();
7032 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
7033 NewVT, true, false))
7034 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
7035 DAG, Subtarget, dl);
7037 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
7038 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
7039 if (NewOp.getNode()) {
7040 MVT NewVT = NewOp.getValueType().getSimpleVT();
7041 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
7042 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
7043 DAG, Subtarget, dl);
7051 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
7052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7053 SDValue V1 = Op.getOperand(0);
7054 SDValue V2 = Op.getOperand(1);
7055 MVT VT = Op.getValueType().getSimpleVT();
7057 unsigned NumElems = VT.getVectorNumElements();
7058 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
7059 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
7060 bool V1IsSplat = false;
7061 bool V2IsSplat = false;
7062 bool HasSSE2 = Subtarget->hasSSE2();
7063 bool HasFp256 = Subtarget->hasFp256();
7064 bool HasInt256 = Subtarget->hasInt256();
7065 MachineFunction &MF = DAG.getMachineFunction();
7066 bool OptForSize = MF.getFunction()->getAttributes().
7067 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
7069 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
7071 if (V1IsUndef && V2IsUndef)
7072 return DAG.getUNDEF(VT);
7074 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
7076 // Vector shuffle lowering takes 3 steps:
7078 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
7079 // narrowing and commutation of operands should be handled.
7080 // 2) Matching of shuffles with known shuffle masks to x86 target specific
7082 // 3) Rewriting of unmatched masks into new generic shuffle operations,
7083 // so the shuffle can be broken into other shuffles and the legalizer can
7084 // try the lowering again.
7086 // The general idea is that no vector_shuffle operation should be left to
7087 // be matched during isel, all of them must be converted to a target specific
7090 // Normalize the input vectors. Here splats, zeroed vectors, profitable
7091 // narrowing and commutation of operands should be handled. The actual code
7092 // doesn't include all of those, work in progress...
7093 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
7094 if (NewOp.getNode())
7097 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
7099 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
7100 // unpckh_undef). Only use pshufd if speed is more important than size.
7101 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7102 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7103 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7104 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7106 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
7107 V2IsUndef && MayFoldVectorLoad(V1))
7108 return getMOVDDup(Op, dl, V1, DAG);
7110 if (isMOVHLPS_v_undef_Mask(M, VT))
7111 return getMOVHighToLow(Op, dl, DAG);
7113 // Use to match splats
7114 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
7115 (VT == MVT::v2f64 || VT == MVT::v2i64))
7116 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7118 if (isPSHUFDMask(M, VT)) {
7119 // The actual implementation will match the mask in the if above and then
7120 // during isel it can match several different instructions, not only pshufd
7121 // as its name says, sad but true, emulate the behavior for now...
7122 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
7123 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
7125 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
7127 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
7128 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
7130 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
7131 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
7134 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
7138 if (isPALIGNRMask(M, VT, Subtarget))
7139 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
7140 getShufflePALIGNRImmediate(SVOp),
7143 // Check if this can be converted into a logical shift.
7144 bool isLeft = false;
7147 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
7148 if (isShift && ShVal.hasOneUse()) {
7149 // If the shifted value has multiple uses, it may be cheaper to use
7150 // v_set0 + movlhps or movhlps, etc.
7151 MVT EltVT = VT.getVectorElementType();
7152 ShAmt *= EltVT.getSizeInBits();
7153 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7156 if (isMOVLMask(M, VT)) {
7157 if (ISD::isBuildVectorAllZeros(V1.getNode()))
7158 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
7159 if (!isMOVLPMask(M, VT)) {
7160 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
7161 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
7163 if (VT == MVT::v4i32 || VT == MVT::v4f32)
7164 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
7168 // FIXME: fold these into legal mask.
7169 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
7170 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
7172 if (isMOVHLPSMask(M, VT))
7173 return getMOVHighToLow(Op, dl, DAG);
7175 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
7176 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
7178 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
7179 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
7181 if (isMOVLPMask(M, VT))
7182 return getMOVLP(Op, dl, DAG, HasSSE2);
7184 if (ShouldXformToMOVHLPS(M, VT) ||
7185 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
7186 return CommuteVectorShuffle(SVOp, DAG);
7189 // No better options. Use a vshldq / vsrldq.
7190 MVT EltVT = VT.getVectorElementType();
7191 ShAmt *= EltVT.getSizeInBits();
7192 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
7195 bool Commuted = false;
7196 // FIXME: This should also accept a bitcast of a splat? Be careful, not
7197 // 1,1,1,1 -> v8i16 though.
7198 V1IsSplat = isSplatVector(V1.getNode());
7199 V2IsSplat = isSplatVector(V2.getNode());
7201 // Canonicalize the splat or undef, if present, to be on the RHS.
7202 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
7203 CommuteVectorShuffleMask(M, NumElems);
7205 std::swap(V1IsSplat, V2IsSplat);
7209 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
7210 // Shuffling low element of v1 into undef, just return v1.
7213 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
7214 // the instruction selector will not match, so get a canonical MOVL with
7215 // swapped operands to undo the commute.
7216 return getMOVL(DAG, dl, VT, V2, V1);
7219 if (isUNPCKLMask(M, VT, HasInt256))
7220 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7222 if (isUNPCKHMask(M, VT, HasInt256))
7223 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7226 // Normalize mask so all entries that point to V2 points to its first
7227 // element then try to match unpck{h|l} again. If match, return a
7228 // new vector_shuffle with the corrected mask.p
7229 SmallVector<int, 8> NewMask(M.begin(), M.end());
7230 NormalizeMask(NewMask, NumElems);
7231 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
7232 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7233 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
7234 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7238 // Commute is back and try unpck* again.
7239 // FIXME: this seems wrong.
7240 CommuteVectorShuffleMask(M, NumElems);
7242 std::swap(V1IsSplat, V2IsSplat);
7245 if (isUNPCKLMask(M, VT, HasInt256))
7246 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
7248 if (isUNPCKHMask(M, VT, HasInt256))
7249 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
7252 // Normalize the node to match x86 shuffle ops if needed
7253 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
7254 return CommuteVectorShuffle(SVOp, DAG);
7256 // The checks below are all present in isShuffleMaskLegal, but they are
7257 // inlined here right now to enable us to directly emit target specific
7258 // nodes, and remove one by one until they don't return Op anymore.
7260 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7261 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7262 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7263 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7266 if (isPSHUFHWMask(M, VT, HasInt256))
7267 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7268 getShufflePSHUFHWImmediate(SVOp),
7271 if (isPSHUFLWMask(M, VT, HasInt256))
7272 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7273 getShufflePSHUFLWImmediate(SVOp),
7276 if (isSHUFPMask(M, VT, HasFp256))
7277 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7278 getShuffleSHUFImmediate(SVOp), DAG);
7280 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7281 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7282 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7283 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7285 //===--------------------------------------------------------------------===//
7286 // Generate target specific nodes for 128 or 256-bit shuffles only
7287 // supported in the AVX instruction set.
7290 // Handle VMOVDDUPY permutations
7291 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7292 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7294 // Handle VPERMILPS/D* permutations
7295 if (isVPERMILPMask(M, VT, HasFp256)) {
7296 if (HasInt256 && VT == MVT::v8i32)
7297 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7298 getShuffleSHUFImmediate(SVOp), DAG);
7299 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7300 getShuffleSHUFImmediate(SVOp), DAG);
7303 // Handle VPERM2F128/VPERM2I128 permutations
7304 if (isVPERM2X128Mask(M, VT, HasFp256))
7305 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7306 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7308 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7309 if (BlendOp.getNode())
7312 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
7313 SmallVector<SDValue, 8> permclMask;
7314 for (unsigned i = 0; i != 8; ++i) {
7315 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
7317 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
7319 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7320 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7321 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7324 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
7325 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
7326 getShuffleCLImmediate(SVOp), DAG);
7328 //===--------------------------------------------------------------------===//
7329 // Since no target specific shuffle was selected for this generic one,
7330 // lower it into other known shuffles. FIXME: this isn't true yet, but
7331 // this is the plan.
7334 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7335 if (VT == MVT::v8i16) {
7336 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7337 if (NewOp.getNode())
7341 if (VT == MVT::v16i8) {
7342 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7343 if (NewOp.getNode())
7347 if (VT == MVT::v32i8) {
7348 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7349 if (NewOp.getNode())
7353 // Handle all 128-bit wide vectors with 4 elements, and match them with
7354 // several different shuffle types.
7355 if (NumElems == 4 && VT.is128BitVector())
7356 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7358 // Handle general 256-bit shuffles
7359 if (VT.is256BitVector())
7360 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7365 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7366 MVT VT = Op.getValueType().getSimpleVT();
7369 if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector())
7372 if (VT.getSizeInBits() == 8) {
7373 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7374 Op.getOperand(0), Op.getOperand(1));
7375 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7376 DAG.getValueType(VT));
7377 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7380 if (VT.getSizeInBits() == 16) {
7381 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7382 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7384 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7385 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7386 DAG.getNode(ISD::BITCAST, dl,
7390 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7391 Op.getOperand(0), Op.getOperand(1));
7392 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7393 DAG.getValueType(VT));
7394 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7397 if (VT == MVT::f32) {
7398 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7399 // the result back to FR32 register. It's only worth matching if the
7400 // result has a single use which is a store or a bitcast to i32. And in
7401 // the case of a store, it's not worth it if the index is a constant 0,
7402 // because a MOVSSmr can be used instead, which is smaller and faster.
7403 if (!Op.hasOneUse())
7405 SDNode *User = *Op.getNode()->use_begin();
7406 if ((User->getOpcode() != ISD::STORE ||
7407 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7408 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7409 (User->getOpcode() != ISD::BITCAST ||
7410 User->getValueType(0) != MVT::i32))
7412 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7413 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7416 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7419 if (VT == MVT::i32 || VT == MVT::i64) {
7420 // ExtractPS/pextrq works with constant index.
7421 if (isa<ConstantSDNode>(Op.getOperand(1)))
7428 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7429 SelectionDAG &DAG) const {
7431 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7434 SDValue Vec = Op.getOperand(0);
7435 MVT VecVT = Vec.getValueType().getSimpleVT();
7437 // If this is a 256-bit vector result, first extract the 128-bit vector and
7438 // then extract the element from the 128-bit vector.
7439 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
7440 SDValue Idx = Op.getOperand(1);
7441 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7443 // Get the 128-bit vector.
7444 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7445 EVT EltVT = VecVT.getVectorElementType();
7447 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
7449 //if (IdxVal >= NumElems/2)
7450 // IdxVal -= NumElems/2;
7451 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
7452 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7453 DAG.getConstant(IdxVal, MVT::i32));
7456 assert(VecVT.is128BitVector() && "Unexpected vector length");
7458 if (Subtarget->hasSSE41()) {
7459 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7464 MVT VT = Op.getValueType().getSimpleVT();
7465 // TODO: handle v16i8.
7466 if (VT.getSizeInBits() == 16) {
7467 SDValue Vec = Op.getOperand(0);
7468 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7470 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7471 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7472 DAG.getNode(ISD::BITCAST, dl,
7475 // Transform it so it match pextrw which produces a 32-bit result.
7476 MVT EltVT = MVT::i32;
7477 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7478 Op.getOperand(0), Op.getOperand(1));
7479 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7480 DAG.getValueType(VT));
7481 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7484 if (VT.getSizeInBits() == 32) {
7485 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7489 // SHUFPS the element to the lowest double word, then movss.
7490 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7491 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7492 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7493 DAG.getUNDEF(VVT), Mask);
7494 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7495 DAG.getIntPtrConstant(0));
7498 if (VT.getSizeInBits() == 64) {
7499 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7500 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7501 // to match extract_elt for f64.
7502 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7506 // UNPCKHPD the element to the lowest double word, then movsd.
7507 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7508 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7509 int Mask[2] = { 1, -1 };
7510 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7511 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7512 DAG.getUNDEF(VVT), Mask);
7513 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7514 DAG.getIntPtrConstant(0));
7520 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7521 MVT VT = Op.getValueType().getSimpleVT();
7522 MVT EltVT = VT.getVectorElementType();
7525 SDValue N0 = Op.getOperand(0);
7526 SDValue N1 = Op.getOperand(1);
7527 SDValue N2 = Op.getOperand(2);
7529 if (!VT.is128BitVector())
7532 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7533 isa<ConstantSDNode>(N2)) {
7535 if (VT == MVT::v8i16)
7536 Opc = X86ISD::PINSRW;
7537 else if (VT == MVT::v16i8)
7538 Opc = X86ISD::PINSRB;
7540 Opc = X86ISD::PINSRB;
7542 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7544 if (N1.getValueType() != MVT::i32)
7545 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7546 if (N2.getValueType() != MVT::i32)
7547 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7548 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7551 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7552 // Bits [7:6] of the constant are the source select. This will always be
7553 // zero here. The DAG Combiner may combine an extract_elt index into these
7554 // bits. For example (insert (extract, 3), 2) could be matched by putting
7555 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7556 // Bits [5:4] of the constant are the destination select. This is the
7557 // value of the incoming immediate.
7558 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7559 // combine either bitwise AND or insert of float 0.0 to set these bits.
7560 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7561 // Create this as a scalar to vector..
7562 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7563 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7566 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7567 // PINSR* works with constant index.
7574 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7575 MVT VT = Op.getValueType().getSimpleVT();
7576 MVT EltVT = VT.getVectorElementType();
7579 SDValue N0 = Op.getOperand(0);
7580 SDValue N1 = Op.getOperand(1);
7581 SDValue N2 = Op.getOperand(2);
7583 // If this is a 256-bit vector result, first extract the 128-bit vector,
7584 // insert the element into the extracted half and then place it back.
7585 if (VT.is256BitVector() || VT.is512BitVector()) {
7586 if (!isa<ConstantSDNode>(N2))
7589 // Get the desired 128-bit vector half.
7590 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7591 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7593 // Insert the element into the desired half.
7594 unsigned NumEltsIn128 = 128/EltVT.getSizeInBits();
7595 unsigned IdxIn128 = IdxVal - (IdxVal/NumEltsIn128) * NumEltsIn128;
7597 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7598 DAG.getConstant(IdxIn128, MVT::i32));
7600 // Insert the changed part back to the 256-bit vector
7601 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7604 if (Subtarget->hasSSE41())
7605 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7607 if (EltVT == MVT::i8)
7610 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7611 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7612 // as its second argument.
7613 if (N1.getValueType() != MVT::i32)
7614 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7615 if (N2.getValueType() != MVT::i32)
7616 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7617 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7622 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7623 LLVMContext *Context = DAG.getContext();
7625 MVT OpVT = Op.getValueType().getSimpleVT();
7627 // If this is a 256-bit vector result, first insert into a 128-bit
7628 // vector and then insert into the 256-bit vector.
7629 if (!OpVT.is128BitVector()) {
7630 // Insert into a 128-bit vector.
7631 unsigned SizeFactor = OpVT.getSizeInBits()/128;
7632 EVT VT128 = EVT::getVectorVT(*Context,
7633 OpVT.getVectorElementType(),
7634 OpVT.getVectorNumElements() / SizeFactor);
7636 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7638 // Insert the 128-bit vector.
7639 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7642 if (OpVT == MVT::v1i64 &&
7643 Op.getOperand(0).getValueType() == MVT::i64)
7644 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7646 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7647 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7648 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7649 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7652 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7653 // a simple subregister reference or explicit instructions to grab
7654 // upper bits of a vector.
7655 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7656 SelectionDAG &DAG) {
7658 SDValue In = Op.getOperand(0);
7659 SDValue Idx = Op.getOperand(1);
7660 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7661 EVT ResVT = Op.getValueType();
7662 EVT InVT = In.getValueType();
7664 if (Subtarget->hasFp256()) {
7665 if (ResVT.is128BitVector() &&
7666 (InVT.is256BitVector() || InVT.is512BitVector()) &&
7667 isa<ConstantSDNode>(Idx)) {
7668 return Extract128BitVector(In, IdxVal, DAG, dl);
7670 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
7671 isa<ConstantSDNode>(Idx)) {
7672 return Extract256BitVector(In, IdxVal, DAG, dl);
7678 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7679 // simple superregister reference or explicit instructions to insert
7680 // the upper bits of a vector.
7681 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7682 SelectionDAG &DAG) {
7683 if (Subtarget->hasFp256()) {
7684 SDLoc dl(Op.getNode());
7685 SDValue Vec = Op.getNode()->getOperand(0);
7686 SDValue SubVec = Op.getNode()->getOperand(1);
7687 SDValue Idx = Op.getNode()->getOperand(2);
7689 if ((Op.getNode()->getValueType(0).is256BitVector() ||
7690 Op.getNode()->getValueType(0).is512BitVector()) &&
7691 SubVec.getNode()->getValueType(0).is128BitVector() &&
7692 isa<ConstantSDNode>(Idx)) {
7693 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7694 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7697 if (Op.getNode()->getValueType(0).is512BitVector() &&
7698 SubVec.getNode()->getValueType(0).is256BitVector() &&
7699 isa<ConstantSDNode>(Idx)) {
7700 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7701 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
7707 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7708 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7709 // one of the above mentioned nodes. It has to be wrapped because otherwise
7710 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7711 // be used to form addressing mode. These wrapped nodes will be selected
7714 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7715 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7717 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7719 unsigned char OpFlag = 0;
7720 unsigned WrapperKind = X86ISD::Wrapper;
7721 CodeModel::Model M = getTargetMachine().getCodeModel();
7723 if (Subtarget->isPICStyleRIPRel() &&
7724 (M == CodeModel::Small || M == CodeModel::Kernel))
7725 WrapperKind = X86ISD::WrapperRIP;
7726 else if (Subtarget->isPICStyleGOT())
7727 OpFlag = X86II::MO_GOTOFF;
7728 else if (Subtarget->isPICStyleStubPIC())
7729 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7731 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7733 CP->getOffset(), OpFlag);
7735 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7736 // With PIC, the address is actually $g + Offset.
7738 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7739 DAG.getNode(X86ISD::GlobalBaseReg,
7740 SDLoc(), getPointerTy()),
7747 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7748 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7750 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7752 unsigned char OpFlag = 0;
7753 unsigned WrapperKind = X86ISD::Wrapper;
7754 CodeModel::Model M = getTargetMachine().getCodeModel();
7756 if (Subtarget->isPICStyleRIPRel() &&
7757 (M == CodeModel::Small || M == CodeModel::Kernel))
7758 WrapperKind = X86ISD::WrapperRIP;
7759 else if (Subtarget->isPICStyleGOT())
7760 OpFlag = X86II::MO_GOTOFF;
7761 else if (Subtarget->isPICStyleStubPIC())
7762 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7764 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7767 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7769 // With PIC, the address is actually $g + Offset.
7771 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7772 DAG.getNode(X86ISD::GlobalBaseReg,
7773 SDLoc(), getPointerTy()),
7780 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7781 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7783 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7785 unsigned char OpFlag = 0;
7786 unsigned WrapperKind = X86ISD::Wrapper;
7787 CodeModel::Model M = getTargetMachine().getCodeModel();
7789 if (Subtarget->isPICStyleRIPRel() &&
7790 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7791 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7792 OpFlag = X86II::MO_GOTPCREL;
7793 WrapperKind = X86ISD::WrapperRIP;
7794 } else if (Subtarget->isPICStyleGOT()) {
7795 OpFlag = X86II::MO_GOT;
7796 } else if (Subtarget->isPICStyleStubPIC()) {
7797 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7798 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7799 OpFlag = X86II::MO_DARWIN_NONLAZY;
7802 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7805 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7807 // With PIC, the address is actually $g + Offset.
7808 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7809 !Subtarget->is64Bit()) {
7810 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7811 DAG.getNode(X86ISD::GlobalBaseReg,
7812 SDLoc(), getPointerTy()),
7816 // For symbols that require a load from a stub to get the address, emit the
7818 if (isGlobalStubReference(OpFlag))
7819 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7820 MachinePointerInfo::getGOT(), false, false, false, 0);
7826 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7827 // Create the TargetBlockAddressAddress node.
7828 unsigned char OpFlags =
7829 Subtarget->ClassifyBlockAddressReference();
7830 CodeModel::Model M = getTargetMachine().getCodeModel();
7831 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7832 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7834 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7837 if (Subtarget->isPICStyleRIPRel() &&
7838 (M == CodeModel::Small || M == CodeModel::Kernel))
7839 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7841 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7843 // With PIC, the address is actually $g + Offset.
7844 if (isGlobalRelativeToPICBase(OpFlags)) {
7845 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7846 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7854 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
7855 int64_t Offset, SelectionDAG &DAG) const {
7856 // Create the TargetGlobalAddress node, folding in the constant
7857 // offset if it is legal.
7858 unsigned char OpFlags =
7859 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7860 CodeModel::Model M = getTargetMachine().getCodeModel();
7862 if (OpFlags == X86II::MO_NO_FLAG &&
7863 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7864 // A direct static reference to a global.
7865 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7868 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7871 if (Subtarget->isPICStyleRIPRel() &&
7872 (M == CodeModel::Small || M == CodeModel::Kernel))
7873 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7875 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7877 // With PIC, the address is actually $g + Offset.
7878 if (isGlobalRelativeToPICBase(OpFlags)) {
7879 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7880 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7884 // For globals that require a load from a stub to get the address, emit the
7886 if (isGlobalStubReference(OpFlags))
7887 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7888 MachinePointerInfo::getGOT(), false, false, false, 0);
7890 // If there was a non-zero offset that we didn't fold, create an explicit
7893 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7894 DAG.getConstant(Offset, getPointerTy()));
7900 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7901 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7902 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7903 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
7907 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7908 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7909 unsigned char OperandFlags, bool LocalDynamic = false) {
7910 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7911 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7913 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7914 GA->getValueType(0),
7918 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7922 SDValue Ops[] = { Chain, TGA, *InFlag };
7923 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
7925 SDValue Ops[] = { Chain, TGA };
7926 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
7929 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7930 MFI->setAdjustsStack(true);
7932 SDValue Flag = Chain.getValue(1);
7933 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7936 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7938 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7941 SDLoc dl(GA); // ? function entry point might be better
7942 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7943 DAG.getNode(X86ISD::GlobalBaseReg,
7944 SDLoc(), PtrVT), InFlag);
7945 InFlag = Chain.getValue(1);
7947 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7950 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7952 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7954 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7955 X86::RAX, X86II::MO_TLSGD);
7958 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7964 // Get the start address of the TLS block for this module.
7965 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7966 .getInfo<X86MachineFunctionInfo>();
7967 MFI->incNumLocalDynamicTLSAccesses();
7971 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7972 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7975 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7976 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
7977 InFlag = Chain.getValue(1);
7978 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7979 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7982 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7986 unsigned char OperandFlags = X86II::MO_DTPOFF;
7987 unsigned WrapperKind = X86ISD::Wrapper;
7988 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7989 GA->getValueType(0),
7990 GA->getOffset(), OperandFlags);
7991 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7993 // Add x@dtpoff with the base.
7994 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7997 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7998 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7999 const EVT PtrVT, TLSModel::Model model,
8000 bool is64Bit, bool isPIC) {
8003 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
8004 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
8005 is64Bit ? 257 : 256));
8007 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
8008 DAG.getIntPtrConstant(0),
8009 MachinePointerInfo(Ptr),
8010 false, false, false, 0);
8012 unsigned char OperandFlags = 0;
8013 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
8015 unsigned WrapperKind = X86ISD::Wrapper;
8016 if (model == TLSModel::LocalExec) {
8017 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
8018 } else if (model == TLSModel::InitialExec) {
8020 OperandFlags = X86II::MO_GOTTPOFF;
8021 WrapperKind = X86ISD::WrapperRIP;
8023 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
8026 llvm_unreachable("Unexpected model");
8029 // emit "addl x@ntpoff,%eax" (local exec)
8030 // or "addl x@indntpoff,%eax" (initial exec)
8031 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
8032 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8033 GA->getValueType(0),
8034 GA->getOffset(), OperandFlags);
8035 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
8037 if (model == TLSModel::InitialExec) {
8038 if (isPIC && !is64Bit) {
8039 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
8040 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
8044 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
8045 MachinePointerInfo::getGOT(), false, false, false,
8049 // The address of the thread local variable is the add of the thread
8050 // pointer with the offset of the variable.
8051 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
8055 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
8057 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
8058 const GlobalValue *GV = GA->getGlobal();
8060 if (Subtarget->isTargetELF()) {
8061 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
8064 case TLSModel::GeneralDynamic:
8065 if (Subtarget->is64Bit())
8066 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
8067 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
8068 case TLSModel::LocalDynamic:
8069 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
8070 Subtarget->is64Bit());
8071 case TLSModel::InitialExec:
8072 case TLSModel::LocalExec:
8073 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
8074 Subtarget->is64Bit(),
8075 getTargetMachine().getRelocationModel() == Reloc::PIC_);
8077 llvm_unreachable("Unknown TLS model.");
8080 if (Subtarget->isTargetDarwin()) {
8081 // Darwin only has one model of TLS. Lower to that.
8082 unsigned char OpFlag = 0;
8083 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
8084 X86ISD::WrapperRIP : X86ISD::Wrapper;
8086 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
8088 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
8089 !Subtarget->is64Bit();
8091 OpFlag = X86II::MO_TLVP_PIC_BASE;
8093 OpFlag = X86II::MO_TLVP;
8095 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
8096 GA->getValueType(0),
8097 GA->getOffset(), OpFlag);
8098 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
8100 // With PIC32, the address is actually $g + Offset.
8102 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8103 DAG.getNode(X86ISD::GlobalBaseReg,
8104 SDLoc(), getPointerTy()),
8107 // Lowering the machine isd will make sure everything is in the right
8109 SDValue Chain = DAG.getEntryNode();
8110 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8111 SDValue Args[] = { Chain, Offset };
8112 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
8114 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
8115 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8116 MFI->setAdjustsStack(true);
8118 // And our return value (tls address) is in the standard call return value
8120 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
8121 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
8125 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
8126 // Just use the implicit TLS architecture
8127 // Need to generate someting similar to:
8128 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
8130 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
8131 // mov rcx, qword [rdx+rcx*8]
8132 // mov eax, .tls$:tlsvar
8133 // [rax+rcx] contains the address
8134 // Windows 64bit: gs:0x58
8135 // Windows 32bit: fs:__tls_array
8137 // If GV is an alias then use the aliasee for determining
8138 // thread-localness.
8139 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
8140 GV = GA->resolveAliasedGlobal(false);
8142 SDValue Chain = DAG.getEntryNode();
8144 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
8145 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
8146 // use its literal value of 0x2C.
8147 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
8148 ? Type::getInt8PtrTy(*DAG.getContext(),
8150 : Type::getInt32PtrTy(*DAG.getContext(),
8153 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
8154 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
8155 DAG.getExternalSymbol("_tls_array", getPointerTy()));
8157 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
8158 MachinePointerInfo(Ptr),
8159 false, false, false, 0);
8161 // Load the _tls_index variable
8162 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
8163 if (Subtarget->is64Bit())
8164 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
8165 IDX, MachinePointerInfo(), MVT::i32,
8168 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
8169 false, false, false, 0);
8171 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
8173 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
8175 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
8176 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
8177 false, false, false, 0);
8179 // Get the offset of start of .tls section
8180 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
8181 GA->getValueType(0),
8182 GA->getOffset(), X86II::MO_SECREL);
8183 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
8185 // The address of the thread local variable is the add of the thread
8186 // pointer with the offset of the variable.
8187 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
8190 llvm_unreachable("TLS not implemented for this target.");
8193 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
8194 /// and take a 2 x i32 value to shift plus a shift amount.
8195 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
8196 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
8197 EVT VT = Op.getValueType();
8198 unsigned VTBits = VT.getSizeInBits();
8200 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
8201 SDValue ShOpLo = Op.getOperand(0);
8202 SDValue ShOpHi = Op.getOperand(1);
8203 SDValue ShAmt = Op.getOperand(2);
8204 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
8205 DAG.getConstant(VTBits - 1, MVT::i8))
8206 : DAG.getConstant(0, VT);
8209 if (Op.getOpcode() == ISD::SHL_PARTS) {
8210 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
8211 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
8213 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
8214 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
8217 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
8218 DAG.getConstant(VTBits, MVT::i8));
8219 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
8220 AndNode, DAG.getConstant(0, MVT::i8));
8223 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8224 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
8225 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
8227 if (Op.getOpcode() == ISD::SHL_PARTS) {
8228 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8229 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8231 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
8232 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
8235 SDValue Ops[2] = { Lo, Hi };
8236 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
8239 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
8240 SelectionDAG &DAG) const {
8241 EVT SrcVT = Op.getOperand(0).getValueType();
8243 if (SrcVT.isVector())
8246 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
8247 "Unknown SINT_TO_FP to lower!");
8249 // These are really Legal; return the operand so the caller accepts it as
8251 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
8253 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
8254 Subtarget->is64Bit()) {
8259 unsigned Size = SrcVT.getSizeInBits()/8;
8260 MachineFunction &MF = DAG.getMachineFunction();
8261 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
8262 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8263 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8265 MachinePointerInfo::getFixedStack(SSFI),
8267 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
8270 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8272 SelectionDAG &DAG) const {
8276 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8278 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8280 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8282 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8284 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8285 MachineMemOperand *MMO;
8287 int SSFI = FI->getIndex();
8289 DAG.getMachineFunction()
8290 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8291 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8293 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8294 StackSlot = StackSlot.getOperand(1);
8296 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8297 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8299 Tys, Ops, array_lengthof(Ops),
8303 Chain = Result.getValue(1);
8304 SDValue InFlag = Result.getValue(2);
8306 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8307 // shouldn't be necessary except that RFP cannot be live across
8308 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8309 MachineFunction &MF = DAG.getMachineFunction();
8310 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8311 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8312 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8313 Tys = DAG.getVTList(MVT::Other);
8315 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8317 MachineMemOperand *MMO =
8318 DAG.getMachineFunction()
8319 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8320 MachineMemOperand::MOStore, SSFISize, SSFISize);
8322 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8323 Ops, array_lengthof(Ops),
8324 Op.getValueType(), MMO);
8325 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8326 MachinePointerInfo::getFixedStack(SSFI),
8327 false, false, false, 0);
8333 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8334 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8335 SelectionDAG &DAG) const {
8336 // This algorithm is not obvious. Here it is what we're trying to output:
8339 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8340 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8344 pshufd $0x4e, %xmm0, %xmm1
8350 LLVMContext *Context = DAG.getContext();
8352 // Build some magic constants.
8353 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8354 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8355 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8357 SmallVector<Constant*,2> CV1;
8359 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8360 APInt(64, 0x4330000000000000ULL))));
8362 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8363 APInt(64, 0x4530000000000000ULL))));
8364 Constant *C1 = ConstantVector::get(CV1);
8365 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8367 // Load the 64-bit value into an XMM register.
8368 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8370 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8371 MachinePointerInfo::getConstantPool(),
8372 false, false, false, 16);
8373 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8374 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8377 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8378 MachinePointerInfo::getConstantPool(),
8379 false, false, false, 16);
8380 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8381 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8384 if (Subtarget->hasSSE3()) {
8385 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8386 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8388 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8389 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8391 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8392 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8396 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8397 DAG.getIntPtrConstant(0));
8400 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8401 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8402 SelectionDAG &DAG) const {
8404 // FP constant to bias correct the final result.
8405 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8408 // Load the 32-bit value into an XMM register.
8409 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8412 // Zero out the upper parts of the register.
8413 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8415 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8416 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8417 DAG.getIntPtrConstant(0));
8419 // Or the load with the bias.
8420 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8421 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8422 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8424 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8425 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8426 MVT::v2f64, Bias)));
8427 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8428 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8429 DAG.getIntPtrConstant(0));
8431 // Subtract the bias.
8432 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8434 // Handle final rounding.
8435 EVT DestVT = Op.getValueType();
8437 if (DestVT.bitsLT(MVT::f64))
8438 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8439 DAG.getIntPtrConstant(0));
8440 if (DestVT.bitsGT(MVT::f64))
8441 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8443 // Handle final rounding.
8447 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8448 SelectionDAG &DAG) const {
8449 SDValue N0 = Op.getOperand(0);
8450 EVT SVT = N0.getValueType();
8453 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8454 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8455 "Custom UINT_TO_FP is not supported!");
8457 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8458 SVT.getVectorNumElements());
8459 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8460 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8463 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8464 SelectionDAG &DAG) const {
8465 SDValue N0 = Op.getOperand(0);
8468 if (Op.getValueType().isVector())
8469 return lowerUINT_TO_FP_vec(Op, DAG);
8471 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8472 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8473 // the optimization here.
8474 if (DAG.SignBitIsZero(N0))
8475 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8477 EVT SrcVT = N0.getValueType();
8478 EVT DstVT = Op.getValueType();
8479 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8480 return LowerUINT_TO_FP_i64(Op, DAG);
8481 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8482 return LowerUINT_TO_FP_i32(Op, DAG);
8483 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8486 // Make a 64-bit buffer, and use it to build an FILD.
8487 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8488 if (SrcVT == MVT::i32) {
8489 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8490 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8491 getPointerTy(), StackSlot, WordOff);
8492 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8493 StackSlot, MachinePointerInfo(),
8495 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8496 OffsetSlot, MachinePointerInfo(),
8498 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8502 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8503 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8504 StackSlot, MachinePointerInfo(),
8506 // For i64 source, we need to add the appropriate power of 2 if the input
8507 // was negative. This is the same as the optimization in
8508 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8509 // we must be careful to do the computation in x87 extended precision, not
8510 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8511 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8512 MachineMemOperand *MMO =
8513 DAG.getMachineFunction()
8514 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8515 MachineMemOperand::MOLoad, 8, 8);
8517 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8518 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8519 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8520 array_lengthof(Ops), MVT::i64, MMO);
8522 APInt FF(32, 0x5F800000ULL);
8524 // Check whether the sign bit is set.
8525 SDValue SignSet = DAG.getSetCC(dl,
8526 getSetCCResultType(*DAG.getContext(), MVT::i64),
8527 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8530 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8531 SDValue FudgePtr = DAG.getConstantPool(
8532 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8535 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8536 SDValue Zero = DAG.getIntPtrConstant(0);
8537 SDValue Four = DAG.getIntPtrConstant(4);
8538 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8540 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8542 // Load the value out, extending it from f32 to f80.
8543 // FIXME: Avoid the extend by constructing the right constant pool?
8544 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8545 FudgePtr, MachinePointerInfo::getConstantPool(),
8546 MVT::f32, false, false, 4);
8547 // Extend everything to 80 bits to force it to be done on x87.
8548 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8549 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8552 std::pair<SDValue,SDValue>
8553 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8554 bool IsSigned, bool IsReplace) const {
8557 EVT DstTy = Op.getValueType();
8559 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8560 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8564 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8565 DstTy.getSimpleVT() >= MVT::i16 &&
8566 "Unknown FP_TO_INT to lower!");
8568 // These are really Legal.
8569 if (DstTy == MVT::i32 &&
8570 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8571 return std::make_pair(SDValue(), SDValue());
8572 if (Subtarget->is64Bit() &&
8573 DstTy == MVT::i64 &&
8574 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8575 return std::make_pair(SDValue(), SDValue());
8577 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8578 // stack slot, or into the FTOL runtime function.
8579 MachineFunction &MF = DAG.getMachineFunction();
8580 unsigned MemSize = DstTy.getSizeInBits()/8;
8581 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8582 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8585 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8586 Opc = X86ISD::WIN_FTOL;
8588 switch (DstTy.getSimpleVT().SimpleTy) {
8589 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8590 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8591 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8592 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8595 SDValue Chain = DAG.getEntryNode();
8596 SDValue Value = Op.getOperand(0);
8597 EVT TheVT = Op.getOperand(0).getValueType();
8598 // FIXME This causes a redundant load/store if the SSE-class value is already
8599 // in memory, such as if it is on the callstack.
8600 if (isScalarFPTypeInSSEReg(TheVT)) {
8601 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8602 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8603 MachinePointerInfo::getFixedStack(SSFI),
8605 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8607 Chain, StackSlot, DAG.getValueType(TheVT)
8610 MachineMemOperand *MMO =
8611 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8612 MachineMemOperand::MOLoad, MemSize, MemSize);
8613 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8614 array_lengthof(Ops), DstTy, MMO);
8615 Chain = Value.getValue(1);
8616 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8617 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8620 MachineMemOperand *MMO =
8621 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8622 MachineMemOperand::MOStore, MemSize, MemSize);
8624 if (Opc != X86ISD::WIN_FTOL) {
8625 // Build the FP_TO_INT*_IN_MEM
8626 SDValue Ops[] = { Chain, Value, StackSlot };
8627 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8628 Ops, array_lengthof(Ops), DstTy,
8630 return std::make_pair(FIST, StackSlot);
8632 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8633 DAG.getVTList(MVT::Other, MVT::Glue),
8635 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8636 MVT::i32, ftol.getValue(1));
8637 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8638 MVT::i32, eax.getValue(2));
8639 SDValue Ops[] = { eax, edx };
8640 SDValue pair = IsReplace
8641 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8642 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8643 return std::make_pair(pair, SDValue());
8647 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8648 const X86Subtarget *Subtarget) {
8649 MVT VT = Op->getValueType(0).getSimpleVT();
8650 SDValue In = Op->getOperand(0);
8651 MVT InVT = In.getValueType().getSimpleVT();
8654 // Optimize vectors in AVX mode:
8657 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8658 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8659 // Concat upper and lower parts.
8662 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8663 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8664 // Concat upper and lower parts.
8667 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8668 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8671 if (Subtarget->hasInt256())
8672 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8674 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8675 SDValue Undef = DAG.getUNDEF(InVT);
8676 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8677 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8678 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8680 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8681 VT.getVectorNumElements()/2);
8683 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8684 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8686 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8689 SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
8690 SelectionDAG &DAG) const {
8691 if (Subtarget->hasFp256()) {
8692 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8699 SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
8700 SelectionDAG &DAG) const {
8702 MVT VT = Op.getValueType().getSimpleVT();
8703 SDValue In = Op.getOperand(0);
8704 MVT SVT = In.getValueType().getSimpleVT();
8706 if (Subtarget->hasFp256()) {
8707 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8712 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8713 VT.getVectorNumElements() != SVT.getVectorNumElements())
8716 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8718 // AVX2 has better support of integer extending.
8719 if (Subtarget->hasInt256())
8720 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8722 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8723 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8724 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8725 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8726 DAG.getUNDEF(MVT::v8i16),
8729 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8732 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8734 MVT VT = Op.getValueType().getSimpleVT();
8735 SDValue In = Op.getOperand(0);
8736 MVT SVT = In.getValueType().getSimpleVT();
8738 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8739 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8740 if (Subtarget->hasInt256()) {
8741 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8742 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8743 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8745 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8746 DAG.getIntPtrConstant(0));
8749 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8750 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8751 DAG.getIntPtrConstant(0));
8752 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8753 DAG.getIntPtrConstant(2));
8755 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8756 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8759 static const int ShufMask1[] = {0, 2, 0, 0};
8760 SDValue Undef = DAG.getUNDEF(VT);
8761 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8762 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8764 // The MOVLHPS mask:
8765 static const int ShufMask2[] = {0, 1, 4, 5};
8766 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8769 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8770 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8771 if (Subtarget->hasInt256()) {
8772 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8774 SmallVector<SDValue,32> pshufbMask;
8775 for (unsigned i = 0; i < 2; ++i) {
8776 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8777 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8778 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8779 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8780 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8781 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8782 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8783 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8784 for (unsigned j = 0; j < 8; ++j)
8785 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8787 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8788 &pshufbMask[0], 32);
8789 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8790 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8792 static const int ShufMask[] = {0, 2, -1, -1};
8793 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8795 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8796 DAG.getIntPtrConstant(0));
8797 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8800 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8801 DAG.getIntPtrConstant(0));
8803 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8804 DAG.getIntPtrConstant(4));
8806 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8807 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8810 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8811 -1, -1, -1, -1, -1, -1, -1, -1};
8813 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8814 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8815 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8817 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8818 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8820 // The MOVLHPS Mask:
8821 static const int ShufMask2[] = {0, 1, 4, 5};
8822 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8823 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8826 // Handle truncation of V256 to V128 using shuffles.
8827 if (!VT.is128BitVector() || !SVT.is256BitVector())
8830 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8832 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8834 unsigned NumElems = VT.getVectorNumElements();
8835 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8838 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8839 // Prepare truncation shuffle mask
8840 for (unsigned i = 0; i != NumElems; ++i)
8842 SDValue V = DAG.getVectorShuffle(NVT, DL,
8843 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8844 DAG.getUNDEF(NVT), &MaskVec[0]);
8845 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8846 DAG.getIntPtrConstant(0));
8849 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8850 SelectionDAG &DAG) const {
8851 MVT VT = Op.getValueType().getSimpleVT();
8852 if (VT.isVector()) {
8853 if (VT == MVT::v8i16)
8854 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT,
8855 DAG.getNode(ISD::FP_TO_SINT, SDLoc(Op),
8856 MVT::v8i32, Op.getOperand(0)));
8860 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8861 /*IsSigned=*/ true, /*IsReplace=*/ false);
8862 SDValue FIST = Vals.first, StackSlot = Vals.second;
8863 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8864 if (FIST.getNode() == 0) return Op;
8866 if (StackSlot.getNode())
8868 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
8869 FIST, StackSlot, MachinePointerInfo(),
8870 false, false, false, 0);
8872 // The node is the result.
8876 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8877 SelectionDAG &DAG) const {
8878 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8879 /*IsSigned=*/ false, /*IsReplace=*/ false);
8880 SDValue FIST = Vals.first, StackSlot = Vals.second;
8881 assert(FIST.getNode() && "Unexpected failure");
8883 if (StackSlot.getNode())
8885 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
8886 FIST, StackSlot, MachinePointerInfo(),
8887 false, false, false, 0);
8889 // The node is the result.
8893 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
8895 MVT VT = Op.getValueType().getSimpleVT();
8896 SDValue In = Op.getOperand(0);
8897 MVT SVT = In.getValueType().getSimpleVT();
8899 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8901 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8902 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8903 In, DAG.getUNDEF(SVT)));
8906 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8907 LLVMContext *Context = DAG.getContext();
8909 MVT VT = Op.getValueType().getSimpleVT();
8911 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8912 if (VT.isVector()) {
8913 EltVT = VT.getVectorElementType();
8914 NumElts = VT.getVectorNumElements();
8917 if (EltVT == MVT::f64)
8918 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8919 APInt(64, ~(1ULL << 63))));
8921 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8922 APInt(32, ~(1U << 31))));
8923 C = ConstantVector::getSplat(NumElts, C);
8924 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8925 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8926 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8927 MachinePointerInfo::getConstantPool(),
8928 false, false, false, Alignment);
8929 if (VT.isVector()) {
8930 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8931 return DAG.getNode(ISD::BITCAST, dl, VT,
8932 DAG.getNode(ISD::AND, dl, ANDVT,
8933 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8935 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8937 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8940 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8941 LLVMContext *Context = DAG.getContext();
8943 MVT VT = Op.getValueType().getSimpleVT();
8945 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8946 if (VT.isVector()) {
8947 EltVT = VT.getVectorElementType();
8948 NumElts = VT.getVectorNumElements();
8951 if (EltVT == MVT::f64)
8952 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8953 APInt(64, 1ULL << 63)));
8955 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8956 APInt(32, 1U << 31)));
8957 C = ConstantVector::getSplat(NumElts, C);
8958 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8959 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8960 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8961 MachinePointerInfo::getConstantPool(),
8962 false, false, false, Alignment);
8963 if (VT.isVector()) {
8964 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8965 return DAG.getNode(ISD::BITCAST, dl, VT,
8966 DAG.getNode(ISD::XOR, dl, XORVT,
8967 DAG.getNode(ISD::BITCAST, dl, XORVT,
8969 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8972 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8975 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8976 LLVMContext *Context = DAG.getContext();
8977 SDValue Op0 = Op.getOperand(0);
8978 SDValue Op1 = Op.getOperand(1);
8980 MVT VT = Op.getValueType().getSimpleVT();
8981 MVT SrcVT = Op1.getValueType().getSimpleVT();
8983 // If second operand is smaller, extend it first.
8984 if (SrcVT.bitsLT(VT)) {
8985 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8988 // And if it is bigger, shrink it first.
8989 if (SrcVT.bitsGT(VT)) {
8990 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8994 // At this point the operands and the result should have the same
8995 // type, and that won't be f80 since that is not custom lowered.
8997 // First get the sign bit of second operand.
8998 SmallVector<Constant*,4> CV;
8999 if (SrcVT == MVT::f64) {
9000 const fltSemantics &Sem = APFloat::IEEEdouble;
9001 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
9002 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9004 const fltSemantics &Sem = APFloat::IEEEsingle;
9005 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
9006 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9007 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9008 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9010 Constant *C = ConstantVector::get(CV);
9011 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9012 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
9013 MachinePointerInfo::getConstantPool(),
9014 false, false, false, 16);
9015 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
9017 // Shift sign bit right or left if the two operands have different types.
9018 if (SrcVT.bitsGT(VT)) {
9019 // Op0 is MVT::f32, Op1 is MVT::f64.
9020 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
9021 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
9022 DAG.getConstant(32, MVT::i32));
9023 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
9024 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
9025 DAG.getIntPtrConstant(0));
9028 // Clear first operand sign bit.
9030 if (VT == MVT::f64) {
9031 const fltSemantics &Sem = APFloat::IEEEdouble;
9032 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9033 APInt(64, ~(1ULL << 63)))));
9034 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
9036 const fltSemantics &Sem = APFloat::IEEEsingle;
9037 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
9038 APInt(32, ~(1U << 31)))));
9039 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9040 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9041 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
9043 C = ConstantVector::get(CV);
9044 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9045 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9046 MachinePointerInfo::getConstantPool(),
9047 false, false, false, 16);
9048 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
9050 // Or the value with the sign bit.
9051 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
9054 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
9055 SDValue N0 = Op.getOperand(0);
9057 MVT VT = Op.getValueType().getSimpleVT();
9059 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
9060 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
9061 DAG.getConstant(1, VT));
9062 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
9065 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
9067 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op,
9068 SelectionDAG &DAG) const {
9069 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
9071 if (!Subtarget->hasSSE41())
9074 if (!Op->hasOneUse())
9077 SDNode *N = Op.getNode();
9080 SmallVector<SDValue, 8> Opnds;
9081 DenseMap<SDValue, unsigned> VecInMap;
9082 EVT VT = MVT::Other;
9084 // Recognize a special case where a vector is casted into wide integer to
9086 Opnds.push_back(N->getOperand(0));
9087 Opnds.push_back(N->getOperand(1));
9089 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
9090 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
9091 // BFS traverse all OR'd operands.
9092 if (I->getOpcode() == ISD::OR) {
9093 Opnds.push_back(I->getOperand(0));
9094 Opnds.push_back(I->getOperand(1));
9095 // Re-evaluate the number of nodes to be traversed.
9096 e += 2; // 2 more nodes (LHS and RHS) are pushed.
9100 // Quit if a non-EXTRACT_VECTOR_ELT
9101 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9104 // Quit if without a constant index.
9105 SDValue Idx = I->getOperand(1);
9106 if (!isa<ConstantSDNode>(Idx))
9109 SDValue ExtractedFromVec = I->getOperand(0);
9110 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
9111 if (M == VecInMap.end()) {
9112 VT = ExtractedFromVec.getValueType();
9113 // Quit if not 128/256-bit vector.
9114 if (!VT.is128BitVector() && !VT.is256BitVector())
9116 // Quit if not the same type.
9117 if (VecInMap.begin() != VecInMap.end() &&
9118 VT != VecInMap.begin()->first.getValueType())
9120 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
9122 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
9125 assert((VT.is128BitVector() || VT.is256BitVector()) &&
9126 "Not extracted from 128-/256-bit vector.");
9128 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
9129 SmallVector<SDValue, 8> VecIns;
9131 for (DenseMap<SDValue, unsigned>::const_iterator
9132 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
9133 // Quit if not all elements are used.
9134 if (I->second != FullMask)
9136 VecIns.push_back(I->first);
9139 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
9141 // Cast all vectors into TestVT for PTEST.
9142 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
9143 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
9145 // If more than one full vectors are evaluated, OR them first before PTEST.
9146 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
9147 // Each iteration will OR 2 nodes and append the result until there is only
9148 // 1 node left, i.e. the final OR'd value of all vectors.
9149 SDValue LHS = VecIns[Slot];
9150 SDValue RHS = VecIns[Slot + 1];
9151 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
9154 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
9155 VecIns.back(), VecIns.back());
9158 /// Emit nodes that will be selected as "test Op0,Op0", or something
9160 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
9161 SelectionDAG &DAG) const {
9164 // CF and OF aren't always set the way we want. Determine which
9165 // of these we need.
9166 bool NeedCF = false;
9167 bool NeedOF = false;
9170 case X86::COND_A: case X86::COND_AE:
9171 case X86::COND_B: case X86::COND_BE:
9174 case X86::COND_G: case X86::COND_GE:
9175 case X86::COND_L: case X86::COND_LE:
9176 case X86::COND_O: case X86::COND_NO:
9181 // See if we can use the EFLAGS value from the operand instead of
9182 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
9183 // we prove that the arithmetic won't overflow, we can't use OF or CF.
9184 if (Op.getResNo() != 0 || NeedOF || NeedCF)
9185 // Emit a CMP with 0, which is the TEST pattern.
9186 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9187 DAG.getConstant(0, Op.getValueType()));
9189 unsigned Opcode = 0;
9190 unsigned NumOperands = 0;
9192 // Truncate operations may prevent the merge of the SETCC instruction
9193 // and the arithmetic intruction before it. Attempt to truncate the operands
9194 // of the arithmetic instruction and use a reduced bit-width instruction.
9195 bool NeedTruncation = false;
9196 SDValue ArithOp = Op;
9197 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
9198 SDValue Arith = Op->getOperand(0);
9199 // Both the trunc and the arithmetic op need to have one user each.
9200 if (Arith->hasOneUse())
9201 switch (Arith.getOpcode()) {
9208 NeedTruncation = true;
9214 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
9215 // which may be the result of a CAST. We use the variable 'Op', which is the
9216 // non-casted variable when we check for possible users.
9217 switch (ArithOp.getOpcode()) {
9219 // Due to an isel shortcoming, be conservative if this add is likely to be
9220 // selected as part of a load-modify-store instruction. When the root node
9221 // in a match is a store, isel doesn't know how to remap non-chain non-flag
9222 // uses of other nodes in the match, such as the ADD in this case. This
9223 // leads to the ADD being left around and reselected, with the result being
9224 // two adds in the output. Alas, even if none our users are stores, that
9225 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
9226 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
9227 // climbing the DAG back to the root, and it doesn't seem to be worth the
9229 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9230 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9231 if (UI->getOpcode() != ISD::CopyToReg &&
9232 UI->getOpcode() != ISD::SETCC &&
9233 UI->getOpcode() != ISD::STORE)
9236 if (ConstantSDNode *C =
9237 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
9238 // An add of one will be selected as an INC.
9239 if (C->getAPIntValue() == 1) {
9240 Opcode = X86ISD::INC;
9245 // An add of negative one (subtract of one) will be selected as a DEC.
9246 if (C->getAPIntValue().isAllOnesValue()) {
9247 Opcode = X86ISD::DEC;
9253 // Otherwise use a regular EFLAGS-setting add.
9254 Opcode = X86ISD::ADD;
9258 // If the primary and result isn't used, don't bother using X86ISD::AND,
9259 // because a TEST instruction will be better.
9260 bool NonFlagUse = false;
9261 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9262 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
9264 unsigned UOpNo = UI.getOperandNo();
9265 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
9266 // Look pass truncate.
9267 UOpNo = User->use_begin().getOperandNo();
9268 User = *User->use_begin();
9271 if (User->getOpcode() != ISD::BRCOND &&
9272 User->getOpcode() != ISD::SETCC &&
9273 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9286 // Due to the ISEL shortcoming noted above, be conservative if this op is
9287 // likely to be selected as part of a load-modify-store instruction.
9288 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9289 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9290 if (UI->getOpcode() == ISD::STORE)
9293 // Otherwise use a regular EFLAGS-setting instruction.
9294 switch (ArithOp.getOpcode()) {
9295 default: llvm_unreachable("unexpected operator!");
9296 case ISD::SUB: Opcode = X86ISD::SUB; break;
9297 case ISD::XOR: Opcode = X86ISD::XOR; break;
9298 case ISD::AND: Opcode = X86ISD::AND; break;
9300 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9301 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
9302 if (EFLAGS.getNode())
9305 Opcode = X86ISD::OR;
9319 return SDValue(Op.getNode(), 1);
9325 // If we found that truncation is beneficial, perform the truncation and
9327 if (NeedTruncation) {
9328 EVT VT = Op.getValueType();
9329 SDValue WideVal = Op->getOperand(0);
9330 EVT WideVT = WideVal.getValueType();
9331 unsigned ConvertedOp = 0;
9332 // Use a target machine opcode to prevent further DAGCombine
9333 // optimizations that may separate the arithmetic operations
9334 // from the setcc node.
9335 switch (WideVal.getOpcode()) {
9337 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9338 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9339 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9340 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9341 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9345 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9346 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9347 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9348 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9349 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9355 // Emit a CMP with 0, which is the TEST pattern.
9356 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9357 DAG.getConstant(0, Op.getValueType()));
9359 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9360 SmallVector<SDValue, 4> Ops;
9361 for (unsigned i = 0; i != NumOperands; ++i)
9362 Ops.push_back(Op.getOperand(i));
9364 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9365 DAG.ReplaceAllUsesWith(Op, New);
9366 return SDValue(New.getNode(), 1);
9369 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9371 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9372 SelectionDAG &DAG) const {
9373 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9374 if (C->getAPIntValue() == 0)
9375 return EmitTest(Op0, X86CC, DAG);
9378 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9379 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9380 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9381 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9382 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9384 return SDValue(Sub.getNode(), 1);
9386 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9389 /// Convert a comparison if required by the subtarget.
9390 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9391 SelectionDAG &DAG) const {
9392 // If the subtarget does not support the FUCOMI instruction, floating-point
9393 // comparisons have to be converted.
9394 if (Subtarget->hasCMov() ||
9395 Cmp.getOpcode() != X86ISD::CMP ||
9396 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9397 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9400 // The instruction selector will select an FUCOM instruction instead of
9401 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9402 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9403 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9405 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9406 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9407 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9408 DAG.getConstant(8, MVT::i8));
9409 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9410 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9413 static bool isAllOnes(SDValue V) {
9414 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9415 return C && C->isAllOnesValue();
9418 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9419 /// if it's possible.
9420 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9421 SDLoc dl, SelectionDAG &DAG) const {
9422 SDValue Op0 = And.getOperand(0);
9423 SDValue Op1 = And.getOperand(1);
9424 if (Op0.getOpcode() == ISD::TRUNCATE)
9425 Op0 = Op0.getOperand(0);
9426 if (Op1.getOpcode() == ISD::TRUNCATE)
9427 Op1 = Op1.getOperand(0);
9430 if (Op1.getOpcode() == ISD::SHL)
9431 std::swap(Op0, Op1);
9432 if (Op0.getOpcode() == ISD::SHL) {
9433 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9434 if (And00C->getZExtValue() == 1) {
9435 // If we looked past a truncate, check that it's only truncating away
9437 unsigned BitWidth = Op0.getValueSizeInBits();
9438 unsigned AndBitWidth = And.getValueSizeInBits();
9439 if (BitWidth > AndBitWidth) {
9441 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9442 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9446 RHS = Op0.getOperand(1);
9448 } else if (Op1.getOpcode() == ISD::Constant) {
9449 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9450 uint64_t AndRHSVal = AndRHS->getZExtValue();
9451 SDValue AndLHS = Op0;
9453 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9454 LHS = AndLHS.getOperand(0);
9455 RHS = AndLHS.getOperand(1);
9458 // Use BT if the immediate can't be encoded in a TEST instruction.
9459 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9461 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9465 if (LHS.getNode()) {
9466 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9467 // instruction. Since the shift amount is in-range-or-undefined, we know
9468 // that doing a bittest on the i32 value is ok. We extend to i32 because
9469 // the encoding for the i16 version is larger than the i32 version.
9470 // Also promote i16 to i32 for performance / code size reason.
9471 if (LHS.getValueType() == MVT::i8 ||
9472 LHS.getValueType() == MVT::i16)
9473 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9475 // If the operand types disagree, extend the shift amount to match. Since
9476 // BT ignores high bits (like shifts) we can use anyextend.
9477 if (LHS.getValueType() != RHS.getValueType())
9478 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9480 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9481 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9482 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9483 DAG.getConstant(Cond, MVT::i8), BT);
9489 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9490 // ones, and then concatenate the result back.
9491 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9492 MVT VT = Op.getValueType().getSimpleVT();
9494 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9495 "Unsupported value type for operation");
9497 unsigned NumElems = VT.getVectorNumElements();
9499 SDValue CC = Op.getOperand(2);
9501 // Extract the LHS vectors
9502 SDValue LHS = Op.getOperand(0);
9503 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9504 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9506 // Extract the RHS vectors
9507 SDValue RHS = Op.getOperand(1);
9508 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9509 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9511 // Issue the operation on the smaller types and concatenate the result back
9512 MVT EltVT = VT.getVectorElementType();
9513 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9514 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9515 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9516 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9519 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9520 SelectionDAG &DAG) {
9522 SDValue Op0 = Op.getOperand(0);
9523 SDValue Op1 = Op.getOperand(1);
9524 SDValue CC = Op.getOperand(2);
9525 MVT VT = Op.getValueType().getSimpleVT();
9526 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9527 bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint();
9532 MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
9533 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9539 // SSE Condition code mapping:
9548 switch (SetCCOpcode) {
9549 default: llvm_unreachable("Unexpected SETCC condition");
9551 case ISD::SETEQ: SSECC = 0; break;
9553 case ISD::SETGT: Swap = true; // Fallthrough
9555 case ISD::SETOLT: SSECC = 1; break;
9557 case ISD::SETGE: Swap = true; // Fallthrough
9559 case ISD::SETOLE: SSECC = 2; break;
9560 case ISD::SETUO: SSECC = 3; break;
9562 case ISD::SETNE: SSECC = 4; break;
9563 case ISD::SETULE: Swap = true; // Fallthrough
9564 case ISD::SETUGE: SSECC = 5; break;
9565 case ISD::SETULT: Swap = true; // Fallthrough
9566 case ISD::SETUGT: SSECC = 6; break;
9567 case ISD::SETO: SSECC = 7; break;
9569 case ISD::SETONE: SSECC = 8; break;
9572 std::swap(Op0, Op1);
9574 // In the two special cases we can't handle, emit two comparisons.
9577 unsigned CombineOpc;
9578 if (SetCCOpcode == ISD::SETUEQ) {
9579 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9581 assert(SetCCOpcode == ISD::SETONE);
9582 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9585 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9586 DAG.getConstant(CC0, MVT::i8));
9587 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9588 DAG.getConstant(CC1, MVT::i8));
9589 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9591 // Handle all other FP comparisons here.
9592 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9593 DAG.getConstant(SSECC, MVT::i8));
9596 // Break 256-bit integer vector compare into smaller ones.
9597 if (VT.is256BitVector() && !Subtarget->hasInt256())
9598 return Lower256IntVSETCC(Op, DAG);
9600 // We are handling one of the integer comparisons here. Since SSE only has
9601 // GT and EQ comparisons for integer, swapping operands and multiple
9602 // operations may be required for some comparisons.
9604 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
9606 switch (SetCCOpcode) {
9607 default: llvm_unreachable("Unexpected SETCC condition");
9608 case ISD::SETNE: Invert = true;
9609 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9610 case ISD::SETLT: Swap = true;
9611 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9612 case ISD::SETGE: Swap = true;
9613 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9614 case ISD::SETULT: Swap = true;
9615 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9616 case ISD::SETUGE: Swap = true;
9617 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9620 // Special case: Use min/max operations for SETULE/SETUGE
9621 MVT VET = VT.getVectorElementType();
9623 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
9624 || (Subtarget->hasSSE2() && (VET == MVT::i8));
9627 switch (SetCCOpcode) {
9629 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
9630 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
9633 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
9637 std::swap(Op0, Op1);
9639 // Check that the operation in question is available (most are plain SSE2,
9640 // but PCMPGTQ and PCMPEQQ have different requirements).
9641 if (VT == MVT::v2i64) {
9642 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9643 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9645 // First cast everything to the right type.
9646 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9647 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9649 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9650 // bits of the inputs before performing those operations. The lower
9651 // compare is always unsigned.
9654 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9656 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
9657 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
9658 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
9659 Sign, Zero, Sign, Zero);
9661 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9662 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9664 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9665 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9666 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9668 // Create masks for only the low parts/high parts of the 64 bit integers.
9669 static const int MaskHi[] = { 1, 1, 3, 3 };
9670 static const int MaskLo[] = { 0, 0, 2, 2 };
9671 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9672 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9673 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9675 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9676 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9679 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9681 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9684 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9685 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9686 // pcmpeqd + pshufd + pand.
9687 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9689 // First cast everything to the right type.
9690 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9691 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9694 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9696 // Make sure the lower and upper halves are both all-ones.
9697 static const int Mask[] = { 1, 0, 3, 2 };
9698 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9699 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9702 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9704 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9708 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9709 // bits of the inputs before performing those operations.
9711 EVT EltVT = VT.getVectorElementType();
9712 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
9713 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
9714 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
9717 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9719 // If the logical-not of the result is required, perform that now.
9721 Result = DAG.getNOT(dl, Result, VT);
9724 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
9729 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9731 MVT VT = Op.getValueType().getSimpleVT();
9733 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9735 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9736 SDValue Op0 = Op.getOperand(0);
9737 SDValue Op1 = Op.getOperand(1);
9739 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9741 // Optimize to BT if possible.
9742 // Lower (X & (1 << N)) == 0 to BT(X, N).
9743 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9744 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9745 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9746 Op1.getOpcode() == ISD::Constant &&
9747 cast<ConstantSDNode>(Op1)->isNullValue() &&
9748 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9749 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9750 if (NewSetCC.getNode())
9754 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9756 if (Op1.getOpcode() == ISD::Constant &&
9757 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9758 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9759 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9761 // If the input is a setcc, then reuse the input setcc or use a new one with
9762 // the inverted condition.
9763 if (Op0.getOpcode() == X86ISD::SETCC) {
9764 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9765 bool Invert = (CC == ISD::SETNE) ^
9766 cast<ConstantSDNode>(Op1)->isNullValue();
9767 if (!Invert) return Op0;
9769 CCode = X86::GetOppositeBranchCondition(CCode);
9770 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9771 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9775 bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint();
9776 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9777 if (X86CC == X86::COND_INVALID)
9780 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9781 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9782 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9783 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9786 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9787 static bool isX86LogicalCmp(SDValue Op) {
9788 unsigned Opc = Op.getNode()->getOpcode();
9789 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9790 Opc == X86ISD::SAHF)
9792 if (Op.getResNo() == 1 &&
9793 (Opc == X86ISD::ADD ||
9794 Opc == X86ISD::SUB ||
9795 Opc == X86ISD::ADC ||
9796 Opc == X86ISD::SBB ||
9797 Opc == X86ISD::SMUL ||
9798 Opc == X86ISD::UMUL ||
9799 Opc == X86ISD::INC ||
9800 Opc == X86ISD::DEC ||
9801 Opc == X86ISD::OR ||
9802 Opc == X86ISD::XOR ||
9803 Opc == X86ISD::AND))
9806 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9812 static bool isZero(SDValue V) {
9813 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9814 return C && C->isNullValue();
9817 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9818 if (V.getOpcode() != ISD::TRUNCATE)
9821 SDValue VOp0 = V.getOperand(0);
9822 unsigned InBits = VOp0.getValueSizeInBits();
9823 unsigned Bits = V.getValueSizeInBits();
9824 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9827 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9828 bool addTest = true;
9829 SDValue Cond = Op.getOperand(0);
9830 SDValue Op1 = Op.getOperand(1);
9831 SDValue Op2 = Op.getOperand(2);
9835 if (Cond.getOpcode() == ISD::SETCC) {
9836 SDValue NewCond = LowerSETCC(Cond, DAG);
9837 if (NewCond.getNode())
9841 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9842 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9843 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9844 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9845 if (Cond.getOpcode() == X86ISD::SETCC &&
9846 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9847 isZero(Cond.getOperand(1).getOperand(1))) {
9848 SDValue Cmp = Cond.getOperand(1);
9850 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9852 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9853 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9854 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9856 SDValue CmpOp0 = Cmp.getOperand(0);
9857 // Apply further optimizations for special cases
9858 // (select (x != 0), -1, 0) -> neg & sbb
9859 // (select (x == 0), 0, -1) -> neg & sbb
9860 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9861 if (YC->isNullValue() &&
9862 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9863 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9864 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9865 DAG.getConstant(0, CmpOp0.getValueType()),
9867 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9868 DAG.getConstant(X86::COND_B, MVT::i8),
9869 SDValue(Neg.getNode(), 1));
9873 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9874 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9875 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9877 SDValue Res = // Res = 0 or -1.
9878 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9879 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9881 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9882 Res = DAG.getNOT(DL, Res, Res.getValueType());
9884 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9885 if (N2C == 0 || !N2C->isNullValue())
9886 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9891 // Look past (and (setcc_carry (cmp ...)), 1).
9892 if (Cond.getOpcode() == ISD::AND &&
9893 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9894 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9895 if (C && C->getAPIntValue() == 1)
9896 Cond = Cond.getOperand(0);
9899 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9900 // setting operand in place of the X86ISD::SETCC.
9901 unsigned CondOpcode = Cond.getOpcode();
9902 if (CondOpcode == X86ISD::SETCC ||
9903 CondOpcode == X86ISD::SETCC_CARRY) {
9904 CC = Cond.getOperand(0);
9906 SDValue Cmp = Cond.getOperand(1);
9907 unsigned Opc = Cmp.getOpcode();
9908 MVT VT = Op.getValueType().getSimpleVT();
9910 bool IllegalFPCMov = false;
9911 if (VT.isFloatingPoint() && !VT.isVector() &&
9912 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9913 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9915 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9916 Opc == X86ISD::BT) { // FIXME
9920 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9921 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9922 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9923 Cond.getOperand(0).getValueType() != MVT::i8)) {
9924 SDValue LHS = Cond.getOperand(0);
9925 SDValue RHS = Cond.getOperand(1);
9929 switch (CondOpcode) {
9930 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9931 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9932 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9933 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9934 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9935 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9936 default: llvm_unreachable("unexpected overflowing operator");
9938 if (CondOpcode == ISD::UMULO)
9939 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9942 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9944 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9946 if (CondOpcode == ISD::UMULO)
9947 Cond = X86Op.getValue(2);
9949 Cond = X86Op.getValue(1);
9951 CC = DAG.getConstant(X86Cond, MVT::i8);
9956 // Look pass the truncate if the high bits are known zero.
9957 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9958 Cond = Cond.getOperand(0);
9960 // We know the result of AND is compared against zero. Try to match
9962 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9963 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9964 if (NewSetCC.getNode()) {
9965 CC = NewSetCC.getOperand(0);
9966 Cond = NewSetCC.getOperand(1);
9973 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9974 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9977 // a < b ? -1 : 0 -> RES = ~setcc_carry
9978 // a < b ? 0 : -1 -> RES = setcc_carry
9979 // a >= b ? -1 : 0 -> RES = setcc_carry
9980 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9981 if (Cond.getOpcode() == X86ISD::SUB) {
9982 Cond = ConvertCmpIfNecessary(Cond, DAG);
9983 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9985 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9986 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9987 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9988 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9989 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9990 return DAG.getNOT(DL, Res, Res.getValueType());
9995 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9996 // widen the cmov and push the truncate through. This avoids introducing a new
9997 // branch during isel and doesn't add any extensions.
9998 if (Op.getValueType() == MVT::i8 &&
9999 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
10000 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
10001 if (T1.getValueType() == T2.getValueType() &&
10002 // Blacklist CopyFromReg to avoid partial register stalls.
10003 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
10004 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
10005 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
10006 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
10010 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
10011 // condition is true.
10012 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
10013 SDValue Ops[] = { Op2, Op1, CC, Cond };
10014 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
10017 SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
10018 SelectionDAG &DAG) const {
10019 MVT VT = Op->getValueType(0).getSimpleVT();
10020 SDValue In = Op->getOperand(0);
10021 MVT InVT = In.getValueType().getSimpleVT();
10024 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
10025 (VT != MVT::v8i32 || InVT != MVT::v8i16))
10028 if (Subtarget->hasInt256())
10029 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
10031 // Optimize vectors in AVX mode
10032 // Sign extend v8i16 to v8i32 and
10035 // Divide input vector into two parts
10036 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
10037 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
10038 // concat the vectors to original VT
10040 unsigned NumElems = InVT.getVectorNumElements();
10041 SDValue Undef = DAG.getUNDEF(InVT);
10043 SmallVector<int,8> ShufMask1(NumElems, -1);
10044 for (unsigned i = 0; i != NumElems/2; ++i)
10047 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
10049 SmallVector<int,8> ShufMask2(NumElems, -1);
10050 for (unsigned i = 0; i != NumElems/2; ++i)
10051 ShufMask2[i] = i + NumElems/2;
10053 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
10055 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
10056 VT.getVectorNumElements()/2);
10058 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
10059 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
10061 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
10064 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
10065 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
10066 // from the AND / OR.
10067 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
10068 Opc = Op.getOpcode();
10069 if (Opc != ISD::OR && Opc != ISD::AND)
10071 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10072 Op.getOperand(0).hasOneUse() &&
10073 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
10074 Op.getOperand(1).hasOneUse());
10077 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
10078 // 1 and that the SETCC node has a single use.
10079 static bool isXor1OfSetCC(SDValue Op) {
10080 if (Op.getOpcode() != ISD::XOR)
10082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10083 if (N1C && N1C->getAPIntValue() == 1) {
10084 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
10085 Op.getOperand(0).hasOneUse();
10090 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
10091 bool addTest = true;
10092 SDValue Chain = Op.getOperand(0);
10093 SDValue Cond = Op.getOperand(1);
10094 SDValue Dest = Op.getOperand(2);
10097 bool Inverted = false;
10099 if (Cond.getOpcode() == ISD::SETCC) {
10100 // Check for setcc([su]{add,sub,mul}o == 0).
10101 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
10102 isa<ConstantSDNode>(Cond.getOperand(1)) &&
10103 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
10104 Cond.getOperand(0).getResNo() == 1 &&
10105 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
10106 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
10107 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
10108 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
10109 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
10110 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
10112 Cond = Cond.getOperand(0);
10114 SDValue NewCond = LowerSETCC(Cond, DAG);
10115 if (NewCond.getNode())
10120 // FIXME: LowerXALUO doesn't handle these!!
10121 else if (Cond.getOpcode() == X86ISD::ADD ||
10122 Cond.getOpcode() == X86ISD::SUB ||
10123 Cond.getOpcode() == X86ISD::SMUL ||
10124 Cond.getOpcode() == X86ISD::UMUL)
10125 Cond = LowerXALUO(Cond, DAG);
10128 // Look pass (and (setcc_carry (cmp ...)), 1).
10129 if (Cond.getOpcode() == ISD::AND &&
10130 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
10131 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
10132 if (C && C->getAPIntValue() == 1)
10133 Cond = Cond.getOperand(0);
10136 // If condition flag is set by a X86ISD::CMP, then use it as the condition
10137 // setting operand in place of the X86ISD::SETCC.
10138 unsigned CondOpcode = Cond.getOpcode();
10139 if (CondOpcode == X86ISD::SETCC ||
10140 CondOpcode == X86ISD::SETCC_CARRY) {
10141 CC = Cond.getOperand(0);
10143 SDValue Cmp = Cond.getOperand(1);
10144 unsigned Opc = Cmp.getOpcode();
10145 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
10146 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
10150 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
10154 // These can only come from an arithmetic instruction with overflow,
10155 // e.g. SADDO, UADDO.
10156 Cond = Cond.getNode()->getOperand(1);
10162 CondOpcode = Cond.getOpcode();
10163 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
10164 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
10165 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
10166 Cond.getOperand(0).getValueType() != MVT::i8)) {
10167 SDValue LHS = Cond.getOperand(0);
10168 SDValue RHS = Cond.getOperand(1);
10169 unsigned X86Opcode;
10172 switch (CondOpcode) {
10173 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
10174 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
10175 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
10176 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
10177 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
10178 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
10179 default: llvm_unreachable("unexpected overflowing operator");
10182 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
10183 if (CondOpcode == ISD::UMULO)
10184 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
10187 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
10189 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
10191 if (CondOpcode == ISD::UMULO)
10192 Cond = X86Op.getValue(2);
10194 Cond = X86Op.getValue(1);
10196 CC = DAG.getConstant(X86Cond, MVT::i8);
10200 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
10201 SDValue Cmp = Cond.getOperand(0).getOperand(1);
10202 if (CondOpc == ISD::OR) {
10203 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
10204 // two branches instead of an explicit OR instruction with a
10206 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10207 isX86LogicalCmp(Cmp)) {
10208 CC = Cond.getOperand(0).getOperand(0);
10209 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10210 Chain, Dest, CC, Cmp);
10211 CC = Cond.getOperand(1).getOperand(0);
10215 } else { // ISD::AND
10216 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
10217 // two branches instead of an explicit AND instruction with a
10218 // separate test. However, we only do this if this block doesn't
10219 // have a fall-through edge, because this requires an explicit
10220 // jmp when the condition is false.
10221 if (Cmp == Cond.getOperand(1).getOperand(1) &&
10222 isX86LogicalCmp(Cmp) &&
10223 Op.getNode()->hasOneUse()) {
10224 X86::CondCode CCode =
10225 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10226 CCode = X86::GetOppositeBranchCondition(CCode);
10227 CC = DAG.getConstant(CCode, MVT::i8);
10228 SDNode *User = *Op.getNode()->use_begin();
10229 // Look for an unconditional branch following this conditional branch.
10230 // We need this because we need to reverse the successors in order
10231 // to implement FCMP_OEQ.
10232 if (User->getOpcode() == ISD::BR) {
10233 SDValue FalseBB = User->getOperand(1);
10235 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10236 assert(NewBR == User);
10240 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10241 Chain, Dest, CC, Cmp);
10242 X86::CondCode CCode =
10243 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
10244 CCode = X86::GetOppositeBranchCondition(CCode);
10245 CC = DAG.getConstant(CCode, MVT::i8);
10251 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
10252 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
10253 // It should be transformed during dag combiner except when the condition
10254 // is set by a arithmetics with overflow node.
10255 X86::CondCode CCode =
10256 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
10257 CCode = X86::GetOppositeBranchCondition(CCode);
10258 CC = DAG.getConstant(CCode, MVT::i8);
10259 Cond = Cond.getOperand(0).getOperand(1);
10261 } else if (Cond.getOpcode() == ISD::SETCC &&
10262 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
10263 // For FCMP_OEQ, we can emit
10264 // two branches instead of an explicit AND instruction with a
10265 // separate test. However, we only do this if this block doesn't
10266 // have a fall-through edge, because this requires an explicit
10267 // jmp when the condition is false.
10268 if (Op.getNode()->hasOneUse()) {
10269 SDNode *User = *Op.getNode()->use_begin();
10270 // Look for an unconditional branch following this conditional branch.
10271 // We need this because we need to reverse the successors in order
10272 // to implement FCMP_OEQ.
10273 if (User->getOpcode() == ISD::BR) {
10274 SDValue FalseBB = User->getOperand(1);
10276 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10277 assert(NewBR == User);
10281 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10282 Cond.getOperand(0), Cond.getOperand(1));
10283 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10284 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10285 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10286 Chain, Dest, CC, Cmp);
10287 CC = DAG.getConstant(X86::COND_P, MVT::i8);
10292 } else if (Cond.getOpcode() == ISD::SETCC &&
10293 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
10294 // For FCMP_UNE, we can emit
10295 // two branches instead of an explicit AND instruction with a
10296 // separate test. However, we only do this if this block doesn't
10297 // have a fall-through edge, because this requires an explicit
10298 // jmp when the condition is false.
10299 if (Op.getNode()->hasOneUse()) {
10300 SDNode *User = *Op.getNode()->use_begin();
10301 // Look for an unconditional branch following this conditional branch.
10302 // We need this because we need to reverse the successors in order
10303 // to implement FCMP_UNE.
10304 if (User->getOpcode() == ISD::BR) {
10305 SDValue FalseBB = User->getOperand(1);
10307 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10308 assert(NewBR == User);
10311 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10312 Cond.getOperand(0), Cond.getOperand(1));
10313 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10314 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10315 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10316 Chain, Dest, CC, Cmp);
10317 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10327 // Look pass the truncate if the high bits are known zero.
10328 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10329 Cond = Cond.getOperand(0);
10331 // We know the result of AND is compared against zero. Try to match
10333 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10334 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10335 if (NewSetCC.getNode()) {
10336 CC = NewSetCC.getOperand(0);
10337 Cond = NewSetCC.getOperand(1);
10344 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10345 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10347 Cond = ConvertCmpIfNecessary(Cond, DAG);
10348 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10349 Chain, Dest, CC, Cond);
10352 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10353 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10354 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10355 // that the guard pages used by the OS virtual memory manager are allocated in
10356 // correct sequence.
10358 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10359 SelectionDAG &DAG) const {
10360 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10361 getTargetMachine().Options.EnableSegmentedStacks) &&
10362 "This should be used only on Windows targets or when segmented stacks "
10364 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10368 SDValue Chain = Op.getOperand(0);
10369 SDValue Size = Op.getOperand(1);
10370 // FIXME: Ensure alignment here
10372 bool Is64Bit = Subtarget->is64Bit();
10373 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10375 if (getTargetMachine().Options.EnableSegmentedStacks) {
10376 MachineFunction &MF = DAG.getMachineFunction();
10377 MachineRegisterInfo &MRI = MF.getRegInfo();
10380 // The 64 bit implementation of segmented stacks needs to clobber both r10
10381 // r11. This makes it impossible to use it along with nested parameters.
10382 const Function *F = MF.getFunction();
10384 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10386 if (I->hasNestAttr())
10387 report_fatal_error("Cannot use segmented stacks with functions that "
10388 "have nested arguments.");
10391 const TargetRegisterClass *AddrRegClass =
10392 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10393 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10394 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10395 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10396 DAG.getRegister(Vreg, SPTy));
10397 SDValue Ops1[2] = { Value, Chain };
10398 return DAG.getMergeValues(Ops1, 2, dl);
10401 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10403 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10404 Flag = Chain.getValue(1);
10405 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10407 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10408 Flag = Chain.getValue(1);
10410 const X86RegisterInfo *RegInfo =
10411 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
10412 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10415 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10416 return DAG.getMergeValues(Ops1, 2, dl);
10420 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10421 MachineFunction &MF = DAG.getMachineFunction();
10422 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10424 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10427 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10428 // vastart just stores the address of the VarArgsFrameIndex slot into the
10429 // memory location argument.
10430 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10432 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10433 MachinePointerInfo(SV), false, false, 0);
10437 // gp_offset (0 - 6 * 8)
10438 // fp_offset (48 - 48 + 8 * 16)
10439 // overflow_arg_area (point to parameters coming in memory).
10441 SmallVector<SDValue, 8> MemOps;
10442 SDValue FIN = Op.getOperand(1);
10444 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10445 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10447 FIN, MachinePointerInfo(SV), false, false, 0);
10448 MemOps.push_back(Store);
10451 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10452 FIN, DAG.getIntPtrConstant(4));
10453 Store = DAG.getStore(Op.getOperand(0), DL,
10454 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10456 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10457 MemOps.push_back(Store);
10459 // Store ptr to overflow_arg_area
10460 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10461 FIN, DAG.getIntPtrConstant(4));
10462 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10464 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10465 MachinePointerInfo(SV, 8),
10467 MemOps.push_back(Store);
10469 // Store ptr to reg_save_area.
10470 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10471 FIN, DAG.getIntPtrConstant(8));
10472 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10474 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10475 MachinePointerInfo(SV, 16), false, false, 0);
10476 MemOps.push_back(Store);
10477 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10478 &MemOps[0], MemOps.size());
10481 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10482 assert(Subtarget->is64Bit() &&
10483 "LowerVAARG only handles 64-bit va_arg!");
10484 assert((Subtarget->isTargetLinux() ||
10485 Subtarget->isTargetDarwin()) &&
10486 "Unhandled target in LowerVAARG");
10487 assert(Op.getNode()->getNumOperands() == 4);
10488 SDValue Chain = Op.getOperand(0);
10489 SDValue SrcPtr = Op.getOperand(1);
10490 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10491 unsigned Align = Op.getConstantOperandVal(3);
10494 EVT ArgVT = Op.getNode()->getValueType(0);
10495 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10496 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10499 // Decide which area this value should be read from.
10500 // TODO: Implement the AMD64 ABI in its entirety. This simple
10501 // selection mechanism works only for the basic types.
10502 if (ArgVT == MVT::f80) {
10503 llvm_unreachable("va_arg for f80 not yet implemented");
10504 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10505 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10506 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10507 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10509 llvm_unreachable("Unhandled argument type in LowerVAARG");
10512 if (ArgMode == 2) {
10513 // Sanity Check: Make sure using fp_offset makes sense.
10514 assert(!getTargetMachine().Options.UseSoftFloat &&
10515 !(DAG.getMachineFunction()
10516 .getFunction()->getAttributes()
10517 .hasAttribute(AttributeSet::FunctionIndex,
10518 Attribute::NoImplicitFloat)) &&
10519 Subtarget->hasSSE1());
10522 // Insert VAARG_64 node into the DAG
10523 // VAARG_64 returns two values: Variable Argument Address, Chain
10524 SmallVector<SDValue, 11> InstOps;
10525 InstOps.push_back(Chain);
10526 InstOps.push_back(SrcPtr);
10527 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10528 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10529 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10530 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10531 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10532 VTs, &InstOps[0], InstOps.size(),
10534 MachinePointerInfo(SV),
10536 /*Volatile=*/false,
10538 /*WriteMem=*/true);
10539 Chain = VAARG.getValue(1);
10541 // Load the next argument and return it
10542 return DAG.getLoad(ArgVT, dl,
10545 MachinePointerInfo(),
10546 false, false, false, 0);
10549 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10550 SelectionDAG &DAG) {
10551 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10552 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10553 SDValue Chain = Op.getOperand(0);
10554 SDValue DstPtr = Op.getOperand(1);
10555 SDValue SrcPtr = Op.getOperand(2);
10556 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10557 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10560 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10561 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10563 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10566 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10567 // may or may not be a constant. Takes immediate version of shift as input.
10568 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, EVT VT,
10569 SDValue SrcOp, SDValue ShAmt,
10570 SelectionDAG &DAG) {
10571 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10573 if (isa<ConstantSDNode>(ShAmt)) {
10574 // Constant may be a TargetConstant. Use a regular constant.
10575 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10577 default: llvm_unreachable("Unknown target vector shift node");
10578 case X86ISD::VSHLI:
10579 case X86ISD::VSRLI:
10580 case X86ISD::VSRAI:
10581 return DAG.getNode(Opc, dl, VT, SrcOp,
10582 DAG.getConstant(ShiftAmt, MVT::i32));
10586 // Change opcode to non-immediate version
10588 default: llvm_unreachable("Unknown target vector shift node");
10589 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10590 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10591 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10594 // Need to build a vector containing shift amount
10595 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10598 ShOps[1] = DAG.getConstant(0, MVT::i32);
10599 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10600 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10602 // The return type has to be a 128-bit type with the same element
10603 // type as the input type.
10604 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10605 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10607 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10608 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10611 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10613 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10615 default: return SDValue(); // Don't custom lower most intrinsics.
10616 // Comparison intrinsics.
10617 case Intrinsic::x86_sse_comieq_ss:
10618 case Intrinsic::x86_sse_comilt_ss:
10619 case Intrinsic::x86_sse_comile_ss:
10620 case Intrinsic::x86_sse_comigt_ss:
10621 case Intrinsic::x86_sse_comige_ss:
10622 case Intrinsic::x86_sse_comineq_ss:
10623 case Intrinsic::x86_sse_ucomieq_ss:
10624 case Intrinsic::x86_sse_ucomilt_ss:
10625 case Intrinsic::x86_sse_ucomile_ss:
10626 case Intrinsic::x86_sse_ucomigt_ss:
10627 case Intrinsic::x86_sse_ucomige_ss:
10628 case Intrinsic::x86_sse_ucomineq_ss:
10629 case Intrinsic::x86_sse2_comieq_sd:
10630 case Intrinsic::x86_sse2_comilt_sd:
10631 case Intrinsic::x86_sse2_comile_sd:
10632 case Intrinsic::x86_sse2_comigt_sd:
10633 case Intrinsic::x86_sse2_comige_sd:
10634 case Intrinsic::x86_sse2_comineq_sd:
10635 case Intrinsic::x86_sse2_ucomieq_sd:
10636 case Intrinsic::x86_sse2_ucomilt_sd:
10637 case Intrinsic::x86_sse2_ucomile_sd:
10638 case Intrinsic::x86_sse2_ucomigt_sd:
10639 case Intrinsic::x86_sse2_ucomige_sd:
10640 case Intrinsic::x86_sse2_ucomineq_sd: {
10644 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10645 case Intrinsic::x86_sse_comieq_ss:
10646 case Intrinsic::x86_sse2_comieq_sd:
10647 Opc = X86ISD::COMI;
10650 case Intrinsic::x86_sse_comilt_ss:
10651 case Intrinsic::x86_sse2_comilt_sd:
10652 Opc = X86ISD::COMI;
10655 case Intrinsic::x86_sse_comile_ss:
10656 case Intrinsic::x86_sse2_comile_sd:
10657 Opc = X86ISD::COMI;
10660 case Intrinsic::x86_sse_comigt_ss:
10661 case Intrinsic::x86_sse2_comigt_sd:
10662 Opc = X86ISD::COMI;
10665 case Intrinsic::x86_sse_comige_ss:
10666 case Intrinsic::x86_sse2_comige_sd:
10667 Opc = X86ISD::COMI;
10670 case Intrinsic::x86_sse_comineq_ss:
10671 case Intrinsic::x86_sse2_comineq_sd:
10672 Opc = X86ISD::COMI;
10675 case Intrinsic::x86_sse_ucomieq_ss:
10676 case Intrinsic::x86_sse2_ucomieq_sd:
10677 Opc = X86ISD::UCOMI;
10680 case Intrinsic::x86_sse_ucomilt_ss:
10681 case Intrinsic::x86_sse2_ucomilt_sd:
10682 Opc = X86ISD::UCOMI;
10685 case Intrinsic::x86_sse_ucomile_ss:
10686 case Intrinsic::x86_sse2_ucomile_sd:
10687 Opc = X86ISD::UCOMI;
10690 case Intrinsic::x86_sse_ucomigt_ss:
10691 case Intrinsic::x86_sse2_ucomigt_sd:
10692 Opc = X86ISD::UCOMI;
10695 case Intrinsic::x86_sse_ucomige_ss:
10696 case Intrinsic::x86_sse2_ucomige_sd:
10697 Opc = X86ISD::UCOMI;
10700 case Intrinsic::x86_sse_ucomineq_ss:
10701 case Intrinsic::x86_sse2_ucomineq_sd:
10702 Opc = X86ISD::UCOMI;
10707 SDValue LHS = Op.getOperand(1);
10708 SDValue RHS = Op.getOperand(2);
10709 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10710 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10711 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10712 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10713 DAG.getConstant(X86CC, MVT::i8), Cond);
10714 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10717 // Arithmetic intrinsics.
10718 case Intrinsic::x86_sse2_pmulu_dq:
10719 case Intrinsic::x86_avx2_pmulu_dq:
10720 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10721 Op.getOperand(1), Op.getOperand(2));
10723 // SSE2/AVX2 sub with unsigned saturation intrinsics
10724 case Intrinsic::x86_sse2_psubus_b:
10725 case Intrinsic::x86_sse2_psubus_w:
10726 case Intrinsic::x86_avx2_psubus_b:
10727 case Intrinsic::x86_avx2_psubus_w:
10728 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10729 Op.getOperand(1), Op.getOperand(2));
10731 // SSE3/AVX horizontal add/sub intrinsics
10732 case Intrinsic::x86_sse3_hadd_ps:
10733 case Intrinsic::x86_sse3_hadd_pd:
10734 case Intrinsic::x86_avx_hadd_ps_256:
10735 case Intrinsic::x86_avx_hadd_pd_256:
10736 case Intrinsic::x86_sse3_hsub_ps:
10737 case Intrinsic::x86_sse3_hsub_pd:
10738 case Intrinsic::x86_avx_hsub_ps_256:
10739 case Intrinsic::x86_avx_hsub_pd_256:
10740 case Intrinsic::x86_ssse3_phadd_w_128:
10741 case Intrinsic::x86_ssse3_phadd_d_128:
10742 case Intrinsic::x86_avx2_phadd_w:
10743 case Intrinsic::x86_avx2_phadd_d:
10744 case Intrinsic::x86_ssse3_phsub_w_128:
10745 case Intrinsic::x86_ssse3_phsub_d_128:
10746 case Intrinsic::x86_avx2_phsub_w:
10747 case Intrinsic::x86_avx2_phsub_d: {
10750 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10751 case Intrinsic::x86_sse3_hadd_ps:
10752 case Intrinsic::x86_sse3_hadd_pd:
10753 case Intrinsic::x86_avx_hadd_ps_256:
10754 case Intrinsic::x86_avx_hadd_pd_256:
10755 Opcode = X86ISD::FHADD;
10757 case Intrinsic::x86_sse3_hsub_ps:
10758 case Intrinsic::x86_sse3_hsub_pd:
10759 case Intrinsic::x86_avx_hsub_ps_256:
10760 case Intrinsic::x86_avx_hsub_pd_256:
10761 Opcode = X86ISD::FHSUB;
10763 case Intrinsic::x86_ssse3_phadd_w_128:
10764 case Intrinsic::x86_ssse3_phadd_d_128:
10765 case Intrinsic::x86_avx2_phadd_w:
10766 case Intrinsic::x86_avx2_phadd_d:
10767 Opcode = X86ISD::HADD;
10769 case Intrinsic::x86_ssse3_phsub_w_128:
10770 case Intrinsic::x86_ssse3_phsub_d_128:
10771 case Intrinsic::x86_avx2_phsub_w:
10772 case Intrinsic::x86_avx2_phsub_d:
10773 Opcode = X86ISD::HSUB;
10776 return DAG.getNode(Opcode, dl, Op.getValueType(),
10777 Op.getOperand(1), Op.getOperand(2));
10780 // SSE2/SSE41/AVX2 integer max/min intrinsics.
10781 case Intrinsic::x86_sse2_pmaxu_b:
10782 case Intrinsic::x86_sse41_pmaxuw:
10783 case Intrinsic::x86_sse41_pmaxud:
10784 case Intrinsic::x86_avx2_pmaxu_b:
10785 case Intrinsic::x86_avx2_pmaxu_w:
10786 case Intrinsic::x86_avx2_pmaxu_d:
10787 case Intrinsic::x86_sse2_pminu_b:
10788 case Intrinsic::x86_sse41_pminuw:
10789 case Intrinsic::x86_sse41_pminud:
10790 case Intrinsic::x86_avx2_pminu_b:
10791 case Intrinsic::x86_avx2_pminu_w:
10792 case Intrinsic::x86_avx2_pminu_d:
10793 case Intrinsic::x86_sse41_pmaxsb:
10794 case Intrinsic::x86_sse2_pmaxs_w:
10795 case Intrinsic::x86_sse41_pmaxsd:
10796 case Intrinsic::x86_avx2_pmaxs_b:
10797 case Intrinsic::x86_avx2_pmaxs_w:
10798 case Intrinsic::x86_avx2_pmaxs_d:
10799 case Intrinsic::x86_sse41_pminsb:
10800 case Intrinsic::x86_sse2_pmins_w:
10801 case Intrinsic::x86_sse41_pminsd:
10802 case Intrinsic::x86_avx2_pmins_b:
10803 case Intrinsic::x86_avx2_pmins_w:
10804 case Intrinsic::x86_avx2_pmins_d: {
10807 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10808 case Intrinsic::x86_sse2_pmaxu_b:
10809 case Intrinsic::x86_sse41_pmaxuw:
10810 case Intrinsic::x86_sse41_pmaxud:
10811 case Intrinsic::x86_avx2_pmaxu_b:
10812 case Intrinsic::x86_avx2_pmaxu_w:
10813 case Intrinsic::x86_avx2_pmaxu_d:
10814 Opcode = X86ISD::UMAX;
10816 case Intrinsic::x86_sse2_pminu_b:
10817 case Intrinsic::x86_sse41_pminuw:
10818 case Intrinsic::x86_sse41_pminud:
10819 case Intrinsic::x86_avx2_pminu_b:
10820 case Intrinsic::x86_avx2_pminu_w:
10821 case Intrinsic::x86_avx2_pminu_d:
10822 Opcode = X86ISD::UMIN;
10824 case Intrinsic::x86_sse41_pmaxsb:
10825 case Intrinsic::x86_sse2_pmaxs_w:
10826 case Intrinsic::x86_sse41_pmaxsd:
10827 case Intrinsic::x86_avx2_pmaxs_b:
10828 case Intrinsic::x86_avx2_pmaxs_w:
10829 case Intrinsic::x86_avx2_pmaxs_d:
10830 Opcode = X86ISD::SMAX;
10832 case Intrinsic::x86_sse41_pminsb:
10833 case Intrinsic::x86_sse2_pmins_w:
10834 case Intrinsic::x86_sse41_pminsd:
10835 case Intrinsic::x86_avx2_pmins_b:
10836 case Intrinsic::x86_avx2_pmins_w:
10837 case Intrinsic::x86_avx2_pmins_d:
10838 Opcode = X86ISD::SMIN;
10841 return DAG.getNode(Opcode, dl, Op.getValueType(),
10842 Op.getOperand(1), Op.getOperand(2));
10845 // SSE/SSE2/AVX floating point max/min intrinsics.
10846 case Intrinsic::x86_sse_max_ps:
10847 case Intrinsic::x86_sse2_max_pd:
10848 case Intrinsic::x86_avx_max_ps_256:
10849 case Intrinsic::x86_avx_max_pd_256:
10850 case Intrinsic::x86_sse_min_ps:
10851 case Intrinsic::x86_sse2_min_pd:
10852 case Intrinsic::x86_avx_min_ps_256:
10853 case Intrinsic::x86_avx_min_pd_256: {
10856 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10857 case Intrinsic::x86_sse_max_ps:
10858 case Intrinsic::x86_sse2_max_pd:
10859 case Intrinsic::x86_avx_max_ps_256:
10860 case Intrinsic::x86_avx_max_pd_256:
10861 Opcode = X86ISD::FMAX;
10863 case Intrinsic::x86_sse_min_ps:
10864 case Intrinsic::x86_sse2_min_pd:
10865 case Intrinsic::x86_avx_min_ps_256:
10866 case Intrinsic::x86_avx_min_pd_256:
10867 Opcode = X86ISD::FMIN;
10870 return DAG.getNode(Opcode, dl, Op.getValueType(),
10871 Op.getOperand(1), Op.getOperand(2));
10874 // AVX2 variable shift intrinsics
10875 case Intrinsic::x86_avx2_psllv_d:
10876 case Intrinsic::x86_avx2_psllv_q:
10877 case Intrinsic::x86_avx2_psllv_d_256:
10878 case Intrinsic::x86_avx2_psllv_q_256:
10879 case Intrinsic::x86_avx2_psrlv_d:
10880 case Intrinsic::x86_avx2_psrlv_q:
10881 case Intrinsic::x86_avx2_psrlv_d_256:
10882 case Intrinsic::x86_avx2_psrlv_q_256:
10883 case Intrinsic::x86_avx2_psrav_d:
10884 case Intrinsic::x86_avx2_psrav_d_256: {
10887 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10888 case Intrinsic::x86_avx2_psllv_d:
10889 case Intrinsic::x86_avx2_psllv_q:
10890 case Intrinsic::x86_avx2_psllv_d_256:
10891 case Intrinsic::x86_avx2_psllv_q_256:
10894 case Intrinsic::x86_avx2_psrlv_d:
10895 case Intrinsic::x86_avx2_psrlv_q:
10896 case Intrinsic::x86_avx2_psrlv_d_256:
10897 case Intrinsic::x86_avx2_psrlv_q_256:
10900 case Intrinsic::x86_avx2_psrav_d:
10901 case Intrinsic::x86_avx2_psrav_d_256:
10905 return DAG.getNode(Opcode, dl, Op.getValueType(),
10906 Op.getOperand(1), Op.getOperand(2));
10909 case Intrinsic::x86_ssse3_pshuf_b_128:
10910 case Intrinsic::x86_avx2_pshuf_b:
10911 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10912 Op.getOperand(1), Op.getOperand(2));
10914 case Intrinsic::x86_ssse3_psign_b_128:
10915 case Intrinsic::x86_ssse3_psign_w_128:
10916 case Intrinsic::x86_ssse3_psign_d_128:
10917 case Intrinsic::x86_avx2_psign_b:
10918 case Intrinsic::x86_avx2_psign_w:
10919 case Intrinsic::x86_avx2_psign_d:
10920 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10921 Op.getOperand(1), Op.getOperand(2));
10923 case Intrinsic::x86_sse41_insertps:
10924 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10925 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10927 case Intrinsic::x86_avx_vperm2f128_ps_256:
10928 case Intrinsic::x86_avx_vperm2f128_pd_256:
10929 case Intrinsic::x86_avx_vperm2f128_si_256:
10930 case Intrinsic::x86_avx2_vperm2i128:
10931 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10932 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10934 case Intrinsic::x86_avx2_permd:
10935 case Intrinsic::x86_avx2_permps:
10936 // Operands intentionally swapped. Mask is last operand to intrinsic,
10937 // but second operand for node/intruction.
10938 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10939 Op.getOperand(2), Op.getOperand(1));
10941 case Intrinsic::x86_sse_sqrt_ps:
10942 case Intrinsic::x86_sse2_sqrt_pd:
10943 case Intrinsic::x86_avx_sqrt_ps_256:
10944 case Intrinsic::x86_avx_sqrt_pd_256:
10945 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
10947 // ptest and testp intrinsics. The intrinsic these come from are designed to
10948 // return an integer value, not just an instruction so lower it to the ptest
10949 // or testp pattern and a setcc for the result.
10950 case Intrinsic::x86_sse41_ptestz:
10951 case Intrinsic::x86_sse41_ptestc:
10952 case Intrinsic::x86_sse41_ptestnzc:
10953 case Intrinsic::x86_avx_ptestz_256:
10954 case Intrinsic::x86_avx_ptestc_256:
10955 case Intrinsic::x86_avx_ptestnzc_256:
10956 case Intrinsic::x86_avx_vtestz_ps:
10957 case Intrinsic::x86_avx_vtestc_ps:
10958 case Intrinsic::x86_avx_vtestnzc_ps:
10959 case Intrinsic::x86_avx_vtestz_pd:
10960 case Intrinsic::x86_avx_vtestc_pd:
10961 case Intrinsic::x86_avx_vtestnzc_pd:
10962 case Intrinsic::x86_avx_vtestz_ps_256:
10963 case Intrinsic::x86_avx_vtestc_ps_256:
10964 case Intrinsic::x86_avx_vtestnzc_ps_256:
10965 case Intrinsic::x86_avx_vtestz_pd_256:
10966 case Intrinsic::x86_avx_vtestc_pd_256:
10967 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10968 bool IsTestPacked = false;
10971 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10972 case Intrinsic::x86_avx_vtestz_ps:
10973 case Intrinsic::x86_avx_vtestz_pd:
10974 case Intrinsic::x86_avx_vtestz_ps_256:
10975 case Intrinsic::x86_avx_vtestz_pd_256:
10976 IsTestPacked = true; // Fallthrough
10977 case Intrinsic::x86_sse41_ptestz:
10978 case Intrinsic::x86_avx_ptestz_256:
10980 X86CC = X86::COND_E;
10982 case Intrinsic::x86_avx_vtestc_ps:
10983 case Intrinsic::x86_avx_vtestc_pd:
10984 case Intrinsic::x86_avx_vtestc_ps_256:
10985 case Intrinsic::x86_avx_vtestc_pd_256:
10986 IsTestPacked = true; // Fallthrough
10987 case Intrinsic::x86_sse41_ptestc:
10988 case Intrinsic::x86_avx_ptestc_256:
10990 X86CC = X86::COND_B;
10992 case Intrinsic::x86_avx_vtestnzc_ps:
10993 case Intrinsic::x86_avx_vtestnzc_pd:
10994 case Intrinsic::x86_avx_vtestnzc_ps_256:
10995 case Intrinsic::x86_avx_vtestnzc_pd_256:
10996 IsTestPacked = true; // Fallthrough
10997 case Intrinsic::x86_sse41_ptestnzc:
10998 case Intrinsic::x86_avx_ptestnzc_256:
11000 X86CC = X86::COND_A;
11004 SDValue LHS = Op.getOperand(1);
11005 SDValue RHS = Op.getOperand(2);
11006 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
11007 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
11008 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
11009 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
11010 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11013 // SSE/AVX shift intrinsics
11014 case Intrinsic::x86_sse2_psll_w:
11015 case Intrinsic::x86_sse2_psll_d:
11016 case Intrinsic::x86_sse2_psll_q:
11017 case Intrinsic::x86_avx2_psll_w:
11018 case Intrinsic::x86_avx2_psll_d:
11019 case Intrinsic::x86_avx2_psll_q:
11020 case Intrinsic::x86_sse2_psrl_w:
11021 case Intrinsic::x86_sse2_psrl_d:
11022 case Intrinsic::x86_sse2_psrl_q:
11023 case Intrinsic::x86_avx2_psrl_w:
11024 case Intrinsic::x86_avx2_psrl_d:
11025 case Intrinsic::x86_avx2_psrl_q:
11026 case Intrinsic::x86_sse2_psra_w:
11027 case Intrinsic::x86_sse2_psra_d:
11028 case Intrinsic::x86_avx2_psra_w:
11029 case Intrinsic::x86_avx2_psra_d: {
11032 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11033 case Intrinsic::x86_sse2_psll_w:
11034 case Intrinsic::x86_sse2_psll_d:
11035 case Intrinsic::x86_sse2_psll_q:
11036 case Intrinsic::x86_avx2_psll_w:
11037 case Intrinsic::x86_avx2_psll_d:
11038 case Intrinsic::x86_avx2_psll_q:
11039 Opcode = X86ISD::VSHL;
11041 case Intrinsic::x86_sse2_psrl_w:
11042 case Intrinsic::x86_sse2_psrl_d:
11043 case Intrinsic::x86_sse2_psrl_q:
11044 case Intrinsic::x86_avx2_psrl_w:
11045 case Intrinsic::x86_avx2_psrl_d:
11046 case Intrinsic::x86_avx2_psrl_q:
11047 Opcode = X86ISD::VSRL;
11049 case Intrinsic::x86_sse2_psra_w:
11050 case Intrinsic::x86_sse2_psra_d:
11051 case Intrinsic::x86_avx2_psra_w:
11052 case Intrinsic::x86_avx2_psra_d:
11053 Opcode = X86ISD::VSRA;
11056 return DAG.getNode(Opcode, dl, Op.getValueType(),
11057 Op.getOperand(1), Op.getOperand(2));
11060 // SSE/AVX immediate shift intrinsics
11061 case Intrinsic::x86_sse2_pslli_w:
11062 case Intrinsic::x86_sse2_pslli_d:
11063 case Intrinsic::x86_sse2_pslli_q:
11064 case Intrinsic::x86_avx2_pslli_w:
11065 case Intrinsic::x86_avx2_pslli_d:
11066 case Intrinsic::x86_avx2_pslli_q:
11067 case Intrinsic::x86_sse2_psrli_w:
11068 case Intrinsic::x86_sse2_psrli_d:
11069 case Intrinsic::x86_sse2_psrli_q:
11070 case Intrinsic::x86_avx2_psrli_w:
11071 case Intrinsic::x86_avx2_psrli_d:
11072 case Intrinsic::x86_avx2_psrli_q:
11073 case Intrinsic::x86_sse2_psrai_w:
11074 case Intrinsic::x86_sse2_psrai_d:
11075 case Intrinsic::x86_avx2_psrai_w:
11076 case Intrinsic::x86_avx2_psrai_d: {
11079 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11080 case Intrinsic::x86_sse2_pslli_w:
11081 case Intrinsic::x86_sse2_pslli_d:
11082 case Intrinsic::x86_sse2_pslli_q:
11083 case Intrinsic::x86_avx2_pslli_w:
11084 case Intrinsic::x86_avx2_pslli_d:
11085 case Intrinsic::x86_avx2_pslli_q:
11086 Opcode = X86ISD::VSHLI;
11088 case Intrinsic::x86_sse2_psrli_w:
11089 case Intrinsic::x86_sse2_psrli_d:
11090 case Intrinsic::x86_sse2_psrli_q:
11091 case Intrinsic::x86_avx2_psrli_w:
11092 case Intrinsic::x86_avx2_psrli_d:
11093 case Intrinsic::x86_avx2_psrli_q:
11094 Opcode = X86ISD::VSRLI;
11096 case Intrinsic::x86_sse2_psrai_w:
11097 case Intrinsic::x86_sse2_psrai_d:
11098 case Intrinsic::x86_avx2_psrai_w:
11099 case Intrinsic::x86_avx2_psrai_d:
11100 Opcode = X86ISD::VSRAI;
11103 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
11104 Op.getOperand(1), Op.getOperand(2), DAG);
11107 case Intrinsic::x86_sse42_pcmpistria128:
11108 case Intrinsic::x86_sse42_pcmpestria128:
11109 case Intrinsic::x86_sse42_pcmpistric128:
11110 case Intrinsic::x86_sse42_pcmpestric128:
11111 case Intrinsic::x86_sse42_pcmpistrio128:
11112 case Intrinsic::x86_sse42_pcmpestrio128:
11113 case Intrinsic::x86_sse42_pcmpistris128:
11114 case Intrinsic::x86_sse42_pcmpestris128:
11115 case Intrinsic::x86_sse42_pcmpistriz128:
11116 case Intrinsic::x86_sse42_pcmpestriz128: {
11120 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11121 case Intrinsic::x86_sse42_pcmpistria128:
11122 Opcode = X86ISD::PCMPISTRI;
11123 X86CC = X86::COND_A;
11125 case Intrinsic::x86_sse42_pcmpestria128:
11126 Opcode = X86ISD::PCMPESTRI;
11127 X86CC = X86::COND_A;
11129 case Intrinsic::x86_sse42_pcmpistric128:
11130 Opcode = X86ISD::PCMPISTRI;
11131 X86CC = X86::COND_B;
11133 case Intrinsic::x86_sse42_pcmpestric128:
11134 Opcode = X86ISD::PCMPESTRI;
11135 X86CC = X86::COND_B;
11137 case Intrinsic::x86_sse42_pcmpistrio128:
11138 Opcode = X86ISD::PCMPISTRI;
11139 X86CC = X86::COND_O;
11141 case Intrinsic::x86_sse42_pcmpestrio128:
11142 Opcode = X86ISD::PCMPESTRI;
11143 X86CC = X86::COND_O;
11145 case Intrinsic::x86_sse42_pcmpistris128:
11146 Opcode = X86ISD::PCMPISTRI;
11147 X86CC = X86::COND_S;
11149 case Intrinsic::x86_sse42_pcmpestris128:
11150 Opcode = X86ISD::PCMPESTRI;
11151 X86CC = X86::COND_S;
11153 case Intrinsic::x86_sse42_pcmpistriz128:
11154 Opcode = X86ISD::PCMPISTRI;
11155 X86CC = X86::COND_E;
11157 case Intrinsic::x86_sse42_pcmpestriz128:
11158 Opcode = X86ISD::PCMPESTRI;
11159 X86CC = X86::COND_E;
11162 SmallVector<SDValue, 5> NewOps;
11163 NewOps.append(Op->op_begin()+1, Op->op_end());
11164 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11165 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11166 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11167 DAG.getConstant(X86CC, MVT::i8),
11168 SDValue(PCMP.getNode(), 1));
11169 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
11172 case Intrinsic::x86_sse42_pcmpistri128:
11173 case Intrinsic::x86_sse42_pcmpestri128: {
11175 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
11176 Opcode = X86ISD::PCMPISTRI;
11178 Opcode = X86ISD::PCMPESTRI;
11180 SmallVector<SDValue, 5> NewOps;
11181 NewOps.append(Op->op_begin()+1, Op->op_end());
11182 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
11183 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
11185 case Intrinsic::x86_fma_vfmadd_ps:
11186 case Intrinsic::x86_fma_vfmadd_pd:
11187 case Intrinsic::x86_fma_vfmsub_ps:
11188 case Intrinsic::x86_fma_vfmsub_pd:
11189 case Intrinsic::x86_fma_vfnmadd_ps:
11190 case Intrinsic::x86_fma_vfnmadd_pd:
11191 case Intrinsic::x86_fma_vfnmsub_ps:
11192 case Intrinsic::x86_fma_vfnmsub_pd:
11193 case Intrinsic::x86_fma_vfmaddsub_ps:
11194 case Intrinsic::x86_fma_vfmaddsub_pd:
11195 case Intrinsic::x86_fma_vfmsubadd_ps:
11196 case Intrinsic::x86_fma_vfmsubadd_pd:
11197 case Intrinsic::x86_fma_vfmadd_ps_256:
11198 case Intrinsic::x86_fma_vfmadd_pd_256:
11199 case Intrinsic::x86_fma_vfmsub_ps_256:
11200 case Intrinsic::x86_fma_vfmsub_pd_256:
11201 case Intrinsic::x86_fma_vfnmadd_ps_256:
11202 case Intrinsic::x86_fma_vfnmadd_pd_256:
11203 case Intrinsic::x86_fma_vfnmsub_ps_256:
11204 case Intrinsic::x86_fma_vfnmsub_pd_256:
11205 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11206 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11207 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11208 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
11211 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
11212 case Intrinsic::x86_fma_vfmadd_ps:
11213 case Intrinsic::x86_fma_vfmadd_pd:
11214 case Intrinsic::x86_fma_vfmadd_ps_256:
11215 case Intrinsic::x86_fma_vfmadd_pd_256:
11216 Opc = X86ISD::FMADD;
11218 case Intrinsic::x86_fma_vfmsub_ps:
11219 case Intrinsic::x86_fma_vfmsub_pd:
11220 case Intrinsic::x86_fma_vfmsub_ps_256:
11221 case Intrinsic::x86_fma_vfmsub_pd_256:
11222 Opc = X86ISD::FMSUB;
11224 case Intrinsic::x86_fma_vfnmadd_ps:
11225 case Intrinsic::x86_fma_vfnmadd_pd:
11226 case Intrinsic::x86_fma_vfnmadd_ps_256:
11227 case Intrinsic::x86_fma_vfnmadd_pd_256:
11228 Opc = X86ISD::FNMADD;
11230 case Intrinsic::x86_fma_vfnmsub_ps:
11231 case Intrinsic::x86_fma_vfnmsub_pd:
11232 case Intrinsic::x86_fma_vfnmsub_ps_256:
11233 case Intrinsic::x86_fma_vfnmsub_pd_256:
11234 Opc = X86ISD::FNMSUB;
11236 case Intrinsic::x86_fma_vfmaddsub_ps:
11237 case Intrinsic::x86_fma_vfmaddsub_pd:
11238 case Intrinsic::x86_fma_vfmaddsub_ps_256:
11239 case Intrinsic::x86_fma_vfmaddsub_pd_256:
11240 Opc = X86ISD::FMADDSUB;
11242 case Intrinsic::x86_fma_vfmsubadd_ps:
11243 case Intrinsic::x86_fma_vfmsubadd_pd:
11244 case Intrinsic::x86_fma_vfmsubadd_ps_256:
11245 case Intrinsic::x86_fma_vfmsubadd_pd_256:
11246 Opc = X86ISD::FMSUBADD;
11250 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
11251 Op.getOperand(2), Op.getOperand(3));
11256 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
11258 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11260 default: return SDValue(); // Don't custom lower most intrinsics.
11262 // RDRAND/RDSEED intrinsics.
11263 case Intrinsic::x86_rdrand_16:
11264 case Intrinsic::x86_rdrand_32:
11265 case Intrinsic::x86_rdrand_64:
11266 case Intrinsic::x86_rdseed_16:
11267 case Intrinsic::x86_rdseed_32:
11268 case Intrinsic::x86_rdseed_64: {
11269 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
11270 IntNo == Intrinsic::x86_rdseed_32 ||
11271 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
11273 // Emit the node with the right value type.
11274 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
11275 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
11277 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
11278 // Otherwise return the value from Rand, which is always 0, casted to i32.
11279 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
11280 DAG.getConstant(1, Op->getValueType(1)),
11281 DAG.getConstant(X86::COND_B, MVT::i32),
11282 SDValue(Result.getNode(), 1) };
11283 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
11284 DAG.getVTList(Op->getValueType(1), MVT::Glue),
11285 Ops, array_lengthof(Ops));
11287 // Return { result, isValid, chain }.
11288 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
11289 SDValue(Result.getNode(), 2));
11292 // XTEST intrinsics.
11293 case Intrinsic::x86_xtest: {
11294 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
11295 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
11296 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
11297 DAG.getConstant(X86::COND_NE, MVT::i8),
11299 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
11300 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11301 Ret, SDValue(InTrans.getNode(), 1));
11306 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11307 SelectionDAG &DAG) const {
11308 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11309 MFI->setReturnAddressIsTaken(true);
11311 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11313 EVT PtrVT = getPointerTy();
11316 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11317 const X86RegisterInfo *RegInfo =
11318 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11319 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11320 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11321 DAG.getNode(ISD::ADD, dl, PtrVT,
11322 FrameAddr, Offset),
11323 MachinePointerInfo(), false, false, false, 0);
11326 // Just load the return address.
11327 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11328 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11329 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11332 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11333 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11334 MFI->setFrameAddressIsTaken(true);
11336 EVT VT = Op.getValueType();
11337 SDLoc dl(Op); // FIXME probably not meaningful
11338 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11339 const X86RegisterInfo *RegInfo =
11340 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11341 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11342 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11343 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11344 "Invalid Frame Register!");
11345 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11347 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11348 MachinePointerInfo(),
11349 false, false, false, 0);
11353 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11354 SelectionDAG &DAG) const {
11355 const X86RegisterInfo *RegInfo =
11356 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11357 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11360 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11361 SDValue Chain = Op.getOperand(0);
11362 SDValue Offset = Op.getOperand(1);
11363 SDValue Handler = Op.getOperand(2);
11366 EVT PtrVT = getPointerTy();
11367 const X86RegisterInfo *RegInfo =
11368 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
11369 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11370 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11371 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11372 "Invalid Frame Register!");
11373 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11374 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11376 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11377 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11378 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
11379 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
11381 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
11383 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
11384 DAG.getRegister(StoreAddrReg, PtrVT));
11387 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
11388 SelectionDAG &DAG) const {
11390 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
11391 DAG.getVTList(MVT::i32, MVT::Other),
11392 Op.getOperand(0), Op.getOperand(1));
11395 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
11396 SelectionDAG &DAG) const {
11398 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
11399 Op.getOperand(0), Op.getOperand(1));
11402 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
11403 return Op.getOperand(0);
11406 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
11407 SelectionDAG &DAG) const {
11408 SDValue Root = Op.getOperand(0);
11409 SDValue Trmp = Op.getOperand(1); // trampoline
11410 SDValue FPtr = Op.getOperand(2); // nested function
11411 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
11414 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11415 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
11417 if (Subtarget->is64Bit()) {
11418 SDValue OutChains[6];
11420 // Large code-model.
11421 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11422 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11424 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
11425 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
11427 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
11429 // Load the pointer to the nested function into R11.
11430 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11431 SDValue Addr = Trmp;
11432 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11433 Addr, MachinePointerInfo(TrmpAddr),
11436 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11437 DAG.getConstant(2, MVT::i64));
11438 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11439 MachinePointerInfo(TrmpAddr, 2),
11442 // Load the 'nest' parameter value into R10.
11443 // R10 is specified in X86CallingConv.td
11444 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11445 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11446 DAG.getConstant(10, MVT::i64));
11447 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11448 Addr, MachinePointerInfo(TrmpAddr, 10),
11451 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11452 DAG.getConstant(12, MVT::i64));
11453 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11454 MachinePointerInfo(TrmpAddr, 12),
11457 // Jump to the nested function.
11458 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11459 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11460 DAG.getConstant(20, MVT::i64));
11461 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11462 Addr, MachinePointerInfo(TrmpAddr, 20),
11465 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11466 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11467 DAG.getConstant(22, MVT::i64));
11468 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11469 MachinePointerInfo(TrmpAddr, 22),
11472 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11474 const Function *Func =
11475 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11476 CallingConv::ID CC = Func->getCallingConv();
11481 llvm_unreachable("Unsupported calling convention");
11482 case CallingConv::C:
11483 case CallingConv::X86_StdCall: {
11484 // Pass 'nest' parameter in ECX.
11485 // Must be kept in sync with X86CallingConv.td
11486 NestReg = X86::ECX;
11488 // Check that ECX wasn't needed by an 'inreg' parameter.
11489 FunctionType *FTy = Func->getFunctionType();
11490 const AttributeSet &Attrs = Func->getAttributes();
11492 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11493 unsigned InRegCount = 0;
11496 for (FunctionType::param_iterator I = FTy->param_begin(),
11497 E = FTy->param_end(); I != E; ++I, ++Idx)
11498 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11499 // FIXME: should only count parameters that are lowered to integers.
11500 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11502 if (InRegCount > 2) {
11503 report_fatal_error("Nest register in use - reduce number of inreg"
11509 case CallingConv::X86_FastCall:
11510 case CallingConv::X86_ThisCall:
11511 case CallingConv::Fast:
11512 // Pass 'nest' parameter in EAX.
11513 // Must be kept in sync with X86CallingConv.td
11514 NestReg = X86::EAX;
11518 SDValue OutChains[4];
11519 SDValue Addr, Disp;
11521 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11522 DAG.getConstant(10, MVT::i32));
11523 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11525 // This is storing the opcode for MOV32ri.
11526 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11527 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11528 OutChains[0] = DAG.getStore(Root, dl,
11529 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11530 Trmp, MachinePointerInfo(TrmpAddr),
11533 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11534 DAG.getConstant(1, MVT::i32));
11535 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11536 MachinePointerInfo(TrmpAddr, 1),
11539 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11540 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11541 DAG.getConstant(5, MVT::i32));
11542 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11543 MachinePointerInfo(TrmpAddr, 5),
11546 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11547 DAG.getConstant(6, MVT::i32));
11548 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11549 MachinePointerInfo(TrmpAddr, 6),
11552 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11556 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11557 SelectionDAG &DAG) const {
11559 The rounding mode is in bits 11:10 of FPSR, and has the following
11561 00 Round to nearest
11566 FLT_ROUNDS, on the other hand, expects the following:
11573 To perform the conversion, we do:
11574 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11577 MachineFunction &MF = DAG.getMachineFunction();
11578 const TargetMachine &TM = MF.getTarget();
11579 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11580 unsigned StackAlignment = TFI.getStackAlignment();
11581 EVT VT = Op.getValueType();
11584 // Save FP Control Word to stack slot
11585 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11586 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11588 MachineMemOperand *MMO =
11589 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11590 MachineMemOperand::MOStore, 2, 2);
11592 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11593 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11594 DAG.getVTList(MVT::Other),
11595 Ops, array_lengthof(Ops), MVT::i16,
11598 // Load FP Control Word from stack slot
11599 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11600 MachinePointerInfo(), false, false, false, 0);
11602 // Transform as necessary
11604 DAG.getNode(ISD::SRL, DL, MVT::i16,
11605 DAG.getNode(ISD::AND, DL, MVT::i16,
11606 CWD, DAG.getConstant(0x800, MVT::i16)),
11607 DAG.getConstant(11, MVT::i8));
11609 DAG.getNode(ISD::SRL, DL, MVT::i16,
11610 DAG.getNode(ISD::AND, DL, MVT::i16,
11611 CWD, DAG.getConstant(0x400, MVT::i16)),
11612 DAG.getConstant(9, MVT::i8));
11615 DAG.getNode(ISD::AND, DL, MVT::i16,
11616 DAG.getNode(ISD::ADD, DL, MVT::i16,
11617 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11618 DAG.getConstant(1, MVT::i16)),
11619 DAG.getConstant(3, MVT::i16));
11621 return DAG.getNode((VT.getSizeInBits() < 16 ?
11622 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11625 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11626 EVT VT = Op.getValueType();
11628 unsigned NumBits = VT.getSizeInBits();
11631 Op = Op.getOperand(0);
11632 if (VT == MVT::i8) {
11633 // Zero extend to i32 since there is not an i8 bsr.
11635 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11638 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11639 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11640 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11642 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11645 DAG.getConstant(NumBits+NumBits-1, OpVT),
11646 DAG.getConstant(X86::COND_E, MVT::i8),
11649 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11651 // Finally xor with NumBits-1.
11652 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11655 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11659 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11660 EVT VT = Op.getValueType();
11662 unsigned NumBits = VT.getSizeInBits();
11665 Op = Op.getOperand(0);
11666 if (VT == MVT::i8) {
11667 // Zero extend to i32 since there is not an i8 bsr.
11669 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11672 // Issue a bsr (scan bits in reverse).
11673 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11674 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11676 // And xor with NumBits-1.
11677 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11680 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11684 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11685 EVT VT = Op.getValueType();
11686 unsigned NumBits = VT.getSizeInBits();
11688 Op = Op.getOperand(0);
11690 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11691 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11692 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11694 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11697 DAG.getConstant(NumBits, VT),
11698 DAG.getConstant(X86::COND_E, MVT::i8),
11701 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11704 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11705 // ones, and then concatenate the result back.
11706 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11707 EVT VT = Op.getValueType();
11709 assert(VT.is256BitVector() && VT.isInteger() &&
11710 "Unsupported value type for operation");
11712 unsigned NumElems = VT.getVectorNumElements();
11715 // Extract the LHS vectors
11716 SDValue LHS = Op.getOperand(0);
11717 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11718 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11720 // Extract the RHS vectors
11721 SDValue RHS = Op.getOperand(1);
11722 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11723 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11725 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11726 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11728 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11729 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11730 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11733 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
11734 assert(Op.getValueType().is256BitVector() &&
11735 Op.getValueType().isInteger() &&
11736 "Only handle AVX 256-bit vector integer operation");
11737 return Lower256IntArith(Op, DAG);
11740 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
11741 assert(Op.getValueType().is256BitVector() &&
11742 Op.getValueType().isInteger() &&
11743 "Only handle AVX 256-bit vector integer operation");
11744 return Lower256IntArith(Op, DAG);
11747 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
11748 SelectionDAG &DAG) {
11750 EVT VT = Op.getValueType();
11752 // Decompose 256-bit ops into smaller 128-bit ops.
11753 if (VT.is256BitVector() && !Subtarget->hasInt256())
11754 return Lower256IntArith(Op, DAG);
11756 SDValue A = Op.getOperand(0);
11757 SDValue B = Op.getOperand(1);
11759 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
11760 if (VT == MVT::v4i32) {
11761 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
11762 "Should not custom lower when pmuldq is available!");
11764 // Extract the odd parts.
11765 static const int UnpackMask[] = { 1, -1, 3, -1 };
11766 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
11767 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
11769 // Multiply the even parts.
11770 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
11771 // Now multiply odd parts.
11772 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
11774 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
11775 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
11777 // Merge the two vectors back together with a shuffle. This expands into 2
11779 static const int ShufMask[] = { 0, 4, 2, 6 };
11780 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
11783 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11784 "Only know how to lower V2I64/V4I64 multiply");
11786 // Ahi = psrlqi(a, 32);
11787 // Bhi = psrlqi(b, 32);
11789 // AloBlo = pmuludq(a, b);
11790 // AloBhi = pmuludq(a, Bhi);
11791 // AhiBlo = pmuludq(Ahi, b);
11793 // AloBhi = psllqi(AloBhi, 32);
11794 // AhiBlo = psllqi(AhiBlo, 32);
11795 // return AloBlo + AloBhi + AhiBlo;
11797 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11799 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11800 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11802 // Bit cast to 32-bit vectors for MULUDQ
11803 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11804 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11805 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11806 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11807 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11809 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11810 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11811 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11813 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11814 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11816 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11817 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11820 SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
11821 EVT VT = Op.getValueType();
11822 EVT EltTy = VT.getVectorElementType();
11823 unsigned NumElts = VT.getVectorNumElements();
11824 SDValue N0 = Op.getOperand(0);
11827 // Lower sdiv X, pow2-const.
11828 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
11832 APInt SplatValue, SplatUndef;
11833 unsigned SplatBitSize;
11835 if (!C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
11837 EltTy.getSizeInBits() < SplatBitSize)
11840 if ((SplatValue != 0) &&
11841 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
11842 unsigned lg2 = SplatValue.countTrailingZeros();
11843 // Splat the sign bit.
11844 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
11845 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
11846 // Add (N0 < 0) ? abs2 - 1 : 0;
11847 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
11848 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
11849 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
11850 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
11851 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
11853 // If we're dividing by a positive value, we're done. Otherwise, we must
11854 // negate the result.
11855 if (SplatValue.isNonNegative())
11858 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
11859 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
11860 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
11865 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
11866 const X86Subtarget *Subtarget) {
11867 EVT VT = Op.getValueType();
11869 SDValue R = Op.getOperand(0);
11870 SDValue Amt = Op.getOperand(1);
11872 // Optimize shl/srl/sra with constant shift amount.
11873 if (isSplatVector(Amt.getNode())) {
11874 SDValue SclrAmt = Amt->getOperand(0);
11875 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11876 uint64_t ShiftAmt = C->getZExtValue();
11878 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11879 (Subtarget->hasInt256() &&
11880 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11881 if (Op.getOpcode() == ISD::SHL)
11882 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11883 DAG.getConstant(ShiftAmt, MVT::i32));
11884 if (Op.getOpcode() == ISD::SRL)
11885 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11886 DAG.getConstant(ShiftAmt, MVT::i32));
11887 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11888 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11889 DAG.getConstant(ShiftAmt, MVT::i32));
11892 if (VT == MVT::v16i8) {
11893 if (Op.getOpcode() == ISD::SHL) {
11894 // Make a large shift.
11895 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11896 DAG.getConstant(ShiftAmt, MVT::i32));
11897 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11898 // Zero out the rightmost bits.
11899 SmallVector<SDValue, 16> V(16,
11900 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11902 return DAG.getNode(ISD::AND, dl, VT, SHL,
11903 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11905 if (Op.getOpcode() == ISD::SRL) {
11906 // Make a large shift.
11907 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11908 DAG.getConstant(ShiftAmt, MVT::i32));
11909 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11910 // Zero out the leftmost bits.
11911 SmallVector<SDValue, 16> V(16,
11912 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11914 return DAG.getNode(ISD::AND, dl, VT, SRL,
11915 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11917 if (Op.getOpcode() == ISD::SRA) {
11918 if (ShiftAmt == 7) {
11919 // R s>> 7 === R s< 0
11920 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11921 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11924 // R s>> a === ((R u>> a) ^ m) - m
11925 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11926 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11928 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11929 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11930 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11933 llvm_unreachable("Unknown shift opcode.");
11936 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11937 if (Op.getOpcode() == ISD::SHL) {
11938 // Make a large shift.
11939 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11940 DAG.getConstant(ShiftAmt, MVT::i32));
11941 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11942 // Zero out the rightmost bits.
11943 SmallVector<SDValue, 32> V(32,
11944 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11946 return DAG.getNode(ISD::AND, dl, VT, SHL,
11947 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11949 if (Op.getOpcode() == ISD::SRL) {
11950 // Make a large shift.
11951 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11952 DAG.getConstant(ShiftAmt, MVT::i32));
11953 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11954 // Zero out the leftmost bits.
11955 SmallVector<SDValue, 32> V(32,
11956 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11958 return DAG.getNode(ISD::AND, dl, VT, SRL,
11959 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11961 if (Op.getOpcode() == ISD::SRA) {
11962 if (ShiftAmt == 7) {
11963 // R s>> 7 === R s< 0
11964 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11965 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11968 // R s>> a === ((R u>> a) ^ m) - m
11969 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11970 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11972 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11973 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11974 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11977 llvm_unreachable("Unknown shift opcode.");
11982 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
11983 if (!Subtarget->is64Bit() &&
11984 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
11985 Amt.getOpcode() == ISD::BITCAST &&
11986 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
11987 Amt = Amt.getOperand(0);
11988 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
11989 VT.getVectorNumElements();
11990 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
11991 uint64_t ShiftAmt = 0;
11992 for (unsigned i = 0; i != Ratio; ++i) {
11993 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
11997 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
11999 // Check remaining shift amounts.
12000 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12001 uint64_t ShAmt = 0;
12002 for (unsigned j = 0; j != Ratio; ++j) {
12003 ConstantSDNode *C =
12004 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
12008 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
12010 if (ShAmt != ShiftAmt)
12013 switch (Op.getOpcode()) {
12015 llvm_unreachable("Unknown shift opcode!");
12017 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
12018 DAG.getConstant(ShiftAmt, MVT::i32));
12020 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
12021 DAG.getConstant(ShiftAmt, MVT::i32));
12023 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
12024 DAG.getConstant(ShiftAmt, MVT::i32));
12031 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
12032 const X86Subtarget* Subtarget) {
12033 EVT VT = Op.getValueType();
12035 SDValue R = Op.getOperand(0);
12036 SDValue Amt = Op.getOperand(1);
12038 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
12039 VT == MVT::v4i32 || VT == MVT::v8i16 ||
12040 (Subtarget->hasInt256() &&
12041 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
12042 VT == MVT::v8i32 || VT == MVT::v16i16))) {
12044 EVT EltVT = VT.getVectorElementType();
12046 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12047 unsigned NumElts = VT.getVectorNumElements();
12049 for (i = 0; i != NumElts; ++i) {
12050 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
12054 for (j = i; j != NumElts; ++j) {
12055 SDValue Arg = Amt.getOperand(j);
12056 if (Arg.getOpcode() == ISD::UNDEF) continue;
12057 if (Arg != Amt.getOperand(i))
12060 if (i != NumElts && j == NumElts)
12061 BaseShAmt = Amt.getOperand(i);
12063 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
12064 Amt = Amt.getOperand(0);
12065 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
12066 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
12067 SDValue InVec = Amt.getOperand(0);
12068 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
12069 unsigned NumElts = InVec.getValueType().getVectorNumElements();
12071 for (; i != NumElts; ++i) {
12072 SDValue Arg = InVec.getOperand(i);
12073 if (Arg.getOpcode() == ISD::UNDEF) continue;
12077 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
12078 if (ConstantSDNode *C =
12079 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
12080 unsigned SplatIdx =
12081 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
12082 if (C->getZExtValue() == SplatIdx)
12083 BaseShAmt = InVec.getOperand(1);
12086 if (BaseShAmt.getNode() == 0)
12087 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
12088 DAG.getIntPtrConstant(0));
12092 if (BaseShAmt.getNode()) {
12093 if (EltVT.bitsGT(MVT::i32))
12094 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
12095 else if (EltVT.bitsLT(MVT::i32))
12096 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
12098 switch (Op.getOpcode()) {
12100 llvm_unreachable("Unknown shift opcode!");
12102 switch (VT.getSimpleVT().SimpleTy) {
12103 default: return SDValue();
12110 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
12113 switch (VT.getSimpleVT().SimpleTy) {
12114 default: return SDValue();
12119 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
12122 switch (VT.getSimpleVT().SimpleTy) {
12123 default: return SDValue();
12130 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
12136 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
12137 if (!Subtarget->is64Bit() &&
12138 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
12139 Amt.getOpcode() == ISD::BITCAST &&
12140 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
12141 Amt = Amt.getOperand(0);
12142 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
12143 VT.getVectorNumElements();
12144 std::vector<SDValue> Vals(Ratio);
12145 for (unsigned i = 0; i != Ratio; ++i)
12146 Vals[i] = Amt.getOperand(i);
12147 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
12148 for (unsigned j = 0; j != Ratio; ++j)
12149 if (Vals[j] != Amt.getOperand(i + j))
12152 switch (Op.getOpcode()) {
12154 llvm_unreachable("Unknown shift opcode!");
12156 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
12158 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
12160 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
12167 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
12169 EVT VT = Op.getValueType();
12171 SDValue R = Op.getOperand(0);
12172 SDValue Amt = Op.getOperand(1);
12175 if (!Subtarget->hasSSE2())
12178 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
12182 V = LowerScalarVariableShift(Op, DAG, Subtarget);
12186 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
12187 if (Subtarget->hasInt256()) {
12188 if (Op.getOpcode() == ISD::SRL &&
12189 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12190 VT == MVT::v4i64 || VT == MVT::v8i32))
12192 if (Op.getOpcode() == ISD::SHL &&
12193 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
12194 VT == MVT::v4i64 || VT == MVT::v8i32))
12196 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
12200 // Lower SHL with variable shift amount.
12201 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
12202 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
12204 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
12205 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
12206 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
12207 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
12209 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
12210 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
12213 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
12214 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
12216 // Turn 'a' into a mask suitable for VSELECT
12217 SDValue VSelM = DAG.getConstant(0x80, VT);
12218 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12219 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12221 SDValue CM1 = DAG.getConstant(0x0f, VT);
12222 SDValue CM2 = DAG.getConstant(0x3f, VT);
12224 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
12225 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
12226 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12227 DAG.getConstant(4, MVT::i32), DAG);
12228 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12229 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12232 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12233 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12234 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12236 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
12237 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
12238 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
12239 DAG.getConstant(2, MVT::i32), DAG);
12240 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
12241 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
12244 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
12245 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
12246 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
12248 // return VSELECT(r, r+r, a);
12249 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
12250 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
12254 // Decompose 256-bit shifts into smaller 128-bit shifts.
12255 if (VT.is256BitVector()) {
12256 unsigned NumElems = VT.getVectorNumElements();
12257 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12258 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12260 // Extract the two vectors
12261 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
12262 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
12264 // Recreate the shift amount vectors
12265 SDValue Amt1, Amt2;
12266 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
12267 // Constant shift amount
12268 SmallVector<SDValue, 4> Amt1Csts;
12269 SmallVector<SDValue, 4> Amt2Csts;
12270 for (unsigned i = 0; i != NumElems/2; ++i)
12271 Amt1Csts.push_back(Amt->getOperand(i));
12272 for (unsigned i = NumElems/2; i != NumElems; ++i)
12273 Amt2Csts.push_back(Amt->getOperand(i));
12275 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12276 &Amt1Csts[0], NumElems/2);
12277 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
12278 &Amt2Csts[0], NumElems/2);
12280 // Variable shift amount
12281 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
12282 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
12285 // Issue new vector shifts for the smaller types
12286 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
12287 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
12289 // Concatenate the result back
12290 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
12296 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
12297 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
12298 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
12299 // looks for this combo and may remove the "setcc" instruction if the "setcc"
12300 // has only one use.
12301 SDNode *N = Op.getNode();
12302 SDValue LHS = N->getOperand(0);
12303 SDValue RHS = N->getOperand(1);
12304 unsigned BaseOp = 0;
12307 switch (Op.getOpcode()) {
12308 default: llvm_unreachable("Unknown ovf instruction!");
12310 // A subtract of one will be selected as a INC. Note that INC doesn't
12311 // set CF, so we can't do this for UADDO.
12312 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12314 BaseOp = X86ISD::INC;
12315 Cond = X86::COND_O;
12318 BaseOp = X86ISD::ADD;
12319 Cond = X86::COND_O;
12322 BaseOp = X86ISD::ADD;
12323 Cond = X86::COND_B;
12326 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12327 // set CF, so we can't do this for USUBO.
12328 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12330 BaseOp = X86ISD::DEC;
12331 Cond = X86::COND_O;
12334 BaseOp = X86ISD::SUB;
12335 Cond = X86::COND_O;
12338 BaseOp = X86ISD::SUB;
12339 Cond = X86::COND_B;
12342 BaseOp = X86ISD::SMUL;
12343 Cond = X86::COND_O;
12345 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12346 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12348 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12351 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12352 DAG.getConstant(X86::COND_O, MVT::i32),
12353 SDValue(Sum.getNode(), 2));
12355 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12359 // Also sets EFLAGS.
12360 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12361 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
12364 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12365 DAG.getConstant(Cond, MVT::i32),
12366 SDValue(Sum.getNode(), 1));
12368 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12371 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
12372 SelectionDAG &DAG) const {
12374 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
12375 EVT VT = Op.getValueType();
12377 if (!Subtarget->hasSSE2() || !VT.isVector())
12380 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
12381 ExtraVT.getScalarType().getSizeInBits();
12382 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
12384 switch (VT.getSimpleVT().SimpleTy) {
12385 default: return SDValue();
12388 if (!Subtarget->hasFp256())
12390 if (!Subtarget->hasInt256()) {
12391 // needs to be split
12392 unsigned NumElems = VT.getVectorNumElements();
12394 // Extract the LHS vectors
12395 SDValue LHS = Op.getOperand(0);
12396 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12397 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12399 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12400 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12402 EVT ExtraEltVT = ExtraVT.getVectorElementType();
12403 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
12404 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
12406 SDValue Extra = DAG.getValueType(ExtraVT);
12408 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
12409 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
12411 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
12416 // (sext (vzext x)) -> (vsext x)
12417 SDValue Op0 = Op.getOperand(0);
12418 SDValue Op00 = Op0.getOperand(0);
12420 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
12421 if (Op0.getOpcode() == ISD::BITCAST &&
12422 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
12423 Tmp1 = LowerVectorIntExtend(Op00, DAG);
12424 if (Tmp1.getNode()) {
12425 SDValue Tmp1Op0 = Tmp1.getOperand(0);
12426 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
12427 "This optimization is invalid without a VZEXT.");
12428 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
12431 // If the above didn't work, then just use Shift-Left + Shift-Right.
12432 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
12433 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
12438 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
12439 SelectionDAG &DAG) {
12441 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
12442 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
12443 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
12444 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
12446 // The only fence that needs an instruction is a sequentially-consistent
12447 // cross-thread fence.
12448 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
12449 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
12450 // no-sse2). There isn't any reason to disable it if the target processor
12452 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
12453 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
12455 SDValue Chain = Op.getOperand(0);
12456 SDValue Zero = DAG.getConstant(0, MVT::i32);
12458 DAG.getRegister(X86::ESP, MVT::i32), // Base
12459 DAG.getTargetConstant(1, MVT::i8), // Scale
12460 DAG.getRegister(0, MVT::i32), // Index
12461 DAG.getTargetConstant(0, MVT::i32), // Disp
12462 DAG.getRegister(0, MVT::i32), // Segment.
12466 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
12467 return SDValue(Res, 0);
12470 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
12471 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
12474 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
12475 SelectionDAG &DAG) {
12476 EVT T = Op.getValueType();
12480 switch(T.getSimpleVT().SimpleTy) {
12481 default: llvm_unreachable("Invalid value type!");
12482 case MVT::i8: Reg = X86::AL; size = 1; break;
12483 case MVT::i16: Reg = X86::AX; size = 2; break;
12484 case MVT::i32: Reg = X86::EAX; size = 4; break;
12486 assert(Subtarget->is64Bit() && "Node not type legal!");
12487 Reg = X86::RAX; size = 8;
12490 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
12491 Op.getOperand(2), SDValue());
12492 SDValue Ops[] = { cpIn.getValue(0),
12495 DAG.getTargetConstant(size, MVT::i8),
12496 cpIn.getValue(1) };
12497 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12498 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
12499 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
12500 Ops, array_lengthof(Ops), T, MMO);
12502 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
12506 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
12507 SelectionDAG &DAG) {
12508 assert(Subtarget->is64Bit() && "Result not type legalized?");
12509 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12510 SDValue TheChain = Op.getOperand(0);
12512 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12513 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
12514 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
12516 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
12517 DAG.getConstant(32, MVT::i8));
12519 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
12522 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
12525 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
12526 EVT SrcVT = Op.getOperand(0).getValueType();
12527 EVT DstVT = Op.getValueType();
12528 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
12529 Subtarget->hasMMX() && "Unexpected custom BITCAST");
12530 assert((DstVT == MVT::i64 ||
12531 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
12532 "Unexpected custom BITCAST");
12533 // i64 <=> MMX conversions are Legal.
12534 if (SrcVT==MVT::i64 && DstVT.isVector())
12536 if (DstVT==MVT::i64 && SrcVT.isVector())
12538 // MMX <=> MMX conversions are Legal.
12539 if (SrcVT.isVector() && DstVT.isVector())
12541 // All other conversions need to be expanded.
12545 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
12546 SDNode *Node = Op.getNode();
12548 EVT T = Node->getValueType(0);
12549 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
12550 DAG.getConstant(0, T), Node->getOperand(2));
12551 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
12552 cast<AtomicSDNode>(Node)->getMemoryVT(),
12553 Node->getOperand(0),
12554 Node->getOperand(1), negOp,
12555 cast<AtomicSDNode>(Node)->getSrcValue(),
12556 cast<AtomicSDNode>(Node)->getAlignment(),
12557 cast<AtomicSDNode>(Node)->getOrdering(),
12558 cast<AtomicSDNode>(Node)->getSynchScope());
12561 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
12562 SDNode *Node = Op.getNode();
12564 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12566 // Convert seq_cst store -> xchg
12567 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
12568 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12569 // (The only way to get a 16-byte store is cmpxchg16b)
12570 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
12571 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
12572 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12573 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
12574 cast<AtomicSDNode>(Node)->getMemoryVT(),
12575 Node->getOperand(0),
12576 Node->getOperand(1), Node->getOperand(2),
12577 cast<AtomicSDNode>(Node)->getMemOperand(),
12578 cast<AtomicSDNode>(Node)->getOrdering(),
12579 cast<AtomicSDNode>(Node)->getSynchScope());
12580 return Swap.getValue(1);
12582 // Other atomic stores have a simple pattern.
12586 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
12587 EVT VT = Op.getNode()->getValueType(0);
12589 // Let legalize expand this if it isn't a legal type yet.
12590 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
12593 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12596 bool ExtraOp = false;
12597 switch (Op.getOpcode()) {
12598 default: llvm_unreachable("Invalid code");
12599 case ISD::ADDC: Opc = X86ISD::ADD; break;
12600 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12601 case ISD::SUBC: Opc = X86ISD::SUB; break;
12602 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12606 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
12608 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
12609 Op.getOperand(1), Op.getOperand(2));
12612 SDValue X86TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
12613 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
12615 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
12616 // which returns the values as { float, float } (in XMM0) or
12617 // { double, double } (which is returned in XMM0, XMM1).
12619 SDValue Arg = Op.getOperand(0);
12620 EVT ArgVT = Arg.getValueType();
12621 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
12624 ArgListEntry Entry;
12628 Entry.isSExt = false;
12629 Entry.isZExt = false;
12630 Args.push_back(Entry);
12632 bool isF64 = ArgVT == MVT::f64;
12633 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
12634 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12635 // the results are returned via SRet in memory.
12636 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
12637 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
12639 Type *RetTy = isF64
12640 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
12641 : (Type*)VectorType::get(ArgTy, 4);
12643 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
12644 false, false, false, false, 0,
12645 CallingConv::C, /*isTaillCall=*/false,
12646 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
12647 Callee, Args, DAG, dl);
12648 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
12651 // Returned in xmm0 and xmm1.
12652 return CallResult.first;
12654 // Returned in bits 0:31 and 32:64 xmm0.
12655 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12656 CallResult.first, DAG.getIntPtrConstant(0));
12657 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12658 CallResult.first, DAG.getIntPtrConstant(1));
12659 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
12660 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
12663 /// LowerOperation - Provide custom lowering hooks for some operations.
12665 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12666 switch (Op.getOpcode()) {
12667 default: llvm_unreachable("Should not custom lower this!");
12668 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12669 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12670 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12671 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12672 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12673 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12674 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12675 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12676 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12677 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12678 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12679 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12680 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12681 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12682 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12683 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12684 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12685 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12686 case ISD::SHL_PARTS:
12687 case ISD::SRA_PARTS:
12688 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12689 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12690 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12691 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
12692 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
12693 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
12694 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
12695 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12696 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12697 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
12698 case ISD::FABS: return LowerFABS(Op, DAG);
12699 case ISD::FNEG: return LowerFNEG(Op, DAG);
12700 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12701 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12702 case ISD::SETCC: return LowerSETCC(Op, DAG);
12703 case ISD::SELECT: return LowerSELECT(Op, DAG);
12704 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12705 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12706 case ISD::VASTART: return LowerVASTART(Op, DAG);
12707 case ISD::VAARG: return LowerVAARG(Op, DAG);
12708 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12709 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12710 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12711 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12712 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12713 case ISD::FRAME_TO_ARGS_OFFSET:
12714 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12715 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12716 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12717 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12718 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12719 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12720 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12721 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12722 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12723 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12724 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12725 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12728 case ISD::SHL: return LowerShift(Op, DAG);
12734 case ISD::UMULO: return LowerXALUO(Op, DAG);
12735 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12736 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
12740 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
12741 case ISD::ADD: return LowerADD(Op, DAG);
12742 case ISD::SUB: return LowerSUB(Op, DAG);
12743 case ISD::SDIV: return LowerSDIV(Op, DAG);
12744 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
12748 static void ReplaceATOMIC_LOAD(SDNode *Node,
12749 SmallVectorImpl<SDValue> &Results,
12750 SelectionDAG &DAG) {
12752 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12754 // Convert wide load -> cmpxchg8b/cmpxchg16b
12755 // FIXME: On 32-bit, load -> fild or movq would be more efficient
12756 // (The only way to get a 16-byte load is cmpxchg16b)
12757 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
12758 SDValue Zero = DAG.getConstant(0, VT);
12759 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
12760 Node->getOperand(0),
12761 Node->getOperand(1), Zero, Zero,
12762 cast<AtomicSDNode>(Node)->getMemOperand(),
12763 cast<AtomicSDNode>(Node)->getOrdering(),
12764 cast<AtomicSDNode>(Node)->getSynchScope());
12765 Results.push_back(Swap.getValue(0));
12766 Results.push_back(Swap.getValue(1));
12770 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
12771 SelectionDAG &DAG, unsigned NewOp) {
12773 assert (Node->getValueType(0) == MVT::i64 &&
12774 "Only know how to expand i64 atomics");
12776 SDValue Chain = Node->getOperand(0);
12777 SDValue In1 = Node->getOperand(1);
12778 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12779 Node->getOperand(2), DAG.getIntPtrConstant(0));
12780 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12781 Node->getOperand(2), DAG.getIntPtrConstant(1));
12782 SDValue Ops[] = { Chain, In1, In2L, In2H };
12783 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
12785 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
12786 cast<MemSDNode>(Node)->getMemOperand());
12787 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
12788 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12789 Results.push_back(Result.getValue(2));
12792 /// ReplaceNodeResults - Replace a node with an illegal result type
12793 /// with a new node built out of custom code.
12794 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
12795 SmallVectorImpl<SDValue>&Results,
12796 SelectionDAG &DAG) const {
12798 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12799 switch (N->getOpcode()) {
12801 llvm_unreachable("Do not know how to custom type legalize this operation!");
12802 case ISD::SIGN_EXTEND_INREG:
12807 // We don't want to expand or promote these.
12809 case ISD::FP_TO_SINT:
12810 case ISD::FP_TO_UINT: {
12811 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12813 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
12816 std::pair<SDValue,SDValue> Vals =
12817 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
12818 SDValue FIST = Vals.first, StackSlot = Vals.second;
12819 if (FIST.getNode() != 0) {
12820 EVT VT = N->getValueType(0);
12821 // Return a load from the stack slot.
12822 if (StackSlot.getNode() != 0)
12823 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
12824 MachinePointerInfo(),
12825 false, false, false, 0));
12827 Results.push_back(FIST);
12831 case ISD::UINT_TO_FP: {
12832 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
12833 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
12834 N->getValueType(0) != MVT::v2f32)
12836 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12838 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12840 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12841 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12842 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12843 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12844 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12845 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12848 case ISD::FP_ROUND: {
12849 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
12851 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
12852 Results.push_back(V);
12855 case ISD::READCYCLECOUNTER: {
12856 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12857 SDValue TheChain = N->getOperand(0);
12858 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12859 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12861 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12863 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12864 SDValue Ops[] = { eax, edx };
12865 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
12866 array_lengthof(Ops)));
12867 Results.push_back(edx.getValue(1));
12870 case ISD::ATOMIC_CMP_SWAP: {
12871 EVT T = N->getValueType(0);
12872 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
12873 bool Regs64bit = T == MVT::i128;
12874 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
12875 SDValue cpInL, cpInH;
12876 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12877 DAG.getConstant(0, HalfT));
12878 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12879 DAG.getConstant(1, HalfT));
12880 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
12881 Regs64bit ? X86::RAX : X86::EAX,
12883 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
12884 Regs64bit ? X86::RDX : X86::EDX,
12885 cpInH, cpInL.getValue(1));
12886 SDValue swapInL, swapInH;
12887 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12888 DAG.getConstant(0, HalfT));
12889 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12890 DAG.getConstant(1, HalfT));
12891 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
12892 Regs64bit ? X86::RBX : X86::EBX,
12893 swapInL, cpInH.getValue(1));
12894 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
12895 Regs64bit ? X86::RCX : X86::ECX,
12896 swapInH, swapInL.getValue(1));
12897 SDValue Ops[] = { swapInH.getValue(0),
12899 swapInH.getValue(1) };
12900 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12901 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
12902 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
12903 X86ISD::LCMPXCHG8_DAG;
12904 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
12905 Ops, array_lengthof(Ops), T, MMO);
12906 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
12907 Regs64bit ? X86::RAX : X86::EAX,
12908 HalfT, Result.getValue(1));
12909 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
12910 Regs64bit ? X86::RDX : X86::EDX,
12911 HalfT, cpOutL.getValue(2));
12912 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
12913 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
12914 Results.push_back(cpOutH.getValue(1));
12917 case ISD::ATOMIC_LOAD_ADD:
12918 case ISD::ATOMIC_LOAD_AND:
12919 case ISD::ATOMIC_LOAD_NAND:
12920 case ISD::ATOMIC_LOAD_OR:
12921 case ISD::ATOMIC_LOAD_SUB:
12922 case ISD::ATOMIC_LOAD_XOR:
12923 case ISD::ATOMIC_LOAD_MAX:
12924 case ISD::ATOMIC_LOAD_MIN:
12925 case ISD::ATOMIC_LOAD_UMAX:
12926 case ISD::ATOMIC_LOAD_UMIN:
12927 case ISD::ATOMIC_SWAP: {
12929 switch (N->getOpcode()) {
12930 default: llvm_unreachable("Unexpected opcode");
12931 case ISD::ATOMIC_LOAD_ADD:
12932 Opc = X86ISD::ATOMADD64_DAG;
12934 case ISD::ATOMIC_LOAD_AND:
12935 Opc = X86ISD::ATOMAND64_DAG;
12937 case ISD::ATOMIC_LOAD_NAND:
12938 Opc = X86ISD::ATOMNAND64_DAG;
12940 case ISD::ATOMIC_LOAD_OR:
12941 Opc = X86ISD::ATOMOR64_DAG;
12943 case ISD::ATOMIC_LOAD_SUB:
12944 Opc = X86ISD::ATOMSUB64_DAG;
12946 case ISD::ATOMIC_LOAD_XOR:
12947 Opc = X86ISD::ATOMXOR64_DAG;
12949 case ISD::ATOMIC_LOAD_MAX:
12950 Opc = X86ISD::ATOMMAX64_DAG;
12952 case ISD::ATOMIC_LOAD_MIN:
12953 Opc = X86ISD::ATOMMIN64_DAG;
12955 case ISD::ATOMIC_LOAD_UMAX:
12956 Opc = X86ISD::ATOMUMAX64_DAG;
12958 case ISD::ATOMIC_LOAD_UMIN:
12959 Opc = X86ISD::ATOMUMIN64_DAG;
12961 case ISD::ATOMIC_SWAP:
12962 Opc = X86ISD::ATOMSWAP64_DAG;
12965 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
12968 case ISD::ATOMIC_LOAD:
12969 ReplaceATOMIC_LOAD(N, Results, DAG);
12973 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
12975 default: return NULL;
12976 case X86ISD::BSF: return "X86ISD::BSF";
12977 case X86ISD::BSR: return "X86ISD::BSR";
12978 case X86ISD::SHLD: return "X86ISD::SHLD";
12979 case X86ISD::SHRD: return "X86ISD::SHRD";
12980 case X86ISD::FAND: return "X86ISD::FAND";
12981 case X86ISD::FOR: return "X86ISD::FOR";
12982 case X86ISD::FXOR: return "X86ISD::FXOR";
12983 case X86ISD::FSRL: return "X86ISD::FSRL";
12984 case X86ISD::FILD: return "X86ISD::FILD";
12985 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
12986 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
12987 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
12988 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
12989 case X86ISD::FLD: return "X86ISD::FLD";
12990 case X86ISD::FST: return "X86ISD::FST";
12991 case X86ISD::CALL: return "X86ISD::CALL";
12992 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
12993 case X86ISD::BT: return "X86ISD::BT";
12994 case X86ISD::CMP: return "X86ISD::CMP";
12995 case X86ISD::COMI: return "X86ISD::COMI";
12996 case X86ISD::UCOMI: return "X86ISD::UCOMI";
12997 case X86ISD::SETCC: return "X86ISD::SETCC";
12998 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
12999 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
13000 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
13001 case X86ISD::CMOV: return "X86ISD::CMOV";
13002 case X86ISD::BRCOND: return "X86ISD::BRCOND";
13003 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
13004 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
13005 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
13006 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
13007 case X86ISD::Wrapper: return "X86ISD::Wrapper";
13008 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
13009 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
13010 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
13011 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
13012 case X86ISD::PINSRB: return "X86ISD::PINSRB";
13013 case X86ISD::PINSRW: return "X86ISD::PINSRW";
13014 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
13015 case X86ISD::ANDNP: return "X86ISD::ANDNP";
13016 case X86ISD::PSIGN: return "X86ISD::PSIGN";
13017 case X86ISD::BLENDV: return "X86ISD::BLENDV";
13018 case X86ISD::BLENDI: return "X86ISD::BLENDI";
13019 case X86ISD::SUBUS: return "X86ISD::SUBUS";
13020 case X86ISD::HADD: return "X86ISD::HADD";
13021 case X86ISD::HSUB: return "X86ISD::HSUB";
13022 case X86ISD::FHADD: return "X86ISD::FHADD";
13023 case X86ISD::FHSUB: return "X86ISD::FHSUB";
13024 case X86ISD::UMAX: return "X86ISD::UMAX";
13025 case X86ISD::UMIN: return "X86ISD::UMIN";
13026 case X86ISD::SMAX: return "X86ISD::SMAX";
13027 case X86ISD::SMIN: return "X86ISD::SMIN";
13028 case X86ISD::FMAX: return "X86ISD::FMAX";
13029 case X86ISD::FMIN: return "X86ISD::FMIN";
13030 case X86ISD::FMAXC: return "X86ISD::FMAXC";
13031 case X86ISD::FMINC: return "X86ISD::FMINC";
13032 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
13033 case X86ISD::FRCP: return "X86ISD::FRCP";
13034 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
13035 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
13036 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
13037 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
13038 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
13039 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
13040 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
13041 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
13042 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
13043 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
13044 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
13045 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
13046 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
13047 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
13048 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
13049 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
13050 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
13051 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
13052 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
13053 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
13054 case X86ISD::VZEXT: return "X86ISD::VZEXT";
13055 case X86ISD::VSEXT: return "X86ISD::VSEXT";
13056 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
13057 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
13058 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
13059 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
13060 case X86ISD::VSHL: return "X86ISD::VSHL";
13061 case X86ISD::VSRL: return "X86ISD::VSRL";
13062 case X86ISD::VSRA: return "X86ISD::VSRA";
13063 case X86ISD::VSHLI: return "X86ISD::VSHLI";
13064 case X86ISD::VSRLI: return "X86ISD::VSRLI";
13065 case X86ISD::VSRAI: return "X86ISD::VSRAI";
13066 case X86ISD::CMPP: return "X86ISD::CMPP";
13067 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
13068 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
13069 case X86ISD::ADD: return "X86ISD::ADD";
13070 case X86ISD::SUB: return "X86ISD::SUB";
13071 case X86ISD::ADC: return "X86ISD::ADC";
13072 case X86ISD::SBB: return "X86ISD::SBB";
13073 case X86ISD::SMUL: return "X86ISD::SMUL";
13074 case X86ISD::UMUL: return "X86ISD::UMUL";
13075 case X86ISD::INC: return "X86ISD::INC";
13076 case X86ISD::DEC: return "X86ISD::DEC";
13077 case X86ISD::OR: return "X86ISD::OR";
13078 case X86ISD::XOR: return "X86ISD::XOR";
13079 case X86ISD::AND: return "X86ISD::AND";
13080 case X86ISD::BLSI: return "X86ISD::BLSI";
13081 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
13082 case X86ISD::BLSR: return "X86ISD::BLSR";
13083 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
13084 case X86ISD::PTEST: return "X86ISD::PTEST";
13085 case X86ISD::TESTP: return "X86ISD::TESTP";
13086 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
13087 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
13088 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
13089 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
13090 case X86ISD::SHUFP: return "X86ISD::SHUFP";
13091 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
13092 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
13093 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
13094 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
13095 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
13096 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
13097 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
13098 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
13099 case X86ISD::MOVSD: return "X86ISD::MOVSD";
13100 case X86ISD::MOVSS: return "X86ISD::MOVSS";
13101 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
13102 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
13103 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
13104 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
13105 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
13106 case X86ISD::VPERMV: return "X86ISD::VPERMV";
13107 case X86ISD::VPERMI: return "X86ISD::VPERMI";
13108 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
13109 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
13110 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
13111 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
13112 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
13113 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
13114 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
13115 case X86ISD::SAHF: return "X86ISD::SAHF";
13116 case X86ISD::RDRAND: return "X86ISD::RDRAND";
13117 case X86ISD::RDSEED: return "X86ISD::RDSEED";
13118 case X86ISD::FMADD: return "X86ISD::FMADD";
13119 case X86ISD::FMSUB: return "X86ISD::FMSUB";
13120 case X86ISD::FNMADD: return "X86ISD::FNMADD";
13121 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
13122 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
13123 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
13124 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
13125 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
13126 case X86ISD::XTEST: return "X86ISD::XTEST";
13130 // isLegalAddressingMode - Return true if the addressing mode represented
13131 // by AM is legal for this target, for a load/store of the specified type.
13132 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
13134 // X86 supports extremely general addressing modes.
13135 CodeModel::Model M = getTargetMachine().getCodeModel();
13136 Reloc::Model R = getTargetMachine().getRelocationModel();
13138 // X86 allows a sign-extended 32-bit immediate field as a displacement.
13139 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
13144 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
13146 // If a reference to this global requires an extra load, we can't fold it.
13147 if (isGlobalStubReference(GVFlags))
13150 // If BaseGV requires a register for the PIC base, we cannot also have a
13151 // BaseReg specified.
13152 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
13155 // If lower 4G is not available, then we must use rip-relative addressing.
13156 if ((M != CodeModel::Small || R != Reloc::Static) &&
13157 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
13161 switch (AM.Scale) {
13167 // These scales always work.
13172 // These scales are formed with basereg+scalereg. Only accept if there is
13177 default: // Other stuff never works.
13184 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
13185 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
13187 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
13188 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
13189 return NumBits1 > NumBits2;
13192 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
13193 return isInt<32>(Imm);
13196 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
13197 // Can also use sub to handle negated immediates.
13198 return isInt<32>(Imm);
13201 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
13202 if (!VT1.isInteger() || !VT2.isInteger())
13204 unsigned NumBits1 = VT1.getSizeInBits();
13205 unsigned NumBits2 = VT2.getSizeInBits();
13206 return NumBits1 > NumBits2;
13209 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
13210 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13211 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
13214 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
13215 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
13216 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
13219 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
13220 EVT VT1 = Val.getValueType();
13221 if (isZExtFree(VT1, VT2))
13224 if (Val.getOpcode() != ISD::LOAD)
13227 if (!VT1.isSimple() || !VT1.isInteger() ||
13228 !VT2.isSimple() || !VT2.isInteger())
13231 switch (VT1.getSimpleVT().SimpleTy) {
13236 // X86 has 8, 16, and 32-bit zero-extending loads.
13244 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
13245 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
13248 VT = VT.getScalarType();
13250 if (!VT.isSimple())
13253 switch (VT.getSimpleVT().SimpleTy) {
13264 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
13265 // i16 instructions are longer (0x66 prefix) and potentially slower.
13266 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
13269 /// isShuffleMaskLegal - Targets can use this to indicate that they only
13270 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
13271 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
13272 /// are assumed to be legal.
13274 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
13276 // Very little shuffling can be done for 64-bit vectors right now.
13277 if (VT.getSizeInBits() == 64)
13280 // FIXME: pshufb, blends, shifts.
13281 return (VT.getVectorNumElements() == 2 ||
13282 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
13283 isMOVLMask(M, VT) ||
13284 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
13285 isPSHUFDMask(M, VT) ||
13286 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
13287 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
13288 isPALIGNRMask(M, VT, Subtarget) ||
13289 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
13290 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
13291 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
13292 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
13296 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
13298 unsigned NumElts = VT.getVectorNumElements();
13299 // FIXME: This collection of masks seems suspect.
13302 if (NumElts == 4 && VT.is128BitVector()) {
13303 return (isMOVLMask(Mask, VT) ||
13304 isCommutedMOVLMask(Mask, VT, true) ||
13305 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
13306 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
13311 //===----------------------------------------------------------------------===//
13312 // X86 Scheduler Hooks
13313 //===----------------------------------------------------------------------===//
13315 /// Utility function to emit xbegin specifying the start of an RTM region.
13316 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
13317 const TargetInstrInfo *TII) {
13318 DebugLoc DL = MI->getDebugLoc();
13320 const BasicBlock *BB = MBB->getBasicBlock();
13321 MachineFunction::iterator I = MBB;
13324 // For the v = xbegin(), we generate
13335 MachineBasicBlock *thisMBB = MBB;
13336 MachineFunction *MF = MBB->getParent();
13337 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13338 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13339 MF->insert(I, mainMBB);
13340 MF->insert(I, sinkMBB);
13342 // Transfer the remainder of BB and its successor edges to sinkMBB.
13343 sinkMBB->splice(sinkMBB->begin(), MBB,
13344 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13345 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13349 // # fallthrough to mainMBB
13350 // # abortion to sinkMBB
13351 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
13352 thisMBB->addSuccessor(mainMBB);
13353 thisMBB->addSuccessor(sinkMBB);
13357 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
13358 mainMBB->addSuccessor(sinkMBB);
13361 // EAX is live into the sinkMBB
13362 sinkMBB->addLiveIn(X86::EAX);
13363 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13364 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13367 MI->eraseFromParent();
13371 // Get CMPXCHG opcode for the specified data type.
13372 static unsigned getCmpXChgOpcode(EVT VT) {
13373 switch (VT.getSimpleVT().SimpleTy) {
13374 case MVT::i8: return X86::LCMPXCHG8;
13375 case MVT::i16: return X86::LCMPXCHG16;
13376 case MVT::i32: return X86::LCMPXCHG32;
13377 case MVT::i64: return X86::LCMPXCHG64;
13381 llvm_unreachable("Invalid operand size!");
13384 // Get LOAD opcode for the specified data type.
13385 static unsigned getLoadOpcode(EVT VT) {
13386 switch (VT.getSimpleVT().SimpleTy) {
13387 case MVT::i8: return X86::MOV8rm;
13388 case MVT::i16: return X86::MOV16rm;
13389 case MVT::i32: return X86::MOV32rm;
13390 case MVT::i64: return X86::MOV64rm;
13394 llvm_unreachable("Invalid operand size!");
13397 // Get opcode of the non-atomic one from the specified atomic instruction.
13398 static unsigned getNonAtomicOpcode(unsigned Opc) {
13400 case X86::ATOMAND8: return X86::AND8rr;
13401 case X86::ATOMAND16: return X86::AND16rr;
13402 case X86::ATOMAND32: return X86::AND32rr;
13403 case X86::ATOMAND64: return X86::AND64rr;
13404 case X86::ATOMOR8: return X86::OR8rr;
13405 case X86::ATOMOR16: return X86::OR16rr;
13406 case X86::ATOMOR32: return X86::OR32rr;
13407 case X86::ATOMOR64: return X86::OR64rr;
13408 case X86::ATOMXOR8: return X86::XOR8rr;
13409 case X86::ATOMXOR16: return X86::XOR16rr;
13410 case X86::ATOMXOR32: return X86::XOR32rr;
13411 case X86::ATOMXOR64: return X86::XOR64rr;
13413 llvm_unreachable("Unhandled atomic-load-op opcode!");
13416 // Get opcode of the non-atomic one from the specified atomic instruction with
13418 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
13419 unsigned &ExtraOpc) {
13421 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
13422 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
13423 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
13424 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
13425 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
13426 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
13427 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
13428 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
13429 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
13430 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
13431 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
13432 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
13433 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
13434 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
13435 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
13436 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
13437 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
13438 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
13439 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
13440 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
13442 llvm_unreachable("Unhandled atomic-load-op opcode!");
13445 // Get opcode of the non-atomic one from the specified atomic instruction for
13446 // 64-bit data type on 32-bit target.
13447 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
13449 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
13450 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
13451 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
13452 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
13453 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
13454 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
13455 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
13456 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
13457 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
13458 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
13460 llvm_unreachable("Unhandled atomic-load-op opcode!");
13463 // Get opcode of the non-atomic one from the specified atomic instruction for
13464 // 64-bit data type on 32-bit target with extra opcode.
13465 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
13467 unsigned &ExtraOpc) {
13469 case X86::ATOMNAND6432:
13470 ExtraOpc = X86::NOT32r;
13471 HiOpc = X86::AND32rr;
13472 return X86::AND32rr;
13474 llvm_unreachable("Unhandled atomic-load-op opcode!");
13477 // Get pseudo CMOV opcode from the specified data type.
13478 static unsigned getPseudoCMOVOpc(EVT VT) {
13479 switch (VT.getSimpleVT().SimpleTy) {
13480 case MVT::i8: return X86::CMOV_GR8;
13481 case MVT::i16: return X86::CMOV_GR16;
13482 case MVT::i32: return X86::CMOV_GR32;
13486 llvm_unreachable("Unknown CMOV opcode!");
13489 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
13490 // They will be translated into a spin-loop or compare-exchange loop from
13493 // dst = atomic-fetch-op MI.addr, MI.val
13499 // t1 = LOAD MI.addr
13501 // t4 = phi(t1, t3 / loop)
13502 // t2 = OP MI.val, t4
13504 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
13510 MachineBasicBlock *
13511 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
13512 MachineBasicBlock *MBB) const {
13513 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13514 DebugLoc DL = MI->getDebugLoc();
13516 MachineFunction *MF = MBB->getParent();
13517 MachineRegisterInfo &MRI = MF->getRegInfo();
13519 const BasicBlock *BB = MBB->getBasicBlock();
13520 MachineFunction::iterator I = MBB;
13523 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
13524 "Unexpected number of operands");
13526 assert(MI->hasOneMemOperand() &&
13527 "Expected atomic-load-op to have one memoperand");
13529 // Memory Reference
13530 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13531 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13533 unsigned DstReg, SrcReg;
13534 unsigned MemOpndSlot;
13536 unsigned CurOp = 0;
13538 DstReg = MI->getOperand(CurOp++).getReg();
13539 MemOpndSlot = CurOp;
13540 CurOp += X86::AddrNumOperands;
13541 SrcReg = MI->getOperand(CurOp++).getReg();
13543 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
13544 MVT::SimpleValueType VT = *RC->vt_begin();
13545 unsigned t1 = MRI.createVirtualRegister(RC);
13546 unsigned t2 = MRI.createVirtualRegister(RC);
13547 unsigned t3 = MRI.createVirtualRegister(RC);
13548 unsigned t4 = MRI.createVirtualRegister(RC);
13549 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
13551 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
13552 unsigned LOADOpc = getLoadOpcode(VT);
13554 // For the atomic load-arith operator, we generate
13557 // t1 = LOAD [MI.addr]
13559 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
13560 // t1 = OP MI.val, EAX
13562 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
13568 MachineBasicBlock *thisMBB = MBB;
13569 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13570 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13571 MF->insert(I, mainMBB);
13572 MF->insert(I, sinkMBB);
13574 MachineInstrBuilder MIB;
13576 // Transfer the remainder of BB and its successor edges to sinkMBB.
13577 sinkMBB->splice(sinkMBB->begin(), MBB,
13578 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13579 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13582 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
13583 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13584 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13586 NewMO.setIsKill(false);
13587 MIB.addOperand(NewMO);
13589 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13590 unsigned flags = (*MMOI)->getFlags();
13591 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13592 MachineMemOperand *MMO =
13593 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13594 (*MMOI)->getSize(),
13595 (*MMOI)->getBaseAlignment(),
13596 (*MMOI)->getTBAAInfo(),
13597 (*MMOI)->getRanges());
13598 MIB.addMemOperand(MMO);
13601 thisMBB->addSuccessor(mainMBB);
13604 MachineBasicBlock *origMainMBB = mainMBB;
13607 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
13608 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13610 unsigned Opc = MI->getOpcode();
13613 llvm_unreachable("Unhandled atomic-load-op opcode!");
13614 case X86::ATOMAND8:
13615 case X86::ATOMAND16:
13616 case X86::ATOMAND32:
13617 case X86::ATOMAND64:
13619 case X86::ATOMOR16:
13620 case X86::ATOMOR32:
13621 case X86::ATOMOR64:
13622 case X86::ATOMXOR8:
13623 case X86::ATOMXOR16:
13624 case X86::ATOMXOR32:
13625 case X86::ATOMXOR64: {
13626 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
13627 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
13631 case X86::ATOMNAND8:
13632 case X86::ATOMNAND16:
13633 case X86::ATOMNAND32:
13634 case X86::ATOMNAND64: {
13635 unsigned Tmp = MRI.createVirtualRegister(RC);
13637 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
13638 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
13640 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
13643 case X86::ATOMMAX8:
13644 case X86::ATOMMAX16:
13645 case X86::ATOMMAX32:
13646 case X86::ATOMMAX64:
13647 case X86::ATOMMIN8:
13648 case X86::ATOMMIN16:
13649 case X86::ATOMMIN32:
13650 case X86::ATOMMIN64:
13651 case X86::ATOMUMAX8:
13652 case X86::ATOMUMAX16:
13653 case X86::ATOMUMAX32:
13654 case X86::ATOMUMAX64:
13655 case X86::ATOMUMIN8:
13656 case X86::ATOMUMIN16:
13657 case X86::ATOMUMIN32:
13658 case X86::ATOMUMIN64: {
13660 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
13662 BuildMI(mainMBB, DL, TII->get(CMPOpc))
13666 if (Subtarget->hasCMov()) {
13667 if (VT != MVT::i8) {
13669 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
13673 // Promote i8 to i32 to use CMOV32
13674 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13675 const TargetRegisterClass *RC32 =
13676 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
13677 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
13678 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
13679 unsigned Tmp = MRI.createVirtualRegister(RC32);
13681 unsigned Undef = MRI.createVirtualRegister(RC32);
13682 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
13684 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
13687 .addImm(X86::sub_8bit);
13688 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
13691 .addImm(X86::sub_8bit);
13693 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
13697 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
13698 .addReg(Tmp, 0, X86::sub_8bit);
13701 // Use pseudo select and lower them.
13702 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
13703 "Invalid atomic-load-op transformation!");
13704 unsigned SelOpc = getPseudoCMOVOpc(VT);
13705 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
13706 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
13707 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
13708 .addReg(SrcReg).addReg(t4)
13710 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13711 // Replace the original PHI node as mainMBB is changed after CMOV
13713 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
13714 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13715 Phi->eraseFromParent();
13721 // Copy PhyReg back from virtual register.
13722 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
13725 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13726 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13727 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13729 NewMO.setIsKill(false);
13730 MIB.addOperand(NewMO);
13733 MIB.setMemRefs(MMOBegin, MMOEnd);
13735 // Copy PhyReg back to virtual register.
13736 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
13739 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13741 mainMBB->addSuccessor(origMainMBB);
13742 mainMBB->addSuccessor(sinkMBB);
13745 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13746 TII->get(TargetOpcode::COPY), DstReg)
13749 MI->eraseFromParent();
13753 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
13754 // instructions. They will be translated into a spin-loop or compare-exchange
13758 // dst = atomic-fetch-op MI.addr, MI.val
13764 // t1L = LOAD [MI.addr + 0]
13765 // t1H = LOAD [MI.addr + 4]
13767 // t4L = phi(t1L, t3L / loop)
13768 // t4H = phi(t1H, t3H / loop)
13769 // t2L = OP MI.val.lo, t4L
13770 // t2H = OP MI.val.hi, t4H
13775 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13783 MachineBasicBlock *
13784 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
13785 MachineBasicBlock *MBB) const {
13786 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13787 DebugLoc DL = MI->getDebugLoc();
13789 MachineFunction *MF = MBB->getParent();
13790 MachineRegisterInfo &MRI = MF->getRegInfo();
13792 const BasicBlock *BB = MBB->getBasicBlock();
13793 MachineFunction::iterator I = MBB;
13796 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
13797 "Unexpected number of operands");
13799 assert(MI->hasOneMemOperand() &&
13800 "Expected atomic-load-op32 to have one memoperand");
13802 // Memory Reference
13803 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13804 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13806 unsigned DstLoReg, DstHiReg;
13807 unsigned SrcLoReg, SrcHiReg;
13808 unsigned MemOpndSlot;
13810 unsigned CurOp = 0;
13812 DstLoReg = MI->getOperand(CurOp++).getReg();
13813 DstHiReg = MI->getOperand(CurOp++).getReg();
13814 MemOpndSlot = CurOp;
13815 CurOp += X86::AddrNumOperands;
13816 SrcLoReg = MI->getOperand(CurOp++).getReg();
13817 SrcHiReg = MI->getOperand(CurOp++).getReg();
13819 const TargetRegisterClass *RC = &X86::GR32RegClass;
13820 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
13822 unsigned t1L = MRI.createVirtualRegister(RC);
13823 unsigned t1H = MRI.createVirtualRegister(RC);
13824 unsigned t2L = MRI.createVirtualRegister(RC);
13825 unsigned t2H = MRI.createVirtualRegister(RC);
13826 unsigned t3L = MRI.createVirtualRegister(RC);
13827 unsigned t3H = MRI.createVirtualRegister(RC);
13828 unsigned t4L = MRI.createVirtualRegister(RC);
13829 unsigned t4H = MRI.createVirtualRegister(RC);
13831 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
13832 unsigned LOADOpc = X86::MOV32rm;
13834 // For the atomic load-arith operator, we generate
13837 // t1L = LOAD [MI.addr + 0]
13838 // t1H = LOAD [MI.addr + 4]
13840 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
13841 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
13842 // t2L = OP MI.val.lo, t4L
13843 // t2H = OP MI.val.hi, t4H
13846 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13854 MachineBasicBlock *thisMBB = MBB;
13855 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13856 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13857 MF->insert(I, mainMBB);
13858 MF->insert(I, sinkMBB);
13860 MachineInstrBuilder MIB;
13862 // Transfer the remainder of BB and its successor edges to sinkMBB.
13863 sinkMBB->splice(sinkMBB->begin(), MBB,
13864 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13865 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13869 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
13870 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13871 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13873 NewMO.setIsKill(false);
13874 MIB.addOperand(NewMO);
13876 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13877 unsigned flags = (*MMOI)->getFlags();
13878 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13879 MachineMemOperand *MMO =
13880 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13881 (*MMOI)->getSize(),
13882 (*MMOI)->getBaseAlignment(),
13883 (*MMOI)->getTBAAInfo(),
13884 (*MMOI)->getRanges());
13885 MIB.addMemOperand(MMO);
13887 MachineInstr *LowMI = MIB;
13890 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
13891 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13892 if (i == X86::AddrDisp) {
13893 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
13895 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13897 NewMO.setIsKill(false);
13898 MIB.addOperand(NewMO);
13901 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
13903 thisMBB->addSuccessor(mainMBB);
13906 MachineBasicBlock *origMainMBB = mainMBB;
13909 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
13910 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
13911 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
13912 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
13914 unsigned Opc = MI->getOpcode();
13917 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
13918 case X86::ATOMAND6432:
13919 case X86::ATOMOR6432:
13920 case X86::ATOMXOR6432:
13921 case X86::ATOMADD6432:
13922 case X86::ATOMSUB6432: {
13924 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13925 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
13927 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
13931 case X86::ATOMNAND6432: {
13932 unsigned HiOpc, NOTOpc;
13933 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
13934 unsigned TmpL = MRI.createVirtualRegister(RC);
13935 unsigned TmpH = MRI.createVirtualRegister(RC);
13936 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
13938 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
13940 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
13941 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
13944 case X86::ATOMMAX6432:
13945 case X86::ATOMMIN6432:
13946 case X86::ATOMUMAX6432:
13947 case X86::ATOMUMIN6432: {
13949 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13950 unsigned cL = MRI.createVirtualRegister(RC8);
13951 unsigned cH = MRI.createVirtualRegister(RC8);
13952 unsigned cL32 = MRI.createVirtualRegister(RC);
13953 unsigned cH32 = MRI.createVirtualRegister(RC);
13954 unsigned cc = MRI.createVirtualRegister(RC);
13955 // cl := cmp src_lo, lo
13956 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13957 .addReg(SrcLoReg).addReg(t4L);
13958 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
13959 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
13960 // ch := cmp src_hi, hi
13961 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13962 .addReg(SrcHiReg).addReg(t4H);
13963 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
13964 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
13965 // cc := if (src_hi == hi) ? cl : ch;
13966 if (Subtarget->hasCMov()) {
13967 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
13968 .addReg(cH32).addReg(cL32);
13970 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
13971 .addReg(cH32).addReg(cL32)
13972 .addImm(X86::COND_E);
13973 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13975 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
13976 if (Subtarget->hasCMov()) {
13977 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
13978 .addReg(SrcLoReg).addReg(t4L);
13979 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
13980 .addReg(SrcHiReg).addReg(t4H);
13982 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
13983 .addReg(SrcLoReg).addReg(t4L)
13984 .addImm(X86::COND_NE);
13985 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13986 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
13987 // 2nd CMOV lowering.
13988 mainMBB->addLiveIn(X86::EFLAGS);
13989 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
13990 .addReg(SrcHiReg).addReg(t4H)
13991 .addImm(X86::COND_NE);
13992 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13993 // Replace the original PHI node as mainMBB is changed after CMOV
13995 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
13996 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
13997 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
13998 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
13999 PhiL->eraseFromParent();
14000 PhiH->eraseFromParent();
14004 case X86::ATOMSWAP6432: {
14006 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
14007 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
14008 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
14013 // Copy EDX:EAX back from HiReg:LoReg
14014 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
14015 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
14016 // Copy ECX:EBX from t1H:t1L
14017 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
14018 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
14020 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
14021 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14022 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
14024 NewMO.setIsKill(false);
14025 MIB.addOperand(NewMO);
14027 MIB.setMemRefs(MMOBegin, MMOEnd);
14029 // Copy EDX:EAX back to t3H:t3L
14030 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
14031 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
14033 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
14035 mainMBB->addSuccessor(origMainMBB);
14036 mainMBB->addSuccessor(sinkMBB);
14039 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14040 TII->get(TargetOpcode::COPY), DstLoReg)
14042 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14043 TII->get(TargetOpcode::COPY), DstHiReg)
14046 MI->eraseFromParent();
14050 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
14051 // or XMM0_V32I8 in AVX all of this code can be replaced with that
14052 // in the .td file.
14053 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
14054 const TargetInstrInfo *TII) {
14056 switch (MI->getOpcode()) {
14057 default: llvm_unreachable("illegal opcode!");
14058 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
14059 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
14060 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
14061 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
14062 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
14063 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
14064 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
14065 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
14068 DebugLoc dl = MI->getDebugLoc();
14069 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14071 unsigned NumArgs = MI->getNumOperands();
14072 for (unsigned i = 1; i < NumArgs; ++i) {
14073 MachineOperand &Op = MI->getOperand(i);
14074 if (!(Op.isReg() && Op.isImplicit()))
14075 MIB.addOperand(Op);
14077 if (MI->hasOneMemOperand())
14078 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14080 BuildMI(*BB, MI, dl,
14081 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14082 .addReg(X86::XMM0);
14084 MI->eraseFromParent();
14088 // FIXME: Custom handling because TableGen doesn't support multiple implicit
14089 // defs in an instruction pattern
14090 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
14091 const TargetInstrInfo *TII) {
14093 switch (MI->getOpcode()) {
14094 default: llvm_unreachable("illegal opcode!");
14095 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
14096 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
14097 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
14098 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
14099 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
14100 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
14101 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
14102 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
14105 DebugLoc dl = MI->getDebugLoc();
14106 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
14108 unsigned NumArgs = MI->getNumOperands(); // remove the results
14109 for (unsigned i = 1; i < NumArgs; ++i) {
14110 MachineOperand &Op = MI->getOperand(i);
14111 if (!(Op.isReg() && Op.isImplicit()))
14112 MIB.addOperand(Op);
14114 if (MI->hasOneMemOperand())
14115 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
14117 BuildMI(*BB, MI, dl,
14118 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
14121 MI->eraseFromParent();
14125 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
14126 const TargetInstrInfo *TII,
14127 const X86Subtarget* Subtarget) {
14128 DebugLoc dl = MI->getDebugLoc();
14130 // Address into RAX/EAX, other two args into ECX, EDX.
14131 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
14132 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
14133 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
14134 for (int i = 0; i < X86::AddrNumOperands; ++i)
14135 MIB.addOperand(MI->getOperand(i));
14137 unsigned ValOps = X86::AddrNumOperands;
14138 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
14139 .addReg(MI->getOperand(ValOps).getReg());
14140 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
14141 .addReg(MI->getOperand(ValOps+1).getReg());
14143 // The instruction doesn't actually take any operands though.
14144 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
14146 MI->eraseFromParent(); // The pseudo is gone now.
14150 MachineBasicBlock *
14151 X86TargetLowering::EmitVAARG64WithCustomInserter(
14153 MachineBasicBlock *MBB) const {
14154 // Emit va_arg instruction on X86-64.
14156 // Operands to this pseudo-instruction:
14157 // 0 ) Output : destination address (reg)
14158 // 1-5) Input : va_list address (addr, i64mem)
14159 // 6 ) ArgSize : Size (in bytes) of vararg type
14160 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
14161 // 8 ) Align : Alignment of type
14162 // 9 ) EFLAGS (implicit-def)
14164 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
14165 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
14167 unsigned DestReg = MI->getOperand(0).getReg();
14168 MachineOperand &Base = MI->getOperand(1);
14169 MachineOperand &Scale = MI->getOperand(2);
14170 MachineOperand &Index = MI->getOperand(3);
14171 MachineOperand &Disp = MI->getOperand(4);
14172 MachineOperand &Segment = MI->getOperand(5);
14173 unsigned ArgSize = MI->getOperand(6).getImm();
14174 unsigned ArgMode = MI->getOperand(7).getImm();
14175 unsigned Align = MI->getOperand(8).getImm();
14177 // Memory Reference
14178 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
14179 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14180 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14182 // Machine Information
14183 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14184 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
14185 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
14186 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
14187 DebugLoc DL = MI->getDebugLoc();
14189 // struct va_list {
14192 // i64 overflow_area (address)
14193 // i64 reg_save_area (address)
14195 // sizeof(va_list) = 24
14196 // alignment(va_list) = 8
14198 unsigned TotalNumIntRegs = 6;
14199 unsigned TotalNumXMMRegs = 8;
14200 bool UseGPOffset = (ArgMode == 1);
14201 bool UseFPOffset = (ArgMode == 2);
14202 unsigned MaxOffset = TotalNumIntRegs * 8 +
14203 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
14205 /* Align ArgSize to a multiple of 8 */
14206 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
14207 bool NeedsAlign = (Align > 8);
14209 MachineBasicBlock *thisMBB = MBB;
14210 MachineBasicBlock *overflowMBB;
14211 MachineBasicBlock *offsetMBB;
14212 MachineBasicBlock *endMBB;
14214 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
14215 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
14216 unsigned OffsetReg = 0;
14218 if (!UseGPOffset && !UseFPOffset) {
14219 // If we only pull from the overflow region, we don't create a branch.
14220 // We don't need to alter control flow.
14221 OffsetDestReg = 0; // unused
14222 OverflowDestReg = DestReg;
14225 overflowMBB = thisMBB;
14228 // First emit code to check if gp_offset (or fp_offset) is below the bound.
14229 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
14230 // If not, pull from overflow_area. (branch to overflowMBB)
14235 // offsetMBB overflowMBB
14240 // Registers for the PHI in endMBB
14241 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
14242 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
14244 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14245 MachineFunction *MF = MBB->getParent();
14246 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14247 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14248 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14250 MachineFunction::iterator MBBIter = MBB;
14253 // Insert the new basic blocks
14254 MF->insert(MBBIter, offsetMBB);
14255 MF->insert(MBBIter, overflowMBB);
14256 MF->insert(MBBIter, endMBB);
14258 // Transfer the remainder of MBB and its successor edges to endMBB.
14259 endMBB->splice(endMBB->begin(), thisMBB,
14260 llvm::next(MachineBasicBlock::iterator(MI)),
14262 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
14264 // Make offsetMBB and overflowMBB successors of thisMBB
14265 thisMBB->addSuccessor(offsetMBB);
14266 thisMBB->addSuccessor(overflowMBB);
14268 // endMBB is a successor of both offsetMBB and overflowMBB
14269 offsetMBB->addSuccessor(endMBB);
14270 overflowMBB->addSuccessor(endMBB);
14272 // Load the offset value into a register
14273 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14274 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
14278 .addDisp(Disp, UseFPOffset ? 4 : 0)
14279 .addOperand(Segment)
14280 .setMemRefs(MMOBegin, MMOEnd);
14282 // Check if there is enough room left to pull this argument.
14283 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
14285 .addImm(MaxOffset + 8 - ArgSizeA8);
14287 // Branch to "overflowMBB" if offset >= max
14288 // Fall through to "offsetMBB" otherwise
14289 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
14290 .addMBB(overflowMBB);
14293 // In offsetMBB, emit code to use the reg_save_area.
14295 assert(OffsetReg != 0);
14297 // Read the reg_save_area address.
14298 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
14299 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
14304 .addOperand(Segment)
14305 .setMemRefs(MMOBegin, MMOEnd);
14307 // Zero-extend the offset
14308 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
14309 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
14312 .addImm(X86::sub_32bit);
14314 // Add the offset to the reg_save_area to get the final address.
14315 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
14316 .addReg(OffsetReg64)
14317 .addReg(RegSaveReg);
14319 // Compute the offset for the next argument
14320 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
14321 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
14323 .addImm(UseFPOffset ? 16 : 8);
14325 // Store it back into the va_list.
14326 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
14330 .addDisp(Disp, UseFPOffset ? 4 : 0)
14331 .addOperand(Segment)
14332 .addReg(NextOffsetReg)
14333 .setMemRefs(MMOBegin, MMOEnd);
14336 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
14341 // Emit code to use overflow area
14344 // Load the overflow_area address into a register.
14345 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
14346 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
14351 .addOperand(Segment)
14352 .setMemRefs(MMOBegin, MMOEnd);
14354 // If we need to align it, do so. Otherwise, just copy the address
14355 // to OverflowDestReg.
14357 // Align the overflow address
14358 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
14359 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
14361 // aligned_addr = (addr + (align-1)) & ~(align-1)
14362 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
14363 .addReg(OverflowAddrReg)
14366 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
14368 .addImm(~(uint64_t)(Align-1));
14370 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
14371 .addReg(OverflowAddrReg);
14374 // Compute the next overflow address after this argument.
14375 // (the overflow address should be kept 8-byte aligned)
14376 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
14377 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
14378 .addReg(OverflowDestReg)
14379 .addImm(ArgSizeA8);
14381 // Store the new overflow address.
14382 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
14387 .addOperand(Segment)
14388 .addReg(NextAddrReg)
14389 .setMemRefs(MMOBegin, MMOEnd);
14391 // If we branched, emit the PHI to the front of endMBB.
14393 BuildMI(*endMBB, endMBB->begin(), DL,
14394 TII->get(X86::PHI), DestReg)
14395 .addReg(OffsetDestReg).addMBB(offsetMBB)
14396 .addReg(OverflowDestReg).addMBB(overflowMBB);
14399 // Erase the pseudo instruction
14400 MI->eraseFromParent();
14405 MachineBasicBlock *
14406 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
14408 MachineBasicBlock *MBB) const {
14409 // Emit code to save XMM registers to the stack. The ABI says that the
14410 // number of registers to save is given in %al, so it's theoretically
14411 // possible to do an indirect jump trick to avoid saving all of them,
14412 // however this code takes a simpler approach and just executes all
14413 // of the stores if %al is non-zero. It's less code, and it's probably
14414 // easier on the hardware branch predictor, and stores aren't all that
14415 // expensive anyway.
14417 // Create the new basic blocks. One block contains all the XMM stores,
14418 // and one block is the final destination regardless of whether any
14419 // stores were performed.
14420 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14421 MachineFunction *F = MBB->getParent();
14422 MachineFunction::iterator MBBIter = MBB;
14424 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
14425 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
14426 F->insert(MBBIter, XMMSaveMBB);
14427 F->insert(MBBIter, EndMBB);
14429 // Transfer the remainder of MBB and its successor edges to EndMBB.
14430 EndMBB->splice(EndMBB->begin(), MBB,
14431 llvm::next(MachineBasicBlock::iterator(MI)),
14433 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
14435 // The original block will now fall through to the XMM save block.
14436 MBB->addSuccessor(XMMSaveMBB);
14437 // The XMMSaveMBB will fall through to the end block.
14438 XMMSaveMBB->addSuccessor(EndMBB);
14440 // Now add the instructions.
14441 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14442 DebugLoc DL = MI->getDebugLoc();
14444 unsigned CountReg = MI->getOperand(0).getReg();
14445 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
14446 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
14448 if (!Subtarget->isTargetWin64()) {
14449 // If %al is 0, branch around the XMM save block.
14450 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
14451 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
14452 MBB->addSuccessor(EndMBB);
14455 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
14456 // In the XMM save block, save all the XMM argument registers.
14457 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
14458 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
14459 MachineMemOperand *MMO =
14460 F->getMachineMemOperand(
14461 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
14462 MachineMemOperand::MOStore,
14463 /*Size=*/16, /*Align=*/16);
14464 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
14465 .addFrameIndex(RegSaveFrameIndex)
14466 .addImm(/*Scale=*/1)
14467 .addReg(/*IndexReg=*/0)
14468 .addImm(/*Disp=*/Offset)
14469 .addReg(/*Segment=*/0)
14470 .addReg(MI->getOperand(i).getReg())
14471 .addMemOperand(MMO);
14474 MI->eraseFromParent(); // The pseudo instruction is gone now.
14479 // The EFLAGS operand of SelectItr might be missing a kill marker
14480 // because there were multiple uses of EFLAGS, and ISel didn't know
14481 // which to mark. Figure out whether SelectItr should have had a
14482 // kill marker, and set it if it should. Returns the correct kill
14484 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
14485 MachineBasicBlock* BB,
14486 const TargetRegisterInfo* TRI) {
14487 // Scan forward through BB for a use/def of EFLAGS.
14488 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
14489 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
14490 const MachineInstr& mi = *miI;
14491 if (mi.readsRegister(X86::EFLAGS))
14493 if (mi.definesRegister(X86::EFLAGS))
14494 break; // Should have kill-flag - update below.
14497 // If we hit the end of the block, check whether EFLAGS is live into a
14499 if (miI == BB->end()) {
14500 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
14501 sEnd = BB->succ_end();
14502 sItr != sEnd; ++sItr) {
14503 MachineBasicBlock* succ = *sItr;
14504 if (succ->isLiveIn(X86::EFLAGS))
14509 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
14510 // out. SelectMI should have a kill flag on EFLAGS.
14511 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
14515 MachineBasicBlock *
14516 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
14517 MachineBasicBlock *BB) const {
14518 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14519 DebugLoc DL = MI->getDebugLoc();
14521 // To "insert" a SELECT_CC instruction, we actually have to insert the
14522 // diamond control-flow pattern. The incoming instruction knows the
14523 // destination vreg to set, the condition code register to branch on, the
14524 // true/false values to select between, and a branch opcode to use.
14525 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14526 MachineFunction::iterator It = BB;
14532 // cmpTY ccX, r1, r2
14534 // fallthrough --> copy0MBB
14535 MachineBasicBlock *thisMBB = BB;
14536 MachineFunction *F = BB->getParent();
14537 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
14538 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
14539 F->insert(It, copy0MBB);
14540 F->insert(It, sinkMBB);
14542 // If the EFLAGS register isn't dead in the terminator, then claim that it's
14543 // live into the sink and copy blocks.
14544 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14545 if (!MI->killsRegister(X86::EFLAGS) &&
14546 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
14547 copy0MBB->addLiveIn(X86::EFLAGS);
14548 sinkMBB->addLiveIn(X86::EFLAGS);
14551 // Transfer the remainder of BB and its successor edges to sinkMBB.
14552 sinkMBB->splice(sinkMBB->begin(), BB,
14553 llvm::next(MachineBasicBlock::iterator(MI)),
14555 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
14557 // Add the true and fallthrough blocks as its successors.
14558 BB->addSuccessor(copy0MBB);
14559 BB->addSuccessor(sinkMBB);
14561 // Create the conditional branch instruction.
14563 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
14564 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
14567 // %FalseValue = ...
14568 // # fallthrough to sinkMBB
14569 copy0MBB->addSuccessor(sinkMBB);
14572 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
14574 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14575 TII->get(X86::PHI), MI->getOperand(0).getReg())
14576 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
14577 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
14579 MI->eraseFromParent(); // The pseudo instruction is gone now.
14583 MachineBasicBlock *
14584 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
14585 bool Is64Bit) const {
14586 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14587 DebugLoc DL = MI->getDebugLoc();
14588 MachineFunction *MF = BB->getParent();
14589 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14591 assert(getTargetMachine().Options.EnableSegmentedStacks);
14593 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
14594 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
14597 // ... [Till the alloca]
14598 // If stacklet is not large enough, jump to mallocMBB
14601 // Allocate by subtracting from RSP
14602 // Jump to continueMBB
14605 // Allocate by call to runtime
14609 // [rest of original BB]
14612 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14613 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14614 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14616 MachineRegisterInfo &MRI = MF->getRegInfo();
14617 const TargetRegisterClass *AddrRegClass =
14618 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
14620 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14621 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14622 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
14623 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
14624 sizeVReg = MI->getOperand(1).getReg(),
14625 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
14627 MachineFunction::iterator MBBIter = BB;
14630 MF->insert(MBBIter, bumpMBB);
14631 MF->insert(MBBIter, mallocMBB);
14632 MF->insert(MBBIter, continueMBB);
14634 continueMBB->splice(continueMBB->begin(), BB, llvm::next
14635 (MachineBasicBlock::iterator(MI)), BB->end());
14636 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
14638 // Add code to the main basic block to check if the stack limit has been hit,
14639 // and if so, jump to mallocMBB otherwise to bumpMBB.
14640 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
14641 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
14642 .addReg(tmpSPVReg).addReg(sizeVReg);
14643 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
14644 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
14645 .addReg(SPLimitVReg);
14646 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
14648 // bumpMBB simply decreases the stack pointer, since we know the current
14649 // stacklet has enough space.
14650 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
14651 .addReg(SPLimitVReg);
14652 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
14653 .addReg(SPLimitVReg);
14654 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14656 // Calls into a routine in libgcc to allocate more space from the heap.
14657 const uint32_t *RegMask =
14658 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14660 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
14662 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
14663 .addExternalSymbol("__morestack_allocate_stack_space")
14664 .addRegMask(RegMask)
14665 .addReg(X86::RDI, RegState::Implicit)
14666 .addReg(X86::RAX, RegState::ImplicitDefine);
14668 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
14670 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
14671 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
14672 .addExternalSymbol("__morestack_allocate_stack_space")
14673 .addRegMask(RegMask)
14674 .addReg(X86::EAX, RegState::ImplicitDefine);
14678 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
14681 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
14682 .addReg(Is64Bit ? X86::RAX : X86::EAX);
14683 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14685 // Set up the CFG correctly.
14686 BB->addSuccessor(bumpMBB);
14687 BB->addSuccessor(mallocMBB);
14688 mallocMBB->addSuccessor(continueMBB);
14689 bumpMBB->addSuccessor(continueMBB);
14691 // Take care of the PHI nodes.
14692 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
14693 MI->getOperand(0).getReg())
14694 .addReg(mallocPtrVReg).addMBB(mallocMBB)
14695 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
14697 // Delete the original pseudo instruction.
14698 MI->eraseFromParent();
14701 return continueMBB;
14704 MachineBasicBlock *
14705 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
14706 MachineBasicBlock *BB) const {
14707 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14708 DebugLoc DL = MI->getDebugLoc();
14710 assert(!Subtarget->isTargetEnvMacho());
14712 // The lowering is pretty easy: we're just emitting the call to _alloca. The
14713 // non-trivial part is impdef of ESP.
14715 if (Subtarget->isTargetWin64()) {
14716 if (Subtarget->isTargetCygMing()) {
14717 // ___chkstk(Mingw64):
14718 // Clobbers R10, R11, RAX and EFLAGS.
14720 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14721 .addExternalSymbol("___chkstk")
14722 .addReg(X86::RAX, RegState::Implicit)
14723 .addReg(X86::RSP, RegState::Implicit)
14724 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
14725 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
14726 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14728 // __chkstk(MSVCRT): does not update stack pointer.
14729 // Clobbers R10, R11 and EFLAGS.
14730 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14731 .addExternalSymbol("__chkstk")
14732 .addReg(X86::RAX, RegState::Implicit)
14733 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14734 // RAX has the offset to be subtracted from RSP.
14735 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
14740 const char *StackProbeSymbol =
14741 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
14743 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
14744 .addExternalSymbol(StackProbeSymbol)
14745 .addReg(X86::EAX, RegState::Implicit)
14746 .addReg(X86::ESP, RegState::Implicit)
14747 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
14748 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
14749 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14752 MI->eraseFromParent(); // The pseudo instruction is gone now.
14756 MachineBasicBlock *
14757 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
14758 MachineBasicBlock *BB) const {
14759 // This is pretty easy. We're taking the value that we received from
14760 // our load from the relocation, sticking it in either RDI (x86-64)
14761 // or EAX and doing an indirect call. The return value will then
14762 // be in the normal return register.
14763 const X86InstrInfo *TII
14764 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
14765 DebugLoc DL = MI->getDebugLoc();
14766 MachineFunction *F = BB->getParent();
14768 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
14769 assert(MI->getOperand(3).isGlobal() && "This should be a global");
14771 // Get a register mask for the lowered call.
14772 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
14773 // proper register mask.
14774 const uint32_t *RegMask =
14775 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14776 if (Subtarget->is64Bit()) {
14777 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14778 TII->get(X86::MOV64rm), X86::RDI)
14780 .addImm(0).addReg(0)
14781 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14782 MI->getOperand(3).getTargetFlags())
14784 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
14785 addDirectMem(MIB, X86::RDI);
14786 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
14787 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
14788 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14789 TII->get(X86::MOV32rm), X86::EAX)
14791 .addImm(0).addReg(0)
14792 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14793 MI->getOperand(3).getTargetFlags())
14795 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14796 addDirectMem(MIB, X86::EAX);
14797 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14799 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14800 TII->get(X86::MOV32rm), X86::EAX)
14801 .addReg(TII->getGlobalBaseReg(F))
14802 .addImm(0).addReg(0)
14803 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14804 MI->getOperand(3).getTargetFlags())
14806 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14807 addDirectMem(MIB, X86::EAX);
14808 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14811 MI->eraseFromParent(); // The pseudo instruction is gone now.
14815 MachineBasicBlock *
14816 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
14817 MachineBasicBlock *MBB) const {
14818 DebugLoc DL = MI->getDebugLoc();
14819 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14821 MachineFunction *MF = MBB->getParent();
14822 MachineRegisterInfo &MRI = MF->getRegInfo();
14824 const BasicBlock *BB = MBB->getBasicBlock();
14825 MachineFunction::iterator I = MBB;
14828 // Memory Reference
14829 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14830 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14833 unsigned MemOpndSlot = 0;
14835 unsigned CurOp = 0;
14837 DstReg = MI->getOperand(CurOp++).getReg();
14838 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14839 assert(RC->hasType(MVT::i32) && "Invalid destination!");
14840 unsigned mainDstReg = MRI.createVirtualRegister(RC);
14841 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
14843 MemOpndSlot = CurOp;
14845 MVT PVT = getPointerTy();
14846 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14847 "Invalid Pointer Size!");
14849 // For v = setjmp(buf), we generate
14852 // buf[LabelOffset] = restoreMBB
14853 // SjLjSetup restoreMBB
14859 // v = phi(main, restore)
14864 MachineBasicBlock *thisMBB = MBB;
14865 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14866 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14867 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
14868 MF->insert(I, mainMBB);
14869 MF->insert(I, sinkMBB);
14870 MF->push_back(restoreMBB);
14872 MachineInstrBuilder MIB;
14874 // Transfer the remainder of BB and its successor edges to sinkMBB.
14875 sinkMBB->splice(sinkMBB->begin(), MBB,
14876 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14877 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14880 unsigned PtrStoreOpc = 0;
14881 unsigned LabelReg = 0;
14882 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14883 Reloc::Model RM = getTargetMachine().getRelocationModel();
14884 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
14885 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
14887 // Prepare IP either in reg or imm.
14888 if (!UseImmLabel) {
14889 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
14890 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
14891 LabelReg = MRI.createVirtualRegister(PtrRC);
14892 if (Subtarget->is64Bit()) {
14893 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
14897 .addMBB(restoreMBB)
14900 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
14901 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
14902 .addReg(XII->getGlobalBaseReg(MF))
14905 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
14909 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
14911 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
14912 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14913 if (i == X86::AddrDisp)
14914 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
14916 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
14919 MIB.addReg(LabelReg);
14921 MIB.addMBB(restoreMBB);
14922 MIB.setMemRefs(MMOBegin, MMOEnd);
14924 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
14925 .addMBB(restoreMBB);
14927 const X86RegisterInfo *RegInfo =
14928 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
14929 MIB.addRegMask(RegInfo->getNoPreservedMask());
14930 thisMBB->addSuccessor(mainMBB);
14931 thisMBB->addSuccessor(restoreMBB);
14935 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
14936 mainMBB->addSuccessor(sinkMBB);
14939 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14940 TII->get(X86::PHI), DstReg)
14941 .addReg(mainDstReg).addMBB(mainMBB)
14942 .addReg(restoreDstReg).addMBB(restoreMBB);
14945 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
14946 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
14947 restoreMBB->addSuccessor(sinkMBB);
14949 MI->eraseFromParent();
14953 MachineBasicBlock *
14954 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
14955 MachineBasicBlock *MBB) const {
14956 DebugLoc DL = MI->getDebugLoc();
14957 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14959 MachineFunction *MF = MBB->getParent();
14960 MachineRegisterInfo &MRI = MF->getRegInfo();
14962 // Memory Reference
14963 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14964 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14966 MVT PVT = getPointerTy();
14967 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14968 "Invalid Pointer Size!");
14970 const TargetRegisterClass *RC =
14971 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
14972 unsigned Tmp = MRI.createVirtualRegister(RC);
14973 // Since FP is only updated here but NOT referenced, it's treated as GPR.
14974 const X86RegisterInfo *RegInfo =
14975 static_cast<const X86RegisterInfo*>(getTargetMachine().getRegisterInfo());
14976 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
14977 unsigned SP = RegInfo->getStackRegister();
14979 MachineInstrBuilder MIB;
14981 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14982 const int64_t SPOffset = 2 * PVT.getStoreSize();
14984 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
14985 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
14988 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
14989 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
14990 MIB.addOperand(MI->getOperand(i));
14991 MIB.setMemRefs(MMOBegin, MMOEnd);
14993 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
14994 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14995 if (i == X86::AddrDisp)
14996 MIB.addDisp(MI->getOperand(i), LabelOffset);
14998 MIB.addOperand(MI->getOperand(i));
15000 MIB.setMemRefs(MMOBegin, MMOEnd);
15002 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
15003 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
15004 if (i == X86::AddrDisp)
15005 MIB.addDisp(MI->getOperand(i), SPOffset);
15007 MIB.addOperand(MI->getOperand(i));
15009 MIB.setMemRefs(MMOBegin, MMOEnd);
15011 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
15013 MI->eraseFromParent();
15017 MachineBasicBlock *
15018 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
15019 MachineBasicBlock *BB) const {
15020 switch (MI->getOpcode()) {
15021 default: llvm_unreachable("Unexpected instr type to insert");
15022 case X86::TAILJMPd64:
15023 case X86::TAILJMPr64:
15024 case X86::TAILJMPm64:
15025 llvm_unreachable("TAILJMP64 would not be touched here.");
15026 case X86::TCRETURNdi64:
15027 case X86::TCRETURNri64:
15028 case X86::TCRETURNmi64:
15030 case X86::WIN_ALLOCA:
15031 return EmitLoweredWinAlloca(MI, BB);
15032 case X86::SEG_ALLOCA_32:
15033 return EmitLoweredSegAlloca(MI, BB, false);
15034 case X86::SEG_ALLOCA_64:
15035 return EmitLoweredSegAlloca(MI, BB, true);
15036 case X86::TLSCall_32:
15037 case X86::TLSCall_64:
15038 return EmitLoweredTLSCall(MI, BB);
15039 case X86::CMOV_GR8:
15040 case X86::CMOV_FR32:
15041 case X86::CMOV_FR64:
15042 case X86::CMOV_V4F32:
15043 case X86::CMOV_V2F64:
15044 case X86::CMOV_V2I64:
15045 case X86::CMOV_V8F32:
15046 case X86::CMOV_V4F64:
15047 case X86::CMOV_V4I64:
15048 case X86::CMOV_GR16:
15049 case X86::CMOV_GR32:
15050 case X86::CMOV_RFP32:
15051 case X86::CMOV_RFP64:
15052 case X86::CMOV_RFP80:
15053 return EmitLoweredSelect(MI, BB);
15055 case X86::FP32_TO_INT16_IN_MEM:
15056 case X86::FP32_TO_INT32_IN_MEM:
15057 case X86::FP32_TO_INT64_IN_MEM:
15058 case X86::FP64_TO_INT16_IN_MEM:
15059 case X86::FP64_TO_INT32_IN_MEM:
15060 case X86::FP64_TO_INT64_IN_MEM:
15061 case X86::FP80_TO_INT16_IN_MEM:
15062 case X86::FP80_TO_INT32_IN_MEM:
15063 case X86::FP80_TO_INT64_IN_MEM: {
15064 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
15065 DebugLoc DL = MI->getDebugLoc();
15067 // Change the floating point control register to use "round towards zero"
15068 // mode when truncating to an integer value.
15069 MachineFunction *F = BB->getParent();
15070 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
15071 addFrameReference(BuildMI(*BB, MI, DL,
15072 TII->get(X86::FNSTCW16m)), CWFrameIdx);
15074 // Load the old value of the high byte of the control word...
15076 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
15077 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
15080 // Set the high part to be round to zero...
15081 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
15084 // Reload the modified control word now...
15085 addFrameReference(BuildMI(*BB, MI, DL,
15086 TII->get(X86::FLDCW16m)), CWFrameIdx);
15088 // Restore the memory image of control word to original value
15089 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
15092 // Get the X86 opcode to use.
15094 switch (MI->getOpcode()) {
15095 default: llvm_unreachable("illegal opcode!");
15096 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
15097 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
15098 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
15099 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
15100 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
15101 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
15102 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
15103 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
15104 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
15108 MachineOperand &Op = MI->getOperand(0);
15110 AM.BaseType = X86AddressMode::RegBase;
15111 AM.Base.Reg = Op.getReg();
15113 AM.BaseType = X86AddressMode::FrameIndexBase;
15114 AM.Base.FrameIndex = Op.getIndex();
15116 Op = MI->getOperand(1);
15118 AM.Scale = Op.getImm();
15119 Op = MI->getOperand(2);
15121 AM.IndexReg = Op.getImm();
15122 Op = MI->getOperand(3);
15123 if (Op.isGlobal()) {
15124 AM.GV = Op.getGlobal();
15126 AM.Disp = Op.getImm();
15128 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
15129 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
15131 // Reload the original control word now.
15132 addFrameReference(BuildMI(*BB, MI, DL,
15133 TII->get(X86::FLDCW16m)), CWFrameIdx);
15135 MI->eraseFromParent(); // The pseudo instruction is gone now.
15138 // String/text processing lowering.
15139 case X86::PCMPISTRM128REG:
15140 case X86::VPCMPISTRM128REG:
15141 case X86::PCMPISTRM128MEM:
15142 case X86::VPCMPISTRM128MEM:
15143 case X86::PCMPESTRM128REG:
15144 case X86::VPCMPESTRM128REG:
15145 case X86::PCMPESTRM128MEM:
15146 case X86::VPCMPESTRM128MEM:
15147 assert(Subtarget->hasSSE42() &&
15148 "Target must have SSE4.2 or AVX features enabled");
15149 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
15151 // String/text processing lowering.
15152 case X86::PCMPISTRIREG:
15153 case X86::VPCMPISTRIREG:
15154 case X86::PCMPISTRIMEM:
15155 case X86::VPCMPISTRIMEM:
15156 case X86::PCMPESTRIREG:
15157 case X86::VPCMPESTRIREG:
15158 case X86::PCMPESTRIMEM:
15159 case X86::VPCMPESTRIMEM:
15160 assert(Subtarget->hasSSE42() &&
15161 "Target must have SSE4.2 or AVX features enabled");
15162 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
15164 // Thread synchronization.
15166 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
15170 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
15172 // Atomic Lowering.
15173 case X86::ATOMAND8:
15174 case X86::ATOMAND16:
15175 case X86::ATOMAND32:
15176 case X86::ATOMAND64:
15179 case X86::ATOMOR16:
15180 case X86::ATOMOR32:
15181 case X86::ATOMOR64:
15183 case X86::ATOMXOR16:
15184 case X86::ATOMXOR8:
15185 case X86::ATOMXOR32:
15186 case X86::ATOMXOR64:
15188 case X86::ATOMNAND8:
15189 case X86::ATOMNAND16:
15190 case X86::ATOMNAND32:
15191 case X86::ATOMNAND64:
15193 case X86::ATOMMAX8:
15194 case X86::ATOMMAX16:
15195 case X86::ATOMMAX32:
15196 case X86::ATOMMAX64:
15198 case X86::ATOMMIN8:
15199 case X86::ATOMMIN16:
15200 case X86::ATOMMIN32:
15201 case X86::ATOMMIN64:
15203 case X86::ATOMUMAX8:
15204 case X86::ATOMUMAX16:
15205 case X86::ATOMUMAX32:
15206 case X86::ATOMUMAX64:
15208 case X86::ATOMUMIN8:
15209 case X86::ATOMUMIN16:
15210 case X86::ATOMUMIN32:
15211 case X86::ATOMUMIN64:
15212 return EmitAtomicLoadArith(MI, BB);
15214 // This group does 64-bit operations on a 32-bit host.
15215 case X86::ATOMAND6432:
15216 case X86::ATOMOR6432:
15217 case X86::ATOMXOR6432:
15218 case X86::ATOMNAND6432:
15219 case X86::ATOMADD6432:
15220 case X86::ATOMSUB6432:
15221 case X86::ATOMMAX6432:
15222 case X86::ATOMMIN6432:
15223 case X86::ATOMUMAX6432:
15224 case X86::ATOMUMIN6432:
15225 case X86::ATOMSWAP6432:
15226 return EmitAtomicLoadArith6432(MI, BB);
15228 case X86::VASTART_SAVE_XMM_REGS:
15229 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
15231 case X86::VAARG_64:
15232 return EmitVAARG64WithCustomInserter(MI, BB);
15234 case X86::EH_SjLj_SetJmp32:
15235 case X86::EH_SjLj_SetJmp64:
15236 return emitEHSjLjSetJmp(MI, BB);
15238 case X86::EH_SjLj_LongJmp32:
15239 case X86::EH_SjLj_LongJmp64:
15240 return emitEHSjLjLongJmp(MI, BB);
15244 //===----------------------------------------------------------------------===//
15245 // X86 Optimization Hooks
15246 //===----------------------------------------------------------------------===//
15248 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
15251 const SelectionDAG &DAG,
15252 unsigned Depth) const {
15253 unsigned BitWidth = KnownZero.getBitWidth();
15254 unsigned Opc = Op.getOpcode();
15255 assert((Opc >= ISD::BUILTIN_OP_END ||
15256 Opc == ISD::INTRINSIC_WO_CHAIN ||
15257 Opc == ISD::INTRINSIC_W_CHAIN ||
15258 Opc == ISD::INTRINSIC_VOID) &&
15259 "Should use MaskedValueIsZero if you don't know whether Op"
15260 " is a target node!");
15262 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
15276 // These nodes' second result is a boolean.
15277 if (Op.getResNo() == 0)
15280 case X86ISD::SETCC:
15281 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
15283 case ISD::INTRINSIC_WO_CHAIN: {
15284 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15285 unsigned NumLoBits = 0;
15288 case Intrinsic::x86_sse_movmsk_ps:
15289 case Intrinsic::x86_avx_movmsk_ps_256:
15290 case Intrinsic::x86_sse2_movmsk_pd:
15291 case Intrinsic::x86_avx_movmsk_pd_256:
15292 case Intrinsic::x86_mmx_pmovmskb:
15293 case Intrinsic::x86_sse2_pmovmskb_128:
15294 case Intrinsic::x86_avx2_pmovmskb: {
15295 // High bits of movmskp{s|d}, pmovmskb are known zero.
15297 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15298 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
15299 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
15300 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
15301 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
15302 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
15303 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
15304 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
15306 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
15315 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
15316 unsigned Depth) const {
15317 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
15318 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
15319 return Op.getValueType().getScalarType().getSizeInBits();
15325 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
15326 /// node is a GlobalAddress + offset.
15327 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
15328 const GlobalValue* &GA,
15329 int64_t &Offset) const {
15330 if (N->getOpcode() == X86ISD::Wrapper) {
15331 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
15332 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
15333 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
15337 return TargetLowering::isGAPlusOffset(N, GA, Offset);
15340 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
15341 /// same as extracting the high 128-bit part of 256-bit vector and then
15342 /// inserting the result into the low part of a new 256-bit vector
15343 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
15344 EVT VT = SVOp->getValueType(0);
15345 unsigned NumElems = VT.getVectorNumElements();
15347 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15348 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
15349 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15350 SVOp->getMaskElt(j) >= 0)
15356 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
15357 /// same as extracting the low 128-bit part of 256-bit vector and then
15358 /// inserting the result into the high part of a new 256-bit vector
15359 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
15360 EVT VT = SVOp->getValueType(0);
15361 unsigned NumElems = VT.getVectorNumElements();
15363 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15364 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
15365 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15366 SVOp->getMaskElt(j) >= 0)
15372 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
15373 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
15374 TargetLowering::DAGCombinerInfo &DCI,
15375 const X86Subtarget* Subtarget) {
15377 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
15378 SDValue V1 = SVOp->getOperand(0);
15379 SDValue V2 = SVOp->getOperand(1);
15380 EVT VT = SVOp->getValueType(0);
15381 unsigned NumElems = VT.getVectorNumElements();
15383 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
15384 V2.getOpcode() == ISD::CONCAT_VECTORS) {
15388 // V UNDEF BUILD_VECTOR UNDEF
15390 // CONCAT_VECTOR CONCAT_VECTOR
15393 // RESULT: V + zero extended
15395 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
15396 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
15397 V1.getOperand(1).getOpcode() != ISD::UNDEF)
15400 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
15403 // To match the shuffle mask, the first half of the mask should
15404 // be exactly the first vector, and all the rest a splat with the
15405 // first element of the second one.
15406 for (unsigned i = 0; i != NumElems/2; ++i)
15407 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
15408 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
15411 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
15412 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
15413 if (Ld->hasNUsesOfValue(1, 0)) {
15414 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
15415 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
15417 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
15418 array_lengthof(Ops),
15420 Ld->getPointerInfo(),
15421 Ld->getAlignment(),
15422 false/*isVolatile*/, true/*ReadMem*/,
15423 false/*WriteMem*/);
15425 // Make sure the newly-created LOAD is in the same position as Ld in
15426 // terms of dependency. We create a TokenFactor for Ld and ResNode,
15427 // and update uses of Ld's output chain to use the TokenFactor.
15428 if (Ld->hasAnyUseOfValue(1)) {
15429 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
15430 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
15431 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
15432 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
15433 SDValue(ResNode.getNode(), 1));
15436 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
15440 // Emit a zeroed vector and insert the desired subvector on its
15442 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15443 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
15444 return DCI.CombineTo(N, InsV);
15447 //===--------------------------------------------------------------------===//
15448 // Combine some shuffles into subvector extracts and inserts:
15451 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15452 if (isShuffleHigh128VectorInsertLow(SVOp)) {
15453 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
15454 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
15455 return DCI.CombineTo(N, InsV);
15458 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15459 if (isShuffleLow128VectorInsertHigh(SVOp)) {
15460 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
15461 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
15462 return DCI.CombineTo(N, InsV);
15468 /// PerformShuffleCombine - Performs several different shuffle combines.
15469 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
15470 TargetLowering::DAGCombinerInfo &DCI,
15471 const X86Subtarget *Subtarget) {
15473 EVT VT = N->getValueType(0);
15475 // Don't create instructions with illegal types after legalize types has run.
15476 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15477 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
15480 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
15481 if (Subtarget->hasFp256() && VT.is256BitVector() &&
15482 N->getOpcode() == ISD::VECTOR_SHUFFLE)
15483 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
15485 // Only handle 128 wide vector from here on.
15486 if (!VT.is128BitVector())
15489 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
15490 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
15491 // consecutive, non-overlapping, and in the right order.
15492 SmallVector<SDValue, 16> Elts;
15493 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
15494 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
15496 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
15499 /// PerformTruncateCombine - Converts truncate operation to
15500 /// a sequence of vector shuffle operations.
15501 /// It is possible when we truncate 256-bit vector to 128-bit vector
15502 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
15503 TargetLowering::DAGCombinerInfo &DCI,
15504 const X86Subtarget *Subtarget) {
15508 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
15509 /// specific shuffle of a load can be folded into a single element load.
15510 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
15511 /// shuffles have been customed lowered so we need to handle those here.
15512 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
15513 TargetLowering::DAGCombinerInfo &DCI) {
15514 if (DCI.isBeforeLegalizeOps())
15517 SDValue InVec = N->getOperand(0);
15518 SDValue EltNo = N->getOperand(1);
15520 if (!isa<ConstantSDNode>(EltNo))
15523 EVT VT = InVec.getValueType();
15525 bool HasShuffleIntoBitcast = false;
15526 if (InVec.getOpcode() == ISD::BITCAST) {
15527 // Don't duplicate a load with other uses.
15528 if (!InVec.hasOneUse())
15530 EVT BCVT = InVec.getOperand(0).getValueType();
15531 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
15533 InVec = InVec.getOperand(0);
15534 HasShuffleIntoBitcast = true;
15537 if (!isTargetShuffle(InVec.getOpcode()))
15540 // Don't duplicate a load with other uses.
15541 if (!InVec.hasOneUse())
15544 SmallVector<int, 16> ShuffleMask;
15546 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
15550 // Select the input vector, guarding against out of range extract vector.
15551 unsigned NumElems = VT.getVectorNumElements();
15552 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
15553 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
15554 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
15555 : InVec.getOperand(1);
15557 // If inputs to shuffle are the same for both ops, then allow 2 uses
15558 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
15560 if (LdNode.getOpcode() == ISD::BITCAST) {
15561 // Don't duplicate a load with other uses.
15562 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
15565 AllowedUses = 1; // only allow 1 load use if we have a bitcast
15566 LdNode = LdNode.getOperand(0);
15569 if (!ISD::isNormalLoad(LdNode.getNode()))
15572 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
15574 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
15577 if (HasShuffleIntoBitcast) {
15578 // If there's a bitcast before the shuffle, check if the load type and
15579 // alignment is valid.
15580 unsigned Align = LN0->getAlignment();
15581 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15582 unsigned NewAlign = TLI.getDataLayout()->
15583 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
15585 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
15589 // All checks match so transform back to vector_shuffle so that DAG combiner
15590 // can finish the job
15593 // Create shuffle node taking into account the case that its a unary shuffle
15594 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
15595 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
15596 InVec.getOperand(0), Shuffle,
15598 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
15599 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
15603 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
15604 /// generation and convert it from being a bunch of shuffles and extracts
15605 /// to a simple store and scalar loads to extract the elements.
15606 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
15607 TargetLowering::DAGCombinerInfo &DCI) {
15608 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
15609 if (NewOp.getNode())
15612 SDValue InputVector = N->getOperand(0);
15613 // Detect whether we are trying to convert from mmx to i32 and the bitcast
15614 // from mmx to v2i32 has a single usage.
15615 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
15616 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
15617 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
15618 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
15619 N->getValueType(0),
15620 InputVector.getNode()->getOperand(0));
15622 // Only operate on vectors of 4 elements, where the alternative shuffling
15623 // gets to be more expensive.
15624 if (InputVector.getValueType() != MVT::v4i32)
15627 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
15628 // single use which is a sign-extend or zero-extend, and all elements are
15630 SmallVector<SDNode *, 4> Uses;
15631 unsigned ExtractedElements = 0;
15632 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
15633 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
15634 if (UI.getUse().getResNo() != InputVector.getResNo())
15637 SDNode *Extract = *UI;
15638 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
15641 if (Extract->getValueType(0) != MVT::i32)
15643 if (!Extract->hasOneUse())
15645 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
15646 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
15648 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
15651 // Record which element was extracted.
15652 ExtractedElements |=
15653 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
15655 Uses.push_back(Extract);
15658 // If not all the elements were used, this may not be worthwhile.
15659 if (ExtractedElements != 15)
15662 // Ok, we've now decided to do the transformation.
15663 SDLoc dl(InputVector);
15665 // Store the value to a temporary stack slot.
15666 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
15667 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
15668 MachinePointerInfo(), false, false, 0);
15670 // Replace each use (extract) with a load of the appropriate element.
15671 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
15672 UE = Uses.end(); UI != UE; ++UI) {
15673 SDNode *Extract = *UI;
15675 // cOMpute the element's address.
15676 SDValue Idx = Extract->getOperand(1);
15678 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
15679 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
15680 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15681 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
15683 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
15684 StackPtr, OffsetVal);
15686 // Load the scalar.
15687 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
15688 ScalarAddr, MachinePointerInfo(),
15689 false, false, false, 0);
15691 // Replace the exact with the load.
15692 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
15695 // The replacement was made in place; don't return anything.
15699 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
15700 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
15701 SDValue RHS, SelectionDAG &DAG,
15702 const X86Subtarget *Subtarget) {
15703 if (!VT.isVector())
15706 switch (VT.getSimpleVT().SimpleTy) {
15711 if (!Subtarget->hasAVX2())
15716 if (!Subtarget->hasSSE2())
15720 // SSE2 has only a small subset of the operations.
15721 bool hasUnsigned = Subtarget->hasSSE41() ||
15722 (Subtarget->hasSSE2() && VT == MVT::v16i8);
15723 bool hasSigned = Subtarget->hasSSE41() ||
15724 (Subtarget->hasSSE2() && VT == MVT::v8i16);
15726 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15728 // Check for x CC y ? x : y.
15729 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15730 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15735 return hasUnsigned ? X86ISD::UMIN : 0;
15738 return hasUnsigned ? X86ISD::UMAX : 0;
15741 return hasSigned ? X86ISD::SMIN : 0;
15744 return hasSigned ? X86ISD::SMAX : 0;
15746 // Check for x CC y ? y : x -- a min/max with reversed arms.
15747 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15748 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15753 return hasUnsigned ? X86ISD::UMAX : 0;
15756 return hasUnsigned ? X86ISD::UMIN : 0;
15759 return hasSigned ? X86ISD::SMAX : 0;
15762 return hasSigned ? X86ISD::SMIN : 0;
15769 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
15771 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
15772 TargetLowering::DAGCombinerInfo &DCI,
15773 const X86Subtarget *Subtarget) {
15775 SDValue Cond = N->getOperand(0);
15776 // Get the LHS/RHS of the select.
15777 SDValue LHS = N->getOperand(1);
15778 SDValue RHS = N->getOperand(2);
15779 EVT VT = LHS.getValueType();
15781 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
15782 // instructions match the semantics of the common C idiom x<y?x:y but not
15783 // x<=y?x:y, because of how they handle negative zero (which can be
15784 // ignored in unsafe-math mode).
15785 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
15786 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
15787 (Subtarget->hasSSE2() ||
15788 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
15789 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15791 unsigned Opcode = 0;
15792 // Check for x CC y ? x : y.
15793 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15794 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15798 // Converting this to a min would handle NaNs incorrectly, and swapping
15799 // the operands would cause it to handle comparisons between positive
15800 // and negative zero incorrectly.
15801 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15802 if (!DAG.getTarget().Options.UnsafeFPMath &&
15803 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15805 std::swap(LHS, RHS);
15807 Opcode = X86ISD::FMIN;
15810 // Converting this to a min would handle comparisons between positive
15811 // and negative zero incorrectly.
15812 if (!DAG.getTarget().Options.UnsafeFPMath &&
15813 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15815 Opcode = X86ISD::FMIN;
15818 // Converting this to a min would handle both negative zeros and NaNs
15819 // incorrectly, but we can swap the operands to fix both.
15820 std::swap(LHS, RHS);
15824 Opcode = X86ISD::FMIN;
15828 // Converting this to a max would handle comparisons between positive
15829 // and negative zero incorrectly.
15830 if (!DAG.getTarget().Options.UnsafeFPMath &&
15831 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15833 Opcode = X86ISD::FMAX;
15836 // Converting this to a max would handle NaNs incorrectly, and swapping
15837 // the operands would cause it to handle comparisons between positive
15838 // and negative zero incorrectly.
15839 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15840 if (!DAG.getTarget().Options.UnsafeFPMath &&
15841 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15843 std::swap(LHS, RHS);
15845 Opcode = X86ISD::FMAX;
15848 // Converting this to a max would handle both negative zeros and NaNs
15849 // incorrectly, but we can swap the operands to fix both.
15850 std::swap(LHS, RHS);
15854 Opcode = X86ISD::FMAX;
15857 // Check for x CC y ? y : x -- a min/max with reversed arms.
15858 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15859 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15863 // Converting this to a min would handle comparisons between positive
15864 // and negative zero incorrectly, and swapping the operands would
15865 // cause it to handle NaNs incorrectly.
15866 if (!DAG.getTarget().Options.UnsafeFPMath &&
15867 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
15868 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15870 std::swap(LHS, RHS);
15872 Opcode = X86ISD::FMIN;
15875 // Converting this to a min would handle NaNs incorrectly.
15876 if (!DAG.getTarget().Options.UnsafeFPMath &&
15877 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
15879 Opcode = X86ISD::FMIN;
15882 // Converting this to a min would handle both negative zeros and NaNs
15883 // incorrectly, but we can swap the operands to fix both.
15884 std::swap(LHS, RHS);
15888 Opcode = X86ISD::FMIN;
15892 // Converting this to a max would handle NaNs incorrectly.
15893 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15895 Opcode = X86ISD::FMAX;
15898 // Converting this to a max would handle comparisons between positive
15899 // and negative zero incorrectly, and swapping the operands would
15900 // cause it to handle NaNs incorrectly.
15901 if (!DAG.getTarget().Options.UnsafeFPMath &&
15902 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
15903 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15905 std::swap(LHS, RHS);
15907 Opcode = X86ISD::FMAX;
15910 // Converting this to a max would handle both negative zeros and NaNs
15911 // incorrectly, but we can swap the operands to fix both.
15912 std::swap(LHS, RHS);
15916 Opcode = X86ISD::FMAX;
15922 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
15925 // If this is a select between two integer constants, try to do some
15927 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
15928 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
15929 // Don't do this for crazy integer types.
15930 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
15931 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
15932 // so that TrueC (the true value) is larger than FalseC.
15933 bool NeedsCondInvert = false;
15935 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
15936 // Efficiently invertible.
15937 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15938 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15939 isa<ConstantSDNode>(Cond.getOperand(1))))) {
15940 NeedsCondInvert = true;
15941 std::swap(TrueC, FalseC);
15944 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
15945 if (FalseC->getAPIntValue() == 0 &&
15946 TrueC->getAPIntValue().isPowerOf2()) {
15947 if (NeedsCondInvert) // Invert the condition if needed.
15948 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15949 DAG.getConstant(1, Cond.getValueType()));
15951 // Zero extend the condition if needed.
15952 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
15954 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15955 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15956 DAG.getConstant(ShAmt, MVT::i8));
15959 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
15960 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15961 if (NeedsCondInvert) // Invert the condition if needed.
15962 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15963 DAG.getConstant(1, Cond.getValueType()));
15965 // Zero extend the condition if needed.
15966 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15967 FalseC->getValueType(0), Cond);
15968 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15969 SDValue(FalseC, 0));
15972 // Optimize cases that will turn into an LEA instruction. This requires
15973 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15974 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15975 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15976 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15978 bool isFastMultiplier = false;
15980 switch ((unsigned char)Diff) {
15982 case 1: // result = add base, cond
15983 case 2: // result = lea base( , cond*2)
15984 case 3: // result = lea base(cond, cond*2)
15985 case 4: // result = lea base( , cond*4)
15986 case 5: // result = lea base(cond, cond*4)
15987 case 8: // result = lea base( , cond*8)
15988 case 9: // result = lea base(cond, cond*8)
15989 isFastMultiplier = true;
15994 if (isFastMultiplier) {
15995 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15996 if (NeedsCondInvert) // Invert the condition if needed.
15997 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15998 DAG.getConstant(1, Cond.getValueType()));
16000 // Zero extend the condition if needed.
16001 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16003 // Scale the condition by the difference.
16005 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16006 DAG.getConstant(Diff, Cond.getValueType()));
16008 // Add the base if non-zero.
16009 if (FalseC->getAPIntValue() != 0)
16010 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16011 SDValue(FalseC, 0));
16018 // Canonicalize max and min:
16019 // (x > y) ? x : y -> (x >= y) ? x : y
16020 // (x < y) ? x : y -> (x <= y) ? x : y
16021 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
16022 // the need for an extra compare
16023 // against zero. e.g.
16024 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
16026 // testl %edi, %edi
16028 // cmovgl %edi, %eax
16032 // cmovsl %eax, %edi
16033 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
16034 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
16035 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
16036 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16041 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
16042 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
16043 Cond.getOperand(0), Cond.getOperand(1), NewCC);
16044 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
16049 // Match VSELECTs into subs with unsigned saturation.
16050 if (!DCI.isBeforeLegalize() &&
16051 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
16052 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
16053 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
16054 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
16055 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
16057 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
16058 // left side invert the predicate to simplify logic below.
16060 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
16062 CC = ISD::getSetCCInverse(CC, true);
16063 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
16067 if (Other.getNode() && Other->getNumOperands() == 2 &&
16068 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
16069 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
16070 SDValue CondRHS = Cond->getOperand(1);
16072 // Look for a general sub with unsigned saturation first.
16073 // x >= y ? x-y : 0 --> subus x, y
16074 // x > y ? x-y : 0 --> subus x, y
16075 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
16076 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
16077 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16079 // If the RHS is a constant we have to reverse the const canonicalization.
16080 // x > C-1 ? x+-C : 0 --> subus x, C
16081 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
16082 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
16083 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16084 if (CondRHS.getConstantOperandVal(0) == -A-1)
16085 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
16086 DAG.getConstant(-A, VT));
16089 // Another special case: If C was a sign bit, the sub has been
16090 // canonicalized into a xor.
16091 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
16092 // it's safe to decanonicalize the xor?
16093 // x s< 0 ? x^C : 0 --> subus x, C
16094 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
16095 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
16096 isSplatVector(OpRHS.getNode())) {
16097 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
16099 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
16104 // Try to match a min/max vector operation.
16105 if (!DCI.isBeforeLegalize() &&
16106 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
16107 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
16108 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
16110 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
16111 if (!DCI.isBeforeLegalize() && N->getOpcode() == ISD::VSELECT &&
16112 Cond.getOpcode() == ISD::SETCC) {
16114 assert(Cond.getValueType().isVector() &&
16115 "vector select expects a vector selector!");
16117 EVT IntVT = Cond.getValueType();
16118 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
16119 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
16121 if (!TValIsAllOnes && !FValIsAllZeros) {
16122 // Try invert the condition if true value is not all 1s and false value
16124 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
16125 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
16127 if (TValIsAllZeros || FValIsAllOnes) {
16128 SDValue CC = Cond.getOperand(2);
16129 ISD::CondCode NewCC =
16130 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
16131 Cond.getOperand(0).getValueType().isInteger());
16132 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
16133 std::swap(LHS, RHS);
16134 TValIsAllOnes = FValIsAllOnes;
16135 FValIsAllZeros = TValIsAllZeros;
16139 if (TValIsAllOnes || FValIsAllZeros) {
16142 if (TValIsAllOnes && FValIsAllZeros)
16144 else if (TValIsAllOnes)
16145 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
16146 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
16147 else if (FValIsAllZeros)
16148 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
16149 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
16151 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
16155 // If we know that this node is legal then we know that it is going to be
16156 // matched by one of the SSE/AVX BLEND instructions. These instructions only
16157 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
16158 // to simplify previous instructions.
16159 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16160 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
16161 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
16162 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
16164 // Don't optimize vector selects that map to mask-registers.
16168 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
16169 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
16171 APInt KnownZero, KnownOne;
16172 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
16173 DCI.isBeforeLegalizeOps());
16174 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
16175 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
16176 DCI.CommitTargetLoweringOpt(TLO);
16182 // Check whether a boolean test is testing a boolean value generated by
16183 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
16186 // Simplify the following patterns:
16187 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
16188 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
16189 // to (Op EFLAGS Cond)
16191 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
16192 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
16193 // to (Op EFLAGS !Cond)
16195 // where Op could be BRCOND or CMOV.
16197 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
16198 // Quit if not CMP and SUB with its value result used.
16199 if (Cmp.getOpcode() != X86ISD::CMP &&
16200 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
16203 // Quit if not used as a boolean value.
16204 if (CC != X86::COND_E && CC != X86::COND_NE)
16207 // Check CMP operands. One of them should be 0 or 1 and the other should be
16208 // an SetCC or extended from it.
16209 SDValue Op1 = Cmp.getOperand(0);
16210 SDValue Op2 = Cmp.getOperand(1);
16213 const ConstantSDNode* C = 0;
16214 bool needOppositeCond = (CC == X86::COND_E);
16215 bool checkAgainstTrue = false; // Is it a comparison against 1?
16217 if ((C = dyn_cast<ConstantSDNode>(Op1)))
16219 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
16221 else // Quit if all operands are not constants.
16224 if (C->getZExtValue() == 1) {
16225 needOppositeCond = !needOppositeCond;
16226 checkAgainstTrue = true;
16227 } else if (C->getZExtValue() != 0)
16228 // Quit if the constant is neither 0 or 1.
16231 bool truncatedToBoolWithAnd = false;
16232 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
16233 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
16234 SetCC.getOpcode() == ISD::TRUNCATE ||
16235 SetCC.getOpcode() == ISD::AND) {
16236 if (SetCC.getOpcode() == ISD::AND) {
16238 ConstantSDNode *CS;
16239 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
16240 CS->getZExtValue() == 1)
16242 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
16243 CS->getZExtValue() == 1)
16247 SetCC = SetCC.getOperand(OpIdx);
16248 truncatedToBoolWithAnd = true;
16250 SetCC = SetCC.getOperand(0);
16253 switch (SetCC.getOpcode()) {
16254 case X86ISD::SETCC_CARRY:
16255 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
16256 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
16257 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
16258 // truncated to i1 using 'and'.
16259 if (checkAgainstTrue && !truncatedToBoolWithAnd)
16261 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
16262 "Invalid use of SETCC_CARRY!");
16264 case X86ISD::SETCC:
16265 // Set the condition code or opposite one if necessary.
16266 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
16267 if (needOppositeCond)
16268 CC = X86::GetOppositeBranchCondition(CC);
16269 return SetCC.getOperand(1);
16270 case X86ISD::CMOV: {
16271 // Check whether false/true value has canonical one, i.e. 0 or 1.
16272 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
16273 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
16274 // Quit if true value is not a constant.
16277 // Quit if false value is not a constant.
16279 SDValue Op = SetCC.getOperand(0);
16280 // Skip 'zext' or 'trunc' node.
16281 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
16282 Op.getOpcode() == ISD::TRUNCATE)
16283 Op = Op.getOperand(0);
16284 // A special case for rdrand/rdseed, where 0 is set if false cond is
16286 if ((Op.getOpcode() != X86ISD::RDRAND &&
16287 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
16290 // Quit if false value is not the constant 0 or 1.
16291 bool FValIsFalse = true;
16292 if (FVal && FVal->getZExtValue() != 0) {
16293 if (FVal->getZExtValue() != 1)
16295 // If FVal is 1, opposite cond is needed.
16296 needOppositeCond = !needOppositeCond;
16297 FValIsFalse = false;
16299 // Quit if TVal is not the constant opposite of FVal.
16300 if (FValIsFalse && TVal->getZExtValue() != 1)
16302 if (!FValIsFalse && TVal->getZExtValue() != 0)
16304 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
16305 if (needOppositeCond)
16306 CC = X86::GetOppositeBranchCondition(CC);
16307 return SetCC.getOperand(3);
16314 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
16315 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
16316 TargetLowering::DAGCombinerInfo &DCI,
16317 const X86Subtarget *Subtarget) {
16320 // If the flag operand isn't dead, don't touch this CMOV.
16321 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
16324 SDValue FalseOp = N->getOperand(0);
16325 SDValue TrueOp = N->getOperand(1);
16326 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
16327 SDValue Cond = N->getOperand(3);
16329 if (CC == X86::COND_E || CC == X86::COND_NE) {
16330 switch (Cond.getOpcode()) {
16334 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
16335 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
16336 return (CC == X86::COND_E) ? FalseOp : TrueOp;
16342 Flags = checkBoolTestSetCCCombine(Cond, CC);
16343 if (Flags.getNode() &&
16344 // Extra check as FCMOV only supports a subset of X86 cond.
16345 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
16346 SDValue Ops[] = { FalseOp, TrueOp,
16347 DAG.getConstant(CC, MVT::i8), Flags };
16348 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
16349 Ops, array_lengthof(Ops));
16352 // If this is a select between two integer constants, try to do some
16353 // optimizations. Note that the operands are ordered the opposite of SELECT
16355 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
16356 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
16357 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
16358 // larger than FalseC (the false value).
16359 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
16360 CC = X86::GetOppositeBranchCondition(CC);
16361 std::swap(TrueC, FalseC);
16362 std::swap(TrueOp, FalseOp);
16365 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
16366 // This is efficient for any integer data type (including i8/i16) and
16368 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
16369 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16370 DAG.getConstant(CC, MVT::i8), Cond);
16372 // Zero extend the condition if needed.
16373 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
16375 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16376 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
16377 DAG.getConstant(ShAmt, MVT::i8));
16378 if (N->getNumValues() == 2) // Dead flag value?
16379 return DCI.CombineTo(N, Cond, SDValue());
16383 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
16384 // for any integer data type, including i8/i16.
16385 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16386 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16387 DAG.getConstant(CC, MVT::i8), Cond);
16389 // Zero extend the condition if needed.
16390 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16391 FalseC->getValueType(0), Cond);
16392 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16393 SDValue(FalseC, 0));
16395 if (N->getNumValues() == 2) // Dead flag value?
16396 return DCI.CombineTo(N, Cond, SDValue());
16400 // Optimize cases that will turn into an LEA instruction. This requires
16401 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16402 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16403 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16404 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16406 bool isFastMultiplier = false;
16408 switch ((unsigned char)Diff) {
16410 case 1: // result = add base, cond
16411 case 2: // result = lea base( , cond*2)
16412 case 3: // result = lea base(cond, cond*2)
16413 case 4: // result = lea base( , cond*4)
16414 case 5: // result = lea base(cond, cond*4)
16415 case 8: // result = lea base( , cond*8)
16416 case 9: // result = lea base(cond, cond*8)
16417 isFastMultiplier = true;
16422 if (isFastMultiplier) {
16423 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16424 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16425 DAG.getConstant(CC, MVT::i8), Cond);
16426 // Zero extend the condition if needed.
16427 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16429 // Scale the condition by the difference.
16431 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16432 DAG.getConstant(Diff, Cond.getValueType()));
16434 // Add the base if non-zero.
16435 if (FalseC->getAPIntValue() != 0)
16436 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16437 SDValue(FalseC, 0));
16438 if (N->getNumValues() == 2) // Dead flag value?
16439 return DCI.CombineTo(N, Cond, SDValue());
16446 // Handle these cases:
16447 // (select (x != c), e, c) -> select (x != c), e, x),
16448 // (select (x == c), c, e) -> select (x == c), x, e)
16449 // where the c is an integer constant, and the "select" is the combination
16450 // of CMOV and CMP.
16452 // The rationale for this change is that the conditional-move from a constant
16453 // needs two instructions, however, conditional-move from a register needs
16454 // only one instruction.
16456 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
16457 // some instruction-combining opportunities. This opt needs to be
16458 // postponed as late as possible.
16460 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
16461 // the DCI.xxxx conditions are provided to postpone the optimization as
16462 // late as possible.
16464 ConstantSDNode *CmpAgainst = 0;
16465 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
16466 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
16467 !isa<ConstantSDNode>(Cond.getOperand(0))) {
16469 if (CC == X86::COND_NE &&
16470 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
16471 CC = X86::GetOppositeBranchCondition(CC);
16472 std::swap(TrueOp, FalseOp);
16475 if (CC == X86::COND_E &&
16476 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
16477 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
16478 DAG.getConstant(CC, MVT::i8), Cond };
16479 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
16480 array_lengthof(Ops));
16488 /// PerformMulCombine - Optimize a single multiply with constant into two
16489 /// in order to implement it with two cheaper instructions, e.g.
16490 /// LEA + SHL, LEA + LEA.
16491 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
16492 TargetLowering::DAGCombinerInfo &DCI) {
16493 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16496 EVT VT = N->getValueType(0);
16497 if (VT != MVT::i64)
16500 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
16503 uint64_t MulAmt = C->getZExtValue();
16504 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
16507 uint64_t MulAmt1 = 0;
16508 uint64_t MulAmt2 = 0;
16509 if ((MulAmt % 9) == 0) {
16511 MulAmt2 = MulAmt / 9;
16512 } else if ((MulAmt % 5) == 0) {
16514 MulAmt2 = MulAmt / 5;
16515 } else if ((MulAmt % 3) == 0) {
16517 MulAmt2 = MulAmt / 3;
16520 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
16523 if (isPowerOf2_64(MulAmt2) &&
16524 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
16525 // If second multiplifer is pow2, issue it first. We want the multiply by
16526 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
16528 std::swap(MulAmt1, MulAmt2);
16531 if (isPowerOf2_64(MulAmt1))
16532 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
16533 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
16535 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
16536 DAG.getConstant(MulAmt1, VT));
16538 if (isPowerOf2_64(MulAmt2))
16539 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
16540 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
16542 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
16543 DAG.getConstant(MulAmt2, VT));
16545 // Do not add new nodes to DAG combiner worklist.
16546 DCI.CombineTo(N, NewMul, false);
16551 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
16552 SDValue N0 = N->getOperand(0);
16553 SDValue N1 = N->getOperand(1);
16554 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
16555 EVT VT = N0.getValueType();
16557 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
16558 // since the result of setcc_c is all zero's or all ones.
16559 if (VT.isInteger() && !VT.isVector() &&
16560 N1C && N0.getOpcode() == ISD::AND &&
16561 N0.getOperand(1).getOpcode() == ISD::Constant) {
16562 SDValue N00 = N0.getOperand(0);
16563 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
16564 ((N00.getOpcode() == ISD::ANY_EXTEND ||
16565 N00.getOpcode() == ISD::ZERO_EXTEND) &&
16566 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
16567 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
16568 APInt ShAmt = N1C->getAPIntValue();
16569 Mask = Mask.shl(ShAmt);
16571 return DAG.getNode(ISD::AND, SDLoc(N), VT,
16572 N00, DAG.getConstant(Mask, VT));
16576 // Hardware support for vector shifts is sparse which makes us scalarize the
16577 // vector operations in many cases. Also, on sandybridge ADD is faster than
16579 // (shl V, 1) -> add V,V
16580 if (isSplatVector(N1.getNode())) {
16581 assert(N0.getValueType().isVector() && "Invalid vector shift type");
16582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
16583 // We shift all of the values by one. In many cases we do not have
16584 // hardware support for this operation. This is better expressed as an ADD
16586 if (N1C && (1 == N1C->getZExtValue())) {
16587 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
16594 /// \brief Returns a vector of 0s if the node in input is a vector logical
16595 /// shift by a constant amount which is known to be bigger than or equal
16596 /// to the vector element size in bits.
16597 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
16598 const X86Subtarget *Subtarget) {
16599 EVT VT = N->getValueType(0);
16601 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
16602 (!Subtarget->hasInt256() ||
16603 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
16606 SDValue Amt = N->getOperand(1);
16608 if (isSplatVector(Amt.getNode())) {
16609 SDValue SclrAmt = Amt->getOperand(0);
16610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
16611 APInt ShiftAmt = C->getAPIntValue();
16612 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
16614 // SSE2/AVX2 logical shifts always return a vector of 0s
16615 // if the shift amount is bigger than or equal to
16616 // the element size. The constant shift amount will be
16617 // encoded as a 8-bit immediate.
16618 if (ShiftAmt.trunc(8).uge(MaxAmount))
16619 return getZeroVector(VT, Subtarget, DAG, DL);
16626 /// PerformShiftCombine - Combine shifts.
16627 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
16628 TargetLowering::DAGCombinerInfo &DCI,
16629 const X86Subtarget *Subtarget) {
16630 if (N->getOpcode() == ISD::SHL) {
16631 SDValue V = PerformSHLCombine(N, DAG);
16632 if (V.getNode()) return V;
16635 if (N->getOpcode() != ISD::SRA) {
16636 // Try to fold this logical shift into a zero vector.
16637 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
16638 if (V.getNode()) return V;
16644 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
16645 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
16646 // and friends. Likewise for OR -> CMPNEQSS.
16647 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
16648 TargetLowering::DAGCombinerInfo &DCI,
16649 const X86Subtarget *Subtarget) {
16652 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
16653 // we're requiring SSE2 for both.
16654 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
16655 SDValue N0 = N->getOperand(0);
16656 SDValue N1 = N->getOperand(1);
16657 SDValue CMP0 = N0->getOperand(1);
16658 SDValue CMP1 = N1->getOperand(1);
16661 // The SETCCs should both refer to the same CMP.
16662 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
16665 SDValue CMP00 = CMP0->getOperand(0);
16666 SDValue CMP01 = CMP0->getOperand(1);
16667 EVT VT = CMP00.getValueType();
16669 if (VT == MVT::f32 || VT == MVT::f64) {
16670 bool ExpectingFlags = false;
16671 // Check for any users that want flags:
16672 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
16673 !ExpectingFlags && UI != UE; ++UI)
16674 switch (UI->getOpcode()) {
16679 ExpectingFlags = true;
16681 case ISD::CopyToReg:
16682 case ISD::SIGN_EXTEND:
16683 case ISD::ZERO_EXTEND:
16684 case ISD::ANY_EXTEND:
16688 if (!ExpectingFlags) {
16689 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
16690 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
16692 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
16693 X86::CondCode tmp = cc0;
16698 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
16699 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
16700 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
16701 X86ISD::NodeType NTOperator = is64BitFP ?
16702 X86ISD::FSETCCsd : X86ISD::FSETCCss;
16703 // FIXME: need symbolic constants for these magic numbers.
16704 // See X86ATTInstPrinter.cpp:printSSECC().
16705 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
16706 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
16707 DAG.getConstant(x86cc, MVT::i8));
16708 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
16710 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
16711 DAG.getConstant(1, MVT::i32));
16712 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
16713 return OneBitOfTruth;
16721 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
16722 /// so it can be folded inside ANDNP.
16723 static bool CanFoldXORWithAllOnes(const SDNode *N) {
16724 EVT VT = N->getValueType(0);
16726 // Match direct AllOnes for 128 and 256-bit vectors
16727 if (ISD::isBuildVectorAllOnes(N))
16730 // Look through a bit convert.
16731 if (N->getOpcode() == ISD::BITCAST)
16732 N = N->getOperand(0).getNode();
16734 // Sometimes the operand may come from a insert_subvector building a 256-bit
16736 if (VT.is256BitVector() &&
16737 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
16738 SDValue V1 = N->getOperand(0);
16739 SDValue V2 = N->getOperand(1);
16741 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
16742 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
16743 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
16744 ISD::isBuildVectorAllOnes(V2.getNode()))
16751 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
16752 // register. In most cases we actually compare or select YMM-sized registers
16753 // and mixing the two types creates horrible code. This method optimizes
16754 // some of the transition sequences.
16755 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
16756 TargetLowering::DAGCombinerInfo &DCI,
16757 const X86Subtarget *Subtarget) {
16758 EVT VT = N->getValueType(0);
16759 if (!VT.is256BitVector())
16762 assert((N->getOpcode() == ISD::ANY_EXTEND ||
16763 N->getOpcode() == ISD::ZERO_EXTEND ||
16764 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
16766 SDValue Narrow = N->getOperand(0);
16767 EVT NarrowVT = Narrow->getValueType(0);
16768 if (!NarrowVT.is128BitVector())
16771 if (Narrow->getOpcode() != ISD::XOR &&
16772 Narrow->getOpcode() != ISD::AND &&
16773 Narrow->getOpcode() != ISD::OR)
16776 SDValue N0 = Narrow->getOperand(0);
16777 SDValue N1 = Narrow->getOperand(1);
16780 // The Left side has to be a trunc.
16781 if (N0.getOpcode() != ISD::TRUNCATE)
16784 // The type of the truncated inputs.
16785 EVT WideVT = N0->getOperand(0)->getValueType(0);
16789 // The right side has to be a 'trunc' or a constant vector.
16790 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
16791 bool RHSConst = (isSplatVector(N1.getNode()) &&
16792 isa<ConstantSDNode>(N1->getOperand(0)));
16793 if (!RHSTrunc && !RHSConst)
16796 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16798 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
16801 // Set N0 and N1 to hold the inputs to the new wide operation.
16802 N0 = N0->getOperand(0);
16804 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
16805 N1->getOperand(0));
16806 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
16807 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
16808 } else if (RHSTrunc) {
16809 N1 = N1->getOperand(0);
16812 // Generate the wide operation.
16813 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
16814 unsigned Opcode = N->getOpcode();
16816 case ISD::ANY_EXTEND:
16818 case ISD::ZERO_EXTEND: {
16819 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
16820 APInt Mask = APInt::getAllOnesValue(InBits);
16821 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
16822 return DAG.getNode(ISD::AND, DL, VT,
16823 Op, DAG.getConstant(Mask, VT));
16825 case ISD::SIGN_EXTEND:
16826 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
16827 Op, DAG.getValueType(NarrowVT));
16829 llvm_unreachable("Unexpected opcode");
16833 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
16834 TargetLowering::DAGCombinerInfo &DCI,
16835 const X86Subtarget *Subtarget) {
16836 EVT VT = N->getValueType(0);
16837 if (DCI.isBeforeLegalizeOps())
16840 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16844 // Create BLSI, and BLSR instructions
16845 // BLSI is X & (-X)
16846 // BLSR is X & (X-1)
16847 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
16848 SDValue N0 = N->getOperand(0);
16849 SDValue N1 = N->getOperand(1);
16852 // Check LHS for neg
16853 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16854 isZero(N0.getOperand(0)))
16855 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
16857 // Check RHS for neg
16858 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16859 isZero(N1.getOperand(0)))
16860 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
16862 // Check LHS for X-1
16863 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16864 isAllOnes(N0.getOperand(1)))
16865 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
16867 // Check RHS for X-1
16868 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16869 isAllOnes(N1.getOperand(1)))
16870 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
16875 // Want to form ANDNP nodes:
16876 // 1) In the hopes of then easily combining them with OR and AND nodes
16877 // to form PBLEND/PSIGN.
16878 // 2) To match ANDN packed intrinsics
16879 if (VT != MVT::v2i64 && VT != MVT::v4i64)
16882 SDValue N0 = N->getOperand(0);
16883 SDValue N1 = N->getOperand(1);
16886 // Check LHS for vnot
16887 if (N0.getOpcode() == ISD::XOR &&
16888 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
16889 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
16890 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
16892 // Check RHS for vnot
16893 if (N1.getOpcode() == ISD::XOR &&
16894 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
16895 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
16896 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
16901 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
16902 TargetLowering::DAGCombinerInfo &DCI,
16903 const X86Subtarget *Subtarget) {
16904 EVT VT = N->getValueType(0);
16905 if (DCI.isBeforeLegalizeOps())
16908 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16912 SDValue N0 = N->getOperand(0);
16913 SDValue N1 = N->getOperand(1);
16915 // look for psign/blend
16916 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
16917 if (!Subtarget->hasSSSE3() ||
16918 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
16921 // Canonicalize pandn to RHS
16922 if (N0.getOpcode() == X86ISD::ANDNP)
16924 // or (and (m, y), (pandn m, x))
16925 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16926 SDValue Mask = N1.getOperand(0);
16927 SDValue X = N1.getOperand(1);
16929 if (N0.getOperand(0) == Mask)
16930 Y = N0.getOperand(1);
16931 if (N0.getOperand(1) == Mask)
16932 Y = N0.getOperand(0);
16934 // Check to see if the mask appeared in both the AND and ANDNP and
16938 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
16939 // Look through mask bitcast.
16940 if (Mask.getOpcode() == ISD::BITCAST)
16941 Mask = Mask.getOperand(0);
16942 if (X.getOpcode() == ISD::BITCAST)
16943 X = X.getOperand(0);
16944 if (Y.getOpcode() == ISD::BITCAST)
16945 Y = Y.getOperand(0);
16947 EVT MaskVT = Mask.getValueType();
16949 // Validate that the Mask operand is a vector sra node.
16950 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
16951 // there is no psrai.b
16952 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
16953 unsigned SraAmt = ~0;
16954 if (Mask.getOpcode() == ISD::SRA) {
16955 SDValue Amt = Mask.getOperand(1);
16956 if (isSplatVector(Amt.getNode())) {
16957 SDValue SclrAmt = Amt->getOperand(0);
16958 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
16959 SraAmt = C->getZExtValue();
16961 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
16962 SDValue SraC = Mask.getOperand(1);
16963 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
16965 if ((SraAmt + 1) != EltBits)
16970 // Now we know we at least have a plendvb with the mask val. See if
16971 // we can form a psignb/w/d.
16972 // psign = x.type == y.type == mask.type && y = sub(0, x);
16973 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16974 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
16975 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
16976 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
16977 "Unsupported VT for PSIGN");
16978 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
16979 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16981 // PBLENDVB only available on SSE 4.1
16982 if (!Subtarget->hasSSE41())
16985 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
16987 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
16988 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
16989 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
16990 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
16991 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16995 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
16998 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
16999 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
17001 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
17003 if (!N0.hasOneUse() || !N1.hasOneUse())
17006 SDValue ShAmt0 = N0.getOperand(1);
17007 if (ShAmt0.getValueType() != MVT::i8)
17009 SDValue ShAmt1 = N1.getOperand(1);
17010 if (ShAmt1.getValueType() != MVT::i8)
17012 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
17013 ShAmt0 = ShAmt0.getOperand(0);
17014 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
17015 ShAmt1 = ShAmt1.getOperand(0);
17018 unsigned Opc = X86ISD::SHLD;
17019 SDValue Op0 = N0.getOperand(0);
17020 SDValue Op1 = N1.getOperand(0);
17021 if (ShAmt0.getOpcode() == ISD::SUB) {
17022 Opc = X86ISD::SHRD;
17023 std::swap(Op0, Op1);
17024 std::swap(ShAmt0, ShAmt1);
17027 unsigned Bits = VT.getSizeInBits();
17028 if (ShAmt1.getOpcode() == ISD::SUB) {
17029 SDValue Sum = ShAmt1.getOperand(0);
17030 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
17031 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
17032 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
17033 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
17034 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
17035 return DAG.getNode(Opc, DL, VT,
17037 DAG.getNode(ISD::TRUNCATE, DL,
17040 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
17041 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
17043 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
17044 return DAG.getNode(Opc, DL, VT,
17045 N0.getOperand(0), N1.getOperand(0),
17046 DAG.getNode(ISD::TRUNCATE, DL,
17053 // Generate NEG and CMOV for integer abs.
17054 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
17055 EVT VT = N->getValueType(0);
17057 // Since X86 does not have CMOV for 8-bit integer, we don't convert
17058 // 8-bit integer abs to NEG and CMOV.
17059 if (VT.isInteger() && VT.getSizeInBits() == 8)
17062 SDValue N0 = N->getOperand(0);
17063 SDValue N1 = N->getOperand(1);
17066 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
17067 // and change it to SUB and CMOV.
17068 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
17069 N0.getOpcode() == ISD::ADD &&
17070 N0.getOperand(1) == N1 &&
17071 N1.getOpcode() == ISD::SRA &&
17072 N1.getOperand(0) == N0.getOperand(0))
17073 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
17074 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
17075 // Generate SUB & CMOV.
17076 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
17077 DAG.getConstant(0, VT), N0.getOperand(0));
17079 SDValue Ops[] = { N0.getOperand(0), Neg,
17080 DAG.getConstant(X86::COND_GE, MVT::i8),
17081 SDValue(Neg.getNode(), 1) };
17082 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
17083 Ops, array_lengthof(Ops));
17088 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
17089 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
17090 TargetLowering::DAGCombinerInfo &DCI,
17091 const X86Subtarget *Subtarget) {
17092 EVT VT = N->getValueType(0);
17093 if (DCI.isBeforeLegalizeOps())
17096 if (Subtarget->hasCMov()) {
17097 SDValue RV = performIntegerAbsCombine(N, DAG);
17102 // Try forming BMI if it is available.
17103 if (!Subtarget->hasBMI())
17106 if (VT != MVT::i32 && VT != MVT::i64)
17109 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
17111 // Create BLSMSK instructions by finding X ^ (X-1)
17112 SDValue N0 = N->getOperand(0);
17113 SDValue N1 = N->getOperand(1);
17116 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
17117 isAllOnes(N0.getOperand(1)))
17118 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
17120 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
17121 isAllOnes(N1.getOperand(1)))
17122 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
17127 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
17128 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
17129 TargetLowering::DAGCombinerInfo &DCI,
17130 const X86Subtarget *Subtarget) {
17131 LoadSDNode *Ld = cast<LoadSDNode>(N);
17132 EVT RegVT = Ld->getValueType(0);
17133 EVT MemVT = Ld->getMemoryVT();
17135 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17136 unsigned RegSz = RegVT.getSizeInBits();
17138 // On Sandybridge unaligned 256bit loads are inefficient.
17139 ISD::LoadExtType Ext = Ld->getExtensionType();
17140 unsigned Alignment = Ld->getAlignment();
17141 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
17142 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
17143 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
17144 unsigned NumElems = RegVT.getVectorNumElements();
17148 SDValue Ptr = Ld->getBasePtr();
17149 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
17151 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17153 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17154 Ld->getPointerInfo(), Ld->isVolatile(),
17155 Ld->isNonTemporal(), Ld->isInvariant(),
17157 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17158 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
17159 Ld->getPointerInfo(), Ld->isVolatile(),
17160 Ld->isNonTemporal(), Ld->isInvariant(),
17161 std::min(16U, Alignment));
17162 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
17164 Load2.getValue(1));
17166 SDValue NewVec = DAG.getUNDEF(RegVT);
17167 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
17168 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
17169 return DCI.CombineTo(N, NewVec, TF, true);
17172 // If this is a vector EXT Load then attempt to optimize it using a
17173 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
17174 // expansion is still better than scalar code.
17175 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
17176 // emit a shuffle and a arithmetic shift.
17177 // TODO: It is possible to support ZExt by zeroing the undef values
17178 // during the shuffle phase or after the shuffle.
17179 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
17180 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
17181 assert(MemVT != RegVT && "Cannot extend to the same type");
17182 assert(MemVT.isVector() && "Must load a vector from memory");
17184 unsigned NumElems = RegVT.getVectorNumElements();
17185 unsigned MemSz = MemVT.getSizeInBits();
17186 assert(RegSz > MemSz && "Register size must be greater than the mem size");
17188 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
17191 // All sizes must be a power of two.
17192 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
17195 // Attempt to load the original value using scalar loads.
17196 // Find the largest scalar type that divides the total loaded size.
17197 MVT SclrLoadTy = MVT::i8;
17198 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17199 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17200 MVT Tp = (MVT::SimpleValueType)tp;
17201 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
17206 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17207 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
17209 SclrLoadTy = MVT::f64;
17211 // Calculate the number of scalar loads that we need to perform
17212 // in order to load our vector from memory.
17213 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
17214 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
17217 unsigned loadRegZize = RegSz;
17218 if (Ext == ISD::SEXTLOAD && RegSz == 256)
17221 // Represent our vector as a sequence of elements which are the
17222 // largest scalar that we can load.
17223 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
17224 loadRegZize/SclrLoadTy.getSizeInBits());
17226 // Represent the data using the same element type that is stored in
17227 // memory. In practice, we ''widen'' MemVT.
17229 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
17230 loadRegZize/MemVT.getScalarType().getSizeInBits());
17232 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
17233 "Invalid vector type");
17235 // We can't shuffle using an illegal type.
17236 if (!TLI.isTypeLegal(WideVecVT))
17239 SmallVector<SDValue, 8> Chains;
17240 SDValue Ptr = Ld->getBasePtr();
17241 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
17242 TLI.getPointerTy());
17243 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
17245 for (unsigned i = 0; i < NumLoads; ++i) {
17246 // Perform a single load.
17247 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
17248 Ptr, Ld->getPointerInfo(),
17249 Ld->isVolatile(), Ld->isNonTemporal(),
17250 Ld->isInvariant(), Ld->getAlignment());
17251 Chains.push_back(ScalarLoad.getValue(1));
17252 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
17253 // another round of DAGCombining.
17255 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
17257 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
17258 ScalarLoad, DAG.getIntPtrConstant(i));
17260 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17263 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17266 // Bitcast the loaded value to a vector of the original element type, in
17267 // the size of the target vector type.
17268 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
17269 unsigned SizeRatio = RegSz/MemSz;
17271 if (Ext == ISD::SEXTLOAD) {
17272 // If we have SSE4.1 we can directly emit a VSEXT node.
17273 if (Subtarget->hasSSE41()) {
17274 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
17275 return DCI.CombineTo(N, Sext, TF, true);
17278 // Otherwise we'll shuffle the small elements in the high bits of the
17279 // larger type and perform an arithmetic shift. If the shift is not legal
17280 // it's better to scalarize.
17281 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
17284 // Redistribute the loaded elements into the different locations.
17285 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17286 for (unsigned i = 0; i != NumElems; ++i)
17287 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
17289 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
17290 DAG.getUNDEF(WideVecVT),
17293 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
17295 // Build the arithmetic shift.
17296 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
17297 MemVT.getVectorElementType().getSizeInBits();
17298 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
17299 DAG.getConstant(Amt, RegVT));
17301 return DCI.CombineTo(N, Shuff, TF, true);
17304 // Redistribute the loaded elements into the different locations.
17305 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17306 for (unsigned i = 0; i != NumElems; ++i)
17307 ShuffleVec[i*SizeRatio] = i;
17309 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
17310 DAG.getUNDEF(WideVecVT),
17313 // Bitcast to the requested type.
17314 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
17315 // Replace the original load with the new sequence
17316 // and return the new chain.
17317 return DCI.CombineTo(N, Shuff, TF, true);
17323 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
17324 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
17325 const X86Subtarget *Subtarget) {
17326 StoreSDNode *St = cast<StoreSDNode>(N);
17327 EVT VT = St->getValue().getValueType();
17328 EVT StVT = St->getMemoryVT();
17330 SDValue StoredVal = St->getOperand(1);
17331 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17333 // If we are saving a concatenation of two XMM registers, perform two stores.
17334 // On Sandy Bridge, 256-bit memory operations are executed by two
17335 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
17336 // memory operation.
17337 unsigned Alignment = St->getAlignment();
17338 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
17339 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
17340 StVT == VT && !IsAligned) {
17341 unsigned NumElems = VT.getVectorNumElements();
17345 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
17346 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
17348 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
17349 SDValue Ptr0 = St->getBasePtr();
17350 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
17352 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
17353 St->getPointerInfo(), St->isVolatile(),
17354 St->isNonTemporal(), Alignment);
17355 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
17356 St->getPointerInfo(), St->isVolatile(),
17357 St->isNonTemporal(),
17358 std::min(16U, Alignment));
17359 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
17362 // Optimize trunc store (of multiple scalars) to shuffle and store.
17363 // First, pack all of the elements in one place. Next, store to memory
17364 // in fewer chunks.
17365 if (St->isTruncatingStore() && VT.isVector()) {
17366 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17367 unsigned NumElems = VT.getVectorNumElements();
17368 assert(StVT != VT && "Cannot truncate to the same type");
17369 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
17370 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
17372 // From, To sizes and ElemCount must be pow of two
17373 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
17374 // We are going to use the original vector elt for storing.
17375 // Accumulated smaller vector elements must be a multiple of the store size.
17376 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
17378 unsigned SizeRatio = FromSz / ToSz;
17380 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
17382 // Create a type on which we perform the shuffle
17383 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
17384 StVT.getScalarType(), NumElems*SizeRatio);
17386 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
17388 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
17389 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17390 for (unsigned i = 0; i != NumElems; ++i)
17391 ShuffleVec[i] = i * SizeRatio;
17393 // Can't shuffle using an illegal type.
17394 if (!TLI.isTypeLegal(WideVecVT))
17397 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
17398 DAG.getUNDEF(WideVecVT),
17400 // At this point all of the data is stored at the bottom of the
17401 // register. We now need to save it to mem.
17403 // Find the largest store unit
17404 MVT StoreType = MVT::i8;
17405 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17406 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17407 MVT Tp = (MVT::SimpleValueType)tp;
17408 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
17412 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17413 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
17414 (64 <= NumElems * ToSz))
17415 StoreType = MVT::f64;
17417 // Bitcast the original vector into a vector of store-size units
17418 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
17419 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
17420 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
17421 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
17422 SmallVector<SDValue, 8> Chains;
17423 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
17424 TLI.getPointerTy());
17425 SDValue Ptr = St->getBasePtr();
17427 // Perform one or more big stores into memory.
17428 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
17429 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
17430 StoreType, ShuffWide,
17431 DAG.getIntPtrConstant(i));
17432 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
17433 St->getPointerInfo(), St->isVolatile(),
17434 St->isNonTemporal(), St->getAlignment());
17435 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17436 Chains.push_back(Ch);
17439 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17443 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
17444 // the FP state in cases where an emms may be missing.
17445 // A preferable solution to the general problem is to figure out the right
17446 // places to insert EMMS. This qualifies as a quick hack.
17448 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
17449 if (VT.getSizeInBits() != 64)
17452 const Function *F = DAG.getMachineFunction().getFunction();
17453 bool NoImplicitFloatOps = F->getAttributes().
17454 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
17455 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
17456 && Subtarget->hasSSE2();
17457 if ((VT.isVector() ||
17458 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
17459 isa<LoadSDNode>(St->getValue()) &&
17460 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
17461 St->getChain().hasOneUse() && !St->isVolatile()) {
17462 SDNode* LdVal = St->getValue().getNode();
17463 LoadSDNode *Ld = 0;
17464 int TokenFactorIndex = -1;
17465 SmallVector<SDValue, 8> Ops;
17466 SDNode* ChainVal = St->getChain().getNode();
17467 // Must be a store of a load. We currently handle two cases: the load
17468 // is a direct child, and it's under an intervening TokenFactor. It is
17469 // possible to dig deeper under nested TokenFactors.
17470 if (ChainVal == LdVal)
17471 Ld = cast<LoadSDNode>(St->getChain());
17472 else if (St->getValue().hasOneUse() &&
17473 ChainVal->getOpcode() == ISD::TokenFactor) {
17474 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
17475 if (ChainVal->getOperand(i).getNode() == LdVal) {
17476 TokenFactorIndex = i;
17477 Ld = cast<LoadSDNode>(St->getValue());
17479 Ops.push_back(ChainVal->getOperand(i));
17483 if (!Ld || !ISD::isNormalLoad(Ld))
17486 // If this is not the MMX case, i.e. we are just turning i64 load/store
17487 // into f64 load/store, avoid the transformation if there are multiple
17488 // uses of the loaded value.
17489 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
17494 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
17495 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
17497 if (Subtarget->is64Bit() || F64IsLegal) {
17498 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
17499 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
17500 Ld->getPointerInfo(), Ld->isVolatile(),
17501 Ld->isNonTemporal(), Ld->isInvariant(),
17502 Ld->getAlignment());
17503 SDValue NewChain = NewLd.getValue(1);
17504 if (TokenFactorIndex != -1) {
17505 Ops.push_back(NewChain);
17506 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17509 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
17510 St->getPointerInfo(),
17511 St->isVolatile(), St->isNonTemporal(),
17512 St->getAlignment());
17515 // Otherwise, lower to two pairs of 32-bit loads / stores.
17516 SDValue LoAddr = Ld->getBasePtr();
17517 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
17518 DAG.getConstant(4, MVT::i32));
17520 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
17521 Ld->getPointerInfo(),
17522 Ld->isVolatile(), Ld->isNonTemporal(),
17523 Ld->isInvariant(), Ld->getAlignment());
17524 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
17525 Ld->getPointerInfo().getWithOffset(4),
17526 Ld->isVolatile(), Ld->isNonTemporal(),
17528 MinAlign(Ld->getAlignment(), 4));
17530 SDValue NewChain = LoLd.getValue(1);
17531 if (TokenFactorIndex != -1) {
17532 Ops.push_back(LoLd);
17533 Ops.push_back(HiLd);
17534 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17538 LoAddr = St->getBasePtr();
17539 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
17540 DAG.getConstant(4, MVT::i32));
17542 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
17543 St->getPointerInfo(),
17544 St->isVolatile(), St->isNonTemporal(),
17545 St->getAlignment());
17546 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
17547 St->getPointerInfo().getWithOffset(4),
17549 St->isNonTemporal(),
17550 MinAlign(St->getAlignment(), 4));
17551 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
17556 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
17557 /// and return the operands for the horizontal operation in LHS and RHS. A
17558 /// horizontal operation performs the binary operation on successive elements
17559 /// of its first operand, then on successive elements of its second operand,
17560 /// returning the resulting values in a vector. For example, if
17561 /// A = < float a0, float a1, float a2, float a3 >
17563 /// B = < float b0, float b1, float b2, float b3 >
17564 /// then the result of doing a horizontal operation on A and B is
17565 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
17566 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
17567 /// A horizontal-op B, for some already available A and B, and if so then LHS is
17568 /// set to A, RHS to B, and the routine returns 'true'.
17569 /// Note that the binary operation should have the property that if one of the
17570 /// operands is UNDEF then the result is UNDEF.
17571 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
17572 // Look for the following pattern: if
17573 // A = < float a0, float a1, float a2, float a3 >
17574 // B = < float b0, float b1, float b2, float b3 >
17576 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
17577 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
17578 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
17579 // which is A horizontal-op B.
17581 // At least one of the operands should be a vector shuffle.
17582 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
17583 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
17586 EVT VT = LHS.getValueType();
17588 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17589 "Unsupported vector type for horizontal add/sub");
17591 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
17592 // operate independently on 128-bit lanes.
17593 unsigned NumElts = VT.getVectorNumElements();
17594 unsigned NumLanes = VT.getSizeInBits()/128;
17595 unsigned NumLaneElts = NumElts / NumLanes;
17596 assert((NumLaneElts % 2 == 0) &&
17597 "Vector type should have an even number of elements in each lane");
17598 unsigned HalfLaneElts = NumLaneElts/2;
17600 // View LHS in the form
17601 // LHS = VECTOR_SHUFFLE A, B, LMask
17602 // If LHS is not a shuffle then pretend it is the shuffle
17603 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
17604 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
17607 SmallVector<int, 16> LMask(NumElts);
17608 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17609 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
17610 A = LHS.getOperand(0);
17611 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
17612 B = LHS.getOperand(1);
17613 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
17614 std::copy(Mask.begin(), Mask.end(), LMask.begin());
17616 if (LHS.getOpcode() != ISD::UNDEF)
17618 for (unsigned i = 0; i != NumElts; ++i)
17622 // Likewise, view RHS in the form
17623 // RHS = VECTOR_SHUFFLE C, D, RMask
17625 SmallVector<int, 16> RMask(NumElts);
17626 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17627 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
17628 C = RHS.getOperand(0);
17629 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
17630 D = RHS.getOperand(1);
17631 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
17632 std::copy(Mask.begin(), Mask.end(), RMask.begin());
17634 if (RHS.getOpcode() != ISD::UNDEF)
17636 for (unsigned i = 0; i != NumElts; ++i)
17640 // Check that the shuffles are both shuffling the same vectors.
17641 if (!(A == C && B == D) && !(A == D && B == C))
17644 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
17645 if (!A.getNode() && !B.getNode())
17648 // If A and B occur in reverse order in RHS, then "swap" them (which means
17649 // rewriting the mask).
17651 CommuteVectorShuffleMask(RMask, NumElts);
17653 // At this point LHS and RHS are equivalent to
17654 // LHS = VECTOR_SHUFFLE A, B, LMask
17655 // RHS = VECTOR_SHUFFLE A, B, RMask
17656 // Check that the masks correspond to performing a horizontal operation.
17657 for (unsigned i = 0; i != NumElts; ++i) {
17658 int LIdx = LMask[i], RIdx = RMask[i];
17660 // Ignore any UNDEF components.
17661 if (LIdx < 0 || RIdx < 0 ||
17662 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
17663 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
17666 // Check that successive elements are being operated on. If not, this is
17667 // not a horizontal operation.
17668 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
17669 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
17670 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
17671 if (!(LIdx == Index && RIdx == Index + 1) &&
17672 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
17676 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
17677 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
17681 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
17682 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
17683 const X86Subtarget *Subtarget) {
17684 EVT VT = N->getValueType(0);
17685 SDValue LHS = N->getOperand(0);
17686 SDValue RHS = N->getOperand(1);
17688 // Try to synthesize horizontal adds from adds of shuffles.
17689 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17690 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17691 isHorizontalBinOp(LHS, RHS, true))
17692 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
17696 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
17697 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
17698 const X86Subtarget *Subtarget) {
17699 EVT VT = N->getValueType(0);
17700 SDValue LHS = N->getOperand(0);
17701 SDValue RHS = N->getOperand(1);
17703 // Try to synthesize horizontal subs from subs of shuffles.
17704 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17705 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17706 isHorizontalBinOp(LHS, RHS, false))
17707 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
17711 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
17712 /// X86ISD::FXOR nodes.
17713 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
17714 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
17715 // F[X]OR(0.0, x) -> x
17716 // F[X]OR(x, 0.0) -> x
17717 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17718 if (C->getValueAPF().isPosZero())
17719 return N->getOperand(1);
17720 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17721 if (C->getValueAPF().isPosZero())
17722 return N->getOperand(0);
17726 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
17727 /// X86ISD::FMAX nodes.
17728 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
17729 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
17731 // Only perform optimizations if UnsafeMath is used.
17732 if (!DAG.getTarget().Options.UnsafeFPMath)
17735 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
17736 // into FMINC and FMAXC, which are Commutative operations.
17737 unsigned NewOp = 0;
17738 switch (N->getOpcode()) {
17739 default: llvm_unreachable("unknown opcode");
17740 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
17741 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
17744 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
17745 N->getOperand(0), N->getOperand(1));
17748 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
17749 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
17750 // FAND(0.0, x) -> 0.0
17751 // FAND(x, 0.0) -> 0.0
17752 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17753 if (C->getValueAPF().isPosZero())
17754 return N->getOperand(0);
17755 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17756 if (C->getValueAPF().isPosZero())
17757 return N->getOperand(1);
17761 static SDValue PerformBTCombine(SDNode *N,
17763 TargetLowering::DAGCombinerInfo &DCI) {
17764 // BT ignores high bits in the bit index operand.
17765 SDValue Op1 = N->getOperand(1);
17766 if (Op1.hasOneUse()) {
17767 unsigned BitWidth = Op1.getValueSizeInBits();
17768 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
17769 APInt KnownZero, KnownOne;
17770 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
17771 !DCI.isBeforeLegalizeOps());
17772 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17773 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
17774 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
17775 DCI.CommitTargetLoweringOpt(TLO);
17780 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
17781 SDValue Op = N->getOperand(0);
17782 if (Op.getOpcode() == ISD::BITCAST)
17783 Op = Op.getOperand(0);
17784 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
17785 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
17786 VT.getVectorElementType().getSizeInBits() ==
17787 OpVT.getVectorElementType().getSizeInBits()) {
17788 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
17793 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
17794 const X86Subtarget *Subtarget) {
17795 EVT VT = N->getValueType(0);
17796 if (!VT.isVector())
17799 SDValue N0 = N->getOperand(0);
17800 SDValue N1 = N->getOperand(1);
17801 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
17804 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
17805 // both SSE and AVX2 since there is no sign-extended shift right
17806 // operation on a vector with 64-bit elements.
17807 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
17808 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
17809 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
17810 N0.getOpcode() == ISD::SIGN_EXTEND)) {
17811 SDValue N00 = N0.getOperand(0);
17813 // EXTLOAD has a better solution on AVX2,
17814 // it may be replaced with X86ISD::VSEXT node.
17815 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
17816 if (!ISD::isNormalLoad(N00.getNode()))
17819 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
17820 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
17822 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
17828 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
17829 TargetLowering::DAGCombinerInfo &DCI,
17830 const X86Subtarget *Subtarget) {
17831 if (!DCI.isBeforeLegalizeOps())
17834 if (!Subtarget->hasFp256())
17837 EVT VT = N->getValueType(0);
17838 if (VT.isVector() && VT.getSizeInBits() == 256) {
17839 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17847 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
17848 const X86Subtarget* Subtarget) {
17850 EVT VT = N->getValueType(0);
17852 // Let legalize expand this if it isn't a legal type yet.
17853 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17856 EVT ScalarVT = VT.getScalarType();
17857 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
17858 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
17861 SDValue A = N->getOperand(0);
17862 SDValue B = N->getOperand(1);
17863 SDValue C = N->getOperand(2);
17865 bool NegA = (A.getOpcode() == ISD::FNEG);
17866 bool NegB = (B.getOpcode() == ISD::FNEG);
17867 bool NegC = (C.getOpcode() == ISD::FNEG);
17869 // Negative multiplication when NegA xor NegB
17870 bool NegMul = (NegA != NegB);
17872 A = A.getOperand(0);
17874 B = B.getOperand(0);
17876 C = C.getOperand(0);
17880 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
17882 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
17884 return DAG.getNode(Opcode, dl, VT, A, B, C);
17887 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
17888 TargetLowering::DAGCombinerInfo &DCI,
17889 const X86Subtarget *Subtarget) {
17890 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
17891 // (and (i32 x86isd::setcc_carry), 1)
17892 // This eliminates the zext. This transformation is necessary because
17893 // ISD::SETCC is always legalized to i8.
17895 SDValue N0 = N->getOperand(0);
17896 EVT VT = N->getValueType(0);
17898 if (N0.getOpcode() == ISD::AND &&
17900 N0.getOperand(0).hasOneUse()) {
17901 SDValue N00 = N0.getOperand(0);
17902 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
17903 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17904 if (!C || C->getZExtValue() != 1)
17906 return DAG.getNode(ISD::AND, dl, VT,
17907 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
17908 N00.getOperand(0), N00.getOperand(1)),
17909 DAG.getConstant(1, VT));
17913 if (VT.is256BitVector()) {
17914 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17922 // Optimize x == -y --> x+y == 0
17923 // x != -y --> x+y != 0
17924 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
17925 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
17926 SDValue LHS = N->getOperand(0);
17927 SDValue RHS = N->getOperand(1);
17929 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17930 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
17931 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
17932 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
17933 LHS.getValueType(), RHS, LHS.getOperand(1));
17934 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
17935 addV, DAG.getConstant(0, addV.getValueType()), CC);
17937 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17938 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
17939 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
17940 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
17941 RHS.getValueType(), LHS, RHS.getOperand(1));
17942 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
17943 addV, DAG.getConstant(0, addV.getValueType()), CC);
17948 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
17949 // as "sbb reg,reg", since it can be extended without zext and produces
17950 // an all-ones bit which is more useful than 0/1 in some cases.
17951 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
17952 return DAG.getNode(ISD::AND, DL, MVT::i8,
17953 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
17954 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
17955 DAG.getConstant(1, MVT::i8));
17958 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
17959 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
17960 TargetLowering::DAGCombinerInfo &DCI,
17961 const X86Subtarget *Subtarget) {
17963 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
17964 SDValue EFLAGS = N->getOperand(1);
17966 if (CC == X86::COND_A) {
17967 // Try to convert COND_A into COND_B in an attempt to facilitate
17968 // materializing "setb reg".
17970 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
17971 // cannot take an immediate as its first operand.
17973 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
17974 EFLAGS.getValueType().isInteger() &&
17975 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
17976 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
17977 EFLAGS.getNode()->getVTList(),
17978 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
17979 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
17980 return MaterializeSETB(DL, NewEFLAGS, DAG);
17984 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
17985 // a zext and produces an all-ones bit which is more useful than 0/1 in some
17987 if (CC == X86::COND_B)
17988 return MaterializeSETB(DL, EFLAGS, DAG);
17992 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17993 if (Flags.getNode()) {
17994 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17995 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
18001 // Optimize branch condition evaluation.
18003 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
18004 TargetLowering::DAGCombinerInfo &DCI,
18005 const X86Subtarget *Subtarget) {
18007 SDValue Chain = N->getOperand(0);
18008 SDValue Dest = N->getOperand(1);
18009 SDValue EFLAGS = N->getOperand(3);
18010 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
18014 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
18015 if (Flags.getNode()) {
18016 SDValue Cond = DAG.getConstant(CC, MVT::i8);
18017 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
18024 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
18025 const X86TargetLowering *XTLI) {
18026 SDValue Op0 = N->getOperand(0);
18027 EVT InVT = Op0->getValueType(0);
18029 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
18030 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
18032 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
18033 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
18034 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
18037 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
18038 // a 32-bit target where SSE doesn't support i64->FP operations.
18039 if (Op0.getOpcode() == ISD::LOAD) {
18040 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
18041 EVT VT = Ld->getValueType(0);
18042 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
18043 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
18044 !XTLI->getSubtarget()->is64Bit() &&
18045 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18046 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
18047 Ld->getChain(), Op0, DAG);
18048 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
18055 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
18056 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
18057 X86TargetLowering::DAGCombinerInfo &DCI) {
18058 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
18059 // the result is either zero or one (depending on the input carry bit).
18060 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
18061 if (X86::isZeroNode(N->getOperand(0)) &&
18062 X86::isZeroNode(N->getOperand(1)) &&
18063 // We don't have a good way to replace an EFLAGS use, so only do this when
18065 SDValue(N, 1).use_empty()) {
18067 EVT VT = N->getValueType(0);
18068 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
18069 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
18070 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
18071 DAG.getConstant(X86::COND_B,MVT::i8),
18073 DAG.getConstant(1, VT));
18074 return DCI.CombineTo(N, Res1, CarryOut);
18080 // fold (add Y, (sete X, 0)) -> adc 0, Y
18081 // (add Y, (setne X, 0)) -> sbb -1, Y
18082 // (sub (sete X, 0), Y) -> sbb 0, Y
18083 // (sub (setne X, 0), Y) -> adc -1, Y
18084 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
18087 // Look through ZExts.
18088 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
18089 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
18092 SDValue SetCC = Ext.getOperand(0);
18093 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
18096 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
18097 if (CC != X86::COND_E && CC != X86::COND_NE)
18100 SDValue Cmp = SetCC.getOperand(1);
18101 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
18102 !X86::isZeroNode(Cmp.getOperand(1)) ||
18103 !Cmp.getOperand(0).getValueType().isInteger())
18106 SDValue CmpOp0 = Cmp.getOperand(0);
18107 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
18108 DAG.getConstant(1, CmpOp0.getValueType()));
18110 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
18111 if (CC == X86::COND_NE)
18112 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
18113 DL, OtherVal.getValueType(), OtherVal,
18114 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
18115 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
18116 DL, OtherVal.getValueType(), OtherVal,
18117 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
18120 /// PerformADDCombine - Do target-specific dag combines on integer adds.
18121 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
18122 const X86Subtarget *Subtarget) {
18123 EVT VT = N->getValueType(0);
18124 SDValue Op0 = N->getOperand(0);
18125 SDValue Op1 = N->getOperand(1);
18127 // Try to synthesize horizontal adds from adds of shuffles.
18128 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18129 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18130 isHorizontalBinOp(Op0, Op1, true))
18131 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
18133 return OptimizeConditionalInDecrement(N, DAG);
18136 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
18137 const X86Subtarget *Subtarget) {
18138 SDValue Op0 = N->getOperand(0);
18139 SDValue Op1 = N->getOperand(1);
18141 // X86 can't encode an immediate LHS of a sub. See if we can push the
18142 // negation into a preceding instruction.
18143 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
18144 // If the RHS of the sub is a XOR with one use and a constant, invert the
18145 // immediate. Then add one to the LHS of the sub so we can turn
18146 // X-Y -> X+~Y+1, saving one register.
18147 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
18148 isa<ConstantSDNode>(Op1.getOperand(1))) {
18149 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
18150 EVT VT = Op0.getValueType();
18151 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
18153 DAG.getConstant(~XorC, VT));
18154 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
18155 DAG.getConstant(C->getAPIntValue()+1, VT));
18159 // Try to synthesize horizontal adds from adds of shuffles.
18160 EVT VT = N->getValueType(0);
18161 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
18162 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
18163 isHorizontalBinOp(Op0, Op1, true))
18164 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
18166 return OptimizeConditionalInDecrement(N, DAG);
18169 /// performVZEXTCombine - Performs build vector combines
18170 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
18171 TargetLowering::DAGCombinerInfo &DCI,
18172 const X86Subtarget *Subtarget) {
18173 // (vzext (bitcast (vzext (x)) -> (vzext x)
18174 SDValue In = N->getOperand(0);
18175 while (In.getOpcode() == ISD::BITCAST)
18176 In = In.getOperand(0);
18178 if (In.getOpcode() != X86ISD::VZEXT)
18181 return DAG.getNode(X86ISD::VZEXT, SDLoc(N), N->getValueType(0),
18185 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
18186 DAGCombinerInfo &DCI) const {
18187 SelectionDAG &DAG = DCI.DAG;
18188 switch (N->getOpcode()) {
18190 case ISD::EXTRACT_VECTOR_ELT:
18191 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
18193 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
18194 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
18195 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
18196 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
18197 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
18198 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
18201 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
18202 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
18203 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
18204 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
18205 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
18206 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
18207 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
18208 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
18209 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
18211 case X86ISD::FOR: return PerformFORCombine(N, DAG);
18213 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
18214 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
18215 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
18216 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
18217 case ISD::ANY_EXTEND:
18218 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
18219 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
18220 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
18221 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
18222 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
18223 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
18224 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
18225 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
18226 case X86ISD::SHUFP: // Handle all target specific shuffles
18227 case X86ISD::PALIGNR:
18228 case X86ISD::UNPCKH:
18229 case X86ISD::UNPCKL:
18230 case X86ISD::MOVHLPS:
18231 case X86ISD::MOVLHPS:
18232 case X86ISD::PSHUFD:
18233 case X86ISD::PSHUFHW:
18234 case X86ISD::PSHUFLW:
18235 case X86ISD::MOVSS:
18236 case X86ISD::MOVSD:
18237 case X86ISD::VPERMILP:
18238 case X86ISD::VPERM2X128:
18239 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
18240 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
18246 /// isTypeDesirableForOp - Return true if the target has native support for
18247 /// the specified value type and it is 'desirable' to use the type for the
18248 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
18249 /// instruction encodings are longer and some i16 instructions are slow.
18250 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
18251 if (!isTypeLegal(VT))
18253 if (VT != MVT::i16)
18260 case ISD::SIGN_EXTEND:
18261 case ISD::ZERO_EXTEND:
18262 case ISD::ANY_EXTEND:
18275 /// IsDesirableToPromoteOp - This method query the target whether it is
18276 /// beneficial for dag combiner to promote the specified node. If true, it
18277 /// should return the desired promotion type by reference.
18278 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
18279 EVT VT = Op.getValueType();
18280 if (VT != MVT::i16)
18283 bool Promote = false;
18284 bool Commute = false;
18285 switch (Op.getOpcode()) {
18288 LoadSDNode *LD = cast<LoadSDNode>(Op);
18289 // If the non-extending load has a single use and it's not live out, then it
18290 // might be folded.
18291 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
18292 Op.hasOneUse()*/) {
18293 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
18294 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
18295 // The only case where we'd want to promote LOAD (rather then it being
18296 // promoted as an operand is when it's only use is liveout.
18297 if (UI->getOpcode() != ISD::CopyToReg)
18304 case ISD::SIGN_EXTEND:
18305 case ISD::ZERO_EXTEND:
18306 case ISD::ANY_EXTEND:
18311 SDValue N0 = Op.getOperand(0);
18312 // Look out for (store (shl (load), x)).
18313 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
18326 SDValue N0 = Op.getOperand(0);
18327 SDValue N1 = Op.getOperand(1);
18328 if (!Commute && MayFoldLoad(N1))
18330 // Avoid disabling potential load folding opportunities.
18331 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
18333 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
18343 //===----------------------------------------------------------------------===//
18344 // X86 Inline Assembly Support
18345 //===----------------------------------------------------------------------===//
18348 // Helper to match a string separated by whitespace.
18349 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
18350 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
18352 for (unsigned i = 0, e = args.size(); i != e; ++i) {
18353 StringRef piece(*args[i]);
18354 if (!s.startswith(piece)) // Check if the piece matches.
18357 s = s.substr(piece.size());
18358 StringRef::size_type pos = s.find_first_not_of(" \t");
18359 if (pos == 0) // We matched a prefix.
18367 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
18370 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
18371 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
18373 std::string AsmStr = IA->getAsmString();
18375 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
18376 if (!Ty || Ty->getBitWidth() % 16 != 0)
18379 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
18380 SmallVector<StringRef, 4> AsmPieces;
18381 SplitString(AsmStr, AsmPieces, ";\n");
18383 switch (AsmPieces.size()) {
18384 default: return false;
18386 // FIXME: this should verify that we are targeting a 486 or better. If not,
18387 // we will turn this bswap into something that will be lowered to logical
18388 // ops instead of emitting the bswap asm. For now, we don't support 486 or
18389 // lower so don't worry about this.
18391 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
18392 matchAsm(AsmPieces[0], "bswapl", "$0") ||
18393 matchAsm(AsmPieces[0], "bswapq", "$0") ||
18394 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
18395 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
18396 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
18397 // No need to check constraints, nothing other than the equivalent of
18398 // "=r,0" would be valid here.
18399 return IntrinsicLowering::LowerToByteSwap(CI);
18402 // rorw $$8, ${0:w} --> llvm.bswap.i16
18403 if (CI->getType()->isIntegerTy(16) &&
18404 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18405 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
18406 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
18408 const std::string &ConstraintsStr = IA->getConstraintString();
18409 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18410 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18411 if (AsmPieces.size() == 4 &&
18412 AsmPieces[0] == "~{cc}" &&
18413 AsmPieces[1] == "~{dirflag}" &&
18414 AsmPieces[2] == "~{flags}" &&
18415 AsmPieces[3] == "~{fpsr}")
18416 return IntrinsicLowering::LowerToByteSwap(CI);
18420 if (CI->getType()->isIntegerTy(32) &&
18421 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18422 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
18423 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
18424 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
18426 const std::string &ConstraintsStr = IA->getConstraintString();
18427 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18428 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18429 if (AsmPieces.size() == 4 &&
18430 AsmPieces[0] == "~{cc}" &&
18431 AsmPieces[1] == "~{dirflag}" &&
18432 AsmPieces[2] == "~{flags}" &&
18433 AsmPieces[3] == "~{fpsr}")
18434 return IntrinsicLowering::LowerToByteSwap(CI);
18437 if (CI->getType()->isIntegerTy(64)) {
18438 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
18439 if (Constraints.size() >= 2 &&
18440 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
18441 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
18442 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
18443 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
18444 matchAsm(AsmPieces[1], "bswap", "%edx") &&
18445 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
18446 return IntrinsicLowering::LowerToByteSwap(CI);
18454 /// getConstraintType - Given a constraint letter, return the type of
18455 /// constraint it is for this target.
18456 X86TargetLowering::ConstraintType
18457 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
18458 if (Constraint.size() == 1) {
18459 switch (Constraint[0]) {
18470 return C_RegisterClass;
18494 return TargetLowering::getConstraintType(Constraint);
18497 /// Examine constraint type and operand type and determine a weight value.
18498 /// This object must already have been set up with the operand type
18499 /// and the current alternative constraint selected.
18500 TargetLowering::ConstraintWeight
18501 X86TargetLowering::getSingleConstraintMatchWeight(
18502 AsmOperandInfo &info, const char *constraint) const {
18503 ConstraintWeight weight = CW_Invalid;
18504 Value *CallOperandVal = info.CallOperandVal;
18505 // If we don't have a value, we can't do a match,
18506 // but allow it at the lowest weight.
18507 if (CallOperandVal == NULL)
18509 Type *type = CallOperandVal->getType();
18510 // Look at the constraint type.
18511 switch (*constraint) {
18513 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
18524 if (CallOperandVal->getType()->isIntegerTy())
18525 weight = CW_SpecificReg;
18530 if (type->isFloatingPointTy())
18531 weight = CW_SpecificReg;
18534 if (type->isX86_MMXTy() && Subtarget->hasMMX())
18535 weight = CW_SpecificReg;
18539 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
18540 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
18541 weight = CW_Register;
18544 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
18545 if (C->getZExtValue() <= 31)
18546 weight = CW_Constant;
18550 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18551 if (C->getZExtValue() <= 63)
18552 weight = CW_Constant;
18556 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18557 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
18558 weight = CW_Constant;
18562 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18563 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
18564 weight = CW_Constant;
18568 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18569 if (C->getZExtValue() <= 3)
18570 weight = CW_Constant;
18574 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18575 if (C->getZExtValue() <= 0xff)
18576 weight = CW_Constant;
18581 if (dyn_cast<ConstantFP>(CallOperandVal)) {
18582 weight = CW_Constant;
18586 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18587 if ((C->getSExtValue() >= -0x80000000LL) &&
18588 (C->getSExtValue() <= 0x7fffffffLL))
18589 weight = CW_Constant;
18593 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18594 if (C->getZExtValue() <= 0xffffffff)
18595 weight = CW_Constant;
18602 /// LowerXConstraint - try to replace an X constraint, which matches anything,
18603 /// with another that has more specific requirements based on the type of the
18604 /// corresponding operand.
18605 const char *X86TargetLowering::
18606 LowerXConstraint(EVT ConstraintVT) const {
18607 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
18608 // 'f' like normal targets.
18609 if (ConstraintVT.isFloatingPoint()) {
18610 if (Subtarget->hasSSE2())
18612 if (Subtarget->hasSSE1())
18616 return TargetLowering::LowerXConstraint(ConstraintVT);
18619 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
18620 /// vector. If it is invalid, don't add anything to Ops.
18621 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
18622 std::string &Constraint,
18623 std::vector<SDValue>&Ops,
18624 SelectionDAG &DAG) const {
18625 SDValue Result(0, 0);
18627 // Only support length 1 constraints for now.
18628 if (Constraint.length() > 1) return;
18630 char ConstraintLetter = Constraint[0];
18631 switch (ConstraintLetter) {
18634 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18635 if (C->getZExtValue() <= 31) {
18636 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18642 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18643 if (C->getZExtValue() <= 63) {
18644 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18650 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18651 if (isInt<8>(C->getSExtValue())) {
18652 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18658 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18659 if (C->getZExtValue() <= 255) {
18660 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18666 // 32-bit signed value
18667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18668 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18669 C->getSExtValue())) {
18670 // Widen to 64 bits here to get it sign extended.
18671 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
18674 // FIXME gcc accepts some relocatable values here too, but only in certain
18675 // memory models; it's complicated.
18680 // 32-bit unsigned value
18681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18682 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18683 C->getZExtValue())) {
18684 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18688 // FIXME gcc accepts some relocatable values here too, but only in certain
18689 // memory models; it's complicated.
18693 // Literal immediates are always ok.
18694 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
18695 // Widen to 64 bits here to get it sign extended.
18696 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
18700 // In any sort of PIC mode addresses need to be computed at runtime by
18701 // adding in a register or some sort of table lookup. These can't
18702 // be used as immediates.
18703 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
18706 // If we are in non-pic codegen mode, we allow the address of a global (with
18707 // an optional displacement) to be used with 'i'.
18708 GlobalAddressSDNode *GA = 0;
18709 int64_t Offset = 0;
18711 // Match either (GA), (GA+C), (GA+C1+C2), etc.
18713 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
18714 Offset += GA->getOffset();
18716 } else if (Op.getOpcode() == ISD::ADD) {
18717 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
18718 Offset += C->getZExtValue();
18719 Op = Op.getOperand(0);
18722 } else if (Op.getOpcode() == ISD::SUB) {
18723 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
18724 Offset += -C->getZExtValue();
18725 Op = Op.getOperand(0);
18730 // Otherwise, this isn't something we can handle, reject it.
18734 const GlobalValue *GV = GA->getGlobal();
18735 // If we require an extra load to get this address, as in PIC mode, we
18736 // can't accept it.
18737 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
18738 getTargetMachine())))
18741 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
18742 GA->getValueType(0), Offset);
18747 if (Result.getNode()) {
18748 Ops.push_back(Result);
18751 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
18754 std::pair<unsigned, const TargetRegisterClass*>
18755 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
18757 // First, see if this is a constraint that directly corresponds to an LLVM
18759 if (Constraint.size() == 1) {
18760 // GCC Constraint Letters
18761 switch (Constraint[0]) {
18763 // TODO: Slight differences here in allocation order and leaving
18764 // RIP in the class. Do they matter any more here than they do
18765 // in the normal allocation?
18766 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
18767 if (Subtarget->is64Bit()) {
18768 if (VT == MVT::i32 || VT == MVT::f32)
18769 return std::make_pair(0U, &X86::GR32RegClass);
18770 if (VT == MVT::i16)
18771 return std::make_pair(0U, &X86::GR16RegClass);
18772 if (VT == MVT::i8 || VT == MVT::i1)
18773 return std::make_pair(0U, &X86::GR8RegClass);
18774 if (VT == MVT::i64 || VT == MVT::f64)
18775 return std::make_pair(0U, &X86::GR64RegClass);
18778 // 32-bit fallthrough
18779 case 'Q': // Q_REGS
18780 if (VT == MVT::i32 || VT == MVT::f32)
18781 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
18782 if (VT == MVT::i16)
18783 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
18784 if (VT == MVT::i8 || VT == MVT::i1)
18785 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
18786 if (VT == MVT::i64)
18787 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
18789 case 'r': // GENERAL_REGS
18790 case 'l': // INDEX_REGS
18791 if (VT == MVT::i8 || VT == MVT::i1)
18792 return std::make_pair(0U, &X86::GR8RegClass);
18793 if (VT == MVT::i16)
18794 return std::make_pair(0U, &X86::GR16RegClass);
18795 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
18796 return std::make_pair(0U, &X86::GR32RegClass);
18797 return std::make_pair(0U, &X86::GR64RegClass);
18798 case 'R': // LEGACY_REGS
18799 if (VT == MVT::i8 || VT == MVT::i1)
18800 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
18801 if (VT == MVT::i16)
18802 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
18803 if (VT == MVT::i32 || !Subtarget->is64Bit())
18804 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
18805 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
18806 case 'f': // FP Stack registers.
18807 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
18808 // value to the correct fpstack register class.
18809 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
18810 return std::make_pair(0U, &X86::RFP32RegClass);
18811 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
18812 return std::make_pair(0U, &X86::RFP64RegClass);
18813 return std::make_pair(0U, &X86::RFP80RegClass);
18814 case 'y': // MMX_REGS if MMX allowed.
18815 if (!Subtarget->hasMMX()) break;
18816 return std::make_pair(0U, &X86::VR64RegClass);
18817 case 'Y': // SSE_REGS if SSE2 allowed
18818 if (!Subtarget->hasSSE2()) break;
18820 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
18821 if (!Subtarget->hasSSE1()) break;
18823 switch (VT.SimpleTy) {
18825 // Scalar SSE types.
18828 return std::make_pair(0U, &X86::FR32RegClass);
18831 return std::make_pair(0U, &X86::FR64RegClass);
18839 return std::make_pair(0U, &X86::VR128RegClass);
18847 return std::make_pair(0U, &X86::VR256RegClass);
18852 return std::make_pair(0U, &X86::VR512RegClass);
18858 // Use the default implementation in TargetLowering to convert the register
18859 // constraint into a member of a register class.
18860 std::pair<unsigned, const TargetRegisterClass*> Res;
18861 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
18863 // Not found as a standard register?
18864 if (Res.second == 0) {
18865 // Map st(0) -> st(7) -> ST0
18866 if (Constraint.size() == 7 && Constraint[0] == '{' &&
18867 tolower(Constraint[1]) == 's' &&
18868 tolower(Constraint[2]) == 't' &&
18869 Constraint[3] == '(' &&
18870 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
18871 Constraint[5] == ')' &&
18872 Constraint[6] == '}') {
18874 Res.first = X86::ST0+Constraint[4]-'0';
18875 Res.second = &X86::RFP80RegClass;
18879 // GCC allows "st(0)" to be called just plain "st".
18880 if (StringRef("{st}").equals_lower(Constraint)) {
18881 Res.first = X86::ST0;
18882 Res.second = &X86::RFP80RegClass;
18887 if (StringRef("{flags}").equals_lower(Constraint)) {
18888 Res.first = X86::EFLAGS;
18889 Res.second = &X86::CCRRegClass;
18893 // 'A' means EAX + EDX.
18894 if (Constraint == "A") {
18895 Res.first = X86::EAX;
18896 Res.second = &X86::GR32_ADRegClass;
18902 // Otherwise, check to see if this is a register class of the wrong value
18903 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
18904 // turn into {ax},{dx}.
18905 if (Res.second->hasType(VT))
18906 return Res; // Correct type already, nothing to do.
18908 // All of the single-register GCC register classes map their values onto
18909 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
18910 // really want an 8-bit or 32-bit register, map to the appropriate register
18911 // class and return the appropriate register.
18912 if (Res.second == &X86::GR16RegClass) {
18913 if (VT == MVT::i8 || VT == MVT::i1) {
18914 unsigned DestReg = 0;
18915 switch (Res.first) {
18917 case X86::AX: DestReg = X86::AL; break;
18918 case X86::DX: DestReg = X86::DL; break;
18919 case X86::CX: DestReg = X86::CL; break;
18920 case X86::BX: DestReg = X86::BL; break;
18923 Res.first = DestReg;
18924 Res.second = &X86::GR8RegClass;
18926 } else if (VT == MVT::i32 || VT == MVT::f32) {
18927 unsigned DestReg = 0;
18928 switch (Res.first) {
18930 case X86::AX: DestReg = X86::EAX; break;
18931 case X86::DX: DestReg = X86::EDX; break;
18932 case X86::CX: DestReg = X86::ECX; break;
18933 case X86::BX: DestReg = X86::EBX; break;
18934 case X86::SI: DestReg = X86::ESI; break;
18935 case X86::DI: DestReg = X86::EDI; break;
18936 case X86::BP: DestReg = X86::EBP; break;
18937 case X86::SP: DestReg = X86::ESP; break;
18940 Res.first = DestReg;
18941 Res.second = &X86::GR32RegClass;
18943 } else if (VT == MVT::i64 || VT == MVT::f64) {
18944 unsigned DestReg = 0;
18945 switch (Res.first) {
18947 case X86::AX: DestReg = X86::RAX; break;
18948 case X86::DX: DestReg = X86::RDX; break;
18949 case X86::CX: DestReg = X86::RCX; break;
18950 case X86::BX: DestReg = X86::RBX; break;
18951 case X86::SI: DestReg = X86::RSI; break;
18952 case X86::DI: DestReg = X86::RDI; break;
18953 case X86::BP: DestReg = X86::RBP; break;
18954 case X86::SP: DestReg = X86::RSP; break;
18957 Res.first = DestReg;
18958 Res.second = &X86::GR64RegClass;
18961 } else if (Res.second == &X86::FR32RegClass ||
18962 Res.second == &X86::FR64RegClass ||
18963 Res.second == &X86::VR128RegClass ||
18964 Res.second == &X86::VR256RegClass ||
18965 Res.second == &X86::FR32XRegClass ||
18966 Res.second == &X86::FR64XRegClass ||
18967 Res.second == &X86::VR128XRegClass ||
18968 Res.second == &X86::VR256XRegClass ||
18969 Res.second == &X86::VR512RegClass) {
18970 // Handle references to XMM physical registers that got mapped into the
18971 // wrong class. This can happen with constraints like {xmm0} where the
18972 // target independent register mapper will just pick the first match it can
18973 // find, ignoring the required type.
18975 if (VT == MVT::f32 || VT == MVT::i32)
18976 Res.second = &X86::FR32RegClass;
18977 else if (VT == MVT::f64 || VT == MVT::i64)
18978 Res.second = &X86::FR64RegClass;
18979 else if (X86::VR128RegClass.hasType(VT))
18980 Res.second = &X86::VR128RegClass;
18981 else if (X86::VR256RegClass.hasType(VT))
18982 Res.second = &X86::VR256RegClass;
18983 else if (X86::VR512RegClass.hasType(VT))
18984 Res.second = &X86::VR512RegClass;