1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86ShuffleDecode.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/MC/MCAsmInfo.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCExpr.h"
41 #include "llvm/MC/MCSymbol.h"
42 #include "llvm/ADT/BitVector.h"
43 #include "llvm/ADT/SmallSet.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/Dwarf.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
54 using namespace dwarf;
56 STATISTIC(NumTailCalls, "Number of tail calls");
58 // Forward declarations.
59 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
62 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
64 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
66 if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
68 return new X8664_MachoTargetObjectFile();
69 return new TargetLoweringObjectFileMachO();
72 if (TM.getSubtarget<X86Subtarget>().isTargetELF() ){
74 return new X8664_ELFTargetObjectFile(TM);
75 return new X8632_ELFTargetObjectFile(TM);
77 if (TM.getSubtarget<X86Subtarget>().isTargetCOFF())
78 return new TargetLoweringObjectFileCOFF();
79 llvm_unreachable("unknown subtarget type");
82 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
83 : TargetLowering(TM, createTLOF(TM)) {
84 Subtarget = &TM.getSubtarget<X86Subtarget>();
85 X86ScalarSSEf64 = Subtarget->hasXMMInt();
86 X86ScalarSSEf32 = Subtarget->hasXMM();
87 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
89 RegInfo = TM.getRegisterInfo();
92 // Set up the TargetLowering object.
93 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
95 // X86 is weird, it always uses i8 for shift amounts and setcc results.
96 setShiftAmountType(MVT::i8);
97 setBooleanContents(ZeroOrOneBooleanContent);
98 setSchedulingPreference(Sched::RegPressure);
99 setStackPointerRegisterToSaveRestore(X86StackPtr);
101 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
102 // Setup Windows compiler runtime calls.
103 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
104 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
105 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
106 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
107 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
108 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
109 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
110 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
113 if (Subtarget->isTargetDarwin()) {
114 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
115 setUseUnderscoreSetJmp(false);
116 setUseUnderscoreLongJmp(false);
117 } else if (Subtarget->isTargetMingw()) {
118 // MS runtime is weird: it exports _setjmp, but longjmp!
119 setUseUnderscoreSetJmp(true);
120 setUseUnderscoreLongJmp(false);
122 setUseUnderscoreSetJmp(true);
123 setUseUnderscoreLongJmp(true);
126 // Set up the register classes.
127 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
128 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
129 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
130 if (Subtarget->is64Bit())
131 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
133 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
135 // We don't accept any truncstore of integer registers.
136 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
137 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
138 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
139 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
140 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
141 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
143 // SETOEQ and SETUNE require checking two conditions.
144 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
145 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
146 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
147 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
148 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
149 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
151 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
153 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
154 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
155 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
157 if (Subtarget->is64Bit()) {
158 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
159 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
160 } else if (!UseSoftFloat) {
161 // We have an algorithm for SSE2->double, and we turn this into a
162 // 64-bit FILD followed by conditional FADD for other targets.
163 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
164 // We have an algorithm for SSE2, and we turn this into a 64-bit
165 // FILD for other targets.
166 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
169 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
171 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
172 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
175 // SSE has no i16 to fp conversion, only i32
176 if (X86ScalarSSEf32) {
177 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
178 // f32 and f64 cases are Legal, f80 case is not
179 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
181 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
182 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
186 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
189 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
190 // are Legal, f80 is custom lowered.
191 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
194 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
196 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
197 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
199 if (X86ScalarSSEf32) {
200 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
201 // f32 and f64 cases are Legal, f80 case is not
202 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
204 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
208 // Handle FP_TO_UINT by promoting the destination to a larger signed
210 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
211 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
212 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
214 if (Subtarget->is64Bit()) {
215 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
216 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
217 } else if (!UseSoftFloat) {
218 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
219 // Expand FP_TO_UINT into a select.
220 // FIXME: We would like to use a Custom expander here eventually to do
221 // the optimal thing for SSE vs. the default expansion in the legalizer.
222 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
224 // With SSE3 we can use fisttpll to convert to a signed i64; without
225 // SSE, we're stuck with a fistpll.
226 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
229 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
230 if (!X86ScalarSSEf64) {
231 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
232 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
233 if (Subtarget->is64Bit()) {
234 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
235 // Without SSE, i64->f64 goes through memory.
236 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
240 // Scalar integer divide and remainder are lowered to use operations that
241 // produce two results, to match the available instructions. This exposes
242 // the two-result form to trivial CSE, which is able to combine x/y and x%y
243 // into a single instruction.
245 // Scalar integer multiply-high is also lowered to use two-result
246 // operations, to match the available instructions. However, plain multiply
247 // (low) operations are left as Legal, as there are single-result
248 // instructions for this in x86. Using the two-result multiply instructions
249 // when both high and low results are needed must be arranged by dagcombine.
250 for (unsigned i = 0, e = 4; i != e; ++i) {
252 setOperationAction(ISD::MULHS, VT, Expand);
253 setOperationAction(ISD::MULHU, VT, Expand);
254 setOperationAction(ISD::SDIV, VT, Expand);
255 setOperationAction(ISD::UDIV, VT, Expand);
256 setOperationAction(ISD::SREM, VT, Expand);
257 setOperationAction(ISD::UREM, VT, Expand);
259 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
260 setOperationAction(ISD::ADDC, VT, Custom);
261 setOperationAction(ISD::ADDE, VT, Custom);
262 setOperationAction(ISD::SUBC, VT, Custom);
263 setOperationAction(ISD::SUBE, VT, Custom);
266 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
267 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
268 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
269 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
270 if (Subtarget->is64Bit())
271 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
272 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
273 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
274 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
275 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
276 setOperationAction(ISD::FREM , MVT::f32 , Expand);
277 setOperationAction(ISD::FREM , MVT::f64 , Expand);
278 setOperationAction(ISD::FREM , MVT::f80 , Expand);
279 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
281 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
282 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
283 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
284 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
285 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
286 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
289 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
292 if (Subtarget->hasPOPCNT()) {
293 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
295 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
296 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
297 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
298 if (Subtarget->is64Bit())
299 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
302 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
303 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
305 // These should be promoted to a larger select which is supported.
306 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
307 // X86 wants to expand cmov itself.
308 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
309 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
310 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
311 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
312 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
313 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
314 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
315 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
316 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
317 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
318 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
319 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
320 if (Subtarget->is64Bit()) {
321 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
322 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
324 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
327 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
328 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
329 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
330 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
331 if (Subtarget->is64Bit())
332 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
333 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
334 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
335 if (Subtarget->is64Bit()) {
336 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
337 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
338 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
339 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
340 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
342 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
343 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
344 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
345 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
346 if (Subtarget->is64Bit()) {
347 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
348 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
349 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
352 if (Subtarget->hasXMM())
353 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
355 // We may not have a libcall for MEMBARRIER so we should lower this.
356 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
358 // On X86 and X86-64, atomic operations are lowered to locked instructions.
359 // Locked instructions, in turn, have implicit fence semantics (all memory
360 // operations are flushed before issuing the locked instruction, and they
361 // are not buffered), so we can fold away the common pattern of
362 // fence-atomic-fence.
363 setShouldFoldAtomicFences(true);
365 // Expand certain atomics
366 for (unsigned i = 0, e = 4; i != e; ++i) {
368 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
372 if (!Subtarget->is64Bit()) {
373 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
374 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
375 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
376 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
377 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
378 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
379 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
382 // FIXME - use subtarget debug flags
383 if (!Subtarget->isTargetDarwin() &&
384 !Subtarget->isTargetELF() &&
385 !Subtarget->isTargetCygMing()) {
386 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
389 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
390 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
391 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
392 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
393 if (Subtarget->is64Bit()) {
394 setExceptionPointerRegister(X86::RAX);
395 setExceptionSelectorRegister(X86::RDX);
397 setExceptionPointerRegister(X86::EAX);
398 setExceptionSelectorRegister(X86::EDX);
400 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
401 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
403 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
405 setOperationAction(ISD::TRAP, MVT::Other, Legal);
407 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
408 setOperationAction(ISD::VASTART , MVT::Other, Custom);
409 setOperationAction(ISD::VAEND , MVT::Other, Expand);
410 if (Subtarget->is64Bit()) {
411 setOperationAction(ISD::VAARG , MVT::Other, Custom);
412 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
414 setOperationAction(ISD::VAARG , MVT::Other, Expand);
415 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
418 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
419 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
420 if (Subtarget->is64Bit())
421 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
422 if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows())
423 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
425 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
427 if (!UseSoftFloat && X86ScalarSSEf64) {
428 // f32 and f64 use SSE.
429 // Set up the FP register classes.
430 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
431 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
433 // Use ANDPD to simulate FABS.
434 setOperationAction(ISD::FABS , MVT::f64, Custom);
435 setOperationAction(ISD::FABS , MVT::f32, Custom);
437 // Use XORP to simulate FNEG.
438 setOperationAction(ISD::FNEG , MVT::f64, Custom);
439 setOperationAction(ISD::FNEG , MVT::f32, Custom);
441 // Use ANDPD and ORPD to simulate FCOPYSIGN.
442 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
443 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
445 // We don't support sin/cos/fmod
446 setOperationAction(ISD::FSIN , MVT::f64, Expand);
447 setOperationAction(ISD::FCOS , MVT::f64, Expand);
448 setOperationAction(ISD::FSIN , MVT::f32, Expand);
449 setOperationAction(ISD::FCOS , MVT::f32, Expand);
451 // Expand FP immediates into loads from the stack, except for the special
453 addLegalFPImmediate(APFloat(+0.0)); // xorpd
454 addLegalFPImmediate(APFloat(+0.0f)); // xorps
455 } else if (!UseSoftFloat && X86ScalarSSEf32) {
456 // Use SSE for f32, x87 for f64.
457 // Set up the FP register classes.
458 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
459 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
461 // Use ANDPS to simulate FABS.
462 setOperationAction(ISD::FABS , MVT::f32, Custom);
464 // Use XORP to simulate FNEG.
465 setOperationAction(ISD::FNEG , MVT::f32, Custom);
467 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
469 // Use ANDPS and ORPS to simulate FCOPYSIGN.
470 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
471 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
473 // We don't support sin/cos/fmod
474 setOperationAction(ISD::FSIN , MVT::f32, Expand);
475 setOperationAction(ISD::FCOS , MVT::f32, Expand);
477 // Special cases we handle for FP constants.
478 addLegalFPImmediate(APFloat(+0.0f)); // xorps
479 addLegalFPImmediate(APFloat(+0.0)); // FLD0
480 addLegalFPImmediate(APFloat(+1.0)); // FLD1
481 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
482 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
485 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
486 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
488 } else if (!UseSoftFloat) {
489 // f32 and f64 in x87.
490 // Set up the FP register classes.
491 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
492 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
494 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
495 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
496 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
497 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
500 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
501 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
503 addLegalFPImmediate(APFloat(+0.0)); // FLD0
504 addLegalFPImmediate(APFloat(+1.0)); // FLD1
505 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
506 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
507 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
508 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
509 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
510 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
513 // Long double always uses X87.
515 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
516 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
517 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
519 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
520 addLegalFPImmediate(TmpFlt); // FLD0
522 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
525 APFloat TmpFlt2(+1.0);
526 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
528 addLegalFPImmediate(TmpFlt2); // FLD1
529 TmpFlt2.changeSign();
530 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
534 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
535 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
539 // Always use a library call for pow.
540 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
541 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
542 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
544 setOperationAction(ISD::FLOG, MVT::f80, Expand);
545 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
546 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
547 setOperationAction(ISD::FEXP, MVT::f80, Expand);
548 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
550 // First set operation action for all vector types to either promote
551 // (for widening) or expand (for scalarization). Then we will selectively
552 // turn on ones that can be effectively codegen'd.
553 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
554 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
555 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
570 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
571 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
579 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
580 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
581 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
582 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
583 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
584 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
585 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
586 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
587 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
588 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
589 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
590 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
591 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
592 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
593 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
594 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
595 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
596 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
597 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
598 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
599 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
600 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
601 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
602 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
603 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
604 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
605 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
606 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
607 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
608 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
609 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
610 setTruncStoreAction((MVT::SimpleValueType)VT,
611 (MVT::SimpleValueType)InnerVT, Expand);
612 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
613 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
614 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
617 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
618 // with -msoft-float, disable use of MMX as well.
619 if (!UseSoftFloat && Subtarget->hasMMX()) {
620 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
621 // No operations on x86mmx supported, everything uses intrinsics.
624 // MMX-sized vectors (other than x86mmx) are expected to be expanded
625 // into smaller operations.
626 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
627 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
628 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
629 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
630 setOperationAction(ISD::AND, MVT::v8i8, Expand);
631 setOperationAction(ISD::AND, MVT::v4i16, Expand);
632 setOperationAction(ISD::AND, MVT::v2i32, Expand);
633 setOperationAction(ISD::AND, MVT::v1i64, Expand);
634 setOperationAction(ISD::OR, MVT::v8i8, Expand);
635 setOperationAction(ISD::OR, MVT::v4i16, Expand);
636 setOperationAction(ISD::OR, MVT::v2i32, Expand);
637 setOperationAction(ISD::OR, MVT::v1i64, Expand);
638 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
639 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
640 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
641 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
642 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
643 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
644 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
645 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
646 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
647 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
648 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
649 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
650 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
651 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
652 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
653 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
654 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
656 if (!UseSoftFloat && Subtarget->hasXMM()) {
657 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
659 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
660 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
661 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
662 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
663 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
664 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
665 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
666 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
667 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
668 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
669 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
670 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
673 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
674 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
676 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
677 // registers cannot be used even for integer operations.
678 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
679 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
680 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
681 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
683 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
684 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
685 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
686 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
687 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
688 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
689 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
690 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
691 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
692 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
693 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
694 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
695 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
696 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
697 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
698 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
700 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
701 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
702 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
703 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
705 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
706 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
707 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
708 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
709 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
711 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
712 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
713 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
714 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
715 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
717 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
718 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
719 EVT VT = (MVT::SimpleValueType)i;
720 // Do not attempt to custom lower non-power-of-2 vectors
721 if (!isPowerOf2_32(VT.getVectorNumElements()))
723 // Do not attempt to custom lower non-128-bit vectors
724 if (!VT.is128BitVector())
726 setOperationAction(ISD::BUILD_VECTOR,
727 VT.getSimpleVT().SimpleTy, Custom);
728 setOperationAction(ISD::VECTOR_SHUFFLE,
729 VT.getSimpleVT().SimpleTy, Custom);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
731 VT.getSimpleVT().SimpleTy, Custom);
734 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
735 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
736 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
737 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
738 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
739 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
741 if (Subtarget->is64Bit()) {
742 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
743 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
746 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
747 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
748 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
751 // Do not attempt to promote non-128-bit vectors
752 if (!VT.is128BitVector())
755 setOperationAction(ISD::AND, SVT, Promote);
756 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
757 setOperationAction(ISD::OR, SVT, Promote);
758 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
759 setOperationAction(ISD::XOR, SVT, Promote);
760 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
761 setOperationAction(ISD::LOAD, SVT, Promote);
762 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
763 setOperationAction(ISD::SELECT, SVT, Promote);
764 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
767 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
769 // Custom lower v2i64 and v2f64 selects.
770 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
771 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
772 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
773 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
775 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
776 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
779 if (Subtarget->hasSSE41()) {
780 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
781 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
782 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
783 setOperationAction(ISD::FRINT, MVT::f32, Legal);
784 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
785 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
786 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
787 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
788 setOperationAction(ISD::FRINT, MVT::f64, Legal);
789 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
791 // FIXME: Do we need to handle scalar-to-vector here?
792 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
794 // Can turn SHL into an integer multiply.
795 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
796 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
798 // i8 and i16 vectors are custom , because the source register and source
799 // source memory operand types are not the same width. f32 vectors are
800 // custom since the immediate controlling the insert encodes additional
802 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
803 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
804 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
805 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
807 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
808 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
809 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
810 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
812 if (Subtarget->is64Bit()) {
813 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
814 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
818 if (Subtarget->hasSSE42())
819 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
821 if (!UseSoftFloat && Subtarget->hasAVX()) {
822 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
823 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
824 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
825 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
826 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
828 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
829 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
830 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
831 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
832 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
833 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
834 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
835 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
836 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
837 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
838 setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
839 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
840 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
841 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
842 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
844 // Operations to consider commented out -v16i16 v32i8
845 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
846 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
847 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
848 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
849 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
850 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
851 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
852 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
853 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
854 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
855 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
856 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
857 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
858 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
860 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
861 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
862 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
863 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
865 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
866 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
867 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
868 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
869 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
871 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
872 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
874 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
876 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
879 // Not sure we want to do this since there are no 256-bit integer
882 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
883 // This includes 256-bit vectors
884 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
885 EVT VT = (MVT::SimpleValueType)i;
887 // Do not attempt to custom lower non-power-of-2 vectors
888 if (!isPowerOf2_32(VT.getVectorNumElements()))
891 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
892 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
893 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
896 if (Subtarget->is64Bit()) {
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
898 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
903 // Not sure we want to do this since there are no 256-bit integer
906 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
907 // Including 256-bit vectors
908 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
909 EVT VT = (MVT::SimpleValueType)i;
911 if (!VT.is256BitVector()) {
914 setOperationAction(ISD::AND, VT, Promote);
915 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
916 setOperationAction(ISD::OR, VT, Promote);
917 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
918 setOperationAction(ISD::XOR, VT, Promote);
919 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
920 setOperationAction(ISD::LOAD, VT, Promote);
921 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
922 setOperationAction(ISD::SELECT, VT, Promote);
923 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
926 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
930 // We want to custom lower some of our intrinsics.
931 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
934 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
935 // handle type legalization for these operations here.
937 // FIXME: We really should do custom legalization for addition and
938 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
939 // than generic legalization for 64-bit multiplication-with-overflow, though.
940 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
941 // Add/Sub/Mul with overflow operations are custom lowered.
943 setOperationAction(ISD::SADDO, VT, Custom);
944 setOperationAction(ISD::UADDO, VT, Custom);
945 setOperationAction(ISD::SSUBO, VT, Custom);
946 setOperationAction(ISD::USUBO, VT, Custom);
947 setOperationAction(ISD::SMULO, VT, Custom);
948 setOperationAction(ISD::UMULO, VT, Custom);
951 // There are no 8-bit 3-address imul/mul instructions
952 setOperationAction(ISD::SMULO, MVT::i8, Expand);
953 setOperationAction(ISD::UMULO, MVT::i8, Expand);
955 if (!Subtarget->is64Bit()) {
956 // These libcalls are not available in 32-bit.
957 setLibcallName(RTLIB::SHL_I128, 0);
958 setLibcallName(RTLIB::SRL_I128, 0);
959 setLibcallName(RTLIB::SRA_I128, 0);
962 // We have target-specific dag combine patterns for the following nodes:
963 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
964 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
965 setTargetDAGCombine(ISD::BUILD_VECTOR);
966 setTargetDAGCombine(ISD::SELECT);
967 setTargetDAGCombine(ISD::SHL);
968 setTargetDAGCombine(ISD::SRA);
969 setTargetDAGCombine(ISD::SRL);
970 setTargetDAGCombine(ISD::OR);
971 setTargetDAGCombine(ISD::AND);
972 setTargetDAGCombine(ISD::ADD);
973 setTargetDAGCombine(ISD::SUB);
974 setTargetDAGCombine(ISD::STORE);
975 setTargetDAGCombine(ISD::ZERO_EXTEND);
976 if (Subtarget->is64Bit())
977 setTargetDAGCombine(ISD::MUL);
979 computeRegisterProperties();
981 // On Darwin, -Os means optimize for size without hurting performance,
982 // do not reduce the limit.
983 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
984 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
985 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
986 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
987 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
988 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
989 setPrefLoopAlignment(16);
990 benefitFromCodePlacementOpt = true;
994 MVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const {
999 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1000 /// the desired ByVal argument alignment.
1001 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
1004 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1005 if (VTy->getBitWidth() == 128)
1007 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1008 unsigned EltAlign = 0;
1009 getMaxByValAlign(ATy->getElementType(), EltAlign);
1010 if (EltAlign > MaxAlign)
1011 MaxAlign = EltAlign;
1012 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
1013 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1014 unsigned EltAlign = 0;
1015 getMaxByValAlign(STy->getElementType(i), EltAlign);
1016 if (EltAlign > MaxAlign)
1017 MaxAlign = EltAlign;
1025 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1026 /// function arguments in the caller parameter area. For X86, aggregates
1027 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1028 /// are at 4-byte boundaries.
1029 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
1030 if (Subtarget->is64Bit()) {
1031 // Max of 8 and alignment of type.
1032 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1039 if (Subtarget->hasXMM())
1040 getMaxByValAlign(Ty, Align);
1044 /// getOptimalMemOpType - Returns the target specific optimal type for load
1045 /// and store operations as a result of memset, memcpy, and memmove
1046 /// lowering. If DstAlign is zero that means it's safe to destination
1047 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1048 /// means there isn't a need to check it against alignment requirement,
1049 /// probably because the source does not need to be loaded. If
1050 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1051 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1052 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1053 /// constant so it does not need to be loaded.
1054 /// It returns EVT::Other if the type should be determined using generic
1055 /// target-independent logic.
1057 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1058 unsigned DstAlign, unsigned SrcAlign,
1059 bool NonScalarIntSafe,
1061 MachineFunction &MF) const {
1062 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1063 // linux. This is because the stack realignment code can't handle certain
1064 // cases like PR2962. This should be removed when PR2962 is fixed.
1065 const Function *F = MF.getFunction();
1066 if (NonScalarIntSafe &&
1067 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1069 (Subtarget->isUnalignedMemAccessFast() ||
1070 ((DstAlign == 0 || DstAlign >= 16) &&
1071 (SrcAlign == 0 || SrcAlign >= 16))) &&
1072 Subtarget->getStackAlignment() >= 16) {
1073 if (Subtarget->hasSSE2())
1075 if (Subtarget->hasSSE1())
1077 } else if (!MemcpyStrSrc && Size >= 8 &&
1078 !Subtarget->is64Bit() &&
1079 Subtarget->getStackAlignment() >= 8 &&
1080 Subtarget->hasXMMInt()) {
1081 // Do not use f64 to lower memcpy if source is string constant. It's
1082 // better to use i32 to avoid the loads.
1086 if (Subtarget->is64Bit() && Size >= 8)
1091 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1092 /// current function. The returned value is a member of the
1093 /// MachineJumpTableInfo::JTEntryKind enum.
1094 unsigned X86TargetLowering::getJumpTableEncoding() const {
1095 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1097 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1098 Subtarget->isPICStyleGOT())
1099 return MachineJumpTableInfo::EK_Custom32;
1101 // Otherwise, use the normal jump table encoding heuristics.
1102 return TargetLowering::getJumpTableEncoding();
1106 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1107 const MachineBasicBlock *MBB,
1108 unsigned uid,MCContext &Ctx) const{
1109 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1110 Subtarget->isPICStyleGOT());
1111 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1113 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1114 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1117 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1119 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1120 SelectionDAG &DAG) const {
1121 if (!Subtarget->is64Bit())
1122 // This doesn't have DebugLoc associated with it, but is not really the
1123 // same as a Register.
1124 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1128 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1129 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1131 const MCExpr *X86TargetLowering::
1132 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1133 MCContext &Ctx) const {
1134 // X86-64 uses RIP relative addressing based on the jump table label.
1135 if (Subtarget->isPICStyleRIPRel())
1136 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1138 // Otherwise, the reference is relative to the PIC base.
1139 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1142 /// getFunctionAlignment - Return the Log2 alignment of this function.
1143 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1144 return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4;
1147 std::pair<const TargetRegisterClass*, uint8_t>
1148 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1149 const TargetRegisterClass *RRC = 0;
1151 switch (VT.getSimpleVT().SimpleTy) {
1153 return TargetLowering::findRepresentativeClass(VT);
1154 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1155 RRC = (Subtarget->is64Bit()
1156 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1159 RRC = X86::VR64RegisterClass;
1161 case MVT::f32: case MVT::f64:
1162 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1163 case MVT::v4f32: case MVT::v2f64:
1164 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1166 RRC = X86::VR128RegisterClass;
1169 return std::make_pair(RRC, Cost);
1173 X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
1174 MachineFunction &MF) const {
1175 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1177 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
1178 switch (RC->getID()) {
1181 case X86::GR32RegClassID:
1183 case X86::GR64RegClassID:
1185 case X86::VR128RegClassID:
1186 return Subtarget->is64Bit() ? 10 : 4;
1187 case X86::VR64RegClassID:
1192 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1193 unsigned &Offset) const {
1194 if (!Subtarget->isTargetLinux())
1197 if (Subtarget->is64Bit()) {
1198 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1200 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1213 //===----------------------------------------------------------------------===//
1214 // Return Value Calling Convention Implementation
1215 //===----------------------------------------------------------------------===//
1217 #include "X86GenCallingConv.inc"
1220 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1221 const SmallVectorImpl<ISD::OutputArg> &Outs,
1222 LLVMContext &Context) const {
1223 SmallVector<CCValAssign, 16> RVLocs;
1224 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1226 return CCInfo.CheckReturn(Outs, RetCC_X86);
1230 X86TargetLowering::LowerReturn(SDValue Chain,
1231 CallingConv::ID CallConv, bool isVarArg,
1232 const SmallVectorImpl<ISD::OutputArg> &Outs,
1233 const SmallVectorImpl<SDValue> &OutVals,
1234 DebugLoc dl, SelectionDAG &DAG) const {
1235 MachineFunction &MF = DAG.getMachineFunction();
1236 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1238 SmallVector<CCValAssign, 16> RVLocs;
1239 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1240 RVLocs, *DAG.getContext());
1241 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1243 // Add the regs to the liveout set for the function.
1244 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1245 for (unsigned i = 0; i != RVLocs.size(); ++i)
1246 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1247 MRI.addLiveOut(RVLocs[i].getLocReg());
1251 SmallVector<SDValue, 6> RetOps;
1252 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1253 // Operand #1 = Bytes To Pop
1254 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1257 // Copy the result values into the output registers.
1258 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1259 CCValAssign &VA = RVLocs[i];
1260 assert(VA.isRegLoc() && "Can only return in registers!");
1261 SDValue ValToCopy = OutVals[i];
1262 EVT ValVT = ValToCopy.getValueType();
1264 // If this is x86-64, and we disabled SSE, we can't return FP values,
1265 // or SSE or MMX vectors.
1266 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1267 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1268 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1269 report_fatal_error("SSE register return with SSE disabled");
1271 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1272 // llvm-gcc has never done it right and no one has noticed, so this
1273 // should be OK for now.
1274 if (ValVT == MVT::f64 &&
1275 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1276 report_fatal_error("SSE2 register return with SSE2 disabled");
1278 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1279 // the RET instruction and handled by the FP Stackifier.
1280 if (VA.getLocReg() == X86::ST0 ||
1281 VA.getLocReg() == X86::ST1) {
1282 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1283 // change the value to the FP stack register class.
1284 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1285 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1286 RetOps.push_back(ValToCopy);
1287 // Don't emit a copytoreg.
1291 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1292 // which is returned in RAX / RDX.
1293 if (Subtarget->is64Bit()) {
1294 if (ValVT == MVT::x86mmx) {
1295 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1296 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1297 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1299 // If we don't have SSE2 available, convert to v4f32 so the generated
1300 // register is legal.
1301 if (!Subtarget->hasSSE2())
1302 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1307 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1308 Flag = Chain.getValue(1);
1311 // The x86-64 ABI for returning structs by value requires that we copy
1312 // the sret argument into %rax for the return. We saved the argument into
1313 // a virtual register in the entry block, so now we copy the value out
1315 if (Subtarget->is64Bit() &&
1316 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1317 MachineFunction &MF = DAG.getMachineFunction();
1318 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1319 unsigned Reg = FuncInfo->getSRetReturnReg();
1321 "SRetReturnReg should have been set in LowerFormalArguments().");
1322 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1324 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1325 Flag = Chain.getValue(1);
1327 // RAX now acts like a return value.
1328 MRI.addLiveOut(X86::RAX);
1331 RetOps[0] = Chain; // Update chain.
1333 // Add the flag if we have it.
1335 RetOps.push_back(Flag);
1337 return DAG.getNode(X86ISD::RET_FLAG, dl,
1338 MVT::Other, &RetOps[0], RetOps.size());
1341 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1342 if (N->getNumValues() != 1)
1344 if (!N->hasNUsesOfValue(1, 0))
1347 SDNode *Copy = *N->use_begin();
1348 if (Copy->getOpcode() != ISD::CopyToReg &&
1349 Copy->getOpcode() != ISD::FP_EXTEND)
1352 bool HasRet = false;
1353 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1355 if (UI->getOpcode() != X86ISD::RET_FLAG)
1363 /// LowerCallResult - Lower the result values of a call into the
1364 /// appropriate copies out of appropriate physical registers.
1367 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1368 CallingConv::ID CallConv, bool isVarArg,
1369 const SmallVectorImpl<ISD::InputArg> &Ins,
1370 DebugLoc dl, SelectionDAG &DAG,
1371 SmallVectorImpl<SDValue> &InVals) const {
1373 // Assign locations to each value returned by this call.
1374 SmallVector<CCValAssign, 16> RVLocs;
1375 bool Is64Bit = Subtarget->is64Bit();
1376 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1377 RVLocs, *DAG.getContext());
1378 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1380 // Copy all of the result registers out of their specified physreg.
1381 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1382 CCValAssign &VA = RVLocs[i];
1383 EVT CopyVT = VA.getValVT();
1385 // If this is x86-64, and we disabled SSE, we can't return FP values
1386 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1387 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1388 report_fatal_error("SSE register return with SSE disabled");
1393 // If this is a call to a function that returns an fp value on the floating
1394 // point stack, we must guarantee the the value is popped from the stack, so
1395 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1396 // if the return value is not used. We use the FpGET_ST0 instructions
1398 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1399 // If we prefer to use the value in xmm registers, copy it out as f80 and
1400 // use a truncate to move it from fp stack reg to xmm reg.
1401 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1402 bool isST0 = VA.getLocReg() == X86::ST0;
1404 if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
1405 if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
1406 if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
1407 SDValue Ops[] = { Chain, InFlag };
1408 Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue,
1410 Val = Chain.getValue(0);
1412 // Round the f80 to the right size, which also moves it to the appropriate
1414 if (CopyVT != VA.getValVT())
1415 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1416 // This truncation won't change the value.
1417 DAG.getIntPtrConstant(1));
1418 } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1419 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1420 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1421 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1422 MVT::v2i64, InFlag).getValue(1);
1423 Val = Chain.getValue(0);
1424 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1425 Val, DAG.getConstant(0, MVT::i64));
1427 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1428 MVT::i64, InFlag).getValue(1);
1429 Val = Chain.getValue(0);
1431 Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val);
1433 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1434 CopyVT, InFlag).getValue(1);
1435 Val = Chain.getValue(0);
1437 InFlag = Chain.getValue(2);
1438 InVals.push_back(Val);
1445 //===----------------------------------------------------------------------===//
1446 // C & StdCall & Fast Calling Convention implementation
1447 //===----------------------------------------------------------------------===//
1448 // StdCall calling convention seems to be standard for many Windows' API
1449 // routines and around. It differs from C calling convention just a little:
1450 // callee should clean up the stack, not caller. Symbols should be also
1451 // decorated in some fancy way :) It doesn't support any vector arguments.
1452 // For info on fast calling convention see Fast Calling Convention (tail call)
1453 // implementation LowerX86_32FastCCCallTo.
1455 /// CallIsStructReturn - Determines whether a call uses struct return
1457 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1461 return Outs[0].Flags.isSRet();
1464 /// ArgsAreStructReturn - Determines whether a function uses struct
1465 /// return semantics.
1467 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1471 return Ins[0].Flags.isSRet();
1474 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1475 /// by "Src" to address "Dst" with size and alignment information specified by
1476 /// the specific parameter attribute. The copy will be passed as a byval
1477 /// function parameter.
1479 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1480 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1482 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1484 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1485 /*isVolatile*/false, /*AlwaysInline=*/true,
1486 MachinePointerInfo(), MachinePointerInfo());
1489 /// IsTailCallConvention - Return true if the calling convention is one that
1490 /// supports tail call optimization.
1491 static bool IsTailCallConvention(CallingConv::ID CC) {
1492 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1495 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1496 /// a tailcall target by changing its ABI.
1497 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1498 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1502 X86TargetLowering::LowerMemArgument(SDValue Chain,
1503 CallingConv::ID CallConv,
1504 const SmallVectorImpl<ISD::InputArg> &Ins,
1505 DebugLoc dl, SelectionDAG &DAG,
1506 const CCValAssign &VA,
1507 MachineFrameInfo *MFI,
1509 // Create the nodes corresponding to a load from this parameter slot.
1510 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1511 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1512 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1515 // If value is passed by pointer we have address passed instead of the value
1517 if (VA.getLocInfo() == CCValAssign::Indirect)
1518 ValVT = VA.getLocVT();
1520 ValVT = VA.getValVT();
1522 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1523 // changed with more analysis.
1524 // In case of tail call optimization mark all arguments mutable. Since they
1525 // could be overwritten by lowering of arguments in case of a tail call.
1526 if (Flags.isByVal()) {
1527 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
1528 VA.getLocMemOffset(), isImmutable);
1529 return DAG.getFrameIndex(FI, getPointerTy());
1531 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1532 VA.getLocMemOffset(), isImmutable);
1533 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1534 return DAG.getLoad(ValVT, dl, Chain, FIN,
1535 MachinePointerInfo::getFixedStack(FI),
1541 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1542 CallingConv::ID CallConv,
1544 const SmallVectorImpl<ISD::InputArg> &Ins,
1547 SmallVectorImpl<SDValue> &InVals)
1549 MachineFunction &MF = DAG.getMachineFunction();
1550 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1552 const Function* Fn = MF.getFunction();
1553 if (Fn->hasExternalLinkage() &&
1554 Subtarget->isTargetCygMing() &&
1555 Fn->getName() == "main")
1556 FuncInfo->setForceFramePointer(true);
1558 MachineFrameInfo *MFI = MF.getFrameInfo();
1559 bool Is64Bit = Subtarget->is64Bit();
1560 bool IsWin64 = Subtarget->isTargetWin64();
1562 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1563 "Var args not supported with calling convention fastcc or ghc");
1565 // Assign locations to all of the incoming arguments.
1566 SmallVector<CCValAssign, 16> ArgLocs;
1567 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1568 ArgLocs, *DAG.getContext());
1569 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1571 unsigned LastVal = ~0U;
1573 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1574 CCValAssign &VA = ArgLocs[i];
1575 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1577 assert(VA.getValNo() != LastVal &&
1578 "Don't support value assigned to multiple locs yet");
1579 LastVal = VA.getValNo();
1581 if (VA.isRegLoc()) {
1582 EVT RegVT = VA.getLocVT();
1583 TargetRegisterClass *RC = NULL;
1584 if (RegVT == MVT::i32)
1585 RC = X86::GR32RegisterClass;
1586 else if (Is64Bit && RegVT == MVT::i64)
1587 RC = X86::GR64RegisterClass;
1588 else if (RegVT == MVT::f32)
1589 RC = X86::FR32RegisterClass;
1590 else if (RegVT == MVT::f64)
1591 RC = X86::FR64RegisterClass;
1592 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1593 RC = X86::VR256RegisterClass;
1594 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1595 RC = X86::VR128RegisterClass;
1596 else if (RegVT == MVT::x86mmx)
1597 RC = X86::VR64RegisterClass;
1599 llvm_unreachable("Unknown argument type!");
1601 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1602 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1604 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1605 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1607 if (VA.getLocInfo() == CCValAssign::SExt)
1608 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1609 DAG.getValueType(VA.getValVT()));
1610 else if (VA.getLocInfo() == CCValAssign::ZExt)
1611 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1612 DAG.getValueType(VA.getValVT()));
1613 else if (VA.getLocInfo() == CCValAssign::BCvt)
1614 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1616 if (VA.isExtInLoc()) {
1617 // Handle MMX values passed in XMM regs.
1618 if (RegVT.isVector()) {
1619 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1622 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1625 assert(VA.isMemLoc());
1626 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1629 // If value is passed via pointer - do a load.
1630 if (VA.getLocInfo() == CCValAssign::Indirect)
1631 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1632 MachinePointerInfo(), false, false, 0);
1634 InVals.push_back(ArgValue);
1637 // The x86-64 ABI for returning structs by value requires that we copy
1638 // the sret argument into %rax for the return. Save the argument into
1639 // a virtual register so that we can access it from the return points.
1640 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1641 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1642 unsigned Reg = FuncInfo->getSRetReturnReg();
1644 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1645 FuncInfo->setSRetReturnReg(Reg);
1647 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1648 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1651 unsigned StackSize = CCInfo.getNextStackOffset();
1652 // Align stack specially for tail calls.
1653 if (FuncIsMadeTailCallSafe(CallConv))
1654 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1656 // If the function takes variable number of arguments, make a frame index for
1657 // the start of the first vararg value... for expansion of llvm.va_start.
1659 if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1660 CallConv != CallingConv::X86_ThisCall))) {
1661 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1664 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1666 // FIXME: We should really autogenerate these arrays
1667 static const unsigned GPR64ArgRegsWin64[] = {
1668 X86::RCX, X86::RDX, X86::R8, X86::R9
1670 static const unsigned GPR64ArgRegs64Bit[] = {
1671 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1673 static const unsigned XMMArgRegs64Bit[] = {
1674 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1675 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1677 const unsigned *GPR64ArgRegs;
1678 unsigned NumXMMRegs = 0;
1681 // The XMM registers which might contain var arg parameters are shadowed
1682 // in their paired GPR. So we only need to save the GPR to their home
1684 TotalNumIntRegs = 4;
1685 GPR64ArgRegs = GPR64ArgRegsWin64;
1687 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1688 GPR64ArgRegs = GPR64ArgRegs64Bit;
1690 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1692 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1695 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1696 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1697 "SSE register cannot be used when SSE is disabled!");
1698 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1699 "SSE register cannot be used when SSE is disabled!");
1700 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1701 // Kernel mode asks for SSE to be disabled, so don't push them
1703 TotalNumXMMRegs = 0;
1706 const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo();
1707 // Get to the caller-allocated home save location. Add 8 to account
1708 // for the return address.
1709 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1710 FuncInfo->setRegSaveFrameIndex(
1711 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1712 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1714 // For X86-64, if there are vararg parameters that are passed via
1715 // registers, then we must store them to their spots on the stack so they
1716 // may be loaded by deferencing the result of va_next.
1717 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1718 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1719 FuncInfo->setRegSaveFrameIndex(
1720 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1724 // Store the integer parameter registers.
1725 SmallVector<SDValue, 8> MemOps;
1726 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1728 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1729 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1730 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1731 DAG.getIntPtrConstant(Offset));
1732 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1733 X86::GR64RegisterClass);
1734 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1736 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1737 MachinePointerInfo::getFixedStack(
1738 FuncInfo->getRegSaveFrameIndex(), Offset),
1740 MemOps.push_back(Store);
1744 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1745 // Now store the XMM (fp + vector) parameter registers.
1746 SmallVector<SDValue, 11> SaveXMMOps;
1747 SaveXMMOps.push_back(Chain);
1749 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1750 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1751 SaveXMMOps.push_back(ALVal);
1753 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1754 FuncInfo->getRegSaveFrameIndex()));
1755 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1756 FuncInfo->getVarArgsFPOffset()));
1758 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1759 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1760 X86::VR128RegisterClass);
1761 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1762 SaveXMMOps.push_back(Val);
1764 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1766 &SaveXMMOps[0], SaveXMMOps.size()));
1769 if (!MemOps.empty())
1770 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1771 &MemOps[0], MemOps.size());
1775 // Some CCs need callee pop.
1776 if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
1777 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1779 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1780 // If this is an sret function, the return should pop the hidden pointer.
1781 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1782 FuncInfo->setBytesToPopOnReturn(4);
1786 // RegSaveFrameIndex is X86-64 only.
1787 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1788 if (CallConv == CallingConv::X86_FastCall ||
1789 CallConv == CallingConv::X86_ThisCall)
1790 // fastcc functions can't have varargs.
1791 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1798 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1799 SDValue StackPtr, SDValue Arg,
1800 DebugLoc dl, SelectionDAG &DAG,
1801 const CCValAssign &VA,
1802 ISD::ArgFlagsTy Flags) const {
1803 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1804 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1805 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1806 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1807 if (Flags.isByVal())
1808 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1810 return DAG.getStore(Chain, dl, Arg, PtrOff,
1811 MachinePointerInfo::getStack(LocMemOffset),
1815 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1816 /// optimization is performed and it is required.
1818 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1819 SDValue &OutRetAddr, SDValue Chain,
1820 bool IsTailCall, bool Is64Bit,
1821 int FPDiff, DebugLoc dl) const {
1822 // Adjust the Return address stack slot.
1823 EVT VT = getPointerTy();
1824 OutRetAddr = getReturnAddressFrameIndex(DAG);
1826 // Load the "old" Return address.
1827 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1829 return SDValue(OutRetAddr.getNode(), 1);
1832 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1833 /// optimization is performed and it is required (FPDiff!=0).
1835 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1836 SDValue Chain, SDValue RetAddrFrIdx,
1837 bool Is64Bit, int FPDiff, DebugLoc dl) {
1838 // Store the return address to the appropriate stack slot.
1839 if (!FPDiff) return Chain;
1840 // Calculate the new stack slot for the return address.
1841 int SlotSize = Is64Bit ? 8 : 4;
1842 int NewReturnAddrFI =
1843 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
1844 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1845 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1846 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1847 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
1853 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1854 CallingConv::ID CallConv, bool isVarArg,
1856 const SmallVectorImpl<ISD::OutputArg> &Outs,
1857 const SmallVectorImpl<SDValue> &OutVals,
1858 const SmallVectorImpl<ISD::InputArg> &Ins,
1859 DebugLoc dl, SelectionDAG &DAG,
1860 SmallVectorImpl<SDValue> &InVals) const {
1861 MachineFunction &MF = DAG.getMachineFunction();
1862 bool Is64Bit = Subtarget->is64Bit();
1863 bool IsStructRet = CallIsStructReturn(Outs);
1864 bool IsSibcall = false;
1867 // Check if it's really possible to do a tail call.
1868 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1869 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1870 Outs, OutVals, Ins, DAG);
1872 // Sibcalls are automatically detected tailcalls which do not require
1874 if (!GuaranteedTailCallOpt && isTailCall)
1881 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1882 "Var args not supported with calling convention fastcc or ghc");
1884 // Analyze operands of the call, assigning locations to each operand.
1885 SmallVector<CCValAssign, 16> ArgLocs;
1886 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1887 ArgLocs, *DAG.getContext());
1888 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
1890 // Get a count of how many bytes are to be pushed on the stack.
1891 unsigned NumBytes = CCInfo.getNextStackOffset();
1893 // This is a sibcall. The memory operands are available in caller's
1894 // own caller's stack.
1896 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
1897 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1900 if (isTailCall && !IsSibcall) {
1901 // Lower arguments at fp - stackoffset + fpdiff.
1902 unsigned NumBytesCallerPushed =
1903 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1904 FPDiff = NumBytesCallerPushed - NumBytes;
1906 // Set the delta of movement of the returnaddr stackslot.
1907 // But only set if delta is greater than previous delta.
1908 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1909 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1913 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1915 SDValue RetAddrFrIdx;
1916 // Load return adress for tail calls.
1917 if (isTailCall && FPDiff)
1918 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
1919 Is64Bit, FPDiff, dl);
1921 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1922 SmallVector<SDValue, 8> MemOpChains;
1925 // Walk the register/memloc assignments, inserting copies/loads. In the case
1926 // of tail call optimization arguments are handle later.
1927 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1928 CCValAssign &VA = ArgLocs[i];
1929 EVT RegVT = VA.getLocVT();
1930 SDValue Arg = OutVals[i];
1931 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1932 bool isByVal = Flags.isByVal();
1934 // Promote the value if needed.
1935 switch (VA.getLocInfo()) {
1936 default: llvm_unreachable("Unknown loc info!");
1937 case CCValAssign::Full: break;
1938 case CCValAssign::SExt:
1939 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1941 case CCValAssign::ZExt:
1942 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1944 case CCValAssign::AExt:
1945 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1946 // Special case: passing MMX values in XMM registers.
1947 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
1948 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1949 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1951 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1953 case CCValAssign::BCvt:
1954 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
1956 case CCValAssign::Indirect: {
1957 // Store the argument.
1958 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1959 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1960 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1961 MachinePointerInfo::getFixedStack(FI),
1968 if (VA.isRegLoc()) {
1969 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1970 if (isVarArg && Subtarget->isTargetWin64()) {
1971 // Win64 ABI requires argument XMM reg to be copied to the corresponding
1972 // shadow reg if callee is a varargs function.
1973 unsigned ShadowReg = 0;
1974 switch (VA.getLocReg()) {
1975 case X86::XMM0: ShadowReg = X86::RCX; break;
1976 case X86::XMM1: ShadowReg = X86::RDX; break;
1977 case X86::XMM2: ShadowReg = X86::R8; break;
1978 case X86::XMM3: ShadowReg = X86::R9; break;
1981 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
1983 } else if (!IsSibcall && (!isTailCall || isByVal)) {
1984 assert(VA.isMemLoc());
1985 if (StackPtr.getNode() == 0)
1986 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1987 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1988 dl, DAG, VA, Flags));
1992 if (!MemOpChains.empty())
1993 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1994 &MemOpChains[0], MemOpChains.size());
1996 // Build a sequence of copy-to-reg nodes chained together with token chain
1997 // and flag operands which copy the outgoing args into registers.
1999 // Tail call byval lowering might overwrite argument registers so in case of
2000 // tail call optimization the copies to registers are lowered later.
2002 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2003 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2004 RegsToPass[i].second, InFlag);
2005 InFlag = Chain.getValue(1);
2008 if (Subtarget->isPICStyleGOT()) {
2009 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2012 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2013 DAG.getNode(X86ISD::GlobalBaseReg,
2014 DebugLoc(), getPointerTy()),
2016 InFlag = Chain.getValue(1);
2018 // If we are tail calling and generating PIC/GOT style code load the
2019 // address of the callee into ECX. The value in ecx is used as target of
2020 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2021 // for tail calls on PIC/GOT architectures. Normally we would just put the
2022 // address of GOT into ebx and then call target@PLT. But for tail calls
2023 // ebx would be restored (since ebx is callee saved) before jumping to the
2026 // Note: The actual moving to ECX is done further down.
2027 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2028 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2029 !G->getGlobal()->hasProtectedVisibility())
2030 Callee = LowerGlobalAddress(Callee, DAG);
2031 else if (isa<ExternalSymbolSDNode>(Callee))
2032 Callee = LowerExternalSymbol(Callee, DAG);
2036 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) {
2037 // From AMD64 ABI document:
2038 // For calls that may call functions that use varargs or stdargs
2039 // (prototype-less calls or calls to functions containing ellipsis (...) in
2040 // the declaration) %al is used as hidden argument to specify the number
2041 // of SSE registers used. The contents of %al do not need to match exactly
2042 // the number of registers, but must be an ubound on the number of SSE
2043 // registers used and is in the range 0 - 8 inclusive.
2045 // Count the number of XMM registers allocated.
2046 static const unsigned XMMArgRegs[] = {
2047 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2048 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2050 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2051 assert((Subtarget->hasXMM() || !NumXMMRegs)
2052 && "SSE registers cannot be used when SSE is disabled");
2054 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2055 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2056 InFlag = Chain.getValue(1);
2060 // For tail calls lower the arguments to the 'real' stack slot.
2062 // Force all the incoming stack arguments to be loaded from the stack
2063 // before any new outgoing arguments are stored to the stack, because the
2064 // outgoing stack slots may alias the incoming argument stack slots, and
2065 // the alias isn't otherwise explicit. This is slightly more conservative
2066 // than necessary, because it means that each store effectively depends
2067 // on every argument instead of just those arguments it would clobber.
2068 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2070 SmallVector<SDValue, 8> MemOpChains2;
2073 // Do not flag preceeding copytoreg stuff together with the following stuff.
2075 if (GuaranteedTailCallOpt) {
2076 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2077 CCValAssign &VA = ArgLocs[i];
2080 assert(VA.isMemLoc());
2081 SDValue Arg = OutVals[i];
2082 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2083 // Create frame index.
2084 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2085 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2086 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2087 FIN = DAG.getFrameIndex(FI, getPointerTy());
2089 if (Flags.isByVal()) {
2090 // Copy relative to framepointer.
2091 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2092 if (StackPtr.getNode() == 0)
2093 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2095 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2097 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2101 // Store relative to framepointer.
2102 MemOpChains2.push_back(
2103 DAG.getStore(ArgChain, dl, Arg, FIN,
2104 MachinePointerInfo::getFixedStack(FI),
2110 if (!MemOpChains2.empty())
2111 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2112 &MemOpChains2[0], MemOpChains2.size());
2114 // Copy arguments to their registers.
2115 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2116 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2117 RegsToPass[i].second, InFlag);
2118 InFlag = Chain.getValue(1);
2122 // Store the return address to the appropriate stack slot.
2123 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2127 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2128 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2129 // In the 64-bit large code model, we have to make all calls
2130 // through a register, since the call instruction's 32-bit
2131 // pc-relative offset may not be large enough to hold the whole
2133 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2134 // If the callee is a GlobalAddress node (quite common, every direct call
2135 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2138 // We should use extra load for direct calls to dllimported functions in
2140 const GlobalValue *GV = G->getGlobal();
2141 if (!GV->hasDLLImportLinkage()) {
2142 unsigned char OpFlags = 0;
2144 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2145 // external symbols most go through the PLT in PIC mode. If the symbol
2146 // has hidden or protected visibility, or if it is static or local, then
2147 // we don't need to use the PLT - we can directly call it.
2148 if (Subtarget->isTargetELF() &&
2149 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2150 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2151 OpFlags = X86II::MO_PLT;
2152 } else if (Subtarget->isPICStyleStubAny() &&
2153 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2154 Subtarget->getDarwinVers() < 9) {
2155 // PC-relative references to external symbols should go through $stub,
2156 // unless we're building with the leopard linker or later, which
2157 // automatically synthesizes these stubs.
2158 OpFlags = X86II::MO_DARWIN_STUB;
2161 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2162 G->getOffset(), OpFlags);
2164 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2165 unsigned char OpFlags = 0;
2167 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2168 // external symbols should go through the PLT.
2169 if (Subtarget->isTargetELF() &&
2170 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2171 OpFlags = X86II::MO_PLT;
2172 } else if (Subtarget->isPICStyleStubAny() &&
2173 Subtarget->getDarwinVers() < 9) {
2174 // PC-relative references to external symbols should go through $stub,
2175 // unless we're building with the leopard linker or later, which
2176 // automatically synthesizes these stubs.
2177 OpFlags = X86II::MO_DARWIN_STUB;
2180 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2184 // Returns a chain & a flag for retval copy to use.
2185 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2186 SmallVector<SDValue, 8> Ops;
2188 if (!IsSibcall && isTailCall) {
2189 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2190 DAG.getIntPtrConstant(0, true), InFlag);
2191 InFlag = Chain.getValue(1);
2194 Ops.push_back(Chain);
2195 Ops.push_back(Callee);
2198 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2200 // Add argument registers to the end of the list so that they are known live
2202 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2203 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2204 RegsToPass[i].second.getValueType()));
2206 // Add an implicit use GOT pointer in EBX.
2207 if (!isTailCall && Subtarget->isPICStyleGOT())
2208 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2210 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2211 if (Is64Bit && isVarArg && !Subtarget->isTargetWin64())
2212 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2214 if (InFlag.getNode())
2215 Ops.push_back(InFlag);
2219 //// If this is the first return lowered for this function, add the regs
2220 //// to the liveout set for the function.
2221 // This isn't right, although it's probably harmless on x86; liveouts
2222 // should be computed from returns not tail calls. Consider a void
2223 // function making a tail call to a function returning int.
2224 return DAG.getNode(X86ISD::TC_RETURN, dl,
2225 NodeTys, &Ops[0], Ops.size());
2228 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2229 InFlag = Chain.getValue(1);
2231 // Create the CALLSEQ_END node.
2232 unsigned NumBytesForCalleeToPush;
2233 if (Subtarget->IsCalleePop(isVarArg, CallConv))
2234 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2235 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2236 // If this is a call to a struct-return function, the callee
2237 // pops the hidden struct pointer, so we have to push it back.
2238 // This is common for Darwin/X86, Linux & Mingw32 targets.
2239 NumBytesForCalleeToPush = 4;
2241 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2243 // Returns a flag for retval copy to use.
2245 Chain = DAG.getCALLSEQ_END(Chain,
2246 DAG.getIntPtrConstant(NumBytes, true),
2247 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2250 InFlag = Chain.getValue(1);
2253 // Handle result values, copying them out of physregs into vregs that we
2255 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2256 Ins, dl, DAG, InVals);
2260 //===----------------------------------------------------------------------===//
2261 // Fast Calling Convention (tail call) implementation
2262 //===----------------------------------------------------------------------===//
2264 // Like std call, callee cleans arguments, convention except that ECX is
2265 // reserved for storing the tail called function address. Only 2 registers are
2266 // free for argument passing (inreg). Tail call optimization is performed
2268 // * tailcallopt is enabled
2269 // * caller/callee are fastcc
2270 // On X86_64 architecture with GOT-style position independent code only local
2271 // (within module) calls are supported at the moment.
2272 // To keep the stack aligned according to platform abi the function
2273 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2274 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2275 // If a tail called function callee has more arguments than the caller the
2276 // caller needs to make sure that there is room to move the RETADDR to. This is
2277 // achieved by reserving an area the size of the argument delta right after the
2278 // original REtADDR, but before the saved framepointer or the spilled registers
2279 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2291 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2292 /// for a 16 byte align requirement.
2294 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2295 SelectionDAG& DAG) const {
2296 MachineFunction &MF = DAG.getMachineFunction();
2297 const TargetMachine &TM = MF.getTarget();
2298 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2299 unsigned StackAlignment = TFI.getStackAlignment();
2300 uint64_t AlignMask = StackAlignment - 1;
2301 int64_t Offset = StackSize;
2302 uint64_t SlotSize = TD->getPointerSize();
2303 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2304 // Number smaller than 12 so just add the difference.
2305 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2307 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2308 Offset = ((~AlignMask) & Offset) + StackAlignment +
2309 (StackAlignment-SlotSize);
2314 /// MatchingStackOffset - Return true if the given stack call argument is
2315 /// already available in the same position (relatively) of the caller's
2316 /// incoming argument stack.
2318 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2319 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2320 const X86InstrInfo *TII) {
2321 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2323 if (Arg.getOpcode() == ISD::CopyFromReg) {
2324 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2325 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
2327 MachineInstr *Def = MRI->getVRegDef(VR);
2330 if (!Flags.isByVal()) {
2331 if (!TII->isLoadFromStackSlot(Def, FI))
2334 unsigned Opcode = Def->getOpcode();
2335 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2336 Def->getOperand(1).isFI()) {
2337 FI = Def->getOperand(1).getIndex();
2338 Bytes = Flags.getByValSize();
2342 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2343 if (Flags.isByVal())
2344 // ByVal argument is passed in as a pointer but it's now being
2345 // dereferenced. e.g.
2346 // define @foo(%struct.X* %A) {
2347 // tail call @bar(%struct.X* byval %A)
2350 SDValue Ptr = Ld->getBasePtr();
2351 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2354 FI = FINode->getIndex();
2358 assert(FI != INT_MAX);
2359 if (!MFI->isFixedObjectIndex(FI))
2361 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2364 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2365 /// for tail call optimization. Targets which want to do tail call
2366 /// optimization should implement this function.
2368 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2369 CallingConv::ID CalleeCC,
2371 bool isCalleeStructRet,
2372 bool isCallerStructRet,
2373 const SmallVectorImpl<ISD::OutputArg> &Outs,
2374 const SmallVectorImpl<SDValue> &OutVals,
2375 const SmallVectorImpl<ISD::InputArg> &Ins,
2376 SelectionDAG& DAG) const {
2377 if (!IsTailCallConvention(CalleeCC) &&
2378 CalleeCC != CallingConv::C)
2381 // If -tailcallopt is specified, make fastcc functions tail-callable.
2382 const MachineFunction &MF = DAG.getMachineFunction();
2383 const Function *CallerF = DAG.getMachineFunction().getFunction();
2384 CallingConv::ID CallerCC = CallerF->getCallingConv();
2385 bool CCMatch = CallerCC == CalleeCC;
2387 if (GuaranteedTailCallOpt) {
2388 if (IsTailCallConvention(CalleeCC) && CCMatch)
2393 // Look for obvious safe cases to perform tail call optimization that do not
2394 // require ABI changes. This is what gcc calls sibcall.
2396 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2397 // emit a special epilogue.
2398 if (RegInfo->needsStackRealignment(MF))
2401 // Do not sibcall optimize vararg calls unless the call site is not passing
2403 if (isVarArg && !Outs.empty())
2406 // Also avoid sibcall optimization if either caller or callee uses struct
2407 // return semantics.
2408 if (isCalleeStructRet || isCallerStructRet)
2411 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2412 // Therefore if it's not used by the call it is not safe to optimize this into
2414 bool Unused = false;
2415 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2422 SmallVector<CCValAssign, 16> RVLocs;
2423 CCState CCInfo(CalleeCC, false, getTargetMachine(),
2424 RVLocs, *DAG.getContext());
2425 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2426 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2427 CCValAssign &VA = RVLocs[i];
2428 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2433 // If the calling conventions do not match, then we'd better make sure the
2434 // results are returned in the same way as what the caller expects.
2436 SmallVector<CCValAssign, 16> RVLocs1;
2437 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
2438 RVLocs1, *DAG.getContext());
2439 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2441 SmallVector<CCValAssign, 16> RVLocs2;
2442 CCState CCInfo2(CallerCC, false, getTargetMachine(),
2443 RVLocs2, *DAG.getContext());
2444 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2446 if (RVLocs1.size() != RVLocs2.size())
2448 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2449 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2451 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2453 if (RVLocs1[i].isRegLoc()) {
2454 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2457 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2463 // If the callee takes no arguments then go on to check the results of the
2465 if (!Outs.empty()) {
2466 // Check if stack adjustment is needed. For now, do not do this if any
2467 // argument is passed on the stack.
2468 SmallVector<CCValAssign, 16> ArgLocs;
2469 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
2470 ArgLocs, *DAG.getContext());
2471 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2472 if (CCInfo.getNextStackOffset()) {
2473 MachineFunction &MF = DAG.getMachineFunction();
2474 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2476 if (Subtarget->isTargetWin64())
2477 // Win64 ABI has additional complications.
2480 // Check if the arguments are already laid out in the right way as
2481 // the caller's fixed stack objects.
2482 MachineFrameInfo *MFI = MF.getFrameInfo();
2483 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2484 const X86InstrInfo *TII =
2485 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2486 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2487 CCValAssign &VA = ArgLocs[i];
2488 SDValue Arg = OutVals[i];
2489 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2490 if (VA.getLocInfo() == CCValAssign::Indirect)
2492 if (!VA.isRegLoc()) {
2493 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2500 // If the tailcall address may be in a register, then make sure it's
2501 // possible to register allocate for it. In 32-bit, the call address can
2502 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2503 // callee-saved registers are restored. These happen to be the same
2504 // registers used to pass 'inreg' arguments so watch out for those.
2505 if (!Subtarget->is64Bit() &&
2506 !isa<GlobalAddressSDNode>(Callee) &&
2507 !isa<ExternalSymbolSDNode>(Callee)) {
2508 unsigned NumInRegs = 0;
2509 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2510 CCValAssign &VA = ArgLocs[i];
2513 unsigned Reg = VA.getLocReg();
2516 case X86::EAX: case X86::EDX: case X86::ECX:
2517 if (++NumInRegs == 3)
2525 // An stdcall caller is expected to clean up its arguments; the callee
2526 // isn't going to do that.
2527 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2534 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2535 return X86::createFastISel(funcInfo);
2539 //===----------------------------------------------------------------------===//
2540 // Other Lowering Hooks
2541 //===----------------------------------------------------------------------===//
2543 static bool MayFoldLoad(SDValue Op) {
2544 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2547 static bool MayFoldIntoStore(SDValue Op) {
2548 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2551 static bool isTargetShuffle(unsigned Opcode) {
2553 default: return false;
2554 case X86ISD::PSHUFD:
2555 case X86ISD::PSHUFHW:
2556 case X86ISD::PSHUFLW:
2557 case X86ISD::SHUFPD:
2558 case X86ISD::PALIGN:
2559 case X86ISD::SHUFPS:
2560 case X86ISD::MOVLHPS:
2561 case X86ISD::MOVLHPD:
2562 case X86ISD::MOVHLPS:
2563 case X86ISD::MOVLPS:
2564 case X86ISD::MOVLPD:
2565 case X86ISD::MOVSHDUP:
2566 case X86ISD::MOVSLDUP:
2567 case X86ISD::MOVDDUP:
2570 case X86ISD::UNPCKLPS:
2571 case X86ISD::UNPCKLPD:
2572 case X86ISD::PUNPCKLWD:
2573 case X86ISD::PUNPCKLBW:
2574 case X86ISD::PUNPCKLDQ:
2575 case X86ISD::PUNPCKLQDQ:
2576 case X86ISD::UNPCKHPS:
2577 case X86ISD::UNPCKHPD:
2578 case X86ISD::PUNPCKHWD:
2579 case X86ISD::PUNPCKHBW:
2580 case X86ISD::PUNPCKHDQ:
2581 case X86ISD::PUNPCKHQDQ:
2587 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2588 SDValue V1, SelectionDAG &DAG) {
2590 default: llvm_unreachable("Unknown x86 shuffle node");
2591 case X86ISD::MOVSHDUP:
2592 case X86ISD::MOVSLDUP:
2593 case X86ISD::MOVDDUP:
2594 return DAG.getNode(Opc, dl, VT, V1);
2600 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2601 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2603 default: llvm_unreachable("Unknown x86 shuffle node");
2604 case X86ISD::PSHUFD:
2605 case X86ISD::PSHUFHW:
2606 case X86ISD::PSHUFLW:
2607 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2613 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2614 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2616 default: llvm_unreachable("Unknown x86 shuffle node");
2617 case X86ISD::PALIGN:
2618 case X86ISD::SHUFPD:
2619 case X86ISD::SHUFPS:
2620 return DAG.getNode(Opc, dl, VT, V1, V2,
2621 DAG.getConstant(TargetMask, MVT::i8));
2626 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2627 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2629 default: llvm_unreachable("Unknown x86 shuffle node");
2630 case X86ISD::MOVLHPS:
2631 case X86ISD::MOVLHPD:
2632 case X86ISD::MOVHLPS:
2633 case X86ISD::MOVLPS:
2634 case X86ISD::MOVLPD:
2637 case X86ISD::UNPCKLPS:
2638 case X86ISD::UNPCKLPD:
2639 case X86ISD::PUNPCKLWD:
2640 case X86ISD::PUNPCKLBW:
2641 case X86ISD::PUNPCKLDQ:
2642 case X86ISD::PUNPCKLQDQ:
2643 case X86ISD::UNPCKHPS:
2644 case X86ISD::UNPCKHPD:
2645 case X86ISD::PUNPCKHWD:
2646 case X86ISD::PUNPCKHBW:
2647 case X86ISD::PUNPCKHDQ:
2648 case X86ISD::PUNPCKHQDQ:
2649 return DAG.getNode(Opc, dl, VT, V1, V2);
2654 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2655 MachineFunction &MF = DAG.getMachineFunction();
2656 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2657 int ReturnAddrIndex = FuncInfo->getRAIndex();
2659 if (ReturnAddrIndex == 0) {
2660 // Set up a frame object for the return address.
2661 uint64_t SlotSize = TD->getPointerSize();
2662 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2664 FuncInfo->setRAIndex(ReturnAddrIndex);
2667 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2671 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2672 bool hasSymbolicDisplacement) {
2673 // Offset should fit into 32 bit immediate field.
2674 if (!isInt<32>(Offset))
2677 // If we don't have a symbolic displacement - we don't have any extra
2679 if (!hasSymbolicDisplacement)
2682 // FIXME: Some tweaks might be needed for medium code model.
2683 if (M != CodeModel::Small && M != CodeModel::Kernel)
2686 // For small code model we assume that latest object is 16MB before end of 31
2687 // bits boundary. We may also accept pretty large negative constants knowing
2688 // that all objects are in the positive half of address space.
2689 if (M == CodeModel::Small && Offset < 16*1024*1024)
2692 // For kernel code model we know that all object resist in the negative half
2693 // of 32bits address space. We may not accept negative offsets, since they may
2694 // be just off and we may accept pretty large positive ones.
2695 if (M == CodeModel::Kernel && Offset > 0)
2701 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2702 /// specific condition code, returning the condition code and the LHS/RHS of the
2703 /// comparison to make.
2704 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2705 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2707 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2708 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2709 // X > -1 -> X == 0, jump !sign.
2710 RHS = DAG.getConstant(0, RHS.getValueType());
2711 return X86::COND_NS;
2712 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2713 // X < 0 -> X == 0, jump on sign.
2715 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2717 RHS = DAG.getConstant(0, RHS.getValueType());
2718 return X86::COND_LE;
2722 switch (SetCCOpcode) {
2723 default: llvm_unreachable("Invalid integer condition!");
2724 case ISD::SETEQ: return X86::COND_E;
2725 case ISD::SETGT: return X86::COND_G;
2726 case ISD::SETGE: return X86::COND_GE;
2727 case ISD::SETLT: return X86::COND_L;
2728 case ISD::SETLE: return X86::COND_LE;
2729 case ISD::SETNE: return X86::COND_NE;
2730 case ISD::SETULT: return X86::COND_B;
2731 case ISD::SETUGT: return X86::COND_A;
2732 case ISD::SETULE: return X86::COND_BE;
2733 case ISD::SETUGE: return X86::COND_AE;
2737 // First determine if it is required or is profitable to flip the operands.
2739 // If LHS is a foldable load, but RHS is not, flip the condition.
2740 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2741 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2742 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2743 std::swap(LHS, RHS);
2746 switch (SetCCOpcode) {
2752 std::swap(LHS, RHS);
2756 // On a floating point condition, the flags are set as follows:
2758 // 0 | 0 | 0 | X > Y
2759 // 0 | 0 | 1 | X < Y
2760 // 1 | 0 | 0 | X == Y
2761 // 1 | 1 | 1 | unordered
2762 switch (SetCCOpcode) {
2763 default: llvm_unreachable("Condcode should be pre-legalized away");
2765 case ISD::SETEQ: return X86::COND_E;
2766 case ISD::SETOLT: // flipped
2768 case ISD::SETGT: return X86::COND_A;
2769 case ISD::SETOLE: // flipped
2771 case ISD::SETGE: return X86::COND_AE;
2772 case ISD::SETUGT: // flipped
2774 case ISD::SETLT: return X86::COND_B;
2775 case ISD::SETUGE: // flipped
2777 case ISD::SETLE: return X86::COND_BE;
2779 case ISD::SETNE: return X86::COND_NE;
2780 case ISD::SETUO: return X86::COND_P;
2781 case ISD::SETO: return X86::COND_NP;
2783 case ISD::SETUNE: return X86::COND_INVALID;
2787 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2788 /// code. Current x86 isa includes the following FP cmov instructions:
2789 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2790 static bool hasFPCMov(unsigned X86CC) {
2806 /// isFPImmLegal - Returns true if the target can instruction select the
2807 /// specified FP immediate natively. If false, the legalizer will
2808 /// materialize the FP immediate as a load from a constant pool.
2809 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2810 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
2811 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
2817 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2818 /// the specified range (L, H].
2819 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2820 return (Val < 0) || (Val >= Low && Val < Hi);
2823 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2824 /// specified value.
2825 static bool isUndefOrEqual(int Val, int CmpVal) {
2826 if (Val < 0 || Val == CmpVal)
2831 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2832 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2833 /// the second operand.
2834 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2835 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
2836 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2837 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2838 return (Mask[0] < 2 && Mask[1] < 2);
2842 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2843 SmallVector<int, 8> M;
2845 return ::isPSHUFDMask(M, N->getValueType(0));
2848 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2849 /// is suitable for input to PSHUFHW.
2850 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2851 if (VT != MVT::v8i16)
2854 // Lower quadword copied in order or undef.
2855 for (int i = 0; i != 4; ++i)
2856 if (Mask[i] >= 0 && Mask[i] != i)
2859 // Upper quadword shuffled.
2860 for (int i = 4; i != 8; ++i)
2861 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2867 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2868 SmallVector<int, 8> M;
2870 return ::isPSHUFHWMask(M, N->getValueType(0));
2873 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2874 /// is suitable for input to PSHUFLW.
2875 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2876 if (VT != MVT::v8i16)
2879 // Upper quadword copied in order.
2880 for (int i = 4; i != 8; ++i)
2881 if (Mask[i] >= 0 && Mask[i] != i)
2884 // Lower quadword shuffled.
2885 for (int i = 0; i != 4; ++i)
2892 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2893 SmallVector<int, 8> M;
2895 return ::isPSHUFLWMask(M, N->getValueType(0));
2898 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
2899 /// is suitable for input to PALIGNR.
2900 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
2902 int i, e = VT.getVectorNumElements();
2904 // Do not handle v2i64 / v2f64 shuffles with palignr.
2905 if (e < 4 || !hasSSSE3)
2908 for (i = 0; i != e; ++i)
2912 // All undef, not a palignr.
2916 // Determine if it's ok to perform a palignr with only the LHS, since we
2917 // don't have access to the actual shuffle elements to see if RHS is undef.
2918 bool Unary = Mask[i] < (int)e;
2919 bool NeedsUnary = false;
2921 int s = Mask[i] - i;
2923 // Check the rest of the elements to see if they are consecutive.
2924 for (++i; i != e; ++i) {
2929 Unary = Unary && (m < (int)e);
2930 NeedsUnary = NeedsUnary || (m < s);
2932 if (NeedsUnary && !Unary)
2934 if (Unary && m != ((s+i) & (e-1)))
2936 if (!Unary && m != (s+i))
2942 bool X86::isPALIGNRMask(ShuffleVectorSDNode *N) {
2943 SmallVector<int, 8> M;
2945 return ::isPALIGNRMask(M, N->getValueType(0), true);
2948 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2949 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2950 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2951 int NumElems = VT.getVectorNumElements();
2952 if (NumElems != 2 && NumElems != 4)
2955 int Half = NumElems / 2;
2956 for (int i = 0; i < Half; ++i)
2957 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2959 for (int i = Half; i < NumElems; ++i)
2960 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2966 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2967 SmallVector<int, 8> M;
2969 return ::isSHUFPMask(M, N->getValueType(0));
2972 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2973 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2974 /// half elements to come from vector 1 (which would equal the dest.) and
2975 /// the upper half to come from vector 2.
2976 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
2977 int NumElems = VT.getVectorNumElements();
2979 if (NumElems != 2 && NumElems != 4)
2982 int Half = NumElems / 2;
2983 for (int i = 0; i < Half; ++i)
2984 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2986 for (int i = Half; i < NumElems; ++i)
2987 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2992 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2993 SmallVector<int, 8> M;
2995 return isCommutedSHUFPMask(M, N->getValueType(0));
2998 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2999 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3000 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3001 if (N->getValueType(0).getVectorNumElements() != 4)
3004 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3005 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3006 isUndefOrEqual(N->getMaskElt(1), 7) &&
3007 isUndefOrEqual(N->getMaskElt(2), 2) &&
3008 isUndefOrEqual(N->getMaskElt(3), 3);
3011 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3012 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3014 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3015 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3020 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3021 isUndefOrEqual(N->getMaskElt(1), 3) &&
3022 isUndefOrEqual(N->getMaskElt(2), 2) &&
3023 isUndefOrEqual(N->getMaskElt(3), 3);
3026 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3027 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3028 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3029 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3031 if (NumElems != 2 && NumElems != 4)
3034 for (unsigned i = 0; i < NumElems/2; ++i)
3035 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3038 for (unsigned i = NumElems/2; i < NumElems; ++i)
3039 if (!isUndefOrEqual(N->getMaskElt(i), i))
3045 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3046 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3047 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3048 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3050 if (NumElems != 2 && NumElems != 4)
3053 for (unsigned i = 0; i < NumElems/2; ++i)
3054 if (!isUndefOrEqual(N->getMaskElt(i), i))
3057 for (unsigned i = 0; i < NumElems/2; ++i)
3058 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3064 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3065 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3066 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3067 bool V2IsSplat = false) {
3068 int NumElts = VT.getVectorNumElements();
3069 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3072 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3074 int BitI1 = Mask[i+1];
3075 if (!isUndefOrEqual(BitI, j))
3078 if (!isUndefOrEqual(BitI1, NumElts))
3081 if (!isUndefOrEqual(BitI1, j + NumElts))
3088 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3089 SmallVector<int, 8> M;
3091 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3094 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3095 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3096 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3097 bool V2IsSplat = false) {
3098 int NumElts = VT.getVectorNumElements();
3099 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
3102 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
3104 int BitI1 = Mask[i+1];
3105 if (!isUndefOrEqual(BitI, j + NumElts/2))
3108 if (isUndefOrEqual(BitI1, NumElts))
3111 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
3118 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3119 SmallVector<int, 8> M;
3121 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3124 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3125 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3127 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3128 int NumElems = VT.getVectorNumElements();
3129 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3132 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
3134 int BitI1 = Mask[i+1];
3135 if (!isUndefOrEqual(BitI, j))
3137 if (!isUndefOrEqual(BitI1, j))
3143 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3144 SmallVector<int, 8> M;
3146 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3149 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3150 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3152 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3153 int NumElems = VT.getVectorNumElements();
3154 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3157 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3159 int BitI1 = Mask[i+1];
3160 if (!isUndefOrEqual(BitI, j))
3162 if (!isUndefOrEqual(BitI1, j))
3168 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3169 SmallVector<int, 8> M;
3171 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3174 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3175 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3176 /// MOVSD, and MOVD, i.e. setting the lowest element.
3177 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3178 if (VT.getVectorElementType().getSizeInBits() < 32)
3181 int NumElts = VT.getVectorNumElements();
3183 if (!isUndefOrEqual(Mask[0], NumElts))
3186 for (int i = 1; i < NumElts; ++i)
3187 if (!isUndefOrEqual(Mask[i], i))
3193 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3194 SmallVector<int, 8> M;
3196 return ::isMOVLMask(M, N->getValueType(0));
3199 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3200 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3201 /// element of vector 2 and the other elements to come from vector 1 in order.
3202 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3203 bool V2IsSplat = false, bool V2IsUndef = false) {
3204 int NumOps = VT.getVectorNumElements();
3205 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3208 if (!isUndefOrEqual(Mask[0], 0))
3211 for (int i = 1; i < NumOps; ++i)
3212 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3213 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3214 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3220 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3221 bool V2IsUndef = false) {
3222 SmallVector<int, 8> M;
3224 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3227 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3228 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3229 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
3230 if (N->getValueType(0).getVectorNumElements() != 4)
3233 // Expect 1, 1, 3, 3
3234 for (unsigned i = 0; i < 2; ++i) {
3235 int Elt = N->getMaskElt(i);
3236 if (Elt >= 0 && Elt != 1)
3241 for (unsigned i = 2; i < 4; ++i) {
3242 int Elt = N->getMaskElt(i);
3243 if (Elt >= 0 && Elt != 3)
3248 // Don't use movshdup if it can be done with a shufps.
3249 // FIXME: verify that matching u, u, 3, 3 is what we want.
3253 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3254 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3255 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
3256 if (N->getValueType(0).getVectorNumElements() != 4)
3259 // Expect 0, 0, 2, 2
3260 for (unsigned i = 0; i < 2; ++i)
3261 if (N->getMaskElt(i) > 0)
3265 for (unsigned i = 2; i < 4; ++i) {
3266 int Elt = N->getMaskElt(i);
3267 if (Elt >= 0 && Elt != 2)
3272 // Don't use movsldup if it can be done with a shufps.
3276 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3277 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
3278 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3279 int e = N->getValueType(0).getVectorNumElements() / 2;
3281 for (int i = 0; i < e; ++i)
3282 if (!isUndefOrEqual(N->getMaskElt(i), i))
3284 for (int i = 0; i < e; ++i)
3285 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3290 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
3291 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
3292 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
3293 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3294 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
3296 unsigned Shift = (NumOperands == 4) ? 2 : 1;
3298 for (int i = 0; i < NumOperands; ++i) {
3299 int Val = SVOp->getMaskElt(NumOperands-i-1);
3300 if (Val < 0) Val = 0;
3301 if (Val >= NumOperands) Val -= NumOperands;
3303 if (i != NumOperands - 1)
3309 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
3310 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
3311 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
3312 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3314 // 8 nodes, but we only care about the last 4.
3315 for (unsigned i = 7; i >= 4; --i) {
3316 int Val = SVOp->getMaskElt(i);
3325 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
3326 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
3327 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
3328 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3330 // 8 nodes, but we only care about the first 4.
3331 for (int i = 3; i >= 0; --i) {
3332 int Val = SVOp->getMaskElt(i);
3341 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
3342 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
3343 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
3344 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3345 EVT VVT = N->getValueType(0);
3346 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
3350 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
3351 Val = SVOp->getMaskElt(i);
3355 return (Val - i) * EltSize;
3358 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
3360 bool X86::isZeroNode(SDValue Elt) {
3361 return ((isa<ConstantSDNode>(Elt) &&
3362 cast<ConstantSDNode>(Elt)->isNullValue()) ||
3363 (isa<ConstantFPSDNode>(Elt) &&
3364 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
3367 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
3368 /// their permute mask.
3369 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
3370 SelectionDAG &DAG) {
3371 EVT VT = SVOp->getValueType(0);
3372 unsigned NumElems = VT.getVectorNumElements();
3373 SmallVector<int, 8> MaskVec;
3375 for (unsigned i = 0; i != NumElems; ++i) {
3376 int idx = SVOp->getMaskElt(i);
3378 MaskVec.push_back(idx);
3379 else if (idx < (int)NumElems)
3380 MaskVec.push_back(idx + NumElems);
3382 MaskVec.push_back(idx - NumElems);
3384 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
3385 SVOp->getOperand(0), &MaskVec[0]);
3388 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3389 /// the two vector operands have swapped position.
3390 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
3391 unsigned NumElems = VT.getVectorNumElements();
3392 for (unsigned i = 0; i != NumElems; ++i) {
3396 else if (idx < (int)NumElems)
3397 Mask[i] = idx + NumElems;
3399 Mask[i] = idx - NumElems;
3403 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
3404 /// match movhlps. The lower half elements should come from upper half of
3405 /// V1 (and in order), and the upper half elements should come from the upper
3406 /// half of V2 (and in order).
3407 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
3408 if (Op->getValueType(0).getVectorNumElements() != 4)
3410 for (unsigned i = 0, e = 2; i != e; ++i)
3411 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
3413 for (unsigned i = 2; i != 4; ++i)
3414 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
3419 /// isScalarLoadToVector - Returns true if the node is a scalar load that
3420 /// is promoted to a vector. It also returns the LoadSDNode by reference if
3422 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
3423 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
3425 N = N->getOperand(0).getNode();
3426 if (!ISD::isNON_EXTLoad(N))
3429 *LD = cast<LoadSDNode>(N);
3433 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
3434 /// match movlp{s|d}. The lower half elements should come from lower half of
3435 /// V1 (and in order), and the upper half elements should come from the upper
3436 /// half of V2 (and in order). And since V1 will become the source of the
3437 /// MOVLP, it must be either a vector load or a scalar load to vector.
3438 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
3439 ShuffleVectorSDNode *Op) {
3440 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
3442 // Is V2 is a vector load, don't do this transformation. We will try to use
3443 // load folding shufps op.
3444 if (ISD::isNON_EXTLoad(V2))
3447 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
3449 if (NumElems != 2 && NumElems != 4)
3451 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3452 if (!isUndefOrEqual(Op->getMaskElt(i), i))
3454 for (unsigned i = NumElems/2; i != NumElems; ++i)
3455 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
3460 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
3462 static bool isSplatVector(SDNode *N) {
3463 if (N->getOpcode() != ISD::BUILD_VECTOR)
3466 SDValue SplatValue = N->getOperand(0);
3467 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
3468 if (N->getOperand(i) != SplatValue)
3473 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
3474 /// to an zero vector.
3475 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
3476 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
3477 SDValue V1 = N->getOperand(0);
3478 SDValue V2 = N->getOperand(1);
3479 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3480 for (unsigned i = 0; i != NumElems; ++i) {
3481 int Idx = N->getMaskElt(i);
3482 if (Idx >= (int)NumElems) {
3483 unsigned Opc = V2.getOpcode();
3484 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
3486 if (Opc != ISD::BUILD_VECTOR ||
3487 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
3489 } else if (Idx >= 0) {
3490 unsigned Opc = V1.getOpcode();
3491 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
3493 if (Opc != ISD::BUILD_VECTOR ||
3494 !X86::isZeroNode(V1.getOperand(Idx)))
3501 /// getZeroVector - Returns a vector of specified type with all zero elements.
3503 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
3505 assert(VT.isVector() && "Expected a vector type");
3507 // Always build SSE zero vectors as <4 x i32> bitcasted
3508 // to their dest type. This ensures they get CSE'd.
3510 if (VT.getSizeInBits() == 128) { // SSE
3511 if (HasSSE2) { // SSE2
3512 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3513 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3515 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3516 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
3518 } else if (VT.getSizeInBits() == 256) { // AVX
3519 // 256-bit logic and arithmetic instructions in AVX are
3520 // all floating-point, no support for integer ops. Default
3521 // to emitting fp zeroed vectors then.
3522 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
3523 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
3524 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
3526 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3529 /// getOnesVector - Returns a vector of specified type with all bits set.
3531 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3532 assert(VT.isVector() && "Expected a vector type");
3534 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
3535 // type. This ensures they get CSE'd.
3536 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
3538 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
3539 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
3543 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
3544 /// that point to V2 points to its first element.
3545 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3546 EVT VT = SVOp->getValueType(0);
3547 unsigned NumElems = VT.getVectorNumElements();
3549 bool Changed = false;
3550 SmallVector<int, 8> MaskVec;
3551 SVOp->getMask(MaskVec);
3553 for (unsigned i = 0; i != NumElems; ++i) {
3554 if (MaskVec[i] > (int)NumElems) {
3555 MaskVec[i] = NumElems;
3560 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
3561 SVOp->getOperand(1), &MaskVec[0]);
3562 return SDValue(SVOp, 0);
3565 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
3566 /// operation of specified width.
3567 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3569 unsigned NumElems = VT.getVectorNumElements();
3570 SmallVector<int, 8> Mask;
3571 Mask.push_back(NumElems);
3572 for (unsigned i = 1; i != NumElems; ++i)
3574 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3577 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
3578 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3580 unsigned NumElems = VT.getVectorNumElements();
3581 SmallVector<int, 8> Mask;
3582 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
3584 Mask.push_back(i + NumElems);
3586 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3589 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
3590 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
3592 unsigned NumElems = VT.getVectorNumElements();
3593 unsigned Half = NumElems/2;
3594 SmallVector<int, 8> Mask;
3595 for (unsigned i = 0; i != Half; ++i) {
3596 Mask.push_back(i + Half);
3597 Mask.push_back(i + NumElems + Half);
3599 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3602 /// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32.
3603 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
3604 EVT PVT = MVT::v4f32;
3605 EVT VT = SV->getValueType(0);
3606 DebugLoc dl = SV->getDebugLoc();
3607 SDValue V1 = SV->getOperand(0);
3608 int NumElems = VT.getVectorNumElements();
3609 int EltNo = SV->getSplatIndex();
3611 // unpack elements to the correct location
3612 while (NumElems > 4) {
3613 if (EltNo < NumElems/2) {
3614 V1 = getUnpackl(DAG, dl, VT, V1, V1);
3616 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3617 EltNo -= NumElems/2;
3622 // Perform the splat.
3623 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3624 V1 = DAG.getNode(ISD::BITCAST, dl, PVT, V1);
3625 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3626 return DAG.getNode(ISD::BITCAST, dl, VT, V1);
3629 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3630 /// vector of zero or undef vector. This produces a shuffle where the low
3631 /// element of V2 is swizzled into the zero/undef vector, landing at element
3632 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3633 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3634 bool isZero, bool HasSSE2,
3635 SelectionDAG &DAG) {
3636 EVT VT = V2.getValueType();
3638 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3639 unsigned NumElems = VT.getVectorNumElements();
3640 SmallVector<int, 16> MaskVec;
3641 for (unsigned i = 0; i != NumElems; ++i)
3642 // If this is the insertion idx, put the low elt of V2 here.
3643 MaskVec.push_back(i == Idx ? NumElems : i);
3644 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3647 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
3648 /// element of the result of the vector shuffle.
3649 SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
3652 return SDValue(); // Limit search depth.
3654 SDValue V = SDValue(N, 0);
3655 EVT VT = V.getValueType();
3656 unsigned Opcode = V.getOpcode();
3658 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
3659 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
3660 Index = SV->getMaskElt(Index);
3663 return DAG.getUNDEF(VT.getVectorElementType());
3665 int NumElems = VT.getVectorNumElements();
3666 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
3667 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
3670 // Recurse into target specific vector shuffles to find scalars.
3671 if (isTargetShuffle(Opcode)) {
3672 int NumElems = VT.getVectorNumElements();
3673 SmallVector<unsigned, 16> ShuffleMask;
3677 case X86ISD::SHUFPS:
3678 case X86ISD::SHUFPD:
3679 ImmN = N->getOperand(N->getNumOperands()-1);
3680 DecodeSHUFPSMask(NumElems,
3681 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3684 case X86ISD::PUNPCKHBW:
3685 case X86ISD::PUNPCKHWD:
3686 case X86ISD::PUNPCKHDQ:
3687 case X86ISD::PUNPCKHQDQ:
3688 DecodePUNPCKHMask(NumElems, ShuffleMask);
3690 case X86ISD::UNPCKHPS:
3691 case X86ISD::UNPCKHPD:
3692 DecodeUNPCKHPMask(NumElems, ShuffleMask);
3694 case X86ISD::PUNPCKLBW:
3695 case X86ISD::PUNPCKLWD:
3696 case X86ISD::PUNPCKLDQ:
3697 case X86ISD::PUNPCKLQDQ:
3698 DecodePUNPCKLMask(NumElems, ShuffleMask);
3700 case X86ISD::UNPCKLPS:
3701 case X86ISD::UNPCKLPD:
3702 DecodeUNPCKLPMask(NumElems, ShuffleMask);
3704 case X86ISD::MOVHLPS:
3705 DecodeMOVHLPSMask(NumElems, ShuffleMask);
3707 case X86ISD::MOVLHPS:
3708 DecodeMOVLHPSMask(NumElems, ShuffleMask);
3710 case X86ISD::PSHUFD:
3711 ImmN = N->getOperand(N->getNumOperands()-1);
3712 DecodePSHUFMask(NumElems,
3713 cast<ConstantSDNode>(ImmN)->getZExtValue(),
3716 case X86ISD::PSHUFHW:
3717 ImmN = N->getOperand(N->getNumOperands()-1);
3718 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3721 case X86ISD::PSHUFLW:
3722 ImmN = N->getOperand(N->getNumOperands()-1);
3723 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
3727 case X86ISD::MOVSD: {
3728 // The index 0 always comes from the first element of the second source,
3729 // this is why MOVSS and MOVSD are used in the first place. The other
3730 // elements come from the other positions of the first source vector.
3731 unsigned OpNum = (Index == 0) ? 1 : 0;
3732 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
3736 assert("not implemented for target shuffle node");
3740 Index = ShuffleMask[Index];
3742 return DAG.getUNDEF(VT.getVectorElementType());
3744 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
3745 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
3749 // Actual nodes that may contain scalar elements
3750 if (Opcode == ISD::BITCAST) {
3751 V = V.getOperand(0);
3752 EVT SrcVT = V.getValueType();
3753 unsigned NumElems = VT.getVectorNumElements();
3755 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
3759 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
3760 return (Index == 0) ? V.getOperand(0)
3761 : DAG.getUNDEF(VT.getVectorElementType());
3763 if (V.getOpcode() == ISD::BUILD_VECTOR)
3764 return V.getOperand(Index);
3769 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
3770 /// shuffle operation which come from a consecutively from a zero. The
3771 /// search can start in two diferent directions, from left or right.
3773 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
3774 bool ZerosFromLeft, SelectionDAG &DAG) {
3777 while (i < NumElems) {
3778 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
3779 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
3780 if (!(Elt.getNode() &&
3781 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
3789 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
3790 /// MaskE correspond consecutively to elements from one of the vector operands,
3791 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
3793 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
3794 int OpIdx, int NumElems, unsigned &OpNum) {
3795 bool SeenV1 = false;
3796 bool SeenV2 = false;
3798 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
3799 int Idx = SVOp->getMaskElt(i);
3800 // Ignore undef indicies
3809 // Only accept consecutive elements from the same vector
3810 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
3814 OpNum = SeenV1 ? 0 : 1;
3818 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
3819 /// logical left shift of a vector.
3820 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3821 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3822 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3823 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3824 false /* check zeros from right */, DAG);
3830 // Considering the elements in the mask that are not consecutive zeros,
3831 // check if they consecutively come from only one of the source vectors.
3833 // V1 = {X, A, B, C} 0
3835 // vector_shuffle V1, V2 <1, 2, 3, X>
3837 if (!isShuffleMaskConsecutive(SVOp,
3838 0, // Mask Start Index
3839 NumElems-NumZeros-1, // Mask End Index
3840 NumZeros, // Where to start looking in the src vector
3841 NumElems, // Number of elements in vector
3842 OpSrc)) // Which source operand ?
3847 ShVal = SVOp->getOperand(OpSrc);
3851 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
3852 /// logical left shift of a vector.
3853 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3854 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3855 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
3856 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
3857 true /* check zeros from left */, DAG);
3863 // Considering the elements in the mask that are not consecutive zeros,
3864 // check if they consecutively come from only one of the source vectors.
3866 // 0 { A, B, X, X } = V2
3868 // vector_shuffle V1, V2 <X, X, 4, 5>
3870 if (!isShuffleMaskConsecutive(SVOp,
3871 NumZeros, // Mask Start Index
3872 NumElems-1, // Mask End Index
3873 0, // Where to start looking in the src vector
3874 NumElems, // Number of elements in vector
3875 OpSrc)) // Which source operand ?
3880 ShVal = SVOp->getOperand(OpSrc);
3884 /// isVectorShift - Returns true if the shuffle can be implemented as a
3885 /// logical left or right shift of a vector.
3886 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3887 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3888 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
3889 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
3895 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3897 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3898 unsigned NumNonZero, unsigned NumZero,
3900 const TargetLowering &TLI) {
3904 DebugLoc dl = Op.getDebugLoc();
3907 for (unsigned i = 0; i < 16; ++i) {
3908 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3909 if (ThisIsNonZero && First) {
3911 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3913 V = DAG.getUNDEF(MVT::v8i16);
3918 SDValue ThisElt(0, 0), LastElt(0, 0);
3919 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3920 if (LastIsNonZero) {
3921 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3922 MVT::i16, Op.getOperand(i-1));
3924 if (ThisIsNonZero) {
3925 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3926 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3927 ThisElt, DAG.getConstant(8, MVT::i8));
3929 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3933 if (ThisElt.getNode())
3934 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3935 DAG.getIntPtrConstant(i/2));
3939 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
3942 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3944 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3945 unsigned NumNonZero, unsigned NumZero,
3947 const TargetLowering &TLI) {
3951 DebugLoc dl = Op.getDebugLoc();
3954 for (unsigned i = 0; i < 8; ++i) {
3955 bool isNonZero = (NonZeros & (1 << i)) != 0;
3959 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3961 V = DAG.getUNDEF(MVT::v8i16);
3964 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3965 MVT::v8i16, V, Op.getOperand(i),
3966 DAG.getIntPtrConstant(i));
3973 /// getVShift - Return a vector logical shift node.
3975 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
3976 unsigned NumBits, SelectionDAG &DAG,
3977 const TargetLowering &TLI, DebugLoc dl) {
3978 EVT ShVT = MVT::v2i64;
3979 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3980 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
3981 return DAG.getNode(ISD::BITCAST, dl, VT,
3982 DAG.getNode(Opc, dl, ShVT, SrcOp,
3983 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3987 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
3988 SelectionDAG &DAG) const {
3990 // Check if the scalar load can be widened into a vector load. And if
3991 // the address is "base + cst" see if the cst can be "absorbed" into
3992 // the shuffle mask.
3993 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
3994 SDValue Ptr = LD->getBasePtr();
3995 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
3997 EVT PVT = LD->getValueType(0);
3998 if (PVT != MVT::i32 && PVT != MVT::f32)
4003 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4004 FI = FINode->getIndex();
4006 } else if (Ptr.getOpcode() == ISD::ADD &&
4007 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4008 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4009 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4010 Offset = Ptr.getConstantOperandVal(1);
4011 Ptr = Ptr.getOperand(0);
4016 SDValue Chain = LD->getChain();
4017 // Make sure the stack object alignment is at least 16.
4018 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4019 if (DAG.InferPtrAlignment(Ptr) < 16) {
4020 if (MFI->isFixedObjectIndex(FI)) {
4021 // Can't change the alignment. FIXME: It's possible to compute
4022 // the exact stack offset and reference FI + adjust offset instead.
4023 // If someone *really* cares about this. That's the way to implement it.
4026 MFI->setObjectAlignment(FI, 16);
4030 // (Offset % 16) must be multiple of 4. Then address is then
4031 // Ptr + (Offset & ~15).
4034 if ((Offset % 16) & 3)
4036 int64_t StartOffset = Offset & ~15;
4038 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4039 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4041 int EltNo = (Offset - StartOffset) >> 2;
4042 int Mask[4] = { EltNo, EltNo, EltNo, EltNo };
4043 EVT VT = (PVT == MVT::i32) ? MVT::v4i32 : MVT::v4f32;
4044 SDValue V1 = DAG.getLoad(VT, dl, Chain, Ptr,
4045 LD->getPointerInfo().getWithOffset(StartOffset),
4047 // Canonicalize it to a v4i32 shuffle.
4048 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V1);
4049 return DAG.getNode(ISD::BITCAST, dl, VT,
4050 DAG.getVectorShuffle(MVT::v4i32, dl, V1,
4051 DAG.getUNDEF(MVT::v4i32),&Mask[0]));
4057 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4058 /// vector of type 'VT', see if the elements can be replaced by a single large
4059 /// load which has the same value as a build_vector whose operands are 'elts'.
4061 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4063 /// FIXME: we'd also like to handle the case where the last elements are zero
4064 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4065 /// There's even a handy isZeroNode for that purpose.
4066 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4067 DebugLoc &DL, SelectionDAG &DAG) {
4068 EVT EltVT = VT.getVectorElementType();
4069 unsigned NumElems = Elts.size();
4071 LoadSDNode *LDBase = NULL;
4072 unsigned LastLoadedElt = -1U;
4074 // For each element in the initializer, see if we've found a load or an undef.
4075 // If we don't find an initial load element, or later load elements are
4076 // non-consecutive, bail out.
4077 for (unsigned i = 0; i < NumElems; ++i) {
4078 SDValue Elt = Elts[i];
4080 if (!Elt.getNode() ||
4081 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4084 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4086 LDBase = cast<LoadSDNode>(Elt.getNode());
4090 if (Elt.getOpcode() == ISD::UNDEF)
4093 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4094 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
4099 // If we have found an entire vector of loads and undefs, then return a large
4100 // load of the entire vector width starting at the base pointer. If we found
4101 // consecutive loads for the low half, generate a vzext_load node.
4102 if (LastLoadedElt == NumElems - 1) {
4103 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
4104 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4105 LDBase->getPointerInfo(),
4106 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
4107 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4108 LDBase->getPointerInfo(),
4109 LDBase->isVolatile(), LDBase->isNonTemporal(),
4110 LDBase->getAlignment());
4111 } else if (NumElems == 4 && LastLoadedElt == 1) {
4112 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4113 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4114 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
4116 LDBase->getMemOperand());
4117 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
4123 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
4124 DebugLoc dl = Op.getDebugLoc();
4125 // All zero's are handled with pxor in SSE2 and above, xorps in SSE1.
4126 // All one's are handled with pcmpeqd. In AVX, zero's are handled with
4127 // vpxor in 128-bit and xor{pd,ps} in 256-bit, but no 256 version of pcmpeqd
4128 // is present, so AllOnes is ignored.
4129 if (ISD::isBuildVectorAllZeros(Op.getNode()) ||
4130 (Op.getValueType().getSizeInBits() != 256 &&
4131 ISD::isBuildVectorAllOnes(Op.getNode()))) {
4132 // Canonicalize this to <4 x i32> (SSE) to
4133 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
4134 // eliminated on x86-32 hosts.
4135 if (Op.getValueType() == MVT::v4i32)
4138 if (ISD::isBuildVectorAllOnes(Op.getNode()))
4139 return getOnesVector(Op.getValueType(), DAG, dl);
4140 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
4143 EVT VT = Op.getValueType();
4144 EVT ExtVT = VT.getVectorElementType();
4145 unsigned EVTBits = ExtVT.getSizeInBits();
4147 unsigned NumElems = Op.getNumOperands();
4148 unsigned NumZero = 0;
4149 unsigned NumNonZero = 0;
4150 unsigned NonZeros = 0;
4151 bool IsAllConstants = true;
4152 SmallSet<SDValue, 8> Values;
4153 for (unsigned i = 0; i < NumElems; ++i) {
4154 SDValue Elt = Op.getOperand(i);
4155 if (Elt.getOpcode() == ISD::UNDEF)
4158 if (Elt.getOpcode() != ISD::Constant &&
4159 Elt.getOpcode() != ISD::ConstantFP)
4160 IsAllConstants = false;
4161 if (X86::isZeroNode(Elt))
4164 NonZeros |= (1 << i);
4169 // All undef vector. Return an UNDEF. All zero vectors were handled above.
4170 if (NumNonZero == 0)
4171 return DAG.getUNDEF(VT);
4173 // Special case for single non-zero, non-undef, element.
4174 if (NumNonZero == 1) {
4175 unsigned Idx = CountTrailingZeros_32(NonZeros);
4176 SDValue Item = Op.getOperand(Idx);
4178 // If this is an insertion of an i64 value on x86-32, and if the top bits of
4179 // the value are obviously zero, truncate the value to i32 and do the
4180 // insertion that way. Only do this if the value is non-constant or if the
4181 // value is a constant being inserted into element 0. It is cheaper to do
4182 // a constant pool load than it is to do a movd + shuffle.
4183 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
4184 (!IsAllConstants || Idx == 0)) {
4185 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
4187 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
4188 EVT VecVT = MVT::v4i32;
4189 unsigned VecElts = 4;
4191 // Truncate the value (which may itself be a constant) to i32, and
4192 // convert it to a vector with movd (S2V+shuffle to zero extend).
4193 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
4194 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
4195 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4196 Subtarget->hasSSE2(), DAG);
4198 // Now we have our 32-bit value zero extended in the low element of
4199 // a vector. If Idx != 0, swizzle it into place.
4201 SmallVector<int, 4> Mask;
4202 Mask.push_back(Idx);
4203 for (unsigned i = 1; i != VecElts; ++i)
4205 Item = DAG.getVectorShuffle(VecVT, dl, Item,
4206 DAG.getUNDEF(Item.getValueType()),
4209 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
4213 // If we have a constant or non-constant insertion into the low element of
4214 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
4215 // the rest of the elements. This will be matched as movd/movq/movss/movsd
4216 // depending on what the source datatype is.
4219 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4220 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
4221 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
4222 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4223 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
4224 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
4226 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
4227 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
4228 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
4229 EVT MiddleVT = MVT::v4i32;
4230 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
4231 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
4232 Subtarget->hasSSE2(), DAG);
4233 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
4237 // Is it a vector logical left shift?
4238 if (NumElems == 2 && Idx == 1 &&
4239 X86::isZeroNode(Op.getOperand(0)) &&
4240 !X86::isZeroNode(Op.getOperand(1))) {
4241 unsigned NumBits = VT.getSizeInBits();
4242 return getVShift(true, VT,
4243 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4244 VT, Op.getOperand(1)),
4245 NumBits/2, DAG, *this, dl);
4248 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
4251 // Otherwise, if this is a vector with i32 or f32 elements, and the element
4252 // is a non-constant being inserted into an element other than the low one,
4253 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
4254 // movd/movss) to move this into the low element, then shuffle it into
4256 if (EVTBits == 32) {
4257 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
4259 // Turn it into a shuffle of zero and zero-extended scalar to vector.
4260 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
4261 Subtarget->hasSSE2(), DAG);
4262 SmallVector<int, 8> MaskVec;
4263 for (unsigned i = 0; i < NumElems; i++)
4264 MaskVec.push_back(i == Idx ? 0 : 1);
4265 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
4269 // Splat is obviously ok. Let legalizer expand it to a shuffle.
4270 if (Values.size() == 1) {
4271 if (EVTBits == 32) {
4272 // Instead of a shuffle like this:
4273 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4274 // Check if it's possible to issue this instead.
4275 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
4276 unsigned Idx = CountTrailingZeros_32(NonZeros);
4277 SDValue Item = Op.getOperand(Idx);
4278 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
4279 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
4284 // A vector full of immediates; various special cases are already
4285 // handled, so this is best done with a single constant-pool load.
4289 // Let legalizer expand 2-wide build_vectors.
4290 if (EVTBits == 64) {
4291 if (NumNonZero == 1) {
4292 // One half is zero or undef.
4293 unsigned Idx = CountTrailingZeros_32(NonZeros);
4294 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
4295 Op.getOperand(Idx));
4296 return getShuffleVectorZeroOrUndef(V2, Idx, true,
4297 Subtarget->hasSSE2(), DAG);
4302 // If element VT is < 32 bits, convert it to inserts into a zero vector.
4303 if (EVTBits == 8 && NumElems == 16) {
4304 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
4306 if (V.getNode()) return V;
4309 if (EVTBits == 16 && NumElems == 8) {
4310 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
4312 if (V.getNode()) return V;
4315 // If element VT is == 32 bits, turn it into a number of shuffles.
4316 SmallVector<SDValue, 8> V;
4318 if (NumElems == 4 && NumZero > 0) {
4319 for (unsigned i = 0; i < 4; ++i) {
4320 bool isZero = !(NonZeros & (1 << i));
4322 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4324 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4327 for (unsigned i = 0; i < 2; ++i) {
4328 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
4331 V[i] = V[i*2]; // Must be a zero vector.
4334 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
4337 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
4340 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
4345 SmallVector<int, 8> MaskVec;
4346 bool Reverse = (NonZeros & 0x3) == 2;
4347 for (unsigned i = 0; i < 2; ++i)
4348 MaskVec.push_back(Reverse ? 1-i : i);
4349 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
4350 for (unsigned i = 0; i < 2; ++i)
4351 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
4352 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
4355 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
4356 // Check for a build vector of consecutive loads.
4357 for (unsigned i = 0; i < NumElems; ++i)
4358 V[i] = Op.getOperand(i);
4360 // Check for elements which are consecutive loads.
4361 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
4365 // For SSE 4.1, use insertps to put the high elements into the low element.
4366 if (getSubtarget()->hasSSE41()) {
4368 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
4369 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
4371 Result = DAG.getUNDEF(VT);
4373 for (unsigned i = 1; i < NumElems; ++i) {
4374 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
4375 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
4376 Op.getOperand(i), DAG.getIntPtrConstant(i));
4381 // Otherwise, expand into a number of unpckl*, start by extending each of
4382 // our (non-undef) elements to the full vector width with the element in the
4383 // bottom slot of the vector (which generates no code for SSE).
4384 for (unsigned i = 0; i < NumElems; ++i) {
4385 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
4386 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
4388 V[i] = DAG.getUNDEF(VT);
4391 // Next, we iteratively mix elements, e.g. for v4f32:
4392 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
4393 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
4394 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
4395 unsigned EltStride = NumElems >> 1;
4396 while (EltStride != 0) {
4397 for (unsigned i = 0; i < EltStride; ++i) {
4398 // If V[i+EltStride] is undef and this is the first round of mixing,
4399 // then it is safe to just drop this shuffle: V[i] is already in the
4400 // right place, the one element (since it's the first round) being
4401 // inserted as undef can be dropped. This isn't safe for successive
4402 // rounds because they will permute elements within both vectors.
4403 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
4404 EltStride == NumElems/2)
4407 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
4417 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
4418 // We support concatenate two MMX registers and place them in a MMX
4419 // register. This is better than doing a stack convert.
4420 DebugLoc dl = Op.getDebugLoc();
4421 EVT ResVT = Op.getValueType();
4422 assert(Op.getNumOperands() == 2);
4423 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
4424 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
4426 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
4427 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4428 InVec = Op.getOperand(1);
4429 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4430 unsigned NumElts = ResVT.getVectorNumElements();
4431 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4432 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
4433 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
4435 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
4436 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
4437 Mask[0] = 0; Mask[1] = 2;
4438 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
4440 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
4443 // v8i16 shuffles - Prefer shuffles in the following order:
4444 // 1. [all] pshuflw, pshufhw, optional move
4445 // 2. [ssse3] 1 x pshufb
4446 // 3. [ssse3] 2 x pshufb + 1 x por
4447 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
4449 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
4450 SelectionDAG &DAG) const {
4451 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4452 SDValue V1 = SVOp->getOperand(0);
4453 SDValue V2 = SVOp->getOperand(1);
4454 DebugLoc dl = SVOp->getDebugLoc();
4455 SmallVector<int, 8> MaskVals;
4457 // Determine if more than 1 of the words in each of the low and high quadwords
4458 // of the result come from the same quadword of one of the two inputs. Undef
4459 // mask values count as coming from any quadword, for better codegen.
4460 SmallVector<unsigned, 4> LoQuad(4);
4461 SmallVector<unsigned, 4> HiQuad(4);
4462 BitVector InputQuads(4);
4463 for (unsigned i = 0; i < 8; ++i) {
4464 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
4465 int EltIdx = SVOp->getMaskElt(i);
4466 MaskVals.push_back(EltIdx);
4475 InputQuads.set(EltIdx / 4);
4478 int BestLoQuad = -1;
4479 unsigned MaxQuad = 1;
4480 for (unsigned i = 0; i < 4; ++i) {
4481 if (LoQuad[i] > MaxQuad) {
4483 MaxQuad = LoQuad[i];
4487 int BestHiQuad = -1;
4489 for (unsigned i = 0; i < 4; ++i) {
4490 if (HiQuad[i] > MaxQuad) {
4492 MaxQuad = HiQuad[i];
4496 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
4497 // of the two input vectors, shuffle them into one input vector so only a
4498 // single pshufb instruction is necessary. If There are more than 2 input
4499 // quads, disable the next transformation since it does not help SSSE3.
4500 bool V1Used = InputQuads[0] || InputQuads[1];
4501 bool V2Used = InputQuads[2] || InputQuads[3];
4502 if (Subtarget->hasSSSE3()) {
4503 if (InputQuads.count() == 2 && V1Used && V2Used) {
4504 BestLoQuad = InputQuads.find_first();
4505 BestHiQuad = InputQuads.find_next(BestLoQuad);
4507 if (InputQuads.count() > 2) {
4513 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
4514 // the shuffle mask. If a quad is scored as -1, that means that it contains
4515 // words from all 4 input quadwords.
4517 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
4518 SmallVector<int, 8> MaskV;
4519 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
4520 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
4521 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
4522 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
4523 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
4524 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
4526 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
4527 // source words for the shuffle, to aid later transformations.
4528 bool AllWordsInNewV = true;
4529 bool InOrder[2] = { true, true };
4530 for (unsigned i = 0; i != 8; ++i) {
4531 int idx = MaskVals[i];
4533 InOrder[i/4] = false;
4534 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
4536 AllWordsInNewV = false;
4540 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
4541 if (AllWordsInNewV) {
4542 for (int i = 0; i != 8; ++i) {
4543 int idx = MaskVals[i];
4546 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
4547 if ((idx != i) && idx < 4)
4549 if ((idx != i) && idx > 3)
4558 // If we've eliminated the use of V2, and the new mask is a pshuflw or
4559 // pshufhw, that's as cheap as it gets. Return the new shuffle.
4560 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
4561 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
4562 unsigned TargetMask = 0;
4563 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
4564 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
4565 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
4566 X86::getShufflePSHUFLWImmediate(NewV.getNode());
4567 V1 = NewV.getOperand(0);
4568 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
4572 // If we have SSSE3, and all words of the result are from 1 input vector,
4573 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
4574 // is present, fall back to case 4.
4575 if (Subtarget->hasSSSE3()) {
4576 SmallVector<SDValue,16> pshufbMask;
4578 // If we have elements from both input vectors, set the high bit of the
4579 // shuffle mask element to zero out elements that come from V2 in the V1
4580 // mask, and elements that come from V1 in the V2 mask, so that the two
4581 // results can be OR'd together.
4582 bool TwoInputs = V1Used && V2Used;
4583 for (unsigned i = 0; i != 8; ++i) {
4584 int EltIdx = MaskVals[i] * 2;
4585 if (TwoInputs && (EltIdx >= 16)) {
4586 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4587 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4590 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4591 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
4593 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
4594 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4595 DAG.getNode(ISD::BUILD_VECTOR, dl,
4596 MVT::v16i8, &pshufbMask[0], 16));
4598 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4600 // Calculate the shuffle mask for the second input, shuffle it, and
4601 // OR it with the first shuffled input.
4603 for (unsigned i = 0; i != 8; ++i) {
4604 int EltIdx = MaskVals[i] * 2;
4606 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4607 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4610 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4611 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
4613 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
4614 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4615 DAG.getNode(ISD::BUILD_VECTOR, dl,
4616 MVT::v16i8, &pshufbMask[0], 16));
4617 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4618 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4621 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
4622 // and update MaskVals with new element order.
4623 BitVector InOrder(8);
4624 if (BestLoQuad >= 0) {
4625 SmallVector<int, 8> MaskV;
4626 for (int i = 0; i != 4; ++i) {
4627 int idx = MaskVals[i];
4629 MaskV.push_back(-1);
4631 } else if ((idx / 4) == BestLoQuad) {
4632 MaskV.push_back(idx & 3);
4635 MaskV.push_back(-1);
4638 for (unsigned i = 4; i != 8; ++i)
4640 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4643 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4644 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
4646 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
4650 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
4651 // and update MaskVals with the new element order.
4652 if (BestHiQuad >= 0) {
4653 SmallVector<int, 8> MaskV;
4654 for (unsigned i = 0; i != 4; ++i)
4656 for (unsigned i = 4; i != 8; ++i) {
4657 int idx = MaskVals[i];
4659 MaskV.push_back(-1);
4661 } else if ((idx / 4) == BestHiQuad) {
4662 MaskV.push_back((idx & 3) + 4);
4665 MaskV.push_back(-1);
4668 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
4671 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
4672 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
4674 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
4678 // In case BestHi & BestLo were both -1, which means each quadword has a word
4679 // from each of the four input quadwords, calculate the InOrder bitvector now
4680 // before falling through to the insert/extract cleanup.
4681 if (BestLoQuad == -1 && BestHiQuad == -1) {
4683 for (int i = 0; i != 8; ++i)
4684 if (MaskVals[i] < 0 || MaskVals[i] == i)
4688 // The other elements are put in the right place using pextrw and pinsrw.
4689 for (unsigned i = 0; i != 8; ++i) {
4692 int EltIdx = MaskVals[i];
4695 SDValue ExtOp = (EltIdx < 8)
4696 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
4697 DAG.getIntPtrConstant(EltIdx))
4698 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
4699 DAG.getIntPtrConstant(EltIdx - 8));
4700 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
4701 DAG.getIntPtrConstant(i));
4706 // v16i8 shuffles - Prefer shuffles in the following order:
4707 // 1. [ssse3] 1 x pshufb
4708 // 2. [ssse3] 2 x pshufb + 1 x por
4709 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
4711 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
4713 const X86TargetLowering &TLI) {
4714 SDValue V1 = SVOp->getOperand(0);
4715 SDValue V2 = SVOp->getOperand(1);
4716 DebugLoc dl = SVOp->getDebugLoc();
4717 SmallVector<int, 16> MaskVals;
4718 SVOp->getMask(MaskVals);
4720 // If we have SSSE3, case 1 is generated when all result bytes come from
4721 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
4722 // present, fall back to case 3.
4723 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
4726 for (unsigned i = 0; i < 16; ++i) {
4727 int EltIdx = MaskVals[i];
4736 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
4737 if (TLI.getSubtarget()->hasSSSE3()) {
4738 SmallVector<SDValue,16> pshufbMask;
4740 // If all result elements are from one input vector, then only translate
4741 // undef mask values to 0x80 (zero out result) in the pshufb mask.
4743 // Otherwise, we have elements from both input vectors, and must zero out
4744 // elements that come from V2 in the first mask, and V1 in the second mask
4745 // so that we can OR them together.
4746 bool TwoInputs = !(V1Only || V2Only);
4747 for (unsigned i = 0; i != 16; ++i) {
4748 int EltIdx = MaskVals[i];
4749 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
4750 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4753 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
4755 // If all the elements are from V2, assign it to V1 and return after
4756 // building the first pshufb.
4759 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
4760 DAG.getNode(ISD::BUILD_VECTOR, dl,
4761 MVT::v16i8, &pshufbMask[0], 16));
4765 // Calculate the shuffle mask for the second input, shuffle it, and
4766 // OR it with the first shuffled input.
4768 for (unsigned i = 0; i != 16; ++i) {
4769 int EltIdx = MaskVals[i];
4771 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
4774 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
4776 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
4777 DAG.getNode(ISD::BUILD_VECTOR, dl,
4778 MVT::v16i8, &pshufbMask[0], 16));
4779 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
4782 // No SSSE3 - Calculate in place words and then fix all out of place words
4783 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
4784 // the 16 different words that comprise the two doublequadword input vectors.
4785 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
4786 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
4787 SDValue NewV = V2Only ? V2 : V1;
4788 for (int i = 0; i != 8; ++i) {
4789 int Elt0 = MaskVals[i*2];
4790 int Elt1 = MaskVals[i*2+1];
4792 // This word of the result is all undef, skip it.
4793 if (Elt0 < 0 && Elt1 < 0)
4796 // This word of the result is already in the correct place, skip it.
4797 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
4799 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
4802 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
4803 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
4806 // If Elt0 and Elt1 are defined, are consecutive, and can be load
4807 // using a single extract together, load it and store it.
4808 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
4809 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4810 DAG.getIntPtrConstant(Elt1 / 2));
4811 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4812 DAG.getIntPtrConstant(i));
4816 // If Elt1 is defined, extract it from the appropriate source. If the
4817 // source byte is not also odd, shift the extracted word left 8 bits
4818 // otherwise clear the bottom 8 bits if we need to do an or.
4820 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
4821 DAG.getIntPtrConstant(Elt1 / 2));
4822 if ((Elt1 & 1) == 0)
4823 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
4824 DAG.getConstant(8, TLI.getShiftAmountTy()));
4826 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
4827 DAG.getConstant(0xFF00, MVT::i16));
4829 // If Elt0 is defined, extract it from the appropriate source. If the
4830 // source byte is not also even, shift the extracted word right 8 bits. If
4831 // Elt1 was also defined, OR the extracted values together before
4832 // inserting them in the result.
4834 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
4835 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
4836 if ((Elt0 & 1) != 0)
4837 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
4838 DAG.getConstant(8, TLI.getShiftAmountTy()));
4840 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
4841 DAG.getConstant(0x00FF, MVT::i16));
4842 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
4845 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
4846 DAG.getIntPtrConstant(i));
4848 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
4851 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
4852 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
4853 /// done when every pair / quad of shuffle mask elements point to elements in
4854 /// the right sequence. e.g.
4855 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
4857 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
4858 SelectionDAG &DAG, DebugLoc dl) {
4859 EVT VT = SVOp->getValueType(0);
4860 SDValue V1 = SVOp->getOperand(0);
4861 SDValue V2 = SVOp->getOperand(1);
4862 unsigned NumElems = VT.getVectorNumElements();
4863 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
4865 switch (VT.getSimpleVT().SimpleTy) {
4866 default: assert(false && "Unexpected!");
4867 case MVT::v4f32: NewVT = MVT::v2f64; break;
4868 case MVT::v4i32: NewVT = MVT::v2i64; break;
4869 case MVT::v8i16: NewVT = MVT::v4i32; break;
4870 case MVT::v16i8: NewVT = MVT::v4i32; break;
4873 int Scale = NumElems / NewWidth;
4874 SmallVector<int, 8> MaskVec;
4875 for (unsigned i = 0; i < NumElems; i += Scale) {
4877 for (int j = 0; j < Scale; ++j) {
4878 int EltIdx = SVOp->getMaskElt(i+j);
4882 StartIdx = EltIdx - (EltIdx % Scale);
4883 if (EltIdx != StartIdx + j)
4887 MaskVec.push_back(-1);
4889 MaskVec.push_back(StartIdx / Scale);
4892 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
4893 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
4894 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
4897 /// getVZextMovL - Return a zero-extending vector move low node.
4899 static SDValue getVZextMovL(EVT VT, EVT OpVT,
4900 SDValue SrcOp, SelectionDAG &DAG,
4901 const X86Subtarget *Subtarget, DebugLoc dl) {
4902 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
4903 LoadSDNode *LD = NULL;
4904 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
4905 LD = dyn_cast<LoadSDNode>(SrcOp);
4907 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
4909 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
4910 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
4911 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
4912 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
4913 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
4915 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
4916 return DAG.getNode(ISD::BITCAST, dl, VT,
4917 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4918 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4926 return DAG.getNode(ISD::BITCAST, dl, VT,
4927 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
4928 DAG.getNode(ISD::BITCAST, dl,
4932 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
4935 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4936 SDValue V1 = SVOp->getOperand(0);
4937 SDValue V2 = SVOp->getOperand(1);
4938 DebugLoc dl = SVOp->getDebugLoc();
4939 EVT VT = SVOp->getValueType(0);
4941 SmallVector<std::pair<int, int>, 8> Locs;
4943 SmallVector<int, 8> Mask1(4U, -1);
4944 SmallVector<int, 8> PermMask;
4945 SVOp->getMask(PermMask);
4949 for (unsigned i = 0; i != 4; ++i) {
4950 int Idx = PermMask[i];
4952 Locs[i] = std::make_pair(-1, -1);
4954 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
4956 Locs[i] = std::make_pair(0, NumLo);
4960 Locs[i] = std::make_pair(1, NumHi);
4962 Mask1[2+NumHi] = Idx;
4968 if (NumLo <= 2 && NumHi <= 2) {
4969 // If no more than two elements come from either vector. This can be
4970 // implemented with two shuffles. First shuffle gather the elements.
4971 // The second shuffle, which takes the first shuffle as both of its
4972 // vector operands, put the elements into the right order.
4973 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4975 SmallVector<int, 8> Mask2(4U, -1);
4977 for (unsigned i = 0; i != 4; ++i) {
4978 if (Locs[i].first == -1)
4981 unsigned Idx = (i < 2) ? 0 : 4;
4982 Idx += Locs[i].first * 2 + Locs[i].second;
4987 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
4988 } else if (NumLo == 3 || NumHi == 3) {
4989 // Otherwise, we must have three elements from one vector, call it X, and
4990 // one element from the other, call it Y. First, use a shufps to build an
4991 // intermediate vector with the one element from Y and the element from X
4992 // that will be in the same half in the final destination (the indexes don't
4993 // matter). Then, use a shufps to build the final vector, taking the half
4994 // containing the element from Y from the intermediate, and the other half
4997 // Normalize it so the 3 elements come from V1.
4998 CommuteVectorShuffleMask(PermMask, VT);
5002 // Find the element from V2.
5004 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
5005 int Val = PermMask[HiIndex];
5012 Mask1[0] = PermMask[HiIndex];
5014 Mask1[2] = PermMask[HiIndex^1];
5016 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5019 Mask1[0] = PermMask[0];
5020 Mask1[1] = PermMask[1];
5021 Mask1[2] = HiIndex & 1 ? 6 : 4;
5022 Mask1[3] = HiIndex & 1 ? 4 : 6;
5023 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
5025 Mask1[0] = HiIndex & 1 ? 2 : 0;
5026 Mask1[1] = HiIndex & 1 ? 0 : 2;
5027 Mask1[2] = PermMask[2];
5028 Mask1[3] = PermMask[3];
5033 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
5037 // Break it into (shuffle shuffle_hi, shuffle_lo).
5039 SmallVector<int,8> LoMask(4U, -1);
5040 SmallVector<int,8> HiMask(4U, -1);
5042 SmallVector<int,8> *MaskPtr = &LoMask;
5043 unsigned MaskIdx = 0;
5046 for (unsigned i = 0; i != 4; ++i) {
5053 int Idx = PermMask[i];
5055 Locs[i] = std::make_pair(-1, -1);
5056 } else if (Idx < 4) {
5057 Locs[i] = std::make_pair(MaskIdx, LoIdx);
5058 (*MaskPtr)[LoIdx] = Idx;
5061 Locs[i] = std::make_pair(MaskIdx, HiIdx);
5062 (*MaskPtr)[HiIdx] = Idx;
5067 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
5068 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
5069 SmallVector<int, 8> MaskOps;
5070 for (unsigned i = 0; i != 4; ++i) {
5071 if (Locs[i].first == -1) {
5072 MaskOps.push_back(-1);
5074 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
5075 MaskOps.push_back(Idx);
5078 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
5081 static bool MayFoldVectorLoad(SDValue V) {
5082 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5083 V = V.getOperand(0);
5084 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5085 V = V.getOperand(0);
5091 // FIXME: the version above should always be used. Since there's
5092 // a bug where several vector shuffles can't be folded because the
5093 // DAG is not updated during lowering and a node claims to have two
5094 // uses while it only has one, use this version, and let isel match
5095 // another instruction if the load really happens to have more than
5096 // one use. Remove this version after this bug get fixed.
5097 // rdar://8434668, PR8156
5098 static bool RelaxedMayFoldVectorLoad(SDValue V) {
5099 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
5100 V = V.getOperand(0);
5101 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5102 V = V.getOperand(0);
5103 if (ISD::isNormalLoad(V.getNode()))
5108 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
5109 /// a vector extract, and if both can be later optimized into a single load.
5110 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
5111 /// here because otherwise a target specific shuffle node is going to be
5112 /// emitted for this shuffle, and the optimization not done.
5113 /// FIXME: This is probably not the best approach, but fix the problem
5114 /// until the right path is decided.
5116 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
5117 const TargetLowering &TLI) {
5118 EVT VT = V.getValueType();
5119 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
5121 // Be sure that the vector shuffle is present in a pattern like this:
5122 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
5126 SDNode *N = *V.getNode()->use_begin();
5127 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5130 SDValue EltNo = N->getOperand(1);
5131 if (!isa<ConstantSDNode>(EltNo))
5134 // If the bit convert changed the number of elements, it is unsafe
5135 // to examine the mask.
5136 bool HasShuffleIntoBitcast = false;
5137 if (V.getOpcode() == ISD::BITCAST) {
5138 EVT SrcVT = V.getOperand(0).getValueType();
5139 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
5141 V = V.getOperand(0);
5142 HasShuffleIntoBitcast = true;
5145 // Select the input vector, guarding against out of range extract vector.
5146 unsigned NumElems = VT.getVectorNumElements();
5147 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5148 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
5149 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
5151 // Skip one more bit_convert if necessary
5152 if (V.getOpcode() == ISD::BITCAST)
5153 V = V.getOperand(0);
5155 if (ISD::isNormalLoad(V.getNode())) {
5156 // Is the original load suitable?
5157 LoadSDNode *LN0 = cast<LoadSDNode>(V);
5159 // FIXME: avoid the multi-use bug that is preventing lots of
5160 // of foldings to be detected, this is still wrong of course, but
5161 // give the temporary desired behavior, and if it happens that
5162 // the load has real more uses, during isel it will not fold, and
5163 // will generate poor code.
5164 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
5167 if (!HasShuffleIntoBitcast)
5170 // If there's a bitcast before the shuffle, check if the load type and
5171 // alignment is valid.
5172 unsigned Align = LN0->getAlignment();
5174 TLI.getTargetData()->getABITypeAlignment(
5175 VT.getTypeForEVT(*DAG.getContext()));
5177 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
5185 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
5186 EVT VT = Op.getValueType();
5188 // Canonizalize to v2f64.
5189 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
5190 return DAG.getNode(ISD::BITCAST, dl, VT,
5191 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
5196 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
5198 SDValue V1 = Op.getOperand(0);
5199 SDValue V2 = Op.getOperand(1);
5200 EVT VT = Op.getValueType();
5202 assert(VT != MVT::v2i64 && "unsupported shuffle type");
5204 if (HasSSE2 && VT == MVT::v2f64)
5205 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
5208 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V2, DAG);
5212 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
5213 SDValue V1 = Op.getOperand(0);
5214 SDValue V2 = Op.getOperand(1);
5215 EVT VT = Op.getValueType();
5217 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
5218 "unsupported shuffle type");
5220 if (V2.getOpcode() == ISD::UNDEF)
5224 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
5228 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
5229 SDValue V1 = Op.getOperand(0);
5230 SDValue V2 = Op.getOperand(1);
5231 EVT VT = Op.getValueType();
5232 unsigned NumElems = VT.getVectorNumElements();
5234 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
5235 // operand of these instructions is only memory, so check if there's a
5236 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
5238 bool CanFoldLoad = false;
5240 // Trivial case, when V2 comes from a load.
5241 if (MayFoldVectorLoad(V2))
5244 // When V1 is a load, it can be folded later into a store in isel, example:
5245 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
5247 // (MOVLPSmr addr:$src1, VR128:$src2)
5248 // So, recognize this potential and also use MOVLPS or MOVLPD
5249 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
5253 if (HasSSE2 && NumElems == 2)
5254 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
5257 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
5260 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5261 // movl and movlp will both match v2i64, but v2i64 is never matched by
5262 // movl earlier because we make it strict to avoid messing with the movlp load
5263 // folding logic (see the code above getMOVLP call). Match it here then,
5264 // this is horrible, but will stay like this until we move all shuffle
5265 // matching to x86 specific nodes. Note that for the 1st condition all
5266 // types are matched with movsd.
5267 if ((HasSSE2 && NumElems == 2) || !X86::isMOVLMask(SVOp))
5268 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5270 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5273 assert(VT != MVT::v4i32 && "unsupported shuffle type");
5275 // Invert the operand order and use SHUFPS to match it.
5276 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V2, V1,
5277 X86::getShuffleSHUFImmediate(SVOp), DAG);
5280 static inline unsigned getUNPCKLOpcode(EVT VT) {
5281 switch(VT.getSimpleVT().SimpleTy) {
5282 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
5283 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
5284 case MVT::v4f32: return X86ISD::UNPCKLPS;
5285 case MVT::v2f64: return X86ISD::UNPCKLPD;
5286 case MVT::v16i8: return X86ISD::PUNPCKLBW;
5287 case MVT::v8i16: return X86ISD::PUNPCKLWD;
5289 llvm_unreachable("Unknow type for unpckl");
5294 static inline unsigned getUNPCKHOpcode(EVT VT) {
5295 switch(VT.getSimpleVT().SimpleTy) {
5296 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
5297 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
5298 case MVT::v4f32: return X86ISD::UNPCKHPS;
5299 case MVT::v2f64: return X86ISD::UNPCKHPD;
5300 case MVT::v16i8: return X86ISD::PUNPCKHBW;
5301 case MVT::v8i16: return X86ISD::PUNPCKHWD;
5303 llvm_unreachable("Unknow type for unpckh");
5309 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
5310 const TargetLowering &TLI,
5311 const X86Subtarget *Subtarget) {
5312 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5313 EVT VT = Op.getValueType();
5314 DebugLoc dl = Op.getDebugLoc();
5315 SDValue V1 = Op.getOperand(0);
5316 SDValue V2 = Op.getOperand(1);
5318 if (isZeroShuffle(SVOp))
5319 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5321 // Handle splat operations
5322 if (SVOp->isSplat()) {
5323 // Special case, this is the only place now where it's
5324 // allowed to return a vector_shuffle operation without
5325 // using a target specific node, because *hopefully* it
5326 // will be optimized away by the dag combiner.
5327 if (VT.getVectorNumElements() <= 4 &&
5328 CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
5331 // Handle splats by matching through known masks
5332 if (VT.getVectorNumElements() <= 4)
5335 // Canonicalize all of the remaining to v4f32.
5336 return PromoteSplat(SVOp, DAG);
5339 // If the shuffle can be profitably rewritten as a narrower shuffle, then
5341 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
5342 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5343 if (NewOp.getNode())
5344 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
5345 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
5346 // FIXME: Figure out a cleaner way to do this.
5347 // Try to make use of movq to zero out the top part.
5348 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
5349 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5350 if (NewOp.getNode()) {
5351 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
5352 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
5353 DAG, Subtarget, dl);
5355 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
5356 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
5357 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
5358 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
5359 DAG, Subtarget, dl);
5366 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
5367 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5368 SDValue V1 = Op.getOperand(0);
5369 SDValue V2 = Op.getOperand(1);
5370 EVT VT = Op.getValueType();
5371 DebugLoc dl = Op.getDebugLoc();
5372 unsigned NumElems = VT.getVectorNumElements();
5373 bool isMMX = VT.getSizeInBits() == 64;
5374 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
5375 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
5376 bool V1IsSplat = false;
5377 bool V2IsSplat = false;
5378 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
5379 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
5380 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
5381 MachineFunction &MF = DAG.getMachineFunction();
5382 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
5384 // Shuffle operations on MMX not supported.
5388 // Vector shuffle lowering takes 3 steps:
5390 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
5391 // narrowing and commutation of operands should be handled.
5392 // 2) Matching of shuffles with known shuffle masks to x86 target specific
5394 // 3) Rewriting of unmatched masks into new generic shuffle operations,
5395 // so the shuffle can be broken into other shuffles and the legalizer can
5396 // try the lowering again.
5398 // The general ideia is that no vector_shuffle operation should be left to
5399 // be matched during isel, all of them must be converted to a target specific
5402 // Normalize the input vectors. Here splats, zeroed vectors, profitable
5403 // narrowing and commutation of operands should be handled. The actual code
5404 // doesn't include all of those, work in progress...
5405 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
5406 if (NewOp.getNode())
5409 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
5410 // unpckh_undef). Only use pshufd if speed is more important than size.
5411 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
5412 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5413 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5414 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
5415 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5416 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5418 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
5419 RelaxedMayFoldVectorLoad(V1))
5420 return getMOVDDup(Op, dl, V1, DAG);
5422 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
5423 return getMOVHighToLow(Op, dl, DAG);
5425 // Use to match splats
5426 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
5427 (VT == MVT::v2f64 || VT == MVT::v2i64))
5428 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5430 if (X86::isPSHUFDMask(SVOp)) {
5431 // The actual implementation will match the mask in the if above and then
5432 // during isel it can match several different instructions, not only pshufd
5433 // as its name says, sad but true, emulate the behavior for now...
5434 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
5435 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
5437 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5439 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
5440 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
5442 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5443 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V1,
5446 if (VT == MVT::v4f32)
5447 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V1,
5451 // Check if this can be converted into a logical shift.
5452 bool isLeft = false;
5455 bool isShift = getSubtarget()->hasSSE2() &&
5456 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
5457 if (isShift && ShVal.hasOneUse()) {
5458 // If the shifted value has multiple uses, it may be cheaper to use
5459 // v_set0 + movlhps or movhlps, etc.
5460 EVT EltVT = VT.getVectorElementType();
5461 ShAmt *= EltVT.getSizeInBits();
5462 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5465 if (X86::isMOVLMask(SVOp)) {
5468 if (ISD::isBuildVectorAllZeros(V1.getNode()))
5469 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
5470 if (!X86::isMOVLPMask(SVOp)) {
5471 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
5472 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
5474 if (VT == MVT::v4i32 || VT == MVT::v4f32)
5475 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
5479 // FIXME: fold these into legal mask.
5480 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
5481 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
5483 if (X86::isMOVHLPSMask(SVOp))
5484 return getMOVHighToLow(Op, dl, DAG);
5486 if (X86::isMOVSHDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5487 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
5489 if (X86::isMOVSLDUPMask(SVOp) && HasSSE3 && V2IsUndef && NumElems == 4)
5490 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
5492 if (X86::isMOVLPMask(SVOp))
5493 return getMOVLP(Op, dl, DAG, HasSSE2);
5495 if (ShouldXformToMOVHLPS(SVOp) ||
5496 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
5497 return CommuteVectorShuffle(SVOp, DAG);
5500 // No better options. Use a vshl / vsrl.
5501 EVT EltVT = VT.getVectorElementType();
5502 ShAmt *= EltVT.getSizeInBits();
5503 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
5506 bool Commuted = false;
5507 // FIXME: This should also accept a bitcast of a splat? Be careful, not
5508 // 1,1,1,1 -> v8i16 though.
5509 V1IsSplat = isSplatVector(V1.getNode());
5510 V2IsSplat = isSplatVector(V2.getNode());
5512 // Canonicalize the splat or undef, if present, to be on the RHS.
5513 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
5514 Op = CommuteVectorShuffle(SVOp, DAG);
5515 SVOp = cast<ShuffleVectorSDNode>(Op);
5516 V1 = SVOp->getOperand(0);
5517 V2 = SVOp->getOperand(1);
5518 std::swap(V1IsSplat, V2IsSplat);
5519 std::swap(V1IsUndef, V2IsUndef);
5523 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
5524 // Shuffling low element of v1 into undef, just return v1.
5527 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
5528 // the instruction selector will not match, so get a canonical MOVL with
5529 // swapped operands to undo the commute.
5530 return getMOVL(DAG, dl, VT, V2, V1);
5533 if (X86::isUNPCKLMask(SVOp))
5534 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
5536 if (X86::isUNPCKHMask(SVOp))
5537 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
5540 // Normalize mask so all entries that point to V2 points to its first
5541 // element then try to match unpck{h|l} again. If match, return a
5542 // new vector_shuffle with the corrected mask.
5543 SDValue NewMask = NormalizeMask(SVOp, DAG);
5544 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
5545 if (NSVOp != SVOp) {
5546 if (X86::isUNPCKLMask(NSVOp, true)) {
5548 } else if (X86::isUNPCKHMask(NSVOp, true)) {
5555 // Commute is back and try unpck* again.
5556 // FIXME: this seems wrong.
5557 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
5558 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
5560 if (X86::isUNPCKLMask(NewSVOp))
5561 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
5563 if (X86::isUNPCKHMask(NewSVOp))
5564 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
5567 // Normalize the node to match x86 shuffle ops if needed
5568 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
5569 return CommuteVectorShuffle(SVOp, DAG);
5571 // The checks below are all present in isShuffleMaskLegal, but they are
5572 // inlined here right now to enable us to directly emit target specific
5573 // nodes, and remove one by one until they don't return Op anymore.
5574 SmallVector<int, 16> M;
5577 if (isPALIGNRMask(M, VT, HasSSSE3))
5578 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
5579 X86::getShufflePALIGNRImmediate(SVOp),
5582 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
5583 SVOp->getSplatIndex() == 0 && V2IsUndef) {
5584 if (VT == MVT::v2f64)
5585 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
5586 if (VT == MVT::v2i64)
5587 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
5590 if (isPSHUFHWMask(M, VT))
5591 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
5592 X86::getShufflePSHUFHWImmediate(SVOp),
5595 if (isPSHUFLWMask(M, VT))
5596 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
5597 X86::getShufflePSHUFLWImmediate(SVOp),
5600 if (isSHUFPMask(M, VT)) {
5601 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
5602 if (VT == MVT::v4f32 || VT == MVT::v4i32)
5603 return getTargetShuffleNode(X86ISD::SHUFPS, dl, VT, V1, V2,
5605 if (VT == MVT::v2f64 || VT == MVT::v2i64)
5606 return getTargetShuffleNode(X86ISD::SHUFPD, dl, VT, V1, V2,
5610 if (X86::isUNPCKL_v_undef_Mask(SVOp))
5611 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5612 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
5613 if (X86::isUNPCKH_v_undef_Mask(SVOp))
5614 if (VT != MVT::v2i64 && VT != MVT::v2f64)
5615 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
5617 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
5618 if (VT == MVT::v8i16) {
5619 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
5620 if (NewOp.getNode())
5624 if (VT == MVT::v16i8) {
5625 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
5626 if (NewOp.getNode())
5630 // Handle all 4 wide cases with a number of shuffles.
5632 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
5638 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
5639 SelectionDAG &DAG) const {
5640 EVT VT = Op.getValueType();
5641 DebugLoc dl = Op.getDebugLoc();
5642 if (VT.getSizeInBits() == 8) {
5643 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
5644 Op.getOperand(0), Op.getOperand(1));
5645 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5646 DAG.getValueType(VT));
5647 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5648 } else if (VT.getSizeInBits() == 16) {
5649 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5650 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
5652 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5653 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5654 DAG.getNode(ISD::BITCAST, dl,
5658 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
5659 Op.getOperand(0), Op.getOperand(1));
5660 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
5661 DAG.getValueType(VT));
5662 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5663 } else if (VT == MVT::f32) {
5664 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
5665 // the result back to FR32 register. It's only worth matching if the
5666 // result has a single use which is a store or a bitcast to i32. And in
5667 // the case of a store, it's not worth it if the index is a constant 0,
5668 // because a MOVSSmr can be used instead, which is smaller and faster.
5669 if (!Op.hasOneUse())
5671 SDNode *User = *Op.getNode()->use_begin();
5672 if ((User->getOpcode() != ISD::STORE ||
5673 (isa<ConstantSDNode>(Op.getOperand(1)) &&
5674 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
5675 (User->getOpcode() != ISD::BITCAST ||
5676 User->getValueType(0) != MVT::i32))
5678 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5679 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
5682 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
5683 } else if (VT == MVT::i32) {
5684 // ExtractPS works with constant index.
5685 if (isa<ConstantSDNode>(Op.getOperand(1)))
5693 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
5694 SelectionDAG &DAG) const {
5695 if (!isa<ConstantSDNode>(Op.getOperand(1)))
5698 if (Subtarget->hasSSE41()) {
5699 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
5704 EVT VT = Op.getValueType();
5705 DebugLoc dl = Op.getDebugLoc();
5706 // TODO: handle v16i8.
5707 if (VT.getSizeInBits() == 16) {
5708 SDValue Vec = Op.getOperand(0);
5709 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5711 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
5712 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
5713 DAG.getNode(ISD::BITCAST, dl,
5716 // Transform it so it match pextrw which produces a 32-bit result.
5717 EVT EltVT = MVT::i32;
5718 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
5719 Op.getOperand(0), Op.getOperand(1));
5720 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
5721 DAG.getValueType(VT));
5722 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
5723 } else if (VT.getSizeInBits() == 32) {
5724 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5728 // SHUFPS the element to the lowest double word, then movss.
5729 int Mask[4] = { Idx, -1, -1, -1 };
5730 EVT VVT = Op.getOperand(0).getValueType();
5731 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5732 DAG.getUNDEF(VVT), Mask);
5733 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5734 DAG.getIntPtrConstant(0));
5735 } else if (VT.getSizeInBits() == 64) {
5736 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
5737 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
5738 // to match extract_elt for f64.
5739 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
5743 // UNPCKHPD the element to the lowest double word, then movsd.
5744 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
5745 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
5746 int Mask[2] = { 1, -1 };
5747 EVT VVT = Op.getOperand(0).getValueType();
5748 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
5749 DAG.getUNDEF(VVT), Mask);
5750 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
5751 DAG.getIntPtrConstant(0));
5758 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
5759 SelectionDAG &DAG) const {
5760 EVT VT = Op.getValueType();
5761 EVT EltVT = VT.getVectorElementType();
5762 DebugLoc dl = Op.getDebugLoc();
5764 SDValue N0 = Op.getOperand(0);
5765 SDValue N1 = Op.getOperand(1);
5766 SDValue N2 = Op.getOperand(2);
5768 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
5769 isa<ConstantSDNode>(N2)) {
5771 if (VT == MVT::v8i16)
5772 Opc = X86ISD::PINSRW;
5773 else if (VT == MVT::v16i8)
5774 Opc = X86ISD::PINSRB;
5776 Opc = X86ISD::PINSRB;
5778 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
5780 if (N1.getValueType() != MVT::i32)
5781 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5782 if (N2.getValueType() != MVT::i32)
5783 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5784 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
5785 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
5786 // Bits [7:6] of the constant are the source select. This will always be
5787 // zero here. The DAG Combiner may combine an extract_elt index into these
5788 // bits. For example (insert (extract, 3), 2) could be matched by putting
5789 // the '3' into bits [7:6] of X86ISD::INSERTPS.
5790 // Bits [5:4] of the constant are the destination select. This is the
5791 // value of the incoming immediate.
5792 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
5793 // combine either bitwise AND or insert of float 0.0 to set these bits.
5794 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
5795 // Create this as a scalar to vector..
5796 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
5797 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
5798 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
5799 // PINSR* works with constant index.
5806 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
5807 EVT VT = Op.getValueType();
5808 EVT EltVT = VT.getVectorElementType();
5810 if (Subtarget->hasSSE41())
5811 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
5813 if (EltVT == MVT::i8)
5816 DebugLoc dl = Op.getDebugLoc();
5817 SDValue N0 = Op.getOperand(0);
5818 SDValue N1 = Op.getOperand(1);
5819 SDValue N2 = Op.getOperand(2);
5821 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
5822 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
5823 // as its second argument.
5824 if (N1.getValueType() != MVT::i32)
5825 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
5826 if (N2.getValueType() != MVT::i32)
5827 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
5828 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
5834 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5835 DebugLoc dl = Op.getDebugLoc();
5837 if (Op.getValueType() == MVT::v1i64 &&
5838 Op.getOperand(0).getValueType() == MVT::i64)
5839 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
5841 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
5842 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
5843 "Expected an SSE type!");
5844 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
5845 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
5848 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
5849 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
5850 // one of the above mentioned nodes. It has to be wrapped because otherwise
5851 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
5852 // be used to form addressing mode. These wrapped nodes will be selected
5855 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
5856 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
5858 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5860 unsigned char OpFlag = 0;
5861 unsigned WrapperKind = X86ISD::Wrapper;
5862 CodeModel::Model M = getTargetMachine().getCodeModel();
5864 if (Subtarget->isPICStyleRIPRel() &&
5865 (M == CodeModel::Small || M == CodeModel::Kernel))
5866 WrapperKind = X86ISD::WrapperRIP;
5867 else if (Subtarget->isPICStyleGOT())
5868 OpFlag = X86II::MO_GOTOFF;
5869 else if (Subtarget->isPICStyleStubPIC())
5870 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5872 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
5874 CP->getOffset(), OpFlag);
5875 DebugLoc DL = CP->getDebugLoc();
5876 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5877 // With PIC, the address is actually $g + Offset.
5879 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5880 DAG.getNode(X86ISD::GlobalBaseReg,
5881 DebugLoc(), getPointerTy()),
5888 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
5889 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
5891 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5893 unsigned char OpFlag = 0;
5894 unsigned WrapperKind = X86ISD::Wrapper;
5895 CodeModel::Model M = getTargetMachine().getCodeModel();
5897 if (Subtarget->isPICStyleRIPRel() &&
5898 (M == CodeModel::Small || M == CodeModel::Kernel))
5899 WrapperKind = X86ISD::WrapperRIP;
5900 else if (Subtarget->isPICStyleGOT())
5901 OpFlag = X86II::MO_GOTOFF;
5902 else if (Subtarget->isPICStyleStubPIC())
5903 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5905 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
5907 DebugLoc DL = JT->getDebugLoc();
5908 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5910 // With PIC, the address is actually $g + Offset.
5912 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5913 DAG.getNode(X86ISD::GlobalBaseReg,
5914 DebugLoc(), getPointerTy()),
5921 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
5922 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
5924 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
5926 unsigned char OpFlag = 0;
5927 unsigned WrapperKind = X86ISD::Wrapper;
5928 CodeModel::Model M = getTargetMachine().getCodeModel();
5930 if (Subtarget->isPICStyleRIPRel() &&
5931 (M == CodeModel::Small || M == CodeModel::Kernel))
5932 WrapperKind = X86ISD::WrapperRIP;
5933 else if (Subtarget->isPICStyleGOT())
5934 OpFlag = X86II::MO_GOTOFF;
5935 else if (Subtarget->isPICStyleStubPIC())
5936 OpFlag = X86II::MO_PIC_BASE_OFFSET;
5938 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
5940 DebugLoc DL = Op.getDebugLoc();
5941 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
5944 // With PIC, the address is actually $g + Offset.
5945 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
5946 !Subtarget->is64Bit()) {
5947 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
5948 DAG.getNode(X86ISD::GlobalBaseReg,
5949 DebugLoc(), getPointerTy()),
5957 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
5958 // Create the TargetBlockAddressAddress node.
5959 unsigned char OpFlags =
5960 Subtarget->ClassifyBlockAddressReference();
5961 CodeModel::Model M = getTargetMachine().getCodeModel();
5962 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
5963 DebugLoc dl = Op.getDebugLoc();
5964 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
5965 /*isTarget=*/true, OpFlags);
5967 if (Subtarget->isPICStyleRIPRel() &&
5968 (M == CodeModel::Small || M == CodeModel::Kernel))
5969 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
5971 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
5973 // With PIC, the address is actually $g + Offset.
5974 if (isGlobalRelativeToPICBase(OpFlags)) {
5975 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
5976 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
5984 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
5986 SelectionDAG &DAG) const {
5987 // Create the TargetGlobalAddress node, folding in the constant
5988 // offset if it is legal.
5989 unsigned char OpFlags =
5990 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
5991 CodeModel::Model M = getTargetMachine().getCodeModel();
5993 if (OpFlags == X86II::MO_NO_FLAG &&
5994 X86::isOffsetSuitableForCodeModel(Offset, M)) {
5995 // A direct static reference to a global.
5996 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
5999 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
6002 if (Subtarget->isPICStyleRIPRel() &&
6003 (M == CodeModel::Small || M == CodeModel::Kernel))
6004 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
6006 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
6008 // With PIC, the address is actually $g + Offset.
6009 if (isGlobalRelativeToPICBase(OpFlags)) {
6010 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6011 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
6015 // For globals that require a load from a stub to get the address, emit the
6017 if (isGlobalStubReference(OpFlags))
6018 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
6019 MachinePointerInfo::getGOT(), false, false, 0);
6021 // If there was a non-zero offset that we didn't fold, create an explicit
6024 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
6025 DAG.getConstant(Offset, getPointerTy()));
6031 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
6032 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
6033 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
6034 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
6038 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
6039 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
6040 unsigned char OperandFlags) {
6041 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6042 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6043 DebugLoc dl = GA->getDebugLoc();
6044 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6045 GA->getValueType(0),
6049 SDValue Ops[] = { Chain, TGA, *InFlag };
6050 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
6052 SDValue Ops[] = { Chain, TGA };
6053 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
6056 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
6057 MFI->setAdjustsStack(true);
6059 SDValue Flag = Chain.getValue(1);
6060 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
6063 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
6065 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6068 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
6069 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
6070 DAG.getNode(X86ISD::GlobalBaseReg,
6071 DebugLoc(), PtrVT), InFlag);
6072 InFlag = Chain.getValue(1);
6074 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
6077 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
6079 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6081 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
6082 X86::RAX, X86II::MO_TLSGD);
6085 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
6086 // "local exec" model.
6087 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
6088 const EVT PtrVT, TLSModel::Model model,
6090 DebugLoc dl = GA->getDebugLoc();
6092 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
6093 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
6094 is64Bit ? 257 : 256));
6096 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
6097 DAG.getIntPtrConstant(0),
6098 MachinePointerInfo(Ptr), false, false, 0);
6100 unsigned char OperandFlags = 0;
6101 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
6103 unsigned WrapperKind = X86ISD::Wrapper;
6104 if (model == TLSModel::LocalExec) {
6105 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
6106 } else if (is64Bit) {
6107 assert(model == TLSModel::InitialExec);
6108 OperandFlags = X86II::MO_GOTTPOFF;
6109 WrapperKind = X86ISD::WrapperRIP;
6111 assert(model == TLSModel::InitialExec);
6112 OperandFlags = X86II::MO_INDNTPOFF;
6115 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
6117 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
6118 GA->getValueType(0),
6119 GA->getOffset(), OperandFlags);
6120 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
6122 if (model == TLSModel::InitialExec)
6123 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
6124 MachinePointerInfo::getGOT(), false, false, 0);
6126 // The address of the thread local variable is the add of the thread
6127 // pointer with the offset of the variable.
6128 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
6132 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
6134 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
6135 const GlobalValue *GV = GA->getGlobal();
6137 if (Subtarget->isTargetELF()) {
6138 // TODO: implement the "local dynamic" model
6139 // TODO: implement the "initial exec"model for pic executables
6141 // If GV is an alias then use the aliasee for determining
6142 // thread-localness.
6143 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
6144 GV = GA->resolveAliasedGlobal(false);
6146 TLSModel::Model model
6147 = getTLSModel(GV, getTargetMachine().getRelocationModel());
6150 case TLSModel::GeneralDynamic:
6151 case TLSModel::LocalDynamic: // not implemented
6152 if (Subtarget->is64Bit())
6153 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
6154 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
6156 case TLSModel::InitialExec:
6157 case TLSModel::LocalExec:
6158 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
6159 Subtarget->is64Bit());
6161 } else if (Subtarget->isTargetDarwin()) {
6162 // Darwin only has one model of TLS. Lower to that.
6163 unsigned char OpFlag = 0;
6164 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
6165 X86ISD::WrapperRIP : X86ISD::Wrapper;
6167 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
6169 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
6170 !Subtarget->is64Bit();
6172 OpFlag = X86II::MO_TLVP_PIC_BASE;
6174 OpFlag = X86II::MO_TLVP;
6175 DebugLoc DL = Op.getDebugLoc();
6176 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
6177 GA->getValueType(0),
6178 GA->getOffset(), OpFlag);
6179 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
6181 // With PIC32, the address is actually $g + Offset.
6183 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
6184 DAG.getNode(X86ISD::GlobalBaseReg,
6185 DebugLoc(), getPointerTy()),
6188 // Lowering the machine isd will make sure everything is in the right
6190 SDValue Chain = DAG.getEntryNode();
6191 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6192 SDValue Args[] = { Chain, Offset };
6193 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
6195 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
6196 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6197 MFI->setAdjustsStack(true);
6199 // And our return value (tls address) is in the standard call return value
6201 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
6202 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
6206 "TLS not implemented for this target.");
6208 llvm_unreachable("Unreachable");
6213 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
6214 /// take a 2 x i32 value to shift plus a shift amount.
6215 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
6216 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
6217 EVT VT = Op.getValueType();
6218 unsigned VTBits = VT.getSizeInBits();
6219 DebugLoc dl = Op.getDebugLoc();
6220 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
6221 SDValue ShOpLo = Op.getOperand(0);
6222 SDValue ShOpHi = Op.getOperand(1);
6223 SDValue ShAmt = Op.getOperand(2);
6224 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
6225 DAG.getConstant(VTBits - 1, MVT::i8))
6226 : DAG.getConstant(0, VT);
6229 if (Op.getOpcode() == ISD::SHL_PARTS) {
6230 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
6231 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
6233 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
6234 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
6237 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
6238 DAG.getConstant(VTBits, MVT::i8));
6239 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
6240 AndNode, DAG.getConstant(0, MVT::i8));
6243 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
6244 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
6245 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
6247 if (Op.getOpcode() == ISD::SHL_PARTS) {
6248 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6249 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6251 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
6252 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
6255 SDValue Ops[2] = { Lo, Hi };
6256 return DAG.getMergeValues(Ops, 2, dl);
6259 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
6260 SelectionDAG &DAG) const {
6261 EVT SrcVT = Op.getOperand(0).getValueType();
6263 if (SrcVT.isVector())
6266 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
6267 "Unknown SINT_TO_FP to lower!");
6269 // These are really Legal; return the operand so the caller accepts it as
6271 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
6273 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
6274 Subtarget->is64Bit()) {
6278 DebugLoc dl = Op.getDebugLoc();
6279 unsigned Size = SrcVT.getSizeInBits()/8;
6280 MachineFunction &MF = DAG.getMachineFunction();
6281 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
6282 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6283 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6285 MachinePointerInfo::getFixedStack(SSFI),
6287 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
6290 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
6292 SelectionDAG &DAG) const {
6294 DebugLoc DL = Op.getDebugLoc();
6296 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
6298 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
6300 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
6302 unsigned ByteSize = SrcVT.getSizeInBits()/8;
6304 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6305 MachineMemOperand *MMO =
6306 DAG.getMachineFunction()
6307 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6308 MachineMemOperand::MOLoad, ByteSize, ByteSize);
6310 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
6311 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
6313 Tys, Ops, array_lengthof(Ops),
6317 Chain = Result.getValue(1);
6318 SDValue InFlag = Result.getValue(2);
6320 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
6321 // shouldn't be necessary except that RFP cannot be live across
6322 // multiple blocks. When stackifier is fixed, they can be uncoupled.
6323 MachineFunction &MF = DAG.getMachineFunction();
6324 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
6325 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
6326 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6327 Tys = DAG.getVTList(MVT::Other);
6329 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
6331 MachineMemOperand *MMO =
6332 DAG.getMachineFunction()
6333 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6334 MachineMemOperand::MOStore, SSFISize, SSFISize);
6336 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
6337 Ops, array_lengthof(Ops),
6338 Op.getValueType(), MMO);
6339 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
6340 MachinePointerInfo::getFixedStack(SSFI),
6347 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
6348 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
6349 SelectionDAG &DAG) const {
6350 // This algorithm is not obvious. Here it is in C code, more or less:
6352 double uint64_to_double( uint32_t hi, uint32_t lo ) {
6353 static const __m128i exp = { 0x4330000045300000ULL, 0 };
6354 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
6356 // Copy ints to xmm registers.
6357 __m128i xh = _mm_cvtsi32_si128( hi );
6358 __m128i xl = _mm_cvtsi32_si128( lo );
6360 // Combine into low half of a single xmm register.
6361 __m128i x = _mm_unpacklo_epi32( xh, xl );
6365 // Merge in appropriate exponents to give the integer bits the right
6367 x = _mm_unpacklo_epi32( x, exp );
6369 // Subtract away the biases to deal with the IEEE-754 double precision
6371 d = _mm_sub_pd( (__m128d) x, bias );
6373 // All conversions up to here are exact. The correctly rounded result is
6374 // calculated using the current rounding mode using the following
6376 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
6377 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
6378 // store doesn't really need to be here (except
6379 // maybe to zero the other double)
6384 DebugLoc dl = Op.getDebugLoc();
6385 LLVMContext *Context = DAG.getContext();
6387 // Build some magic constants.
6388 std::vector<Constant*> CV0;
6389 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
6390 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
6391 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6392 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
6393 Constant *C0 = ConstantVector::get(CV0);
6394 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
6396 std::vector<Constant*> CV1;
6398 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
6400 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
6401 Constant *C1 = ConstantVector::get(CV1);
6402 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
6404 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6405 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6407 DAG.getIntPtrConstant(1)));
6408 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6409 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6411 DAG.getIntPtrConstant(0)));
6412 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
6413 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
6414 MachinePointerInfo::getConstantPool(),
6416 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
6417 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
6418 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
6419 MachinePointerInfo::getConstantPool(),
6421 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
6423 // Add the halves; easiest way is to swap them into another reg first.
6424 int ShufMask[2] = { 1, -1 };
6425 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
6426 DAG.getUNDEF(MVT::v2f64), ShufMask);
6427 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
6428 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
6429 DAG.getIntPtrConstant(0));
6432 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
6433 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
6434 SelectionDAG &DAG) const {
6435 DebugLoc dl = Op.getDebugLoc();
6436 // FP constant to bias correct the final result.
6437 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
6440 // Load the 32-bit value into an XMM register.
6441 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
6442 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6444 DAG.getIntPtrConstant(0)));
6446 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6447 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
6448 DAG.getIntPtrConstant(0));
6450 // Or the load with the bias.
6451 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
6452 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6453 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6455 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6456 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6457 MVT::v2f64, Bias)));
6458 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6459 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
6460 DAG.getIntPtrConstant(0));
6462 // Subtract the bias.
6463 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
6465 // Handle final rounding.
6466 EVT DestVT = Op.getValueType();
6468 if (DestVT.bitsLT(MVT::f64)) {
6469 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6470 DAG.getIntPtrConstant(0));
6471 } else if (DestVT.bitsGT(MVT::f64)) {
6472 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6475 // Handle final rounding.
6479 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
6480 SelectionDAG &DAG) const {
6481 SDValue N0 = Op.getOperand(0);
6482 DebugLoc dl = Op.getDebugLoc();
6484 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
6485 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
6486 // the optimization here.
6487 if (DAG.SignBitIsZero(N0))
6488 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
6490 EVT SrcVT = N0.getValueType();
6491 EVT DstVT = Op.getValueType();
6492 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
6493 return LowerUINT_TO_FP_i64(Op, DAG);
6494 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
6495 return LowerUINT_TO_FP_i32(Op, DAG);
6497 // Make a 64-bit buffer, and use it to build an FILD.
6498 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
6499 if (SrcVT == MVT::i32) {
6500 SDValue WordOff = DAG.getConstant(4, getPointerTy());
6501 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
6502 getPointerTy(), StackSlot, WordOff);
6503 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6504 StackSlot, MachinePointerInfo(),
6506 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
6507 OffsetSlot, MachinePointerInfo(),
6509 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
6513 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
6514 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
6515 StackSlot, MachinePointerInfo(),
6517 // For i64 source, we need to add the appropriate power of 2 if the input
6518 // was negative. This is the same as the optimization in
6519 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
6520 // we must be careful to do the computation in x87 extended precision, not
6521 // in SSE. (The generic code can't know it's OK to do this, or how to.)
6522 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
6523 MachineMemOperand *MMO =
6524 DAG.getMachineFunction()
6525 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6526 MachineMemOperand::MOLoad, 8, 8);
6528 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
6529 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
6530 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
6533 APInt FF(32, 0x5F800000ULL);
6535 // Check whether the sign bit is set.
6536 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
6537 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
6540 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
6541 SDValue FudgePtr = DAG.getConstantPool(
6542 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
6545 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
6546 SDValue Zero = DAG.getIntPtrConstant(0);
6547 SDValue Four = DAG.getIntPtrConstant(4);
6548 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
6550 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
6552 // Load the value out, extending it from f32 to f80.
6553 // FIXME: Avoid the extend by constructing the right constant pool?
6554 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, dl, DAG.getEntryNode(),
6555 FudgePtr, MachinePointerInfo::getConstantPool(),
6556 MVT::f32, false, false, 4);
6557 // Extend everything to 80 bits to force it to be done on x87.
6558 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
6559 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
6562 std::pair<SDValue,SDValue> X86TargetLowering::
6563 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
6564 DebugLoc DL = Op.getDebugLoc();
6566 EVT DstTy = Op.getValueType();
6569 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
6573 assert(DstTy.getSimpleVT() <= MVT::i64 &&
6574 DstTy.getSimpleVT() >= MVT::i16 &&
6575 "Unknown FP_TO_SINT to lower!");
6577 // These are really Legal.
6578 if (DstTy == MVT::i32 &&
6579 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6580 return std::make_pair(SDValue(), SDValue());
6581 if (Subtarget->is64Bit() &&
6582 DstTy == MVT::i64 &&
6583 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
6584 return std::make_pair(SDValue(), SDValue());
6586 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
6588 MachineFunction &MF = DAG.getMachineFunction();
6589 unsigned MemSize = DstTy.getSizeInBits()/8;
6590 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6591 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6596 switch (DstTy.getSimpleVT().SimpleTy) {
6597 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
6598 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
6599 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
6600 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
6603 SDValue Chain = DAG.getEntryNode();
6604 SDValue Value = Op.getOperand(0);
6605 EVT TheVT = Op.getOperand(0).getValueType();
6606 if (isScalarFPTypeInSSEReg(TheVT)) {
6607 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
6608 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
6609 MachinePointerInfo::getFixedStack(SSFI),
6611 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
6613 Chain, StackSlot, DAG.getValueType(TheVT)
6616 MachineMemOperand *MMO =
6617 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6618 MachineMemOperand::MOLoad, MemSize, MemSize);
6619 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
6621 Chain = Value.getValue(1);
6622 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
6623 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6626 MachineMemOperand *MMO =
6627 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
6628 MachineMemOperand::MOStore, MemSize, MemSize);
6630 // Build the FP_TO_INT*_IN_MEM
6631 SDValue Ops[] = { Chain, Value, StackSlot };
6632 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
6633 Ops, 3, DstTy, MMO);
6635 return std::make_pair(FIST, StackSlot);
6638 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
6639 SelectionDAG &DAG) const {
6640 if (Op.getValueType().isVector())
6643 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
6644 SDValue FIST = Vals.first, StackSlot = Vals.second;
6645 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
6646 if (FIST.getNode() == 0) return Op;
6649 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6650 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6653 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
6654 SelectionDAG &DAG) const {
6655 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
6656 SDValue FIST = Vals.first, StackSlot = Vals.second;
6657 assert(FIST.getNode() && "Unexpected failure");
6660 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
6661 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
6664 SDValue X86TargetLowering::LowerFABS(SDValue Op,
6665 SelectionDAG &DAG) const {
6666 LLVMContext *Context = DAG.getContext();
6667 DebugLoc dl = Op.getDebugLoc();
6668 EVT VT = Op.getValueType();
6671 EltVT = VT.getVectorElementType();
6672 std::vector<Constant*> CV;
6673 if (EltVT == MVT::f64) {
6674 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
6678 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
6684 Constant *C = ConstantVector::get(CV);
6685 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6686 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6687 MachinePointerInfo::getConstantPool(),
6689 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
6692 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
6693 LLVMContext *Context = DAG.getContext();
6694 DebugLoc dl = Op.getDebugLoc();
6695 EVT VT = Op.getValueType();
6698 EltVT = VT.getVectorElementType();
6699 std::vector<Constant*> CV;
6700 if (EltVT == MVT::f64) {
6701 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
6705 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
6711 Constant *C = ConstantVector::get(CV);
6712 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6713 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6714 MachinePointerInfo::getConstantPool(),
6716 if (VT.isVector()) {
6717 return DAG.getNode(ISD::BITCAST, dl, VT,
6718 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
6719 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
6721 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
6723 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
6727 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
6728 LLVMContext *Context = DAG.getContext();
6729 SDValue Op0 = Op.getOperand(0);
6730 SDValue Op1 = Op.getOperand(1);
6731 DebugLoc dl = Op.getDebugLoc();
6732 EVT VT = Op.getValueType();
6733 EVT SrcVT = Op1.getValueType();
6735 // If second operand is smaller, extend it first.
6736 if (SrcVT.bitsLT(VT)) {
6737 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
6740 // And if it is bigger, shrink it first.
6741 if (SrcVT.bitsGT(VT)) {
6742 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
6746 // At this point the operands and the result should have the same
6747 // type, and that won't be f80 since that is not custom lowered.
6749 // First get the sign bit of second operand.
6750 std::vector<Constant*> CV;
6751 if (SrcVT == MVT::f64) {
6752 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
6753 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6755 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
6756 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6757 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6758 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6760 Constant *C = ConstantVector::get(CV);
6761 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6762 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
6763 MachinePointerInfo::getConstantPool(),
6765 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
6767 // Shift sign bit right or left if the two operands have different types.
6768 if (SrcVT.bitsGT(VT)) {
6769 // Op0 is MVT::f32, Op1 is MVT::f64.
6770 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
6771 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
6772 DAG.getConstant(32, MVT::i32));
6773 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
6774 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
6775 DAG.getIntPtrConstant(0));
6778 // Clear first operand sign bit.
6780 if (VT == MVT::f64) {
6781 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
6782 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
6784 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
6785 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6786 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6787 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
6789 C = ConstantVector::get(CV);
6790 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
6791 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
6792 MachinePointerInfo::getConstantPool(),
6794 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
6796 // Or the value with the sign bit.
6797 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
6800 /// Emit nodes that will be selected as "test Op0,Op0", or something
6802 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
6803 SelectionDAG &DAG) const {
6804 DebugLoc dl = Op.getDebugLoc();
6806 // CF and OF aren't always set the way we want. Determine which
6807 // of these we need.
6808 bool NeedCF = false;
6809 bool NeedOF = false;
6812 case X86::COND_A: case X86::COND_AE:
6813 case X86::COND_B: case X86::COND_BE:
6816 case X86::COND_G: case X86::COND_GE:
6817 case X86::COND_L: case X86::COND_LE:
6818 case X86::COND_O: case X86::COND_NO:
6823 // See if we can use the EFLAGS value from the operand instead of
6824 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
6825 // we prove that the arithmetic won't overflow, we can't use OF or CF.
6826 if (Op.getResNo() != 0 || NeedOF || NeedCF)
6827 // Emit a CMP with 0, which is the TEST pattern.
6828 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6829 DAG.getConstant(0, Op.getValueType()));
6831 unsigned Opcode = 0;
6832 unsigned NumOperands = 0;
6833 switch (Op.getNode()->getOpcode()) {
6835 // Due to an isel shortcoming, be conservative if this add is likely to be
6836 // selected as part of a load-modify-store instruction. When the root node
6837 // in a match is a store, isel doesn't know how to remap non-chain non-flag
6838 // uses of other nodes in the match, such as the ADD in this case. This
6839 // leads to the ADD being left around and reselected, with the result being
6840 // two adds in the output. Alas, even if none our users are stores, that
6841 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
6842 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
6843 // climbing the DAG back to the root, and it doesn't seem to be worth the
6845 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6846 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6847 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
6850 if (ConstantSDNode *C =
6851 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
6852 // An add of one will be selected as an INC.
6853 if (C->getAPIntValue() == 1) {
6854 Opcode = X86ISD::INC;
6859 // An add of negative one (subtract of one) will be selected as a DEC.
6860 if (C->getAPIntValue().isAllOnesValue()) {
6861 Opcode = X86ISD::DEC;
6867 // Otherwise use a regular EFLAGS-setting add.
6868 Opcode = X86ISD::ADD;
6872 // If the primary and result isn't used, don't bother using X86ISD::AND,
6873 // because a TEST instruction will be better.
6874 bool NonFlagUse = false;
6875 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6876 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
6878 unsigned UOpNo = UI.getOperandNo();
6879 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
6880 // Look pass truncate.
6881 UOpNo = User->use_begin().getOperandNo();
6882 User = *User->use_begin();
6885 if (User->getOpcode() != ISD::BRCOND &&
6886 User->getOpcode() != ISD::SETCC &&
6887 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
6900 // Due to the ISEL shortcoming noted above, be conservative if this op is
6901 // likely to be selected as part of a load-modify-store instruction.
6902 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
6903 UE = Op.getNode()->use_end(); UI != UE; ++UI)
6904 if (UI->getOpcode() == ISD::STORE)
6907 // Otherwise use a regular EFLAGS-setting instruction.
6908 switch (Op.getNode()->getOpcode()) {
6909 default: llvm_unreachable("unexpected operator!");
6910 case ISD::SUB: Opcode = X86ISD::SUB; break;
6911 case ISD::OR: Opcode = X86ISD::OR; break;
6912 case ISD::XOR: Opcode = X86ISD::XOR; break;
6913 case ISD::AND: Opcode = X86ISD::AND; break;
6925 return SDValue(Op.getNode(), 1);
6932 // Emit a CMP with 0, which is the TEST pattern.
6933 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
6934 DAG.getConstant(0, Op.getValueType()));
6936 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
6937 SmallVector<SDValue, 4> Ops;
6938 for (unsigned i = 0; i != NumOperands; ++i)
6939 Ops.push_back(Op.getOperand(i));
6941 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
6942 DAG.ReplaceAllUsesWith(Op, New);
6943 return SDValue(New.getNode(), 1);
6946 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
6948 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
6949 SelectionDAG &DAG) const {
6950 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
6951 if (C->getAPIntValue() == 0)
6952 return EmitTest(Op0, X86CC, DAG);
6954 DebugLoc dl = Op0.getDebugLoc();
6955 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
6958 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
6959 /// if it's possible.
6960 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
6961 DebugLoc dl, SelectionDAG &DAG) const {
6962 SDValue Op0 = And.getOperand(0);
6963 SDValue Op1 = And.getOperand(1);
6964 if (Op0.getOpcode() == ISD::TRUNCATE)
6965 Op0 = Op0.getOperand(0);
6966 if (Op1.getOpcode() == ISD::TRUNCATE)
6967 Op1 = Op1.getOperand(0);
6970 if (Op1.getOpcode() == ISD::SHL)
6971 std::swap(Op0, Op1);
6972 if (Op0.getOpcode() == ISD::SHL) {
6973 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
6974 if (And00C->getZExtValue() == 1) {
6975 // If we looked past a truncate, check that it's only truncating away
6977 unsigned BitWidth = Op0.getValueSizeInBits();
6978 unsigned AndBitWidth = And.getValueSizeInBits();
6979 if (BitWidth > AndBitWidth) {
6980 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
6981 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
6982 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
6986 RHS = Op0.getOperand(1);
6988 } else if (Op1.getOpcode() == ISD::Constant) {
6989 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
6990 SDValue AndLHS = Op0;
6991 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
6992 LHS = AndLHS.getOperand(0);
6993 RHS = AndLHS.getOperand(1);
6997 if (LHS.getNode()) {
6998 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
6999 // instruction. Since the shift amount is in-range-or-undefined, we know
7000 // that doing a bittest on the i32 value is ok. We extend to i32 because
7001 // the encoding for the i16 version is larger than the i32 version.
7002 // Also promote i16 to i32 for performance / code size reason.
7003 if (LHS.getValueType() == MVT::i8 ||
7004 LHS.getValueType() == MVT::i16)
7005 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
7007 // If the operand types disagree, extend the shift amount to match. Since
7008 // BT ignores high bits (like shifts) we can use anyextend.
7009 if (LHS.getValueType() != RHS.getValueType())
7010 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
7012 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
7013 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
7014 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7015 DAG.getConstant(Cond, MVT::i8), BT);
7021 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
7022 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
7023 SDValue Op0 = Op.getOperand(0);
7024 SDValue Op1 = Op.getOperand(1);
7025 DebugLoc dl = Op.getDebugLoc();
7026 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
7028 // Optimize to BT if possible.
7029 // Lower (X & (1 << N)) == 0 to BT(X, N).
7030 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
7031 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
7032 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
7033 Op1.getOpcode() == ISD::Constant &&
7034 cast<ConstantSDNode>(Op1)->isNullValue() &&
7035 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7036 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
7037 if (NewSetCC.getNode())
7041 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
7043 if (Op1.getOpcode() == ISD::Constant &&
7044 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
7045 cast<ConstantSDNode>(Op1)->isNullValue()) &&
7046 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
7048 // If the input is a setcc, then reuse the input setcc or use a new one with
7049 // the inverted condition.
7050 if (Op0.getOpcode() == X86ISD::SETCC) {
7051 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
7052 bool Invert = (CC == ISD::SETNE) ^
7053 cast<ConstantSDNode>(Op1)->isNullValue();
7054 if (!Invert) return Op0;
7056 CCode = X86::GetOppositeBranchCondition(CCode);
7057 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7058 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
7062 bool isFP = Op1.getValueType().isFloatingPoint();
7063 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
7064 if (X86CC == X86::COND_INVALID)
7067 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
7068 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7069 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
7072 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
7074 SDValue Op0 = Op.getOperand(0);
7075 SDValue Op1 = Op.getOperand(1);
7076 SDValue CC = Op.getOperand(2);
7077 EVT VT = Op.getValueType();
7078 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
7079 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
7080 DebugLoc dl = Op.getDebugLoc();
7084 EVT VT0 = Op0.getValueType();
7085 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
7086 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
7089 switch (SetCCOpcode) {
7092 case ISD::SETEQ: SSECC = 0; break;
7094 case ISD::SETGT: Swap = true; // Fallthrough
7096 case ISD::SETOLT: SSECC = 1; break;
7098 case ISD::SETGE: Swap = true; // Fallthrough
7100 case ISD::SETOLE: SSECC = 2; break;
7101 case ISD::SETUO: SSECC = 3; break;
7103 case ISD::SETNE: SSECC = 4; break;
7104 case ISD::SETULE: Swap = true;
7105 case ISD::SETUGE: SSECC = 5; break;
7106 case ISD::SETULT: Swap = true;
7107 case ISD::SETUGT: SSECC = 6; break;
7108 case ISD::SETO: SSECC = 7; break;
7111 std::swap(Op0, Op1);
7113 // In the two special cases we can't handle, emit two comparisons.
7115 if (SetCCOpcode == ISD::SETUEQ) {
7117 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
7118 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
7119 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
7121 else if (SetCCOpcode == ISD::SETONE) {
7123 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
7124 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
7125 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
7127 llvm_unreachable("Illegal FP comparison");
7129 // Handle all other FP comparisons here.
7130 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
7133 // We are handling one of the integer comparisons here. Since SSE only has
7134 // GT and EQ comparisons for integer, swapping operands and multiple
7135 // operations may be required for some comparisons.
7136 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
7137 bool Swap = false, Invert = false, FlipSigns = false;
7139 switch (VT.getSimpleVT().SimpleTy) {
7141 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
7142 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
7143 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
7144 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
7147 switch (SetCCOpcode) {
7149 case ISD::SETNE: Invert = true;
7150 case ISD::SETEQ: Opc = EQOpc; break;
7151 case ISD::SETLT: Swap = true;
7152 case ISD::SETGT: Opc = GTOpc; break;
7153 case ISD::SETGE: Swap = true;
7154 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
7155 case ISD::SETULT: Swap = true;
7156 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
7157 case ISD::SETUGE: Swap = true;
7158 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
7161 std::swap(Op0, Op1);
7163 // Since SSE has no unsigned integer comparisons, we need to flip the sign
7164 // bits of the inputs before performing those operations.
7166 EVT EltVT = VT.getVectorElementType();
7167 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
7169 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
7170 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
7172 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
7173 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
7176 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
7178 // If the logical-not of the result is required, perform that now.
7180 Result = DAG.getNOT(dl, Result, VT);
7185 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
7186 static bool isX86LogicalCmp(SDValue Op) {
7187 unsigned Opc = Op.getNode()->getOpcode();
7188 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
7190 if (Op.getResNo() == 1 &&
7191 (Opc == X86ISD::ADD ||
7192 Opc == X86ISD::SUB ||
7193 Opc == X86ISD::ADC ||
7194 Opc == X86ISD::SBB ||
7195 Opc == X86ISD::SMUL ||
7196 Opc == X86ISD::UMUL ||
7197 Opc == X86ISD::INC ||
7198 Opc == X86ISD::DEC ||
7199 Opc == X86ISD::OR ||
7200 Opc == X86ISD::XOR ||
7201 Opc == X86ISD::AND))
7204 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
7210 static bool isZero(SDValue V) {
7211 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7212 return C && C->isNullValue();
7215 static bool isAllOnes(SDValue V) {
7216 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
7217 return C && C->isAllOnesValue();
7220 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
7221 bool addTest = true;
7222 SDValue Cond = Op.getOperand(0);
7223 SDValue Op1 = Op.getOperand(1);
7224 SDValue Op2 = Op.getOperand(2);
7225 DebugLoc DL = Op.getDebugLoc();
7228 if (Cond.getOpcode() == ISD::SETCC) {
7229 SDValue NewCond = LowerSETCC(Cond, DAG);
7230 if (NewCond.getNode())
7234 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
7235 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
7236 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
7237 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
7238 if (Cond.getOpcode() == X86ISD::SETCC &&
7239 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
7240 isZero(Cond.getOperand(1).getOperand(1))) {
7241 SDValue Cmp = Cond.getOperand(1);
7243 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
7245 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
7246 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
7247 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
7249 SDValue CmpOp0 = Cmp.getOperand(0);
7250 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
7251 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
7253 SDValue Res = // Res = 0 or -1.
7254 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7255 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
7257 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
7258 Res = DAG.getNOT(DL, Res, Res.getValueType());
7260 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
7261 if (N2C == 0 || !N2C->isNullValue())
7262 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
7267 // Look past (and (setcc_carry (cmp ...)), 1).
7268 if (Cond.getOpcode() == ISD::AND &&
7269 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7270 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7271 if (C && C->getAPIntValue() == 1)
7272 Cond = Cond.getOperand(0);
7275 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7276 // setting operand in place of the X86ISD::SETCC.
7277 if (Cond.getOpcode() == X86ISD::SETCC ||
7278 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7279 CC = Cond.getOperand(0);
7281 SDValue Cmp = Cond.getOperand(1);
7282 unsigned Opc = Cmp.getOpcode();
7283 EVT VT = Op.getValueType();
7285 bool IllegalFPCMov = false;
7286 if (VT.isFloatingPoint() && !VT.isVector() &&
7287 !isScalarFPTypeInSSEReg(VT)) // FPStack?
7288 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
7290 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
7291 Opc == X86ISD::BT) { // FIXME
7298 // Look pass the truncate.
7299 if (Cond.getOpcode() == ISD::TRUNCATE)
7300 Cond = Cond.getOperand(0);
7302 // We know the result of AND is compared against zero. Try to match
7304 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7305 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
7306 if (NewSetCC.getNode()) {
7307 CC = NewSetCC.getOperand(0);
7308 Cond = NewSetCC.getOperand(1);
7315 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7316 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7319 // a < b ? -1 : 0 -> RES = ~setcc_carry
7320 // a < b ? 0 : -1 -> RES = setcc_carry
7321 // a >= b ? -1 : 0 -> RES = setcc_carry
7322 // a >= b ? 0 : -1 -> RES = ~setcc_carry
7323 if (Cond.getOpcode() == X86ISD::CMP) {
7324 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
7326 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
7327 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
7328 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
7329 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
7330 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
7331 return DAG.getNOT(DL, Res, Res.getValueType());
7336 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
7337 // condition is true.
7338 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
7339 SDValue Ops[] = { Op2, Op1, CC, Cond };
7340 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
7343 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
7344 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
7345 // from the AND / OR.
7346 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
7347 Opc = Op.getOpcode();
7348 if (Opc != ISD::OR && Opc != ISD::AND)
7350 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7351 Op.getOperand(0).hasOneUse() &&
7352 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
7353 Op.getOperand(1).hasOneUse());
7356 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
7357 // 1 and that the SETCC node has a single use.
7358 static bool isXor1OfSetCC(SDValue Op) {
7359 if (Op.getOpcode() != ISD::XOR)
7361 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7362 if (N1C && N1C->getAPIntValue() == 1) {
7363 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
7364 Op.getOperand(0).hasOneUse();
7369 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
7370 bool addTest = true;
7371 SDValue Chain = Op.getOperand(0);
7372 SDValue Cond = Op.getOperand(1);
7373 SDValue Dest = Op.getOperand(2);
7374 DebugLoc dl = Op.getDebugLoc();
7377 if (Cond.getOpcode() == ISD::SETCC) {
7378 SDValue NewCond = LowerSETCC(Cond, DAG);
7379 if (NewCond.getNode())
7383 // FIXME: LowerXALUO doesn't handle these!!
7384 else if (Cond.getOpcode() == X86ISD::ADD ||
7385 Cond.getOpcode() == X86ISD::SUB ||
7386 Cond.getOpcode() == X86ISD::SMUL ||
7387 Cond.getOpcode() == X86ISD::UMUL)
7388 Cond = LowerXALUO(Cond, DAG);
7391 // Look pass (and (setcc_carry (cmp ...)), 1).
7392 if (Cond.getOpcode() == ISD::AND &&
7393 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
7394 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
7395 if (C && C->getAPIntValue() == 1)
7396 Cond = Cond.getOperand(0);
7399 // If condition flag is set by a X86ISD::CMP, then use it as the condition
7400 // setting operand in place of the X86ISD::SETCC.
7401 if (Cond.getOpcode() == X86ISD::SETCC ||
7402 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
7403 CC = Cond.getOperand(0);
7405 SDValue Cmp = Cond.getOperand(1);
7406 unsigned Opc = Cmp.getOpcode();
7407 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
7408 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
7412 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
7416 // These can only come from an arithmetic instruction with overflow,
7417 // e.g. SADDO, UADDO.
7418 Cond = Cond.getNode()->getOperand(1);
7425 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
7426 SDValue Cmp = Cond.getOperand(0).getOperand(1);
7427 if (CondOpc == ISD::OR) {
7428 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
7429 // two branches instead of an explicit OR instruction with a
7431 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7432 isX86LogicalCmp(Cmp)) {
7433 CC = Cond.getOperand(0).getOperand(0);
7434 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7435 Chain, Dest, CC, Cmp);
7436 CC = Cond.getOperand(1).getOperand(0);
7440 } else { // ISD::AND
7441 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
7442 // two branches instead of an explicit AND instruction with a
7443 // separate test. However, we only do this if this block doesn't
7444 // have a fall-through edge, because this requires an explicit
7445 // jmp when the condition is false.
7446 if (Cmp == Cond.getOperand(1).getOperand(1) &&
7447 isX86LogicalCmp(Cmp) &&
7448 Op.getNode()->hasOneUse()) {
7449 X86::CondCode CCode =
7450 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7451 CCode = X86::GetOppositeBranchCondition(CCode);
7452 CC = DAG.getConstant(CCode, MVT::i8);
7453 SDNode *User = *Op.getNode()->use_begin();
7454 // Look for an unconditional branch following this conditional branch.
7455 // We need this because we need to reverse the successors in order
7456 // to implement FCMP_OEQ.
7457 if (User->getOpcode() == ISD::BR) {
7458 SDValue FalseBB = User->getOperand(1);
7460 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
7461 assert(NewBR == User);
7465 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7466 Chain, Dest, CC, Cmp);
7467 X86::CondCode CCode =
7468 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
7469 CCode = X86::GetOppositeBranchCondition(CCode);
7470 CC = DAG.getConstant(CCode, MVT::i8);
7476 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
7477 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
7478 // It should be transformed during dag combiner except when the condition
7479 // is set by a arithmetics with overflow node.
7480 X86::CondCode CCode =
7481 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
7482 CCode = X86::GetOppositeBranchCondition(CCode);
7483 CC = DAG.getConstant(CCode, MVT::i8);
7484 Cond = Cond.getOperand(0).getOperand(1);
7490 // Look pass the truncate.
7491 if (Cond.getOpcode() == ISD::TRUNCATE)
7492 Cond = Cond.getOperand(0);
7494 // We know the result of AND is compared against zero. Try to match
7496 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
7497 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
7498 if (NewSetCC.getNode()) {
7499 CC = NewSetCC.getOperand(0);
7500 Cond = NewSetCC.getOperand(1);
7507 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7508 Cond = EmitTest(Cond, X86::COND_NE, DAG);
7510 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
7511 Chain, Dest, CC, Cond);
7515 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
7516 // Calls to _alloca is needed to probe the stack when allocating more than 4k
7517 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
7518 // that the guard pages used by the OS virtual memory manager are allocated in
7519 // correct sequence.
7521 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
7522 SelectionDAG &DAG) const {
7523 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) &&
7524 "This should be used only on Windows targets");
7525 DebugLoc dl = Op.getDebugLoc();
7528 SDValue Chain = Op.getOperand(0);
7529 SDValue Size = Op.getOperand(1);
7530 // FIXME: Ensure alignment here
7534 EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
7536 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
7537 Flag = Chain.getValue(1);
7539 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7541 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
7542 Flag = Chain.getValue(1);
7544 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
7546 SDValue Ops1[2] = { Chain.getValue(0), Chain };
7547 return DAG.getMergeValues(Ops1, 2, dl);
7550 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
7551 MachineFunction &MF = DAG.getMachineFunction();
7552 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
7554 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7555 DebugLoc DL = Op.getDebugLoc();
7557 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
7558 // vastart just stores the address of the VarArgsFrameIndex slot into the
7559 // memory location argument.
7560 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7562 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
7563 MachinePointerInfo(SV), false, false, 0);
7567 // gp_offset (0 - 6 * 8)
7568 // fp_offset (48 - 48 + 8 * 16)
7569 // overflow_arg_area (point to parameters coming in memory).
7571 SmallVector<SDValue, 8> MemOps;
7572 SDValue FIN = Op.getOperand(1);
7574 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
7575 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
7577 FIN, MachinePointerInfo(SV), false, false, 0);
7578 MemOps.push_back(Store);
7581 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7582 FIN, DAG.getIntPtrConstant(4));
7583 Store = DAG.getStore(Op.getOperand(0), DL,
7584 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
7586 FIN, MachinePointerInfo(SV, 4), false, false, 0);
7587 MemOps.push_back(Store);
7589 // Store ptr to overflow_arg_area
7590 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7591 FIN, DAG.getIntPtrConstant(4));
7592 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
7594 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
7595 MachinePointerInfo(SV, 8),
7597 MemOps.push_back(Store);
7599 // Store ptr to reg_save_area.
7600 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7601 FIN, DAG.getIntPtrConstant(8));
7602 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
7604 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
7605 MachinePointerInfo(SV, 16), false, false, 0);
7606 MemOps.push_back(Store);
7607 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
7608 &MemOps[0], MemOps.size());
7611 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
7612 assert(Subtarget->is64Bit() &&
7613 "LowerVAARG only handles 64-bit va_arg!");
7614 assert((Subtarget->isTargetLinux() ||
7615 Subtarget->isTargetDarwin()) &&
7616 "Unhandled target in LowerVAARG");
7617 assert(Op.getNode()->getNumOperands() == 4);
7618 SDValue Chain = Op.getOperand(0);
7619 SDValue SrcPtr = Op.getOperand(1);
7620 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
7621 unsigned Align = Op.getConstantOperandVal(3);
7622 DebugLoc dl = Op.getDebugLoc();
7624 EVT ArgVT = Op.getNode()->getValueType(0);
7625 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
7626 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
7629 // Decide which area this value should be read from.
7630 // TODO: Implement the AMD64 ABI in its entirety. This simple
7631 // selection mechanism works only for the basic types.
7632 if (ArgVT == MVT::f80) {
7633 llvm_unreachable("va_arg for f80 not yet implemented");
7634 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
7635 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
7636 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
7637 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
7639 llvm_unreachable("Unhandled argument type in LowerVAARG");
7643 // Sanity Check: Make sure using fp_offset makes sense.
7644 assert(!UseSoftFloat &&
7645 !(DAG.getMachineFunction()
7646 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
7647 Subtarget->hasXMM());
7650 // Insert VAARG_64 node into the DAG
7651 // VAARG_64 returns two values: Variable Argument Address, Chain
7652 SmallVector<SDValue, 11> InstOps;
7653 InstOps.push_back(Chain);
7654 InstOps.push_back(SrcPtr);
7655 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
7656 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
7657 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
7658 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
7659 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
7660 VTs, &InstOps[0], InstOps.size(),
7662 MachinePointerInfo(SV),
7667 Chain = VAARG.getValue(1);
7669 // Load the next argument and return it
7670 return DAG.getLoad(ArgVT, dl,
7673 MachinePointerInfo(),
7677 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
7678 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
7679 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
7680 SDValue Chain = Op.getOperand(0);
7681 SDValue DstPtr = Op.getOperand(1);
7682 SDValue SrcPtr = Op.getOperand(2);
7683 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
7684 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
7685 DebugLoc DL = Op.getDebugLoc();
7687 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
7688 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
7690 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
7694 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
7695 DebugLoc dl = Op.getDebugLoc();
7696 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7698 default: return SDValue(); // Don't custom lower most intrinsics.
7699 // Comparison intrinsics.
7700 case Intrinsic::x86_sse_comieq_ss:
7701 case Intrinsic::x86_sse_comilt_ss:
7702 case Intrinsic::x86_sse_comile_ss:
7703 case Intrinsic::x86_sse_comigt_ss:
7704 case Intrinsic::x86_sse_comige_ss:
7705 case Intrinsic::x86_sse_comineq_ss:
7706 case Intrinsic::x86_sse_ucomieq_ss:
7707 case Intrinsic::x86_sse_ucomilt_ss:
7708 case Intrinsic::x86_sse_ucomile_ss:
7709 case Intrinsic::x86_sse_ucomigt_ss:
7710 case Intrinsic::x86_sse_ucomige_ss:
7711 case Intrinsic::x86_sse_ucomineq_ss:
7712 case Intrinsic::x86_sse2_comieq_sd:
7713 case Intrinsic::x86_sse2_comilt_sd:
7714 case Intrinsic::x86_sse2_comile_sd:
7715 case Intrinsic::x86_sse2_comigt_sd:
7716 case Intrinsic::x86_sse2_comige_sd:
7717 case Intrinsic::x86_sse2_comineq_sd:
7718 case Intrinsic::x86_sse2_ucomieq_sd:
7719 case Intrinsic::x86_sse2_ucomilt_sd:
7720 case Intrinsic::x86_sse2_ucomile_sd:
7721 case Intrinsic::x86_sse2_ucomigt_sd:
7722 case Intrinsic::x86_sse2_ucomige_sd:
7723 case Intrinsic::x86_sse2_ucomineq_sd: {
7725 ISD::CondCode CC = ISD::SETCC_INVALID;
7728 case Intrinsic::x86_sse_comieq_ss:
7729 case Intrinsic::x86_sse2_comieq_sd:
7733 case Intrinsic::x86_sse_comilt_ss:
7734 case Intrinsic::x86_sse2_comilt_sd:
7738 case Intrinsic::x86_sse_comile_ss:
7739 case Intrinsic::x86_sse2_comile_sd:
7743 case Intrinsic::x86_sse_comigt_ss:
7744 case Intrinsic::x86_sse2_comigt_sd:
7748 case Intrinsic::x86_sse_comige_ss:
7749 case Intrinsic::x86_sse2_comige_sd:
7753 case Intrinsic::x86_sse_comineq_ss:
7754 case Intrinsic::x86_sse2_comineq_sd:
7758 case Intrinsic::x86_sse_ucomieq_ss:
7759 case Intrinsic::x86_sse2_ucomieq_sd:
7760 Opc = X86ISD::UCOMI;
7763 case Intrinsic::x86_sse_ucomilt_ss:
7764 case Intrinsic::x86_sse2_ucomilt_sd:
7765 Opc = X86ISD::UCOMI;
7768 case Intrinsic::x86_sse_ucomile_ss:
7769 case Intrinsic::x86_sse2_ucomile_sd:
7770 Opc = X86ISD::UCOMI;
7773 case Intrinsic::x86_sse_ucomigt_ss:
7774 case Intrinsic::x86_sse2_ucomigt_sd:
7775 Opc = X86ISD::UCOMI;
7778 case Intrinsic::x86_sse_ucomige_ss:
7779 case Intrinsic::x86_sse2_ucomige_sd:
7780 Opc = X86ISD::UCOMI;
7783 case Intrinsic::x86_sse_ucomineq_ss:
7784 case Intrinsic::x86_sse2_ucomineq_sd:
7785 Opc = X86ISD::UCOMI;
7790 SDValue LHS = Op.getOperand(1);
7791 SDValue RHS = Op.getOperand(2);
7792 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
7793 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
7794 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
7795 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
7796 DAG.getConstant(X86CC, MVT::i8), Cond);
7797 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7799 // ptest and testp intrinsics. The intrinsic these come from are designed to
7800 // return an integer value, not just an instruction so lower it to the ptest
7801 // or testp pattern and a setcc for the result.
7802 case Intrinsic::x86_sse41_ptestz:
7803 case Intrinsic::x86_sse41_ptestc:
7804 case Intrinsic::x86_sse41_ptestnzc:
7805 case Intrinsic::x86_avx_ptestz_256:
7806 case Intrinsic::x86_avx_ptestc_256:
7807 case Intrinsic::x86_avx_ptestnzc_256:
7808 case Intrinsic::x86_avx_vtestz_ps:
7809 case Intrinsic::x86_avx_vtestc_ps:
7810 case Intrinsic::x86_avx_vtestnzc_ps:
7811 case Intrinsic::x86_avx_vtestz_pd:
7812 case Intrinsic::x86_avx_vtestc_pd:
7813 case Intrinsic::x86_avx_vtestnzc_pd:
7814 case Intrinsic::x86_avx_vtestz_ps_256:
7815 case Intrinsic::x86_avx_vtestc_ps_256:
7816 case Intrinsic::x86_avx_vtestnzc_ps_256:
7817 case Intrinsic::x86_avx_vtestz_pd_256:
7818 case Intrinsic::x86_avx_vtestc_pd_256:
7819 case Intrinsic::x86_avx_vtestnzc_pd_256: {
7820 bool IsTestPacked = false;
7823 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
7824 case Intrinsic::x86_avx_vtestz_ps:
7825 case Intrinsic::x86_avx_vtestz_pd:
7826 case Intrinsic::x86_avx_vtestz_ps_256:
7827 case Intrinsic::x86_avx_vtestz_pd_256:
7828 IsTestPacked = true; // Fallthrough
7829 case Intrinsic::x86_sse41_ptestz:
7830 case Intrinsic::x86_avx_ptestz_256:
7832 X86CC = X86::COND_E;
7834 case Intrinsic::x86_avx_vtestc_ps:
7835 case Intrinsic::x86_avx_vtestc_pd:
7836 case Intrinsic::x86_avx_vtestc_ps_256:
7837 case Intrinsic::x86_avx_vtestc_pd_256:
7838 IsTestPacked = true; // Fallthrough
7839 case Intrinsic::x86_sse41_ptestc:
7840 case Intrinsic::x86_avx_ptestc_256:
7842 X86CC = X86::COND_B;
7844 case Intrinsic::x86_avx_vtestnzc_ps:
7845 case Intrinsic::x86_avx_vtestnzc_pd:
7846 case Intrinsic::x86_avx_vtestnzc_ps_256:
7847 case Intrinsic::x86_avx_vtestnzc_pd_256:
7848 IsTestPacked = true; // Fallthrough
7849 case Intrinsic::x86_sse41_ptestnzc:
7850 case Intrinsic::x86_avx_ptestnzc_256:
7852 X86CC = X86::COND_A;
7856 SDValue LHS = Op.getOperand(1);
7857 SDValue RHS = Op.getOperand(2);
7858 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
7859 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
7860 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
7861 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
7862 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
7865 // Fix vector shift instructions where the last operand is a non-immediate
7867 case Intrinsic::x86_sse2_pslli_w:
7868 case Intrinsic::x86_sse2_pslli_d:
7869 case Intrinsic::x86_sse2_pslli_q:
7870 case Intrinsic::x86_sse2_psrli_w:
7871 case Intrinsic::x86_sse2_psrli_d:
7872 case Intrinsic::x86_sse2_psrli_q:
7873 case Intrinsic::x86_sse2_psrai_w:
7874 case Intrinsic::x86_sse2_psrai_d:
7875 case Intrinsic::x86_mmx_pslli_w:
7876 case Intrinsic::x86_mmx_pslli_d:
7877 case Intrinsic::x86_mmx_pslli_q:
7878 case Intrinsic::x86_mmx_psrli_w:
7879 case Intrinsic::x86_mmx_psrli_d:
7880 case Intrinsic::x86_mmx_psrli_q:
7881 case Intrinsic::x86_mmx_psrai_w:
7882 case Intrinsic::x86_mmx_psrai_d: {
7883 SDValue ShAmt = Op.getOperand(2);
7884 if (isa<ConstantSDNode>(ShAmt))
7887 unsigned NewIntNo = 0;
7888 EVT ShAmtVT = MVT::v4i32;
7890 case Intrinsic::x86_sse2_pslli_w:
7891 NewIntNo = Intrinsic::x86_sse2_psll_w;
7893 case Intrinsic::x86_sse2_pslli_d:
7894 NewIntNo = Intrinsic::x86_sse2_psll_d;
7896 case Intrinsic::x86_sse2_pslli_q:
7897 NewIntNo = Intrinsic::x86_sse2_psll_q;
7899 case Intrinsic::x86_sse2_psrli_w:
7900 NewIntNo = Intrinsic::x86_sse2_psrl_w;
7902 case Intrinsic::x86_sse2_psrli_d:
7903 NewIntNo = Intrinsic::x86_sse2_psrl_d;
7905 case Intrinsic::x86_sse2_psrli_q:
7906 NewIntNo = Intrinsic::x86_sse2_psrl_q;
7908 case Intrinsic::x86_sse2_psrai_w:
7909 NewIntNo = Intrinsic::x86_sse2_psra_w;
7911 case Intrinsic::x86_sse2_psrai_d:
7912 NewIntNo = Intrinsic::x86_sse2_psra_d;
7915 ShAmtVT = MVT::v2i32;
7917 case Intrinsic::x86_mmx_pslli_w:
7918 NewIntNo = Intrinsic::x86_mmx_psll_w;
7920 case Intrinsic::x86_mmx_pslli_d:
7921 NewIntNo = Intrinsic::x86_mmx_psll_d;
7923 case Intrinsic::x86_mmx_pslli_q:
7924 NewIntNo = Intrinsic::x86_mmx_psll_q;
7926 case Intrinsic::x86_mmx_psrli_w:
7927 NewIntNo = Intrinsic::x86_mmx_psrl_w;
7929 case Intrinsic::x86_mmx_psrli_d:
7930 NewIntNo = Intrinsic::x86_mmx_psrl_d;
7932 case Intrinsic::x86_mmx_psrli_q:
7933 NewIntNo = Intrinsic::x86_mmx_psrl_q;
7935 case Intrinsic::x86_mmx_psrai_w:
7936 NewIntNo = Intrinsic::x86_mmx_psra_w;
7938 case Intrinsic::x86_mmx_psrai_d:
7939 NewIntNo = Intrinsic::x86_mmx_psra_d;
7941 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
7947 // The vector shift intrinsics with scalars uses 32b shift amounts but
7948 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
7952 ShOps[1] = DAG.getConstant(0, MVT::i32);
7953 if (ShAmtVT == MVT::v4i32) {
7954 ShOps[2] = DAG.getUNDEF(MVT::i32);
7955 ShOps[3] = DAG.getUNDEF(MVT::i32);
7956 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
7958 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
7959 // FIXME this must be lowered to get rid of the invalid type.
7962 EVT VT = Op.getValueType();
7963 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
7964 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
7965 DAG.getConstant(NewIntNo, MVT::i32),
7966 Op.getOperand(1), ShAmt);
7971 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
7972 SelectionDAG &DAG) const {
7973 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7974 MFI->setReturnAddressIsTaken(true);
7976 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7977 DebugLoc dl = Op.getDebugLoc();
7980 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7982 DAG.getConstant(TD->getPointerSize(),
7983 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
7984 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7985 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7987 MachinePointerInfo(), false, false, 0);
7990 // Just load the return address.
7991 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
7992 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7993 RetAddrFI, MachinePointerInfo(), false, false, 0);
7996 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
7997 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7998 MFI->setFrameAddressIsTaken(true);
8000 EVT VT = Op.getValueType();
8001 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
8002 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8003 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
8004 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
8006 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
8007 MachinePointerInfo(),
8012 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
8013 SelectionDAG &DAG) const {
8014 return DAG.getIntPtrConstant(2*TD->getPointerSize());
8017 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
8018 MachineFunction &MF = DAG.getMachineFunction();
8019 SDValue Chain = Op.getOperand(0);
8020 SDValue Offset = Op.getOperand(1);
8021 SDValue Handler = Op.getOperand(2);
8022 DebugLoc dl = Op.getDebugLoc();
8024 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
8025 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
8027 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
8029 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
8030 DAG.getIntPtrConstant(TD->getPointerSize()));
8031 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
8032 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
8034 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
8035 MF.getRegInfo().addLiveOut(StoreAddrReg);
8037 return DAG.getNode(X86ISD::EH_RETURN, dl,
8039 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
8042 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
8043 SelectionDAG &DAG) const {
8044 SDValue Root = Op.getOperand(0);
8045 SDValue Trmp = Op.getOperand(1); // trampoline
8046 SDValue FPtr = Op.getOperand(2); // nested function
8047 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
8048 DebugLoc dl = Op.getDebugLoc();
8050 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
8052 if (Subtarget->is64Bit()) {
8053 SDValue OutChains[6];
8055 // Large code-model.
8056 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
8057 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
8059 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
8060 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
8062 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
8064 // Load the pointer to the nested function into R11.
8065 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
8066 SDValue Addr = Trmp;
8067 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8068 Addr, MachinePointerInfo(TrmpAddr),
8071 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8072 DAG.getConstant(2, MVT::i64));
8073 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
8074 MachinePointerInfo(TrmpAddr, 2),
8077 // Load the 'nest' parameter value into R10.
8078 // R10 is specified in X86CallingConv.td
8079 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
8080 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8081 DAG.getConstant(10, MVT::i64));
8082 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8083 Addr, MachinePointerInfo(TrmpAddr, 10),
8086 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8087 DAG.getConstant(12, MVT::i64));
8088 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
8089 MachinePointerInfo(TrmpAddr, 12),
8092 // Jump to the nested function.
8093 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
8094 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8095 DAG.getConstant(20, MVT::i64));
8096 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
8097 Addr, MachinePointerInfo(TrmpAddr, 20),
8100 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
8101 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
8102 DAG.getConstant(22, MVT::i64));
8103 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
8104 MachinePointerInfo(TrmpAddr, 22),
8108 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
8109 return DAG.getMergeValues(Ops, 2, dl);
8111 const Function *Func =
8112 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
8113 CallingConv::ID CC = Func->getCallingConv();
8118 llvm_unreachable("Unsupported calling convention");
8119 case CallingConv::C:
8120 case CallingConv::X86_StdCall: {
8121 // Pass 'nest' parameter in ECX.
8122 // Must be kept in sync with X86CallingConv.td
8125 // Check that ECX wasn't needed by an 'inreg' parameter.
8126 const FunctionType *FTy = Func->getFunctionType();
8127 const AttrListPtr &Attrs = Func->getAttributes();
8129 if (!Attrs.isEmpty() && !Func->isVarArg()) {
8130 unsigned InRegCount = 0;
8133 for (FunctionType::param_iterator I = FTy->param_begin(),
8134 E = FTy->param_end(); I != E; ++I, ++Idx)
8135 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
8136 // FIXME: should only count parameters that are lowered to integers.
8137 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
8139 if (InRegCount > 2) {
8140 report_fatal_error("Nest register in use - reduce number of inreg"
8146 case CallingConv::X86_FastCall:
8147 case CallingConv::X86_ThisCall:
8148 case CallingConv::Fast:
8149 // Pass 'nest' parameter in EAX.
8150 // Must be kept in sync with X86CallingConv.td
8155 SDValue OutChains[4];
8158 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8159 DAG.getConstant(10, MVT::i32));
8160 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
8162 // This is storing the opcode for MOV32ri.
8163 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
8164 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
8165 OutChains[0] = DAG.getStore(Root, dl,
8166 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
8167 Trmp, MachinePointerInfo(TrmpAddr),
8170 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8171 DAG.getConstant(1, MVT::i32));
8172 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
8173 MachinePointerInfo(TrmpAddr, 1),
8176 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
8177 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8178 DAG.getConstant(5, MVT::i32));
8179 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
8180 MachinePointerInfo(TrmpAddr, 5),
8183 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
8184 DAG.getConstant(6, MVT::i32));
8185 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
8186 MachinePointerInfo(TrmpAddr, 6),
8190 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
8191 return DAG.getMergeValues(Ops, 2, dl);
8195 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
8196 SelectionDAG &DAG) const {
8198 The rounding mode is in bits 11:10 of FPSR, and has the following
8205 FLT_ROUNDS, on the other hand, expects the following:
8212 To perform the conversion, we do:
8213 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
8216 MachineFunction &MF = DAG.getMachineFunction();
8217 const TargetMachine &TM = MF.getTarget();
8218 const TargetFrameInfo &TFI = *TM.getFrameInfo();
8219 unsigned StackAlignment = TFI.getStackAlignment();
8220 EVT VT = Op.getValueType();
8221 DebugLoc DL = Op.getDebugLoc();
8223 // Save FP Control Word to stack slot
8224 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
8225 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8228 MachineMemOperand *MMO =
8229 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8230 MachineMemOperand::MOStore, 2, 2);
8232 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
8233 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
8234 DAG.getVTList(MVT::Other),
8235 Ops, 2, MVT::i16, MMO);
8237 // Load FP Control Word from stack slot
8238 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
8239 MachinePointerInfo(), false, false, 0);
8241 // Transform as necessary
8243 DAG.getNode(ISD::SRL, DL, MVT::i16,
8244 DAG.getNode(ISD::AND, DL, MVT::i16,
8245 CWD, DAG.getConstant(0x800, MVT::i16)),
8246 DAG.getConstant(11, MVT::i8));
8248 DAG.getNode(ISD::SRL, DL, MVT::i16,
8249 DAG.getNode(ISD::AND, DL, MVT::i16,
8250 CWD, DAG.getConstant(0x400, MVT::i16)),
8251 DAG.getConstant(9, MVT::i8));
8254 DAG.getNode(ISD::AND, DL, MVT::i16,
8255 DAG.getNode(ISD::ADD, DL, MVT::i16,
8256 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
8257 DAG.getConstant(1, MVT::i16)),
8258 DAG.getConstant(3, MVT::i16));
8261 return DAG.getNode((VT.getSizeInBits() < 16 ?
8262 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
8265 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
8266 EVT VT = Op.getValueType();
8268 unsigned NumBits = VT.getSizeInBits();
8269 DebugLoc dl = Op.getDebugLoc();
8271 Op = Op.getOperand(0);
8272 if (VT == MVT::i8) {
8273 // Zero extend to i32 since there is not an i8 bsr.
8275 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8278 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
8279 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8280 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
8282 // If src is zero (i.e. bsr sets ZF), returns NumBits.
8285 DAG.getConstant(NumBits+NumBits-1, OpVT),
8286 DAG.getConstant(X86::COND_E, MVT::i8),
8289 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8291 // Finally xor with NumBits-1.
8292 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
8295 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8299 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
8300 EVT VT = Op.getValueType();
8302 unsigned NumBits = VT.getSizeInBits();
8303 DebugLoc dl = Op.getDebugLoc();
8305 Op = Op.getOperand(0);
8306 if (VT == MVT::i8) {
8308 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
8311 // Issue a bsf (scan bits forward) which also sets EFLAGS.
8312 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
8313 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
8315 // If src is zero (i.e. bsf sets ZF), returns NumBits.
8318 DAG.getConstant(NumBits, OpVT),
8319 DAG.getConstant(X86::COND_E, MVT::i8),
8322 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
8325 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
8329 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) const {
8330 EVT VT = Op.getValueType();
8331 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
8332 DebugLoc dl = Op.getDebugLoc();
8334 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
8335 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
8336 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
8337 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
8338 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
8340 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
8341 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
8342 // return AloBlo + AloBhi + AhiBlo;
8344 SDValue A = Op.getOperand(0);
8345 SDValue B = Op.getOperand(1);
8347 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8348 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8349 A, DAG.getConstant(32, MVT::i32));
8350 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8351 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8352 B, DAG.getConstant(32, MVT::i32));
8353 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8354 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8356 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8357 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8359 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8360 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
8362 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8363 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8364 AloBhi, DAG.getConstant(32, MVT::i32));
8365 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8366 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8367 AhiBlo, DAG.getConstant(32, MVT::i32));
8368 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
8369 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
8373 SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
8374 EVT VT = Op.getValueType();
8375 DebugLoc dl = Op.getDebugLoc();
8376 SDValue R = Op.getOperand(0);
8378 LLVMContext *Context = DAG.getContext();
8380 assert(Subtarget->hasSSE41() && "Cannot lower SHL without SSE4.1 or later");
8382 if (VT == MVT::v4i32) {
8383 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8384 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8385 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
8387 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
8389 std::vector<Constant*> CV(4, CI);
8390 Constant *C = ConstantVector::get(CV);
8391 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8392 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8393 MachinePointerInfo::getConstantPool(),
8396 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
8397 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
8398 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
8399 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
8401 if (VT == MVT::v16i8) {
8403 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8404 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8405 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
8407 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
8408 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
8410 std::vector<Constant*> CVM1(16, CM1);
8411 std::vector<Constant*> CVM2(16, CM2);
8412 Constant *C = ConstantVector::get(CVM1);
8413 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8414 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8415 MachinePointerInfo::getConstantPool(),
8418 // r = pblendv(r, psllw(r & (char16)15, 4), a);
8419 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8420 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8421 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8422 DAG.getConstant(4, MVT::i32));
8423 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8425 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8427 C = ConstantVector::get(CVM2);
8428 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8429 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8430 MachinePointerInfo::getConstantPool(),
8433 // r = pblendv(r, psllw(r & (char16)63, 2), a);
8434 M = DAG.getNode(ISD::AND, dl, VT, R, M);
8435 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
8436 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
8437 DAG.getConstant(2, MVT::i32));
8438 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, M, Op);
8440 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
8442 // return pblendv(r, r+r, a);
8443 R = DAG.getNode(X86ISD::PBLENDVB, dl, VT,
8444 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
8450 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
8451 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
8452 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
8453 // looks for this combo and may remove the "setcc" instruction if the "setcc"
8454 // has only one use.
8455 SDNode *N = Op.getNode();
8456 SDValue LHS = N->getOperand(0);
8457 SDValue RHS = N->getOperand(1);
8458 unsigned BaseOp = 0;
8460 DebugLoc DL = Op.getDebugLoc();
8461 switch (Op.getOpcode()) {
8462 default: llvm_unreachable("Unknown ovf instruction!");
8464 // A subtract of one will be selected as a INC. Note that INC doesn't
8465 // set CF, so we can't do this for UADDO.
8466 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8467 if (C->getAPIntValue() == 1) {
8468 BaseOp = X86ISD::INC;
8472 BaseOp = X86ISD::ADD;
8476 BaseOp = X86ISD::ADD;
8480 // A subtract of one will be selected as a DEC. Note that DEC doesn't
8481 // set CF, so we can't do this for USUBO.
8482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
8483 if (C->getAPIntValue() == 1) {
8484 BaseOp = X86ISD::DEC;
8488 BaseOp = X86ISD::SUB;
8492 BaseOp = X86ISD::SUB;
8496 BaseOp = X86ISD::SMUL;
8499 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
8500 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
8502 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
8505 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8506 DAG.getConstant(X86::COND_O, MVT::i32),
8507 SDValue(Sum.getNode(), 2));
8509 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8514 // Also sets EFLAGS.
8515 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
8516 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
8519 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
8520 DAG.getConstant(Cond, MVT::i32),
8521 SDValue(Sum.getNode(), 1));
8523 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
8527 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
8528 DebugLoc dl = Op.getDebugLoc();
8530 if (!Subtarget->hasSSE2()) {
8531 SDValue Chain = Op.getOperand(0);
8532 SDValue Zero = DAG.getConstant(0,
8533 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
8535 DAG.getRegister(X86::ESP, MVT::i32), // Base
8536 DAG.getTargetConstant(1, MVT::i8), // Scale
8537 DAG.getRegister(0, MVT::i32), // Index
8538 DAG.getTargetConstant(0, MVT::i32), // Disp
8539 DAG.getRegister(0, MVT::i32), // Segment.
8544 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
8545 array_lengthof(Ops));
8546 return SDValue(Res, 0);
8549 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
8551 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
8553 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
8554 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
8555 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
8556 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
8558 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
8559 if (!Op1 && !Op2 && !Op3 && Op4)
8560 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
8562 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
8563 if (Op1 && !Op2 && !Op3 && !Op4)
8564 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
8566 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
8568 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
8571 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
8572 EVT T = Op.getValueType();
8573 DebugLoc DL = Op.getDebugLoc();
8576 switch(T.getSimpleVT().SimpleTy) {
8578 assert(false && "Invalid value type!");
8579 case MVT::i8: Reg = X86::AL; size = 1; break;
8580 case MVT::i16: Reg = X86::AX; size = 2; break;
8581 case MVT::i32: Reg = X86::EAX; size = 4; break;
8583 assert(Subtarget->is64Bit() && "Node not type legal!");
8584 Reg = X86::RAX; size = 8;
8587 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
8588 Op.getOperand(2), SDValue());
8589 SDValue Ops[] = { cpIn.getValue(0),
8592 DAG.getTargetConstant(size, MVT::i8),
8594 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8595 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
8596 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
8599 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
8603 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
8604 SelectionDAG &DAG) const {
8605 assert(Subtarget->is64Bit() && "Result not type legalized?");
8606 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8607 SDValue TheChain = Op.getOperand(0);
8608 DebugLoc dl = Op.getDebugLoc();
8609 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8610 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
8611 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
8613 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
8614 DAG.getConstant(32, MVT::i8));
8616 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
8619 return DAG.getMergeValues(Ops, 2, dl);
8622 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
8623 SelectionDAG &DAG) const {
8624 EVT SrcVT = Op.getOperand(0).getValueType();
8625 EVT DstVT = Op.getValueType();
8626 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
8627 Subtarget->hasMMX() && "Unexpected custom BITCAST");
8628 assert((DstVT == MVT::i64 ||
8629 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
8630 "Unexpected custom BITCAST");
8631 // i64 <=> MMX conversions are Legal.
8632 if (SrcVT==MVT::i64 && DstVT.isVector())
8634 if (DstVT==MVT::i64 && SrcVT.isVector())
8636 // MMX <=> MMX conversions are Legal.
8637 if (SrcVT.isVector() && DstVT.isVector())
8639 // All other conversions need to be expanded.
8643 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
8644 SDNode *Node = Op.getNode();
8645 DebugLoc dl = Node->getDebugLoc();
8646 EVT T = Node->getValueType(0);
8647 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
8648 DAG.getConstant(0, T), Node->getOperand(2));
8649 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
8650 cast<AtomicSDNode>(Node)->getMemoryVT(),
8651 Node->getOperand(0),
8652 Node->getOperand(1), negOp,
8653 cast<AtomicSDNode>(Node)->getSrcValue(),
8654 cast<AtomicSDNode>(Node)->getAlignment());
8657 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
8658 EVT VT = Op.getNode()->getValueType(0);
8660 // Let legalize expand this if it isn't a legal type yet.
8661 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8664 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
8667 bool ExtraOp = false;
8668 switch (Op.getOpcode()) {
8669 default: assert(0 && "Invalid code");
8670 case ISD::ADDC: Opc = X86ISD::ADD; break;
8671 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
8672 case ISD::SUBC: Opc = X86ISD::SUB; break;
8673 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
8677 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
8679 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
8680 Op.getOperand(1), Op.getOperand(2));
8683 /// LowerOperation - Provide custom lowering hooks for some operations.
8685 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
8686 switch (Op.getOpcode()) {
8687 default: llvm_unreachable("Should not custom lower this!");
8688 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
8689 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
8690 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
8691 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
8692 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
8693 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
8694 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
8695 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
8696 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
8697 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
8698 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
8699 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
8700 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
8701 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
8702 case ISD::SHL_PARTS:
8703 case ISD::SRA_PARTS:
8704 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
8705 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
8706 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
8707 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
8708 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
8709 case ISD::FABS: return LowerFABS(Op, DAG);
8710 case ISD::FNEG: return LowerFNEG(Op, DAG);
8711 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
8712 case ISD::SETCC: return LowerSETCC(Op, DAG);
8713 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
8714 case ISD::SELECT: return LowerSELECT(Op, DAG);
8715 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
8716 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
8717 case ISD::VASTART: return LowerVASTART(Op, DAG);
8718 case ISD::VAARG: return LowerVAARG(Op, DAG);
8719 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
8720 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
8721 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
8722 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
8723 case ISD::FRAME_TO_ARGS_OFFSET:
8724 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
8725 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
8726 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
8727 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
8728 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
8729 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
8730 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
8731 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
8732 case ISD::SHL: return LowerSHL(Op, DAG);
8738 case ISD::UMULO: return LowerXALUO(Op, DAG);
8739 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
8740 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
8744 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
8748 void X86TargetLowering::
8749 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
8750 SelectionDAG &DAG, unsigned NewOp) const {
8751 EVT T = Node->getValueType(0);
8752 DebugLoc dl = Node->getDebugLoc();
8753 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
8755 SDValue Chain = Node->getOperand(0);
8756 SDValue In1 = Node->getOperand(1);
8757 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8758 Node->getOperand(2), DAG.getIntPtrConstant(0));
8759 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
8760 Node->getOperand(2), DAG.getIntPtrConstant(1));
8761 SDValue Ops[] = { Chain, In1, In2L, In2H };
8762 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
8764 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
8765 cast<MemSDNode>(Node)->getMemOperand());
8766 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
8767 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8768 Results.push_back(Result.getValue(2));
8771 /// ReplaceNodeResults - Replace a node with an illegal result type
8772 /// with a new node built out of custom code.
8773 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
8774 SmallVectorImpl<SDValue>&Results,
8775 SelectionDAG &DAG) const {
8776 DebugLoc dl = N->getDebugLoc();
8777 switch (N->getOpcode()) {
8779 assert(false && "Do not know how to custom type legalize this operation!");
8785 // We don't want to expand or promote these.
8787 case ISD::FP_TO_SINT: {
8788 std::pair<SDValue,SDValue> Vals =
8789 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
8790 SDValue FIST = Vals.first, StackSlot = Vals.second;
8791 if (FIST.getNode() != 0) {
8792 EVT VT = N->getValueType(0);
8793 // Return a load from the stack slot.
8794 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
8795 MachinePointerInfo(), false, false, 0));
8799 case ISD::READCYCLECOUNTER: {
8800 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8801 SDValue TheChain = N->getOperand(0);
8802 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
8803 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
8805 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
8807 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
8808 SDValue Ops[] = { eax, edx };
8809 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
8810 Results.push_back(edx.getValue(1));
8813 case ISD::ATOMIC_CMP_SWAP: {
8814 EVT T = N->getValueType(0);
8815 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
8816 SDValue cpInL, cpInH;
8817 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8818 DAG.getConstant(0, MVT::i32));
8819 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
8820 DAG.getConstant(1, MVT::i32));
8821 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
8822 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
8824 SDValue swapInL, swapInH;
8825 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8826 DAG.getConstant(0, MVT::i32));
8827 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
8828 DAG.getConstant(1, MVT::i32));
8829 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
8831 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
8832 swapInL.getValue(1));
8833 SDValue Ops[] = { swapInH.getValue(0),
8835 swapInH.getValue(1) };
8836 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
8837 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
8838 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG8_DAG, dl, Tys,
8840 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
8841 MVT::i32, Result.getValue(1));
8842 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
8843 MVT::i32, cpOutL.getValue(2));
8844 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
8845 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
8846 Results.push_back(cpOutH.getValue(1));
8849 case ISD::ATOMIC_LOAD_ADD:
8850 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
8852 case ISD::ATOMIC_LOAD_AND:
8853 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
8855 case ISD::ATOMIC_LOAD_NAND:
8856 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
8858 case ISD::ATOMIC_LOAD_OR:
8859 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
8861 case ISD::ATOMIC_LOAD_SUB:
8862 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
8864 case ISD::ATOMIC_LOAD_XOR:
8865 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
8867 case ISD::ATOMIC_SWAP:
8868 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
8873 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
8875 default: return NULL;
8876 case X86ISD::BSF: return "X86ISD::BSF";
8877 case X86ISD::BSR: return "X86ISD::BSR";
8878 case X86ISD::SHLD: return "X86ISD::SHLD";
8879 case X86ISD::SHRD: return "X86ISD::SHRD";
8880 case X86ISD::FAND: return "X86ISD::FAND";
8881 case X86ISD::FOR: return "X86ISD::FOR";
8882 case X86ISD::FXOR: return "X86ISD::FXOR";
8883 case X86ISD::FSRL: return "X86ISD::FSRL";
8884 case X86ISD::FILD: return "X86ISD::FILD";
8885 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
8886 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
8887 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
8888 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
8889 case X86ISD::FLD: return "X86ISD::FLD";
8890 case X86ISD::FST: return "X86ISD::FST";
8891 case X86ISD::CALL: return "X86ISD::CALL";
8892 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
8893 case X86ISD::BT: return "X86ISD::BT";
8894 case X86ISD::CMP: return "X86ISD::CMP";
8895 case X86ISD::COMI: return "X86ISD::COMI";
8896 case X86ISD::UCOMI: return "X86ISD::UCOMI";
8897 case X86ISD::SETCC: return "X86ISD::SETCC";
8898 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
8899 case X86ISD::CMOV: return "X86ISD::CMOV";
8900 case X86ISD::BRCOND: return "X86ISD::BRCOND";
8901 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
8902 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
8903 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
8904 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
8905 case X86ISD::Wrapper: return "X86ISD::Wrapper";
8906 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
8907 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
8908 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
8909 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
8910 case X86ISD::PINSRB: return "X86ISD::PINSRB";
8911 case X86ISD::PINSRW: return "X86ISD::PINSRW";
8912 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
8913 case X86ISD::PANDN: return "X86ISD::PANDN";
8914 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
8915 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
8916 case X86ISD::PSIGND: return "X86ISD::PSIGND";
8917 case X86ISD::PBLENDVB: return "X86ISD::PBLENDVB";
8918 case X86ISD::FMAX: return "X86ISD::FMAX";
8919 case X86ISD::FMIN: return "X86ISD::FMIN";
8920 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
8921 case X86ISD::FRCP: return "X86ISD::FRCP";
8922 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
8923 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
8924 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
8925 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
8926 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
8927 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
8928 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
8929 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
8930 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
8931 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
8932 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
8933 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
8934 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
8935 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
8936 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
8937 case X86ISD::VSHL: return "X86ISD::VSHL";
8938 case X86ISD::VSRL: return "X86ISD::VSRL";
8939 case X86ISD::CMPPD: return "X86ISD::CMPPD";
8940 case X86ISD::CMPPS: return "X86ISD::CMPPS";
8941 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
8942 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
8943 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
8944 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
8945 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
8946 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
8947 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
8948 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
8949 case X86ISD::ADD: return "X86ISD::ADD";
8950 case X86ISD::SUB: return "X86ISD::SUB";
8951 case X86ISD::ADC: return "X86ISD::ADC";
8952 case X86ISD::SBB: return "X86ISD::SBB";
8953 case X86ISD::SMUL: return "X86ISD::SMUL";
8954 case X86ISD::UMUL: return "X86ISD::UMUL";
8955 case X86ISD::INC: return "X86ISD::INC";
8956 case X86ISD::DEC: return "X86ISD::DEC";
8957 case X86ISD::OR: return "X86ISD::OR";
8958 case X86ISD::XOR: return "X86ISD::XOR";
8959 case X86ISD::AND: return "X86ISD::AND";
8960 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
8961 case X86ISD::PTEST: return "X86ISD::PTEST";
8962 case X86ISD::TESTP: return "X86ISD::TESTP";
8963 case X86ISD::PALIGN: return "X86ISD::PALIGN";
8964 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
8965 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
8966 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
8967 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
8968 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
8969 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
8970 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
8971 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
8972 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
8973 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
8974 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
8975 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
8976 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
8977 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
8978 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
8979 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
8980 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
8981 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
8982 case X86ISD::MOVSD: return "X86ISD::MOVSD";
8983 case X86ISD::MOVSS: return "X86ISD::MOVSS";
8984 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
8985 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
8986 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
8987 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
8988 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
8989 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
8990 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
8991 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
8992 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
8993 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
8994 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
8995 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
8996 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
8997 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
8998 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
9002 // isLegalAddressingMode - Return true if the addressing mode represented
9003 // by AM is legal for this target, for a load/store of the specified type.
9004 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
9005 const Type *Ty) const {
9006 // X86 supports extremely general addressing modes.
9007 CodeModel::Model M = getTargetMachine().getCodeModel();
9008 Reloc::Model R = getTargetMachine().getRelocationModel();
9010 // X86 allows a sign-extended 32-bit immediate field as a displacement.
9011 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
9016 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
9018 // If a reference to this global requires an extra load, we can't fold it.
9019 if (isGlobalStubReference(GVFlags))
9022 // If BaseGV requires a register for the PIC base, we cannot also have a
9023 // BaseReg specified.
9024 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
9027 // If lower 4G is not available, then we must use rip-relative addressing.
9028 if ((M != CodeModel::Small || R != Reloc::Static) &&
9029 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
9039 // These scales always work.
9044 // These scales are formed with basereg+scalereg. Only accept if there is
9049 default: // Other stuff never works.
9057 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
9058 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9060 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9061 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9062 if (NumBits1 <= NumBits2)
9067 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9068 if (!VT1.isInteger() || !VT2.isInteger())
9070 unsigned NumBits1 = VT1.getSizeInBits();
9071 unsigned NumBits2 = VT2.getSizeInBits();
9072 if (NumBits1 <= NumBits2)
9077 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
9078 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9079 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
9082 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
9083 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
9084 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
9087 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
9088 // i16 instructions are longer (0x66 prefix) and potentially slower.
9089 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
9092 /// isShuffleMaskLegal - Targets can use this to indicate that they only
9093 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
9094 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
9095 /// are assumed to be legal.
9097 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
9099 // Very little shuffling can be done for 64-bit vectors right now.
9100 if (VT.getSizeInBits() == 64)
9101 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
9103 // FIXME: pshufb, blends, shifts.
9104 return (VT.getVectorNumElements() == 2 ||
9105 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
9106 isMOVLMask(M, VT) ||
9107 isSHUFPMask(M, VT) ||
9108 isPSHUFDMask(M, VT) ||
9109 isPSHUFHWMask(M, VT) ||
9110 isPSHUFLWMask(M, VT) ||
9111 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
9112 isUNPCKLMask(M, VT) ||
9113 isUNPCKHMask(M, VT) ||
9114 isUNPCKL_v_undef_Mask(M, VT) ||
9115 isUNPCKH_v_undef_Mask(M, VT));
9119 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
9121 unsigned NumElts = VT.getVectorNumElements();
9122 // FIXME: This collection of masks seems suspect.
9125 if (NumElts == 4 && VT.getSizeInBits() == 128) {
9126 return (isMOVLMask(Mask, VT) ||
9127 isCommutedMOVLMask(Mask, VT, true) ||
9128 isSHUFPMask(Mask, VT) ||
9129 isCommutedSHUFPMask(Mask, VT));
9134 //===----------------------------------------------------------------------===//
9135 // X86 Scheduler Hooks
9136 //===----------------------------------------------------------------------===//
9138 // private utility function
9140 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
9141 MachineBasicBlock *MBB,
9148 TargetRegisterClass *RC,
9149 bool invSrc) const {
9150 // For the atomic bitwise operator, we generate
9153 // ld t1 = [bitinstr.addr]
9154 // op t2 = t1, [bitinstr.val]
9156 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9158 // fallthrough -->nextMBB
9159 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9160 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9161 MachineFunction::iterator MBBIter = MBB;
9164 /// First build the CFG
9165 MachineFunction *F = MBB->getParent();
9166 MachineBasicBlock *thisMBB = MBB;
9167 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9168 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9169 F->insert(MBBIter, newMBB);
9170 F->insert(MBBIter, nextMBB);
9172 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9173 nextMBB->splice(nextMBB->begin(), thisMBB,
9174 llvm::next(MachineBasicBlock::iterator(bInstr)),
9176 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9178 // Update thisMBB to fall through to newMBB
9179 thisMBB->addSuccessor(newMBB);
9181 // newMBB jumps to itself and fall through to nextMBB
9182 newMBB->addSuccessor(nextMBB);
9183 newMBB->addSuccessor(newMBB);
9185 // Insert instructions into newMBB based on incoming instruction
9186 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9187 "unexpected number of operands");
9188 DebugLoc dl = bInstr->getDebugLoc();
9189 MachineOperand& destOper = bInstr->getOperand(0);
9190 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9191 int numArgs = bInstr->getNumOperands() - 1;
9192 for (int i=0; i < numArgs; ++i)
9193 argOpers[i] = &bInstr->getOperand(i+1);
9195 // x86 address has 4 operands: base, index, scale, and displacement
9196 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9197 int valArgIndx = lastAddrIndx + 1;
9199 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9200 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
9201 for (int i=0; i <= lastAddrIndx; ++i)
9202 (*MIB).addOperand(*argOpers[i]);
9204 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
9206 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
9211 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9212 assert((argOpers[valArgIndx]->isReg() ||
9213 argOpers[valArgIndx]->isImm()) &&
9215 if (argOpers[valArgIndx]->isReg())
9216 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
9218 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
9220 (*MIB).addOperand(*argOpers[valArgIndx]);
9222 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
9225 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
9226 for (int i=0; i <= lastAddrIndx; ++i)
9227 (*MIB).addOperand(*argOpers[i]);
9229 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9230 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9231 bInstr->memoperands_end());
9233 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9237 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9239 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9243 // private utility function: 64 bit atomics on 32 bit host.
9245 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
9246 MachineBasicBlock *MBB,
9251 bool invSrc) const {
9252 // For the atomic bitwise operator, we generate
9253 // thisMBB (instructions are in pairs, except cmpxchg8b)
9254 // ld t1,t2 = [bitinstr.addr]
9256 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
9257 // op t5, t6 <- out1, out2, [bitinstr.val]
9258 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
9259 // mov ECX, EBX <- t5, t6
9260 // mov EAX, EDX <- t1, t2
9261 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
9262 // mov t3, t4 <- EAX, EDX
9264 // result in out1, out2
9265 // fallthrough -->nextMBB
9267 const TargetRegisterClass *RC = X86::GR32RegisterClass;
9268 const unsigned LoadOpc = X86::MOV32rm;
9269 const unsigned NotOpc = X86::NOT32r;
9270 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9271 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9272 MachineFunction::iterator MBBIter = MBB;
9275 /// First build the CFG
9276 MachineFunction *F = MBB->getParent();
9277 MachineBasicBlock *thisMBB = MBB;
9278 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9279 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9280 F->insert(MBBIter, newMBB);
9281 F->insert(MBBIter, nextMBB);
9283 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9284 nextMBB->splice(nextMBB->begin(), thisMBB,
9285 llvm::next(MachineBasicBlock::iterator(bInstr)),
9287 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9289 // Update thisMBB to fall through to newMBB
9290 thisMBB->addSuccessor(newMBB);
9292 // newMBB jumps to itself and fall through to nextMBB
9293 newMBB->addSuccessor(nextMBB);
9294 newMBB->addSuccessor(newMBB);
9296 DebugLoc dl = bInstr->getDebugLoc();
9297 // Insert instructions into newMBB based on incoming instruction
9298 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
9299 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
9300 "unexpected number of operands");
9301 MachineOperand& dest1Oper = bInstr->getOperand(0);
9302 MachineOperand& dest2Oper = bInstr->getOperand(1);
9303 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9304 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
9305 argOpers[i] = &bInstr->getOperand(i+2);
9307 // We use some of the operands multiple times, so conservatively just
9308 // clear any kill flags that might be present.
9309 if (argOpers[i]->isReg() && argOpers[i]->isUse())
9310 argOpers[i]->setIsKill(false);
9313 // x86 address has 5 operands: base, index, scale, displacement, and segment.
9314 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9316 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
9317 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
9318 for (int i=0; i <= lastAddrIndx; ++i)
9319 (*MIB).addOperand(*argOpers[i]);
9320 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
9321 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
9322 // add 4 to displacement.
9323 for (int i=0; i <= lastAddrIndx-2; ++i)
9324 (*MIB).addOperand(*argOpers[i]);
9325 MachineOperand newOp3 = *(argOpers[3]);
9327 newOp3.setImm(newOp3.getImm()+4);
9329 newOp3.setOffset(newOp3.getOffset()+4);
9330 (*MIB).addOperand(newOp3);
9331 (*MIB).addOperand(*argOpers[lastAddrIndx]);
9333 // t3/4 are defined later, at the bottom of the loop
9334 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
9335 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
9336 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
9337 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
9338 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
9339 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
9341 // The subsequent operations should be using the destination registers of
9342 //the PHI instructions.
9344 t1 = F->getRegInfo().createVirtualRegister(RC);
9345 t2 = F->getRegInfo().createVirtualRegister(RC);
9346 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
9347 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
9349 t1 = dest1Oper.getReg();
9350 t2 = dest2Oper.getReg();
9353 int valArgIndx = lastAddrIndx + 1;
9354 assert((argOpers[valArgIndx]->isReg() ||
9355 argOpers[valArgIndx]->isImm()) &&
9357 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
9358 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
9359 if (argOpers[valArgIndx]->isReg())
9360 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
9362 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
9363 if (regOpcL != X86::MOV32rr)
9365 (*MIB).addOperand(*argOpers[valArgIndx]);
9366 assert(argOpers[valArgIndx + 1]->isReg() ==
9367 argOpers[valArgIndx]->isReg());
9368 assert(argOpers[valArgIndx + 1]->isImm() ==
9369 argOpers[valArgIndx]->isImm());
9370 if (argOpers[valArgIndx + 1]->isReg())
9371 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
9373 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
9374 if (regOpcH != X86::MOV32rr)
9376 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
9378 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9380 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
9383 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
9385 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
9388 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
9389 for (int i=0; i <= lastAddrIndx; ++i)
9390 (*MIB).addOperand(*argOpers[i]);
9392 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9393 (*MIB).setMemRefs(bInstr->memoperands_begin(),
9394 bInstr->memoperands_end());
9396 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
9397 MIB.addReg(X86::EAX);
9398 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
9399 MIB.addReg(X86::EDX);
9402 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9404 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
9408 // private utility function
9410 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
9411 MachineBasicBlock *MBB,
9412 unsigned cmovOpc) const {
9413 // For the atomic min/max operator, we generate
9416 // ld t1 = [min/max.addr]
9417 // mov t2 = [min/max.val]
9419 // cmov[cond] t2 = t1
9421 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
9423 // fallthrough -->nextMBB
9425 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9426 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9427 MachineFunction::iterator MBBIter = MBB;
9430 /// First build the CFG
9431 MachineFunction *F = MBB->getParent();
9432 MachineBasicBlock *thisMBB = MBB;
9433 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
9434 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
9435 F->insert(MBBIter, newMBB);
9436 F->insert(MBBIter, nextMBB);
9438 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
9439 nextMBB->splice(nextMBB->begin(), thisMBB,
9440 llvm::next(MachineBasicBlock::iterator(mInstr)),
9442 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9444 // Update thisMBB to fall through to newMBB
9445 thisMBB->addSuccessor(newMBB);
9447 // newMBB jumps to newMBB and fall through to nextMBB
9448 newMBB->addSuccessor(nextMBB);
9449 newMBB->addSuccessor(newMBB);
9451 DebugLoc dl = mInstr->getDebugLoc();
9452 // Insert instructions into newMBB based on incoming instruction
9453 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
9454 "unexpected number of operands");
9455 MachineOperand& destOper = mInstr->getOperand(0);
9456 MachineOperand* argOpers[2 + X86::AddrNumOperands];
9457 int numArgs = mInstr->getNumOperands() - 1;
9458 for (int i=0; i < numArgs; ++i)
9459 argOpers[i] = &mInstr->getOperand(i+1);
9461 // x86 address has 4 operands: base, index, scale, and displacement
9462 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
9463 int valArgIndx = lastAddrIndx + 1;
9465 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9466 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
9467 for (int i=0; i <= lastAddrIndx; ++i)
9468 (*MIB).addOperand(*argOpers[i]);
9470 // We only support register and immediate values
9471 assert((argOpers[valArgIndx]->isReg() ||
9472 argOpers[valArgIndx]->isImm()) &&
9475 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9476 if (argOpers[valArgIndx]->isReg())
9477 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
9479 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
9480 (*MIB).addOperand(*argOpers[valArgIndx]);
9482 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
9485 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
9490 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
9491 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
9495 // Cmp and exchange if none has modified the memory location
9496 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
9497 for (int i=0; i <= lastAddrIndx; ++i)
9498 (*MIB).addOperand(*argOpers[i]);
9500 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
9501 (*MIB).setMemRefs(mInstr->memoperands_begin(),
9502 mInstr->memoperands_end());
9504 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
9505 MIB.addReg(X86::EAX);
9508 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
9510 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
9514 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
9515 // or XMM0_V32I8 in AVX all of this code can be replaced with that
9518 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
9519 unsigned numArgs, bool memArg) const {
9520 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
9521 "Target must have SSE4.2 or AVX features enabled");
9523 DebugLoc dl = MI->getDebugLoc();
9524 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9526 if (!Subtarget->hasAVX()) {
9528 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
9530 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
9533 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
9535 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
9538 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
9539 for (unsigned i = 0; i < numArgs; ++i) {
9540 MachineOperand &Op = MI->getOperand(i+1);
9541 if (!(Op.isReg() && Op.isImplicit()))
9544 BuildMI(*BB, MI, dl, TII->get(X86::MOVAPSrr), MI->getOperand(0).getReg())
9547 MI->eraseFromParent();
9552 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
9553 DebugLoc dl = MI->getDebugLoc();
9554 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9556 // Address into RAX/EAX, other two args into ECX, EDX.
9557 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
9558 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
9559 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
9560 for (int i = 0; i < X86::AddrNumOperands; ++i)
9561 MIB.addOperand(MI->getOperand(i));
9563 unsigned ValOps = X86::AddrNumOperands;
9564 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9565 .addReg(MI->getOperand(ValOps).getReg());
9566 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
9567 .addReg(MI->getOperand(ValOps+1).getReg());
9569 // The instruction doesn't actually take any operands though.
9570 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
9572 MI->eraseFromParent(); // The pseudo is gone now.
9577 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
9578 DebugLoc dl = MI->getDebugLoc();
9579 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9581 // First arg in ECX, the second in EAX.
9582 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
9583 .addReg(MI->getOperand(0).getReg());
9584 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
9585 .addReg(MI->getOperand(1).getReg());
9587 // The instruction doesn't actually take any operands though.
9588 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
9590 MI->eraseFromParent(); // The pseudo is gone now.
9595 X86TargetLowering::EmitVAARG64WithCustomInserter(
9597 MachineBasicBlock *MBB) const {
9598 // Emit va_arg instruction on X86-64.
9600 // Operands to this pseudo-instruction:
9601 // 0 ) Output : destination address (reg)
9602 // 1-5) Input : va_list address (addr, i64mem)
9603 // 6 ) ArgSize : Size (in bytes) of vararg type
9604 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
9605 // 8 ) Align : Alignment of type
9606 // 9 ) EFLAGS (implicit-def)
9608 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
9609 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
9611 unsigned DestReg = MI->getOperand(0).getReg();
9612 MachineOperand &Base = MI->getOperand(1);
9613 MachineOperand &Scale = MI->getOperand(2);
9614 MachineOperand &Index = MI->getOperand(3);
9615 MachineOperand &Disp = MI->getOperand(4);
9616 MachineOperand &Segment = MI->getOperand(5);
9617 unsigned ArgSize = MI->getOperand(6).getImm();
9618 unsigned ArgMode = MI->getOperand(7).getImm();
9619 unsigned Align = MI->getOperand(8).getImm();
9622 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
9623 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
9624 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
9626 // Machine Information
9627 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9628 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
9629 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
9630 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
9631 DebugLoc DL = MI->getDebugLoc();
9636 // i64 overflow_area (address)
9637 // i64 reg_save_area (address)
9639 // sizeof(va_list) = 24
9640 // alignment(va_list) = 8
9642 unsigned TotalNumIntRegs = 6;
9643 unsigned TotalNumXMMRegs = 8;
9644 bool UseGPOffset = (ArgMode == 1);
9645 bool UseFPOffset = (ArgMode == 2);
9646 unsigned MaxOffset = TotalNumIntRegs * 8 +
9647 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
9649 /* Align ArgSize to a multiple of 8 */
9650 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
9651 bool NeedsAlign = (Align > 8);
9653 MachineBasicBlock *thisMBB = MBB;
9654 MachineBasicBlock *overflowMBB;
9655 MachineBasicBlock *offsetMBB;
9656 MachineBasicBlock *endMBB;
9658 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
9659 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
9660 unsigned OffsetReg = 0;
9662 if (!UseGPOffset && !UseFPOffset) {
9663 // If we only pull from the overflow region, we don't create a branch.
9664 // We don't need to alter control flow.
9665 OffsetDestReg = 0; // unused
9666 OverflowDestReg = DestReg;
9669 overflowMBB = thisMBB;
9672 // First emit code to check if gp_offset (or fp_offset) is below the bound.
9673 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
9674 // If not, pull from overflow_area. (branch to overflowMBB)
9679 // offsetMBB overflowMBB
9684 // Registers for the PHI in endMBB
9685 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
9686 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
9688 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9689 MachineFunction *MF = MBB->getParent();
9690 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9691 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9692 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
9694 MachineFunction::iterator MBBIter = MBB;
9697 // Insert the new basic blocks
9698 MF->insert(MBBIter, offsetMBB);
9699 MF->insert(MBBIter, overflowMBB);
9700 MF->insert(MBBIter, endMBB);
9702 // Transfer the remainder of MBB and its successor edges to endMBB.
9703 endMBB->splice(endMBB->begin(), thisMBB,
9704 llvm::next(MachineBasicBlock::iterator(MI)),
9706 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
9708 // Make offsetMBB and overflowMBB successors of thisMBB
9709 thisMBB->addSuccessor(offsetMBB);
9710 thisMBB->addSuccessor(overflowMBB);
9712 // endMBB is a successor of both offsetMBB and overflowMBB
9713 offsetMBB->addSuccessor(endMBB);
9714 overflowMBB->addSuccessor(endMBB);
9716 // Load the offset value into a register
9717 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9718 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
9722 .addDisp(Disp, UseFPOffset ? 4 : 0)
9723 .addOperand(Segment)
9724 .setMemRefs(MMOBegin, MMOEnd);
9726 // Check if there is enough room left to pull this argument.
9727 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
9729 .addImm(MaxOffset + 8 - ArgSizeA8);
9731 // Branch to "overflowMBB" if offset >= max
9732 // Fall through to "offsetMBB" otherwise
9733 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
9734 .addMBB(overflowMBB);
9737 // In offsetMBB, emit code to use the reg_save_area.
9739 assert(OffsetReg != 0);
9741 // Read the reg_save_area address.
9742 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
9743 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
9748 .addOperand(Segment)
9749 .setMemRefs(MMOBegin, MMOEnd);
9751 // Zero-extend the offset
9752 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
9753 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
9756 .addImm(X86::sub_32bit);
9758 // Add the offset to the reg_save_area to get the final address.
9759 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
9760 .addReg(OffsetReg64)
9761 .addReg(RegSaveReg);
9763 // Compute the offset for the next argument
9764 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
9765 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
9767 .addImm(UseFPOffset ? 16 : 8);
9769 // Store it back into the va_list.
9770 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
9774 .addDisp(Disp, UseFPOffset ? 4 : 0)
9775 .addOperand(Segment)
9776 .addReg(NextOffsetReg)
9777 .setMemRefs(MMOBegin, MMOEnd);
9780 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
9785 // Emit code to use overflow area
9788 // Load the overflow_area address into a register.
9789 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
9790 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
9795 .addOperand(Segment)
9796 .setMemRefs(MMOBegin, MMOEnd);
9798 // If we need to align it, do so. Otherwise, just copy the address
9799 // to OverflowDestReg.
9801 // Align the overflow address
9802 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
9803 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
9805 // aligned_addr = (addr + (align-1)) & ~(align-1)
9806 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
9807 .addReg(OverflowAddrReg)
9810 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
9812 .addImm(~(uint64_t)(Align-1));
9814 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
9815 .addReg(OverflowAddrReg);
9818 // Compute the next overflow address after this argument.
9819 // (the overflow address should be kept 8-byte aligned)
9820 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
9821 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
9822 .addReg(OverflowDestReg)
9825 // Store the new overflow address.
9826 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
9831 .addOperand(Segment)
9832 .addReg(NextAddrReg)
9833 .setMemRefs(MMOBegin, MMOEnd);
9835 // If we branched, emit the PHI to the front of endMBB.
9837 BuildMI(*endMBB, endMBB->begin(), DL,
9838 TII->get(X86::PHI), DestReg)
9839 .addReg(OffsetDestReg).addMBB(offsetMBB)
9840 .addReg(OverflowDestReg).addMBB(overflowMBB);
9843 // Erase the pseudo instruction
9844 MI->eraseFromParent();
9850 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
9852 MachineBasicBlock *MBB) const {
9853 // Emit code to save XMM registers to the stack. The ABI says that the
9854 // number of registers to save is given in %al, so it's theoretically
9855 // possible to do an indirect jump trick to avoid saving all of them,
9856 // however this code takes a simpler approach and just executes all
9857 // of the stores if %al is non-zero. It's less code, and it's probably
9858 // easier on the hardware branch predictor, and stores aren't all that
9859 // expensive anyway.
9861 // Create the new basic blocks. One block contains all the XMM stores,
9862 // and one block is the final destination regardless of whether any
9863 // stores were performed.
9864 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
9865 MachineFunction *F = MBB->getParent();
9866 MachineFunction::iterator MBBIter = MBB;
9868 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
9869 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
9870 F->insert(MBBIter, XMMSaveMBB);
9871 F->insert(MBBIter, EndMBB);
9873 // Transfer the remainder of MBB and its successor edges to EndMBB.
9874 EndMBB->splice(EndMBB->begin(), MBB,
9875 llvm::next(MachineBasicBlock::iterator(MI)),
9877 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
9879 // The original block will now fall through to the XMM save block.
9880 MBB->addSuccessor(XMMSaveMBB);
9881 // The XMMSaveMBB will fall through to the end block.
9882 XMMSaveMBB->addSuccessor(EndMBB);
9884 // Now add the instructions.
9885 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9886 DebugLoc DL = MI->getDebugLoc();
9888 unsigned CountReg = MI->getOperand(0).getReg();
9889 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
9890 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
9892 if (!Subtarget->isTargetWin64()) {
9893 // If %al is 0, branch around the XMM save block.
9894 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
9895 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
9896 MBB->addSuccessor(EndMBB);
9899 // In the XMM save block, save all the XMM argument registers.
9900 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
9901 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
9902 MachineMemOperand *MMO =
9903 F->getMachineMemOperand(
9904 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
9905 MachineMemOperand::MOStore,
9906 /*Size=*/16, /*Align=*/16);
9907 BuildMI(XMMSaveMBB, DL, TII->get(X86::MOVAPSmr))
9908 .addFrameIndex(RegSaveFrameIndex)
9909 .addImm(/*Scale=*/1)
9910 .addReg(/*IndexReg=*/0)
9911 .addImm(/*Disp=*/Offset)
9912 .addReg(/*Segment=*/0)
9913 .addReg(MI->getOperand(i).getReg())
9914 .addMemOperand(MMO);
9917 MI->eraseFromParent(); // The pseudo instruction is gone now.
9923 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
9924 MachineBasicBlock *BB) const {
9925 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
9926 DebugLoc DL = MI->getDebugLoc();
9928 // To "insert" a SELECT_CC instruction, we actually have to insert the
9929 // diamond control-flow pattern. The incoming instruction knows the
9930 // destination vreg to set, the condition code register to branch on, the
9931 // true/false values to select between, and a branch opcode to use.
9932 const BasicBlock *LLVM_BB = BB->getBasicBlock();
9933 MachineFunction::iterator It = BB;
9939 // cmpTY ccX, r1, r2
9941 // fallthrough --> copy0MBB
9942 MachineBasicBlock *thisMBB = BB;
9943 MachineFunction *F = BB->getParent();
9944 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
9945 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
9946 F->insert(It, copy0MBB);
9947 F->insert(It, sinkMBB);
9949 // If the EFLAGS register isn't dead in the terminator, then claim that it's
9950 // live into the sink and copy blocks.
9951 const MachineFunction *MF = BB->getParent();
9952 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
9953 BitVector ReservedRegs = TRI->getReservedRegs(*MF);
9955 for (unsigned I = 0, E = MI->getNumOperands(); I != E; ++I) {
9956 const MachineOperand &MO = MI->getOperand(I);
9957 if (!MO.isReg() || !MO.isUse() || MO.isKill()) continue;
9958 unsigned Reg = MO.getReg();
9959 if (Reg != X86::EFLAGS) continue;
9960 copy0MBB->addLiveIn(Reg);
9961 sinkMBB->addLiveIn(Reg);
9964 // Transfer the remainder of BB and its successor edges to sinkMBB.
9965 sinkMBB->splice(sinkMBB->begin(), BB,
9966 llvm::next(MachineBasicBlock::iterator(MI)),
9968 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
9970 // Add the true and fallthrough blocks as its successors.
9971 BB->addSuccessor(copy0MBB);
9972 BB->addSuccessor(sinkMBB);
9974 // Create the conditional branch instruction.
9976 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
9977 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
9980 // %FalseValue = ...
9981 // # fallthrough to sinkMBB
9982 copy0MBB->addSuccessor(sinkMBB);
9985 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
9987 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
9988 TII->get(X86::PHI), MI->getOperand(0).getReg())
9989 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
9990 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
9992 MI->eraseFromParent(); // The pseudo instruction is gone now.
9997 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
9998 MachineBasicBlock *BB) const {
9999 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10000 DebugLoc DL = MI->getDebugLoc();
10002 // The lowering is pretty easy: we're just emitting the call to _alloca. The
10003 // non-trivial part is impdef of ESP.
10004 // FIXME: The code should be tweaked as soon as we'll try to do codegen for
10007 const char *StackProbeSymbol =
10008 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
10010 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
10011 .addExternalSymbol(StackProbeSymbol)
10012 .addReg(X86::EAX, RegState::Implicit)
10013 .addReg(X86::ESP, RegState::Implicit)
10014 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
10015 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
10016 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
10018 MI->eraseFromParent(); // The pseudo instruction is gone now.
10022 MachineBasicBlock *
10023 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
10024 MachineBasicBlock *BB) const {
10025 // This is pretty easy. We're taking the value that we received from
10026 // our load from the relocation, sticking it in either RDI (x86-64)
10027 // or EAX and doing an indirect call. The return value will then
10028 // be in the normal return register.
10029 const X86InstrInfo *TII
10030 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
10031 DebugLoc DL = MI->getDebugLoc();
10032 MachineFunction *F = BB->getParent();
10034 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
10035 assert(MI->getOperand(3).isGlobal() && "This should be a global");
10037 if (Subtarget->is64Bit()) {
10038 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10039 TII->get(X86::MOV64rm), X86::RDI)
10041 .addImm(0).addReg(0)
10042 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10043 MI->getOperand(3).getTargetFlags())
10045 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
10046 addDirectMem(MIB, X86::RDI);
10047 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
10048 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10049 TII->get(X86::MOV32rm), X86::EAX)
10051 .addImm(0).addReg(0)
10052 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10053 MI->getOperand(3).getTargetFlags())
10055 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10056 addDirectMem(MIB, X86::EAX);
10058 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
10059 TII->get(X86::MOV32rm), X86::EAX)
10060 .addReg(TII->getGlobalBaseReg(F))
10061 .addImm(0).addReg(0)
10062 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
10063 MI->getOperand(3).getTargetFlags())
10065 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
10066 addDirectMem(MIB, X86::EAX);
10069 MI->eraseFromParent(); // The pseudo instruction is gone now.
10073 MachineBasicBlock *
10074 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
10075 MachineBasicBlock *BB) const {
10076 switch (MI->getOpcode()) {
10077 default: assert(false && "Unexpected instr type to insert");
10078 case X86::WIN_ALLOCA:
10079 return EmitLoweredWinAlloca(MI, BB);
10080 case X86::TLSCall_32:
10081 case X86::TLSCall_64:
10082 return EmitLoweredTLSCall(MI, BB);
10083 case X86::CMOV_GR8:
10084 case X86::CMOV_FR32:
10085 case X86::CMOV_FR64:
10086 case X86::CMOV_V4F32:
10087 case X86::CMOV_V2F64:
10088 case X86::CMOV_V2I64:
10089 case X86::CMOV_GR16:
10090 case X86::CMOV_GR32:
10091 case X86::CMOV_RFP32:
10092 case X86::CMOV_RFP64:
10093 case X86::CMOV_RFP80:
10094 return EmitLoweredSelect(MI, BB);
10096 case X86::FP32_TO_INT16_IN_MEM:
10097 case X86::FP32_TO_INT32_IN_MEM:
10098 case X86::FP32_TO_INT64_IN_MEM:
10099 case X86::FP64_TO_INT16_IN_MEM:
10100 case X86::FP64_TO_INT32_IN_MEM:
10101 case X86::FP64_TO_INT64_IN_MEM:
10102 case X86::FP80_TO_INT16_IN_MEM:
10103 case X86::FP80_TO_INT32_IN_MEM:
10104 case X86::FP80_TO_INT64_IN_MEM: {
10105 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10106 DebugLoc DL = MI->getDebugLoc();
10108 // Change the floating point control register to use "round towards zero"
10109 // mode when truncating to an integer value.
10110 MachineFunction *F = BB->getParent();
10111 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
10112 addFrameReference(BuildMI(*BB, MI, DL,
10113 TII->get(X86::FNSTCW16m)), CWFrameIdx);
10115 // Load the old value of the high byte of the control word...
10117 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
10118 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
10121 // Set the high part to be round to zero...
10122 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
10125 // Reload the modified control word now...
10126 addFrameReference(BuildMI(*BB, MI, DL,
10127 TII->get(X86::FLDCW16m)), CWFrameIdx);
10129 // Restore the memory image of control word to original value
10130 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
10133 // Get the X86 opcode to use.
10135 switch (MI->getOpcode()) {
10136 default: llvm_unreachable("illegal opcode!");
10137 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
10138 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
10139 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
10140 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
10141 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
10142 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
10143 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
10144 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
10145 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
10149 MachineOperand &Op = MI->getOperand(0);
10151 AM.BaseType = X86AddressMode::RegBase;
10152 AM.Base.Reg = Op.getReg();
10154 AM.BaseType = X86AddressMode::FrameIndexBase;
10155 AM.Base.FrameIndex = Op.getIndex();
10157 Op = MI->getOperand(1);
10159 AM.Scale = Op.getImm();
10160 Op = MI->getOperand(2);
10162 AM.IndexReg = Op.getImm();
10163 Op = MI->getOperand(3);
10164 if (Op.isGlobal()) {
10165 AM.GV = Op.getGlobal();
10167 AM.Disp = Op.getImm();
10169 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
10170 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
10172 // Reload the original control word now.
10173 addFrameReference(BuildMI(*BB, MI, DL,
10174 TII->get(X86::FLDCW16m)), CWFrameIdx);
10176 MI->eraseFromParent(); // The pseudo instruction is gone now.
10179 // String/text processing lowering.
10180 case X86::PCMPISTRM128REG:
10181 case X86::VPCMPISTRM128REG:
10182 return EmitPCMP(MI, BB, 3, false /* in-mem */);
10183 case X86::PCMPISTRM128MEM:
10184 case X86::VPCMPISTRM128MEM:
10185 return EmitPCMP(MI, BB, 3, true /* in-mem */);
10186 case X86::PCMPESTRM128REG:
10187 case X86::VPCMPESTRM128REG:
10188 return EmitPCMP(MI, BB, 5, false /* in mem */);
10189 case X86::PCMPESTRM128MEM:
10190 case X86::VPCMPESTRM128MEM:
10191 return EmitPCMP(MI, BB, 5, true /* in mem */);
10193 // Thread synchronization.
10195 return EmitMonitor(MI, BB);
10197 return EmitMwait(MI, BB);
10199 // Atomic Lowering.
10200 case X86::ATOMAND32:
10201 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10202 X86::AND32ri, X86::MOV32rm,
10204 X86::NOT32r, X86::EAX,
10205 X86::GR32RegisterClass);
10206 case X86::ATOMOR32:
10207 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
10208 X86::OR32ri, X86::MOV32rm,
10210 X86::NOT32r, X86::EAX,
10211 X86::GR32RegisterClass);
10212 case X86::ATOMXOR32:
10213 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
10214 X86::XOR32ri, X86::MOV32rm,
10216 X86::NOT32r, X86::EAX,
10217 X86::GR32RegisterClass);
10218 case X86::ATOMNAND32:
10219 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
10220 X86::AND32ri, X86::MOV32rm,
10222 X86::NOT32r, X86::EAX,
10223 X86::GR32RegisterClass, true);
10224 case X86::ATOMMIN32:
10225 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
10226 case X86::ATOMMAX32:
10227 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
10228 case X86::ATOMUMIN32:
10229 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
10230 case X86::ATOMUMAX32:
10231 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
10233 case X86::ATOMAND16:
10234 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10235 X86::AND16ri, X86::MOV16rm,
10237 X86::NOT16r, X86::AX,
10238 X86::GR16RegisterClass);
10239 case X86::ATOMOR16:
10240 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
10241 X86::OR16ri, X86::MOV16rm,
10243 X86::NOT16r, X86::AX,
10244 X86::GR16RegisterClass);
10245 case X86::ATOMXOR16:
10246 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
10247 X86::XOR16ri, X86::MOV16rm,
10249 X86::NOT16r, X86::AX,
10250 X86::GR16RegisterClass);
10251 case X86::ATOMNAND16:
10252 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
10253 X86::AND16ri, X86::MOV16rm,
10255 X86::NOT16r, X86::AX,
10256 X86::GR16RegisterClass, true);
10257 case X86::ATOMMIN16:
10258 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
10259 case X86::ATOMMAX16:
10260 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
10261 case X86::ATOMUMIN16:
10262 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
10263 case X86::ATOMUMAX16:
10264 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
10266 case X86::ATOMAND8:
10267 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10268 X86::AND8ri, X86::MOV8rm,
10270 X86::NOT8r, X86::AL,
10271 X86::GR8RegisterClass);
10273 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
10274 X86::OR8ri, X86::MOV8rm,
10276 X86::NOT8r, X86::AL,
10277 X86::GR8RegisterClass);
10278 case X86::ATOMXOR8:
10279 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
10280 X86::XOR8ri, X86::MOV8rm,
10282 X86::NOT8r, X86::AL,
10283 X86::GR8RegisterClass);
10284 case X86::ATOMNAND8:
10285 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
10286 X86::AND8ri, X86::MOV8rm,
10288 X86::NOT8r, X86::AL,
10289 X86::GR8RegisterClass, true);
10290 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
10291 // This group is for 64-bit host.
10292 case X86::ATOMAND64:
10293 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10294 X86::AND64ri32, X86::MOV64rm,
10296 X86::NOT64r, X86::RAX,
10297 X86::GR64RegisterClass);
10298 case X86::ATOMOR64:
10299 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
10300 X86::OR64ri32, X86::MOV64rm,
10302 X86::NOT64r, X86::RAX,
10303 X86::GR64RegisterClass);
10304 case X86::ATOMXOR64:
10305 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
10306 X86::XOR64ri32, X86::MOV64rm,
10308 X86::NOT64r, X86::RAX,
10309 X86::GR64RegisterClass);
10310 case X86::ATOMNAND64:
10311 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
10312 X86::AND64ri32, X86::MOV64rm,
10314 X86::NOT64r, X86::RAX,
10315 X86::GR64RegisterClass, true);
10316 case X86::ATOMMIN64:
10317 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
10318 case X86::ATOMMAX64:
10319 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
10320 case X86::ATOMUMIN64:
10321 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
10322 case X86::ATOMUMAX64:
10323 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
10325 // This group does 64-bit operations on a 32-bit host.
10326 case X86::ATOMAND6432:
10327 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10328 X86::AND32rr, X86::AND32rr,
10329 X86::AND32ri, X86::AND32ri,
10331 case X86::ATOMOR6432:
10332 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10333 X86::OR32rr, X86::OR32rr,
10334 X86::OR32ri, X86::OR32ri,
10336 case X86::ATOMXOR6432:
10337 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10338 X86::XOR32rr, X86::XOR32rr,
10339 X86::XOR32ri, X86::XOR32ri,
10341 case X86::ATOMNAND6432:
10342 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10343 X86::AND32rr, X86::AND32rr,
10344 X86::AND32ri, X86::AND32ri,
10346 case X86::ATOMADD6432:
10347 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10348 X86::ADD32rr, X86::ADC32rr,
10349 X86::ADD32ri, X86::ADC32ri,
10351 case X86::ATOMSUB6432:
10352 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10353 X86::SUB32rr, X86::SBB32rr,
10354 X86::SUB32ri, X86::SBB32ri,
10356 case X86::ATOMSWAP6432:
10357 return EmitAtomicBit6432WithCustomInserter(MI, BB,
10358 X86::MOV32rr, X86::MOV32rr,
10359 X86::MOV32ri, X86::MOV32ri,
10361 case X86::VASTART_SAVE_XMM_REGS:
10362 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
10364 case X86::VAARG_64:
10365 return EmitVAARG64WithCustomInserter(MI, BB);
10369 //===----------------------------------------------------------------------===//
10370 // X86 Optimization Hooks
10371 //===----------------------------------------------------------------------===//
10373 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10377 const SelectionDAG &DAG,
10378 unsigned Depth) const {
10379 unsigned Opc = Op.getOpcode();
10380 assert((Opc >= ISD::BUILTIN_OP_END ||
10381 Opc == ISD::INTRINSIC_WO_CHAIN ||
10382 Opc == ISD::INTRINSIC_W_CHAIN ||
10383 Opc == ISD::INTRINSIC_VOID) &&
10384 "Should use MaskedValueIsZero if you don't know whether Op"
10385 " is a target node!");
10387 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
10401 // These nodes' second result is a boolean.
10402 if (Op.getResNo() == 0)
10405 case X86ISD::SETCC:
10406 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
10407 Mask.getBitWidth() - 1);
10412 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
10413 unsigned Depth) const {
10414 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
10415 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
10416 return Op.getValueType().getScalarType().getSizeInBits();
10422 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
10423 /// node is a GlobalAddress + offset.
10424 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
10425 const GlobalValue* &GA,
10426 int64_t &Offset) const {
10427 if (N->getOpcode() == X86ISD::Wrapper) {
10428 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
10429 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
10430 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
10434 return TargetLowering::isGAPlusOffset(N, GA, Offset);
10437 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
10438 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
10439 /// if the load addresses are consecutive, non-overlapping, and in the right
10441 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
10442 TargetLowering::DAGCombinerInfo &DCI) {
10443 DebugLoc dl = N->getDebugLoc();
10444 EVT VT = N->getValueType(0);
10446 if (VT.getSizeInBits() != 128)
10449 // Don't create instructions with illegal types after legalize types has run.
10450 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10451 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
10454 SmallVector<SDValue, 16> Elts;
10455 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
10456 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
10458 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
10461 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
10462 /// generation and convert it from being a bunch of shuffles and extracts
10463 /// to a simple store and scalar loads to extract the elements.
10464 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
10465 const TargetLowering &TLI) {
10466 SDValue InputVector = N->getOperand(0);
10468 // Only operate on vectors of 4 elements, where the alternative shuffling
10469 // gets to be more expensive.
10470 if (InputVector.getValueType() != MVT::v4i32)
10473 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
10474 // single use which is a sign-extend or zero-extend, and all elements are
10476 SmallVector<SDNode *, 4> Uses;
10477 unsigned ExtractedElements = 0;
10478 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
10479 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
10480 if (UI.getUse().getResNo() != InputVector.getResNo())
10483 SDNode *Extract = *UI;
10484 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10487 if (Extract->getValueType(0) != MVT::i32)
10489 if (!Extract->hasOneUse())
10491 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
10492 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
10494 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
10497 // Record which element was extracted.
10498 ExtractedElements |=
10499 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
10501 Uses.push_back(Extract);
10504 // If not all the elements were used, this may not be worthwhile.
10505 if (ExtractedElements != 15)
10508 // Ok, we've now decided to do the transformation.
10509 DebugLoc dl = InputVector.getDebugLoc();
10511 // Store the value to a temporary stack slot.
10512 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
10513 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
10514 MachinePointerInfo(), false, false, 0);
10516 // Replace each use (extract) with a load of the appropriate element.
10517 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
10518 UE = Uses.end(); UI != UE; ++UI) {
10519 SDNode *Extract = *UI;
10521 // Compute the element's address.
10522 SDValue Idx = Extract->getOperand(1);
10524 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
10525 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
10526 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
10528 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(),
10529 StackPtr, OffsetVal);
10531 // Load the scalar.
10532 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
10533 ScalarAddr, MachinePointerInfo(),
10536 // Replace the exact with the load.
10537 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
10540 // The replacement was made in place; don't return anything.
10544 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
10545 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
10546 const X86Subtarget *Subtarget) {
10547 DebugLoc DL = N->getDebugLoc();
10548 SDValue Cond = N->getOperand(0);
10549 // Get the LHS/RHS of the select.
10550 SDValue LHS = N->getOperand(1);
10551 SDValue RHS = N->getOperand(2);
10553 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
10554 // instructions match the semantics of the common C idiom x<y?x:y but not
10555 // x<=y?x:y, because of how they handle negative zero (which can be
10556 // ignored in unsafe-math mode).
10557 if (Subtarget->hasSSE2() &&
10558 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
10559 Cond.getOpcode() == ISD::SETCC) {
10560 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
10562 unsigned Opcode = 0;
10563 // Check for x CC y ? x : y.
10564 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
10565 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
10569 // Converting this to a min would handle NaNs incorrectly, and swapping
10570 // the operands would cause it to handle comparisons between positive
10571 // and negative zero incorrectly.
10572 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10573 if (!UnsafeFPMath &&
10574 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10576 std::swap(LHS, RHS);
10578 Opcode = X86ISD::FMIN;
10581 // Converting this to a min would handle comparisons between positive
10582 // and negative zero incorrectly.
10583 if (!UnsafeFPMath &&
10584 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
10586 Opcode = X86ISD::FMIN;
10589 // Converting this to a min would handle both negative zeros and NaNs
10590 // incorrectly, but we can swap the operands to fix both.
10591 std::swap(LHS, RHS);
10595 Opcode = X86ISD::FMIN;
10599 // Converting this to a max would handle comparisons between positive
10600 // and negative zero incorrectly.
10601 if (!UnsafeFPMath &&
10602 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(LHS))
10604 Opcode = X86ISD::FMAX;
10607 // Converting this to a max would handle NaNs incorrectly, and swapping
10608 // the operands would cause it to handle comparisons between positive
10609 // and negative zero incorrectly.
10610 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
10611 if (!UnsafeFPMath &&
10612 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10614 std::swap(LHS, RHS);
10616 Opcode = X86ISD::FMAX;
10619 // Converting this to a max would handle both negative zeros and NaNs
10620 // incorrectly, but we can swap the operands to fix both.
10621 std::swap(LHS, RHS);
10625 Opcode = X86ISD::FMAX;
10628 // Check for x CC y ? y : x -- a min/max with reversed arms.
10629 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
10630 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
10634 // Converting this to a min would handle comparisons between positive
10635 // and negative zero incorrectly, and swapping the operands would
10636 // cause it to handle NaNs incorrectly.
10637 if (!UnsafeFPMath &&
10638 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
10639 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10641 std::swap(LHS, RHS);
10643 Opcode = X86ISD::FMIN;
10646 // Converting this to a min would handle NaNs incorrectly.
10647 if (!UnsafeFPMath &&
10648 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
10650 Opcode = X86ISD::FMIN;
10653 // Converting this to a min would handle both negative zeros and NaNs
10654 // incorrectly, but we can swap the operands to fix both.
10655 std::swap(LHS, RHS);
10659 Opcode = X86ISD::FMIN;
10663 // Converting this to a max would handle NaNs incorrectly.
10664 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10666 Opcode = X86ISD::FMAX;
10669 // Converting this to a max would handle comparisons between positive
10670 // and negative zero incorrectly, and swapping the operands would
10671 // cause it to handle NaNs incorrectly.
10672 if (!UnsafeFPMath &&
10673 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
10674 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
10676 std::swap(LHS, RHS);
10678 Opcode = X86ISD::FMAX;
10681 // Converting this to a max would handle both negative zeros and NaNs
10682 // incorrectly, but we can swap the operands to fix both.
10683 std::swap(LHS, RHS);
10687 Opcode = X86ISD::FMAX;
10693 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
10696 // If this is a select between two integer constants, try to do some
10698 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
10699 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
10700 // Don't do this for crazy integer types.
10701 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
10702 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
10703 // so that TrueC (the true value) is larger than FalseC.
10704 bool NeedsCondInvert = false;
10706 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
10707 // Efficiently invertible.
10708 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
10709 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
10710 isa<ConstantSDNode>(Cond.getOperand(1))))) {
10711 NeedsCondInvert = true;
10712 std::swap(TrueC, FalseC);
10715 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
10716 if (FalseC->getAPIntValue() == 0 &&
10717 TrueC->getAPIntValue().isPowerOf2()) {
10718 if (NeedsCondInvert) // Invert the condition if needed.
10719 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10720 DAG.getConstant(1, Cond.getValueType()));
10722 // Zero extend the condition if needed.
10723 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
10725 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10726 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
10727 DAG.getConstant(ShAmt, MVT::i8));
10730 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
10731 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10732 if (NeedsCondInvert) // Invert the condition if needed.
10733 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10734 DAG.getConstant(1, Cond.getValueType()));
10736 // Zero extend the condition if needed.
10737 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10738 FalseC->getValueType(0), Cond);
10739 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10740 SDValue(FalseC, 0));
10743 // Optimize cases that will turn into an LEA instruction. This requires
10744 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10745 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10746 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10747 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10749 bool isFastMultiplier = false;
10751 switch ((unsigned char)Diff) {
10753 case 1: // result = add base, cond
10754 case 2: // result = lea base( , cond*2)
10755 case 3: // result = lea base(cond, cond*2)
10756 case 4: // result = lea base( , cond*4)
10757 case 5: // result = lea base(cond, cond*4)
10758 case 8: // result = lea base( , cond*8)
10759 case 9: // result = lea base(cond, cond*8)
10760 isFastMultiplier = true;
10765 if (isFastMultiplier) {
10766 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10767 if (NeedsCondInvert) // Invert the condition if needed.
10768 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
10769 DAG.getConstant(1, Cond.getValueType()));
10771 // Zero extend the condition if needed.
10772 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10774 // Scale the condition by the difference.
10776 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10777 DAG.getConstant(Diff, Cond.getValueType()));
10779 // Add the base if non-zero.
10780 if (FalseC->getAPIntValue() != 0)
10781 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10782 SDValue(FalseC, 0));
10792 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
10793 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
10794 TargetLowering::DAGCombinerInfo &DCI) {
10795 DebugLoc DL = N->getDebugLoc();
10797 // If the flag operand isn't dead, don't touch this CMOV.
10798 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
10801 // If this is a select between two integer constants, try to do some
10802 // optimizations. Note that the operands are ordered the opposite of SELECT
10804 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
10805 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10806 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
10807 // larger than FalseC (the false value).
10808 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
10810 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
10811 CC = X86::GetOppositeBranchCondition(CC);
10812 std::swap(TrueC, FalseC);
10815 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
10816 // This is efficient for any integer data type (including i8/i16) and
10818 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
10819 SDValue Cond = N->getOperand(3);
10820 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10821 DAG.getConstant(CC, MVT::i8), Cond);
10823 // Zero extend the condition if needed.
10824 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
10826 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
10827 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
10828 DAG.getConstant(ShAmt, MVT::i8));
10829 if (N->getNumValues() == 2) // Dead flag value?
10830 return DCI.CombineTo(N, Cond, SDValue());
10834 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
10835 // for any integer data type, including i8/i16.
10836 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
10837 SDValue Cond = N->getOperand(3);
10838 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10839 DAG.getConstant(CC, MVT::i8), Cond);
10841 // Zero extend the condition if needed.
10842 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
10843 FalseC->getValueType(0), Cond);
10844 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10845 SDValue(FalseC, 0));
10847 if (N->getNumValues() == 2) // Dead flag value?
10848 return DCI.CombineTo(N, Cond, SDValue());
10852 // Optimize cases that will turn into an LEA instruction. This requires
10853 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
10854 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
10855 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
10856 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
10858 bool isFastMultiplier = false;
10860 switch ((unsigned char)Diff) {
10862 case 1: // result = add base, cond
10863 case 2: // result = lea base( , cond*2)
10864 case 3: // result = lea base(cond, cond*2)
10865 case 4: // result = lea base( , cond*4)
10866 case 5: // result = lea base(cond, cond*4)
10867 case 8: // result = lea base( , cond*8)
10868 case 9: // result = lea base(cond, cond*8)
10869 isFastMultiplier = true;
10874 if (isFastMultiplier) {
10875 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
10876 SDValue Cond = N->getOperand(3);
10877 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10878 DAG.getConstant(CC, MVT::i8), Cond);
10879 // Zero extend the condition if needed.
10880 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
10882 // Scale the condition by the difference.
10884 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
10885 DAG.getConstant(Diff, Cond.getValueType()));
10887 // Add the base if non-zero.
10888 if (FalseC->getAPIntValue() != 0)
10889 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
10890 SDValue(FalseC, 0));
10891 if (N->getNumValues() == 2) // Dead flag value?
10892 return DCI.CombineTo(N, Cond, SDValue());
10902 /// PerformMulCombine - Optimize a single multiply with constant into two
10903 /// in order to implement it with two cheaper instructions, e.g.
10904 /// LEA + SHL, LEA + LEA.
10905 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
10906 TargetLowering::DAGCombinerInfo &DCI) {
10907 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
10910 EVT VT = N->getValueType(0);
10911 if (VT != MVT::i64)
10914 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
10917 uint64_t MulAmt = C->getZExtValue();
10918 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
10921 uint64_t MulAmt1 = 0;
10922 uint64_t MulAmt2 = 0;
10923 if ((MulAmt % 9) == 0) {
10925 MulAmt2 = MulAmt / 9;
10926 } else if ((MulAmt % 5) == 0) {
10928 MulAmt2 = MulAmt / 5;
10929 } else if ((MulAmt % 3) == 0) {
10931 MulAmt2 = MulAmt / 3;
10934 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
10935 DebugLoc DL = N->getDebugLoc();
10937 if (isPowerOf2_64(MulAmt2) &&
10938 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
10939 // If second multiplifer is pow2, issue it first. We want the multiply by
10940 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
10942 std::swap(MulAmt1, MulAmt2);
10945 if (isPowerOf2_64(MulAmt1))
10946 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
10947 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
10949 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
10950 DAG.getConstant(MulAmt1, VT));
10952 if (isPowerOf2_64(MulAmt2))
10953 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
10954 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
10956 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
10957 DAG.getConstant(MulAmt2, VT));
10959 // Do not add new nodes to DAG combiner worklist.
10960 DCI.CombineTo(N, NewMul, false);
10965 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
10966 SDValue N0 = N->getOperand(0);
10967 SDValue N1 = N->getOperand(1);
10968 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
10969 EVT VT = N0.getValueType();
10971 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
10972 // since the result of setcc_c is all zero's or all ones.
10973 if (N1C && N0.getOpcode() == ISD::AND &&
10974 N0.getOperand(1).getOpcode() == ISD::Constant) {
10975 SDValue N00 = N0.getOperand(0);
10976 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
10977 ((N00.getOpcode() == ISD::ANY_EXTEND ||
10978 N00.getOpcode() == ISD::ZERO_EXTEND) &&
10979 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
10980 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
10981 APInt ShAmt = N1C->getAPIntValue();
10982 Mask = Mask.shl(ShAmt);
10984 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
10985 N00, DAG.getConstant(Mask, VT));
10992 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
10994 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
10995 const X86Subtarget *Subtarget) {
10996 EVT VT = N->getValueType(0);
10997 if (!VT.isVector() && VT.isInteger() &&
10998 N->getOpcode() == ISD::SHL)
10999 return PerformSHLCombine(N, DAG);
11001 // On X86 with SSE2 support, we can transform this to a vector shift if
11002 // all elements are shifted by the same amount. We can't do this in legalize
11003 // because the a constant vector is typically transformed to a constant pool
11004 // so we have no knowledge of the shift amount.
11005 if (!Subtarget->hasSSE2())
11008 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
11011 SDValue ShAmtOp = N->getOperand(1);
11012 EVT EltVT = VT.getVectorElementType();
11013 DebugLoc DL = N->getDebugLoc();
11014 SDValue BaseShAmt = SDValue();
11015 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
11016 unsigned NumElts = VT.getVectorNumElements();
11018 for (; i != NumElts; ++i) {
11019 SDValue Arg = ShAmtOp.getOperand(i);
11020 if (Arg.getOpcode() == ISD::UNDEF) continue;
11024 for (; i != NumElts; ++i) {
11025 SDValue Arg = ShAmtOp.getOperand(i);
11026 if (Arg.getOpcode() == ISD::UNDEF) continue;
11027 if (Arg != BaseShAmt) {
11031 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
11032 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
11033 SDValue InVec = ShAmtOp.getOperand(0);
11034 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
11035 unsigned NumElts = InVec.getValueType().getVectorNumElements();
11037 for (; i != NumElts; ++i) {
11038 SDValue Arg = InVec.getOperand(i);
11039 if (Arg.getOpcode() == ISD::UNDEF) continue;
11043 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
11044 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
11045 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
11046 if (C->getZExtValue() == SplatIdx)
11047 BaseShAmt = InVec.getOperand(1);
11050 if (BaseShAmt.getNode() == 0)
11051 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
11052 DAG.getIntPtrConstant(0));
11056 // The shift amount is an i32.
11057 if (EltVT.bitsGT(MVT::i32))
11058 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
11059 else if (EltVT.bitsLT(MVT::i32))
11060 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
11062 // The shift amount is identical so we can do a vector shift.
11063 SDValue ValOp = N->getOperand(0);
11064 switch (N->getOpcode()) {
11066 llvm_unreachable("Unknown shift opcode!");
11069 if (VT == MVT::v2i64)
11070 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11071 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
11073 if (VT == MVT::v4i32)
11074 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11075 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
11077 if (VT == MVT::v8i16)
11078 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11079 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
11083 if (VT == MVT::v4i32)
11084 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11085 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
11087 if (VT == MVT::v8i16)
11088 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11089 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
11093 if (VT == MVT::v2i64)
11094 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11095 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
11097 if (VT == MVT::v4i32)
11098 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11099 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
11101 if (VT == MVT::v8i16)
11102 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
11103 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
11111 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
11112 TargetLowering::DAGCombinerInfo &DCI,
11113 const X86Subtarget *Subtarget) {
11114 if (DCI.isBeforeLegalizeOps())
11117 // Want to form PANDN nodes, in the hopes of then easily combining them with
11118 // OR and AND nodes to form PBLEND/PSIGN.
11119 EVT VT = N->getValueType(0);
11120 if (VT != MVT::v2i64)
11123 SDValue N0 = N->getOperand(0);
11124 SDValue N1 = N->getOperand(1);
11125 DebugLoc DL = N->getDebugLoc();
11127 // Check LHS for vnot
11128 if (N0.getOpcode() == ISD::XOR &&
11129 ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
11130 return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1);
11132 // Check RHS for vnot
11133 if (N1.getOpcode() == ISD::XOR &&
11134 ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
11135 return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0);
11140 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
11141 TargetLowering::DAGCombinerInfo &DCI,
11142 const X86Subtarget *Subtarget) {
11143 if (DCI.isBeforeLegalizeOps())
11146 EVT VT = N->getValueType(0);
11147 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
11150 SDValue N0 = N->getOperand(0);
11151 SDValue N1 = N->getOperand(1);
11153 // look for psign/blend
11154 if (Subtarget->hasSSSE3()) {
11155 if (VT == MVT::v2i64) {
11156 // Canonicalize pandn to RHS
11157 if (N0.getOpcode() == X86ISD::PANDN)
11159 // or (and (m, x), (pandn m, y))
11160 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::PANDN) {
11161 SDValue Mask = N1.getOperand(0);
11162 SDValue X = N1.getOperand(1);
11164 if (N0.getOperand(0) == Mask)
11165 Y = N0.getOperand(1);
11166 if (N0.getOperand(1) == Mask)
11167 Y = N0.getOperand(0);
11169 // Check to see if the mask appeared in both the AND and PANDN and
11173 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
11174 if (Mask.getOpcode() != ISD::BITCAST ||
11175 X.getOpcode() != ISD::BITCAST ||
11176 Y.getOpcode() != ISD::BITCAST)
11179 // Look through mask bitcast.
11180 Mask = Mask.getOperand(0);
11181 EVT MaskVT = Mask.getValueType();
11183 // Validate that the Mask operand is a vector sra node. The sra node
11184 // will be an intrinsic.
11185 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
11188 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
11189 // there is no psrai.b
11190 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
11191 case Intrinsic::x86_sse2_psrai_w:
11192 case Intrinsic::x86_sse2_psrai_d:
11194 default: return SDValue();
11197 // Check that the SRA is all signbits.
11198 SDValue SraC = Mask.getOperand(2);
11199 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
11200 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
11201 if ((SraAmt + 1) != EltBits)
11204 DebugLoc DL = N->getDebugLoc();
11206 // Now we know we at least have a plendvb with the mask val. See if
11207 // we can form a psignb/w/d.
11208 // psign = x.type == y.type == mask.type && y = sub(0, x);
11209 X = X.getOperand(0);
11210 Y = Y.getOperand(0);
11211 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
11212 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
11213 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
11216 case 8: Opc = X86ISD::PSIGNB; break;
11217 case 16: Opc = X86ISD::PSIGNW; break;
11218 case 32: Opc = X86ISD::PSIGND; break;
11222 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
11223 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
11226 // PBLENDVB only available on SSE 4.1
11227 if (!Subtarget->hasSSE41())
11230 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
11231 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
11232 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
11233 Mask = DAG.getNode(X86ISD::PBLENDVB, DL, MVT::v16i8, X, Y, Mask);
11234 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
11239 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
11240 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
11242 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
11244 if (!N0.hasOneUse() || !N1.hasOneUse())
11247 SDValue ShAmt0 = N0.getOperand(1);
11248 if (ShAmt0.getValueType() != MVT::i8)
11250 SDValue ShAmt1 = N1.getOperand(1);
11251 if (ShAmt1.getValueType() != MVT::i8)
11253 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
11254 ShAmt0 = ShAmt0.getOperand(0);
11255 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
11256 ShAmt1 = ShAmt1.getOperand(0);
11258 DebugLoc DL = N->getDebugLoc();
11259 unsigned Opc = X86ISD::SHLD;
11260 SDValue Op0 = N0.getOperand(0);
11261 SDValue Op1 = N1.getOperand(0);
11262 if (ShAmt0.getOpcode() == ISD::SUB) {
11263 Opc = X86ISD::SHRD;
11264 std::swap(Op0, Op1);
11265 std::swap(ShAmt0, ShAmt1);
11268 unsigned Bits = VT.getSizeInBits();
11269 if (ShAmt1.getOpcode() == ISD::SUB) {
11270 SDValue Sum = ShAmt1.getOperand(0);
11271 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
11272 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
11273 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
11274 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
11275 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
11276 return DAG.getNode(Opc, DL, VT,
11278 DAG.getNode(ISD::TRUNCATE, DL,
11281 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
11282 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
11284 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
11285 return DAG.getNode(Opc, DL, VT,
11286 N0.getOperand(0), N1.getOperand(0),
11287 DAG.getNode(ISD::TRUNCATE, DL,
11294 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
11295 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
11296 const X86Subtarget *Subtarget) {
11297 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
11298 // the FP state in cases where an emms may be missing.
11299 // A preferable solution to the general problem is to figure out the right
11300 // places to insert EMMS. This qualifies as a quick hack.
11302 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
11303 StoreSDNode *St = cast<StoreSDNode>(N);
11304 EVT VT = St->getValue().getValueType();
11305 if (VT.getSizeInBits() != 64)
11308 const Function *F = DAG.getMachineFunction().getFunction();
11309 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
11310 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
11311 && Subtarget->hasSSE2();
11312 if ((VT.isVector() ||
11313 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
11314 isa<LoadSDNode>(St->getValue()) &&
11315 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
11316 St->getChain().hasOneUse() && !St->isVolatile()) {
11317 SDNode* LdVal = St->getValue().getNode();
11318 LoadSDNode *Ld = 0;
11319 int TokenFactorIndex = -1;
11320 SmallVector<SDValue, 8> Ops;
11321 SDNode* ChainVal = St->getChain().getNode();
11322 // Must be a store of a load. We currently handle two cases: the load
11323 // is a direct child, and it's under an intervening TokenFactor. It is
11324 // possible to dig deeper under nested TokenFactors.
11325 if (ChainVal == LdVal)
11326 Ld = cast<LoadSDNode>(St->getChain());
11327 else if (St->getValue().hasOneUse() &&
11328 ChainVal->getOpcode() == ISD::TokenFactor) {
11329 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
11330 if (ChainVal->getOperand(i).getNode() == LdVal) {
11331 TokenFactorIndex = i;
11332 Ld = cast<LoadSDNode>(St->getValue());
11334 Ops.push_back(ChainVal->getOperand(i));
11338 if (!Ld || !ISD::isNormalLoad(Ld))
11341 // If this is not the MMX case, i.e. we are just turning i64 load/store
11342 // into f64 load/store, avoid the transformation if there are multiple
11343 // uses of the loaded value.
11344 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
11347 DebugLoc LdDL = Ld->getDebugLoc();
11348 DebugLoc StDL = N->getDebugLoc();
11349 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
11350 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
11352 if (Subtarget->is64Bit() || F64IsLegal) {
11353 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
11354 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
11355 Ld->getPointerInfo(), Ld->isVolatile(),
11356 Ld->isNonTemporal(), Ld->getAlignment());
11357 SDValue NewChain = NewLd.getValue(1);
11358 if (TokenFactorIndex != -1) {
11359 Ops.push_back(NewChain);
11360 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11363 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
11364 St->getPointerInfo(),
11365 St->isVolatile(), St->isNonTemporal(),
11366 St->getAlignment());
11369 // Otherwise, lower to two pairs of 32-bit loads / stores.
11370 SDValue LoAddr = Ld->getBasePtr();
11371 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
11372 DAG.getConstant(4, MVT::i32));
11374 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
11375 Ld->getPointerInfo(),
11376 Ld->isVolatile(), Ld->isNonTemporal(),
11377 Ld->getAlignment());
11378 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
11379 Ld->getPointerInfo().getWithOffset(4),
11380 Ld->isVolatile(), Ld->isNonTemporal(),
11381 MinAlign(Ld->getAlignment(), 4));
11383 SDValue NewChain = LoLd.getValue(1);
11384 if (TokenFactorIndex != -1) {
11385 Ops.push_back(LoLd);
11386 Ops.push_back(HiLd);
11387 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
11391 LoAddr = St->getBasePtr();
11392 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
11393 DAG.getConstant(4, MVT::i32));
11395 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
11396 St->getPointerInfo(),
11397 St->isVolatile(), St->isNonTemporal(),
11398 St->getAlignment());
11399 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
11400 St->getPointerInfo().getWithOffset(4),
11402 St->isNonTemporal(),
11403 MinAlign(St->getAlignment(), 4));
11404 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
11409 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
11410 /// X86ISD::FXOR nodes.
11411 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
11412 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
11413 // F[X]OR(0.0, x) -> x
11414 // F[X]OR(x, 0.0) -> x
11415 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11416 if (C->getValueAPF().isPosZero())
11417 return N->getOperand(1);
11418 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11419 if (C->getValueAPF().isPosZero())
11420 return N->getOperand(0);
11424 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
11425 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
11426 // FAND(0.0, x) -> 0.0
11427 // FAND(x, 0.0) -> 0.0
11428 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
11429 if (C->getValueAPF().isPosZero())
11430 return N->getOperand(0);
11431 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
11432 if (C->getValueAPF().isPosZero())
11433 return N->getOperand(1);
11437 static SDValue PerformBTCombine(SDNode *N,
11439 TargetLowering::DAGCombinerInfo &DCI) {
11440 // BT ignores high bits in the bit index operand.
11441 SDValue Op1 = N->getOperand(1);
11442 if (Op1.hasOneUse()) {
11443 unsigned BitWidth = Op1.getValueSizeInBits();
11444 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
11445 APInt KnownZero, KnownOne;
11446 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
11447 !DCI.isBeforeLegalizeOps());
11448 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11449 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
11450 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
11451 DCI.CommitTargetLoweringOpt(TLO);
11456 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
11457 SDValue Op = N->getOperand(0);
11458 if (Op.getOpcode() == ISD::BITCAST)
11459 Op = Op.getOperand(0);
11460 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
11461 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
11462 VT.getVectorElementType().getSizeInBits() ==
11463 OpVT.getVectorElementType().getSizeInBits()) {
11464 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
11469 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
11470 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
11471 // (and (i32 x86isd::setcc_carry), 1)
11472 // This eliminates the zext. This transformation is necessary because
11473 // ISD::SETCC is always legalized to i8.
11474 DebugLoc dl = N->getDebugLoc();
11475 SDValue N0 = N->getOperand(0);
11476 EVT VT = N->getValueType(0);
11477 if (N0.getOpcode() == ISD::AND &&
11479 N0.getOperand(0).hasOneUse()) {
11480 SDValue N00 = N0.getOperand(0);
11481 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
11483 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
11484 if (!C || C->getZExtValue() != 1)
11486 return DAG.getNode(ISD::AND, dl, VT,
11487 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
11488 N00.getOperand(0), N00.getOperand(1)),
11489 DAG.getConstant(1, VT));
11495 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
11496 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
11497 unsigned X86CC = N->getConstantOperandVal(0);
11498 SDValue EFLAG = N->getOperand(1);
11499 DebugLoc DL = N->getDebugLoc();
11501 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
11502 // a zext and produces an all-ones bit which is more useful than 0/1 in some
11504 if (X86CC == X86::COND_B)
11505 return DAG.getNode(ISD::AND, DL, MVT::i8,
11506 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
11507 DAG.getConstant(X86CC, MVT::i8), EFLAG),
11508 DAG.getConstant(1, MVT::i8));
11513 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
11514 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
11515 X86TargetLowering::DAGCombinerInfo &DCI) {
11516 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
11517 // the result is either zero or one (depending on the input carry bit).
11518 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
11519 if (X86::isZeroNode(N->getOperand(0)) &&
11520 X86::isZeroNode(N->getOperand(1)) &&
11521 // We don't have a good way to replace an EFLAGS use, so only do this when
11523 SDValue(N, 1).use_empty()) {
11524 DebugLoc DL = N->getDebugLoc();
11525 EVT VT = N->getValueType(0);
11526 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
11527 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
11528 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
11529 DAG.getConstant(X86::COND_B,MVT::i8),
11531 DAG.getConstant(1, VT));
11532 return DCI.CombineTo(N, Res1, CarryOut);
11538 // fold (add Y, (sete X, 0)) -> adc 0, Y
11539 // (add Y, (setne X, 0)) -> sbb -1, Y
11540 // (sub (sete X, 0), Y) -> sbb 0, Y
11541 // (sub (setne X, 0), Y) -> adc -1, Y
11542 static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) {
11543 DebugLoc DL = N->getDebugLoc();
11545 // Look through ZExts.
11546 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
11547 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
11550 SDValue SetCC = Ext.getOperand(0);
11551 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
11554 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
11555 if (CC != X86::COND_E && CC != X86::COND_NE)
11558 SDValue Cmp = SetCC.getOperand(1);
11559 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
11560 !X86::isZeroNode(Cmp.getOperand(1)))
11563 SDValue CmpOp0 = Cmp.getOperand(0);
11564 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
11565 DAG.getConstant(1, CmpOp0.getValueType()));
11567 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
11568 if (CC == X86::COND_NE)
11569 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
11570 DL, OtherVal.getValueType(), OtherVal,
11571 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
11572 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
11573 DL, OtherVal.getValueType(), OtherVal,
11574 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
11577 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
11578 DAGCombinerInfo &DCI) const {
11579 SelectionDAG &DAG = DCI.DAG;
11580 switch (N->getOpcode()) {
11582 case ISD::EXTRACT_VECTOR_ELT:
11583 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
11584 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
11585 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
11587 case ISD::SUB: return OptimizeConditonalInDecrement(N, DAG);
11588 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
11589 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
11592 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
11593 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
11594 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
11595 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
11597 case X86ISD::FOR: return PerformFORCombine(N, DAG);
11598 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
11599 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
11600 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
11601 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
11602 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
11603 case X86ISD::SHUFPS: // Handle all target specific shuffles
11604 case X86ISD::SHUFPD:
11605 case X86ISD::PALIGN:
11606 case X86ISD::PUNPCKHBW:
11607 case X86ISD::PUNPCKHWD:
11608 case X86ISD::PUNPCKHDQ:
11609 case X86ISD::PUNPCKHQDQ:
11610 case X86ISD::UNPCKHPS:
11611 case X86ISD::UNPCKHPD:
11612 case X86ISD::PUNPCKLBW:
11613 case X86ISD::PUNPCKLWD:
11614 case X86ISD::PUNPCKLDQ:
11615 case X86ISD::PUNPCKLQDQ:
11616 case X86ISD::UNPCKLPS:
11617 case X86ISD::UNPCKLPD:
11618 case X86ISD::MOVHLPS:
11619 case X86ISD::MOVLHPS:
11620 case X86ISD::PSHUFD:
11621 case X86ISD::PSHUFHW:
11622 case X86ISD::PSHUFLW:
11623 case X86ISD::MOVSS:
11624 case X86ISD::MOVSD:
11625 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI);
11631 /// isTypeDesirableForOp - Return true if the target has native support for
11632 /// the specified value type and it is 'desirable' to use the type for the
11633 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
11634 /// instruction encodings are longer and some i16 instructions are slow.
11635 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
11636 if (!isTypeLegal(VT))
11638 if (VT != MVT::i16)
11645 case ISD::SIGN_EXTEND:
11646 case ISD::ZERO_EXTEND:
11647 case ISD::ANY_EXTEND:
11660 /// IsDesirableToPromoteOp - This method query the target whether it is
11661 /// beneficial for dag combiner to promote the specified node. If true, it
11662 /// should return the desired promotion type by reference.
11663 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
11664 EVT VT = Op.getValueType();
11665 if (VT != MVT::i16)
11668 bool Promote = false;
11669 bool Commute = false;
11670 switch (Op.getOpcode()) {
11673 LoadSDNode *LD = cast<LoadSDNode>(Op);
11674 // If the non-extending load has a single use and it's not live out, then it
11675 // might be folded.
11676 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
11677 Op.hasOneUse()*/) {
11678 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
11679 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
11680 // The only case where we'd want to promote LOAD (rather then it being
11681 // promoted as an operand is when it's only use is liveout.
11682 if (UI->getOpcode() != ISD::CopyToReg)
11689 case ISD::SIGN_EXTEND:
11690 case ISD::ZERO_EXTEND:
11691 case ISD::ANY_EXTEND:
11696 SDValue N0 = Op.getOperand(0);
11697 // Look out for (store (shl (load), x)).
11698 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
11711 SDValue N0 = Op.getOperand(0);
11712 SDValue N1 = Op.getOperand(1);
11713 if (!Commute && MayFoldLoad(N1))
11715 // Avoid disabling potential load folding opportunities.
11716 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
11718 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
11728 //===----------------------------------------------------------------------===//
11729 // X86 Inline Assembly Support
11730 //===----------------------------------------------------------------------===//
11732 static bool LowerToBSwap(CallInst *CI) {
11733 // FIXME: this should verify that we are targetting a 486 or better. If not,
11734 // we will turn this bswap into something that will be lowered to logical ops
11735 // instead of emitting the bswap asm. For now, we don't support 486 or lower
11736 // so don't worry about this.
11738 // Verify this is a simple bswap.
11739 if (CI->getNumArgOperands() != 1 ||
11740 CI->getType() != CI->getArgOperand(0)->getType() ||
11741 !CI->getType()->isIntegerTy())
11744 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11745 if (!Ty || Ty->getBitWidth() % 16 != 0)
11748 // Okay, we can do this xform, do so now.
11749 const Type *Tys[] = { Ty };
11750 Module *M = CI->getParent()->getParent()->getParent();
11751 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
11753 Value *Op = CI->getArgOperand(0);
11754 Op = CallInst::Create(Int, Op, CI->getName(), CI);
11756 CI->replaceAllUsesWith(Op);
11757 CI->eraseFromParent();
11761 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
11762 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11763 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
11765 std::string AsmStr = IA->getAsmString();
11767 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
11768 SmallVector<StringRef, 4> AsmPieces;
11769 SplitString(AsmStr, AsmPieces, ";\n");
11771 switch (AsmPieces.size()) {
11772 default: return false;
11774 AsmStr = AsmPieces[0];
11776 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
11779 if (AsmPieces.size() == 2 &&
11780 (AsmPieces[0] == "bswap" ||
11781 AsmPieces[0] == "bswapq" ||
11782 AsmPieces[0] == "bswapl") &&
11783 (AsmPieces[1] == "$0" ||
11784 AsmPieces[1] == "${0:q}")) {
11785 // No need to check constraints, nothing other than the equivalent of
11786 // "=r,0" would be valid here.
11787 return LowerToBSwap(CI);
11789 // rorw $$8, ${0:w} --> llvm.bswap.i16
11790 if (CI->getType()->isIntegerTy(16) &&
11791 AsmPieces.size() == 3 &&
11792 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
11793 AsmPieces[1] == "$$8," &&
11794 AsmPieces[2] == "${0:w}" &&
11795 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11797 const std::string &Constraints = IA->getConstraintString();
11798 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11799 std::sort(AsmPieces.begin(), AsmPieces.end());
11800 if (AsmPieces.size() == 4 &&
11801 AsmPieces[0] == "~{cc}" &&
11802 AsmPieces[1] == "~{dirflag}" &&
11803 AsmPieces[2] == "~{flags}" &&
11804 AsmPieces[3] == "~{fpsr}") {
11805 return LowerToBSwap(CI);
11810 if (CI->getType()->isIntegerTy(32) &&
11811 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
11812 SmallVector<StringRef, 4> Words;
11813 SplitString(AsmPieces[0], Words, " \t,");
11814 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11815 Words[2] == "${0:w}") {
11817 SplitString(AsmPieces[1], Words, " \t,");
11818 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
11819 Words[2] == "$0") {
11821 SplitString(AsmPieces[2], Words, " \t,");
11822 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
11823 Words[2] == "${0:w}") {
11825 const std::string &Constraints = IA->getConstraintString();
11826 SplitString(StringRef(Constraints).substr(5), AsmPieces, ",");
11827 std::sort(AsmPieces.begin(), AsmPieces.end());
11828 if (AsmPieces.size() == 4 &&
11829 AsmPieces[0] == "~{cc}" &&
11830 AsmPieces[1] == "~{dirflag}" &&
11831 AsmPieces[2] == "~{flags}" &&
11832 AsmPieces[3] == "~{fpsr}") {
11833 return LowerToBSwap(CI);
11839 if (CI->getType()->isIntegerTy(64) &&
11840 Constraints.size() >= 2 &&
11841 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
11842 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
11843 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
11844 SmallVector<StringRef, 4> Words;
11845 SplitString(AsmPieces[0], Words, " \t");
11846 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
11848 SplitString(AsmPieces[1], Words, " \t");
11849 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
11851 SplitString(AsmPieces[2], Words, " \t,");
11852 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
11853 Words[2] == "%edx") {
11854 return LowerToBSwap(CI);
11866 /// getConstraintType - Given a constraint letter, return the type of
11867 /// constraint it is for this target.
11868 X86TargetLowering::ConstraintType
11869 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
11870 if (Constraint.size() == 1) {
11871 switch (Constraint[0]) {
11881 return C_RegisterClass;
11905 return TargetLowering::getConstraintType(Constraint);
11908 /// Examine constraint type and operand type and determine a weight value.
11909 /// This object must already have been set up with the operand type
11910 /// and the current alternative constraint selected.
11911 TargetLowering::ConstraintWeight
11912 X86TargetLowering::getSingleConstraintMatchWeight(
11913 AsmOperandInfo &info, const char *constraint) const {
11914 ConstraintWeight weight = CW_Invalid;
11915 Value *CallOperandVal = info.CallOperandVal;
11916 // If we don't have a value, we can't do a match,
11917 // but allow it at the lowest weight.
11918 if (CallOperandVal == NULL)
11920 const Type *type = CallOperandVal->getType();
11921 // Look at the constraint type.
11922 switch (*constraint) {
11924 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11935 if (CallOperandVal->getType()->isIntegerTy())
11936 weight = CW_SpecificReg;
11941 if (type->isFloatingPointTy())
11942 weight = CW_SpecificReg;
11945 if (type->isX86_MMXTy() && Subtarget->hasMMX())
11946 weight = CW_SpecificReg;
11950 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
11951 weight = CW_Register;
11954 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
11955 if (C->getZExtValue() <= 31)
11956 weight = CW_Constant;
11960 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11961 if (C->getZExtValue() <= 63)
11962 weight = CW_Constant;
11966 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11967 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
11968 weight = CW_Constant;
11972 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11973 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
11974 weight = CW_Constant;
11978 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11979 if (C->getZExtValue() <= 3)
11980 weight = CW_Constant;
11984 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11985 if (C->getZExtValue() <= 0xff)
11986 weight = CW_Constant;
11991 if (dyn_cast<ConstantFP>(CallOperandVal)) {
11992 weight = CW_Constant;
11996 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
11997 if ((C->getSExtValue() >= -0x80000000LL) &&
11998 (C->getSExtValue() <= 0x7fffffffLL))
11999 weight = CW_Constant;
12003 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
12004 if (C->getZExtValue() <= 0xffffffff)
12005 weight = CW_Constant;
12012 /// LowerXConstraint - try to replace an X constraint, which matches anything,
12013 /// with another that has more specific requirements based on the type of the
12014 /// corresponding operand.
12015 const char *X86TargetLowering::
12016 LowerXConstraint(EVT ConstraintVT) const {
12017 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
12018 // 'f' like normal targets.
12019 if (ConstraintVT.isFloatingPoint()) {
12020 if (Subtarget->hasXMMInt())
12022 if (Subtarget->hasXMM())
12026 return TargetLowering::LowerXConstraint(ConstraintVT);
12029 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
12030 /// vector. If it is invalid, don't add anything to Ops.
12031 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
12033 std::vector<SDValue>&Ops,
12034 SelectionDAG &DAG) const {
12035 SDValue Result(0, 0);
12037 switch (Constraint) {
12040 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12041 if (C->getZExtValue() <= 31) {
12042 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12049 if (C->getZExtValue() <= 63) {
12050 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12056 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12057 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
12058 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12065 if (C->getZExtValue() <= 255) {
12066 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12072 // 32-bit signed value
12073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12074 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12075 C->getSExtValue())) {
12076 // Widen to 64 bits here to get it sign extended.
12077 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
12080 // FIXME gcc accepts some relocatable values here too, but only in certain
12081 // memory models; it's complicated.
12086 // 32-bit unsigned value
12087 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
12088 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
12089 C->getZExtValue())) {
12090 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
12094 // FIXME gcc accepts some relocatable values here too, but only in certain
12095 // memory models; it's complicated.
12099 // Literal immediates are always ok.
12100 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
12101 // Widen to 64 bits here to get it sign extended.
12102 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
12106 // In any sort of PIC mode addresses need to be computed at runtime by
12107 // adding in a register or some sort of table lookup. These can't
12108 // be used as immediates.
12109 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
12112 // If we are in non-pic codegen mode, we allow the address of a global (with
12113 // an optional displacement) to be used with 'i'.
12114 GlobalAddressSDNode *GA = 0;
12115 int64_t Offset = 0;
12117 // Match either (GA), (GA+C), (GA+C1+C2), etc.
12119 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
12120 Offset += GA->getOffset();
12122 } else if (Op.getOpcode() == ISD::ADD) {
12123 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12124 Offset += C->getZExtValue();
12125 Op = Op.getOperand(0);
12128 } else if (Op.getOpcode() == ISD::SUB) {
12129 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
12130 Offset += -C->getZExtValue();
12131 Op = Op.getOperand(0);
12136 // Otherwise, this isn't something we can handle, reject it.
12140 const GlobalValue *GV = GA->getGlobal();
12141 // If we require an extra load to get this address, as in PIC mode, we
12142 // can't accept it.
12143 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
12144 getTargetMachine())))
12147 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
12148 GA->getValueType(0), Offset);
12153 if (Result.getNode()) {
12154 Ops.push_back(Result);
12157 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
12160 std::vector<unsigned> X86TargetLowering::
12161 getRegClassForInlineAsmConstraint(const std::string &Constraint,
12163 if (Constraint.size() == 1) {
12164 // FIXME: not handling fp-stack yet!
12165 switch (Constraint[0]) { // GCC X86 Constraint Letters
12166 default: break; // Unknown constraint letter
12167 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
12168 if (Subtarget->is64Bit()) {
12169 if (VT == MVT::i32)
12170 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
12171 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
12172 X86::R10D,X86::R11D,X86::R12D,
12173 X86::R13D,X86::R14D,X86::R15D,
12174 X86::EBP, X86::ESP, 0);
12175 else if (VT == MVT::i16)
12176 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
12177 X86::SI, X86::DI, X86::R8W,X86::R9W,
12178 X86::R10W,X86::R11W,X86::R12W,
12179 X86::R13W,X86::R14W,X86::R15W,
12180 X86::BP, X86::SP, 0);
12181 else if (VT == MVT::i8)
12182 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
12183 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
12184 X86::R10B,X86::R11B,X86::R12B,
12185 X86::R13B,X86::R14B,X86::R15B,
12186 X86::BPL, X86::SPL, 0);
12188 else if (VT == MVT::i64)
12189 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
12190 X86::RSI, X86::RDI, X86::R8, X86::R9,
12191 X86::R10, X86::R11, X86::R12,
12192 X86::R13, X86::R14, X86::R15,
12193 X86::RBP, X86::RSP, 0);
12197 // 32-bit fallthrough
12198 case 'Q': // Q_REGS
12199 if (VT == MVT::i32)
12200 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
12201 else if (VT == MVT::i16)
12202 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
12203 else if (VT == MVT::i8)
12204 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
12205 else if (VT == MVT::i64)
12206 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
12211 return std::vector<unsigned>();
12214 std::pair<unsigned, const TargetRegisterClass*>
12215 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
12217 // First, see if this is a constraint that directly corresponds to an LLVM
12219 if (Constraint.size() == 1) {
12220 // GCC Constraint Letters
12221 switch (Constraint[0]) {
12223 case 'r': // GENERAL_REGS
12224 case 'l': // INDEX_REGS
12226 return std::make_pair(0U, X86::GR8RegisterClass);
12227 if (VT == MVT::i16)
12228 return std::make_pair(0U, X86::GR16RegisterClass);
12229 if (VT == MVT::i32 || !Subtarget->is64Bit())
12230 return std::make_pair(0U, X86::GR32RegisterClass);
12231 return std::make_pair(0U, X86::GR64RegisterClass);
12232 case 'R': // LEGACY_REGS
12234 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
12235 if (VT == MVT::i16)
12236 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
12237 if (VT == MVT::i32 || !Subtarget->is64Bit())
12238 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
12239 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
12240 case 'f': // FP Stack registers.
12241 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
12242 // value to the correct fpstack register class.
12243 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
12244 return std::make_pair(0U, X86::RFP32RegisterClass);
12245 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
12246 return std::make_pair(0U, X86::RFP64RegisterClass);
12247 return std::make_pair(0U, X86::RFP80RegisterClass);
12248 case 'y': // MMX_REGS if MMX allowed.
12249 if (!Subtarget->hasMMX()) break;
12250 return std::make_pair(0U, X86::VR64RegisterClass);
12251 case 'Y': // SSE_REGS if SSE2 allowed
12252 if (!Subtarget->hasXMMInt()) break;
12254 case 'x': // SSE_REGS if SSE1 allowed
12255 if (!Subtarget->hasXMM()) break;
12257 switch (VT.getSimpleVT().SimpleTy) {
12259 // Scalar SSE types.
12262 return std::make_pair(0U, X86::FR32RegisterClass);
12265 return std::make_pair(0U, X86::FR64RegisterClass);
12273 return std::make_pair(0U, X86::VR128RegisterClass);
12279 // Use the default implementation in TargetLowering to convert the register
12280 // constraint into a member of a register class.
12281 std::pair<unsigned, const TargetRegisterClass*> Res;
12282 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
12284 // Not found as a standard register?
12285 if (Res.second == 0) {
12286 // Map st(0) -> st(7) -> ST0
12287 if (Constraint.size() == 7 && Constraint[0] == '{' &&
12288 tolower(Constraint[1]) == 's' &&
12289 tolower(Constraint[2]) == 't' &&
12290 Constraint[3] == '(' &&
12291 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
12292 Constraint[5] == ')' &&
12293 Constraint[6] == '}') {
12295 Res.first = X86::ST0+Constraint[4]-'0';
12296 Res.second = X86::RFP80RegisterClass;
12300 // GCC allows "st(0)" to be called just plain "st".
12301 if (StringRef("{st}").equals_lower(Constraint)) {
12302 Res.first = X86::ST0;
12303 Res.second = X86::RFP80RegisterClass;
12308 if (StringRef("{flags}").equals_lower(Constraint)) {
12309 Res.first = X86::EFLAGS;
12310 Res.second = X86::CCRRegisterClass;
12314 // 'A' means EAX + EDX.
12315 if (Constraint == "A") {
12316 Res.first = X86::EAX;
12317 Res.second = X86::GR32_ADRegisterClass;
12323 // Otherwise, check to see if this is a register class of the wrong value
12324 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
12325 // turn into {ax},{dx}.
12326 if (Res.second->hasType(VT))
12327 return Res; // Correct type already, nothing to do.
12329 // All of the single-register GCC register classes map their values onto
12330 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
12331 // really want an 8-bit or 32-bit register, map to the appropriate register
12332 // class and return the appropriate register.
12333 if (Res.second == X86::GR16RegisterClass) {
12334 if (VT == MVT::i8) {
12335 unsigned DestReg = 0;
12336 switch (Res.first) {
12338 case X86::AX: DestReg = X86::AL; break;
12339 case X86::DX: DestReg = X86::DL; break;
12340 case X86::CX: DestReg = X86::CL; break;
12341 case X86::BX: DestReg = X86::BL; break;
12344 Res.first = DestReg;
12345 Res.second = X86::GR8RegisterClass;
12347 } else if (VT == MVT::i32) {
12348 unsigned DestReg = 0;
12349 switch (Res.first) {
12351 case X86::AX: DestReg = X86::EAX; break;
12352 case X86::DX: DestReg = X86::EDX; break;
12353 case X86::CX: DestReg = X86::ECX; break;
12354 case X86::BX: DestReg = X86::EBX; break;
12355 case X86::SI: DestReg = X86::ESI; break;
12356 case X86::DI: DestReg = X86::EDI; break;
12357 case X86::BP: DestReg = X86::EBP; break;
12358 case X86::SP: DestReg = X86::ESP; break;
12361 Res.first = DestReg;
12362 Res.second = X86::GR32RegisterClass;
12364 } else if (VT == MVT::i64) {
12365 unsigned DestReg = 0;
12366 switch (Res.first) {
12368 case X86::AX: DestReg = X86::RAX; break;
12369 case X86::DX: DestReg = X86::RDX; break;
12370 case X86::CX: DestReg = X86::RCX; break;
12371 case X86::BX: DestReg = X86::RBX; break;
12372 case X86::SI: DestReg = X86::RSI; break;
12373 case X86::DI: DestReg = X86::RDI; break;
12374 case X86::BP: DestReg = X86::RBP; break;
12375 case X86::SP: DestReg = X86::RSP; break;
12378 Res.first = DestReg;
12379 Res.second = X86::GR64RegisterClass;
12382 } else if (Res.second == X86::FR32RegisterClass ||
12383 Res.second == X86::FR64RegisterClass ||
12384 Res.second == X86::VR128RegisterClass) {
12385 // Handle references to XMM physical registers that got mapped into the
12386 // wrong class. This can happen with constraints like {xmm0} where the
12387 // target independent register mapper will just pick the first match it can
12388 // find, ignoring the required type.
12389 if (VT == MVT::f32)
12390 Res.second = X86::FR32RegisterClass;
12391 else if (VT == MVT::f64)
12392 Res.second = X86::FR64RegisterClass;
12393 else if (X86::VR128RegisterClass->hasType(VT))
12394 Res.second = X86::VR128RegisterClass;