1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallBitVector.h"
23 #include "llvm/ADT/SmallSet.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/VariadicFunction.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/IR/CallSite.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DerivedTypes.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalAlias.h"
41 #include "llvm/IR/GlobalVariable.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/MC/MCAsmInfo.h"
45 #include "llvm/MC/MCContext.h"
46 #include "llvm/MC/MCExpr.h"
47 #include "llvm/MC/MCSymbol.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "X86IntrinsicsInfo.h"
59 #define DEBUG_TYPE "x86-isel"
61 STATISTIC(NumTailCalls, "Number of tail calls");
63 static cl::opt<bool> ExperimentalVectorWideningLegalization(
64 "x86-experimental-vector-widening-legalization", cl::init(false),
65 cl::desc("Enable an experimental vector type legalization through widening "
66 "rather than promotion."),
69 static cl::opt<bool> ExperimentalVectorShuffleLowering(
70 "x86-experimental-vector-shuffle-lowering", cl::init(true),
71 cl::desc("Enable an experimental vector shuffle lowering code path."),
74 static cl::opt<int> ReciprocalEstimateRefinementSteps(
75 "x86-recip-refinement-steps", cl::init(1),
76 cl::desc("Specify the number of Newton-Raphson iterations applied to the "
77 "result of the hardware reciprocal estimate instruction."),
80 // Forward declarations.
81 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
84 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
85 SelectionDAG &DAG, SDLoc dl,
86 unsigned vectorWidth) {
87 assert((vectorWidth == 128 || vectorWidth == 256) &&
88 "Unsupported vector width");
89 EVT VT = Vec.getValueType();
90 EVT ElVT = VT.getVectorElementType();
91 unsigned Factor = VT.getSizeInBits()/vectorWidth;
92 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
93 VT.getVectorNumElements()/Factor);
95 // Extract from UNDEF is UNDEF.
96 if (Vec.getOpcode() == ISD::UNDEF)
97 return DAG.getUNDEF(ResultVT);
99 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
100 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
102 // This is the index of the first element of the vectorWidth-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
107 // If the input is a buildvector just emit a smaller one.
108 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
109 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
110 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
113 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
114 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
117 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
118 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
119 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
120 /// instructions or a simple subregister reference. Idx is an index in the
121 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
122 /// lowering EXTRACT_VECTOR_ELT operations easier.
123 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
124 SelectionDAG &DAG, SDLoc dl) {
125 assert((Vec.getValueType().is256BitVector() ||
126 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
127 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
130 /// Generate a DAG to grab 256-bits from a 512-bit vector.
131 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
132 SelectionDAG &DAG, SDLoc dl) {
133 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
134 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
137 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
138 unsigned IdxVal, SelectionDAG &DAG,
139 SDLoc dl, unsigned vectorWidth) {
140 assert((vectorWidth == 128 || vectorWidth == 256) &&
141 "Unsupported vector width");
142 // Inserting UNDEF is Result
143 if (Vec.getOpcode() == ISD::UNDEF)
145 EVT VT = Vec.getValueType();
146 EVT ElVT = VT.getVectorElementType();
147 EVT ResultVT = Result.getValueType();
149 // Insert the relevant vectorWidth bits.
150 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
152 // This is the index of the first element of the vectorWidth-bit chunk
154 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
157 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
158 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
161 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
162 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
163 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
164 /// simple superregister reference. Idx is an index in the 128 bits
165 /// we want. It need not be aligned to a 128-bit boundary. That makes
166 /// lowering INSERT_VECTOR_ELT operations easier.
167 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
168 SelectionDAG &DAG,SDLoc dl) {
169 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
170 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
173 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
174 SelectionDAG &DAG, SDLoc dl) {
175 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
176 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
179 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
180 /// instructions. This is used because creating CONCAT_VECTOR nodes of
181 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
182 /// large BUILD_VECTORS.
183 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
184 unsigned NumElems, SelectionDAG &DAG,
186 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
187 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
190 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
191 unsigned NumElems, SelectionDAG &DAG,
193 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
194 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
197 // FIXME: This should stop caching the target machine as soon as
198 // we can remove resetOperationActions et al.
199 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM)
200 : TargetLowering(TM) {
201 Subtarget = &TM.getSubtarget<X86Subtarget>();
202 X86ScalarSSEf64 = Subtarget->hasSSE2();
203 X86ScalarSSEf32 = Subtarget->hasSSE1();
204 TD = getDataLayout();
206 resetOperationActions();
209 void X86TargetLowering::resetOperationActions() {
210 const TargetMachine &TM = getTargetMachine();
211 static bool FirstTimeThrough = true;
213 // If none of the target options have changed, then we don't need to reset the
214 // operation actions.
215 if (!FirstTimeThrough && TO == TM.Options) return;
217 if (!FirstTimeThrough) {
218 // Reinitialize the actions.
220 FirstTimeThrough = false;
225 // Set up the TargetLowering object.
226 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
228 // X86 is weird. It always uses i8 for shift amounts and setcc results.
229 setBooleanContents(ZeroOrOneBooleanContent);
230 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
233 // For 64-bit, since we have so many registers, use the ILP scheduler.
234 // For 32-bit, use the register pressure specific scheduling.
235 // For Atom, always use ILP scheduling.
236 if (Subtarget->isAtom())
237 setSchedulingPreference(Sched::ILP);
238 else if (Subtarget->is64Bit())
239 setSchedulingPreference(Sched::ILP);
241 setSchedulingPreference(Sched::RegPressure);
242 const X86RegisterInfo *RegInfo =
243 TM.getSubtarget<X86Subtarget>().getRegisterInfo();
244 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
246 // Bypass expensive divides on Atom when compiling with O2.
247 if (TM.getOptLevel() >= CodeGenOpt::Default) {
248 if (Subtarget->hasSlowDivide32())
249 addBypassSlowDiv(32, 8);
250 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
251 addBypassSlowDiv(64, 16);
254 if (Subtarget->isTargetKnownWindowsMSVC()) {
255 // Setup Windows compiler runtime calls.
256 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
257 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
258 setLibcallName(RTLIB::SREM_I64, "_allrem");
259 setLibcallName(RTLIB::UREM_I64, "_aullrem");
260 setLibcallName(RTLIB::MUL_I64, "_allmul");
261 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
262 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
263 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
264 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
265 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
267 // The _ftol2 runtime function has an unusual calling conv, which
268 // is modeled by a special pseudo-instruction.
269 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
270 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
271 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
272 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
275 if (Subtarget->isTargetDarwin()) {
276 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
277 setUseUnderscoreSetJmp(false);
278 setUseUnderscoreLongJmp(false);
279 } else if (Subtarget->isTargetWindowsGNU()) {
280 // MS runtime is weird: it exports _setjmp, but longjmp!
281 setUseUnderscoreSetJmp(true);
282 setUseUnderscoreLongJmp(false);
284 setUseUnderscoreSetJmp(true);
285 setUseUnderscoreLongJmp(true);
288 // Set up the register classes.
289 addRegisterClass(MVT::i8, &X86::GR8RegClass);
290 addRegisterClass(MVT::i16, &X86::GR16RegClass);
291 addRegisterClass(MVT::i32, &X86::GR32RegClass);
292 if (Subtarget->is64Bit())
293 addRegisterClass(MVT::i64, &X86::GR64RegClass);
295 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
297 // We don't accept any truncstore of integer registers.
298 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
299 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
300 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
301 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
302 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
303 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
305 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
307 // SETOEQ and SETUNE require checking two conditions.
308 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
310 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
311 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
312 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
313 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
315 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
317 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
318 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
319 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
321 if (Subtarget->is64Bit()) {
322 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
323 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
324 } else if (!TM.Options.UseSoftFloat) {
325 // We have an algorithm for SSE2->double, and we turn this into a
326 // 64-bit FILD followed by conditional FADD for other targets.
327 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
328 // We have an algorithm for SSE2, and we turn this into a 64-bit
329 // FILD for other targets.
330 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
333 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
335 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
336 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
338 if (!TM.Options.UseSoftFloat) {
339 // SSE has no i16 to fp conversion, only i32
340 if (X86ScalarSSEf32) {
341 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
342 // f32 and f64 cases are Legal, f80 case is not
343 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
345 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
346 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
349 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
350 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
353 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
354 // are Legal, f80 is custom lowered.
355 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
356 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
358 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
360 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
361 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
363 if (X86ScalarSSEf32) {
364 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
365 // f32 and f64 cases are Legal, f80 case is not
366 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
368 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
369 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
372 // Handle FP_TO_UINT by promoting the destination to a larger signed
374 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
375 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
376 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
378 if (Subtarget->is64Bit()) {
379 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
380 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
381 } else if (!TM.Options.UseSoftFloat) {
382 // Since AVX is a superset of SSE3, only check for SSE here.
383 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
384 // Expand FP_TO_UINT into a select.
385 // FIXME: We would like to use a Custom expander here eventually to do
386 // the optimal thing for SSE vs. the default expansion in the legalizer.
387 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
389 // With SSE3 we can use fisttpll to convert to a signed i64; without
390 // SSE, we're stuck with a fistpll.
391 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
394 if (isTargetFTOL()) {
395 // Use the _ftol2 runtime function, which has a pseudo-instruction
396 // to handle its weird calling convention.
397 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
400 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
401 if (!X86ScalarSSEf64) {
402 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
403 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
404 if (Subtarget->is64Bit()) {
405 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
406 // Without SSE, i64->f64 goes through memory.
407 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
411 // Scalar integer divide and remainder are lowered to use operations that
412 // produce two results, to match the available instructions. This exposes
413 // the two-result form to trivial CSE, which is able to combine x/y and x%y
414 // into a single instruction.
416 // Scalar integer multiply-high is also lowered to use two-result
417 // operations, to match the available instructions. However, plain multiply
418 // (low) operations are left as Legal, as there are single-result
419 // instructions for this in x86. Using the two-result multiply instructions
420 // when both high and low results are needed must be arranged by dagcombine.
421 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
423 setOperationAction(ISD::MULHS, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::SDIV, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UREM, VT, Expand);
430 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
431 setOperationAction(ISD::ADDC, VT, Custom);
432 setOperationAction(ISD::ADDE, VT, Custom);
433 setOperationAction(ISD::SUBC, VT, Custom);
434 setOperationAction(ISD::SUBE, VT, Custom);
437 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
438 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
439 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
440 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
441 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
442 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
443 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
444 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
445 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
446 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
447 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
448 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
449 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
450 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
451 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
452 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
453 if (Subtarget->is64Bit())
454 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
455 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
456 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
457 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
458 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
459 setOperationAction(ISD::FREM , MVT::f32 , Expand);
460 setOperationAction(ISD::FREM , MVT::f64 , Expand);
461 setOperationAction(ISD::FREM , MVT::f80 , Expand);
462 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
464 // Promote the i8 variants and force them on up to i32 which has a shorter
466 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
467 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
468 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
469 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
470 if (Subtarget->hasBMI()) {
471 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
472 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
476 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
477 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
478 if (Subtarget->is64Bit())
479 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
482 if (Subtarget->hasLZCNT()) {
483 // When promoting the i8 variants, force them to i32 for a shorter
485 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
486 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
487 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
488 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
489 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
490 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
491 if (Subtarget->is64Bit())
492 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
494 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
495 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
496 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
497 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
498 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
499 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
500 if (Subtarget->is64Bit()) {
501 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
502 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
506 // Special handling for half-precision floating point conversions.
507 // If we don't have F16C support, then lower half float conversions
508 // into library calls.
509 if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {
510 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
511 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
514 // There's never any support for operations beyond MVT::f32.
515 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
516 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
517 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
518 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
520 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
521 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
522 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
523 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
525 if (Subtarget->hasPOPCNT()) {
526 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
528 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
529 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
530 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
531 if (Subtarget->is64Bit())
532 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
535 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
537 if (!Subtarget->hasMOVBE())
538 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
540 // These should be promoted to a larger select which is supported.
541 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
542 // X86 wants to expand cmov itself.
543 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
544 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
545 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
546 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
547 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
548 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
549 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
550 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
551 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
552 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
553 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
554 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
555 if (Subtarget->is64Bit()) {
556 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
557 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
559 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
560 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
561 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
562 // support continuation, user-level threading, and etc.. As a result, no
563 // other SjLj exception interfaces are implemented and please don't build
564 // your own exception handling based on them.
565 // LLVM/Clang supports zero-cost DWARF exception handling.
566 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
567 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
570 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
571 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
572 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
573 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
574 if (Subtarget->is64Bit())
575 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
576 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
577 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
578 if (Subtarget->is64Bit()) {
579 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
580 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
581 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
582 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
583 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
585 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
586 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
587 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
588 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
589 if (Subtarget->is64Bit()) {
590 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
591 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
592 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
595 if (Subtarget->hasSSE1())
596 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
598 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
600 // Expand certain atomics
601 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
603 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
604 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
605 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
608 if (Subtarget->hasCmpxchg16b()) {
609 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
612 // FIXME - use subtarget debug flags
613 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
614 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
615 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
618 if (Subtarget->is64Bit()) {
619 setExceptionPointerRegister(X86::RAX);
620 setExceptionSelectorRegister(X86::RDX);
622 setExceptionPointerRegister(X86::EAX);
623 setExceptionSelectorRegister(X86::EDX);
625 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
626 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
628 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
629 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
631 setOperationAction(ISD::TRAP, MVT::Other, Legal);
632 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
634 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
635 setOperationAction(ISD::VASTART , MVT::Other, Custom);
636 setOperationAction(ISD::VAEND , MVT::Other, Expand);
637 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
638 // TargetInfo::X86_64ABIBuiltinVaList
639 setOperationAction(ISD::VAARG , MVT::Other, Custom);
640 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
642 // TargetInfo::CharPtrBuiltinVaList
643 setOperationAction(ISD::VAARG , MVT::Other, Expand);
644 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
647 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
648 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
652 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
653 // f32 and f64 use SSE.
654 // Set up the FP register classes.
655 addRegisterClass(MVT::f32, &X86::FR32RegClass);
656 addRegisterClass(MVT::f64, &X86::FR64RegClass);
658 // Use ANDPD to simulate FABS.
659 setOperationAction(ISD::FABS , MVT::f64, Custom);
660 setOperationAction(ISD::FABS , MVT::f32, Custom);
662 // Use XORP to simulate FNEG.
663 setOperationAction(ISD::FNEG , MVT::f64, Custom);
664 setOperationAction(ISD::FNEG , MVT::f32, Custom);
666 // Use ANDPD and ORPD to simulate FCOPYSIGN.
667 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
668 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
670 // Lower this to FGETSIGNx86 plus an AND.
671 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
672 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
674 // We don't support sin/cos/fmod
675 setOperationAction(ISD::FSIN , MVT::f64, Expand);
676 setOperationAction(ISD::FCOS , MVT::f64, Expand);
677 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 setOperationAction(ISD::FSIN , MVT::f32, Expand);
679 setOperationAction(ISD::FCOS , MVT::f32, Expand);
680 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
682 // Expand FP immediates into loads from the stack, except for the special
684 addLegalFPImmediate(APFloat(+0.0)); // xorpd
685 addLegalFPImmediate(APFloat(+0.0f)); // xorps
686 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
687 // Use SSE for f32, x87 for f64.
688 // Set up the FP register classes.
689 addRegisterClass(MVT::f32, &X86::FR32RegClass);
690 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
692 // Use ANDPS to simulate FABS.
693 setOperationAction(ISD::FABS , MVT::f32, Custom);
695 // Use XORP to simulate FNEG.
696 setOperationAction(ISD::FNEG , MVT::f32, Custom);
698 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
700 // Use ANDPS and ORPS to simulate FCOPYSIGN.
701 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
702 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
704 // We don't support sin/cos/fmod
705 setOperationAction(ISD::FSIN , MVT::f32, Expand);
706 setOperationAction(ISD::FCOS , MVT::f32, Expand);
707 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
709 // Special cases we handle for FP constants.
710 addLegalFPImmediate(APFloat(+0.0f)); // xorps
711 addLegalFPImmediate(APFloat(+0.0)); // FLD0
712 addLegalFPImmediate(APFloat(+1.0)); // FLD1
713 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
714 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
716 if (!TM.Options.UnsafeFPMath) {
717 setOperationAction(ISD::FSIN , MVT::f64, Expand);
718 setOperationAction(ISD::FCOS , MVT::f64, Expand);
719 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
721 } else if (!TM.Options.UseSoftFloat) {
722 // f32 and f64 in x87.
723 // Set up the FP register classes.
724 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
725 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
727 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
728 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
729 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
730 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
732 if (!TM.Options.UnsafeFPMath) {
733 setOperationAction(ISD::FSIN , MVT::f64, Expand);
734 setOperationAction(ISD::FSIN , MVT::f32, Expand);
735 setOperationAction(ISD::FCOS , MVT::f64, Expand);
736 setOperationAction(ISD::FCOS , MVT::f32, Expand);
737 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
738 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
740 addLegalFPImmediate(APFloat(+0.0)); // FLD0
741 addLegalFPImmediate(APFloat(+1.0)); // FLD1
742 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
743 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
744 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
745 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
746 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
747 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
750 // We don't support FMA.
751 setOperationAction(ISD::FMA, MVT::f64, Expand);
752 setOperationAction(ISD::FMA, MVT::f32, Expand);
754 // Long double always uses X87.
755 if (!TM.Options.UseSoftFloat) {
756 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
757 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
758 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
760 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
761 addLegalFPImmediate(TmpFlt); // FLD0
763 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
766 APFloat TmpFlt2(+1.0);
767 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
769 addLegalFPImmediate(TmpFlt2); // FLD1
770 TmpFlt2.changeSign();
771 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
774 if (!TM.Options.UnsafeFPMath) {
775 setOperationAction(ISD::FSIN , MVT::f80, Expand);
776 setOperationAction(ISD::FCOS , MVT::f80, Expand);
777 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
780 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
781 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
782 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
783 setOperationAction(ISD::FRINT, MVT::f80, Expand);
784 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
785 setOperationAction(ISD::FMA, MVT::f80, Expand);
788 // Always use a library call for pow.
789 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
790 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
791 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
793 setOperationAction(ISD::FLOG, MVT::f80, Expand);
794 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
795 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
796 setOperationAction(ISD::FEXP, MVT::f80, Expand);
797 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
798 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
799 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
801 // First set operation action for all vector types to either promote
802 // (for widening) or expand (for scalarization). Then we will selectively
803 // turn on ones that can be effectively codegen'd.
804 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
805 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
806 MVT VT = (MVT::SimpleValueType)i;
807 setOperationAction(ISD::ADD , VT, Expand);
808 setOperationAction(ISD::SUB , VT, Expand);
809 setOperationAction(ISD::FADD, VT, Expand);
810 setOperationAction(ISD::FNEG, VT, Expand);
811 setOperationAction(ISD::FSUB, VT, Expand);
812 setOperationAction(ISD::MUL , VT, Expand);
813 setOperationAction(ISD::FMUL, VT, Expand);
814 setOperationAction(ISD::SDIV, VT, Expand);
815 setOperationAction(ISD::UDIV, VT, Expand);
816 setOperationAction(ISD::FDIV, VT, Expand);
817 setOperationAction(ISD::SREM, VT, Expand);
818 setOperationAction(ISD::UREM, VT, Expand);
819 setOperationAction(ISD::LOAD, VT, Expand);
820 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
821 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
822 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
823 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
824 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
825 setOperationAction(ISD::FABS, VT, Expand);
826 setOperationAction(ISD::FSIN, VT, Expand);
827 setOperationAction(ISD::FSINCOS, VT, Expand);
828 setOperationAction(ISD::FCOS, VT, Expand);
829 setOperationAction(ISD::FSINCOS, VT, Expand);
830 setOperationAction(ISD::FREM, VT, Expand);
831 setOperationAction(ISD::FMA, VT, Expand);
832 setOperationAction(ISD::FPOWI, VT, Expand);
833 setOperationAction(ISD::FSQRT, VT, Expand);
834 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
835 setOperationAction(ISD::FFLOOR, VT, Expand);
836 setOperationAction(ISD::FCEIL, VT, Expand);
837 setOperationAction(ISD::FTRUNC, VT, Expand);
838 setOperationAction(ISD::FRINT, VT, Expand);
839 setOperationAction(ISD::FNEARBYINT, VT, Expand);
840 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
841 setOperationAction(ISD::MULHS, VT, Expand);
842 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
843 setOperationAction(ISD::MULHU, VT, Expand);
844 setOperationAction(ISD::SDIVREM, VT, Expand);
845 setOperationAction(ISD::UDIVREM, VT, Expand);
846 setOperationAction(ISD::FPOW, VT, Expand);
847 setOperationAction(ISD::CTPOP, VT, Expand);
848 setOperationAction(ISD::CTTZ, VT, Expand);
849 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
850 setOperationAction(ISD::CTLZ, VT, Expand);
851 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
852 setOperationAction(ISD::SHL, VT, Expand);
853 setOperationAction(ISD::SRA, VT, Expand);
854 setOperationAction(ISD::SRL, VT, Expand);
855 setOperationAction(ISD::ROTL, VT, Expand);
856 setOperationAction(ISD::ROTR, VT, Expand);
857 setOperationAction(ISD::BSWAP, VT, Expand);
858 setOperationAction(ISD::SETCC, VT, Expand);
859 setOperationAction(ISD::FLOG, VT, Expand);
860 setOperationAction(ISD::FLOG2, VT, Expand);
861 setOperationAction(ISD::FLOG10, VT, Expand);
862 setOperationAction(ISD::FEXP, VT, Expand);
863 setOperationAction(ISD::FEXP2, VT, Expand);
864 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
865 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
866 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
867 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
868 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
869 setOperationAction(ISD::TRUNCATE, VT, Expand);
870 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
871 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
872 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
873 setOperationAction(ISD::VSELECT, VT, Expand);
874 setOperationAction(ISD::SELECT_CC, VT, Expand);
875 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
876 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
877 setTruncStoreAction(VT,
878 (MVT::SimpleValueType)InnerVT, Expand);
879 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
880 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
882 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like types,
883 // we have to deal with them whether we ask for Expansion or not. Setting
884 // Expand causes its own optimisation problems though, so leave them legal.
885 if (VT.getVectorElementType() == MVT::i1)
886 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
889 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
890 // with -msoft-float, disable use of MMX as well.
891 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
892 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
893 // No operations on x86mmx supported, everything uses intrinsics.
896 // MMX-sized vectors (other than x86mmx) are expected to be expanded
897 // into smaller operations.
898 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
899 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
900 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
901 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
902 setOperationAction(ISD::AND, MVT::v8i8, Expand);
903 setOperationAction(ISD::AND, MVT::v4i16, Expand);
904 setOperationAction(ISD::AND, MVT::v2i32, Expand);
905 setOperationAction(ISD::AND, MVT::v1i64, Expand);
906 setOperationAction(ISD::OR, MVT::v8i8, Expand);
907 setOperationAction(ISD::OR, MVT::v4i16, Expand);
908 setOperationAction(ISD::OR, MVT::v2i32, Expand);
909 setOperationAction(ISD::OR, MVT::v1i64, Expand);
910 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
911 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
912 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
913 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
914 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
915 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
916 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
917 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
918 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
919 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
920 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
921 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
922 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
923 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
924 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
925 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
926 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
928 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
929 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
931 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
932 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
933 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
934 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
935 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
936 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
937 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
938 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
939 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
940 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
941 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
942 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
943 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
946 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
947 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
949 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
950 // registers cannot be used even for integer operations.
951 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
952 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
953 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
954 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
956 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
957 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
958 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
959 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
960 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
961 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
962 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
963 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
964 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
965 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
966 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
967 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
968 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
969 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
970 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
971 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
972 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
973 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
974 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
975 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
976 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
977 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
979 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
980 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
981 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
982 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
984 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
985 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
986 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
987 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
988 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
990 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
991 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
992 MVT VT = (MVT::SimpleValueType)i;
993 // Do not attempt to custom lower non-power-of-2 vectors
994 if (!isPowerOf2_32(VT.getVectorNumElements()))
996 // Do not attempt to custom lower non-128-bit vectors
997 if (!VT.is128BitVector())
999 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1000 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1004 // We support custom legalizing of sext and anyext loads for specific
1005 // memory vector types which we can load as a scalar (or sequence of
1006 // scalars) and extend in-register to a legal 128-bit vector type. For sext
1007 // loads these must work with a single scalar load.
1008 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Custom);
1009 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Custom);
1010 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i8, Custom);
1011 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Custom);
1012 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Custom);
1013 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, Custom);
1014 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Custom);
1015 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Custom);
1016 setLoadExtAction(ISD::EXTLOAD, MVT::v8i8, Custom);
1018 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
1019 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
1020 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
1021 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
1025 if (Subtarget->is64Bit()) {
1026 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1027 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1030 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
1031 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
1032 MVT VT = (MVT::SimpleValueType)i;
1034 // Do not attempt to promote non-128-bit vectors
1035 if (!VT.is128BitVector())
1038 setOperationAction(ISD::AND, VT, Promote);
1039 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
1040 setOperationAction(ISD::OR, VT, Promote);
1041 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
1042 setOperationAction(ISD::XOR, VT, Promote);
1043 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
1044 setOperationAction(ISD::LOAD, VT, Promote);
1045 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
1046 setOperationAction(ISD::SELECT, VT, Promote);
1047 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
1050 // Custom lower v2i64 and v2f64 selects.
1051 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
1052 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
1053 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
1054 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
1056 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1057 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1059 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
1060 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
1061 // As there is no 64-bit GPR available, we need build a special custom
1062 // sequence to convert from v2i32 to v2f32.
1063 if (!Subtarget->is64Bit())
1064 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
1066 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
1067 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
1069 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1071 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
1072 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
1073 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
1076 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {
1077 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1078 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1079 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1080 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1081 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1088 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1089 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1090 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1091 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1092 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1093 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1094 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1095 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1096 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1097 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1099 // FIXME: Do we need to handle scalar-to-vector here?
1100 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1102 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
1103 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
1104 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
1105 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
1106 setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
1107 // There is no BLENDI for byte vectors. We don't need to custom lower
1108 // some vselects for now.
1109 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1111 // SSE41 brings specific instructions for doing vector sign extend even in
1112 // cases where we don't have SRA.
1113 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Custom);
1114 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Custom);
1115 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, Custom);
1117 // i8 and i16 vectors are custom because the source register and source
1118 // source memory operand types are not the same width. f32 vectors are
1119 // custom since the immediate controlling the insert encodes additional
1121 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1122 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1123 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1124 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1126 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1127 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1128 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1129 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1131 // FIXME: these should be Legal, but that's only for the case where
1132 // the index is constant. For now custom expand to deal with that.
1133 if (Subtarget->is64Bit()) {
1134 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1135 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1139 if (Subtarget->hasSSE2()) {
1140 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1141 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1143 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1144 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1146 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1147 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1149 // In the customized shift lowering, the legal cases in AVX2 will be
1151 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1152 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1154 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1155 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1157 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1160 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1161 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1162 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1163 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1164 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1165 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1166 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1168 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1169 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1170 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1172 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1173 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1174 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1175 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1176 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1177 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1178 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1179 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1180 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1181 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1182 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1183 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1185 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1186 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1187 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1188 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1189 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1190 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1191 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1192 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1193 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1194 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1195 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1196 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1198 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1199 // even though v8i16 is a legal type.
1200 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1201 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1202 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1204 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1205 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1206 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1208 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1209 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1211 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1213 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1214 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1216 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1217 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1220 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1222 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1223 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1224 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1225 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1227 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1228 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1229 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1231 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1232 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1233 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1234 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1236 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1237 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1238 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1239 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1240 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1241 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1242 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1243 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1244 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1245 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1246 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1247 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1249 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1250 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1251 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1252 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1253 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1254 setOperationAction(ISD::FMA, MVT::f32, Legal);
1255 setOperationAction(ISD::FMA, MVT::f64, Legal);
1258 if (Subtarget->hasInt256()) {
1259 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1260 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1261 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1262 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1264 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1265 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1266 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1267 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1269 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1270 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1271 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1272 // Don't lower v32i8 because there is no 128-bit byte mul
1274 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1275 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1276 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1277 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1279 setOperationAction(ISD::VSELECT, MVT::v16i16, Custom);
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1283 // when we have a 256bit-wide blend with immediate.
1284 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1286 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1287 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1288 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1289 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1291 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1292 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1293 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1294 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1296 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1297 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1298 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1299 // Don't lower v32i8 because there is no 128-bit byte mul
1302 // In the customized shift lowering, the legal cases in AVX2 will be
1304 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1305 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1307 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1308 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1310 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1312 // Custom lower several nodes for 256-bit types.
1313 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1314 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1315 MVT VT = (MVT::SimpleValueType)i;
1317 // Extract subvector is special because the value type
1318 // (result) is 128-bit but the source is 256-bit wide.
1319 if (VT.is128BitVector()) {
1320 if (VT.getScalarSizeInBits() >= 32) {
1321 setOperationAction(ISD::MLOAD, VT, Custom);
1322 setOperationAction(ISD::MSTORE, VT, Custom);
1324 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1326 // Do not attempt to custom lower other non-256-bit vectors
1327 if (!VT.is256BitVector())
1330 if (VT.getScalarSizeInBits() >= 32) {
1331 setOperationAction(ISD::MLOAD, VT, Legal);
1332 setOperationAction(ISD::MSTORE, VT, Legal);
1334 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1335 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1336 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1337 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1338 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1339 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1340 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1343 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1344 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1345 MVT VT = (MVT::SimpleValueType)i;
1347 // Do not attempt to promote non-256-bit vectors
1348 if (!VT.is256BitVector())
1351 setOperationAction(ISD::AND, VT, Promote);
1352 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1353 setOperationAction(ISD::OR, VT, Promote);
1354 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1355 setOperationAction(ISD::XOR, VT, Promote);
1356 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1357 setOperationAction(ISD::LOAD, VT, Promote);
1358 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1359 setOperationAction(ISD::SELECT, VT, Promote);
1360 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1364 if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {
1365 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1366 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1367 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1368 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1370 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1371 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1372 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1374 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1375 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1376 setOperationAction(ISD::XOR, MVT::i1, Legal);
1377 setOperationAction(ISD::OR, MVT::i1, Legal);
1378 setOperationAction(ISD::AND, MVT::i1, Legal);
1379 setLoadExtAction(ISD::EXTLOAD, MVT::v8f32, Legal);
1380 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1381 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1382 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1383 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1384 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1386 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1387 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1388 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1389 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1390 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1391 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1393 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1394 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1395 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1396 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1397 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1398 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1399 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1400 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1402 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1403 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1406 if (Subtarget->is64Bit()) {
1407 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1408 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1409 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1410 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1412 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1413 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1414 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1418 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1419 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1422 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1423 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1424 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1425 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1427 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1428 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1429 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1432 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1433 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1434 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1441 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1442 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1443 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1444 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1445 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1446 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1448 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1449 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1451 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1454 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1455 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1456 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1458 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1459 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1460 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1461 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1463 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1464 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1466 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1467 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1469 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1471 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1472 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1474 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1477 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1478 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1480 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1481 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1482 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1483 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1484 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1485 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1487 if (Subtarget->hasCDI()) {
1488 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1489 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1492 // Custom lower several nodes.
1493 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1494 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1495 MVT VT = (MVT::SimpleValueType)i;
1497 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1498 // Extract subvector is special because the value type
1499 // (result) is 256/128-bit but the source is 512-bit wide.
1500 if (VT.is128BitVector() || VT.is256BitVector()) {
1501 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1502 if ( EltSize >= 32) {
1503 setOperationAction(ISD::MLOAD, VT, Legal);
1504 setOperationAction(ISD::MSTORE, VT, Legal);
1507 if (VT.getVectorElementType() == MVT::i1)
1508 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1510 // Do not attempt to custom lower other non-512-bit vectors
1511 if (!VT.is512BitVector())
1514 if ( EltSize >= 32) {
1515 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1516 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1517 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1518 setOperationAction(ISD::VSELECT, VT, Legal);
1519 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1520 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1521 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1522 setOperationAction(ISD::MLOAD, VT, Legal);
1523 setOperationAction(ISD::MSTORE, VT, Legal);
1526 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1527 MVT VT = (MVT::SimpleValueType)i;
1529 // Do not attempt to promote non-256-bit vectors.
1530 if (!VT.is512BitVector())
1533 setOperationAction(ISD::SELECT, VT, Promote);
1534 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1538 if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
1539 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1540 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1542 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1543 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1545 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1546 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1547 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1548 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1550 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1551 const MVT VT = (MVT::SimpleValueType)i;
1553 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1555 // Do not attempt to promote non-256-bit vectors.
1556 if (!VT.is512BitVector())
1560 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1561 setOperationAction(ISD::VSELECT, VT, Legal);
1566 if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {
1567 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1568 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1570 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1571 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1572 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Legal);
1575 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1576 // of this type with custom code.
1577 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1578 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1579 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1583 // We want to custom lower some of our intrinsics.
1584 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1585 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1586 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1587 if (!Subtarget->is64Bit())
1588 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1590 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1591 // handle type legalization for these operations here.
1593 // FIXME: We really should do custom legalization for addition and
1594 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1595 // than generic legalization for 64-bit multiplication-with-overflow, though.
1596 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1597 // Add/Sub/Mul with overflow operations are custom lowered.
1599 setOperationAction(ISD::SADDO, VT, Custom);
1600 setOperationAction(ISD::UADDO, VT, Custom);
1601 setOperationAction(ISD::SSUBO, VT, Custom);
1602 setOperationAction(ISD::USUBO, VT, Custom);
1603 setOperationAction(ISD::SMULO, VT, Custom);
1604 setOperationAction(ISD::UMULO, VT, Custom);
1608 if (!Subtarget->is64Bit()) {
1609 // These libcalls are not available in 32-bit.
1610 setLibcallName(RTLIB::SHL_I128, nullptr);
1611 setLibcallName(RTLIB::SRL_I128, nullptr);
1612 setLibcallName(RTLIB::SRA_I128, nullptr);
1615 // Combine sin / cos into one node or libcall if possible.
1616 if (Subtarget->hasSinCos()) {
1617 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1618 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1619 if (Subtarget->isTargetDarwin()) {
1620 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1621 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1622 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1623 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1627 if (Subtarget->isTargetWin64()) {
1628 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1629 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1630 setOperationAction(ISD::SREM, MVT::i128, Custom);
1631 setOperationAction(ISD::UREM, MVT::i128, Custom);
1632 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1633 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1636 // We have target-specific dag combine patterns for the following nodes:
1637 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1638 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1639 setTargetDAGCombine(ISD::VSELECT);
1640 setTargetDAGCombine(ISD::SELECT);
1641 setTargetDAGCombine(ISD::SHL);
1642 setTargetDAGCombine(ISD::SRA);
1643 setTargetDAGCombine(ISD::SRL);
1644 setTargetDAGCombine(ISD::OR);
1645 setTargetDAGCombine(ISD::AND);
1646 setTargetDAGCombine(ISD::ADD);
1647 setTargetDAGCombine(ISD::FADD);
1648 setTargetDAGCombine(ISD::FSUB);
1649 setTargetDAGCombine(ISD::FMA);
1650 setTargetDAGCombine(ISD::SUB);
1651 setTargetDAGCombine(ISD::LOAD);
1652 setTargetDAGCombine(ISD::STORE);
1653 setTargetDAGCombine(ISD::ZERO_EXTEND);
1654 setTargetDAGCombine(ISD::ANY_EXTEND);
1655 setTargetDAGCombine(ISD::SIGN_EXTEND);
1656 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1657 setTargetDAGCombine(ISD::TRUNCATE);
1658 setTargetDAGCombine(ISD::SINT_TO_FP);
1659 setTargetDAGCombine(ISD::SETCC);
1660 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1661 setTargetDAGCombine(ISD::BUILD_VECTOR);
1662 if (Subtarget->is64Bit())
1663 setTargetDAGCombine(ISD::MUL);
1664 setTargetDAGCombine(ISD::XOR);
1666 computeRegisterProperties();
1668 // On Darwin, -Os means optimize for size without hurting performance,
1669 // do not reduce the limit.
1670 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1671 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1672 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1673 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1674 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1675 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1676 setPrefLoopAlignment(4); // 2^4 bytes.
1678 // Predictable cmov don't hurt on atom because it's in-order.
1679 PredictableSelectIsExpensive = !Subtarget->isAtom();
1681 setPrefFunctionAlignment(4); // 2^4 bytes.
1683 verifyIntrinsicTables();
1686 // This has so far only been implemented for 64-bit MachO.
1687 bool X86TargetLowering::useLoadStackGuardNode() const {
1688 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1691 TargetLoweringBase::LegalizeTypeAction
1692 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1693 if (ExperimentalVectorWideningLegalization &&
1694 VT.getVectorNumElements() != 1 &&
1695 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1696 return TypeWidenVector;
1698 return TargetLoweringBase::getPreferredVectorAction(VT);
1701 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1703 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1705 const unsigned NumElts = VT.getVectorNumElements();
1706 const EVT EltVT = VT.getVectorElementType();
1707 if (VT.is512BitVector()) {
1708 if (Subtarget->hasAVX512())
1709 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1710 EltVT == MVT::f32 || EltVT == MVT::f64)
1712 case 8: return MVT::v8i1;
1713 case 16: return MVT::v16i1;
1715 if (Subtarget->hasBWI())
1716 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1718 case 32: return MVT::v32i1;
1719 case 64: return MVT::v64i1;
1723 if (VT.is256BitVector() || VT.is128BitVector()) {
1724 if (Subtarget->hasVLX())
1725 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1726 EltVT == MVT::f32 || EltVT == MVT::f64)
1728 case 2: return MVT::v2i1;
1729 case 4: return MVT::v4i1;
1730 case 8: return MVT::v8i1;
1732 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1733 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1735 case 8: return MVT::v8i1;
1736 case 16: return MVT::v16i1;
1737 case 32: return MVT::v32i1;
1741 return VT.changeVectorElementTypeToInteger();
1744 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1745 /// the desired ByVal argument alignment.
1746 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1749 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1750 if (VTy->getBitWidth() == 128)
1752 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1753 unsigned EltAlign = 0;
1754 getMaxByValAlign(ATy->getElementType(), EltAlign);
1755 if (EltAlign > MaxAlign)
1756 MaxAlign = EltAlign;
1757 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1758 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1759 unsigned EltAlign = 0;
1760 getMaxByValAlign(STy->getElementType(i), EltAlign);
1761 if (EltAlign > MaxAlign)
1762 MaxAlign = EltAlign;
1769 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1770 /// function arguments in the caller parameter area. For X86, aggregates
1771 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1772 /// are at 4-byte boundaries.
1773 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1774 if (Subtarget->is64Bit()) {
1775 // Max of 8 and alignment of type.
1776 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1783 if (Subtarget->hasSSE1())
1784 getMaxByValAlign(Ty, Align);
1788 /// getOptimalMemOpType - Returns the target specific optimal type for load
1789 /// and store operations as a result of memset, memcpy, and memmove
1790 /// lowering. If DstAlign is zero that means it's safe to destination
1791 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1792 /// means there isn't a need to check it against alignment requirement,
1793 /// probably because the source does not need to be loaded. If 'IsMemset' is
1794 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1795 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1796 /// source is constant so it does not need to be loaded.
1797 /// It returns EVT::Other if the type should be determined using generic
1798 /// target-independent logic.
1800 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1801 unsigned DstAlign, unsigned SrcAlign,
1802 bool IsMemset, bool ZeroMemset,
1804 MachineFunction &MF) const {
1805 const Function *F = MF.getFunction();
1806 if ((!IsMemset || ZeroMemset) &&
1807 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1808 Attribute::NoImplicitFloat)) {
1810 (Subtarget->isUnalignedMemAccessFast() ||
1811 ((DstAlign == 0 || DstAlign >= 16) &&
1812 (SrcAlign == 0 || SrcAlign >= 16)))) {
1814 if (Subtarget->hasInt256())
1816 if (Subtarget->hasFp256())
1819 if (Subtarget->hasSSE2())
1821 if (Subtarget->hasSSE1())
1823 } else if (!MemcpyStrSrc && Size >= 8 &&
1824 !Subtarget->is64Bit() &&
1825 Subtarget->hasSSE2()) {
1826 // Do not use f64 to lower memcpy if source is string constant. It's
1827 // better to use i32 to avoid the loads.
1831 if (Subtarget->is64Bit() && Size >= 8)
1836 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1838 return X86ScalarSSEf32;
1839 else if (VT == MVT::f64)
1840 return X86ScalarSSEf64;
1845 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1850 *Fast = Subtarget->isUnalignedMemAccessFast();
1854 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1855 /// current function. The returned value is a member of the
1856 /// MachineJumpTableInfo::JTEntryKind enum.
1857 unsigned X86TargetLowering::getJumpTableEncoding() const {
1858 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1860 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1861 Subtarget->isPICStyleGOT())
1862 return MachineJumpTableInfo::EK_Custom32;
1864 // Otherwise, use the normal jump table encoding heuristics.
1865 return TargetLowering::getJumpTableEncoding();
1869 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1870 const MachineBasicBlock *MBB,
1871 unsigned uid,MCContext &Ctx) const{
1872 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1873 Subtarget->isPICStyleGOT());
1874 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1876 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1877 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1880 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1882 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1883 SelectionDAG &DAG) const {
1884 if (!Subtarget->is64Bit())
1885 // This doesn't have SDLoc associated with it, but is not really the
1886 // same as a Register.
1887 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1891 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1892 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1894 const MCExpr *X86TargetLowering::
1895 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1896 MCContext &Ctx) const {
1897 // X86-64 uses RIP relative addressing based on the jump table label.
1898 if (Subtarget->isPICStyleRIPRel())
1899 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1901 // Otherwise, the reference is relative to the PIC base.
1902 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1905 // FIXME: Why this routine is here? Move to RegInfo!
1906 std::pair<const TargetRegisterClass*, uint8_t>
1907 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1908 const TargetRegisterClass *RRC = nullptr;
1910 switch (VT.SimpleTy) {
1912 return TargetLowering::findRepresentativeClass(VT);
1913 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1914 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1917 RRC = &X86::VR64RegClass;
1919 case MVT::f32: case MVT::f64:
1920 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1921 case MVT::v4f32: case MVT::v2f64:
1922 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1924 RRC = &X86::VR128RegClass;
1927 return std::make_pair(RRC, Cost);
1930 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1931 unsigned &Offset) const {
1932 if (!Subtarget->isTargetLinux())
1935 if (Subtarget->is64Bit()) {
1936 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1938 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1950 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1951 unsigned DestAS) const {
1952 assert(SrcAS != DestAS && "Expected different address spaces!");
1954 return SrcAS < 256 && DestAS < 256;
1957 //===----------------------------------------------------------------------===//
1958 // Return Value Calling Convention Implementation
1959 //===----------------------------------------------------------------------===//
1961 #include "X86GenCallingConv.inc"
1964 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1965 MachineFunction &MF, bool isVarArg,
1966 const SmallVectorImpl<ISD::OutputArg> &Outs,
1967 LLVMContext &Context) const {
1968 SmallVector<CCValAssign, 16> RVLocs;
1969 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1970 return CCInfo.CheckReturn(Outs, RetCC_X86);
1973 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1974 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1979 X86TargetLowering::LowerReturn(SDValue Chain,
1980 CallingConv::ID CallConv, bool isVarArg,
1981 const SmallVectorImpl<ISD::OutputArg> &Outs,
1982 const SmallVectorImpl<SDValue> &OutVals,
1983 SDLoc dl, SelectionDAG &DAG) const {
1984 MachineFunction &MF = DAG.getMachineFunction();
1985 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1987 SmallVector<CCValAssign, 16> RVLocs;
1988 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1989 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1992 SmallVector<SDValue, 6> RetOps;
1993 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1994 // Operand #1 = Bytes To Pop
1995 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1998 // Copy the result values into the output registers.
1999 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2000 CCValAssign &VA = RVLocs[i];
2001 assert(VA.isRegLoc() && "Can only return in registers!");
2002 SDValue ValToCopy = OutVals[i];
2003 EVT ValVT = ValToCopy.getValueType();
2005 // Promote values to the appropriate types.
2006 if (VA.getLocInfo() == CCValAssign::SExt)
2007 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2008 else if (VA.getLocInfo() == CCValAssign::ZExt)
2009 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2010 else if (VA.getLocInfo() == CCValAssign::AExt)
2011 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2012 else if (VA.getLocInfo() == CCValAssign::BCvt)
2013 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
2015 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2016 "Unexpected FP-extend for return value.");
2018 // If this is x86-64, and we disabled SSE, we can't return FP values,
2019 // or SSE or MMX vectors.
2020 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2021 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2022 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2023 report_fatal_error("SSE register return with SSE disabled");
2025 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2026 // llvm-gcc has never done it right and no one has noticed, so this
2027 // should be OK for now.
2028 if (ValVT == MVT::f64 &&
2029 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2030 report_fatal_error("SSE2 register return with SSE2 disabled");
2032 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2033 // the RET instruction and handled by the FP Stackifier.
2034 if (VA.getLocReg() == X86::FP0 ||
2035 VA.getLocReg() == X86::FP1) {
2036 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2037 // change the value to the FP stack register class.
2038 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2039 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2040 RetOps.push_back(ValToCopy);
2041 // Don't emit a copytoreg.
2045 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2046 // which is returned in RAX / RDX.
2047 if (Subtarget->is64Bit()) {
2048 if (ValVT == MVT::x86mmx) {
2049 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2050 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
2051 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2053 // If we don't have SSE2 available, convert to v4f32 so the generated
2054 // register is legal.
2055 if (!Subtarget->hasSSE2())
2056 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
2061 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2062 Flag = Chain.getValue(1);
2063 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2066 // The x86-64 ABIs require that for returning structs by value we copy
2067 // the sret argument into %rax/%eax (depending on ABI) for the return.
2068 // Win32 requires us to put the sret argument to %eax as well.
2069 // We saved the argument into a virtual register in the entry block,
2070 // so now we copy the value out and into %rax/%eax.
2071 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
2072 (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC())) {
2073 MachineFunction &MF = DAG.getMachineFunction();
2074 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2075 unsigned Reg = FuncInfo->getSRetReturnReg();
2077 "SRetReturnReg should have been set in LowerFormalArguments().");
2078 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
2081 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2082 X86::RAX : X86::EAX;
2083 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2084 Flag = Chain.getValue(1);
2086 // RAX/EAX now acts like a return value.
2087 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2090 RetOps[0] = Chain; // Update chain.
2092 // Add the flag if we have it.
2094 RetOps.push_back(Flag);
2096 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2099 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2100 if (N->getNumValues() != 1)
2102 if (!N->hasNUsesOfValue(1, 0))
2105 SDValue TCChain = Chain;
2106 SDNode *Copy = *N->use_begin();
2107 if (Copy->getOpcode() == ISD::CopyToReg) {
2108 // If the copy has a glue operand, we conservatively assume it isn't safe to
2109 // perform a tail call.
2110 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2112 TCChain = Copy->getOperand(0);
2113 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2116 bool HasRet = false;
2117 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2119 if (UI->getOpcode() != X86ISD::RET_FLAG)
2121 // If we are returning more than one value, we can definitely
2122 // not make a tail call see PR19530
2123 if (UI->getNumOperands() > 4)
2125 if (UI->getNumOperands() == 4 &&
2126 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2139 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2140 ISD::NodeType ExtendKind) const {
2142 // TODO: Is this also valid on 32-bit?
2143 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2144 ReturnMVT = MVT::i8;
2146 ReturnMVT = MVT::i32;
2148 EVT MinVT = getRegisterType(Context, ReturnMVT);
2149 return VT.bitsLT(MinVT) ? MinVT : VT;
2152 /// LowerCallResult - Lower the result values of a call into the
2153 /// appropriate copies out of appropriate physical registers.
2156 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2157 CallingConv::ID CallConv, bool isVarArg,
2158 const SmallVectorImpl<ISD::InputArg> &Ins,
2159 SDLoc dl, SelectionDAG &DAG,
2160 SmallVectorImpl<SDValue> &InVals) const {
2162 // Assign locations to each value returned by this call.
2163 SmallVector<CCValAssign, 16> RVLocs;
2164 bool Is64Bit = Subtarget->is64Bit();
2165 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2167 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2169 // Copy all of the result registers out of their specified physreg.
2170 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2171 CCValAssign &VA = RVLocs[i];
2172 EVT CopyVT = VA.getValVT();
2174 // If this is x86-64, and we disabled SSE, we can't return FP values
2175 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2176 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2177 report_fatal_error("SSE register return with SSE disabled");
2180 // If we prefer to use the value in xmm registers, copy it out as f80 and
2181 // use a truncate to move it from fp stack reg to xmm reg.
2182 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2183 isScalarFPTypeInSSEReg(VA.getValVT()))
2186 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2187 CopyVT, InFlag).getValue(1);
2188 SDValue Val = Chain.getValue(0);
2190 if (CopyVT != VA.getValVT())
2191 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2192 // This truncation won't change the value.
2193 DAG.getIntPtrConstant(1));
2195 InFlag = Chain.getValue(2);
2196 InVals.push_back(Val);
2202 //===----------------------------------------------------------------------===//
2203 // C & StdCall & Fast Calling Convention implementation
2204 //===----------------------------------------------------------------------===//
2205 // StdCall calling convention seems to be standard for many Windows' API
2206 // routines and around. It differs from C calling convention just a little:
2207 // callee should clean up the stack, not caller. Symbols should be also
2208 // decorated in some fancy way :) It doesn't support any vector arguments.
2209 // For info on fast calling convention see Fast Calling Convention (tail call)
2210 // implementation LowerX86_32FastCCCallTo.
2212 /// CallIsStructReturn - Determines whether a call uses struct return
2214 enum StructReturnType {
2219 static StructReturnType
2220 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2222 return NotStructReturn;
2224 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2225 if (!Flags.isSRet())
2226 return NotStructReturn;
2227 if (Flags.isInReg())
2228 return RegStructReturn;
2229 return StackStructReturn;
2232 /// ArgsAreStructReturn - Determines whether a function uses struct
2233 /// return semantics.
2234 static StructReturnType
2235 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2237 return NotStructReturn;
2239 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2240 if (!Flags.isSRet())
2241 return NotStructReturn;
2242 if (Flags.isInReg())
2243 return RegStructReturn;
2244 return StackStructReturn;
2247 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2248 /// by "Src" to address "Dst" with size and alignment information specified by
2249 /// the specific parameter attribute. The copy will be passed as a byval
2250 /// function parameter.
2252 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2253 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2255 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2257 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2258 /*isVolatile*/false, /*AlwaysInline=*/true,
2259 MachinePointerInfo(), MachinePointerInfo());
2262 /// IsTailCallConvention - Return true if the calling convention is one that
2263 /// supports tail call optimization.
2264 static bool IsTailCallConvention(CallingConv::ID CC) {
2265 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2266 CC == CallingConv::HiPE);
2269 /// \brief Return true if the calling convention is a C calling convention.
2270 static bool IsCCallConvention(CallingConv::ID CC) {
2271 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2272 CC == CallingConv::X86_64_SysV);
2275 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2276 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2280 CallingConv::ID CalleeCC = CS.getCallingConv();
2281 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2287 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
2288 /// a tailcall target by changing its ABI.
2289 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2290 bool GuaranteedTailCallOpt) {
2291 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2295 X86TargetLowering::LowerMemArgument(SDValue Chain,
2296 CallingConv::ID CallConv,
2297 const SmallVectorImpl<ISD::InputArg> &Ins,
2298 SDLoc dl, SelectionDAG &DAG,
2299 const CCValAssign &VA,
2300 MachineFrameInfo *MFI,
2302 // Create the nodes corresponding to a load from this parameter slot.
2303 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2304 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2305 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2306 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2309 // If value is passed by pointer we have address passed instead of the value
2311 if (VA.getLocInfo() == CCValAssign::Indirect)
2312 ValVT = VA.getLocVT();
2314 ValVT = VA.getValVT();
2316 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2317 // changed with more analysis.
2318 // In case of tail call optimization mark all arguments mutable. Since they
2319 // could be overwritten by lowering of arguments in case of a tail call.
2320 if (Flags.isByVal()) {
2321 unsigned Bytes = Flags.getByValSize();
2322 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2323 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2324 return DAG.getFrameIndex(FI, getPointerTy());
2326 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2327 VA.getLocMemOffset(), isImmutable);
2328 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2329 return DAG.getLoad(ValVT, dl, Chain, FIN,
2330 MachinePointerInfo::getFixedStack(FI),
2331 false, false, false, 0);
2335 // FIXME: Get this from tablegen.
2336 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2337 const X86Subtarget *Subtarget) {
2338 assert(Subtarget->is64Bit());
2340 if (Subtarget->isCallingConvWin64(CallConv)) {
2341 static const MCPhysReg GPR64ArgRegsWin64[] = {
2342 X86::RCX, X86::RDX, X86::R8, X86::R9
2344 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2347 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2348 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2350 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2353 // FIXME: Get this from tablegen.
2354 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2355 CallingConv::ID CallConv,
2356 const X86Subtarget *Subtarget) {
2357 assert(Subtarget->is64Bit());
2358 if (Subtarget->isCallingConvWin64(CallConv)) {
2359 // The XMM registers which might contain var arg parameters are shadowed
2360 // in their paired GPR. So we only need to save the GPR to their home
2362 // TODO: __vectorcall will change this.
2366 const Function *Fn = MF.getFunction();
2367 bool NoImplicitFloatOps = Fn->getAttributes().
2368 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2369 assert(!(MF.getTarget().Options.UseSoftFloat && NoImplicitFloatOps) &&
2370 "SSE register cannot be used when SSE is disabled!");
2371 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2372 !Subtarget->hasSSE1())
2373 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2377 static const MCPhysReg XMMArgRegs64Bit[] = {
2378 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2379 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2381 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2385 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2386 CallingConv::ID CallConv,
2388 const SmallVectorImpl<ISD::InputArg> &Ins,
2391 SmallVectorImpl<SDValue> &InVals)
2393 MachineFunction &MF = DAG.getMachineFunction();
2394 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2396 const Function* Fn = MF.getFunction();
2397 if (Fn->hasExternalLinkage() &&
2398 Subtarget->isTargetCygMing() &&
2399 Fn->getName() == "main")
2400 FuncInfo->setForceFramePointer(true);
2402 MachineFrameInfo *MFI = MF.getFrameInfo();
2403 bool Is64Bit = Subtarget->is64Bit();
2404 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2406 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2407 "Var args not supported with calling convention fastcc, ghc or hipe");
2409 // Assign locations to all of the incoming arguments.
2410 SmallVector<CCValAssign, 16> ArgLocs;
2411 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2413 // Allocate shadow area for Win64
2415 CCInfo.AllocateStack(32, 8);
2417 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2419 unsigned LastVal = ~0U;
2421 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2422 CCValAssign &VA = ArgLocs[i];
2423 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2425 assert(VA.getValNo() != LastVal &&
2426 "Don't support value assigned to multiple locs yet");
2428 LastVal = VA.getValNo();
2430 if (VA.isRegLoc()) {
2431 EVT RegVT = VA.getLocVT();
2432 const TargetRegisterClass *RC;
2433 if (RegVT == MVT::i32)
2434 RC = &X86::GR32RegClass;
2435 else if (Is64Bit && RegVT == MVT::i64)
2436 RC = &X86::GR64RegClass;
2437 else if (RegVT == MVT::f32)
2438 RC = &X86::FR32RegClass;
2439 else if (RegVT == MVT::f64)
2440 RC = &X86::FR64RegClass;
2441 else if (RegVT.is512BitVector())
2442 RC = &X86::VR512RegClass;
2443 else if (RegVT.is256BitVector())
2444 RC = &X86::VR256RegClass;
2445 else if (RegVT.is128BitVector())
2446 RC = &X86::VR128RegClass;
2447 else if (RegVT == MVT::x86mmx)
2448 RC = &X86::VR64RegClass;
2449 else if (RegVT == MVT::i1)
2450 RC = &X86::VK1RegClass;
2451 else if (RegVT == MVT::v8i1)
2452 RC = &X86::VK8RegClass;
2453 else if (RegVT == MVT::v16i1)
2454 RC = &X86::VK16RegClass;
2455 else if (RegVT == MVT::v32i1)
2456 RC = &X86::VK32RegClass;
2457 else if (RegVT == MVT::v64i1)
2458 RC = &X86::VK64RegClass;
2460 llvm_unreachable("Unknown argument type!");
2462 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2463 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2465 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2466 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2468 if (VA.getLocInfo() == CCValAssign::SExt)
2469 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2470 DAG.getValueType(VA.getValVT()));
2471 else if (VA.getLocInfo() == CCValAssign::ZExt)
2472 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2473 DAG.getValueType(VA.getValVT()));
2474 else if (VA.getLocInfo() == CCValAssign::BCvt)
2475 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2477 if (VA.isExtInLoc()) {
2478 // Handle MMX values passed in XMM regs.
2479 if (RegVT.isVector())
2480 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2482 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2485 assert(VA.isMemLoc());
2486 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2489 // If value is passed via pointer - do a load.
2490 if (VA.getLocInfo() == CCValAssign::Indirect)
2491 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2492 MachinePointerInfo(), false, false, false, 0);
2494 InVals.push_back(ArgValue);
2497 if (Subtarget->is64Bit() || Subtarget->isTargetKnownWindowsMSVC()) {
2498 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2499 // The x86-64 ABIs require that for returning structs by value we copy
2500 // the sret argument into %rax/%eax (depending on ABI) for the return.
2501 // Win32 requires us to put the sret argument to %eax as well.
2502 // Save the argument into a virtual register so that we can access it
2503 // from the return points.
2504 if (Ins[i].Flags.isSRet()) {
2505 unsigned Reg = FuncInfo->getSRetReturnReg();
2507 MVT PtrTy = getPointerTy();
2508 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2509 FuncInfo->setSRetReturnReg(Reg);
2511 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2512 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2518 unsigned StackSize = CCInfo.getNextStackOffset();
2519 // Align stack specially for tail calls.
2520 if (FuncIsMadeTailCallSafe(CallConv,
2521 MF.getTarget().Options.GuaranteedTailCallOpt))
2522 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2524 // If the function takes variable number of arguments, make a frame index for
2525 // the start of the first vararg value... for expansion of llvm.va_start. We
2526 // can skip this if there are no va_start calls.
2527 if (MFI->hasVAStart() &&
2528 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2529 CallConv != CallingConv::X86_ThisCall))) {
2530 FuncInfo->setVarArgsFrameIndex(
2531 MFI->CreateFixedObject(1, StackSize, true));
2534 // 64-bit calling conventions support varargs and register parameters, so we
2535 // have to do extra work to spill them in the prologue or forward them to
2537 if (Is64Bit && isVarArg &&
2538 (MFI->hasVAStart() || MFI->hasMustTailInVarArgFunc())) {
2539 // Find the first unallocated argument registers.
2540 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2541 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2542 unsigned NumIntRegs =
2543 CCInfo.getFirstUnallocated(ArgGPRs.data(), ArgGPRs.size());
2544 unsigned NumXMMRegs =
2545 CCInfo.getFirstUnallocated(ArgXMMs.data(), ArgXMMs.size());
2546 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2547 "SSE register cannot be used when SSE is disabled!");
2549 // Gather all the live in physical registers.
2550 SmallVector<SDValue, 6> LiveGPRs;
2551 SmallVector<SDValue, 8> LiveXMMRegs;
2553 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2554 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2556 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2558 if (!ArgXMMs.empty()) {
2559 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2560 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2561 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2562 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2563 LiveXMMRegs.push_back(
2564 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2568 // Store them to the va_list returned by va_start.
2569 if (MFI->hasVAStart()) {
2571 const TargetFrameLowering &TFI = *MF.getSubtarget().getFrameLowering();
2572 // Get to the caller-allocated home save location. Add 8 to account
2573 // for the return address.
2574 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2575 FuncInfo->setRegSaveFrameIndex(
2576 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2577 // Fixup to set vararg frame on shadow area (4 x i64).
2579 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2581 // For X86-64, if there are vararg parameters that are passed via
2582 // registers, then we must store them to their spots on the stack so
2583 // they may be loaded by deferencing the result of va_next.
2584 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2585 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2586 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2587 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2590 // Store the integer parameter registers.
2591 SmallVector<SDValue, 8> MemOps;
2592 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2594 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2595 for (SDValue Val : LiveGPRs) {
2596 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2597 DAG.getIntPtrConstant(Offset));
2599 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2600 MachinePointerInfo::getFixedStack(
2601 FuncInfo->getRegSaveFrameIndex(), Offset),
2603 MemOps.push_back(Store);
2607 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2608 // Now store the XMM (fp + vector) parameter registers.
2609 SmallVector<SDValue, 12> SaveXMMOps;
2610 SaveXMMOps.push_back(Chain);
2611 SaveXMMOps.push_back(ALVal);
2612 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2613 FuncInfo->getRegSaveFrameIndex()));
2614 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2615 FuncInfo->getVarArgsFPOffset()));
2616 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2618 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2619 MVT::Other, SaveXMMOps));
2622 if (!MemOps.empty())
2623 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2625 // Add all GPRs, al, and XMMs to the list of forwards. We will add then
2626 // to the liveout set on a musttail call.
2627 assert(MFI->hasMustTailInVarArgFunc());
2628 auto &Forwards = FuncInfo->getForwardedMustTailRegParms();
2629 typedef X86MachineFunctionInfo::Forward Forward;
2631 for (unsigned I = 0, E = LiveGPRs.size(); I != E; ++I) {
2633 MF.getRegInfo().createVirtualRegister(&X86::GR64RegClass);
2634 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveGPRs[I]);
2635 Forwards.push_back(Forward(VReg, ArgGPRs[NumIntRegs + I], MVT::i64));
2638 if (!ArgXMMs.empty()) {
2640 MF.getRegInfo().createVirtualRegister(&X86::GR8RegClass);
2641 Chain = DAG.getCopyToReg(Chain, dl, ALVReg, ALVal);
2642 Forwards.push_back(Forward(ALVReg, X86::AL, MVT::i8));
2644 for (unsigned I = 0, E = LiveXMMRegs.size(); I != E; ++I) {
2646 MF.getRegInfo().createVirtualRegister(&X86::VR128RegClass);
2647 Chain = DAG.getCopyToReg(Chain, dl, VReg, LiveXMMRegs[I]);
2649 Forward(VReg, ArgXMMs[NumXMMRegs + I], MVT::v4f32));
2655 // Some CCs need callee pop.
2656 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2657 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2658 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2660 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2661 // If this is an sret function, the return should pop the hidden pointer.
2662 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2663 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2664 argsAreStructReturn(Ins) == StackStructReturn)
2665 FuncInfo->setBytesToPopOnReturn(4);
2669 // RegSaveFrameIndex is X86-64 only.
2670 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2671 if (CallConv == CallingConv::X86_FastCall ||
2672 CallConv == CallingConv::X86_ThisCall)
2673 // fastcc functions can't have varargs.
2674 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2677 FuncInfo->setArgumentStackSize(StackSize);
2683 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2684 SDValue StackPtr, SDValue Arg,
2685 SDLoc dl, SelectionDAG &DAG,
2686 const CCValAssign &VA,
2687 ISD::ArgFlagsTy Flags) const {
2688 unsigned LocMemOffset = VA.getLocMemOffset();
2689 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2690 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2691 if (Flags.isByVal())
2692 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2694 return DAG.getStore(Chain, dl, Arg, PtrOff,
2695 MachinePointerInfo::getStack(LocMemOffset),
2699 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2700 /// optimization is performed and it is required.
2702 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2703 SDValue &OutRetAddr, SDValue Chain,
2704 bool IsTailCall, bool Is64Bit,
2705 int FPDiff, SDLoc dl) const {
2706 // Adjust the Return address stack slot.
2707 EVT VT = getPointerTy();
2708 OutRetAddr = getReturnAddressFrameIndex(DAG);
2710 // Load the "old" Return address.
2711 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2712 false, false, false, 0);
2713 return SDValue(OutRetAddr.getNode(), 1);
2716 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2717 /// optimization is performed and it is required (FPDiff!=0).
2718 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2719 SDValue Chain, SDValue RetAddrFrIdx,
2720 EVT PtrVT, unsigned SlotSize,
2721 int FPDiff, SDLoc dl) {
2722 // Store the return address to the appropriate stack slot.
2723 if (!FPDiff) return Chain;
2724 // Calculate the new stack slot for the return address.
2725 int NewReturnAddrFI =
2726 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2728 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2729 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2730 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2736 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2737 SmallVectorImpl<SDValue> &InVals) const {
2738 SelectionDAG &DAG = CLI.DAG;
2740 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2741 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2742 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2743 SDValue Chain = CLI.Chain;
2744 SDValue Callee = CLI.Callee;
2745 CallingConv::ID CallConv = CLI.CallConv;
2746 bool &isTailCall = CLI.IsTailCall;
2747 bool isVarArg = CLI.IsVarArg;
2749 MachineFunction &MF = DAG.getMachineFunction();
2750 bool Is64Bit = Subtarget->is64Bit();
2751 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2752 StructReturnType SR = callIsStructReturn(Outs);
2753 bool IsSibcall = false;
2754 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2756 if (MF.getTarget().Options.DisableTailCalls)
2759 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2761 // Force this to be a tail call. The verifier rules are enough to ensure
2762 // that we can lower this successfully without moving the return address
2765 } else if (isTailCall) {
2766 // Check if it's really possible to do a tail call.
2767 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2768 isVarArg, SR != NotStructReturn,
2769 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2770 Outs, OutVals, Ins, DAG);
2772 // Sibcalls are automatically detected tailcalls which do not require
2774 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2781 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2782 "Var args not supported with calling convention fastcc, ghc or hipe");
2784 // Analyze operands of the call, assigning locations to each operand.
2785 SmallVector<CCValAssign, 16> ArgLocs;
2786 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2788 // Allocate shadow area for Win64
2790 CCInfo.AllocateStack(32, 8);
2792 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2794 // Get a count of how many bytes are to be pushed on the stack.
2795 unsigned NumBytes = CCInfo.getNextStackOffset();
2797 // This is a sibcall. The memory operands are available in caller's
2798 // own caller's stack.
2800 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2801 IsTailCallConvention(CallConv))
2802 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2805 if (isTailCall && !IsSibcall && !IsMustTail) {
2806 // Lower arguments at fp - stackoffset + fpdiff.
2807 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2809 FPDiff = NumBytesCallerPushed - NumBytes;
2811 // Set the delta of movement of the returnaddr stackslot.
2812 // But only set if delta is greater than previous delta.
2813 if (FPDiff < X86Info->getTCReturnAddrDelta())
2814 X86Info->setTCReturnAddrDelta(FPDiff);
2817 unsigned NumBytesToPush = NumBytes;
2818 unsigned NumBytesToPop = NumBytes;
2820 // If we have an inalloca argument, all stack space has already been allocated
2821 // for us and be right at the top of the stack. We don't support multiple
2822 // arguments passed in memory when using inalloca.
2823 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2825 if (!ArgLocs.back().isMemLoc())
2826 report_fatal_error("cannot use inalloca attribute on a register "
2828 if (ArgLocs.back().getLocMemOffset() != 0)
2829 report_fatal_error("any parameter with the inalloca attribute must be "
2830 "the only memory argument");
2834 Chain = DAG.getCALLSEQ_START(
2835 Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);
2837 SDValue RetAddrFrIdx;
2838 // Load return address for tail calls.
2839 if (isTailCall && FPDiff)
2840 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2841 Is64Bit, FPDiff, dl);
2843 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2844 SmallVector<SDValue, 8> MemOpChains;
2847 // Walk the register/memloc assignments, inserting copies/loads. In the case
2848 // of tail call optimization arguments are handle later.
2849 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
2850 DAG.getSubtarget().getRegisterInfo());
2851 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2852 // Skip inalloca arguments, they have already been written.
2853 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2854 if (Flags.isInAlloca())
2857 CCValAssign &VA = ArgLocs[i];
2858 EVT RegVT = VA.getLocVT();
2859 SDValue Arg = OutVals[i];
2860 bool isByVal = Flags.isByVal();
2862 // Promote the value if needed.
2863 switch (VA.getLocInfo()) {
2864 default: llvm_unreachable("Unknown loc info!");
2865 case CCValAssign::Full: break;
2866 case CCValAssign::SExt:
2867 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2869 case CCValAssign::ZExt:
2870 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2872 case CCValAssign::AExt:
2873 if (RegVT.is128BitVector()) {
2874 // Special case: passing MMX values in XMM registers.
2875 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2876 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2877 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2879 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2881 case CCValAssign::BCvt:
2882 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2884 case CCValAssign::Indirect: {
2885 // Store the argument.
2886 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2887 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2888 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2889 MachinePointerInfo::getFixedStack(FI),
2896 if (VA.isRegLoc()) {
2897 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2898 if (isVarArg && IsWin64) {
2899 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2900 // shadow reg if callee is a varargs function.
2901 unsigned ShadowReg = 0;
2902 switch (VA.getLocReg()) {
2903 case X86::XMM0: ShadowReg = X86::RCX; break;
2904 case X86::XMM1: ShadowReg = X86::RDX; break;
2905 case X86::XMM2: ShadowReg = X86::R8; break;
2906 case X86::XMM3: ShadowReg = X86::R9; break;
2909 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2911 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2912 assert(VA.isMemLoc());
2913 if (!StackPtr.getNode())
2914 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2916 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2917 dl, DAG, VA, Flags));
2921 if (!MemOpChains.empty())
2922 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2924 if (Subtarget->isPICStyleGOT()) {
2925 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2928 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2929 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2931 // If we are tail calling and generating PIC/GOT style code load the
2932 // address of the callee into ECX. The value in ecx is used as target of
2933 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2934 // for tail calls on PIC/GOT architectures. Normally we would just put the
2935 // address of GOT into ebx and then call target@PLT. But for tail calls
2936 // ebx would be restored (since ebx is callee saved) before jumping to the
2939 // Note: The actual moving to ECX is done further down.
2940 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2941 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2942 !G->getGlobal()->hasProtectedVisibility())
2943 Callee = LowerGlobalAddress(Callee, DAG);
2944 else if (isa<ExternalSymbolSDNode>(Callee))
2945 Callee = LowerExternalSymbol(Callee, DAG);
2949 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2950 // From AMD64 ABI document:
2951 // For calls that may call functions that use varargs or stdargs
2952 // (prototype-less calls or calls to functions containing ellipsis (...) in
2953 // the declaration) %al is used as hidden argument to specify the number
2954 // of SSE registers used. The contents of %al do not need to match exactly
2955 // the number of registers, but must be an ubound on the number of SSE
2956 // registers used and is in the range 0 - 8 inclusive.
2958 // Count the number of XMM registers allocated.
2959 static const MCPhysReg XMMArgRegs[] = {
2960 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2961 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2963 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2964 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2965 && "SSE registers cannot be used when SSE is disabled");
2967 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2968 DAG.getConstant(NumXMMRegs, MVT::i8)));
2971 if (Is64Bit && isVarArg && IsMustTail) {
2972 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
2973 for (const auto &F : Forwards) {
2974 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2975 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
2979 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
2980 // don't need this because the eligibility check rejects calls that require
2981 // shuffling arguments passed in memory.
2982 if (!IsSibcall && isTailCall) {
2983 // Force all the incoming stack arguments to be loaded from the stack
2984 // before any new outgoing arguments are stored to the stack, because the
2985 // outgoing stack slots may alias the incoming argument stack slots, and
2986 // the alias isn't otherwise explicit. This is slightly more conservative
2987 // than necessary, because it means that each store effectively depends
2988 // on every argument instead of just those arguments it would clobber.
2989 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2991 SmallVector<SDValue, 8> MemOpChains2;
2994 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2995 CCValAssign &VA = ArgLocs[i];
2998 assert(VA.isMemLoc());
2999 SDValue Arg = OutVals[i];
3000 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3001 // Skip inalloca arguments. They don't require any work.
3002 if (Flags.isInAlloca())
3004 // Create frame index.
3005 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3006 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3007 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3008 FIN = DAG.getFrameIndex(FI, getPointerTy());
3010 if (Flags.isByVal()) {
3011 // Copy relative to framepointer.
3012 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
3013 if (!StackPtr.getNode())
3014 StackPtr = DAG.getCopyFromReg(Chain, dl,
3015 RegInfo->getStackRegister(),
3017 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3019 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3023 // Store relative to framepointer.
3024 MemOpChains2.push_back(
3025 DAG.getStore(ArgChain, dl, Arg, FIN,
3026 MachinePointerInfo::getFixedStack(FI),
3031 if (!MemOpChains2.empty())
3032 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3034 // Store the return address to the appropriate stack slot.
3035 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3036 getPointerTy(), RegInfo->getSlotSize(),
3040 // Build a sequence of copy-to-reg nodes chained together with token chain
3041 // and flag operands which copy the outgoing args into registers.
3043 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3044 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3045 RegsToPass[i].second, InFlag);
3046 InFlag = Chain.getValue(1);
3049 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3050 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3051 // In the 64-bit large code model, we have to make all calls
3052 // through a register, since the call instruction's 32-bit
3053 // pc-relative offset may not be large enough to hold the whole
3055 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3056 // If the callee is a GlobalAddress node (quite common, every direct call
3057 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3060 // We should use extra load for direct calls to dllimported functions in
3062 const GlobalValue *GV = G->getGlobal();
3063 if (!GV->hasDLLImportStorageClass()) {
3064 unsigned char OpFlags = 0;
3065 bool ExtraLoad = false;
3066 unsigned WrapperKind = ISD::DELETED_NODE;
3068 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3069 // external symbols most go through the PLT in PIC mode. If the symbol
3070 // has hidden or protected visibility, or if it is static or local, then
3071 // we don't need to use the PLT - we can directly call it.
3072 if (Subtarget->isTargetELF() &&
3073 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3074 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3075 OpFlags = X86II::MO_PLT;
3076 } else if (Subtarget->isPICStyleStubAny() &&
3077 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3078 (!Subtarget->getTargetTriple().isMacOSX() ||
3079 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3080 // PC-relative references to external symbols should go through $stub,
3081 // unless we're building with the leopard linker or later, which
3082 // automatically synthesizes these stubs.
3083 OpFlags = X86II::MO_DARWIN_STUB;
3084 } else if (Subtarget->isPICStyleRIPRel() &&
3085 isa<Function>(GV) &&
3086 cast<Function>(GV)->getAttributes().
3087 hasAttribute(AttributeSet::FunctionIndex,
3088 Attribute::NonLazyBind)) {
3089 // If the function is marked as non-lazy, generate an indirect call
3090 // which loads from the GOT directly. This avoids runtime overhead
3091 // at the cost of eager binding (and one extra byte of encoding).
3092 OpFlags = X86II::MO_GOTPCREL;
3093 WrapperKind = X86ISD::WrapperRIP;
3097 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3098 G->getOffset(), OpFlags);
3100 // Add a wrapper if needed.
3101 if (WrapperKind != ISD::DELETED_NODE)
3102 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3103 // Add extra indirection if needed.
3105 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3106 MachinePointerInfo::getGOT(),
3107 false, false, false, 0);
3109 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3110 unsigned char OpFlags = 0;
3112 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3113 // external symbols should go through the PLT.
3114 if (Subtarget->isTargetELF() &&
3115 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3116 OpFlags = X86II::MO_PLT;
3117 } else if (Subtarget->isPICStyleStubAny() &&
3118 (!Subtarget->getTargetTriple().isMacOSX() ||
3119 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3120 // PC-relative references to external symbols should go through $stub,
3121 // unless we're building with the leopard linker or later, which
3122 // automatically synthesizes these stubs.
3123 OpFlags = X86II::MO_DARWIN_STUB;
3126 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3128 } else if (Subtarget->isTarget64BitILP32() && Callee->getValueType(0) == MVT::i32) {
3129 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3130 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3133 // Returns a chain & a flag for retval copy to use.
3134 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3135 SmallVector<SDValue, 8> Ops;
3137 if (!IsSibcall && isTailCall) {
3138 Chain = DAG.getCALLSEQ_END(Chain,
3139 DAG.getIntPtrConstant(NumBytesToPop, true),
3140 DAG.getIntPtrConstant(0, true), InFlag, dl);
3141 InFlag = Chain.getValue(1);
3144 Ops.push_back(Chain);
3145 Ops.push_back(Callee);
3148 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
3150 // Add argument registers to the end of the list so that they are known live
3152 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3153 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3154 RegsToPass[i].second.getValueType()));
3156 // Add a register mask operand representing the call-preserved registers.
3157 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
3158 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3159 assert(Mask && "Missing call preserved mask for calling convention");
3160 Ops.push_back(DAG.getRegisterMask(Mask));
3162 if (InFlag.getNode())
3163 Ops.push_back(InFlag);
3167 //// If this is the first return lowered for this function, add the regs
3168 //// to the liveout set for the function.
3169 // This isn't right, although it's probably harmless on x86; liveouts
3170 // should be computed from returns not tail calls. Consider a void
3171 // function making a tail call to a function returning int.
3172 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3175 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3176 InFlag = Chain.getValue(1);
3178 // Create the CALLSEQ_END node.
3179 unsigned NumBytesForCalleeToPop;
3180 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3181 DAG.getTarget().Options.GuaranteedTailCallOpt))
3182 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3183 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3184 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3185 SR == StackStructReturn)
3186 // If this is a call to a struct-return function, the callee
3187 // pops the hidden struct pointer, so we have to push it back.
3188 // This is common for Darwin/X86, Linux & Mingw32 targets.
3189 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3190 NumBytesForCalleeToPop = 4;
3192 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3194 // Returns a flag for retval copy to use.
3196 Chain = DAG.getCALLSEQ_END(Chain,
3197 DAG.getIntPtrConstant(NumBytesToPop, true),
3198 DAG.getIntPtrConstant(NumBytesForCalleeToPop,
3201 InFlag = Chain.getValue(1);
3204 // Handle result values, copying them out of physregs into vregs that we
3206 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3207 Ins, dl, DAG, InVals);
3210 //===----------------------------------------------------------------------===//
3211 // Fast Calling Convention (tail call) implementation
3212 //===----------------------------------------------------------------------===//
3214 // Like std call, callee cleans arguments, convention except that ECX is
3215 // reserved for storing the tail called function address. Only 2 registers are
3216 // free for argument passing (inreg). Tail call optimization is performed
3218 // * tailcallopt is enabled
3219 // * caller/callee are fastcc
3220 // On X86_64 architecture with GOT-style position independent code only local
3221 // (within module) calls are supported at the moment.
3222 // To keep the stack aligned according to platform abi the function
3223 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3224 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3225 // If a tail called function callee has more arguments than the caller the
3226 // caller needs to make sure that there is room to move the RETADDR to. This is
3227 // achieved by reserving an area the size of the argument delta right after the
3228 // original RETADDR, but before the saved framepointer or the spilled registers
3229 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3241 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3242 /// for a 16 byte align requirement.
3244 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3245 SelectionDAG& DAG) const {
3246 MachineFunction &MF = DAG.getMachineFunction();
3247 const TargetMachine &TM = MF.getTarget();
3248 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3249 TM.getSubtargetImpl()->getRegisterInfo());
3250 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
3251 unsigned StackAlignment = TFI.getStackAlignment();
3252 uint64_t AlignMask = StackAlignment - 1;
3253 int64_t Offset = StackSize;
3254 unsigned SlotSize = RegInfo->getSlotSize();
3255 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3256 // Number smaller than 12 so just add the difference.
3257 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3259 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3260 Offset = ((~AlignMask) & Offset) + StackAlignment +
3261 (StackAlignment-SlotSize);
3266 /// MatchingStackOffset - Return true if the given stack call argument is
3267 /// already available in the same position (relatively) of the caller's
3268 /// incoming argument stack.
3270 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3271 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3272 const X86InstrInfo *TII) {
3273 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3275 if (Arg.getOpcode() == ISD::CopyFromReg) {
3276 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3277 if (!TargetRegisterInfo::isVirtualRegister(VR))
3279 MachineInstr *Def = MRI->getVRegDef(VR);
3282 if (!Flags.isByVal()) {
3283 if (!TII->isLoadFromStackSlot(Def, FI))
3286 unsigned Opcode = Def->getOpcode();
3287 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
3288 Def->getOperand(1).isFI()) {
3289 FI = Def->getOperand(1).getIndex();
3290 Bytes = Flags.getByValSize();
3294 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3295 if (Flags.isByVal())
3296 // ByVal argument is passed in as a pointer but it's now being
3297 // dereferenced. e.g.
3298 // define @foo(%struct.X* %A) {
3299 // tail call @bar(%struct.X* byval %A)
3302 SDValue Ptr = Ld->getBasePtr();
3303 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3306 FI = FINode->getIndex();
3307 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3308 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3309 FI = FINode->getIndex();
3310 Bytes = Flags.getByValSize();
3314 assert(FI != INT_MAX);
3315 if (!MFI->isFixedObjectIndex(FI))
3317 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3320 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3321 /// for tail call optimization. Targets which want to do tail call
3322 /// optimization should implement this function.
3324 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3325 CallingConv::ID CalleeCC,
3327 bool isCalleeStructRet,
3328 bool isCallerStructRet,
3330 const SmallVectorImpl<ISD::OutputArg> &Outs,
3331 const SmallVectorImpl<SDValue> &OutVals,
3332 const SmallVectorImpl<ISD::InputArg> &Ins,
3333 SelectionDAG &DAG) const {
3334 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3337 // If -tailcallopt is specified, make fastcc functions tail-callable.
3338 const MachineFunction &MF = DAG.getMachineFunction();
3339 const Function *CallerF = MF.getFunction();
3341 // If the function return type is x86_fp80 and the callee return type is not,
3342 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3343 // perform a tailcall optimization here.
3344 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3347 CallingConv::ID CallerCC = CallerF->getCallingConv();
3348 bool CCMatch = CallerCC == CalleeCC;
3349 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3350 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3352 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3353 if (IsTailCallConvention(CalleeCC) && CCMatch)
3358 // Look for obvious safe cases to perform tail call optimization that do not
3359 // require ABI changes. This is what gcc calls sibcall.
3361 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3362 // emit a special epilogue.
3363 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3364 DAG.getSubtarget().getRegisterInfo());
3365 if (RegInfo->needsStackRealignment(MF))
3368 // Also avoid sibcall optimization if either caller or callee uses struct
3369 // return semantics.
3370 if (isCalleeStructRet || isCallerStructRet)
3373 // An stdcall/thiscall caller is expected to clean up its arguments; the
3374 // callee isn't going to do that.
3375 // FIXME: this is more restrictive than needed. We could produce a tailcall
3376 // when the stack adjustment matches. For example, with a thiscall that takes
3377 // only one argument.
3378 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3379 CallerCC == CallingConv::X86_ThisCall))
3382 // Do not sibcall optimize vararg calls unless all arguments are passed via
3384 if (isVarArg && !Outs.empty()) {
3386 // Optimizing for varargs on Win64 is unlikely to be safe without
3387 // additional testing.
3388 if (IsCalleeWin64 || IsCallerWin64)
3391 SmallVector<CCValAssign, 16> ArgLocs;
3392 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3395 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3396 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3397 if (!ArgLocs[i].isRegLoc())
3401 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3402 // stack. Therefore, if it's not used by the call it is not safe to optimize
3403 // this into a sibcall.
3404 bool Unused = false;
3405 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3412 SmallVector<CCValAssign, 16> RVLocs;
3413 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3415 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3416 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3417 CCValAssign &VA = RVLocs[i];
3418 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3423 // If the calling conventions do not match, then we'd better make sure the
3424 // results are returned in the same way as what the caller expects.
3426 SmallVector<CCValAssign, 16> RVLocs1;
3427 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3429 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3431 SmallVector<CCValAssign, 16> RVLocs2;
3432 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3434 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3436 if (RVLocs1.size() != RVLocs2.size())
3438 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3439 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3441 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3443 if (RVLocs1[i].isRegLoc()) {
3444 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3447 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3453 // If the callee takes no arguments then go on to check the results of the
3455 if (!Outs.empty()) {
3456 // Check if stack adjustment is needed. For now, do not do this if any
3457 // argument is passed on the stack.
3458 SmallVector<CCValAssign, 16> ArgLocs;
3459 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3462 // Allocate shadow area for Win64
3464 CCInfo.AllocateStack(32, 8);
3466 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3467 if (CCInfo.getNextStackOffset()) {
3468 MachineFunction &MF = DAG.getMachineFunction();
3469 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3472 // Check if the arguments are already laid out in the right way as
3473 // the caller's fixed stack objects.
3474 MachineFrameInfo *MFI = MF.getFrameInfo();
3475 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3476 const X86InstrInfo *TII =
3477 static_cast<const X86InstrInfo *>(DAG.getSubtarget().getInstrInfo());
3478 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3479 CCValAssign &VA = ArgLocs[i];
3480 SDValue Arg = OutVals[i];
3481 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3482 if (VA.getLocInfo() == CCValAssign::Indirect)
3484 if (!VA.isRegLoc()) {
3485 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3492 // If the tailcall address may be in a register, then make sure it's
3493 // possible to register allocate for it. In 32-bit, the call address can
3494 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3495 // callee-saved registers are restored. These happen to be the same
3496 // registers used to pass 'inreg' arguments so watch out for those.
3497 if (!Subtarget->is64Bit() &&
3498 ((!isa<GlobalAddressSDNode>(Callee) &&
3499 !isa<ExternalSymbolSDNode>(Callee)) ||
3500 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3501 unsigned NumInRegs = 0;
3502 // In PIC we need an extra register to formulate the address computation
3504 unsigned MaxInRegs =
3505 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3507 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3508 CCValAssign &VA = ArgLocs[i];
3511 unsigned Reg = VA.getLocReg();
3514 case X86::EAX: case X86::EDX: case X86::ECX:
3515 if (++NumInRegs == MaxInRegs)
3527 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3528 const TargetLibraryInfo *libInfo) const {
3529 return X86::createFastISel(funcInfo, libInfo);
3532 //===----------------------------------------------------------------------===//
3533 // Other Lowering Hooks
3534 //===----------------------------------------------------------------------===//
3536 static bool MayFoldLoad(SDValue Op) {
3537 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3540 static bool MayFoldIntoStore(SDValue Op) {
3541 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3544 static bool isTargetShuffle(unsigned Opcode) {
3546 default: return false;
3547 case X86ISD::BLENDI:
3548 case X86ISD::PSHUFB:
3549 case X86ISD::PSHUFD:
3550 case X86ISD::PSHUFHW:
3551 case X86ISD::PSHUFLW:
3553 case X86ISD::PALIGNR:
3554 case X86ISD::MOVLHPS:
3555 case X86ISD::MOVLHPD:
3556 case X86ISD::MOVHLPS:
3557 case X86ISD::MOVLPS:
3558 case X86ISD::MOVLPD:
3559 case X86ISD::MOVSHDUP:
3560 case X86ISD::MOVSLDUP:
3561 case X86ISD::MOVDDUP:
3564 case X86ISD::UNPCKL:
3565 case X86ISD::UNPCKH:
3566 case X86ISD::VPERMILPI:
3567 case X86ISD::VPERM2X128:
3568 case X86ISD::VPERMI:
3573 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3574 SDValue V1, SelectionDAG &DAG) {
3576 default: llvm_unreachable("Unknown x86 shuffle node");
3577 case X86ISD::MOVSHDUP:
3578 case X86ISD::MOVSLDUP:
3579 case X86ISD::MOVDDUP:
3580 return DAG.getNode(Opc, dl, VT, V1);
3584 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3585 SDValue V1, unsigned TargetMask,
3586 SelectionDAG &DAG) {
3588 default: llvm_unreachable("Unknown x86 shuffle node");
3589 case X86ISD::PSHUFD:
3590 case X86ISD::PSHUFHW:
3591 case X86ISD::PSHUFLW:
3592 case X86ISD::VPERMILPI:
3593 case X86ISD::VPERMI:
3594 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3598 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3599 SDValue V1, SDValue V2, unsigned TargetMask,
3600 SelectionDAG &DAG) {
3602 default: llvm_unreachable("Unknown x86 shuffle node");
3603 case X86ISD::PALIGNR:
3604 case X86ISD::VALIGN:
3606 case X86ISD::VPERM2X128:
3607 return DAG.getNode(Opc, dl, VT, V1, V2,
3608 DAG.getConstant(TargetMask, MVT::i8));
3612 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3613 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3615 default: llvm_unreachable("Unknown x86 shuffle node");
3616 case X86ISD::MOVLHPS:
3617 case X86ISD::MOVLHPD:
3618 case X86ISD::MOVHLPS:
3619 case X86ISD::MOVLPS:
3620 case X86ISD::MOVLPD:
3623 case X86ISD::UNPCKL:
3624 case X86ISD::UNPCKH:
3625 return DAG.getNode(Opc, dl, VT, V1, V2);
3629 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3630 MachineFunction &MF = DAG.getMachineFunction();
3631 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
3632 DAG.getSubtarget().getRegisterInfo());
3633 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3634 int ReturnAddrIndex = FuncInfo->getRAIndex();
3636 if (ReturnAddrIndex == 0) {
3637 // Set up a frame object for the return address.
3638 unsigned SlotSize = RegInfo->getSlotSize();
3639 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3642 FuncInfo->setRAIndex(ReturnAddrIndex);
3645 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3648 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3649 bool hasSymbolicDisplacement) {
3650 // Offset should fit into 32 bit immediate field.
3651 if (!isInt<32>(Offset))
3654 // If we don't have a symbolic displacement - we don't have any extra
3656 if (!hasSymbolicDisplacement)
3659 // FIXME: Some tweaks might be needed for medium code model.
3660 if (M != CodeModel::Small && M != CodeModel::Kernel)
3663 // For small code model we assume that latest object is 16MB before end of 31
3664 // bits boundary. We may also accept pretty large negative constants knowing
3665 // that all objects are in the positive half of address space.
3666 if (M == CodeModel::Small && Offset < 16*1024*1024)
3669 // For kernel code model we know that all object resist in the negative half
3670 // of 32bits address space. We may not accept negative offsets, since they may
3671 // be just off and we may accept pretty large positive ones.
3672 if (M == CodeModel::Kernel && Offset >= 0)
3678 /// isCalleePop - Determines whether the callee is required to pop its
3679 /// own arguments. Callee pop is necessary to support tail calls.
3680 bool X86::isCalleePop(CallingConv::ID CallingConv,
3681 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3682 switch (CallingConv) {
3685 case CallingConv::X86_StdCall:
3686 case CallingConv::X86_FastCall:
3687 case CallingConv::X86_ThisCall:
3689 case CallingConv::Fast:
3690 case CallingConv::GHC:
3691 case CallingConv::HiPE:
3698 /// \brief Return true if the condition is an unsigned comparison operation.
3699 static bool isX86CCUnsigned(unsigned X86CC) {
3701 default: llvm_unreachable("Invalid integer condition!");
3702 case X86::COND_E: return true;
3703 case X86::COND_G: return false;
3704 case X86::COND_GE: return false;
3705 case X86::COND_L: return false;
3706 case X86::COND_LE: return false;
3707 case X86::COND_NE: return true;
3708 case X86::COND_B: return true;
3709 case X86::COND_A: return true;
3710 case X86::COND_BE: return true;
3711 case X86::COND_AE: return true;
3713 llvm_unreachable("covered switch fell through?!");
3716 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3717 /// specific condition code, returning the condition code and the LHS/RHS of the
3718 /// comparison to make.
3719 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3720 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3722 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3723 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3724 // X > -1 -> X == 0, jump !sign.
3725 RHS = DAG.getConstant(0, RHS.getValueType());
3726 return X86::COND_NS;
3728 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3729 // X < 0 -> X == 0, jump on sign.
3732 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3734 RHS = DAG.getConstant(0, RHS.getValueType());
3735 return X86::COND_LE;
3739 switch (SetCCOpcode) {
3740 default: llvm_unreachable("Invalid integer condition!");
3741 case ISD::SETEQ: return X86::COND_E;
3742 case ISD::SETGT: return X86::COND_G;
3743 case ISD::SETGE: return X86::COND_GE;
3744 case ISD::SETLT: return X86::COND_L;
3745 case ISD::SETLE: return X86::COND_LE;
3746 case ISD::SETNE: return X86::COND_NE;
3747 case ISD::SETULT: return X86::COND_B;
3748 case ISD::SETUGT: return X86::COND_A;
3749 case ISD::SETULE: return X86::COND_BE;
3750 case ISD::SETUGE: return X86::COND_AE;
3754 // First determine if it is required or is profitable to flip the operands.
3756 // If LHS is a foldable load, but RHS is not, flip the condition.
3757 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3758 !ISD::isNON_EXTLoad(RHS.getNode())) {
3759 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3760 std::swap(LHS, RHS);
3763 switch (SetCCOpcode) {
3769 std::swap(LHS, RHS);
3773 // On a floating point condition, the flags are set as follows:
3775 // 0 | 0 | 0 | X > Y
3776 // 0 | 0 | 1 | X < Y
3777 // 1 | 0 | 0 | X == Y
3778 // 1 | 1 | 1 | unordered
3779 switch (SetCCOpcode) {
3780 default: llvm_unreachable("Condcode should be pre-legalized away");
3782 case ISD::SETEQ: return X86::COND_E;
3783 case ISD::SETOLT: // flipped
3785 case ISD::SETGT: return X86::COND_A;
3786 case ISD::SETOLE: // flipped
3788 case ISD::SETGE: return X86::COND_AE;
3789 case ISD::SETUGT: // flipped
3791 case ISD::SETLT: return X86::COND_B;
3792 case ISD::SETUGE: // flipped
3794 case ISD::SETLE: return X86::COND_BE;
3796 case ISD::SETNE: return X86::COND_NE;
3797 case ISD::SETUO: return X86::COND_P;
3798 case ISD::SETO: return X86::COND_NP;
3800 case ISD::SETUNE: return X86::COND_INVALID;
3804 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3805 /// code. Current x86 isa includes the following FP cmov instructions:
3806 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3807 static bool hasFPCMov(unsigned X86CC) {
3823 /// isFPImmLegal - Returns true if the target can instruction select the
3824 /// specified FP immediate natively. If false, the legalizer will
3825 /// materialize the FP immediate as a load from a constant pool.
3826 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3827 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3828 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3834 /// \brief Returns true if it is beneficial to convert a load of a constant
3835 /// to just the constant itself.
3836 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3838 assert(Ty->isIntegerTy());
3840 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3841 if (BitSize == 0 || BitSize > 64)
3846 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3847 /// the specified range (L, H].
3848 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3849 return (Val < 0) || (Val >= Low && Val < Hi);
3852 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3853 /// specified value.
3854 static bool isUndefOrEqual(int Val, int CmpVal) {
3855 return (Val < 0 || Val == CmpVal);
3858 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3859 /// from position Pos and ending in Pos+Size, falls within the specified
3860 /// sequential range (L, L+Pos]. or is undef.
3861 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3862 unsigned Pos, unsigned Size, int Low) {
3863 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3864 if (!isUndefOrEqual(Mask[i], Low))
3869 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3870 /// is suitable for input to PSHUFD. That is, it doesn't reference the other
3871 /// operand - by default will match for first operand.
3872 static bool isPSHUFDMask(ArrayRef<int> Mask, MVT VT,
3873 bool TestSecondOperand = false) {
3874 if (VT != MVT::v4f32 && VT != MVT::v4i32 &&
3875 VT != MVT::v2f64 && VT != MVT::v2i64)
3878 unsigned NumElems = VT.getVectorNumElements();
3879 unsigned Lo = TestSecondOperand ? NumElems : 0;
3880 unsigned Hi = Lo + NumElems;
3882 for (unsigned i = 0; i < NumElems; ++i)
3883 if (!isUndefOrInRange(Mask[i], (int)Lo, (int)Hi))
3889 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3890 /// is suitable for input to PSHUFHW.
3891 static bool isPSHUFHWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3892 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3895 // Lower quadword copied in order or undef.
3896 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3899 // Upper quadword shuffled.
3900 for (unsigned i = 4; i != 8; ++i)
3901 if (!isUndefOrInRange(Mask[i], 4, 8))
3904 if (VT == MVT::v16i16) {
3905 // Lower quadword copied in order or undef.
3906 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3909 // Upper quadword shuffled.
3910 for (unsigned i = 12; i != 16; ++i)
3911 if (!isUndefOrInRange(Mask[i], 12, 16))
3918 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3919 /// is suitable for input to PSHUFLW.
3920 static bool isPSHUFLWMask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
3921 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3924 // Upper quadword copied in order.
3925 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3928 // Lower quadword shuffled.
3929 for (unsigned i = 0; i != 4; ++i)
3930 if (!isUndefOrInRange(Mask[i], 0, 4))
3933 if (VT == MVT::v16i16) {
3934 // Upper quadword copied in order.
3935 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3938 // Lower quadword shuffled.
3939 for (unsigned i = 8; i != 12; ++i)
3940 if (!isUndefOrInRange(Mask[i], 8, 12))
3947 /// \brief Return true if the mask specifies a shuffle of elements that is
3948 /// suitable for input to intralane (palignr) or interlane (valign) vector
3950 static bool isAlignrMask(ArrayRef<int> Mask, MVT VT, bool InterLane) {
3951 unsigned NumElts = VT.getVectorNumElements();
3952 unsigned NumLanes = InterLane ? 1: VT.getSizeInBits()/128;
3953 unsigned NumLaneElts = NumElts/NumLanes;
3955 // Do not handle 64-bit element shuffles with palignr.
3956 if (NumLaneElts == 2)
3959 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3961 for (i = 0; i != NumLaneElts; ++i) {
3966 // Lane is all undef, go to next lane
3967 if (i == NumLaneElts)
3970 int Start = Mask[i+l];
3972 // Make sure its in this lane in one of the sources
3973 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3974 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3977 // If not lane 0, then we must match lane 0
3978 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3981 // Correct second source to be contiguous with first source
3982 if (Start >= (int)NumElts)
3983 Start -= NumElts - NumLaneElts;
3985 // Make sure we're shifting in the right direction.
3986 if (Start <= (int)(i+l))
3991 // Check the rest of the elements to see if they are consecutive.
3992 for (++i; i != NumLaneElts; ++i) {
3993 int Idx = Mask[i+l];
3995 // Make sure its in this lane
3996 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3997 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
4000 // If not lane 0, then we must match lane 0
4001 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
4004 if (Idx >= (int)NumElts)
4005 Idx -= NumElts - NumLaneElts;
4007 if (!isUndefOrEqual(Idx, Start+i))
4016 /// \brief Return true if the node specifies a shuffle of elements that is
4017 /// suitable for input to PALIGNR.
4018 static bool isPALIGNRMask(ArrayRef<int> Mask, MVT VT,
4019 const X86Subtarget *Subtarget) {
4020 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
4021 (VT.is256BitVector() && !Subtarget->hasInt256()) ||
4022 VT.is512BitVector())
4023 // FIXME: Add AVX512BW.
4026 return isAlignrMask(Mask, VT, false);
4029 /// \brief Return true if the node specifies a shuffle of elements that is
4030 /// suitable for input to VALIGN.
4031 static bool isVALIGNMask(ArrayRef<int> Mask, MVT VT,
4032 const X86Subtarget *Subtarget) {
4033 // FIXME: Add AVX512VL.
4034 if (!VT.is512BitVector() || !Subtarget->hasAVX512())
4036 return isAlignrMask(Mask, VT, true);
4039 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4040 /// the two vector operands have swapped position.
4041 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
4042 unsigned NumElems) {
4043 for (unsigned i = 0; i != NumElems; ++i) {
4047 else if (idx < (int)NumElems)
4048 Mask[i] = idx + NumElems;
4050 Mask[i] = idx - NumElems;
4054 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
4055 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
4056 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
4057 /// reverse of what x86 shuffles want.
4058 static bool isSHUFPMask(ArrayRef<int> Mask, MVT VT, bool Commuted = false) {
4060 unsigned NumElems = VT.getVectorNumElements();
4061 unsigned NumLanes = VT.getSizeInBits()/128;
4062 unsigned NumLaneElems = NumElems/NumLanes;
4064 if (NumLaneElems != 2 && NumLaneElems != 4)
4067 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4068 bool symetricMaskRequired =
4069 (VT.getSizeInBits() >= 256) && (EltSize == 32);
4071 // VSHUFPSY divides the resulting vector into 4 chunks.
4072 // The sources are also splitted into 4 chunks, and each destination
4073 // chunk must come from a different source chunk.
4075 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
4076 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
4078 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
4079 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
4081 // VSHUFPDY divides the resulting vector into 4 chunks.
4082 // The sources are also splitted into 4 chunks, and each destination
4083 // chunk must come from a different source chunk.
4085 // SRC1 => X3 X2 X1 X0
4086 // SRC2 => Y3 Y2 Y1 Y0
4088 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
4090 SmallVector<int, 4> MaskVal(NumLaneElems, -1);
4091 unsigned HalfLaneElems = NumLaneElems/2;
4092 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
4093 for (unsigned i = 0; i != NumLaneElems; ++i) {
4094 int Idx = Mask[i+l];
4095 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
4096 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
4098 // For VSHUFPSY, the mask of the second half must be the same as the
4099 // first but with the appropriate offsets. This works in the same way as
4100 // VPERMILPS works with masks.
4101 if (!symetricMaskRequired || Idx < 0)
4103 if (MaskVal[i] < 0) {
4104 MaskVal[i] = Idx - l;
4107 if ((signed)(Idx - l) != MaskVal[i])
4115 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
4116 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
4117 static bool isMOVHLPSMask(ArrayRef<int> Mask, MVT VT) {
4118 if (!VT.is128BitVector())
4121 unsigned NumElems = VT.getVectorNumElements();
4126 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
4127 return isUndefOrEqual(Mask[0], 6) &&
4128 isUndefOrEqual(Mask[1], 7) &&
4129 isUndefOrEqual(Mask[2], 2) &&
4130 isUndefOrEqual(Mask[3], 3);
4133 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
4134 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
4136 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, MVT VT) {
4137 if (!VT.is128BitVector())
4140 unsigned NumElems = VT.getVectorNumElements();
4145 return isUndefOrEqual(Mask[0], 2) &&
4146 isUndefOrEqual(Mask[1], 3) &&
4147 isUndefOrEqual(Mask[2], 2) &&
4148 isUndefOrEqual(Mask[3], 3);
4151 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
4152 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
4153 static bool isMOVLPMask(ArrayRef<int> Mask, MVT VT) {
4154 if (!VT.is128BitVector())
4157 unsigned NumElems = VT.getVectorNumElements();
4159 if (NumElems != 2 && NumElems != 4)
4162 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4163 if (!isUndefOrEqual(Mask[i], i + NumElems))
4166 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4167 if (!isUndefOrEqual(Mask[i], i))
4173 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
4174 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
4175 static bool isMOVLHPSMask(ArrayRef<int> Mask, MVT VT) {
4176 if (!VT.is128BitVector())
4179 unsigned NumElems = VT.getVectorNumElements();
4181 if (NumElems != 2 && NumElems != 4)
4184 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4185 if (!isUndefOrEqual(Mask[i], i))
4188 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4189 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
4195 /// isINSERTPSMask - Return true if the specified VECTOR_SHUFFLE operand
4196 /// specifies a shuffle of elements that is suitable for input to INSERTPS.
4197 /// i. e: If all but one element come from the same vector.
4198 static bool isINSERTPSMask(ArrayRef<int> Mask, MVT VT) {
4199 // TODO: Deal with AVX's VINSERTPS
4200 if (!VT.is128BitVector() || (VT != MVT::v4f32 && VT != MVT::v4i32))
4203 unsigned CorrectPosV1 = 0;
4204 unsigned CorrectPosV2 = 0;
4205 for (int i = 0, e = (int)VT.getVectorNumElements(); i != e; ++i) {
4206 if (Mask[i] == -1) {
4214 else if (Mask[i] == i + 4)
4218 if (CorrectPosV1 == 3 || CorrectPosV2 == 3)
4219 // We have 3 elements (undefs count as elements from any vector) from one
4220 // vector, and one from another.
4227 // Some special combinations that can be optimized.
4230 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
4231 SelectionDAG &DAG) {
4232 MVT VT = SVOp->getSimpleValueType(0);
4235 if (VT != MVT::v8i32 && VT != MVT::v8f32)
4238 ArrayRef<int> Mask = SVOp->getMask();
4240 // These are the special masks that may be optimized.
4241 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
4242 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
4243 bool MatchEvenMask = true;
4244 bool MatchOddMask = true;
4245 for (int i=0; i<8; ++i) {
4246 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
4247 MatchEvenMask = false;
4248 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
4249 MatchOddMask = false;
4252 if (!MatchEvenMask && !MatchOddMask)
4255 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
4257 SDValue Op0 = SVOp->getOperand(0);
4258 SDValue Op1 = SVOp->getOperand(1);
4260 if (MatchEvenMask) {
4261 // Shift the second operand right to 32 bits.
4262 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
4263 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
4265 // Shift the first operand left to 32 bits.
4266 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
4267 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
4269 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
4270 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
4273 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
4274 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
4275 static bool isUNPCKLMask(ArrayRef<int> Mask, MVT VT,
4276 bool HasInt256, bool V2IsSplat = false) {
4278 assert(VT.getSizeInBits() >= 128 &&
4279 "Unsupported vector type for unpckl");
4281 unsigned NumElts = VT.getVectorNumElements();
4282 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4283 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4286 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4287 "Unsupported vector type for unpckh");
4289 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4290 unsigned NumLanes = VT.getSizeInBits()/128;
4291 unsigned NumLaneElts = NumElts/NumLanes;
4293 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4294 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4295 int BitI = Mask[l+i];
4296 int BitI1 = Mask[l+i+1];
4297 if (!isUndefOrEqual(BitI, j))
4300 if (!isUndefOrEqual(BitI1, NumElts))
4303 if (!isUndefOrEqual(BitI1, j + NumElts))
4312 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
4313 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
4314 static bool isUNPCKHMask(ArrayRef<int> Mask, MVT VT,
4315 bool HasInt256, bool V2IsSplat = false) {
4316 assert(VT.getSizeInBits() >= 128 &&
4317 "Unsupported vector type for unpckh");
4319 unsigned NumElts = VT.getVectorNumElements();
4320 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4321 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4324 assert((!VT.is512BitVector() || VT.getScalarType().getSizeInBits() >= 32) &&
4325 "Unsupported vector type for unpckh");
4327 // AVX defines UNPCK* to operate independently on 128-bit lanes.
4328 unsigned NumLanes = VT.getSizeInBits()/128;
4329 unsigned NumLaneElts = NumElts/NumLanes;
4331 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4332 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4333 int BitI = Mask[l+i];
4334 int BitI1 = Mask[l+i+1];
4335 if (!isUndefOrEqual(BitI, j))
4338 if (isUndefOrEqual(BitI1, NumElts))
4341 if (!isUndefOrEqual(BitI1, j+NumElts))
4349 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
4350 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
4352 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4353 unsigned NumElts = VT.getVectorNumElements();
4354 bool Is256BitVec = VT.is256BitVector();
4356 if (VT.is512BitVector())
4358 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4359 "Unsupported vector type for unpckh");
4361 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
4362 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4365 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
4366 // FIXME: Need a better way to get rid of this, there's no latency difference
4367 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
4368 // the former later. We should also remove the "_undef" special mask.
4369 if (NumElts == 4 && Is256BitVec)
4372 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4373 // independently on 128-bit lanes.
4374 unsigned NumLanes = VT.getSizeInBits()/128;
4375 unsigned NumLaneElts = NumElts/NumLanes;
4377 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4378 for (unsigned i = 0, j = l; i != NumLaneElts; i += 2, ++j) {
4379 int BitI = Mask[l+i];
4380 int BitI1 = Mask[l+i+1];
4382 if (!isUndefOrEqual(BitI, j))
4384 if (!isUndefOrEqual(BitI1, j))
4392 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
4393 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
4395 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, MVT VT, bool HasInt256) {
4396 unsigned NumElts = VT.getVectorNumElements();
4398 if (VT.is512BitVector())
4401 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4402 "Unsupported vector type for unpckh");
4404 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
4405 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
4408 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
4409 // independently on 128-bit lanes.
4410 unsigned NumLanes = VT.getSizeInBits()/128;
4411 unsigned NumLaneElts = NumElts/NumLanes;
4413 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
4414 for (unsigned i = 0, j = l+NumLaneElts/2; i != NumLaneElts; i += 2, ++j) {
4415 int BitI = Mask[l+i];
4416 int BitI1 = Mask[l+i+1];
4417 if (!isUndefOrEqual(BitI, j))
4419 if (!isUndefOrEqual(BitI1, j))
4426 // Match for INSERTI64x4 INSERTF64x4 instructions (src0[0], src1[0]) or
4427 // (src1[0], src0[1]), manipulation with 256-bit sub-vectors
4428 static bool isINSERT64x4Mask(ArrayRef<int> Mask, MVT VT, unsigned int *Imm) {
4429 if (!VT.is512BitVector())
4432 unsigned NumElts = VT.getVectorNumElements();
4433 unsigned HalfSize = NumElts/2;
4434 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, 0)) {
4435 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, NumElts)) {
4440 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, NumElts)) {
4441 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, HalfSize)) {
4449 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
4450 /// specifies a shuffle of elements that is suitable for input to MOVSS,
4451 /// MOVSD, and MOVD, i.e. setting the lowest element.
4452 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
4453 if (VT.getVectorElementType().getSizeInBits() < 32)
4455 if (!VT.is128BitVector())
4458 unsigned NumElts = VT.getVectorNumElements();
4460 if (!isUndefOrEqual(Mask[0], NumElts))
4463 for (unsigned i = 1; i != NumElts; ++i)
4464 if (!isUndefOrEqual(Mask[i], i))
4470 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
4471 /// as permutations between 128-bit chunks or halves. As an example: this
4473 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
4474 /// The first half comes from the second half of V1 and the second half from the
4475 /// the second half of V2.
4476 static bool isVPERM2X128Mask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4477 if (!HasFp256 || !VT.is256BitVector())
4480 // The shuffle result is divided into half A and half B. In total the two
4481 // sources have 4 halves, namely: C, D, E, F. The final values of A and
4482 // B must come from C, D, E or F.
4483 unsigned HalfSize = VT.getVectorNumElements()/2;
4484 bool MatchA = false, MatchB = false;
4486 // Check if A comes from one of C, D, E, F.
4487 for (unsigned Half = 0; Half != 4; ++Half) {
4488 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
4494 // Check if B comes from one of C, D, E, F.
4495 for (unsigned Half = 0; Half != 4; ++Half) {
4496 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
4502 return MatchA && MatchB;
4505 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
4506 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
4507 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
4508 MVT VT = SVOp->getSimpleValueType(0);
4510 unsigned HalfSize = VT.getVectorNumElements()/2;
4512 unsigned FstHalf = 0, SndHalf = 0;
4513 for (unsigned i = 0; i < HalfSize; ++i) {
4514 if (SVOp->getMaskElt(i) > 0) {
4515 FstHalf = SVOp->getMaskElt(i)/HalfSize;
4519 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
4520 if (SVOp->getMaskElt(i) > 0) {
4521 SndHalf = SVOp->getMaskElt(i)/HalfSize;
4526 return (FstHalf | (SndHalf << 4));
4529 // Symetric in-lane mask. Each lane has 4 elements (for imm8)
4530 static bool isPermImmMask(ArrayRef<int> Mask, MVT VT, unsigned& Imm8) {
4531 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4535 unsigned NumElts = VT.getVectorNumElements();
4537 if (VT.is128BitVector() || (VT.is256BitVector() && EltSize == 64)) {
4538 for (unsigned i = 0; i != NumElts; ++i) {
4541 Imm8 |= Mask[i] << (i*2);
4546 unsigned LaneSize = 4;
4547 SmallVector<int, 4> MaskVal(LaneSize, -1);
4549 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4550 for (unsigned i = 0; i != LaneSize; ++i) {
4551 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4555 if (MaskVal[i] < 0) {
4556 MaskVal[i] = Mask[i+l] - l;
4557 Imm8 |= MaskVal[i] << (i*2);
4560 if (Mask[i+l] != (signed)(MaskVal[i]+l))
4567 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
4568 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
4569 /// Note that VPERMIL mask matching is different depending whether theunderlying
4570 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
4571 /// to the same elements of the low, but to the higher half of the source.
4572 /// In VPERMILPD the two lanes could be shuffled independently of each other
4573 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
4574 static bool isVPERMILPMask(ArrayRef<int> Mask, MVT VT) {
4575 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4576 if (VT.getSizeInBits() < 256 || EltSize < 32)
4578 bool symetricMaskRequired = (EltSize == 32);
4579 unsigned NumElts = VT.getVectorNumElements();
4581 unsigned NumLanes = VT.getSizeInBits()/128;
4582 unsigned LaneSize = NumElts/NumLanes;
4583 // 2 or 4 elements in one lane
4585 SmallVector<int, 4> ExpectedMaskVal(LaneSize, -1);
4586 for (unsigned l = 0; l != NumElts; l += LaneSize) {
4587 for (unsigned i = 0; i != LaneSize; ++i) {
4588 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
4590 if (symetricMaskRequired) {
4591 if (ExpectedMaskVal[i] < 0 && Mask[i+l] >= 0) {
4592 ExpectedMaskVal[i] = Mask[i+l] - l;
4595 if (!isUndefOrEqual(Mask[i+l], ExpectedMaskVal[i]+l))
4603 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
4604 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
4605 /// element of vector 2 and the other elements to come from vector 1 in order.
4606 static bool isCommutedMOVLMask(ArrayRef<int> Mask, MVT VT,
4607 bool V2IsSplat = false, bool V2IsUndef = false) {
4608 if (!VT.is128BitVector())
4611 unsigned NumOps = VT.getVectorNumElements();
4612 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
4615 if (!isUndefOrEqual(Mask[0], 0))
4618 for (unsigned i = 1; i != NumOps; ++i)
4619 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
4620 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
4621 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
4627 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4628 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
4629 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
4630 static bool isMOVSHDUPMask(ArrayRef<int> Mask, MVT VT,
4631 const X86Subtarget *Subtarget) {
4632 if (!Subtarget->hasSSE3())
4635 unsigned NumElems = VT.getVectorNumElements();
4637 if ((VT.is128BitVector() && NumElems != 4) ||
4638 (VT.is256BitVector() && NumElems != 8) ||
4639 (VT.is512BitVector() && NumElems != 16))
4642 // "i+1" is the value the indexed mask element must have
4643 for (unsigned i = 0; i != NumElems; i += 2)
4644 if (!isUndefOrEqual(Mask[i], i+1) ||
4645 !isUndefOrEqual(Mask[i+1], i+1))
4651 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4652 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
4653 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
4654 static bool isMOVSLDUPMask(ArrayRef<int> Mask, MVT VT,
4655 const X86Subtarget *Subtarget) {
4656 if (!Subtarget->hasSSE3())
4659 unsigned NumElems = VT.getVectorNumElements();
4661 if ((VT.is128BitVector() && NumElems != 4) ||
4662 (VT.is256BitVector() && NumElems != 8) ||
4663 (VT.is512BitVector() && NumElems != 16))
4666 // "i" is the value the indexed mask element must have
4667 for (unsigned i = 0; i != NumElems; i += 2)
4668 if (!isUndefOrEqual(Mask[i], i) ||
4669 !isUndefOrEqual(Mask[i+1], i))
4675 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4676 /// specifies a shuffle of elements that is suitable for input to 256-bit
4677 /// version of MOVDDUP.
4678 static bool isMOVDDUPYMask(ArrayRef<int> Mask, MVT VT, bool HasFp256) {
4679 if (!HasFp256 || !VT.is256BitVector())
4682 unsigned NumElts = VT.getVectorNumElements();
4686 for (unsigned i = 0; i != NumElts/2; ++i)
4687 if (!isUndefOrEqual(Mask[i], 0))
4689 for (unsigned i = NumElts/2; i != NumElts; ++i)
4690 if (!isUndefOrEqual(Mask[i], NumElts/2))
4695 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4696 /// specifies a shuffle of elements that is suitable for input to 128-bit
4697 /// version of MOVDDUP.
4698 static bool isMOVDDUPMask(ArrayRef<int> Mask, MVT VT) {
4699 if (!VT.is128BitVector())
4702 unsigned e = VT.getVectorNumElements() / 2;
4703 for (unsigned i = 0; i != e; ++i)
4704 if (!isUndefOrEqual(Mask[i], i))
4706 for (unsigned i = 0; i != e; ++i)
4707 if (!isUndefOrEqual(Mask[e+i], i))
4712 /// isVEXTRACTIndex - Return true if the specified
4713 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4714 /// suitable for instruction that extract 128 or 256 bit vectors
4715 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4716 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4717 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4720 // The index should be aligned on a vecWidth-bit boundary.
4722 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4724 MVT VT = N->getSimpleValueType(0);
4725 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4726 bool Result = (Index * ElSize) % vecWidth == 0;
4731 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
4732 /// operand specifies a subvector insert that is suitable for input to
4733 /// insertion of 128 or 256-bit subvectors
4734 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4735 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4736 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4738 // The index should be aligned on a vecWidth-bit boundary.
4740 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4742 MVT VT = N->getSimpleValueType(0);
4743 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4744 bool Result = (Index * ElSize) % vecWidth == 0;
4749 bool X86::isVINSERT128Index(SDNode *N) {
4750 return isVINSERTIndex(N, 128);
4753 bool X86::isVINSERT256Index(SDNode *N) {
4754 return isVINSERTIndex(N, 256);
4757 bool X86::isVEXTRACT128Index(SDNode *N) {
4758 return isVEXTRACTIndex(N, 128);
4761 bool X86::isVEXTRACT256Index(SDNode *N) {
4762 return isVEXTRACTIndex(N, 256);
4765 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4766 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4767 /// Handles 128-bit and 256-bit.
4768 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4769 MVT VT = N->getSimpleValueType(0);
4771 assert((VT.getSizeInBits() >= 128) &&
4772 "Unsupported vector type for PSHUF/SHUFP");
4774 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4775 // independently on 128-bit lanes.
4776 unsigned NumElts = VT.getVectorNumElements();
4777 unsigned NumLanes = VT.getSizeInBits()/128;
4778 unsigned NumLaneElts = NumElts/NumLanes;
4780 assert((NumLaneElts == 2 || NumLaneElts == 4 || NumLaneElts == 8) &&
4781 "Only supports 2, 4 or 8 elements per lane");
4783 unsigned Shift = (NumLaneElts >= 4) ? 1 : 0;
4785 for (unsigned i = 0; i != NumElts; ++i) {
4786 int Elt = N->getMaskElt(i);
4787 if (Elt < 0) continue;
4788 Elt &= NumLaneElts - 1;
4789 unsigned ShAmt = (i << Shift) % 8;
4790 Mask |= Elt << ShAmt;
4796 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4797 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4798 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4799 MVT VT = N->getSimpleValueType(0);
4801 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4802 "Unsupported vector type for PSHUFHW");
4804 unsigned NumElts = VT.getVectorNumElements();
4807 for (unsigned l = 0; l != NumElts; l += 8) {
4808 // 8 nodes per lane, but we only care about the last 4.
4809 for (unsigned i = 0; i < 4; ++i) {
4810 int Elt = N->getMaskElt(l+i+4);
4811 if (Elt < 0) continue;
4812 Elt &= 0x3; // only 2-bits.
4813 Mask |= Elt << (i * 2);
4820 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4821 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4822 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4823 MVT VT = N->getSimpleValueType(0);
4825 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4826 "Unsupported vector type for PSHUFHW");
4828 unsigned NumElts = VT.getVectorNumElements();
4831 for (unsigned l = 0; l != NumElts; l += 8) {
4832 // 8 nodes per lane, but we only care about the first 4.
4833 for (unsigned i = 0; i < 4; ++i) {
4834 int Elt = N->getMaskElt(l+i);
4835 if (Elt < 0) continue;
4836 Elt &= 0x3; // only 2-bits
4837 Mask |= Elt << (i * 2);
4844 /// \brief Return the appropriate immediate to shuffle the specified
4845 /// VECTOR_SHUFFLE mask with the PALIGNR (if InterLane is false) or with
4846 /// VALIGN (if Interlane is true) instructions.
4847 static unsigned getShuffleAlignrImmediate(ShuffleVectorSDNode *SVOp,
4849 MVT VT = SVOp->getSimpleValueType(0);
4850 unsigned EltSize = InterLane ? 1 :
4851 VT.getVectorElementType().getSizeInBits() >> 3;
4853 unsigned NumElts = VT.getVectorNumElements();
4854 unsigned NumLanes = VT.is512BitVector() ? 1 : VT.getSizeInBits()/128;
4855 unsigned NumLaneElts = NumElts/NumLanes;
4859 for (i = 0; i != NumElts; ++i) {
4860 Val = SVOp->getMaskElt(i);
4864 if (Val >= (int)NumElts)
4865 Val -= NumElts - NumLaneElts;
4867 assert(Val - i > 0 && "PALIGNR imm should be positive");
4868 return (Val - i) * EltSize;
4871 /// \brief Return the appropriate immediate to shuffle the specified
4872 /// VECTOR_SHUFFLE mask with the PALIGNR instruction.
4873 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4874 return getShuffleAlignrImmediate(SVOp, false);
4877 /// \brief Return the appropriate immediate to shuffle the specified
4878 /// VECTOR_SHUFFLE mask with the VALIGN instruction.
4879 static unsigned getShuffleVALIGNImmediate(ShuffleVectorSDNode *SVOp) {
4880 return getShuffleAlignrImmediate(SVOp, true);
4884 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4885 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4886 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4887 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4890 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4892 MVT VecVT = N->getOperand(0).getSimpleValueType();
4893 MVT ElVT = VecVT.getVectorElementType();
4895 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4896 return Index / NumElemsPerChunk;
4899 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4900 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4901 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4902 llvm_unreachable("Illegal insert subvector for VINSERT");
4905 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4907 MVT VecVT = N->getSimpleValueType(0);
4908 MVT ElVT = VecVT.getVectorElementType();
4910 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4911 return Index / NumElemsPerChunk;
4914 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4915 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4916 /// and VINSERTI128 instructions.
4917 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4918 return getExtractVEXTRACTImmediate(N, 128);
4921 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4922 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4923 /// and VINSERTI64x4 instructions.
4924 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4925 return getExtractVEXTRACTImmediate(N, 256);
4928 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4929 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4930 /// and VINSERTI128 instructions.
4931 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4932 return getInsertVINSERTImmediate(N, 128);
4935 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4936 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4937 /// and VINSERTI64x4 instructions.
4938 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4939 return getInsertVINSERTImmediate(N, 256);
4942 /// isZero - Returns true if Elt is a constant integer zero
4943 static bool isZero(SDValue V) {
4944 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4945 return C && C->isNullValue();
4948 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4950 bool X86::isZeroNode(SDValue Elt) {
4953 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4954 return CFP->getValueAPF().isPosZero();
4958 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4959 /// match movhlps. The lower half elements should come from upper half of
4960 /// V1 (and in order), and the upper half elements should come from the upper
4961 /// half of V2 (and in order).
4962 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, MVT VT) {
4963 if (!VT.is128BitVector())
4965 if (VT.getVectorNumElements() != 4)
4967 for (unsigned i = 0, e = 2; i != e; ++i)
4968 if (!isUndefOrEqual(Mask[i], i+2))
4970 for (unsigned i = 2; i != 4; ++i)
4971 if (!isUndefOrEqual(Mask[i], i+4))
4976 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4977 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4979 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = nullptr) {
4980 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4982 N = N->getOperand(0).getNode();
4983 if (!ISD::isNON_EXTLoad(N))
4986 *LD = cast<LoadSDNode>(N);
4990 // Test whether the given value is a vector value which will be legalized
4992 static bool WillBeConstantPoolLoad(SDNode *N) {
4993 if (N->getOpcode() != ISD::BUILD_VECTOR)
4996 // Check for any non-constant elements.
4997 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4998 switch (N->getOperand(i).getNode()->getOpcode()) {
5000 case ISD::ConstantFP:
5007 // Vectors of all-zeros and all-ones are materialized with special
5008 // instructions rather than being loaded.
5009 return !ISD::isBuildVectorAllZeros(N) &&
5010 !ISD::isBuildVectorAllOnes(N);
5013 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
5014 /// match movlp{s|d}. The lower half elements should come from lower half of
5015 /// V1 (and in order), and the upper half elements should come from the upper
5016 /// half of V2 (and in order). And since V1 will become the source of the
5017 /// MOVLP, it must be either a vector load or a scalar load to vector.
5018 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
5019 ArrayRef<int> Mask, MVT VT) {
5020 if (!VT.is128BitVector())
5023 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
5025 // Is V2 is a vector load, don't do this transformation. We will try to use
5026 // load folding shufps op.
5027 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
5030 unsigned NumElems = VT.getVectorNumElements();
5032 if (NumElems != 2 && NumElems != 4)
5034 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
5035 if (!isUndefOrEqual(Mask[i], i))
5037 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
5038 if (!isUndefOrEqual(Mask[i], i+NumElems))
5043 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
5044 /// to an zero vector.
5045 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
5046 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
5047 SDValue V1 = N->getOperand(0);
5048 SDValue V2 = N->getOperand(1);
5049 unsigned NumElems = N->getValueType(0).getVectorNumElements();
5050 for (unsigned i = 0; i != NumElems; ++i) {
5051 int Idx = N->getMaskElt(i);
5052 if (Idx >= (int)NumElems) {
5053 unsigned Opc = V2.getOpcode();
5054 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
5056 if (Opc != ISD::BUILD_VECTOR ||
5057 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
5059 } else if (Idx >= 0) {
5060 unsigned Opc = V1.getOpcode();
5061 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
5063 if (Opc != ISD::BUILD_VECTOR ||
5064 !X86::isZeroNode(V1.getOperand(Idx)))
5071 /// getZeroVector - Returns a vector of specified type with all zero elements.
5073 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
5074 SelectionDAG &DAG, SDLoc dl) {
5075 assert(VT.isVector() && "Expected a vector type");
5077 // Always build SSE zero vectors as <4 x i32> bitcasted
5078 // to their dest type. This ensures they get CSE'd.
5080 if (VT.is128BitVector()) { // SSE
5081 if (Subtarget->hasSSE2()) { // SSE2
5082 SDValue Cst = DAG.getConstant(0, MVT::i32);
5083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5085 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5086 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
5088 } else if (VT.is256BitVector()) { // AVX
5089 if (Subtarget->hasInt256()) { // AVX2
5090 SDValue Cst = DAG.getConstant(0, MVT::i32);
5091 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5092 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5094 // 256-bit logic and arithmetic instructions in AVX are all
5095 // floating-point, no support for integer ops. Emit fp zeroed vectors.
5096 SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);
5097 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5098 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
5100 } else if (VT.is512BitVector()) { // AVX-512
5101 SDValue Cst = DAG.getConstant(0, MVT::i32);
5102 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
5103 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5104 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
5105 } else if (VT.getScalarType() == MVT::i1) {
5106 assert(VT.getVectorNumElements() <= 16 && "Unexpected vector type");
5107 SDValue Cst = DAG.getConstant(0, MVT::i1);
5108 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5109 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5111 llvm_unreachable("Unexpected vector type");
5113 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5116 /// getOnesVector - Returns a vector of specified type with all bits set.
5117 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
5118 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
5119 /// Then bitcast to their original type, ensuring they get CSE'd.
5120 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
5122 assert(VT.isVector() && "Expected a vector type");
5124 SDValue Cst = DAG.getConstant(~0U, MVT::i32);
5126 if (VT.is256BitVector()) {
5127 if (HasInt256) { // AVX2
5128 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
5129 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
5131 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5132 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
5134 } else if (VT.is128BitVector()) {
5135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
5137 llvm_unreachable("Unexpected vector type");
5139 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
5142 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
5143 /// that point to V2 points to its first element.
5144 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
5145 for (unsigned i = 0; i != NumElems; ++i) {
5146 if (Mask[i] > (int)NumElems) {
5152 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
5153 /// operation of specified width.
5154 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
5156 unsigned NumElems = VT.getVectorNumElements();
5157 SmallVector<int, 8> Mask;
5158 Mask.push_back(NumElems);
5159 for (unsigned i = 1; i != NumElems; ++i)
5161 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5164 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
5165 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5167 unsigned NumElems = VT.getVectorNumElements();
5168 SmallVector<int, 8> Mask;
5169 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
5171 Mask.push_back(i + NumElems);
5173 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5176 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
5177 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
5179 unsigned NumElems = VT.getVectorNumElements();
5180 SmallVector<int, 8> Mask;
5181 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
5182 Mask.push_back(i + Half);
5183 Mask.push_back(i + NumElems + Half);
5185 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
5188 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
5189 // a generic shuffle instruction because the target has no such instructions.
5190 // Generate shuffles which repeat i16 and i8 several times until they can be
5191 // represented by v4f32 and then be manipulated by target suported shuffles.
5192 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
5193 MVT VT = V.getSimpleValueType();
5194 int NumElems = VT.getVectorNumElements();
5197 while (NumElems > 4) {
5198 if (EltNo < NumElems/2) {
5199 V = getUnpackl(DAG, dl, VT, V, V);
5201 V = getUnpackh(DAG, dl, VT, V, V);
5202 EltNo -= NumElems/2;
5209 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
5210 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
5211 MVT VT = V.getSimpleValueType();
5214 if (VT.is128BitVector()) {
5215 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
5216 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
5217 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
5219 } else if (VT.is256BitVector()) {
5220 // To use VPERMILPS to splat scalars, the second half of indicies must
5221 // refer to the higher part, which is a duplication of the lower one,
5222 // because VPERMILPS can only handle in-lane permutations.
5223 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
5224 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
5226 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
5227 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
5230 llvm_unreachable("Vector size not supported");
5232 return DAG.getNode(ISD::BITCAST, dl, VT, V);
5235 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
5236 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
5237 MVT SrcVT = SV->getSimpleValueType(0);
5238 SDValue V1 = SV->getOperand(0);
5241 int EltNo = SV->getSplatIndex();
5242 int NumElems = SrcVT.getVectorNumElements();
5243 bool Is256BitVec = SrcVT.is256BitVector();
5245 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
5246 "Unknown how to promote splat for type");
5248 // Extract the 128-bit part containing the splat element and update
5249 // the splat element index when it refers to the higher register.
5251 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
5252 if (EltNo >= NumElems/2)
5253 EltNo -= NumElems/2;
5256 // All i16 and i8 vector types can't be used directly by a generic shuffle
5257 // instruction because the target has no such instruction. Generate shuffles
5258 // which repeat i16 and i8 several times until they fit in i32, and then can
5259 // be manipulated by target suported shuffles.
5260 MVT EltVT = SrcVT.getVectorElementType();
5261 if (EltVT == MVT::i8 || EltVT == MVT::i16)
5262 V1 = PromoteSplati8i16(V1, DAG, EltNo);
5264 // Recreate the 256-bit vector and place the same 128-bit vector
5265 // into the low and high part. This is necessary because we want
5266 // to use VPERM* to shuffle the vectors
5268 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
5271 return getLegalSplat(DAG, V1, EltNo);
5274 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
5275 /// vector of zero or undef vector. This produces a shuffle where the low
5276 /// element of V2 is swizzled into the zero/undef vector, landing at element
5277 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
5278 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
5280 const X86Subtarget *Subtarget,
5281 SelectionDAG &DAG) {
5282 MVT VT = V2.getSimpleValueType();
5284 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
5285 unsigned NumElems = VT.getVectorNumElements();
5286 SmallVector<int, 16> MaskVec;
5287 for (unsigned i = 0; i != NumElems; ++i)
5288 // If this is the insertion idx, put the low elt of V2 here.
5289 MaskVec.push_back(i == Idx ? NumElems : i);
5290 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
5293 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
5294 /// target specific opcode. Returns true if the Mask could be calculated. Sets
5295 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
5296 /// shuffles which use a single input multiple times, and in those cases it will
5297 /// adjust the mask to only have indices within that single input.
5298 static bool getTargetShuffleMask(SDNode *N, MVT VT,
5299 SmallVectorImpl<int> &Mask, bool &IsUnary) {
5300 unsigned NumElems = VT.getVectorNumElements();
5304 bool IsFakeUnary = false;
5305 switch(N->getOpcode()) {
5306 case X86ISD::BLENDI:
5307 ImmN = N->getOperand(N->getNumOperands()-1);
5308 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5311 ImmN = N->getOperand(N->getNumOperands()-1);
5312 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5313 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5315 case X86ISD::UNPCKH:
5316 DecodeUNPCKHMask(VT, Mask);
5317 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5319 case X86ISD::UNPCKL:
5320 DecodeUNPCKLMask(VT, Mask);
5321 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5323 case X86ISD::MOVHLPS:
5324 DecodeMOVHLPSMask(NumElems, Mask);
5325 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5327 case X86ISD::MOVLHPS:
5328 DecodeMOVLHPSMask(NumElems, Mask);
5329 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
5331 case X86ISD::PALIGNR:
5332 ImmN = N->getOperand(N->getNumOperands()-1);
5333 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5335 case X86ISD::PSHUFD:
5336 case X86ISD::VPERMILPI:
5337 ImmN = N->getOperand(N->getNumOperands()-1);
5338 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5341 case X86ISD::PSHUFHW:
5342 ImmN = N->getOperand(N->getNumOperands()-1);
5343 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5346 case X86ISD::PSHUFLW:
5347 ImmN = N->getOperand(N->getNumOperands()-1);
5348 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5351 case X86ISD::PSHUFB: {
5353 SDValue MaskNode = N->getOperand(1);
5354 while (MaskNode->getOpcode() == ISD::BITCAST)
5355 MaskNode = MaskNode->getOperand(0);
5357 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
5358 // If we have a build-vector, then things are easy.
5359 EVT VT = MaskNode.getValueType();
5360 assert(VT.isVector() &&
5361 "Can't produce a non-vector with a build_vector!");
5362 if (!VT.isInteger())
5365 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
5367 SmallVector<uint64_t, 32> RawMask;
5368 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
5369 SDValue Op = MaskNode->getOperand(i);
5370 if (Op->getOpcode() == ISD::UNDEF) {
5371 RawMask.push_back((uint64_t)SM_SentinelUndef);
5374 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
5377 APInt MaskElement = CN->getAPIntValue();
5379 // We now have to decode the element which could be any integer size and
5380 // extract each byte of it.
5381 for (int j = 0; j < NumBytesPerElement; ++j) {
5382 // Note that this is x86 and so always little endian: the low byte is
5383 // the first byte of the mask.
5384 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
5385 MaskElement = MaskElement.lshr(8);
5388 DecodePSHUFBMask(RawMask, Mask);
5392 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
5396 SDValue Ptr = MaskLoad->getBasePtr();
5397 if (Ptr->getOpcode() == X86ISD::Wrapper)
5398 Ptr = Ptr->getOperand(0);
5400 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
5401 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5404 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5405 // FIXME: Support AVX-512 here.
5406 Type *Ty = C->getType();
5407 if (!Ty->isVectorTy() || (Ty->getVectorNumElements() != 16 &&
5408 Ty->getVectorNumElements() != 32))
5411 DecodePSHUFBMask(C, Mask);
5417 case X86ISD::VPERMI:
5418 ImmN = N->getOperand(N->getNumOperands()-1);
5419 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5423 case X86ISD::MOVSD: {
5424 // The index 0 always comes from the first element of the second source,
5425 // this is why MOVSS and MOVSD are used in the first place. The other
5426 // elements come from the other positions of the first source vector
5427 Mask.push_back(NumElems);
5428 for (unsigned i = 1; i != NumElems; ++i) {
5433 case X86ISD::VPERM2X128:
5434 ImmN = N->getOperand(N->getNumOperands()-1);
5435 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
5436 if (Mask.empty()) return false;
5438 case X86ISD::MOVSLDUP:
5439 DecodeMOVSLDUPMask(VT, Mask);
5441 case X86ISD::MOVSHDUP:
5442 DecodeMOVSHDUPMask(VT, Mask);
5444 case X86ISD::MOVDDUP:
5445 case X86ISD::MOVLHPD:
5446 case X86ISD::MOVLPD:
5447 case X86ISD::MOVLPS:
5448 // Not yet implemented
5450 default: llvm_unreachable("unknown target shuffle node");
5453 // If we have a fake unary shuffle, the shuffle mask is spread across two
5454 // inputs that are actually the same node. Re-map the mask to always point
5455 // into the first input.
5458 if (M >= (int)Mask.size())
5464 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
5465 /// element of the result of the vector shuffle.
5466 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5469 return SDValue(); // Limit search depth.
5471 SDValue V = SDValue(N, 0);
5472 EVT VT = V.getValueType();
5473 unsigned Opcode = V.getOpcode();
5475 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5476 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5477 int Elt = SV->getMaskElt(Index);
5480 return DAG.getUNDEF(VT.getVectorElementType());
5482 unsigned NumElems = VT.getVectorNumElements();
5483 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5484 : SV->getOperand(1);
5485 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5488 // Recurse into target specific vector shuffles to find scalars.
5489 if (isTargetShuffle(Opcode)) {
5490 MVT ShufVT = V.getSimpleValueType();
5491 unsigned NumElems = ShufVT.getVectorNumElements();
5492 SmallVector<int, 16> ShuffleMask;
5495 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
5498 int Elt = ShuffleMask[Index];
5500 return DAG.getUNDEF(ShufVT.getVectorElementType());
5502 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
5504 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5508 // Actual nodes that may contain scalar elements
5509 if (Opcode == ISD::BITCAST) {
5510 V = V.getOperand(0);
5511 EVT SrcVT = V.getValueType();
5512 unsigned NumElems = VT.getVectorNumElements();
5514 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5518 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5519 return (Index == 0) ? V.getOperand(0)
5520 : DAG.getUNDEF(VT.getVectorElementType());
5522 if (V.getOpcode() == ISD::BUILD_VECTOR)
5523 return V.getOperand(Index);
5528 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
5529 /// shuffle operation which come from a consecutively from a zero. The
5530 /// search can start in two different directions, from left or right.
5531 /// We count undefs as zeros until PreferredNum is reached.
5532 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
5533 unsigned NumElems, bool ZerosFromLeft,
5535 unsigned PreferredNum = -1U) {
5536 unsigned NumZeros = 0;
5537 for (unsigned i = 0; i != NumElems; ++i) {
5538 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
5539 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
5543 if (X86::isZeroNode(Elt))
5545 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
5546 NumZeros = std::min(NumZeros + 1, PreferredNum);
5554 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
5555 /// correspond consecutively to elements from one of the vector operands,
5556 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
5558 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
5559 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
5560 unsigned NumElems, unsigned &OpNum) {
5561 bool SeenV1 = false;
5562 bool SeenV2 = false;
5564 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
5565 int Idx = SVOp->getMaskElt(i);
5566 // Ignore undef indicies
5570 if (Idx < (int)NumElems)
5575 // Only accept consecutive elements from the same vector
5576 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
5580 OpNum = SeenV1 ? 0 : 1;
5584 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
5585 /// logical left shift of a vector.
5586 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5587 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5589 SVOp->getSimpleValueType(0).getVectorNumElements();
5590 unsigned NumZeros = getNumOfConsecutiveZeros(
5591 SVOp, NumElems, false /* check zeros from right */, DAG,
5592 SVOp->getMaskElt(0));
5598 // Considering the elements in the mask that are not consecutive zeros,
5599 // check if they consecutively come from only one of the source vectors.
5601 // V1 = {X, A, B, C} 0
5603 // vector_shuffle V1, V2 <1, 2, 3, X>
5605 if (!isShuffleMaskConsecutive(SVOp,
5606 0, // Mask Start Index
5607 NumElems-NumZeros, // Mask End Index(exclusive)
5608 NumZeros, // Where to start looking in the src vector
5609 NumElems, // Number of elements in vector
5610 OpSrc)) // Which source operand ?
5615 ShVal = SVOp->getOperand(OpSrc);
5619 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
5620 /// logical left shift of a vector.
5621 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5622 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5624 SVOp->getSimpleValueType(0).getVectorNumElements();
5625 unsigned NumZeros = getNumOfConsecutiveZeros(
5626 SVOp, NumElems, true /* check zeros from left */, DAG,
5627 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
5633 // Considering the elements in the mask that are not consecutive zeros,
5634 // check if they consecutively come from only one of the source vectors.
5636 // 0 { A, B, X, X } = V2
5638 // vector_shuffle V1, V2 <X, X, 4, 5>
5640 if (!isShuffleMaskConsecutive(SVOp,
5641 NumZeros, // Mask Start Index
5642 NumElems, // Mask End Index(exclusive)
5643 0, // Where to start looking in the src vector
5644 NumElems, // Number of elements in vector
5645 OpSrc)) // Which source operand ?
5650 ShVal = SVOp->getOperand(OpSrc);
5654 /// isVectorShift - Returns true if the shuffle can be implemented as a
5655 /// logical left or right shift of a vector.
5656 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
5657 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
5658 // Although the logic below support any bitwidth size, there are no
5659 // shift instructions which handle more than 128-bit vectors.
5660 if (!SVOp->getSimpleValueType(0).is128BitVector())
5663 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
5664 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
5670 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
5672 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5673 unsigned NumNonZero, unsigned NumZero,
5675 const X86Subtarget* Subtarget,
5676 const TargetLowering &TLI) {
5683 for (unsigned i = 0; i < 16; ++i) {
5684 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5685 if (ThisIsNonZero && First) {
5687 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5689 V = DAG.getUNDEF(MVT::v8i16);
5694 SDValue ThisElt, LastElt;
5695 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5696 if (LastIsNonZero) {
5697 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5698 MVT::i16, Op.getOperand(i-1));
5700 if (ThisIsNonZero) {
5701 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5702 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5703 ThisElt, DAG.getConstant(8, MVT::i8));
5705 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5709 if (ThisElt.getNode())
5710 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5711 DAG.getIntPtrConstant(i/2));
5715 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
5718 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
5720 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5721 unsigned NumNonZero, unsigned NumZero,
5723 const X86Subtarget* Subtarget,
5724 const TargetLowering &TLI) {
5731 for (unsigned i = 0; i < 8; ++i) {
5732 bool isNonZero = (NonZeros & (1 << i)) != 0;
5736 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5738 V = DAG.getUNDEF(MVT::v8i16);
5741 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5742 MVT::v8i16, V, Op.getOperand(i),
5743 DAG.getIntPtrConstant(i));
5750 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
5751 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5752 const X86Subtarget *Subtarget,
5753 const TargetLowering &TLI) {
5754 // Find all zeroable elements.
5756 for (int i=0; i < 4; ++i) {
5757 SDValue Elt = Op->getOperand(i);
5758 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5760 assert(std::count_if(&Zeroable[0], &Zeroable[4],
5761 [](bool M) { return !M; }) > 1 &&
5762 "We expect at least two non-zero elements!");
5764 // We only know how to deal with build_vector nodes where elements are either
5765 // zeroable or extract_vector_elt with constant index.
5766 SDValue FirstNonZero;
5767 unsigned FirstNonZeroIdx;
5768 for (unsigned i=0; i < 4; ++i) {
5771 SDValue Elt = Op->getOperand(i);
5772 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5773 !isa<ConstantSDNode>(Elt.getOperand(1)))
5775 // Make sure that this node is extracting from a 128-bit vector.
5776 MVT VT = Elt.getOperand(0).getSimpleValueType();
5777 if (!VT.is128BitVector())
5779 if (!FirstNonZero.getNode()) {
5781 FirstNonZeroIdx = i;
5785 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5786 SDValue V1 = FirstNonZero.getOperand(0);
5787 MVT VT = V1.getSimpleValueType();
5789 // See if this build_vector can be lowered as a blend with zero.
5791 unsigned EltMaskIdx, EltIdx;
5793 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5794 if (Zeroable[EltIdx]) {
5795 // The zero vector will be on the right hand side.
5796 Mask[EltIdx] = EltIdx+4;
5800 Elt = Op->getOperand(EltIdx);
5801 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5802 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5803 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5805 Mask[EltIdx] = EltIdx;
5809 // Let the shuffle legalizer deal with blend operations.
5810 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5811 if (V1.getSimpleValueType() != VT)
5812 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5813 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5816 // See if we can lower this build_vector to a INSERTPS.
5817 if (!Subtarget->hasSSE41())
5820 SDValue V2 = Elt.getOperand(0);
5821 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5824 bool CanFold = true;
5825 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5829 SDValue Current = Op->getOperand(i);
5830 SDValue SrcVector = Current->getOperand(0);
5833 CanFold = SrcVector == V1 &&
5834 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5840 assert(V1.getNode() && "Expected at least two non-zero elements!");
5841 if (V1.getSimpleValueType() != MVT::v4f32)
5842 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5843 if (V2.getSimpleValueType() != MVT::v4f32)
5844 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5846 // Ok, we can emit an INSERTPS instruction.
5848 for (int i = 0; i < 4; ++i)
5852 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5853 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5854 SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,
5855 DAG.getIntPtrConstant(InsertPSMask));
5856 return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);
5859 /// getVShift - Return a vector logical shift node.
5861 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5862 unsigned NumBits, SelectionDAG &DAG,
5863 const TargetLowering &TLI, SDLoc dl) {
5864 assert(VT.is128BitVector() && "Unknown type for VShift");
5865 EVT ShVT = MVT::v2i64;
5866 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5867 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
5868 return DAG.getNode(ISD::BITCAST, dl, VT,
5869 DAG.getNode(Opc, dl, ShVT, SrcOp,
5870 DAG.getConstant(NumBits,
5871 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
5875 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5877 // Check if the scalar load can be widened into a vector load. And if
5878 // the address is "base + cst" see if the cst can be "absorbed" into
5879 // the shuffle mask.
5880 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5881 SDValue Ptr = LD->getBasePtr();
5882 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5884 EVT PVT = LD->getValueType(0);
5885 if (PVT != MVT::i32 && PVT != MVT::f32)
5890 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5891 FI = FINode->getIndex();
5893 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5894 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5895 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5896 Offset = Ptr.getConstantOperandVal(1);
5897 Ptr = Ptr.getOperand(0);
5902 // FIXME: 256-bit vector instructions don't require a strict alignment,
5903 // improve this code to support it better.
5904 unsigned RequiredAlign = VT.getSizeInBits()/8;
5905 SDValue Chain = LD->getChain();
5906 // Make sure the stack object alignment is at least 16 or 32.
5907 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5908 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5909 if (MFI->isFixedObjectIndex(FI)) {
5910 // Can't change the alignment. FIXME: It's possible to compute
5911 // the exact stack offset and reference FI + adjust offset instead.
5912 // If someone *really* cares about this. That's the way to implement it.
5915 MFI->setObjectAlignment(FI, RequiredAlign);
5919 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5920 // Ptr + (Offset & ~15).
5923 if ((Offset % RequiredAlign) & 3)
5925 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5927 Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),
5928 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5930 int EltNo = (Offset - StartOffset) >> 2;
5931 unsigned NumElems = VT.getVectorNumElements();
5933 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5934 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5935 LD->getPointerInfo().getWithOffset(StartOffset),
5936 false, false, false, 0);
5938 SmallVector<int, 8> Mask;
5939 for (unsigned i = 0; i != NumElems; ++i)
5940 Mask.push_back(EltNo);
5942 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5948 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5949 /// vector of type 'VT', see if the elements can be replaced by a single large
5950 /// load which has the same value as a build_vector whose operands are 'elts'.
5952 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5954 /// FIXME: we'd also like to handle the case where the last elements are zero
5955 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5956 /// There's even a handy isZeroNode for that purpose.
5957 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5958 SDLoc &DL, SelectionDAG &DAG,
5959 bool isAfterLegalize) {
5960 EVT EltVT = VT.getVectorElementType();
5961 unsigned NumElems = Elts.size();
5963 LoadSDNode *LDBase = nullptr;
5964 unsigned LastLoadedElt = -1U;
5966 // For each element in the initializer, see if we've found a load or an undef.
5967 // If we don't find an initial load element, or later load elements are
5968 // non-consecutive, bail out.
5969 for (unsigned i = 0; i < NumElems; ++i) {
5970 SDValue Elt = Elts[i];
5972 if (!Elt.getNode() ||
5973 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5976 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5978 LDBase = cast<LoadSDNode>(Elt.getNode());
5982 if (Elt.getOpcode() == ISD::UNDEF)
5985 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5986 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5991 // If we have found an entire vector of loads and undefs, then return a large
5992 // load of the entire vector width starting at the base pointer. If we found
5993 // consecutive loads for the low half, generate a vzext_load node.
5994 if (LastLoadedElt == NumElems - 1) {
5996 if (isAfterLegalize &&
5997 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
6000 SDValue NewLd = SDValue();
6002 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
6003 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6004 LDBase->getPointerInfo(),
6005 LDBase->isVolatile(), LDBase->isNonTemporal(),
6006 LDBase->isInvariant(), 0);
6007 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
6008 LDBase->getPointerInfo(),
6009 LDBase->isVolatile(), LDBase->isNonTemporal(),
6010 LDBase->isInvariant(), LDBase->getAlignment());
6012 if (LDBase->hasAnyUseOfValue(1)) {
6013 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6015 SDValue(NewLd.getNode(), 1));
6016 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6017 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6018 SDValue(NewLd.getNode(), 1));
6024 //TODO: The code below fires only for for loading the low v2i32 / v2f32
6025 //of a v4i32 / v4f32. It's probably worth generalizing.
6026 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
6027 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
6028 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
6029 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
6031 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
6032 LDBase->getPointerInfo(),
6033 LDBase->getAlignment(),
6034 false/*isVolatile*/, true/*ReadMem*/,
6037 // Make sure the newly-created LOAD is in the same position as LDBase in
6038 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
6039 // update uses of LDBase's output chain to use the TokenFactor.
6040 if (LDBase->hasAnyUseOfValue(1)) {
6041 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
6042 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
6043 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
6044 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
6045 SDValue(ResNode.getNode(), 1));
6048 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
6053 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
6054 /// to generate a splat value for the following cases:
6055 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
6056 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
6057 /// a scalar load, or a constant.
6058 /// The VBROADCAST node is returned when a pattern is found,
6059 /// or SDValue() otherwise.
6060 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
6061 SelectionDAG &DAG) {
6062 // VBROADCAST requires AVX.
6063 // TODO: Splats could be generated for non-AVX CPUs using SSE
6064 // instructions, but there's less potential gain for only 128-bit vectors.
6065 if (!Subtarget->hasAVX())
6068 MVT VT = Op.getSimpleValueType();
6071 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
6072 "Unsupported vector type for broadcast.");
6077 switch (Op.getOpcode()) {
6079 // Unknown pattern found.
6082 case ISD::BUILD_VECTOR: {
6083 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
6084 BitVector UndefElements;
6085 SDValue Splat = BVOp->getSplatValue(&UndefElements);
6087 // We need a splat of a single value to use broadcast, and it doesn't
6088 // make any sense if the value is only in one element of the vector.
6089 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
6093 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6094 Ld.getOpcode() == ISD::ConstantFP);
6096 // Make sure that all of the users of a non-constant load are from the
6097 // BUILD_VECTOR node.
6098 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
6103 case ISD::VECTOR_SHUFFLE: {
6104 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6106 // Shuffles must have a splat mask where the first element is
6108 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
6111 SDValue Sc = Op.getOperand(0);
6112 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
6113 Sc.getOpcode() != ISD::BUILD_VECTOR) {
6115 if (!Subtarget->hasInt256())
6118 // Use the register form of the broadcast instruction available on AVX2.
6119 if (VT.getSizeInBits() >= 256)
6120 Sc = Extract128BitVector(Sc, 0, DAG, dl);
6121 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
6124 Ld = Sc.getOperand(0);
6125 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
6126 Ld.getOpcode() == ISD::ConstantFP);
6128 // The scalar_to_vector node and the suspected
6129 // load node must have exactly one user.
6130 // Constants may have multiple users.
6132 // AVX-512 has register version of the broadcast
6133 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
6134 Ld.getValueType().getSizeInBits() >= 32;
6135 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
6142 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
6143 bool IsGE256 = (VT.getSizeInBits() >= 256);
6145 // When optimizing for size, generate up to 5 extra bytes for a broadcast
6146 // instruction to save 8 or more bytes of constant pool data.
6147 // TODO: If multiple splats are generated to load the same constant,
6148 // it may be detrimental to overall size. There needs to be a way to detect
6149 // that condition to know if this is truly a size win.
6150 const Function *F = DAG.getMachineFunction().getFunction();
6151 bool OptForSize = F->getAttributes().
6152 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6154 // Handle broadcasting a single constant scalar from the constant pool
6156 // On Sandybridge (no AVX2), it is still better to load a constant vector
6157 // from the constant pool and not to broadcast it from a scalar.
6158 // But override that restriction when optimizing for size.
6159 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
6160 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
6161 EVT CVT = Ld.getValueType();
6162 assert(!CVT.isVector() && "Must not broadcast a vector type");
6164 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
6165 // For size optimization, also splat v2f64 and v2i64, and for size opt
6166 // with AVX2, also splat i8 and i16.
6167 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
6168 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
6169 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
6170 const Constant *C = nullptr;
6171 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
6172 C = CI->getConstantIntValue();
6173 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
6174 C = CF->getConstantFPValue();
6176 assert(C && "Invalid constant type");
6178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6179 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
6180 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
6181 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
6182 MachinePointerInfo::getConstantPool(),
6183 false, false, false, Alignment);
6185 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6189 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
6191 // Handle AVX2 in-register broadcasts.
6192 if (!IsLoad && Subtarget->hasInt256() &&
6193 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
6194 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6196 // The scalar source must be a normal load.
6200 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64))
6201 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6203 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
6204 // double since there is no vbroadcastsd xmm
6205 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
6206 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
6207 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
6210 // Unsupported broadcast.
6214 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
6215 /// underlying vector and index.
6217 /// Modifies \p ExtractedFromVec to the real vector and returns the real
6219 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
6221 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
6222 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
6225 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
6227 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
6229 // (extract_vector_elt (vector_shuffle<2,u,u,u>
6230 // (extract_subvector (v8f32 %vreg0), Constant<4>),
6233 // In this case the vector is the extract_subvector expression and the index
6234 // is 2, as specified by the shuffle.
6235 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
6236 SDValue ShuffleVec = SVOp->getOperand(0);
6237 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
6238 assert(ShuffleVecVT.getVectorElementType() ==
6239 ExtractedFromVec.getSimpleValueType().getVectorElementType());
6241 int ShuffleIdx = SVOp->getMaskElt(Idx);
6242 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
6243 ExtractedFromVec = ShuffleVec;
6249 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
6250 MVT VT = Op.getSimpleValueType();
6252 // Skip if insert_vec_elt is not supported.
6253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6254 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
6258 unsigned NumElems = Op.getNumOperands();
6262 SmallVector<unsigned, 4> InsertIndices;
6263 SmallVector<int, 8> Mask(NumElems, -1);
6265 for (unsigned i = 0; i != NumElems; ++i) {
6266 unsigned Opc = Op.getOperand(i).getOpcode();
6268 if (Opc == ISD::UNDEF)
6271 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
6272 // Quit if more than 1 elements need inserting.
6273 if (InsertIndices.size() > 1)
6276 InsertIndices.push_back(i);
6280 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
6281 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
6282 // Quit if non-constant index.
6283 if (!isa<ConstantSDNode>(ExtIdx))
6285 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
6287 // Quit if extracted from vector of different type.
6288 if (ExtractedFromVec.getValueType() != VT)
6291 if (!VecIn1.getNode())
6292 VecIn1 = ExtractedFromVec;
6293 else if (VecIn1 != ExtractedFromVec) {
6294 if (!VecIn2.getNode())
6295 VecIn2 = ExtractedFromVec;
6296 else if (VecIn2 != ExtractedFromVec)
6297 // Quit if more than 2 vectors to shuffle
6301 if (ExtractedFromVec == VecIn1)
6303 else if (ExtractedFromVec == VecIn2)
6304 Mask[i] = Idx + NumElems;
6307 if (!VecIn1.getNode())
6310 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6311 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
6312 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
6313 unsigned Idx = InsertIndices[i];
6314 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
6315 DAG.getIntPtrConstant(Idx));
6321 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
6323 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
6325 MVT VT = Op.getSimpleValueType();
6326 assert((VT.getVectorElementType() == MVT::i1) && (VT.getSizeInBits() <= 16) &&
6327 "Unexpected type in LowerBUILD_VECTORvXi1!");
6330 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6331 SDValue Cst = DAG.getTargetConstant(0, MVT::i1);
6332 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6333 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6336 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
6337 SDValue Cst = DAG.getTargetConstant(1, MVT::i1);
6338 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
6339 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
6342 bool AllContants = true;
6343 uint64_t Immediate = 0;
6344 int NonConstIdx = -1;
6345 bool IsSplat = true;
6346 unsigned NumNonConsts = 0;
6347 unsigned NumConsts = 0;
6348 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
6349 SDValue In = Op.getOperand(idx);
6350 if (In.getOpcode() == ISD::UNDEF)
6352 if (!isa<ConstantSDNode>(In)) {
6353 AllContants = false;
6358 if (cast<ConstantSDNode>(In)->getZExtValue())
6359 Immediate |= (1ULL << idx);
6361 if (In != Op.getOperand(0))
6366 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,
6367 DAG.getConstant(Immediate, MVT::i16));
6368 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,
6369 DAG.getIntPtrConstant(0));
6372 if (NumNonConsts == 1 && NonConstIdx != 0) {
6375 SDValue VecAsImm = DAG.getConstant(Immediate,
6376 MVT::getIntegerVT(VT.getSizeInBits()));
6377 DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);
6380 DstVec = DAG.getUNDEF(VT);
6381 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
6382 Op.getOperand(NonConstIdx),
6383 DAG.getIntPtrConstant(NonConstIdx));
6385 if (!IsSplat && (NonConstIdx != 0))
6386 llvm_unreachable("Unsupported BUILD_VECTOR operation");
6387 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8;
6390 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6391 DAG.getConstant(-1, SelectVT),
6392 DAG.getConstant(0, SelectVT));
6394 Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),
6395 DAG.getConstant((Immediate | 1), SelectVT),
6396 DAG.getConstant(Immediate, SelectVT));
6397 return DAG.getNode(ISD::BITCAST, dl, VT, Select);
6400 /// \brief Return true if \p N implements a horizontal binop and return the
6401 /// operands for the horizontal binop into V0 and V1.
6403 /// This is a helper function of PerformBUILD_VECTORCombine.
6404 /// This function checks that the build_vector \p N in input implements a
6405 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
6406 /// operation to match.
6407 /// For example, if \p Opcode is equal to ISD::ADD, then this function
6408 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
6409 /// is equal to ISD::SUB, then this function checks if this is a horizontal
6412 /// This function only analyzes elements of \p N whose indices are
6413 /// in range [BaseIdx, LastIdx).
6414 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
6416 unsigned BaseIdx, unsigned LastIdx,
6417 SDValue &V0, SDValue &V1) {
6418 EVT VT = N->getValueType(0);
6420 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
6421 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
6422 "Invalid Vector in input!");
6424 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
6425 bool CanFold = true;
6426 unsigned ExpectedVExtractIdx = BaseIdx;
6427 unsigned NumElts = LastIdx - BaseIdx;
6428 V0 = DAG.getUNDEF(VT);
6429 V1 = DAG.getUNDEF(VT);
6431 // Check if N implements a horizontal binop.
6432 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
6433 SDValue Op = N->getOperand(i + BaseIdx);
6436 if (Op->getOpcode() == ISD::UNDEF) {
6437 // Update the expected vector extract index.
6438 if (i * 2 == NumElts)
6439 ExpectedVExtractIdx = BaseIdx;
6440 ExpectedVExtractIdx += 2;
6444 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
6449 SDValue Op0 = Op.getOperand(0);
6450 SDValue Op1 = Op.getOperand(1);
6452 // Try to match the following pattern:
6453 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
6454 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6455 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6456 Op0.getOperand(0) == Op1.getOperand(0) &&
6457 isa<ConstantSDNode>(Op0.getOperand(1)) &&
6458 isa<ConstantSDNode>(Op1.getOperand(1)));
6462 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6463 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
6465 if (i * 2 < NumElts) {
6466 if (V0.getOpcode() == ISD::UNDEF)
6467 V0 = Op0.getOperand(0);
6469 if (V1.getOpcode() == ISD::UNDEF)
6470 V1 = Op0.getOperand(0);
6471 if (i * 2 == NumElts)
6472 ExpectedVExtractIdx = BaseIdx;
6475 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
6476 if (I0 == ExpectedVExtractIdx)
6477 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
6478 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
6479 // Try to match the following dag sequence:
6480 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
6481 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
6485 ExpectedVExtractIdx += 2;
6491 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
6492 /// a concat_vector.
6494 /// This is a helper function of PerformBUILD_VECTORCombine.
6495 /// This function expects two 256-bit vectors called V0 and V1.
6496 /// At first, each vector is split into two separate 128-bit vectors.
6497 /// Then, the resulting 128-bit vectors are used to implement two
6498 /// horizontal binary operations.
6500 /// The kind of horizontal binary operation is defined by \p X86Opcode.
6502 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
6503 /// the two new horizontal binop.
6504 /// When Mode is set, the first horizontal binop dag node would take as input
6505 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
6506 /// horizontal binop dag node would take as input the lower 128-bit of V1
6507 /// and the upper 128-bit of V1.
6509 /// HADD V0_LO, V0_HI
6510 /// HADD V1_LO, V1_HI
6512 /// Otherwise, the first horizontal binop dag node takes as input the lower
6513 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
6514 /// dag node takes the the upper 128-bit of V0 and the upper 128-bit of V1.
6516 /// HADD V0_LO, V1_LO
6517 /// HADD V0_HI, V1_HI
6519 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
6520 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
6521 /// the upper 128-bits of the result.
6522 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6523 SDLoc DL, SelectionDAG &DAG,
6524 unsigned X86Opcode, bool Mode,
6525 bool isUndefLO, bool isUndefHI) {
6526 EVT VT = V0.getValueType();
6527 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6528 "Invalid nodes in input!");
6530 unsigned NumElts = VT.getVectorNumElements();
6531 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6532 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6533 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6534 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6535 EVT NewVT = V0_LO.getValueType();
6537 SDValue LO = DAG.getUNDEF(NewVT);
6538 SDValue HI = DAG.getUNDEF(NewVT);
6541 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6542 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6543 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6544 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6545 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6547 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6548 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6549 V1_LO->getOpcode() != ISD::UNDEF))
6550 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6552 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6553 V1_HI->getOpcode() != ISD::UNDEF))
6554 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6557 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6560 /// \brief Try to fold a build_vector that performs an 'addsub' into the
6561 /// sequence of 'vadd + vsub + blendi'.
6562 static SDValue matchAddSub(const BuildVectorSDNode *BV, SelectionDAG &DAG,
6563 const X86Subtarget *Subtarget) {
6565 EVT VT = BV->getValueType(0);
6566 unsigned NumElts = VT.getVectorNumElements();
6567 SDValue InVec0 = DAG.getUNDEF(VT);
6568 SDValue InVec1 = DAG.getUNDEF(VT);
6570 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6571 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6573 // Odd-numbered elements in the input build vector are obtained from
6574 // adding two integer/float elements.
6575 // Even-numbered elements in the input build vector are obtained from
6576 // subtracting two integer/float elements.
6577 unsigned ExpectedOpcode = ISD::FSUB;
6578 unsigned NextExpectedOpcode = ISD::FADD;
6579 bool AddFound = false;
6580 bool SubFound = false;
6582 for (unsigned i = 0, e = NumElts; i != e; i++) {
6583 SDValue Op = BV->getOperand(i);
6585 // Skip 'undef' values.
6586 unsigned Opcode = Op.getOpcode();
6587 if (Opcode == ISD::UNDEF) {
6588 std::swap(ExpectedOpcode, NextExpectedOpcode);
6592 // Early exit if we found an unexpected opcode.
6593 if (Opcode != ExpectedOpcode)
6596 SDValue Op0 = Op.getOperand(0);
6597 SDValue Op1 = Op.getOperand(1);
6599 // Try to match the following pattern:
6600 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6601 // Early exit if we cannot match that sequence.
6602 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6603 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6604 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6605 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6606 Op0.getOperand(1) != Op1.getOperand(1))
6609 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6613 // We found a valid add/sub node. Update the information accordingly.
6619 // Update InVec0 and InVec1.
6620 if (InVec0.getOpcode() == ISD::UNDEF)
6621 InVec0 = Op0.getOperand(0);
6622 if (InVec1.getOpcode() == ISD::UNDEF)
6623 InVec1 = Op1.getOperand(0);
6625 // Make sure that operands in input to each add/sub node always
6626 // come from a same pair of vectors.
6627 if (InVec0 != Op0.getOperand(0)) {
6628 if (ExpectedOpcode == ISD::FSUB)
6631 // FADD is commutable. Try to commute the operands
6632 // and then test again.
6633 std::swap(Op0, Op1);
6634 if (InVec0 != Op0.getOperand(0))
6638 if (InVec1 != Op1.getOperand(0))
6641 // Update the pair of expected opcodes.
6642 std::swap(ExpectedOpcode, NextExpectedOpcode);
6645 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6646 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6647 InVec1.getOpcode() != ISD::UNDEF)
6648 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6653 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG,
6654 const X86Subtarget *Subtarget) {
6656 EVT VT = N->getValueType(0);
6657 unsigned NumElts = VT.getVectorNumElements();
6658 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
6659 SDValue InVec0, InVec1;
6661 // Try to match an ADDSUB.
6662 if ((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
6663 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))) {
6664 SDValue Value = matchAddSub(BV, DAG, Subtarget);
6665 if (Value.getNode())
6669 // Try to match horizontal ADD/SUB.
6670 unsigned NumUndefsLO = 0;
6671 unsigned NumUndefsHI = 0;
6672 unsigned Half = NumElts/2;
6674 // Count the number of UNDEF operands in the build_vector in input.
6675 for (unsigned i = 0, e = Half; i != e; ++i)
6676 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6679 for (unsigned i = Half, e = NumElts; i != e; ++i)
6680 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6683 // Early exit if this is either a build_vector of all UNDEFs or all the
6684 // operands but one are UNDEF.
6685 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6688 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6689 // Try to match an SSE3 float HADD/HSUB.
6690 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6691 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6693 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6694 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6695 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6696 // Try to match an SSSE3 integer HADD/HSUB.
6697 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6698 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6700 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6701 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6704 if (!Subtarget->hasAVX())
6707 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6708 // Try to match an AVX horizontal add/sub of packed single/double
6709 // precision floating point values from 256-bit vectors.
6710 SDValue InVec2, InVec3;
6711 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6712 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6713 ((InVec0.getOpcode() == ISD::UNDEF ||
6714 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6715 ((InVec1.getOpcode() == ISD::UNDEF ||
6716 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6717 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6719 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6720 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6721 ((InVec0.getOpcode() == ISD::UNDEF ||
6722 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6723 ((InVec1.getOpcode() == ISD::UNDEF ||
6724 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6725 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6726 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6727 // Try to match an AVX2 horizontal add/sub of signed integers.
6728 SDValue InVec2, InVec3;
6730 bool CanFold = true;
6732 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6733 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6734 ((InVec0.getOpcode() == ISD::UNDEF ||
6735 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6736 ((InVec1.getOpcode() == ISD::UNDEF ||
6737 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6738 X86Opcode = X86ISD::HADD;
6739 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6740 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6741 ((InVec0.getOpcode() == ISD::UNDEF ||
6742 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6743 ((InVec1.getOpcode() == ISD::UNDEF ||
6744 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6745 X86Opcode = X86ISD::HSUB;
6750 // Fold this build_vector into a single horizontal add/sub.
6751 // Do this only if the target has AVX2.
6752 if (Subtarget->hasAVX2())
6753 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6755 // Do not try to expand this build_vector into a pair of horizontal
6756 // add/sub if we can emit a pair of scalar add/sub.
6757 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6760 // Convert this build_vector into a pair of horizontal binop followed by
6762 bool isUndefLO = NumUndefsLO == Half;
6763 bool isUndefHI = NumUndefsHI == Half;
6764 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6765 isUndefLO, isUndefHI);
6769 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6770 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6772 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6773 X86Opcode = X86ISD::HADD;
6774 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6775 X86Opcode = X86ISD::HSUB;
6776 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6777 X86Opcode = X86ISD::FHADD;
6778 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6779 X86Opcode = X86ISD::FHSUB;
6783 // Don't try to expand this build_vector into a pair of horizontal add/sub
6784 // if we can simply emit a pair of scalar add/sub.
6785 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6788 // Convert this build_vector into two horizontal add/sub followed by
6790 bool isUndefLO = NumUndefsLO == Half;
6791 bool isUndefHI = NumUndefsHI == Half;
6792 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6793 isUndefLO, isUndefHI);
6800 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6803 MVT VT = Op.getSimpleValueType();
6804 MVT ExtVT = VT.getVectorElementType();
6805 unsigned NumElems = Op.getNumOperands();
6807 // Generate vectors for predicate vectors.
6808 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6809 return LowerBUILD_VECTORvXi1(Op, DAG);
6811 // Vectors containing all zeros can be matched by pxor and xorps later
6812 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6813 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6814 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6815 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6818 return getZeroVector(VT, Subtarget, DAG, dl);
6821 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6822 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6823 // vpcmpeqd on 256-bit vectors.
6824 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6825 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6828 if (!VT.is512BitVector())
6829 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
6832 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
6833 if (Broadcast.getNode())
6836 unsigned EVTBits = ExtVT.getSizeInBits();
6838 unsigned NumZero = 0;
6839 unsigned NumNonZero = 0;
6840 unsigned NonZeros = 0;
6841 bool IsAllConstants = true;
6842 SmallSet<SDValue, 8> Values;
6843 for (unsigned i = 0; i < NumElems; ++i) {
6844 SDValue Elt = Op.getOperand(i);
6845 if (Elt.getOpcode() == ISD::UNDEF)
6848 if (Elt.getOpcode() != ISD::Constant &&
6849 Elt.getOpcode() != ISD::ConstantFP)
6850 IsAllConstants = false;
6851 if (X86::isZeroNode(Elt))
6854 NonZeros |= (1 << i);
6859 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6860 if (NumNonZero == 0)
6861 return DAG.getUNDEF(VT);
6863 // Special case for single non-zero, non-undef, element.
6864 if (NumNonZero == 1) {
6865 unsigned Idx = countTrailingZeros(NonZeros);
6866 SDValue Item = Op.getOperand(Idx);
6868 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6869 // the value are obviously zero, truncate the value to i32 and do the
6870 // insertion that way. Only do this if the value is non-constant or if the
6871 // value is a constant being inserted into element 0. It is cheaper to do
6872 // a constant pool load than it is to do a movd + shuffle.
6873 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6874 (!IsAllConstants || Idx == 0)) {
6875 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6877 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6878 EVT VecVT = MVT::v4i32;
6879 unsigned VecElts = 4;
6881 // Truncate the value (which may itself be a constant) to i32, and
6882 // convert it to a vector with movd (S2V+shuffle to zero extend).
6883 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6884 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6886 // If using the new shuffle lowering, just directly insert this.
6887 if (ExperimentalVectorShuffleLowering)
6889 ISD::BITCAST, dl, VT,
6890 getShuffleVectorZeroOrUndef(Item, Idx * 2, true, Subtarget, DAG));
6892 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6894 // Now we have our 32-bit value zero extended in the low element of
6895 // a vector. If Idx != 0, swizzle it into place.
6897 SmallVector<int, 4> Mask;
6898 Mask.push_back(Idx);
6899 for (unsigned i = 1; i != VecElts; ++i)
6901 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
6904 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6908 // If we have a constant or non-constant insertion into the low element of
6909 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6910 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6911 // depending on what the source datatype is.
6914 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6916 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6917 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6918 if (VT.is256BitVector() || VT.is512BitVector()) {
6919 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6920 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6921 Item, DAG.getIntPtrConstant(0));
6923 assert(VT.is128BitVector() && "Expected an SSE value type!");
6924 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6925 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6926 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6929 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6930 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6931 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6932 if (VT.is256BitVector()) {
6933 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6934 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6936 assert(VT.is128BitVector() && "Expected an SSE value type!");
6937 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6939 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
6943 // Is it a vector logical left shift?
6944 if (NumElems == 2 && Idx == 1 &&
6945 X86::isZeroNode(Op.getOperand(0)) &&
6946 !X86::isZeroNode(Op.getOperand(1))) {
6947 unsigned NumBits = VT.getSizeInBits();
6948 return getVShift(true, VT,
6949 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6950 VT, Op.getOperand(1)),
6951 NumBits/2, DAG, *this, dl);
6954 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6957 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6958 // is a non-constant being inserted into an element other than the low one,
6959 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6960 // movd/movss) to move this into the low element, then shuffle it into
6962 if (EVTBits == 32) {
6963 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6965 // If using the new shuffle lowering, just directly insert this.
6966 if (ExperimentalVectorShuffleLowering)
6967 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6969 // Turn it into a shuffle of zero and zero-extended scalar to vector.
6970 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
6971 SmallVector<int, 8> MaskVec;
6972 for (unsigned i = 0; i != NumElems; ++i)
6973 MaskVec.push_back(i == Idx ? 0 : 1);
6974 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
6978 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6979 if (Values.size() == 1) {
6980 if (EVTBits == 32) {
6981 // Instead of a shuffle like this:
6982 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6983 // Check if it's possible to issue this instead.
6984 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6985 unsigned Idx = countTrailingZeros(NonZeros);
6986 SDValue Item = Op.getOperand(Idx);
6987 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6988 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6993 // A vector full of immediates; various special cases are already
6994 // handled, so this is best done with a single constant-pool load.
6998 // For AVX-length vectors, see if we can use a vector load to get all of the
6999 // elements, otherwise build the individual 128-bit pieces and use
7000 // shuffles to put them in place.
7001 if (VT.is256BitVector() || VT.is512BitVector()) {
7002 SmallVector<SDValue, 64> V;
7003 for (unsigned i = 0; i != NumElems; ++i)
7004 V.push_back(Op.getOperand(i));
7006 // Check for a build vector of consecutive loads.
7007 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
7010 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
7012 // Build both the lower and upper subvector.
7013 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7014 makeArrayRef(&V[0], NumElems/2));
7015 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
7016 makeArrayRef(&V[NumElems / 2], NumElems/2));
7018 // Recreate the wider vector with the lower and upper part.
7019 if (VT.is256BitVector())
7020 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7021 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
7024 // Let legalizer expand 2-wide build_vectors.
7025 if (EVTBits == 64) {
7026 if (NumNonZero == 1) {
7027 // One half is zero or undef.
7028 unsigned Idx = countTrailingZeros(NonZeros);
7029 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
7030 Op.getOperand(Idx));
7031 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
7036 // If element VT is < 32 bits, convert it to inserts into a zero vector.
7037 if (EVTBits == 8 && NumElems == 16) {
7038 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
7040 if (V.getNode()) return V;
7043 if (EVTBits == 16 && NumElems == 8) {
7044 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
7046 if (V.getNode()) return V;
7049 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
7050 if (EVTBits == 32 && NumElems == 4) {
7051 SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this);
7056 // If element VT is == 32 bits, turn it into a number of shuffles.
7057 SmallVector<SDValue, 8> V(NumElems);
7058 if (NumElems == 4 && NumZero > 0) {
7059 for (unsigned i = 0; i < 4; ++i) {
7060 bool isZero = !(NonZeros & (1 << i));
7062 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
7064 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7067 for (unsigned i = 0; i < 2; ++i) {
7068 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
7071 V[i] = V[i*2]; // Must be a zero vector.
7074 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
7077 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
7080 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
7085 bool Reverse1 = (NonZeros & 0x3) == 2;
7086 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
7090 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
7091 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
7093 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
7096 if (Values.size() > 1 && VT.is128BitVector()) {
7097 // Check for a build vector of consecutive loads.
7098 for (unsigned i = 0; i < NumElems; ++i)
7099 V[i] = Op.getOperand(i);
7101 // Check for elements which are consecutive loads.
7102 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false);
7106 // Check for a build vector from mostly shuffle plus few inserting.
7107 SDValue Sh = buildFromShuffleMostly(Op, DAG);
7111 // For SSE 4.1, use insertps to put the high elements into the low element.
7112 if (getSubtarget()->hasSSE41()) {
7114 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
7115 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
7117 Result = DAG.getUNDEF(VT);
7119 for (unsigned i = 1; i < NumElems; ++i) {
7120 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
7121 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
7122 Op.getOperand(i), DAG.getIntPtrConstant(i));
7127 // Otherwise, expand into a number of unpckl*, start by extending each of
7128 // our (non-undef) elements to the full vector width with the element in the
7129 // bottom slot of the vector (which generates no code for SSE).
7130 for (unsigned i = 0; i < NumElems; ++i) {
7131 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
7132 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
7134 V[i] = DAG.getUNDEF(VT);
7137 // Next, we iteratively mix elements, e.g. for v4f32:
7138 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
7139 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
7140 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
7141 unsigned EltStride = NumElems >> 1;
7142 while (EltStride != 0) {
7143 for (unsigned i = 0; i < EltStride; ++i) {
7144 // If V[i+EltStride] is undef and this is the first round of mixing,
7145 // then it is safe to just drop this shuffle: V[i] is already in the
7146 // right place, the one element (since it's the first round) being
7147 // inserted as undef can be dropped. This isn't safe for successive
7148 // rounds because they will permute elements within both vectors.
7149 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
7150 EltStride == NumElems/2)
7153 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
7162 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
7163 // to create 256-bit vectors from two other 128-bit ones.
7164 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7166 MVT ResVT = Op.getSimpleValueType();
7168 assert((ResVT.is256BitVector() ||
7169 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
7171 SDValue V1 = Op.getOperand(0);
7172 SDValue V2 = Op.getOperand(1);
7173 unsigned NumElems = ResVT.getVectorNumElements();
7174 if(ResVT.is256BitVector())
7175 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7177 if (Op.getNumOperands() == 4) {
7178 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
7179 ResVT.getVectorNumElements()/2);
7180 SDValue V3 = Op.getOperand(2);
7181 SDValue V4 = Op.getOperand(3);
7182 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
7183 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
7185 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
7188 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
7189 MVT LLVM_ATTRIBUTE_UNUSED VT = Op.getSimpleValueType();
7190 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
7191 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
7192 Op.getNumOperands() == 4)));
7194 // AVX can use the vinsertf128 instruction to create 256-bit vectors
7195 // from two other 128-bit ones.
7197 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
7198 return LowerAVXCONCAT_VECTORS(Op, DAG);
7202 //===----------------------------------------------------------------------===//
7203 // Vector shuffle lowering
7205 // This is an experimental code path for lowering vector shuffles on x86. It is
7206 // designed to handle arbitrary vector shuffles and blends, gracefully
7207 // degrading performance as necessary. It works hard to recognize idiomatic
7208 // shuffles and lower them to optimal instruction patterns without leaving
7209 // a framework that allows reasonably efficient handling of all vector shuffle
7211 //===----------------------------------------------------------------------===//
7213 /// \brief Tiny helper function to identify a no-op mask.
7215 /// This is a somewhat boring predicate function. It checks whether the mask
7216 /// array input, which is assumed to be a single-input shuffle mask of the kind
7217 /// used by the X86 shuffle instructions (not a fully general
7218 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
7219 /// in-place shuffle are 'no-op's.
7220 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
7221 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7222 if (Mask[i] != -1 && Mask[i] != i)
7227 /// \brief Helper function to classify a mask as a single-input mask.
7229 /// This isn't a generic single-input test because in the vector shuffle
7230 /// lowering we canonicalize single inputs to be the first input operand. This
7231 /// means we can more quickly test for a single input by only checking whether
7232 /// an input from the second operand exists. We also assume that the size of
7233 /// mask corresponds to the size of the input vectors which isn't true in the
7234 /// fully general case.
7235 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
7237 if (M >= (int)Mask.size())
7242 /// \brief Test whether there are elements crossing 128-bit lanes in this
7245 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
7246 /// and we routinely test for these.
7247 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
7248 int LaneSize = 128 / VT.getScalarSizeInBits();
7249 int Size = Mask.size();
7250 for (int i = 0; i < Size; ++i)
7251 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
7256 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
7258 /// This checks a shuffle mask to see if it is performing the same
7259 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
7260 /// that it is also not lane-crossing. It may however involve a blend from the
7261 /// same lane of a second vector.
7263 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
7264 /// non-trivial to compute in the face of undef lanes. The representation is
7265 /// *not* suitable for use with existing 128-bit shuffles as it will contain
7266 /// entries from both V1 and V2 inputs to the wider mask.
7268 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
7269 SmallVectorImpl<int> &RepeatedMask) {
7270 int LaneSize = 128 / VT.getScalarSizeInBits();
7271 RepeatedMask.resize(LaneSize, -1);
7272 int Size = Mask.size();
7273 for (int i = 0; i < Size; ++i) {
7276 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
7277 // This entry crosses lanes, so there is no way to model this shuffle.
7280 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
7281 if (RepeatedMask[i % LaneSize] == -1)
7282 // This is the first non-undef entry in this slot of a 128-bit lane.
7283 RepeatedMask[i % LaneSize] =
7284 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
7285 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
7286 // Found a mismatch with the repeated mask.
7292 // Hide this symbol with an anonymous namespace instead of 'static' so that MSVC
7293 // 2013 will allow us to use it as a non-type template parameter.
7296 /// \brief Implementation of the \c isShuffleEquivalent variadic functor.
7298 /// See its documentation for details.
7299 bool isShuffleEquivalentImpl(ArrayRef<int> Mask, ArrayRef<const int *> Args) {
7300 if (Mask.size() != Args.size())
7302 for (int i = 0, e = Mask.size(); i < e; ++i) {
7303 assert(*Args[i] >= 0 && "Arguments must be positive integers!");
7304 if (Mask[i] != -1 && Mask[i] != *Args[i])
7312 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
7315 /// This is a fast way to test a shuffle mask against a fixed pattern:
7317 /// if (isShuffleEquivalent(Mask, 3, 2, 1, 0)) { ... }
7319 /// It returns true if the mask is exactly as wide as the argument list, and
7320 /// each element of the mask is either -1 (signifying undef) or the value given
7321 /// in the argument.
7322 static const VariadicFunction1<
7323 bool, ArrayRef<int>, int, isShuffleEquivalentImpl> isShuffleEquivalent = {};
7325 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
7327 /// This helper function produces an 8-bit shuffle immediate corresponding to
7328 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
7329 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
7332 /// NB: We rely heavily on "undef" masks preserving the input lane.
7333 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,
7334 SelectionDAG &DAG) {
7335 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
7336 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
7337 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
7338 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
7339 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
7342 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
7343 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
7344 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
7345 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
7346 return DAG.getConstant(Imm, MVT::i8);
7349 /// \brief Try to emit a blend instruction for a shuffle.
7351 /// This doesn't do any checks for the availability of instructions for blending
7352 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7353 /// be matched in the backend with the type given. What it does check for is
7354 /// that the shuffle mask is in fact a blend.
7355 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7356 SDValue V2, ArrayRef<int> Mask,
7357 const X86Subtarget *Subtarget,
7358 SelectionDAG &DAG) {
7360 unsigned BlendMask = 0;
7361 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7362 if (Mask[i] >= Size) {
7363 if (Mask[i] != i + Size)
7364 return SDValue(); // Shuffled V2 input!
7365 BlendMask |= 1u << i;
7368 if (Mask[i] >= 0 && Mask[i] != i)
7369 return SDValue(); // Shuffled V1 input!
7371 switch (VT.SimpleTy) {
7376 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7377 DAG.getConstant(BlendMask, MVT::i8));
7381 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7385 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7386 // that instruction.
7387 if (Subtarget->hasAVX2()) {
7388 // Scale the blend by the number of 32-bit dwords per element.
7389 int Scale = VT.getScalarSizeInBits() / 32;
7391 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7392 if (Mask[i] >= Size)
7393 for (int j = 0; j < Scale; ++j)
7394 BlendMask |= 1u << (i * Scale + j);
7396 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7397 V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);
7398 V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);
7399 return DAG.getNode(ISD::BITCAST, DL, VT,
7400 DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7401 DAG.getConstant(BlendMask, MVT::i8)));
7405 // For integer shuffles we need to expand the mask and cast the inputs to
7406 // v8i16s prior to blending.
7407 int Scale = 8 / VT.getVectorNumElements();
7409 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7410 if (Mask[i] >= Size)
7411 for (int j = 0; j < Scale; ++j)
7412 BlendMask |= 1u << (i * Scale + j);
7414 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
7415 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
7416 return DAG.getNode(ISD::BITCAST, DL, VT,
7417 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7418 DAG.getConstant(BlendMask, MVT::i8)));
7422 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7423 SmallVector<int, 8> RepeatedMask;
7424 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7425 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7426 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7428 for (int i = 0; i < 8; ++i)
7429 if (RepeatedMask[i] >= 16)
7430 BlendMask |= 1u << i;
7431 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7432 DAG.getConstant(BlendMask, MVT::i8));
7437 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7438 // Scale the blend by the number of bytes per element.
7439 int Scale = VT.getScalarSizeInBits() / 8;
7440 assert(Mask.size() * Scale == 32 && "Not a 256-bit vector!");
7442 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7443 // mix of LLVM's code generator and the x86 backend. We tell the code
7444 // generator that boolean values in the elements of an x86 vector register
7445 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7446 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7447 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7448 // of the element (the remaining are ignored) and 0 in that high bit would
7449 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7450 // the LLVM model for boolean values in vector elements gets the relevant
7451 // bit set, it is set backwards and over constrained relative to x86's
7453 SDValue VSELECTMask[32];
7454 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7455 for (int j = 0; j < Scale; ++j)
7456 VSELECTMask[Scale * i + j] =
7457 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7458 : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8);
7460 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1);
7461 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V2);
7463 ISD::BITCAST, DL, VT,
7464 DAG.getNode(ISD::VSELECT, DL, MVT::v32i8,
7465 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, VSELECTMask),
7470 llvm_unreachable("Not a supported integer vector type!");
7474 /// \brief Generic routine to lower a shuffle and blend as a decomposed set of
7475 /// unblended shuffles followed by an unshuffled blend.
7477 /// This matches the extremely common pattern for handling combined
7478 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7480 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7484 SelectionDAG &DAG) {
7485 // Shuffle the input elements into the desired positions in V1 and V2 and
7486 // blend them together.
7487 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7488 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7489 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7490 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7491 if (Mask[i] >= 0 && Mask[i] < Size) {
7492 V1Mask[i] = Mask[i];
7494 } else if (Mask[i] >= Size) {
7495 V2Mask[i] = Mask[i] - Size;
7496 BlendMask[i] = i + Size;
7499 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7500 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7501 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7504 /// \brief Try to lower a vector shuffle as a byte rotation.
7506 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7507 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7508 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7509 /// try to generically lower a vector shuffle through such an pattern. It
7510 /// does not check for the profitability of lowering either as PALIGNR or
7511 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7512 /// This matches shuffle vectors that look like:
7514 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7516 /// Essentially it concatenates V1 and V2, shifts right by some number of
7517 /// elements, and takes the low elements as the result. Note that while this is
7518 /// specified as a *right shift* because x86 is little-endian, it is a *left
7519 /// rotate* of the vector lanes.
7521 /// Note that this only handles 128-bit vector widths currently.
7522 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7525 const X86Subtarget *Subtarget,
7526 SelectionDAG &DAG) {
7527 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7529 // We need to detect various ways of spelling a rotation:
7530 // [11, 12, 13, 14, 15, 0, 1, 2]
7531 // [-1, 12, 13, 14, -1, -1, 1, -1]
7532 // [-1, -1, -1, -1, -1, -1, 1, 2]
7533 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7534 // [-1, 4, 5, 6, -1, -1, 9, -1]
7535 // [-1, 4, 5, 6, -1, -1, -1, -1]
7538 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7541 assert(Mask[i] >= 0 && "Only -1 is a valid negative mask element!");
7543 // Based on the mod-Size value of this mask element determine where
7544 // a rotated vector would have started.
7545 int StartIdx = i - (Mask[i] % Size);
7547 // The identity rotation isn't interesting, stop.
7550 // If we found the tail of a vector the rotation must be the missing
7551 // front. If we found the head of a vector, it must be how much of the head.
7552 int CandidateRotation = StartIdx < 0 ? -StartIdx : Size - StartIdx;
7555 Rotation = CandidateRotation;
7556 else if (Rotation != CandidateRotation)
7557 // The rotations don't match, so we can't match this mask.
7560 // Compute which value this mask is pointing at.
7561 SDValue MaskV = Mask[i] < Size ? V1 : V2;
7563 // Compute which of the two target values this index should be assigned to.
7564 // This reflects whether the high elements are remaining or the low elements
7566 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7568 // Either set up this value if we've not encountered it before, or check
7569 // that it remains consistent.
7572 else if (TargetV != MaskV)
7573 // This may be a rotation, but it pulls from the inputs in some
7574 // unsupported interleaving.
7578 // Check that we successfully analyzed the mask, and normalize the results.
7579 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7580 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7586 assert(VT.getSizeInBits() == 128 &&
7587 "Rotate-based lowering only supports 128-bit lowering!");
7588 assert(Mask.size() <= 16 &&
7589 "Can shuffle at most 16 bytes in a 128-bit vector!");
7591 // The actual rotate instruction rotates bytes, so we need to scale the
7592 // rotation based on how many bytes are in the vector.
7593 int Scale = 16 / Mask.size();
7595 // SSSE3 targets can use the palignr instruction
7596 if (Subtarget->hasSSSE3()) {
7597 // Cast the inputs to v16i8 to match PALIGNR.
7598 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Lo);
7599 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Hi);
7601 return DAG.getNode(ISD::BITCAST, DL, VT,
7602 DAG.getNode(X86ISD::PALIGNR, DL, MVT::v16i8, Hi, Lo,
7603 DAG.getConstant(Rotation * Scale, MVT::i8)));
7606 // Default SSE2 implementation
7607 int LoByteShift = 16 - Rotation * Scale;
7608 int HiByteShift = Rotation * Scale;
7610 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7611 Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Lo);
7612 Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);
7614 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7615 DAG.getConstant(8 * LoByteShift, MVT::i8));
7616 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7617 DAG.getConstant(8 * HiByteShift, MVT::i8));
7618 return DAG.getNode(ISD::BITCAST, DL, VT,
7619 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7622 /// \brief Compute whether each element of a shuffle is zeroable.
7624 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
7625 /// Either it is an undef element in the shuffle mask, the element of the input
7626 /// referenced is undef, or the element of the input referenced is known to be
7627 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
7628 /// as many lanes with this technique as possible to simplify the remaining
7630 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
7631 SDValue V1, SDValue V2) {
7632 SmallBitVector Zeroable(Mask.size(), false);
7634 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7635 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7637 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7639 // Handle the easy cases.
7640 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
7645 // If this is an index into a build_vector node, dig out the input value and
7647 SDValue V = M < Size ? V1 : V2;
7648 if (V.getOpcode() != ISD::BUILD_VECTOR)
7651 SDValue Input = V.getOperand(M % Size);
7652 // The UNDEF opcode check really should be dead code here, but not quite
7653 // worth asserting on (it isn't invalid, just unexpected).
7654 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
7661 /// \brief Try to lower a vector shuffle as a byte shift (shifts in zeros).
7663 /// Attempts to match a shuffle mask against the PSRLDQ and PSLLDQ SSE2
7664 /// byte-shift instructions. The mask must consist of a shifted sequential
7665 /// shuffle from one of the input vectors and zeroable elements for the
7666 /// remaining 'shifted in' elements.
7668 /// Note that this only handles 128-bit vector widths currently.
7669 static SDValue lowerVectorShuffleAsByteShift(SDLoc DL, MVT VT, SDValue V1,
7670 SDValue V2, ArrayRef<int> Mask,
7671 SelectionDAG &DAG) {
7672 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7674 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7676 int Size = Mask.size();
7677 int Scale = 16 / Size;
7679 auto isSequential = [](int Base, int StartIndex, int EndIndex, int MaskOffset,
7680 ArrayRef<int> Mask) {
7681 for (int i = StartIndex; i < EndIndex; i++) {
7684 if (i + Base != Mask[i] - MaskOffset)
7690 for (int Shift = 1; Shift < Size; Shift++) {
7691 int ByteShift = Shift * Scale;
7693 // PSRLDQ : (little-endian) right byte shift
7694 // [ 5, 6, 7, zz, zz, zz, zz, zz]
7695 // [ -1, 5, 6, 7, zz, zz, zz, zz]
7696 // [ 1, 2, -1, -1, -1, -1, zz, zz]
7697 bool ZeroableRight = true;
7698 for (int i = Size - Shift; i < Size; i++) {
7699 ZeroableRight &= Zeroable[i];
7702 if (ZeroableRight) {
7703 bool ValidShiftRight1 = isSequential(Shift, 0, Size - Shift, 0, Mask);
7704 bool ValidShiftRight2 = isSequential(Shift, 0, Size - Shift, Size, Mask);
7706 if (ValidShiftRight1 || ValidShiftRight2) {
7707 // Cast the inputs to v2i64 to match PSRLDQ.
7708 SDValue &TargetV = ValidShiftRight1 ? V1 : V2;
7709 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7710 SDValue Shifted = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, V,
7711 DAG.getConstant(ByteShift * 8, MVT::i8));
7712 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7716 // PSLLDQ : (little-endian) left byte shift
7717 // [ zz, 0, 1, 2, 3, 4, 5, 6]
7718 // [ zz, zz, -1, -1, 2, 3, 4, -1]
7719 // [ zz, zz, zz, zz, zz, zz, -1, 1]
7720 bool ZeroableLeft = true;
7721 for (int i = 0; i < Shift; i++) {
7722 ZeroableLeft &= Zeroable[i];
7726 bool ValidShiftLeft1 = isSequential(-Shift, Shift, Size, 0, Mask);
7727 bool ValidShiftLeft2 = isSequential(-Shift, Shift, Size, Size, Mask);
7729 if (ValidShiftLeft1 || ValidShiftLeft2) {
7730 // Cast the inputs to v2i64 to match PSLLDQ.
7731 SDValue &TargetV = ValidShiftLeft1 ? V1 : V2;
7732 SDValue V = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, TargetV);
7733 SDValue Shifted = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, V,
7734 DAG.getConstant(ByteShift * 8, MVT::i8));
7735 return DAG.getNode(ISD::BITCAST, DL, VT, Shifted);
7743 /// \brief Lower a vector shuffle as a zero or any extension.
7745 /// Given a specific number of elements, element bit width, and extension
7746 /// stride, produce either a zero or any extension based on the available
7747 /// features of the subtarget.
7748 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7749 SDLoc DL, MVT VT, int NumElements, int Scale, bool AnyExt, SDValue InputV,
7750 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7751 assert(Scale > 1 && "Need a scale to extend.");
7752 int EltBits = VT.getSizeInBits() / NumElements;
7753 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7754 "Only 8, 16, and 32 bit elements can be extended.");
7755 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7757 // Found a valid zext mask! Try various lowering strategies based on the
7758 // input type and available ISA extensions.
7759 if (Subtarget->hasSSE41()) {
7760 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7761 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7762 NumElements / Scale);
7763 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7764 return DAG.getNode(ISD::BITCAST, DL, VT,
7765 DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7768 // For any extends we can cheat for larger element sizes and use shuffle
7769 // instructions that can fold with a load and/or copy.
7770 if (AnyExt && EltBits == 32) {
7771 int PSHUFDMask[4] = {0, -1, 1, -1};
7773 ISD::BITCAST, DL, VT,
7774 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7775 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7776 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
7778 if (AnyExt && EltBits == 16 && Scale > 2) {
7779 int PSHUFDMask[4] = {0, -1, 0, -1};
7780 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7781 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),
7782 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));
7783 int PSHUFHWMask[4] = {1, -1, -1, -1};
7785 ISD::BITCAST, DL, VT,
7786 DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7787 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),
7788 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));
7791 // If this would require more than 2 unpack instructions to expand, use
7792 // pshufb when available. We can only use more than 2 unpack instructions
7793 // when zero extending i8 elements which also makes it easier to use pshufb.
7794 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7795 assert(NumElements == 16 && "Unexpected byte vector width!");
7796 SDValue PSHUFBMask[16];
7797 for (int i = 0; i < 16; ++i)
7799 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);
7800 InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);
7801 return DAG.getNode(ISD::BITCAST, DL, VT,
7802 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7803 DAG.getNode(ISD::BUILD_VECTOR, DL,
7804 MVT::v16i8, PSHUFBMask)));
7807 // Otherwise emit a sequence of unpacks.
7809 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7810 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7811 : getZeroVector(InputVT, Subtarget, DAG, DL);
7812 InputV = DAG.getNode(ISD::BITCAST, DL, InputVT, InputV);
7813 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7817 } while (Scale > 1);
7818 return DAG.getNode(ISD::BITCAST, DL, VT, InputV);
7821 /// \brief Try to lower a vector shuffle as a zero extension on any micrarch.
7823 /// This routine will try to do everything in its power to cleverly lower
7824 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7825 /// check for the profitability of this lowering, it tries to aggressively
7826 /// match this pattern. It will use all of the micro-architectural details it
7827 /// can to emit an efficient lowering. It handles both blends with all-zero
7828 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7829 /// masking out later).
7831 /// The reason we have dedicated lowering for zext-style shuffles is that they
7832 /// are both incredibly common and often quite performance sensitive.
7833 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7834 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7835 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7836 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7838 int Bits = VT.getSizeInBits();
7839 int NumElements = Mask.size();
7841 // Define a helper function to check a particular ext-scale and lower to it if
7843 auto Lower = [&](int Scale) -> SDValue {
7846 for (int i = 0; i < NumElements; ++i) {
7848 continue; // Valid anywhere but doesn't tell us anything.
7849 if (i % Scale != 0) {
7850 // Each of the extend elements needs to be zeroable.
7854 // We no lorger are in the anyext case.
7859 // Each of the base elements needs to be consecutive indices into the
7860 // same input vector.
7861 SDValue V = Mask[i] < NumElements ? V1 : V2;
7864 else if (InputV != V)
7865 return SDValue(); // Flip-flopping inputs.
7867 if (Mask[i] % NumElements != i / Scale)
7868 return SDValue(); // Non-consecutive strided elemenst.
7871 // If we fail to find an input, we have a zero-shuffle which should always
7872 // have already been handled.
7873 // FIXME: Maybe handle this here in case during blending we end up with one?
7877 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7878 DL, VT, NumElements, Scale, AnyExt, InputV, Subtarget, DAG);
7881 // The widest scale possible for extending is to a 64-bit integer.
7882 assert(Bits % 64 == 0 &&
7883 "The number of bits in a vector must be divisible by 64 on x86!");
7884 int NumExtElements = Bits / 64;
7886 // Each iteration, try extending the elements half as much, but into twice as
7888 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7889 assert(NumElements % NumExtElements == 0 &&
7890 "The input vector size must be divisble by the extended size.");
7891 if (SDValue V = Lower(NumElements / NumExtElements))
7895 // No viable ext lowering found.
7899 /// \brief Try to get a scalar value for a specific element of a vector.
7901 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7902 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7903 SelectionDAG &DAG) {
7904 MVT VT = V.getSimpleValueType();
7905 MVT EltVT = VT.getVectorElementType();
7906 while (V.getOpcode() == ISD::BITCAST)
7907 V = V.getOperand(0);
7908 // If the bitcasts shift the element size, we can't extract an equivalent
7910 MVT NewVT = V.getSimpleValueType();
7911 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7914 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7915 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR))
7916 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, V.getOperand(Idx));
7921 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7923 /// This is particularly important because the set of instructions varies
7924 /// significantly based on whether the operand is a load or not.
7925 static bool isShuffleFoldableLoad(SDValue V) {
7926 while (V.getOpcode() == ISD::BITCAST)
7927 V = V.getOperand(0);
7929 return ISD::isNON_EXTLoad(V.getNode());
7932 /// \brief Try to lower insertion of a single element into a zero vector.
7934 /// This is a common pattern that we have especially efficient patterns to lower
7935 /// across all subtarget feature sets.
7936 static SDValue lowerVectorShuffleAsElementInsertion(
7937 MVT VT, SDLoc DL, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7938 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7939 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7941 MVT EltVT = VT.getVectorElementType();
7943 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7944 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7946 bool IsV1Zeroable = true;
7947 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7948 if (i != V2Index && !Zeroable[i]) {
7949 IsV1Zeroable = false;
7953 // Check for a single input from a SCALAR_TO_VECTOR node.
7954 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7955 // all the smarts here sunk into that routine. However, the current
7956 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7957 // vector shuffle lowering is dead.
7958 if (SDValue V2S = getScalarValueForVectorElement(
7959 V2, Mask[V2Index] - Mask.size(), DAG)) {
7960 // We need to zext the scalar if it is smaller than an i32.
7961 V2S = DAG.getNode(ISD::BITCAST, DL, EltVT, V2S);
7962 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7963 // Using zext to expand a narrow element won't work for non-zero
7968 // Zero-extend directly to i32.
7970 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7972 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7973 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7974 EltVT == MVT::i16) {
7975 // Either not inserting from the low element of the input or the input
7976 // element size is too small to use VZEXT_MOVL to clear the high bits.
7980 if (!IsV1Zeroable) {
7981 // If V1 can't be treated as a zero vector we have fewer options to lower
7982 // this. We can't support integer vectors or non-zero targets cheaply, and
7983 // the V1 elements can't be permuted in any way.
7984 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7985 if (!VT.isFloatingPoint() || V2Index != 0)
7987 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7988 V1Mask[V2Index] = -1;
7989 if (!isNoopShuffleMask(V1Mask))
7991 // This is essentially a special case blend operation, but if we have
7992 // general purpose blend operations, they are always faster. Bail and let
7993 // the rest of the lowering handle these as blends.
7994 if (Subtarget->hasSSE41())
7997 // Otherwise, use MOVSD or MOVSS.
7998 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7999 "Only two types of floating point element types to handle!");
8000 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8004 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8006 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8009 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8010 // the desired position. Otherwise it is more efficient to do a vector
8011 // shift left. We know that we can do a vector shift left because all
8012 // the inputs are zero.
8013 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8014 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8015 V2Shuffle[V2Index] = 0;
8016 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8018 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, V2);
8020 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8022 V2Index * EltVT.getSizeInBits(),
8023 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
8024 V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);
8030 /// \brief Try to lower broadcast of a single element.
8032 /// For convenience, this code also bundles all of the subtarget feature set
8033 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8034 /// a convenient way to factor it out.
8035 static SDValue lowerVectorShuffleAsBroadcast(MVT VT, SDLoc DL, SDValue V,
8037 const X86Subtarget *Subtarget,
8038 SelectionDAG &DAG) {
8039 if (!Subtarget->hasAVX())
8041 if (VT.isInteger() && !Subtarget->hasAVX2())
8044 // Check that the mask is a broadcast.
8045 int BroadcastIdx = -1;
8047 if (M >= 0 && BroadcastIdx == -1)
8049 else if (M >= 0 && M != BroadcastIdx)
8052 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8053 "a sorted mask where the broadcast "
8056 // Go up the chain of (vector) values to try and find a scalar load that
8057 // we can combine with the broadcast.
8059 switch (V.getOpcode()) {
8060 case ISD::CONCAT_VECTORS: {
8061 int OperandSize = Mask.size() / V.getNumOperands();
8062 V = V.getOperand(BroadcastIdx / OperandSize);
8063 BroadcastIdx %= OperandSize;
8067 case ISD::INSERT_SUBVECTOR: {
8068 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8069 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8073 int BeginIdx = (int)ConstantIdx->getZExtValue();
8075 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
8076 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8077 BroadcastIdx -= BeginIdx;
8088 // Check if this is a broadcast of a scalar. We special case lowering
8089 // for scalars so that we can more effectively fold with loads.
8090 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8091 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8092 V = V.getOperand(BroadcastIdx);
8094 // If the scalar isn't a load we can't broadcast from it in AVX1, only with
8096 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8098 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8099 // We can't broadcast from a vector register w/o AVX2, and we can only
8100 // broadcast from the zero-element of a vector register.
8104 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8107 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8109 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8110 /// support for floating point shuffles but not integer shuffles. These
8111 /// instructions will incur a domain crossing penalty on some chips though so
8112 /// it is better to avoid lowering through this for integer vectors where
8114 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8115 const X86Subtarget *Subtarget,
8116 SelectionDAG &DAG) {
8118 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8119 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8120 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8121 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8122 ArrayRef<int> Mask = SVOp->getMask();
8123 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8125 if (isSingleInputShuffleMask(Mask)) {
8126 // Straight shuffle of a single input vector. Simulate this by using the
8127 // single input as both of the "inputs" to this instruction..
8128 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8130 if (Subtarget->hasAVX()) {
8131 // If we have AVX, we can use VPERMILPS which will allow folding a load
8132 // into the shuffle.
8133 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8134 DAG.getConstant(SHUFPDMask, MVT::i8));
8137 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,
8138 DAG.getConstant(SHUFPDMask, MVT::i8));
8140 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8141 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8143 // Use dedicated unpack instructions for masks that match their pattern.
8144 if (isShuffleEquivalent(Mask, 0, 2))
8145 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8146 if (isShuffleEquivalent(Mask, 1, 3))
8147 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8149 // If we have a single input, insert that into V1 if we can do so cheaply.
8150 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8151 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8152 MVT::v2f64, DL, V1, V2, Mask, Subtarget, DAG))
8154 // Try inverting the insertion since for v2 masks it is easy to do and we
8155 // can't reliably sort the mask one way or the other.
8156 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8157 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8158 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8159 MVT::v2f64, DL, V2, V1, InverseMask, Subtarget, DAG))
8163 // Try to use one of the special instruction patterns to handle two common
8164 // blend patterns if a zero-blend above didn't work.
8165 if (isShuffleEquivalent(Mask, 0, 3) || isShuffleEquivalent(Mask, 1, 3))
8166 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8167 // We can either use a special instruction to load over the low double or
8168 // to move just the low double.
8170 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8172 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8174 if (Subtarget->hasSSE41())
8175 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8179 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8180 return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,
8181 DAG.getConstant(SHUFPDMask, MVT::i8));
8184 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8186 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8187 /// the integer unit to minimize domain crossing penalties. However, for blends
8188 /// it falls back to the floating point shuffle operation with appropriate bit
8190 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8191 const X86Subtarget *Subtarget,
8192 SelectionDAG &DAG) {
8194 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8195 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8196 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8197 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8198 ArrayRef<int> Mask = SVOp->getMask();
8199 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8201 if (isSingleInputShuffleMask(Mask)) {
8202 // Check for being able to broadcast a single element.
8203 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v2i64, DL, V1,
8204 Mask, Subtarget, DAG))
8207 // Straight shuffle of a single input vector. For everything from SSE2
8208 // onward this has a single fast instruction with no scary immediates.
8209 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8210 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V1);
8211 int WidenedMask[4] = {
8212 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8213 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8215 ISD::BITCAST, DL, MVT::v2i64,
8216 DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,
8217 getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));
8220 // Try to use byte shift instructions.
8221 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8222 DL, MVT::v2i64, V1, V2, Mask, DAG))
8225 // If we have a single input from V2 insert that into V1 if we can do so
8227 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8228 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8229 MVT::v2i64, DL, V1, V2, Mask, Subtarget, DAG))
8231 // Try inverting the insertion since for v2 masks it is easy to do and we
8232 // can't reliably sort the mask one way or the other.
8233 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8234 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8235 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8236 MVT::v2i64, DL, V2, V1, InverseMask, Subtarget, DAG))
8240 // Use dedicated unpack instructions for masks that match their pattern.
8241 if (isShuffleEquivalent(Mask, 0, 2))
8242 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8243 if (isShuffleEquivalent(Mask, 1, 3))
8244 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8246 if (Subtarget->hasSSE41())
8247 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8251 // Try to use byte rotation instructions.
8252 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8253 if (Subtarget->hasSSSE3())
8254 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8255 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8258 // We implement this with SHUFPD which is pretty lame because it will likely
8259 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8260 // However, all the alternatives are still more cycles and newer chips don't
8261 // have this problem. It would be really nice if x86 had better shuffles here.
8262 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V1);
8263 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, V2);
8264 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
8265 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8268 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8270 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8271 /// It makes no assumptions about whether this is the *best* lowering, it simply
8273 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8274 ArrayRef<int> Mask, SDValue V1,
8275 SDValue V2, SelectionDAG &DAG) {
8276 SDValue LowV = V1, HighV = V2;
8277 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8280 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8282 if (NumV2Elements == 1) {
8284 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8287 // Compute the index adjacent to V2Index and in the same half by toggling
8289 int V2AdjIndex = V2Index ^ 1;
8291 if (Mask[V2AdjIndex] == -1) {
8292 // Handles all the cases where we have a single V2 element and an undef.
8293 // This will only ever happen in the high lanes because we commute the
8294 // vector otherwise.
8296 std::swap(LowV, HighV);
8297 NewMask[V2Index] -= 4;
8299 // Handle the case where the V2 element ends up adjacent to a V1 element.
8300 // To make this work, blend them together as the first step.
8301 int V1Index = V2AdjIndex;
8302 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8303 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8304 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8306 // Now proceed to reconstruct the final blend as we have the necessary
8307 // high or low half formed.
8314 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8315 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8317 } else if (NumV2Elements == 2) {
8318 if (Mask[0] < 4 && Mask[1] < 4) {
8319 // Handle the easy case where we have V1 in the low lanes and V2 in the
8323 } else if (Mask[2] < 4 && Mask[3] < 4) {
8324 // We also handle the reversed case because this utility may get called
8325 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8326 // arrange things in the right direction.
8332 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8333 // trying to place elements directly, just blend them and set up the final
8334 // shuffle to place them.
8336 // The first two blend mask elements are for V1, the second two are for
8338 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8339 Mask[2] < 4 ? Mask[2] : Mask[3],
8340 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8341 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8342 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8343 getV4X86ShuffleImm8ForMask(BlendMask, DAG));
8345 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8348 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8349 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8350 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8351 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8354 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8355 getV4X86ShuffleImm8ForMask(NewMask, DAG));
8358 /// \brief Lower 4-lane 32-bit floating point shuffles.
8360 /// Uses instructions exclusively from the floating point unit to minimize
8361 /// domain crossing penalties, as these are sufficient to implement all v4f32
8363 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8364 const X86Subtarget *Subtarget,
8365 SelectionDAG &DAG) {
8367 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8368 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8369 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8370 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8371 ArrayRef<int> Mask = SVOp->getMask();
8372 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8375 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8377 if (NumV2Elements == 0) {
8378 // Check for being able to broadcast a single element.
8379 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f32, DL, V1,
8380 Mask, Subtarget, DAG))
8383 if (Subtarget->hasAVX()) {
8384 // If we have AVX, we can use VPERMILPS which will allow folding a load
8385 // into the shuffle.
8386 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8387 getV4X86ShuffleImm8ForMask(Mask, DAG));
8390 // Otherwise, use a straight shuffle of a single input vector. We pass the
8391 // input vector to both operands to simulate this with a SHUFPS.
8392 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8393 getV4X86ShuffleImm8ForMask(Mask, DAG));
8396 // Use dedicated unpack instructions for masks that match their pattern.
8397 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8398 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8399 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8400 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8402 // There are special ways we can lower some single-element blends. However, we
8403 // have custom ways we can lower more complex single-element blends below that
8404 // we defer to if both this and BLENDPS fail to match, so restrict this to
8405 // when the V2 input is targeting element 0 of the mask -- that is the fast
8407 if (NumV2Elements == 1 && Mask[0] >= 4)
8408 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4f32, DL, V1, V2,
8409 Mask, Subtarget, DAG))
8412 if (Subtarget->hasSSE41())
8413 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8417 // Check for whether we can use INSERTPS to perform the blend. We only use
8418 // INSERTPS when the V1 elements are already in the correct locations
8419 // because otherwise we can just always use two SHUFPS instructions which
8420 // are much smaller to encode than a SHUFPS and an INSERTPS.
8421 if (NumV2Elements == 1 && Subtarget->hasSSE41()) {
8423 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8426 // When using INSERTPS we can zero any lane of the destination. Collect
8427 // the zero inputs into a mask and drop them from the lanes of V1 which
8428 // actually need to be present as inputs to the INSERTPS.
8429 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8431 // Synthesize a shuffle mask for the non-zero and non-v2 inputs.
8432 bool InsertNeedsShuffle = false;
8434 for (int i = 0; i < 4; ++i)
8438 } else if (Mask[i] != i) {
8439 InsertNeedsShuffle = true;
8444 // We don't want to use INSERTPS or other insertion techniques if it will
8445 // require shuffling anyways.
8446 if (!InsertNeedsShuffle) {
8447 // If all of V1 is zeroable, replace it with undef.
8448 if ((ZMask | 1 << V2Index) == 0xF)
8449 V1 = DAG.getUNDEF(MVT::v4f32);
8451 unsigned InsertPSMask = (Mask[V2Index] - 4) << 6 | V2Index << 4 | ZMask;
8452 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8454 // Insert the V2 element into the desired position.
8455 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8456 DAG.getConstant(InsertPSMask, MVT::i8));
8460 // Otherwise fall back to a SHUFPS lowering strategy.
8461 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8464 /// \brief Lower 4-lane i32 vector shuffles.
8466 /// We try to handle these with integer-domain shuffles where we can, but for
8467 /// blends we use the floating point domain blend instructions.
8468 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8469 const X86Subtarget *Subtarget,
8470 SelectionDAG &DAG) {
8472 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8473 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8474 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8476 ArrayRef<int> Mask = SVOp->getMask();
8477 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8479 // Whenever we can lower this as a zext, that instruction is strictly faster
8480 // than any alternative. It also allows us to fold memory operands into the
8481 // shuffle in many cases.
8482 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8483 Mask, Subtarget, DAG))
8487 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8489 if (NumV2Elements == 0) {
8490 // Check for being able to broadcast a single element.
8491 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i32, DL, V1,
8492 Mask, Subtarget, DAG))
8495 // Straight shuffle of a single input vector. For everything from SSE2
8496 // onward this has a single fast instruction with no scary immediates.
8497 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8498 // but we aren't actually going to use the UNPCK instruction because doing
8499 // so prevents folding a load into this instruction or making a copy.
8500 const int UnpackLoMask[] = {0, 0, 1, 1};
8501 const int UnpackHiMask[] = {2, 2, 3, 3};
8502 if (isShuffleEquivalent(Mask, 0, 0, 1, 1))
8503 Mask = UnpackLoMask;
8504 else if (isShuffleEquivalent(Mask, 2, 2, 3, 3))
8505 Mask = UnpackHiMask;
8507 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8508 getV4X86ShuffleImm8ForMask(Mask, DAG));
8511 // Try to use byte shift instructions.
8512 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8513 DL, MVT::v4i32, V1, V2, Mask, DAG))
8516 // There are special ways we can lower some single-element blends.
8517 if (NumV2Elements == 1)
8518 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v4i32, DL, V1, V2,
8519 Mask, Subtarget, DAG))
8522 // Use dedicated unpack instructions for masks that match their pattern.
8523 if (isShuffleEquivalent(Mask, 0, 4, 1, 5))
8524 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8525 if (isShuffleEquivalent(Mask, 2, 6, 3, 7))
8526 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8528 if (Subtarget->hasSSE41())
8529 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8533 // Try to use byte rotation instructions.
8534 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8535 if (Subtarget->hasSSSE3())
8536 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8537 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8540 // We implement this with SHUFPS because it can blend from two vectors.
8541 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8542 // up the inputs, bypassing domain shift penalties that we would encur if we
8543 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8545 return DAG.getNode(ISD::BITCAST, DL, MVT::v4i32,
8546 DAG.getVectorShuffle(
8548 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V1),
8549 DAG.getNode(ISD::BITCAST, DL, MVT::v4f32, V2), Mask));
8552 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8553 /// shuffle lowering, and the most complex part.
8555 /// The lowering strategy is to try to form pairs of input lanes which are
8556 /// targeted at the same half of the final vector, and then use a dword shuffle
8557 /// to place them onto the right half, and finally unpack the paired lanes into
8558 /// their final position.
8560 /// The exact breakdown of how to form these dword pairs and align them on the
8561 /// correct sides is really tricky. See the comments within the function for
8562 /// more of the details.
8563 static SDValue lowerV8I16SingleInputVectorShuffle(
8564 SDLoc DL, SDValue V, MutableArrayRef<int> Mask,
8565 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8566 assert(V.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
8567 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8568 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8570 SmallVector<int, 4> LoInputs;
8571 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8572 [](int M) { return M >= 0; });
8573 std::sort(LoInputs.begin(), LoInputs.end());
8574 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8575 SmallVector<int, 4> HiInputs;
8576 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8577 [](int M) { return M >= 0; });
8578 std::sort(HiInputs.begin(), HiInputs.end());
8579 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8581 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8582 int NumHToL = LoInputs.size() - NumLToL;
8584 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8585 int NumHToH = HiInputs.size() - NumLToH;
8586 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8587 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8588 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8589 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8591 // Check for being able to broadcast a single element.
8592 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i16, DL, V,
8593 Mask, Subtarget, DAG))
8596 // Try to use byte shift instructions.
8597 if (SDValue Shift = lowerVectorShuffleAsByteShift(
8598 DL, MVT::v8i16, V, V, Mask, DAG))
8601 // Use dedicated unpack instructions for masks that match their pattern.
8602 if (isShuffleEquivalent(Mask, 0, 0, 1, 1, 2, 2, 3, 3))
8603 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V, V);
8604 if (isShuffleEquivalent(Mask, 4, 4, 5, 5, 6, 6, 7, 7))
8605 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V, V);
8607 // Try to use byte rotation instructions.
8608 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8609 DL, MVT::v8i16, V, V, Mask, Subtarget, DAG))
8612 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8613 // such inputs we can swap two of the dwords across the half mark and end up
8614 // with <=2 inputs to each half in each half. Once there, we can fall through
8615 // to the generic code below. For example:
8617 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8618 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8620 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8621 // and an existing 2-into-2 on the other half. In this case we may have to
8622 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8623 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8624 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8625 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8626 // half than the one we target for fixing) will be fixed when we re-enter this
8627 // path. We will also combine away any sequence of PSHUFD instructions that
8628 // result into a single instruction. Here is an example of the tricky case:
8630 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8631 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8633 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8635 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8636 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8638 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8639 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8641 // The result is fine to be handled by the generic logic.
8642 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8643 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8644 int AOffset, int BOffset) {
8645 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8646 "Must call this with A having 3 or 1 inputs from the A half.");
8647 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8648 "Must call this with B having 1 or 3 inputs from the B half.");
8649 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8650 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8652 // Compute the index of dword with only one word among the three inputs in
8653 // a half by taking the sum of the half with three inputs and subtracting
8654 // the sum of the actual three inputs. The difference is the remaining
8657 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8658 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8659 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8660 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8661 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8662 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8663 int TripleNonInputIdx =
8664 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8665 TripleDWord = TripleNonInputIdx / 2;
8667 // We use xor with one to compute the adjacent DWord to whichever one the
8669 OneInputDWord = (OneInput / 2) ^ 1;
8671 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8672 // and BToA inputs. If there is also such a problem with the BToB and AToB
8673 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8674 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8675 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8676 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8677 // Compute how many inputs will be flipped by swapping these DWords. We
8679 // to balance this to ensure we don't form a 3-1 shuffle in the other
8681 int NumFlippedAToBInputs =
8682 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8683 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8684 int NumFlippedBToBInputs =
8685 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8686 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8687 if ((NumFlippedAToBInputs == 1 &&
8688 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8689 (NumFlippedBToBInputs == 1 &&
8690 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8691 // We choose whether to fix the A half or B half based on whether that
8692 // half has zero flipped inputs. At zero, we may not be able to fix it
8693 // with that half. We also bias towards fixing the B half because that
8694 // will more commonly be the high half, and we have to bias one way.
8695 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8696 ArrayRef<int> Inputs) {
8697 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8698 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8699 PinnedIdx ^ 1) != Inputs.end();
8700 // Determine whether the free index is in the flipped dword or the
8701 // unflipped dword based on where the pinned index is. We use this bit
8702 // in an xor to conditionally select the adjacent dword.
8703 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8704 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8705 FixFreeIdx) != Inputs.end();
8706 if (IsFixIdxInput == IsFixFreeIdxInput)
8708 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8709 FixFreeIdx) != Inputs.end();
8710 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8711 "We need to be changing the number of flipped inputs!");
8712 int PSHUFHalfMask[] = {0, 1, 2, 3};
8713 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8714 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8716 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));
8719 if (M != -1 && M == FixIdx)
8721 else if (M != -1 && M == FixFreeIdx)
8724 if (NumFlippedBToBInputs != 0) {
8726 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8727 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8729 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8731 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8732 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8737 int PSHUFDMask[] = {0, 1, 2, 3};
8738 PSHUFDMask[ADWord] = BDWord;
8739 PSHUFDMask[BDWord] = ADWord;
8740 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8741 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8742 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8743 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8745 // Adjust the mask to match the new locations of A and B.
8747 if (M != -1 && M/2 == ADWord)
8748 M = 2 * BDWord + M % 2;
8749 else if (M != -1 && M/2 == BDWord)
8750 M = 2 * ADWord + M % 2;
8752 // Recurse back into this routine to re-compute state now that this isn't
8753 // a 3 and 1 problem.
8754 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
8757 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8758 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8759 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8760 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8762 // At this point there are at most two inputs to the low and high halves from
8763 // each half. That means the inputs can always be grouped into dwords and
8764 // those dwords can then be moved to the correct half with a dword shuffle.
8765 // We use at most one low and one high word shuffle to collect these paired
8766 // inputs into dwords, and finally a dword shuffle to place them.
8767 int PSHUFLMask[4] = {-1, -1, -1, -1};
8768 int PSHUFHMask[4] = {-1, -1, -1, -1};
8769 int PSHUFDMask[4] = {-1, -1, -1, -1};
8771 // First fix the masks for all the inputs that are staying in their
8772 // original halves. This will then dictate the targets of the cross-half
8774 auto fixInPlaceInputs =
8775 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8776 MutableArrayRef<int> SourceHalfMask,
8777 MutableArrayRef<int> HalfMask, int HalfOffset) {
8778 if (InPlaceInputs.empty())
8780 if (InPlaceInputs.size() == 1) {
8781 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8782 InPlaceInputs[0] - HalfOffset;
8783 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8786 if (IncomingInputs.empty()) {
8787 // Just fix all of the in place inputs.
8788 for (int Input : InPlaceInputs) {
8789 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8790 PSHUFDMask[Input / 2] = Input / 2;
8795 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8796 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8797 InPlaceInputs[0] - HalfOffset;
8798 // Put the second input next to the first so that they are packed into
8799 // a dword. We find the adjacent index by toggling the low bit.
8800 int AdjIndex = InPlaceInputs[0] ^ 1;
8801 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8802 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8803 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8805 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8806 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8808 // Now gather the cross-half inputs and place them into a free dword of
8809 // their target half.
8810 // FIXME: This operation could almost certainly be simplified dramatically to
8811 // look more like the 3-1 fixing operation.
8812 auto moveInputsToRightHalf = [&PSHUFDMask](
8813 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8814 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8815 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8817 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8818 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8820 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8822 int LowWord = Word & ~1;
8823 int HighWord = Word | 1;
8824 return isWordClobbered(SourceHalfMask, LowWord) ||
8825 isWordClobbered(SourceHalfMask, HighWord);
8828 if (IncomingInputs.empty())
8831 if (ExistingInputs.empty()) {
8832 // Map any dwords with inputs from them into the right half.
8833 for (int Input : IncomingInputs) {
8834 // If the source half mask maps over the inputs, turn those into
8835 // swaps and use the swapped lane.
8836 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8837 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8838 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8839 Input - SourceOffset;
8840 // We have to swap the uses in our half mask in one sweep.
8841 for (int &M : HalfMask)
8842 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8844 else if (M == Input)
8845 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8847 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8848 Input - SourceOffset &&
8849 "Previous placement doesn't match!");
8851 // Note that this correctly re-maps both when we do a swap and when
8852 // we observe the other side of the swap above. We rely on that to
8853 // avoid swapping the members of the input list directly.
8854 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8857 // Map the input's dword into the correct half.
8858 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8859 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8861 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8863 "Previous placement doesn't match!");
8866 // And just directly shift any other-half mask elements to be same-half
8867 // as we will have mirrored the dword containing the element into the
8868 // same position within that half.
8869 for (int &M : HalfMask)
8870 if (M >= SourceOffset && M < SourceOffset + 4) {
8871 M = M - SourceOffset + DestOffset;
8872 assert(M >= 0 && "This should never wrap below zero!");
8877 // Ensure we have the input in a viable dword of its current half. This
8878 // is particularly tricky because the original position may be clobbered
8879 // by inputs being moved and *staying* in that half.
8880 if (IncomingInputs.size() == 1) {
8881 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8882 int InputFixed = std::find(std::begin(SourceHalfMask),
8883 std::end(SourceHalfMask), -1) -
8884 std::begin(SourceHalfMask) + SourceOffset;
8885 SourceHalfMask[InputFixed - SourceOffset] =
8886 IncomingInputs[0] - SourceOffset;
8887 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8889 IncomingInputs[0] = InputFixed;
8891 } else if (IncomingInputs.size() == 2) {
8892 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8893 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8894 // We have two non-adjacent or clobbered inputs we need to extract from
8895 // the source half. To do this, we need to map them into some adjacent
8896 // dword slot in the source mask.
8897 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8898 IncomingInputs[1] - SourceOffset};
8900 // If there is a free slot in the source half mask adjacent to one of
8901 // the inputs, place the other input in it. We use (Index XOR 1) to
8902 // compute an adjacent index.
8903 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8904 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8905 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8906 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8907 InputsFixed[1] = InputsFixed[0] ^ 1;
8908 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8909 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8910 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8911 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8912 InputsFixed[0] = InputsFixed[1] ^ 1;
8913 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8914 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8915 // The two inputs are in the same DWord but it is clobbered and the
8916 // adjacent DWord isn't used at all. Move both inputs to the free
8918 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8919 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8920 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8921 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8923 // The only way we hit this point is if there is no clobbering
8924 // (because there are no off-half inputs to this half) and there is no
8925 // free slot adjacent to one of the inputs. In this case, we have to
8926 // swap an input with a non-input.
8927 for (int i = 0; i < 4; ++i)
8928 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8929 "We can't handle any clobbers here!");
8930 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8931 "Cannot have adjacent inputs here!");
8933 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8934 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8936 // We also have to update the final source mask in this case because
8937 // it may need to undo the above swap.
8938 for (int &M : FinalSourceHalfMask)
8939 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8940 M = InputsFixed[1] + SourceOffset;
8941 else if (M == InputsFixed[1] + SourceOffset)
8942 M = (InputsFixed[0] ^ 1) + SourceOffset;
8944 InputsFixed[1] = InputsFixed[0] ^ 1;
8947 // Point everything at the fixed inputs.
8948 for (int &M : HalfMask)
8949 if (M == IncomingInputs[0])
8950 M = InputsFixed[0] + SourceOffset;
8951 else if (M == IncomingInputs[1])
8952 M = InputsFixed[1] + SourceOffset;
8954 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8955 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8958 llvm_unreachable("Unhandled input size!");
8961 // Now hoist the DWord down to the right half.
8962 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8963 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8964 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8965 for (int &M : HalfMask)
8966 for (int Input : IncomingInputs)
8968 M = FreeDWord * 2 + Input % 2;
8970 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8971 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8972 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8973 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8975 // Now enact all the shuffles we've computed to move the inputs into their
8977 if (!isNoopShuffleMask(PSHUFLMask))
8978 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
8979 getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));
8980 if (!isNoopShuffleMask(PSHUFHMask))
8981 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
8982 getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));
8983 if (!isNoopShuffleMask(PSHUFDMask))
8984 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
8985 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
8986 DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V),
8987 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
8989 // At this point, each half should contain all its inputs, and we can then
8990 // just shuffle them into their final position.
8991 assert(std::count_if(LoMask.begin(), LoMask.end(),
8992 [](int M) { return M >= 4; }) == 0 &&
8993 "Failed to lift all the high half inputs to the low mask!");
8994 assert(std::count_if(HiMask.begin(), HiMask.end(),
8995 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8996 "Failed to lift all the low half inputs to the high mask!");
8998 // Do a half shuffle for the low mask.
8999 if (!isNoopShuffleMask(LoMask))
9000 V = DAG.getNode(X86ISD::PSHUFLW, DL, MVT::v8i16, V,
9001 getV4X86ShuffleImm8ForMask(LoMask, DAG));
9003 // Do a half shuffle with the high mask after shifting its values down.
9004 for (int &M : HiMask)
9007 if (!isNoopShuffleMask(HiMask))
9008 V = DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16, V,
9009 getV4X86ShuffleImm8ForMask(HiMask, DAG));
9014 /// \brief Detect whether the mask pattern should be lowered through
9017 /// This essentially tests whether viewing the mask as an interleaving of two
9018 /// sub-sequences reduces the cross-input traffic of a blend operation. If so,
9019 /// lowering it through interleaving is a significantly better strategy.
9020 static bool shouldLowerAsInterleaving(ArrayRef<int> Mask) {
9021 int NumEvenInputs[2] = {0, 0};
9022 int NumOddInputs[2] = {0, 0};
9023 int NumLoInputs[2] = {0, 0};
9024 int NumHiInputs[2] = {0, 0};
9025 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
9029 int InputIdx = Mask[i] >= Size;
9032 ++NumLoInputs[InputIdx];
9034 ++NumHiInputs[InputIdx];
9037 ++NumEvenInputs[InputIdx];
9039 ++NumOddInputs[InputIdx];
9042 // The minimum number of cross-input results for both the interleaved and
9043 // split cases. If interleaving results in fewer cross-input results, return
9045 int InterleavedCrosses = std::min(NumEvenInputs[1] + NumOddInputs[0],
9046 NumEvenInputs[0] + NumOddInputs[1]);
9047 int SplitCrosses = std::min(NumLoInputs[1] + NumHiInputs[0],
9048 NumLoInputs[0] + NumHiInputs[1]);
9049 return InterleavedCrosses < SplitCrosses;
9052 /// \brief Blend two v8i16 vectors using a naive unpack strategy.
9054 /// This strategy only works when the inputs from each vector fit into a single
9055 /// half of that vector, and generally there are not so many inputs as to leave
9056 /// the in-place shuffles required highly constrained (and thus expensive). It
9057 /// shifts all the inputs into a single side of both input vectors and then
9058 /// uses an unpack to interleave these inputs in a single vector. At that
9059 /// point, we will fall back on the generic single input shuffle lowering.
9060 static SDValue lowerV8I16BasicBlendVectorShuffle(SDLoc DL, SDValue V1,
9062 MutableArrayRef<int> Mask,
9063 const X86Subtarget *Subtarget,
9064 SelectionDAG &DAG) {
9065 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9066 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad input type!");
9067 SmallVector<int, 3> LoV1Inputs, HiV1Inputs, LoV2Inputs, HiV2Inputs;
9068 for (int i = 0; i < 8; ++i)
9069 if (Mask[i] >= 0 && Mask[i] < 4)
9070 LoV1Inputs.push_back(i);
9071 else if (Mask[i] >= 4 && Mask[i] < 8)
9072 HiV1Inputs.push_back(i);
9073 else if (Mask[i] >= 8 && Mask[i] < 12)
9074 LoV2Inputs.push_back(i);
9075 else if (Mask[i] >= 12)
9076 HiV2Inputs.push_back(i);
9078 int NumV1Inputs = LoV1Inputs.size() + HiV1Inputs.size();
9079 int NumV2Inputs = LoV2Inputs.size() + HiV2Inputs.size();
9082 assert(NumV1Inputs > 0 && NumV1Inputs <= 3 && "At most 3 inputs supported");
9083 assert(NumV2Inputs > 0 && NumV2Inputs <= 3 && "At most 3 inputs supported");
9084 assert(NumV1Inputs + NumV2Inputs <= 4 && "At most 4 combined inputs");
9086 bool MergeFromLo = LoV1Inputs.size() + LoV2Inputs.size() >=
9087 HiV1Inputs.size() + HiV2Inputs.size();
9089 auto moveInputsToHalf = [&](SDValue V, ArrayRef<int> LoInputs,
9090 ArrayRef<int> HiInputs, bool MoveToLo,
9092 ArrayRef<int> GoodInputs = MoveToLo ? LoInputs : HiInputs;
9093 ArrayRef<int> BadInputs = MoveToLo ? HiInputs : LoInputs;
9094 if (BadInputs.empty())
9097 int MoveMask[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9098 int MoveOffset = MoveToLo ? 0 : 4;
9100 if (GoodInputs.empty()) {
9101 for (int BadInput : BadInputs) {
9102 MoveMask[Mask[BadInput] % 4 + MoveOffset] = Mask[BadInput] - MaskOffset;
9103 Mask[BadInput] = Mask[BadInput] % 4 + MoveOffset + MaskOffset;
9106 if (GoodInputs.size() == 2) {
9107 // If the low inputs are spread across two dwords, pack them into
9109 MoveMask[MoveOffset] = Mask[GoodInputs[0]] - MaskOffset;
9110 MoveMask[MoveOffset + 1] = Mask[GoodInputs[1]] - MaskOffset;
9111 Mask[GoodInputs[0]] = MoveOffset + MaskOffset;
9112 Mask[GoodInputs[1]] = MoveOffset + 1 + MaskOffset;
9114 // Otherwise pin the good inputs.
9115 for (int GoodInput : GoodInputs)
9116 MoveMask[Mask[GoodInput] - MaskOffset] = Mask[GoodInput] - MaskOffset;
9119 if (BadInputs.size() == 2) {
9120 // If we have two bad inputs then there may be either one or two good
9121 // inputs fixed in place. Find a fixed input, and then find the *other*
9122 // two adjacent indices by using modular arithmetic.
9124 std::find_if(std::begin(MoveMask) + MoveOffset, std::end(MoveMask),
9125 [](int M) { return M >= 0; }) -
9126 std::begin(MoveMask);
9128 ((((GoodMaskIdx - MoveOffset) & ~1) + 2) % 4) + MoveOffset;
9129 assert(MoveMask[MoveMaskIdx] == -1 && "Expected empty slot");
9130 assert(MoveMask[MoveMaskIdx + 1] == -1 && "Expected empty slot");
9131 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9132 MoveMask[MoveMaskIdx + 1] = Mask[BadInputs[1]] - MaskOffset;
9133 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9134 Mask[BadInputs[1]] = MoveMaskIdx + 1 + MaskOffset;
9136 assert(BadInputs.size() == 1 && "All sizes handled");
9137 int MoveMaskIdx = std::find(std::begin(MoveMask) + MoveOffset,
9138 std::end(MoveMask), -1) -
9139 std::begin(MoveMask);
9140 MoveMask[MoveMaskIdx] = Mask[BadInputs[0]] - MaskOffset;
9141 Mask[BadInputs[0]] = MoveMaskIdx + MaskOffset;
9145 return DAG.getVectorShuffle(MVT::v8i16, DL, V, DAG.getUNDEF(MVT::v8i16),
9148 V1 = moveInputsToHalf(V1, LoV1Inputs, HiV1Inputs, MergeFromLo,
9150 V2 = moveInputsToHalf(V2, LoV2Inputs, HiV2Inputs, MergeFromLo,
9153 // FIXME: Select an interleaving of the merge of V1 and V2 that minimizes
9154 // cross-half traffic in the final shuffle.
9156 // Munge the mask to be a single-input mask after the unpack merges the
9160 M = 2 * (M % 4) + (M / 8);
9162 return DAG.getVectorShuffle(
9163 MVT::v8i16, DL, DAG.getNode(MergeFromLo ? X86ISD::UNPCKL : X86ISD::UNPCKH,
9164 DL, MVT::v8i16, V1, V2),
9165 DAG.getUNDEF(MVT::v8i16), Mask);
9168 /// \brief Generic lowering of 8-lane i16 shuffles.
9170 /// This handles both single-input shuffles and combined shuffle/blends with
9171 /// two inputs. The single input shuffles are immediately delegated to
9172 /// a dedicated lowering routine.
9174 /// The blends are lowered in one of three fundamental ways. If there are few
9175 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9176 /// of the input is significantly cheaper when lowered as an interleaving of
9177 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9178 /// halves of the inputs separately (making them have relatively few inputs)
9179 /// and then concatenate them.
9180 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9181 const X86Subtarget *Subtarget,
9182 SelectionDAG &DAG) {
9184 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9185 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9186 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9187 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9188 ArrayRef<int> OrigMask = SVOp->getMask();
9189 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9190 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9191 MutableArrayRef<int> Mask(MaskStorage);
9193 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9195 // Whenever we can lower this as a zext, that instruction is strictly faster
9196 // than any alternative.
9197 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9198 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9201 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9202 auto isV2 = [](int M) { return M >= 8; };
9204 int NumV1Inputs = std::count_if(Mask.begin(), Mask.end(), isV1);
9205 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9207 if (NumV2Inputs == 0)
9208 return lowerV8I16SingleInputVectorShuffle(DL, V1, Mask, Subtarget, DAG);
9210 assert(NumV1Inputs > 0 && "All single-input shuffles should be canonicalized "
9211 "to be V1-input shuffles.");
9213 // Try to use byte shift instructions.
9214 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9215 DL, MVT::v8i16, V1, V2, Mask, DAG))
9218 // There are special ways we can lower some single-element blends.
9219 if (NumV2Inputs == 1)
9220 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v8i16, DL, V1, V2,
9221 Mask, Subtarget, DAG))
9224 // Use dedicated unpack instructions for masks that match their pattern.
9225 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 2, 10, 3, 11))
9226 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9227 if (isShuffleEquivalent(Mask, 4, 12, 5, 13, 6, 14, 7, 15))
9228 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9230 if (Subtarget->hasSSE41())
9231 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9235 // Try to use byte rotation instructions.
9236 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9237 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9240 if (NumV1Inputs + NumV2Inputs <= 4)
9241 return lowerV8I16BasicBlendVectorShuffle(DL, V1, V2, Mask, Subtarget, DAG);
9243 // Check whether an interleaving lowering is likely to be more efficient.
9244 // This isn't perfect but it is a strong heuristic that tends to work well on
9245 // the kinds of shuffles that show up in practice.
9247 // FIXME: Handle 1x, 2x, and 4x interleaving.
9248 if (shouldLowerAsInterleaving(Mask)) {
9249 // FIXME: Figure out whether we should pack these into the low or high
9252 int EMask[8], OMask[8];
9253 for (int i = 0; i < 4; ++i) {
9254 EMask[i] = Mask[2*i];
9255 OMask[i] = Mask[2*i + 1];
9260 SDValue Evens = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, EMask);
9261 SDValue Odds = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, OMask);
9263 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, Evens, Odds);
9266 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9267 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9269 for (int i = 0; i < 4; ++i) {
9270 LoBlendMask[i] = Mask[i];
9271 HiBlendMask[i] = Mask[i + 4];
9274 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9275 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9276 LoV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, LoV);
9277 HiV = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, HiV);
9279 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9280 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, LoV, HiV));
9283 /// \brief Check whether a compaction lowering can be done by dropping even
9284 /// elements and compute how many times even elements must be dropped.
9286 /// This handles shuffles which take every Nth element where N is a power of
9287 /// two. Example shuffle masks:
9289 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9290 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9291 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9292 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9293 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9294 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9296 /// Any of these lanes can of course be undef.
9298 /// This routine only supports N <= 3.
9299 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9302 /// \returns N above, or the number of times even elements must be dropped if
9303 /// there is such a number. Otherwise returns zero.
9304 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9305 // Figure out whether we're looping over two inputs or just one.
9306 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9308 // The modulus for the shuffle vector entries is based on whether this is
9309 // a single input or not.
9310 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9311 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9312 "We should only be called with masks with a power-of-2 size!");
9314 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9316 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9317 // and 2^3 simultaneously. This is because we may have ambiguity with
9318 // partially undef inputs.
9319 bool ViableForN[3] = {true, true, true};
9321 for (int i = 0, e = Mask.size(); i < e; ++i) {
9322 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9327 bool IsAnyViable = false;
9328 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9329 if (ViableForN[j]) {
9332 // The shuffle mask must be equal to (i * 2^N) % M.
9333 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9336 ViableForN[j] = false;
9338 // Early exit if we exhaust the possible powers of two.
9343 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9347 // Return 0 as there is no viable power of two.
9351 /// \brief Generic lowering of v16i8 shuffles.
9353 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9354 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9355 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9356 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9358 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9359 const X86Subtarget *Subtarget,
9360 SelectionDAG &DAG) {
9362 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9363 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9364 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9366 ArrayRef<int> OrigMask = SVOp->getMask();
9367 assert(OrigMask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9369 // Try to use byte shift instructions.
9370 if (SDValue Shift = lowerVectorShuffleAsByteShift(
9371 DL, MVT::v16i8, V1, V2, OrigMask, DAG))
9374 // Try to use byte rotation instructions.
9375 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9376 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9379 // Try to use a zext lowering.
9380 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9381 DL, MVT::v16i8, V1, V2, OrigMask, Subtarget, DAG))
9384 int MaskStorage[16] = {
9385 OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9386 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7],
9387 OrigMask[8], OrigMask[9], OrigMask[10], OrigMask[11],
9388 OrigMask[12], OrigMask[13], OrigMask[14], OrigMask[15]};
9389 MutableArrayRef<int> Mask(MaskStorage);
9390 MutableArrayRef<int> LoMask = Mask.slice(0, 8);
9391 MutableArrayRef<int> HiMask = Mask.slice(8, 8);
9394 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9396 // For single-input shuffles, there are some nicer lowering tricks we can use.
9397 if (NumV2Elements == 0) {
9398 // Check for being able to broadcast a single element.
9399 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i8, DL, V1,
9400 Mask, Subtarget, DAG))
9403 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9404 // Notably, this handles splat and partial-splat shuffles more efficiently.
9405 // However, it only makes sense if the pre-duplication shuffle simplifies
9406 // things significantly. Currently, this means we need to be able to
9407 // express the pre-duplication shuffle as an i16 shuffle.
9409 // FIXME: We should check for other patterns which can be widened into an
9410 // i16 shuffle as well.
9411 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9412 for (int i = 0; i < 16; i += 2)
9413 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9418 auto tryToWidenViaDuplication = [&]() -> SDValue {
9419 if (!canWidenViaDuplication(Mask))
9421 SmallVector<int, 4> LoInputs;
9422 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9423 [](int M) { return M >= 0 && M < 8; });
9424 std::sort(LoInputs.begin(), LoInputs.end());
9425 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9427 SmallVector<int, 4> HiInputs;
9428 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9429 [](int M) { return M >= 8; });
9430 std::sort(HiInputs.begin(), HiInputs.end());
9431 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9434 bool TargetLo = LoInputs.size() >= HiInputs.size();
9435 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9436 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9438 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9439 SmallDenseMap<int, int, 8> LaneMap;
9440 for (int I : InPlaceInputs) {
9441 PreDupI16Shuffle[I/2] = I/2;
9444 int j = TargetLo ? 0 : 4, je = j + 4;
9445 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9446 // Check if j is already a shuffle of this input. This happens when
9447 // there are two adjacent bytes after we move the low one.
9448 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9449 // If we haven't yet mapped the input, search for a slot into which
9451 while (j < je && PreDupI16Shuffle[j] != -1)
9455 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9458 // Map this input with the i16 shuffle.
9459 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9462 // Update the lane map based on the mapping we ended up with.
9463 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9466 ISD::BITCAST, DL, MVT::v16i8,
9467 DAG.getVectorShuffle(MVT::v8i16, DL,
9468 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9469 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9471 // Unpack the bytes to form the i16s that will be shuffled into place.
9472 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9473 MVT::v16i8, V1, V1);
9475 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9476 for (int i = 0; i < 16; ++i)
9477 if (Mask[i] != -1) {
9478 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9479 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9480 if (PostDupI16Shuffle[i / 2] == -1)
9481 PostDupI16Shuffle[i / 2] = MappedMask;
9483 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9484 "Conflicting entrties in the original shuffle!");
9487 ISD::BITCAST, DL, MVT::v16i8,
9488 DAG.getVectorShuffle(MVT::v8i16, DL,
9489 DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1),
9490 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9492 if (SDValue V = tryToWidenViaDuplication())
9496 // Check whether an interleaving lowering is likely to be more efficient.
9497 // This isn't perfect but it is a strong heuristic that tends to work well on
9498 // the kinds of shuffles that show up in practice.
9500 // FIXME: We need to handle other interleaving widths (i16, i32, ...).
9501 if (shouldLowerAsInterleaving(Mask)) {
9502 int NumLoHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9503 return (M >= 0 && M < 8) || (M >= 16 && M < 24);
9505 int NumHiHalf = std::count_if(Mask.begin(), Mask.end(), [](int M) {
9506 return (M >= 8 && M < 16) || M >= 24;
9508 int EMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9509 -1, -1, -1, -1, -1, -1, -1, -1};
9510 int OMask[16] = {-1, -1, -1, -1, -1, -1, -1, -1,
9511 -1, -1, -1, -1, -1, -1, -1, -1};
9512 bool UnpackLo = NumLoHalf >= NumHiHalf;
9513 MutableArrayRef<int> TargetEMask(UnpackLo ? EMask : EMask + 8, 8);
9514 MutableArrayRef<int> TargetOMask(UnpackLo ? OMask : OMask + 8, 8);
9515 for (int i = 0; i < 8; ++i) {
9516 TargetEMask[i] = Mask[2 * i];
9517 TargetOMask[i] = Mask[2 * i + 1];
9520 SDValue Evens = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, EMask);
9521 SDValue Odds = DAG.getVectorShuffle(MVT::v16i8, DL, V1, V2, OMask);
9523 return DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9524 MVT::v16i8, Evens, Odds);
9527 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9528 // with PSHUFB. It is important to do this before we attempt to generate any
9529 // blends but after all of the single-input lowerings. If the single input
9530 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9531 // want to preserve that and we can DAG combine any longer sequences into
9532 // a PSHUFB in the end. But once we start blending from multiple inputs,
9533 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9534 // and there are *very* few patterns that would actually be faster than the
9535 // PSHUFB approach because of its ability to zero lanes.
9537 // FIXME: The only exceptions to the above are blends which are exact
9538 // interleavings with direct instructions supporting them. We currently don't
9539 // handle those well here.
9540 if (Subtarget->hasSSSE3()) {
9543 for (int i = 0; i < 16; ++i)
9544 if (Mask[i] == -1) {
9545 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9547 V1Mask[i] = DAG.getConstant(Mask[i] < 16 ? Mask[i] : 0x80, MVT::i8);
9549 DAG.getConstant(Mask[i] < 16 ? 0x80 : Mask[i] - 16, MVT::i8);
9551 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V1,
9552 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9553 if (isSingleInputShuffleMask(Mask))
9554 return V1; // Single inputs are easy.
9556 // Otherwise, blend the two.
9557 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, V2,
9558 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9559 return DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9562 // There are special ways we can lower some single-element blends.
9563 if (NumV2Elements == 1)
9564 if (SDValue V = lowerVectorShuffleAsElementInsertion(MVT::v16i8, DL, V1, V2,
9565 Mask, Subtarget, DAG))
9568 // Check whether a compaction lowering can be done. This handles shuffles
9569 // which take every Nth element for some even N. See the helper function for
9572 // We special case these as they can be particularly efficiently handled with
9573 // the PACKUSB instruction on x86 and they show up in common patterns of
9574 // rearranging bytes to truncate wide elements.
9575 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9576 // NumEvenDrops is the power of two stride of the elements. Another way of
9577 // thinking about it is that we need to drop the even elements this many
9578 // times to get the original input.
9579 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9581 // First we need to zero all the dropped bytes.
9582 assert(NumEvenDrops <= 3 &&
9583 "No support for dropping even elements more than 3 times.");
9584 // We use the mask type to pick which bytes are preserved based on how many
9585 // elements are dropped.
9586 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9587 SDValue ByteClearMask =
9588 DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,
9589 DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));
9590 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9592 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9594 // Now pack things back together.
9595 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V1);
9596 V2 = IsSingleInput ? V1 : DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);
9597 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9598 for (int i = 1; i < NumEvenDrops; ++i) {
9599 Result = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, Result);
9600 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9606 int V1LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9607 int V1HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9608 int V2LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9609 int V2HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9611 auto buildBlendMasks = [](MutableArrayRef<int> HalfMask,
9612 MutableArrayRef<int> V1HalfBlendMask,
9613 MutableArrayRef<int> V2HalfBlendMask) {
9614 for (int i = 0; i < 8; ++i)
9615 if (HalfMask[i] >= 0 && HalfMask[i] < 16) {
9616 V1HalfBlendMask[i] = HalfMask[i];
9618 } else if (HalfMask[i] >= 16) {
9619 V2HalfBlendMask[i] = HalfMask[i] - 16;
9620 HalfMask[i] = i + 8;
9623 buildBlendMasks(LoMask, V1LoBlendMask, V2LoBlendMask);
9624 buildBlendMasks(HiMask, V1HiBlendMask, V2HiBlendMask);
9626 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9628 auto buildLoAndHiV8s = [&](SDValue V, MutableArrayRef<int> LoBlendMask,
9629 MutableArrayRef<int> HiBlendMask) {
9631 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9632 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9634 if (std::none_of(LoBlendMask.begin(), LoBlendMask.end(),
9635 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9636 std::none_of(HiBlendMask.begin(), HiBlendMask.end(),
9637 [](int M) { return M >= 0 && M % 2 == 1; })) {
9638 // Use a mask to drop the high bytes.
9639 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
9640 V1 = DAG.getNode(ISD::AND, DL, MVT::v8i16, V1,
9641 DAG.getConstant(0x00FF, MVT::v8i16));
9643 // This will be a single vector shuffle instead of a blend so nuke V2.
9644 V2 = DAG.getUNDEF(MVT::v8i16);
9646 // Squash the masks to point directly into V1.
9647 for (int &M : LoBlendMask)
9650 for (int &M : HiBlendMask)
9654 // Otherwise just unpack the low half of V into V1 and the high half into
9655 // V2 so that we can blend them as i16s.
9656 V1 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9657 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9658 V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16,
9659 DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9662 SDValue BlendedLo = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, LoBlendMask);
9663 SDValue BlendedHi = DAG.getVectorShuffle(MVT::v8i16, DL, V1, V2, HiBlendMask);
9664 return std::make_pair(BlendedLo, BlendedHi);
9666 SDValue V1Lo, V1Hi, V2Lo, V2Hi;
9667 std::tie(V1Lo, V1Hi) = buildLoAndHiV8s(V1, V1LoBlendMask, V1HiBlendMask);
9668 std::tie(V2Lo, V2Hi) = buildLoAndHiV8s(V2, V2LoBlendMask, V2HiBlendMask);
9670 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Lo, V2Lo, LoMask);
9671 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, V1Hi, V2Hi, HiMask);
9673 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9676 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9678 /// This routine breaks down the specific type of 128-bit shuffle and
9679 /// dispatches to the lowering routines accordingly.
9680 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9681 MVT VT, const X86Subtarget *Subtarget,
9682 SelectionDAG &DAG) {
9683 switch (VT.SimpleTy) {
9685 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9687 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9689 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9691 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9693 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9695 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9698 llvm_unreachable("Unimplemented!");
9702 /// \brief Helper function to test whether a shuffle mask could be
9703 /// simplified by widening the elements being shuffled.
9705 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9706 /// leaves it in an unspecified state.
9708 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9709 /// shuffle masks. The latter have the special property of a '-2' representing
9710 /// a zero-ed lane of a vector.
9711 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9712 SmallVectorImpl<int> &WidenedMask) {
9713 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9714 // If both elements are undef, its trivial.
9715 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9716 WidenedMask.push_back(SM_SentinelUndef);
9720 // Check for an undef mask and a mask value properly aligned to fit with
9721 // a pair of values. If we find such a case, use the non-undef mask's value.
9722 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9723 WidenedMask.push_back(Mask[i + 1] / 2);
9726 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9727 WidenedMask.push_back(Mask[i] / 2);
9731 // When zeroing, we need to spread the zeroing across both lanes to widen.
9732 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9733 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9734 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9735 WidenedMask.push_back(SM_SentinelZero);
9741 // Finally check if the two mask values are adjacent and aligned with
9743 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9744 WidenedMask.push_back(Mask[i] / 2);
9748 // Otherwise we can't safely widen the elements used in this shuffle.
9751 assert(WidenedMask.size() == Mask.size() / 2 &&
9752 "Incorrect size of mask after widening the elements!");
9757 /// \brief Generic routine to split ector shuffle into half-sized shuffles.
9759 /// This routine just extracts two subvectors, shuffles them independently, and
9760 /// then concatenates them back together. This should work effectively with all
9761 /// AVX vector shuffle types.
9762 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9763 SDValue V2, ArrayRef<int> Mask,
9764 SelectionDAG &DAG) {
9765 assert(VT.getSizeInBits() >= 256 &&
9766 "Only for 256-bit or wider vector shuffles!");
9767 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9768 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9770 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9771 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9773 int NumElements = VT.getVectorNumElements();
9774 int SplitNumElements = NumElements / 2;
9775 MVT ScalarVT = VT.getScalarType();
9776 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9778 SDValue LoV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9779 DAG.getIntPtrConstant(0));
9780 SDValue HiV1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V1,
9781 DAG.getIntPtrConstant(SplitNumElements));
9782 SDValue LoV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9783 DAG.getIntPtrConstant(0));
9784 SDValue HiV2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, V2,
9785 DAG.getIntPtrConstant(SplitNumElements));
9787 // Now create two 4-way blends of these half-width vectors.
9788 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9789 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9790 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9791 for (int i = 0; i < SplitNumElements; ++i) {
9792 int M = HalfMask[i];
9793 if (M >= NumElements) {
9794 if (M >= NumElements + SplitNumElements)
9798 V2BlendMask.push_back(M - NumElements);
9799 V1BlendMask.push_back(-1);
9800 BlendMask.push_back(SplitNumElements + i);
9801 } else if (M >= 0) {
9802 if (M >= SplitNumElements)
9806 V2BlendMask.push_back(-1);
9807 V1BlendMask.push_back(M);
9808 BlendMask.push_back(i);
9810 V2BlendMask.push_back(-1);
9811 V1BlendMask.push_back(-1);
9812 BlendMask.push_back(-1);
9816 // Because the lowering happens after all combining takes place, we need to
9817 // manually combine these blend masks as much as possible so that we create
9818 // a minimal number of high-level vector shuffle nodes.
9820 // First try just blending the halves of V1 or V2.
9821 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9822 return DAG.getUNDEF(SplitVT);
9823 if (!UseLoV2 && !UseHiV2)
9824 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9825 if (!UseLoV1 && !UseHiV1)
9826 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9828 SDValue V1Blend, V2Blend;
9829 if (UseLoV1 && UseHiV1) {
9831 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9833 // We only use half of V1 so map the usage down into the final blend mask.
9834 V1Blend = UseLoV1 ? LoV1 : HiV1;
9835 for (int i = 0; i < SplitNumElements; ++i)
9836 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9837 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9839 if (UseLoV2 && UseHiV2) {
9841 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9843 // We only use half of V2 so map the usage down into the final blend mask.
9844 V2Blend = UseLoV2 ? LoV2 : HiV2;
9845 for (int i = 0; i < SplitNumElements; ++i)
9846 if (BlendMask[i] >= SplitNumElements)
9847 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9849 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9851 SDValue Lo = HalfBlend(LoMask);
9852 SDValue Hi = HalfBlend(HiMask);
9853 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9856 /// \brief Either split a vector in halves or decompose the shuffles and the
9859 /// This is provided as a good fallback for many lowerings of non-single-input
9860 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9861 /// between splitting the shuffle into 128-bit components and stitching those
9862 /// back together vs. extracting the single-input shuffles and blending those
9864 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9865 SDValue V2, ArrayRef<int> Mask,
9866 SelectionDAG &DAG) {
9867 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9868 "lower single-input shuffles as it "
9869 "could then recurse on itself.");
9870 int Size = Mask.size();
9872 // If this can be modeled as a broadcast of two elements followed by a blend,
9873 // prefer that lowering. This is especially important because broadcasts can
9874 // often fold with memory operands.
9875 auto DoBothBroadcast = [&] {
9876 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9879 if (V2BroadcastIdx == -1)
9880 V2BroadcastIdx = M - Size;
9881 else if (M - Size != V2BroadcastIdx)
9883 } else if (M >= 0) {
9884 if (V1BroadcastIdx == -1)
9886 else if (M != V1BroadcastIdx)
9891 if (DoBothBroadcast())
9892 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9895 // If the inputs all stem from a single 128-bit lane of each input, then we
9896 // split them rather than blending because the split will decompose to
9897 // unusually few instructions.
9898 int LaneCount = VT.getSizeInBits() / 128;
9899 int LaneSize = Size / LaneCount;
9900 SmallBitVector LaneInputs[2];
9901 LaneInputs[0].resize(LaneCount, false);
9902 LaneInputs[1].resize(LaneCount, false);
9903 for (int i = 0; i < Size; ++i)
9905 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9906 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9907 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9909 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9910 // that the decomposed single-input shuffles don't end up here.
9911 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9914 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9915 /// a permutation and blend of those lanes.
9917 /// This essentially blends the out-of-lane inputs to each lane into the lane
9918 /// from a permuted copy of the vector. This lowering strategy results in four
9919 /// instructions in the worst case for a single-input cross lane shuffle which
9920 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9921 /// of. Special cases for each particular shuffle pattern should be handled
9922 /// prior to trying this lowering.
9923 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9924 SDValue V1, SDValue V2,
9926 SelectionDAG &DAG) {
9927 // FIXME: This should probably be generalized for 512-bit vectors as well.
9928 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9929 int LaneSize = Mask.size() / 2;
9931 // If there are only inputs from one 128-bit lane, splitting will in fact be
9932 // less expensive. The flags track wether the given lane contains an element
9933 // that crosses to another lane.
9934 bool LaneCrossing[2] = {false, false};
9935 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9936 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9937 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9938 if (!LaneCrossing[0] || !LaneCrossing[1])
9939 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9941 if (isSingleInputShuffleMask(Mask)) {
9942 SmallVector<int, 32> FlippedBlendMask;
9943 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9944 FlippedBlendMask.push_back(
9945 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9947 : Mask[i] % LaneSize +
9948 (i / LaneSize) * LaneSize + Size));
9950 // Flip the vector, and blend the results which should now be in-lane. The
9951 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9952 // 5 for the high source. The value 3 selects the high half of source 2 and
9953 // the value 2 selects the low half of source 2. We only use source 2 to
9954 // allow folding it into a memory operand.
9955 unsigned PERMMask = 3 | 2 << 4;
9956 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9957 V1, DAG.getConstant(PERMMask, MVT::i8));
9958 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9961 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9962 // will be handled by the above logic and a blend of the results, much like
9963 // other patterns in AVX.
9964 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9967 /// \brief Handle lowering 2-lane 128-bit shuffles.
9968 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9969 SDValue V2, ArrayRef<int> Mask,
9970 const X86Subtarget *Subtarget,
9971 SelectionDAG &DAG) {
9972 // Blends are faster and handle all the non-lane-crossing cases.
9973 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9977 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9978 VT.getVectorNumElements() / 2);
9979 // Check for patterns which can be matched with a single insert of a 128-bit
9981 if (isShuffleEquivalent(Mask, 0, 1, 0, 1) ||
9982 isShuffleEquivalent(Mask, 0, 1, 4, 5)) {
9983 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9984 DAG.getIntPtrConstant(0));
9985 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9986 Mask[2] < 4 ? V1 : V2, DAG.getIntPtrConstant(0));
9987 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9989 if (isShuffleEquivalent(Mask, 0, 1, 6, 7)) {
9990 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9991 DAG.getIntPtrConstant(0));
9992 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V2,
9993 DAG.getIntPtrConstant(2));
9994 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9997 // Otherwise form a 128-bit permutation.
9998 // FIXME: Detect zero-vector inputs and use the VPERM2X128 to zero that half.
9999 unsigned PermMask = Mask[0] / 2 | (Mask[2] / 2) << 4;
10000 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10001 DAG.getConstant(PermMask, MVT::i8));
10004 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10005 /// shuffling each lane.
10007 /// This will only succeed when the result of fixing the 128-bit lanes results
10008 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10009 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10010 /// the lane crosses early and then use simpler shuffles within each lane.
10012 /// FIXME: It might be worthwhile at some point to support this without
10013 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10014 /// in x86 only floating point has interesting non-repeating shuffles, and even
10015 /// those are still *marginally* more expensive.
10016 static SDValue lowerVectorShuffleByMerging128BitLanes(
10017 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10018 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10019 assert(!isSingleInputShuffleMask(Mask) &&
10020 "This is only useful with multiple inputs.");
10022 int Size = Mask.size();
10023 int LaneSize = 128 / VT.getScalarSizeInBits();
10024 int NumLanes = Size / LaneSize;
10025 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10027 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10028 // check whether the in-128-bit lane shuffles share a repeating pattern.
10029 SmallVector<int, 4> Lanes;
10030 Lanes.resize(NumLanes, -1);
10031 SmallVector<int, 4> InLaneMask;
10032 InLaneMask.resize(LaneSize, -1);
10033 for (int i = 0; i < Size; ++i) {
10037 int j = i / LaneSize;
10039 if (Lanes[j] < 0) {
10040 // First entry we've seen for this lane.
10041 Lanes[j] = Mask[i] / LaneSize;
10042 } else if (Lanes[j] != Mask[i] / LaneSize) {
10043 // This doesn't match the lane selected previously!
10047 // Check that within each lane we have a consistent shuffle mask.
10048 int k = i % LaneSize;
10049 if (InLaneMask[k] < 0) {
10050 InLaneMask[k] = Mask[i] % LaneSize;
10051 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10052 // This doesn't fit a repeating in-lane mask.
10057 // First shuffle the lanes into place.
10058 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10059 VT.getSizeInBits() / 64);
10060 SmallVector<int, 8> LaneMask;
10061 LaneMask.resize(NumLanes * 2, -1);
10062 for (int i = 0; i < NumLanes; ++i)
10063 if (Lanes[i] >= 0) {
10064 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10065 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10068 V1 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V1);
10069 V2 = DAG.getNode(ISD::BITCAST, DL, LaneVT, V2);
10070 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10072 // Cast it back to the type we actually want.
10073 LaneShuffle = DAG.getNode(ISD::BITCAST, DL, VT, LaneShuffle);
10075 // Now do a simple shuffle that isn't lane crossing.
10076 SmallVector<int, 8> NewMask;
10077 NewMask.resize(Size, -1);
10078 for (int i = 0; i < Size; ++i)
10080 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10081 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10082 "Must not introduce lane crosses at this point!");
10084 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10087 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10090 /// This returns true if the elements from a particular input are already in the
10091 /// slot required by the given mask and require no permutation.
10092 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10093 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10094 int Size = Mask.size();
10095 for (int i = 0; i < Size; ++i)
10096 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10102 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10104 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10105 /// isn't available.
10106 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10107 const X86Subtarget *Subtarget,
10108 SelectionDAG &DAG) {
10110 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10111 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10112 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10113 ArrayRef<int> Mask = SVOp->getMask();
10114 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10116 SmallVector<int, 4> WidenedMask;
10117 if (canWidenShuffleElements(Mask, WidenedMask))
10118 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10121 if (isSingleInputShuffleMask(Mask)) {
10122 // Check for being able to broadcast a single element.
10123 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4f64, DL, V1,
10124 Mask, Subtarget, DAG))
10127 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10128 // Non-half-crossing single input shuffles can be lowerid with an
10129 // interleaved permutation.
10130 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10131 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10132 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10133 DAG.getConstant(VPERMILPMask, MVT::i8));
10136 // With AVX2 we have direct support for this permutation.
10137 if (Subtarget->hasAVX2())
10138 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10139 getV4X86ShuffleImm8ForMask(Mask, DAG));
10141 // Otherwise, fall back.
10142 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10146 // X86 has dedicated unpack instructions that can handle specific blend
10147 // operations: UNPCKH and UNPCKL.
10148 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10149 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10150 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10151 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10153 // If we have a single input to the zero element, insert that into V1 if we
10154 // can do so cheaply.
10155 int NumV2Elements =
10156 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
10157 if (NumV2Elements == 1 && Mask[0] >= 4)
10158 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10159 MVT::v4f64, DL, V1, V2, Mask, Subtarget, DAG))
10162 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10166 // Check if the blend happens to exactly fit that of SHUFPD.
10167 if ((Mask[0] == -1 || Mask[0] < 2) &&
10168 (Mask[1] == -1 || (Mask[1] >= 4 && Mask[1] < 6)) &&
10169 (Mask[2] == -1 || (Mask[2] >= 2 && Mask[2] < 4)) &&
10170 (Mask[3] == -1 || Mask[3] >= 6)) {
10171 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |
10172 ((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);
10173 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,
10174 DAG.getConstant(SHUFPDMask, MVT::i8));
10176 if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&
10177 (Mask[1] == -1 || Mask[1] < 2) &&
10178 (Mask[2] == -1 || Mask[2] >= 6) &&
10179 (Mask[3] == -1 || (Mask[3] >= 2 && Mask[3] < 4))) {
10180 unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |
10181 ((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);
10182 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,
10183 DAG.getConstant(SHUFPDMask, MVT::i8));
10186 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10187 // shuffle. However, if we have AVX2 and either inputs are already in place,
10188 // we will be able to shuffle even across lanes the other input in a single
10189 // instruction so skip this pattern.
10190 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10191 isShuffleMaskInputInPlace(1, Mask))))
10192 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10193 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10196 // If we have AVX2 then we always want to lower with a blend because an v4 we
10197 // can fully permute the elements.
10198 if (Subtarget->hasAVX2())
10199 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10202 // Otherwise fall back on generic lowering.
10203 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10206 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10208 /// This routine is only called when we have AVX2 and thus a reasonable
10209 /// instruction set for v4i64 shuffling..
10210 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10211 const X86Subtarget *Subtarget,
10212 SelectionDAG &DAG) {
10214 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10215 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10216 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10217 ArrayRef<int> Mask = SVOp->getMask();
10218 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10219 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10221 SmallVector<int, 4> WidenedMask;
10222 if (canWidenShuffleElements(Mask, WidenedMask))
10223 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10226 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10230 // Check for being able to broadcast a single element.
10231 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v4i64, DL, V1,
10232 Mask, Subtarget, DAG))
10235 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10236 // use lower latency instructions that will operate on both 128-bit lanes.
10237 SmallVector<int, 2> RepeatedMask;
10238 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10239 if (isSingleInputShuffleMask(Mask)) {
10240 int PSHUFDMask[] = {-1, -1, -1, -1};
10241 for (int i = 0; i < 2; ++i)
10242 if (RepeatedMask[i] >= 0) {
10243 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10244 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10246 return DAG.getNode(
10247 ISD::BITCAST, DL, MVT::v4i64,
10248 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10249 DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),
10250 getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));
10253 // Use dedicated unpack instructions for masks that match their pattern.
10254 if (isShuffleEquivalent(Mask, 0, 4, 2, 6))
10255 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10256 if (isShuffleEquivalent(Mask, 1, 5, 3, 7))
10257 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10260 // AVX2 provides a direct instruction for permuting a single input across
10262 if (isSingleInputShuffleMask(Mask))
10263 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10264 getV4X86ShuffleImm8ForMask(Mask, DAG));
10266 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10267 // shuffle. However, if we have AVX2 and either inputs are already in place,
10268 // we will be able to shuffle even across lanes the other input in a single
10269 // instruction so skip this pattern.
10270 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10271 isShuffleMaskInputInPlace(1, Mask))))
10272 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10273 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10276 // Otherwise fall back on generic blend lowering.
10277 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10281 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10283 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10284 /// isn't available.
10285 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10286 const X86Subtarget *Subtarget,
10287 SelectionDAG &DAG) {
10289 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10290 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10291 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10292 ArrayRef<int> Mask = SVOp->getMask();
10293 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10295 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10299 // Check for being able to broadcast a single element.
10300 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8f32, DL, V1,
10301 Mask, Subtarget, DAG))
10304 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10305 // options to efficiently lower the shuffle.
10306 SmallVector<int, 4> RepeatedMask;
10307 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10308 assert(RepeatedMask.size() == 4 &&
10309 "Repeated masks must be half the mask width!");
10310 if (isSingleInputShuffleMask(Mask))
10311 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10312 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10314 // Use dedicated unpack instructions for masks that match their pattern.
10315 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10316 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10317 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10318 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10320 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10321 // have already handled any direct blends. We also need to squash the
10322 // repeated mask into a simulated v4f32 mask.
10323 for (int i = 0; i < 4; ++i)
10324 if (RepeatedMask[i] >= 8)
10325 RepeatedMask[i] -= 4;
10326 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10329 // If we have a single input shuffle with different shuffle patterns in the
10330 // two 128-bit lanes use the variable mask to VPERMILPS.
10331 if (isSingleInputShuffleMask(Mask)) {
10332 SDValue VPermMask[8];
10333 for (int i = 0; i < 8; ++i)
10334 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10335 : DAG.getConstant(Mask[i], MVT::i32);
10336 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10337 return DAG.getNode(
10338 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10339 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10341 if (Subtarget->hasAVX2())
10342 return DAG.getNode(X86ISD::VPERMV, DL, MVT::v8f32,
10343 DAG.getNode(ISD::BITCAST, DL, MVT::v8f32,
10344 DAG.getNode(ISD::BUILD_VECTOR, DL,
10345 MVT::v8i32, VPermMask)),
10348 // Otherwise, fall back.
10349 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10353 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10355 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10356 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10359 // If we have AVX2 then we always want to lower with a blend because at v8 we
10360 // can fully permute the elements.
10361 if (Subtarget->hasAVX2())
10362 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10365 // Otherwise fall back on generic lowering.
10366 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10369 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10371 /// This routine is only called when we have AVX2 and thus a reasonable
10372 /// instruction set for v8i32 shuffling..
10373 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10374 const X86Subtarget *Subtarget,
10375 SelectionDAG &DAG) {
10377 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10378 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10379 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10380 ArrayRef<int> Mask = SVOp->getMask();
10381 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10382 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10384 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10388 // Check for being able to broadcast a single element.
10389 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v8i32, DL, V1,
10390 Mask, Subtarget, DAG))
10393 // If the shuffle mask is repeated in each 128-bit lane we can use more
10394 // efficient instructions that mirror the shuffles across the two 128-bit
10396 SmallVector<int, 4> RepeatedMask;
10397 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10398 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10399 if (isSingleInputShuffleMask(Mask))
10400 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10401 getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));
10403 // Use dedicated unpack instructions for masks that match their pattern.
10404 if (isShuffleEquivalent(Mask, 0, 8, 1, 9, 4, 12, 5, 13))
10405 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10406 if (isShuffleEquivalent(Mask, 2, 10, 3, 11, 6, 14, 7, 15))
10407 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10410 // If the shuffle patterns aren't repeated but it is a single input, directly
10411 // generate a cross-lane VPERMD instruction.
10412 if (isSingleInputShuffleMask(Mask)) {
10413 SDValue VPermMask[8];
10414 for (int i = 0; i < 8; ++i)
10415 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10416 : DAG.getConstant(Mask[i], MVT::i32);
10417 return DAG.getNode(
10418 X86ISD::VPERMV, DL, MVT::v8i32,
10419 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10422 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10424 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10425 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10428 // Otherwise fall back on generic blend lowering.
10429 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10433 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10435 /// This routine is only called when we have AVX2 and thus a reasonable
10436 /// instruction set for v16i16 shuffling..
10437 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10438 const X86Subtarget *Subtarget,
10439 SelectionDAG &DAG) {
10441 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10442 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10443 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10444 ArrayRef<int> Mask = SVOp->getMask();
10445 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10446 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10448 // Check for being able to broadcast a single element.
10449 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v16i16, DL, V1,
10450 Mask, Subtarget, DAG))
10453 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10457 // Use dedicated unpack instructions for masks that match their pattern.
10458 if (isShuffleEquivalent(Mask,
10459 // First 128-bit lane:
10460 0, 16, 1, 17, 2, 18, 3, 19,
10461 // Second 128-bit lane:
10462 8, 24, 9, 25, 10, 26, 11, 27))
10463 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10464 if (isShuffleEquivalent(Mask,
10465 // First 128-bit lane:
10466 4, 20, 5, 21, 6, 22, 7, 23,
10467 // Second 128-bit lane:
10468 12, 28, 13, 29, 14, 30, 15, 31))
10469 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10471 if (isSingleInputShuffleMask(Mask)) {
10472 // There are no generalized cross-lane shuffle operations available on i16
10474 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10475 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10478 SDValue PSHUFBMask[32];
10479 for (int i = 0; i < 16; ++i) {
10480 if (Mask[i] == -1) {
10481 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10485 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10486 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10487 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);
10488 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);
10490 return DAG.getNode(
10491 ISD::BITCAST, DL, MVT::v16i16,
10493 X86ISD::PSHUFB, DL, MVT::v32i8,
10494 DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, V1),
10495 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)));
10498 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10500 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10501 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10504 // Otherwise fall back on generic lowering.
10505 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10508 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10510 /// This routine is only called when we have AVX2 and thus a reasonable
10511 /// instruction set for v32i8 shuffling..
10512 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10513 const X86Subtarget *Subtarget,
10514 SelectionDAG &DAG) {
10516 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10517 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10518 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10519 ArrayRef<int> Mask = SVOp->getMask();
10520 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10521 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10523 // Check for being able to broadcast a single element.
10524 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(MVT::v32i8, DL, V1,
10525 Mask, Subtarget, DAG))
10528 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10532 // Use dedicated unpack instructions for masks that match their pattern.
10533 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10535 if (isShuffleEquivalent(
10537 // First 128-bit lane:
10538 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10539 // Second 128-bit lane:
10540 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55))
10541 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10542 if (isShuffleEquivalent(
10544 // First 128-bit lane:
10545 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10546 // Second 128-bit lane:
10547 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63))
10548 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10550 if (isSingleInputShuffleMask(Mask)) {
10551 // There are no generalized cross-lane shuffle operations available on i8
10553 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10554 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10557 SDValue PSHUFBMask[32];
10558 for (int i = 0; i < 32; ++i)
10561 ? DAG.getUNDEF(MVT::i8)
10562 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);
10564 return DAG.getNode(
10565 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10566 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10569 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10571 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10572 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10575 // Otherwise fall back on generic lowering.
10576 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10579 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10581 /// This routine either breaks down the specific type of a 256-bit x86 vector
10582 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10583 /// together based on the available instructions.
10584 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10585 MVT VT, const X86Subtarget *Subtarget,
10586 SelectionDAG &DAG) {
10588 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10589 ArrayRef<int> Mask = SVOp->getMask();
10591 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10592 // check for those subtargets here and avoid much of the subtarget querying in
10593 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10594 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10595 // floating point types there eventually, just immediately cast everything to
10596 // a float and operate entirely in that domain.
10597 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10598 int ElementBits = VT.getScalarSizeInBits();
10599 if (ElementBits < 32)
10600 // No floating point type available, decompose into 128-bit vectors.
10601 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10603 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10604 VT.getVectorNumElements());
10605 V1 = DAG.getNode(ISD::BITCAST, DL, FpVT, V1);
10606 V2 = DAG.getNode(ISD::BITCAST, DL, FpVT, V2);
10607 return DAG.getNode(ISD::BITCAST, DL, VT,
10608 DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10611 switch (VT.SimpleTy) {
10613 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10615 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10617 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10619 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10621 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10623 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10626 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10630 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10631 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10632 const X86Subtarget *Subtarget,
10633 SelectionDAG &DAG) {
10635 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10636 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10637 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10638 ArrayRef<int> Mask = SVOp->getMask();
10639 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10641 // FIXME: Implement direct support for this type!
10642 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10645 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10646 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10647 const X86Subtarget *Subtarget,
10648 SelectionDAG &DAG) {
10650 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10651 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10652 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10653 ArrayRef<int> Mask = SVOp->getMask();
10654 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10656 // FIXME: Implement direct support for this type!
10657 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10660 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10661 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10662 const X86Subtarget *Subtarget,
10663 SelectionDAG &DAG) {
10665 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10666 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10667 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10668 ArrayRef<int> Mask = SVOp->getMask();
10669 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10671 // FIXME: Implement direct support for this type!
10672 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10675 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10676 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10677 const X86Subtarget *Subtarget,
10678 SelectionDAG &DAG) {
10680 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10681 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10682 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10683 ArrayRef<int> Mask = SVOp->getMask();
10684 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10686 // FIXME: Implement direct support for this type!
10687 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10690 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10691 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10692 const X86Subtarget *Subtarget,
10693 SelectionDAG &DAG) {
10695 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10696 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10697 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10698 ArrayRef<int> Mask = SVOp->getMask();
10699 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10700 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10702 // FIXME: Implement direct support for this type!
10703 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10706 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10707 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10708 const X86Subtarget *Subtarget,
10709 SelectionDAG &DAG) {
10711 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10712 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10713 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10714 ArrayRef<int> Mask = SVOp->getMask();
10715 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10716 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10718 // FIXME: Implement direct support for this type!
10719 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10722 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10724 /// This routine either breaks down the specific type of a 512-bit x86 vector
10725 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10726 /// together based on the available instructions.
10727 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10728 MVT VT, const X86Subtarget *Subtarget,
10729 SelectionDAG &DAG) {
10731 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10732 ArrayRef<int> Mask = SVOp->getMask();
10733 assert(Subtarget->hasAVX512() &&
10734 "Cannot lower 512-bit vectors w/ basic ISA!");
10736 // Check for being able to broadcast a single element.
10737 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(VT.SimpleTy, DL, V1,
10738 Mask, Subtarget, DAG))
10741 // Dispatch to each element type for lowering. If we don't have supprot for
10742 // specific element type shuffles at 512 bits, immediately split them and
10743 // lower them. Each lowering routine of a given type is allowed to assume that
10744 // the requisite ISA extensions for that element type are available.
10745 switch (VT.SimpleTy) {
10747 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10749 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10751 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10753 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10755 if (Subtarget->hasBWI())
10756 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10759 if (Subtarget->hasBWI())
10760 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10764 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10767 // Otherwise fall back on splitting.
10768 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10771 /// \brief Top-level lowering for x86 vector shuffles.
10773 /// This handles decomposition, canonicalization, and lowering of all x86
10774 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10775 /// above in helper routines. The canonicalization attempts to widen shuffles
10776 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10777 /// s.t. only one of the two inputs needs to be tested, etc.
10778 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10779 SelectionDAG &DAG) {
10780 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10781 ArrayRef<int> Mask = SVOp->getMask();
10782 SDValue V1 = Op.getOperand(0);
10783 SDValue V2 = Op.getOperand(1);
10784 MVT VT = Op.getSimpleValueType();
10785 int NumElements = VT.getVectorNumElements();
10788 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10790 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10791 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10792 if (V1IsUndef && V2IsUndef)
10793 return DAG.getUNDEF(VT);
10795 // When we create a shuffle node we put the UNDEF node to second operand,
10796 // but in some cases the first operand may be transformed to UNDEF.
10797 // In this case we should just commute the node.
10799 return DAG.getCommutedVectorShuffle(*SVOp);
10801 // Check for non-undef masks pointing at an undef vector and make the masks
10802 // undef as well. This makes it easier to match the shuffle based solely on
10806 if (M >= NumElements) {
10807 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10808 for (int &M : NewMask)
10809 if (M >= NumElements)
10811 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10814 // Try to collapse shuffles into using a vector type with fewer elements but
10815 // wider element types. We cap this to not form integers or floating point
10816 // elements wider than 64 bits, but it might be interesting to form i128
10817 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10818 SmallVector<int, 16> WidenedMask;
10819 if (VT.getScalarSizeInBits() < 64 &&
10820 canWidenShuffleElements(Mask, WidenedMask)) {
10821 MVT NewEltVT = VT.isFloatingPoint()
10822 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10823 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10824 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10825 // Make sure that the new vector type is legal. For example, v2f64 isn't
10827 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10828 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
10829 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
10830 return DAG.getNode(ISD::BITCAST, dl, VT,
10831 DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10835 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10836 for (int M : SVOp->getMask())
10838 ++NumUndefElements;
10839 else if (M < NumElements)
10844 // Commute the shuffle as needed such that more elements come from V1 than
10845 // V2. This allows us to match the shuffle pattern strictly on how many
10846 // elements come from V1 without handling the symmetric cases.
10847 if (NumV2Elements > NumV1Elements)
10848 return DAG.getCommutedVectorShuffle(*SVOp);
10850 // When the number of V1 and V2 elements are the same, try to minimize the
10851 // number of uses of V2 in the low half of the vector. When that is tied,
10852 // ensure that the sum of indices for V1 is equal to or lower than the sum
10853 // indices for V2. When those are equal, try to ensure that the number of odd
10854 // indices for V1 is lower than the number of odd indices for V2.
10855 if (NumV1Elements == NumV2Elements) {
10856 int LowV1Elements = 0, LowV2Elements = 0;
10857 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10858 if (M >= NumElements)
10862 if (LowV2Elements > LowV1Elements) {
10863 return DAG.getCommutedVectorShuffle(*SVOp);
10864 } else if (LowV2Elements == LowV1Elements) {
10865 int SumV1Indices = 0, SumV2Indices = 0;
10866 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10867 if (SVOp->getMask()[i] >= NumElements)
10869 else if (SVOp->getMask()[i] >= 0)
10871 if (SumV2Indices < SumV1Indices) {
10872 return DAG.getCommutedVectorShuffle(*SVOp);
10873 } else if (SumV2Indices == SumV1Indices) {
10874 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10875 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10876 if (SVOp->getMask()[i] >= NumElements)
10877 NumV2OddIndices += i % 2;
10878 else if (SVOp->getMask()[i] >= 0)
10879 NumV1OddIndices += i % 2;
10880 if (NumV2OddIndices < NumV1OddIndices)
10881 return DAG.getCommutedVectorShuffle(*SVOp);
10886 // For each vector width, delegate to a specialized lowering routine.
10887 if (VT.getSizeInBits() == 128)
10888 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10890 if (VT.getSizeInBits() == 256)
10891 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10893 // Force AVX-512 vectors to be scalarized for now.
10894 // FIXME: Implement AVX-512 support!
10895 if (VT.getSizeInBits() == 512)
10896 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10898 llvm_unreachable("Unimplemented!");
10902 //===----------------------------------------------------------------------===//
10903 // Legacy vector shuffle lowering
10905 // This code is the legacy code handling vector shuffles until the above
10906 // replaces its functionality and performance.
10907 //===----------------------------------------------------------------------===//
10909 static bool isBlendMask(ArrayRef<int> MaskVals, MVT VT, bool hasSSE41,
10910 bool hasInt256, unsigned *MaskOut = nullptr) {
10911 MVT EltVT = VT.getVectorElementType();
10913 // There is no blend with immediate in AVX-512.
10914 if (VT.is512BitVector())
10917 if (!hasSSE41 || EltVT == MVT::i8)
10919 if (!hasInt256 && VT == MVT::v16i16)
10922 unsigned MaskValue = 0;
10923 unsigned NumElems = VT.getVectorNumElements();
10924 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10925 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10926 unsigned NumElemsInLane = NumElems / NumLanes;
10928 // Blend for v16i16 should be symetric for the both lanes.
10929 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10931 int SndLaneEltIdx = (NumLanes == 2) ? MaskVals[i + NumElemsInLane] : -1;
10932 int EltIdx = MaskVals[i];
10934 if ((EltIdx < 0 || EltIdx == (int)i) &&
10935 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
10938 if (((unsigned)EltIdx == (i + NumElems)) &&
10939 (SndLaneEltIdx < 0 ||
10940 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
10941 MaskValue |= (1 << i);
10947 *MaskOut = MaskValue;
10951 // Try to lower a shuffle node into a simple blend instruction.
10952 // This function assumes isBlendMask returns true for this
10953 // SuffleVectorSDNode
10954 static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
10955 unsigned MaskValue,
10956 const X86Subtarget *Subtarget,
10957 SelectionDAG &DAG) {
10958 MVT VT = SVOp->getSimpleValueType(0);
10959 MVT EltVT = VT.getVectorElementType();
10960 assert(isBlendMask(SVOp->getMask(), VT, Subtarget->hasSSE41(),
10961 Subtarget->hasInt256() && "Trying to lower a "
10962 "VECTOR_SHUFFLE to a Blend but "
10963 "with the wrong mask"));
10964 SDValue V1 = SVOp->getOperand(0);
10965 SDValue V2 = SVOp->getOperand(1);
10967 unsigned NumElems = VT.getVectorNumElements();
10969 // Convert i32 vectors to floating point if it is not AVX2.
10970 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
10972 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
10973 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
10975 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
10976 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
10979 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
10980 DAG.getConstant(MaskValue, MVT::i32));
10981 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
10984 /// In vector type \p VT, return true if the element at index \p InputIdx
10985 /// falls on a different 128-bit lane than \p OutputIdx.
10986 static bool ShuffleCrosses128bitLane(MVT VT, unsigned InputIdx,
10987 unsigned OutputIdx) {
10988 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
10989 return InputIdx * EltSize / 128 != OutputIdx * EltSize / 128;
10992 /// Generate a PSHUFB if possible. Selects elements from \p V1 according to
10993 /// \p MaskVals. MaskVals[OutputIdx] = InputIdx specifies that we want to
10994 /// shuffle the element at InputIdx in V1 to OutputIdx in the result. If \p
10995 /// MaskVals refers to elements outside of \p V1 or is undef (-1), insert a
10997 static SDValue getPSHUFB(ArrayRef<int> MaskVals, SDValue V1, SDLoc &dl,
10998 SelectionDAG &DAG) {
10999 MVT VT = V1.getSimpleValueType();
11000 assert(VT.is128BitVector() || VT.is256BitVector());
11002 MVT EltVT = VT.getVectorElementType();
11003 unsigned EltSizeInBytes = EltVT.getSizeInBits() / 8;
11004 unsigned NumElts = VT.getVectorNumElements();
11006 SmallVector<SDValue, 32> PshufbMask;
11007 for (unsigned OutputIdx = 0; OutputIdx < NumElts; ++OutputIdx) {
11008 int InputIdx = MaskVals[OutputIdx];
11009 unsigned InputByteIdx;
11011 if (InputIdx < 0 || NumElts <= (unsigned)InputIdx)
11012 InputByteIdx = 0x80;
11014 // Cross lane is not allowed.
11015 if (ShuffleCrosses128bitLane(VT, InputIdx, OutputIdx))
11017 InputByteIdx = InputIdx * EltSizeInBytes;
11018 // Index is an byte offset within the 128-bit lane.
11019 InputByteIdx &= 0xf;
11022 for (unsigned j = 0; j < EltSizeInBytes; ++j) {
11023 PshufbMask.push_back(DAG.getConstant(InputByteIdx, MVT::i8));
11024 if (InputByteIdx != 0x80)
11029 MVT ShufVT = MVT::getVectorVT(MVT::i8, PshufbMask.size());
11031 V1 = DAG.getNode(ISD::BITCAST, dl, ShufVT, V1);
11032 return DAG.getNode(X86ISD::PSHUFB, dl, ShufVT, V1,
11033 DAG.getNode(ISD::BUILD_VECTOR, dl, ShufVT, PshufbMask));
11036 // v8i16 shuffles - Prefer shuffles in the following order:
11037 // 1. [all] pshuflw, pshufhw, optional move
11038 // 2. [ssse3] 1 x pshufb
11039 // 3. [ssse3] 2 x pshufb + 1 x por
11040 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
11042 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
11043 SelectionDAG &DAG) {
11044 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11045 SDValue V1 = SVOp->getOperand(0);
11046 SDValue V2 = SVOp->getOperand(1);
11048 SmallVector<int, 8> MaskVals;
11050 // Determine if more than 1 of the words in each of the low and high quadwords
11051 // of the result come from the same quadword of one of the two inputs. Undef
11052 // mask values count as coming from any quadword, for better codegen.
11054 // Lo/HiQuad[i] = j indicates how many words from the ith quad of the input
11055 // feeds this quad. For i, 0 and 1 refer to V1, 2 and 3 refer to V2.
11056 unsigned LoQuad[] = { 0, 0, 0, 0 };
11057 unsigned HiQuad[] = { 0, 0, 0, 0 };
11058 // Indices of quads used.
11059 std::bitset<4> InputQuads;
11060 for (unsigned i = 0; i < 8; ++i) {
11061 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
11062 int EltIdx = SVOp->getMaskElt(i);
11063 MaskVals.push_back(EltIdx);
11071 ++Quad[EltIdx / 4];
11072 InputQuads.set(EltIdx / 4);
11075 int BestLoQuad = -1;
11076 unsigned MaxQuad = 1;
11077 for (unsigned i = 0; i < 4; ++i) {
11078 if (LoQuad[i] > MaxQuad) {
11080 MaxQuad = LoQuad[i];
11084 int BestHiQuad = -1;
11086 for (unsigned i = 0; i < 4; ++i) {
11087 if (HiQuad[i] > MaxQuad) {
11089 MaxQuad = HiQuad[i];
11093 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
11094 // of the two input vectors, shuffle them into one input vector so only a
11095 // single pshufb instruction is necessary. If there are more than 2 input
11096 // quads, disable the next transformation since it does not help SSSE3.
11097 bool V1Used = InputQuads[0] || InputQuads[1];
11098 bool V2Used = InputQuads[2] || InputQuads[3];
11099 if (Subtarget->hasSSSE3()) {
11100 if (InputQuads.count() == 2 && V1Used && V2Used) {
11101 BestLoQuad = InputQuads[0] ? 0 : 1;
11102 BestHiQuad = InputQuads[2] ? 2 : 3;
11104 if (InputQuads.count() > 2) {
11110 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
11111 // the shuffle mask. If a quad is scored as -1, that means that it contains
11112 // words from all 4 input quadwords.
11114 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
11116 BestLoQuad < 0 ? 0 : BestLoQuad,
11117 BestHiQuad < 0 ? 1 : BestHiQuad
11119 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
11120 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
11121 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
11122 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
11124 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
11125 // source words for the shuffle, to aid later transformations.
11126 bool AllWordsInNewV = true;
11127 bool InOrder[2] = { true, true };
11128 for (unsigned i = 0; i != 8; ++i) {
11129 int idx = MaskVals[i];
11131 InOrder[i/4] = false;
11132 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
11134 AllWordsInNewV = false;
11138 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
11139 if (AllWordsInNewV) {
11140 for (int i = 0; i != 8; ++i) {
11141 int idx = MaskVals[i];
11144 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
11145 if ((idx != i) && idx < 4)
11147 if ((idx != i) && idx > 3)
11156 // If we've eliminated the use of V2, and the new mask is a pshuflw or
11157 // pshufhw, that's as cheap as it gets. Return the new shuffle.
11158 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
11159 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
11160 unsigned TargetMask = 0;
11161 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
11162 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
11163 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11164 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
11165 getShufflePSHUFLWImmediate(SVOp);
11166 V1 = NewV.getOperand(0);
11167 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
11171 // Promote splats to a larger type which usually leads to more efficient code.
11172 // FIXME: Is this true if pshufb is available?
11173 if (SVOp->isSplat())
11174 return PromoteSplat(SVOp, DAG);
11176 // If we have SSSE3, and all words of the result are from 1 input vector,
11177 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
11178 // is present, fall back to case 4.
11179 if (Subtarget->hasSSSE3()) {
11180 SmallVector<SDValue,16> pshufbMask;
11182 // If we have elements from both input vectors, set the high bit of the
11183 // shuffle mask element to zero out elements that come from V2 in the V1
11184 // mask, and elements that come from V1 in the V2 mask, so that the two
11185 // results can be OR'd together.
11186 bool TwoInputs = V1Used && V2Used;
11187 V1 = getPSHUFB(MaskVals, V1, dl, DAG);
11189 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11191 // Calculate the shuffle mask for the second input, shuffle it, and
11192 // OR it with the first shuffled input.
11193 CommuteVectorShuffleMask(MaskVals, 8);
11194 V2 = getPSHUFB(MaskVals, V2, dl, DAG);
11195 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11196 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11199 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
11200 // and update MaskVals with new element order.
11201 std::bitset<8> InOrder;
11202 if (BestLoQuad >= 0) {
11203 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
11204 for (int i = 0; i != 4; ++i) {
11205 int idx = MaskVals[i];
11208 } else if ((idx / 4) == BestLoQuad) {
11209 MaskV[i] = idx & 3;
11213 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11216 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11217 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11218 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
11219 NewV.getOperand(0),
11220 getShufflePSHUFLWImmediate(SVOp), DAG);
11224 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
11225 // and update MaskVals with the new element order.
11226 if (BestHiQuad >= 0) {
11227 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
11228 for (unsigned i = 4; i != 8; ++i) {
11229 int idx = MaskVals[i];
11232 } else if ((idx / 4) == BestHiQuad) {
11233 MaskV[i] = (idx & 3) + 4;
11237 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
11240 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSE2()) {
11241 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
11242 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
11243 NewV.getOperand(0),
11244 getShufflePSHUFHWImmediate(SVOp), DAG);
11248 // In case BestHi & BestLo were both -1, which means each quadword has a word
11249 // from each of the four input quadwords, calculate the InOrder bitvector now
11250 // before falling through to the insert/extract cleanup.
11251 if (BestLoQuad == -1 && BestHiQuad == -1) {
11253 for (int i = 0; i != 8; ++i)
11254 if (MaskVals[i] < 0 || MaskVals[i] == i)
11258 // The other elements are put in the right place using pextrw and pinsrw.
11259 for (unsigned i = 0; i != 8; ++i) {
11262 int EltIdx = MaskVals[i];
11265 SDValue ExtOp = (EltIdx < 8) ?
11266 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
11267 DAG.getIntPtrConstant(EltIdx)) :
11268 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
11269 DAG.getIntPtrConstant(EltIdx - 8));
11270 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
11271 DAG.getIntPtrConstant(i));
11276 /// \brief v16i16 shuffles
11278 /// FIXME: We only support generation of a single pshufb currently. We can
11279 /// generalize the other applicable cases from LowerVECTOR_SHUFFLEv8i16 as
11280 /// well (e.g 2 x pshufb + 1 x por).
11282 LowerVECTOR_SHUFFLEv16i16(SDValue Op, SelectionDAG &DAG) {
11283 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11284 SDValue V1 = SVOp->getOperand(0);
11285 SDValue V2 = SVOp->getOperand(1);
11288 if (V2.getOpcode() != ISD::UNDEF)
11291 SmallVector<int, 16> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11292 return getPSHUFB(MaskVals, V1, dl, DAG);
11295 // v16i8 shuffles - Prefer shuffles in the following order:
11296 // 1. [ssse3] 1 x pshufb
11297 // 2. [ssse3] 2 x pshufb + 1 x por
11298 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
11299 static SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
11300 const X86Subtarget* Subtarget,
11301 SelectionDAG &DAG) {
11302 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
11303 SDValue V1 = SVOp->getOperand(0);
11304 SDValue V2 = SVOp->getOperand(1);
11306 ArrayRef<int> MaskVals = SVOp->getMask();
11308 // Promote splats to a larger type which usually leads to more efficient code.
11309 // FIXME: Is this true if pshufb is available?
11310 if (SVOp->isSplat())
11311 return PromoteSplat(SVOp, DAG);
11313 // If we have SSSE3, case 1 is generated when all result bytes come from
11314 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
11315 // present, fall back to case 3.
11317 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
11318 if (Subtarget->hasSSSE3()) {
11319 SmallVector<SDValue,16> pshufbMask;
11321 // If all result elements are from one input vector, then only translate
11322 // undef mask values to 0x80 (zero out result) in the pshufb mask.
11324 // Otherwise, we have elements from both input vectors, and must zero out
11325 // elements that come from V2 in the first mask, and V1 in the second mask
11326 // so that we can OR them together.
11327 for (unsigned i = 0; i != 16; ++i) {
11328 int EltIdx = MaskVals[i];
11329 if (EltIdx < 0 || EltIdx >= 16)
11331 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11333 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
11334 DAG.getNode(ISD::BUILD_VECTOR, dl,
11335 MVT::v16i8, pshufbMask));
11337 // As PSHUFB will zero elements with negative indices, it's safe to ignore
11338 // the 2nd operand if it's undefined or zero.
11339 if (V2.getOpcode() == ISD::UNDEF ||
11340 ISD::isBuildVectorAllZeros(V2.getNode()))
11343 // Calculate the shuffle mask for the second input, shuffle it, and
11344 // OR it with the first shuffled input.
11345 pshufbMask.clear();
11346 for (unsigned i = 0; i != 16; ++i) {
11347 int EltIdx = MaskVals[i];
11348 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
11349 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
11351 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
11352 DAG.getNode(ISD::BUILD_VECTOR, dl,
11353 MVT::v16i8, pshufbMask));
11354 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
11357 // No SSSE3 - Calculate in place words and then fix all out of place words
11358 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
11359 // the 16 different words that comprise the two doublequadword input vectors.
11360 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
11361 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
11363 for (int i = 0; i != 8; ++i) {
11364 int Elt0 = MaskVals[i*2];
11365 int Elt1 = MaskVals[i*2+1];
11367 // This word of the result is all undef, skip it.
11368 if (Elt0 < 0 && Elt1 < 0)
11371 // This word of the result is already in the correct place, skip it.
11372 if ((Elt0 == i*2) && (Elt1 == i*2+1))
11375 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
11376 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
11379 // If Elt0 and Elt1 are defined, are consecutive, and can be load
11380 // using a single extract together, load it and store it.
11381 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
11382 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11383 DAG.getIntPtrConstant(Elt1 / 2));
11384 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11385 DAG.getIntPtrConstant(i));
11389 // If Elt1 is defined, extract it from the appropriate source. If the
11390 // source byte is not also odd, shift the extracted word left 8 bits
11391 // otherwise clear the bottom 8 bits if we need to do an or.
11393 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
11394 DAG.getIntPtrConstant(Elt1 / 2));
11395 if ((Elt1 & 1) == 0)
11396 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
11398 TLI.getShiftAmountTy(InsElt.getValueType())));
11399 else if (Elt0 >= 0)
11400 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
11401 DAG.getConstant(0xFF00, MVT::i16));
11403 // If Elt0 is defined, extract it from the appropriate source. If the
11404 // source byte is not also even, shift the extracted word right 8 bits. If
11405 // Elt1 was also defined, OR the extracted values together before
11406 // inserting them in the result.
11408 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
11409 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
11410 if ((Elt0 & 1) != 0)
11411 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
11413 TLI.getShiftAmountTy(InsElt0.getValueType())));
11414 else if (Elt1 >= 0)
11415 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
11416 DAG.getConstant(0x00FF, MVT::i16));
11417 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
11420 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
11421 DAG.getIntPtrConstant(i));
11423 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
11426 // v32i8 shuffles - Translate to VPSHUFB if possible.
11428 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
11429 const X86Subtarget *Subtarget,
11430 SelectionDAG &DAG) {
11431 MVT VT = SVOp->getSimpleValueType(0);
11432 SDValue V1 = SVOp->getOperand(0);
11433 SDValue V2 = SVOp->getOperand(1);
11435 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
11437 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11438 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
11439 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
11441 // VPSHUFB may be generated if
11442 // (1) one of input vector is undefined or zeroinitializer.
11443 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
11444 // And (2) the mask indexes don't cross the 128-bit lane.
11445 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
11446 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
11449 if (V1IsAllZero && !V2IsAllZero) {
11450 CommuteVectorShuffleMask(MaskVals, 32);
11453 return getPSHUFB(MaskVals, V1, dl, DAG);
11456 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
11457 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
11458 /// done when every pair / quad of shuffle mask elements point to elements in
11459 /// the right sequence. e.g.
11460 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
11462 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
11463 SelectionDAG &DAG) {
11464 MVT VT = SVOp->getSimpleValueType(0);
11466 unsigned NumElems = VT.getVectorNumElements();
11469 switch (VT.SimpleTy) {
11470 default: llvm_unreachable("Unexpected!");
11473 return SDValue(SVOp, 0);
11474 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
11475 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
11476 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
11477 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
11478 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
11479 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
11482 SmallVector<int, 8> MaskVec;
11483 for (unsigned i = 0; i != NumElems; i += Scale) {
11485 for (unsigned j = 0; j != Scale; ++j) {
11486 int EltIdx = SVOp->getMaskElt(i+j);
11490 StartIdx = (EltIdx / Scale);
11491 if (EltIdx != (int)(StartIdx*Scale + j))
11494 MaskVec.push_back(StartIdx);
11497 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
11498 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
11499 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
11502 /// getVZextMovL - Return a zero-extending vector move low node.
11504 static SDValue getVZextMovL(MVT VT, MVT OpVT,
11505 SDValue SrcOp, SelectionDAG &DAG,
11506 const X86Subtarget *Subtarget, SDLoc dl) {
11507 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
11508 LoadSDNode *LD = nullptr;
11509 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
11510 LD = dyn_cast<LoadSDNode>(SrcOp);
11512 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
11514 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
11515 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
11516 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11517 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
11518 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
11520 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
11521 return DAG.getNode(ISD::BITCAST, dl, VT,
11522 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11523 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
11525 SrcOp.getOperand(0)
11531 return DAG.getNode(ISD::BITCAST, dl, VT,
11532 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
11533 DAG.getNode(ISD::BITCAST, dl,
11537 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
11538 /// which could not be matched by any known target speficic shuffle
11540 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11542 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
11543 if (NewOp.getNode())
11546 MVT VT = SVOp->getSimpleValueType(0);
11548 unsigned NumElems = VT.getVectorNumElements();
11549 unsigned NumLaneElems = NumElems / 2;
11552 MVT EltVT = VT.getVectorElementType();
11553 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
11556 SmallVector<int, 16> Mask;
11557 for (unsigned l = 0; l < 2; ++l) {
11558 // Build a shuffle mask for the output, discovering on the fly which
11559 // input vectors to use as shuffle operands (recorded in InputUsed).
11560 // If building a suitable shuffle vector proves too hard, then bail
11561 // out with UseBuildVector set.
11562 bool UseBuildVector = false;
11563 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
11564 unsigned LaneStart = l * NumLaneElems;
11565 for (unsigned i = 0; i != NumLaneElems; ++i) {
11566 // The mask element. This indexes into the input.
11567 int Idx = SVOp->getMaskElt(i+LaneStart);
11569 // the mask element does not index into any input vector.
11570 Mask.push_back(-1);
11574 // The input vector this mask element indexes into.
11575 int Input = Idx / NumLaneElems;
11577 // Turn the index into an offset from the start of the input vector.
11578 Idx -= Input * NumLaneElems;
11580 // Find or create a shuffle vector operand to hold this input.
11582 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
11583 if (InputUsed[OpNo] == Input)
11584 // This input vector is already an operand.
11586 if (InputUsed[OpNo] < 0) {
11587 // Create a new operand for this input vector.
11588 InputUsed[OpNo] = Input;
11593 if (OpNo >= array_lengthof(InputUsed)) {
11594 // More than two input vectors used! Give up on trying to create a
11595 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
11596 UseBuildVector = true;
11600 // Add the mask index for the new shuffle vector.
11601 Mask.push_back(Idx + OpNo * NumLaneElems);
11604 if (UseBuildVector) {
11605 SmallVector<SDValue, 16> SVOps;
11606 for (unsigned i = 0; i != NumLaneElems; ++i) {
11607 // The mask element. This indexes into the input.
11608 int Idx = SVOp->getMaskElt(i+LaneStart);
11610 SVOps.push_back(DAG.getUNDEF(EltVT));
11614 // The input vector this mask element indexes into.
11615 int Input = Idx / NumElems;
11617 // Turn the index into an offset from the start of the input vector.
11618 Idx -= Input * NumElems;
11620 // Extract the vector element by hand.
11621 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
11622 SVOp->getOperand(Input),
11623 DAG.getIntPtrConstant(Idx)));
11626 // Construct the output using a BUILD_VECTOR.
11627 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, SVOps);
11628 } else if (InputUsed[0] < 0) {
11629 // No input vectors were used! The result is undefined.
11630 Output[l] = DAG.getUNDEF(NVT);
11632 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
11633 (InputUsed[0] % 2) * NumLaneElems,
11635 // If only one input was used, use an undefined vector for the other.
11636 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
11637 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
11638 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
11639 // At least one input vector was used. Create a new shuffle vector.
11640 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
11646 // Concatenate the result back
11647 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
11650 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
11651 /// 4 elements, and match them with several different shuffle types.
11653 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
11654 SDValue V1 = SVOp->getOperand(0);
11655 SDValue V2 = SVOp->getOperand(1);
11657 MVT VT = SVOp->getSimpleValueType(0);
11659 assert(VT.is128BitVector() && "Unsupported vector size");
11661 std::pair<int, int> Locs[4];
11662 int Mask1[] = { -1, -1, -1, -1 };
11663 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
11665 unsigned NumHi = 0;
11666 unsigned NumLo = 0;
11667 for (unsigned i = 0; i != 4; ++i) {
11668 int Idx = PermMask[i];
11670 Locs[i] = std::make_pair(-1, -1);
11672 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
11674 Locs[i] = std::make_pair(0, NumLo);
11675 Mask1[NumLo] = Idx;
11678 Locs[i] = std::make_pair(1, NumHi);
11680 Mask1[2+NumHi] = Idx;
11686 if (NumLo <= 2 && NumHi <= 2) {
11687 // If no more than two elements come from either vector. This can be
11688 // implemented with two shuffles. First shuffle gather the elements.
11689 // The second shuffle, which takes the first shuffle as both of its
11690 // vector operands, put the elements into the right order.
11691 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11693 int Mask2[] = { -1, -1, -1, -1 };
11695 for (unsigned i = 0; i != 4; ++i)
11696 if (Locs[i].first != -1) {
11697 unsigned Idx = (i < 2) ? 0 : 4;
11698 Idx += Locs[i].first * 2 + Locs[i].second;
11702 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
11705 if (NumLo == 3 || NumHi == 3) {
11706 // Otherwise, we must have three elements from one vector, call it X, and
11707 // one element from the other, call it Y. First, use a shufps to build an
11708 // intermediate vector with the one element from Y and the element from X
11709 // that will be in the same half in the final destination (the indexes don't
11710 // matter). Then, use a shufps to build the final vector, taking the half
11711 // containing the element from Y from the intermediate, and the other half
11714 // Normalize it so the 3 elements come from V1.
11715 CommuteVectorShuffleMask(PermMask, 4);
11719 // Find the element from V2.
11721 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
11722 int Val = PermMask[HiIndex];
11729 Mask1[0] = PermMask[HiIndex];
11731 Mask1[2] = PermMask[HiIndex^1];
11733 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11735 if (HiIndex >= 2) {
11736 Mask1[0] = PermMask[0];
11737 Mask1[1] = PermMask[1];
11738 Mask1[2] = HiIndex & 1 ? 6 : 4;
11739 Mask1[3] = HiIndex & 1 ? 4 : 6;
11740 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
11743 Mask1[0] = HiIndex & 1 ? 2 : 0;
11744 Mask1[1] = HiIndex & 1 ? 0 : 2;
11745 Mask1[2] = PermMask[2];
11746 Mask1[3] = PermMask[3];
11751 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
11754 // Break it into (shuffle shuffle_hi, shuffle_lo).
11755 int LoMask[] = { -1, -1, -1, -1 };
11756 int HiMask[] = { -1, -1, -1, -1 };
11758 int *MaskPtr = LoMask;
11759 unsigned MaskIdx = 0;
11760 unsigned LoIdx = 0;
11761 unsigned HiIdx = 2;
11762 for (unsigned i = 0; i != 4; ++i) {
11769 int Idx = PermMask[i];
11771 Locs[i] = std::make_pair(-1, -1);
11772 } else if (Idx < 4) {
11773 Locs[i] = std::make_pair(MaskIdx, LoIdx);
11774 MaskPtr[LoIdx] = Idx;
11777 Locs[i] = std::make_pair(MaskIdx, HiIdx);
11778 MaskPtr[HiIdx] = Idx;
11783 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
11784 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
11785 int MaskOps[] = { -1, -1, -1, -1 };
11786 for (unsigned i = 0; i != 4; ++i)
11787 if (Locs[i].first != -1)
11788 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
11789 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
11792 static bool MayFoldVectorLoad(SDValue V) {
11793 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
11794 V = V.getOperand(0);
11796 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
11797 V = V.getOperand(0);
11798 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
11799 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
11800 // BUILD_VECTOR (load), undef
11801 V = V.getOperand(0);
11803 return MayFoldLoad(V);
11807 SDValue getMOVDDup(SDValue &Op, SDLoc &dl, SDValue V1, SelectionDAG &DAG) {
11808 MVT VT = Op.getSimpleValueType();
11810 // Canonizalize to v2f64.
11811 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
11812 return DAG.getNode(ISD::BITCAST, dl, VT,
11813 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
11818 SDValue getMOVLowToHigh(SDValue &Op, SDLoc &dl, SelectionDAG &DAG,
11820 SDValue V1 = Op.getOperand(0);
11821 SDValue V2 = Op.getOperand(1);
11822 MVT VT = Op.getSimpleValueType();
11824 assert(VT != MVT::v2i64 && "unsupported shuffle type");
11826 if (HasSSE2 && VT == MVT::v2f64)
11827 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
11829 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
11830 return DAG.getNode(ISD::BITCAST, dl, VT,
11831 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
11832 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
11833 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
11837 SDValue getMOVHighToLow(SDValue &Op, SDLoc &dl, SelectionDAG &DAG) {
11838 SDValue V1 = Op.getOperand(0);
11839 SDValue V2 = Op.getOperand(1);
11840 MVT VT = Op.getSimpleValueType();
11842 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
11843 "unsupported shuffle type");
11845 if (V2.getOpcode() == ISD::UNDEF)
11849 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
11853 SDValue getMOVLP(SDValue &Op, SDLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
11854 SDValue V1 = Op.getOperand(0);
11855 SDValue V2 = Op.getOperand(1);
11856 MVT VT = Op.getSimpleValueType();
11857 unsigned NumElems = VT.getVectorNumElements();
11859 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
11860 // operand of these instructions is only memory, so check if there's a
11861 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
11863 bool CanFoldLoad = false;
11865 // Trivial case, when V2 comes from a load.
11866 if (MayFoldVectorLoad(V2))
11867 CanFoldLoad = true;
11869 // When V1 is a load, it can be folded later into a store in isel, example:
11870 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
11872 // (MOVLPSmr addr:$src1, VR128:$src2)
11873 // So, recognize this potential and also use MOVLPS or MOVLPD
11874 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
11875 CanFoldLoad = true;
11877 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11879 if (HasSSE2 && NumElems == 2)
11880 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
11883 // If we don't care about the second element, proceed to use movss.
11884 if (SVOp->getMaskElt(1) != -1)
11885 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
11888 // movl and movlp will both match v2i64, but v2i64 is never matched by
11889 // movl earlier because we make it strict to avoid messing with the movlp load
11890 // folding logic (see the code above getMOVLP call). Match it here then,
11891 // this is horrible, but will stay like this until we move all shuffle
11892 // matching to x86 specific nodes. Note that for the 1st condition all
11893 // types are matched with movsd.
11895 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
11896 // as to remove this logic from here, as much as possible
11897 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
11898 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
11899 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
11902 assert(VT != MVT::v4i32 && "unsupported shuffle type");
11904 // Invert the operand order and use SHUFPS to match it.
11905 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
11906 getShuffleSHUFImmediate(SVOp), DAG);
11909 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
11910 SelectionDAG &DAG) {
11912 MVT VT = Load->getSimpleValueType(0);
11913 MVT EVT = VT.getVectorElementType();
11914 SDValue Addr = Load->getOperand(1);
11915 SDValue NewAddr = DAG.getNode(
11916 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
11917 DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));
11920 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
11921 DAG.getMachineFunction().getMachineMemOperand(
11922 Load->getMemOperand(), 0, EVT.getStoreSize()));
11926 // It is only safe to call this function if isINSERTPSMask is true for
11927 // this shufflevector mask.
11928 static SDValue getINSERTPS(ShuffleVectorSDNode *SVOp, SDLoc &dl,
11929 SelectionDAG &DAG) {
11930 // Generate an insertps instruction when inserting an f32 from memory onto a
11931 // v4f32 or when copying a member from one v4f32 to another.
11932 // We also use it for transferring i32 from one register to another,
11933 // since it simply copies the same bits.
11934 // If we're transferring an i32 from memory to a specific element in a
11935 // register, we output a generic DAG that will match the PINSRD
11937 MVT VT = SVOp->getSimpleValueType(0);
11938 MVT EVT = VT.getVectorElementType();
11939 SDValue V1 = SVOp->getOperand(0);
11940 SDValue V2 = SVOp->getOperand(1);
11941 auto Mask = SVOp->getMask();
11942 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
11943 "unsupported vector type for insertps/pinsrd");
11945 auto FromV1Predicate = [](const int &i) { return i < 4 && i > -1; };
11946 auto FromV2Predicate = [](const int &i) { return i >= 4; };
11947 int FromV1 = std::count_if(Mask.begin(), Mask.end(), FromV1Predicate);
11951 unsigned DestIndex;
11955 DestIndex = std::find_if(Mask.begin(), Mask.end(), FromV1Predicate) -
11958 // If we have 1 element from each vector, we have to check if we're
11959 // changing V1's element's place. If so, we're done. Otherwise, we
11960 // should assume we're changing V2's element's place and behave
11962 int FromV2 = std::count_if(Mask.begin(), Mask.end(), FromV2Predicate);
11963 assert(DestIndex <= INT32_MAX && "truncated destination index");
11964 if (FromV1 == FromV2 &&
11965 static_cast<int>(DestIndex) == Mask[DestIndex] % 4) {
11969 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11972 assert(std::count_if(Mask.begin(), Mask.end(), FromV2Predicate) == 1 &&
11973 "More than one element from V1 and from V2, or no elements from one "
11974 "of the vectors. This case should not have returned true from "
11979 std::find_if(Mask.begin(), Mask.end(), FromV2Predicate) - Mask.begin();
11982 // Get an index into the source vector in the range [0,4) (the mask is
11983 // in the range [0,8) because it can address V1 and V2)
11984 unsigned SrcIndex = Mask[DestIndex] % 4;
11985 if (MayFoldLoad(From)) {
11986 // Trivial case, when From comes from a load and is only used by the
11987 // shuffle. Make it use insertps from the vector that we need from that
11990 NarrowVectorLoadToElement(cast<LoadSDNode>(From), SrcIndex, DAG);
11991 if (!NewLoad.getNode())
11994 if (EVT == MVT::f32) {
11995 // Create this as a scalar to vector to match the instruction pattern.
11996 SDValue LoadScalarToVector =
11997 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, NewLoad);
11998 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4);
11999 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, LoadScalarToVector,
12001 } else { // EVT == MVT::i32
12002 // If we're getting an i32 from memory, use an INSERT_VECTOR_ELT
12003 // instruction, to match the PINSRD instruction, which loads an i32 to a
12004 // certain vector element.
12005 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, To, NewLoad,
12006 DAG.getConstant(DestIndex, MVT::i32));
12010 // Vector-element-to-vector
12011 SDValue InsertpsMask = DAG.getIntPtrConstant(DestIndex << 4 | SrcIndex << 6);
12012 return DAG.getNode(X86ISD::INSERTPS, dl, VT, To, From, InsertpsMask);
12015 // Reduce a vector shuffle to zext.
12016 static SDValue LowerVectorIntExtend(SDValue Op, const X86Subtarget *Subtarget,
12017 SelectionDAG &DAG) {
12018 // PMOVZX is only available from SSE41.
12019 if (!Subtarget->hasSSE41())
12022 MVT VT = Op.getSimpleValueType();
12024 // Only AVX2 support 256-bit vector integer extending.
12025 if (!Subtarget->hasInt256() && VT.is256BitVector())
12028 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12030 SDValue V1 = Op.getOperand(0);
12031 SDValue V2 = Op.getOperand(1);
12032 unsigned NumElems = VT.getVectorNumElements();
12034 // Extending is an unary operation and the element type of the source vector
12035 // won't be equal to or larger than i64.
12036 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
12037 VT.getVectorElementType() == MVT::i64)
12040 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
12041 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
12042 while ((1U << Shift) < NumElems) {
12043 if (SVOp->getMaskElt(1U << Shift) == 1)
12046 // The maximal ratio is 8, i.e. from i8 to i64.
12051 // Check the shuffle mask.
12052 unsigned Mask = (1U << Shift) - 1;
12053 for (unsigned i = 0; i != NumElems; ++i) {
12054 int EltIdx = SVOp->getMaskElt(i);
12055 if ((i & Mask) != 0 && EltIdx != -1)
12057 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
12061 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
12062 MVT NeVT = MVT::getIntegerVT(NBits);
12063 MVT NVT = MVT::getVectorVT(NeVT, NumElems >> Shift);
12065 if (!DAG.getTargetLoweringInfo().isTypeLegal(NVT))
12068 return DAG.getNode(ISD::BITCAST, DL, VT,
12069 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
12072 static SDValue NormalizeVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
12073 SelectionDAG &DAG) {
12074 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12075 MVT VT = Op.getSimpleValueType();
12077 SDValue V1 = Op.getOperand(0);
12078 SDValue V2 = Op.getOperand(1);
12080 if (isZeroShuffle(SVOp))
12081 return getZeroVector(VT, Subtarget, DAG, dl);
12083 // Handle splat operations
12084 if (SVOp->isSplat()) {
12085 // Use vbroadcast whenever the splat comes from a foldable load
12086 SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG);
12087 if (Broadcast.getNode())
12091 // Check integer expanding shuffles.
12092 SDValue NewOp = LowerVectorIntExtend(Op, Subtarget, DAG);
12093 if (NewOp.getNode())
12096 // If the shuffle can be profitably rewritten as a narrower shuffle, then
12098 if (VT == MVT::v8i16 || VT == MVT::v16i8 || VT == MVT::v16i16 ||
12099 VT == MVT::v32i8) {
12100 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12101 if (NewOp.getNode())
12102 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
12103 } else if (VT.is128BitVector() && Subtarget->hasSSE2()) {
12104 // FIXME: Figure out a cleaner way to do this.
12105 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
12106 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12107 if (NewOp.getNode()) {
12108 MVT NewVT = NewOp.getSimpleValueType();
12109 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
12110 NewVT, true, false))
12111 return getVZextMovL(VT, NewVT, NewOp.getOperand(0), DAG, Subtarget,
12114 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
12115 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
12116 if (NewOp.getNode()) {
12117 MVT NewVT = NewOp.getSimpleValueType();
12118 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
12119 return getVZextMovL(VT, NewVT, NewOp.getOperand(1), DAG, Subtarget,
12128 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
12129 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
12130 SDValue V1 = Op.getOperand(0);
12131 SDValue V2 = Op.getOperand(1);
12132 MVT VT = Op.getSimpleValueType();
12134 unsigned NumElems = VT.getVectorNumElements();
12135 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
12136 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
12137 bool V1IsSplat = false;
12138 bool V2IsSplat = false;
12139 bool HasSSE2 = Subtarget->hasSSE2();
12140 bool HasFp256 = Subtarget->hasFp256();
12141 bool HasInt256 = Subtarget->hasInt256();
12142 MachineFunction &MF = DAG.getMachineFunction();
12143 bool OptForSize = MF.getFunction()->getAttributes().
12144 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
12146 // Check if we should use the experimental vector shuffle lowering. If so,
12147 // delegate completely to that code path.
12148 if (ExperimentalVectorShuffleLowering)
12149 return lowerVectorShuffle(Op, Subtarget, DAG);
12151 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
12153 if (V1IsUndef && V2IsUndef)
12154 return DAG.getUNDEF(VT);
12156 // When we create a shuffle node we put the UNDEF node to second operand,
12157 // but in some cases the first operand may be transformed to UNDEF.
12158 // In this case we should just commute the node.
12160 return DAG.getCommutedVectorShuffle(*SVOp);
12162 // Vector shuffle lowering takes 3 steps:
12164 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
12165 // narrowing and commutation of operands should be handled.
12166 // 2) Matching of shuffles with known shuffle masks to x86 target specific
12168 // 3) Rewriting of unmatched masks into new generic shuffle operations,
12169 // so the shuffle can be broken into other shuffles and the legalizer can
12170 // try the lowering again.
12172 // The general idea is that no vector_shuffle operation should be left to
12173 // be matched during isel, all of them must be converted to a target specific
12176 // Normalize the input vectors. Here splats, zeroed vectors, profitable
12177 // narrowing and commutation of operands should be handled. The actual code
12178 // doesn't include all of those, work in progress...
12179 SDValue NewOp = NormalizeVectorShuffle(Op, Subtarget, DAG);
12180 if (NewOp.getNode())
12183 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
12185 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
12186 // unpckh_undef). Only use pshufd if speed is more important than size.
12187 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12188 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12189 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12190 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12192 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
12193 V2IsUndef && MayFoldVectorLoad(V1))
12194 return getMOVDDup(Op, dl, V1, DAG);
12196 if (isMOVHLPS_v_undef_Mask(M, VT))
12197 return getMOVHighToLow(Op, dl, DAG);
12199 // Use to match splats
12200 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
12201 (VT == MVT::v2f64 || VT == MVT::v2i64))
12202 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12204 if (isPSHUFDMask(M, VT)) {
12205 // The actual implementation will match the mask in the if above and then
12206 // during isel it can match several different instructions, not only pshufd
12207 // as its name says, sad but true, emulate the behavior for now...
12208 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
12209 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
12211 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
12213 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
12214 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
12216 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
12217 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1, TargetMask,
12220 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
12224 if (isPALIGNRMask(M, VT, Subtarget))
12225 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
12226 getShufflePALIGNRImmediate(SVOp),
12229 if (isVALIGNMask(M, VT, Subtarget))
12230 return getTargetShuffleNode(X86ISD::VALIGN, dl, VT, V1, V2,
12231 getShuffleVALIGNImmediate(SVOp),
12234 // Check if this can be converted into a logical shift.
12235 bool isLeft = false;
12236 unsigned ShAmt = 0;
12238 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
12239 if (isShift && ShVal.hasOneUse()) {
12240 // If the shifted value has multiple uses, it may be cheaper to use
12241 // v_set0 + movlhps or movhlps, etc.
12242 MVT EltVT = VT.getVectorElementType();
12243 ShAmt *= EltVT.getSizeInBits();
12244 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12247 if (isMOVLMask(M, VT)) {
12248 if (ISD::isBuildVectorAllZeros(V1.getNode()))
12249 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
12250 if (!isMOVLPMask(M, VT)) {
12251 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
12252 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
12254 if (VT == MVT::v4i32 || VT == MVT::v4f32)
12255 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
12259 // FIXME: fold these into legal mask.
12260 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
12261 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
12263 if (isMOVHLPSMask(M, VT))
12264 return getMOVHighToLow(Op, dl, DAG);
12266 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
12267 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
12269 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
12270 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
12272 if (isMOVLPMask(M, VT))
12273 return getMOVLP(Op, dl, DAG, HasSSE2);
12275 if (ShouldXformToMOVHLPS(M, VT) ||
12276 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
12277 return DAG.getCommutedVectorShuffle(*SVOp);
12280 // No better options. Use a vshldq / vsrldq.
12281 MVT EltVT = VT.getVectorElementType();
12282 ShAmt *= EltVT.getSizeInBits();
12283 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
12286 bool Commuted = false;
12287 // FIXME: This should also accept a bitcast of a splat? Be careful, not
12288 // 1,1,1,1 -> v8i16 though.
12289 BitVector UndefElements;
12290 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V1.getNode()))
12291 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12293 if (auto *BVOp = dyn_cast<BuildVectorSDNode>(V2.getNode()))
12294 if (BVOp->getConstantSplatNode(&UndefElements) && UndefElements.none())
12297 // Canonicalize the splat or undef, if present, to be on the RHS.
12298 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
12299 CommuteVectorShuffleMask(M, NumElems);
12301 std::swap(V1IsSplat, V2IsSplat);
12305 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
12306 // Shuffling low element of v1 into undef, just return v1.
12309 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
12310 // the instruction selector will not match, so get a canonical MOVL with
12311 // swapped operands to undo the commute.
12312 return getMOVL(DAG, dl, VT, V2, V1);
12315 if (isUNPCKLMask(M, VT, HasInt256))
12316 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12318 if (isUNPCKHMask(M, VT, HasInt256))
12319 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12322 // Normalize mask so all entries that point to V2 points to its first
12323 // element then try to match unpck{h|l} again. If match, return a
12324 // new vector_shuffle with the corrected mask.p
12325 SmallVector<int, 8> NewMask(M.begin(), M.end());
12326 NormalizeMask(NewMask, NumElems);
12327 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
12328 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12329 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
12330 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12334 // Commute is back and try unpck* again.
12335 // FIXME: this seems wrong.
12336 CommuteVectorShuffleMask(M, NumElems);
12338 std::swap(V1IsSplat, V2IsSplat);
12340 if (isUNPCKLMask(M, VT, HasInt256))
12341 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
12343 if (isUNPCKHMask(M, VT, HasInt256))
12344 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
12347 // Normalize the node to match x86 shuffle ops if needed
12348 if (!V2IsUndef && (isSHUFPMask(M, VT, /* Commuted */ true)))
12349 return DAG.getCommutedVectorShuffle(*SVOp);
12351 // The checks below are all present in isShuffleMaskLegal, but they are
12352 // inlined here right now to enable us to directly emit target specific
12353 // nodes, and remove one by one until they don't return Op anymore.
12355 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
12356 SVOp->getSplatIndex() == 0 && V2IsUndef) {
12357 if (VT == MVT::v2f64 || VT == MVT::v2i64)
12358 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12361 if (isPSHUFHWMask(M, VT, HasInt256))
12362 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
12363 getShufflePSHUFHWImmediate(SVOp),
12366 if (isPSHUFLWMask(M, VT, HasInt256))
12367 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
12368 getShufflePSHUFLWImmediate(SVOp),
12371 unsigned MaskValue;
12372 if (isBlendMask(M, VT, Subtarget->hasSSE41(), Subtarget->hasInt256(),
12374 return LowerVECTOR_SHUFFLEtoBlend(SVOp, MaskValue, Subtarget, DAG);
12376 if (isSHUFPMask(M, VT))
12377 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
12378 getShuffleSHUFImmediate(SVOp), DAG);
12380 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
12381 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
12382 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
12383 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
12385 //===--------------------------------------------------------------------===//
12386 // Generate target specific nodes for 128 or 256-bit shuffles only
12387 // supported in the AVX instruction set.
12390 // Handle VMOVDDUPY permutations
12391 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
12392 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
12394 // Handle VPERMILPS/D* permutations
12395 if (isVPERMILPMask(M, VT)) {
12396 if ((HasInt256 && VT == MVT::v8i32) || VT == MVT::v16i32)
12397 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
12398 getShuffleSHUFImmediate(SVOp), DAG);
12399 return getTargetShuffleNode(X86ISD::VPERMILPI, dl, VT, V1,
12400 getShuffleSHUFImmediate(SVOp), DAG);
12404 if (VT.is512BitVector() && isINSERT64x4Mask(M, VT, &Idx))
12405 return Insert256BitVector(V1, Extract256BitVector(V2, 0, DAG, dl),
12406 Idx*(NumElems/2), DAG, dl);
12408 // Handle VPERM2F128/VPERM2I128 permutations
12409 if (isVPERM2X128Mask(M, VT, HasFp256))
12410 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
12411 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
12413 if (Subtarget->hasSSE41() && isINSERTPSMask(M, VT))
12414 return getINSERTPS(SVOp, dl, DAG);
12417 if (V2IsUndef && HasInt256 && isPermImmMask(M, VT, Imm8))
12418 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1, Imm8, DAG);
12420 if ((V2IsUndef && HasInt256 && VT.is256BitVector() && NumElems == 8) ||
12421 VT.is512BitVector()) {
12422 MVT MaskEltVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
12423 MVT MaskVectorVT = MVT::getVectorVT(MaskEltVT, NumElems);
12424 SmallVector<SDValue, 16> permclMask;
12425 for (unsigned i = 0; i != NumElems; ++i) {
12426 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MaskEltVT));
12429 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVectorVT, permclMask);
12431 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
12432 return DAG.getNode(X86ISD::VPERMV, dl, VT,
12433 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
12434 return DAG.getNode(X86ISD::VPERMV3, dl, VT, V1,
12435 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V2);
12438 //===--------------------------------------------------------------------===//
12439 // Since no target specific shuffle was selected for this generic one,
12440 // lower it into other known shuffles. FIXME: this isn't true yet, but
12441 // this is the plan.
12444 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
12445 if (VT == MVT::v8i16) {
12446 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
12447 if (NewOp.getNode())
12451 if (VT == MVT::v16i16 && Subtarget->hasInt256()) {
12452 SDValue NewOp = LowerVECTOR_SHUFFLEv16i16(Op, DAG);
12453 if (NewOp.getNode())
12457 if (VT == MVT::v16i8) {
12458 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, Subtarget, DAG);
12459 if (NewOp.getNode())
12463 if (VT == MVT::v32i8) {
12464 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
12465 if (NewOp.getNode())
12469 // Handle all 128-bit wide vectors with 4 elements, and match them with
12470 // several different shuffle types.
12471 if (NumElems == 4 && VT.is128BitVector())
12472 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
12474 // Handle general 256-bit shuffles
12475 if (VT.is256BitVector())
12476 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
12481 // This function assumes its argument is a BUILD_VECTOR of constants or
12482 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
12484 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
12485 unsigned &MaskValue) {
12487 unsigned NumElems = BuildVector->getNumOperands();
12488 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
12489 unsigned NumLanes = (NumElems - 1) / 8 + 1;
12490 unsigned NumElemsInLane = NumElems / NumLanes;
12492 // Blend for v16i16 should be symetric for the both lanes.
12493 for (unsigned i = 0; i < NumElemsInLane; ++i) {
12494 SDValue EltCond = BuildVector->getOperand(i);
12495 SDValue SndLaneEltCond =
12496 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
12498 int Lane1Cond = -1, Lane2Cond = -1;
12499 if (isa<ConstantSDNode>(EltCond))
12500 Lane1Cond = !isZero(EltCond);
12501 if (isa<ConstantSDNode>(SndLaneEltCond))
12502 Lane2Cond = !isZero(SndLaneEltCond);
12504 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
12505 // Lane1Cond != 0, means we want the first argument.
12506 // Lane1Cond == 0, means we want the second argument.
12507 // The encoding of this argument is 0 for the first argument, 1
12508 // for the second. Therefore, invert the condition.
12509 MaskValue |= !Lane1Cond << i;
12510 else if (Lane1Cond < 0)
12511 MaskValue |= !Lane2Cond << i;
12518 /// \brief Try to lower a VSELECT instruction to an immediate-controlled blend
12520 static SDValue lowerVSELECTtoBLENDI(SDValue Op, const X86Subtarget *Subtarget,
12521 SelectionDAG &DAG) {
12522 SDValue Cond = Op.getOperand(0);
12523 SDValue LHS = Op.getOperand(1);
12524 SDValue RHS = Op.getOperand(2);
12526 MVT VT = Op.getSimpleValueType();
12527 MVT EltVT = VT.getVectorElementType();
12528 unsigned NumElems = VT.getVectorNumElements();
12530 // There is no blend with immediate in AVX-512.
12531 if (VT.is512BitVector())
12534 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
12536 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
12539 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
12542 // Check the mask for BLEND and build the value.
12543 unsigned MaskValue = 0;
12544 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
12547 // Convert i32 vectors to floating point if it is not AVX2.
12548 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
12550 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
12551 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
12553 LHS = DAG.getNode(ISD::BITCAST, dl, VT, LHS);
12554 RHS = DAG.getNode(ISD::BITCAST, dl, VT, RHS);
12557 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, LHS, RHS,
12558 DAG.getConstant(MaskValue, MVT::i32));
12559 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
12562 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
12563 // A vselect where all conditions and data are constants can be optimized into
12564 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
12565 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
12566 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
12567 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
12570 SDValue BlendOp = lowerVSELECTtoBLENDI(Op, Subtarget, DAG);
12571 if (BlendOp.getNode())
12574 // Some types for vselect were previously set to Expand, not Legal or
12575 // Custom. Return an empty SDValue so we fall-through to Expand, after
12576 // the Custom lowering phase.
12577 MVT VT = Op.getSimpleValueType();
12578 switch (VT.SimpleTy) {
12583 if (Subtarget->hasBWI() && Subtarget->hasVLX())
12588 // We couldn't create a "Blend with immediate" node.
12589 // This node should still be legal, but we'll have to emit a blendv*
12594 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
12595 MVT VT = Op.getSimpleValueType();
12598 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
12601 if (VT.getSizeInBits() == 8) {
12602 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
12603 Op.getOperand(0), Op.getOperand(1));
12604 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12605 DAG.getValueType(VT));
12606 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12609 if (VT.getSizeInBits() == 16) {
12610 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12611 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
12613 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12614 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12615 DAG.getNode(ISD::BITCAST, dl,
12618 Op.getOperand(1)));
12619 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
12620 Op.getOperand(0), Op.getOperand(1));
12621 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
12622 DAG.getValueType(VT));
12623 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12626 if (VT == MVT::f32) {
12627 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
12628 // the result back to FR32 register. It's only worth matching if the
12629 // result has a single use which is a store or a bitcast to i32. And in
12630 // the case of a store, it's not worth it if the index is a constant 0,
12631 // because a MOVSSmr can be used instead, which is smaller and faster.
12632 if (!Op.hasOneUse())
12634 SDNode *User = *Op.getNode()->use_begin();
12635 if ((User->getOpcode() != ISD::STORE ||
12636 (isa<ConstantSDNode>(Op.getOperand(1)) &&
12637 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
12638 (User->getOpcode() != ISD::BITCAST ||
12639 User->getValueType(0) != MVT::i32))
12641 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12642 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
12645 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
12648 if (VT == MVT::i32 || VT == MVT::i64) {
12649 // ExtractPS/pextrq works with constant index.
12650 if (isa<ConstantSDNode>(Op.getOperand(1)))
12656 /// Extract one bit from mask vector, like v16i1 or v8i1.
12657 /// AVX-512 feature.
12659 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
12660 SDValue Vec = Op.getOperand(0);
12662 MVT VecVT = Vec.getSimpleValueType();
12663 SDValue Idx = Op.getOperand(1);
12664 MVT EltVT = Op.getSimpleValueType();
12666 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
12668 // variable index can't be handled in mask registers,
12669 // extend vector to VR512
12670 if (!isa<ConstantSDNode>(Idx)) {
12671 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12672 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
12673 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
12674 ExtVT.getVectorElementType(), Ext, Idx);
12675 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
12678 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12679 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12680 unsigned MaxSift = rc->getSize()*8 - 1;
12681 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
12682 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12683 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
12684 DAG.getConstant(MaxSift, MVT::i8));
12685 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
12686 DAG.getIntPtrConstant(0));
12690 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
12691 SelectionDAG &DAG) const {
12693 SDValue Vec = Op.getOperand(0);
12694 MVT VecVT = Vec.getSimpleValueType();
12695 SDValue Idx = Op.getOperand(1);
12697 if (Op.getSimpleValueType() == MVT::i1)
12698 return ExtractBitFromMaskVector(Op, DAG);
12700 if (!isa<ConstantSDNode>(Idx)) {
12701 if (VecVT.is512BitVector() ||
12702 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
12703 VecVT.getVectorElementType().getSizeInBits() == 32)) {
12706 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
12707 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
12708 MaskEltVT.getSizeInBits());
12710 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
12711 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
12712 getZeroVector(MaskVT, Subtarget, DAG, dl),
12713 Idx, DAG.getConstant(0, getPointerTy()));
12714 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
12715 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
12716 Perm, DAG.getConstant(0, getPointerTy()));
12721 // If this is a 256-bit vector result, first extract the 128-bit vector and
12722 // then extract the element from the 128-bit vector.
12723 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
12725 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12726 // Get the 128-bit vector.
12727 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
12728 MVT EltVT = VecVT.getVectorElementType();
12730 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
12732 //if (IdxVal >= NumElems/2)
12733 // IdxVal -= NumElems/2;
12734 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
12735 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
12736 DAG.getConstant(IdxVal, MVT::i32));
12739 assert(VecVT.is128BitVector() && "Unexpected vector length");
12741 if (Subtarget->hasSSE41()) {
12742 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
12747 MVT VT = Op.getSimpleValueType();
12748 // TODO: handle v16i8.
12749 if (VT.getSizeInBits() == 16) {
12750 SDValue Vec = Op.getOperand(0);
12751 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12753 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
12754 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
12755 DAG.getNode(ISD::BITCAST, dl,
12757 Op.getOperand(1)));
12758 // Transform it so it match pextrw which produces a 32-bit result.
12759 MVT EltVT = MVT::i32;
12760 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
12761 Op.getOperand(0), Op.getOperand(1));
12762 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
12763 DAG.getValueType(VT));
12764 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
12767 if (VT.getSizeInBits() == 32) {
12768 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12772 // SHUFPS the element to the lowest double word, then movss.
12773 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
12774 MVT VVT = Op.getOperand(0).getSimpleValueType();
12775 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12776 DAG.getUNDEF(VVT), Mask);
12777 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12778 DAG.getIntPtrConstant(0));
12781 if (VT.getSizeInBits() == 64) {
12782 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
12783 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
12784 // to match extract_elt for f64.
12785 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
12789 // UNPCKHPD the element to the lowest double word, then movsd.
12790 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
12791 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
12792 int Mask[2] = { 1, -1 };
12793 MVT VVT = Op.getOperand(0).getSimpleValueType();
12794 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
12795 DAG.getUNDEF(VVT), Mask);
12796 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
12797 DAG.getIntPtrConstant(0));
12803 /// Insert one bit to mask vector, like v16i1 or v8i1.
12804 /// AVX-512 feature.
12806 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
12808 SDValue Vec = Op.getOperand(0);
12809 SDValue Elt = Op.getOperand(1);
12810 SDValue Idx = Op.getOperand(2);
12811 MVT VecVT = Vec.getSimpleValueType();
12813 if (!isa<ConstantSDNode>(Idx)) {
12814 // Non constant index. Extend source and destination,
12815 // insert element and then truncate the result.
12816 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
12817 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
12818 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
12819 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
12820 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
12821 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
12824 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12825 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
12826 if (Vec.getOpcode() == ISD::UNDEF)
12827 return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12828 DAG.getConstant(IdxVal, MVT::i8));
12829 const TargetRegisterClass* rc = getRegClassFor(VecVT);
12830 unsigned MaxSift = rc->getSize()*8 - 1;
12831 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
12832 DAG.getConstant(MaxSift, MVT::i8));
12833 EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,
12834 DAG.getConstant(MaxSift - IdxVal, MVT::i8));
12835 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
12838 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
12839 SelectionDAG &DAG) const {
12840 MVT VT = Op.getSimpleValueType();
12841 MVT EltVT = VT.getVectorElementType();
12843 if (EltVT == MVT::i1)
12844 return InsertBitToMaskVector(Op, DAG);
12847 SDValue N0 = Op.getOperand(0);
12848 SDValue N1 = Op.getOperand(1);
12849 SDValue N2 = Op.getOperand(2);
12850 if (!isa<ConstantSDNode>(N2))
12852 auto *N2C = cast<ConstantSDNode>(N2);
12853 unsigned IdxVal = N2C->getZExtValue();
12855 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
12856 // into that, and then insert the subvector back into the result.
12857 if (VT.is256BitVector() || VT.is512BitVector()) {
12858 // Get the desired 128-bit vector half.
12859 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
12861 // Insert the element into the desired half.
12862 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
12863 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
12865 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
12866 DAG.getConstant(IdxIn128, MVT::i32));
12868 // Insert the changed part back to the 256-bit vector
12869 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
12871 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
12873 if (Subtarget->hasSSE41()) {
12874 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
12876 if (VT == MVT::v8i16) {
12877 Opc = X86ISD::PINSRW;
12879 assert(VT == MVT::v16i8);
12880 Opc = X86ISD::PINSRB;
12883 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
12885 if (N1.getValueType() != MVT::i32)
12886 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12887 if (N2.getValueType() != MVT::i32)
12888 N2 = DAG.getIntPtrConstant(IdxVal);
12889 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
12892 if (EltVT == MVT::f32) {
12893 // Bits [7:6] of the constant are the source select. This will always be
12894 // zero here. The DAG Combiner may combine an extract_elt index into
12896 // bits. For example (insert (extract, 3), 2) could be matched by
12898 // the '3' into bits [7:6] of X86ISD::INSERTPS.
12899 // Bits [5:4] of the constant are the destination select. This is the
12900 // value of the incoming immediate.
12901 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
12902 // combine either bitwise AND or insert of float 0.0 to set these bits.
12903 N2 = DAG.getIntPtrConstant(IdxVal << 4);
12904 // Create this as a scalar to vector..
12905 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
12906 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
12909 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
12910 // PINSR* works with constant index.
12915 if (EltVT == MVT::i8)
12918 if (EltVT.getSizeInBits() == 16) {
12919 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
12920 // as its second argument.
12921 if (N1.getValueType() != MVT::i32)
12922 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
12923 if (N2.getValueType() != MVT::i32)
12924 N2 = DAG.getIntPtrConstant(IdxVal);
12925 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
12930 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
12932 MVT OpVT = Op.getSimpleValueType();
12934 // If this is a 256-bit vector result, first insert into a 128-bit
12935 // vector and then insert into the 256-bit vector.
12936 if (!OpVT.is128BitVector()) {
12937 // Insert into a 128-bit vector.
12938 unsigned SizeFactor = OpVT.getSizeInBits()/128;
12939 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
12940 OpVT.getVectorNumElements() / SizeFactor);
12942 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
12944 // Insert the 128-bit vector.
12945 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
12948 if (OpVT == MVT::v1i64 &&
12949 Op.getOperand(0).getValueType() == MVT::i64)
12950 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
12952 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
12953 assert(OpVT.is128BitVector() && "Expected an SSE type!");
12954 return DAG.getNode(ISD::BITCAST, dl, OpVT,
12955 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
12958 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
12959 // a simple subregister reference or explicit instructions to grab
12960 // upper bits of a vector.
12961 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12962 SelectionDAG &DAG) {
12964 SDValue In = Op.getOperand(0);
12965 SDValue Idx = Op.getOperand(1);
12966 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12967 MVT ResVT = Op.getSimpleValueType();
12968 MVT InVT = In.getSimpleValueType();
12970 if (Subtarget->hasFp256()) {
12971 if (ResVT.is128BitVector() &&
12972 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12973 isa<ConstantSDNode>(Idx)) {
12974 return Extract128BitVector(In, IdxVal, DAG, dl);
12976 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12977 isa<ConstantSDNode>(Idx)) {
12978 return Extract256BitVector(In, IdxVal, DAG, dl);
12984 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12985 // simple superregister reference or explicit instructions to insert
12986 // the upper bits of a vector.
12987 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12988 SelectionDAG &DAG) {
12989 if (Subtarget->hasFp256()) {
12990 SDLoc dl(Op.getNode());
12991 SDValue Vec = Op.getNode()->getOperand(0);
12992 SDValue SubVec = Op.getNode()->getOperand(1);
12993 SDValue Idx = Op.getNode()->getOperand(2);
12995 if ((Op.getNode()->getSimpleValueType(0).is256BitVector() ||
12996 Op.getNode()->getSimpleValueType(0).is512BitVector()) &&
12997 SubVec.getNode()->getSimpleValueType(0).is128BitVector() &&
12998 isa<ConstantSDNode>(Idx)) {
12999 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13000 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
13003 if (Op.getNode()->getSimpleValueType(0).is512BitVector() &&
13004 SubVec.getNode()->getSimpleValueType(0).is256BitVector() &&
13005 isa<ConstantSDNode>(Idx)) {
13006 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
13007 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
13013 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
13014 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
13015 // one of the above mentioned nodes. It has to be wrapped because otherwise
13016 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
13017 // be used to form addressing mode. These wrapped nodes will be selected
13020 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
13021 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
13023 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13024 // global base reg.
13025 unsigned char OpFlag = 0;
13026 unsigned WrapperKind = X86ISD::Wrapper;
13027 CodeModel::Model M = DAG.getTarget().getCodeModel();
13029 if (Subtarget->isPICStyleRIPRel() &&
13030 (M == CodeModel::Small || M == CodeModel::Kernel))
13031 WrapperKind = X86ISD::WrapperRIP;
13032 else if (Subtarget->isPICStyleGOT())
13033 OpFlag = X86II::MO_GOTOFF;
13034 else if (Subtarget->isPICStyleStubPIC())
13035 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13037 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
13038 CP->getAlignment(),
13039 CP->getOffset(), OpFlag);
13041 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13042 // With PIC, the address is actually $g + Offset.
13044 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13045 DAG.getNode(X86ISD::GlobalBaseReg,
13046 SDLoc(), getPointerTy()),
13053 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
13054 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
13056 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13057 // global base reg.
13058 unsigned char OpFlag = 0;
13059 unsigned WrapperKind = X86ISD::Wrapper;
13060 CodeModel::Model M = DAG.getTarget().getCodeModel();
13062 if (Subtarget->isPICStyleRIPRel() &&
13063 (M == CodeModel::Small || M == CodeModel::Kernel))
13064 WrapperKind = X86ISD::WrapperRIP;
13065 else if (Subtarget->isPICStyleGOT())
13066 OpFlag = X86II::MO_GOTOFF;
13067 else if (Subtarget->isPICStyleStubPIC())
13068 OpFlag = X86II::MO_PIC_BASE_OFFSET;
13070 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
13073 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13075 // With PIC, the address is actually $g + Offset.
13077 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13078 DAG.getNode(X86ISD::GlobalBaseReg,
13079 SDLoc(), getPointerTy()),
13086 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
13087 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
13089 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13090 // global base reg.
13091 unsigned char OpFlag = 0;
13092 unsigned WrapperKind = X86ISD::Wrapper;
13093 CodeModel::Model M = DAG.getTarget().getCodeModel();
13095 if (Subtarget->isPICStyleRIPRel() &&
13096 (M == CodeModel::Small || M == CodeModel::Kernel)) {
13097 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
13098 OpFlag = X86II::MO_GOTPCREL;
13099 WrapperKind = X86ISD::WrapperRIP;
13100 } else if (Subtarget->isPICStyleGOT()) {
13101 OpFlag = X86II::MO_GOT;
13102 } else if (Subtarget->isPICStyleStubPIC()) {
13103 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
13104 } else if (Subtarget->isPICStyleStubNoDynamic()) {
13105 OpFlag = X86II::MO_DARWIN_NONLAZY;
13108 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
13111 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13113 // With PIC, the address is actually $g + Offset.
13114 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
13115 !Subtarget->is64Bit()) {
13116 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13117 DAG.getNode(X86ISD::GlobalBaseReg,
13118 SDLoc(), getPointerTy()),
13122 // For symbols that require a load from a stub to get the address, emit the
13124 if (isGlobalStubReference(OpFlag))
13125 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
13126 MachinePointerInfo::getGOT(), false, false, false, 0);
13132 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
13133 // Create the TargetBlockAddressAddress node.
13134 unsigned char OpFlags =
13135 Subtarget->ClassifyBlockAddressReference();
13136 CodeModel::Model M = DAG.getTarget().getCodeModel();
13137 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
13138 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
13140 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
13143 if (Subtarget->isPICStyleRIPRel() &&
13144 (M == CodeModel::Small || M == CodeModel::Kernel))
13145 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13147 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13149 // With PIC, the address is actually $g + Offset.
13150 if (isGlobalRelativeToPICBase(OpFlags)) {
13151 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13152 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13160 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
13161 int64_t Offset, SelectionDAG &DAG) const {
13162 // Create the TargetGlobalAddress node, folding in the constant
13163 // offset if it is legal.
13164 unsigned char OpFlags =
13165 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
13166 CodeModel::Model M = DAG.getTarget().getCodeModel();
13168 if (OpFlags == X86II::MO_NO_FLAG &&
13169 X86::isOffsetSuitableForCodeModel(Offset, M)) {
13170 // A direct static reference to a global.
13171 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
13174 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
13177 if (Subtarget->isPICStyleRIPRel() &&
13178 (M == CodeModel::Small || M == CodeModel::Kernel))
13179 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
13181 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
13183 // With PIC, the address is actually $g + Offset.
13184 if (isGlobalRelativeToPICBase(OpFlags)) {
13185 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
13186 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
13190 // For globals that require a load from a stub to get the address, emit the
13192 if (isGlobalStubReference(OpFlags))
13193 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
13194 MachinePointerInfo::getGOT(), false, false, false, 0);
13196 // If there was a non-zero offset that we didn't fold, create an explicit
13197 // addition for it.
13199 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
13200 DAG.getConstant(Offset, getPointerTy()));
13206 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
13207 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
13208 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
13209 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
13213 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
13214 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
13215 unsigned char OperandFlags, bool LocalDynamic = false) {
13216 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13217 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13219 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13220 GA->getValueType(0),
13224 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
13228 SDValue Ops[] = { Chain, TGA, *InFlag };
13229 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13231 SDValue Ops[] = { Chain, TGA };
13232 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
13235 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
13236 MFI->setAdjustsStack(true);
13237 MFI->setHasCalls(true);
13239 SDValue Flag = Chain.getValue(1);
13240 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
13243 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
13245 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13248 SDLoc dl(GA); // ? function entry point might be better
13249 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13250 DAG.getNode(X86ISD::GlobalBaseReg,
13251 SDLoc(), PtrVT), InFlag);
13252 InFlag = Chain.getValue(1);
13254 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
13257 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
13259 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13261 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
13262 X86::RAX, X86II::MO_TLSGD);
13265 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
13271 // Get the start address of the TLS block for this module.
13272 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
13273 .getInfo<X86MachineFunctionInfo>();
13274 MFI->incNumLocalDynamicTLSAccesses();
13278 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
13279 X86II::MO_TLSLD, /*LocalDynamic=*/true);
13282 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
13283 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
13284 InFlag = Chain.getValue(1);
13285 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
13286 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
13289 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
13293 unsigned char OperandFlags = X86II::MO_DTPOFF;
13294 unsigned WrapperKind = X86ISD::Wrapper;
13295 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13296 GA->getValueType(0),
13297 GA->getOffset(), OperandFlags);
13298 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13300 // Add x@dtpoff with the base.
13301 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
13304 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
13305 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
13306 const EVT PtrVT, TLSModel::Model model,
13307 bool is64Bit, bool isPIC) {
13310 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
13311 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
13312 is64Bit ? 257 : 256));
13314 SDValue ThreadPointer =
13315 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),
13316 MachinePointerInfo(Ptr), false, false, false, 0);
13318 unsigned char OperandFlags = 0;
13319 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
13321 unsigned WrapperKind = X86ISD::Wrapper;
13322 if (model == TLSModel::LocalExec) {
13323 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
13324 } else if (model == TLSModel::InitialExec) {
13326 OperandFlags = X86II::MO_GOTTPOFF;
13327 WrapperKind = X86ISD::WrapperRIP;
13329 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
13332 llvm_unreachable("Unexpected model");
13335 // emit "addl x@ntpoff,%eax" (local exec)
13336 // or "addl x@indntpoff,%eax" (initial exec)
13337 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
13339 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
13340 GA->getOffset(), OperandFlags);
13341 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
13343 if (model == TLSModel::InitialExec) {
13344 if (isPIC && !is64Bit) {
13345 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
13346 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
13350 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
13351 MachinePointerInfo::getGOT(), false, false, false, 0);
13354 // The address of the thread local variable is the add of the thread
13355 // pointer with the offset of the variable.
13356 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
13360 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
13362 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
13363 const GlobalValue *GV = GA->getGlobal();
13365 if (Subtarget->isTargetELF()) {
13366 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
13369 case TLSModel::GeneralDynamic:
13370 if (Subtarget->is64Bit())
13371 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
13372 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
13373 case TLSModel::LocalDynamic:
13374 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
13375 Subtarget->is64Bit());
13376 case TLSModel::InitialExec:
13377 case TLSModel::LocalExec:
13378 return LowerToTLSExecModel(
13379 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
13380 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
13382 llvm_unreachable("Unknown TLS model.");
13385 if (Subtarget->isTargetDarwin()) {
13386 // Darwin only has one model of TLS. Lower to that.
13387 unsigned char OpFlag = 0;
13388 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
13389 X86ISD::WrapperRIP : X86ISD::Wrapper;
13391 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
13392 // global base reg.
13393 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
13394 !Subtarget->is64Bit();
13396 OpFlag = X86II::MO_TLVP_PIC_BASE;
13398 OpFlag = X86II::MO_TLVP;
13400 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
13401 GA->getValueType(0),
13402 GA->getOffset(), OpFlag);
13403 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
13405 // With PIC32, the address is actually $g + Offset.
13407 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
13408 DAG.getNode(X86ISD::GlobalBaseReg,
13409 SDLoc(), getPointerTy()),
13412 // Lowering the machine isd will make sure everything is in the right
13414 SDValue Chain = DAG.getEntryNode();
13415 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
13416 SDValue Args[] = { Chain, Offset };
13417 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
13419 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
13420 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13421 MFI->setAdjustsStack(true);
13423 // And our return value (tls address) is in the standard call return value
13425 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13426 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
13427 Chain.getValue(1));
13430 if (Subtarget->isTargetKnownWindowsMSVC() ||
13431 Subtarget->isTargetWindowsGNU()) {
13432 // Just use the implicit TLS architecture
13433 // Need to generate someting similar to:
13434 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
13436 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
13437 // mov rcx, qword [rdx+rcx*8]
13438 // mov eax, .tls$:tlsvar
13439 // [rax+rcx] contains the address
13440 // Windows 64bit: gs:0x58
13441 // Windows 32bit: fs:__tls_array
13444 SDValue Chain = DAG.getEntryNode();
13446 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
13447 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
13448 // use its literal value of 0x2C.
13449 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
13450 ? Type::getInt8PtrTy(*DAG.getContext(),
13452 : Type::getInt32PtrTy(*DAG.getContext(),
13456 Subtarget->is64Bit()
13457 ? DAG.getIntPtrConstant(0x58)
13458 : (Subtarget->isTargetWindowsGNU()
13459 ? DAG.getIntPtrConstant(0x2C)
13460 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
13462 SDValue ThreadPointer =
13463 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
13464 MachinePointerInfo(Ptr), false, false, false, 0);
13466 // Load the _tls_index variable
13467 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
13468 if (Subtarget->is64Bit())
13469 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
13470 IDX, MachinePointerInfo(), MVT::i32,
13471 false, false, false, 0);
13473 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
13474 false, false, false, 0);
13476 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
13478 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
13480 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
13481 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
13482 false, false, false, 0);
13484 // Get the offset of start of .tls section
13485 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
13486 GA->getValueType(0),
13487 GA->getOffset(), X86II::MO_SECREL);
13488 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
13490 // The address of the thread local variable is the add of the thread
13491 // pointer with the offset of the variable.
13492 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
13495 llvm_unreachable("TLS not implemented for this target.");
13498 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
13499 /// and take a 2 x i32 value to shift plus a shift amount.
13500 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
13501 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
13502 MVT VT = Op.getSimpleValueType();
13503 unsigned VTBits = VT.getSizeInBits();
13505 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
13506 SDValue ShOpLo = Op.getOperand(0);
13507 SDValue ShOpHi = Op.getOperand(1);
13508 SDValue ShAmt = Op.getOperand(2);
13509 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
13510 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
13512 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13513 DAG.getConstant(VTBits - 1, MVT::i8));
13514 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
13515 DAG.getConstant(VTBits - 1, MVT::i8))
13516 : DAG.getConstant(0, VT);
13518 SDValue Tmp2, Tmp3;
13519 if (Op.getOpcode() == ISD::SHL_PARTS) {
13520 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
13521 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
13523 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
13524 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
13527 // If the shift amount is larger or equal than the width of a part we can't
13528 // rely on the results of shld/shrd. Insert a test and select the appropriate
13529 // values for large shift amounts.
13530 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
13531 DAG.getConstant(VTBits, MVT::i8));
13532 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
13533 AndNode, DAG.getConstant(0, MVT::i8));
13536 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
13537 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
13538 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
13540 if (Op.getOpcode() == ISD::SHL_PARTS) {
13541 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13542 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13544 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
13545 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
13548 SDValue Ops[2] = { Lo, Hi };
13549 return DAG.getMergeValues(Ops, dl);
13552 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
13553 SelectionDAG &DAG) const {
13554 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
13557 if (SrcVT.isVector()) {
13558 if (SrcVT.getVectorElementType() == MVT::i1) {
13559 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
13560 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13561 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT,
13562 Op.getOperand(0)));
13567 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
13568 "Unknown SINT_TO_FP to lower!");
13570 // These are really Legal; return the operand so the caller accepts it as
13572 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
13574 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
13575 Subtarget->is64Bit()) {
13579 unsigned Size = SrcVT.getSizeInBits()/8;
13580 MachineFunction &MF = DAG.getMachineFunction();
13581 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
13582 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13583 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13585 MachinePointerInfo::getFixedStack(SSFI),
13587 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
13590 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
13592 SelectionDAG &DAG) const {
13596 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
13598 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
13600 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
13602 unsigned ByteSize = SrcVT.getSizeInBits()/8;
13604 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
13605 MachineMemOperand *MMO;
13607 int SSFI = FI->getIndex();
13609 DAG.getMachineFunction()
13610 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13611 MachineMemOperand::MOLoad, ByteSize, ByteSize);
13613 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
13614 StackSlot = StackSlot.getOperand(1);
13616 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
13617 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
13619 Tys, Ops, SrcVT, MMO);
13622 Chain = Result.getValue(1);
13623 SDValue InFlag = Result.getValue(2);
13625 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
13626 // shouldn't be necessary except that RFP cannot be live across
13627 // multiple blocks. When stackifier is fixed, they can be uncoupled.
13628 MachineFunction &MF = DAG.getMachineFunction();
13629 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
13630 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
13631 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
13632 Tys = DAG.getVTList(MVT::Other);
13634 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
13636 MachineMemOperand *MMO =
13637 DAG.getMachineFunction()
13638 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13639 MachineMemOperand::MOStore, SSFISize, SSFISize);
13641 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
13642 Ops, Op.getValueType(), MMO);
13643 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
13644 MachinePointerInfo::getFixedStack(SSFI),
13645 false, false, false, 0);
13651 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
13652 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
13653 SelectionDAG &DAG) const {
13654 // This algorithm is not obvious. Here it is what we're trying to output:
13657 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
13658 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
13660 haddpd %xmm0, %xmm0
13662 pshufd $0x4e, %xmm0, %xmm1
13668 LLVMContext *Context = DAG.getContext();
13670 // Build some magic constants.
13671 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
13672 Constant *C0 = ConstantDataVector::get(*Context, CV0);
13673 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
13675 SmallVector<Constant*,2> CV1;
13677 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13678 APInt(64, 0x4330000000000000ULL))));
13680 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
13681 APInt(64, 0x4530000000000000ULL))));
13682 Constant *C1 = ConstantVector::get(CV1);
13683 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
13685 // Load the 64-bit value into an XMM register.
13686 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
13688 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
13689 MachinePointerInfo::getConstantPool(),
13690 false, false, false, 16);
13691 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
13692 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
13695 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
13696 MachinePointerInfo::getConstantPool(),
13697 false, false, false, 16);
13698 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
13699 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
13702 if (Subtarget->hasSSE3()) {
13703 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
13704 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
13706 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
13707 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
13709 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
13710 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
13714 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
13715 DAG.getIntPtrConstant(0));
13718 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
13719 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
13720 SelectionDAG &DAG) const {
13722 // FP constant to bias correct the final result.
13723 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
13726 // Load the 32-bit value into an XMM register.
13727 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
13730 // Zero out the upper parts of the register.
13731 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
13733 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13734 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
13735 DAG.getIntPtrConstant(0));
13737 // Or the load with the bias.
13738 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
13739 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13740 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13741 MVT::v2f64, Load)),
13742 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
13743 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
13744 MVT::v2f64, Bias)));
13745 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
13746 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
13747 DAG.getIntPtrConstant(0));
13749 // Subtract the bias.
13750 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
13752 // Handle final rounding.
13753 EVT DestVT = Op.getValueType();
13755 if (DestVT.bitsLT(MVT::f64))
13756 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
13757 DAG.getIntPtrConstant(0));
13758 if (DestVT.bitsGT(MVT::f64))
13759 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
13761 // Handle final rounding.
13765 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
13766 const X86Subtarget &Subtarget) {
13767 // The algorithm is the following:
13768 // #ifdef __SSE4_1__
13769 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13770 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13771 // (uint4) 0x53000000, 0xaa);
13773 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13774 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13776 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13777 // return (float4) lo + fhi;
13780 SDValue V = Op->getOperand(0);
13781 EVT VecIntVT = V.getValueType();
13782 bool Is128 = VecIntVT == MVT::v4i32;
13783 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
13784 // If we convert to something else than the supported type, e.g., to v4f64,
13786 if (VecFloatVT != Op->getValueType(0))
13789 unsigned NumElts = VecIntVT.getVectorNumElements();
13790 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
13791 "Unsupported custom type");
13792 assert(NumElts <= 8 && "The size of the constant array must be fixed");
13794 // In the #idef/#else code, we have in common:
13795 // - The vector of constants:
13801 // Create the splat vector for 0x4b000000.
13802 SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);
13803 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
13804 CstLow, CstLow, CstLow, CstLow};
13805 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13806 makeArrayRef(&CstLowArray[0], NumElts));
13807 // Create the splat vector for 0x53000000.
13808 SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);
13809 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
13810 CstHigh, CstHigh, CstHigh, CstHigh};
13811 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13812 makeArrayRef(&CstHighArray[0], NumElts));
13814 // Create the right shift.
13815 SDValue CstShift = DAG.getConstant(16, MVT::i32);
13816 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
13817 CstShift, CstShift, CstShift, CstShift};
13818 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
13819 makeArrayRef(&CstShiftArray[0], NumElts));
13820 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
13823 if (Subtarget.hasSSE41()) {
13824 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
13825 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
13826 SDValue VecCstLowBitcast =
13827 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstLow);
13828 SDValue VecBitcast = DAG.getNode(ISD::BITCAST, DL, VecI16VT, V);
13829 // Low will be bitcasted right away, so do not bother bitcasting back to its
13831 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
13832 VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));
13833 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
13834 // (uint4) 0x53000000, 0xaa);
13835 SDValue VecCstHighBitcast =
13836 DAG.getNode(ISD::BITCAST, DL, VecI16VT, VecCstHigh);
13837 SDValue VecShiftBitcast =
13838 DAG.getNode(ISD::BITCAST, DL, VecI16VT, HighShift);
13839 // High will be bitcasted right away, so do not bother bitcasting back to
13840 // its original type.
13841 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
13842 VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));
13844 SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);
13845 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
13846 CstMask, CstMask, CstMask);
13847 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
13848 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
13849 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
13851 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
13852 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
13855 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
13856 SDValue CstFAdd = DAG.getConstantFP(
13857 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);
13858 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
13859 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
13860 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
13861 makeArrayRef(&CstFAddArray[0], NumElts));
13863 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
13864 SDValue HighBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, High);
13866 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
13867 // return (float4) lo + fhi;
13868 SDValue LowBitcast = DAG.getNode(ISD::BITCAST, DL, VecFloatVT, Low);
13869 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
13872 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
13873 SelectionDAG &DAG) const {
13874 SDValue N0 = Op.getOperand(0);
13875 MVT SVT = N0.getSimpleValueType();
13878 switch (SVT.SimpleTy) {
13880 llvm_unreachable("Custom UINT_TO_FP is not supported!");
13885 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
13886 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
13887 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
13891 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
13893 llvm_unreachable(nullptr);
13896 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13897 SelectionDAG &DAG) const {
13898 SDValue N0 = Op.getOperand(0);
13901 if (Op.getValueType().isVector())
13902 return lowerUINT_TO_FP_vec(Op, DAG);
13904 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13905 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13906 // the optimization here.
13907 if (DAG.SignBitIsZero(N0))
13908 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13910 MVT SrcVT = N0.getSimpleValueType();
13911 MVT DstVT = Op.getSimpleValueType();
13912 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13913 return LowerUINT_TO_FP_i64(Op, DAG);
13914 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13915 return LowerUINT_TO_FP_i32(Op, DAG);
13916 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13919 // Make a 64-bit buffer, and use it to build an FILD.
13920 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13921 if (SrcVT == MVT::i32) {
13922 SDValue WordOff = DAG.getConstant(4, getPointerTy());
13923 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
13924 getPointerTy(), StackSlot, WordOff);
13925 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13926 StackSlot, MachinePointerInfo(),
13928 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
13929 OffsetSlot, MachinePointerInfo(),
13931 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13935 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13936 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13937 StackSlot, MachinePointerInfo(),
13939 // For i64 source, we need to add the appropriate power of 2 if the input
13940 // was negative. This is the same as the optimization in
13941 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13942 // we must be careful to do the computation in x87 extended precision, not
13943 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13944 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13945 MachineMemOperand *MMO =
13946 DAG.getMachineFunction()
13947 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
13948 MachineMemOperand::MOLoad, 8, 8);
13950 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13951 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13952 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13955 APInt FF(32, 0x5F800000ULL);
13957 // Check whether the sign bit is set.
13958 SDValue SignSet = DAG.getSetCC(dl,
13959 getSetCCResultType(*DAG.getContext(), MVT::i64),
13960 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
13963 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13964 SDValue FudgePtr = DAG.getConstantPool(
13965 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
13968 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13969 SDValue Zero = DAG.getIntPtrConstant(0);
13970 SDValue Four = DAG.getIntPtrConstant(4);
13971 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13973 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
13975 // Load the value out, extending it from f32 to f80.
13976 // FIXME: Avoid the extend by constructing the right constant pool?
13977 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
13978 FudgePtr, MachinePointerInfo::getConstantPool(),
13979 MVT::f32, false, false, false, 4);
13980 // Extend everything to 80 bits to force it to be done on x87.
13981 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13982 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
13985 std::pair<SDValue,SDValue>
13986 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13987 bool IsSigned, bool IsReplace) const {
13990 EVT DstTy = Op.getValueType();
13992 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
13993 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13997 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13998 DstTy.getSimpleVT() >= MVT::i16 &&
13999 "Unknown FP_TO_INT to lower!");
14001 // These are really Legal.
14002 if (DstTy == MVT::i32 &&
14003 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14004 return std::make_pair(SDValue(), SDValue());
14005 if (Subtarget->is64Bit() &&
14006 DstTy == MVT::i64 &&
14007 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
14008 return std::make_pair(SDValue(), SDValue());
14010 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
14011 // stack slot, or into the FTOL runtime function.
14012 MachineFunction &MF = DAG.getMachineFunction();
14013 unsigned MemSize = DstTy.getSizeInBits()/8;
14014 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14015 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14018 if (!IsSigned && isIntegerTypeFTOL(DstTy))
14019 Opc = X86ISD::WIN_FTOL;
14021 switch (DstTy.getSimpleVT().SimpleTy) {
14022 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
14023 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
14024 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
14025 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
14028 SDValue Chain = DAG.getEntryNode();
14029 SDValue Value = Op.getOperand(0);
14030 EVT TheVT = Op.getOperand(0).getValueType();
14031 // FIXME This causes a redundant load/store if the SSE-class value is already
14032 // in memory, such as if it is on the callstack.
14033 if (isScalarFPTypeInSSEReg(TheVT)) {
14034 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
14035 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
14036 MachinePointerInfo::getFixedStack(SSFI),
14038 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
14040 Chain, StackSlot, DAG.getValueType(TheVT)
14043 MachineMemOperand *MMO =
14044 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14045 MachineMemOperand::MOLoad, MemSize, MemSize);
14046 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
14047 Chain = Value.getValue(1);
14048 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
14049 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
14052 MachineMemOperand *MMO =
14053 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
14054 MachineMemOperand::MOStore, MemSize, MemSize);
14056 if (Opc != X86ISD::WIN_FTOL) {
14057 // Build the FP_TO_INT*_IN_MEM
14058 SDValue Ops[] = { Chain, Value, StackSlot };
14059 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
14061 return std::make_pair(FIST, StackSlot);
14063 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
14064 DAG.getVTList(MVT::Other, MVT::Glue),
14066 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
14067 MVT::i32, ftol.getValue(1));
14068 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
14069 MVT::i32, eax.getValue(2));
14070 SDValue Ops[] = { eax, edx };
14071 SDValue pair = IsReplace
14072 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
14073 : DAG.getMergeValues(Ops, DL);
14074 return std::make_pair(pair, SDValue());
14078 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
14079 const X86Subtarget *Subtarget) {
14080 MVT VT = Op->getSimpleValueType(0);
14081 SDValue In = Op->getOperand(0);
14082 MVT InVT = In.getSimpleValueType();
14085 // Optimize vectors in AVX mode:
14088 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
14089 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
14090 // Concat upper and lower parts.
14093 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
14094 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
14095 // Concat upper and lower parts.
14098 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
14099 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
14100 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
14103 if (Subtarget->hasInt256())
14104 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
14106 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
14107 SDValue Undef = DAG.getUNDEF(InVT);
14108 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
14109 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14110 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
14112 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
14113 VT.getVectorNumElements()/2);
14115 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
14116 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
14118 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14121 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
14122 SelectionDAG &DAG) {
14123 MVT VT = Op->getSimpleValueType(0);
14124 SDValue In = Op->getOperand(0);
14125 MVT InVT = In.getSimpleValueType();
14127 unsigned int NumElts = VT.getVectorNumElements();
14128 if (NumElts != 8 && NumElts != 16)
14131 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
14132 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
14134 EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;
14135 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14136 // Now we have only mask extension
14137 assert(InVT.getVectorElementType() == MVT::i1);
14138 SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());
14139 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14140 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
14141 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14142 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14143 MachinePointerInfo::getConstantPool(),
14144 false, false, false, Alignment);
14146 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, DL, ExtVT, In, Ld);
14147 if (VT.is512BitVector())
14149 return DAG.getNode(X86ISD::VTRUNC, DL, VT, Brcst);
14152 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14153 SelectionDAG &DAG) {
14154 if (Subtarget->hasFp256()) {
14155 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14163 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14164 SelectionDAG &DAG) {
14166 MVT VT = Op.getSimpleValueType();
14167 SDValue In = Op.getOperand(0);
14168 MVT SVT = In.getSimpleValueType();
14170 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
14171 return LowerZERO_EXTEND_AVX512(Op, DAG);
14173 if (Subtarget->hasFp256()) {
14174 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
14179 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
14180 VT.getVectorNumElements() != SVT.getVectorNumElements());
14184 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
14186 MVT VT = Op.getSimpleValueType();
14187 SDValue In = Op.getOperand(0);
14188 MVT InVT = In.getSimpleValueType();
14190 if (VT == MVT::i1) {
14191 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
14192 "Invalid scalar TRUNCATE operation");
14193 if (InVT.getSizeInBits() >= 32)
14195 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
14196 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
14198 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
14199 "Invalid TRUNCATE operation");
14201 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
14202 if (VT.getVectorElementType().getSizeInBits() >=8)
14203 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
14205 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14206 unsigned NumElts = InVT.getVectorNumElements();
14207 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
14208 if (InVT.getSizeInBits() < 512) {
14209 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
14210 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
14214 SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());
14215 const Constant *C = (dyn_cast<ConstantSDNode>(Cst))->getConstantIntValue();
14216 SDValue CP = DAG.getConstantPool(C, getPointerTy());
14217 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
14218 SDValue Ld = DAG.getLoad(Cst.getValueType(), DL, DAG.getEntryNode(), CP,
14219 MachinePointerInfo::getConstantPool(),
14220 false, false, false, Alignment);
14221 SDValue OneV = DAG.getNode(X86ISD::VBROADCAST, DL, InVT, Ld);
14222 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
14223 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
14226 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
14227 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
14228 if (Subtarget->hasInt256()) {
14229 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
14230 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
14231 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
14233 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
14234 DAG.getIntPtrConstant(0));
14237 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14238 DAG.getIntPtrConstant(0));
14239 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14240 DAG.getIntPtrConstant(2));
14241 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14242 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14243 static const int ShufMask[] = {0, 2, 4, 6};
14244 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
14247 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
14248 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
14249 if (Subtarget->hasInt256()) {
14250 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
14252 SmallVector<SDValue,32> pshufbMask;
14253 for (unsigned i = 0; i < 2; ++i) {
14254 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
14255 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
14256 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
14257 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
14258 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
14259 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
14260 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
14261 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
14262 for (unsigned j = 0; j < 8; ++j)
14263 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
14265 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
14266 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
14267 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
14269 static const int ShufMask[] = {0, 2, -1, -1};
14270 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
14272 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
14273 DAG.getIntPtrConstant(0));
14274 return DAG.getNode(ISD::BITCAST, DL, VT, In);
14277 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14278 DAG.getIntPtrConstant(0));
14280 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
14281 DAG.getIntPtrConstant(4));
14283 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
14284 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
14286 // The PSHUFB mask:
14287 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
14288 -1, -1, -1, -1, -1, -1, -1, -1};
14290 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
14291 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
14292 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
14294 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
14295 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
14297 // The MOVLHPS Mask:
14298 static const int ShufMask2[] = {0, 1, 4, 5};
14299 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
14300 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
14303 // Handle truncation of V256 to V128 using shuffles.
14304 if (!VT.is128BitVector() || !InVT.is256BitVector())
14307 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
14309 unsigned NumElems = VT.getVectorNumElements();
14310 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
14312 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
14313 // Prepare truncation shuffle mask
14314 for (unsigned i = 0; i != NumElems; ++i)
14315 MaskVec[i] = i * 2;
14316 SDValue V = DAG.getVectorShuffle(NVT, DL,
14317 DAG.getNode(ISD::BITCAST, DL, NVT, In),
14318 DAG.getUNDEF(NVT), &MaskVec[0]);
14319 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
14320 DAG.getIntPtrConstant(0));
14323 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
14324 SelectionDAG &DAG) const {
14325 assert(!Op.getSimpleValueType().isVector());
14327 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14328 /*IsSigned=*/ true, /*IsReplace=*/ false);
14329 SDValue FIST = Vals.first, StackSlot = Vals.second;
14330 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
14331 if (!FIST.getNode()) return Op;
14333 if (StackSlot.getNode())
14334 // Load the result.
14335 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14336 FIST, StackSlot, MachinePointerInfo(),
14337 false, false, false, 0);
14339 // The node is the result.
14343 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
14344 SelectionDAG &DAG) const {
14345 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
14346 /*IsSigned=*/ false, /*IsReplace=*/ false);
14347 SDValue FIST = Vals.first, StackSlot = Vals.second;
14348 assert(FIST.getNode() && "Unexpected failure");
14350 if (StackSlot.getNode())
14351 // Load the result.
14352 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
14353 FIST, StackSlot, MachinePointerInfo(),
14354 false, false, false, 0);
14356 // The node is the result.
14360 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
14362 MVT VT = Op.getSimpleValueType();
14363 SDValue In = Op.getOperand(0);
14364 MVT SVT = In.getSimpleValueType();
14366 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
14368 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
14369 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
14370 In, DAG.getUNDEF(SVT)));
14373 /// The only differences between FABS and FNEG are the mask and the logic op.
14374 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
14375 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
14376 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
14377 "Wrong opcode for lowering FABS or FNEG.");
14379 bool IsFABS = (Op.getOpcode() == ISD::FABS);
14381 // If this is a FABS and it has an FNEG user, bail out to fold the combination
14382 // into an FNABS. We'll lower the FABS after that if it is still in use.
14384 for (SDNode *User : Op->uses())
14385 if (User->getOpcode() == ISD::FNEG)
14388 SDValue Op0 = Op.getOperand(0);
14389 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
14392 MVT VT = Op.getSimpleValueType();
14393 // Assume scalar op for initialization; update for vector if needed.
14394 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
14395 // generate a 16-byte vector constant and logic op even for the scalar case.
14396 // Using a 16-byte mask allows folding the load of the mask with
14397 // the logic op, so it can save (~4 bytes) on code size.
14399 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
14400 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
14401 // decide if we should generate a 16-byte constant mask when we only need 4 or
14402 // 8 bytes for the scalar case.
14403 if (VT.isVector()) {
14404 EltVT = VT.getVectorElementType();
14405 NumElts = VT.getVectorNumElements();
14408 unsigned EltBits = EltVT.getSizeInBits();
14409 LLVMContext *Context = DAG.getContext();
14410 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
14412 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
14413 Constant *C = ConstantInt::get(*Context, MaskElt);
14414 C = ConstantVector::getSplat(NumElts, C);
14415 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14416 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
14417 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
14418 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14419 MachinePointerInfo::getConstantPool(),
14420 false, false, false, Alignment);
14422 if (VT.isVector()) {
14423 // For a vector, cast operands to a vector type, perform the logic op,
14424 // and cast the result back to the original value type.
14425 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
14426 SDValue MaskCasted = DAG.getNode(ISD::BITCAST, dl, VecVT, Mask);
14427 SDValue Operand = IsFNABS ?
14428 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0.getOperand(0)) :
14429 DAG.getNode(ISD::BITCAST, dl, VecVT, Op0);
14430 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
14431 return DAG.getNode(ISD::BITCAST, dl, VT,
14432 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
14435 // If not vector, then scalar.
14436 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
14437 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
14438 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
14441 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
14442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14443 LLVMContext *Context = DAG.getContext();
14444 SDValue Op0 = Op.getOperand(0);
14445 SDValue Op1 = Op.getOperand(1);
14447 MVT VT = Op.getSimpleValueType();
14448 MVT SrcVT = Op1.getSimpleValueType();
14450 // If second operand is smaller, extend it first.
14451 if (SrcVT.bitsLT(VT)) {
14452 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
14455 // And if it is bigger, shrink it first.
14456 if (SrcVT.bitsGT(VT)) {
14457 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
14461 // At this point the operands and the result should have the same
14462 // type, and that won't be f80 since that is not custom lowered.
14464 const fltSemantics &Sem =
14465 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
14466 const unsigned SizeInBits = VT.getSizeInBits();
14468 SmallVector<Constant *, 4> CV(
14469 VT == MVT::f64 ? 2 : 4,
14470 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
14472 // First, clear all bits but the sign bit from the second operand (sign).
14473 CV[0] = ConstantFP::get(*Context,
14474 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
14475 Constant *C = ConstantVector::get(CV);
14476 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14477 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
14478 MachinePointerInfo::getConstantPool(),
14479 false, false, false, 16);
14480 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
14482 // Next, clear the sign bit from the first operand (magnitude).
14483 CV[0] = ConstantFP::get(
14484 *Context, APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
14485 C = ConstantVector::get(CV);
14486 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
14487 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
14488 MachinePointerInfo::getConstantPool(),
14489 false, false, false, 16);
14490 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
14492 // OR the magnitude value with the sign bit.
14493 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
14496 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
14497 SDValue N0 = Op.getOperand(0);
14499 MVT VT = Op.getSimpleValueType();
14501 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
14502 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
14503 DAG.getConstant(1, VT));
14504 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
14507 // Check whether an OR'd tree is PTEST-able.
14508 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
14509 SelectionDAG &DAG) {
14510 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
14512 if (!Subtarget->hasSSE41())
14515 if (!Op->hasOneUse())
14518 SDNode *N = Op.getNode();
14521 SmallVector<SDValue, 8> Opnds;
14522 DenseMap<SDValue, unsigned> VecInMap;
14523 SmallVector<SDValue, 8> VecIns;
14524 EVT VT = MVT::Other;
14526 // Recognize a special case where a vector is casted into wide integer to
14528 Opnds.push_back(N->getOperand(0));
14529 Opnds.push_back(N->getOperand(1));
14531 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
14532 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
14533 // BFS traverse all OR'd operands.
14534 if (I->getOpcode() == ISD::OR) {
14535 Opnds.push_back(I->getOperand(0));
14536 Opnds.push_back(I->getOperand(1));
14537 // Re-evaluate the number of nodes to be traversed.
14538 e += 2; // 2 more nodes (LHS and RHS) are pushed.
14542 // Quit if a non-EXTRACT_VECTOR_ELT
14543 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14546 // Quit if without a constant index.
14547 SDValue Idx = I->getOperand(1);
14548 if (!isa<ConstantSDNode>(Idx))
14551 SDValue ExtractedFromVec = I->getOperand(0);
14552 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
14553 if (M == VecInMap.end()) {
14554 VT = ExtractedFromVec.getValueType();
14555 // Quit if not 128/256-bit vector.
14556 if (!VT.is128BitVector() && !VT.is256BitVector())
14558 // Quit if not the same type.
14559 if (VecInMap.begin() != VecInMap.end() &&
14560 VT != VecInMap.begin()->first.getValueType())
14562 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
14563 VecIns.push_back(ExtractedFromVec);
14565 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
14568 assert((VT.is128BitVector() || VT.is256BitVector()) &&
14569 "Not extracted from 128-/256-bit vector.");
14571 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
14573 for (DenseMap<SDValue, unsigned>::const_iterator
14574 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
14575 // Quit if not all elements are used.
14576 if (I->second != FullMask)
14580 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
14582 // Cast all vectors into TestVT for PTEST.
14583 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
14584 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
14586 // If more than one full vectors are evaluated, OR them first before PTEST.
14587 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
14588 // Each iteration will OR 2 nodes and append the result until there is only
14589 // 1 node left, i.e. the final OR'd value of all vectors.
14590 SDValue LHS = VecIns[Slot];
14591 SDValue RHS = VecIns[Slot + 1];
14592 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
14595 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
14596 VecIns.back(), VecIns.back());
14599 /// \brief return true if \c Op has a use that doesn't just read flags.
14600 static bool hasNonFlagsUse(SDValue Op) {
14601 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
14603 SDNode *User = *UI;
14604 unsigned UOpNo = UI.getOperandNo();
14605 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
14606 // Look pass truncate.
14607 UOpNo = User->use_begin().getOperandNo();
14608 User = *User->use_begin();
14611 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
14612 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
14618 /// Emit nodes that will be selected as "test Op0,Op0", or something
14620 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
14621 SelectionDAG &DAG) const {
14622 if (Op.getValueType() == MVT::i1)
14623 // KORTEST instruction should be selected
14624 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14625 DAG.getConstant(0, Op.getValueType()));
14627 // CF and OF aren't always set the way we want. Determine which
14628 // of these we need.
14629 bool NeedCF = false;
14630 bool NeedOF = false;
14633 case X86::COND_A: case X86::COND_AE:
14634 case X86::COND_B: case X86::COND_BE:
14637 case X86::COND_G: case X86::COND_GE:
14638 case X86::COND_L: case X86::COND_LE:
14639 case X86::COND_O: case X86::COND_NO: {
14640 // Check if we really need to set the
14641 // Overflow flag. If NoSignedWrap is present
14642 // that is not actually needed.
14643 switch (Op->getOpcode()) {
14648 const BinaryWithFlagsSDNode *BinNode =
14649 cast<BinaryWithFlagsSDNode>(Op.getNode());
14650 if (BinNode->hasNoSignedWrap())
14660 // See if we can use the EFLAGS value from the operand instead of
14661 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
14662 // we prove that the arithmetic won't overflow, we can't use OF or CF.
14663 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
14664 // Emit a CMP with 0, which is the TEST pattern.
14665 //if (Op.getValueType() == MVT::i1)
14666 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
14667 // DAG.getConstant(0, MVT::i1));
14668 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14669 DAG.getConstant(0, Op.getValueType()));
14671 unsigned Opcode = 0;
14672 unsigned NumOperands = 0;
14674 // Truncate operations may prevent the merge of the SETCC instruction
14675 // and the arithmetic instruction before it. Attempt to truncate the operands
14676 // of the arithmetic instruction and use a reduced bit-width instruction.
14677 bool NeedTruncation = false;
14678 SDValue ArithOp = Op;
14679 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
14680 SDValue Arith = Op->getOperand(0);
14681 // Both the trunc and the arithmetic op need to have one user each.
14682 if (Arith->hasOneUse())
14683 switch (Arith.getOpcode()) {
14690 NeedTruncation = true;
14696 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
14697 // which may be the result of a CAST. We use the variable 'Op', which is the
14698 // non-casted variable when we check for possible users.
14699 switch (ArithOp.getOpcode()) {
14701 // Due to an isel shortcoming, be conservative if this add is likely to be
14702 // selected as part of a load-modify-store instruction. When the root node
14703 // in a match is a store, isel doesn't know how to remap non-chain non-flag
14704 // uses of other nodes in the match, such as the ADD in this case. This
14705 // leads to the ADD being left around and reselected, with the result being
14706 // two adds in the output. Alas, even if none our users are stores, that
14707 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
14708 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
14709 // climbing the DAG back to the root, and it doesn't seem to be worth the
14711 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14712 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14713 if (UI->getOpcode() != ISD::CopyToReg &&
14714 UI->getOpcode() != ISD::SETCC &&
14715 UI->getOpcode() != ISD::STORE)
14718 if (ConstantSDNode *C =
14719 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14720 // An add of one will be selected as an INC.
14721 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
14722 Opcode = X86ISD::INC;
14727 // An add of negative one (subtract of one) will be selected as a DEC.
14728 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
14729 Opcode = X86ISD::DEC;
14735 // Otherwise use a regular EFLAGS-setting add.
14736 Opcode = X86ISD::ADD;
14741 // If we have a constant logical shift that's only used in a comparison
14742 // against zero turn it into an equivalent AND. This allows turning it into
14743 // a TEST instruction later.
14744 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14745 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14746 EVT VT = Op.getValueType();
14747 unsigned BitWidth = VT.getSizeInBits();
14748 unsigned ShAmt = Op->getConstantOperandVal(1);
14749 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14751 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14752 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14753 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14754 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14756 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14757 DAG.getConstant(Mask, VT));
14758 DAG.ReplaceAllUsesWith(Op, New);
14764 // If the primary and result isn't used, don't bother using X86ISD::AND,
14765 // because a TEST instruction will be better.
14766 if (!hasNonFlagsUse(Op))
14772 // Due to the ISEL shortcoming noted above, be conservative if this op is
14773 // likely to be selected as part of a load-modify-store instruction.
14774 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14775 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14776 if (UI->getOpcode() == ISD::STORE)
14779 // Otherwise use a regular EFLAGS-setting instruction.
14780 switch (ArithOp.getOpcode()) {
14781 default: llvm_unreachable("unexpected operator!");
14782 case ISD::SUB: Opcode = X86ISD::SUB; break;
14783 case ISD::XOR: Opcode = X86ISD::XOR; break;
14784 case ISD::AND: Opcode = X86ISD::AND; break;
14786 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14787 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14788 if (EFLAGS.getNode())
14791 Opcode = X86ISD::OR;
14805 return SDValue(Op.getNode(), 1);
14811 // If we found that truncation is beneficial, perform the truncation and
14813 if (NeedTruncation) {
14814 EVT VT = Op.getValueType();
14815 SDValue WideVal = Op->getOperand(0);
14816 EVT WideVT = WideVal.getValueType();
14817 unsigned ConvertedOp = 0;
14818 // Use a target machine opcode to prevent further DAGCombine
14819 // optimizations that may separate the arithmetic operations
14820 // from the setcc node.
14821 switch (WideVal.getOpcode()) {
14823 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14824 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14825 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14826 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14827 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14831 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14832 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14833 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14834 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14835 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14841 // Emit a CMP with 0, which is the TEST pattern.
14842 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14843 DAG.getConstant(0, Op.getValueType()));
14845 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14846 SmallVector<SDValue, 4> Ops;
14847 for (unsigned i = 0; i != NumOperands; ++i)
14848 Ops.push_back(Op.getOperand(i));
14850 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14851 DAG.ReplaceAllUsesWith(Op, New);
14852 return SDValue(New.getNode(), 1);
14855 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14857 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14858 SDLoc dl, SelectionDAG &DAG) const {
14859 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
14860 if (C->getAPIntValue() == 0)
14861 return EmitTest(Op0, X86CC, dl, DAG);
14863 if (Op0.getValueType() == MVT::i1)
14864 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
14867 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14868 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14869 // Do the comparison at i32 if it's smaller, besides the Atom case.
14870 // This avoids subregister aliasing issues. Keep the smaller reference
14871 // if we're optimizing for size, however, as that'll allow better folding
14872 // of memory operations.
14873 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14874 !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(
14875 AttributeSet::FunctionIndex, Attribute::MinSize) &&
14876 !Subtarget->isAtom()) {
14877 unsigned ExtendOp =
14878 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14879 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14880 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14882 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14883 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14884 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14886 return SDValue(Sub.getNode(), 1);
14888 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14891 /// Convert a comparison if required by the subtarget.
14892 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14893 SelectionDAG &DAG) const {
14894 // If the subtarget does not support the FUCOMI instruction, floating-point
14895 // comparisons have to be converted.
14896 if (Subtarget->hasCMov() ||
14897 Cmp.getOpcode() != X86ISD::CMP ||
14898 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14899 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14902 // The instruction selector will select an FUCOM instruction instead of
14903 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14904 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14905 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14907 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14908 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14909 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14910 DAG.getConstant(8, MVT::i8));
14911 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14912 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14915 /// The minimum architected relative accuracy is 2^-12. We need one
14916 /// Newton-Raphson step to have a good float result (24 bits of precision).
14917 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14918 DAGCombinerInfo &DCI,
14919 unsigned &RefinementSteps,
14920 bool &UseOneConstNR) const {
14921 // FIXME: We should use instruction latency models to calculate the cost of
14922 // each potential sequence, but this is very hard to do reliably because
14923 // at least Intel's Core* chips have variable timing based on the number of
14924 // significant digits in the divisor and/or sqrt operand.
14925 if (!Subtarget->useSqrtEst())
14928 EVT VT = Op.getValueType();
14930 // SSE1 has rsqrtss and rsqrtps.
14931 // TODO: Add support for AVX512 (v16f32).
14932 // It is likely not profitable to do this for f64 because a double-precision
14933 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14934 // instructions: convert to single, rsqrtss, convert back to double, refine
14935 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14936 // along with FMA, this could be a throughput win.
14937 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14938 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14939 RefinementSteps = 1;
14940 UseOneConstNR = false;
14941 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14946 /// The minimum architected relative accuracy is 2^-12. We need one
14947 /// Newton-Raphson step to have a good float result (24 bits of precision).
14948 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14949 DAGCombinerInfo &DCI,
14950 unsigned &RefinementSteps) const {
14951 // FIXME: We should use instruction latency models to calculate the cost of
14952 // each potential sequence, but this is very hard to do reliably because
14953 // at least Intel's Core* chips have variable timing based on the number of
14954 // significant digits in the divisor.
14955 if (!Subtarget->useReciprocalEst())
14958 EVT VT = Op.getValueType();
14960 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14961 // TODO: Add support for AVX512 (v16f32).
14962 // It is likely not profitable to do this for f64 because a double-precision
14963 // reciprocal estimate with refinement on x86 prior to FMA requires
14964 // 15 instructions: convert to single, rcpss, convert back to double, refine
14965 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14966 // along with FMA, this could be a throughput win.
14967 if ((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
14968 (Subtarget->hasAVX() && VT == MVT::v8f32)) {
14969 RefinementSteps = ReciprocalEstimateRefinementSteps;
14970 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14975 static bool isAllOnes(SDValue V) {
14976 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14977 return C && C->isAllOnesValue();
14980 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14981 /// if it's possible.
14982 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14983 SDLoc dl, SelectionDAG &DAG) const {
14984 SDValue Op0 = And.getOperand(0);
14985 SDValue Op1 = And.getOperand(1);
14986 if (Op0.getOpcode() == ISD::TRUNCATE)
14987 Op0 = Op0.getOperand(0);
14988 if (Op1.getOpcode() == ISD::TRUNCATE)
14989 Op1 = Op1.getOperand(0);
14992 if (Op1.getOpcode() == ISD::SHL)
14993 std::swap(Op0, Op1);
14994 if (Op0.getOpcode() == ISD::SHL) {
14995 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14996 if (And00C->getZExtValue() == 1) {
14997 // If we looked past a truncate, check that it's only truncating away
14999 unsigned BitWidth = Op0.getValueSizeInBits();
15000 unsigned AndBitWidth = And.getValueSizeInBits();
15001 if (BitWidth > AndBitWidth) {
15003 DAG.computeKnownBits(Op0, Zeros, Ones);
15004 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
15008 RHS = Op0.getOperand(1);
15010 } else if (Op1.getOpcode() == ISD::Constant) {
15011 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
15012 uint64_t AndRHSVal = AndRHS->getZExtValue();
15013 SDValue AndLHS = Op0;
15015 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
15016 LHS = AndLHS.getOperand(0);
15017 RHS = AndLHS.getOperand(1);
15020 // Use BT if the immediate can't be encoded in a TEST instruction.
15021 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
15023 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
15027 if (LHS.getNode()) {
15028 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
15029 // instruction. Since the shift amount is in-range-or-undefined, we know
15030 // that doing a bittest on the i32 value is ok. We extend to i32 because
15031 // the encoding for the i16 version is larger than the i32 version.
15032 // Also promote i16 to i32 for performance / code size reason.
15033 if (LHS.getValueType() == MVT::i8 ||
15034 LHS.getValueType() == MVT::i16)
15035 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
15037 // If the operand types disagree, extend the shift amount to match. Since
15038 // BT ignores high bits (like shifts) we can use anyextend.
15039 if (LHS.getValueType() != RHS.getValueType())
15040 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
15042 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
15043 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
15044 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15045 DAG.getConstant(Cond, MVT::i8), BT);
15051 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
15053 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
15058 // SSE Condition code mapping:
15067 switch (SetCCOpcode) {
15068 default: llvm_unreachable("Unexpected SETCC condition");
15070 case ISD::SETEQ: SSECC = 0; break;
15072 case ISD::SETGT: Swap = true; // Fallthrough
15074 case ISD::SETOLT: SSECC = 1; break;
15076 case ISD::SETGE: Swap = true; // Fallthrough
15078 case ISD::SETOLE: SSECC = 2; break;
15079 case ISD::SETUO: SSECC = 3; break;
15081 case ISD::SETNE: SSECC = 4; break;
15082 case ISD::SETULE: Swap = true; // Fallthrough
15083 case ISD::SETUGE: SSECC = 5; break;
15084 case ISD::SETULT: Swap = true; // Fallthrough
15085 case ISD::SETUGT: SSECC = 6; break;
15086 case ISD::SETO: SSECC = 7; break;
15088 case ISD::SETONE: SSECC = 8; break;
15091 std::swap(Op0, Op1);
15096 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
15097 // ones, and then concatenate the result back.
15098 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
15099 MVT VT = Op.getSimpleValueType();
15101 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
15102 "Unsupported value type for operation");
15104 unsigned NumElems = VT.getVectorNumElements();
15106 SDValue CC = Op.getOperand(2);
15108 // Extract the LHS vectors
15109 SDValue LHS = Op.getOperand(0);
15110 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
15111 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
15113 // Extract the RHS vectors
15114 SDValue RHS = Op.getOperand(1);
15115 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
15116 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
15118 // Issue the operation on the smaller types and concatenate the result back
15119 MVT EltVT = VT.getVectorElementType();
15120 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
15121 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
15122 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
15123 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
15126 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
15127 const X86Subtarget *Subtarget) {
15128 SDValue Op0 = Op.getOperand(0);
15129 SDValue Op1 = Op.getOperand(1);
15130 SDValue CC = Op.getOperand(2);
15131 MVT VT = Op.getSimpleValueType();
15134 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
15135 Op.getValueType().getScalarType() == MVT::i1 &&
15136 "Cannot set masked compare for this operation");
15138 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15140 bool Unsigned = false;
15143 switch (SetCCOpcode) {
15144 default: llvm_unreachable("Unexpected SETCC condition");
15145 case ISD::SETNE: SSECC = 4; break;
15146 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
15147 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
15148 case ISD::SETLT: Swap = true; //fall-through
15149 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
15150 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
15151 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
15152 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
15153 case ISD::SETULE: Unsigned = true; //fall-through
15154 case ISD::SETLE: SSECC = 2; break;
15158 std::swap(Op0, Op1);
15160 return DAG.getNode(Opc, dl, VT, Op0, Op1);
15161 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
15162 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15163 DAG.getConstant(SSECC, MVT::i8));
15166 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
15167 /// operand \p Op1. If non-trivial (for example because it's not constant)
15168 /// return an empty value.
15169 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
15171 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
15175 MVT VT = Op1.getSimpleValueType();
15176 MVT EVT = VT.getVectorElementType();
15177 unsigned n = VT.getVectorNumElements();
15178 SmallVector<SDValue, 8> ULTOp1;
15180 for (unsigned i = 0; i < n; ++i) {
15181 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
15182 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
15185 // Avoid underflow.
15186 APInt Val = Elt->getAPIntValue();
15190 ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));
15193 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
15196 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
15197 SelectionDAG &DAG) {
15198 SDValue Op0 = Op.getOperand(0);
15199 SDValue Op1 = Op.getOperand(1);
15200 SDValue CC = Op.getOperand(2);
15201 MVT VT = Op.getSimpleValueType();
15202 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
15203 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
15208 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
15209 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
15212 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
15213 unsigned Opc = X86ISD::CMPP;
15214 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
15215 assert(VT.getVectorNumElements() <= 16);
15216 Opc = X86ISD::CMPM;
15218 // In the two special cases we can't handle, emit two comparisons.
15221 unsigned CombineOpc;
15222 if (SetCCOpcode == ISD::SETUEQ) {
15223 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
15225 assert(SetCCOpcode == ISD::SETONE);
15226 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
15229 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15230 DAG.getConstant(CC0, MVT::i8));
15231 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
15232 DAG.getConstant(CC1, MVT::i8));
15233 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
15235 // Handle all other FP comparisons here.
15236 return DAG.getNode(Opc, dl, VT, Op0, Op1,
15237 DAG.getConstant(SSECC, MVT::i8));
15240 // Break 256-bit integer vector compare into smaller ones.
15241 if (VT.is256BitVector() && !Subtarget->hasInt256())
15242 return Lower256IntVSETCC(Op, DAG);
15244 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
15245 EVT OpVT = Op1.getValueType();
15246 if (Subtarget->hasAVX512()) {
15247 if (Op1.getValueType().is512BitVector() ||
15248 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
15249 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
15250 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
15252 // In AVX-512 architecture setcc returns mask with i1 elements,
15253 // But there is no compare instruction for i8 and i16 elements in KNL.
15254 // We are not talking about 512-bit operands in this case, these
15255 // types are illegal.
15257 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
15258 OpVT.getVectorElementType().getSizeInBits() >= 8))
15259 return DAG.getNode(ISD::TRUNCATE, dl, VT,
15260 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
15263 // We are handling one of the integer comparisons here. Since SSE only has
15264 // GT and EQ comparisons for integer, swapping operands and multiple
15265 // operations may be required for some comparisons.
15267 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
15268 bool Subus = false;
15270 switch (SetCCOpcode) {
15271 default: llvm_unreachable("Unexpected SETCC condition");
15272 case ISD::SETNE: Invert = true;
15273 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
15274 case ISD::SETLT: Swap = true;
15275 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
15276 case ISD::SETGE: Swap = true;
15277 case ISD::SETLE: Opc = X86ISD::PCMPGT;
15278 Invert = true; break;
15279 case ISD::SETULT: Swap = true;
15280 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
15281 FlipSigns = true; break;
15282 case ISD::SETUGE: Swap = true;
15283 case ISD::SETULE: Opc = X86ISD::PCMPGT;
15284 FlipSigns = true; Invert = true; break;
15287 // Special case: Use min/max operations for SETULE/SETUGE
15288 MVT VET = VT.getVectorElementType();
15290 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
15291 || (Subtarget->hasSSE2() && (VET == MVT::i8));
15294 switch (SetCCOpcode) {
15296 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
15297 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
15300 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
15303 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
15304 if (!MinMax && hasSubus) {
15305 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
15307 // t = psubus Op0, Op1
15308 // pcmpeq t, <0..0>
15309 switch (SetCCOpcode) {
15311 case ISD::SETULT: {
15312 // If the comparison is against a constant we can turn this into a
15313 // setule. With psubus, setule does not require a swap. This is
15314 // beneficial because the constant in the register is no longer
15315 // destructed as the destination so it can be hoisted out of a loop.
15316 // Only do this pre-AVX since vpcmp* is no longer destructive.
15317 if (Subtarget->hasAVX())
15319 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
15320 if (ULEOp1.getNode()) {
15322 Subus = true; Invert = false; Swap = false;
15326 // Psubus is better than flip-sign because it requires no inversion.
15327 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
15328 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
15332 Opc = X86ISD::SUBUS;
15338 std::swap(Op0, Op1);
15340 // Check that the operation in question is available (most are plain SSE2,
15341 // but PCMPGTQ and PCMPEQQ have different requirements).
15342 if (VT == MVT::v2i64) {
15343 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
15344 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
15346 // First cast everything to the right type.
15347 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15348 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15350 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15351 // bits of the inputs before performing those operations. The lower
15352 // compare is always unsigned.
15355 SB = DAG.getConstant(0x80000000U, MVT::v4i32);
15357 SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);
15358 SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);
15359 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
15360 Sign, Zero, Sign, Zero);
15362 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
15363 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
15365 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
15366 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
15367 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
15369 // Create masks for only the low parts/high parts of the 64 bit integers.
15370 static const int MaskHi[] = { 1, 1, 3, 3 };
15371 static const int MaskLo[] = { 0, 0, 2, 2 };
15372 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
15373 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
15374 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
15376 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
15377 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
15380 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15382 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15385 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
15386 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
15387 // pcmpeqd + pshufd + pand.
15388 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
15390 // First cast everything to the right type.
15391 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
15392 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
15395 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
15397 // Make sure the lower and upper halves are both all-ones.
15398 static const int Mask[] = { 1, 0, 3, 2 };
15399 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
15400 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
15403 Result = DAG.getNOT(dl, Result, MVT::v4i32);
15405 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
15409 // Since SSE has no unsigned integer comparisons, we need to flip the sign
15410 // bits of the inputs before performing those operations.
15412 EVT EltVT = VT.getVectorElementType();
15413 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
15414 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
15415 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
15418 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
15420 // If the logical-not of the result is required, perform that now.
15422 Result = DAG.getNOT(dl, Result, VT);
15425 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
15428 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
15429 getZeroVector(VT, Subtarget, DAG, dl));
15434 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
15436 MVT VT = Op.getSimpleValueType();
15438 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
15440 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
15441 && "SetCC type must be 8-bit or 1-bit integer");
15442 SDValue Op0 = Op.getOperand(0);
15443 SDValue Op1 = Op.getOperand(1);
15445 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
15447 // Optimize to BT if possible.
15448 // Lower (X & (1 << N)) == 0 to BT(X, N).
15449 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
15450 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
15451 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
15452 Op1.getOpcode() == ISD::Constant &&
15453 cast<ConstantSDNode>(Op1)->isNullValue() &&
15454 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15455 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
15456 if (NewSetCC.getNode()) {
15458 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
15463 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
15465 if (Op1.getOpcode() == ISD::Constant &&
15466 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
15467 cast<ConstantSDNode>(Op1)->isNullValue()) &&
15468 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15470 // If the input is a setcc, then reuse the input setcc or use a new one with
15471 // the inverted condition.
15472 if (Op0.getOpcode() == X86ISD::SETCC) {
15473 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
15474 bool Invert = (CC == ISD::SETNE) ^
15475 cast<ConstantSDNode>(Op1)->isNullValue();
15479 CCode = X86::GetOppositeBranchCondition(CCode);
15480 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15481 DAG.getConstant(CCode, MVT::i8),
15482 Op0.getOperand(1));
15484 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15488 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
15489 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
15490 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
15492 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
15493 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);
15496 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
15497 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
15498 if (X86CC == X86::COND_INVALID)
15501 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
15502 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
15503 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15504 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
15506 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
15510 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
15511 static bool isX86LogicalCmp(SDValue Op) {
15512 unsigned Opc = Op.getNode()->getOpcode();
15513 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
15514 Opc == X86ISD::SAHF)
15516 if (Op.getResNo() == 1 &&
15517 (Opc == X86ISD::ADD ||
15518 Opc == X86ISD::SUB ||
15519 Opc == X86ISD::ADC ||
15520 Opc == X86ISD::SBB ||
15521 Opc == X86ISD::SMUL ||
15522 Opc == X86ISD::UMUL ||
15523 Opc == X86ISD::INC ||
15524 Opc == X86ISD::DEC ||
15525 Opc == X86ISD::OR ||
15526 Opc == X86ISD::XOR ||
15527 Opc == X86ISD::AND))
15530 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
15536 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
15537 if (V.getOpcode() != ISD::TRUNCATE)
15540 SDValue VOp0 = V.getOperand(0);
15541 unsigned InBits = VOp0.getValueSizeInBits();
15542 unsigned Bits = V.getValueSizeInBits();
15543 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
15546 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
15547 bool addTest = true;
15548 SDValue Cond = Op.getOperand(0);
15549 SDValue Op1 = Op.getOperand(1);
15550 SDValue Op2 = Op.getOperand(2);
15552 EVT VT = Op1.getValueType();
15555 // Lower fp selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
15556 // are available. Otherwise fp cmovs get lowered into a less efficient branch
15557 // sequence later on.
15558 if (Cond.getOpcode() == ISD::SETCC &&
15559 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
15560 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
15561 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
15562 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
15563 int SSECC = translateX86FSETCC(
15564 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
15567 if (Subtarget->hasAVX512()) {
15568 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
15569 DAG.getConstant(SSECC, MVT::i8));
15570 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
15572 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
15573 DAG.getConstant(SSECC, MVT::i8));
15574 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15575 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15576 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15580 if (Cond.getOpcode() == ISD::SETCC) {
15581 SDValue NewCond = LowerSETCC(Cond, DAG);
15582 if (NewCond.getNode())
15586 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15587 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15588 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15589 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15590 if (Cond.getOpcode() == X86ISD::SETCC &&
15591 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15592 isZero(Cond.getOperand(1).getOperand(1))) {
15593 SDValue Cmp = Cond.getOperand(1);
15595 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15597 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
15598 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15599 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
15601 SDValue CmpOp0 = Cmp.getOperand(0);
15602 // Apply further optimizations for special cases
15603 // (select (x != 0), -1, 0) -> neg & sbb
15604 // (select (x == 0), 0, -1) -> neg & sbb
15605 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
15606 if (YC->isNullValue() &&
15607 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
15608 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15609 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15610 DAG.getConstant(0, CmpOp0.getValueType()),
15612 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15613 DAG.getConstant(X86::COND_B, MVT::i8),
15614 SDValue(Neg.getNode(), 1));
15618 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15619 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
15620 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15622 SDValue Res = // Res = 0 or -1.
15623 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15624 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
15626 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
15627 Res = DAG.getNOT(DL, Res, Res.getValueType());
15629 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
15630 if (!N2C || !N2C->isNullValue())
15631 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15636 // Look past (and (setcc_carry (cmp ...)), 1).
15637 if (Cond.getOpcode() == ISD::AND &&
15638 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15639 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15640 if (C && C->getAPIntValue() == 1)
15641 Cond = Cond.getOperand(0);
15644 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15645 // setting operand in place of the X86ISD::SETCC.
15646 unsigned CondOpcode = Cond.getOpcode();
15647 if (CondOpcode == X86ISD::SETCC ||
15648 CondOpcode == X86ISD::SETCC_CARRY) {
15649 CC = Cond.getOperand(0);
15651 SDValue Cmp = Cond.getOperand(1);
15652 unsigned Opc = Cmp.getOpcode();
15653 MVT VT = Op.getSimpleValueType();
15655 bool IllegalFPCMov = false;
15656 if (VT.isFloatingPoint() && !VT.isVector() &&
15657 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15658 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15660 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15661 Opc == X86ISD::BT) { // FIXME
15665 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15666 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15667 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15668 Cond.getOperand(0).getValueType() != MVT::i8)) {
15669 SDValue LHS = Cond.getOperand(0);
15670 SDValue RHS = Cond.getOperand(1);
15671 unsigned X86Opcode;
15674 switch (CondOpcode) {
15675 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15676 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15677 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15678 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15679 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15680 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15681 default: llvm_unreachable("unexpected overflowing operator");
15683 if (CondOpcode == ISD::UMULO)
15684 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15687 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15689 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15691 if (CondOpcode == ISD::UMULO)
15692 Cond = X86Op.getValue(2);
15694 Cond = X86Op.getValue(1);
15696 CC = DAG.getConstant(X86Cond, MVT::i8);
15701 // Look pass the truncate if the high bits are known zero.
15702 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15703 Cond = Cond.getOperand(0);
15705 // We know the result of AND is compared against zero. Try to match
15707 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15708 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
15709 if (NewSetCC.getNode()) {
15710 CC = NewSetCC.getOperand(0);
15711 Cond = NewSetCC.getOperand(1);
15718 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
15719 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15722 // a < b ? -1 : 0 -> RES = ~setcc_carry
15723 // a < b ? 0 : -1 -> RES = setcc_carry
15724 // a >= b ? -1 : 0 -> RES = setcc_carry
15725 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15726 if (Cond.getOpcode() == X86ISD::SUB) {
15727 Cond = ConvertCmpIfNecessary(Cond, DAG);
15728 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15730 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15731 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
15732 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15733 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
15734 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
15735 return DAG.getNOT(DL, Res, Res.getValueType());
15740 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15741 // widen the cmov and push the truncate through. This avoids introducing a new
15742 // branch during isel and doesn't add any extensions.
15743 if (Op.getValueType() == MVT::i8 &&
15744 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15745 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15746 if (T1.getValueType() == T2.getValueType() &&
15747 // Blacklist CopyFromReg to avoid partial register stalls.
15748 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15749 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15750 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15751 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15755 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15756 // condition is true.
15757 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15758 SDValue Ops[] = { Op2, Op1, CC, Cond };
15759 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15762 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op, const X86Subtarget *Subtarget,
15763 SelectionDAG &DAG) {
15764 MVT VT = Op->getSimpleValueType(0);
15765 SDValue In = Op->getOperand(0);
15766 MVT InVT = In.getSimpleValueType();
15767 MVT VTElt = VT.getVectorElementType();
15768 MVT InVTElt = InVT.getVectorElementType();
15772 if ((InVTElt == MVT::i1) &&
15773 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15774 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15776 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15777 VTElt.getSizeInBits() <= 16)) ||
15779 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15780 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15782 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15783 VTElt.getSizeInBits() >= 32))))
15784 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15786 unsigned int NumElts = VT.getVectorNumElements();
15788 if (NumElts != 8 && NumElts != 16)
15791 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15792 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15793 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15794 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15798 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15800 MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;
15801 Constant *C = ConstantInt::get(*DAG.getContext(),
15802 APInt::getAllOnesValue(ExtVT.getScalarType().getSizeInBits()));
15804 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
15805 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
15806 SDValue Ld = DAG.getLoad(ExtVT.getScalarType(), dl, DAG.getEntryNode(), CP,
15807 MachinePointerInfo::getConstantPool(),
15808 false, false, false, Alignment);
15809 SDValue Brcst = DAG.getNode(X86ISD::VBROADCASTM, dl, ExtVT, In, Ld);
15810 if (VT.is512BitVector())
15812 return DAG.getNode(X86ISD::VTRUNC, dl, VT, Brcst);
15815 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15816 SelectionDAG &DAG) {
15817 MVT VT = Op->getSimpleValueType(0);
15818 SDValue In = Op->getOperand(0);
15819 MVT InVT = In.getSimpleValueType();
15822 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15823 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15825 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15826 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15827 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15830 if (Subtarget->hasInt256())
15831 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15833 // Optimize vectors in AVX mode
15834 // Sign extend v8i16 to v8i32 and
15837 // Divide input vector into two parts
15838 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15839 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15840 // concat the vectors to original VT
15842 unsigned NumElems = InVT.getVectorNumElements();
15843 SDValue Undef = DAG.getUNDEF(InVT);
15845 SmallVector<int,8> ShufMask1(NumElems, -1);
15846 for (unsigned i = 0; i != NumElems/2; ++i)
15849 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15851 SmallVector<int,8> ShufMask2(NumElems, -1);
15852 for (unsigned i = 0; i != NumElems/2; ++i)
15853 ShufMask2[i] = i + NumElems/2;
15855 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15857 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15858 VT.getVectorNumElements()/2);
15860 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15861 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15863 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15866 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15867 // may emit an illegal shuffle but the expansion is still better than scalar
15868 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15869 // we'll emit a shuffle and a arithmetic shift.
15870 // TODO: It is possible to support ZExt by zeroing the undef values during
15871 // the shuffle phase or after the shuffle.
15872 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15873 SelectionDAG &DAG) {
15874 MVT RegVT = Op.getSimpleValueType();
15875 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15876 assert(RegVT.isInteger() &&
15877 "We only custom lower integer vector sext loads.");
15879 // Nothing useful we can do without SSE2 shuffles.
15880 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15882 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15884 EVT MemVT = Ld->getMemoryVT();
15885 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15886 unsigned RegSz = RegVT.getSizeInBits();
15888 ISD::LoadExtType Ext = Ld->getExtensionType();
15890 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15891 && "Only anyext and sext are currently implemented.");
15892 assert(MemVT != RegVT && "Cannot extend to the same type");
15893 assert(MemVT.isVector() && "Must load a vector from memory");
15895 unsigned NumElems = RegVT.getVectorNumElements();
15896 unsigned MemSz = MemVT.getSizeInBits();
15897 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15899 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15900 // The only way in which we have a legal 256-bit vector result but not the
15901 // integer 256-bit operations needed to directly lower a sextload is if we
15902 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15903 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15904 // correctly legalized. We do this late to allow the canonical form of
15905 // sextload to persist throughout the rest of the DAG combiner -- it wants
15906 // to fold together any extensions it can, and so will fuse a sign_extend
15907 // of an sextload into a sextload targeting a wider value.
15909 if (MemSz == 128) {
15910 // Just switch this to a normal load.
15911 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15912 "it must be a legal 128-bit vector "
15914 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15915 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15916 Ld->isInvariant(), Ld->getAlignment());
15918 assert(MemSz < 128 &&
15919 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15920 // Do an sext load to a 128-bit vector type. We want to use the same
15921 // number of elements, but elements half as wide. This will end up being
15922 // recursively lowered by this routine, but will succeed as we definitely
15923 // have all the necessary features if we're using AVX1.
15925 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15926 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15928 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15929 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15930 Ld->isNonTemporal(), Ld->isInvariant(),
15931 Ld->getAlignment());
15934 // Replace chain users with the new chain.
15935 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15936 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15938 // Finally, do a normal sign-extend to the desired register.
15939 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15942 // All sizes must be a power of two.
15943 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15944 "Non-power-of-two elements are not custom lowered!");
15946 // Attempt to load the original value using scalar loads.
15947 // Find the largest scalar type that divides the total loaded size.
15948 MVT SclrLoadTy = MVT::i8;
15949 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
15950 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
15951 MVT Tp = (MVT::SimpleValueType)tp;
15952 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15957 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15958 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15960 SclrLoadTy = MVT::f64;
15962 // Calculate the number of scalar loads that we need to perform
15963 // in order to load our vector from memory.
15964 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15966 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15967 "Can only lower sext loads with a single scalar load!");
15969 unsigned loadRegZize = RegSz;
15970 if (Ext == ISD::SEXTLOAD && RegSz == 256)
15973 // Represent our vector as a sequence of elements which are the
15974 // largest scalar that we can load.
15975 EVT LoadUnitVecVT = EVT::getVectorVT(
15976 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15978 // Represent the data using the same element type that is stored in
15979 // memory. In practice, we ''widen'' MemVT.
15981 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15982 loadRegZize / MemVT.getScalarType().getSizeInBits());
15984 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15985 "Invalid vector type");
15987 // We can't shuffle using an illegal type.
15988 assert(TLI.isTypeLegal(WideVecVT) &&
15989 "We only lower types that form legal widened vector types");
15991 SmallVector<SDValue, 8> Chains;
15992 SDValue Ptr = Ld->getBasePtr();
15993 SDValue Increment =
15994 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());
15995 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15997 for (unsigned i = 0; i < NumLoads; ++i) {
15998 // Perform a single load.
15999 SDValue ScalarLoad =
16000 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
16001 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
16002 Ld->getAlignment());
16003 Chains.push_back(ScalarLoad.getValue(1));
16004 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16005 // another round of DAGCombining.
16007 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16009 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16010 ScalarLoad, DAG.getIntPtrConstant(i));
16012 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16015 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
16017 // Bitcast the loaded value to a vector of the original element type, in
16018 // the size of the target vector type.
16019 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16020 unsigned SizeRatio = RegSz / MemSz;
16022 if (Ext == ISD::SEXTLOAD) {
16023 // If we have SSE4.1, we can directly emit a VSEXT node.
16024 if (Subtarget->hasSSE41()) {
16025 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16026 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16030 // Otherwise we'll shuffle the small elements in the high bits of the
16031 // larger type and perform an arithmetic shift. If the shift is not legal
16032 // it's better to scalarize.
16033 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
16034 "We can't implement a sext load without an arithmetic right shift!");
16036 // Redistribute the loaded elements into the different locations.
16037 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16038 for (unsigned i = 0; i != NumElems; ++i)
16039 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
16041 SDValue Shuff = DAG.getVectorShuffle(
16042 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16044 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16046 // Build the arithmetic shift.
16047 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16048 MemVT.getVectorElementType().getSizeInBits();
16050 DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));
16052 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16056 // Redistribute the loaded elements into the different locations.
16057 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
16058 for (unsigned i = 0; i != NumElems; ++i)
16059 ShuffleVec[i * SizeRatio] = i;
16061 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16062 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
16064 // Bitcast to the requested type.
16065 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16066 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
16070 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
16071 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
16072 // from the AND / OR.
16073 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
16074 Opc = Op.getOpcode();
16075 if (Opc != ISD::OR && Opc != ISD::AND)
16077 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16078 Op.getOperand(0).hasOneUse() &&
16079 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
16080 Op.getOperand(1).hasOneUse());
16083 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
16084 // 1 and that the SETCC node has a single use.
16085 static bool isXor1OfSetCC(SDValue Op) {
16086 if (Op.getOpcode() != ISD::XOR)
16088 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
16089 if (N1C && N1C->getAPIntValue() == 1) {
16090 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
16091 Op.getOperand(0).hasOneUse();
16096 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
16097 bool addTest = true;
16098 SDValue Chain = Op.getOperand(0);
16099 SDValue Cond = Op.getOperand(1);
16100 SDValue Dest = Op.getOperand(2);
16103 bool Inverted = false;
16105 if (Cond.getOpcode() == ISD::SETCC) {
16106 // Check for setcc([su]{add,sub,mul}o == 0).
16107 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
16108 isa<ConstantSDNode>(Cond.getOperand(1)) &&
16109 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
16110 Cond.getOperand(0).getResNo() == 1 &&
16111 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
16112 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
16113 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
16114 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
16115 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
16116 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
16118 Cond = Cond.getOperand(0);
16120 SDValue NewCond = LowerSETCC(Cond, DAG);
16121 if (NewCond.getNode())
16126 // FIXME: LowerXALUO doesn't handle these!!
16127 else if (Cond.getOpcode() == X86ISD::ADD ||
16128 Cond.getOpcode() == X86ISD::SUB ||
16129 Cond.getOpcode() == X86ISD::SMUL ||
16130 Cond.getOpcode() == X86ISD::UMUL)
16131 Cond = LowerXALUO(Cond, DAG);
16134 // Look pass (and (setcc_carry (cmp ...)), 1).
16135 if (Cond.getOpcode() == ISD::AND &&
16136 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
16137 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
16138 if (C && C->getAPIntValue() == 1)
16139 Cond = Cond.getOperand(0);
16142 // If condition flag is set by a X86ISD::CMP, then use it as the condition
16143 // setting operand in place of the X86ISD::SETCC.
16144 unsigned CondOpcode = Cond.getOpcode();
16145 if (CondOpcode == X86ISD::SETCC ||
16146 CondOpcode == X86ISD::SETCC_CARRY) {
16147 CC = Cond.getOperand(0);
16149 SDValue Cmp = Cond.getOperand(1);
16150 unsigned Opc = Cmp.getOpcode();
16151 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
16152 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
16156 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
16160 // These can only come from an arithmetic instruction with overflow,
16161 // e.g. SADDO, UADDO.
16162 Cond = Cond.getNode()->getOperand(1);
16168 CondOpcode = Cond.getOpcode();
16169 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
16170 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
16171 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
16172 Cond.getOperand(0).getValueType() != MVT::i8)) {
16173 SDValue LHS = Cond.getOperand(0);
16174 SDValue RHS = Cond.getOperand(1);
16175 unsigned X86Opcode;
16178 // Keep this in sync with LowerXALUO, otherwise we might create redundant
16179 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
16181 switch (CondOpcode) {
16182 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
16184 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16186 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
16189 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
16190 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
16192 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
16194 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
16197 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
16198 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
16199 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
16200 default: llvm_unreachable("unexpected overflowing operator");
16203 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
16204 if (CondOpcode == ISD::UMULO)
16205 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
16208 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
16210 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
16212 if (CondOpcode == ISD::UMULO)
16213 Cond = X86Op.getValue(2);
16215 Cond = X86Op.getValue(1);
16217 CC = DAG.getConstant(X86Cond, MVT::i8);
16221 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
16222 SDValue Cmp = Cond.getOperand(0).getOperand(1);
16223 if (CondOpc == ISD::OR) {
16224 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
16225 // two branches instead of an explicit OR instruction with a
16227 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16228 isX86LogicalCmp(Cmp)) {
16229 CC = Cond.getOperand(0).getOperand(0);
16230 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16231 Chain, Dest, CC, Cmp);
16232 CC = Cond.getOperand(1).getOperand(0);
16236 } else { // ISD::AND
16237 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
16238 // two branches instead of an explicit AND instruction with a
16239 // separate test. However, we only do this if this block doesn't
16240 // have a fall-through edge, because this requires an explicit
16241 // jmp when the condition is false.
16242 if (Cmp == Cond.getOperand(1).getOperand(1) &&
16243 isX86LogicalCmp(Cmp) &&
16244 Op.getNode()->hasOneUse()) {
16245 X86::CondCode CCode =
16246 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16247 CCode = X86::GetOppositeBranchCondition(CCode);
16248 CC = DAG.getConstant(CCode, MVT::i8);
16249 SDNode *User = *Op.getNode()->use_begin();
16250 // Look for an unconditional branch following this conditional branch.
16251 // We need this because we need to reverse the successors in order
16252 // to implement FCMP_OEQ.
16253 if (User->getOpcode() == ISD::BR) {
16254 SDValue FalseBB = User->getOperand(1);
16256 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16257 assert(NewBR == User);
16261 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16262 Chain, Dest, CC, Cmp);
16263 X86::CondCode CCode =
16264 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
16265 CCode = X86::GetOppositeBranchCondition(CCode);
16266 CC = DAG.getConstant(CCode, MVT::i8);
16272 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
16273 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
16274 // It should be transformed during dag combiner except when the condition
16275 // is set by a arithmetics with overflow node.
16276 X86::CondCode CCode =
16277 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
16278 CCode = X86::GetOppositeBranchCondition(CCode);
16279 CC = DAG.getConstant(CCode, MVT::i8);
16280 Cond = Cond.getOperand(0).getOperand(1);
16282 } else if (Cond.getOpcode() == ISD::SETCC &&
16283 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
16284 // For FCMP_OEQ, we can emit
16285 // two branches instead of an explicit AND instruction with a
16286 // separate test. However, we only do this if this block doesn't
16287 // have a fall-through edge, because this requires an explicit
16288 // jmp when the condition is false.
16289 if (Op.getNode()->hasOneUse()) {
16290 SDNode *User = *Op.getNode()->use_begin();
16291 // Look for an unconditional branch following this conditional branch.
16292 // We need this because we need to reverse the successors in order
16293 // to implement FCMP_OEQ.
16294 if (User->getOpcode() == ISD::BR) {
16295 SDValue FalseBB = User->getOperand(1);
16297 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16298 assert(NewBR == User);
16302 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16303 Cond.getOperand(0), Cond.getOperand(1));
16304 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16305 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16306 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16307 Chain, Dest, CC, Cmp);
16308 CC = DAG.getConstant(X86::COND_P, MVT::i8);
16313 } else if (Cond.getOpcode() == ISD::SETCC &&
16314 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
16315 // For FCMP_UNE, we can emit
16316 // two branches instead of an explicit AND instruction with a
16317 // separate test. However, we only do this if this block doesn't
16318 // have a fall-through edge, because this requires an explicit
16319 // jmp when the condition is false.
16320 if (Op.getNode()->hasOneUse()) {
16321 SDNode *User = *Op.getNode()->use_begin();
16322 // Look for an unconditional branch following this conditional branch.
16323 // We need this because we need to reverse the successors in order
16324 // to implement FCMP_UNE.
16325 if (User->getOpcode() == ISD::BR) {
16326 SDValue FalseBB = User->getOperand(1);
16328 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
16329 assert(NewBR == User);
16332 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
16333 Cond.getOperand(0), Cond.getOperand(1));
16334 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
16335 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
16336 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16337 Chain, Dest, CC, Cmp);
16338 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
16348 // Look pass the truncate if the high bits are known zero.
16349 if (isTruncWithZeroHighBitsInput(Cond, DAG))
16350 Cond = Cond.getOperand(0);
16352 // We know the result of AND is compared against zero. Try to match
16354 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
16355 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
16356 if (NewSetCC.getNode()) {
16357 CC = NewSetCC.getOperand(0);
16358 Cond = NewSetCC.getOperand(1);
16365 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
16366 CC = DAG.getConstant(X86Cond, MVT::i8);
16367 Cond = EmitTest(Cond, X86Cond, dl, DAG);
16369 Cond = ConvertCmpIfNecessary(Cond, DAG);
16370 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
16371 Chain, Dest, CC, Cond);
16374 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
16375 // Calls to _alloca are needed to probe the stack when allocating more than 4k
16376 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
16377 // that the guard pages used by the OS virtual memory manager are allocated in
16378 // correct sequence.
16380 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
16381 SelectionDAG &DAG) const {
16382 MachineFunction &MF = DAG.getMachineFunction();
16383 bool SplitStack = MF.shouldSplitStack();
16384 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
16389 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16390 SDNode* Node = Op.getNode();
16392 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
16393 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
16394 " not tell us which reg is the stack pointer!");
16395 EVT VT = Node->getValueType(0);
16396 SDValue Tmp1 = SDValue(Node, 0);
16397 SDValue Tmp2 = SDValue(Node, 1);
16398 SDValue Tmp3 = Node->getOperand(2);
16399 SDValue Chain = Tmp1.getOperand(0);
16401 // Chain the dynamic stack allocation so that it doesn't modify the stack
16402 // pointer when other instructions are using the stack.
16403 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
16406 SDValue Size = Tmp2.getOperand(1);
16407 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
16408 Chain = SP.getValue(1);
16409 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
16410 const TargetFrameLowering &TFI = *DAG.getSubtarget().getFrameLowering();
16411 unsigned StackAlign = TFI.getStackAlignment();
16412 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
16413 if (Align > StackAlign)
16414 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
16415 DAG.getConstant(-(uint64_t)Align, VT));
16416 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
16418 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
16419 DAG.getIntPtrConstant(0, true), SDValue(),
16422 SDValue Ops[2] = { Tmp1, Tmp2 };
16423 return DAG.getMergeValues(Ops, dl);
16427 SDValue Chain = Op.getOperand(0);
16428 SDValue Size = Op.getOperand(1);
16429 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
16430 EVT VT = Op.getNode()->getValueType(0);
16432 bool Is64Bit = Subtarget->is64Bit();
16433 EVT SPTy = getPointerTy();
16436 MachineRegisterInfo &MRI = MF.getRegInfo();
16439 // The 64 bit implementation of segmented stacks needs to clobber both r10
16440 // r11. This makes it impossible to use it along with nested parameters.
16441 const Function *F = MF.getFunction();
16443 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
16445 if (I->hasNestAttr())
16446 report_fatal_error("Cannot use segmented stacks with functions that "
16447 "have nested arguments.");
16450 const TargetRegisterClass *AddrRegClass =
16451 getRegClassFor(getPointerTy());
16452 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
16453 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
16454 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
16455 DAG.getRegister(Vreg, SPTy));
16456 SDValue Ops1[2] = { Value, Chain };
16457 return DAG.getMergeValues(Ops1, dl);
16460 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
16462 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
16463 Flag = Chain.getValue(1);
16464 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
16466 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
16468 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
16469 DAG.getSubtarget().getRegisterInfo());
16470 unsigned SPReg = RegInfo->getStackRegister();
16471 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
16472 Chain = SP.getValue(1);
16475 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
16476 DAG.getConstant(-(uint64_t)Align, VT));
16477 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
16480 SDValue Ops1[2] = { SP, Chain };
16481 return DAG.getMergeValues(Ops1, dl);
16485 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
16486 MachineFunction &MF = DAG.getMachineFunction();
16487 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16489 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16492 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
16493 // vastart just stores the address of the VarArgsFrameIndex slot into the
16494 // memory location argument.
16495 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16497 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
16498 MachinePointerInfo(SV), false, false, 0);
16502 // gp_offset (0 - 6 * 8)
16503 // fp_offset (48 - 48 + 8 * 16)
16504 // overflow_arg_area (point to parameters coming in memory).
16506 SmallVector<SDValue, 8> MemOps;
16507 SDValue FIN = Op.getOperand(1);
16509 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16510 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16512 FIN, MachinePointerInfo(SV), false, false, 0);
16513 MemOps.push_back(Store);
16516 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16517 FIN, DAG.getIntPtrConstant(4));
16518 Store = DAG.getStore(Op.getOperand(0), DL,
16519 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
16521 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16522 MemOps.push_back(Store);
16524 // Store ptr to overflow_arg_area
16525 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16526 FIN, DAG.getIntPtrConstant(4));
16527 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
16529 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16530 MachinePointerInfo(SV, 8),
16532 MemOps.push_back(Store);
16534 // Store ptr to reg_save_area.
16535 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
16536 FIN, DAG.getIntPtrConstant(8));
16537 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
16539 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
16540 MachinePointerInfo(SV, 16), false, false, 0);
16541 MemOps.push_back(Store);
16542 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16545 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16546 assert(Subtarget->is64Bit() &&
16547 "LowerVAARG only handles 64-bit va_arg!");
16548 assert((Subtarget->isTargetLinux() ||
16549 Subtarget->isTargetDarwin()) &&
16550 "Unhandled target in LowerVAARG");
16551 assert(Op.getNode()->getNumOperands() == 4);
16552 SDValue Chain = Op.getOperand(0);
16553 SDValue SrcPtr = Op.getOperand(1);
16554 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16555 unsigned Align = Op.getConstantOperandVal(3);
16558 EVT ArgVT = Op.getNode()->getValueType(0);
16559 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16560 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
16563 // Decide which area this value should be read from.
16564 // TODO: Implement the AMD64 ABI in its entirety. This simple
16565 // selection mechanism works only for the basic types.
16566 if (ArgVT == MVT::f80) {
16567 llvm_unreachable("va_arg for f80 not yet implemented");
16568 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16569 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16570 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16571 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16573 llvm_unreachable("Unhandled argument type in LowerVAARG");
16576 if (ArgMode == 2) {
16577 // Sanity Check: Make sure using fp_offset makes sense.
16578 assert(!DAG.getTarget().Options.UseSoftFloat &&
16579 !(DAG.getMachineFunction()
16580 .getFunction()->getAttributes()
16581 .hasAttribute(AttributeSet::FunctionIndex,
16582 Attribute::NoImplicitFloat)) &&
16583 Subtarget->hasSSE1());
16586 // Insert VAARG_64 node into the DAG
16587 // VAARG_64 returns two values: Variable Argument Address, Chain
16588 SmallVector<SDValue, 11> InstOps;
16589 InstOps.push_back(Chain);
16590 InstOps.push_back(SrcPtr);
16591 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
16592 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
16593 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
16594 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
16595 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16596 VTs, InstOps, MVT::i64,
16597 MachinePointerInfo(SV),
16599 /*Volatile=*/false,
16601 /*WriteMem=*/true);
16602 Chain = VAARG.getValue(1);
16604 // Load the next argument and return it
16605 return DAG.getLoad(ArgVT, dl,
16608 MachinePointerInfo(),
16609 false, false, false, 0);
16612 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16613 SelectionDAG &DAG) {
16614 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
16615 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16616 SDValue Chain = Op.getOperand(0);
16617 SDValue DstPtr = Op.getOperand(1);
16618 SDValue SrcPtr = Op.getOperand(2);
16619 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16620 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16623 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16624 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
16626 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16629 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16630 // amount is a constant. Takes immediate version of shift as input.
16631 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16632 SDValue SrcOp, uint64_t ShiftAmt,
16633 SelectionDAG &DAG) {
16634 MVT ElementType = VT.getVectorElementType();
16636 // Fold this packed shift into its first operand if ShiftAmt is 0.
16640 // Check for ShiftAmt >= element width
16641 if (ShiftAmt >= ElementType.getSizeInBits()) {
16642 if (Opc == X86ISD::VSRAI)
16643 ShiftAmt = ElementType.getSizeInBits() - 1;
16645 return DAG.getConstant(0, VT);
16648 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16649 && "Unknown target vector shift-by-constant node");
16651 // Fold this packed vector shift into a build vector if SrcOp is a
16652 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16653 if (VT == SrcOp.getSimpleValueType() &&
16654 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16655 SmallVector<SDValue, 8> Elts;
16656 unsigned NumElts = SrcOp->getNumOperands();
16657 ConstantSDNode *ND;
16660 default: llvm_unreachable(nullptr);
16661 case X86ISD::VSHLI:
16662 for (unsigned i=0; i!=NumElts; ++i) {
16663 SDValue CurrentOp = SrcOp->getOperand(i);
16664 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16665 Elts.push_back(CurrentOp);
16668 ND = cast<ConstantSDNode>(CurrentOp);
16669 const APInt &C = ND->getAPIntValue();
16670 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));
16673 case X86ISD::VSRLI:
16674 for (unsigned i=0; i!=NumElts; ++i) {
16675 SDValue CurrentOp = SrcOp->getOperand(i);
16676 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16677 Elts.push_back(CurrentOp);
16680 ND = cast<ConstantSDNode>(CurrentOp);
16681 const APInt &C = ND->getAPIntValue();
16682 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));
16685 case X86ISD::VSRAI:
16686 for (unsigned i=0; i!=NumElts; ++i) {
16687 SDValue CurrentOp = SrcOp->getOperand(i);
16688 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16689 Elts.push_back(CurrentOp);
16692 ND = cast<ConstantSDNode>(CurrentOp);
16693 const APInt &C = ND->getAPIntValue();
16694 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));
16699 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16702 return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));
16705 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16706 // may or may not be a constant. Takes immediate version of shift as input.
16707 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16708 SDValue SrcOp, SDValue ShAmt,
16709 SelectionDAG &DAG) {
16710 MVT SVT = ShAmt.getSimpleValueType();
16711 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16713 // Catch shift-by-constant.
16714 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16715 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16716 CShAmt->getZExtValue(), DAG);
16718 // Change opcode to non-immediate version
16720 default: llvm_unreachable("Unknown target vector shift node");
16721 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16722 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16723 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16726 const X86Subtarget &Subtarget =
16727 DAG.getTarget().getSubtarget<X86Subtarget>();
16728 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16729 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16730 // Let the shuffle legalizer expand this shift amount node.
16731 SDValue Op0 = ShAmt.getOperand(0);
16732 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16733 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16735 // Need to build a vector containing shift amount.
16736 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16737 SmallVector<SDValue, 4> ShOps;
16738 ShOps.push_back(ShAmt);
16739 if (SVT == MVT::i32) {
16740 ShOps.push_back(DAG.getConstant(0, SVT));
16741 ShOps.push_back(DAG.getUNDEF(SVT));
16743 ShOps.push_back(DAG.getUNDEF(SVT));
16745 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16746 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16749 // The return type has to be a 128-bit type with the same element
16750 // type as the input type.
16751 MVT EltVT = VT.getVectorElementType();
16752 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16754 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
16755 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16758 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16759 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16760 /// necessary casting for \p Mask when lowering masking intrinsics.
16761 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16762 SDValue PreservedSrc,
16763 const X86Subtarget *Subtarget,
16764 SelectionDAG &DAG) {
16765 EVT VT = Op.getValueType();
16766 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16767 MVT::i1, VT.getVectorNumElements());
16768 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16769 Mask.getValueType().getSizeInBits());
16772 assert(MaskVT.isSimple() && "invalid mask type");
16774 if (isAllOnes(Mask))
16777 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16778 // are extracted by EXTRACT_SUBVECTOR.
16779 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16780 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16781 DAG.getIntPtrConstant(0));
16783 switch (Op.getOpcode()) {
16785 case X86ISD::PCMPEQM:
16786 case X86ISD::PCMPGTM:
16788 case X86ISD::CMPMU:
16789 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16791 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16792 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16793 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
16796 /// \brief Creates an SDNode for a predicated scalar operation.
16797 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16798 /// The mask is comming as MVT::i8 and it should be truncated
16799 /// to MVT::i1 while lowering masking intrinsics.
16800 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16801 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
16802 /// a scalar instruction.
16803 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16804 SDValue PreservedSrc,
16805 const X86Subtarget *Subtarget,
16806 SelectionDAG &DAG) {
16807 if (isAllOnes(Mask))
16810 EVT VT = Op.getValueType();
16812 // The mask should be of type MVT::i1
16813 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16815 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16816 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16817 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16820 static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
16822 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16823 case Intrinsic::x86_fma_vfmadd_ps:
16824 case Intrinsic::x86_fma_vfmadd_pd:
16825 case Intrinsic::x86_fma_vfmadd_ps_256:
16826 case Intrinsic::x86_fma_vfmadd_pd_256:
16827 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
16828 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
16829 return X86ISD::FMADD;
16830 case Intrinsic::x86_fma_vfmsub_ps:
16831 case Intrinsic::x86_fma_vfmsub_pd:
16832 case Intrinsic::x86_fma_vfmsub_ps_256:
16833 case Intrinsic::x86_fma_vfmsub_pd_256:
16834 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
16835 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
16836 return X86ISD::FMSUB;
16837 case Intrinsic::x86_fma_vfnmadd_ps:
16838 case Intrinsic::x86_fma_vfnmadd_pd:
16839 case Intrinsic::x86_fma_vfnmadd_ps_256:
16840 case Intrinsic::x86_fma_vfnmadd_pd_256:
16841 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
16842 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
16843 return X86ISD::FNMADD;
16844 case Intrinsic::x86_fma_vfnmsub_ps:
16845 case Intrinsic::x86_fma_vfnmsub_pd:
16846 case Intrinsic::x86_fma_vfnmsub_ps_256:
16847 case Intrinsic::x86_fma_vfnmsub_pd_256:
16848 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
16849 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
16850 return X86ISD::FNMSUB;
16851 case Intrinsic::x86_fma_vfmaddsub_ps:
16852 case Intrinsic::x86_fma_vfmaddsub_pd:
16853 case Intrinsic::x86_fma_vfmaddsub_ps_256:
16854 case Intrinsic::x86_fma_vfmaddsub_pd_256:
16855 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
16856 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
16857 return X86ISD::FMADDSUB;
16858 case Intrinsic::x86_fma_vfmsubadd_ps:
16859 case Intrinsic::x86_fma_vfmsubadd_pd:
16860 case Intrinsic::x86_fma_vfmsubadd_ps_256:
16861 case Intrinsic::x86_fma_vfmsubadd_pd_256:
16862 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
16863 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512:
16864 return X86ISD::FMSUBADD;
16868 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16869 SelectionDAG &DAG) {
16871 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16872 EVT VT = Op.getValueType();
16873 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16875 switch(IntrData->Type) {
16876 case INTR_TYPE_1OP:
16877 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16878 case INTR_TYPE_2OP:
16879 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16881 case INTR_TYPE_3OP:
16882 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16883 Op.getOperand(2), Op.getOperand(3));
16884 case INTR_TYPE_1OP_MASK_RM: {
16885 SDValue Src = Op.getOperand(1);
16886 SDValue Src0 = Op.getOperand(2);
16887 SDValue Mask = Op.getOperand(3);
16888 SDValue RoundingMode = Op.getOperand(4);
16889 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16891 Mask, Src0, Subtarget, DAG);
16893 case INTR_TYPE_SCALAR_MASK_RM: {
16894 SDValue Src1 = Op.getOperand(1);
16895 SDValue Src2 = Op.getOperand(2);
16896 SDValue Src0 = Op.getOperand(3);
16897 SDValue Mask = Op.getOperand(4);
16898 SDValue RoundingMode = Op.getOperand(5);
16899 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16901 Mask, Src0, Subtarget, DAG);
16903 case INTR_TYPE_2OP_MASK: {
16904 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),
16906 Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);
16909 case CMP_MASK_CC: {
16910 // Comparison intrinsics with masks.
16911 // Example of transformation:
16912 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16913 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16915 // (v8i1 (insert_subvector undef,
16916 // (v2i1 (and (PCMPEQM %a, %b),
16917 // (extract_subvector
16918 // (v8i1 (bitcast %mask)), 0))), 0))))
16919 EVT VT = Op.getOperand(1).getValueType();
16920 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16921 VT.getVectorNumElements());
16922 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16923 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16924 Mask.getValueType().getSizeInBits());
16926 if (IntrData->Type == CMP_MASK_CC) {
16927 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16928 Op.getOperand(2), Op.getOperand(3));
16930 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16931 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16934 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16935 DAG.getTargetConstant(0, MaskVT),
16937 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16938 DAG.getUNDEF(BitcastVT), CmpMask,
16939 DAG.getIntPtrConstant(0));
16940 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
16942 case COMI: { // Comparison intrinsics
16943 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16944 SDValue LHS = Op.getOperand(1);
16945 SDValue RHS = Op.getOperand(2);
16946 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
16947 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16948 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16949 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16950 DAG.getConstant(X86CC, MVT::i8), Cond);
16951 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16954 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16955 Op.getOperand(1), Op.getOperand(2), DAG);
16957 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16958 Op.getSimpleValueType(),
16960 Op.getOperand(2), DAG),
16961 Op.getOperand(4), Op.getOperand(3), Subtarget,
16963 case COMPRESS_TO_REG: {
16964 SDValue Mask = Op.getOperand(3);
16965 SDValue DataToCompress = Op.getOperand(1);
16966 SDValue PassThru = Op.getOperand(2);
16967 if (isAllOnes(Mask)) // return data as is
16968 return Op.getOperand(1);
16969 EVT VT = Op.getValueType();
16970 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16971 VT.getVectorNumElements());
16972 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16973 Mask.getValueType().getSizeInBits());
16975 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16976 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
16977 DAG.getIntPtrConstant(0));
16979 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,
16988 default: return SDValue(); // Don't custom lower most intrinsics.
16990 case Intrinsic::x86_avx512_mask_valign_q_512:
16991 case Intrinsic::x86_avx512_mask_valign_d_512:
16992 // Vector source operands are swapped.
16993 return getVectorMaskingNode(DAG.getNode(X86ISD::VALIGN, dl,
16994 Op.getValueType(), Op.getOperand(2),
16997 Op.getOperand(5), Op.getOperand(4),
17000 // ptest and testp intrinsics. The intrinsic these come from are designed to
17001 // return an integer value, not just an instruction so lower it to the ptest
17002 // or testp pattern and a setcc for the result.
17003 case Intrinsic::x86_sse41_ptestz:
17004 case Intrinsic::x86_sse41_ptestc:
17005 case Intrinsic::x86_sse41_ptestnzc:
17006 case Intrinsic::x86_avx_ptestz_256:
17007 case Intrinsic::x86_avx_ptestc_256:
17008 case Intrinsic::x86_avx_ptestnzc_256:
17009 case Intrinsic::x86_avx_vtestz_ps:
17010 case Intrinsic::x86_avx_vtestc_ps:
17011 case Intrinsic::x86_avx_vtestnzc_ps:
17012 case Intrinsic::x86_avx_vtestz_pd:
17013 case Intrinsic::x86_avx_vtestc_pd:
17014 case Intrinsic::x86_avx_vtestnzc_pd:
17015 case Intrinsic::x86_avx_vtestz_ps_256:
17016 case Intrinsic::x86_avx_vtestc_ps_256:
17017 case Intrinsic::x86_avx_vtestnzc_ps_256:
17018 case Intrinsic::x86_avx_vtestz_pd_256:
17019 case Intrinsic::x86_avx_vtestc_pd_256:
17020 case Intrinsic::x86_avx_vtestnzc_pd_256: {
17021 bool IsTestPacked = false;
17024 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
17025 case Intrinsic::x86_avx_vtestz_ps:
17026 case Intrinsic::x86_avx_vtestz_pd:
17027 case Intrinsic::x86_avx_vtestz_ps_256:
17028 case Intrinsic::x86_avx_vtestz_pd_256:
17029 IsTestPacked = true; // Fallthrough
17030 case Intrinsic::x86_sse41_ptestz:
17031 case Intrinsic::x86_avx_ptestz_256:
17033 X86CC = X86::COND_E;
17035 case Intrinsic::x86_avx_vtestc_ps:
17036 case Intrinsic::x86_avx_vtestc_pd:
17037 case Intrinsic::x86_avx_vtestc_ps_256:
17038 case Intrinsic::x86_avx_vtestc_pd_256:
17039 IsTestPacked = true; // Fallthrough
17040 case Intrinsic::x86_sse41_ptestc:
17041 case Intrinsic::x86_avx_ptestc_256:
17043 X86CC = X86::COND_B;
17045 case Intrinsic::x86_avx_vtestnzc_ps:
17046 case Intrinsic::x86_avx_vtestnzc_pd:
17047 case Intrinsic::x86_avx_vtestnzc_ps_256:
17048 case Intrinsic::x86_avx_vtestnzc_pd_256:
17049 IsTestPacked = true; // Fallthrough
17050 case Intrinsic::x86_sse41_ptestnzc:
17051 case Intrinsic::x86_avx_ptestnzc_256:
17053 X86CC = X86::COND_A;
17057 SDValue LHS = Op.getOperand(1);
17058 SDValue RHS = Op.getOperand(2);
17059 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17060 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17061 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17062 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17063 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17065 case Intrinsic::x86_avx512_kortestz_w:
17066 case Intrinsic::x86_avx512_kortestc_w: {
17067 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17068 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));
17069 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));
17070 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
17071 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17072 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17073 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17076 case Intrinsic::x86_sse42_pcmpistria128:
17077 case Intrinsic::x86_sse42_pcmpestria128:
17078 case Intrinsic::x86_sse42_pcmpistric128:
17079 case Intrinsic::x86_sse42_pcmpestric128:
17080 case Intrinsic::x86_sse42_pcmpistrio128:
17081 case Intrinsic::x86_sse42_pcmpestrio128:
17082 case Intrinsic::x86_sse42_pcmpistris128:
17083 case Intrinsic::x86_sse42_pcmpestris128:
17084 case Intrinsic::x86_sse42_pcmpistriz128:
17085 case Intrinsic::x86_sse42_pcmpestriz128: {
17089 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17090 case Intrinsic::x86_sse42_pcmpistria128:
17091 Opcode = X86ISD::PCMPISTRI;
17092 X86CC = X86::COND_A;
17094 case Intrinsic::x86_sse42_pcmpestria128:
17095 Opcode = X86ISD::PCMPESTRI;
17096 X86CC = X86::COND_A;
17098 case Intrinsic::x86_sse42_pcmpistric128:
17099 Opcode = X86ISD::PCMPISTRI;
17100 X86CC = X86::COND_B;
17102 case Intrinsic::x86_sse42_pcmpestric128:
17103 Opcode = X86ISD::PCMPESTRI;
17104 X86CC = X86::COND_B;
17106 case Intrinsic::x86_sse42_pcmpistrio128:
17107 Opcode = X86ISD::PCMPISTRI;
17108 X86CC = X86::COND_O;
17110 case Intrinsic::x86_sse42_pcmpestrio128:
17111 Opcode = X86ISD::PCMPESTRI;
17112 X86CC = X86::COND_O;
17114 case Intrinsic::x86_sse42_pcmpistris128:
17115 Opcode = X86ISD::PCMPISTRI;
17116 X86CC = X86::COND_S;
17118 case Intrinsic::x86_sse42_pcmpestris128:
17119 Opcode = X86ISD::PCMPESTRI;
17120 X86CC = X86::COND_S;
17122 case Intrinsic::x86_sse42_pcmpistriz128:
17123 Opcode = X86ISD::PCMPISTRI;
17124 X86CC = X86::COND_E;
17126 case Intrinsic::x86_sse42_pcmpestriz128:
17127 Opcode = X86ISD::PCMPESTRI;
17128 X86CC = X86::COND_E;
17131 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17132 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17133 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17134 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17135 DAG.getConstant(X86CC, MVT::i8),
17136 SDValue(PCMP.getNode(), 1));
17137 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17140 case Intrinsic::x86_sse42_pcmpistri128:
17141 case Intrinsic::x86_sse42_pcmpestri128: {
17143 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17144 Opcode = X86ISD::PCMPISTRI;
17146 Opcode = X86ISD::PCMPESTRI;
17148 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17149 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17150 return DAG.getNode(Opcode, dl, VTs, NewOps);
17153 case Intrinsic::x86_fma_mask_vfmadd_ps_512:
17154 case Intrinsic::x86_fma_mask_vfmadd_pd_512:
17155 case Intrinsic::x86_fma_mask_vfmsub_ps_512:
17156 case Intrinsic::x86_fma_mask_vfmsub_pd_512:
17157 case Intrinsic::x86_fma_mask_vfnmadd_ps_512:
17158 case Intrinsic::x86_fma_mask_vfnmadd_pd_512:
17159 case Intrinsic::x86_fma_mask_vfnmsub_ps_512:
17160 case Intrinsic::x86_fma_mask_vfnmsub_pd_512:
17161 case Intrinsic::x86_fma_mask_vfmaddsub_ps_512:
17162 case Intrinsic::x86_fma_mask_vfmaddsub_pd_512:
17163 case Intrinsic::x86_fma_mask_vfmsubadd_ps_512:
17164 case Intrinsic::x86_fma_mask_vfmsubadd_pd_512: {
17165 auto *SAE = cast<ConstantSDNode>(Op.getOperand(5));
17166 if (SAE->getZExtValue() == X86::STATIC_ROUNDING::CUR_DIRECTION)
17167 return getVectorMaskingNode(DAG.getNode(getOpcodeForFMAIntrinsic(IntNo),
17168 dl, Op.getValueType(),
17172 Op.getOperand(4), Op.getOperand(1),
17178 case Intrinsic::x86_fma_vfmadd_ps:
17179 case Intrinsic::x86_fma_vfmadd_pd:
17180 case Intrinsic::x86_fma_vfmsub_ps:
17181 case Intrinsic::x86_fma_vfmsub_pd:
17182 case Intrinsic::x86_fma_vfnmadd_ps:
17183 case Intrinsic::x86_fma_vfnmadd_pd:
17184 case Intrinsic::x86_fma_vfnmsub_ps:
17185 case Intrinsic::x86_fma_vfnmsub_pd:
17186 case Intrinsic::x86_fma_vfmaddsub_ps:
17187 case Intrinsic::x86_fma_vfmaddsub_pd:
17188 case Intrinsic::x86_fma_vfmsubadd_ps:
17189 case Intrinsic::x86_fma_vfmsubadd_pd:
17190 case Intrinsic::x86_fma_vfmadd_ps_256:
17191 case Intrinsic::x86_fma_vfmadd_pd_256:
17192 case Intrinsic::x86_fma_vfmsub_ps_256:
17193 case Intrinsic::x86_fma_vfmsub_pd_256:
17194 case Intrinsic::x86_fma_vfnmadd_ps_256:
17195 case Intrinsic::x86_fma_vfnmadd_pd_256:
17196 case Intrinsic::x86_fma_vfnmsub_ps_256:
17197 case Intrinsic::x86_fma_vfnmsub_pd_256:
17198 case Intrinsic::x86_fma_vfmaddsub_ps_256:
17199 case Intrinsic::x86_fma_vfmaddsub_pd_256:
17200 case Intrinsic::x86_fma_vfmsubadd_ps_256:
17201 case Intrinsic::x86_fma_vfmsubadd_pd_256:
17202 return DAG.getNode(getOpcodeForFMAIntrinsic(IntNo), dl, Op.getValueType(),
17203 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
17207 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17208 SDValue Src, SDValue Mask, SDValue Base,
17209 SDValue Index, SDValue ScaleOp, SDValue Chain,
17210 const X86Subtarget * Subtarget) {
17212 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17213 assert(C && "Invalid scale type");
17214 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17215 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17216 Index.getSimpleValueType().getVectorNumElements());
17218 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17220 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17222 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17223 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17224 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17225 SDValue Segment = DAG.getRegister(0, MVT::i32);
17226 if (Src.getOpcode() == ISD::UNDEF)
17227 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
17228 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17229 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17230 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17231 return DAG.getMergeValues(RetOps, dl);
17234 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17235 SDValue Src, SDValue Mask, SDValue Base,
17236 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17238 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17239 assert(C && "Invalid scale type");
17240 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17241 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17242 SDValue Segment = DAG.getRegister(0, MVT::i32);
17243 EVT MaskVT = MVT::getVectorVT(MVT::i1,
17244 Index.getSimpleValueType().getVectorNumElements());
17246 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17248 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17250 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17251 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17252 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17253 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17254 return SDValue(Res, 1);
17257 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17258 SDValue Mask, SDValue Base, SDValue Index,
17259 SDValue ScaleOp, SDValue Chain) {
17261 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
17262 assert(C && "Invalid scale type");
17263 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);
17264 SDValue Disp = DAG.getTargetConstant(0, MVT::i32);
17265 SDValue Segment = DAG.getRegister(0, MVT::i32);
17267 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17269 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17271 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);
17273 MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);
17274 //SDVTList VTs = DAG.getVTList(MVT::Other);
17275 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17276 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17277 return SDValue(Res, 0);
17280 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17281 // read performance monitor counters (x86_rdpmc).
17282 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17283 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17284 SmallVectorImpl<SDValue> &Results) {
17285 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17286 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17289 // The ECX register is used to select the index of the performance counter
17291 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17293 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17295 // Reads the content of a 64-bit performance counter and returns it in the
17296 // registers EDX:EAX.
17297 if (Subtarget->is64Bit()) {
17298 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17299 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17302 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17303 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17306 Chain = HI.getValue(1);
17308 if (Subtarget->is64Bit()) {
17309 // The EAX register is loaded with the low-order 32 bits. The EDX register
17310 // is loaded with the supported high-order bits of the counter.
17311 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17312 DAG.getConstant(32, MVT::i8));
17313 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17314 Results.push_back(Chain);
17318 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17319 SDValue Ops[] = { LO, HI };
17320 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17321 Results.push_back(Pair);
17322 Results.push_back(Chain);
17325 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17326 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17327 // also used to custom lower READCYCLECOUNTER nodes.
17328 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17329 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17330 SmallVectorImpl<SDValue> &Results) {
17331 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17332 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17335 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17336 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17337 // and the EAX register is loaded with the low-order 32 bits.
17338 if (Subtarget->is64Bit()) {
17339 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17340 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17343 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17344 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17347 SDValue Chain = HI.getValue(1);
17349 if (Opcode == X86ISD::RDTSCP_DAG) {
17350 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17352 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17353 // the ECX register. Add 'ecx' explicitly to the chain.
17354 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17356 // Explicitly store the content of ECX at the location passed in input
17357 // to the 'rdtscp' intrinsic.
17358 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17359 MachinePointerInfo(), false, false, 0);
17362 if (Subtarget->is64Bit()) {
17363 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17364 // the EAX register is loaded with the low-order 32 bits.
17365 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17366 DAG.getConstant(32, MVT::i8));
17367 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17368 Results.push_back(Chain);
17372 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17373 SDValue Ops[] = { LO, HI };
17374 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17375 Results.push_back(Pair);
17376 Results.push_back(Chain);
17379 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17380 SelectionDAG &DAG) {
17381 SmallVector<SDValue, 2> Results;
17383 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17385 return DAG.getMergeValues(Results, DL);
17389 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17390 SelectionDAG &DAG) {
17391 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17393 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17398 switch(IntrData->Type) {
17400 llvm_unreachable("Unknown Intrinsic Type");
17404 // Emit the node with the right value type.
17405 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17406 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17408 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17409 // Otherwise return the value from Rand, which is always 0, casted to i32.
17410 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17411 DAG.getConstant(1, Op->getValueType(1)),
17412 DAG.getConstant(X86::COND_B, MVT::i32),
17413 SDValue(Result.getNode(), 1) };
17414 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17415 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17418 // Return { result, isValid, chain }.
17419 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17420 SDValue(Result.getNode(), 2));
17423 //gather(v1, mask, index, base, scale);
17424 SDValue Chain = Op.getOperand(0);
17425 SDValue Src = Op.getOperand(2);
17426 SDValue Base = Op.getOperand(3);
17427 SDValue Index = Op.getOperand(4);
17428 SDValue Mask = Op.getOperand(5);
17429 SDValue Scale = Op.getOperand(6);
17430 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
17434 //scatter(base, mask, index, v1, scale);
17435 SDValue Chain = Op.getOperand(0);
17436 SDValue Base = Op.getOperand(2);
17437 SDValue Mask = Op.getOperand(3);
17438 SDValue Index = Op.getOperand(4);
17439 SDValue Src = Op.getOperand(5);
17440 SDValue Scale = Op.getOperand(6);
17441 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
17444 SDValue Hint = Op.getOperand(6);
17446 if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
17447 (HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
17448 llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
17449 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17450 SDValue Chain = Op.getOperand(0);
17451 SDValue Mask = Op.getOperand(2);
17452 SDValue Index = Op.getOperand(3);
17453 SDValue Base = Op.getOperand(4);
17454 SDValue Scale = Op.getOperand(5);
17455 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17457 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17459 SmallVector<SDValue, 2> Results;
17460 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
17461 return DAG.getMergeValues(Results, dl);
17463 // Read Performance Monitoring Counters.
17465 SmallVector<SDValue, 2> Results;
17466 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17467 return DAG.getMergeValues(Results, dl);
17469 // XTEST intrinsics.
17471 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17472 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17473 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17474 DAG.getConstant(X86::COND_NE, MVT::i8),
17476 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17477 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17478 Ret, SDValue(InTrans.getNode(), 1));
17482 SmallVector<SDValue, 2> Results;
17483 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17484 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17485 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17486 DAG.getConstant(-1, MVT::i8));
17487 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17488 Op.getOperand(4), GenCF.getValue(1));
17489 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17490 Op.getOperand(5), MachinePointerInfo(),
17492 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17493 DAG.getConstant(X86::COND_B, MVT::i8),
17495 Results.push_back(SetCC);
17496 Results.push_back(Store);
17497 return DAG.getMergeValues(Results, dl);
17499 case COMPRESS_TO_MEM: {
17501 SDValue Mask = Op.getOperand(4);
17502 SDValue DataToCompress = Op.getOperand(3);
17503 SDValue Addr = Op.getOperand(2);
17504 SDValue Chain = Op.getOperand(0);
17506 if (isAllOnes(Mask)) // return just a store
17507 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17508 MachinePointerInfo(), false, false, 0);
17510 EVT VT = DataToCompress.getValueType();
17511 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17512 VT.getVectorNumElements());
17513 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
17514 Mask.getValueType().getSizeInBits());
17515 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17516 DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),
17517 DAG.getIntPtrConstant(0));
17519 SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,
17520 DataToCompress, DAG.getUNDEF(VT));
17521 return DAG.getStore(Chain, dl, Compressed, Addr,
17522 MachinePointerInfo(), false, false, 0);
17527 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17528 SelectionDAG &DAG) const {
17529 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17530 MFI->setReturnAddressIsTaken(true);
17532 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17535 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17537 EVT PtrVT = getPointerTy();
17540 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17541 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17542 DAG.getSubtarget().getRegisterInfo());
17543 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
17544 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17545 DAG.getNode(ISD::ADD, dl, PtrVT,
17546 FrameAddr, Offset),
17547 MachinePointerInfo(), false, false, false, 0);
17550 // Just load the return address.
17551 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17552 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17553 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17556 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17557 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17558 MFI->setFrameAddressIsTaken(true);
17560 EVT VT = Op.getValueType();
17561 SDLoc dl(Op); // FIXME probably not meaningful
17562 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17563 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17564 DAG.getSubtarget().getRegisterInfo());
17565 unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(
17566 DAG.getMachineFunction());
17567 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17568 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17569 "Invalid Frame Register!");
17570 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17572 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17573 MachinePointerInfo(),
17574 false, false, false, 0);
17578 // FIXME? Maybe this could be a TableGen attribute on some registers and
17579 // this table could be generated automatically from RegInfo.
17580 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
17582 unsigned Reg = StringSwitch<unsigned>(RegName)
17583 .Case("esp", X86::ESP)
17584 .Case("rsp", X86::RSP)
17588 report_fatal_error("Invalid register name global variable");
17591 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17592 SelectionDAG &DAG) const {
17593 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17594 DAG.getSubtarget().getRegisterInfo());
17595 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
17598 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17599 SDValue Chain = Op.getOperand(0);
17600 SDValue Offset = Op.getOperand(1);
17601 SDValue Handler = Op.getOperand(2);
17604 EVT PtrVT = getPointerTy();
17605 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
17606 DAG.getSubtarget().getRegisterInfo());
17607 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17608 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17609 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17610 "Invalid Frame Register!");
17611 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17612 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17614 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17615 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
17616 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17617 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17619 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17621 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17622 DAG.getRegister(StoreAddrReg, PtrVT));
17625 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17626 SelectionDAG &DAG) const {
17628 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17629 DAG.getVTList(MVT::i32, MVT::Other),
17630 Op.getOperand(0), Op.getOperand(1));
17633 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17634 SelectionDAG &DAG) const {
17636 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17637 Op.getOperand(0), Op.getOperand(1));
17640 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17641 return Op.getOperand(0);
17644 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17645 SelectionDAG &DAG) const {
17646 SDValue Root = Op.getOperand(0);
17647 SDValue Trmp = Op.getOperand(1); // trampoline
17648 SDValue FPtr = Op.getOperand(2); // nested function
17649 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17652 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17653 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
17655 if (Subtarget->is64Bit()) {
17656 SDValue OutChains[6];
17658 // Large code-model.
17659 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17660 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17662 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17663 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17665 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17667 // Load the pointer to the nested function into R11.
17668 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17669 SDValue Addr = Trmp;
17670 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17671 Addr, MachinePointerInfo(TrmpAddr),
17674 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17675 DAG.getConstant(2, MVT::i64));
17676 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17677 MachinePointerInfo(TrmpAddr, 2),
17680 // Load the 'nest' parameter value into R10.
17681 // R10 is specified in X86CallingConv.td
17682 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17683 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17684 DAG.getConstant(10, MVT::i64));
17685 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17686 Addr, MachinePointerInfo(TrmpAddr, 10),
17689 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17690 DAG.getConstant(12, MVT::i64));
17691 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17692 MachinePointerInfo(TrmpAddr, 12),
17695 // Jump to the nested function.
17696 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17697 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17698 DAG.getConstant(20, MVT::i64));
17699 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
17700 Addr, MachinePointerInfo(TrmpAddr, 20),
17703 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17704 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17705 DAG.getConstant(22, MVT::i64));
17706 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
17707 MachinePointerInfo(TrmpAddr, 22),
17710 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17712 const Function *Func =
17713 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17714 CallingConv::ID CC = Func->getCallingConv();
17719 llvm_unreachable("Unsupported calling convention");
17720 case CallingConv::C:
17721 case CallingConv::X86_StdCall: {
17722 // Pass 'nest' parameter in ECX.
17723 // Must be kept in sync with X86CallingConv.td
17724 NestReg = X86::ECX;
17726 // Check that ECX wasn't needed by an 'inreg' parameter.
17727 FunctionType *FTy = Func->getFunctionType();
17728 const AttributeSet &Attrs = Func->getAttributes();
17730 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17731 unsigned InRegCount = 0;
17734 for (FunctionType::param_iterator I = FTy->param_begin(),
17735 E = FTy->param_end(); I != E; ++I, ++Idx)
17736 if (Attrs.hasAttribute(Idx, Attribute::InReg))
17737 // FIXME: should only count parameters that are lowered to integers.
17738 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
17740 if (InRegCount > 2) {
17741 report_fatal_error("Nest register in use - reduce number of inreg"
17747 case CallingConv::X86_FastCall:
17748 case CallingConv::X86_ThisCall:
17749 case CallingConv::Fast:
17750 // Pass 'nest' parameter in EAX.
17751 // Must be kept in sync with X86CallingConv.td
17752 NestReg = X86::EAX;
17756 SDValue OutChains[4];
17757 SDValue Addr, Disp;
17759 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17760 DAG.getConstant(10, MVT::i32));
17761 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17763 // This is storing the opcode for MOV32ri.
17764 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17765 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17766 OutChains[0] = DAG.getStore(Root, dl,
17767 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
17768 Trmp, MachinePointerInfo(TrmpAddr),
17771 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17772 DAG.getConstant(1, MVT::i32));
17773 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17774 MachinePointerInfo(TrmpAddr, 1),
17777 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17778 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17779 DAG.getConstant(5, MVT::i32));
17780 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
17781 MachinePointerInfo(TrmpAddr, 5),
17784 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17785 DAG.getConstant(6, MVT::i32));
17786 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17787 MachinePointerInfo(TrmpAddr, 6),
17790 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17794 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17795 SelectionDAG &DAG) const {
17797 The rounding mode is in bits 11:10 of FPSR, and has the following
17799 00 Round to nearest
17804 FLT_ROUNDS, on the other hand, expects the following:
17811 To perform the conversion, we do:
17812 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17815 MachineFunction &MF = DAG.getMachineFunction();
17816 const TargetMachine &TM = MF.getTarget();
17817 const TargetFrameLowering &TFI = *TM.getSubtargetImpl()->getFrameLowering();
17818 unsigned StackAlignment = TFI.getStackAlignment();
17819 MVT VT = Op.getSimpleValueType();
17822 // Save FP Control Word to stack slot
17823 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17824 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
17826 MachineMemOperand *MMO =
17827 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
17828 MachineMemOperand::MOStore, 2, 2);
17830 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17831 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17832 DAG.getVTList(MVT::Other),
17833 Ops, MVT::i16, MMO);
17835 // Load FP Control Word from stack slot
17836 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17837 MachinePointerInfo(), false, false, false, 0);
17839 // Transform as necessary
17841 DAG.getNode(ISD::SRL, DL, MVT::i16,
17842 DAG.getNode(ISD::AND, DL, MVT::i16,
17843 CWD, DAG.getConstant(0x800, MVT::i16)),
17844 DAG.getConstant(11, MVT::i8));
17846 DAG.getNode(ISD::SRL, DL, MVT::i16,
17847 DAG.getNode(ISD::AND, DL, MVT::i16,
17848 CWD, DAG.getConstant(0x400, MVT::i16)),
17849 DAG.getConstant(9, MVT::i8));
17852 DAG.getNode(ISD::AND, DL, MVT::i16,
17853 DAG.getNode(ISD::ADD, DL, MVT::i16,
17854 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17855 DAG.getConstant(1, MVT::i16)),
17856 DAG.getConstant(3, MVT::i16));
17858 return DAG.getNode((VT.getSizeInBits() < 16 ?
17859 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17862 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
17863 MVT VT = Op.getSimpleValueType();
17865 unsigned NumBits = VT.getSizeInBits();
17868 Op = Op.getOperand(0);
17869 if (VT == MVT::i8) {
17870 // Zero extend to i32 since there is not an i8 bsr.
17872 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17875 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17876 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17877 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17879 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17882 DAG.getConstant(NumBits+NumBits-1, OpVT),
17883 DAG.getConstant(X86::COND_E, MVT::i8),
17886 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17888 // Finally xor with NumBits-1.
17889 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17892 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17896 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
17897 MVT VT = Op.getSimpleValueType();
17899 unsigned NumBits = VT.getSizeInBits();
17902 Op = Op.getOperand(0);
17903 if (VT == MVT::i8) {
17904 // Zero extend to i32 since there is not an i8 bsr.
17906 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17909 // Issue a bsr (scan bits in reverse).
17910 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17911 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17913 // And xor with NumBits-1.
17914 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
17917 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17921 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17922 MVT VT = Op.getSimpleValueType();
17923 unsigned NumBits = VT.getSizeInBits();
17925 Op = Op.getOperand(0);
17927 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17928 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17929 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
17931 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17934 DAG.getConstant(NumBits, VT),
17935 DAG.getConstant(X86::COND_E, MVT::i8),
17938 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17941 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17942 // ones, and then concatenate the result back.
17943 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17944 MVT VT = Op.getSimpleValueType();
17946 assert(VT.is256BitVector() && VT.isInteger() &&
17947 "Unsupported value type for operation");
17949 unsigned NumElems = VT.getVectorNumElements();
17952 // Extract the LHS vectors
17953 SDValue LHS = Op.getOperand(0);
17954 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17955 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17957 // Extract the RHS vectors
17958 SDValue RHS = Op.getOperand(1);
17959 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17960 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17962 MVT EltVT = VT.getVectorElementType();
17963 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17965 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17966 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17967 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17970 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17971 assert(Op.getSimpleValueType().is256BitVector() &&
17972 Op.getSimpleValueType().isInteger() &&
17973 "Only handle AVX 256-bit vector integer operation");
17974 return Lower256IntArith(Op, DAG);
17977 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17978 assert(Op.getSimpleValueType().is256BitVector() &&
17979 Op.getSimpleValueType().isInteger() &&
17980 "Only handle AVX 256-bit vector integer operation");
17981 return Lower256IntArith(Op, DAG);
17984 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17985 SelectionDAG &DAG) {
17987 MVT VT = Op.getSimpleValueType();
17989 // Decompose 256-bit ops into smaller 128-bit ops.
17990 if (VT.is256BitVector() && !Subtarget->hasInt256())
17991 return Lower256IntArith(Op, DAG);
17993 SDValue A = Op.getOperand(0);
17994 SDValue B = Op.getOperand(1);
17996 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17997 if (VT == MVT::v4i32) {
17998 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17999 "Should not custom lower when pmuldq is available!");
18001 // Extract the odd parts.
18002 static const int UnpackMask[] = { 1, -1, 3, -1 };
18003 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18004 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18006 // Multiply the even parts.
18007 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18008 // Now multiply odd parts.
18009 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18011 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
18012 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
18014 // Merge the two vectors back together with a shuffle. This expands into 2
18016 static const int ShufMask[] = { 0, 4, 2, 6 };
18017 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18020 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18021 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18023 // Ahi = psrlqi(a, 32);
18024 // Bhi = psrlqi(b, 32);
18026 // AloBlo = pmuludq(a, b);
18027 // AloBhi = pmuludq(a, Bhi);
18028 // AhiBlo = pmuludq(Ahi, b);
18030 // AloBhi = psllqi(AloBhi, 32);
18031 // AhiBlo = psllqi(AhiBlo, 32);
18032 // return AloBlo + AloBhi + AhiBlo;
18034 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18035 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18037 // Bit cast to 32-bit vectors for MULUDQ
18038 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18039 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18040 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
18041 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
18042 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
18043 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
18045 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18046 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18047 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18049 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18050 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18052 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18053 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18056 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18057 assert(Subtarget->isTargetWin64() && "Unexpected target");
18058 EVT VT = Op.getValueType();
18059 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18060 "Unexpected return type for lowering");
18064 switch (Op->getOpcode()) {
18065 default: llvm_unreachable("Unexpected request for libcall!");
18066 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18067 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18068 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18069 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18070 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18071 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18075 SDValue InChain = DAG.getEntryNode();
18077 TargetLowering::ArgListTy Args;
18078 TargetLowering::ArgListEntry Entry;
18079 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18080 EVT ArgVT = Op->getOperand(i).getValueType();
18081 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18082 "Unexpected argument type for lowering");
18083 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18084 Entry.Node = StackPtr;
18085 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18087 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18088 Entry.Ty = PointerType::get(ArgTy,0);
18089 Entry.isSExt = false;
18090 Entry.isZExt = false;
18091 Args.push_back(Entry);
18094 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18097 TargetLowering::CallLoweringInfo CLI(DAG);
18098 CLI.setDebugLoc(dl).setChain(InChain)
18099 .setCallee(getLibcallCallingConv(LC),
18100 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18101 Callee, std::move(Args), 0)
18102 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18104 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18105 return DAG.getNode(ISD::BITCAST, dl, VT, CallInfo.first);
18108 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18109 SelectionDAG &DAG) {
18110 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18111 EVT VT = Op0.getValueType();
18114 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18115 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18117 // PMULxD operations multiply each even value (starting at 0) of LHS with
18118 // the related value of RHS and produce a widen result.
18119 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18120 // => <2 x i64> <ae|cg>
18122 // In other word, to have all the results, we need to perform two PMULxD:
18123 // 1. one with the even values.
18124 // 2. one with the odd values.
18125 // To achieve #2, with need to place the odd values at an even position.
18127 // Place the odd value at an even position (basically, shift all values 1
18128 // step to the left):
18129 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18130 // <a|b|c|d> => <b|undef|d|undef>
18131 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18132 // <e|f|g|h> => <f|undef|h|undef>
18133 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18135 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18137 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18138 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18140 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18141 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18142 // => <2 x i64> <ae|cg>
18143 SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT,
18144 DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18145 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18146 // => <2 x i64> <bf|dh>
18147 SDValue Mul2 = DAG.getNode(ISD::BITCAST, dl, VT,
18148 DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18150 // Shuffle it back into the right order.
18151 SDValue Highs, Lows;
18152 if (VT == MVT::v8i32) {
18153 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18154 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18155 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18156 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18158 const int HighMask[] = {1, 5, 3, 7};
18159 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18160 const int LowMask[] = {0, 4, 2, 6};
18161 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18164 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18165 // unsigned multiply.
18166 if (IsSigned && !Subtarget->hasSSE41()) {
18168 DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
18169 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18170 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18171 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18172 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18174 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18175 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18178 // The first result of MUL_LOHI is actually the low value, followed by the
18180 SDValue Ops[] = {Lows, Highs};
18181 return DAG.getMergeValues(Ops, dl);
18184 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18185 const X86Subtarget *Subtarget) {
18186 MVT VT = Op.getSimpleValueType();
18188 SDValue R = Op.getOperand(0);
18189 SDValue Amt = Op.getOperand(1);
18191 // Optimize shl/srl/sra with constant shift amount.
18192 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18193 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18194 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18196 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
18197 (Subtarget->hasInt256() &&
18198 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18199 (Subtarget->hasAVX512() &&
18200 (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18201 if (Op.getOpcode() == ISD::SHL)
18202 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18204 if (Op.getOpcode() == ISD::SRL)
18205 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18207 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
18208 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18212 if (VT == MVT::v16i8) {
18213 if (Op.getOpcode() == ISD::SHL) {
18214 // Make a large shift.
18215 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18216 MVT::v8i16, R, ShiftAmt,
18218 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18219 // Zero out the rightmost bits.
18220 SmallVector<SDValue, 16> V(16,
18221 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18223 return DAG.getNode(ISD::AND, dl, VT, SHL,
18224 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18226 if (Op.getOpcode() == ISD::SRL) {
18227 // Make a large shift.
18228 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18229 MVT::v8i16, R, ShiftAmt,
18231 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18232 // Zero out the leftmost bits.
18233 SmallVector<SDValue, 16> V(16,
18234 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18236 return DAG.getNode(ISD::AND, dl, VT, SRL,
18237 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18239 if (Op.getOpcode() == ISD::SRA) {
18240 if (ShiftAmt == 7) {
18241 // R s>> 7 === R s< 0
18242 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18243 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18246 // R s>> a === ((R u>> a) ^ m) - m
18247 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18248 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
18250 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18251 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18252 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18255 llvm_unreachable("Unknown shift opcode.");
18258 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
18259 if (Op.getOpcode() == ISD::SHL) {
18260 // Make a large shift.
18261 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl,
18262 MVT::v16i16, R, ShiftAmt,
18264 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
18265 // Zero out the rightmost bits.
18266 SmallVector<SDValue, 32> V(32,
18267 DAG.getConstant(uint8_t(-1U << ShiftAmt),
18269 return DAG.getNode(ISD::AND, dl, VT, SHL,
18270 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18272 if (Op.getOpcode() == ISD::SRL) {
18273 // Make a large shift.
18274 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl,
18275 MVT::v16i16, R, ShiftAmt,
18277 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
18278 // Zero out the leftmost bits.
18279 SmallVector<SDValue, 32> V(32,
18280 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
18282 return DAG.getNode(ISD::AND, dl, VT, SRL,
18283 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18285 if (Op.getOpcode() == ISD::SRA) {
18286 if (ShiftAmt == 7) {
18287 // R s>> 7 === R s< 0
18288 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18289 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18292 // R s>> a === ((R u>> a) ^ m) - m
18293 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18294 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
18296 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18297 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18298 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18301 llvm_unreachable("Unknown shift opcode.");
18306 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18307 if (!Subtarget->is64Bit() &&
18308 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18309 Amt.getOpcode() == ISD::BITCAST &&
18310 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18311 Amt = Amt.getOperand(0);
18312 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18313 VT.getVectorNumElements();
18314 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18315 uint64_t ShiftAmt = 0;
18316 for (unsigned i = 0; i != Ratio; ++i) {
18317 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
18321 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18323 // Check remaining shift amounts.
18324 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18325 uint64_t ShAmt = 0;
18326 for (unsigned j = 0; j != Ratio; ++j) {
18327 ConstantSDNode *C =
18328 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18332 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18334 if (ShAmt != ShiftAmt)
18337 switch (Op.getOpcode()) {
18339 llvm_unreachable("Unknown shift opcode!");
18341 return getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, R, ShiftAmt,
18344 return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,
18347 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, R, ShiftAmt,
18355 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18356 const X86Subtarget* Subtarget) {
18357 MVT VT = Op.getSimpleValueType();
18359 SDValue R = Op.getOperand(0);
18360 SDValue Amt = Op.getOperand(1);
18362 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
18363 VT == MVT::v4i32 || VT == MVT::v8i16 ||
18364 (Subtarget->hasInt256() &&
18365 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
18366 VT == MVT::v8i32 || VT == MVT::v16i16)) ||
18367 (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {
18369 EVT EltVT = VT.getVectorElementType();
18371 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18372 // Check if this build_vector node is doing a splat.
18373 // If so, then set BaseShAmt equal to the splat value.
18374 BaseShAmt = BV->getSplatValue();
18375 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18376 BaseShAmt = SDValue();
18378 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18379 Amt = Amt.getOperand(0);
18381 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18382 if (SVN && SVN->isSplat()) {
18383 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18384 SDValue InVec = Amt.getOperand(0);
18385 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18386 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18387 "Unexpected shuffle index found!");
18388 BaseShAmt = InVec.getOperand(SplatIdx);
18389 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18390 if (ConstantSDNode *C =
18391 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18392 if (C->getZExtValue() == SplatIdx)
18393 BaseShAmt = InVec.getOperand(1);
18398 // Avoid introducing an extract element from a shuffle.
18399 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18400 DAG.getIntPtrConstant(SplatIdx));
18404 if (BaseShAmt.getNode()) {
18405 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18406 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18407 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18408 else if (EltVT.bitsLT(MVT::i32))
18409 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18411 switch (Op.getOpcode()) {
18413 llvm_unreachable("Unknown shift opcode!");
18415 switch (VT.SimpleTy) {
18416 default: return SDValue();
18425 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
18428 switch (VT.SimpleTy) {
18429 default: return SDValue();
18436 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
18439 switch (VT.SimpleTy) {
18440 default: return SDValue();
18449 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
18455 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18456 if (!Subtarget->is64Bit() &&
18457 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64) ||
18458 (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&
18459 Amt.getOpcode() == ISD::BITCAST &&
18460 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18461 Amt = Amt.getOperand(0);
18462 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18463 VT.getVectorNumElements();
18464 std::vector<SDValue> Vals(Ratio);
18465 for (unsigned i = 0; i != Ratio; ++i)
18466 Vals[i] = Amt.getOperand(i);
18467 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18468 for (unsigned j = 0; j != Ratio; ++j)
18469 if (Vals[j] != Amt.getOperand(i + j))
18472 switch (Op.getOpcode()) {
18474 llvm_unreachable("Unknown shift opcode!");
18476 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
18478 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
18480 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
18487 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18488 SelectionDAG &DAG) {
18489 MVT VT = Op.getSimpleValueType();
18491 SDValue R = Op.getOperand(0);
18492 SDValue Amt = Op.getOperand(1);
18495 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18496 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18498 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
18502 V = LowerScalarVariableShift(Op, DAG, Subtarget);
18506 if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))
18508 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
18509 if (Subtarget->hasInt256()) {
18510 if (Op.getOpcode() == ISD::SRL &&
18511 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18512 VT == MVT::v4i64 || VT == MVT::v8i32))
18514 if (Op.getOpcode() == ISD::SHL &&
18515 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18516 VT == MVT::v4i64 || VT == MVT::v8i32))
18518 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
18522 // If possible, lower this packed shift into a vector multiply instead of
18523 // expanding it into a sequence of scalar shifts.
18524 // Do this only if the vector shift count is a constant build_vector.
18525 if (Op.getOpcode() == ISD::SHL &&
18526 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18527 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18528 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18529 SmallVector<SDValue, 8> Elts;
18530 EVT SVT = VT.getScalarType();
18531 unsigned SVTBits = SVT.getSizeInBits();
18532 const APInt &One = APInt(SVTBits, 1);
18533 unsigned NumElems = VT.getVectorNumElements();
18535 for (unsigned i=0; i !=NumElems; ++i) {
18536 SDValue Op = Amt->getOperand(i);
18537 if (Op->getOpcode() == ISD::UNDEF) {
18538 Elts.push_back(Op);
18542 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18543 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18544 uint64_t ShAmt = C.getZExtValue();
18545 if (ShAmt >= SVTBits) {
18546 Elts.push_back(DAG.getUNDEF(SVT));
18549 Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));
18551 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18552 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18555 // Lower SHL with variable shift amount.
18556 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18557 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
18559 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
18560 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
18561 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18562 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18565 // If possible, lower this shift as a sequence of two shifts by
18566 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18568 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18570 // Could be rewritten as:
18571 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18573 // The advantage is that the two shifts from the example would be
18574 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18575 // the vector shift into four scalar shifts plus four pairs of vector
18577 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18578 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18579 unsigned TargetOpcode = X86ISD::MOVSS;
18580 bool CanBeSimplified;
18581 // The splat value for the first packed shift (the 'X' from the example).
18582 SDValue Amt1 = Amt->getOperand(0);
18583 // The splat value for the second packed shift (the 'Y' from the example).
18584 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18585 Amt->getOperand(2);
18587 // See if it is possible to replace this node with a sequence of
18588 // two shifts followed by a MOVSS/MOVSD
18589 if (VT == MVT::v4i32) {
18590 // Check if it is legal to use a MOVSS.
18591 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18592 Amt2 == Amt->getOperand(3);
18593 if (!CanBeSimplified) {
18594 // Otherwise, check if we can still simplify this node using a MOVSD.
18595 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18596 Amt->getOperand(2) == Amt->getOperand(3);
18597 TargetOpcode = X86ISD::MOVSD;
18598 Amt2 = Amt->getOperand(2);
18601 // Do similar checks for the case where the machine value type
18603 CanBeSimplified = Amt1 == Amt->getOperand(1);
18604 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18605 CanBeSimplified = Amt2 == Amt->getOperand(i);
18607 if (!CanBeSimplified) {
18608 TargetOpcode = X86ISD::MOVSD;
18609 CanBeSimplified = true;
18610 Amt2 = Amt->getOperand(4);
18611 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18612 CanBeSimplified = Amt1 == Amt->getOperand(i);
18613 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18614 CanBeSimplified = Amt2 == Amt->getOperand(j);
18618 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18619 isa<ConstantSDNode>(Amt2)) {
18620 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18621 EVT CastVT = MVT::v4i32;
18623 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);
18624 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18626 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);
18627 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18628 if (TargetOpcode == X86ISD::MOVSD)
18629 CastVT = MVT::v2i64;
18630 SDValue BitCast1 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift1);
18631 SDValue BitCast2 = DAG.getNode(ISD::BITCAST, dl, CastVT, Shift2);
18632 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18634 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
18638 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
18639 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
18642 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
18643 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
18645 // Turn 'a' into a mask suitable for VSELECT
18646 SDValue VSelM = DAG.getConstant(0x80, VT);
18647 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18648 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18650 SDValue CM1 = DAG.getConstant(0x0f, VT);
18651 SDValue CM2 = DAG.getConstant(0x3f, VT);
18653 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
18654 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
18655 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 4, DAG);
18656 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18657 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18660 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18661 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18662 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18664 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
18665 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
18666 M = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, MVT::v8i16, M, 2, DAG);
18667 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
18668 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
18671 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
18672 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
18673 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
18675 // return VSELECT(r, r+r, a);
18676 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
18677 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
18681 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18682 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18683 // solution better.
18684 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18685 MVT NewVT = VT == MVT::v8i16 ? MVT::v8i32 : MVT::v16i16;
18687 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18688 R = DAG.getNode(ExtOpc, dl, NewVT, R);
18689 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, NewVT, Amt);
18690 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18691 DAG.getNode(Op.getOpcode(), dl, NewVT, R, Amt));
18694 // Decompose 256-bit shifts into smaller 128-bit shifts.
18695 if (VT.is256BitVector()) {
18696 unsigned NumElems = VT.getVectorNumElements();
18697 MVT EltVT = VT.getVectorElementType();
18698 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18700 // Extract the two vectors
18701 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18702 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18704 // Recreate the shift amount vectors
18705 SDValue Amt1, Amt2;
18706 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18707 // Constant shift amount
18708 SmallVector<SDValue, 4> Amt1Csts;
18709 SmallVector<SDValue, 4> Amt2Csts;
18710 for (unsigned i = 0; i != NumElems/2; ++i)
18711 Amt1Csts.push_back(Amt->getOperand(i));
18712 for (unsigned i = NumElems/2; i != NumElems; ++i)
18713 Amt2Csts.push_back(Amt->getOperand(i));
18715 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18716 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18718 // Variable shift amount
18719 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18720 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18723 // Issue new vector shifts for the smaller types
18724 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18725 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18727 // Concatenate the result back
18728 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18734 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18735 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18736 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18737 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18738 // has only one use.
18739 SDNode *N = Op.getNode();
18740 SDValue LHS = N->getOperand(0);
18741 SDValue RHS = N->getOperand(1);
18742 unsigned BaseOp = 0;
18745 switch (Op.getOpcode()) {
18746 default: llvm_unreachable("Unknown ovf instruction!");
18748 // A subtract of one will be selected as a INC. Note that INC doesn't
18749 // set CF, so we can't do this for UADDO.
18750 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18752 BaseOp = X86ISD::INC;
18753 Cond = X86::COND_O;
18756 BaseOp = X86ISD::ADD;
18757 Cond = X86::COND_O;
18760 BaseOp = X86ISD::ADD;
18761 Cond = X86::COND_B;
18764 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18765 // set CF, so we can't do this for USUBO.
18766 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18768 BaseOp = X86ISD::DEC;
18769 Cond = X86::COND_O;
18772 BaseOp = X86ISD::SUB;
18773 Cond = X86::COND_O;
18776 BaseOp = X86ISD::SUB;
18777 Cond = X86::COND_B;
18780 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18781 Cond = X86::COND_O;
18783 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18784 if (N->getValueType(0) == MVT::i8) {
18785 BaseOp = X86ISD::UMUL8;
18786 Cond = X86::COND_O;
18789 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18791 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18794 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18795 DAG.getConstant(X86::COND_O, MVT::i32),
18796 SDValue(Sum.getNode(), 2));
18798 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18802 // Also sets EFLAGS.
18803 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18804 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18807 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18808 DAG.getConstant(Cond, MVT::i32),
18809 SDValue(Sum.getNode(), 1));
18811 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18814 // Sign extension of the low part of vector elements. This may be used either
18815 // when sign extend instructions are not available or if the vector element
18816 // sizes already match the sign-extended size. If the vector elements are in
18817 // their pre-extended size and sign extend instructions are available, that will
18818 // be handled by LowerSIGN_EXTEND.
18819 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
18820 SelectionDAG &DAG) const {
18822 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
18823 MVT VT = Op.getSimpleValueType();
18825 if (!Subtarget->hasSSE2() || !VT.isVector())
18828 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
18829 ExtraVT.getScalarType().getSizeInBits();
18831 switch (VT.SimpleTy) {
18832 default: return SDValue();
18835 if (!Subtarget->hasFp256())
18837 if (!Subtarget->hasInt256()) {
18838 // needs to be split
18839 unsigned NumElems = VT.getVectorNumElements();
18841 // Extract the LHS vectors
18842 SDValue LHS = Op.getOperand(0);
18843 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18844 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18846 MVT EltVT = VT.getVectorElementType();
18847 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18849 EVT ExtraEltVT = ExtraVT.getVectorElementType();
18850 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
18851 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
18853 SDValue Extra = DAG.getValueType(ExtraVT);
18855 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
18856 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
18858 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
18863 SDValue Op0 = Op.getOperand(0);
18865 // This is a sign extension of some low part of vector elements without
18866 // changing the size of the vector elements themselves:
18867 // Shift-Left + Shift-Right-Algebraic.
18868 SDValue Shl = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, Op0,
18870 return getTargetVShiftByConstNode(X86ISD::VSRAI, dl, VT, Shl, BitsDiff,
18876 /// Returns true if the operand type is exactly twice the native width, and
18877 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18878 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18879 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18880 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
18881 const X86Subtarget &Subtarget =
18882 getTargetMachine().getSubtarget<X86Subtarget>();
18883 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18886 return !Subtarget.is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18887 else if (OpWidth == 128)
18888 return Subtarget.hasCmpxchg16b();
18893 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18894 return needsCmpXchgNb(SI->getValueOperand()->getType());
18897 // Note: this turns large loads into lock cmpxchg8b/16b.
18898 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18899 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18900 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18901 return needsCmpXchgNb(PTy->getElementType());
18904 bool X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18905 const X86Subtarget &Subtarget =
18906 getTargetMachine().getSubtarget<X86Subtarget>();
18907 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18908 const Type *MemType = AI->getType();
18910 // If the operand is too big, we must see if cmpxchg8/16b is available
18911 // and default to library calls otherwise.
18912 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18913 return needsCmpXchgNb(MemType);
18915 AtomicRMWInst::BinOp Op = AI->getOperation();
18918 llvm_unreachable("Unknown atomic operation");
18919 case AtomicRMWInst::Xchg:
18920 case AtomicRMWInst::Add:
18921 case AtomicRMWInst::Sub:
18922 // It's better to use xadd, xsub or xchg for these in all cases.
18924 case AtomicRMWInst::Or:
18925 case AtomicRMWInst::And:
18926 case AtomicRMWInst::Xor:
18927 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18928 // prefix to a normal instruction for these operations.
18929 return !AI->use_empty();
18930 case AtomicRMWInst::Nand:
18931 case AtomicRMWInst::Max:
18932 case AtomicRMWInst::Min:
18933 case AtomicRMWInst::UMax:
18934 case AtomicRMWInst::UMin:
18935 // These always require a non-trivial set of data operations on x86. We must
18936 // use a cmpxchg loop.
18941 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18942 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18943 // no-sse2). There isn't any reason to disable it if the target processor
18945 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18949 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18950 const X86Subtarget &Subtarget =
18951 getTargetMachine().getSubtarget<X86Subtarget>();
18952 unsigned NativeWidth = Subtarget.is64Bit() ? 64 : 32;
18953 const Type *MemType = AI->getType();
18954 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18955 // there is no benefit in turning such RMWs into loads, and it is actually
18956 // harmful as it introduces a mfence.
18957 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18960 auto Builder = IRBuilder<>(AI);
18961 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18962 auto SynchScope = AI->getSynchScope();
18963 // We must restrict the ordering to avoid generating loads with Release or
18964 // ReleaseAcquire orderings.
18965 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18966 auto Ptr = AI->getPointerOperand();
18968 // Before the load we need a fence. Here is an example lifted from
18969 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18972 // x.store(1, relaxed);
18973 // r1 = y.fetch_add(0, release);
18975 // y.fetch_add(42, acquire);
18976 // r2 = x.load(relaxed);
18977 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18978 // lowered to just a load without a fence. A mfence flushes the store buffer,
18979 // making the optimization clearly correct.
18980 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18981 // otherwise, we might be able to be more agressive on relaxed idempotent
18982 // rmw. In practice, they do not look useful, so we don't try to be
18983 // especially clever.
18984 if (SynchScope == SingleThread) {
18985 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
18986 // the IR level, so we must wrap it in an intrinsic.
18988 } else if (hasMFENCE(Subtarget)) {
18989 Function *MFence = llvm::Intrinsic::getDeclaration(M,
18990 Intrinsic::x86_sse2_mfence);
18991 Builder.CreateCall(MFence);
18993 // FIXME: it might make sense to use a locked operation here but on a
18994 // different cache-line to prevent cache-line bouncing. In practice it
18995 // is probably a small win, and x86 processors without mfence are rare
18996 // enough that we do not bother.
19000 // Finally we can emit the atomic load.
19001 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19002 AI->getType()->getPrimitiveSizeInBits());
19003 Loaded->setAtomic(Order, SynchScope);
19004 AI->replaceAllUsesWith(Loaded);
19005 AI->eraseFromParent();
19009 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19010 SelectionDAG &DAG) {
19012 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19013 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19014 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19015 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19017 // The only fence that needs an instruction is a sequentially-consistent
19018 // cross-thread fence.
19019 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19020 if (hasMFENCE(*Subtarget))
19021 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19023 SDValue Chain = Op.getOperand(0);
19024 SDValue Zero = DAG.getConstant(0, MVT::i32);
19026 DAG.getRegister(X86::ESP, MVT::i32), // Base
19027 DAG.getTargetConstant(1, MVT::i8), // Scale
19028 DAG.getRegister(0, MVT::i32), // Index
19029 DAG.getTargetConstant(0, MVT::i32), // Disp
19030 DAG.getRegister(0, MVT::i32), // Segment.
19034 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19035 return SDValue(Res, 0);
19038 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19039 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19042 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19043 SelectionDAG &DAG) {
19044 MVT T = Op.getSimpleValueType();
19048 switch(T.SimpleTy) {
19049 default: llvm_unreachable("Invalid value type!");
19050 case MVT::i8: Reg = X86::AL; size = 1; break;
19051 case MVT::i16: Reg = X86::AX; size = 2; break;
19052 case MVT::i32: Reg = X86::EAX; size = 4; break;
19054 assert(Subtarget->is64Bit() && "Node not type legal!");
19055 Reg = X86::RAX; size = 8;
19058 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19059 Op.getOperand(2), SDValue());
19060 SDValue Ops[] = { cpIn.getValue(0),
19063 DAG.getTargetConstant(size, MVT::i8),
19064 cpIn.getValue(1) };
19065 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19066 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19067 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19071 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19072 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19073 MVT::i32, cpOut.getValue(2));
19074 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19075 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19077 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19078 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19079 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19083 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19084 SelectionDAG &DAG) {
19085 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19086 MVT DstVT = Op.getSimpleValueType();
19088 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19089 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19090 if (DstVT != MVT::f64)
19091 // This conversion needs to be expanded.
19094 SDValue InVec = Op->getOperand(0);
19096 unsigned NumElts = SrcVT.getVectorNumElements();
19097 EVT SVT = SrcVT.getVectorElementType();
19099 // Widen the vector in input in the case of MVT::v2i32.
19100 // Example: from MVT::v2i32 to MVT::v4i32.
19101 SmallVector<SDValue, 16> Elts;
19102 for (unsigned i = 0, e = NumElts; i != e; ++i)
19103 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19104 DAG.getIntPtrConstant(i)));
19106 // Explicitly mark the extra elements as Undef.
19107 SDValue Undef = DAG.getUNDEF(SVT);
19108 for (unsigned i = NumElts, e = NumElts * 2; i != e; ++i)
19109 Elts.push_back(Undef);
19111 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19112 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19113 SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);
19114 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19115 DAG.getIntPtrConstant(0));
19118 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19119 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19120 assert((DstVT == MVT::i64 ||
19121 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19122 "Unexpected custom BITCAST");
19123 // i64 <=> MMX conversions are Legal.
19124 if (SrcVT==MVT::i64 && DstVT.isVector())
19126 if (DstVT==MVT::i64 && SrcVT.isVector())
19128 // MMX <=> MMX conversions are Legal.
19129 if (SrcVT.isVector() && DstVT.isVector())
19131 // All other conversions need to be expanded.
19135 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19136 SDNode *Node = Op.getNode();
19138 EVT T = Node->getValueType(0);
19139 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19140 DAG.getConstant(0, T), Node->getOperand(2));
19141 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19142 cast<AtomicSDNode>(Node)->getMemoryVT(),
19143 Node->getOperand(0),
19144 Node->getOperand(1), negOp,
19145 cast<AtomicSDNode>(Node)->getMemOperand(),
19146 cast<AtomicSDNode>(Node)->getOrdering(),
19147 cast<AtomicSDNode>(Node)->getSynchScope());
19150 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19151 SDNode *Node = Op.getNode();
19153 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19155 // Convert seq_cst store -> xchg
19156 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19157 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19158 // (The only way to get a 16-byte store is cmpxchg16b)
19159 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19160 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19161 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19162 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19163 cast<AtomicSDNode>(Node)->getMemoryVT(),
19164 Node->getOperand(0),
19165 Node->getOperand(1), Node->getOperand(2),
19166 cast<AtomicSDNode>(Node)->getMemOperand(),
19167 cast<AtomicSDNode>(Node)->getOrdering(),
19168 cast<AtomicSDNode>(Node)->getSynchScope());
19169 return Swap.getValue(1);
19171 // Other atomic stores have a simple pattern.
19175 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19176 EVT VT = Op.getNode()->getSimpleValueType(0);
19178 // Let legalize expand this if it isn't a legal type yet.
19179 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19182 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19185 bool ExtraOp = false;
19186 switch (Op.getOpcode()) {
19187 default: llvm_unreachable("Invalid code");
19188 case ISD::ADDC: Opc = X86ISD::ADD; break;
19189 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19190 case ISD::SUBC: Opc = X86ISD::SUB; break;
19191 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19195 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19197 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19198 Op.getOperand(1), Op.getOperand(2));
19201 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19202 SelectionDAG &DAG) {
19203 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19205 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19206 // which returns the values as { float, float } (in XMM0) or
19207 // { double, double } (which is returned in XMM0, XMM1).
19209 SDValue Arg = Op.getOperand(0);
19210 EVT ArgVT = Arg.getValueType();
19211 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19213 TargetLowering::ArgListTy Args;
19214 TargetLowering::ArgListEntry Entry;
19218 Entry.isSExt = false;
19219 Entry.isZExt = false;
19220 Args.push_back(Entry);
19222 bool isF64 = ArgVT == MVT::f64;
19223 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19224 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19225 // the results are returned via SRet in memory.
19226 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19227 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19228 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
19230 Type *RetTy = isF64
19231 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19232 : (Type*)VectorType::get(ArgTy, 4);
19234 TargetLowering::CallLoweringInfo CLI(DAG);
19235 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19236 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19238 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19241 // Returned in xmm0 and xmm1.
19242 return CallResult.first;
19244 // Returned in bits 0:31 and 32:64 xmm0.
19245 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19246 CallResult.first, DAG.getIntPtrConstant(0));
19247 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19248 CallResult.first, DAG.getIntPtrConstant(1));
19249 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19250 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19253 /// LowerOperation - Provide custom lowering hooks for some operations.
19255 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19256 switch (Op.getOpcode()) {
19257 default: llvm_unreachable("Should not custom lower this!");
19258 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
19259 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19260 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19261 return LowerCMP_SWAP(Op, Subtarget, DAG);
19262 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19263 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19264 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19265 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
19266 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
19267 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19268 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19269 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19270 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19271 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19272 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19273 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19274 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19275 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19276 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19277 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19278 case ISD::SHL_PARTS:
19279 case ISD::SRA_PARTS:
19280 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19281 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19282 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19283 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19284 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19285 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19286 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19287 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19288 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19289 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19290 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19292 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19293 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19294 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19295 case ISD::SETCC: return LowerSETCC(Op, DAG);
19296 case ISD::SELECT: return LowerSELECT(Op, DAG);
19297 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19298 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19299 case ISD::VASTART: return LowerVASTART(Op, DAG);
19300 case ISD::VAARG: return LowerVAARG(Op, DAG);
19301 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19302 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19303 case ISD::INTRINSIC_VOID:
19304 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19305 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19306 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19307 case ISD::FRAME_TO_ARGS_OFFSET:
19308 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19309 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19310 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19311 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19312 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19313 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19314 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19315 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19316 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
19317 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
19318 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
19319 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19320 case ISD::UMUL_LOHI:
19321 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19324 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19330 case ISD::UMULO: return LowerXALUO(Op, DAG);
19331 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19332 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19336 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19337 case ISD::ADD: return LowerADD(Op, DAG);
19338 case ISD::SUB: return LowerSUB(Op, DAG);
19339 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19343 /// ReplaceNodeResults - Replace a node with an illegal result type
19344 /// with a new node built out of custom code.
19345 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19346 SmallVectorImpl<SDValue>&Results,
19347 SelectionDAG &DAG) const {
19349 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19350 switch (N->getOpcode()) {
19352 llvm_unreachable("Do not know how to custom type legalize this operation!");
19353 case ISD::SIGN_EXTEND_INREG:
19358 // We don't want to expand or promote these.
19365 case ISD::UDIVREM: {
19366 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19367 Results.push_back(V);
19370 case ISD::FP_TO_SINT:
19371 case ISD::FP_TO_UINT: {
19372 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19374 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
19377 std::pair<SDValue,SDValue> Vals =
19378 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19379 SDValue FIST = Vals.first, StackSlot = Vals.second;
19380 if (FIST.getNode()) {
19381 EVT VT = N->getValueType(0);
19382 // Return a load from the stack slot.
19383 if (StackSlot.getNode())
19384 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19385 MachinePointerInfo(),
19386 false, false, false, 0));
19388 Results.push_back(FIST);
19392 case ISD::UINT_TO_FP: {
19393 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19394 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19395 N->getValueType(0) != MVT::v2f32)
19397 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19399 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
19401 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19402 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19403 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
19404 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
19405 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19406 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19409 case ISD::FP_ROUND: {
19410 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19412 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19413 Results.push_back(V);
19416 case ISD::INTRINSIC_W_CHAIN: {
19417 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19419 default : llvm_unreachable("Do not know how to custom type "
19420 "legalize this intrinsic operation!");
19421 case Intrinsic::x86_rdtsc:
19422 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19424 case Intrinsic::x86_rdtscp:
19425 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19427 case Intrinsic::x86_rdpmc:
19428 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19431 case ISD::READCYCLECOUNTER: {
19432 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19435 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19436 EVT T = N->getValueType(0);
19437 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19438 bool Regs64bit = T == MVT::i128;
19439 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19440 SDValue cpInL, cpInH;
19441 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19442 DAG.getConstant(0, HalfT));
19443 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19444 DAG.getConstant(1, HalfT));
19445 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19446 Regs64bit ? X86::RAX : X86::EAX,
19448 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19449 Regs64bit ? X86::RDX : X86::EDX,
19450 cpInH, cpInL.getValue(1));
19451 SDValue swapInL, swapInH;
19452 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19453 DAG.getConstant(0, HalfT));
19454 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19455 DAG.getConstant(1, HalfT));
19456 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19457 Regs64bit ? X86::RBX : X86::EBX,
19458 swapInL, cpInH.getValue(1));
19459 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19460 Regs64bit ? X86::RCX : X86::ECX,
19461 swapInH, swapInL.getValue(1));
19462 SDValue Ops[] = { swapInH.getValue(0),
19464 swapInH.getValue(1) };
19465 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19466 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19467 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19468 X86ISD::LCMPXCHG8_DAG;
19469 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19470 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19471 Regs64bit ? X86::RAX : X86::EAX,
19472 HalfT, Result.getValue(1));
19473 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19474 Regs64bit ? X86::RDX : X86::EDX,
19475 HalfT, cpOutL.getValue(2));
19476 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19478 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19479 MVT::i32, cpOutH.getValue(2));
19481 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19482 DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);
19483 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19485 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19486 Results.push_back(Success);
19487 Results.push_back(EFLAGS.getValue(1));
19490 case ISD::ATOMIC_SWAP:
19491 case ISD::ATOMIC_LOAD_ADD:
19492 case ISD::ATOMIC_LOAD_SUB:
19493 case ISD::ATOMIC_LOAD_AND:
19494 case ISD::ATOMIC_LOAD_OR:
19495 case ISD::ATOMIC_LOAD_XOR:
19496 case ISD::ATOMIC_LOAD_NAND:
19497 case ISD::ATOMIC_LOAD_MIN:
19498 case ISD::ATOMIC_LOAD_MAX:
19499 case ISD::ATOMIC_LOAD_UMIN:
19500 case ISD::ATOMIC_LOAD_UMAX:
19501 case ISD::ATOMIC_LOAD: {
19502 // Delegate to generic TypeLegalization. Situations we can really handle
19503 // should have already been dealt with by AtomicExpandPass.cpp.
19506 case ISD::BITCAST: {
19507 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19508 EVT DstVT = N->getValueType(0);
19509 EVT SrcVT = N->getOperand(0)->getValueType(0);
19511 if (SrcVT != MVT::f64 ||
19512 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19515 unsigned NumElts = DstVT.getVectorNumElements();
19516 EVT SVT = DstVT.getVectorElementType();
19517 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19518 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19519 MVT::v2f64, N->getOperand(0));
19520 SDValue ToVecInt = DAG.getNode(ISD::BITCAST, dl, WiderVT, Expanded);
19522 if (ExperimentalVectorWideningLegalization) {
19523 // If we are legalizing vectors by widening, we already have the desired
19524 // legal vector type, just return it.
19525 Results.push_back(ToVecInt);
19529 SmallVector<SDValue, 8> Elts;
19530 for (unsigned i = 0, e = NumElts; i != e; ++i)
19531 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19532 ToVecInt, DAG.getIntPtrConstant(i)));
19534 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19539 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19541 default: return nullptr;
19542 case X86ISD::BSF: return "X86ISD::BSF";
19543 case X86ISD::BSR: return "X86ISD::BSR";
19544 case X86ISD::SHLD: return "X86ISD::SHLD";
19545 case X86ISD::SHRD: return "X86ISD::SHRD";
19546 case X86ISD::FAND: return "X86ISD::FAND";
19547 case X86ISD::FANDN: return "X86ISD::FANDN";
19548 case X86ISD::FOR: return "X86ISD::FOR";
19549 case X86ISD::FXOR: return "X86ISD::FXOR";
19550 case X86ISD::FSRL: return "X86ISD::FSRL";
19551 case X86ISD::FILD: return "X86ISD::FILD";
19552 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19553 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19554 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19555 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19556 case X86ISD::FLD: return "X86ISD::FLD";
19557 case X86ISD::FST: return "X86ISD::FST";
19558 case X86ISD::CALL: return "X86ISD::CALL";
19559 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19560 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19561 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19562 case X86ISD::BT: return "X86ISD::BT";
19563 case X86ISD::CMP: return "X86ISD::CMP";
19564 case X86ISD::COMI: return "X86ISD::COMI";
19565 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19566 case X86ISD::CMPM: return "X86ISD::CMPM";
19567 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19568 case X86ISD::SETCC: return "X86ISD::SETCC";
19569 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19570 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19571 case X86ISD::CMOV: return "X86ISD::CMOV";
19572 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19573 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19574 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19575 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19576 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19577 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19578 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19579 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19580 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19581 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19582 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19583 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19584 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19585 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19586 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19587 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19588 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19589 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19590 case X86ISD::HADD: return "X86ISD::HADD";
19591 case X86ISD::HSUB: return "X86ISD::HSUB";
19592 case X86ISD::FHADD: return "X86ISD::FHADD";
19593 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19594 case X86ISD::UMAX: return "X86ISD::UMAX";
19595 case X86ISD::UMIN: return "X86ISD::UMIN";
19596 case X86ISD::SMAX: return "X86ISD::SMAX";
19597 case X86ISD::SMIN: return "X86ISD::SMIN";
19598 case X86ISD::FMAX: return "X86ISD::FMAX";
19599 case X86ISD::FMIN: return "X86ISD::FMIN";
19600 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19601 case X86ISD::FMINC: return "X86ISD::FMINC";
19602 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19603 case X86ISD::FRCP: return "X86ISD::FRCP";
19604 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19605 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19606 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19607 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19608 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19609 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19610 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19611 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
19612 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
19613 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
19614 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
19615 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
19616 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
19617 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
19618 case X86ISD::VZEXT: return "X86ISD::VZEXT";
19619 case X86ISD::VSEXT: return "X86ISD::VSEXT";
19620 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
19621 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
19622 case X86ISD::VINSERT: return "X86ISD::VINSERT";
19623 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
19624 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
19625 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
19626 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
19627 case X86ISD::VSHL: return "X86ISD::VSHL";
19628 case X86ISD::VSRL: return "X86ISD::VSRL";
19629 case X86ISD::VSRA: return "X86ISD::VSRA";
19630 case X86ISD::VSHLI: return "X86ISD::VSHLI";
19631 case X86ISD::VSRLI: return "X86ISD::VSRLI";
19632 case X86ISD::VSRAI: return "X86ISD::VSRAI";
19633 case X86ISD::CMPP: return "X86ISD::CMPP";
19634 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
19635 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
19636 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
19637 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
19638 case X86ISD::ADD: return "X86ISD::ADD";
19639 case X86ISD::SUB: return "X86ISD::SUB";
19640 case X86ISD::ADC: return "X86ISD::ADC";
19641 case X86ISD::SBB: return "X86ISD::SBB";
19642 case X86ISD::SMUL: return "X86ISD::SMUL";
19643 case X86ISD::UMUL: return "X86ISD::UMUL";
19644 case X86ISD::SMUL8: return "X86ISD::SMUL8";
19645 case X86ISD::UMUL8: return "X86ISD::UMUL8";
19646 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
19647 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
19648 case X86ISD::INC: return "X86ISD::INC";
19649 case X86ISD::DEC: return "X86ISD::DEC";
19650 case X86ISD::OR: return "X86ISD::OR";
19651 case X86ISD::XOR: return "X86ISD::XOR";
19652 case X86ISD::AND: return "X86ISD::AND";
19653 case X86ISD::BEXTR: return "X86ISD::BEXTR";
19654 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
19655 case X86ISD::PTEST: return "X86ISD::PTEST";
19656 case X86ISD::TESTP: return "X86ISD::TESTP";
19657 case X86ISD::TESTM: return "X86ISD::TESTM";
19658 case X86ISD::TESTNM: return "X86ISD::TESTNM";
19659 case X86ISD::KORTEST: return "X86ISD::KORTEST";
19660 case X86ISD::PACKSS: return "X86ISD::PACKSS";
19661 case X86ISD::PACKUS: return "X86ISD::PACKUS";
19662 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
19663 case X86ISD::VALIGN: return "X86ISD::VALIGN";
19664 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
19665 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
19666 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
19667 case X86ISD::SHUFP: return "X86ISD::SHUFP";
19668 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
19669 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
19670 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
19671 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
19672 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
19673 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
19674 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
19675 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
19676 case X86ISD::MOVSD: return "X86ISD::MOVSD";
19677 case X86ISD::MOVSS: return "X86ISD::MOVSS";
19678 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
19679 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
19680 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
19681 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
19682 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
19683 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
19684 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
19685 case X86ISD::VPERMV: return "X86ISD::VPERMV";
19686 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
19687 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
19688 case X86ISD::VPERMI: return "X86ISD::VPERMI";
19689 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
19690 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
19691 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
19692 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
19693 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
19694 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
19695 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
19696 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
19697 case X86ISD::SAHF: return "X86ISD::SAHF";
19698 case X86ISD::RDRAND: return "X86ISD::RDRAND";
19699 case X86ISD::RDSEED: return "X86ISD::RDSEED";
19700 case X86ISD::FMADD: return "X86ISD::FMADD";
19701 case X86ISD::FMSUB: return "X86ISD::FMSUB";
19702 case X86ISD::FNMADD: return "X86ISD::FNMADD";
19703 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
19704 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
19705 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
19706 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
19707 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
19708 case X86ISD::XTEST: return "X86ISD::XTEST";
19709 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
19713 // isLegalAddressingMode - Return true if the addressing mode represented
19714 // by AM is legal for this target, for a load/store of the specified type.
19715 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
19717 // X86 supports extremely general addressing modes.
19718 CodeModel::Model M = getTargetMachine().getCodeModel();
19719 Reloc::Model R = getTargetMachine().getRelocationModel();
19721 // X86 allows a sign-extended 32-bit immediate field as a displacement.
19722 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
19727 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
19729 // If a reference to this global requires an extra load, we can't fold it.
19730 if (isGlobalStubReference(GVFlags))
19733 // If BaseGV requires a register for the PIC base, we cannot also have a
19734 // BaseReg specified.
19735 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
19738 // If lower 4G is not available, then we must use rip-relative addressing.
19739 if ((M != CodeModel::Small || R != Reloc::Static) &&
19740 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
19744 switch (AM.Scale) {
19750 // These scales always work.
19755 // These scales are formed with basereg+scalereg. Only accept if there is
19760 default: // Other stuff never works.
19767 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
19768 unsigned Bits = Ty->getScalarSizeInBits();
19770 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
19771 // particularly cheaper than those without.
19775 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
19776 // variable shifts just as cheap as scalar ones.
19777 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
19780 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
19781 // fully general vector.
19785 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
19786 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19788 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
19789 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
19790 return NumBits1 > NumBits2;
19793 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
19794 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
19797 if (!isTypeLegal(EVT::getEVT(Ty1)))
19800 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
19802 // Assuming the caller doesn't have a zeroext or signext return parameter,
19803 // truncation all the way down to i1 is valid.
19807 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
19808 return isInt<32>(Imm);
19811 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
19812 // Can also use sub to handle negated immediates.
19813 return isInt<32>(Imm);
19816 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
19817 if (!VT1.isInteger() || !VT2.isInteger())
19819 unsigned NumBits1 = VT1.getSizeInBits();
19820 unsigned NumBits2 = VT2.getSizeInBits();
19821 return NumBits1 > NumBits2;
19824 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19825 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19826 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19829 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19830 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19831 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19834 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19835 EVT VT1 = Val.getValueType();
19836 if (isZExtFree(VT1, VT2))
19839 if (Val.getOpcode() != ISD::LOAD)
19842 if (!VT1.isSimple() || !VT1.isInteger() ||
19843 !VT2.isSimple() || !VT2.isInteger())
19846 switch (VT1.getSimpleVT().SimpleTy) {
19851 // X86 has 8, 16, and 32-bit zero-extending loads.
19859 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19860 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4()))
19863 VT = VT.getScalarType();
19865 if (!VT.isSimple())
19868 switch (VT.getSimpleVT().SimpleTy) {
19879 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19880 // i16 instructions are longer (0x66 prefix) and potentially slower.
19881 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19884 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19885 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19886 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19887 /// are assumed to be legal.
19889 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19891 if (!VT.isSimple())
19894 MVT SVT = VT.getSimpleVT();
19896 // Very little shuffling can be done for 64-bit vectors right now.
19897 if (VT.getSizeInBits() == 64)
19900 // If this is a single-input shuffle with no 128 bit lane crossings we can
19901 // lower it into pshufb.
19902 if ((SVT.is128BitVector() && Subtarget->hasSSSE3()) ||
19903 (SVT.is256BitVector() && Subtarget->hasInt256())) {
19904 bool isLegal = true;
19905 for (unsigned I = 0, E = M.size(); I != E; ++I) {
19906 if (M[I] >= (int)SVT.getVectorNumElements() ||
19907 ShuffleCrosses128bitLane(SVT, I, M[I])) {
19916 // FIXME: blends, shifts.
19917 return (SVT.getVectorNumElements() == 2 ||
19918 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
19919 isMOVLMask(M, SVT) ||
19920 isCommutedMOVLMask(M, SVT) ||
19921 isMOVHLPSMask(M, SVT) ||
19922 isSHUFPMask(M, SVT) ||
19923 isSHUFPMask(M, SVT, /* Commuted */ true) ||
19924 isPSHUFDMask(M, SVT) ||
19925 isPSHUFDMask(M, SVT, /* SecondOperand */ true) ||
19926 isPSHUFHWMask(M, SVT, Subtarget->hasInt256()) ||
19927 isPSHUFLWMask(M, SVT, Subtarget->hasInt256()) ||
19928 isPALIGNRMask(M, SVT, Subtarget) ||
19929 isUNPCKLMask(M, SVT, Subtarget->hasInt256()) ||
19930 isUNPCKHMask(M, SVT, Subtarget->hasInt256()) ||
19931 isUNPCKL_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19932 isUNPCKH_v_undef_Mask(M, SVT, Subtarget->hasInt256()) ||
19933 isBlendMask(M, SVT, Subtarget->hasSSE41(), Subtarget->hasInt256()) ||
19934 (Subtarget->hasSSE41() && isINSERTPSMask(M, SVT)));
19938 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19940 if (!VT.isSimple())
19943 MVT SVT = VT.getSimpleVT();
19944 unsigned NumElts = SVT.getVectorNumElements();
19945 // FIXME: This collection of masks seems suspect.
19948 if (NumElts == 4 && SVT.is128BitVector()) {
19949 return (isMOVLMask(Mask, SVT) ||
19950 isCommutedMOVLMask(Mask, SVT, true) ||
19951 isSHUFPMask(Mask, SVT) ||
19952 isSHUFPMask(Mask, SVT, /* Commuted */ true) ||
19953 isBlendMask(Mask, SVT, Subtarget->hasSSE41(),
19954 Subtarget->hasInt256()));
19959 //===----------------------------------------------------------------------===//
19960 // X86 Scheduler Hooks
19961 //===----------------------------------------------------------------------===//
19963 /// Utility function to emit xbegin specifying the start of an RTM region.
19964 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19965 const TargetInstrInfo *TII) {
19966 DebugLoc DL = MI->getDebugLoc();
19968 const BasicBlock *BB = MBB->getBasicBlock();
19969 MachineFunction::iterator I = MBB;
19972 // For the v = xbegin(), we generate
19983 MachineBasicBlock *thisMBB = MBB;
19984 MachineFunction *MF = MBB->getParent();
19985 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19986 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19987 MF->insert(I, mainMBB);
19988 MF->insert(I, sinkMBB);
19990 // Transfer the remainder of BB and its successor edges to sinkMBB.
19991 sinkMBB->splice(sinkMBB->begin(), MBB,
19992 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19993 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19997 // # fallthrough to mainMBB
19998 // # abortion to sinkMBB
19999 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20000 thisMBB->addSuccessor(mainMBB);
20001 thisMBB->addSuccessor(sinkMBB);
20005 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20006 mainMBB->addSuccessor(sinkMBB);
20009 // EAX is live into the sinkMBB
20010 sinkMBB->addLiveIn(X86::EAX);
20011 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20012 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20015 MI->eraseFromParent();
20019 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20020 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20021 // in the .td file.
20022 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20023 const TargetInstrInfo *TII) {
20025 switch (MI->getOpcode()) {
20026 default: llvm_unreachable("illegal opcode!");
20027 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20028 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20029 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20030 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20031 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20032 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20033 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20034 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20037 DebugLoc dl = MI->getDebugLoc();
20038 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20040 unsigned NumArgs = MI->getNumOperands();
20041 for (unsigned i = 1; i < NumArgs; ++i) {
20042 MachineOperand &Op = MI->getOperand(i);
20043 if (!(Op.isReg() && Op.isImplicit()))
20044 MIB.addOperand(Op);
20046 if (MI->hasOneMemOperand())
20047 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20049 BuildMI(*BB, MI, dl,
20050 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20051 .addReg(X86::XMM0);
20053 MI->eraseFromParent();
20057 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20058 // defs in an instruction pattern
20059 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20060 const TargetInstrInfo *TII) {
20062 switch (MI->getOpcode()) {
20063 default: llvm_unreachable("illegal opcode!");
20064 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20065 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20066 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20067 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20068 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20069 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20070 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20071 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20074 DebugLoc dl = MI->getDebugLoc();
20075 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20077 unsigned NumArgs = MI->getNumOperands(); // remove the results
20078 for (unsigned i = 1; i < NumArgs; ++i) {
20079 MachineOperand &Op = MI->getOperand(i);
20080 if (!(Op.isReg() && Op.isImplicit()))
20081 MIB.addOperand(Op);
20083 if (MI->hasOneMemOperand())
20084 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20086 BuildMI(*BB, MI, dl,
20087 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20090 MI->eraseFromParent();
20094 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20095 const TargetInstrInfo *TII,
20096 const X86Subtarget* Subtarget) {
20097 DebugLoc dl = MI->getDebugLoc();
20099 // Address into RAX/EAX, other two args into ECX, EDX.
20100 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20101 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20102 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20103 for (int i = 0; i < X86::AddrNumOperands; ++i)
20104 MIB.addOperand(MI->getOperand(i));
20106 unsigned ValOps = X86::AddrNumOperands;
20107 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20108 .addReg(MI->getOperand(ValOps).getReg());
20109 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20110 .addReg(MI->getOperand(ValOps+1).getReg());
20112 // The instruction doesn't actually take any operands though.
20113 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20115 MI->eraseFromParent(); // The pseudo is gone now.
20119 MachineBasicBlock *
20120 X86TargetLowering::EmitVAARG64WithCustomInserter(
20122 MachineBasicBlock *MBB) const {
20123 // Emit va_arg instruction on X86-64.
20125 // Operands to this pseudo-instruction:
20126 // 0 ) Output : destination address (reg)
20127 // 1-5) Input : va_list address (addr, i64mem)
20128 // 6 ) ArgSize : Size (in bytes) of vararg type
20129 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20130 // 8 ) Align : Alignment of type
20131 // 9 ) EFLAGS (implicit-def)
20133 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20134 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
20136 unsigned DestReg = MI->getOperand(0).getReg();
20137 MachineOperand &Base = MI->getOperand(1);
20138 MachineOperand &Scale = MI->getOperand(2);
20139 MachineOperand &Index = MI->getOperand(3);
20140 MachineOperand &Disp = MI->getOperand(4);
20141 MachineOperand &Segment = MI->getOperand(5);
20142 unsigned ArgSize = MI->getOperand(6).getImm();
20143 unsigned ArgMode = MI->getOperand(7).getImm();
20144 unsigned Align = MI->getOperand(8).getImm();
20146 // Memory Reference
20147 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20148 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20149 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20151 // Machine Information
20152 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20153 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20154 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20155 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20156 DebugLoc DL = MI->getDebugLoc();
20158 // struct va_list {
20161 // i64 overflow_area (address)
20162 // i64 reg_save_area (address)
20164 // sizeof(va_list) = 24
20165 // alignment(va_list) = 8
20167 unsigned TotalNumIntRegs = 6;
20168 unsigned TotalNumXMMRegs = 8;
20169 bool UseGPOffset = (ArgMode == 1);
20170 bool UseFPOffset = (ArgMode == 2);
20171 unsigned MaxOffset = TotalNumIntRegs * 8 +
20172 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20174 /* Align ArgSize to a multiple of 8 */
20175 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20176 bool NeedsAlign = (Align > 8);
20178 MachineBasicBlock *thisMBB = MBB;
20179 MachineBasicBlock *overflowMBB;
20180 MachineBasicBlock *offsetMBB;
20181 MachineBasicBlock *endMBB;
20183 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20184 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20185 unsigned OffsetReg = 0;
20187 if (!UseGPOffset && !UseFPOffset) {
20188 // If we only pull from the overflow region, we don't create a branch.
20189 // We don't need to alter control flow.
20190 OffsetDestReg = 0; // unused
20191 OverflowDestReg = DestReg;
20193 offsetMBB = nullptr;
20194 overflowMBB = thisMBB;
20197 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20198 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20199 // If not, pull from overflow_area. (branch to overflowMBB)
20204 // offsetMBB overflowMBB
20209 // Registers for the PHI in endMBB
20210 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20211 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20213 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20214 MachineFunction *MF = MBB->getParent();
20215 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20216 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20217 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20219 MachineFunction::iterator MBBIter = MBB;
20222 // Insert the new basic blocks
20223 MF->insert(MBBIter, offsetMBB);
20224 MF->insert(MBBIter, overflowMBB);
20225 MF->insert(MBBIter, endMBB);
20227 // Transfer the remainder of MBB and its successor edges to endMBB.
20228 endMBB->splice(endMBB->begin(), thisMBB,
20229 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20230 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20232 // Make offsetMBB and overflowMBB successors of thisMBB
20233 thisMBB->addSuccessor(offsetMBB);
20234 thisMBB->addSuccessor(overflowMBB);
20236 // endMBB is a successor of both offsetMBB and overflowMBB
20237 offsetMBB->addSuccessor(endMBB);
20238 overflowMBB->addSuccessor(endMBB);
20240 // Load the offset value into a register
20241 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20242 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20246 .addDisp(Disp, UseFPOffset ? 4 : 0)
20247 .addOperand(Segment)
20248 .setMemRefs(MMOBegin, MMOEnd);
20250 // Check if there is enough room left to pull this argument.
20251 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20253 .addImm(MaxOffset + 8 - ArgSizeA8);
20255 // Branch to "overflowMBB" if offset >= max
20256 // Fall through to "offsetMBB" otherwise
20257 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20258 .addMBB(overflowMBB);
20261 // In offsetMBB, emit code to use the reg_save_area.
20263 assert(OffsetReg != 0);
20265 // Read the reg_save_area address.
20266 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20267 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20272 .addOperand(Segment)
20273 .setMemRefs(MMOBegin, MMOEnd);
20275 // Zero-extend the offset
20276 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20277 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20280 .addImm(X86::sub_32bit);
20282 // Add the offset to the reg_save_area to get the final address.
20283 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20284 .addReg(OffsetReg64)
20285 .addReg(RegSaveReg);
20287 // Compute the offset for the next argument
20288 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20289 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20291 .addImm(UseFPOffset ? 16 : 8);
20293 // Store it back into the va_list.
20294 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20298 .addDisp(Disp, UseFPOffset ? 4 : 0)
20299 .addOperand(Segment)
20300 .addReg(NextOffsetReg)
20301 .setMemRefs(MMOBegin, MMOEnd);
20304 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
20309 // Emit code to use overflow area
20312 // Load the overflow_area address into a register.
20313 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20314 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20319 .addOperand(Segment)
20320 .setMemRefs(MMOBegin, MMOEnd);
20322 // If we need to align it, do so. Otherwise, just copy the address
20323 // to OverflowDestReg.
20325 // Align the overflow address
20326 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20327 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20329 // aligned_addr = (addr + (align-1)) & ~(align-1)
20330 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20331 .addReg(OverflowAddrReg)
20334 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20336 .addImm(~(uint64_t)(Align-1));
20338 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20339 .addReg(OverflowAddrReg);
20342 // Compute the next overflow address after this argument.
20343 // (the overflow address should be kept 8-byte aligned)
20344 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20345 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20346 .addReg(OverflowDestReg)
20347 .addImm(ArgSizeA8);
20349 // Store the new overflow address.
20350 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20355 .addOperand(Segment)
20356 .addReg(NextAddrReg)
20357 .setMemRefs(MMOBegin, MMOEnd);
20359 // If we branched, emit the PHI to the front of endMBB.
20361 BuildMI(*endMBB, endMBB->begin(), DL,
20362 TII->get(X86::PHI), DestReg)
20363 .addReg(OffsetDestReg).addMBB(offsetMBB)
20364 .addReg(OverflowDestReg).addMBB(overflowMBB);
20367 // Erase the pseudo instruction
20368 MI->eraseFromParent();
20373 MachineBasicBlock *
20374 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20376 MachineBasicBlock *MBB) const {
20377 // Emit code to save XMM registers to the stack. The ABI says that the
20378 // number of registers to save is given in %al, so it's theoretically
20379 // possible to do an indirect jump trick to avoid saving all of them,
20380 // however this code takes a simpler approach and just executes all
20381 // of the stores if %al is non-zero. It's less code, and it's probably
20382 // easier on the hardware branch predictor, and stores aren't all that
20383 // expensive anyway.
20385 // Create the new basic blocks. One block contains all the XMM stores,
20386 // and one block is the final destination regardless of whether any
20387 // stores were performed.
20388 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20389 MachineFunction *F = MBB->getParent();
20390 MachineFunction::iterator MBBIter = MBB;
20392 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20393 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20394 F->insert(MBBIter, XMMSaveMBB);
20395 F->insert(MBBIter, EndMBB);
20397 // Transfer the remainder of MBB and its successor edges to EndMBB.
20398 EndMBB->splice(EndMBB->begin(), MBB,
20399 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20400 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20402 // The original block will now fall through to the XMM save block.
20403 MBB->addSuccessor(XMMSaveMBB);
20404 // The XMMSaveMBB will fall through to the end block.
20405 XMMSaveMBB->addSuccessor(EndMBB);
20407 // Now add the instructions.
20408 const TargetInstrInfo *TII = MBB->getParent()->getSubtarget().getInstrInfo();
20409 DebugLoc DL = MI->getDebugLoc();
20411 unsigned CountReg = MI->getOperand(0).getReg();
20412 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20413 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20415 if (!Subtarget->isTargetWin64()) {
20416 // If %al is 0, branch around the XMM save block.
20417 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20418 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
20419 MBB->addSuccessor(EndMBB);
20422 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20423 // that was just emitted, but clearly shouldn't be "saved".
20424 assert((MI->getNumOperands() <= 3 ||
20425 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20426 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20427 && "Expected last argument to be EFLAGS");
20428 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20429 // In the XMM save block, save all the XMM argument registers.
20430 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20431 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20432 MachineMemOperand *MMO =
20433 F->getMachineMemOperand(
20434 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
20435 MachineMemOperand::MOStore,
20436 /*Size=*/16, /*Align=*/16);
20437 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20438 .addFrameIndex(RegSaveFrameIndex)
20439 .addImm(/*Scale=*/1)
20440 .addReg(/*IndexReg=*/0)
20441 .addImm(/*Disp=*/Offset)
20442 .addReg(/*Segment=*/0)
20443 .addReg(MI->getOperand(i).getReg())
20444 .addMemOperand(MMO);
20447 MI->eraseFromParent(); // The pseudo instruction is gone now.
20452 // The EFLAGS operand of SelectItr might be missing a kill marker
20453 // because there were multiple uses of EFLAGS, and ISel didn't know
20454 // which to mark. Figure out whether SelectItr should have had a
20455 // kill marker, and set it if it should. Returns the correct kill
20457 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20458 MachineBasicBlock* BB,
20459 const TargetRegisterInfo* TRI) {
20460 // Scan forward through BB for a use/def of EFLAGS.
20461 MachineBasicBlock::iterator miI(std::next(SelectItr));
20462 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20463 const MachineInstr& mi = *miI;
20464 if (mi.readsRegister(X86::EFLAGS))
20466 if (mi.definesRegister(X86::EFLAGS))
20467 break; // Should have kill-flag - update below.
20470 // If we hit the end of the block, check whether EFLAGS is live into a
20472 if (miI == BB->end()) {
20473 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20474 sEnd = BB->succ_end();
20475 sItr != sEnd; ++sItr) {
20476 MachineBasicBlock* succ = *sItr;
20477 if (succ->isLiveIn(X86::EFLAGS))
20482 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20483 // out. SelectMI should have a kill flag on EFLAGS.
20484 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20488 MachineBasicBlock *
20489 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20490 MachineBasicBlock *BB) const {
20491 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20492 DebugLoc DL = MI->getDebugLoc();
20494 // To "insert" a SELECT_CC instruction, we actually have to insert the
20495 // diamond control-flow pattern. The incoming instruction knows the
20496 // destination vreg to set, the condition code register to branch on, the
20497 // true/false values to select between, and a branch opcode to use.
20498 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20499 MachineFunction::iterator It = BB;
20505 // cmpTY ccX, r1, r2
20507 // fallthrough --> copy0MBB
20508 MachineBasicBlock *thisMBB = BB;
20509 MachineFunction *F = BB->getParent();
20510 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
20511 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
20512 F->insert(It, copy0MBB);
20513 F->insert(It, sinkMBB);
20515 // If the EFLAGS register isn't dead in the terminator, then claim that it's
20516 // live into the sink and copy blocks.
20517 const TargetRegisterInfo *TRI =
20518 BB->getParent()->getSubtarget().getRegisterInfo();
20519 if (!MI->killsRegister(X86::EFLAGS) &&
20520 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
20521 copy0MBB->addLiveIn(X86::EFLAGS);
20522 sinkMBB->addLiveIn(X86::EFLAGS);
20525 // Transfer the remainder of BB and its successor edges to sinkMBB.
20526 sinkMBB->splice(sinkMBB->begin(), BB,
20527 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20528 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
20530 // Add the true and fallthrough blocks as its successors.
20531 BB->addSuccessor(copy0MBB);
20532 BB->addSuccessor(sinkMBB);
20534 // Create the conditional branch instruction.
20536 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
20537 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
20540 // %FalseValue = ...
20541 // # fallthrough to sinkMBB
20542 copy0MBB->addSuccessor(sinkMBB);
20545 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
20547 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20548 TII->get(X86::PHI), MI->getOperand(0).getReg())
20549 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
20550 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
20552 MI->eraseFromParent(); // The pseudo instruction is gone now.
20556 MachineBasicBlock *
20557 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
20558 MachineBasicBlock *BB) const {
20559 MachineFunction *MF = BB->getParent();
20560 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20561 DebugLoc DL = MI->getDebugLoc();
20562 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20564 assert(MF->shouldSplitStack());
20566 const bool Is64Bit = Subtarget->is64Bit();
20567 const bool IsLP64 = Subtarget->isTarget64BitLP64();
20569 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
20570 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
20573 // ... [Till the alloca]
20574 // If stacklet is not large enough, jump to mallocMBB
20577 // Allocate by subtracting from RSP
20578 // Jump to continueMBB
20581 // Allocate by call to runtime
20585 // [rest of original BB]
20588 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20589 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20590 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20592 MachineRegisterInfo &MRI = MF->getRegInfo();
20593 const TargetRegisterClass *AddrRegClass =
20594 getRegClassFor(getPointerTy());
20596 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20597 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
20598 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
20599 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
20600 sizeVReg = MI->getOperand(1).getReg(),
20601 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
20603 MachineFunction::iterator MBBIter = BB;
20606 MF->insert(MBBIter, bumpMBB);
20607 MF->insert(MBBIter, mallocMBB);
20608 MF->insert(MBBIter, continueMBB);
20610 continueMBB->splice(continueMBB->begin(), BB,
20611 std::next(MachineBasicBlock::iterator(MI)), BB->end());
20612 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
20614 // Add code to the main basic block to check if the stack limit has been hit,
20615 // and if so, jump to mallocMBB otherwise to bumpMBB.
20616 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
20617 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
20618 .addReg(tmpSPVReg).addReg(sizeVReg);
20619 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
20620 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
20621 .addReg(SPLimitVReg);
20622 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
20624 // bumpMBB simply decreases the stack pointer, since we know the current
20625 // stacklet has enough space.
20626 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
20627 .addReg(SPLimitVReg);
20628 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
20629 .addReg(SPLimitVReg);
20630 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20632 // Calls into a routine in libgcc to allocate more space from the heap.
20633 const uint32_t *RegMask = MF->getTarget()
20634 .getSubtargetImpl()
20635 ->getRegisterInfo()
20636 ->getCallPreservedMask(CallingConv::C);
20638 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
20640 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20641 .addExternalSymbol("__morestack_allocate_stack_space")
20642 .addRegMask(RegMask)
20643 .addReg(X86::RDI, RegState::Implicit)
20644 .addReg(X86::RAX, RegState::ImplicitDefine);
20645 } else if (Is64Bit) {
20646 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
20648 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
20649 .addExternalSymbol("__morestack_allocate_stack_space")
20650 .addRegMask(RegMask)
20651 .addReg(X86::EDI, RegState::Implicit)
20652 .addReg(X86::EAX, RegState::ImplicitDefine);
20654 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
20656 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
20657 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
20658 .addExternalSymbol("__morestack_allocate_stack_space")
20659 .addRegMask(RegMask)
20660 .addReg(X86::EAX, RegState::ImplicitDefine);
20664 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
20667 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
20668 .addReg(IsLP64 ? X86::RAX : X86::EAX);
20669 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
20671 // Set up the CFG correctly.
20672 BB->addSuccessor(bumpMBB);
20673 BB->addSuccessor(mallocMBB);
20674 mallocMBB->addSuccessor(continueMBB);
20675 bumpMBB->addSuccessor(continueMBB);
20677 // Take care of the PHI nodes.
20678 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
20679 MI->getOperand(0).getReg())
20680 .addReg(mallocPtrVReg).addMBB(mallocMBB)
20681 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
20683 // Delete the original pseudo instruction.
20684 MI->eraseFromParent();
20687 return continueMBB;
20690 MachineBasicBlock *
20691 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
20692 MachineBasicBlock *BB) const {
20693 const TargetInstrInfo *TII = BB->getParent()->getSubtarget().getInstrInfo();
20694 DebugLoc DL = MI->getDebugLoc();
20696 assert(!Subtarget->isTargetMachO());
20698 // The lowering is pretty easy: we're just emitting the call to _alloca. The
20699 // non-trivial part is impdef of ESP.
20701 if (Subtarget->isTargetWin64()) {
20702 if (Subtarget->isTargetCygMing()) {
20703 // ___chkstk(Mingw64):
20704 // Clobbers R10, R11, RAX and EFLAGS.
20706 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20707 .addExternalSymbol("___chkstk")
20708 .addReg(X86::RAX, RegState::Implicit)
20709 .addReg(X86::RSP, RegState::Implicit)
20710 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
20711 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
20712 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20714 // __chkstk(MSVCRT): does not update stack pointer.
20715 // Clobbers R10, R11 and EFLAGS.
20716 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
20717 .addExternalSymbol("__chkstk")
20718 .addReg(X86::RAX, RegState::Implicit)
20719 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20720 // RAX has the offset to be subtracted from RSP.
20721 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
20726 const char *StackProbeSymbol = (Subtarget->isTargetKnownWindowsMSVC() ||
20727 Subtarget->isTargetWindowsItanium())
20731 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
20732 .addExternalSymbol(StackProbeSymbol)
20733 .addReg(X86::EAX, RegState::Implicit)
20734 .addReg(X86::ESP, RegState::Implicit)
20735 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
20736 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
20737 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
20740 MI->eraseFromParent(); // The pseudo instruction is gone now.
20744 MachineBasicBlock *
20745 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
20746 MachineBasicBlock *BB) const {
20747 // This is pretty easy. We're taking the value that we received from
20748 // our load from the relocation, sticking it in either RDI (x86-64)
20749 // or EAX and doing an indirect call. The return value will then
20750 // be in the normal return register.
20751 MachineFunction *F = BB->getParent();
20752 const X86InstrInfo *TII =
20753 static_cast<const X86InstrInfo *>(F->getSubtarget().getInstrInfo());
20754 DebugLoc DL = MI->getDebugLoc();
20756 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
20757 assert(MI->getOperand(3).isGlobal() && "This should be a global");
20759 // Get a register mask for the lowered call.
20760 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
20761 // proper register mask.
20762 const uint32_t *RegMask = F->getTarget()
20763 .getSubtargetImpl()
20764 ->getRegisterInfo()
20765 ->getCallPreservedMask(CallingConv::C);
20766 if (Subtarget->is64Bit()) {
20767 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20768 TII->get(X86::MOV64rm), X86::RDI)
20770 .addImm(0).addReg(0)
20771 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20772 MI->getOperand(3).getTargetFlags())
20774 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
20775 addDirectMem(MIB, X86::RDI);
20776 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
20777 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
20778 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20779 TII->get(X86::MOV32rm), X86::EAX)
20781 .addImm(0).addReg(0)
20782 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20783 MI->getOperand(3).getTargetFlags())
20785 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20786 addDirectMem(MIB, X86::EAX);
20787 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20789 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
20790 TII->get(X86::MOV32rm), X86::EAX)
20791 .addReg(TII->getGlobalBaseReg(F))
20792 .addImm(0).addReg(0)
20793 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
20794 MI->getOperand(3).getTargetFlags())
20796 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20797 addDirectMem(MIB, X86::EAX);
20798 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20801 MI->eraseFromParent(); // The pseudo instruction is gone now.
20805 MachineBasicBlock *
20806 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20807 MachineBasicBlock *MBB) const {
20808 DebugLoc DL = MI->getDebugLoc();
20809 MachineFunction *MF = MBB->getParent();
20810 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20811 MachineRegisterInfo &MRI = MF->getRegInfo();
20813 const BasicBlock *BB = MBB->getBasicBlock();
20814 MachineFunction::iterator I = MBB;
20817 // Memory Reference
20818 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20819 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20822 unsigned MemOpndSlot = 0;
20824 unsigned CurOp = 0;
20826 DstReg = MI->getOperand(CurOp++).getReg();
20827 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20828 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20829 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20830 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20832 MemOpndSlot = CurOp;
20834 MVT PVT = getPointerTy();
20835 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20836 "Invalid Pointer Size!");
20838 // For v = setjmp(buf), we generate
20841 // buf[LabelOffset] = restoreMBB
20842 // SjLjSetup restoreMBB
20848 // v = phi(main, restore)
20851 // if base pointer being used, load it from frame
20854 MachineBasicBlock *thisMBB = MBB;
20855 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20856 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20857 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20858 MF->insert(I, mainMBB);
20859 MF->insert(I, sinkMBB);
20860 MF->push_back(restoreMBB);
20862 MachineInstrBuilder MIB;
20864 // Transfer the remainder of BB and its successor edges to sinkMBB.
20865 sinkMBB->splice(sinkMBB->begin(), MBB,
20866 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20867 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20870 unsigned PtrStoreOpc = 0;
20871 unsigned LabelReg = 0;
20872 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20873 Reloc::Model RM = MF->getTarget().getRelocationModel();
20874 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20875 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20877 // Prepare IP either in reg or imm.
20878 if (!UseImmLabel) {
20879 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20880 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20881 LabelReg = MRI.createVirtualRegister(PtrRC);
20882 if (Subtarget->is64Bit()) {
20883 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20887 .addMBB(restoreMBB)
20890 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20891 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20892 .addReg(XII->getGlobalBaseReg(MF))
20895 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20899 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20901 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20902 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20903 if (i == X86::AddrDisp)
20904 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20906 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20909 MIB.addReg(LabelReg);
20911 MIB.addMBB(restoreMBB);
20912 MIB.setMemRefs(MMOBegin, MMOEnd);
20914 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20915 .addMBB(restoreMBB);
20917 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20918 MF->getSubtarget().getRegisterInfo());
20919 MIB.addRegMask(RegInfo->getNoPreservedMask());
20920 thisMBB->addSuccessor(mainMBB);
20921 thisMBB->addSuccessor(restoreMBB);
20925 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20926 mainMBB->addSuccessor(sinkMBB);
20929 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20930 TII->get(X86::PHI), DstReg)
20931 .addReg(mainDstReg).addMBB(mainMBB)
20932 .addReg(restoreDstReg).addMBB(restoreMBB);
20935 if (RegInfo->hasBasePointer(*MF)) {
20936 const X86Subtarget &STI = MF->getTarget().getSubtarget<X86Subtarget>();
20937 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
20938 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20939 X86FI->setRestoreBasePointer(MF);
20940 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20941 unsigned BasePtr = RegInfo->getBaseRegister();
20942 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20943 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20944 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20945 .setMIFlag(MachineInstr::FrameSetup);
20947 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20948 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
20949 restoreMBB->addSuccessor(sinkMBB);
20951 MI->eraseFromParent();
20955 MachineBasicBlock *
20956 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20957 MachineBasicBlock *MBB) const {
20958 DebugLoc DL = MI->getDebugLoc();
20959 MachineFunction *MF = MBB->getParent();
20960 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
20961 MachineRegisterInfo &MRI = MF->getRegInfo();
20963 // Memory Reference
20964 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20965 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20967 MVT PVT = getPointerTy();
20968 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20969 "Invalid Pointer Size!");
20971 const TargetRegisterClass *RC =
20972 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20973 unsigned Tmp = MRI.createVirtualRegister(RC);
20974 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20975 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>(
20976 MF->getSubtarget().getRegisterInfo());
20977 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20978 unsigned SP = RegInfo->getStackRegister();
20980 MachineInstrBuilder MIB;
20982 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20983 const int64_t SPOffset = 2 * PVT.getStoreSize();
20985 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20986 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20989 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20990 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20991 MIB.addOperand(MI->getOperand(i));
20992 MIB.setMemRefs(MMOBegin, MMOEnd);
20994 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20995 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20996 if (i == X86::AddrDisp)
20997 MIB.addDisp(MI->getOperand(i), LabelOffset);
20999 MIB.addOperand(MI->getOperand(i));
21001 MIB.setMemRefs(MMOBegin, MMOEnd);
21003 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21004 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21005 if (i == X86::AddrDisp)
21006 MIB.addDisp(MI->getOperand(i), SPOffset);
21008 MIB.addOperand(MI->getOperand(i));
21010 MIB.setMemRefs(MMOBegin, MMOEnd);
21012 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21014 MI->eraseFromParent();
21018 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21019 // accumulator loops. Writing back to the accumulator allows the coalescer
21020 // to remove extra copies in the loop.
21021 MachineBasicBlock *
21022 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21023 MachineBasicBlock *MBB) const {
21024 MachineOperand &AddendOp = MI->getOperand(3);
21026 // Bail out early if the addend isn't a register - we can't switch these.
21027 if (!AddendOp.isReg())
21030 MachineFunction &MF = *MBB->getParent();
21031 MachineRegisterInfo &MRI = MF.getRegInfo();
21033 // Check whether the addend is defined by a PHI:
21034 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21035 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21036 if (!AddendDef.isPHI())
21039 // Look for the following pattern:
21041 // %addend = phi [%entry, 0], [%loop, %result]
21043 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21047 // %addend = phi [%entry, 0], [%loop, %result]
21049 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21051 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21052 assert(AddendDef.getOperand(i).isReg());
21053 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21054 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21055 if (&PHISrcInst == MI) {
21056 // Found a matching instruction.
21057 unsigned NewFMAOpc = 0;
21058 switch (MI->getOpcode()) {
21059 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21060 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21061 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21062 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21063 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21064 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21065 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21066 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21067 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21068 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21069 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21070 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21071 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21072 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21073 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21074 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21075 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21076 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21077 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21078 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21080 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21081 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21082 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21083 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21084 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21085 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21086 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21087 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21088 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21089 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21090 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21091 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21092 default: llvm_unreachable("Unrecognized FMA variant.");
21095 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
21096 MachineInstrBuilder MIB =
21097 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21098 .addOperand(MI->getOperand(0))
21099 .addOperand(MI->getOperand(3))
21100 .addOperand(MI->getOperand(2))
21101 .addOperand(MI->getOperand(1));
21102 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21103 MI->eraseFromParent();
21110 MachineBasicBlock *
21111 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21112 MachineBasicBlock *BB) const {
21113 switch (MI->getOpcode()) {
21114 default: llvm_unreachable("Unexpected instr type to insert");
21115 case X86::TAILJMPd64:
21116 case X86::TAILJMPr64:
21117 case X86::TAILJMPm64:
21118 llvm_unreachable("TAILJMP64 would not be touched here.");
21119 case X86::TCRETURNdi64:
21120 case X86::TCRETURNri64:
21121 case X86::TCRETURNmi64:
21123 case X86::WIN_ALLOCA:
21124 return EmitLoweredWinAlloca(MI, BB);
21125 case X86::SEG_ALLOCA_32:
21126 case X86::SEG_ALLOCA_64:
21127 return EmitLoweredSegAlloca(MI, BB);
21128 case X86::TLSCall_32:
21129 case X86::TLSCall_64:
21130 return EmitLoweredTLSCall(MI, BB);
21131 case X86::CMOV_GR8:
21132 case X86::CMOV_FR32:
21133 case X86::CMOV_FR64:
21134 case X86::CMOV_V4F32:
21135 case X86::CMOV_V2F64:
21136 case X86::CMOV_V2I64:
21137 case X86::CMOV_V8F32:
21138 case X86::CMOV_V4F64:
21139 case X86::CMOV_V4I64:
21140 case X86::CMOV_V16F32:
21141 case X86::CMOV_V8F64:
21142 case X86::CMOV_V8I64:
21143 case X86::CMOV_GR16:
21144 case X86::CMOV_GR32:
21145 case X86::CMOV_RFP32:
21146 case X86::CMOV_RFP64:
21147 case X86::CMOV_RFP80:
21148 return EmitLoweredSelect(MI, BB);
21150 case X86::FP32_TO_INT16_IN_MEM:
21151 case X86::FP32_TO_INT32_IN_MEM:
21152 case X86::FP32_TO_INT64_IN_MEM:
21153 case X86::FP64_TO_INT16_IN_MEM:
21154 case X86::FP64_TO_INT32_IN_MEM:
21155 case X86::FP64_TO_INT64_IN_MEM:
21156 case X86::FP80_TO_INT16_IN_MEM:
21157 case X86::FP80_TO_INT32_IN_MEM:
21158 case X86::FP80_TO_INT64_IN_MEM: {
21159 MachineFunction *F = BB->getParent();
21160 const TargetInstrInfo *TII = F->getSubtarget().getInstrInfo();
21161 DebugLoc DL = MI->getDebugLoc();
21163 // Change the floating point control register to use "round towards zero"
21164 // mode when truncating to an integer value.
21165 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21166 addFrameReference(BuildMI(*BB, MI, DL,
21167 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21169 // Load the old value of the high byte of the control word...
21171 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21172 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21175 // Set the high part to be round to zero...
21176 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21179 // Reload the modified control word now...
21180 addFrameReference(BuildMI(*BB, MI, DL,
21181 TII->get(X86::FLDCW16m)), CWFrameIdx);
21183 // Restore the memory image of control word to original value
21184 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21187 // Get the X86 opcode to use.
21189 switch (MI->getOpcode()) {
21190 default: llvm_unreachable("illegal opcode!");
21191 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21192 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21193 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21194 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21195 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21196 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21197 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21198 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21199 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21203 MachineOperand &Op = MI->getOperand(0);
21205 AM.BaseType = X86AddressMode::RegBase;
21206 AM.Base.Reg = Op.getReg();
21208 AM.BaseType = X86AddressMode::FrameIndexBase;
21209 AM.Base.FrameIndex = Op.getIndex();
21211 Op = MI->getOperand(1);
21213 AM.Scale = Op.getImm();
21214 Op = MI->getOperand(2);
21216 AM.IndexReg = Op.getImm();
21217 Op = MI->getOperand(3);
21218 if (Op.isGlobal()) {
21219 AM.GV = Op.getGlobal();
21221 AM.Disp = Op.getImm();
21223 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21224 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21226 // Reload the original control word now.
21227 addFrameReference(BuildMI(*BB, MI, DL,
21228 TII->get(X86::FLDCW16m)), CWFrameIdx);
21230 MI->eraseFromParent(); // The pseudo instruction is gone now.
21233 // String/text processing lowering.
21234 case X86::PCMPISTRM128REG:
21235 case X86::VPCMPISTRM128REG:
21236 case X86::PCMPISTRM128MEM:
21237 case X86::VPCMPISTRM128MEM:
21238 case X86::PCMPESTRM128REG:
21239 case X86::VPCMPESTRM128REG:
21240 case X86::PCMPESTRM128MEM:
21241 case X86::VPCMPESTRM128MEM:
21242 assert(Subtarget->hasSSE42() &&
21243 "Target must have SSE4.2 or AVX features enabled");
21244 return EmitPCMPSTRM(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21246 // String/text processing lowering.
21247 case X86::PCMPISTRIREG:
21248 case X86::VPCMPISTRIREG:
21249 case X86::PCMPISTRIMEM:
21250 case X86::VPCMPISTRIMEM:
21251 case X86::PCMPESTRIREG:
21252 case X86::VPCMPESTRIREG:
21253 case X86::PCMPESTRIMEM:
21254 case X86::VPCMPESTRIMEM:
21255 assert(Subtarget->hasSSE42() &&
21256 "Target must have SSE4.2 or AVX features enabled");
21257 return EmitPCMPSTRI(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21259 // Thread synchronization.
21261 return EmitMonitor(MI, BB, BB->getParent()->getSubtarget().getInstrInfo(),
21266 return EmitXBegin(MI, BB, BB->getParent()->getSubtarget().getInstrInfo());
21268 case X86::VASTART_SAVE_XMM_REGS:
21269 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21271 case X86::VAARG_64:
21272 return EmitVAARG64WithCustomInserter(MI, BB);
21274 case X86::EH_SjLj_SetJmp32:
21275 case X86::EH_SjLj_SetJmp64:
21276 return emitEHSjLjSetJmp(MI, BB);
21278 case X86::EH_SjLj_LongJmp32:
21279 case X86::EH_SjLj_LongJmp64:
21280 return emitEHSjLjLongJmp(MI, BB);
21282 case TargetOpcode::STATEPOINT:
21283 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21284 // this point in the process. We diverge later.
21285 return emitPatchPoint(MI, BB);
21287 case TargetOpcode::STACKMAP:
21288 case TargetOpcode::PATCHPOINT:
21289 return emitPatchPoint(MI, BB);
21291 case X86::VFMADDPDr213r:
21292 case X86::VFMADDPSr213r:
21293 case X86::VFMADDSDr213r:
21294 case X86::VFMADDSSr213r:
21295 case X86::VFMSUBPDr213r:
21296 case X86::VFMSUBPSr213r:
21297 case X86::VFMSUBSDr213r:
21298 case X86::VFMSUBSSr213r:
21299 case X86::VFNMADDPDr213r:
21300 case X86::VFNMADDPSr213r:
21301 case X86::VFNMADDSDr213r:
21302 case X86::VFNMADDSSr213r:
21303 case X86::VFNMSUBPDr213r:
21304 case X86::VFNMSUBPSr213r:
21305 case X86::VFNMSUBSDr213r:
21306 case X86::VFNMSUBSSr213r:
21307 case X86::VFMADDSUBPDr213r:
21308 case X86::VFMADDSUBPSr213r:
21309 case X86::VFMSUBADDPDr213r:
21310 case X86::VFMSUBADDPSr213r:
21311 case X86::VFMADDPDr213rY:
21312 case X86::VFMADDPSr213rY:
21313 case X86::VFMSUBPDr213rY:
21314 case X86::VFMSUBPSr213rY:
21315 case X86::VFNMADDPDr213rY:
21316 case X86::VFNMADDPSr213rY:
21317 case X86::VFNMSUBPDr213rY:
21318 case X86::VFNMSUBPSr213rY:
21319 case X86::VFMADDSUBPDr213rY:
21320 case X86::VFMADDSUBPSr213rY:
21321 case X86::VFMSUBADDPDr213rY:
21322 case X86::VFMSUBADDPSr213rY:
21323 return emitFMA3Instr(MI, BB);
21327 //===----------------------------------------------------------------------===//
21328 // X86 Optimization Hooks
21329 //===----------------------------------------------------------------------===//
21331 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21334 const SelectionDAG &DAG,
21335 unsigned Depth) const {
21336 unsigned BitWidth = KnownZero.getBitWidth();
21337 unsigned Opc = Op.getOpcode();
21338 assert((Opc >= ISD::BUILTIN_OP_END ||
21339 Opc == ISD::INTRINSIC_WO_CHAIN ||
21340 Opc == ISD::INTRINSIC_W_CHAIN ||
21341 Opc == ISD::INTRINSIC_VOID) &&
21342 "Should use MaskedValueIsZero if you don't know whether Op"
21343 " is a target node!");
21345 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
21359 // These nodes' second result is a boolean.
21360 if (Op.getResNo() == 0)
21363 case X86ISD::SETCC:
21364 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
21366 case ISD::INTRINSIC_WO_CHAIN: {
21367 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
21368 unsigned NumLoBits = 0;
21371 case Intrinsic::x86_sse_movmsk_ps:
21372 case Intrinsic::x86_avx_movmsk_ps_256:
21373 case Intrinsic::x86_sse2_movmsk_pd:
21374 case Intrinsic::x86_avx_movmsk_pd_256:
21375 case Intrinsic::x86_mmx_pmovmskb:
21376 case Intrinsic::x86_sse2_pmovmskb_128:
21377 case Intrinsic::x86_avx2_pmovmskb: {
21378 // High bits of movmskp{s|d}, pmovmskb are known zero.
21380 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
21381 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
21382 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
21383 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
21384 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
21385 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
21386 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
21387 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
21389 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
21398 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
21400 const SelectionDAG &,
21401 unsigned Depth) const {
21402 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
21403 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
21404 return Op.getValueType().getScalarType().getSizeInBits();
21410 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
21411 /// node is a GlobalAddress + offset.
21412 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
21413 const GlobalValue* &GA,
21414 int64_t &Offset) const {
21415 if (N->getOpcode() == X86ISD::Wrapper) {
21416 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
21417 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
21418 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
21422 return TargetLowering::isGAPlusOffset(N, GA, Offset);
21425 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
21426 /// same as extracting the high 128-bit part of 256-bit vector and then
21427 /// inserting the result into the low part of a new 256-bit vector
21428 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
21429 EVT VT = SVOp->getValueType(0);
21430 unsigned NumElems = VT.getVectorNumElements();
21432 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21433 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
21434 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21435 SVOp->getMaskElt(j) >= 0)
21441 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
21442 /// same as extracting the low 128-bit part of 256-bit vector and then
21443 /// inserting the result into the high part of a new 256-bit vector
21444 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
21445 EVT VT = SVOp->getValueType(0);
21446 unsigned NumElems = VT.getVectorNumElements();
21448 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21449 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
21450 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
21451 SVOp->getMaskElt(j) >= 0)
21457 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
21458 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
21459 TargetLowering::DAGCombinerInfo &DCI,
21460 const X86Subtarget* Subtarget) {
21462 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21463 SDValue V1 = SVOp->getOperand(0);
21464 SDValue V2 = SVOp->getOperand(1);
21465 EVT VT = SVOp->getValueType(0);
21466 unsigned NumElems = VT.getVectorNumElements();
21468 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
21469 V2.getOpcode() == ISD::CONCAT_VECTORS) {
21473 // V UNDEF BUILD_VECTOR UNDEF
21475 // CONCAT_VECTOR CONCAT_VECTOR
21478 // RESULT: V + zero extended
21480 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
21481 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
21482 V1.getOperand(1).getOpcode() != ISD::UNDEF)
21485 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
21488 // To match the shuffle mask, the first half of the mask should
21489 // be exactly the first vector, and all the rest a splat with the
21490 // first element of the second one.
21491 for (unsigned i = 0; i != NumElems/2; ++i)
21492 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
21493 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
21496 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
21497 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
21498 if (Ld->hasNUsesOfValue(1, 0)) {
21499 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
21500 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
21502 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
21504 Ld->getPointerInfo(),
21505 Ld->getAlignment(),
21506 false/*isVolatile*/, true/*ReadMem*/,
21507 false/*WriteMem*/);
21509 // Make sure the newly-created LOAD is in the same position as Ld in
21510 // terms of dependency. We create a TokenFactor for Ld and ResNode,
21511 // and update uses of Ld's output chain to use the TokenFactor.
21512 if (Ld->hasAnyUseOfValue(1)) {
21513 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
21514 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
21515 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
21516 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
21517 SDValue(ResNode.getNode(), 1));
21520 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
21524 // Emit a zeroed vector and insert the desired subvector on its
21526 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
21527 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
21528 return DCI.CombineTo(N, InsV);
21531 //===--------------------------------------------------------------------===//
21532 // Combine some shuffles into subvector extracts and inserts:
21535 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
21536 if (isShuffleHigh128VectorInsertLow(SVOp)) {
21537 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
21538 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
21539 return DCI.CombineTo(N, InsV);
21542 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
21543 if (isShuffleLow128VectorInsertHigh(SVOp)) {
21544 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
21545 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
21546 return DCI.CombineTo(N, InsV);
21552 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
21555 /// This is the leaf of the recursive combinine below. When we have found some
21556 /// chain of single-use x86 shuffle instructions and accumulated the combined
21557 /// shuffle mask represented by them, this will try to pattern match that mask
21558 /// into either a single instruction if there is a special purpose instruction
21559 /// for this operation, or into a PSHUFB instruction which is a fully general
21560 /// instruction but should only be used to replace chains over a certain depth.
21561 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
21562 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
21563 TargetLowering::DAGCombinerInfo &DCI,
21564 const X86Subtarget *Subtarget) {
21565 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
21567 // Find the operand that enters the chain. Note that multiple uses are OK
21568 // here, we're not going to remove the operand we find.
21569 SDValue Input = Op.getOperand(0);
21570 while (Input.getOpcode() == ISD::BITCAST)
21571 Input = Input.getOperand(0);
21573 MVT VT = Input.getSimpleValueType();
21574 MVT RootVT = Root.getSimpleValueType();
21577 // Just remove no-op shuffle masks.
21578 if (Mask.size() == 1) {
21579 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Input),
21584 // Use the float domain if the operand type is a floating point type.
21585 bool FloatDomain = VT.isFloatingPoint();
21587 // For floating point shuffles, we don't have free copies in the shuffle
21588 // instructions or the ability to load as part of the instruction, so
21589 // canonicalize their shuffles to UNPCK or MOV variants.
21591 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
21592 // vectors because it can have a load folded into it that UNPCK cannot. This
21593 // doesn't preclude something switching to the shorter encoding post-RA.
21595 if (Mask.equals(0, 0) || Mask.equals(1, 1)) {
21596 bool Lo = Mask.equals(0, 0);
21599 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
21600 // is no slower than UNPCKLPD but has the option to fold the input operand
21601 // into even an unaligned memory load.
21602 if (Lo && Subtarget->hasSSE3()) {
21603 Shuffle = X86ISD::MOVDDUP;
21604 ShuffleVT = MVT::v2f64;
21606 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
21607 // than the UNPCK variants.
21608 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
21609 ShuffleVT = MVT::v4f32;
21611 if (Depth == 1 && Root->getOpcode() == Shuffle)
21612 return false; // Nothing to do!
21613 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21614 DCI.AddToWorklist(Op.getNode());
21615 if (Shuffle == X86ISD::MOVDDUP)
21616 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21618 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21619 DCI.AddToWorklist(Op.getNode());
21620 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21624 if (Subtarget->hasSSE3() &&
21625 (Mask.equals(0, 0, 2, 2) || Mask.equals(1, 1, 3, 3))) {
21626 bool Lo = Mask.equals(0, 0, 2, 2);
21627 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
21628 MVT ShuffleVT = MVT::v4f32;
21629 if (Depth == 1 && Root->getOpcode() == Shuffle)
21630 return false; // Nothing to do!
21631 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21632 DCI.AddToWorklist(Op.getNode());
21633 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
21634 DCI.AddToWorklist(Op.getNode());
21635 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21639 if (Mask.equals(0, 0, 1, 1) || Mask.equals(2, 2, 3, 3)) {
21640 bool Lo = Mask.equals(0, 0, 1, 1);
21641 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21642 MVT ShuffleVT = MVT::v4f32;
21643 if (Depth == 1 && Root->getOpcode() == Shuffle)
21644 return false; // Nothing to do!
21645 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21646 DCI.AddToWorklist(Op.getNode());
21647 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21648 DCI.AddToWorklist(Op.getNode());
21649 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21655 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
21656 // variants as none of these have single-instruction variants that are
21657 // superior to the UNPCK formulation.
21658 if (!FloatDomain &&
21659 (Mask.equals(0, 0, 1, 1, 2, 2, 3, 3) ||
21660 Mask.equals(4, 4, 5, 5, 6, 6, 7, 7) ||
21661 Mask.equals(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7) ||
21662 Mask.equals(8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15,
21664 bool Lo = Mask[0] == 0;
21665 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
21666 if (Depth == 1 && Root->getOpcode() == Shuffle)
21667 return false; // Nothing to do!
21669 switch (Mask.size()) {
21671 ShuffleVT = MVT::v8i16;
21674 ShuffleVT = MVT::v16i8;
21677 llvm_unreachable("Impossible mask size!");
21679 Op = DAG.getNode(ISD::BITCAST, DL, ShuffleVT, Input);
21680 DCI.AddToWorklist(Op.getNode());
21681 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
21682 DCI.AddToWorklist(Op.getNode());
21683 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21688 // Don't try to re-form single instruction chains under any circumstances now
21689 // that we've done encoding canonicalization for them.
21693 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
21694 // can replace them with a single PSHUFB instruction profitably. Intel's
21695 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
21696 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
21697 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
21698 SmallVector<SDValue, 16> PSHUFBMask;
21699 assert(Mask.size() <= 16 && "Can't shuffle elements smaller than bytes!");
21700 int Ratio = 16 / Mask.size();
21701 for (unsigned i = 0; i < 16; ++i) {
21702 if (Mask[i / Ratio] == SM_SentinelUndef) {
21703 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
21706 int M = Mask[i / Ratio] != SM_SentinelZero
21707 ? Ratio * Mask[i / Ratio] + i % Ratio
21709 PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));
21711 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Input);
21712 DCI.AddToWorklist(Op.getNode());
21713 SDValue PSHUFBMaskOp =
21714 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, PSHUFBMask);
21715 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
21716 Op = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, Op, PSHUFBMaskOp);
21717 DCI.AddToWorklist(Op.getNode());
21718 DCI.CombineTo(Root.getNode(), DAG.getNode(ISD::BITCAST, DL, RootVT, Op),
21723 // Failed to find any combines.
21727 /// \brief Fully generic combining of x86 shuffle instructions.
21729 /// This should be the last combine run over the x86 shuffle instructions. Once
21730 /// they have been fully optimized, this will recursively consider all chains
21731 /// of single-use shuffle instructions, build a generic model of the cumulative
21732 /// shuffle operation, and check for simpler instructions which implement this
21733 /// operation. We use this primarily for two purposes:
21735 /// 1) Collapse generic shuffles to specialized single instructions when
21736 /// equivalent. In most cases, this is just an encoding size win, but
21737 /// sometimes we will collapse multiple generic shuffles into a single
21738 /// special-purpose shuffle.
21739 /// 2) Look for sequences of shuffle instructions with 3 or more total
21740 /// instructions, and replace them with the slightly more expensive SSSE3
21741 /// PSHUFB instruction if available. We do this as the last combining step
21742 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
21743 /// a suitable short sequence of other instructions. The PHUFB will either
21744 /// use a register or have to read from memory and so is slightly (but only
21745 /// slightly) more expensive than the other shuffle instructions.
21747 /// Because this is inherently a quadratic operation (for each shuffle in
21748 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
21749 /// This should never be an issue in practice as the shuffle lowering doesn't
21750 /// produce sequences of more than 8 instructions.
21752 /// FIXME: We will currently miss some cases where the redundant shuffling
21753 /// would simplify under the threshold for PSHUFB formation because of
21754 /// combine-ordering. To fix this, we should do the redundant instruction
21755 /// combining in this recursive walk.
21756 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
21757 ArrayRef<int> RootMask,
21758 int Depth, bool HasPSHUFB,
21760 TargetLowering::DAGCombinerInfo &DCI,
21761 const X86Subtarget *Subtarget) {
21762 // Bound the depth of our recursive combine because this is ultimately
21763 // quadratic in nature.
21767 // Directly rip through bitcasts to find the underlying operand.
21768 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
21769 Op = Op.getOperand(0);
21771 MVT VT = Op.getSimpleValueType();
21772 if (!VT.isVector())
21773 return false; // Bail if we hit a non-vector.
21774 // FIXME: This routine should be taught about 256-bit shuffles, or a 256-bit
21775 // version should be added.
21776 if (VT.getSizeInBits() != 128)
21779 assert(Root.getSimpleValueType().isVector() &&
21780 "Shuffles operate on vector types!");
21781 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
21782 "Can only combine shuffles of the same vector register size.");
21784 if (!isTargetShuffle(Op.getOpcode()))
21786 SmallVector<int, 16> OpMask;
21788 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
21789 // We only can combine unary shuffles which we can decode the mask for.
21790 if (!HaveMask || !IsUnary)
21793 assert(VT.getVectorNumElements() == OpMask.size() &&
21794 "Different mask size from vector size!");
21795 assert(((RootMask.size() > OpMask.size() &&
21796 RootMask.size() % OpMask.size() == 0) ||
21797 (OpMask.size() > RootMask.size() &&
21798 OpMask.size() % RootMask.size() == 0) ||
21799 OpMask.size() == RootMask.size()) &&
21800 "The smaller number of elements must divide the larger.");
21801 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21802 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21803 assert(((RootRatio == 1 && OpRatio == 1) ||
21804 (RootRatio == 1) != (OpRatio == 1)) &&
21805 "Must not have a ratio for both incoming and op masks!");
21807 SmallVector<int, 16> Mask;
21808 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21810 // Merge this shuffle operation's mask into our accumulated mask. Note that
21811 // this shuffle's mask will be the first applied to the input, followed by the
21812 // root mask to get us all the way to the root value arrangement. The reason
21813 // for this order is that we are recursing up the operation chain.
21814 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21815 int RootIdx = i / RootRatio;
21816 if (RootMask[RootIdx] < 0) {
21817 // This is a zero or undef lane, we're done.
21818 Mask.push_back(RootMask[RootIdx]);
21822 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21823 int OpIdx = RootMaskedIdx / OpRatio;
21824 if (OpMask[OpIdx] < 0) {
21825 // The incoming lanes are zero or undef, it doesn't matter which ones we
21827 Mask.push_back(OpMask[OpIdx]);
21831 // Ok, we have non-zero lanes, map them through.
21832 Mask.push_back(OpMask[OpIdx] * OpRatio +
21833 RootMaskedIdx % OpRatio);
21836 // See if we can recurse into the operand to combine more things.
21837 switch (Op.getOpcode()) {
21838 case X86ISD::PSHUFB:
21840 case X86ISD::PSHUFD:
21841 case X86ISD::PSHUFHW:
21842 case X86ISD::PSHUFLW:
21843 if (Op.getOperand(0).hasOneUse() &&
21844 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21845 HasPSHUFB, DAG, DCI, Subtarget))
21849 case X86ISD::UNPCKL:
21850 case X86ISD::UNPCKH:
21851 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21852 // We can't check for single use, we have to check that this shuffle is the only user.
21853 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21854 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21855 HasPSHUFB, DAG, DCI, Subtarget))
21860 // Minor canonicalization of the accumulated shuffle mask to make it easier
21861 // to match below. All this does is detect masks with squential pairs of
21862 // elements, and shrink them to the half-width mask. It does this in a loop
21863 // so it will reduce the size of the mask to the minimal width mask which
21864 // performs an equivalent shuffle.
21865 SmallVector<int, 16> WidenedMask;
21866 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21867 Mask = std::move(WidenedMask);
21868 WidenedMask.clear();
21871 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21875 /// \brief Get the PSHUF-style mask from PSHUF node.
21877 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21878 /// PSHUF-style masks that can be reused with such instructions.
21879 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21880 SmallVector<int, 4> Mask;
21882 bool HaveMask = getTargetShuffleMask(N.getNode(), N.getSimpleValueType(), Mask, IsUnary);
21886 switch (N.getOpcode()) {
21887 case X86ISD::PSHUFD:
21889 case X86ISD::PSHUFLW:
21892 case X86ISD::PSHUFHW:
21893 Mask.erase(Mask.begin(), Mask.begin() + 4);
21894 for (int &M : Mask)
21898 llvm_unreachable("No valid shuffle instruction found!");
21902 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21904 /// We walk up the chain and look for a combinable shuffle, skipping over
21905 /// shuffles that we could hoist this shuffle's transformation past without
21906 /// altering anything.
21908 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21910 TargetLowering::DAGCombinerInfo &DCI) {
21911 assert(N.getOpcode() == X86ISD::PSHUFD &&
21912 "Called with something other than an x86 128-bit half shuffle!");
21915 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21916 // of the shuffles in the chain so that we can form a fresh chain to replace
21918 SmallVector<SDValue, 8> Chain;
21919 SDValue V = N.getOperand(0);
21920 for (; V.hasOneUse(); V = V.getOperand(0)) {
21921 switch (V.getOpcode()) {
21923 return SDValue(); // Nothing combined!
21926 // Skip bitcasts as we always know the type for the target specific
21930 case X86ISD::PSHUFD:
21931 // Found another dword shuffle.
21934 case X86ISD::PSHUFLW:
21935 // Check that the low words (being shuffled) are the identity in the
21936 // dword shuffle, and the high words are self-contained.
21937 if (Mask[0] != 0 || Mask[1] != 1 ||
21938 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21941 Chain.push_back(V);
21944 case X86ISD::PSHUFHW:
21945 // Check that the high words (being shuffled) are the identity in the
21946 // dword shuffle, and the low words are self-contained.
21947 if (Mask[2] != 2 || Mask[3] != 3 ||
21948 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21951 Chain.push_back(V);
21954 case X86ISD::UNPCKL:
21955 case X86ISD::UNPCKH:
21956 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21957 // shuffle into a preceding word shuffle.
21958 if (V.getValueType() != MVT::v16i8 && V.getValueType() != MVT::v8i16)
21961 // Search for a half-shuffle which we can combine with.
21962 unsigned CombineOp =
21963 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21964 if (V.getOperand(0) != V.getOperand(1) ||
21965 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21967 Chain.push_back(V);
21968 V = V.getOperand(0);
21970 switch (V.getOpcode()) {
21972 return SDValue(); // Nothing to combine.
21974 case X86ISD::PSHUFLW:
21975 case X86ISD::PSHUFHW:
21976 if (V.getOpcode() == CombineOp)
21979 Chain.push_back(V);
21983 V = V.getOperand(0);
21987 } while (V.hasOneUse());
21990 // Break out of the loop if we break out of the switch.
21994 if (!V.hasOneUse())
21995 // We fell out of the loop without finding a viable combining instruction.
21998 // Merge this node's mask and our incoming mask.
21999 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22000 for (int &M : Mask)
22002 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22003 getV4X86ShuffleImm8ForMask(Mask, DAG));
22005 // Rebuild the chain around this new shuffle.
22006 while (!Chain.empty()) {
22007 SDValue W = Chain.pop_back_val();
22009 if (V.getValueType() != W.getOperand(0).getValueType())
22010 V = DAG.getNode(ISD::BITCAST, DL, W.getOperand(0).getValueType(), V);
22012 switch (W.getOpcode()) {
22014 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22016 case X86ISD::UNPCKL:
22017 case X86ISD::UNPCKH:
22018 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22021 case X86ISD::PSHUFD:
22022 case X86ISD::PSHUFLW:
22023 case X86ISD::PSHUFHW:
22024 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22028 if (V.getValueType() != N.getValueType())
22029 V = DAG.getNode(ISD::BITCAST, DL, N.getValueType(), V);
22031 // Return the new chain to replace N.
22035 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
22037 /// We walk up the chain, skipping shuffles of the other half and looking
22038 /// through shuffles which switch halves trying to find a shuffle of the same
22039 /// pair of dwords.
22040 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22042 TargetLowering::DAGCombinerInfo &DCI) {
22044 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22045 "Called with something other than an x86 128-bit half shuffle!");
22047 unsigned CombineOpcode = N.getOpcode();
22049 // Walk up a single-use chain looking for a combinable shuffle.
22050 SDValue V = N.getOperand(0);
22051 for (; V.hasOneUse(); V = V.getOperand(0)) {
22052 switch (V.getOpcode()) {
22054 return false; // Nothing combined!
22057 // Skip bitcasts as we always know the type for the target specific
22061 case X86ISD::PSHUFLW:
22062 case X86ISD::PSHUFHW:
22063 if (V.getOpcode() == CombineOpcode)
22066 // Other-half shuffles are no-ops.
22069 // Break out of the loop if we break out of the switch.
22073 if (!V.hasOneUse())
22074 // We fell out of the loop without finding a viable combining instruction.
22077 // Combine away the bottom node as its shuffle will be accumulated into
22078 // a preceding shuffle.
22079 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22081 // Record the old value.
22084 // Merge this node's mask and our incoming mask (adjusted to account for all
22085 // the pshufd instructions encountered).
22086 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22087 for (int &M : Mask)
22089 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22090 getV4X86ShuffleImm8ForMask(Mask, DAG));
22092 // Check that the shuffles didn't cancel each other out. If not, we need to
22093 // combine to the new one.
22095 // Replace the combinable shuffle with the combined one, updating all users
22096 // so that we re-evaluate the chain here.
22097 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22102 /// \brief Try to combine x86 target specific shuffles.
22103 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22104 TargetLowering::DAGCombinerInfo &DCI,
22105 const X86Subtarget *Subtarget) {
22107 MVT VT = N.getSimpleValueType();
22108 SmallVector<int, 4> Mask;
22110 switch (N.getOpcode()) {
22111 case X86ISD::PSHUFD:
22112 case X86ISD::PSHUFLW:
22113 case X86ISD::PSHUFHW:
22114 Mask = getPSHUFShuffleMask(N);
22115 assert(Mask.size() == 4);
22121 // Nuke no-op shuffles that show up after combining.
22122 if (isNoopShuffleMask(Mask))
22123 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22125 // Look for simplifications involving one or two shuffle instructions.
22126 SDValue V = N.getOperand(0);
22127 switch (N.getOpcode()) {
22130 case X86ISD::PSHUFLW:
22131 case X86ISD::PSHUFHW:
22132 assert(VT == MVT::v8i16);
22135 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22136 return SDValue(); // We combined away this shuffle, so we're done.
22138 // See if this reduces to a PSHUFD which is no more expensive and can
22139 // combine with more operations. Note that it has to at least flip the
22140 // dwords as otherwise it would have been removed as a no-op.
22141 if (Mask[0] == 2 && Mask[1] == 3 && Mask[2] == 0 && Mask[3] == 1) {
22142 int DMask[] = {0, 1, 2, 3};
22143 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22144 DMask[DOffset + 0] = DOffset + 1;
22145 DMask[DOffset + 1] = DOffset + 0;
22146 V = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, V);
22147 DCI.AddToWorklist(V.getNode());
22148 V = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V,
22149 getV4X86ShuffleImm8ForMask(DMask, DAG));
22150 DCI.AddToWorklist(V.getNode());
22151 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);
22154 // Look for shuffle patterns which can be implemented as a single unpack.
22155 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22156 // only works when we have a PSHUFD followed by two half-shuffles.
22157 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22158 (V.getOpcode() == X86ISD::PSHUFLW ||
22159 V.getOpcode() == X86ISD::PSHUFHW) &&
22160 V.getOpcode() != N.getOpcode() &&
22162 SDValue D = V.getOperand(0);
22163 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22164 D = D.getOperand(0);
22165 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22166 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22167 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22168 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22169 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22171 for (int i = 0; i < 4; ++i) {
22172 WordMask[i + NOffset] = Mask[i] + NOffset;
22173 WordMask[i + VOffset] = VMask[i] + VOffset;
22175 // Map the word mask through the DWord mask.
22177 for (int i = 0; i < 8; ++i)
22178 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22179 const int UnpackLoMask[] = {0, 0, 1, 1, 2, 2, 3, 3};
22180 const int UnpackHiMask[] = {4, 4, 5, 5, 6, 6, 7, 7};
22181 if (std::equal(std::begin(MappedMask), std::end(MappedMask),
22182 std::begin(UnpackLoMask)) ||
22183 std::equal(std::begin(MappedMask), std::end(MappedMask),
22184 std::begin(UnpackHiMask))) {
22185 // We can replace all three shuffles with an unpack.
22186 V = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, D.getOperand(0));
22187 DCI.AddToWorklist(V.getNode());
22188 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22190 DL, MVT::v8i16, V, V);
22197 case X86ISD::PSHUFD:
22198 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22207 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22209 /// We combine this directly on the abstract vector shuffle nodes so it is
22210 /// easier to generically match. We also insert dummy vector shuffle nodes for
22211 /// the operands which explicitly discard the lanes which are unused by this
22212 /// operation to try to flow through the rest of the combiner the fact that
22213 /// they're unused.
22214 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22216 EVT VT = N->getValueType(0);
22218 // We only handle target-independent shuffles.
22219 // FIXME: It would be easy and harmless to use the target shuffle mask
22220 // extraction tool to support more.
22221 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22224 auto *SVN = cast<ShuffleVectorSDNode>(N);
22225 ArrayRef<int> Mask = SVN->getMask();
22226 SDValue V1 = N->getOperand(0);
22227 SDValue V2 = N->getOperand(1);
22229 // We require the first shuffle operand to be the SUB node, and the second to
22230 // be the ADD node.
22231 // FIXME: We should support the commuted patterns.
22232 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22235 // If there are other uses of these operations we can't fold them.
22236 if (!V1->hasOneUse() || !V2->hasOneUse())
22239 // Ensure that both operations have the same operands. Note that we can
22240 // commute the FADD operands.
22241 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22242 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22243 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22246 // We're looking for blends between FADD and FSUB nodes. We insist on these
22247 // nodes being lined up in a specific expected pattern.
22248 if (!(isShuffleEquivalent(Mask, 0, 3) ||
22249 isShuffleEquivalent(Mask, 0, 5, 2, 7) ||
22250 isShuffleEquivalent(Mask, 0, 9, 2, 11, 4, 13, 6, 15)))
22253 // Only specific types are legal at this point, assert so we notice if and
22254 // when these change.
22255 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22256 VT == MVT::v4f64) &&
22257 "Unknown vector type encountered!");
22259 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22262 /// PerformShuffleCombine - Performs several different shuffle combines.
22263 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22264 TargetLowering::DAGCombinerInfo &DCI,
22265 const X86Subtarget *Subtarget) {
22267 SDValue N0 = N->getOperand(0);
22268 SDValue N1 = N->getOperand(1);
22269 EVT VT = N->getValueType(0);
22271 // Don't create instructions with illegal types after legalize types has run.
22272 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22273 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22276 // If we have legalized the vector types, look for blends of FADD and FSUB
22277 // nodes that we can fuse into an ADDSUB node.
22278 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22279 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22282 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22283 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22284 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22285 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22287 // During Type Legalization, when promoting illegal vector types,
22288 // the backend might introduce new shuffle dag nodes and bitcasts.
22290 // This code performs the following transformation:
22291 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22292 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22294 // We do this only if both the bitcast and the BINOP dag nodes have
22295 // one use. Also, perform this transformation only if the new binary
22296 // operation is legal. This is to avoid introducing dag nodes that
22297 // potentially need to be further expanded (or custom lowered) into a
22298 // less optimal sequence of dag nodes.
22299 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22300 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22301 N0.getOpcode() == ISD::BITCAST) {
22302 SDValue BC0 = N0.getOperand(0);
22303 EVT SVT = BC0.getValueType();
22304 unsigned Opcode = BC0.getOpcode();
22305 unsigned NumElts = VT.getVectorNumElements();
22307 if (BC0.hasOneUse() && SVT.isVector() &&
22308 SVT.getVectorNumElements() * 2 == NumElts &&
22309 TLI.isOperationLegal(Opcode, VT)) {
22310 bool CanFold = false;
22322 unsigned SVTNumElts = SVT.getVectorNumElements();
22323 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22324 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22325 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22326 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22327 CanFold = SVOp->getMaskElt(i) < 0;
22330 SDValue BC00 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(0));
22331 SDValue BC01 = DAG.getNode(ISD::BITCAST, dl, VT, BC0.getOperand(1));
22332 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
22333 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
22338 // Only handle 128 wide vector from here on.
22339 if (!VT.is128BitVector())
22342 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
22343 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
22344 // consecutive, non-overlapping, and in the right order.
22345 SmallVector<SDValue, 16> Elts;
22346 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
22347 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
22349 SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true);
22353 if (isTargetShuffle(N->getOpcode())) {
22355 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
22356 if (Shuffle.getNode())
22359 // Try recursively combining arbitrary sequences of x86 shuffle
22360 // instructions into higher-order shuffles. We do this after combining
22361 // specific PSHUF instruction sequences into their minimal form so that we
22362 // can evaluate how many specialized shuffle instructions are involved in
22363 // a particular chain.
22364 SmallVector<int, 1> NonceMask; // Just a placeholder.
22365 NonceMask.push_back(0);
22366 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
22367 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
22369 return SDValue(); // This routine will use CombineTo to replace N.
22375 /// PerformTruncateCombine - Converts truncate operation to
22376 /// a sequence of vector shuffle operations.
22377 /// It is possible when we truncate 256-bit vector to 128-bit vector
22378 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
22379 TargetLowering::DAGCombinerInfo &DCI,
22380 const X86Subtarget *Subtarget) {
22384 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
22385 /// specific shuffle of a load can be folded into a single element load.
22386 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
22387 /// shuffles have been custom lowered so we need to handle those here.
22388 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
22389 TargetLowering::DAGCombinerInfo &DCI) {
22390 if (DCI.isBeforeLegalizeOps())
22393 SDValue InVec = N->getOperand(0);
22394 SDValue EltNo = N->getOperand(1);
22396 if (!isa<ConstantSDNode>(EltNo))
22399 EVT OriginalVT = InVec.getValueType();
22401 if (InVec.getOpcode() == ISD::BITCAST) {
22402 // Don't duplicate a load with other uses.
22403 if (!InVec.hasOneUse())
22405 EVT BCVT = InVec.getOperand(0).getValueType();
22406 if (BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
22408 InVec = InVec.getOperand(0);
22411 EVT CurrentVT = InVec.getValueType();
22413 if (!isTargetShuffle(InVec.getOpcode()))
22416 // Don't duplicate a load with other uses.
22417 if (!InVec.hasOneUse())
22420 SmallVector<int, 16> ShuffleMask;
22422 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
22423 ShuffleMask, UnaryShuffle))
22426 // Select the input vector, guarding against out of range extract vector.
22427 unsigned NumElems = CurrentVT.getVectorNumElements();
22428 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
22429 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
22430 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
22431 : InVec.getOperand(1);
22433 // If inputs to shuffle are the same for both ops, then allow 2 uses
22434 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
22436 if (LdNode.getOpcode() == ISD::BITCAST) {
22437 // Don't duplicate a load with other uses.
22438 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
22441 AllowedUses = 1; // only allow 1 load use if we have a bitcast
22442 LdNode = LdNode.getOperand(0);
22445 if (!ISD::isNormalLoad(LdNode.getNode()))
22448 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
22450 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
22453 EVT EltVT = N->getValueType(0);
22454 // If there's a bitcast before the shuffle, check if the load type and
22455 // alignment is valid.
22456 unsigned Align = LN0->getAlignment();
22457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22458 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
22459 EltVT.getTypeForEVT(*DAG.getContext()));
22461 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
22464 // All checks match so transform back to vector_shuffle so that DAG combiner
22465 // can finish the job
22468 // Create shuffle node taking into account the case that its a unary shuffle
22469 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
22470 : InVec.getOperand(1);
22471 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
22472 InVec.getOperand(0), Shuffle,
22474 Shuffle = DAG.getNode(ISD::BITCAST, dl, OriginalVT, Shuffle);
22475 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
22479 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
22480 /// generation and convert it from being a bunch of shuffles and extracts
22481 /// into a somewhat faster sequence. For i686, the best sequence is apparently
22482 /// storing the value and loading scalars back, while for x64 we should
22483 /// use 64-bit extracts and shifts.
22484 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
22485 TargetLowering::DAGCombinerInfo &DCI) {
22486 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
22487 if (NewOp.getNode())
22490 SDValue InputVector = N->getOperand(0);
22492 // Detect whether we are trying to convert from mmx to i32 and the bitcast
22493 // from mmx to v2i32 has a single usage.
22494 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
22495 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
22496 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
22497 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
22498 N->getValueType(0),
22499 InputVector.getNode()->getOperand(0));
22501 // Only operate on vectors of 4 elements, where the alternative shuffling
22502 // gets to be more expensive.
22503 if (InputVector.getValueType() != MVT::v4i32)
22506 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
22507 // single use which is a sign-extend or zero-extend, and all elements are
22509 SmallVector<SDNode *, 4> Uses;
22510 unsigned ExtractedElements = 0;
22511 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
22512 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
22513 if (UI.getUse().getResNo() != InputVector.getResNo())
22516 SDNode *Extract = *UI;
22517 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
22520 if (Extract->getValueType(0) != MVT::i32)
22522 if (!Extract->hasOneUse())
22524 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
22525 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
22527 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
22530 // Record which element was extracted.
22531 ExtractedElements |=
22532 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
22534 Uses.push_back(Extract);
22537 // If not all the elements were used, this may not be worthwhile.
22538 if (ExtractedElements != 15)
22541 // Ok, we've now decided to do the transformation.
22542 // If 64-bit shifts are legal, use the extract-shift sequence,
22543 // otherwise bounce the vector off the cache.
22544 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22546 SDLoc dl(InputVector);
22548 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
22549 SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);
22550 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
22551 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22552 DAG.getConstant(0, VecIdxTy));
22553 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
22554 DAG.getConstant(1, VecIdxTy));
22556 SDValue ShAmt = DAG.getConstant(32,
22557 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
22558 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
22559 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22560 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
22561 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
22562 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
22563 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
22565 // Store the value to a temporary stack slot.
22566 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
22567 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
22568 MachinePointerInfo(), false, false, 0);
22570 EVT ElementType = InputVector.getValueType().getVectorElementType();
22571 unsigned EltSize = ElementType.getSizeInBits() / 8;
22573 // Replace each use (extract) with a load of the appropriate element.
22574 for (unsigned i = 0; i < 4; ++i) {
22575 uint64_t Offset = EltSize * i;
22576 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
22578 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
22579 StackPtr, OffsetVal);
22581 // Load the scalar.
22582 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
22583 ScalarAddr, MachinePointerInfo(),
22584 false, false, false, 0);
22589 // Replace the extracts
22590 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
22591 UE = Uses.end(); UI != UE; ++UI) {
22592 SDNode *Extract = *UI;
22594 SDValue Idx = Extract->getOperand(1);
22595 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
22596 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
22599 // The replacement was made in place; don't return anything.
22603 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
22604 static std::pair<unsigned, bool>
22605 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
22606 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
22607 if (!VT.isVector())
22608 return std::make_pair(0, false);
22610 bool NeedSplit = false;
22611 switch (VT.getSimpleVT().SimpleTy) {
22612 default: return std::make_pair(0, false);
22616 if (!Subtarget->hasAVX2())
22618 if (!Subtarget->hasAVX())
22619 return std::make_pair(0, false);
22624 if (!Subtarget->hasSSE2())
22625 return std::make_pair(0, false);
22628 // SSE2 has only a small subset of the operations.
22629 bool hasUnsigned = Subtarget->hasSSE41() ||
22630 (Subtarget->hasSSE2() && VT == MVT::v16i8);
22631 bool hasSigned = Subtarget->hasSSE41() ||
22632 (Subtarget->hasSSE2() && VT == MVT::v8i16);
22634 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22637 // Check for x CC y ? x : y.
22638 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22639 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22644 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22647 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22650 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22653 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22655 // Check for x CC y ? y : x -- a min/max with reversed arms.
22656 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22657 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22662 Opc = hasUnsigned ? X86ISD::UMAX : 0; break;
22665 Opc = hasUnsigned ? X86ISD::UMIN : 0; break;
22668 Opc = hasSigned ? X86ISD::SMAX : 0; break;
22671 Opc = hasSigned ? X86ISD::SMIN : 0; break;
22675 return std::make_pair(Opc, NeedSplit);
22679 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
22680 const X86Subtarget *Subtarget) {
22682 SDValue Cond = N->getOperand(0);
22683 SDValue LHS = N->getOperand(1);
22684 SDValue RHS = N->getOperand(2);
22686 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
22687 SDValue CondSrc = Cond->getOperand(0);
22688 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
22689 Cond = CondSrc->getOperand(0);
22692 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
22695 // A vselect where all conditions and data are constants can be optimized into
22696 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
22697 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
22698 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
22701 unsigned MaskValue = 0;
22702 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
22705 MVT VT = N->getSimpleValueType(0);
22706 unsigned NumElems = VT.getVectorNumElements();
22707 SmallVector<int, 8> ShuffleMask(NumElems, -1);
22708 for (unsigned i = 0; i < NumElems; ++i) {
22709 // Be sure we emit undef where we can.
22710 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
22711 ShuffleMask[i] = -1;
22713 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
22716 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22717 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
22719 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
22722 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
22724 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
22725 TargetLowering::DAGCombinerInfo &DCI,
22726 const X86Subtarget *Subtarget) {
22728 SDValue Cond = N->getOperand(0);
22729 // Get the LHS/RHS of the select.
22730 SDValue LHS = N->getOperand(1);
22731 SDValue RHS = N->getOperand(2);
22732 EVT VT = LHS.getValueType();
22733 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22735 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22736 // instructions match the semantics of the common C idiom x<y?x:y but not
22737 // x<=y?x:y, because of how they handle negative zero (which can be
22738 // ignored in unsafe-math mode).
22739 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22740 VT != MVT::f80 && TLI.isTypeLegal(VT) &&
22741 (Subtarget->hasSSE2() ||
22742 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22743 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22745 unsigned Opcode = 0;
22746 // Check for x CC y ? x : y.
22747 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22748 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22752 // Converting this to a min would handle NaNs incorrectly, and swapping
22753 // the operands would cause it to handle comparisons between positive
22754 // and negative zero incorrectly.
22755 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22756 if (!DAG.getTarget().Options.UnsafeFPMath &&
22757 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22759 std::swap(LHS, RHS);
22761 Opcode = X86ISD::FMIN;
22764 // Converting this to a min would handle comparisons between positive
22765 // and negative zero incorrectly.
22766 if (!DAG.getTarget().Options.UnsafeFPMath &&
22767 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22769 Opcode = X86ISD::FMIN;
22772 // Converting this to a min would handle both negative zeros and NaNs
22773 // incorrectly, but we can swap the operands to fix both.
22774 std::swap(LHS, RHS);
22778 Opcode = X86ISD::FMIN;
22782 // Converting this to a max would handle comparisons between positive
22783 // and negative zero incorrectly.
22784 if (!DAG.getTarget().Options.UnsafeFPMath &&
22785 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22787 Opcode = X86ISD::FMAX;
22790 // Converting this to a max would handle NaNs incorrectly, and swapping
22791 // the operands would cause it to handle comparisons between positive
22792 // and negative zero incorrectly.
22793 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22794 if (!DAG.getTarget().Options.UnsafeFPMath &&
22795 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22797 std::swap(LHS, RHS);
22799 Opcode = X86ISD::FMAX;
22802 // Converting this to a max would handle both negative zeros and NaNs
22803 // incorrectly, but we can swap the operands to fix both.
22804 std::swap(LHS, RHS);
22808 Opcode = X86ISD::FMAX;
22811 // Check for x CC y ? y : x -- a min/max with reversed arms.
22812 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22813 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22817 // Converting this to a min would handle comparisons between positive
22818 // and negative zero incorrectly, and swapping the operands would
22819 // cause it to handle NaNs incorrectly.
22820 if (!DAG.getTarget().Options.UnsafeFPMath &&
22821 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22822 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22824 std::swap(LHS, RHS);
22826 Opcode = X86ISD::FMIN;
22829 // Converting this to a min would handle NaNs incorrectly.
22830 if (!DAG.getTarget().Options.UnsafeFPMath &&
22831 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22833 Opcode = X86ISD::FMIN;
22836 // Converting this to a min would handle both negative zeros and NaNs
22837 // incorrectly, but we can swap the operands to fix both.
22838 std::swap(LHS, RHS);
22842 Opcode = X86ISD::FMIN;
22846 // Converting this to a max would handle NaNs incorrectly.
22847 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22849 Opcode = X86ISD::FMAX;
22852 // Converting this to a max would handle comparisons between positive
22853 // and negative zero incorrectly, and swapping the operands would
22854 // cause it to handle NaNs incorrectly.
22855 if (!DAG.getTarget().Options.UnsafeFPMath &&
22856 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22857 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22859 std::swap(LHS, RHS);
22861 Opcode = X86ISD::FMAX;
22864 // Converting this to a max would handle both negative zeros and NaNs
22865 // incorrectly, but we can swap the operands to fix both.
22866 std::swap(LHS, RHS);
22870 Opcode = X86ISD::FMAX;
22876 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22879 EVT CondVT = Cond.getValueType();
22880 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22881 CondVT.getVectorElementType() == MVT::i1) {
22882 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22883 // lowering on KNL. In this case we convert it to
22884 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22885 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22886 // Since SKX these selects have a proper lowering.
22887 EVT OpVT = LHS.getValueType();
22888 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22889 (OpVT.getVectorElementType() == MVT::i8 ||
22890 OpVT.getVectorElementType() == MVT::i16) &&
22891 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22892 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22893 DCI.AddToWorklist(Cond.getNode());
22894 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22897 // If this is a select between two integer constants, try to do some
22899 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22900 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22901 // Don't do this for crazy integer types.
22902 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22903 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22904 // so that TrueC (the true value) is larger than FalseC.
22905 bool NeedsCondInvert = false;
22907 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22908 // Efficiently invertible.
22909 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22910 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22911 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22912 NeedsCondInvert = true;
22913 std::swap(TrueC, FalseC);
22916 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22917 if (FalseC->getAPIntValue() == 0 &&
22918 TrueC->getAPIntValue().isPowerOf2()) {
22919 if (NeedsCondInvert) // Invert the condition if needed.
22920 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22921 DAG.getConstant(1, Cond.getValueType()));
22923 // Zero extend the condition if needed.
22924 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22926 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22927 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22928 DAG.getConstant(ShAmt, MVT::i8));
22931 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22932 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22933 if (NeedsCondInvert) // Invert the condition if needed.
22934 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22935 DAG.getConstant(1, Cond.getValueType()));
22937 // Zero extend the condition if needed.
22938 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22939 FalseC->getValueType(0), Cond);
22940 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22941 SDValue(FalseC, 0));
22944 // Optimize cases that will turn into an LEA instruction. This requires
22945 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22946 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22947 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22948 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22950 bool isFastMultiplier = false;
22952 switch ((unsigned char)Diff) {
22954 case 1: // result = add base, cond
22955 case 2: // result = lea base( , cond*2)
22956 case 3: // result = lea base(cond, cond*2)
22957 case 4: // result = lea base( , cond*4)
22958 case 5: // result = lea base(cond, cond*4)
22959 case 8: // result = lea base( , cond*8)
22960 case 9: // result = lea base(cond, cond*8)
22961 isFastMultiplier = true;
22966 if (isFastMultiplier) {
22967 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22968 if (NeedsCondInvert) // Invert the condition if needed.
22969 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22970 DAG.getConstant(1, Cond.getValueType()));
22972 // Zero extend the condition if needed.
22973 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22975 // Scale the condition by the difference.
22977 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22978 DAG.getConstant(Diff, Cond.getValueType()));
22980 // Add the base if non-zero.
22981 if (FalseC->getAPIntValue() != 0)
22982 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22983 SDValue(FalseC, 0));
22990 // Canonicalize max and min:
22991 // (x > y) ? x : y -> (x >= y) ? x : y
22992 // (x < y) ? x : y -> (x <= y) ? x : y
22993 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22994 // the need for an extra compare
22995 // against zero. e.g.
22996 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22998 // testl %edi, %edi
23000 // cmovgl %edi, %eax
23004 // cmovsl %eax, %edi
23005 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23006 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23007 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23008 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23013 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23014 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23015 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23016 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23021 // Early exit check
23022 if (!TLI.isTypeLegal(VT))
23025 // Match VSELECTs into subs with unsigned saturation.
23026 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23027 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23028 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23029 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23030 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23032 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23033 // left side invert the predicate to simplify logic below.
23035 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23037 CC = ISD::getSetCCInverse(CC, true);
23038 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23042 if (Other.getNode() && Other->getNumOperands() == 2 &&
23043 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23044 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23045 SDValue CondRHS = Cond->getOperand(1);
23047 // Look for a general sub with unsigned saturation first.
23048 // x >= y ? x-y : 0 --> subus x, y
23049 // x > y ? x-y : 0 --> subus x, y
23050 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23051 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23052 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23054 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23055 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23056 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23057 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23058 // If the RHS is a constant we have to reverse the const
23059 // canonicalization.
23060 // x > C-1 ? x+-C : 0 --> subus x, C
23061 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23062 CondRHSConst->getAPIntValue() ==
23063 (-OpRHSConst->getAPIntValue() - 1))
23064 return DAG.getNode(
23065 X86ISD::SUBUS, DL, VT, OpLHS,
23066 DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));
23068 // Another special case: If C was a sign bit, the sub has been
23069 // canonicalized into a xor.
23070 // FIXME: Would it be better to use computeKnownBits to determine
23071 // whether it's safe to decanonicalize the xor?
23072 // x s< 0 ? x^C : 0 --> subus x, C
23073 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23074 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23075 OpRHSConst->getAPIntValue().isSignBit())
23076 // Note that we have to rebuild the RHS constant here to ensure we
23077 // don't rely on particular values of undef lanes.
23078 return DAG.getNode(
23079 X86ISD::SUBUS, DL, VT, OpLHS,
23080 DAG.getConstant(OpRHSConst->getAPIntValue(), VT));
23085 // Try to match a min/max vector operation.
23086 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
23087 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
23088 unsigned Opc = ret.first;
23089 bool NeedSplit = ret.second;
23091 if (Opc && NeedSplit) {
23092 unsigned NumElems = VT.getVectorNumElements();
23093 // Extract the LHS vectors
23094 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
23095 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
23097 // Extract the RHS vectors
23098 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
23099 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
23101 // Create min/max for each subvector
23102 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
23103 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
23105 // Merge the result
23106 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
23108 return DAG.getNode(Opc, DL, VT, LHS, RHS);
23111 // Simplify vector selection if condition value type matches vselect
23113 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23114 assert(Cond.getValueType().isVector() &&
23115 "vector select expects a vector selector!");
23117 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23118 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23120 // Try invert the condition if true value is not all 1s and false value
23122 if (!TValIsAllOnes && !FValIsAllZeros &&
23123 // Check if the selector will be produced by CMPP*/PCMP*
23124 Cond.getOpcode() == ISD::SETCC &&
23125 // Check if SETCC has already been promoted
23126 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
23127 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23128 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23130 if (TValIsAllZeros || FValIsAllOnes) {
23131 SDValue CC = Cond.getOperand(2);
23132 ISD::CondCode NewCC =
23133 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23134 Cond.getOperand(0).getValueType().isInteger());
23135 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23136 std::swap(LHS, RHS);
23137 TValIsAllOnes = FValIsAllOnes;
23138 FValIsAllZeros = TValIsAllZeros;
23142 if (TValIsAllOnes || FValIsAllZeros) {
23145 if (TValIsAllOnes && FValIsAllZeros)
23147 else if (TValIsAllOnes)
23148 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
23149 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
23150 else if (FValIsAllZeros)
23151 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23152 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
23154 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
23158 // If we know that this node is legal then we know that it is going to be
23159 // matched by one of the SSE/AVX BLEND instructions. These instructions only
23160 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
23161 // to simplify previous instructions.
23162 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23163 !DCI.isBeforeLegalize() &&
23164 // We explicitly check against v8i16 and v16i16 because, although
23165 // they're marked as Custom, they might only be legal when Cond is a
23166 // build_vector of constants. This will be taken care in a later
23168 (TLI.isOperationLegalOrCustom(ISD::VSELECT, VT) && VT != MVT::v16i16 &&
23169 VT != MVT::v8i16) &&
23170 // Don't optimize vector of constants. Those are handled by
23171 // the generic code and all the bits must be properly set for
23172 // the generic optimizer.
23173 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23174 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23176 // Don't optimize vector selects that map to mask-registers.
23180 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23181 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23183 APInt KnownZero, KnownOne;
23184 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23185 DCI.isBeforeLegalizeOps());
23186 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23187 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23189 // If we changed the computation somewhere in the DAG, this change
23190 // will affect all users of Cond.
23191 // Make sure it is fine and update all the nodes so that we do not
23192 // use the generic VSELECT anymore. Otherwise, we may perform
23193 // wrong optimizations as we messed up with the actual expectation
23194 // for the vector boolean values.
23195 if (Cond != TLO.Old) {
23196 // Check all uses of that condition operand to check whether it will be
23197 // consumed by non-BLEND instructions, which may depend on all bits are
23199 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23201 if (I->getOpcode() != ISD::VSELECT)
23202 // TODO: Add other opcodes eventually lowered into BLEND.
23205 // Update all the users of the condition, before committing the change,
23206 // so that the VSELECT optimizations that expect the correct vector
23207 // boolean value will not be triggered.
23208 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23210 DAG.ReplaceAllUsesOfValueWith(
23212 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23213 Cond, I->getOperand(1), I->getOperand(2)));
23214 DCI.CommitTargetLoweringOpt(TLO);
23217 // At this point, only Cond is changed. Change the condition
23218 // just for N to keep the opportunity to optimize all other
23219 // users their own way.
23220 DAG.ReplaceAllUsesOfValueWith(
23222 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23223 TLO.New, N->getOperand(1), N->getOperand(2)));
23228 // We should generate an X86ISD::BLENDI from a vselect if its argument
23229 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23230 // constants. This specific pattern gets generated when we split a
23231 // selector for a 512 bit vector in a machine without AVX512 (but with
23232 // 256-bit vectors), during legalization:
23234 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23236 // Iff we find this pattern and the build_vectors are built from
23237 // constants, we translate the vselect into a shuffle_vector that we
23238 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23239 if ((N->getOpcode() == ISD::VSELECT ||
23240 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23241 !DCI.isBeforeLegalize()) {
23242 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23243 if (Shuffle.getNode())
23250 // Check whether a boolean test is testing a boolean value generated by
23251 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23254 // Simplify the following patterns:
23255 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23256 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23257 // to (Op EFLAGS Cond)
23259 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23260 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23261 // to (Op EFLAGS !Cond)
23263 // where Op could be BRCOND or CMOV.
23265 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23266 // Quit if not CMP and SUB with its value result used.
23267 if (Cmp.getOpcode() != X86ISD::CMP &&
23268 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23271 // Quit if not used as a boolean value.
23272 if (CC != X86::COND_E && CC != X86::COND_NE)
23275 // Check CMP operands. One of them should be 0 or 1 and the other should be
23276 // an SetCC or extended from it.
23277 SDValue Op1 = Cmp.getOperand(0);
23278 SDValue Op2 = Cmp.getOperand(1);
23281 const ConstantSDNode* C = nullptr;
23282 bool needOppositeCond = (CC == X86::COND_E);
23283 bool checkAgainstTrue = false; // Is it a comparison against 1?
23285 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23287 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23289 else // Quit if all operands are not constants.
23292 if (C->getZExtValue() == 1) {
23293 needOppositeCond = !needOppositeCond;
23294 checkAgainstTrue = true;
23295 } else if (C->getZExtValue() != 0)
23296 // Quit if the constant is neither 0 or 1.
23299 bool truncatedToBoolWithAnd = false;
23300 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23301 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23302 SetCC.getOpcode() == ISD::TRUNCATE ||
23303 SetCC.getOpcode() == ISD::AND) {
23304 if (SetCC.getOpcode() == ISD::AND) {
23306 ConstantSDNode *CS;
23307 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23308 CS->getZExtValue() == 1)
23310 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23311 CS->getZExtValue() == 1)
23315 SetCC = SetCC.getOperand(OpIdx);
23316 truncatedToBoolWithAnd = true;
23318 SetCC = SetCC.getOperand(0);
23321 switch (SetCC.getOpcode()) {
23322 case X86ISD::SETCC_CARRY:
23323 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23324 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23325 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23326 // truncated to i1 using 'and'.
23327 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23329 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23330 "Invalid use of SETCC_CARRY!");
23332 case X86ISD::SETCC:
23333 // Set the condition code or opposite one if necessary.
23334 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23335 if (needOppositeCond)
23336 CC = X86::GetOppositeBranchCondition(CC);
23337 return SetCC.getOperand(1);
23338 case X86ISD::CMOV: {
23339 // Check whether false/true value has canonical one, i.e. 0 or 1.
23340 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23341 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23342 // Quit if true value is not a constant.
23345 // Quit if false value is not a constant.
23347 SDValue Op = SetCC.getOperand(0);
23348 // Skip 'zext' or 'trunc' node.
23349 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23350 Op.getOpcode() == ISD::TRUNCATE)
23351 Op = Op.getOperand(0);
23352 // A special case for rdrand/rdseed, where 0 is set if false cond is
23354 if ((Op.getOpcode() != X86ISD::RDRAND &&
23355 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23358 // Quit if false value is not the constant 0 or 1.
23359 bool FValIsFalse = true;
23360 if (FVal && FVal->getZExtValue() != 0) {
23361 if (FVal->getZExtValue() != 1)
23363 // If FVal is 1, opposite cond is needed.
23364 needOppositeCond = !needOppositeCond;
23365 FValIsFalse = false;
23367 // Quit if TVal is not the constant opposite of FVal.
23368 if (FValIsFalse && TVal->getZExtValue() != 1)
23370 if (!FValIsFalse && TVal->getZExtValue() != 0)
23372 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23373 if (needOppositeCond)
23374 CC = X86::GetOppositeBranchCondition(CC);
23375 return SetCC.getOperand(3);
23382 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
23383 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
23384 TargetLowering::DAGCombinerInfo &DCI,
23385 const X86Subtarget *Subtarget) {
23388 // If the flag operand isn't dead, don't touch this CMOV.
23389 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
23392 SDValue FalseOp = N->getOperand(0);
23393 SDValue TrueOp = N->getOperand(1);
23394 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
23395 SDValue Cond = N->getOperand(3);
23397 if (CC == X86::COND_E || CC == X86::COND_NE) {
23398 switch (Cond.getOpcode()) {
23402 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
23403 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
23404 return (CC == X86::COND_E) ? FalseOp : TrueOp;
23410 Flags = checkBoolTestSetCCCombine(Cond, CC);
23411 if (Flags.getNode() &&
23412 // Extra check as FCMOV only supports a subset of X86 cond.
23413 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
23414 SDValue Ops[] = { FalseOp, TrueOp,
23415 DAG.getConstant(CC, MVT::i8), Flags };
23416 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
23419 // If this is a select between two integer constants, try to do some
23420 // optimizations. Note that the operands are ordered the opposite of SELECT
23422 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
23423 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
23424 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
23425 // larger than FalseC (the false value).
23426 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
23427 CC = X86::GetOppositeBranchCondition(CC);
23428 std::swap(TrueC, FalseC);
23429 std::swap(TrueOp, FalseOp);
23432 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
23433 // This is efficient for any integer data type (including i8/i16) and
23435 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
23436 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23437 DAG.getConstant(CC, MVT::i8), Cond);
23439 // Zero extend the condition if needed.
23440 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
23442 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23443 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
23444 DAG.getConstant(ShAmt, MVT::i8));
23445 if (N->getNumValues() == 2) // Dead flag value?
23446 return DCI.CombineTo(N, Cond, SDValue());
23450 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
23451 // for any integer data type, including i8/i16.
23452 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23453 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23454 DAG.getConstant(CC, MVT::i8), Cond);
23456 // Zero extend the condition if needed.
23457 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23458 FalseC->getValueType(0), Cond);
23459 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23460 SDValue(FalseC, 0));
23462 if (N->getNumValues() == 2) // Dead flag value?
23463 return DCI.CombineTo(N, Cond, SDValue());
23467 // Optimize cases that will turn into an LEA instruction. This requires
23468 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23469 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23470 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23471 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23473 bool isFastMultiplier = false;
23475 switch ((unsigned char)Diff) {
23477 case 1: // result = add base, cond
23478 case 2: // result = lea base( , cond*2)
23479 case 3: // result = lea base(cond, cond*2)
23480 case 4: // result = lea base( , cond*4)
23481 case 5: // result = lea base(cond, cond*4)
23482 case 8: // result = lea base( , cond*8)
23483 case 9: // result = lea base(cond, cond*8)
23484 isFastMultiplier = true;
23489 if (isFastMultiplier) {
23490 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23491 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
23492 DAG.getConstant(CC, MVT::i8), Cond);
23493 // Zero extend the condition if needed.
23494 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23496 // Scale the condition by the difference.
23498 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23499 DAG.getConstant(Diff, Cond.getValueType()));
23501 // Add the base if non-zero.
23502 if (FalseC->getAPIntValue() != 0)
23503 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23504 SDValue(FalseC, 0));
23505 if (N->getNumValues() == 2) // Dead flag value?
23506 return DCI.CombineTo(N, Cond, SDValue());
23513 // Handle these cases:
23514 // (select (x != c), e, c) -> select (x != c), e, x),
23515 // (select (x == c), c, e) -> select (x == c), x, e)
23516 // where the c is an integer constant, and the "select" is the combination
23517 // of CMOV and CMP.
23519 // The rationale for this change is that the conditional-move from a constant
23520 // needs two instructions, however, conditional-move from a register needs
23521 // only one instruction.
23523 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
23524 // some instruction-combining opportunities. This opt needs to be
23525 // postponed as late as possible.
23527 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
23528 // the DCI.xxxx conditions are provided to postpone the optimization as
23529 // late as possible.
23531 ConstantSDNode *CmpAgainst = nullptr;
23532 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
23533 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
23534 !isa<ConstantSDNode>(Cond.getOperand(0))) {
23536 if (CC == X86::COND_NE &&
23537 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
23538 CC = X86::GetOppositeBranchCondition(CC);
23539 std::swap(TrueOp, FalseOp);
23542 if (CC == X86::COND_E &&
23543 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
23544 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
23545 DAG.getConstant(CC, MVT::i8), Cond };
23546 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
23554 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
23555 const X86Subtarget *Subtarget) {
23556 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
23558 default: return SDValue();
23559 // SSE/AVX/AVX2 blend intrinsics.
23560 case Intrinsic::x86_avx2_pblendvb:
23561 case Intrinsic::x86_avx2_pblendw:
23562 case Intrinsic::x86_avx2_pblendd_128:
23563 case Intrinsic::x86_avx2_pblendd_256:
23564 // Don't try to simplify this intrinsic if we don't have AVX2.
23565 if (!Subtarget->hasAVX2())
23568 case Intrinsic::x86_avx_blend_pd_256:
23569 case Intrinsic::x86_avx_blend_ps_256:
23570 case Intrinsic::x86_avx_blendv_pd_256:
23571 case Intrinsic::x86_avx_blendv_ps_256:
23572 // Don't try to simplify this intrinsic if we don't have AVX.
23573 if (!Subtarget->hasAVX())
23576 case Intrinsic::x86_sse41_pblendw:
23577 case Intrinsic::x86_sse41_blendpd:
23578 case Intrinsic::x86_sse41_blendps:
23579 case Intrinsic::x86_sse41_blendvps:
23580 case Intrinsic::x86_sse41_blendvpd:
23581 case Intrinsic::x86_sse41_pblendvb: {
23582 SDValue Op0 = N->getOperand(1);
23583 SDValue Op1 = N->getOperand(2);
23584 SDValue Mask = N->getOperand(3);
23586 // Don't try to simplify this intrinsic if we don't have SSE4.1.
23587 if (!Subtarget->hasSSE41())
23590 // fold (blend A, A, Mask) -> A
23593 // fold (blend A, B, allZeros) -> A
23594 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
23596 // fold (blend A, B, allOnes) -> B
23597 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
23600 // Simplify the case where the mask is a constant i32 value.
23601 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
23602 if (C->isNullValue())
23604 if (C->isAllOnesValue())
23611 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
23612 case Intrinsic::x86_sse2_psrai_w:
23613 case Intrinsic::x86_sse2_psrai_d:
23614 case Intrinsic::x86_avx2_psrai_w:
23615 case Intrinsic::x86_avx2_psrai_d:
23616 case Intrinsic::x86_sse2_psra_w:
23617 case Intrinsic::x86_sse2_psra_d:
23618 case Intrinsic::x86_avx2_psra_w:
23619 case Intrinsic::x86_avx2_psra_d: {
23620 SDValue Op0 = N->getOperand(1);
23621 SDValue Op1 = N->getOperand(2);
23622 EVT VT = Op0.getValueType();
23623 assert(VT.isVector() && "Expected a vector type!");
23625 if (isa<BuildVectorSDNode>(Op1))
23626 Op1 = Op1.getOperand(0);
23628 if (!isa<ConstantSDNode>(Op1))
23631 EVT SVT = VT.getVectorElementType();
23632 unsigned SVTBits = SVT.getSizeInBits();
23634 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
23635 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
23636 uint64_t ShAmt = C.getZExtValue();
23638 // Don't try to convert this shift into a ISD::SRA if the shift
23639 // count is bigger than or equal to the element size.
23640 if (ShAmt >= SVTBits)
23643 // Trivial case: if the shift count is zero, then fold this
23644 // into the first operand.
23648 // Replace this packed shift intrinsic with a target independent
23650 SDValue Splat = DAG.getConstant(C, VT);
23651 return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);
23656 /// PerformMulCombine - Optimize a single multiply with constant into two
23657 /// in order to implement it with two cheaper instructions, e.g.
23658 /// LEA + SHL, LEA + LEA.
23659 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23660 TargetLowering::DAGCombinerInfo &DCI) {
23661 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23664 EVT VT = N->getValueType(0);
23665 if (VT != MVT::i64)
23668 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23671 uint64_t MulAmt = C->getZExtValue();
23672 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23675 uint64_t MulAmt1 = 0;
23676 uint64_t MulAmt2 = 0;
23677 if ((MulAmt % 9) == 0) {
23679 MulAmt2 = MulAmt / 9;
23680 } else if ((MulAmt % 5) == 0) {
23682 MulAmt2 = MulAmt / 5;
23683 } else if ((MulAmt % 3) == 0) {
23685 MulAmt2 = MulAmt / 3;
23688 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23691 if (isPowerOf2_64(MulAmt2) &&
23692 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23693 // If second multiplifer is pow2, issue it first. We want the multiply by
23694 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23696 std::swap(MulAmt1, MulAmt2);
23699 if (isPowerOf2_64(MulAmt1))
23700 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23701 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
23703 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23704 DAG.getConstant(MulAmt1, VT));
23706 if (isPowerOf2_64(MulAmt2))
23707 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23708 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
23710 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23711 DAG.getConstant(MulAmt2, VT));
23713 // Do not add new nodes to DAG combiner worklist.
23714 DCI.CombineTo(N, NewMul, false);
23719 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23720 SDValue N0 = N->getOperand(0);
23721 SDValue N1 = N->getOperand(1);
23722 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23723 EVT VT = N0.getValueType();
23725 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23726 // since the result of setcc_c is all zero's or all ones.
23727 if (VT.isInteger() && !VT.isVector() &&
23728 N1C && N0.getOpcode() == ISD::AND &&
23729 N0.getOperand(1).getOpcode() == ISD::Constant) {
23730 SDValue N00 = N0.getOperand(0);
23731 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23732 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23733 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23734 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23735 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23736 APInt ShAmt = N1C->getAPIntValue();
23737 Mask = Mask.shl(ShAmt);
23739 return DAG.getNode(ISD::AND, SDLoc(N), VT,
23740 N00, DAG.getConstant(Mask, VT));
23744 // Hardware support for vector shifts is sparse which makes us scalarize the
23745 // vector operations in many cases. Also, on sandybridge ADD is faster than
23747 // (shl V, 1) -> add V,V
23748 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23749 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23750 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23751 // We shift all of the values by one. In many cases we do not have
23752 // hardware support for this operation. This is better expressed as an ADD
23754 if (N1SplatC->getZExtValue() == 1)
23755 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23761 /// \brief Returns a vector of 0s if the node in input is a vector logical
23762 /// shift by a constant amount which is known to be bigger than or equal
23763 /// to the vector element size in bits.
23764 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23765 const X86Subtarget *Subtarget) {
23766 EVT VT = N->getValueType(0);
23768 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23769 (!Subtarget->hasInt256() ||
23770 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23773 SDValue Amt = N->getOperand(1);
23775 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23776 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23777 APInt ShiftAmt = AmtSplat->getAPIntValue();
23778 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23780 // SSE2/AVX2 logical shifts always return a vector of 0s
23781 // if the shift amount is bigger than or equal to
23782 // the element size. The constant shift amount will be
23783 // encoded as a 8-bit immediate.
23784 if (ShiftAmt.trunc(8).uge(MaxAmount))
23785 return getZeroVector(VT, Subtarget, DAG, DL);
23791 /// PerformShiftCombine - Combine shifts.
23792 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23793 TargetLowering::DAGCombinerInfo &DCI,
23794 const X86Subtarget *Subtarget) {
23795 if (N->getOpcode() == ISD::SHL) {
23796 SDValue V = PerformSHLCombine(N, DAG);
23797 if (V.getNode()) return V;
23800 if (N->getOpcode() != ISD::SRA) {
23801 // Try to fold this logical shift into a zero vector.
23802 SDValue V = performShiftToAllZeros(N, DAG, Subtarget);
23803 if (V.getNode()) return V;
23809 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23810 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23811 // and friends. Likewise for OR -> CMPNEQSS.
23812 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23813 TargetLowering::DAGCombinerInfo &DCI,
23814 const X86Subtarget *Subtarget) {
23817 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23818 // we're requiring SSE2 for both.
23819 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23820 SDValue N0 = N->getOperand(0);
23821 SDValue N1 = N->getOperand(1);
23822 SDValue CMP0 = N0->getOperand(1);
23823 SDValue CMP1 = N1->getOperand(1);
23826 // The SETCCs should both refer to the same CMP.
23827 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23830 SDValue CMP00 = CMP0->getOperand(0);
23831 SDValue CMP01 = CMP0->getOperand(1);
23832 EVT VT = CMP00.getValueType();
23834 if (VT == MVT::f32 || VT == MVT::f64) {
23835 bool ExpectingFlags = false;
23836 // Check for any users that want flags:
23837 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23838 !ExpectingFlags && UI != UE; ++UI)
23839 switch (UI->getOpcode()) {
23844 ExpectingFlags = true;
23846 case ISD::CopyToReg:
23847 case ISD::SIGN_EXTEND:
23848 case ISD::ZERO_EXTEND:
23849 case ISD::ANY_EXTEND:
23853 if (!ExpectingFlags) {
23854 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23855 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23857 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23858 X86::CondCode tmp = cc0;
23863 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23864 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23865 // FIXME: need symbolic constants for these magic numbers.
23866 // See X86ATTInstPrinter.cpp:printSSECC().
23867 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23868 if (Subtarget->hasAVX512()) {
23869 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23870 CMP01, DAG.getConstant(x86cc, MVT::i8));
23871 if (N->getValueType(0) != MVT::i1)
23872 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23876 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23877 CMP00.getValueType(), CMP00, CMP01,
23878 DAG.getConstant(x86cc, MVT::i8));
23880 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23881 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23883 if (is64BitFP && !Subtarget->is64Bit()) {
23884 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23885 // 64-bit integer, since that's not a legal type. Since
23886 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23887 // bits, but can do this little dance to extract the lowest 32 bits
23888 // and work with those going forward.
23889 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23891 SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,
23893 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23894 Vector32, DAG.getIntPtrConstant(0));
23898 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);
23899 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23900 DAG.getConstant(1, IntVT));
23901 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
23902 return OneBitOfTruth;
23910 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23911 /// so it can be folded inside ANDNP.
23912 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23913 EVT VT = N->getValueType(0);
23915 // Match direct AllOnes for 128 and 256-bit vectors
23916 if (ISD::isBuildVectorAllOnes(N))
23919 // Look through a bit convert.
23920 if (N->getOpcode() == ISD::BITCAST)
23921 N = N->getOperand(0).getNode();
23923 // Sometimes the operand may come from a insert_subvector building a 256-bit
23925 if (VT.is256BitVector() &&
23926 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23927 SDValue V1 = N->getOperand(0);
23928 SDValue V2 = N->getOperand(1);
23930 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23931 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23932 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23933 ISD::isBuildVectorAllOnes(V2.getNode()))
23940 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23941 // register. In most cases we actually compare or select YMM-sized registers
23942 // and mixing the two types creates horrible code. This method optimizes
23943 // some of the transition sequences.
23944 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23945 TargetLowering::DAGCombinerInfo &DCI,
23946 const X86Subtarget *Subtarget) {
23947 EVT VT = N->getValueType(0);
23948 if (!VT.is256BitVector())
23951 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23952 N->getOpcode() == ISD::ZERO_EXTEND ||
23953 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23955 SDValue Narrow = N->getOperand(0);
23956 EVT NarrowVT = Narrow->getValueType(0);
23957 if (!NarrowVT.is128BitVector())
23960 if (Narrow->getOpcode() != ISD::XOR &&
23961 Narrow->getOpcode() != ISD::AND &&
23962 Narrow->getOpcode() != ISD::OR)
23965 SDValue N0 = Narrow->getOperand(0);
23966 SDValue N1 = Narrow->getOperand(1);
23969 // The Left side has to be a trunc.
23970 if (N0.getOpcode() != ISD::TRUNCATE)
23973 // The type of the truncated inputs.
23974 EVT WideVT = N0->getOperand(0)->getValueType(0);
23978 // The right side has to be a 'trunc' or a constant vector.
23979 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23980 ConstantSDNode *RHSConstSplat = nullptr;
23981 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23982 RHSConstSplat = RHSBV->getConstantSplatNode();
23983 if (!RHSTrunc && !RHSConstSplat)
23986 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23988 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23991 // Set N0 and N1 to hold the inputs to the new wide operation.
23992 N0 = N0->getOperand(0);
23993 if (RHSConstSplat) {
23994 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23995 SDValue(RHSConstSplat, 0));
23996 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23997 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23998 } else if (RHSTrunc) {
23999 N1 = N1->getOperand(0);
24002 // Generate the wide operation.
24003 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24004 unsigned Opcode = N->getOpcode();
24006 case ISD::ANY_EXTEND:
24008 case ISD::ZERO_EXTEND: {
24009 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24010 APInt Mask = APInt::getAllOnesValue(InBits);
24011 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24012 return DAG.getNode(ISD::AND, DL, VT,
24013 Op, DAG.getConstant(Mask, VT));
24015 case ISD::SIGN_EXTEND:
24016 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24017 Op, DAG.getValueType(NarrowVT));
24019 llvm_unreachable("Unexpected opcode");
24023 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24024 TargetLowering::DAGCombinerInfo &DCI,
24025 const X86Subtarget *Subtarget) {
24026 EVT VT = N->getValueType(0);
24027 if (DCI.isBeforeLegalizeOps())
24030 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24034 // Create BEXTR instructions
24035 // BEXTR is ((X >> imm) & (2**size-1))
24036 if (VT == MVT::i32 || VT == MVT::i64) {
24037 SDValue N0 = N->getOperand(0);
24038 SDValue N1 = N->getOperand(1);
24041 // Check for BEXTR.
24042 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24043 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24044 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24045 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24046 if (MaskNode && ShiftNode) {
24047 uint64_t Mask = MaskNode->getZExtValue();
24048 uint64_t Shift = ShiftNode->getZExtValue();
24049 if (isMask_64(Mask)) {
24050 uint64_t MaskSize = CountPopulation_64(Mask);
24051 if (Shift + MaskSize <= VT.getSizeInBits())
24052 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24053 DAG.getConstant(Shift | (MaskSize << 8), VT));
24061 // Want to form ANDNP nodes:
24062 // 1) In the hopes of then easily combining them with OR and AND nodes
24063 // to form PBLEND/PSIGN.
24064 // 2) To match ANDN packed intrinsics
24065 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24068 SDValue N0 = N->getOperand(0);
24069 SDValue N1 = N->getOperand(1);
24072 // Check LHS for vnot
24073 if (N0.getOpcode() == ISD::XOR &&
24074 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24075 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24076 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24078 // Check RHS for vnot
24079 if (N1.getOpcode() == ISD::XOR &&
24080 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24081 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24082 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24087 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24088 TargetLowering::DAGCombinerInfo &DCI,
24089 const X86Subtarget *Subtarget) {
24090 if (DCI.isBeforeLegalizeOps())
24093 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
24097 SDValue N0 = N->getOperand(0);
24098 SDValue N1 = N->getOperand(1);
24099 EVT VT = N->getValueType(0);
24101 // look for psign/blend
24102 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24103 if (!Subtarget->hasSSSE3() ||
24104 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24107 // Canonicalize pandn to RHS
24108 if (N0.getOpcode() == X86ISD::ANDNP)
24110 // or (and (m, y), (pandn m, x))
24111 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24112 SDValue Mask = N1.getOperand(0);
24113 SDValue X = N1.getOperand(1);
24115 if (N0.getOperand(0) == Mask)
24116 Y = N0.getOperand(1);
24117 if (N0.getOperand(1) == Mask)
24118 Y = N0.getOperand(0);
24120 // Check to see if the mask appeared in both the AND and ANDNP and
24124 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24125 // Look through mask bitcast.
24126 if (Mask.getOpcode() == ISD::BITCAST)
24127 Mask = Mask.getOperand(0);
24128 if (X.getOpcode() == ISD::BITCAST)
24129 X = X.getOperand(0);
24130 if (Y.getOpcode() == ISD::BITCAST)
24131 Y = Y.getOperand(0);
24133 EVT MaskVT = Mask.getValueType();
24135 // Validate that the Mask operand is a vector sra node.
24136 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24137 // there is no psrai.b
24138 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24139 unsigned SraAmt = ~0;
24140 if (Mask.getOpcode() == ISD::SRA) {
24141 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24142 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24143 SraAmt = AmtConst->getZExtValue();
24144 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24145 SDValue SraC = Mask.getOperand(1);
24146 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24148 if ((SraAmt + 1) != EltBits)
24153 // Now we know we at least have a plendvb with the mask val. See if
24154 // we can form a psignb/w/d.
24155 // psign = x.type == y.type == mask.type && y = sub(0, x);
24156 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24157 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24158 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24159 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24160 "Unsupported VT for PSIGN");
24161 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24162 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24164 // PBLENDVB only available on SSE 4.1
24165 if (!Subtarget->hasSSE41())
24168 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24170 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
24171 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
24172 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
24173 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24174 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
24178 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24181 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24182 MachineFunction &MF = DAG.getMachineFunction();
24183 bool OptForSize = MF.getFunction()->getAttributes().
24184 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
24186 // SHLD/SHRD instructions have lower register pressure, but on some
24187 // platforms they have higher latency than the equivalent
24188 // series of shifts/or that would otherwise be generated.
24189 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24190 // have higher latencies and we are not optimizing for size.
24191 if (!OptForSize && Subtarget->isSHLDSlow())
24194 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24196 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24198 if (!N0.hasOneUse() || !N1.hasOneUse())
24201 SDValue ShAmt0 = N0.getOperand(1);
24202 if (ShAmt0.getValueType() != MVT::i8)
24204 SDValue ShAmt1 = N1.getOperand(1);
24205 if (ShAmt1.getValueType() != MVT::i8)
24207 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24208 ShAmt0 = ShAmt0.getOperand(0);
24209 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24210 ShAmt1 = ShAmt1.getOperand(0);
24213 unsigned Opc = X86ISD::SHLD;
24214 SDValue Op0 = N0.getOperand(0);
24215 SDValue Op1 = N1.getOperand(0);
24216 if (ShAmt0.getOpcode() == ISD::SUB) {
24217 Opc = X86ISD::SHRD;
24218 std::swap(Op0, Op1);
24219 std::swap(ShAmt0, ShAmt1);
24222 unsigned Bits = VT.getSizeInBits();
24223 if (ShAmt1.getOpcode() == ISD::SUB) {
24224 SDValue Sum = ShAmt1.getOperand(0);
24225 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24226 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24227 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24228 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24229 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24230 return DAG.getNode(Opc, DL, VT,
24232 DAG.getNode(ISD::TRUNCATE, DL,
24235 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24236 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24238 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24239 return DAG.getNode(Opc, DL, VT,
24240 N0.getOperand(0), N1.getOperand(0),
24241 DAG.getNode(ISD::TRUNCATE, DL,
24248 // Generate NEG and CMOV for integer abs.
24249 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24250 EVT VT = N->getValueType(0);
24252 // Since X86 does not have CMOV for 8-bit integer, we don't convert
24253 // 8-bit integer abs to NEG and CMOV.
24254 if (VT.isInteger() && VT.getSizeInBits() == 8)
24257 SDValue N0 = N->getOperand(0);
24258 SDValue N1 = N->getOperand(1);
24261 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
24262 // and change it to SUB and CMOV.
24263 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
24264 N0.getOpcode() == ISD::ADD &&
24265 N0.getOperand(1) == N1 &&
24266 N1.getOpcode() == ISD::SRA &&
24267 N1.getOperand(0) == N0.getOperand(0))
24268 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
24269 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
24270 // Generate SUB & CMOV.
24271 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
24272 DAG.getConstant(0, VT), N0.getOperand(0));
24274 SDValue Ops[] = { N0.getOperand(0), Neg,
24275 DAG.getConstant(X86::COND_GE, MVT::i8),
24276 SDValue(Neg.getNode(), 1) };
24277 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
24282 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
24283 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
24284 TargetLowering::DAGCombinerInfo &DCI,
24285 const X86Subtarget *Subtarget) {
24286 if (DCI.isBeforeLegalizeOps())
24289 if (Subtarget->hasCMov()) {
24290 SDValue RV = performIntegerAbsCombine(N, DAG);
24298 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
24299 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
24300 TargetLowering::DAGCombinerInfo &DCI,
24301 const X86Subtarget *Subtarget) {
24302 LoadSDNode *Ld = cast<LoadSDNode>(N);
24303 EVT RegVT = Ld->getValueType(0);
24304 EVT MemVT = Ld->getMemoryVT();
24306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24308 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
24309 // into two 16-byte operations.
24310 ISD::LoadExtType Ext = Ld->getExtensionType();
24311 unsigned Alignment = Ld->getAlignment();
24312 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
24313 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24314 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
24315 unsigned NumElems = RegVT.getVectorNumElements();
24319 SDValue Ptr = Ld->getBasePtr();
24320 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
24322 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
24324 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24325 Ld->getPointerInfo(), Ld->isVolatile(),
24326 Ld->isNonTemporal(), Ld->isInvariant(),
24328 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24329 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
24330 Ld->getPointerInfo(), Ld->isVolatile(),
24331 Ld->isNonTemporal(), Ld->isInvariant(),
24332 std::min(16U, Alignment));
24333 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
24335 Load2.getValue(1));
24337 SDValue NewVec = DAG.getUNDEF(RegVT);
24338 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
24339 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
24340 return DCI.CombineTo(N, NewVec, TF, true);
24346 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
24347 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
24348 const X86Subtarget *Subtarget) {
24349 StoreSDNode *St = cast<StoreSDNode>(N);
24350 EVT VT = St->getValue().getValueType();
24351 EVT StVT = St->getMemoryVT();
24353 SDValue StoredVal = St->getOperand(1);
24354 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24356 // If we are saving a concatenation of two XMM registers and 32-byte stores
24357 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
24358 unsigned Alignment = St->getAlignment();
24359 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
24360 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
24361 StVT == VT && !IsAligned) {
24362 unsigned NumElems = VT.getVectorNumElements();
24366 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
24367 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
24369 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
24370 SDValue Ptr0 = St->getBasePtr();
24371 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
24373 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
24374 St->getPointerInfo(), St->isVolatile(),
24375 St->isNonTemporal(), Alignment);
24376 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
24377 St->getPointerInfo(), St->isVolatile(),
24378 St->isNonTemporal(),
24379 std::min(16U, Alignment));
24380 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
24383 // Optimize trunc store (of multiple scalars) to shuffle and store.
24384 // First, pack all of the elements in one place. Next, store to memory
24385 // in fewer chunks.
24386 if (St->isTruncatingStore() && VT.isVector()) {
24387 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24388 unsigned NumElems = VT.getVectorNumElements();
24389 assert(StVT != VT && "Cannot truncate to the same type");
24390 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
24391 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24393 // From, To sizes and ElemCount must be pow of two
24394 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24395 // We are going to use the original vector elt for storing.
24396 // Accumulated smaller vector elements must be a multiple of the store size.
24397 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24399 unsigned SizeRatio = FromSz / ToSz;
24401 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24403 // Create a type on which we perform the shuffle
24404 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24405 StVT.getScalarType(), NumElems*SizeRatio);
24407 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24409 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
24410 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24411 for (unsigned i = 0; i != NumElems; ++i)
24412 ShuffleVec[i] = i * SizeRatio;
24414 // Can't shuffle using an illegal type.
24415 if (!TLI.isTypeLegal(WideVecVT))
24418 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24419 DAG.getUNDEF(WideVecVT),
24421 // At this point all of the data is stored at the bottom of the
24422 // register. We now need to save it to mem.
24424 // Find the largest store unit
24425 MVT StoreType = MVT::i8;
24426 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
24427 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
24428 MVT Tp = (MVT::SimpleValueType)tp;
24429 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24433 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24434 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24435 (64 <= NumElems * ToSz))
24436 StoreType = MVT::f64;
24438 // Bitcast the original vector into a vector of store-size units
24439 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24440 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24441 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24442 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
24443 SmallVector<SDValue, 8> Chains;
24444 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
24445 TLI.getPointerTy());
24446 SDValue Ptr = St->getBasePtr();
24448 // Perform one or more big stores into memory.
24449 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24450 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24451 StoreType, ShuffWide,
24452 DAG.getIntPtrConstant(i));
24453 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24454 St->getPointerInfo(), St->isVolatile(),
24455 St->isNonTemporal(), St->getAlignment());
24456 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24457 Chains.push_back(Ch);
24460 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24463 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24464 // the FP state in cases where an emms may be missing.
24465 // A preferable solution to the general problem is to figure out the right
24466 // places to insert EMMS. This qualifies as a quick hack.
24468 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24469 if (VT.getSizeInBits() != 64)
24472 const Function *F = DAG.getMachineFunction().getFunction();
24473 bool NoImplicitFloatOps = F->getAttributes().
24474 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
24475 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
24476 && Subtarget->hasSSE2();
24477 if ((VT.isVector() ||
24478 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24479 isa<LoadSDNode>(St->getValue()) &&
24480 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24481 St->getChain().hasOneUse() && !St->isVolatile()) {
24482 SDNode* LdVal = St->getValue().getNode();
24483 LoadSDNode *Ld = nullptr;
24484 int TokenFactorIndex = -1;
24485 SmallVector<SDValue, 8> Ops;
24486 SDNode* ChainVal = St->getChain().getNode();
24487 // Must be a store of a load. We currently handle two cases: the load
24488 // is a direct child, and it's under an intervening TokenFactor. It is
24489 // possible to dig deeper under nested TokenFactors.
24490 if (ChainVal == LdVal)
24491 Ld = cast<LoadSDNode>(St->getChain());
24492 else if (St->getValue().hasOneUse() &&
24493 ChainVal->getOpcode() == ISD::TokenFactor) {
24494 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24495 if (ChainVal->getOperand(i).getNode() == LdVal) {
24496 TokenFactorIndex = i;
24497 Ld = cast<LoadSDNode>(St->getValue());
24499 Ops.push_back(ChainVal->getOperand(i));
24503 if (!Ld || !ISD::isNormalLoad(Ld))
24506 // If this is not the MMX case, i.e. we are just turning i64 load/store
24507 // into f64 load/store, avoid the transformation if there are multiple
24508 // uses of the loaded value.
24509 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24514 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24515 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24517 if (Subtarget->is64Bit() || F64IsLegal) {
24518 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24519 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24520 Ld->getPointerInfo(), Ld->isVolatile(),
24521 Ld->isNonTemporal(), Ld->isInvariant(),
24522 Ld->getAlignment());
24523 SDValue NewChain = NewLd.getValue(1);
24524 if (TokenFactorIndex != -1) {
24525 Ops.push_back(NewChain);
24526 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24528 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24529 St->getPointerInfo(),
24530 St->isVolatile(), St->isNonTemporal(),
24531 St->getAlignment());
24534 // Otherwise, lower to two pairs of 32-bit loads / stores.
24535 SDValue LoAddr = Ld->getBasePtr();
24536 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24537 DAG.getConstant(4, MVT::i32));
24539 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24540 Ld->getPointerInfo(),
24541 Ld->isVolatile(), Ld->isNonTemporal(),
24542 Ld->isInvariant(), Ld->getAlignment());
24543 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24544 Ld->getPointerInfo().getWithOffset(4),
24545 Ld->isVolatile(), Ld->isNonTemporal(),
24547 MinAlign(Ld->getAlignment(), 4));
24549 SDValue NewChain = LoLd.getValue(1);
24550 if (TokenFactorIndex != -1) {
24551 Ops.push_back(LoLd);
24552 Ops.push_back(HiLd);
24553 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24556 LoAddr = St->getBasePtr();
24557 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24558 DAG.getConstant(4, MVT::i32));
24560 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24561 St->getPointerInfo(),
24562 St->isVolatile(), St->isNonTemporal(),
24563 St->getAlignment());
24564 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24565 St->getPointerInfo().getWithOffset(4),
24567 St->isNonTemporal(),
24568 MinAlign(St->getAlignment(), 4));
24569 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24574 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
24575 /// and return the operands for the horizontal operation in LHS and RHS. A
24576 /// horizontal operation performs the binary operation on successive elements
24577 /// of its first operand, then on successive elements of its second operand,
24578 /// returning the resulting values in a vector. For example, if
24579 /// A = < float a0, float a1, float a2, float a3 >
24581 /// B = < float b0, float b1, float b2, float b3 >
24582 /// then the result of doing a horizontal operation on A and B is
24583 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24584 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24585 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24586 /// set to A, RHS to B, and the routine returns 'true'.
24587 /// Note that the binary operation should have the property that if one of the
24588 /// operands is UNDEF then the result is UNDEF.
24589 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24590 // Look for the following pattern: if
24591 // A = < float a0, float a1, float a2, float a3 >
24592 // B = < float b0, float b1, float b2, float b3 >
24594 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24595 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24596 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24597 // which is A horizontal-op B.
24599 // At least one of the operands should be a vector shuffle.
24600 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24601 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24604 MVT VT = LHS.getSimpleValueType();
24606 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24607 "Unsupported vector type for horizontal add/sub");
24609 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24610 // operate independently on 128-bit lanes.
24611 unsigned NumElts = VT.getVectorNumElements();
24612 unsigned NumLanes = VT.getSizeInBits()/128;
24613 unsigned NumLaneElts = NumElts / NumLanes;
24614 assert((NumLaneElts % 2 == 0) &&
24615 "Vector type should have an even number of elements in each lane");
24616 unsigned HalfLaneElts = NumLaneElts/2;
24618 // View LHS in the form
24619 // LHS = VECTOR_SHUFFLE A, B, LMask
24620 // If LHS is not a shuffle then pretend it is the shuffle
24621 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24622 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24625 SmallVector<int, 16> LMask(NumElts);
24626 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24627 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24628 A = LHS.getOperand(0);
24629 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24630 B = LHS.getOperand(1);
24631 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24632 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24634 if (LHS.getOpcode() != ISD::UNDEF)
24636 for (unsigned i = 0; i != NumElts; ++i)
24640 // Likewise, view RHS in the form
24641 // RHS = VECTOR_SHUFFLE C, D, RMask
24643 SmallVector<int, 16> RMask(NumElts);
24644 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24645 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24646 C = RHS.getOperand(0);
24647 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24648 D = RHS.getOperand(1);
24649 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24650 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24652 if (RHS.getOpcode() != ISD::UNDEF)
24654 for (unsigned i = 0; i != NumElts; ++i)
24658 // Check that the shuffles are both shuffling the same vectors.
24659 if (!(A == C && B == D) && !(A == D && B == C))
24662 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24663 if (!A.getNode() && !B.getNode())
24666 // If A and B occur in reverse order in RHS, then "swap" them (which means
24667 // rewriting the mask).
24669 CommuteVectorShuffleMask(RMask, NumElts);
24671 // At this point LHS and RHS are equivalent to
24672 // LHS = VECTOR_SHUFFLE A, B, LMask
24673 // RHS = VECTOR_SHUFFLE A, B, RMask
24674 // Check that the masks correspond to performing a horizontal operation.
24675 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24676 for (unsigned i = 0; i != NumLaneElts; ++i) {
24677 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24679 // Ignore any UNDEF components.
24680 if (LIdx < 0 || RIdx < 0 ||
24681 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24682 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24685 // Check that successive elements are being operated on. If not, this is
24686 // not a horizontal operation.
24687 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24688 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24689 if (!(LIdx == Index && RIdx == Index + 1) &&
24690 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24695 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24696 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24700 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
24701 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24702 const X86Subtarget *Subtarget) {
24703 EVT VT = N->getValueType(0);
24704 SDValue LHS = N->getOperand(0);
24705 SDValue RHS = N->getOperand(1);
24707 // Try to synthesize horizontal adds from adds of shuffles.
24708 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24709 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24710 isHorizontalBinOp(LHS, RHS, true))
24711 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24715 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
24716 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24717 const X86Subtarget *Subtarget) {
24718 EVT VT = N->getValueType(0);
24719 SDValue LHS = N->getOperand(0);
24720 SDValue RHS = N->getOperand(1);
24722 // Try to synthesize horizontal subs from subs of shuffles.
24723 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24724 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24725 isHorizontalBinOp(LHS, RHS, false))
24726 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24730 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
24731 /// X86ISD::FXOR nodes.
24732 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24733 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24734 // F[X]OR(0.0, x) -> x
24735 // F[X]OR(x, 0.0) -> x
24736 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24737 if (C->getValueAPF().isPosZero())
24738 return N->getOperand(1);
24739 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24740 if (C->getValueAPF().isPosZero())
24741 return N->getOperand(0);
24745 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
24746 /// X86ISD::FMAX nodes.
24747 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24748 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24750 // Only perform optimizations if UnsafeMath is used.
24751 if (!DAG.getTarget().Options.UnsafeFPMath)
24754 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24755 // into FMINC and FMAXC, which are Commutative operations.
24756 unsigned NewOp = 0;
24757 switch (N->getOpcode()) {
24758 default: llvm_unreachable("unknown opcode");
24759 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24760 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24763 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24764 N->getOperand(0), N->getOperand(1));
24767 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
24768 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24769 // FAND(0.0, x) -> 0.0
24770 // FAND(x, 0.0) -> 0.0
24771 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24772 if (C->getValueAPF().isPosZero())
24773 return N->getOperand(0);
24774 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24775 if (C->getValueAPF().isPosZero())
24776 return N->getOperand(1);
24780 /// PerformFANDNCombine - Do target-specific dag combines on X86ISD::FANDN nodes
24781 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24782 // FANDN(x, 0.0) -> 0.0
24783 // FANDN(0.0, x) -> x
24784 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24785 if (C->getValueAPF().isPosZero())
24786 return N->getOperand(1);
24787 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24788 if (C->getValueAPF().isPosZero())
24789 return N->getOperand(1);
24793 static SDValue PerformBTCombine(SDNode *N,
24795 TargetLowering::DAGCombinerInfo &DCI) {
24796 // BT ignores high bits in the bit index operand.
24797 SDValue Op1 = N->getOperand(1);
24798 if (Op1.hasOneUse()) {
24799 unsigned BitWidth = Op1.getValueSizeInBits();
24800 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24801 APInt KnownZero, KnownOne;
24802 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24803 !DCI.isBeforeLegalizeOps());
24804 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24805 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24806 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24807 DCI.CommitTargetLoweringOpt(TLO);
24812 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24813 SDValue Op = N->getOperand(0);
24814 if (Op.getOpcode() == ISD::BITCAST)
24815 Op = Op.getOperand(0);
24816 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24817 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24818 VT.getVectorElementType().getSizeInBits() ==
24819 OpVT.getVectorElementType().getSizeInBits()) {
24820 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24825 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24826 const X86Subtarget *Subtarget) {
24827 EVT VT = N->getValueType(0);
24828 if (!VT.isVector())
24831 SDValue N0 = N->getOperand(0);
24832 SDValue N1 = N->getOperand(1);
24833 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24836 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24837 // both SSE and AVX2 since there is no sign-extended shift right
24838 // operation on a vector with 64-bit elements.
24839 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24840 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24841 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24842 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24843 SDValue N00 = N0.getOperand(0);
24845 // EXTLOAD has a better solution on AVX2,
24846 // it may be replaced with X86ISD::VSEXT node.
24847 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24848 if (!ISD::isNormalLoad(N00.getNode()))
24851 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24852 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24854 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24860 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24861 TargetLowering::DAGCombinerInfo &DCI,
24862 const X86Subtarget *Subtarget) {
24863 SDValue N0 = N->getOperand(0);
24864 EVT VT = N->getValueType(0);
24866 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24867 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24868 // This exposes the sext to the sdivrem lowering, so that it directly extends
24869 // from AH (which we otherwise need to do contortions to access).
24870 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24871 N0.getValueType() == MVT::i8 && VT == MVT::i32) {
24873 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24874 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, dl, NodeTys,
24875 N0.getOperand(0), N0.getOperand(1));
24876 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24877 return R.getValue(1);
24880 if (!DCI.isBeforeLegalizeOps())
24883 if (!Subtarget->hasFp256())
24886 if (VT.isVector() && VT.getSizeInBits() == 256) {
24887 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24895 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24896 const X86Subtarget* Subtarget) {
24898 EVT VT = N->getValueType(0);
24900 // Let legalize expand this if it isn't a legal type yet.
24901 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24904 EVT ScalarVT = VT.getScalarType();
24905 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24906 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
24909 SDValue A = N->getOperand(0);
24910 SDValue B = N->getOperand(1);
24911 SDValue C = N->getOperand(2);
24913 bool NegA = (A.getOpcode() == ISD::FNEG);
24914 bool NegB = (B.getOpcode() == ISD::FNEG);
24915 bool NegC = (C.getOpcode() == ISD::FNEG);
24917 // Negative multiplication when NegA xor NegB
24918 bool NegMul = (NegA != NegB);
24920 A = A.getOperand(0);
24922 B = B.getOperand(0);
24924 C = C.getOperand(0);
24928 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24930 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24932 return DAG.getNode(Opcode, dl, VT, A, B, C);
24935 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24936 TargetLowering::DAGCombinerInfo &DCI,
24937 const X86Subtarget *Subtarget) {
24938 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24939 // (and (i32 x86isd::setcc_carry), 1)
24940 // This eliminates the zext. This transformation is necessary because
24941 // ISD::SETCC is always legalized to i8.
24943 SDValue N0 = N->getOperand(0);
24944 EVT VT = N->getValueType(0);
24946 if (N0.getOpcode() == ISD::AND &&
24948 N0.getOperand(0).hasOneUse()) {
24949 SDValue N00 = N0.getOperand(0);
24950 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24951 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24952 if (!C || C->getZExtValue() != 1)
24954 return DAG.getNode(ISD::AND, dl, VT,
24955 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24956 N00.getOperand(0), N00.getOperand(1)),
24957 DAG.getConstant(1, VT));
24961 if (N0.getOpcode() == ISD::TRUNCATE &&
24963 N0.getOperand(0).hasOneUse()) {
24964 SDValue N00 = N0.getOperand(0);
24965 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24966 return DAG.getNode(ISD::AND, dl, VT,
24967 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24968 N00.getOperand(0), N00.getOperand(1)),
24969 DAG.getConstant(1, VT));
24972 if (VT.is256BitVector()) {
24973 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
24978 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24979 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24980 // This exposes the zext to the udivrem lowering, so that it directly extends
24981 // from AH (which we otherwise need to do contortions to access).
24982 if (N0.getOpcode() == ISD::UDIVREM &&
24983 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24984 (VT == MVT::i32 || VT == MVT::i64)) {
24985 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24986 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24987 N0.getOperand(0), N0.getOperand(1));
24988 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24989 return R.getValue(1);
24995 // Optimize x == -y --> x+y == 0
24996 // x != -y --> x+y != 0
24997 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24998 const X86Subtarget* Subtarget) {
24999 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
25000 SDValue LHS = N->getOperand(0);
25001 SDValue RHS = N->getOperand(1);
25002 EVT VT = N->getValueType(0);
25005 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
25006 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
25007 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
25008 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25009 LHS.getValueType(), RHS, LHS.getOperand(1));
25010 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25011 addV, DAG.getConstant(0, addV.getValueType()), CC);
25013 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
25014 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
25015 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
25016 SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N),
25017 RHS.getValueType(), LHS, RHS.getOperand(1));
25018 return DAG.getSetCC(SDLoc(N), N->getValueType(0),
25019 addV, DAG.getConstant(0, addV.getValueType()), CC);
25022 if (VT.getScalarType() == MVT::i1) {
25023 bool IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
25024 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25025 bool IsVZero0 = ISD::isBuildVectorAllZeros(LHS.getNode());
25026 if (!IsSEXT0 && !IsVZero0)
25028 bool IsSEXT1 = (RHS.getOpcode() == ISD::SIGN_EXTEND) &&
25029 (RHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
25030 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
25032 if (!IsSEXT1 && !IsVZero1)
25035 if (IsSEXT0 && IsVZero1) {
25036 assert(VT == LHS.getOperand(0).getValueType() && "Uexpected operand type");
25037 if (CC == ISD::SETEQ)
25038 return DAG.getNOT(DL, LHS.getOperand(0), VT);
25039 return LHS.getOperand(0);
25041 if (IsSEXT1 && IsVZero0) {
25042 assert(VT == RHS.getOperand(0).getValueType() && "Uexpected operand type");
25043 if (CC == ISD::SETEQ)
25044 return DAG.getNOT(DL, RHS.getOperand(0), VT);
25045 return RHS.getOperand(0);
25052 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
25053 const X86Subtarget *Subtarget) {
25055 MVT VT = N->getOperand(1)->getSimpleValueType(0);
25056 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
25057 "X86insertps is only defined for v4x32");
25059 SDValue Ld = N->getOperand(1);
25060 if (MayFoldLoad(Ld)) {
25061 // Extract the countS bits from the immediate so we can get the proper
25062 // address when narrowing the vector load to a specific element.
25063 // When the second source op is a memory address, interps doesn't use
25064 // countS and just gets an f32 from that address.
25065 unsigned DestIndex =
25066 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
25067 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
25071 // Create this as a scalar to vector to match the instruction pattern.
25072 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
25073 // countS bits are ignored when loading from memory on insertps, which
25074 // means we don't need to explicitly set them to 0.
25075 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
25076 LoadScalarToVector, N->getOperand(2));
25079 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
25080 // as "sbb reg,reg", since it can be extended without zext and produces
25081 // an all-ones bit which is more useful than 0/1 in some cases.
25082 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
25085 return DAG.getNode(ISD::AND, DL, VT,
25086 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25087 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
25088 DAG.getConstant(1, VT));
25089 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
25090 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
25091 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
25092 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));
25095 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
25096 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
25097 TargetLowering::DAGCombinerInfo &DCI,
25098 const X86Subtarget *Subtarget) {
25100 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
25101 SDValue EFLAGS = N->getOperand(1);
25103 if (CC == X86::COND_A) {
25104 // Try to convert COND_A into COND_B in an attempt to facilitate
25105 // materializing "setb reg".
25107 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
25108 // cannot take an immediate as its first operand.
25110 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
25111 EFLAGS.getValueType().isInteger() &&
25112 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
25113 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
25114 EFLAGS.getNode()->getVTList(),
25115 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
25116 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
25117 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
25121 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
25122 // a zext and produces an all-ones bit which is more useful than 0/1 in some
25124 if (CC == X86::COND_B)
25125 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
25129 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25130 if (Flags.getNode()) {
25131 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25132 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
25138 // Optimize branch condition evaluation.
25140 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
25141 TargetLowering::DAGCombinerInfo &DCI,
25142 const X86Subtarget *Subtarget) {
25144 SDValue Chain = N->getOperand(0);
25145 SDValue Dest = N->getOperand(1);
25146 SDValue EFLAGS = N->getOperand(3);
25147 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
25151 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
25152 if (Flags.getNode()) {
25153 SDValue Cond = DAG.getConstant(CC, MVT::i8);
25154 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
25161 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
25162 SelectionDAG &DAG) {
25163 // Take advantage of vector comparisons producing 0 or -1 in each lane to
25164 // optimize away operation when it's from a constant.
25166 // The general transformation is:
25167 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
25168 // AND(VECTOR_CMP(x,y), constant2)
25169 // constant2 = UNARYOP(constant)
25171 // Early exit if this isn't a vector operation, the operand of the
25172 // unary operation isn't a bitwise AND, or if the sizes of the operations
25173 // aren't the same.
25174 EVT VT = N->getValueType(0);
25175 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
25176 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
25177 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
25180 // Now check that the other operand of the AND is a constant. We could
25181 // make the transformation for non-constant splats as well, but it's unclear
25182 // that would be a benefit as it would not eliminate any operations, just
25183 // perform one more step in scalar code before moving to the vector unit.
25184 if (BuildVectorSDNode *BV =
25185 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
25186 // Bail out if the vector isn't a constant.
25187 if (!BV->isConstant())
25190 // Everything checks out. Build up the new and improved node.
25192 EVT IntVT = BV->getValueType(0);
25193 // Create a new constant of the appropriate type for the transformed
25195 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
25196 // The AND node needs bitcasts to/from an integer vector type around it.
25197 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);
25198 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
25199 N->getOperand(0)->getOperand(0), MaskConst);
25200 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);
25207 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
25208 const X86TargetLowering *XTLI) {
25209 // First try to optimize away the conversion entirely when it's
25210 // conditionally from a constant. Vectors only.
25211 SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG);
25212 if (Res != SDValue())
25215 // Now move on to more general possibilities.
25216 SDValue Op0 = N->getOperand(0);
25217 EVT InVT = Op0->getValueType(0);
25219 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
25220 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
25222 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
25223 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
25224 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
25227 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
25228 // a 32-bit target where SSE doesn't support i64->FP operations.
25229 if (Op0.getOpcode() == ISD::LOAD) {
25230 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25231 EVT VT = Ld->getValueType(0);
25232 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
25233 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25234 !XTLI->getSubtarget()->is64Bit() &&
25236 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
25237 Ld->getChain(), Op0, DAG);
25238 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25245 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25246 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25247 X86TargetLowering::DAGCombinerInfo &DCI) {
25248 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25249 // the result is either zero or one (depending on the input carry bit).
25250 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25251 if (X86::isZeroNode(N->getOperand(0)) &&
25252 X86::isZeroNode(N->getOperand(1)) &&
25253 // We don't have a good way to replace an EFLAGS use, so only do this when
25255 SDValue(N, 1).use_empty()) {
25257 EVT VT = N->getValueType(0);
25258 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
25259 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25260 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25261 DAG.getConstant(X86::COND_B,MVT::i8),
25263 DAG.getConstant(1, VT));
25264 return DCI.CombineTo(N, Res1, CarryOut);
25270 // fold (add Y, (sete X, 0)) -> adc 0, Y
25271 // (add Y, (setne X, 0)) -> sbb -1, Y
25272 // (sub (sete X, 0), Y) -> sbb 0, Y
25273 // (sub (setne X, 0), Y) -> adc -1, Y
25274 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25277 // Look through ZExts.
25278 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25279 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25282 SDValue SetCC = Ext.getOperand(0);
25283 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25286 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25287 if (CC != X86::COND_E && CC != X86::COND_NE)
25290 SDValue Cmp = SetCC.getOperand(1);
25291 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25292 !X86::isZeroNode(Cmp.getOperand(1)) ||
25293 !Cmp.getOperand(0).getValueType().isInteger())
25296 SDValue CmpOp0 = Cmp.getOperand(0);
25297 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25298 DAG.getConstant(1, CmpOp0.getValueType()));
25300 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25301 if (CC == X86::COND_NE)
25302 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25303 DL, OtherVal.getValueType(), OtherVal,
25304 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
25305 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25306 DL, OtherVal.getValueType(), OtherVal,
25307 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
25310 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25311 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25312 const X86Subtarget *Subtarget) {
25313 EVT VT = N->getValueType(0);
25314 SDValue Op0 = N->getOperand(0);
25315 SDValue Op1 = N->getOperand(1);
25317 // Try to synthesize horizontal adds from adds of shuffles.
25318 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25319 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25320 isHorizontalBinOp(Op0, Op1, true))
25321 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25323 return OptimizeConditionalInDecrement(N, DAG);
25326 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25327 const X86Subtarget *Subtarget) {
25328 SDValue Op0 = N->getOperand(0);
25329 SDValue Op1 = N->getOperand(1);
25331 // X86 can't encode an immediate LHS of a sub. See if we can push the
25332 // negation into a preceding instruction.
25333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25334 // If the RHS of the sub is a XOR with one use and a constant, invert the
25335 // immediate. Then add one to the LHS of the sub so we can turn
25336 // X-Y -> X+~Y+1, saving one register.
25337 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25338 isa<ConstantSDNode>(Op1.getOperand(1))) {
25339 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25340 EVT VT = Op0.getValueType();
25341 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25343 DAG.getConstant(~XorC, VT));
25344 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25345 DAG.getConstant(C->getAPIntValue()+1, VT));
25349 // Try to synthesize horizontal adds from adds of shuffles.
25350 EVT VT = N->getValueType(0);
25351 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25352 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25353 isHorizontalBinOp(Op0, Op1, true))
25354 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25356 return OptimizeConditionalInDecrement(N, DAG);
25359 /// performVZEXTCombine - Performs build vector combines
25360 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25361 TargetLowering::DAGCombinerInfo &DCI,
25362 const X86Subtarget *Subtarget) {
25364 MVT VT = N->getSimpleValueType(0);
25365 SDValue Op = N->getOperand(0);
25366 MVT OpVT = Op.getSimpleValueType();
25367 MVT OpEltVT = OpVT.getVectorElementType();
25368 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25370 // (vzext (bitcast (vzext (x)) -> (vzext x)
25372 while (V.getOpcode() == ISD::BITCAST)
25373 V = V.getOperand(0);
25375 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25376 MVT InnerVT = V.getSimpleValueType();
25377 MVT InnerEltVT = InnerVT.getVectorElementType();
25379 // If the element sizes match exactly, we can just do one larger vzext. This
25380 // is always an exact type match as vzext operates on integer types.
25381 if (OpEltVT == InnerEltVT) {
25382 assert(OpVT == InnerVT && "Types must match for vzext!");
25383 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25386 // The only other way we can combine them is if only a single element of the
25387 // inner vzext is used in the input to the outer vzext.
25388 if (InnerEltVT.getSizeInBits() < InputBits)
25391 // In this case, the inner vzext is completely dead because we're going to
25392 // only look at bits inside of the low element. Just do the outer vzext on
25393 // a bitcast of the input to the inner.
25394 return DAG.getNode(X86ISD::VZEXT, DL, VT,
25395 DAG.getNode(ISD::BITCAST, DL, OpVT, V));
25398 // Check if we can bypass extracting and re-inserting an element of an input
25399 // vector. Essentialy:
25400 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25401 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25402 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25403 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25404 SDValue ExtractedV = V.getOperand(0);
25405 SDValue OrigV = ExtractedV.getOperand(0);
25406 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25407 if (ExtractIdx->getZExtValue() == 0) {
25408 MVT OrigVT = OrigV.getSimpleValueType();
25409 // Extract a subvector if necessary...
25410 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25411 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25412 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25413 OrigVT.getVectorNumElements() / Ratio);
25414 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25415 DAG.getIntPtrConstant(0));
25417 Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);
25418 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25425 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25426 DAGCombinerInfo &DCI) const {
25427 SelectionDAG &DAG = DCI.DAG;
25428 switch (N->getOpcode()) {
25430 case ISD::EXTRACT_VECTOR_ELT:
25431 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25434 case X86ISD::SHRUNKBLEND:
25435 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25436 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25437 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25438 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25439 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25440 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25443 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25444 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25445 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25446 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25447 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25448 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25449 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
25450 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25451 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25453 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25455 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25456 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25457 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25458 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25459 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25460 case ISD::ANY_EXTEND:
25461 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25462 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25463 case ISD::SIGN_EXTEND_INREG:
25464 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25465 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
25466 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25467 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25468 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25469 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25470 case X86ISD::SHUFP: // Handle all target specific shuffles
25471 case X86ISD::PALIGNR:
25472 case X86ISD::UNPCKH:
25473 case X86ISD::UNPCKL:
25474 case X86ISD::MOVHLPS:
25475 case X86ISD::MOVLHPS:
25476 case X86ISD::PSHUFB:
25477 case X86ISD::PSHUFD:
25478 case X86ISD::PSHUFHW:
25479 case X86ISD::PSHUFLW:
25480 case X86ISD::MOVSS:
25481 case X86ISD::MOVSD:
25482 case X86ISD::VPERMILPI:
25483 case X86ISD::VPERM2X128:
25484 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25485 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25486 case ISD::INTRINSIC_WO_CHAIN:
25487 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25488 case X86ISD::INSERTPS:
25489 return PerformINSERTPSCombine(N, DAG, Subtarget);
25490 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget);
25496 /// isTypeDesirableForOp - Return true if the target has native support for
25497 /// the specified value type and it is 'desirable' to use the type for the
25498 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25499 /// instruction encodings are longer and some i16 instructions are slow.
25500 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25501 if (!isTypeLegal(VT))
25503 if (VT != MVT::i16)
25510 case ISD::SIGN_EXTEND:
25511 case ISD::ZERO_EXTEND:
25512 case ISD::ANY_EXTEND:
25525 /// IsDesirableToPromoteOp - This method query the target whether it is
25526 /// beneficial for dag combiner to promote the specified node. If true, it
25527 /// should return the desired promotion type by reference.
25528 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25529 EVT VT = Op.getValueType();
25530 if (VT != MVT::i16)
25533 bool Promote = false;
25534 bool Commute = false;
25535 switch (Op.getOpcode()) {
25538 LoadSDNode *LD = cast<LoadSDNode>(Op);
25539 // If the non-extending load has a single use and it's not live out, then it
25540 // might be folded.
25541 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25542 Op.hasOneUse()*/) {
25543 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25544 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25545 // The only case where we'd want to promote LOAD (rather then it being
25546 // promoted as an operand is when it's only use is liveout.
25547 if (UI->getOpcode() != ISD::CopyToReg)
25554 case ISD::SIGN_EXTEND:
25555 case ISD::ZERO_EXTEND:
25556 case ISD::ANY_EXTEND:
25561 SDValue N0 = Op.getOperand(0);
25562 // Look out for (store (shl (load), x)).
25563 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25576 SDValue N0 = Op.getOperand(0);
25577 SDValue N1 = Op.getOperand(1);
25578 if (!Commute && MayFoldLoad(N1))
25580 // Avoid disabling potential load folding opportunities.
25581 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25583 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25593 //===----------------------------------------------------------------------===//
25594 // X86 Inline Assembly Support
25595 //===----------------------------------------------------------------------===//
25598 // Helper to match a string separated by whitespace.
25599 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
25600 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
25602 for (unsigned i = 0, e = args.size(); i != e; ++i) {
25603 StringRef piece(*args[i]);
25604 if (!s.startswith(piece)) // Check if the piece matches.
25607 s = s.substr(piece.size());
25608 StringRef::size_type pos = s.find_first_not_of(" \t");
25609 if (pos == 0) // We matched a prefix.
25617 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
25620 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25622 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25623 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25624 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25625 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25627 if (AsmPieces.size() == 3)
25629 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25636 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25637 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25639 std::string AsmStr = IA->getAsmString();
25641 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25642 if (!Ty || Ty->getBitWidth() % 16 != 0)
25645 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25646 SmallVector<StringRef, 4> AsmPieces;
25647 SplitString(AsmStr, AsmPieces, ";\n");
25649 switch (AsmPieces.size()) {
25650 default: return false;
25652 // FIXME: this should verify that we are targeting a 486 or better. If not,
25653 // we will turn this bswap into something that will be lowered to logical
25654 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25655 // lower so don't worry about this.
25657 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
25658 matchAsm(AsmPieces[0], "bswapl", "$0") ||
25659 matchAsm(AsmPieces[0], "bswapq", "$0") ||
25660 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
25661 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
25662 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
25663 // No need to check constraints, nothing other than the equivalent of
25664 // "=r,0" would be valid here.
25665 return IntrinsicLowering::LowerToByteSwap(CI);
25668 // rorw $$8, ${0:w} --> llvm.bswap.i16
25669 if (CI->getType()->isIntegerTy(16) &&
25670 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25671 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
25672 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
25674 const std::string &ConstraintsStr = IA->getConstraintString();
25675 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25676 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25677 if (clobbersFlagRegisters(AsmPieces))
25678 return IntrinsicLowering::LowerToByteSwap(CI);
25682 if (CI->getType()->isIntegerTy(32) &&
25683 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25684 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
25685 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
25686 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
25688 const std::string &ConstraintsStr = IA->getConstraintString();
25689 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25690 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25691 if (clobbersFlagRegisters(AsmPieces))
25692 return IntrinsicLowering::LowerToByteSwap(CI);
25695 if (CI->getType()->isIntegerTy(64)) {
25696 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25697 if (Constraints.size() >= 2 &&
25698 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25699 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25700 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25701 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
25702 matchAsm(AsmPieces[1], "bswap", "%edx") &&
25703 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
25704 return IntrinsicLowering::LowerToByteSwap(CI);
25712 /// getConstraintType - Given a constraint letter, return the type of
25713 /// constraint it is for this target.
25714 X86TargetLowering::ConstraintType
25715 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25716 if (Constraint.size() == 1) {
25717 switch (Constraint[0]) {
25728 return C_RegisterClass;
25752 return TargetLowering::getConstraintType(Constraint);
25755 /// Examine constraint type and operand type and determine a weight value.
25756 /// This object must already have been set up with the operand type
25757 /// and the current alternative constraint selected.
25758 TargetLowering::ConstraintWeight
25759 X86TargetLowering::getSingleConstraintMatchWeight(
25760 AsmOperandInfo &info, const char *constraint) const {
25761 ConstraintWeight weight = CW_Invalid;
25762 Value *CallOperandVal = info.CallOperandVal;
25763 // If we don't have a value, we can't do a match,
25764 // but allow it at the lowest weight.
25765 if (!CallOperandVal)
25767 Type *type = CallOperandVal->getType();
25768 // Look at the constraint type.
25769 switch (*constraint) {
25771 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25782 if (CallOperandVal->getType()->isIntegerTy())
25783 weight = CW_SpecificReg;
25788 if (type->isFloatingPointTy())
25789 weight = CW_SpecificReg;
25792 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25793 weight = CW_SpecificReg;
25797 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25798 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25799 weight = CW_Register;
25802 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25803 if (C->getZExtValue() <= 31)
25804 weight = CW_Constant;
25808 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25809 if (C->getZExtValue() <= 63)
25810 weight = CW_Constant;
25814 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25815 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25816 weight = CW_Constant;
25820 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25821 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25822 weight = CW_Constant;
25826 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25827 if (C->getZExtValue() <= 3)
25828 weight = CW_Constant;
25832 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25833 if (C->getZExtValue() <= 0xff)
25834 weight = CW_Constant;
25839 if (dyn_cast<ConstantFP>(CallOperandVal)) {
25840 weight = CW_Constant;
25844 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25845 if ((C->getSExtValue() >= -0x80000000LL) &&
25846 (C->getSExtValue() <= 0x7fffffffLL))
25847 weight = CW_Constant;
25851 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25852 if (C->getZExtValue() <= 0xffffffff)
25853 weight = CW_Constant;
25860 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25861 /// with another that has more specific requirements based on the type of the
25862 /// corresponding operand.
25863 const char *X86TargetLowering::
25864 LowerXConstraint(EVT ConstraintVT) const {
25865 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25866 // 'f' like normal targets.
25867 if (ConstraintVT.isFloatingPoint()) {
25868 if (Subtarget->hasSSE2())
25870 if (Subtarget->hasSSE1())
25874 return TargetLowering::LowerXConstraint(ConstraintVT);
25877 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25878 /// vector. If it is invalid, don't add anything to Ops.
25879 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25880 std::string &Constraint,
25881 std::vector<SDValue>&Ops,
25882 SelectionDAG &DAG) const {
25885 // Only support length 1 constraints for now.
25886 if (Constraint.length() > 1) return;
25888 char ConstraintLetter = Constraint[0];
25889 switch (ConstraintLetter) {
25892 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25893 if (C->getZExtValue() <= 31) {
25894 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25900 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25901 if (C->getZExtValue() <= 63) {
25902 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25908 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25909 if (isInt<8>(C->getSExtValue())) {
25910 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25916 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25917 if (C->getZExtValue() <= 255) {
25918 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25924 // 32-bit signed value
25925 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25926 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25927 C->getSExtValue())) {
25928 // Widen to 64 bits here to get it sign extended.
25929 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
25932 // FIXME gcc accepts some relocatable values here too, but only in certain
25933 // memory models; it's complicated.
25938 // 32-bit unsigned value
25939 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25940 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25941 C->getZExtValue())) {
25942 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
25946 // FIXME gcc accepts some relocatable values here too, but only in certain
25947 // memory models; it's complicated.
25951 // Literal immediates are always ok.
25952 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25953 // Widen to 64 bits here to get it sign extended.
25954 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
25958 // In any sort of PIC mode addresses need to be computed at runtime by
25959 // adding in a register or some sort of table lookup. These can't
25960 // be used as immediates.
25961 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25964 // If we are in non-pic codegen mode, we allow the address of a global (with
25965 // an optional displacement) to be used with 'i'.
25966 GlobalAddressSDNode *GA = nullptr;
25967 int64_t Offset = 0;
25969 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25971 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25972 Offset += GA->getOffset();
25974 } else if (Op.getOpcode() == ISD::ADD) {
25975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25976 Offset += C->getZExtValue();
25977 Op = Op.getOperand(0);
25980 } else if (Op.getOpcode() == ISD::SUB) {
25981 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25982 Offset += -C->getZExtValue();
25983 Op = Op.getOperand(0);
25988 // Otherwise, this isn't something we can handle, reject it.
25992 const GlobalValue *GV = GA->getGlobal();
25993 // If we require an extra load to get this address, as in PIC mode, we
25994 // can't accept it.
25995 if (isGlobalStubReference(
25996 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25999 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
26000 GA->getValueType(0), Offset);
26005 if (Result.getNode()) {
26006 Ops.push_back(Result);
26009 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
26012 std::pair<unsigned, const TargetRegisterClass*>
26013 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
26015 // First, see if this is a constraint that directly corresponds to an LLVM
26017 if (Constraint.size() == 1) {
26018 // GCC Constraint Letters
26019 switch (Constraint[0]) {
26021 // TODO: Slight differences here in allocation order and leaving
26022 // RIP in the class. Do they matter any more here than they do
26023 // in the normal allocation?
26024 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
26025 if (Subtarget->is64Bit()) {
26026 if (VT == MVT::i32 || VT == MVT::f32)
26027 return std::make_pair(0U, &X86::GR32RegClass);
26028 if (VT == MVT::i16)
26029 return std::make_pair(0U, &X86::GR16RegClass);
26030 if (VT == MVT::i8 || VT == MVT::i1)
26031 return std::make_pair(0U, &X86::GR8RegClass);
26032 if (VT == MVT::i64 || VT == MVT::f64)
26033 return std::make_pair(0U, &X86::GR64RegClass);
26036 // 32-bit fallthrough
26037 case 'Q': // Q_REGS
26038 if (VT == MVT::i32 || VT == MVT::f32)
26039 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
26040 if (VT == MVT::i16)
26041 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
26042 if (VT == MVT::i8 || VT == MVT::i1)
26043 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
26044 if (VT == MVT::i64)
26045 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
26047 case 'r': // GENERAL_REGS
26048 case 'l': // INDEX_REGS
26049 if (VT == MVT::i8 || VT == MVT::i1)
26050 return std::make_pair(0U, &X86::GR8RegClass);
26051 if (VT == MVT::i16)
26052 return std::make_pair(0U, &X86::GR16RegClass);
26053 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
26054 return std::make_pair(0U, &X86::GR32RegClass);
26055 return std::make_pair(0U, &X86::GR64RegClass);
26056 case 'R': // LEGACY_REGS
26057 if (VT == MVT::i8 || VT == MVT::i1)
26058 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
26059 if (VT == MVT::i16)
26060 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
26061 if (VT == MVT::i32 || !Subtarget->is64Bit())
26062 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
26063 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
26064 case 'f': // FP Stack registers.
26065 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
26066 // value to the correct fpstack register class.
26067 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
26068 return std::make_pair(0U, &X86::RFP32RegClass);
26069 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
26070 return std::make_pair(0U, &X86::RFP64RegClass);
26071 return std::make_pair(0U, &X86::RFP80RegClass);
26072 case 'y': // MMX_REGS if MMX allowed.
26073 if (!Subtarget->hasMMX()) break;
26074 return std::make_pair(0U, &X86::VR64RegClass);
26075 case 'Y': // SSE_REGS if SSE2 allowed
26076 if (!Subtarget->hasSSE2()) break;
26078 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
26079 if (!Subtarget->hasSSE1()) break;
26081 switch (VT.SimpleTy) {
26083 // Scalar SSE types.
26086 return std::make_pair(0U, &X86::FR32RegClass);
26089 return std::make_pair(0U, &X86::FR64RegClass);
26097 return std::make_pair(0U, &X86::VR128RegClass);
26105 return std::make_pair(0U, &X86::VR256RegClass);
26110 return std::make_pair(0U, &X86::VR512RegClass);
26116 // Use the default implementation in TargetLowering to convert the register
26117 // constraint into a member of a register class.
26118 std::pair<unsigned, const TargetRegisterClass*> Res;
26119 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
26121 // Not found as a standard register?
26123 // Map st(0) -> st(7) -> ST0
26124 if (Constraint.size() == 7 && Constraint[0] == '{' &&
26125 tolower(Constraint[1]) == 's' &&
26126 tolower(Constraint[2]) == 't' &&
26127 Constraint[3] == '(' &&
26128 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
26129 Constraint[5] == ')' &&
26130 Constraint[6] == '}') {
26132 Res.first = X86::FP0+Constraint[4]-'0';
26133 Res.second = &X86::RFP80RegClass;
26137 // GCC allows "st(0)" to be called just plain "st".
26138 if (StringRef("{st}").equals_lower(Constraint)) {
26139 Res.first = X86::FP0;
26140 Res.second = &X86::RFP80RegClass;
26145 if (StringRef("{flags}").equals_lower(Constraint)) {
26146 Res.first = X86::EFLAGS;
26147 Res.second = &X86::CCRRegClass;
26151 // 'A' means EAX + EDX.
26152 if (Constraint == "A") {
26153 Res.first = X86::EAX;
26154 Res.second = &X86::GR32_ADRegClass;
26160 // Otherwise, check to see if this is a register class of the wrong value
26161 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
26162 // turn into {ax},{dx}.
26163 if (Res.second->hasType(VT))
26164 return Res; // Correct type already, nothing to do.
26166 // All of the single-register GCC register classes map their values onto
26167 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
26168 // really want an 8-bit or 32-bit register, map to the appropriate register
26169 // class and return the appropriate register.
26170 if (Res.second == &X86::GR16RegClass) {
26171 if (VT == MVT::i8 || VT == MVT::i1) {
26172 unsigned DestReg = 0;
26173 switch (Res.first) {
26175 case X86::AX: DestReg = X86::AL; break;
26176 case X86::DX: DestReg = X86::DL; break;
26177 case X86::CX: DestReg = X86::CL; break;
26178 case X86::BX: DestReg = X86::BL; break;
26181 Res.first = DestReg;
26182 Res.second = &X86::GR8RegClass;
26184 } else if (VT == MVT::i32 || VT == MVT::f32) {
26185 unsigned DestReg = 0;
26186 switch (Res.first) {
26188 case X86::AX: DestReg = X86::EAX; break;
26189 case X86::DX: DestReg = X86::EDX; break;
26190 case X86::CX: DestReg = X86::ECX; break;
26191 case X86::BX: DestReg = X86::EBX; break;
26192 case X86::SI: DestReg = X86::ESI; break;
26193 case X86::DI: DestReg = X86::EDI; break;
26194 case X86::BP: DestReg = X86::EBP; break;
26195 case X86::SP: DestReg = X86::ESP; break;
26198 Res.first = DestReg;
26199 Res.second = &X86::GR32RegClass;
26201 } else if (VT == MVT::i64 || VT == MVT::f64) {
26202 unsigned DestReg = 0;
26203 switch (Res.first) {
26205 case X86::AX: DestReg = X86::RAX; break;
26206 case X86::DX: DestReg = X86::RDX; break;
26207 case X86::CX: DestReg = X86::RCX; break;
26208 case X86::BX: DestReg = X86::RBX; break;
26209 case X86::SI: DestReg = X86::RSI; break;
26210 case X86::DI: DestReg = X86::RDI; break;
26211 case X86::BP: DestReg = X86::RBP; break;
26212 case X86::SP: DestReg = X86::RSP; break;
26215 Res.first = DestReg;
26216 Res.second = &X86::GR64RegClass;
26219 } else if (Res.second == &X86::FR32RegClass ||
26220 Res.second == &X86::FR64RegClass ||
26221 Res.second == &X86::VR128RegClass ||
26222 Res.second == &X86::VR256RegClass ||
26223 Res.second == &X86::FR32XRegClass ||
26224 Res.second == &X86::FR64XRegClass ||
26225 Res.second == &X86::VR128XRegClass ||
26226 Res.second == &X86::VR256XRegClass ||
26227 Res.second == &X86::VR512RegClass) {
26228 // Handle references to XMM physical registers that got mapped into the
26229 // wrong class. This can happen with constraints like {xmm0} where the
26230 // target independent register mapper will just pick the first match it can
26231 // find, ignoring the required type.
26233 if (VT == MVT::f32 || VT == MVT::i32)
26234 Res.second = &X86::FR32RegClass;
26235 else if (VT == MVT::f64 || VT == MVT::i64)
26236 Res.second = &X86::FR64RegClass;
26237 else if (X86::VR128RegClass.hasType(VT))
26238 Res.second = &X86::VR128RegClass;
26239 else if (X86::VR256RegClass.hasType(VT))
26240 Res.second = &X86::VR256RegClass;
26241 else if (X86::VR512RegClass.hasType(VT))
26242 Res.second = &X86::VR512RegClass;
26248 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26250 // Scaling factors are not free at all.
26251 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26252 // will take 2 allocations in the out of order engine instead of 1
26253 // for plain addressing mode, i.e. inst (reg1).
26255 // vaddps (%rsi,%drx), %ymm0, %ymm1
26256 // Requires two allocations (one for the load, one for the computation)
26258 // vaddps (%rsi), %ymm0, %ymm1
26259 // Requires just 1 allocation, i.e., freeing allocations for other operations
26260 // and having less micro operations to execute.
26262 // For some X86 architectures, this is even worse because for instance for
26263 // stores, the complex addressing mode forces the instruction to use the
26264 // "load" ports instead of the dedicated "store" port.
26265 // E.g., on Haswell:
26266 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26267 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26268 if (isLegalAddressingMode(AM, Ty))
26269 // Scale represents reg2 * scale, thus account for 1
26270 // as soon as we use a second register.
26271 return AM.Scale != 0;
26275 bool X86TargetLowering::isTargetFTOL() const {
26276 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();